[PATCH 14/14] Revert "arm: dts: rockchip: radxa-cm3-io, rock-3a: enable regulators for usb"

[Jonas Karlman]

Remove regulator-boot-on prop from regulators now that the phy core has
support for phy-supply after commit "phy: add support for phy-supply"
and regulators support a basic reference counter after commit
"regulator: implement basic reference counter".

This reverts commit 7911f409ff20dce5995cc1b703a6e30c94022f6b.

Signed-off-by: Jonas Karlman 
---
After [1] and [2] these regulator-boot-on props can be removed.

[1] 
https://patchwork.ozlabs.org/project/uboot/patch/20230419134014.128461-3-eugen.hris...@collabora.com/
[2] 
https://patchwork.ozlabs.org/project/uboot/patch/20230419134526.128800-1-eugen.hris...@collabora.com/

 arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 4 
 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi  | 8 
 2 files changed, 12 deletions(-)

diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi 
b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
index d2ee19aaa8d5..332f81b3bc7e 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
@@ -77,7 +77,3 @@
bootph-all;
status = "okay";
 };
-
-_usb30 {
-   regulator-boot-on;
-};
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 7cd2dc80c317..8abee24c02c3 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -111,11 +111,3 @@
bootph-all;
status = "okay";
 };
-
-_usb_host {
-   regulator-boot-on;
-};
-
-_usb_hub {
-   regulator-boot-on;
-};
-- 
2.40.0

[PATCH 13/14] rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash

[Jonas Karlman]

Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 5 Model B.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 24 
 arch/arm/dts/rk3588s-u-boot.dtsi| 20 
 arch/arm/mach-rockchip/rk3588/rk3588.c  |  1 +
 configs/rock5b-rk3588_defconfig | 10 ++
 4 files changed, 55 insertions(+)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi 
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 4bbc19058c90..b63dd40deb6d 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -11,6 +11,7 @@
 / {
aliases {
mmc1 = 
+   spi0 = 
};
 
chosen {
@@ -43,6 +44,25 @@
pinctrl-0 = <_bus8 _clk _cmd _data_strobe 
_rstnout>;
 };
 
+ {
+   bootph-pre-ram;
+   u-boot,spl-sfc-no-dma;
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
+
  {
bootph-all;
 
@@ -69,6 +89,10 @@
bootph-all;
 };
 
+_pins {
+   bootph-all;
+};
+
 _bus4 {
bootph-all;
 };
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index cd7e6cb50ee2..d8a471a37fd1 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -104,6 +104,15 @@
};
};
 
+   sfc: spi@fe2b {
+   compatible = "rockchip,sfc";
+   reg = <0x0 0xfe2b 0x0 0x4000>;
+   interrupts = ;
+   clocks = < SCLK_SFC>, < HCLK_SFC>;
+   clock-names = "clk_sfc", "hclk_sfc";
+   status = "disabled";
+   };
+
otp: nvmem@fecc {
compatible = "rockchip,rk3588-otp";
reg = <0x0 0xfecc 0x0 0x400>;
@@ -164,3 +173,14 @@
  {
bootph-pre-ram;
 };
+
+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+ {
+   simple-bin-spi {
+   mkimage {
+   args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+   offset = <0x8000>;
+   };
+   };
+};
+#endif
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c 
b/arch/arm/mach-rockchip/rk3588/rk3588.c
index 18e67b5ca9b2..0e85893e0096 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -41,6 +41,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/mmc@fe2e",
[BROM_BOOTSOURCE_SPINOR] = "/spi@fe2b/flash@0",
[BROM_BOOTSOURCE_SD] = "/mmc@fe2c",
+   [6] = "/spi@fe2b/flash@0",
 };
 
 static struct mm_region rk3588_mem_map[] = {
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 2f0a74ee5559..e6a903853fb7 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -8,15 +8,20 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
 CONFIG_ROCKCHIP_RK3588=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_TARGET_ROCK5B_RK3588=y
 CONFIG_SPL_STACK=0x40
 CONFIG_DEBUG_UART_BASE=0xFEB5
 CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
@@ -35,6 +40,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
 CONFIG_SPL_ATF=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
@@ -59,6 +66,8 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 # CONFIG_SPL_MMC_SDHCI_SDMA is not set
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_XTX=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -69,6 +78,7 @@ CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
-- 
2.40.0

[PATCH 12/14] rockchip: rk3588-rock-5b: Add bootph prop to pinctrl for uart2 and sdhci

[Jonas Karlman]

Enable pinctrl for sdhci in SPL to support loading of FIT image from SD
and eMMC storage when booting from SPI NOR flash.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 28 +
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi 
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 715328d204c2..4bbc19058c90 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -61,6 +61,14 @@
bootph-all;
 };
 
+_pull_none {
+   bootph-all;
+};
+
+_xfer {
+   bootph-all;
+};
+
 _bus4 {
bootph-all;
 };
@@ -77,6 +85,26 @@
bootph-all;
 };
 
+_bus8 {
+   bootph-all;
+};
+
+_clk {
+   bootph-all;
+};
+
+_cmd {
+   bootph-all;
+};
+
+_data_strobe {
+   bootph-all;
+};
+
+_rstnout {
+   bootph-all;
+};
+
 _host0_ehci {
companion = <_host0_ohci>;
phys = <_host>;
-- 
2.40.0

[PATCH 11/14] rockchip: rk3588-rock-5b: Update defconfig

[Jonas Karlman]

Update defconfig for rk3588-rock-5b with new defaults.

Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.

Extend SPL_MAX_SIZE to 0x4, SPL is loaded to 0x0 and TF-A is loaded
to 0x4, use the space in between as SPL_MAX_SIZE.

Add config option to include useful gpio cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.

Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.

Signed-off-by: Jonas Karlman 
---
 configs/rock5b-rk3588_defconfig | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 2e034b724cc9..2f0a74ee5559 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -10,9 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
 CONFIG_ROCKCHIP_RK3588=y
-CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_TARGET_ROCK5B_RK3588=y
@@ -29,7 +27,7 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2
+CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x400
@@ -38,6 +36,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -47,7 +46,6 @@ CONFIG_CMD_REGULATOR=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
 CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
@@ -70,6 +68,7 @@ CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
-- 
2.40.0

[PATCH 10/14] rockchip: rk3588-evb: Update defconfig

[Jonas Karlman]

Update defconfig for rk3588-evb with new defaults.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.

Extend SPL_MAX_SIZE to 0x4, SPL is loaded to 0x0 and TF-A is loaded
to 0x4, use the space in between as SPL_MAX_SIZE.

Add config options to include useful gpio and regulator cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.

Disable CONFIG_SPL_MMC_SDHCI_SDMA option to use PIO to load TF-A into
DRAM and SRAM.

Remove CONFIG_DEBUG_UART_ANNOUNCE=y to remove debug messages.

Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.

Signed-off-by: Jonas Karlman 
---
 configs/evb-rk3588_defconfig | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index 8760671a1772..70e435b1f745 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -21,12 +21,13 @@ CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2
+CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x400
@@ -35,14 +36,15 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
@@ -54,6 +56,7 @@ CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
+# CONFIG_SPL_MMC_SDHCI_SDMA is not set
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
@@ -62,6 +65,6 @@ CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_ERRNO_STR=y
-- 
2.40.0

[PATCH 09/14] rockchip: rk3588: Select DM_RESET and DM_REGULATOR_FIXED in arch Kconfig

[Jonas Karlman]

Like other Rockchip SoCs, DM_RESET and DM_REGULATOR_FIXED is useful
across RK3588 platform. Select them from arch Kconfig.

Signed-off-by: Jonas Karlman 
---
 arch/arm/mach-rockchip/Kconfig| 2 ++
 configs/evb-rk3588_defconfig  | 2 --
 configs/neu6a-io-rk3588_defconfig | 1 -
 configs/rock5b-rk3588_defconfig   | 2 --
 4 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 327779a79818..9d6d20bf8ed6 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -311,6 +311,8 @@ config ROCKCHIP_RK3588
select REGMAP
select SYSCON
select BOARD_LATE_INIT
+   select DM_REGULATOR_FIXED
+   select DM_RESET
imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
imply ROCKCHIP_COMMON_BOARD
imply OF_LIBFDT_OVERLAY
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index ddeadb8a760f..8760671a1772 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -9,10 +9,8 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10"
-CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3588=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_TARGET_EVB_RK3588=y
diff --git a/configs/neu6a-io-rk3588_defconfig 
b/configs/neu6a-io-rk3588_defconfig
index fb1ce4c1746f..09729a0ea429 100644
--- a/configs/neu6a-io-rk3588_defconfig
+++ b/configs/neu6a-io-rk3588_defconfig
@@ -9,7 +9,6 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6a-io"
-CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3588=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
 CONFIG_SPL_SERIAL=y
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index c57de5a5be02..2e034b724cc9 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -9,7 +9,6 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
-CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3588=y
 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
@@ -67,7 +66,6 @@ CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_REGULATOR_PWM=y
-CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=150
-- 
2.40.0

[PATCH 08/14] rockchip: rk3568-rock-3a: Enable boot from SPI NOR flash

[Jonas Karlman]

Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 3 Model A.

Unlike prior generation SoCs the BootRom in RK3568 can read all data and
look for idbloader at 0x8000, same as on SD and eMMC.

Use the rksd format and modify the mkimage offset to generate a bootable
u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The
FIT image is loaded from 0x6.

  => sf probe
  SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 
MiB

  => load mmc 1:1 1000 u-boot-rockchip-spi.bin
  1384448 bytes read in 119 ms (11.1 MiB/s)

  => sf update $fileaddr 0 $filesize
  device 0 offset 0x0, size 0x152000
  1179648 bytes written, 204800 bytes skipped in 9.901s, speed 143185 B/s

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 25 +
 arch/arm/dts/rk356x-u-boot.dtsi | 11 +++
 configs/rock-3a-rk3568_defconfig| 10 ++
 3 files changed, 46 insertions(+)

diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index b2af3b1dbed6..7cd2dc80c317 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -7,6 +7,10 @@
 #include "rk356x-u-boot.dtsi"
 
 / {
+   aliases {
+   spi0 = 
+   };
+
chosen {
stdout-path = 
u-boot,spl-boot-order = "same-as-spl", , 
@@ -33,6 +37,10 @@
bootph-pre-ram;
 };
 
+_pins {
+   bootph-pre-ram;
+};
+
 _bus4 {
bootph-pre-ram;
 };
@@ -65,6 +73,23 @@
bootph-pre-ram;
 };
 
+ {
+   bootph-pre-ram;
+   u-boot,spl-sfc-no-dma;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
+
  {
cap-mmc-highspeed;
mmc-ddr-1_8v;
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index a1c2d03c52f0..c340c2bba6ff 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -68,3 +68,14 @@
bootph-pre-ram;
status = "okay";
 };
+
+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+ {
+   simple-bin-spi {
+   mkimage {
+   args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+   offset = <0x8000>;
+   };
+   };
+};
+#endif
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 2e556dc2c1a2..64864a300153 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -8,15 +8,20 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a"
 CONFIG_ROCKCHIP_RK3568=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_TARGET_EVB_RK3568=y
 CONFIG_SPL_STACK=0x40
 CONFIG_DEBUG_UART_BASE=0xFE66
 CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
@@ -34,6 +39,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
 CONFIG_SPL_ATF=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
@@ -59,6 +66,8 @@ CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_XTX=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -72,6 +81,7 @@ CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
-- 
2.40.0

[PATCH 07/14] rockchip: rk3568-rock-3a: Use pinctrl for sdmmc and sdhci in SPL

[Jonas Karlman]

Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT
image from SD and eMMC storage when booting from SPI NOR flash.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 52 +
 configs/rock-3a-rk3568_defconfig|  3 +-
 2 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 801c91af5b41..b2af3b1dbed6 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -13,6 +13,58 @@
};
 };
 
+ {
+   bootph-pre-ram;
+};
+
+_pull_up {
+   bootph-pre-ram;
+};
+
+_pull_none {
+   bootph-pre-ram;
+};
+
+_pull_up_drv_level_2 {
+   bootph-pre-ram;
+};
+
+_xfer {
+   bootph-pre-ram;
+};
+
+_bus4 {
+   bootph-pre-ram;
+};
+
+_clk {
+   bootph-pre-ram;
+};
+
+_cmd {
+   bootph-pre-ram;
+};
+
+_det {
+   bootph-pre-ram;
+};
+
+_bus8 {
+   bootph-pre-ram;
+};
+
+_clk {
+   bootph-pre-ram;
+};
+
+_cmd {
+   bootph-pre-ram;
+};
+
+_datastrobe {
+   bootph-pre-ram;
+};
+
  {
cap-mmc-highspeed;
mmc-ddr-1_8v;
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 5126feb6b11d..2e556dc2c1a2 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -46,7 +46,7 @@ CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
@@ -63,6 +63,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_RK8XX=y
-- 
2.40.0

[PATCH 06/14] rockchip: rk3568-rock-3a: Update defconfig

[Jonas Karlman]

Update defconfig for rk3568-rock-3a with new defaults.

Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.

Extend SPL_MAX_SIZE to 0x4, SPL is loaded to 0x0 and TF-A is loaded
to 0x4, use the space in between as SPL_MAX_SIZE.

Add config option to include useful gpio cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.

Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
U-Boot proper will read and configure assigned-clock props.

Remove the CONFIG_SPL_PMIC_RK8XX=y option, the pmic is not used in SPL.

Signed-off-by: Jonas Karlman 
---
 configs/rock-3a-rk3568_defconfig | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index f0db15baa30e..5126feb6b11d 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -10,9 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a"
 CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_TARGET_EVB_RK3568=y
@@ -23,11 +21,12 @@ CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2
+CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x400
@@ -36,6 +35,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -46,7 +46,7 @@ CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
-CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
@@ -65,7 +65,6 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_RK8XX=y
-CONFIG_SPL_PMIC_RK8XX=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
-- 
2.40.0

[PATCH 05/14] rockchip: rk3568-evb: Update defconfig

[Jonas Karlman]

Update defconfig for rk3568-evb with new defaults.

Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.

Extend SPL_MAX_SIZE to 0x4, SPL is loaded to 0x0 and TF-A is loaded
to 0x4, use the space in between as SPL_MAX_SIZE.

Add config options to include useful gpio, i2c, pmic and regulator cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.

Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
U-Boot proper will read and configure assigned-clock props.

Add config options to enable support for the RK809 PMIC.

Signed-off-by: Jonas Karlman 
---
 configs/evb-rk3568_defconfig | 15 ++-
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
index c929bac509c0..0b4fc52e263d 100644
--- a/configs/evb-rk3568_defconfig
+++ b/configs/evb-rk3568_defconfig
@@ -10,9 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
 CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
 CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_TARGET_EVB_RK3568=y
@@ -23,11 +21,12 @@ CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2
+CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x400
@@ -36,13 +35,17 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
-CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
@@ -57,7 +60,9 @@ CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
-CONFIG_REGULATOR_PWM=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=150
-- 
2.40.0

[PATCH 04/14] rockchip: rk3566-radxa-cm3-io: Use pinctrl for sdmmc and sdhci in SPL

[Jonas Karlman]

Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT
image from SD and eMMC storage when booting from SPI NOR flash.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 56 
 configs/radxa-cm3-io-rk3566_defconfig|  3 +-
 2 files changed, 58 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi 
b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
index a8c31fecafd8..d2ee19aaa8d5 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
@@ -11,6 +11,62 @@
};
 };
 
+ {
+   bootph-pre-ram;
+};
+
+_pull_up {
+   bootph-pre-ram;
+};
+
+_pull_none {
+   bootph-pre-ram;
+};
+
+_pull_up_drv_level_2 {
+   bootph-pre-ram;
+};
+
+_xfer {
+   bootph-pre-ram;
+};
+
+_bus4 {
+   bootph-pre-ram;
+};
+
+_clk {
+   bootph-pre-ram;
+};
+
+_cmd {
+   bootph-pre-ram;
+};
+
+_det {
+   bootph-pre-ram;
+};
+
+_pwren {
+   bootph-pre-ram;
+};
+
+_bus8 {
+   bootph-pre-ram;
+};
+
+_clk {
+   bootph-pre-ram;
+};
+
+_cmd {
+   bootph-pre-ram;
+};
+
+_datastrobe {
+   bootph-pre-ram;
+};
+
  {
cap-mmc-highspeed;
mmc-ddr-1_8v;
diff --git a/configs/radxa-cm3-io-rk3566_defconfig 
b/configs/radxa-cm3-io-rk3566_defconfig
index dfaacbc8839e..dd1dd36a59b7 100644
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -46,7 +46,7 @@ CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
@@ -63,6 +63,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_RK8XX=y
-- 
2.40.0

[PATCH 03/14] rockchip: rk3566-radxa-cm3-io: Update defconfig

[Jonas Karlman]

Update defconfig for rk3566-radxa-cm3-io with new defaults. Also add
missing supported mmc modes to sdhci node.

Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.

Extend SPL_MAX_SIZE to 0x4, SPL is loaded to 0x0 and TF-A is loaded
to 0x4, use the space in between as SPL_MAX_SIZE.

Add config option to include useful gpio cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.

Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
U-Boot proper will read and configure assigned-clock props.

Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 5 +
 configs/radxa-cm3-io-rk3566_defconfig| 9 +
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi 
b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
index d183e935754d..a8c31fecafd8 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
@@ -11,6 +11,11 @@
};
 };
 
+ {
+   cap-mmc-highspeed;
+   mmc-ddr-1_8v;
+};
+
  {
clock-frequency = <2400>;
bootph-all;
diff --git a/configs/radxa-cm3-io-rk3566_defconfig 
b/configs/radxa-cm3-io-rk3566_defconfig
index 1df9cab79d51..dfaacbc8839e 100644
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -10,9 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
 CONFIG_DEFAULT_DEVICE_TREE="rk3566-radxa-cm3-io"
 CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x60
 CONFIG_TARGET_EVB_RK3568=y
@@ -23,11 +21,12 @@ CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-radxa-cm3-io.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2
+CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x400
@@ -36,6 +35,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -46,7 +46,7 @@ CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
-CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
@@ -70,6 +70,7 @@ CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
-- 
2.40.0

[PATCH 01/14] spi: rockchip_sfc: Use linux rockchip,sfc-no-dma prop

[Jonas Karlman]

Use the same prop as linux to control the use of fifo or dma mode. Also
add a u-boot,spl-sfc-no-dma prop to control the same in SPL.

Signed-off-by: Jonas Karlman 
---
 drivers/spi/rockchip_sfc.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c
index 851a6482985b..1c26802c618e 100644
--- a/drivers/spi/rockchip_sfc.c
+++ b/drivers/spi/rockchip_sfc.c
@@ -227,10 +227,12 @@ static int rockchip_sfc_ofdata_to_platdata(struct udevice 
*bus)
struct rockchip_sfc *sfc = dev_get_plat(bus);
 
sfc->regbase = dev_read_addr_ptr(bus);
-   if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma"))
-   sfc->use_dma = false;
-   else
-   sfc->use_dma = true;
+   sfc->use_dma = !dev_read_bool(bus, "rockchip,sfc-no-dma");
+
+#ifdef CONFIG_SPL_BUILD
+   if (sfc->use_dma)
+   sfc->use_dma = !dev_read_bool(bus, "u-boot,spl-sfc-no-dma");
+#endif
 
 #if CONFIG_IS_ENABLED(CLK)
int ret;
-- 
2.40.0

[PATCH 02/14] rockchip: rk356x-u-boot: Add xin24m clock node to SPL

[Jonas Karlman]

Add bootph-all prop to xin24m clock node, it is referenced by cru node.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk356x-u-boot.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index 0a764ce5119c..a1c2d03c52f0 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -34,6 +34,11 @@
};
 };
 
+ {
+   bootph-all;
+   status = "okay";
+};
+
  {
bootph-all;
status = "okay";
-- 
2.40.0

[PATCH 00/14] rockchip: rk35xx: Update defconfigs and enable boot from SPI NOR flash

[Jonas Karlman]

This series sync some defconfig options across the different rk35xx
boards and enables boot from SPI NOR flash on rk3568-rock-3a and
rk3588-rock-5b.

Patch 1 fixes use of sfc-no-dma prop in rockchip sfc driver.
Patch 2-7 updates defconfig for rk356x boards.
Patch 8 enables boot from SPI NOR flash on rk3568-rock-3a.
Patch 9-12 updates defconfig for rk3588 boards.
Patch 13 enables boot from SPI NOR flash on rk3588-rock-5b.
Patch 14 reverts addition of regulator-boot-on props.

Please note that patches related to rk3588 depend on [1] and [2], they
may not apply clean. The final patch revert a workaround to fix usb that
is not needed after series [1] and [3].

This series can also be found at [4].

[1] 
https://patchwork.ozlabs.org/project/uboot/patch/20230419134014.128461-1-eugen.hris...@collabora.com/
[2] 
https://patchwork.ozlabs.org/project/uboot/patch/20230417100641.5703-1-eugen.hris...@collabora.com/
[3] 
https://patchwork.ozlabs.org/project/uboot/patch/20230419134526.128800-1-eugen.hris...@collabora.com/
[4] https://github.com/Kwiboo/u-boot-rockchip/commits/rk35xx-defconfig-spi-v1

Jonas Karlman (14):
  spi: rockchip_sfc: Use linux rockchip,sfc-no-dma prop
  rockchip: rk356x-u-boot: Add xin24m clock node to SPL
  rockchip: rk3566-radxa-cm3-io: Update defconfig
  rockchip: rk3566-radxa-cm3-io: Use pinctrl for sdmmc and sdhci in SPL
  rockchip: rk3568-evb: Update defconfig
  rockchip: rk3568-rock-3a: Update defconfig
  rockchip: rk3568-rock-3a: Use pinctrl for sdmmc and sdhci in SPL
  rockchip: rk3568-rock-3a: Enable boot from SPI NOR flash
  rockchip: rk3588: Select DM_RESET and DM_REGULATOR_FIXED in arch
Kconfig
  rockchip: rk3588-evb: Update defconfig
  rockchip: rk3588-rock-5b: Update defconfig
  rockchip: rk3588-rock-5b: Add bootph prop to pinctrl for uart2 and
sdhci
  rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash
  Revert "arm: dts: rockchip: radxa-cm3-io, rock-3a: enable regulators
for usb"

 arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 65 ++-
 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi  | 85 ++--
 arch/arm/dts/rk356x-u-boot.dtsi  | 16 
 arch/arm/dts/rk3588-rock-5b-u-boot.dtsi  | 52 
 arch/arm/dts/rk3588s-u-boot.dtsi | 20 +
 arch/arm/mach-rockchip/Kconfig   |  2 +
 arch/arm/mach-rockchip/rk3588/rk3588.c   |  1 +
 configs/evb-rk3568_defconfig | 15 ++--
 configs/evb-rk3588_defconfig | 11 +--
 configs/neu6a-io-rk3588_defconfig|  1 -
 configs/radxa-cm3-io-rk3566_defconfig| 10 ++-
 configs/rock-3a-rk3568_defconfig | 20 +++--
 configs/rock5b-rk3588_defconfig  | 19 +++--
 drivers/spi/rockchip_sfc.c   | 10 ++-
 14 files changed, 285 insertions(+), 42 deletions(-)

-- 
2.40.0

[PATCH v4 1/3] net: ipv6: Add support for default gateway discovery.

[emohandesi]

From: Ehsan Mohandesi 

In IPv6, the default gateway and prefix length are determined by receiving
a router advertisement as defined in -
https://www.rfc-editor.org/rfc/rfc4861.

Add support for sending router solicitation (RS) and processing router
advertisements (RA).

If the RA has prefix info option and following conditions are met, then
gatewayip6 and net_prefix_length of ip6addr env variables are initialized.
These are later consumed by IPv6 code for non-local destination IP.

- "Router Lifetime" != 0
- Prefix is NOT link-local prefix (0xfe80::/10)
- L flag is 1
- "Valid Lifetime" != 0

Timing Parameters:
- MAX_RTR_SOLICITATION_DELAY (0-1s)
- RTR_SOLICITATION_INTERVAL (4s) (min retransmit delay)
- MAX_RTR_SOLICITATIONS (3 RS transmissions)

The functionality is enabled by CONFIG_IPV6_ROUTER_DISCOVERY and invoked
automatically from net_init_loop().

Signed-off-by: Ehsan Mohandesi 
---
 cmd/Kconfig |   6 ++
 include/ndisc.h |  35 
 include/net.h   |   2 +-
 include/net6.h  |  40 ++
 net/ndisc.c | 243 +---
 net/net.c   |  23 +-
 net/net6.c  |   1 +
 7 files changed, 338 insertions(+), 12 deletions(-)

diff --git a/cmd/Kconfig b/cmd/Kconfig
index e45b884..6919d31 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1916,6 +1916,12 @@ config CMD_NCSI
  Normally this happens automatically before other network
  operations.
 
+config IPV6_ROUTER_DISCOVERY
+   bool "Do IPv6 router discovery"
+   depends on IPV6
+   help
+ Will automatically perform router solicitation on first IPv6
+ network operation
 endif
 
 config CMD_ETHSW
diff --git a/include/ndisc.h b/include/ndisc.h
index f6f8eb6..12fa9e7 100644
--- a/include/ndisc.h
+++ b/include/ndisc.h
@@ -19,6 +19,20 @@ struct nd_msg {
__u8opt[0];
 };
 
+/* struct rs_msg - ICMPv6 Router Solicitation message format */
+struct rs_msg {
+   struct icmp6hdr icmph;
+   __u8opt[0];
+};
+
+/* struct ra_msg - ICMPv6 Router Advertisement message format */
+struct ra_msg {
+   struct icmp6hdr icmph;
+   __u32   reachable_time;
+   __u32   retransmission_timer;
+   __u8opt[0];
+};
+
 /* struct echo_msg - ICMPv6 echo request/reply message format */
 struct echo_msg {
struct icmp6hdr icmph;
@@ -57,6 +71,11 @@ extern int net_nd_try;
  */
 void ndisc_init(void);
 
+/*
+ * ip6_send_rs() - Send IPv6 Router Solicitation Message
+ */
+void ip6_send_rs(void);
+
 /**
  * ndisc_receive() - Handle ND packet
  *
@@ -78,6 +97,8 @@ void ndisc_request(void);
  * Return: 0 if no timeout, -1 otherwise
  */
 int ndisc_timeout_check(void);
+bool validate_ra(struct ip6_hdr *ip6);
+int process_ra(struct ip6_hdr *ip6, int len);
 #else
 static inline void ndisc_init(void)
 {
@@ -97,6 +118,20 @@ static inline int ndisc_timeout_check(void)
 {
return 0;
 }
+
+void ip6_send_rs(void)
+{
+}
+
+static inline bool validate_ra(struct ip6_hdr *ip6)
+{
+   return true;
+}
+
+static inline int process_ra(struct ip6_hdr *ip6, int len)
+{
+   return 0;
+}
 #endif
 
 #endif /* __NDISC_H__ */
diff --git a/include/net.h b/include/net.h
index 399af5e..25c43b3 100644
--- a/include/net.h
+++ b/include/net.h
@@ -505,7 +505,7 @@ extern int  net_restart_wrap;   /* Tried all 
network devices */
 
 enum proto_t {
BOOTP, RARP, ARP, TFTPGET, DHCP, PING, PING6, DNS, NFS, CDP, NETCONS,
-   SNTP, TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP, NCSI, WGET
+   SNTP, TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP, NCSI, WGET, RS
 };
 
 extern charnet_boot_file_name[1024];/* Boot File name */
diff --git a/include/net6.h b/include/net6.h
index 2d7c5a0..beafc05 100644
--- a/include/net6.h
+++ b/include/net6.h
@@ -81,8 +81,17 @@ struct udp_hdr {
  0x00, 0x00, 0x00, 0x00, \
  0x00, 0x00, 0x00, 0x00, \
  0x00, 0x00, 0x00, 0x00 } } }
+/*
+ * All-routers multicast address is the link-local scope address to reach all
+ * routers.
+ */
+#define ALL_ROUTERS_MULT_ADDR { { { 0xFF, 0x02, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x02 } } }
 
 #define IPV6_LINK_LOCAL_PREFIX 0xfe80
+#define IPV6_LINK_LOCAL_MASK   0xffb0 /* The first 10-bit of address mask. */
 
 /* hop limit for neighbour discovery packets */
 #define IPV6_NDISC_HOPLIMIT 255
@@ -166,6 +175,37 @@ struct icmp6hdr {
 #define icmp6_rt_lifetime  icmp6_dataun.u_nd_ra.rt_lifetime
 } __packed;
 
+/*
+ * struct icmp6_ra_prefix_info - Prefix Information option of the ICMPv6 
message
+ * The Prefix Information option provides hosts with on-link prefixes and
+ * prefixes for Address Autoconfiguration. Refer to RFC 4861 for more info.
+ */
+struct icmp6_ra_prefix_info {
+   u8  type;   /* Type is 3 for 

[PATCH v4 3/3] test: eth: IPv6 network discovery unit test

[emohandesi]

From: Ehsan Mohandesi 

Test router advertisement validation and processing functions.

Signed-off-by: Ehsan Mohandesi 
---
 test/dm/eth.c | 88 +++
 1 file changed, 88 insertions(+)

diff --git a/test/dm/eth.c b/test/dm/eth.c
index ebf01d8..d05d2a9 100644
--- a/test/dm/eth.c
+++ b/test/dm/eth.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define DM_TEST_ETH_NUM4
 
@@ -607,3 +608,90 @@ static int dm_test_eth_async_ping_reply(struct 
unit_test_state *uts)
 }
 
 DM_TEST(dm_test_eth_async_ping_reply, UT_TESTF_SCAN_FDT);
+
+#if IS_ENABLED(CONFIG_IPV6_ROUTER_DISCOVERY)
+
+static u8 ip6_ra_buf[] = {0x60, 0xf, 0xc5, 0x4a, 0x0, 0x38, 0x3a, 0xff, 0xfe,
+ 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0x85, 0xe6,
+ 0x29, 0x77, 0xcb, 0xc8, 0x53, 0xff, 0x2, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0x1, 0x86, 0x0, 0xdc, 0x90, 0x40, 0x80, 0x15, 0x18,
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x4,
+ 0x40, 0xc0, 0x0, 0x0, 0x37, 0xdc, 0x0, 0x0, 0x37,
+ 0x78, 0x0, 0x0, 0x0, 0x0, 0x20, 0x1, 0xca, 0xfe, 0xca,
+ 0xfe, 0xca, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x1, 0x1, 0x0, 0x15, 0x5d, 0xe2, 0x8a, 0x2};
+
+static int dm_test_validate_ra(struct unit_test_state *uts)
+{
+   struct ip6_hdr *ip6 = (struct ip6_hdr *)ip6_ra_buf;
+   struct icmp6hdr *icmp = (struct icmp6hdr *)(ip6 + 1);
+   __be16 temp = 0;
+
+   ut_assert(validate_ra(ip6) == true);
+
+   temp = ip6->payload_len;
+   ip6->payload_len = 15;
+   ut_assert(validate_ra(ip6) == false);
+   ip6->payload_len = temp;
+
+   temp = ip6->saddr.s6_addr16[0];
+   ip6->saddr.s6_addr16[0] = 0x2001;
+   ut_assert(validate_ra(ip6) == false);
+   ip6->saddr.s6_addr16[0] = temp;
+
+   temp = ip6->hop_limit;
+   ip6->hop_limit = 15;
+   ut_assert(validate_ra(ip6) == false);
+   ip6->hop_limit = temp;
+
+   temp = icmp->icmp6_code;
+   icmp->icmp6_code = 15;
+   ut_assert(validate_ra(ip6) == false);
+   icmp->icmp6_code = temp;
+
+   return 0;
+}
+
+DM_TEST(dm_test_validate_ra, 0);
+
+static int dm_test_process_ra(struct unit_test_state *uts)
+{
+   int len = sizeof(ip6_ra_buf);
+   struct ip6_hdr *ip6 = (struct ip6_hdr *)ip6_ra_buf;
+   struct icmp6hdr *icmp = (struct icmp6hdr *)(ip6 + 1);
+   struct ra_msg *msg = (struct ra_msg *)icmp;
+   unsigned char *option = msg->opt;
+   struct icmp6_ra_prefix_info *prefix =
+   (struct icmp6_ra_prefix_info *)option;
+   __be16 temp = 0;
+   unsigned char option_len = option[1];
+
+   ut_assert(process_ra(ip6, len) == 0);
+
+   temp = icmp->icmp6_rt_lifetime;
+   icmp->icmp6_rt_lifetime = 0;
+   ut_assert(process_ra(ip6, len) != 0);
+   icmp->icmp6_rt_lifetime = temp;
+
+   ut_assert(process_ra(ip6, 0) != 0);
+
+   option[1] = 0;
+   ut_assert(process_ra(ip6, len) != 0);
+   option[1] = option_len;
+
+   prefix->on_link = false;
+   ut_assert(process_ra(ip6, len) != 0);
+   prefix->on_link = true;
+
+   temp = prefix->prefix.s6_addr16[0];
+   prefix->prefix.s6_addr16[0] = 0x80fe;
+   ut_assert(process_ra(ip6, len) != 0);
+   prefix->prefix.s6_addr16[0] = temp;
+
+   return 0;
+}
+
+DM_TEST(dm_test_process_ra, 0);
+
+#endif
-- 
1.8.3.1

[PATCH v4 2/3] test/py: IPv6 network discovery test

[emohandesi]

From: Ehsan Mohandesi 

Test the IPv6 network discovery feature if indicated by boardenv file.

Signed-off-by: Ehsan Mohandesi 
---
 configs/sandbox64_defconfig|  2 ++
 configs/sandbox_defconfig  |  2 ++
 configs/sandbox_flattree_defconfig |  2 ++
 test/py/tests/test_net.py  | 31 ++-
 4 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index af2c56a..be36ede 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -260,3 +260,5 @@ CONFIG_FWU_MULTI_BANK_UPDATE=y
 CONFIG_UNIT_TEST=y
 CONFIG_UT_TIME=y
 CONFIG_UT_DM=y
+CONFIG_IPV6=y
+CONFIG_IPV6_ROUTER_DISCOVERY=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index ca95b2c..0673c69 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -341,3 +341,5 @@ CONFIG_UNIT_TEST=y
 CONFIG_UT_TIME=y
 CONFIG_UT_DM=y
 CONFIG_CMD_2048=y
+CONFIG_IPV6=y
+CONFIG_IPV6_ROUTER_DISCOVERY=y
diff --git a/configs/sandbox_flattree_defconfig 
b/configs/sandbox_flattree_defconfig
index e9fcc5b..d6c8dd2 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -229,3 +229,5 @@ CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
 CONFIG_UNIT_TEST=y
 CONFIG_UT_TIME=y
 CONFIG_UT_DM=y
+CONFIG_IPV6=y
+CONFIG_IPV6_ROUTER_DISCOVERY=y
diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py
index 9ca6743..f85071d 100644
--- a/test/py/tests/test_net.py
+++ b/test/py/tests/test_net.py
@@ -9,7 +9,7 @@ import u_boot_utils
 
 """
 Note: This test relies on boardenv_* containing configuration values to define
-which the network environment available for testing. Without this, this test
+which network environment is available for testing. Without this, this test
 will be automatically skipped.
 
 For example:
@@ -55,6 +55,11 @@ env__net_nfs_readable_file = {
 'size': 5058624,
 'crc32': 'c2244b26',
 }
+
+# True if a router advertisement service is connected to the network, and 
should
+# be tested. If router advertisement testing is not possible or desired, this
+variable may be omitted or set to False.
+env__router_on_net = True
 """
 
 net_set_up = False
@@ -126,6 +131,30 @@ def test_net_ping(u_boot_console):
 output = u_boot_console.run_command('ping $serverip')
 assert 'is alive' in output
 
+@pytest.mark.buildconfigspec('IPV6_ROUTER_DISCOVERY')
+def test_net_network_discovery(u_boot_console):
+"""Test the network discovery feature of IPv6.
+
+An IPv6 network command (ping6 in this case) is run to make U-Boot send a
+router solicitation packet, receive a router advertisement message, and
+parse it.
+A router advertisement service needs to be running for this test to 
succeed.
+U-Boot receives the RA, processes it, and if successful, assigns the 
gateway
+IP and prefix length.
+The configuration is provided by the boardenv_* file; see the comment at
+the beginning of this file.
+"""
+
+router_on_net = u_boot_console.config.env.get('env__router_on_net', False)
+if not router_on_net:
+pytest.skip('No router on network')
+
+fake_host_ip = 'fe80::215:5dff:fef6:2ec6'
+output = u_boot_console.run_command('ping6 ' + fake_host_ip)
+assert 'ROUTER SOLICITATION 1' in output
+assert 'Set gatewayip6:' in output
+assert ':::::::' not in output
+
 @pytest.mark.buildconfigspec('cmd_net')
 def test_net_tftpboot(u_boot_console):
 """Test the tftpboot command.
-- 
1.8.3.1

[PATCH v4 0/3] Add IPv6 Network Discovery

[emohandesi]

From: Ehsan Mohandesi 

This series adds IPv6 network discovery to U-Boot. When an IPv6 command is
run in U-Boot, it sends a router solicitation (RS) message to the network.
The router on the network responds with a router advertisement (RA)
message. Then U-Boot processes the RA message and sets the gatewayip6 and
net_prefix_length environment variables.
It is based on RFC 4861, but not everything in the RFC is supported here.
https://www.rfc-editor.org/rfc/rfc4861

Changes in v4:
- Removed the changes that were mistakenly pulled from the local workspace.

Changes in v3:
- Removed the extra revert commit that was mistakenly added in v2.

Changes in v2:
- Improved IPv6 network discovery code.
- Added IPv6 network discovery feature test (Python test).
- Added unit tests (C code).

Ehsan Mohandesi (3):
  net: ipv6: Add support for default gateway discovery.
  test/py: IPv6 network discovery test
  test: eth: IPv6 network discovery unit test

 cmd/Kconfig|   6 +
 configs/sandbox64_defconfig|   2 +
 configs/sandbox_defconfig  |   2 +
 configs/sandbox_flattree_defconfig |   2 +
 include/ndisc.h|  35 ++
 include/net.h  |   2 +-
 include/net6.h |  40 ++
 net/ndisc.c| 243 +++--
 net/net.c  |  23 +++-
 net/net6.c |   1 +
 test/dm/eth.c  |  88 ++
 test/py/tests/test_net.py  |  31 -
 12 files changed, 462 insertions(+), 13 deletions(-)

-- 
1.8.3.1

Re: [PATCH v1 1/1] misc: extcon: add MAX14526 MUIC support

[Tim Harvey]

On Fri, Apr 21, 2023 at 9:36 AM Svyatoslav Ryhel  wrote:
>
> пт, 21 квіт. 2023 р. о 19:30 Tim Harvey  пише:
> >
> > On Thu, Apr 20, 2023 at 9:54 AM Svyatoslav Ryhel  wrote:
> > >
> > > чт, 20 квіт. 2023 р. о 19:30 Simon Glass  пише:
> > > >
> > > > Hi Svyatoslav,
> > > >
> > > > On Thu, 20 Apr 2023 at 18:01, Svyatoslav Ryhel  
> > > > wrote:
> > > > >
> > > > > чт, 20 квіт. 2023 р. о 01:41 Simon Glass  пише:
> > > > > >
> > > > > > Hi Svyatoslav,
> > > > > >
> > > > > > On Wed, 19 Apr 2023 at 12:53, Svyatoslav Ryhel  
> > > > > > wrote:
> > > > > > >
> > > > > > > MAX14526 is a powerful extcon chip which allows detection of 
> > > > > > > various
> > > > > > > plugs like usb, mhl, uart, headset etc. This version of driver
> > > > > > > implements support of AP-usb and CP-usb/uart paths.
> > > > > > >
> > > > > > > Tested-by: Andreas Westman Dorcsak  # LG P880 
> > > > > > > T30
> > > > > > > Tested-by: Svyatoslav Ryhel  # LG P895 T30
> > > > > > > Signed-off-by: Svyatoslav Ryhel 
> > > > > > > ---
> > > > > > >  drivers/misc/Kconfig  |   2 +
> > > > > > >  drivers/misc/Makefile |   1 +
> > > > > > >  drivers/misc/extcon/Kconfig   |   8 ++
> > > > > > >  drivers/misc/extcon/Makefile  |   2 +
> > > > > > >  drivers/misc/extcon/extcon-max14526.c | 153 
> > > > > > > ++
> > > > > > >  5 files changed, 166 insertions(+)
> > > > > > >  create mode 100644 drivers/misc/extcon/Kconfig
> > > > > > >  create mode 100644 drivers/misc/extcon/Makefile
> > > > > > >  create mode 100644 drivers/misc/extcon/extcon-max14526.c
> > > > > > >
> > > > > > > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> > > > > > > index 4e1ae03e9f..1b49f3cf72 100644
> > > > > > > --- a/drivers/misc/Kconfig
> > > > > > > +++ b/drivers/misc/Kconfig
> > > > > > > @@ -659,4 +659,6 @@ config SL28CPLD
> > > > > > >   the base driver which provides common access methods 
> > > > > > > for the
> > > > > > >   sub-drivers.
> > > > > > >
> > > > > > > +source "drivers/misc/extcon/Kconfig"
> > > > > > > +
> > > > > > >  endmenu
> > > > > > > diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> > > > > > > index 3b792f2a14..6d4fc8ddf9 100644
> > > > > > > --- a/drivers/misc/Makefile
> > > > > > > +++ b/drivers/misc/Makefile
> > > > > > > @@ -87,3 +87,4 @@ obj-$(CONFIG_K3_AVS0) += k3_avs.o
> > > > > > >  obj-$(CONFIG_ESM_K3) += k3_esm.o
> > > > > > >  obj-$(CONFIG_ESM_PMIC) += esm_pmic.o
> > > > > > >  obj-$(CONFIG_SL28CPLD) += sl28cpld.o
> > > > > > > +obj-y += extcon/
> > > > > > > diff --git a/drivers/misc/extcon/Kconfig 
> > > > > > > b/drivers/misc/extcon/Kconfig
> > > > > > > new file mode 100644
> > > > > > > index 00..99c38224f3
> > > > > > > --- /dev/null
> > > > > > > +++ b/drivers/misc/extcon/Kconfig
> > > > > > > @@ -0,0 +1,8 @@
> > > > > > > +config EXTCON_MAX14526
> > > > > > > +   bool "Maxim MAX14526 EXTCON Support"
> > > > > > > +   select DM_I2C
> > > > > > > +   select DM_MISC
> > > > > > > +   help
> > > > > > > + If you say yes here you get support for the MUIC device 
> > > > > > > of
> > > > > > > + Maxim MAX14526. The MAX14526 MUIC is a USB port 
> > > > > > > accessory
> > > > > > > + detector and switch.
> > > > > > > diff --git a/drivers/misc/extcon/Makefile 
> > > > > > > b/drivers/misc/extcon/Makefile
> > > > > > > new file mode 100644
> > > > > > > index 00..f012b688ce
> > > > > > > --- /dev/null
> > > > > > > +++ b/drivers/misc/extcon/Makefile
> > > > > > > @@ -0,0 +1,2 @@
> > > > > > > +# SPDX-License-Identifier: GPL-2.0+
> > > > > > > +obj-$(CONFIG_EXTCON_MAX14526) += extcon-max14526.o
> > > > > > > diff --git a/drivers/misc/extcon/extcon-max14526.c 
> > > > > > > b/drivers/misc/extcon/extcon-max14526.c
> > > > > > > new file mode 100644
> > > > > > > index 00..c8505dae49
> > > > > > > --- /dev/null
> > > > > > > +++ b/drivers/misc/extcon/extcon-max14526.c
> > > > > > > @@ -0,0 +1,153 @@
> > > > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > > > +/*
> > > > > > > + * Copyright (c) 2022 Svyatoslav Ryhel 
> > > > > > > + *
> > > > > > > + * U-boot lacks extcon DM.
> > > > > >
> > > > > > In that case I think it is best to add a new uclass for it.
> > > > > >
> > > > > > Regards,
> > > > > > Simon
> > > > >
> > > > > Thank you, Simon!
> > > > >
> > > > > First of all, thanks for your reviews, all of them apart from those I 
> > > > > have
> > > > > responded to are fairly reasonable and will be implemented.
> > > > >
> > > > > About extcon uclass. My vision is to leave this driver as is in misc 
> > > > > for
> > > > > some time and check if there will be any other extcon devices added.
> > > > > In case these devices become at least sometimes used on supported
> > > > > devices there will be good reasons to create a new uclass. As for now,
> > > > > it is a bit pointless to waste time for a new uclass and new 
> > > > > framework for
> > > > > only 

Re: [PATCH v2 7/7] smegw01: Enable EMMC boot from multiple partitions

[Pali Rohár]

On Friday 21 April 2023 07:56:50 Fabio Estevam wrote:
> +uint mmc_get_env_part(struct mmc *mmc)
> +{
> + uint part;
> +
> + if (mmc->part_config == MMCPART_NOAVAILABLE) {
> + part = 0;
> + } else {
> + switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
> + case 0: /* Booting from this eMMC device is disabled */
> + printf("Error - Booting from this eMMC device is 
> disabled\n");
> + printf("Hint: Use 'mmc partconf' command to choose boot 
> partition\n");
> + return -ENODEV;

This does not look to be correct. Return type of the function is uint
but here you are trying to return negative number.

I think that there is some layering or API issue. Caller of this
function probably does not expect any failure and use returned value as
partition number. But you are reading partition number from the source
which may return failure (as the source does not have to contain it).

I'm not sure what is the correct way how to handle these kind of error.
I hope that this is something which you would know.

Which partition want to choose? Same from which was u-boot/spl loaded at
runtime? If yes then maybe this my patch series for mvebu may be
interested for you:
https://lore.kernel.org/u-boot/20230413205750.10641-1-p...@kernel.org/t/#u

I added there ability to store emmc partition from which was bootloader
loaded into access bits of mmc->part_config variable and then via macro
EXT_CSD_EXTRACT_PARTITION_ACCESS() it can be extracted. See function
spl_mmc_emmc_boot_partition() in that mvebu patch series.

But I'm not sure how reliable access bits of mmc->part_config are on
other platforms. As currently only mvebu in that patch series is doing
to use it.

> + case 1: /* Boot partition 1 is used for booting */
> + part = 1;
> + break;
> + case 2: /* Boot partition 2 is used for booting */
> + part = 2;
> + break;
> + case 7: /* User area is used for booting */
> + part = 0;
> + break;
> + default: /* Other values are reserved / unsupported */
> + printf("Error - This eMMC device has configured 
> Reserved boot option\n");
> + printf("Hint: Use 'mmc partconf' command to choose boot 
> partition\n");
> + return -ENODEV;
> + }
> + }
> +
> + return part;
> +}

[PATCH v3 9/9] arm: dts: msm: add GENI SE QUP device tree node

[Vladimir Zapolskiy]

On modern Qualcomm platforms including SDM845 a GENI SE QUP IP
description is supposed to be found in board device tree nodes,
the version of the IP is used by the GENI UART driver to properly
set an oversampling divider value, which impacts UART baudrate.

The change touches dragonboard845c and starqltechn board device
tree source files, a device tree node label to "debug" UART is
renamed to 'uart9' according to the naming found in Linux.

Signed-off-by: Vladimir Zapolskiy 
---
 arch/arm/dts/dragonboard845c.dts |  2 +-
 arch/arm/dts/sdm845.dtsi | 25 +++--
 arch/arm/dts/starqltechn.dts |  2 +-
 3 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/arch/arm/dts/dragonboard845c.dts b/arch/arm/dts/dragonboard845c.dts
index 1722dce33ff2..b4f057ac6537 100644
--- a/arch/arm/dts/dragonboard845c.dts
+++ b/arch/arm/dts/dragonboard845c.dts
@@ -21,7 +21,7 @@
};
 
aliases {
-   serial0 = _uart;
+   serial0 = 
};
 
memory {
diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
index 92bdc82177d6..3b86b9328fc6 100644
--- a/arch/arm/dts/sdm845.dtsi
+++ b/arch/arm/dts/sdm845.dtsi
@@ -51,16 +51,21 @@
};
};
 
-   debug_uart: serial@a84000 {
-   compatible = "qcom,geni-debug-uart";
-   reg = <0xa84000 0x4000>;
-   reg-names = "se_phys";
-   clock-names = "se";
-   clocks = < GCC_QUPV3_WRAP1_S1_CLK>;
-   pinctrl-names = "default";
-   pinctrl-0 = <_uart9>;
-   qcom,wrapper-core = <0x8a>;
-   status = "disabled";
+   qupv3_id_1: geniqup@ac {
+   compatible = "qcom,geni-se-qup";
+   reg = <0x00ac 0x6000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   uart9: serial@a84000 {
+   compatible = "qcom,geni-debug-uart";
+   reg = <0xa84000 0x4000>;
+   clock-names = "se";
+   clocks = < GCC_QUPV3_WRAP1_S1_CLK>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_uart9>;
+   };
};
 
spmi@c44 {
diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts
index 34a4f59cbd17..dcbc3b6d4966 100644
--- a/arch/arm/dts/starqltechn.dts
+++ b/arch/arm/dts/starqltechn.dts
@@ -21,7 +21,7 @@
};
 
aliases {
-   serial0 = _uart;
+   serial0 = 
};
 
memory {
-- 
2.33.0

[PATCH v3 8/9] serial: msm-geni: correct oversampling value based on QUP hardware revision

[Vladimir Zapolskiy]

Starting from QUP v2.5 the value of oversampling is changed from 32
to 16, keeping the old value on newer platforms results on wrong set
UART IP clock divider, thus the asked baudrate does not correspond to
the actually set with all the consequencies for a user.

The change links the driver to a new Qualcomm GENI SE QUP driver
to get its hardware version and update the oversampling value.

Deliberately the code under CONFIG_DEBUG_UART_MSM_GENI is not touched,
since a wanted baudrate can be controlled by setting a modified
CONFIG_DEBUG_UART_CLOCK build time variable.

Signed-off-by: Vladimir Zapolskiy 
---
 drivers/serial/Kconfig   |  2 ++
 drivers/serial/serial_msm_geni.c | 35 +++-
 2 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index bb5083201b38..d50a1fd3f382 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -938,6 +938,8 @@ config MSM_SERIAL
 
 config MSM_GENI_SERIAL
bool "Qualcomm on-chip GENI UART"
+   select MISC
+   imply QCOM_GENI_SE
help
  Support UART based on Generic Interface (GENI) Serial Engine (SE),
  used on Qualcomm Snapdragon SoCs. Should support all qualcomm SOCs
diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index 29fae810d6fe..78fd9389c036 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #define UART_OVERSAMPLING  32
@@ -110,6 +111,10 @@
 #define TX_FIFO_DEPTH_MSK  (GENMASK(21, 16))
 #define TX_FIFO_DEPTH_SHFT 16
 
+/* GENI SE QUP Registers */
+#define QUP_HW_VER_REG 0x4
+#define  QUP_SE_VERSION_2_50x2005
+
 /*
  * Predefined packing configuration of the serial engine (CFG0, CFG1 regs)
  * for uart mode.
@@ -127,6 +132,7 @@ DECLARE_GLOBAL_DATA_PTR;
 struct msm_serial_data {
phys_addr_t base;
u32 baud;
+   u32 oversampling;
 };
 
 unsigned long root_freq[] = {7372800,  14745600, 1920, 29491200,
@@ -246,7 +252,7 @@ static int msm_serial_setbrg(struct udevice *dev, int baud)
 
priv->baud = baud;
 
-   clk_rate = get_clk_div_rate(baud, UART_OVERSAMPLING, _div);
+   clk_rate = get_clk_div_rate(baud, priv->oversampling, _div);
geni_serial_set_clock_rate(dev, clk_rate);
geni_serial_baud(priv->base, clk_div, baud);
 
@@ -480,6 +486,31 @@ static const struct dm_serial_ops msm_serial_ops = {
.setbrg = msm_serial_setbrg,
 };
 
+static void geni_set_oversampling(struct udevice *dev)
+{
+   struct msm_serial_data *priv = dev_get_priv(dev);
+   struct udevice *parent_dev = dev_get_parent(dev);
+   u32 geni_se_version;
+   int ret;
+
+   priv->oversampling = UART_OVERSAMPLING;
+
+   /*
+* It could happen that GENI SE IP is missing in the board's device
+* tree or GENI UART node is a direct child of SoC device tree node.
+*/
+   if (device_get_uclass_id(parent_dev) != UCLASS_MISC)
+   return;
+
+   ret = misc_read(parent_dev, QUP_HW_VER_REG,
+   _se_version, sizeof(geni_se_version));
+   if (ret != sizeof(geni_se_version))
+   return;
+
+   if (geni_se_version >= QUP_SE_VERSION_2_5)
+   priv->oversampling /= 2;
+}
+
 static inline void geni_serial_init(struct udevice *dev)
 {
struct msm_serial_data *priv = dev_get_priv(dev);
@@ -523,6 +554,8 @@ static int msm_serial_probe(struct udevice *dev)
 {
struct msm_serial_data *priv = dev_get_priv(dev);
 
+   geni_set_oversampling(dev);
+
/* No need to reinitialize the UART after relocation */
if (gd->flags & GD_FLG_RELOC)
return 0;
-- 
2.33.0

[PATCH v3 7/9] serial: msm-geni: Use upstream Linux bindings

[Vladimir Zapolskiy]

From: Konrad Dybcio 

The name "se" is used in upstream Linux device trees and has been for
ages, long before this U-Boot-ism was introduced. Same goes for the
existing compatible. Get rid of that.

[vzapolskiy: removed a ready change in the driver]
Signed-off-by: Konrad Dybcio 
Signed-off-by: Vladimir Zapolskiy 
---
 arch/arm/dts/sdm845.dtsi| 4 ++--
 doc/device-tree-bindings/serial/msm-geni-serial.txt | 2 +-
 drivers/serial/serial_msm_geni.c| 4 +++-
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
index 607af277f8be..92bdc82177d6 100644
--- a/arch/arm/dts/sdm845.dtsi
+++ b/arch/arm/dts/sdm845.dtsi
@@ -52,10 +52,10 @@
};
 
debug_uart: serial@a84000 {
-   compatible = "qcom,msm-geni-uart";
+   compatible = "qcom,geni-debug-uart";
reg = <0xa84000 0x4000>;
reg-names = "se_phys";
-   clock-names = "se-clk";
+   clock-names = "se";
clocks = < GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <_uart9>;
diff --git a/doc/device-tree-bindings/serial/msm-geni-serial.txt 
b/doc/device-tree-bindings/serial/msm-geni-serial.txt
index 9eadc2561b4b..eaa39c949b10 100644
--- a/doc/device-tree-bindings/serial/msm-geni-serial.txt
+++ b/doc/device-tree-bindings/serial/msm-geni-serial.txt
@@ -1,6 +1,6 @@
 Qualcomm GENI UART
 
 Required properties:
-- compatible: must be "qcom,msm-geni-uart"
+- compatible: must be "qcom,geni-debug-uart"
 - reg: start address and size of the registers
 - clock: interface clock (must accept baudrate as a frequency)
diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index 3a200f45a6ce..29fae810d6fe 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -547,7 +547,9 @@ static int msm_serial_ofdata_to_platdata(struct udevice 
*dev)
 }
 
 static const struct udevice_id msm_serial_ids[] = {
-   {.compatible = "qcom,msm-geni-uart"}, {}};
+   { .compatible = "qcom,geni-debug-uart" },
+   { }
+};
 
 U_BOOT_DRIVER(serial_msm_geni) = {
.name = "serial_msm_geni",
-- 
2.33.0

[PATCH v3 6/9] serial: msm-geni: fix a compile time warning from msm_serial_setbrg()

[Vladimir Zapolskiy]

A compiler warns about a missing function prototype, which is valid
and fixed by converting the function into static one, also fix
interleaved local variable declarations and assignments.

Signed-off-by: Vladimir Zapolskiy 
Fixes: 324df15a292e ("serial: qcom: add support for GENI serial driver")
Reviewed-by: Konrad Dybcio 
---
 drivers/serial/serial_msm_geni.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index 55dd9188a56c..3a200f45a6ce 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -238,13 +238,13 @@ static inline void geni_serial_baud(phys_addr_t 
base_address, u32 clk_div,
writel(s_clk_cfg, base_address + GENI_SER_S_CLK_CFG);
 }
 
-int msm_serial_setbrg(struct udevice *dev, int baud)
+static int msm_serial_setbrg(struct udevice *dev, int baud)
 {
struct msm_serial_data *priv = dev_get_priv(dev);
+   u64 clk_rate;
+   u32 clk_div;
 
priv->baud = baud;
-   u32 clk_div;
-   u64 clk_rate;
 
clk_rate = get_clk_div_rate(baud, UART_OVERSAMPLING, _div);
geni_serial_set_clock_rate(dev, clk_rate);
-- 
2.33.0

[PATCH v3 5/9] serial: msm-geni: fix code indentation

[Vladimir Zapolskiy]

This a cosmetic change, which corrects code indentation in a few places.

Signed-off-by: Vladimir Zapolskiy 
Reviewed-by: Konrad Dybcio 
---
 drivers/serial/serial_msm_geni.c | 11 +--
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index 8fd769eb4d0d..55dd9188a56c 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -130,8 +130,8 @@ struct msm_serial_data {
 };
 
 unsigned long root_freq[] = {7372800,  14745600, 1920, 29491200,
-3200, 4800, 6400, 8000,
-9600, 1};
+3200, 4800, 6400, 8000,
+9600, 1};
 
 /**
  * get_clk_cfg() - Get clock rate to apply on clock supplier.
@@ -160,8 +160,7 @@ static int get_clk_cfg(unsigned long clk_freq)
  *
  * Return: frequency, supported by clock supplier, multiple of clk_freq.
  */
-static int get_clk_div_rate(u32 baud,
-   u64 sampling_rate, u32 
*clk_div)
+static int get_clk_div_rate(u32 baud, u64 sampling_rate, u32 *clk_div)
 {
unsigned long ser_clk;
unsigned long desired_clk;
@@ -228,7 +227,7 @@ static inline u32 geni_se_get_tx_fifo_width(long base)
 }
 
 static inline void geni_serial_baud(phys_addr_t base_address, u32 clk_div,
-   int 
baud)
+   int baud)
 {
u32 s_clk_cfg = 0;
 
@@ -268,7 +267,7 @@ int msm_serial_setbrg(struct udevice *dev, int baud)
  * reached.
  */
 static bool qcom_geni_serial_poll_bit(const struct udevice *dev, int offset,
- int field, bool set)
+ int field, bool set)
 {
u32 reg;
struct msm_serial_data *priv = dev_get_priv(dev);
-- 
2.33.0

[PATCH v3 4/9] serial: msm-geni: remove invalid se-clk clock name

[Vladimir Zapolskiy]

There is only one clock supplier to the serial IP, thus getting it by
name is not needed, also note that "clock-names" property is not listed
under doc/device-tree-bindings/serial/msm-geni-serial.txt, and finally
"se-clk" clock name is invalid, if added, it shall get "se" value like
it's already described in Linux device tree documentation.

Signed-off-by: Vladimir Zapolskiy 
Reviewed-by: Konrad Dybcio 
---
 drivers/serial/serial_msm_geni.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index 146b05748459..8fd769eb4d0d 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -183,7 +183,7 @@ static int geni_serial_set_clock_rate(struct udevice *dev, 
u64 rate)
struct clk *clk;
int ret;
 
-   clk = devm_clk_get(dev, "se-clk");
+   clk = devm_clk_get(dev, NULL);
if (!clk)
return -EINVAL;
 
-- 
2.33.0

[PATCH v3 3/9] serial: msm-geni: Always bind before relocation

[Vladimir Zapolskiy]

From: Konrad Dybcio 

In preparation for supporting upstream Linux device trees on Qualcomm
platforms, make this the default behavior.

[vzapolskiy: extracted the driver change from a combination with dts changes]
Signed-off-by: Konrad Dybcio 
Signed-off-by: Vladimir Zapolskiy 
---
 drivers/serial/serial_msm_geni.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index df61ae04df0a..146b05748459 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -558,6 +558,7 @@ U_BOOT_DRIVER(serial_msm_geni) = {
.priv_auto = sizeof(struct msm_serial_data),
.probe = msm_serial_probe,
.ops = _serial_ops,
+   .flags = DM_FLAG_PRE_RELOC,
 };
 
 #ifdef CONFIG_DEBUG_UART_MSM_GENI
-- 
2.33.0

[PATCH v3 2/9] serial: msm-geni: remove redundant includes

[Vladimir Zapolskiy]

For whatever reason, likely a driver stub was copied from another
driver, the driver contains a bunch of unnecessary and confusing
includes like watchdog.h etc., the change reduces the list.

Signed-off-by: Vladimir Zapolskiy 
Reviewed-by: Konrad Dybcio 
---
 drivers/serial/serial_msm_geni.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index 3943ca43e49e..df61ae04df0a 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -11,15 +11,9 @@
 #include 
 #include 
 #include 
-#include 
 #include 
-#include 
-#include 
 #include 
-#include 
 #include 
-#include 
-#include 
 
 #define UART_OVERSAMPLING  32
 #define STALE_TIMEOUT  160
-- 
2.33.0

[PATCH v3 1/9] misc: add Qualcomm GENI SE QUP device driver

[Vladimir Zapolskiy]

This change adds a Qualcomm GENI SE QUP device driver as a wrapper for
actually enabled and used serial devices found on a board.

At the moment the driver is pretty simple, its intention is to populate
childred devices and provide I/O mem read interface to them as clients,
this is needed for GENI UART driver to set up a proper clock divider
and provide the actually asked baud rate.

Signed-off-by: Vladimir Zapolskiy 
Reviewed-by: Konrad Dybcio 
---
 drivers/misc/Kconfig|  7 +++
 drivers/misc/Makefile   |  1 +
 drivers/misc/qcom-geni-se.c | 41 +
 3 files changed, 49 insertions(+)
 create mode 100644 drivers/misc/qcom-geni-se.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index b5707a15c504..fc4c893334d3 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -511,6 +511,13 @@ config WINBOND_W83627
  legacy UART or other devices in the Winbond Super IO chips
  on X86 platforms.
 
+config QCOM_GENI_SE
+   bool "Qualcomm GENI Serial Engine Driver"
+   depends on ARCH_SNAPDRAGON
+   help
+ The driver manages Generic Interface (GENI) firmware based
+ Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper.
+
 config QFW
bool
help
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 3b792f2a14ce..52aed096021f 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
 obj-$(CONFIG_P2SB) += p2sb-uclass.o
 obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
 obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
+obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
 ifdef CONFIG_QFW
 obj-y += qfw.o
 obj-$(CONFIG_QFW_PIO) += qfw_pio.o
diff --git a/drivers/misc/qcom-geni-se.c b/drivers/misc/qcom-geni-se.c
new file mode 100644
index ..281a5ec819a9
--- /dev/null
+++ b/drivers/misc/qcom-geni-se.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm Generic Interface (GENI) Serial Engine (SE) Wrapper
+ *
+ * Copyright (C) 2023 Linaro Ltd. 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static int geni_se_qup_read(struct udevice *dev, int offset,
+   void *buf, int size)
+{
+   fdt_addr_t base = dev_read_addr(dev);
+
+   if (size != sizeof(u32))
+   return -EINVAL;
+
+   *(u32 *)buf = readl(base + offset);
+
+   return size;
+}
+
+static struct misc_ops geni_se_qup_ops = {
+   .read = geni_se_qup_read,
+};
+
+static const struct udevice_id geni_se_qup_ids[] = {
+   { .compatible = "qcom,geni-se-qup" },
+   {}
+};
+
+U_BOOT_DRIVER(geni_se_qup) = {
+   .name = "geni_se_qup",
+   .id = UCLASS_MISC,
+   .of_match = geni_se_qup_ids,
+   .ops = _se_qup_ops,
+   .flags  = DM_FLAG_PRE_RELOC,
+};
-- 
2.33.0

[PATCH v3 0/9] serial: msm-geni: fix UART baudrate on modern platforms

[Vladimir Zapolskiy]

The changeset touches Qualcomm platforms, it adds a new quite trivial
misc wrapper driver to be accessed by GENI UART to get information
about a proper clock divisor.

The change does not intend to break any currently supported Qualcomm
platforms, there should be no need to update board config or dts files.

Changes from v2 to v3:
* fixed return value of misc_read() from the new GENI SE QUP driver,
  thanks to Simon for the review comment.

Changes from v1 to v2:
* fixes according to the code review by Konrad,
* added two changes developed by Konrad to the series,
* removed .bind from the GENI SE wrapper driver,
* minor fix in MSM GENI serial driver Kconfig to match the new changes,
* changed dts files of SDM845 powered boards by adding GENI SE wrapper.

Konrad Dybcio (2):
  serial: msm-geni: Always bind before relocation
  serial: msm-geni: Use upstream Linux bindings

Vladimir Zapolskiy (7):
  misc: add Qualcomm GENI SE QUP device driver
  serial: msm-geni: remove redundant includes
  serial: msm-geni: remove invalid se-clk clock name
  serial: msm-geni: fix code indentation
  serial: msm-geni: fix a compile time warning from msm_serial_setbrg()
  serial: msm-geni: correct oversampling value based on QUP hardware revision
  arm: dts: msm: add GENI SE QUP device tree node

 arch/arm/dts/dragonboard845c.dts  |  2 +-
 arch/arm/dts/sdm845.dtsi  | 25 ---
 arch/arm/dts/starqltechn.dts  |  2 +-
 .../serial/msm-geni-serial.txt|  2 +-
 drivers/misc/Kconfig  |  7 ++
 drivers/misc/Makefile |  1 +
 drivers/misc/qcom-geni-se.c   | 41 
 drivers/serial/Kconfig|  2 +
 drivers/serial/serial_msm_geni.c  | 65 ++-
 9 files changed, 116 insertions(+), 31 deletions(-)
 create mode 100644 drivers/misc/qcom-geni-se.c

-- 
2.33.0

Re: [PATCH 1/3] vexpress64: Use OF_HAS_PRIOR_STAGE for BASE_FVP variant

[Andre Przywara]

On Fri, 31 Mar 2023 09:58:11 +0100
Peter Hoyes  wrote:

> From: Peter Hoyes 
> 
> BASE_FVP now typically uses a devicetree provided by a prior boot stage
> (typically Arm TF-A), so imply this option by default when
> TARGET_VEXPRESS64_BASE_FVP is selected.
> 
> OF_HAS_PRIOR_STAGE selects OF_BOARD so this change is minor, but aligns
> TARGET_VEXPRESS64_BASE_FVP with TARGET_VEXPRESS64_BASER_FVP.

Yeah, makes sense. Both secure firmware implementations commonly used
(boot-wrapper and TF-A) provide a DTB.

> Signed-off-by: Peter Hoyes 

Reviewed-by: Andre Przywara 

Cheers,
Andre

> ---
>  board/armltd/vexpress64/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig
> index 5616e223a9..bd15cbeb7e 100644
> --- a/board/armltd/vexpress64/Kconfig
> +++ b/board/armltd/vexpress64/Kconfig
> @@ -23,7 +23,7 @@ choice
>  config TARGET_VEXPRESS64_BASE_FVP
>   bool "Support Versatile Express ARMv8a FVP BASE model"
>   select VEXPRESS64_BASE_MODEL
> - select OF_BOARD
> + imply OF_HAS_PRIOR_STAGE
>  
>  config TARGET_VEXPRESS64_BASER_FVP
>   bool "Support Versatile Express ARMv8r64 FVP BASE model"

Re: [PATCH v1 1/1] misc: extcon: add MAX14526 MUIC support

[Svyatoslav Ryhel]

пт, 21 квіт. 2023 р. о 19:30 Tim Harvey  пише:
>
> On Thu, Apr 20, 2023 at 9:54 AM Svyatoslav Ryhel  wrote:
> >
> > чт, 20 квіт. 2023 р. о 19:30 Simon Glass  пише:
> > >
> > > Hi Svyatoslav,
> > >
> > > On Thu, 20 Apr 2023 at 18:01, Svyatoslav Ryhel  wrote:
> > > >
> > > > чт, 20 квіт. 2023 р. о 01:41 Simon Glass  пише:
> > > > >
> > > > > Hi Svyatoslav,
> > > > >
> > > > > On Wed, 19 Apr 2023 at 12:53, Svyatoslav Ryhel  
> > > > > wrote:
> > > > > >
> > > > > > MAX14526 is a powerful extcon chip which allows detection of various
> > > > > > plugs like usb, mhl, uart, headset etc. This version of driver
> > > > > > implements support of AP-usb and CP-usb/uart paths.
> > > > > >
> > > > > > Tested-by: Andreas Westman Dorcsak  # LG P880 T30
> > > > > > Tested-by: Svyatoslav Ryhel  # LG P895 T30
> > > > > > Signed-off-by: Svyatoslav Ryhel 
> > > > > > ---
> > > > > >  drivers/misc/Kconfig  |   2 +
> > > > > >  drivers/misc/Makefile |   1 +
> > > > > >  drivers/misc/extcon/Kconfig   |   8 ++
> > > > > >  drivers/misc/extcon/Makefile  |   2 +
> > > > > >  drivers/misc/extcon/extcon-max14526.c | 153 
> > > > > > ++
> > > > > >  5 files changed, 166 insertions(+)
> > > > > >  create mode 100644 drivers/misc/extcon/Kconfig
> > > > > >  create mode 100644 drivers/misc/extcon/Makefile
> > > > > >  create mode 100644 drivers/misc/extcon/extcon-max14526.c
> > > > > >
> > > > > > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> > > > > > index 4e1ae03e9f..1b49f3cf72 100644
> > > > > > --- a/drivers/misc/Kconfig
> > > > > > +++ b/drivers/misc/Kconfig
> > > > > > @@ -659,4 +659,6 @@ config SL28CPLD
> > > > > >   the base driver which provides common access methods for 
> > > > > > the
> > > > > >   sub-drivers.
> > > > > >
> > > > > > +source "drivers/misc/extcon/Kconfig"
> > > > > > +
> > > > > >  endmenu
> > > > > > diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> > > > > > index 3b792f2a14..6d4fc8ddf9 100644
> > > > > > --- a/drivers/misc/Makefile
> > > > > > +++ b/drivers/misc/Makefile
> > > > > > @@ -87,3 +87,4 @@ obj-$(CONFIG_K3_AVS0) += k3_avs.o
> > > > > >  obj-$(CONFIG_ESM_K3) += k3_esm.o
> > > > > >  obj-$(CONFIG_ESM_PMIC) += esm_pmic.o
> > > > > >  obj-$(CONFIG_SL28CPLD) += sl28cpld.o
> > > > > > +obj-y += extcon/
> > > > > > diff --git a/drivers/misc/extcon/Kconfig 
> > > > > > b/drivers/misc/extcon/Kconfig
> > > > > > new file mode 100644
> > > > > > index 00..99c38224f3
> > > > > > --- /dev/null
> > > > > > +++ b/drivers/misc/extcon/Kconfig
> > > > > > @@ -0,0 +1,8 @@
> > > > > > +config EXTCON_MAX14526
> > > > > > +   bool "Maxim MAX14526 EXTCON Support"
> > > > > > +   select DM_I2C
> > > > > > +   select DM_MISC
> > > > > > +   help
> > > > > > + If you say yes here you get support for the MUIC device of
> > > > > > + Maxim MAX14526. The MAX14526 MUIC is a USB port accessory
> > > > > > + detector and switch.
> > > > > > diff --git a/drivers/misc/extcon/Makefile 
> > > > > > b/drivers/misc/extcon/Makefile
> > > > > > new file mode 100644
> > > > > > index 00..f012b688ce
> > > > > > --- /dev/null
> > > > > > +++ b/drivers/misc/extcon/Makefile
> > > > > > @@ -0,0 +1,2 @@
> > > > > > +# SPDX-License-Identifier: GPL-2.0+
> > > > > > +obj-$(CONFIG_EXTCON_MAX14526) += extcon-max14526.o
> > > > > > diff --git a/drivers/misc/extcon/extcon-max14526.c 
> > > > > > b/drivers/misc/extcon/extcon-max14526.c
> > > > > > new file mode 100644
> > > > > > index 00..c8505dae49
> > > > > > --- /dev/null
> > > > > > +++ b/drivers/misc/extcon/extcon-max14526.c
> > > > > > @@ -0,0 +1,153 @@
> > > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > > +/*
> > > > > > + * Copyright (c) 2022 Svyatoslav Ryhel 
> > > > > > + *
> > > > > > + * U-boot lacks extcon DM.
> > > > >
> > > > > In that case I think it is best to add a new uclass for it.
> > > > >
> > > > > Regards,
> > > > > Simon
> > > >
> > > > Thank you, Simon!
> > > >
> > > > First of all, thanks for your reviews, all of them apart from those I 
> > > > have
> > > > responded to are fairly reasonable and will be implemented.
> > > >
> > > > About extcon uclass. My vision is to leave this driver as is in misc for
> > > > some time and check if there will be any other extcon devices added.
> > > > In case these devices become at least sometimes used on supported
> > > > devices there will be good reasons to create a new uclass. As for now,
> > > > it is a bit pointless to waste time for a new uclass and new framework 
> > > > for
> > > > only one device used by one board.
> > >
> > > I am sure there will be more.
> > >
> > > The problem with accepting this patch as is, is that the burden of
> > > creating the uclass (which is actually not that large at all) falls on
> > > the second driver submitter, as well as the burden of converting your
> > > driver. In practice what happens is that no one can 

Re: [PATCH v1 1/1] misc: extcon: add MAX14526 MUIC support

[Tim Harvey]

On Thu, Apr 20, 2023 at 9:54 AM Svyatoslav Ryhel  wrote:
>
> чт, 20 квіт. 2023 р. о 19:30 Simon Glass  пише:
> >
> > Hi Svyatoslav,
> >
> > On Thu, 20 Apr 2023 at 18:01, Svyatoslav Ryhel  wrote:
> > >
> > > чт, 20 квіт. 2023 р. о 01:41 Simon Glass  пише:
> > > >
> > > > Hi Svyatoslav,
> > > >
> > > > On Wed, 19 Apr 2023 at 12:53, Svyatoslav Ryhel  
> > > > wrote:
> > > > >
> > > > > MAX14526 is a powerful extcon chip which allows detection of various
> > > > > plugs like usb, mhl, uart, headset etc. This version of driver
> > > > > implements support of AP-usb and CP-usb/uart paths.
> > > > >
> > > > > Tested-by: Andreas Westman Dorcsak  # LG P880 T30
> > > > > Tested-by: Svyatoslav Ryhel  # LG P895 T30
> > > > > Signed-off-by: Svyatoslav Ryhel 
> > > > > ---
> > > > >  drivers/misc/Kconfig  |   2 +
> > > > >  drivers/misc/Makefile |   1 +
> > > > >  drivers/misc/extcon/Kconfig   |   8 ++
> > > > >  drivers/misc/extcon/Makefile  |   2 +
> > > > >  drivers/misc/extcon/extcon-max14526.c | 153 
> > > > > ++
> > > > >  5 files changed, 166 insertions(+)
> > > > >  create mode 100644 drivers/misc/extcon/Kconfig
> > > > >  create mode 100644 drivers/misc/extcon/Makefile
> > > > >  create mode 100644 drivers/misc/extcon/extcon-max14526.c
> > > > >
> > > > > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> > > > > index 4e1ae03e9f..1b49f3cf72 100644
> > > > > --- a/drivers/misc/Kconfig
> > > > > +++ b/drivers/misc/Kconfig
> > > > > @@ -659,4 +659,6 @@ config SL28CPLD
> > > > >   the base driver which provides common access methods for the
> > > > >   sub-drivers.
> > > > >
> > > > > +source "drivers/misc/extcon/Kconfig"
> > > > > +
> > > > >  endmenu
> > > > > diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> > > > > index 3b792f2a14..6d4fc8ddf9 100644
> > > > > --- a/drivers/misc/Makefile
> > > > > +++ b/drivers/misc/Makefile
> > > > > @@ -87,3 +87,4 @@ obj-$(CONFIG_K3_AVS0) += k3_avs.o
> > > > >  obj-$(CONFIG_ESM_K3) += k3_esm.o
> > > > >  obj-$(CONFIG_ESM_PMIC) += esm_pmic.o
> > > > >  obj-$(CONFIG_SL28CPLD) += sl28cpld.o
> > > > > +obj-y += extcon/
> > > > > diff --git a/drivers/misc/extcon/Kconfig b/drivers/misc/extcon/Kconfig
> > > > > new file mode 100644
> > > > > index 00..99c38224f3
> > > > > --- /dev/null
> > > > > +++ b/drivers/misc/extcon/Kconfig
> > > > > @@ -0,0 +1,8 @@
> > > > > +config EXTCON_MAX14526
> > > > > +   bool "Maxim MAX14526 EXTCON Support"
> > > > > +   select DM_I2C
> > > > > +   select DM_MISC
> > > > > +   help
> > > > > + If you say yes here you get support for the MUIC device of
> > > > > + Maxim MAX14526. The MAX14526 MUIC is a USB port accessory
> > > > > + detector and switch.
> > > > > diff --git a/drivers/misc/extcon/Makefile 
> > > > > b/drivers/misc/extcon/Makefile
> > > > > new file mode 100644
> > > > > index 00..f012b688ce
> > > > > --- /dev/null
> > > > > +++ b/drivers/misc/extcon/Makefile
> > > > > @@ -0,0 +1,2 @@
> > > > > +# SPDX-License-Identifier: GPL-2.0+
> > > > > +obj-$(CONFIG_EXTCON_MAX14526) += extcon-max14526.o
> > > > > diff --git a/drivers/misc/extcon/extcon-max14526.c 
> > > > > b/drivers/misc/extcon/extcon-max14526.c
> > > > > new file mode 100644
> > > > > index 00..c8505dae49
> > > > > --- /dev/null
> > > > > +++ b/drivers/misc/extcon/extcon-max14526.c
> > > > > @@ -0,0 +1,153 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > +/*
> > > > > + * Copyright (c) 2022 Svyatoslav Ryhel 
> > > > > + *
> > > > > + * U-boot lacks extcon DM.
> > > >
> > > > In that case I think it is best to add a new uclass for it.
> > > >
> > > > Regards,
> > > > Simon
> > >
> > > Thank you, Simon!
> > >
> > > First of all, thanks for your reviews, all of them apart from those I have
> > > responded to are fairly reasonable and will be implemented.
> > >
> > > About extcon uclass. My vision is to leave this driver as is in misc for
> > > some time and check if there will be any other extcon devices added.
> > > In case these devices become at least sometimes used on supported
> > > devices there will be good reasons to create a new uclass. As for now,
> > > it is a bit pointless to waste time for a new uclass and new framework for
> > > only one device used by one board.
> >
> > I am sure there will be more.
> >
> > The problem with accepting this patch as is, is that the burden of
> > creating the uclass (which is actually not that large at all) falls on
> > the second driver submitter, as well as the burden of converting your
> > driver. In practice what happens is that no one can be bothered.
> >
> > See UCLASS_PCH for a simple uclass. You just need to define the API
> > (which may just be empty), any uclass-private struct then add
> > something to test.dst and a simple test to test/dm/extcon.c
> >
> > Regards
> >
> > Simon
>
> Ok, I will look into this a bit deeper

Svyatoslav,

I agree with 

[PATCH] board: rockchip: add Anbernic RGXX3 Series Devices

[Chris Morgan]

From: Chris Morgan 

The Anbernic RGxx3 is a "pseudo-device" that encompasses the following
devices:

 - Anbernic RG353M
 - Anbernic RG353P
 - Anbernic RG353V
 - Anbernic RG353VS
 - Anbernic RG503

The rk3566-anbernic-rgxx3.dtsi is synced with upstream Linux, but
rk3566-anbernic-rgxx3.dts is a U-Boot specific devicetree that
is used for all RGxx3 devices.

Via the board.c file, the bootloader automatically sets the correct
fdtfile, board, and board_name environment variables so that the
correct devicetree can be passed to Linux. It is also possible to
simply hard-code a single devicetree in the boot.scr file and use
that to load Linux as well.

The common specifications for each device are:

 - Rockchip RK3566 SoC
 - 2 external SDMMC slots
 - 1 USB-C host port, 1 USB-C peripheral port
 - 1 mini-HDMI output
 - MIPI-DSI based display panel
 - ADC controlled joysticks with a GPIO mux
 - GPIO buttons
 - A PWM controlled vibrator
 - An ADC controlled button

All of the common features are defined in the devicetree synced from
upstream Linux.

TODO: DSI panel auto-detection for the RG353 devices (requires porting
of DSI controller driver and DSI-DPHY driver to send DSI commands to
the panel).

Signed-off-by: Chris Morgan 

Changes from V1:
 - Fixed sphinx error for title underline.
 - Updated u-boot.dtsi file to support bootph.
---
 arch/arm/dts/Makefile |   1 +
 .../arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi |  86 ++
 arch/arm/dts/rk3566-anbernic-rgxx3.dts|  18 +
 arch/arm/dts/rk3566-anbernic-rgxx3.dtsi   | 786 ++
 arch/arm/mach-rockchip/rk3568/Kconfig |  14 +
 board/anbernic/rgxx3_rk3566/Kconfig   |  15 +
 board/anbernic/rgxx3_rk3566/MAINTAINERS   |   6 +
 board/anbernic/rgxx3_rk3566/Makefile  |   6 +
 board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c| 203 +
 configs/anbernic-rgxx3_defconfig  |  78 ++
 doc/board/anbernic/index.rst  |   9 +
 doc/board/anbernic/rgxx3.rst  |  47 ++
 doc/board/index.rst   |   1 +
 doc/board/rockchip/rockchip.rst   |   3 +
 include/configs/anbernic-rgxx3-rk3566.h   |  12 +
 15 files changed, 1285 insertions(+)
 create mode 100644 arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3566-anbernic-rgxx3.dts
 create mode 100644 arch/arm/dts/rk3566-anbernic-rgxx3.dtsi
 create mode 100644 board/anbernic/rgxx3_rk3566/Kconfig
 create mode 100644 board/anbernic/rgxx3_rk3566/MAINTAINERS
 create mode 100644 board/anbernic/rgxx3_rk3566/Makefile
 create mode 100644 board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
 create mode 100644 configs/anbernic-rgxx3_defconfig
 create mode 100644 doc/board/anbernic/index.rst
 create mode 100644 doc/board/anbernic/rgxx3.rst
 create mode 100644 include/configs/anbernic-rgxx3-rk3566.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 337bee7e1e..22cb5bc3db 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -165,6 +165,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399pro-rock-pi-n10.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3568) += \
+   rk3566-anbernic-rgxx3.dtb \
rk3568-evb.dtb \
rk3566-radxa-cm3-io.dtb \
rk3568-rock-3a.dtb
diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi 
b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
new file mode 100644
index 00..a18e5d1cf7
--- /dev/null
+++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   u-boot,spl-boot-order = "same-as-spl", , 
+   };
+
+   rng: rng@fe388000 {
+   compatible = "rockchip,cryptov2-rng";
+   reg = <0x0 0xfe388000 0x0 0x2000>;
+   status = "okay";
+   };
+};
+
+ {
+   assigned-clocks =
+   < CLK_RTC_32K>,
+   < PLL_PPLL>,
+   < PCLK_PMU>, < PLL_CPLL>,
+   < PLL_GPLL>,
+   < ACLK_BUS>, < PCLK_BUS>,
+   < ACLK_TOP_HIGH>, < ACLK_TOP_LOW>,
+   < HCLK_TOP>, < PCLK_TOP>,
+   < ACLK_PERIMID>, < HCLK_PERIMID>,
+   < CPLL_500M>, < CPLL_333M>,
+   < CPLL_250M>, < CPLL_125M>,
+   < CPLL_100M>, < CPLL_62P5M>,
+   < CPLL_50M>, < CPLL_25M>;
+   assigned-clock-rates =
+   <32768>,
+   <2>,
+   <1>, <10>,
+   <118800>,
+   <15000>, <1>,
+   <5>, <4>,
+   <15000>, <1>,
+   <3>, <15000>,
+   <5>, <3>,
+   

Re: [PATCH v8 00/24] Fixes for Rockchip NFC driver part 1

[Johan Jonker]

On 4/21/23 05:15, Kever Yang wrote:
> Hi Johan,
> 
>     I got below error report from CI test, I think it should be relate to 
> this patch set.
> 
> === FAILURES 
> ===
> 1107 
> _
>  test_ut[ut_dm_dm_test_fdt_get_addr_ptr_flat] _
> 1108 
> test/py/tests/test_ut.py:346:
>  in test_ut
> 1109 
> assert
>  output.endswith('Failures: 0')
> 1110 
> E
>  AssertionError: assert False
>  
> E
>  + where False =  0x7f7089240c10>('Failures: 0')
> 1112 
> E
>  + where  = 'Test: 
> dm_test_fdt_get_addr_ptr_flat: test-fdt.c (flat 
> tree)\r\r\ntest/dm/test-fdt.c:627, 

dm_test_fdt_get_addr_ptr_fla...xpected 8000, got 
10009000\r\r\nTest dm_test_fdt_get_addr_ptr_flat failed 1 
times\r\r\nFailures: 1'.endswith

It turns out that the suggestion by Simon to use map_sysmem() doesn't work with 
devfdt_get_addr_index_ptr() somehow.

To reproduce with this serie:
make sandbox_defconfig all
./u-boot -T -c "ut dm fdt*"

Test: dm_test_fdt_get_addr_ptr_flat: test-fdt.c (flat tree)
test/dm/test-fdt.c:627, dm_test_fdt_get_addr_ptr_flat(): (void *)0x8000 = ptr: 
Expected 8000, got 10009000
Test fdt* failed 1 times

===

Could Simon have a look at the internal map_sysmem() stuff?

Will send 1 patch to replace:
[PATCH v8 14/24] core: fdtaddr: add devfdt_get_addr_size_index_ptr function

for:

[PATCH v9] core: fdtaddr: add devfdt_get_addr_size_index_ptr function

Could Kever retest with the patch above replacement?

Johan

> 
> 
> Thanks,
> - Kever
> On 2023/3/13 08:23, Johan Jonker wrote:
>> This serie contains fixes for the Rockchip NFC driver,
>> which was ported to U-boot and merged with little review
>> and testing it seems.
>> Part 1 aims at passing the probe function without errors.
>> Extended with tree wide function cleanup needed for 64bit DT parsing.
>>
>> Fixed are:
>>   64bit FDT parsing
>>   compatible string removal
>>   add missing layout structure
>>   add missing flash_node pointer
>>   add missing chip ID
>>
>> Changed V8:
>>   change comments
>>   use uintptr_t size instead of phys_addr_t
>>   add another fdt_addr_t fix
>>
>> Changed V7:
>>   add proof of concept for syscon node with variable reg size handling
>>   use another map_sysmem() function as cast
>>   remove cast
>>
>> Changed V6:
>>   use -EINVAL on return
>>   drop cast
>>   use map_sysmem() function as cast
>>   add and rename patch
>>
>> Changed V5:
>>   sort patch order
>>   add more fixes with pointer functions
>>   add debug text fixes
>>   test with binman for ARM only due to limited resources
>>
>> Changed V4:
>>   fix cast and divider in syscon-uclass.c
>>
>> Changed V3:
>>   use dev_read_addr_ptr
>>   fix oobfree
>>
>> Johan Jonker (23):
>>   mtd: nand: raw: rockchip_nfc: use dev_read_addr_ptr
>>   mtd: nand: raw: rockchip_nfc: remove the compatible string
>> "rockchip,rk3308-nfc"
>>   mtd: nand: raw: rockchip_nfc: add layout structure
>>   mtd: nand: raw: rockchip_nfc: add flash_node to chip structure
>>   mtd: nand: raw: rockchip_nfc: fix oobfree offset and description
>>   rockchip: adc: rockchip-saradc: use dev_read_addr_ptr
>>   rockchip: timer: dw-apb-timer: use regs variable with uintptr_t size
>>   rockchip: pwm: rk_pwm: use base variable with uintptr_t size
>>   rockchip: spi: rk_spi: use base variable with uintptr_t size
>>   include: dm: ofnode: fix headers
>>   core: remap: fix regmap_init_mem_plat() reg size handeling
>>   rockchip: rk3288: syscon_rk3288: store syscon platdata in regmap
>>   core: fdtaddr: add devfdt_get_addr_size_index_ptr function
>>   core: read: add dev_read_addr_index_ptr function
>>   spi: spi-aspeed-smc: use devfdt_get_addr_index_ptr
>>   drivers: use dev_read_addr_index_ptr when cast to pointer
>>   drivers: use dev_read_addr_ptr when cast to pointer
>>   drivers: use devfdt_get_addr_size_index_ptr when cast to pointer
>>   drivers: use devfdt_get_addr_index_ptr when cast to pointer
>>   drivers: use devfdt_get_addr_ptr when cast to pointer
>>   drivers: fix debug string with fdt_addr_t input
>>   arm: stm32mp: spl: fix function with fdt_addr_t input
>>   include: fdtdec: decouple fdt_addr_t and phys_addr_t size
>>
>> Paweł Jarosz (1):
>>   mtd: nand: add support for the Sandisk SDTNQGAMA chip
>>
>>  Kconfig   |   8 ++
>>  arch/arm/mach-mvebu/cpu.c |   2 +-
>>  arch/arm/mach-mvebu/system-controller.c   |   4 +-
>>  

[PATCH v9] core: fdtaddr: add devfdt_get_addr_size_index_ptr function

[Johan Jonker]

Add devfdt_get_addr_size_index_ptr function with the same
functionality as devfdt_get_addr_size_index, but instead
a return pointer is given.

Suggested-by: Michael Nazzareno Trimarchi 
Signed-off-by: Johan Jonker 
Reviewed-by: Michael Trimarchi 
Reviewed-by: Simon Glass 
---

Changed V9:
  remove map_sysmem()

Changed V7:
  use map_sysmem()

Changed V5:
  fix spelling
  use tabs
---
 drivers/core/fdtaddr.c |  8 
 include/dm/fdtaddr.h   | 17 -
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c
index a499f3b5..a68e31df 100644
--- a/drivers/core/fdtaddr.c
+++ b/drivers/core/fdtaddr.c
@@ -134,6 +134,14 @@ fdt_addr_t devfdt_get_addr_size_index(const struct udevice 
*dev, int index,
 #endif
 }

+void *devfdt_get_addr_size_index_ptr(const struct udevice *dev, int index,
+fdt_size_t *size)
+{
+   fdt_addr_t addr = devfdt_get_addr_size_index(dev, index, size);
+
+   return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr;
+}
+
 fdt_addr_t devfdt_get_addr_name(const struct udevice *dev, const char *name)
 {
 #if CONFIG_IS_ENABLED(OF_CONTROL)
diff --git a/include/dm/fdtaddr.h b/include/dm/fdtaddr.h
index c9d2b27b..dcdc1913 100644
--- a/include/dm/fdtaddr.h
+++ b/include/dm/fdtaddr.h
@@ -111,7 +111,7 @@ void *devfdt_get_addr_index_ptr(const struct udevice *dev, 
int index);
  * @dev: Pointer to a device
  * @index: the 'reg' property can hold a list of  pairs
  *and @index is used to select which one is required
- * @size: Pointer to size varible - this function returns the size
+ * @size: Pointer to size variable - this function returns the size
  *specified in the 'reg' property here
  *
  * Return: addr
@@ -119,6 +119,21 @@ void *devfdt_get_addr_index_ptr(const struct udevice *dev, 
int index);
 fdt_addr_t devfdt_get_addr_size_index(const struct udevice *dev, int index,
  fdt_size_t *size);

+/**
+ * devfdt_get_addr_size_index_ptr() - Return indexed pointer to the address of 
the
+ *reg property of a device
+ *
+ * @dev: Pointer to a device
+ * @index: the 'reg' property can hold a list of  pairs
+ *and @index is used to select which one is required
+ * @size: Pointer to size variable - this function returns the size
+ *specified in the 'reg' property here
+ *
+ * Return: Pointer to addr, or NULL if there is no such property
+ */
+void *devfdt_get_addr_size_index_ptr(const struct udevice *dev, int index,
+fdt_size_t *size);
+
 /**
  * devfdt_get_addr_name() - Get the reg property of a device, indexed by name
  *
--
2.20.1

Re: [PATCH] arm: mach-k3: common: Default to non fitImage boot on HS-FS

[Kamlesh Gurudasani]

Vignesh Raghavendra  writes:

> Allow non fitImage bootflow on Field Securable (HS-FS) devices in
> addition to GP, force fitImage boot only on Security enforced (HS-SE)
> devices where signed images are necessary to maintain chain of trust.
>
> Signed-off-by: Vignesh Raghavendra 
Reviewed-by: Kamlesh Gurudasani 

[PATCH v3 04/19] j721e: schema: yaml: Add general schema and J721E board config files

[Neha Malcom Francis]

Schema file in YAML must be provided in board/ti/common for validating
input config files and packaging system firmware. The schema includes
entries for rm-cfg, board-cfg, pm-cfg and sec-cfg.

Board config files must be provided in board/ti/ in YAML.
These can then be consumed for generation of binaries to package system
firmware. Added YAML configs for J721E in particular.

Signed-off-by: Tarun Sahu 
[n-fran...@ti.com: prepared patch for upstreaming]
Signed-off-by: Neha Malcom Francis 
---
 board/ti/common/schema.yaml   |  355 +
 board/ti/j721e/board-cfg.yaml |   37 +
 board/ti/j721e/pm-cfg.yaml|   13 +
 board/ti/j721e/rm-cfg.yaml| 2757 +
 board/ti/j721e/sec-cfg.yaml   |  379 +
 5 files changed, 3541 insertions(+)
 create mode 100644 board/ti/common/schema.yaml
 create mode 100644 board/ti/j721e/board-cfg.yaml
 create mode 100644 board/ti/j721e/pm-cfg.yaml
 create mode 100644 board/ti/j721e/rm-cfg.yaml
 create mode 100644 board/ti/j721e/sec-cfg.yaml

diff --git a/board/ti/common/schema.yaml b/board/ti/common/schema.yaml
new file mode 100644
index 00..070ff797e0
--- /dev/null
+++ b/board/ti/common/schema.yaml
@@ -0,0 +1,355 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Config schema for TI K3 devices
+#
+
+---
+
+definitions:
+u8:
+type: integer
+minimum: 0
+maximum: 0xff
+u16:
+type: integer
+minimum: 0
+maximum: 0x
+u32:
+type: integer
+minimum: 0
+maximum: 0x
+
+
+
+type: object
+properties:
+pm-cfg:
+type: object
+properties:
+rev:
+type: object
+properties:
+boardcfg_abi_maj:
+$ref: "#/definitions/u8"
+boardcfg_abi_min:
+$ref: "#/definitions/u8"
+board-cfg:
+type: object
+properties:
+rev:
+type: object
+properties:
+boardcfg_abi_maj:
+$ref: "#/definitions/u8"
+boardcfg_abi_min:
+$ref: "#/definitions/u8"
+control:
+type: object
+properties:
+subhdr:
+type: object
+properties:
+magic:
+$ref: "#/definitions/u16"
+size:
+$ref: "#/definitions/u16"
+main_isolation_enable:
+$ref: "#/definitions/u8"
+main_isolation_hostid:
+$ref: "#/definitions/u16"
+
+
+secproxy:
+type: object
+properties:
+subhdr:
+type: object
+properties:
+magic:
+$ref: "#/definitions/u16"
+size:
+$ref: "#/definitions/u16"
+scaling_factor:
+$ref: "#/definitions/u8"
+scaling_profile:
+$ref: "#/definitions/u8"
+disable_main_nav_secure_proxy:
+$ref: "#/definitions/u8"
+
+msmc:
+type: object
+properties:
+subhdr:
+type: object
+properties:
+magic:
+$ref: "#/definitions/u16"
+size:
+$ref: "#/definitions/u16"
+msmc_cache_size:
+$ref: "#/definitions/u8"
+debug_cfg:
+type: object
+properties:
+subhdr:
+type: object
+properties:
+magic:
+$ref: "#/definitions/u16"
+size:
+$ref: "#/definitions/u16"
+trace_dst_enables:
+$ref: "#/definitions/u16"
+trace_src_enables:
+$ref: "#/definitions/u16"
+
+sec-cfg:
+type: object
+properties:
+rev:
+type: object
+properties:
+boardcfg_abi_maj:
+$ref: "#/definitions/u8"
+boardcfg_abi_min:
+$ref: "#/definitions/u8"
+
+processor_acl_list:
+type: object
+properties:
+subhdr:
+type: object
+   

Re: [PATCH] doc:fix typo in 'mmc write' example

[Shirokov Alexander]

Hello Simon,

Thanks for your answer.Using 0x explicitly shows that we are working with
HEX.
But without the prefix, it looks like a decimal number. And it's more
confusing
when the number of blocks looks like a decimal but is interpreted as HEX.

Here is an example:

mmc write 0x4000 0x5000 16
MMC write: dev # 1, block # 20480, count 22 ... 22 blocks written: OK

This looks better. If we know that all number is HEX by default
mmc write 4000 5000 16

Do we have to use something like this?

[PATCH v3 18/19] k3: tools: config.mk: Update makefile and remove scripts

[Neha Malcom Francis]

Since binman is used to package bootloader images for all K3 devices, we
do not have to rely on the earlier methods to package them.

config.mk has been edited to only have binman required make commands.

Scripts that were used to generate x509 certificate for tiboot3.bin and
generate tispl.bin have also been removed.

Signed-off-by: Neha Malcom Francis 
---
 arch/arm/mach-k3/config.mk |  92 -
 tools/k3_fit_atf.sh| 123 -
 tools/k3_gen_x509_cert.sh  | 262 -
 3 files changed, 477 deletions(-)
 delete mode 100755 tools/k3_fit_atf.sh
 delete mode 100755 tools/k3_gen_x509_cert.sh

diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk
index b342a56538..39767196a7 100644
--- a/arch/arm/mach-k3/config.mk
+++ b/arch/arm/mach-k3/config.mk
@@ -11,34 +11,6 @@ ifeq ($(shell which openssl),)
 $(error "No openssl in $(PATH), consider installing openssl")
 endif
 
-IMAGE_SIZE= $(shell cat $(obj)/u-boot-spl.bin | wc -c)
-MAX_SIZE= $(shell printf "%d" $(CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE))
-
-ifeq ($(CONFIG_SYS_K3_KEY), "")
-KEY=""
-# On HS use real key or warn if not available
-ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
-ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/keys/custMpk.pem),)
-KEY=$(TI_SECURE_DEV_PKG)/keys/custMpk.pem
-else
-$(warning "WARNING: signing key not found. Random key will NOT work on HS 
hardware!")
-endif
-endif
-else
-KEY=$(patsubst "%",$(srctree)/%,$(CONFIG_SYS_K3_KEY))
-endif
-
-# X509 SWRV default
-SWRV = $(CONFIG_K3_X509_SWRV)
-# On HS use SECDEV provided software revision or warn if not available
-ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
-ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/keys/swrv.txt),)
-SWRV= $(shell cat $(TI_SECURE_DEV_PKG)/keys/swrv.txt)
-else
-$(warning "WARNING: Software revision file not found. Default may not work on 
HS hardware.")
-endif
-endif
-
 O ?= .
 
 # Board config binary artifacts necessary for packaging of tiboot3.bin
@@ -88,68 +60,4 @@ INPUTS-y += schema.yaml
 INPUTS-y   += custMpk.pem
 INPUTS-y   += ti-degenerate-key.pem
 endif
-
-# tiboot3.bin is mandated by ROM and ROM only supports R5 boot.
-# So restrict tiboot3.bin creation for CPU_V7R.
-ifndef CONFIG_BINMAN
-ifdef CONFIG_CPU_V7R
-image_check: $(obj)/u-boot-spl.bin FORCE
-   @if [ $(IMAGE_SIZE) -gt $(MAX_SIZE) ]; then \
-   echo "===" >&2; \
-   echo "ERROR: Final Image too big. " >&2;\
-   echo "$< size = $(IMAGE_SIZE), max size = $(MAX_SIZE)" >&2; \
-   echo "===" >&2; \
-   exit 1; \
-   fi
-
-tiboot3.bin: image_check FORCE
-   $(srctree)/tools/k3_gen_x509_cert.sh -c 16 -b $(obj)/u-boot-spl.bin \
-   -o $@ -l $(CONFIG_SPL_TEXT_BASE) -r $(SWRV) -k 
$(KEY)
-
-INPUTS-y   += tiboot3.bin
-endif
-endif
-
-ifdef CONFIG_ARM64
-
-ifeq ($(CONFIG_SOC_K3_J721E),)
-export DM := /dev/null
 endif
-
-ifndef CONFIG_BINMAN
-ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
-SPL_ITS := u-boot-spl-k3_HS.its
-$(SPL_ITS): export IS_HS=1
-INPUTS-y   += tispl.bin_HS
-else
-SPL_ITS := u-boot-spl-k3.its
-INPUTS-y   += tispl.bin
-endif
-endif
-
-ifeq ($(CONFIG_SPL_OF_LIST),)
-LIST_OF_DTB := $(CONFIG_DEFAULT_DEVICE_TREE)
-else
-LIST_OF_DTB := $(CONFIG_SPL_OF_LIST)
-endif
-
-quiet_cmd_k3_mkits = MKITS   $@
-cmd_k3_mkits = \
-   $(srctree)/tools/k3_fit_atf.sh \
-   $(CONFIG_K3_ATF_LOAD_ADDR) \
-   $(patsubst %,$(obj)/dts/%.dtb,$(subst ",,$(LIST_OF_DTB))) > $@
-
-$(SPL_ITS): FORCE
-   $(call cmd,k3_mkits)
-endif
-
-else
-
-ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
-INPUTS-y   += u-boot.img_HS
-else
-INPUTS-y   += u-boot.img
-endif
-endif
-
-include $(srctree)/arch/arm/mach-k3/config_secure.mk
diff --git a/tools/k3_fit_atf.sh b/tools/k3_fit_atf.sh
deleted file mode 100755
index 7bc07ad074..00
--- a/tools/k3_fit_atf.sh
+++ /dev/null
@@ -1,123 +0,0 @@
-#!/bin/sh
-# SPDX-License-Identifier: GPL-2.0+
-#
-# script to generate FIT image source for K3 Family boards with
-# ATF, OPTEE, SPL and multiple device trees (given on the command line).
-# Inspired from board/sunxi/mksunxi_fit_atf.sh
-#
-# usage: $0   [ [&2
-   ATF=/dev/null
-fi
-
-[ -z "$TEE" ] && TEE="bl32.bin"
-
-if [ ! -f $TEE ]; then
-   echo "WARNING OPTEE file $TEE NOT found, resulting might be 
non-functional" >&2
-   TEE=/dev/null
-fi
-
-[ -z "$DM" ] && DM="dm.bin"
-
-if [ ! -e $DM ]; then
-   echo "WARNING DM file $DM NOT found, resulting might be non-functional" 
>&2
-   DM=/dev/null
-fi
-
-if [ ! -z "$IS_HS" ]; then
-   HS_APPEND=_HS
-fi
-
-cat << __HEADER_EOF
-/dts-v1/;
-
-/ {
-   description = "Configuration to load ATF and SPL";
-   #address-cells = <1>;
-
-   images {
-   atf {
-   description = "ARM Trusted Firmware";
-

[PATCH v3 15/19] am625: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img

[Neha Malcom Francis]

Support added for HS and GP boot binaries for AM62

tiboot3.bin, tispl.bin and u-boot.img: For HS-SE devices
tiboot3.bin_fs, tispl.bin and u-boot.img: For HS-FS devices
tiboot3.bin_unsigned, tispl.bin_unsigned, u-boot.img_unsigned: For GP
devices

It is to be noted that the bootflow followed by AM62 requires:

tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
* TIFS
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg

tispl.bin:
* DM
* ATF
* OPTEE
* A72 SPL
* A72 SPL dtbs

u-boot.img:
* A72 U-Boot
* A72 U-Boot dtbs

Signed-off-by: Neha Malcom Francis 
---
 arch/arm/dts/k3-am625-r5-sk.dts  |   1 +
 arch/arm/dts/k3-am625-sk-binman.dtsi | 529 +++
 arch/arm/dts/k3-am625-sk-u-boot.dtsi |   2 +
 board/ti/am62x/Kconfig   |   2 +
 4 files changed, 534 insertions(+)
 create mode 100644 arch/arm/dts/k3-am625-sk-binman.dtsi

diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts
index dad46704a2..26ccfa0a4b 100644
--- a/arch/arm/dts/k3-am625-r5-sk.dts
+++ b/arch/arm/dts/k3-am625-r5-sk.dts
@@ -9,6 +9,7 @@
 #include "k3-am62-ddr.dtsi"
 
 #include "k3-am625-sk-u-boot.dtsi"
+#include "k3-am625-sk-binman.dtsi"
 
 / {
aliases {
diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi 
b/arch/arm/dts/k3-am625-sk-binman.dtsi
new file mode 100644
index 00..ab172e4ce7
--- /dev/null
+++ b/arch/arm/dts/k3-am625-sk-binman.dtsi
@@ -0,0 +1,529 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+   binman: binman {
+   multiple-images;
+   };
+};
+
+#ifdef CONFIG_TARGET_AM625_R5_EVM
+
+ {
+   board-cfg {
+   filename = "board-cfg.bin";
+   ti-board-config {
+   config = "board-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   pm-cfg {
+   filename = "pm-cfg.bin";
+   ti-board-config {
+   config = "pm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   rm-cfg {
+   filename = "rm-cfg.bin";
+   ti-board-config {
+   config = "rm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   sec-cfg {
+   filename = "sec-cfg.bin";
+   ti-board-config {
+   config = "sec-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   combined-tifs-cfg {
+   filename = "combined-tifs-cfg.bin";
+   ti-board-config {
+   board-cfg {
+   config = "board-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   sec-cfg {
+   config = "sec-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   pm-cfg {
+   config = "pm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   rm-cfg {
+   config = "rm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   };
+   combined-dm-cfg {
+   filename = "combined-dm-cfg.bin";
+   ti-board-config {
+   pm-cfg {
+   config = "pm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   rm-cfg {
+   config = "rm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+
+   };
+   };
+   tiboot3 {
+   filename = "tiboot3.bin";
+   ti-secure-rom {
+   content = <_boot_spl>, <_fs_enc>, 
<_tifs_cfg>,
+   <_dm_cfg>, <_inner_cert>;
+   combined;
+   dm-data;
+   sysfw-inner-cert;
+   keyfile = "custMpk.pem";
+   sw-rev = <1>;
+   content-sbl = <_boot_spl>;
+   content-sysfw = <_fs_enc>;
+   content-sysfw-data = <_tifs_cfg>;
+   content-sysfw-inner-cert = <_inner_cert>;
+   content-dm-data = <_dm_cfg>;
+   load = <0x43c0>;
+   load-sysfw = <0x4>;
+   load-sysfw-data = <0x67000>;
+   load-dm-data = <0x43c3a800>;
+   };
+   u_boot_spl: u-boot-spl {
+   no-expanded;
+   };
+   ti_fs_enc: 

[PATCH v3 19/19] doc: board: ti: Update documentation for binman flow

[Neha Malcom Francis]

Earlier documentation specified builds for generating bootloader images
using an external TI repository k3-image-gen and core-secdev-k3. Modify
this to using the binman flow so that user understands how to build the
final boot images.

Signed-off-by: Neha Malcom Francis 
---
 doc/board/ti/am62x_sk.rst  | 20 
 doc/board/ti/j721e_evm.rst | 37 -
 doc/board/ti/k3.rst| 67 ++
 3 files changed, 36 insertions(+), 88 deletions(-)

diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst
index b1b7d99bef..f5e0774899 100644
--- a/doc/board/ti/am62x_sk.rst
+++ b/doc/board/ti/am62x_sk.rst
@@ -115,23 +115,19 @@ Below is the pictorial representation of boot flow:
 
 Sources:
 
-1. SYSFW:
-   Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git
-   Branch: master
-
-2. ATF:
+1. ATF:
Tree: https://github.com/ARM-software/arm-trusted-firmware.git
Branch: master
 
-3. OPTEE:
+2. OPTEE:
Tree: https://github.com/OP-TEE/optee_os.git
Branch: master
 
-4. U-Boot:
+3. U-Boot:
Tree: https://source.denx.de/u-boot/u-boot
Branch: master
 
-5. TI Linux Firmware:
+4. TI Linux Firmware:
Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git
Branch: ti-linux-firmware
 
@@ -156,18 +152,14 @@ Build procedure:
 .. code-block:: text
 
  $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- 
am62x_evm_r5_defconfig O=/tmp/r5
- $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- O=/tmp/r5
- $ cd 
- $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- SOC=am62x 
SBL=/tmp/r5/spl/u-boot-spl.bin SYSFW_PATH=/ti-sysfw/ti-fs-firmware-am62x-gp.bin
-
-Use the tiboot3.bin generated from last command
+ $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- O=/tmp/r5 
BINMAN_INDIRS=
 
 * 3.2 A53:
 
 .. code-block:: text
 
  $ make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu- am62x_evm_a53_defconfig 
O=/tmp/a53
- $ make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu- ATF=/build/k3/lite/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin DM=/ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f 
O=/tmp/a53
+ $ make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu- BL31=/build/k3/lite/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin 
BINMAN_INDIRS=
 
 Target Images
 --
diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst
index e898601c41..c90e2b8279 100644
--- a/doc/board/ti/j721e_evm.rst
+++ b/doc/board/ti/j721e_evm.rst
@@ -130,67 +130,56 @@ support. Below is the pictorial representation of boot 
flow:
 
 Sources:
 
-1. SYSFW:
-   Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git
-   Branch: master
-
-2. ATF:
+1. ATF:
Tree: https://github.com/ARM-software/arm-trusted-firmware.git
Branch: master
 
-3. OPTEE:
+2. OPTEE:
Tree: https://github.com/OP-TEE/optee_os.git
Branch: master
 
-4. DM Firmware:
-   Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git
-   Branch: ti-linux-firmware
-
-5. U-Boot:
+3. U-Boot:
Tree: https://source.denx.de/u-boot/u-boot
Branch: master
 
+4. TI Linux Firmware:
+   Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git
+   Branch: ti-linux-firmware
+
 Build procedure:
 
-1. SYSFW:
-
-.. code-block:: bash
-
-make CROSS_COMPILE=arm-linux-gnueabihf- SOC=j721e
-
-2. ATF:
+1. ATF:
 
 .. code-block:: bash
 
 make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 
TARGET_BOARD=generic SPD=opteed
 
-3. OPTEE:
+2. OPTEE:
 
 .. code-block:: bash
 
 make PLATFORM=k3-j721e CFG_ARM64_core=y
 
-4. U-Boot:
+3. U-Boot:
 
 * 4.1 R5:
 
 .. code-block:: bash
 
 make CROSS_COMPILE=arm-linux-gnueabihf- j721e_evm_r5_defconfig O=build/r5
-make CROSS_COMPILE=arm-linux-gnueabihf- O=build/r5
+make CROSS_COMPILE=arm-linux-gnueabihf- O=build/r5 
BINMAN_INDIRS=
 
 * 4.2 A72:
 
 .. code-block:: bash
 
 make CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=build/a72
-make CROSS_COMPILE=aarch64-linux-gnu- ATF=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin DM=/ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f O=build/a72
+make CROSS_COMPILE=aarch64-linux-gnu- BL31=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin 
BINMAN_INDIRS=
 
 Target Images
 --
 Copy the below images to an SD card and boot:
- - sysfw.itb from step 1
- - tiboot3.bin from step 4.1
+ - tiboot3.bin and sysfw.itb from step 4.1
  - tispl.bin, u-boot.img from 4.2
 
 Image formats:
diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst
index b49a60caf1..a34468fa2f 100644
--- a/doc/board/ti/k3.rst
+++ b/doc/board/ti/k3.rst
@@ -114,11 +114,6 @@ online
   | **source:** https://source.denx.de/u-boot/u-boot.git
   | **branch:** master
 
-* **K3 Image Gen**
-
-  | **source:** https://git.ti.com/git/k3-image-gen/k3-image-gen.git
-  | 

[PATCH v3 16/19] am62a: yaml: Add board configs for AM62ax

[Neha Malcom Francis]

Added YAML configs for AM62ax

Signed-off-by: Neha Malcom Francis 
---
 board/ti/am62ax/board-cfg.yaml |   36 +
 board/ti/am62ax/pm-cfg.yaml|   12 +
 board/ti/am62ax/rm-cfg.yaml| 1151 
 board/ti/am62ax/sec-cfg.yaml   |  375 +++
 4 files changed, 1574 insertions(+)
 create mode 100644 board/ti/am62ax/board-cfg.yaml
 create mode 100644 board/ti/am62ax/pm-cfg.yaml
 create mode 100644 board/ti/am62ax/rm-cfg.yaml
 create mode 100644 board/ti/am62ax/sec-cfg.yaml

diff --git a/board/ti/am62ax/board-cfg.yaml b/board/ti/am62ax/board-cfg.yaml
new file mode 100644
index 00..6e45b494e0
--- /dev/null
+++ b/board/ti/am62ax/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for AM62ax
+#
+
+---
+
+board-cfg:
+rev:
+boardcfg_abi_maj : 0x0
+boardcfg_abi_min : 0x1
+control:
+subhdr:
+magic: 0xC1D3
+size: 7
+main_isolation_enable : 0x5A
+main_isolation_hostid : 0x2
+secproxy:
+subhdr:
+magic: 0x1207
+size: 7
+scaling_factor : 0x1
+scaling_profile : 0x1
+disable_main_nav_secure_proxy : 0
+msmc:
+subhdr:
+magic: 0xA5C3
+size: 5
+msmc_cache_size : 0x10
+debug_cfg:
+subhdr:
+magic: 0x020C
+size: 8
+trace_dst_enables : 0x00
+trace_src_enables : 0x00
diff --git a/board/ti/am62ax/pm-cfg.yaml b/board/ti/am62ax/pm-cfg.yaml
new file mode 100644
index 00..a491f11260
--- /dev/null
+++ b/board/ti/am62ax/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for AM62ax
+#
+
+---
+
+pm-cfg:
+rev:
+boardcfg_abi_maj : 0x0
+boardcfg_abi_min : 0x1
diff --git a/board/ti/am62ax/rm-cfg.yaml b/board/ti/am62ax/rm-cfg.yaml
new file mode 100644
index 00..f7315dd2b0
--- /dev/null
+++ b/board/ti/am62ax/rm-cfg.yaml
@@ -0,0 +1,1151 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM62ax
+#
+
+---
+
+rm-cfg:
+rm_boardcfg:
+rev:
+boardcfg_abi_maj : 0x0
+boardcfg_abi_min : 0x1
+host_cfg:
+subhdr:
+magic: 0x4C41
+size : 356
+host_cfg_entries:
+- #1
+host_id: 12
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #2
+host_id: 30
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #3
+host_id: 36
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #4
+host_id: 0
+allowed_atype : 0
+allowed_qos : 0
+allowed_orderid : 0
+allowed_priority : 0
+allowed_sched_priority : 0
+- #5
+host_id: 0
+allowed_atype : 0
+allowed_qos : 0
+allowed_orderid : 0
+allowed_priority : 0
+allowed_sched_priority : 0
+- #6
+host_id: 0
+allowed_atype : 0
+allowed_qos : 0
+allowed_orderid : 0
+allowed_priority : 0
+allowed_sched_priority : 0
+- #7
+host_id: 0
+allowed_atype : 0
+allowed_qos : 0
+allowed_orderid : 0
+allowed_priority : 0
+allowed_sched_priority : 0
+- #8
+host_id: 0
+allowed_atype : 0
+allowed_qos : 0
+allowed_orderid : 0
+allowed_priority : 0
+allowed_sched_priority : 0
+- #9
+host_id: 0
+allowed_atype : 0
+allowed_qos : 0
+allowed_orderid : 0
+allowed_priority : 0
+

[PATCH v3 17/19] am62a: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img

[Neha Malcom Francis]

Support added for HS and GP boot binaries for AM62ax.

tiboot3.bin, tispl.bin and u-boot.img: For HS-SE devices
tiboot3.bin_fs, tispl.bin and u-boot.img: For HS-FS devices
tiboot3.bin_unsigned, tispl.bin_unsigned and u-boot.img_unsigned: For GP
devices

It is to be noted that the bootflow followed by AM62ax requires:

tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
* TIFS
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg

tispl.bin:
* DM
* ATF
* OPTEE
* A72 SPL
* A72 SPL dtbs

u-boot.img:
* A72 U-Boot
* A72 U-Boot dtbs

Signed-off-by: Neha Malcom Francis 
---
 arch/arm/dts/k3-am62a-sk-binman.dtsi | 528 +++
 arch/arm/dts/k3-am62a7-r5-sk.dts |   1 +
 arch/arm/dts/k3-am62a7-sk.dts|   1 +
 board/ti/am62ax/Kconfig  |   2 +
 4 files changed, 532 insertions(+)
 create mode 100644 arch/arm/dts/k3-am62a-sk-binman.dtsi

diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi 
b/arch/arm/dts/k3-am62a-sk-binman.dtsi
new file mode 100644
index 00..63aec72b03
--- /dev/null
+++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi
@@ -0,0 +1,528 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+   binman: binman {
+   multiple-images;
+   };
+};
+
+#ifdef CONFIG_TARGET_AM62A7_R5_EVM
+
+ {
+   board-cfg {
+   filename = "board-cfg.bin";
+   ti-board-config {
+   config = "board-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   pm-cfg {
+   filename = "pm-cfg.bin";
+   ti-board-config {
+   config = "pm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   rm-cfg {
+   filename = "rm-cfg.bin";
+   ti-board-config {
+   config = "rm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   sec-cfg {
+   filename = "sec-cfg.bin";
+   ti-board-config {
+   config = "sec-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   combined-tifs-cfg {
+   filename = "combined-tifs-cfg.bin";
+   ti-board-config {
+   board-cfg {
+   config = "board-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   sec-cfg {
+   config = "sec-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   pm-cfg {
+   config = "pm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   rm-cfg {
+   config = "rm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   };
+   combined-dm-cfg {
+   filename = "combined-dm-cfg.bin";
+   ti-board-config {
+   pm-cfg {
+   config = "pm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   rm-cfg {
+   config = "rm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+
+   };
+   };
+
+   tiboot3 {
+   filename = "tiboot3.bin";
+   ti-secure-rom {
+   content = <_boot_spl>, <_fs_enc>, 
<_tifs_cfg>,
+   <_dm_cfg>, <_inner_cert>;
+   combined;
+   dm-data;
+   sysfw-inner-cert;
+   keyfile = "custMpk.pem";
+   sw-rev = <1>;
+   content-sbl = <_boot_spl>;
+   content-sysfw = <_fs_enc>;
+   content-sysfw-data = <_tifs_cfg>;
+   content-sysfw-inner-cert = <_inner_cert>;
+   content-dm-data = <_dm_cfg>;
+   load = <0x43c0>;
+   load-sysfw = <0x4>;
+   load-sysfw-data = <0x67000>;
+   load-dm-data = <0x43c3a800>;
+   };
+   u_boot_spl: u-boot-spl {
+   no-expanded;
+   };
+   ti_fs_enc: ti-fs-enc.bin {
+   filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-enc.bin";
+   type = "blob-ext";
+   optional;
+   };
+   combined_tifs_cfg: combined-tifs-cfg.bin {
+   filename = "combined-tifs-cfg.bin";
+   

[PATCH v3 14/19] am62: yaml: Add board configs for AM62

[Neha Malcom Francis]

Added YAML configs for AM62

Signed-off-by: Neha Malcom Francis 
---
 board/ti/am62x/board-cfg.yaml |   36 ++
 board/ti/am62x/pm-cfg.yaml|   12 +
 board/ti/am62x/rm-cfg.yaml| 1088 +
 board/ti/am62x/sec-cfg.yaml   |  375 
 board/ti/am65x/rm-cfg.yaml|  144 ++---
 5 files changed, 1583 insertions(+), 72 deletions(-)
 create mode 100644 board/ti/am62x/board-cfg.yaml
 create mode 100644 board/ti/am62x/pm-cfg.yaml
 create mode 100644 board/ti/am62x/rm-cfg.yaml
 create mode 100644 board/ti/am62x/sec-cfg.yaml

diff --git a/board/ti/am62x/board-cfg.yaml b/board/ti/am62x/board-cfg.yaml
new file mode 100644
index 00..a26ef55bd4
--- /dev/null
+++ b/board/ti/am62x/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for AM62
+#
+
+---
+
+board-cfg:
+rev:
+boardcfg_abi_maj : 0x0
+boardcfg_abi_min : 0x1
+control:
+subhdr:
+magic: 0xC1D3
+size: 7
+main_isolation_enable : 0x5A
+main_isolation_hostid : 0x2
+secproxy:
+subhdr:
+magic: 0x1207
+size: 7
+scaling_factor : 0x1
+scaling_profile : 0x1
+disable_main_nav_secure_proxy : 0
+msmc:
+subhdr:
+magic: 0xA5C3
+size: 5
+msmc_cache_size : 0x0
+debug_cfg:
+subhdr:
+magic: 0x020C
+size: 8
+trace_dst_enables : 0x00
+trace_src_enables : 0x00
diff --git a/board/ti/am62x/pm-cfg.yaml b/board/ti/am62x/pm-cfg.yaml
new file mode 100644
index 00..aa94097e97
--- /dev/null
+++ b/board/ti/am62x/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for AM62
+#
+
+---
+
+pm-cfg:
+rev:
+boardcfg_abi_maj : 0x0
+boardcfg_abi_min : 0x1
diff --git a/board/ti/am62x/rm-cfg.yaml b/board/ti/am62x/rm-cfg.yaml
new file mode 100644
index 00..ba82146551
--- /dev/null
+++ b/board/ti/am62x/rm-cfg.yaml
@@ -0,0 +1,1088 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM62
+#
+
+---
+
+rm-cfg:
+rm_boardcfg:
+rev:
+boardcfg_abi_maj : 0x0
+boardcfg_abi_min : 0x1
+host_cfg:
+subhdr:
+magic: 0x4C41
+size : 356
+host_cfg_entries:
+- #1
+host_id: 12
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #2
+host_id: 30
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #3
+host_id: 36
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #4
+host_id: 0
+allowed_atype : 0
+allowed_qos : 0
+allowed_orderid : 0
+allowed_priority : 0
+allowed_sched_priority : 0
+- #5
+host_id: 0
+allowed_atype : 0
+allowed_qos : 0
+allowed_orderid : 0
+allowed_priority : 0
+allowed_sched_priority : 0
+- #6
+host_id: 0
+allowed_atype : 0
+allowed_qos : 0
+allowed_orderid : 0
+allowed_priority : 0
+allowed_sched_priority : 0
+- #7
+host_id: 0
+allowed_atype : 0
+allowed_qos : 0
+allowed_orderid : 0
+allowed_priority : 0
+allowed_sched_priority : 0
+- #8
+host_id: 0
+allowed_atype : 0
+allowed_qos : 0
+allowed_orderid : 0
+allowed_priority : 0
+allowed_sched_priority : 0
+- #9
+host_id: 0
+allowed_atype : 0
+allowed_qos : 0
+allowed_orderid : 0
+

[PATCH v3 12/19] j721s2: yaml: Add board configs for J721S2

[Neha Malcom Francis]

Added YAML configs for J721S2

Signed-off-by: Neha Malcom Francis 
---
 board/ti/j721s2/board-cfg.yaml |   37 +
 board/ti/j721s2/pm-cfg.yaml|   12 +
 board/ti/j721s2/rm-cfg.yaml| 2901 
 board/ti/j721s2/sec-cfg.yaml   |  375 +
 4 files changed, 3325 insertions(+)
 create mode 100644 board/ti/j721s2/board-cfg.yaml
 create mode 100644 board/ti/j721s2/pm-cfg.yaml
 create mode 100644 board/ti/j721s2/rm-cfg.yaml
 create mode 100644 board/ti/j721s2/sec-cfg.yaml

diff --git a/board/ti/j721s2/board-cfg.yaml b/board/ti/j721s2/board-cfg.yaml
new file mode 100644
index 00..d80f308ca6
--- /dev/null
+++ b/board/ti/j721s2/board-cfg.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for J721S2
+#
+
+---
+
+board-cfg:
+rev:
+boardcfg_abi_maj : 0x0
+boardcfg_abi_min : 0x1
+control:
+subhdr:
+magic: 0xC1D3
+size: 7
+main_isolation_enable : 0x5A
+main_isolation_hostid : 0x2
+secproxy:
+subhdr:
+magic: 0x1207
+size: 7
+scaling_factor : 0x1
+scaling_profile : 0x1
+disable_main_nav_secure_proxy : 0
+msmc:
+subhdr:
+magic: 0xA5C3
+size: 5
+msmc_cache_size : 0x0
+debug_cfg:
+subhdr:
+magic: 0x020C
+size: 8
+trace_dst_enables : 0x00
+trace_src_enables : 0x00
+
diff --git a/board/ti/j721s2/pm-cfg.yaml b/board/ti/j721s2/pm-cfg.yaml
new file mode 100644
index 00..45994e23cc
--- /dev/null
+++ b/board/ti/j721s2/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for J721S2
+#
+
+---
+
+pm-cfg:
+rev:
+boardcfg_abi_maj : 0x0
+boardcfg_abi_min : 0x1
diff --git a/board/ti/j721s2/rm-cfg.yaml b/board/ti/j721s2/rm-cfg.yaml
new file mode 100644
index 00..d18288ae08
--- /dev/null
+++ b/board/ti/j721s2/rm-cfg.yaml
@@ -0,0 +1,2901 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for J721S2
+#
+
+---
+
+rm-cfg:
+rm_boardcfg:
+rev:
+boardcfg_abi_maj : 0x0
+boardcfg_abi_min : 0x1
+host_cfg:
+subhdr:
+magic: 0x4C41
+size : 356
+host_cfg_entries:
+- #1
+host_id: 3
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #2
+host_id: 5
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #3
+host_id: 12
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #4
+host_id: 13
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #5
+host_id: 21
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #6
+host_id: 23
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #7
+host_id: 35
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #8
+host_id: 37
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #9
+host_id: 40
+allowed_atype : 0x2A
+  

[PATCH v3 13/19] j721s2: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img

[Neha Malcom Francis]

Support added for HS and GP boot binaries for J721S2.

tiboot3.bin, tispl.bin and u-boot.img: For HS-SE devices
tiboot3.bin_fs, tispl.bin and u-boot.img: For HS-FS devices
tiboot3.bin_unsigned, tispl.bin_unsigned, u-boot.img_unsigned: For GP
devices

It is to be noted that the bootflow followed by J721S2 requires:

tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
* TIFS
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg

tispl.bin:
* DM
* ATF
* OPTEE
* A72 SPL
* A72 SPL dtbs

u-boot.img:
* A72 U-Boot
* A72 U-Boot dtbs

Signed-off-by: Neha Malcom Francis 
---
 arch/arm/dts/k3-j721s2-binman.dtsi| 613 ++
 .../k3-j721s2-common-proc-board-u-boot.dtsi   |   2 +
 .../dts/k3-j721s2-r5-common-proc-board.dts|   1 +
 board/ti/j721s2/Kconfig   |   2 +
 4 files changed, 618 insertions(+)
 create mode 100644 arch/arm/dts/k3-j721s2-binman.dtsi

diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi 
b/arch/arm/dts/k3-j721s2-binman.dtsi
new file mode 100644
index 00..e2e3742fe3
--- /dev/null
+++ b/arch/arm/dts/k3-j721s2-binman.dtsi
@@ -0,0 +1,613 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+   binman: binman {
+   multiple-images;
+   };
+};
+
+#ifdef CONFIG_TARGET_J721S2_R5_EVM
+
+ {
+   board-cfg {
+   filename = "board-cfg.bin";
+   ti-board-config {
+   config = "board-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   pm-cfg {
+   filename = "pm-cfg.bin";
+   ti-board-config {
+   config = "pm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   rm-cfg {
+   filename = "rm-cfg.bin";
+   ti-board-config {
+   config = "rm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   sec-cfg {
+   filename = "sec-cfg.bin";
+   ti-board-config {
+   config = "sec-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   combined-tifs-cfg {
+   filename = "combined-tifs-cfg.bin";
+   ti-board-config {
+   board-cfg {
+   config = "board-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   sec-cfg {
+   config = "sec-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   pm-cfg {
+   config = "pm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   rm-cfg {
+   config = "rm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   };
+   combined-dm-cfg {
+   filename = "combined-dm-cfg.bin";
+   ti-board-config {
+   pm-cfg {
+   config = "pm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   rm-cfg {
+   config = "rm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+
+   };
+   };
+
+   tiboot3 {
+   filename = "tiboot3.bin";
+   ti-secure-rom {
+   content = <_boot_spl>, <_fs_enc>, 
<_tifs_cfg>,
+   <_dm_cfg>, <_inner_cert>;
+   combined;
+   dm-data;
+   sysfw-inner-cert;
+   keyfile = "custMpk.pem";
+   sw-rev = <1>;
+   content-sbl = <_boot_spl>;
+   content-sysfw = <_fs_enc>;
+   content-sysfw-data = <_tifs_cfg>;
+   content-sysfw-inner-cert = <_inner_cert>;
+   content-dm-data = <_dm_cfg>;
+   load = <0x41c0>;
+   load-sysfw = <0x4>;
+   load-sysfw-data = <0x67000>;
+   load-dm-data = <0x41c8>;
+   };
+   u_boot_spl: u-boot-spl {
+   no-expanded;
+   };
+   ti_fs_enc: ti-fs-enc.bin {
+   filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-enc.bin";
+   type = "blob-ext";
+   optional;
+   };
+   combined_tifs_cfg: combined-tifs-cfg.bin {
+   filename = "combined-tifs-cfg.bin";

[PATCH v3 11/19] am64x: dts: binman: Package tiboot3.bin, tispl.bin u-boot.img

[Neha Malcom Francis]

Support added for HS and GP boot binaries for AM64x.

tiboot3.bin, tispl.bin and u-boot.img: For HS-SE devices
tiboot3.bin_fs, tispl.bin and u-boot.img: For HS-FS devices
tiboot3.bin_unsigned, tispl.bin_unsigned, u-boot.img_unsigned: For GP
devices

Note that the bootflow followed by AM64x requires:

tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
* sysfw
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg

tispl.bin:
* ATF
* OPTEE
* A53 SPL
* A53 SPL dtbs

u-boot.img:
* A53 U-Boot
* A53 U-Boot dtbs

Signed-off-by: Neha Malcom Francis 
---
 arch/arm/dts/k3-am642-evm-u-boot.dtsi |   2 +
 arch/arm/dts/k3-am642-r5-evm.dts  |   1 +
 arch/arm/dts/k3-am64x-binman.dtsi | 569 ++
 board/ti/am64x/Kconfig|   2 +
 4 files changed, 574 insertions(+)
 create mode 100644 arch/arm/dts/k3-am64x-binman.dtsi

diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi 
b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
index 64857b0909..73577e8cfd 100644
--- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
@@ -3,6 +3,8 @@
  * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#include "k3-am64x-binman.dtsi"
+
 / {
chosen {
stdout-path = "serial2:115200n8";
diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts
index ca5ce4a35a..d6b1ec6e58 100644
--- a/arch/arm/dts/k3-am642-r5-evm.dts
+++ b/arch/arm/dts/k3-am642-r5-evm.dts
@@ -8,6 +8,7 @@
 #include "k3-am642.dtsi"
 #include "k3-am64-evm-ddr4-1600MTs.dtsi"
 #include "k3-am64-ddr.dtsi"
+#include "k3-am64x-binman.dtsi"
 
 / {
chosen {
diff --git a/arch/arm/dts/k3-am64x-binman.dtsi 
b/arch/arm/dts/k3-am64x-binman.dtsi
new file mode 100644
index 00..72ffc798b7
--- /dev/null
+++ b/arch/arm/dts/k3-am64x-binman.dtsi
@@ -0,0 +1,569 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+
+#include 
+
+/ {
+   binman: binman {
+   multiple-images;
+   };
+};
+
+#ifdef CONFIG_TARGET_AM642_R5_EVM
+
+ {
+   board-cfg {
+   filename = "board-cfg.bin";
+   ti-board-config {
+   config = "board-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   pm-cfg {
+   filename = "pm-cfg.bin";
+   ti-board-config {
+   config = "pm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   rm-cfg {
+   filename = "rm-cfg.bin";
+   ti-board-config {
+   config = "rm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   sec-cfg {
+   filename = "sec-cfg.bin";
+   ti-board-config {
+   config = "sec-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   combined-sysfw-cfg {
+   filename = "combined-sysfw-cfg.bin";
+   ti-board-config {
+   board-cfg {
+   config = "board-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   sec-cfg {
+   config = "sec-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   pm-cfg {
+   config = "pm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   rm-cfg {
+   config = "rm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   };
+   tiboot3 {
+   filename = "tiboot3.bin";
+   ti-secure-rom {
+   content = <_boot_spl>, <_sci_enc>,
+   <_sysfw_cfg>, <_inner_cert>;
+   combined;
+   sysfw-inner-cert;
+   keyfile = "custMpk.pem";
+   sw-rev = <1>;
+   content-sbl = <_boot_spl>;
+   content-sysfw = <_sci_enc>;
+   content-sysfw-data = <_sysfw_cfg>;
+   content-sysfw-inner-cert = <_inner_cert>;
+   load = <0x7000>;
+   load-sysfw = <0x44000>;
+   load-sysfw-data = <0x7b000>;
+   };
+   u_boot_spl: u-boot-spl {
+   no-expanded;
+   };
+   ti_sci_enc: ti-fs-enc.bin {
+   filename = 
"ti-sysfw/ti-sci-firmware-am64x_sr2-hs-enc.bin";
+   type = "blob-ext";
+   optional;
+   };
+

[PATCH v3 10/19] am64x: yaml: Add board configs for AM64x

[Neha Malcom Francis]

Added YAML configs for AM64xx

Signed-off-by: Neha Malcom Francis 
---
 board/ti/am64x/board-cfg.yaml |   37 +
 board/ti/am64x/pm-cfg.yaml|   12 +
 board/ti/am64x/rm-cfg.yaml| 1400 +
 board/ti/am64x/sec-cfg.yaml   |  378 +
 4 files changed, 1827 insertions(+)
 create mode 100644 board/ti/am64x/board-cfg.yaml
 create mode 100644 board/ti/am64x/pm-cfg.yaml
 create mode 100644 board/ti/am64x/rm-cfg.yaml
 create mode 100644 board/ti/am64x/sec-cfg.yaml

diff --git a/board/ti/am64x/board-cfg.yaml b/board/ti/am64x/board-cfg.yaml
new file mode 100644
index 00..f1f7c68d50
--- /dev/null
+++ b/board/ti/am64x/board-cfg.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for AM64x
+#
+
+---
+
+board-cfg:
+rev:
+boardcfg_abi_maj : 0x0
+boardcfg_abi_min : 0x1
+control:
+subhdr:
+magic: 0xC1D3
+size: 7
+main_isolation_enable : 0x5A
+main_isolation_hostid : 0x2
+secproxy:
+subhdr:
+magic: 0x1207
+size: 7
+scaling_factor : 0x1
+scaling_profile : 0x1
+disable_main_nav_secure_proxy : 0
+msmc:
+subhdr:
+magic: 0xA5C3
+size: 5
+msmc_cache_size : 0x0
+debug_cfg:
+subhdr:
+magic: 0x020C
+size: 8
+trace_dst_enables : 0x00
+trace_src_enables : 0x00
+
diff --git a/board/ti/am64x/pm-cfg.yaml b/board/ti/am64x/pm-cfg.yaml
new file mode 100644
index 00..c97495f482
--- /dev/null
+++ b/board/ti/am64x/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for AM64x
+#
+
+---
+
+pm-cfg:
+rev:
+boardcfg_abi_maj : 0x0
+boardcfg_abi_min : 0x1
diff --git a/board/ti/am64x/rm-cfg.yaml b/board/ti/am64x/rm-cfg.yaml
new file mode 100644
index 00..6488c8a9c5
--- /dev/null
+++ b/board/ti/am64x/rm-cfg.yaml
@@ -0,0 +1,1400 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM64x
+#
+
+---
+
+rm-cfg:
+rm_boardcfg:
+rev:
+boardcfg_abi_maj : 0x0
+boardcfg_abi_min : 0x1
+host_cfg:
+subhdr:
+magic: 0x4C41
+size : 356
+host_cfg_entries:
+- #1
+host_id: 12
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #2
+host_id: 30
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #3
+host_id: 36
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #4
+host_id: 38
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #5
+host_id: 41
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+

[PATCH v3 08/19] am65x: yaml: Add AM65x board config files

[Neha Malcom Francis]

Added YAML configs for AM65x

Signed-off-by: Neha Malcom Francis 
---
 board/ti/am65x/board-cfg.yaml |   36 +
 board/ti/am65x/pm-cfg.yaml|   12 +
 board/ti/am65x/rm-cfg.yaml| 2068 +
 board/ti/am65x/sec-cfg.yaml   |  375 ++
 4 files changed, 2491 insertions(+)
 create mode 100644 board/ti/am65x/board-cfg.yaml
 create mode 100644 board/ti/am65x/pm-cfg.yaml
 create mode 100644 board/ti/am65x/rm-cfg.yaml
 create mode 100644 board/ti/am65x/sec-cfg.yaml

diff --git a/board/ti/am65x/board-cfg.yaml b/board/ti/am65x/board-cfg.yaml
new file mode 100644
index 00..133720ec3e
--- /dev/null
+++ b/board/ti/am65x/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for AM65x
+#
+
+---
+
+board-cfg:
+rev:
+boardcfg_abi_maj : 0x0
+boardcfg_abi_min : 0x1
+control:
+subhdr:
+magic: 0xC1D3
+size: 7
+main_isolation_enable : 0x5A
+main_isolation_hostid : 0x2
+secproxy:
+subhdr:
+magic: 0x1207
+size: 7
+scaling_factor : 0x1
+scaling_profile : 0x1
+disable_main_nav_secure_proxy : 0
+msmc:
+subhdr:
+magic: 0xA5C3
+size: 5
+msmc_cache_size : 0x10
+debug_cfg:
+subhdr:
+magic: 0x020C
+size: 8
+trace_dst_enables : 0x00
+trace_src_enables : 0x00
diff --git a/board/ti/am65x/pm-cfg.yaml b/board/ti/am65x/pm-cfg.yaml
new file mode 100644
index 00..4b1ce475cd
--- /dev/null
+++ b/board/ti/am65x/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for AM65x
+#
+
+---
+
+pm-cfg:
+rev:
+boardcfg_abi_maj : 0x0
+boardcfg_abi_min : 0x1
diff --git a/board/ti/am65x/rm-cfg.yaml b/board/ti/am65x/rm-cfg.yaml
new file mode 100644
index 00..501cc464c4
--- /dev/null
+++ b/board/ti/am65x/rm-cfg.yaml
@@ -0,0 +1,2068 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM65x
+#
+
+---
+
+rm-cfg:
+rm_boardcfg:
+rev:
+boardcfg_abi_maj : 0x0
+boardcfg_abi_min : 0x1
+host_cfg:
+subhdr:
+magic: 0x4C41
+size : 356
+host_cfg_entries:
+- #1
+host_id: 3
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #2
+host_id: 5
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #3
+host_id: 12
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #4
+host_id: 13
+allowed_atype : 0x2A
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #5
+host_id: 0
+allowed_atype : 0
+allowed_qos : 0
+allowed_orderid : 0
+allowed_priority : 0
+allowed_sched_priority : 0
+- #6
+host_id: 0
+allowed_atype : 0
+allowed_qos : 0
+allowed_orderid : 0
+allowed_priority : 0
+allowed_sched_priority : 0
+- #7
+host_id: 0
+allowed_atype : 0
+allowed_qos : 0
+allowed_orderid : 0
+allowed_priority : 0
+allowed_sched_priority : 0
+- #8
+host_id: 0
+allowed_atype : 0
+allowed_qos : 0
+allowed_orderid : 0
+allowed_priority : 0
+allowed_sched_priority : 0
+- #9
+host_id: 0
+allowed_atype : 0
+allowed_qos : 0
+allowed_orderid : 0
+allowed_priority : 0
+

[PATCH v3 09/19] am65: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.img

[Neha Malcom Francis]

Support added for HS and GP boot binaries for AM65x.

tiboot3.bin, sysfw.itb, tispl.bin and u-boot.img: For HS devices
tiboot3.bin_unsigned, sysfw.itb, tispl.bin_unsigned,
u-boot.img_unsigned: For GP devices

Note that the bootflow followed by AM65x requires:

tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
sysfw.itb:
* sysfw
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg

tispl.bin:
* ATF
* OPTEE
* A53 SPL
* A53 SPL dtbs

u-boot.img:
* A53 U-Boot
* A53 U-Boot dtbs

Signed-off-by: Neha Malcom Francis 
---
 arch/arm/dts/k3-am654-base-board-u-boot.dtsi  |   1 +
 .../dts/k3-am654-r5-base-board-u-boot.dtsi|   1 +
 arch/arm/dts/k3-am65x-binman.dtsi | 551 ++
 board/ti/am65x/Kconfig|   2 +
 4 files changed, 555 insertions(+)
 create mode 100644 arch/arm/dts/k3-am65x-binman.dtsi

diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi 
b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index 0c1305df7e..e4cbc47c2a 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include "k3-am654-r5-base-board-u-boot.dtsi"
+#include "k3-am65x-binman.dtsi"
 
 _0 {
remoteproc-name = "pru0_0";
diff --git a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi 
b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
index 4516ab1437..949320c91d 100644
--- a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
@@ -5,6 +5,7 @@
 
 #include 
 #include 
+#include "k3-am65x-binman.dtsi"
 
 / {
chosen {
diff --git a/arch/arm/dts/k3-am65x-binman.dtsi 
b/arch/arm/dts/k3-am65x-binman.dtsi
new file mode 100644
index 00..5103997505
--- /dev/null
+++ b/arch/arm/dts/k3-am65x-binman.dtsi
@@ -0,0 +1,551 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+   binman: binman {
+   multiple-images;
+   };
+};
+
+#ifdef CONFIG_TARGET_AM654_R5_EVM
+
+ {
+   board-cfg {
+   filename = "board-cfg.bin";
+   ti-board-config {
+   config = "board-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   pm-cfg {
+   filename = "pm-cfg.bin";
+   ti-board-config {
+   config = "pm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   rm-cfg {
+   filename = "rm-cfg.bin";
+   ti-board-config {
+   config = "rm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   sec-cfg {
+   filename = "sec-cfg.bin";
+   ti-board-config {
+   config = "sec-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+
+   tiboot3 {
+   filename = "tiboot3.bin";
+   ti-secure-rom {
+   content = <_boot_spl>;
+   core = "public";
+   load = ;
+   keyfile = "custMpk.pem";
+   };
+   u_boot_spl: u-boot-spl {
+   no-expanded;
+   };
+   };
+   sysfw {
+   filename = "sysfw.bin";
+   ti-secure-rom {
+   content = <_sci_cert>;
+   core = "secure";
+   load = <0x4>;
+   keyfile = "custMpk.pem";
+   countersign;
+   };
+   ti_sci_cert: ti-sci-cert.bin {
+   filename = "ti-sysfw/ti-sci-firmware-am65x-hs-cert.bin";
+   type = "blob-ext";
+   optional;
+   };
+   ti-sci-firmware-am65x-hs-enc.bin {
+   filename = "ti-sysfw/ti-sci-firmware-am65x-hs-enc.bin";
+   type = "blob-ext";
+   optional;
+   };
+   };
+   itb {
+   filename = "sysfw-am65x-hs.itb";
+   fit {
+   description = "SYSFW and Config fragments";
+   #address-cells = <1>;
+   images {
+   sysfw.bin {
+   description = "sysfw";
+   type = "firmware";
+   arch = "arm";
+   compression = "none";
+   blob-ext {
+   filename = "sysfw.bin";
+   };
+   };
+   board-cfg.bin {
+   description = 

[PATCH v3 06/19] j7200: yaml: Add J7200 board config files

[Neha Malcom Francis]

Added YAML configs for J7200

Signed-off-by: Neha Malcom Francis 
---
 board/ti/j721e/board-cfg_j7200.yaml |   36 +
 board/ti/j721e/pm-cfg_j7200.yaml|   12 +
 board/ti/j721e/rm-cfg_j7200.yaml| 2065 +++
 board/ti/j721e/sec-cfg_j7200.yaml   |  378 +
 4 files changed, 2491 insertions(+)
 create mode 100644 board/ti/j721e/board-cfg_j7200.yaml
 create mode 100644 board/ti/j721e/pm-cfg_j7200.yaml
 create mode 100644 board/ti/j721e/rm-cfg_j7200.yaml
 create mode 100644 board/ti/j721e/sec-cfg_j7200.yaml

diff --git a/board/ti/j721e/board-cfg_j7200.yaml 
b/board/ti/j721e/board-cfg_j7200.yaml
new file mode 100644
index 00..1453317ecb
--- /dev/null
+++ b/board/ti/j721e/board-cfg_j7200.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for J7200
+#
+
+---
+
+board-cfg:
+rev:
+boardcfg_abi_maj : 0x0
+boardcfg_abi_min : 0x1
+control:
+subhdr:
+magic: 0xC1D3
+size: 7
+main_isolation_enable : 0x5A
+main_isolation_hostid : 0x2
+secproxy:
+subhdr:
+magic: 0x1207
+size: 7
+scaling_factor : 0x1
+scaling_profile : 0x1
+disable_main_nav_secure_proxy : 0
+msmc:
+subhdr:
+magic: 0xA5C3
+size: 5
+msmc_cache_size : 0x10
+debug_cfg:
+subhdr:
+magic: 0x020C
+size: 8
+trace_dst_enables : 0x00
+trace_src_enables : 0x00
diff --git a/board/ti/j721e/pm-cfg_j7200.yaml b/board/ti/j721e/pm-cfg_j7200.yaml
new file mode 100644
index 00..588a1d530d
--- /dev/null
+++ b/board/ti/j721e/pm-cfg_j7200.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for J7200
+#
+
+---
+
+pm-cfg:
+rev:
+boardcfg_abi_maj : 0x0
+boardcfg_abi_min : 0x1
diff --git a/board/ti/j721e/rm-cfg_j7200.yaml b/board/ti/j721e/rm-cfg_j7200.yaml
new file mode 100644
index 00..66b589f370
--- /dev/null
+++ b/board/ti/j721e/rm-cfg_j7200.yaml
@@ -0,0 +1,2065 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for J7200
+#
+
+---
+
+rm-cfg:
+rm_boardcfg:
+rev:
+boardcfg_abi_maj : 0x0
+boardcfg_abi_min : 0x1
+host_cfg:
+subhdr:
+magic: 0x4C41
+size : 356
+host_cfg_entries:
+- #1
+host_id: 3
+allowed_atype : 0b101010
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #2
+host_id: 5
+allowed_atype : 0b101010
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #3
+host_id: 12
+allowed_atype : 0b101010
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #4
+host_id: 13
+allowed_atype : 0b101010
+allowed_qos : 0x
+allowed_orderid : 0x
+allowed_priority : 0x
+allowed_sched_priority : 0xAA
+- #5
+host_id: 35
+allowed_atype : 0b101010
+allowed_qos : 0x
+allowed_orderid : 

[PATCH v3 07/19] j7200: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img

[Neha Malcom Francis]

Support added for HS and GP boot binaries for J7200.

tiboot3.bin, tispl.bin and u-boot.img: For HS-SE devices
tiboot3.bin_fs, tispl.bin and u-boot.img: For HS-FS devices
tiboot3.bin_unsigned, tispl.bin_unsigned and u-boot.img_unsigned: For GP
devices

It is to be noted that the bootflow followed by J7200 requires:

tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
* TIFS
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg

tispl.bin:
* DM
* ATF
* OPTEE
* A72 SPL
* A72 SPL dtbs

u-boot.img:
* A72 U-Boot
* A72 U-Boot dtbs

Signed-off-by: Neha Malcom Francis 
---
 arch/arm/dts/k3-j7200-binman.dtsi | 529 ++
 .../k3-j7200-common-proc-board-u-boot.dtsi|   2 +
 board/ti/j721e/Kconfig|   2 +
 3 files changed, 533 insertions(+)
 create mode 100644 arch/arm/dts/k3-j7200-binman.dtsi

diff --git a/arch/arm/dts/k3-j7200-binman.dtsi 
b/arch/arm/dts/k3-j7200-binman.dtsi
new file mode 100644
index 00..59bd446355
--- /dev/null
+++ b/arch/arm/dts/k3-j7200-binman.dtsi
@@ -0,0 +1,529 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+   binman: binman {
+   multiple-images;
+   };
+};
+
+#ifdef CONFIG_TARGET_J7200_R5_EVM
+
+ {
+   board-cfg {
+   filename = "board-cfg.bin";
+   ti-board-config {
+   config = "board-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   pm-cfg {
+   filename = "pm-cfg.bin";
+   ti-board-config {
+   config = "pm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   rm-cfg {
+   filename = "rm-cfg.bin";
+   ti-board-config {
+   config = "rm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   sec-cfg {
+   filename = "sec-cfg.bin";
+   ti-board-config {
+   config = "sec-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+
+   combined-tifs-cfg {
+   filename = "combined-tifs-cfg.bin";
+   ti-board-config {
+   board-cfg {
+   config = "board-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   sec-cfg {
+   config = "sec-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   pm-cfg {
+   config = "pm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   rm-cfg {
+   config = "rm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   };
+   combined-dm-cfg {
+   filename = "combined-dm-cfg.bin";
+   ti-board-config {
+   pm-cfg {
+   config = "pm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   rm-cfg {
+   config = "rm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   };
+
+   tiboot3 {
+   filename = "tiboot3.bin";
+   ti-secure-rom {
+   content = <_boot_spl>, <_fs_enc>, 
<_tifs_cfg>,
+   <_dm_cfg>, <_inner_cert>;
+   combined;
+   dm-data;
+   sysfw-inner-cert;
+   keyfile = "custMpk.pem";
+   sw-rev = <1>;
+   content-sbl = <_boot_spl>;
+   content-sysfw = <_fs_enc>;
+   content-sysfw-data = <_tifs_cfg>;
+   content-sysfw-inner-cert = <_inner_cert>;
+   content-dm-data = <_dm_cfg>;
+   load = <0x41c0>;
+   load-sysfw = <0x4>;
+   load-sysfw-data = <0x7f000>;
+   load-dm-data = <0x41c8>;
+   };
+   u_boot_spl: u-boot-spl {
+   no-expanded;
+   };
+   ti_fs_enc: ti-fs-enc.bin {
+   filename = "ti-sysfw/ti-fs-firmware-j7200-hs-enc.bin";
+   type = "blob-ext";
+   optional;
+   };
+   combined_tifs_cfg: combined-tifs-cfg.bin {
+   filename = "combined-tifs-cfg.bin";
+   type = "blob-ext";
+   

[PATCH v3 05/19] j721e: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.img

[Neha Malcom Francis]

By providing entries in the binman node of the device tree, binman will
be able to find and package board config artifacts generated by
TIBoardConfig with sysfw.bin and generate the final image sysfw.itb.
It will also pick out the R5 SPL and sign it with the help of TI signing
entry and generate the final tiboot3.bin.

Entries for A72 build have been added to k3-j721e-binman.dtsi to
generate tispl.bin and u-boot.img.

Support has been added for both HS-SE(SR 1.1), HS-FS(SR 2.0) and GP images
In HS-SE, the encrypted system firmware binary must be signed along with
the signed certificate binary.

tiboot3.bin and sysfw-j721e_sr1_1-hs.itb: For HS-SE devices
tiboot3.bin_fs and sysfw-j721e_sr2-hs-fs.itb: For HS-FS devices
tiboot3.bin_unsigned and sysfw-j721e-gp-evm.itb: For GP devices
.bin/img: For HS devices
.bin_unsigned/img_unsigned: For GP devices

Intention of patch is to move signing and packaging to binman,
thus making makefile target only if binman is not enabled.

It is to be noted that the bootflow followed by J721E requires:

tiboot3.bin:
* R5 SPL
* R5 SPL dtbs

sysfw.itb:
* TIFS
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg

tispl.bin:
* DM
* ATF
* OPTEE
* A72 SPL
* A72 SPL dtbs

u-boot.img:
* A72 U-Boot
* A72 U-Boot dtbs

Signed-off-by: Neha Malcom Francis 
---
 arch/arm/dts/k3-j721e-binman.dtsi | 732 ++
 .../k3-j721e-common-proc-board-u-boot.dtsi|   1 +
 .../arm/dts/k3-j721e-r5-common-proc-board.dts |   1 +
 arch/arm/mach-k3/config.mk|   4 +
 board/ti/j721e/Kconfig|   2 +
 scripts/Makefile.spl  |   2 +
 6 files changed, 742 insertions(+)
 create mode 100644 arch/arm/dts/k3-j721e-binman.dtsi

diff --git a/arch/arm/dts/k3-j721e-binman.dtsi 
b/arch/arm/dts/k3-j721e-binman.dtsi
new file mode 100644
index 00..92556eb719
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-binman.dtsi
@@ -0,0 +1,732 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+   binman: binman {
+   multiple-images;
+   };
+};
+
+#ifdef CONFIG_TARGET_J721E_R5_EVM
+
+ {
+   board-cfg {
+   filename = "board-cfg.bin";
+   ti-board-config {
+   config = "board-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   pm-cfg {
+   filename = "pm-cfg.bin";
+   ti-board-config {
+   config = "pm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   rm-cfg {
+   filename = "rm-cfg.bin";
+   ti-board-config {
+   config = "rm-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   sec-cfg {
+   filename = "sec-cfg.bin";
+   ti-board-config {
+   config = "sec-cfg.yaml";
+   schema = "schema.yaml";
+   };
+   };
+   tiboot3 {
+   filename = "tiboot3.bin";
+   ti-secure-rom {
+   content = <_boot_spl>;
+   core = "public";
+   load = ;
+   keyfile = "custMpk.pem";
+   };
+   u_boot_spl: u-boot-spl {
+   no-expanded;
+   };
+   };
+   sysfw {
+   filename = "sysfw.bin";
+   ti-secure-rom {
+   content = <_fs_cert>;
+   core = "secure";
+   load = <0x4>;
+   keyfile = "custMpk.pem";
+   countersign;
+   };
+   ti_fs_cert: ti-fs-cert.bin {
+   filename = 
"ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-cert.bin";
+   type = "blob-ext";
+   optional;
+   };
+   ti-fs-firmware-j721e_sr1_1-hs-enc.bin {
+   filename = 
"ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-enc.bin";
+   type = "blob-ext";
+   optional;
+   };
+   };
+   itb {
+   filename = "sysfw-j721e_sr1_1-hs.itb";
+   fit {
+   description = "SYSFW and Config fragments";
+   #address-cells = <1>;
+   images {
+   sysfw.bin {
+   description = "sysfw";
+   type = "firmware";
+   arch = "arm";
+   compression = "none";
+   blob-ext {
+   filename = "sysfw.bin";
+   

[PATCH v3 02/19] binman: ti-secure: Add support for TI signing

[Neha Malcom Francis]

The ti-secure entry contains certificate for binaries that will be
loaded or booted by system firmware whereas the ti-secure-rom entry
contains certificate for binaries that will be booted by ROM. Support
for both these types of certificates is necessary for booting of K3
devices.

Signed-off-by: Neha Malcom Francis 
---
 board/ti/keys/custMpk.pem |  51 
 board/ti/keys/ti-degenerate-key.pem   |  10 +
 tools/binman/btool/openssl.py | 244 +
 tools/binman/entries.rst  |  65 +
 tools/binman/etype/ti_secure.py   |  82 ++
 tools/binman/etype/ti_secure_rom.py   | 250 ++
 tools/binman/etype/x509_cert.py   |  87 +-
 tools/binman/ftest.py |  52 
 tools/binman/test/279_ti_secure.dts   |  17 ++
 tools/binman/test/280_ti_secure_rom.dts   |  17 ++
 .../test/281_ti_secure_rom_combined.dts   |  25 ++
 .../test/282_ti_secure_rom_combined_a.dts |  24 ++
 .../test/283_ti_secure_rom_combined_b.dts |  24 ++
 .../test/284_ti_secure_rom_combined_c.dts |  21 ++
 tools/binman/test/285_ti_secure_a.dts |  17 ++
 tools/binman/test/286_ti_secure_b.dts |  18 ++
 tools/binman/test/288_ti_secure_rom_a.dts |  19 ++
 tools/binman/test/289_ti_secure_rom_b.dts |  18 ++
 18 files changed, 1033 insertions(+), 8 deletions(-)
 create mode 100644 board/ti/keys/custMpk.pem
 create mode 100644 board/ti/keys/ti-degenerate-key.pem
 create mode 100644 tools/binman/etype/ti_secure.py
 create mode 100644 tools/binman/etype/ti_secure_rom.py
 create mode 100644 tools/binman/test/279_ti_secure.dts
 create mode 100644 tools/binman/test/280_ti_secure_rom.dts
 create mode 100644 tools/binman/test/281_ti_secure_rom_combined.dts
 create mode 100644 tools/binman/test/282_ti_secure_rom_combined_a.dts
 create mode 100644 tools/binman/test/283_ti_secure_rom_combined_b.dts
 create mode 100644 tools/binman/test/284_ti_secure_rom_combined_c.dts
 create mode 100644 tools/binman/test/285_ti_secure_a.dts
 create mode 100644 tools/binman/test/286_ti_secure_b.dts
 create mode 100644 tools/binman/test/288_ti_secure_rom_a.dts
 create mode 100644 tools/binman/test/289_ti_secure_rom_b.dts

diff --git a/board/ti/keys/custMpk.pem b/board/ti/keys/custMpk.pem
new file mode 100644
index 00..adba378c80
--- /dev/null
+++ b/board/ti/keys/custMpk.pem
@@ -0,0 +1,51 @@
+-BEGIN RSA PRIVATE KEY-
+MIIJKQIBAAKCAgEAvxSuSdh/ctNrI83rSA5l3CJN8g5PgvbttfLd23yR+m5Z/9X3
+tt4EHYrM0pXZ0eDEwfhQv/9IDJEiUJpMe4vzlgooJrOk2eCpVUEa+z5bJ2y/ysBx
+ry9yIu5GASVirT7HBPaxGLYswBJuD+KbPuWmoKgGRQNBF04WH6l01oRO1nmnELgR
+qQ6SHyXdf7Hy0bnyaNgzWUuCfXfM0Zz6I7T7WIjyzerVFvIsdS36YsPBCW7gBnDg
+tQcJmWLZ1uTnbG3IggdQk/fi2O3RX+PQns+TVNlf3V3ON2DxqxSKBHtlp7p/30VF
+fEuhW65OxpQ9jE6H0pQ8pPOf2vzyNnznDa1aQjfxKoHQbqGnZwMeh+0Au3NKaCgx
+ooKaowTB6If/RX6qwZ/UOwXHg/0hcf69fzjJFhlSDuYDM40dHsk2HM1OnYIpiM2b
+Kr5sX3uysjp5AGp99a0anR7NWCrPXvROgKs7T9341N40osQg2VkZLYUCXh9osUyN
+uREG6S12tViMUKg3bmZ4b4MwRk00n7QYSrm7+nvFrtYyEISEbD+agDM1/E281W5g
+VFDPfm2AlwT6jwsg/b2YK6E3vVn9SuxFoQmLF8lyFDO3BV4SXeJaHc4hVPbh6tVV
+qifrTQnfGUCCLmaJF2XZbrPWOE6NYRbWdNTeFl9RGdVCuIPSyN5LqWmXto0CAwEA
+AQKCAgAzkAwcJ0z1GnId/lJQZno8NhGckRoJuEKbR8dwlCP8VUz6Ca5H7Y9kvXDa
+Hs/hn+rYgP6hYOz7XyrIX2rmJ/T6dxEwqGeC1+o59FConcIRWHpE5zuGT6JYJL5F
+TuZa48bm4v8VMQvQZOjIZpkIFwao8c6HTwKAnHTB5IN/48I2hCt+Cn3RhfoOZ7Rm
+4gkpaSkt+7GXlhXHb82YfujNO+hbktEamhUYlQ9EK70Wa8aqmf3gHxO0JgsEFjW8
+lJaSnultlTW8SDcx3LMUUjCYumECk4oX/VlJfmKYjPlVjkr3QQ+Cm3nNucb4K4hc
+c+JL+2ERhSj8RjXL7VgbNgdPnIjvQDJuTNqecTU8xWPYrkOLQpNibbLjnutLkhJz
+fMyRtmDtrsey8WiCDuCHkPJ8/f8RjL2zWI9fzTDDIzdlEKouUFGOovaHVnbua6pn
+hymcu9d9FV3p2rcbj0ivCs7e8j+vhSxFJEJoAbcQdXCTi/n2uR7pLtoMNiUzsejy
+d46Uz+KEU920NTwE2z6JJq8I2vegnxjc7PDDrV3/5rK04B93aXiqvwWseCpxelrI
+xaMkRHbXrIXRO6MXQ3N+zNq8Dg3hjGTTvaBKuwgvqLwlXY8+Aa3ooFzEOInIOSsI
+XcWqXxt/tgZgsj9RwpC42t8kbA+BkbNk9EIUa+P5kEr2P/fO7QKCAQEA4EtArnOX
+D6tQF8uTw8USOZC2P9s/ez1z4jRq3oKP0Kv4tJiuIObJ/dUvGVD7aM5v2xaCfhm8
+xpk09VPUgghfG5jR5qVvQr75kCNToJQudWi4ngk1HwKJzzTO11giFEdybvTUA+Pj
+fmxCM0dYYqRWZoj0hLqXlUCwxE74BFIhJVjeYbf+nTQrqpllTLoW7MTZHzGx5SXx
+4dNzyVAUH49Yt2D8mgXXCkf5sGLh762wj34b/rR10Kr4O5utGMZrfTRIbuQ1pNjU
+m66baPzq+mC0BzqZEW70TgEb7lOr8rcVXLOi3r36omfd9/MHx7iZD6o3K1axSO15
+grD4ZrN7Ac3QJwKCAQEA2heCoBdpvy6YUk8AO2k8qDygTdmPQRuwjjT+Z2fMslBt
+D7DkpKwZ6Bl9OclcpiiLHmH+hv65KqYg+tR0RRb7PcogB9El9x7yKkGTPZEYWGky
+n8P84rJpKwjnwWQvPQktI1cs3YGvZA9DQTFBavRrwuzgd1oSJq5aPQ2tme0kMvWp
+l1/B/cPK+PKCi/Wfisaze1TjijP9qIeUwkdNN6WLrLU3QgsGppcg2I7RQtAIikT6
+GkuiOQAvWMsrJVV6PNrVKz4fJDJ59Rz6jbDHZNi1MEYNxQoB/Pl7QIakbfjWpHLv
+8Ey7cB2JKxjQy8tmyl8WNQVbXbE6daPXcMTUmaRAKwKCAQBv1lYMJmq+T2eCVen6
+BbvOpE+bi5EdvEiaFBTtmiBnpjg+pJq+oRU60h/H+c9CNR0lGxY6Fk9An4f+g6xE
+ojP6KLsQzJCrsVny+wpp2TlJJcxYULMCIVvhy60PR0zG29E9biqBPhJjKUvhEcQK
+e3LxcXyq6fdHXphFajLUxLbuTl+kTgBRFoBnclFGbsubh5PTsA3J+p+fQLZNPPar
+veg4l82cZykQYU8pGkUaI3sUMYd3+zd7sqRP5JHs9pMGPRmY4YW2CsAIWIn5UZNB

[PATCH v3 03/19] ti: sysfw: tiboot3: Add support for packaging sysfw.itb and tiboot3.bin

[Neha Malcom Francis]

Board config binary artifacts must be populated in the R5 output
directory to be used by binman to package sysfw.itb and tiboot3.bin.

For devices that follow combined flow, these board configuration
binaries must again be packaged into a combined board configuration
blobs to be used by binman to package tiboot3.bin.

Modify config.mk to generate all the board configuration binaries
needed.

Signed-off-by: Neha Malcom Francis 
---
 arch/arm/mach-k3/config.mk | 50 ++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk
index 9306f2627d..b280a6a048 100644
--- a/arch/arm/mach-k3/config.mk
+++ b/arch/arm/mach-k3/config.mk
@@ -39,6 +39,56 @@ $(warning "WARNING: Software revision file not found. 
Default may not work on HS
 endif
 endif
 
+O ?= .
+
+# Board config binary artifacts necessary for packaging of tiboot3.bin
+# and sysfw.itb by binman, currently for general purpose devices and
+# devices that require sysfw.itb in ROM boot image.
+
+ifdef CONFIG_BINMAN
+
+ifndef CONFIG_TARGET_J7200_R5_EVM
+BOARD_YAML = $(srctree)/board/ti/$(BOARD)/board-cfg.yaml
+RM_YAML = $(srctree)/board/ti/$(BOARD)/rm-cfg.yaml
+SEC_YAML = $(srctree)/board/ti/$(BOARD)/sec-cfg.yaml
+PM_YAML = $(srctree)/board/ti/$(BOARD)/pm-cfg.yaml
+else
+BOARD_YAML = $(srctree)/board/ti/$(BOARD)/board-cfg_j7200.yaml
+RM_YAML = $(srctree)/board/ti/$(BOARD)/rm-cfg_j7200.yaml
+SEC_YAML = $(srctree)/board/ti/$(BOARD)/sec-cfg_j7200.yaml
+PM_YAML = $(srctree)/board/ti/$(BOARD)/pm-cfg_j7200.yaml
+endif
+
+CUSTOMER_KEY = $(srctree)/board/ti/keys/custMpk.pem
+TI_DEGENERATE_KEY = $(srctree)/board/ti/keys/ti-degenerate-key.pem
+
+SCHEMA_YAML = $(srctree)/board/ti/common/schema.yaml
+
+board-cfg.yaml: $(BOARD_YAML)
+   @cp $< $@
+rm-cfg.yaml: $(RM_YAML)
+   @cp $< $@
+sec-cfg.yaml: $(SEC_YAML)
+   @cp $< $@
+pm-cfg.yaml: $(PM_YAML)
+   @cp $< $@
+
+schema.yaml: $(SCHEMA_YAML)
+   @cp $< $@
+custMpk.pem: $(CUSTOMER_KEY)
+   @cp $< $@
+ti-degenerate-key.pem: $(TI_DEGENERATE_KEY)
+   @cp $< $@
+
+INPUTS-y   += board-cfg.yaml
+INPUTS-y   += rm-cfg.yaml
+INPUTS-y   += sec-cfg.yaml
+INPUTS-y   += pm-cfg.yaml
+INPUTS-y   += schema.yaml
+INPUTS-y   += custMpk.pem
+INPUTS-y   += ti-degenerate-key.pem
+endif
+
 # tiboot3.bin is mandated by ROM and ROM only supports R5 boot.
 # So restrict tiboot3.bin creation for CPU_V7R.
 ifdef CONFIG_CPU_V7R
-- 
2.34.1

[PATCH v3 01/19] binman: ti-board-config: Add support for TI board config binaries

[Neha Malcom Francis]

The ti-board-config entry loads and validates a given YAML config file
against a given schema, and generates the board config binary. K3
devices require these binaries to be packed into the final system
firmware images.

Signed-off-by: Neha Malcom Francis 
---
 tools/binman/entries.rst  |  48 
 tools/binman/etype/ti_board_config.py | 269 ++
 tools/binman/ftest.py |  32 +++
 tools/binman/pyproject.toml   |   2 +-
 tools/binman/test/277_ti_board_cfg.dts|  11 +
 .../binman/test/278_ti_board_cfg_combined.dts |  25 ++
 .../binman/test/279_ti_board_cfg_no_type.dts  |  11 +
 .../binman/test/280_ti_board_cfg_no_file.dts  |  11 +
 .../281_ti_board_cfg_combined_no_file.dts |  13 +
 tools/binman/test/yaml/config.yaml|  19 ++
 tools/binman/test/yaml/schema.yaml|  51 
 tools/binman/test/yaml/schema_notype.yaml |  40 +++
 12 files changed, 531 insertions(+), 1 deletion(-)
 create mode 100644 tools/binman/etype/ti_board_config.py
 create mode 100644 tools/binman/test/277_ti_board_cfg.dts
 create mode 100644 tools/binman/test/278_ti_board_cfg_combined.dts
 create mode 100644 tools/binman/test/279_ti_board_cfg_no_type.dts
 create mode 100644 tools/binman/test/280_ti_board_cfg_no_file.dts
 create mode 100644 tools/binman/test/281_ti_board_cfg_combined_no_file.dts
 create mode 100644 tools/binman/test/yaml/config.yaml
 create mode 100644 tools/binman/test/yaml/schema.yaml
 create mode 100644 tools/binman/test/yaml/schema_notype.yaml

diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst
index b71af801fd..14a2d03fad 100644
--- a/tools/binman/entries.rst
+++ b/tools/binman/entries.rst
@@ -1658,6 +1658,54 @@ by setting the size of the entry to something larger 
than the text.
 
 
 
+.. _etype_ti_board_config:
+
+Entry: ti-board-config: An entry containing a TI schema validated board config 
binary
+-
+
+This etype supports generation of two kinds of board configuration
+binaries: singular board config binary as well as combined board config
+binary.
+
+Properties / Entry arguments:
+- config-file: File containing board configuration data in YAML
+- schema-file: File containing board configuration YAML schema against
+  which the config file is validated
+
+Output files:
+- board config binary: File containing board configuration binary
+
+These above parameters are used only when the generated binary is
+intended to be a single board configuration binary. Example::
+
+my-ti-board-config {
+ti-board-config {
+config = "board-config.yaml";
+schema = "schema.yaml";
+};
+};
+
+To generate a combined board configuration binary, we pack the
+needed individual binaries into a ti-board-config binary. In this case,
+the available supported subnode names are board-cfg, pm-cfg, sec-cfg and
+rm-cfg. The final binary is prepended with a header containing details about
+the included board config binaries. Example::
+
+my-combined-ti-board-config {
+ti-board-config {
+board-cfg {
+config = "board-cfg.yaml";
+schema = "schema.yaml";
+};
+sec-cfg {
+config = "sec-cfg.yaml";
+schema = "schema.yaml";
+};
+}
+}
+
+
+
 .. _etype_u_boot:
 
 Entry: u-boot: U-Boot flat binary
diff --git a/tools/binman/etype/ti_board_config.py 
b/tools/binman/etype/ti_board_config.py
new file mode 100644
index 00..cd7d80cdc4
--- /dev/null
+++ b/tools/binman/etype/ti_board_config.py
@@ -0,0 +1,269 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2022 Texas Instruments Incorporated - https://www.ti.com/
+# Written by Neha Malcom Francis 
+#
+# Entry-type module for generating schema validated TI board
+# configuration binary
+#
+
+import os
+import struct
+import tempfile
+import yaml
+
+from collections import OrderedDict
+from jsonschema import validate
+from shutil import copyfileobj
+from shutil import rmtree
+
+from binman.entry import Entry
+from binman.etype.section import Entry_section
+from binman.etype.blob_ext import Entry_blob_ext
+from binman.etype.blob_ext_list import Entry_blob_ext_list
+from dtoc import fdt_util
+from u_boot_pylib import tools, tout
+
+BOARDCFG = 0xB
+BOARDCFG_SEC = 0xD
+BOARDCFG_PM = 0xE
+BOARDCFG_RM = 0xC
+BOARDCFG_NUM_ELEMS = 4
+
+class Entry_ti_board_config(Entry_section):
+"""An entry containing a TI schema validated board config binary
+
+This etype supports generation of two kinds of board configuration
+binaries: singular board config binary as well as combined board config
+binary.
+
+Properties / Entry arguments:
+- config-file: File containing board configuration data in YAML
+- schema-file: File containing board configuration YAML schema against
+  

[PATCH v3 00/19] Migration to using binman for bootloader

[Neha Malcom Francis]

This series aims to eliminate the use of additional custom repositories
such as k3-image-gen (K3 Image Generation) repo and core-secdev-k3 (K3
Security Development Tools) that was plumbed into the U-Boot build flow
to generate boot images for TI K3 platform devices. And instead, we move
towards using binman that aligns better with the community standard build
flow.

This series uses binman for all K3 platforms supported on U-Boot currently;
both HS (High Security, both SE and FS) and GP (General Purpose) devices.

Background on using k3-image-gen:
* TI K3 devices require a SYSFW (System Firmware) image consisting
of a signed system firmware image and board configuration binaries,
this is needed to bring up system firmware during U-Boot R5 SPL
startup.
* Board configuration data contain board-specific information
such as resource management, power management and security.

Background on using core-secdev-k3:
* Contains resources to sign x509 certificates for HS devices

Series intends to use binman to take over the packaging and signing for
the R5 bootloader images tiboot3.bin (and sysfw.itb, for non-combined
boot flow) instead of k3-image-gen.

Series also packages the A72/A53 bootloader images (tispl.bin and
u-boot.img) using ATF, OPTEE and DM (Device Manager)

Changes in v3:
- added support for HS-FS devices
- added support for AM68-sk
- added back dropped documentation patch
- changed prefix for SYSFW and DM files to expected directory
  name
- extended test coverage to 100%
- documentation fixes
- corrected formatting changes

Changes in v2:
- removed all external scripts
- created ti-board-config etype to support generation of board
  config binaries
- created ti-secure and ti-secure-rom etypes to handle signing
  instead of using external TI_SECURE_DEV_PKG
- updated openssl btool to support x509 certificate generation
- dropped Makefile changes to obtain external binary components,
  moving to using BINMAN_INDIRS to achieve the same

v1: 
https://patchwork.ozlabs.org/project/uboot/cover/20230120101903.179959-1-n-fran...@ti.com/
v2: 
https://patchwork.ozlabs.org/project/uboot/cover/20230404121342.446935-1-n-fran...@ti.com/

Neha Malcom Francis (19):
  binman: ti-board-config: Add support for TI board config binaries
  binman: ti-secure: Add support for TI signing
  ti: sysfw: tiboot3: Add support for packaging sysfw.itb and
tiboot3.bin
  j721e: schema: yaml: Add general schema and J721E board config files
  j721e: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin,
u-boot.img
  j7200: yaml: Add J7200 board config files
  j7200: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img
  am65x: yaml: Add AM65x board config files
  am65: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin,
u-boot.img
  am64x: yaml: Add board configs for AM64x
  am64x: dts: binman: Package tiboot3.bin, tispl.bin u-boot.img
  j721s2: yaml: Add board configs for J721S2
  j721s2: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img
  am62: yaml: Add board configs for AM62
  am625: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img
  am62a: yaml: Add board configs for AM62ax
  am62a: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img
  k3: tools: config.mk: Update makefile and remove scripts
  doc: board: ti: Update documentation for binman flow

 arch/arm/dts/k3-am625-r5-sk.dts   |1 +
 arch/arm/dts/k3-am625-sk-binman.dtsi  |  529 +++
 arch/arm/dts/k3-am625-sk-u-boot.dtsi  |2 +
 arch/arm/dts/k3-am62a-sk-binman.dtsi  |  528 +++
 arch/arm/dts/k3-am62a7-r5-sk.dts  |1 +
 arch/arm/dts/k3-am62a7-sk.dts |1 +
 arch/arm/dts/k3-am642-evm-u-boot.dtsi |2 +
 arch/arm/dts/k3-am642-r5-evm.dts  |1 +
 arch/arm/dts/k3-am64x-binman.dtsi |  569 
 arch/arm/dts/k3-am654-base-board-u-boot.dtsi  |1 +
 .../dts/k3-am654-r5-base-board-u-boot.dtsi|1 +
 arch/arm/dts/k3-am65x-binman.dtsi |  551 
 arch/arm/dts/k3-j7200-binman.dtsi |  529 +++
 .../k3-j7200-common-proc-board-u-boot.dtsi|2 +
 arch/arm/dts/k3-j721e-binman.dtsi |  732 +
 .../k3-j721e-common-proc-board-u-boot.dtsi|1 +
 .../arm/dts/k3-j721e-r5-common-proc-board.dts |1 +
 arch/arm/dts/k3-j721s2-binman.dtsi|  613 
 .../k3-j721s2-common-proc-board-u-boot.dtsi   |2 +
 .../dts/k3-j721s2-r5-common-proc-board.dts|1 +
 arch/arm/mach-k3/config.mk|  126 +-
 board/ti/am62ax/Kconfig   |2 +
 board/ti/am62ax/board-cfg.yaml|   36 +
 board/ti/am62ax/pm-cfg.yaml   |   12 +
 board/ti/am62ax/rm-cfg.yaml   | 1151 +++
 board/ti/am62ax/sec-cfg.yaml  |  375 +++
 

Pull request for efi-2023-07-rc1-2

[Heinrich Schuchardt]

Dear Tom,

The following changes since commit 5db4972a5bbdbf9e3af48ffc9bc4fec73b7b6a79:

  Merge tag 'u-boot-nand-20230417' of
https://source.denx.de/u-boot/custodians/u-boot-nand-flash (2023-04-17
10:47:33 -0400)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-efi.git
tags/efi-2023-07-rc1-2

for you to fetch changes up to b10bfd0019f601e2608370ed47741da201423d55:

  efi_loader: Fix flexible array member definitions (2023-04-21
08:50:35 +0200)

Gitlab CI showed no issues:
https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/16067


Pull request for efi-2023-07-rc1-2

Documentation:

* Describe Python coding style

UEFI:

* Enable tests for authenticated capsules on the sandbox
* Fix pylint warnings
* Correct struct efi_hii_keyboard_layout definition


Heinrich Schuchardt (5):
  doc: codingstyle: Python coding style
  efi_loader: remove unused efi_capsule_authenticate
  test: fix pylint warning for capsule tests
  sandbox: enable CONFIG_EFI_CAPSULE_AUTHENTICATE
  test: fix launch_efi()

Ilias Apalodimas (1):
  efi_loader: Fix flexible array member definitions

 configs/sandbox_defconfig  |  1 +
 configs/sandbox_flattree_defconfig |  1 +
 doc/develop/codingstyle.rst|  7 
 include/efi_api.h  |  2 +-
 lib/efi_loader/efi_capsule.c   |  6 
 test/py/tests/test_efi_capsule/conftest.py | 27 +-
 .../test_efi_capsule/test_capsule_firmware_fit.py  | 35 +-
 .../test_capsule_firmware_signed_fit.py| 41
+++---
 .../test_capsule_firmware_signed_raw.py| 38
++--
 test/py/tests/test_efi_fit.py  |  4 ++-
 10 files changed, 78 insertions(+), 84 deletions(-)

Re: [PATCH 1/2] firmware: zynqmp: Mask expected and show unexpected warning

[Stefan Herbrechtsmeier]

Am 21.04.2023 um 12:08 schrieb Michal Simek:

On 4/21/23 11:56, Stefan Herbrechtsmeier wrote:

Hi Michal,

Am 20.04.2023 um 14:39 schrieb Michal Simek:


On 4/20/23 14:30, Stefan Herbrechtsmeier wrote:

Am 20.04.2023 um 14:11 schrieb Michal Simek:

On 4/20/23 14:03, Stefan Herbrechtsmeier wrote:

Hi Michal,

Am 20.04.2023 um 13:06 schrieb Michal Simek:

Hi,

On 4/19/23 09:58, Stefan Herbrechtsmeier wrote:

Hi Michal,

Am 17.04.2023 um 12:16 schrieb Michal Simek:


On 4/3/23 15:34, Stefan Herbrechtsmeier wrote:

From: Stefan Herbrechtsmeier


Mask the expected and show the unexpected warning "No 
permission to

change config object" for NODE_OCM_BANK_0 because this node is
used to
detect if further zynqmp_pmufw_node function calls should be
skipped.

Signed-off-by: Stefan Herbrechtsmeier

---

  drivers/firmware/firmware-zynqmp.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/firmware/firmware-zynqmp.c
b/drivers/firmware/firmware-zynqmp.c
index dc8e3ad2b9..8435b58ef9 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -251,7 +251,7 @@ int zynqmp_pmufw_load_config_object(const 
void

*cfg_obj, size_t size)
 err = xilinx_pm_request(PM_SET_CONFIGURATION,
(u32)(u64)cfg_obj, 0, 0,
 0, ret_payload);
 if (err == XST_PM_NO_ACCESS) {
-   if (((u32 *)cfg_obj)[NODE_ID_LOCATION] ==
NODE_OCM_BANK_0) {
+   if (((u32 *)cfg_obj)[NODE_ID_LOCATION] !=
NODE_OCM_BANK_0) {
 printf("PMUFW:  No permission to change
config object\n");
 return err;
 }


First of all we should very likely create a macro for 
NODE_OCM_BANK_0

to cover that dependency that it is used in 3 different locations
which have to match.


Okay, I will add a PMUFW_CFG_OBJ_SUPPORT_NODE macro.

The second is the change you have in 2/2 should be the part of 
this

patch because when only 1/2 is applied you change behavior.


The patches should be independent, and the behavior change is
intended.
The message should be printed if you don’t heave the permission 
for a

specific config object and not if the driver checks for support of
config objects. The NODE_OCM_BANK_0 call should never fail if 
load of

config objects is supported.


And changes in 2/2 makes sense.

I would be even fine to move skip_config out of 
zynqmp_pmufw_node()


The zynqmp_pmufw_node() function doesn't return an error and the
skip_config variable is static inside the function.

and setting up skip_config value directly in 
zynqmp_power_probe() not

to check in every call.


We still need to check the skip_config variable inside
zynqmp_pmufw_node
to skip the load of the config object if the pmufw doesn't 
support it.




 85 if (ret == XST_PM_NO_ACCESS && id == NODE_OCM_BANK_0)
 86 skip_config = true;


Without testing on HW I though to change it like this that 
skip_config

is configured and checked only once at probe time.

What do you think?


Patch looks okay except the printf. Is this really necessary? 
Could we

use a debug instead?


It is feature which you need to explicitly enable in PMUFW to work.


Is this information really necessary for a production build?


For production build no. But there are other messages which are 
likely not needed. Like a silicon version (production is only one 
version) for example.


Could we use log_info instead of printf?


That should be fine that you can filter it out if you like.




It means having information in boot log is quite worth.


Either we should print a message in any case or only if the feature is
disabled because in this case the zynqmp_pmufw_node() is a nop.


By default that feature should be disabled in standard pmufw build.
I don't have a preference but I want to see that message only once, 
disabled or enabled.


Is it possible to call the zynqmp_pmufw_node() in the probe() for the 
other platforms?


Not sure what you mean by other platforms.
If you mean different xilinx SoCs then no.
If you mean other then SOM. You can enable that feature and use it but 
it is only tested and enabled by default on SOMs.


I was confused by the `IS_ENABLED(CONFIG_ARCH_ZYNQMP)`. Why is this needed?


Actually maybe even we should create variable based on it to be able
to use it in scripts.
Because it is everybody decision if you want to let OS to send that
config fragments to PMUFW or just close that doors (right now you can
do it via command).

Also thinking that by default that skip_config should be false by
default and only enable it before calling that OCM. Or just change 
the

name to enable_config to be able to place it to bss section.


The skip_config is false by default and the function is called by the
probe as first user.


It should be but question is if it is in all cases. At least you can 
disable power domain driver and then first call can be via command.


We should call the zynqmp_pmufw_node() in 

[PATCH 13/13] smegw01: Fix fallback to altbootcmd

[Fabio Estevam]

From: Eduard Strehlau 

The bootcmd/altbootcmd mechanism is not invoked for bootmenus.
Manually compare bootcount and bootlimit to implement fallback on all
codepaths.

Signed-off-by: Eduard Strehlau 
Signed-off-by: Fabio Estevam 
---
Changes since v1:
- None

 configs/smegw01_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index fe8152f33e..3d2713f528 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -23,7 +23,7 @@ CONFIG_AUTOBOOT_MENU_SHOW=y
 # CONFIG_CMD_BOOTEFI_BOOTMGR is not set
 CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="if test \"${ustate}\" = 1; then setenv upgrade_available 
1; saveenv; fi; run mmcboot; "
+CONFIG_BOOTCOMMAND="if test \"${bootcount}\" -gt \"${bootlimit}\"; then run 
altbootcmd; else if test \"${ustate}\" = 1; then setenv upgrade_available 1; 
saveenv; fi; run mmcboot; fi;"
 CONFIG_USE_PREBOOT=y
 CONFIG_PREBOOT="run setup_boot_menu;"
 CONFIG_HUSH_PARSER=y
-- 
2.38.1

[PATCH v2 12/13] smegw01: Disable additional boot menu options

[Fabio Estevam]

From: Eduard Strehlau 

Defaults have changed, we do not want the bootmenu to contain EFI
options.

Signed-off-by: Eduard Strehlau 
Signed-off-by: Fabio Estevam 
---
Changes since v1:
- None

 configs/smegw01_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index ea25b3b87c..fe8152f33e 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -19,6 +19,8 @@ CONFIG_SYS_MEMTEST_END=0xa000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_AUTOBOOT_MENU_SHOW=y
+# CONFIG_BOOTSTD is not set
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
 CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="if test \"${ustate}\" = 1; then setenv upgrade_available 
1; saveenv; fi; run mmcboot; "
-- 
2.38.1

[PATCH v2 11/13] smegw01: Read the second MAC address

[Fabio Estevam]

From: Fabio Estevam 

Currently, only the first MAC address is read from the fuses.

The second MAC address is not read and Linux assigns a random one.

To prevent this behavior, read the second MAC address from the fuses
and store it into the eth1addr environment variable so that it
can be passed to Linux.

Signed-off-by: Fabio Estevam 
---
Changes since v1:
- Fixed typo in the Subject "smegw01".

 board/storopack/smegw01/smegw01.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/board/storopack/smegw01/smegw01.c 
b/board/storopack/smegw01/smegw01.c
index e786429476..605253ead3 100644
--- a/board/storopack/smegw01/smegw01.c
+++ b/board/storopack/smegw01/smegw01.c
@@ -82,6 +82,7 @@ int board_init(void)
 int board_late_init(void)
 {
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+   unsigned char eth1addr[6];
 
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 
@@ -93,6 +94,11 @@ int board_late_init(void)
 */
clrsetbits_le16(>wcr, 0, 0x10);
 
+   /* Get the second MAC address */
+   imx_get_mac_from_fuse(1, eth1addr);
+   if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
+   eth_env_set_enetaddr("eth1addr", eth1addr);
+
return 0;
 }
 
-- 
2.38.1

[PATCH v2 10/13] smegw01: Add lockdown U-Boot env support

[Fabio Estevam]

From: Eduard Strehlau 

Add lockdown U-Boot env support so that only certain U-Boot environment
variables are allowed to be modified.

Signed-off-by: Eduard Strehlau 
Signed-off-by: Fabio Estevam 
---
Changes since v1:
- None

 board/storopack/smegw01/Kconfig   |  7 +
 board/storopack/smegw01/smegw01.c | 17 +++
 configs/smegw01_defconfig | 11 ++-
 include/configs/smegw01.h | 48 +--
 4 files changed, 79 insertions(+), 4 deletions(-)

diff --git a/board/storopack/smegw01/Kconfig b/board/storopack/smegw01/Kconfig
index d8f24695d0..390214c285 100644
--- a/board/storopack/smegw01/Kconfig
+++ b/board/storopack/smegw01/Kconfig
@@ -12,4 +12,11 @@ config SYS_CONFIG_NAME
 config IMX_CONFIG
default "board/storopack/smegw01/imximage.cfg"
 
+config SYS_BOOT_LOCKED
+   bool "Lock boot process to EMMC"
+   default y
+   help
+ Say N here if you want to boot from eMMC and SD.
+ Say Y to boot from eMMC.
+
 endif
diff --git a/board/storopack/smegw01/smegw01.c 
b/board/storopack/smegw01/smegw01.c
index 9482f88773..e786429476 100644
--- a/board/storopack/smegw01/smegw01.c
+++ b/board/storopack/smegw01/smegw01.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -113,3 +114,19 @@ uint mmc_get_env_part(struct mmc *mmc)
 
return part;
 }
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+   if (op == ENVOP_SAVE || op == ENVOP_ERASE)
+   return ENVL_MMC;
+
+   switch (prio) {
+   case 0:
+   return ENVL_NOWHERE;
+
+   case 1:
+   return ENVL_MMC;
+   }
+
+   return ENVL_UNKNOWN;
+}
diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index 54cf1cfc1f..ea25b3b87c 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -7,6 +7,7 @@ CONFIG_ENV_OFFSET=0x10
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx7d-smegw01"
 CONFIG_TARGET_SMEGW01=y
+# CONFIG_SYS_BOOT_LOCKED is not set
 CONFIG_ENV_OFFSET_REDUND=0x11
 CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
 # CONFIG_ARMV7_VIRT is not set
@@ -17,13 +18,18 @@ CONFIG_SYS_MEMTEST_START=0x8000
 CONFIG_SYS_MEMTEST_END=0xa000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_AUTOBOOT_MENU_SHOW=y
+CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="if test \"${ustate}\" = 1; then setenv upgrade_available 
1; saveenv; fi; if run loadimage; then run mmcboot; else run altbootcmd; fi; "
+CONFIG_BOOTCOMMAND="if test \"${ustate}\" = 1; then setenv upgrade_available 
1; saveenv; fi; run mmcboot; "
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run setup_boot_menu;"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
 # CONFIG_CMD_BOOTD is not set
 CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_BOOTMENU=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_XIMG is not set
 CONFIG_CMD_MEMTEST=y
@@ -43,9 +49,12 @@ CONFIG_CMD_SQUASHFS=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_WRITEABLE_LIST=y
+CONFIG_ENV_ACCESS_IGNORE_FORCE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOOTCOUNT_LIMIT=y
diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 8521883277..6f373973ab 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -22,6 +22,32 @@
 #define EXTRA_BOOTPARAMS
 #endif
 
+#ifdef CONFIG_SYS_BOOT_LOCKED
+#define EXTRA_ENV_FLAGS
+#define SETUP_BOOT_MENU "setup_boot_menu=setenv bootmenu_0 eMMC=run bootcmd\0"
+#else
+#define EXTRA_ENV_FLAGS "mmcdev:dw,"
+#define SETUP_BOOT_MENU "setup_boot_menu=" \
+   "if test \"${mmcdev}\" = 1; then " \
+   "setenv emmc_priority 0;" \
+   "setenv sd_priority 1;" \
+   "else " \
+   "setenv emmc_priority 1;" \
+   "setenv sd_priority 0;" \
+   "fi;" \
+   "setenv bootmenu_${emmc_priority} eMMC=run boot_emmc;" \
+   "setenv bootmenu_${sd_priority} SD=run boot_sd;\0"
+#endif
+
+#define CFG_ENV_FLAGS_LIST_STATIC \
+   "mmcpart:dw," \
+   "mmcpart_committed:dw," \
+   "ustate:dw," \
+   "bootcount:dw," \
+   "bootlimit:dw," \
+   "upgrade_available:dw," \
+   EXTRA_ENV_FLAGS
+
 #define CFG_EXTRA_ENV_SETTINGS \
"image=fitImage\0" \
"console=ttymxc0\0" \
@@ -40,13 +66,28 @@
  "fi;\0" \
"bootlimit=3\0" \
"fit_addr=0x8800\0" \
-   "loadimage=load mmc ${mmcdev}#rootfs-${mmcpart_committed} ${fit_addr} 
boot/${image}\0" \
+   "loadimage=load mmc ${mmcdev}:${gpt_partition_entry} ${fit_addr} 
boot/${image}\0" \
"loadpart=gpt setenv mmc ${mmcdev} rootfs-${mmcpart_committed}\0" \
"loadbootpart=mmc partconf 1 boot_part\0" \
-   "mmcboot=echo Booting from mmc ...; " \
+   "boot_sd=setenv 

[PATCH v2 09/13] smegw01: Switch to fitImage

[Fabio Estevam]

From: Eduard Strehlau 

Instead of loading the zImage kernel and the devicetree separately, switch
to the fitImage format, which is more convenient when working with secure
boot, for example.

Signed-off-by: Eduard Strehlau 
Signed-off-by: Fabio Estevam 
---
Changes since v1:
- None

 include/configs/smegw01.h | 14 +-
 1 file changed, 5 insertions(+), 9 deletions(-)

diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 8f68472f5b..8521883277 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -23,7 +23,7 @@
 #endif
 
 #define CFG_EXTRA_ENV_SETTINGS \
-   "image=zImage\0" \
+   "image=fitImage\0" \
"console=ttymxc0\0" \
"fdtfile=imx7d-smegw01.dtb\0" \
"fdt_addr=0x8300\0" \
@@ -39,8 +39,8 @@
"saveenv;" \
  "fi;\0" \
"bootlimit=3\0" \
-   "loadimage=load mmc ${mmcdev}#rootfs-${mmcpart_committed} ${loadaddr} 
boot/${image}\0" \
-   "loadfdt=load mmc ${mmcdev}#rootfs-${mmcpart_committed} ${fdt_addr} 
boot/${fdtfile}\0" \
+   "fit_addr=0x8800\0" \
+   "loadimage=load mmc ${mmcdev}#rootfs-${mmcpart_committed} ${fit_addr} 
boot/${image}\0" \
"loadpart=gpt setenv mmc ${mmcdev} rootfs-${mmcpart_committed}\0" \
"loadbootpart=mmc partconf 1 boot_part\0" \
"mmcboot=echo Booting from mmc ...; " \
@@ -48,12 +48,8 @@
"run loadpart; " \
"run loadbootpart; " \
"run mmcargs; " \
-   "if run loadfdt; then " \
-   "if bootz ${loadaddr} - ${fdt_addr}; then " \
-   "; " \
-   "else " \
-   "run altbootcmd; " \
-   "fi;" \
+   "if bootm ${fit_addr}; then " \
+   "; " \
"else " \
"run altbootcmd; " \
"fi;\0" \
-- 
2.38.1

[PATCH v2 08/13] smegw01: Change default boot device to eMMC

[Fabio Estevam]

From: Eduard Strehlau 

Let eMMC be the default boot medium.

Signed-off-by: Eduard Strehlau 
Signed-off-by: Fabio Estevam 
---
Changes since v1:
- None

 include/configs/smegw01.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 71f2d9c8e8..8f68472f5b 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -28,7 +28,7 @@
"fdtfile=imx7d-smegw01.dtb\0" \
"fdt_addr=0x8300\0" \
"bootm_size=0x1000\0" \
-   "mmcdev=0\0" \
+   "mmcdev=1\0" \
"mmcpart=1\0" \
"mmcpart_committed=1\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
-- 
2.38.1

[PATCH v2 7/7] smegw01: Enable EMMC boot from multiple partitions

[Fabio Estevam]

From: Eduard Strehlau 

GPT Partition labels are used for determining the right
root filesystem to boot from.

The U-Boot environment is configured to reside in the eMMC hardware
boot partition we are currently booted from.

This should enable a dual copy approach for upgrading the bootloader.
One can overwrite the inactive hardware partition with new bootloader
and environment and afterwards switch the eMMC boot partition for an
atomic bootloader switch.

Signed-off-by: Eduard Strehlau 
Signed-off-by: Fabio Estevam 
---
Changes since v1:
- Remove custom mmc macro (Pali)
- Handle all the possible partition cases (Pali).

Cc: Pali Rohár 

 board/storopack/smegw01/smegw01.c | 32 +++
 configs/smegw01_defconfig |  2 ++
 include/configs/smegw01.h | 12 
 3 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/board/storopack/smegw01/smegw01.c 
b/board/storopack/smegw01/smegw01.c
index e6bff80e5565..db6069a02722 100644
--- a/board/storopack/smegw01/smegw01.c
+++ b/board/storopack/smegw01/smegw01.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -93,3 +94,34 @@ int board_late_init(void)
 
return 0;
 }
+
+uint mmc_get_env_part(struct mmc *mmc)
+{
+   uint part;
+
+   if (mmc->part_config == MMCPART_NOAVAILABLE) {
+   part = 0;
+   } else {
+   switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
+   case 0: /* Booting from this eMMC device is disabled */
+   printf("Error - Booting from this eMMC device is 
disabled\n");
+   printf("Hint: Use 'mmc partconf' command to choose boot 
partition\n");
+   return -ENODEV;
+   case 1: /* Boot partition 1 is used for booting */
+   part = 1;
+   break;
+   case 2: /* Boot partition 2 is used for booting */
+   part = 2;
+   break;
+   case 7: /* User area is used for booting */
+   part = 0;
+   break;
+   default: /* Other values are reserved / unsupported */
+   printf("Error - This eMMC device has configured 
Reserved boot option\n");
+   printf("Hint: Use 'mmc partconf' command to choose boot 
partition\n");
+   return -ENODEV;
+   }
+   }
+
+   return part;
+}
diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index b3580d5d6e54..54cf1cfc1f1b 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -30,6 +30,7 @@ CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_UNZIP=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
 CONFIG_CMD_DHCP=y
@@ -44,6 +45,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOOTCOUNT_LIMIT=y
diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 277c828d0e07..71f2d9c8e85c 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -32,17 +32,21 @@
"mmcpart=1\0" \
"mmcpart_committed=1\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
-   "root=/dev/mmcblk0p${mmcpart_committed} rootwait rw " \
-   __stringify(EXTRA_BOOTPARAMS) "\0" \
+   "root=/dev/mmcblk${mmcdev}p${gpt_partition_entry} rootwait rw " 
\
+   __stringify(EXTRA_BOOTPARAMS) " SM_ROOT_DEV=${mmcdev} 
SM_ROOT_PART=${gpt_partition_entry} SM_BOOT_PART=${boot_part}\0" \
"commit_mmc=if test \"${ustate}\" = 1 -a \"${mmcpart}\" != 
\"${mmcpart_committed}\"; then " \
  "setenv mmcpart_committed ${mmcpart};" \
"saveenv;" \
  "fi;\0" \
"bootlimit=3\0" \
-   "loadimage=load mmc ${mmcdev}:${mmcpart_committed} ${loadaddr} 
boot/${image}\0" \
-   "loadfdt=load mmc ${mmcdev}:${mmcpart_committed} ${fdt_addr} 
boot/${fdtfile}\0" \
+   "loadimage=load mmc ${mmcdev}#rootfs-${mmcpart_committed} ${loadaddr} 
boot/${image}\0" \
+   "loadfdt=load mmc ${mmcdev}#rootfs-${mmcpart_committed} ${fdt_addr} 
boot/${fdtfile}\0" \
+   "loadpart=gpt setenv mmc ${mmcdev} rootfs-${mmcpart_committed}\0" \
+   "loadbootpart=mmc partconf 1 boot_part\0" \
"mmcboot=echo Booting from mmc ...; " \
  "run commit_mmc; " \
+   "run loadpart; " \
+   "run loadbootpart; " \
"run mmcargs; " \
"if run loadfdt; then " \
"if bootz ${loadaddr} - ${fdt_addr}; then " \
-- 
2.34.1

[PATCH v2 06/13] smegw01: Only commit to new partition if update was successful

[Fabio Estevam]

From: Eduard Strehlau 

When performing rootfs update via swupdate, it is convenient to check the
'ustate' variable to decide whether the update succeeded or not.

Signed-off-by: Eduard Strehlau 
Signed-off-by: Fabio Estevam 
---
Changes since v1:
- None

 include/configs/smegw01.h | 16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 05edaac42f..277c828d0e 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -30,13 +30,19 @@
"bootm_size=0x1000\0" \
"mmcdev=0\0" \
"mmcpart=1\0" \
+   "mmcpart_committed=1\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
-   "root=/dev/mmcblk0p${mmcpart} rootwait rw " \
+   "root=/dev/mmcblk0p${mmcpart_committed} rootwait rw " \
__stringify(EXTRA_BOOTPARAMS) "\0" \
+   "commit_mmc=if test \"${ustate}\" = 1 -a \"${mmcpart}\" != 
\"${mmcpart_committed}\"; then " \
+ "setenv mmcpart_committed ${mmcpart};" \
+   "saveenv;" \
+ "fi;\0" \
"bootlimit=3\0" \
-   "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \
-   "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \
+   "loadimage=load mmc ${mmcdev}:${mmcpart_committed} ${loadaddr} 
boot/${image}\0" \
+   "loadfdt=load mmc ${mmcdev}:${mmcpart_committed} ${fdt_addr} 
boot/${fdtfile}\0" \
"mmcboot=echo Booting from mmc ...; " \
+ "run commit_mmc; " \
"run mmcargs; " \
"if run loadfdt; then " \
"if bootz ${loadaddr} - ${fdt_addr}; then " \
@@ -48,10 +54,12 @@
"run altbootcmd; " \
"fi;\0" \
"altbootcmd=echo Performing rollback...; " \
-   "if test \"${mmcpart}\" = 1; then " \
+   "if test \"${mmcpart_committed}\" = 1; then " \
"setenv mmcpart 2; " \
+   "setenv mmcpart_committed 2;" \
"else " \
"setenv mmcpart 1; " \
+   "setenv mmcpart_committed 1;" \
"fi; setenv bootcount 0; setenv upgrade_available; setenv 
ustate 3; saveenv; " \
"run bootcmd;\0"
 
-- 
2.38.1

[PATCH v2 05/13] smegw01: Run altbootcmd in the case of failure

[Fabio Estevam]

From: Eduard Strehlau 

Run the altbootcmd script if any step of bootcmd fails.

This ensures that always a valid image can be run.

Signed-off-by: Eduard Strehlau 
Signed-off-by: Fabio Estevam 
---
Changes since v1:
- None

 configs/smegw01_defconfig | 2 +-
 include/configs/smegw01.h | 8 +++-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index 418151a6de..b3580d5d6e 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -18,7 +18,7 @@ CONFIG_SYS_MEMTEST_END=0xa000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="if test \"${ustate}\" = 1; then setenv upgrade_available 
1; saveenv; fi; if run loadimage; then run mmcboot; fi; "
+CONFIG_BOOTCOMMAND="if test \"${ustate}\" = 1; then setenv upgrade_available 
1; saveenv; fi; if run loadimage; then run mmcboot; else run altbootcmd; fi; "
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 6ee4acc70d..05edaac42f 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -39,7 +39,13 @@
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if run loadfdt; then " \
-   "bootz ${loadaddr} - ${fdt_addr}; " \
+   "if bootz ${loadaddr} - ${fdt_addr}; then " \
+   "; " \
+   "else " \
+   "run altbootcmd; " \
+   "fi;" \
+   "else " \
+   "run altbootcmd; " \
"fi;\0" \
"altbootcmd=echo Performing rollback...; " \
"if test \"${mmcpart}\" = 1; then " \
-- 
2.38.1

[PATCH v2 04/13] smegw01: Add altbootcmd

[Fabio Estevam]

From: Eduard Strehlau 

Add an altbootcmd script, which is convenient way to integrate with
swupdate and perform a roll back of the previous working version in the
case of update failure.

Signed-off-by: Eduard Strehlau 
Signed-off-by: Fabio Estevam 
---
Changes since v1:
- None

 configs/smegw01_defconfig | 2 +-
 include/configs/smegw01.h | 8 
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index 5d9d419463..418151a6de 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -18,7 +18,7 @@ CONFIG_SYS_MEMTEST_END=0xa000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="if run loadimage; then run mmcboot; fi; "
+CONFIG_BOOTCOMMAND="if test \"${ustate}\" = 1; then setenv upgrade_available 
1; saveenv; fi; if run loadimage; then run mmcboot; fi; "
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index a356f095a6..6ee4acc70d 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -33,6 +33,7 @@
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/mmcblk0p${mmcpart} rootwait rw " \
__stringify(EXTRA_BOOTPARAMS) "\0" \
+   "bootlimit=3\0" \
"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \
"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \
"mmcboot=echo Booting from mmc ...; " \
@@ -40,6 +41,13 @@
"if run loadfdt; then " \
"bootz ${loadaddr} - ${fdt_addr}; " \
"fi;\0" \
+   "altbootcmd=echo Performing rollback...; " \
+   "if test \"${mmcpart}\" = 1; then " \
+   "setenv mmcpart 2; " \
+   "else " \
+   "setenv mmcpart 1; " \
+   "fi; setenv bootcount 0; setenv upgrade_available; setenv 
ustate 3; saveenv; " \
+   "run bootcmd;\0"
 
 /* Physical Memory Map */
 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-- 
2.38.1

[PATCH v2 03/13] smegw01: Select bootcount support

[Fabio Estevam]

From: Eduard Strehlau 

Add automatic boot counter that increases after every
reset. After a power-on reset, it will be initialized with 1,
and each reboot will increment the value by 1. By default it is
disabled if bootlimit isn't set.

Signed-off-by: Eduard Strehlau 
Signed-off-by: Fabio Estevam 
---
Changes since v1:
- None

 configs/smegw01_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index f15291f1dd..5d9d419463 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -46,6 +46,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_BOUNCE_BUFFER=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
 CONFIG_DFU_MMC=y
 CONFIG_DM_I2C=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-- 
2.38.1

[PATCH v2 02/13] smegw01: Select CONFIG_CMD_SQUASHFS

[Fabio Estevam]

From: Eduard Strehlau 

Select CONFIG_CMD_SQUASHFS so that the SquashFS U-Boot commands
are available.

Signed-off-by: Eduard Strehlau 
Signed-off-by: Fabio Estevam 
---
Changes since v1:
- None

 configs/smegw01_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index 1e0b9aa5be..f15291f1dd 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -38,6 +38,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_SQUASHFS=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
-- 
2.38.1

[PATCH v2 01/13] smegw01: Enable setting additional boot params

[Fabio Estevam]

From: Eduard Strehlau 

Introduce EXTRA_BOOTPARAMS to allow passing additional parameters
to kernel command line. This is useful for debugging purposes.

Signed-off-by: Eduard Strehlau 
Signed-off-by: Fabio Estevam 
---
Changes since v1:
- None

 include/configs/smegw01.h | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 11031744be..a356f095a6 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -17,6 +17,11 @@
 /* MMC Config*/
 #define CFG_SYS_FSL_ESDHC_ADDR 0
 
+/* default to no extra bootparams, we need an empty define for 
stringification*/
+#ifndef EXTRA_BOOTPARAMS
+#define EXTRA_BOOTPARAMS
+#endif
+
 #define CFG_EXTRA_ENV_SETTINGS \
"image=zImage\0" \
"console=ttymxc0\0" \
@@ -26,7 +31,8 @@
"mmcdev=0\0" \
"mmcpart=1\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
-   "root=/dev/mmcblk0p${mmcpart} rootwait rw\0" \
+   "root=/dev/mmcblk0p${mmcpart} rootwait rw " \
+   __stringify(EXTRA_BOOTPARAMS) "\0" \
"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \
"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \
"mmcboot=echo Booting from mmc ...; " \
-- 
2.38.1

[PATCH v6] imx: support i.MX8QM DMSSE20 a1 board

[Oliver Graute]

Add i.MX8QM DMSSE20 a1 board support

U-Boot 2023.04-00030-g7be2f547b2 (Apr 21 2023 - 11:11:43 +0200)

Model: Advantech iMX8QM DMSSE20
Board: DMS-SE20A1 8GB
Build: SCFW 549b1e18, SECO-FW c9de51c0, ATF 5782363
Boot:  USB
DRAM:  8 GiB
Core:  100 devices, 19 uclasses, devicetree: separate
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:serial@5a06
Out:   serial@5a06
Err:   serial@5a06
Net:   eth0: ethernet@5b04
Warning: ethernet@5b05 (eth1) using random MAC address - 32:05:0c:f9:5e:10
, eth1: ethernet@5b05
Hit any key to stop autoboot:  0

Signed-off-by: Oliver Graute 
---

Changes for v6
 - move environment in imx8qm_dmsse20-a1.env
 - replaced imx-atf repo url in imx8qm-dmsse20-a1.rst
 - move CONFIG_SYS_MMC_ENV_DEV to imx8qm_dmsse20a1_defconfig
 - move CONFIG_REMAKE_ELF to imx8qm_dmsse20a1_defconfig
 - move CONFIG_SPL_BSS_START_ADDR to imx8qm_dmsse20a1_defconfig
 - move CONFIG_NR_DRAM_BANKS to imx8qm_dmsse20a1_defconfig
 - move CONFIG_ENV_OVERWRITE to imx8qm_dmsse20a1_defconfig
 - move CONFIG_SUPPORT_EMMC_BOOT to imx8qm_dmsse20a1_defconfig
 - move CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG to imx8qm_dmsse20a1_defconfig
 - move CONFIG_PHY_GIGE to imx8qm_dmsse20a1_defconfig
 - move CONFIG_ENV_SECT_SIZE to imx8qm_dmsse20a1_defconfig
 - move CONFIG_SYS_MMC_ENV_PART to imx8qm_dmsse20a1_defconfig
 - move CONFIG_SYS_MEMTEST_START to imx8qm_dmsse20a1_defconfig
 - move CONFIG_SYS_MEMTEST_END to imx8qm_dmsse20a1_defconfig
 - move CONFIG_BAUDRATE to imx8qm_dmsse20a1_defconfig
 - move CONFIG_BOOTCOMMAND to imx8qm_dmsse20a1_defconfig
 - fixed implicit function declaration warning
 - replaced CONFIG_SYS_TEXT with CONFIG_TEXT_BASE
 - replaced CONFIG_SYS_FSL_ESDHC_ADDR with CFG_SYS_FSL_ESDHC_ADDR
 - replaced CONFIG_SYS_FSL_USDHC_NUM with CFG_SYS_FSL_USDHC_NUM
 - replaced CONFIG_SYS_SDRAM_BASE with CFG_SYS_SDRAM_BASE
 - replaced CONFIG_EXTRA_ENV_SETTINGS with CFG_EXTRA_ENV_SETTINGS
 - drop CONFIG_QSPI_BOOT related defines
 - drop CONFIG_FSL_FSPI related defines
 - set CONFIG_SYS_BOOTM_LEN=0x0400

Changes for v5
 - added binman support
 - fixed SPDX notations
 - fixed regulator grouping
 - drop source "board/freescale/common/Kconfig" in Kconfig
 - move CONFIG_SPL_MAX_SIZE to imx8qm_dmsse20a1_defconfig
 - move CONFIG_SPL_BSS_MAX_SIZE to imx8qm_dmsse20a1_defconfig
 - move CONFIG_SYS_INIT_SP_ADDR to imx8qm_dmsse20a1_defconfig
 - enable CONFIG_EVENT and CONFIG_DM_EVENT

Changes for v4
 - update atf fw version
 - update seco fw version
 - update scfw version
 - move CONFIG_IMX_SMMU to imx8qm_dmsse20a1_defconfig
 - move CONFIG_LOADADDR to imx8qm_dmsse20a1_defconfig
 - move CONFIG_SYS_LOAD_ADDR to imx8qm_dmsse20a1_defconfig
 - move CONFIG_SYS_MALLOC_LEN to imx8qm_dmsse20a1_defconfig
 - move CONFIG_SYS_MMC_IMG_LOAD_PART to imx8qm_dmsse20a1_defconfig
 - move CONFIG_FSL_USDHC to imx8qm_dmsse20a1_defconfig
 - replaced CONFIG_SPL_MMC_SUPPORT with CONFIG_SPL_MMC
 - replaced CONFIG_SPL_SERIAL_SUPPORT with CONFIG_SPL_SERIAL
 - drop CONFIG_FEC_XCV_TYPE

Changes for v3
 - Remove addr parameter from reset_cpu()
 - moved some configs into defconfig

Changes for v2
 - replaced bd_t with struct bd_info
 - added missing DTS in MAINTAINERS
 - replaced README with imx8qm-dmsse20-a1.rst
 - move CMD_FUSE to Kconfig
 - removed fdt_high
 - added i2c support
 - added rtc support

 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/imx8qm-dmsse20-a1.dts| 397 ++
 arch/arm/mach-imx/imx8/Kconfig|   8 +
 board/advantech/imx8qm_dmsse20_a1/Kconfig |  15 +
 board/advantech/imx8qm_dmsse20_a1/MAINTAINERS |   7 +
 board/advantech/imx8qm_dmsse20_a1/Makefile|   8 +
 .../imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env   |  48 +++
 .../imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c | 188 +
 .../advantech/imx8qm_dmsse20_a1/imximage.cfg  |  23 +
 board/advantech/imx8qm_dmsse20_a1/spl.c   | 223 ++
 common/Kconfig|   2 +-
 configs/imx8qm_dmsse20a1_defconfig| 129 ++
 doc/board/advantech/imx8qm-dmsse20-a1.rst |  58 +++
 doc/board/advantech/index.rst |   1 +
 include/configs/imx8qm_dmsse20.h  |  48 +++
 15 files changed, 1155 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/imx8qm-dmsse20-a1.dts
 create mode 100644 board/advantech/imx8qm_dmsse20_a1/Kconfig
 create mode 100644 board/advantech/imx8qm_dmsse20_a1/MAINTAINERS
 create mode 100644 board/advantech/imx8qm_dmsse20_a1/Makefile
 create mode 100644 board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env
 create mode 100644 board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c
 create mode 100644 board/advantech/imx8qm_dmsse20_a1/imximage.cfg
 create mode 100644 board/advantech/imx8qm_dmsse20_a1/spl.c
 create mode 100644 configs/imx8qm_dmsse20a1_defconfig
 create mode 100644 doc/board/advantech/imx8qm-dmsse20-a1.rst
 create mode 100644 include/configs/imx8qm_dmsse20.h

diff --git 

Re: [PATCH 1/2] firmware: zynqmp: Mask expected and show unexpected warning

[Michal Simek]

On 4/21/23 11:56, Stefan Herbrechtsmeier wrote:

Hi Michal,

Am 20.04.2023 um 14:39 schrieb Michal Simek:


On 4/20/23 14:30, Stefan Herbrechtsmeier wrote:

Am 20.04.2023 um 14:11 schrieb Michal Simek:

On 4/20/23 14:03, Stefan Herbrechtsmeier wrote:

Hi Michal,

Am 20.04.2023 um 13:06 schrieb Michal Simek:

Hi,

On 4/19/23 09:58, Stefan Herbrechtsmeier wrote:

Hi Michal,

Am 17.04.2023 um 12:16 schrieb Michal Simek:


On 4/3/23 15:34, Stefan Herbrechtsmeier wrote:

From: Stefan Herbrechtsmeier


Mask the expected and show the unexpected warning "No permission to
change config object" for NODE_OCM_BANK_0 because this node is
used to
detect if further zynqmp_pmufw_node function calls should be
skipped.

Signed-off-by: Stefan Herbrechtsmeier

---

  drivers/firmware/firmware-zynqmp.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/firmware/firmware-zynqmp.c
b/drivers/firmware/firmware-zynqmp.c
index dc8e3ad2b9..8435b58ef9 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -251,7 +251,7 @@ int zynqmp_pmufw_load_config_object(const void
*cfg_obj, size_t size)
 err = xilinx_pm_request(PM_SET_CONFIGURATION,
(u32)(u64)cfg_obj, 0, 0,
 0, ret_payload);
 if (err == XST_PM_NO_ACCESS) {
-   if (((u32 *)cfg_obj)[NODE_ID_LOCATION] ==
NODE_OCM_BANK_0) {
+   if (((u32 *)cfg_obj)[NODE_ID_LOCATION] !=
NODE_OCM_BANK_0) {
 printf("PMUFW:  No permission to change
config object\n");
 return err;
 }


First of all we should very likely create a macro for NODE_OCM_BANK_0
to cover that dependency that it is used in 3 different locations
which have to match.


Okay, I will add a PMUFW_CFG_OBJ_SUPPORT_NODE macro.


The second is the change you have in 2/2 should be the part of this
patch because when only 1/2 is applied you change behavior.


The patches should be independent, and the behavior change is
intended.
The message should be printed if you don’t heave the permission for a
specific config object and not if the driver checks for support of
config objects. The NODE_OCM_BANK_0 call should never fail if load of
config objects is supported.


And changes in 2/2 makes sense.

I would be even fine to move skip_config out of zynqmp_pmufw_node()


The zynqmp_pmufw_node() function doesn't return an error and the
skip_config variable is static inside the function.


and setting up skip_config value directly in zynqmp_power_probe() not
to check in every call.


We still need to check the skip_config variable inside
zynqmp_pmufw_node
to skip the load of the config object if the pmufw doesn't support it.



 85 if (ret == XST_PM_NO_ACCESS && id == NODE_OCM_BANK_0)
 86 skip_config = true;


Without testing on HW I though to change it like this that skip_config
is configured and checked only once at probe time.

What do you think?


Patch looks okay except the printf. Is this really necessary? Could we
use a debug instead?


It is feature which you need to explicitly enable in PMUFW to work.


Is this information really necessary for a production build?


For production build no. But there are other messages which are likely not 
needed. Like a silicon version (production is only one version) for example.


Could we use log_info instead of printf?


That should be fine that you can filter it out if you like.




It means having information in boot log is quite worth.


Either we should print a message in any case or only if the feature is
disabled because in this case the zynqmp_pmufw_node() is a nop.


By default that feature should be disabled in standard pmufw build.
I don't have a preference but I want to see that message only once, disabled 
or enabled.


Is it possible to call the zynqmp_pmufw_node() in the probe() for the other 
platforms?


Not sure what you mean by other platforms.
If you mean different xilinx SoCs then no.
If you mean other then SOM. You can enable that feature and use it but it is 
only tested and enabled by default on SOMs.




Actually maybe even we should create variable based on it to be able
to use it in scripts.
Because it is everybody decision if you want to let OS to send that
config fragments to PMUFW or just close that doors (right now you can
do it via command).

Also thinking that by default that skip_config should be false by
default and only enable it before calling that OCM. Or just change the
name to enable_config to be able to place it to bss section.


The skip_config is false by default and the function is called by the
probe as first user.


It should be but question is if it is in all cases. At least you can disable 
power domain driver and then first call can be via command.


We should call the zynqmp_pmufw_node() in probe() for all platforms to enable / 
disable the feature.


as above. Please explain what you mean by all platforms.
And it is called from 

Re: [PATCH 1/2] firmware: zynqmp: Mask expected and show unexpected warning

[Stefan Herbrechtsmeier]

Hi Michal,

Am 20.04.2023 um 14:39 schrieb Michal Simek:


On 4/20/23 14:30, Stefan Herbrechtsmeier wrote:

Am 20.04.2023 um 14:11 schrieb Michal Simek:

On 4/20/23 14:03, Stefan Herbrechtsmeier wrote:

Hi Michal,

Am 20.04.2023 um 13:06 schrieb Michal Simek:

Hi,

On 4/19/23 09:58, Stefan Herbrechtsmeier wrote:

Hi Michal,

Am 17.04.2023 um 12:16 schrieb Michal Simek:


On 4/3/23 15:34, Stefan Herbrechtsmeier wrote:

From: Stefan Herbrechtsmeier


Mask the expected and show the unexpected warning "No 
permission to

change config object" for NODE_OCM_BANK_0 because this node is
used to
detect if further zynqmp_pmufw_node function calls should be
skipped.

Signed-off-by: Stefan Herbrechtsmeier

---

  drivers/firmware/firmware-zynqmp.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/firmware/firmware-zynqmp.c
b/drivers/firmware/firmware-zynqmp.c
index dc8e3ad2b9..8435b58ef9 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -251,7 +251,7 @@ int zynqmp_pmufw_load_config_object(const void
*cfg_obj, size_t size)
 err = xilinx_pm_request(PM_SET_CONFIGURATION,
(u32)(u64)cfg_obj, 0, 0,
 0, ret_payload);
 if (err == XST_PM_NO_ACCESS) {
-   if (((u32 *)cfg_obj)[NODE_ID_LOCATION] ==
NODE_OCM_BANK_0) {
+   if (((u32 *)cfg_obj)[NODE_ID_LOCATION] !=
NODE_OCM_BANK_0) {
 printf("PMUFW:  No permission to change
config object\n");
 return err;
 }


First of all we should very likely create a macro for 
NODE_OCM_BANK_0

to cover that dependency that it is used in 3 different locations
which have to match.


Okay, I will add a PMUFW_CFG_OBJ_SUPPORT_NODE macro.


The second is the change you have in 2/2 should be the part of this
patch because when only 1/2 is applied you change behavior.


The patches should be independent, and the behavior change is
intended.
The message should be printed if you don’t heave the permission 
for a

specific config object and not if the driver checks for support of
config objects. The NODE_OCM_BANK_0 call should never fail if 
load of

config objects is supported.


And changes in 2/2 makes sense.

I would be even fine to move skip_config out of zynqmp_pmufw_node()


The zynqmp_pmufw_node() function doesn't return an error and the
skip_config variable is static inside the function.

and setting up skip_config value directly in 
zynqmp_power_probe() not

to check in every call.


We still need to check the skip_config variable inside
zynqmp_pmufw_node
to skip the load of the config object if the pmufw doesn't 
support it.




 85 if (ret == XST_PM_NO_ACCESS && id == NODE_OCM_BANK_0)
 86 skip_config = true;


Without testing on HW I though to change it like this that 
skip_config

is configured and checked only once at probe time.

What do you think?


Patch looks okay except the printf. Is this really necessary? Could we
use a debug instead?


It is feature which you need to explicitly enable in PMUFW to work.


Is this information really necessary for a production build?


For production build no. But there are other messages which are likely 
not needed. Like a silicon version (production is only one version) 
for example.


Could we use log_info instead of printf?


It means having information in boot log is quite worth.


Either we should print a message in any case or only if the feature is
disabled because in this case the zynqmp_pmufw_node() is a nop.


By default that feature should be disabled in standard pmufw build.
I don't have a preference but I want to see that message only once, 
disabled or enabled.


Is it possible to call the zynqmp_pmufw_node() in the probe() for the 
other platforms?



Actually maybe even we should create variable based on it to be able
to use it in scripts.
Because it is everybody decision if you want to let OS to send that
config fragments to PMUFW or just close that doors (right now you can
do it via command).

Also thinking that by default that skip_config should be false by
default and only enable it before calling that OCM. Or just change the
name to enable_config to be able to place it to bss section.


The skip_config is false by default and the function is called by the
probe as first user.


It should be but question is if it is in all cases. At least you can 
disable power domain driver and then first call can be via command.


We should call the zynqmp_pmufw_node() in probe() for all platforms to 
enable / disable the feature.


I have test your changes and they works.

Regards
  Stefan

Re: [PATCH 7/7] configs: rock5b-rk3588: add pci drivers and command

[Kever Yang]

Hi Eugen,

On 2023/4/17 17:19, Eugen Hristev wrote:

Add drivers for pciE , phy, and command.

Signed-off-by: Eugen Hristev 
---
  configs/rock5b-rk3588_defconfig | 6 +-
  1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 8c097ab3a109..a14fcd2ee924 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -47,6 +47,7 @@ CONFIG_SPL_ATF=y
  CONFIG_CMD_GPIO=y
  CONFIG_CMD_GPT=y
  CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
  CONFIG_CMD_SPI=y
  CONFIG_CMD_USB=y
  # CONFIG_CMD_SETEXPR is not set
@@ -71,7 +72,10 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y
  CONFIG_SPI_FLASH_MACRONIX=y
  CONFIG_ETH_DESIGNWARE=y
  CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
  CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y

Does this board have pcie2 interface and need to enable in U-Boot?

  CONFIG_SPL_PINCTRL=y
  CONFIG_REGULATOR_PWM=y
  CONFIG_DM_REGULATOR_FIXED=y
@@ -81,7 +85,6 @@ CONFIG_BAUDRATE=150
  CONFIG_DEBUG_UART_SHIFT=2
  CONFIG_ROCKCHIP_SFC=y
  CONFIG_SYSRESET=y
-# CONFIG_BINMAN_FDT is not set
  CONFIG_USB=y
  CONFIG_USB_EHCI_HCD=y
  CONFIG_USB_EHCI_GENERIC=y
@@ -95,4 +98,5 @@ CONFIG_USB_ETHER_LAN78XX=y
  CONFIG_USB_ETHER_MCS7830=y
  CONFIG_USB_ETHER_RTL8152=y
  CONFIG_USB_ETHER_SMSC95XX=y
+# CONFIG_BINMAN_FDT is not set


This should have been removed after [1]

Thanks,

- Kever

[1]https://patchwork.ozlabs.org/project/uboot/patch/20230417190708.1982556-2-jo...@kwiboo.se/


  CONFIG_ERRNO_STR=y

Re: [PATCH 5/7] ARM: dts: rockchip: rk3588s-u-boot: add pcie2x1l2 with PHY

[Kever Yang]

On 2023/4/17 17:19, Eugen Hristev wrote:

From: Joseph Chen 

Add the node for pciE 2x1l 2 device together with the corresponding
combphy.

Signed-off-by: Joseph Chen 
[eugen.hris...@collabora.com: moved to -u-boot.dtsi, minor
adaptations]
Signed-off-by: Eugen Hristev 
---
  arch/arm/dts/rk3588s-u-boot.dtsi | 73 
  1 file changed, 73 insertions(+)

diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index f23112bf7ab6..17348c8f9789 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -4,6 +4,7 @@
   */
  
  #include "rockchip-u-boot.dtsi"

+#include 
  
  / {

dmc {
@@ -58,6 +59,11 @@
reg = <0x0 0xfd58a000 0x0 0x2000>;
};
  
+	pipe_phy0_grf: syscon@fd5bc000 {

+   compatible = "rockchip,pipe-phy-grf", "syscon";
+   reg = <0x0 0xfd5bc000 0x0 0x100>;
+   };
+
usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
 "simple-mfd";
@@ -104,6 +110,58 @@
};
};
  
+	pcie2x1l2: pcie@fe19 {

+   compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";


The mainline kernel should have this node, we should sync with kernel?


Thanks,

- Kever


+   #address-cells = <3>;
+   #size-cells = <2>;
+   bus-range = <0x40 0x4f>;
+   clocks = < ACLK_PCIE_1L2_MSTR>, < ACLK_PCIE_1L2_SLV>,
+< ACLK_PCIE_1L2_DBI>, < PCLK_PCIE_1L2>,
+< CLK_PCIE_AUX4>;
+   clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk", "aux";
+   device_type = "pci";
+   interrupts = ,
+,
+,
+,
+;
+   interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1 _intc 0>,
+   <0 0 0 2 _intc 1>,
+   <0 0 0 3 _intc 2>,
+   <0 0 0 4 _intc 3>;
+   linux,pci-domain = <4>;
+   num-ib-windows = <8>;
+   num-ob-windows = <8>;
+   max-link-speed = <2>;
+   msi-map = <0x4000  0x4000 0x1000>;
+   num-lanes = <1>;
+   phys = <_ps PHY_TYPE_PCIE>;
+   phy-names = "pcie-phy";
+   power-domains = < RK3588_PD_PHP>;
+   ranges = <0x0800 0x0 0xf400 0x0 0xf400 0x0 0x10
+ 0x8100 0x0 0xf410 0x0 0xf410 0x0 0x10
+ 0x8200 0x0 0xf420 0x0 0xf420 0x0 0xe0
+ 0xc300 0xa 0x 0xa 0x 0x0 
0x4000>;
+   reg = <0xa 0x4100 0x0 0x40>,
+ <0x0 0xfe19 0x0 0x1>;
+   reg-names = "pcie-dbi", "pcie-apb";
+   resets = < SRST_PCIE4_POWER_UP>;
+   reset-names = "pipe";
+   status = "disabled";
+
+   pcie2x1l2_intc: legacy-interrupt-controller {
+   interrupt-controller;
+   #address-cells = <0>;
+   #interrupt-cells = <1>;
+   interrupt-parent = <>;
+   interrupts = ;
+   };
+   };
+
sfc: spi@fe2b {
compatible = "rockchip,sfc";
reg = <0x0 0xfe2b 0x0 0x4000>;
@@ -128,6 +186,21 @@
reg = <0x07 0x10>;
};
};
+
+   combphy0_ps: phy@fee0 {
+   compatible = "rockchip,rk3588-naneng-combphy";
+   reg = <0x0 0xfee0 0x0 0x100>;
+   #phy-cells = <1>;
+   clocks = < CLK_REF_PIPE_PHY0>, < 
PCLK_PCIE_COMBO_PIPE_PHY0>;
+   clock-names = "refclk", "apbclk";
+   assigned-clocks = < CLK_REF_PIPE_PHY0>;
+   assigned-clock-rates = <1>;
+   resets = < SRST_P_PCIE2_PHY0>, < SRST_REF_PIPE_PHY0>;
+   reset-names = "combphy-apb", "combphy";
+   rockchip,pipe-grf = <_grf>;
+   rockchip,pipe-phy-grf = <_phy0_grf>;
+   status = "disabled";
+   };
  };
  
   {

Re: [PATCH 3/7] phy: rockchip: naneng-combphy: Add support for multiple resets

[Kever Yang]

On 2023/4/17 17:19, Eugen Hristev wrote:

Some variants of the PHY have more than just one reset.
To cover all cases, request the rests in bulk rather than just
the reset at index 0.

Co-developed-by: Ren Jianing 
Signed-off-by: Ren Jianing 
Signed-off-by: Eugen Hristev 

Reviewed-by: Kever Yang 

Thanks,
- Kever


---
  drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 8 
  1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c 
b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index 78da5fe79700..b673a8da9f8e 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -76,7 +76,7 @@ struct rockchip_combphy_priv {
struct regmap *pipe_grf;
struct regmap *phy_grf;
struct phy *phy;
-   struct reset_ctl phy_rst;
+   struct reset_ctl_bulk phy_rsts;
struct clk ref_clk;
const struct rockchip_combphy_cfg *cfg;
  };
@@ -189,7 +189,7 @@ static int rockchip_combphy_init(struct phy *phy)
if (ret)
goto err_clk;
  
-	reset_deassert(>phy_rst);

+   reset_deassert_bulk(>phy_rsts);
  
  	return 0;
  
@@ -204,7 +204,7 @@ static int rockchip_combphy_exit(struct phy *phy)

struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
  
  	clk_disable(>ref_clk);

-   reset_assert(>phy_rst);
+   reset_assert_bulk(>phy_rsts);
  
  	return 0;

  }
@@ -255,7 +255,7 @@ static int rockchip_combphy_parse_dt(struct udevice *dev,
return PTR_ERR(>ref_clk);
}
  
-	ret = reset_get_by_index(dev, 0, >phy_rst);

+   ret = reset_get_bulk(dev, >phy_rsts);
if (ret) {
dev_err(dev, "no phy reset control specified\n");
return ret;

Re: [PATCH 4/7] phy: rockchip: naneng-combphy: Support rk3588

[Kever Yang]

On 2023/4/17 17:19, Eugen Hristev wrote:

From: Jon Lin 

Add support for rk3588 phy variant.
The PHY clock is fixed at 100MHz.

Signed-off-by: Jon Lin 
[kever.y...@rock-chips.com: update pcie pll parameters]
Co-developed-by: Kever Yang 
Signed-off-by: Kever Yang 
[eugen.hris...@collabora.com: squashed, tidy up]
Signed-off-by: Eugen Hristev 

Reviewed-by: Kever Yang 

Thanks,
- Kever


---
  .../rockchip/phy-rockchip-naneng-combphy.c| 95 +++
  1 file changed, 95 insertions(+)

diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c 
b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index b673a8da9f8e..d5408ccac976 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -58,6 +58,7 @@ struct rockchip_combphy_grfcfg {
struct combphy_reg con2_for_sata;
struct combphy_reg con3_for_sata;
struct combphy_reg pipe_con0_for_sata;
+   struct combphy_reg pipe_con1_for_sata;
struct combphy_reg pipe_sgmii_mac_sel;
struct combphy_reg pipe_xpcs_phy_ready;
struct combphy_reg u3otg0_port_en;
@@ -423,11 +424,105 @@ static const struct rockchip_combphy_cfg 
rk3568_combphy_cfgs = {
.combphy_cfg= rk3568_combphy_cfg,
  };
  
+static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)

+{
+   const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+   u32 val;
+
+   switch (priv->mode) {
+   case PHY_TYPE_PCIE:
+   param_write(priv->phy_grf, >con0_for_pcie, true);
+   param_write(priv->phy_grf, >con1_for_pcie, true);
+   param_write(priv->phy_grf, >con2_for_pcie, true);
+   param_write(priv->phy_grf, >con3_for_pcie, true);
+   break;
+   case PHY_TYPE_USB3:
+   param_write(priv->phy_grf, >pipe_txcomp_sel, false);
+   param_write(priv->phy_grf, >pipe_txelec_sel, false);
+   param_write(priv->phy_grf, >usb_mode_set, true);
+   break;
+   case PHY_TYPE_SATA:
+   param_write(priv->phy_grf, >con0_for_sata, true);
+   param_write(priv->phy_grf, >con1_for_sata, true);
+   param_write(priv->phy_grf, >con2_for_sata, true);
+   param_write(priv->phy_grf, >con3_for_sata, true);
+   param_write(priv->pipe_grf, >pipe_con0_for_sata, true);
+   param_write(priv->pipe_grf, >pipe_con1_for_sata, true);
+   break;
+   case PHY_TYPE_SGMII:
+   case PHY_TYPE_QSGMII:
+   default:
+   dev_err(priv->dev, "incompatible PHY type\n");
+   return -EINVAL;
+   }
+
+   /* 100MHz refclock signal is good */
+   clk_set_rate(>ref_clk, 1);
+   param_write(priv->phy_grf, >pipe_clk_100m, true);
+   if (priv->mode == PHY_TYPE_PCIE) {
+   /* PLL KVCO tuning fine */
+   val = readl(priv->mmio + (0x20 << 2));
+   val &= ~GENMASK(4, 2);
+   val |= 0x4 << 2;
+   writel(val, priv->mmio + (0x20 << 2));
+
+   /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
+   val = 0x4c;
+   writel(val, priv->mmio + (0x1b << 2));
+
+   /* Set up su_trim: T3 */
+   val = 0xb0;
+   writel(val, priv->mmio + (0xa << 2));
+   val = 0x47;
+   writel(val, priv->mmio + (0xb << 2));
+   val = 0x57;
+   writel(val, priv->mmio + (0xd << 2));
+   }
+
+   return 0;
+}
+
+static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
+   /* pipe-phy-grf */
+   .pcie_mode_set  = { 0x, 5, 0, 0x00, 0x11 },
+   .usb_mode_set   = { 0x, 5, 0, 0x00, 0x04 },
+   .pipe_rxterm_set= { 0x, 12, 12, 0x00, 0x01 },
+   .pipe_txelec_set= { 0x0004, 1, 1, 0x00, 0x01 },
+   .pipe_txcomp_set= { 0x0004, 4, 4, 0x00, 0x01 },
+   .pipe_clk_25m   = { 0x0004, 14, 13, 0x00, 0x01 },
+   .pipe_clk_100m  = { 0x0004, 14, 13, 0x00, 0x02 },
+   .pipe_rxterm_sel= { 0x0008, 8, 8, 0x00, 0x01 },
+   .pipe_txelec_sel= { 0x0008, 12, 12, 0x00, 0x01 },
+   .pipe_txcomp_sel= { 0x0008, 15, 15, 0x00, 0x01 },
+   .pipe_clk_ext   = { 0x000c, 9, 8, 0x02, 0x01 },
+   .pipe_phy_status= { 0x0034, 6, 6, 0x01, 0x00 },
+   .con0_for_pcie  = { 0x, 15, 0, 0x00, 0x1000 },
+   .con1_for_pcie  = { 0x0004, 15, 0, 0x00, 0x },
+   .con2_for_pcie  = { 0x0008, 15, 0, 0x00, 0x0101 },
+   .con3_for_pcie  = { 0x000c, 15, 0, 0x00, 0x0200 },
+   .con0_for_sata  = { 0x, 15, 0, 0x00, 0x0129 },
+   .con1_for_sata  = { 0x0004, 15, 0, 0x00, 0x0040 },
+   .con2_for_sata  = { 0x0008, 15, 0, 0x00, 0x80c1 },
+   .con3_for_sata  = { 0x000c, 15, 0, 0x00, 0x0407 },
+   

Re: [PATCH 1/7] pci: pcie_dw_rockchip: Add rk3588 compatible

[Kever Yang]

On 2023/4/17 17:19, Eugen Hristev wrote:

From: Jon Lin 

Add compatible for RK3588 SoC.

Signed-off-by: Jon Lin 

Reviewed-by: Kever Yang 

Thanks,
- Kever


---
  drivers/pci/pcie_dw_rockchip.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 6155710a9f5f..ff121046604a 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -468,6 +468,7 @@ static const struct dm_pci_ops rockchip_pcie_ops = {
  
  static const struct udevice_id rockchip_pcie_ids[] = {

{ .compatible = "rockchip,rk3568-pcie" },
+   { .compatible = "rockchip,rk3588-pcie" },
{ }
  };
  

Re: [PATCH v11 09/10] arm_ffa: efi: introduce FF-A MM communication

[Ilias Apalodimas]

Hi Abdellatif,

[...]

>
> @@ -162,7 +450,16 @@ static efi_status_t mm_communicate(u8 *comm_buf, 
> efi_uintn_t dsize)
>   mm_hdr = (struct efi_mm_communicate_header *)comm_buf;
>   var_hdr = (struct smm_variable_communicate_header *)mm_hdr->data;
>
> - ret = optee_mm_communicate(comm_buf, dsize);
> + mm_comms = select_mm_comms();

switch()/case probably looks more readable here

> + if (mm_comms == MM_COMMS_UNDEFINED) {
> + ret = EFI_UNSUPPORTED;
> + } else {
> + if (mm_comms == MM_COMMS_OPTEE)
> + ret = optee_mm_communicate(comm_buf, dsize);
> + else
> + ret = ffa_mm_communicate(comm_buf, dsize);
> + }
> +
>   if (ret != EFI_SUCCESS) {
>   log_err("%s failed!\n", __func__);
>   return ret;
> @@ -258,6 +555,13 @@ efi_status_t EFIAPI get_max_payload(efi_uintn_t *size)
>   goto out;
>   }
>   *size = var_payload->size;
> +
> + #if (IS_ENABLED(CONFIG_ARM_FFA_TRANSPORT))
> + if (*size > FFA_SHARED_MM_BUFFER_SIZE)
> + *size = FFA_SHARED_MM_BUFFER_SIZE - 
> MM_COMMUNICATE_HEADER_SIZE  -
> + MM_VARIABLE_COMMUNICATE_SIZE;
> + #endif
> +
>   /*
>* There seems to be a bug in EDK2 miscalculating the boundaries and
>* size checks, so deduct 2 more bytes to fulfill this requirement. Fix
> @@ -697,7 +1001,7 @@ void efi_variables_boot_exit_notify(void)
>   ret = EFI_NOT_FOUND;
>
>   if (ret != EFI_SUCCESS)
> - log_err("Unable to notify StMM for ExitBootServices\n");
> + log_err("Unable to notify the MM partition for 
> ExitBootServices\n");
>   free(comm_buf);
>
>   /*
> --
> 2.25.1
>

Thanks
/Ilias

Re: [PATCH v2 4/4] configs: rockchip: radxa-cm3-io: drop CONFIG_USB_DWC3_GENERIC

[Kever Yang]

On 2023/4/20 20:00, FUKAUMI Naoki wrote:

it's not used by rk35xx

Signed-off-by: FUKAUMI Naoki 

Reviewed-by: Kever Yang 

Thanks,
- Kever


---
v2:
- new patch

  configs/radxa-cm3-io-rk3566_defconfig | 1 -
  1 file changed, 1 deletion(-)

diff --git a/configs/radxa-cm3-io-rk3566_defconfig 
b/configs/radxa-cm3-io-rk3566_defconfig
index 9b99181714..1df9cab79d 100644
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -77,5 +77,4 @@ CONFIG_USB_XHCI_DWC3=y
  CONFIG_USB_EHCI_HCD=y
  CONFIG_USB_EHCI_GENERIC=y
  CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
  CONFIG_ERRNO_STR=y

Re: [PATCH v2 1/4] configs: rockchip: rock-3a: make usb host work

[Kever Yang]

On 2023/4/20 20:00, FUKAUMI Naoki wrote:

add support for USB host function on ROCK 3A

Signed-off-by: FUKAUMI Naoki 

Reviewed-by: Kever Yang 

Thanks,
- Kever


---
v2:
- drop CONFIG_USB_DWC3_GENERIC

  configs/rock-3a-rk3568_defconfig | 11 +++
  1 file changed, 11 insertions(+)

diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index e753832183..16a8b6092c 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -39,6 +39,7 @@ CONFIG_SPL_ATF=y
  CONFIG_CMD_GPT=y
  CONFIG_CMD_I2C=y
  CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
  # CONFIG_CMD_SETEXPR is not set
  # CONFIG_SPL_DOS_PARTITION is not set
  CONFIG_SPL_OF_CONTROL=y
@@ -58,6 +59,8 @@ CONFIG_MMC_SDHCI_SDMA=y
  CONFIG_MMC_SDHCI_ROCKCHIP=y
  CONFIG_ETH_DESIGNWARE=y
  CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
  CONFIG_DM_PMIC=y
  CONFIG_PMIC_RK8XX=y
  CONFIG_SPL_PMIC_RK8XX=y
@@ -69,5 +72,13 @@ CONFIG_BAUDRATE=150
  CONFIG_DEBUG_UART_SHIFT=2
  CONFIG_SYS_NS16550_MEM32=y
  CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
  # CONFIG_BINMAN_FDT is not set
  CONFIG_ERRNO_STR=y

Re: [PATCH v3 08/10] pinctrl: rockchip: Fix IO mux selection on RK3568

[Kever Yang]

On 2023/4/18 03:07, Jonas Karlman wrote:

IO mux selection is not working correctly for all pins. Sync mux route
data from linux to add any missing and update wrong trigger pins to fix
this. Also apply the pull-up fix needed for GPIO0 D3-D6.

Fixes: 1977d746aa54 ("rockchip: rk3568: add rk3568 pinctrl driver")
Signed-off-by: Jonas Karlman 



Reviewed-by: Kever Yang 

Thanks,
- Kever


---
v3:
- Patch picked from [1]

[1] 
https://patchwork.ozlabs.org/project/uboot/patch/20230318233039.799975-1-jo...@kwiboo.se/

  drivers/pinctrl/rockchip/pinctrl-rk3568.c | 66 +--
  1 file changed, 38 insertions(+), 28 deletions(-)

diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c 
b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
index 935aed9efc62..314edb5a6064 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3568.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
@@ -13,6 +13,12 @@
  #include "pinctrl-rockchip.h"
  
  static struct rockchip_mux_route_data rk3568_mux_route_data[] = {

+   MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(1, 0, 
0)), /* PWM0 IO mux selection M0 */
+   MR_PMUGRF(RK_GPIO0, RK_PC7, RK_FUNC_2, 0x0110, RK_GENMASK_VAL(1, 0, 
1)), /* PWM0 IO mux selection M1 */
+   MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(3, 2, 
0)), /* PWM1 IO mux selection M0 */
+   MR_PMUGRF(RK_GPIO0, RK_PB5, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(3, 2, 
1)), /* PWM1 IO mux selection M1 */
+   MR_PMUGRF(RK_GPIO0, RK_PC1, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(5, 4, 
0)), /* PWM2 IO mux selection M0 */
+   MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(5, 4, 
1)), /* PWM2 IO mux selection M1 */
MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 
0)), /* CAN0 IO mux selection M0 */
MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 
1)), /* CAN0 IO mux selection M1 */
MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 
0)), /* CAN1 IO mux selection M0 */
@@ -33,30 +39,22 @@ static struct rockchip_mux_route_data 
rk3568_mux_route_data[] = {
MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 
1)), /* I2C4 IO mux selection M1 */
MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 
0)), /* I2C5 IO mux selection M0 */
MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 
1)), /* I2C5 IO mux selection M1 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 
0)), /* PWM4 IO mux selection M0 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 
1)), /* PWM4 IO mux selection M1 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 
0)), /* PWM5 IO mux selection M0 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 
1)), /* PWM5 IO mux selection M1 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 
0)), /* PWM6 IO mux selection M0 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 
1)), /* PWM6 IO mux selection M1 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 
0)), /* PWM7 IO mux selection M0 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 
1)), /* PWM7 IO mux selection M1 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 
0)), /* PWM8 IO mux selection M0 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 
1)), /* PWM8 IO mux selection M1 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 
0)), /* PWM9 IO mux selection M0 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 
1)), /* PWM9 IO mux selection M1 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 
0)), /* PWM10 IO mux selection M0 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 
1)), /* PWM10 IO mux selection M1 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 
0)), /* PWM11 IO mux selection M0 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 
1)), /* PWM11 IO mux selection M1 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 
0)), /* PWM12 IO mux selection M0 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 
1)), /* PWM12 IO mux selection M1 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 
0)), /* PWM13 IO mux selection M0 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 
1)), /* PWM13 IO mux selection M1 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 
0)), /* PWM14 IO mux selection M0 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 
1)), /* PWM14 IO mux selection M1 */
-   MR_TOPGRF(RK_GPIO3, RK_PD2, 

[PATCH v3 3/3] extcon: add MAX14526 MUIC support

[Svyatoslav Ryhel]

MAX14526 is a powerful extcon chip which allows detection of various
plugs like usb, mhl, uart, headset etc. This version of driver
implements support of AP-usb and CP-usb/uart paths.

Tested-by: Andreas Westman Dorcsak  # LG P880 T30
Tested-by: Svyatoslav Ryhel  # LG P895 T30
Signed-off-by: Svyatoslav Ryhel 
---
 drivers/extcon/Kconfig   |   9 ++
 drivers/extcon/Makefile  |   1 +
 drivers/extcon/extcon-max14526.c | 151 +++
 3 files changed, 161 insertions(+)
 create mode 100644 drivers/extcon/extcon-max14526.c

diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig
index 6fd3d2b97b..fbb73354aa 100644
--- a/drivers/extcon/Kconfig
+++ b/drivers/extcon/Kconfig
@@ -19,4 +19,13 @@ config EXTCON_SANDBOX
  Enable extcon support for sandbox. This is an emulation of a real
  extcon. Currectly all configuration is done in the probe.
 
+config EXTCON_MAX14526
+   bool "Maxim MAX14526 EXTCON Support"
+   depends on DM_I2C
+   depends on EXTCON
+   help
+ If you say yes here you get support for the MUIC device of
+ Maxim MAX14526. The MAX14526 MUIC is a USB port accessory
+ detector and switch.
+
 endmenu
diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile
index c4223d97d1..3309f2aac2 100644
--- a/drivers/extcon/Makefile
+++ b/drivers/extcon/Makefile
@@ -4,3 +4,4 @@
 
 obj-$(CONFIG_EXTCON) += extcon-uclass.o
 obj-$(CONFIG_EXTCON_SANDBOX) += extcon-sandbox.o
+obj-$(CONFIG_EXTCON_MAX14526) += extcon-max14526.o
diff --git a/drivers/extcon/extcon-max14526.c b/drivers/extcon/extcon-max14526.c
new file mode 100644
index 00..a33b5ef919
--- /dev/null
+++ b/drivers/extcon/extcon-max14526.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Svyatoslav Ryhel 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CONTROL_1  0x01
+#define SW_CONTROL 0x03
+
+#define ID_200 0x10
+#define ADC_EN 0x02
+#define CP_EN  0x01
+
+#define DP_USB 0x00
+#define DP_UART0x08
+#define DP_AUDIO   0x10
+#define DP_OPEN0x38
+
+#define DM_USB 0x00
+#define DM_UART0x01
+#define DM_AUDIO   0x02
+#define DM_OPEN0x07
+
+#define AP_USB BIT(0)
+#define CP_USB BIT(1)
+#define CP_UARTBIT(2)
+
+struct max14526_priv {
+   struct gpio_desc usif_gpio;
+   struct gpio_desc dp2t_gpio;
+   struct gpio_desc ifx_usb_vbus_gpio;
+};
+
+static void max14526_set_mode(struct udevice *dev, int mode)
+{
+   struct max14526_priv *priv = dev_get_priv(dev);
+   int ret;
+
+   if ((mode & AP_USB) || (mode & CP_USB)) {
+   /* Connect CP UART signals to AP */
+   ret = dm_gpio_set_value(>usif_gpio, 0);
+   if (ret)
+   log_debug("cp-uart > ap failed (%d)\n", ret);
+   }
+
+   if (mode & CP_UART) {
+   /* Connect CP UART signals to DP2T */
+   ret = dm_gpio_set_value(>usif_gpio, 1);
+   if (ret)
+   log_debug("cp-uart > dp2t failed (%d)\n", ret);
+   }
+
+   if (mode & CP_USB) {
+   /* Connect CP USB to MUIC UART */
+   ret = dm_gpio_set_value(>ifx_usb_vbus_gpio, 1);
+   if (ret)
+   log_debug("usb-vbus-gpio enable failed (%d)\n", ret);
+
+   ret = dm_gpio_set_value(>dp2t_gpio, 1);
+   if (ret)
+   log_debug("cp-usb > muic-uart failed (%d)\n", ret);
+   }
+
+   if ((mode & AP_USB) || (mode & CP_UART)) {
+   /* Connect CP UART to MUIC UART */
+   ret = dm_gpio_set_value(>dp2t_gpio, 0);
+   if (ret)
+   log_debug("cp-uart > muic-uart failed (%d)\n", ret);
+   }
+
+   if (mode & AP_USB) {
+   /* Enables USB Path */
+   ret = dm_i2c_reg_write(dev, SW_CONTROL, DP_USB | DM_USB);
+   if (ret)
+   log_debug("USB path set failed: %d\n", ret);
+   }
+
+   if ((mode & CP_USB) || (mode & CP_UART)) {
+   /* Enables UART Path */
+   ret = dm_i2c_reg_write(dev, SW_CONTROL, DP_UART | DM_UART);
+   if (ret)
+   log_debug("UART path set failed: %d\n", ret);
+   }
+
+   /* Enables 200K, Charger Pump, and ADC */
+   ret = dm_i2c_reg_write(dev, CONTROL_1, ID_200 | ADC_EN | CP_EN);
+   if (ret)
+   log_debug("200K, Charger Pump, and ADC set failed: %d\n", ret);
+}
+
+static int max14526_probe(struct udevice *dev)
+{
+   struct max14526_priv *priv = dev_get_priv(dev);
+   int ret, mode = 0;
+
+   ret = gpio_request_by_name(dev, "usif-gpios", 0,
+  >usif_gpio, GPIOD_IS_OUT);
+   if (ret) {
+   log_err("could not decode 

[PATCH v3 2/3] test: Add tests for the extcon

[Svyatoslav Ryhel]

Provide tests to the simple extcon device.

Signed-off-by: Svyatoslav Ryhel 
---
 arch/sandbox/dts/test.dts   |  4 
 drivers/extcon/Kconfig  |  7 +++
 drivers/extcon/Makefile |  1 +
 drivers/extcon/extcon-sandbox.c | 17 +
 test/dm/Makefile|  1 +
 test/dm/extcon.c| 21 +
 6 files changed, 51 insertions(+)
 create mode 100644 drivers/extcon/extcon-sandbox.c
 create mode 100644 test/dm/extcon.c

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 7c1ee71cb7..731b48459d 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -1802,6 +1802,10 @@
compatible = "u-boot,fwu-mdata-gpt";
fwu-mdata-store = <>;
};
+
+   extcon {
+   compatible = "sandbox,extcon";
+   };
 };
 
 #include "sandbox_pmic.dtsi"
diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig
index 8a50250d21..6fd3d2b97b 100644
--- a/drivers/extcon/Kconfig
+++ b/drivers/extcon/Kconfig
@@ -12,4 +12,11 @@ config EXTCON
  and to host USB ports. Many of 30-pin connectors including PDMI
  are also good examples.
 
+config EXTCON_SANDBOX
+   bool "Sandbox extcon"
+   depends on EXTCON
+   help
+ Enable extcon support for sandbox. This is an emulation of a real
+ extcon. Currectly all configuration is done in the probe.
+
 endmenu
diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile
index 2510e91c07..c4223d97d1 100644
--- a/drivers/extcon/Makefile
+++ b/drivers/extcon/Makefile
@@ -3,3 +3,4 @@
 # Copyright (C) 2023 Svyatoslav Ryhel 
 
 obj-$(CONFIG_EXTCON) += extcon-uclass.o
+obj-$(CONFIG_EXTCON_SANDBOX) += extcon-sandbox.o
diff --git a/drivers/extcon/extcon-sandbox.c b/drivers/extcon/extcon-sandbox.c
new file mode 100644
index 00..ab6a6c1cfd
--- /dev/null
+++ b/drivers/extcon/extcon-sandbox.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Svyatoslav Ryhel 
+ */
+
+#include 
+
+static const struct udevice_id sandbox_extcon_ids[] = {
+   { .compatible = "sandbox,extcon" },
+   { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(extcon_sandbox) = {
+   .name   = "extcon_sandbox",
+   .id = UCLASS_EXTCON,
+   .of_match   = sandbox_extcon_ids,
+};
diff --git a/test/dm/Makefile b/test/dm/Makefile
index e15bdbf04b..5ada659974 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_DM_DSA) += dsa.o
 obj-$(CONFIG_ECDSA_VERIFY) += ecdsa.o
 obj-$(CONFIG_EFI_MEDIA_SANDBOX) += efi_media.o
 obj-$(CONFIG_DM_ETH) += eth.o
+obj-$(CONFIG_EXTCON) += extcon.o
 ifneq ($(CONFIG_EFI_PARTITION),)
 obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fastboot.o
 endif
diff --git a/test/dm/extcon.c b/test/dm/extcon.c
new file mode 100644
index 00..6a4e22bfdc
--- /dev/null
+++ b/test/dm/extcon.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Svyatoslav Ryhel 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static int dm_test_extcon(struct unit_test_state *uts)
+{
+   struct udevice *dev;
+
+   ut_assertok(uclass_get_device_by_name(UCLASS_EXTCON, "extcon", ));
+
+   return 0;
+}
+
+DM_TEST(dm_test_extcon, UT_TESTF_SCAN_FDT);
-- 
2.37.2

[PATCH v3 1/3] dm: extcom: add an uclass for extcon

[Svyatoslav Ryhel]

Add a new simple uclass for extcon. Currently all setup is done
in the probe. Uclass struct and ops are empty for now.

Signed-off-by: Svyatoslav Ryhel 
---
 drivers/Kconfig|  2 ++
 drivers/Makefile   |  1 +
 drivers/extcon/Kconfig | 15 +++
 drivers/extcon/Makefile|  5 +
 drivers/extcon/extcon-uclass.c | 16 
 include/dm/uclass-id.h |  1 +
 include/extcon.h   | 19 +++
 7 files changed, 59 insertions(+)
 create mode 100644 drivers/extcon/Kconfig
 create mode 100644 drivers/extcon/Makefile
 create mode 100644 drivers/extcon/extcon-uclass.c
 create mode 100644 include/extcon.h

diff --git a/drivers/Kconfig b/drivers/Kconfig
index 9101e538b0..75937fbb6d 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -36,6 +36,8 @@ source "drivers/dfu/Kconfig"
 
 source "drivers/dma/Kconfig"
 
+source "drivers/extcon/Kconfig"
+
 source "drivers/fastboot/Kconfig"
 
 source "drivers/firmware/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 58be410135..ed1e71c4d6 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_$(SPL_TPL_)DM) += core/
 obj-$(CONFIG_$(SPL_TPL_)DMA) += dma/
 obj-$(CONFIG_$(SPL_TPL_)DMA_LEGACY) += dma/
 obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/
+obj-$(CONFIG_$(SPL_TPL_)EXTCON) += extcon/
 obj-$(CONFIG_$(SPL_TPL_)GPIO) += gpio/
 obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC) += misc/
 obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset/
diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig
new file mode 100644
index 00..8a50250d21
--- /dev/null
+++ b/drivers/extcon/Kconfig
@@ -0,0 +1,15 @@
+menu "Extcon Support"
+
+config EXTCON
+   bool "External Connector Class (extcon) support"
+   depends on DM
+   help
+ Say Y here to enable external connector class (extcon) support.
+ This allows monitoring external connectors and supports external
+ connectors with multiple states; i.e., an extcon that may have
+ multiple cables attached. For example, an external connector
+ of a device may be used to connect an HDMI cable and a AC adaptor,
+ and to host USB ports. Many of 30-pin connectors including PDMI
+ are also good examples.
+
+endmenu
diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile
new file mode 100644
index 00..2510e91c07
--- /dev/null
+++ b/drivers/extcon/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Svyatoslav Ryhel 
+
+obj-$(CONFIG_EXTCON) += extcon-uclass.o
diff --git a/drivers/extcon/extcon-uclass.c b/drivers/extcon/extcon-uclass.c
new file mode 100644
index 00..9dd22b5762
--- /dev/null
+++ b/drivers/extcon/extcon-uclass.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Svyatoslav Ryhel 
+ */
+
+#define LOG_CATEGORY UCLASS_EXTCON
+
+#include 
+#include 
+#include 
+
+UCLASS_DRIVER(extcon) = {
+   .id = UCLASS_EXTCON,
+   .name   = "extcon",
+   .per_device_plat_auto   = sizeof(struct extcon_uc_plat),
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 576237b954..94ab46c5ba 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -56,6 +56,7 @@ enum uclass_id {
UCLASS_EFI_MEDIA,   /* Devices provided by UEFI firmware */
UCLASS_ETH, /* Ethernet device */
UCLASS_ETH_PHY, /* Ethernet PHY device */
+   UCLASS_EXTCON,  /* External Connector Class */
UCLASS_FIRMWARE,/* Firmware */
UCLASS_FPGA,/* FPGA device */
UCLASS_FUZZING_ENGINE,  /* Fuzzing engine */
diff --git a/include/extcon.h b/include/extcon.h
new file mode 100644
index 00..d060f5a3c1
--- /dev/null
+++ b/include/extcon.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 Svyatoslav Ryhel 
+ */
+
+#ifndef __EXTCON_H
+#define __EXTCON_H
+
+struct udevice;
+
+/**
+ * struct extcon_uc_plat - Platform data the uclass stores about each device
+ *
+ * To be filled
+ */
+struct extcon_uc_plat {
+};
+
+#endif
-- 
2.37.2

[PATCH v3 0/3] Add MAX14526 MUIC driver

[Svyatoslav Ryhel]

MAX14526 MUIC is used by LG P880/P895 which are currently
in the process of merging.

MAX14526 is a powerful extcon device which has the ability to
accurately determine plugged devices. In this implementation
muic can be configured to represent 3 modes: CP-USB/UART and
AP-USB. Unfortunately AP-UART was disabled on P880/P895.
Additionally the driver configures some stuff required by
the charger.

Extcon class has empty platform struct and ops, all configuration
is performed in the probe. Filling of struct and ops is welcomed.

---
Changes from v2:
- created a new simple extcon uclass

Changes from v1:
- used log_* instead of printf
- log messages made simpler
---

Svyatoslav Ryhel (3):
  dm: extcom: add an uclass for extcon
  test: Add tests for the extcon
  extcon: add MAX14526 MUIC support

 arch/sandbox/dts/test.dts|   4 +
 drivers/Kconfig  |   2 +
 drivers/Makefile |   1 +
 drivers/extcon/Kconfig   |  31 +++
 drivers/extcon/Makefile  |   7 ++
 drivers/extcon/extcon-max14526.c | 151 +++
 drivers/extcon/extcon-sandbox.c  |  17 
 drivers/extcon/extcon-uclass.c   |  16 
 include/dm/uclass-id.h   |   1 +
 include/extcon.h |  19 
 test/dm/Makefile |   1 +
 test/dm/extcon.c |  21 +
 12 files changed, 271 insertions(+)
 create mode 100644 drivers/extcon/Kconfig
 create mode 100644 drivers/extcon/Makefile
 create mode 100644 drivers/extcon/extcon-max14526.c
 create mode 100644 drivers/extcon/extcon-sandbox.c
 create mode 100644 drivers/extcon/extcon-uclass.c
 create mode 100644 include/extcon.h
 create mode 100644 test/dm/extcon.c

-- 
2.37.2