Re: [PATCH v8 00/24] Fixes for Rockchip NFC driver part 1

[Kever Yang]

Hi Johan,

On 2023/4/21 23:34, Johan Jonker wrote:


On 4/21/23 05:15, Kever Yang wrote:

Hi Johan,

     I got below error report from CI test, I think it should be relate to this 
patch set.

=== FAILURES ===
1107 
_
 test_ut[ut_dm_dm_test_fdt_get_addr_ptr_flat] _
1108 
test/py/tests/test_ut.py:346:
 in test_ut
1109 
assert
 output.endswith('Failures: 0')
1110 
E 
AssertionError: assert False
 E 
+ where False = ('Failures: 
0')
1112 E 
+ where  = 'Test: 
dm_test_fdt_get_addr_ptr_flat: test-fdt.c (flat tree)\r\r\ntest/dm/test-fdt.c:627,

dm_test_fdt_get_addr_ptr_fla...xpected 8000, got 
10009000\r\r\nTest dm_test_fdt_get_addr_ptr_flat failed 1 
times\r\r\nFailures: 1'.endswith

It turns out that the suggestion by Simon to use map_sysmem() doesn't work with 
devfdt_get_addr_index_ptr() somehow.

To reproduce with this serie:
make sandbox_defconfig all
./u-boot -T -c "ut dm fdt*"

Test: dm_test_fdt_get_addr_ptr_flat: test-fdt.c (flat tree)
test/dm/test-fdt.c:627, dm_test_fdt_get_addr_ptr_flat(): (void *)0x8000 = ptr: 
Expected 8000, got 10009000
Test fdt* failed 1 times

===

Could Simon have a look at the internal map_sysmem() stuff?

Will send 1 patch to replace:
[PATCH v8 14/24] core: fdtaddr: add devfdt_get_addr_size_index_ptr function

for:

[PATCH v9] core: fdtaddr: add devfdt_get_addr_size_index_ptr function

Could Kever retest with the patch above replacement?


The CI test pass with this replacement.


Thanks,

- Kever

Pull request: u-boot-rockchip-20230421

[Kever Yang]

Hi Tom,

This is the first PR for rockchip platform, and still many patches are in the
list for some reason, suppose to have one more PR in next week.

Please pull the updates for rockchip platform:
- Add rk3588 evb support;
- Update pinctrl for rk3568 and rk3588;
- Update rk3288 dts;
- Update mmc support for rk3568 and rk3588;
- Add rng support for rk3588;
- Add DSI support for rk3568;
- Some other misc fixes in dts, config, driver;

CI:
https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/16071

Thanks,
- Kever

The following changes since commit 5db4972a5bbdbf9e3af48ffc9bc4fec73b7b6a79:

  Merge tag 'u-boot-nand-20230417' of 
https://source.denx.de/u-boot/custodians/u-boot-nand-flash (2023-04-17 10:47:33 
-0400)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-rockchip.git 
tags/u-boot-rockchip-20230421

for you to fetch changes up to a1c68192549246fe80a6f931986b8e9d5651cb16:

  configs: rockchip: radxa-cm3-io: drop CONFIG_USB_DWC3_GENERIC (2023-04-21 
16:09:29 +0800)


Chris Morgan (4):
  drivers: phy: add Innosilicon DSI-DPHY driver
  rockchip: video: Add support for RK3568 DSI Host
  rockchip: rng: add trngv1 for rk3588
  ARM: dts: rockchip: rk3588s-u-boot: Add rng node

FUKAUMI Naoki (4):
  configs: rockchip: rock-3a: make usb host work
  configs: rockchip: radxa-cm3-io, rock-3a: enable commands for 
i2c/pmic/regulator
  arm: dts: rockchip: radxa-cm3-io, rock-3a: enable regulators for usb
  configs: rockchip: radxa-cm3-io: drop CONFIG_USB_DWC3_GENERIC

Jianqun Xu (1):
  pinctrl: rockchip: support rk3588 pinctrl

Johan Jonker (13):
  arm: dts: rockchip: rk3288: move io-domains nodes
  arm: dts: rockchip: rk3288: partial sync grf and pmu nodes
  video: rockchip: rk_vop: add rk3288-dp compare string
  arm: dts: rockchip: rk3288: partial sync edp node
  arm: dts: rockchip: rk3288: partial sync vop/lvds/mipi/hdmi nodes
  clk: rockchip: clk_rk3288: add PCLK_RKPWM
  arm: dts: rockchip: rk3288: partial sync pwm nodes
  rockchip: gpio: rk_gpio: use ROCKCHIP_GPIOS_PER_BANK as divider
  arm: dts: rockchip: rk3066a-u-boot: add gpio-ranges
  arm: dts: rockchip: rk3188-u-boot: add gpio-ranges
  arm: dts: rockchip: sync rk3066/rk3188 DT files from linux-next v6.2-rc4
  rockchip: configs: mk808: change CONFIG_TPL_TEXT_BASE
  rockchip: configs: mk808: enable usb support

John Keeping (4):
  rockchip: rk3288: Use ft_system_setup instead of ft_board_setup
  rockchip: misc: fix misc_read() return check
  rockchip: efuse: fix misc_read() return values
  rockchip: otp: fix misc_read() return values

Jonas Karlman (26):
  rockchip: Use an external TPL binary on RK3588
  gpio: rockchip: Add support for RK3568 and RK3588 banks
  rockchip: rk3588-rock-5b: Fix sdmmc boot
  rockchip: rk35xx: Fix boot with a large fdt blob
  rockchip: rk35xx: Enable fdtoverlay and kernel compression
  clk: scmi: Add Kconfig option for SPL
  rockchip: rk3588: Add support for sdmmc clocks in SPL
  rockchip: rk3588: Sync sdmmc node from linux-next
  pinctrl: rockchip: Fix IO mux selection on RK3568
  clk: rockchip: rk3568: Add dummy I2S1_MCLKOUT_TX clock support
  mmc: sdhci: Fix HISPD bit handling for MMC HS 52MHz mode
  mmc: sdhci: Set UHS Mode Select field for UHS SDR25 mode
  mmc: rockchip_sdhci: Fix use of device private data
  mmc: rockchip_sdhci: Remove unneeded emmc_phy_init
  mmc: rockchip_sdhci: Add set_clock and config_dll sdhci_ops
  mmc: rockchip_sdhci: Use set_clock and config_dll sdhci_ops
  mmc: rockchip_sdhci: Refactor execute tuning error handling
  mmc: rockchip_sdhci: Update speed mode controls in set_ios_post
  mmc: rockchip_sdhci: Remove empty get_phy and set_enhanced_strobe ops
  mmc: rockchip_sdhci: Rearrange and simplify used regs and flags
  mmc: rockchip_sdhci: Fix HS400 and HS400ES mode on RK3568
  rockchip: rk3568-rock-3a: Enable support for more eMMC modes
  mmc: rockchip_sdhci: Add support for RK3588
  rockchip: rk3588-rock-5b: Include eMMC node in SPL dtb
  clk: rockchip: rk3588: Add limited TMCLK_EMMC clock support
  mmc: rockchip_sdhci: Limit number of blocks read in a single command

Jonathan Liu (1):
  ram: rk3399: add missing high row detection

Kever Yang (1):
  board: rockchip: Add rk3588 evb

Peter Geis (1):
  mmc: sdhci: Allow disabling of SDMA in SPL

Quentin Schulz (2):
  rockchip: puma-rk3399: enforce ENV_IS_NOWHERE with Kconfig select
  rockchip: ringneck-px30: enforce ENV_IS_NOWHERE with Kconfig select

Vasily Khoruzhick (1):
  rockchip: sdhci: rk3568: fix clock setting logic

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/rk3066a-mk808.dts |  27 +-
 arch/arm/dts/rk3066a-u-boot.dtsi   |  25 

[PATCH 4/4] mtd: spi: renesas: Add 4 bytes address mode support

[Marek Vasut]

From: Cong Dang 

This patch adds 4-byte address mode support. Because traditional access
based on FIFO/shift register, it's complex to specify information like
opcode, address length, dummy bytes etc to flash. Replace the traditional
access by spi-mem layer which is essential to make 4-byte address mode
support possible.

Reviewed-by: Marek Vasut 
Signed-off-by: Cong Dang 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
---
Cc: Jagan Teki 
Cc: Vignesh R 
---
 drivers/spi/renesas_rpc_spi.c | 172 +++---
 1 file changed, 78 insertions(+), 94 deletions(-)

diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
index af1b368f69e..51c37d72eb6 100644
--- a/drivers/spi/renesas_rpc_spi.c
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #define RPC_CMNCR  0x  /* R/W */
@@ -168,10 +169,6 @@ struct rpc_spi_priv {
fdt_addr_t  regs;
fdt_addr_t  extr;
struct clk  clk;
-
-   u8  cmdcopy[8];
-   u32 cmdlen;
-   boolcmdstarted;
 };
 
 static int rpc_spi_wait_sslf(struct udevice *dev)
@@ -258,72 +255,84 @@ static int rpc_spi_release_bus(struct udevice *dev)
return 0;
 }
 
-static int rpc_spi_xfer(struct udevice *dev, unsigned int bitlen,
-   const void *dout, void *din, unsigned long flags)
+static int rpc_spi_mem_exec_op(struct spi_slave *spi,
+  const struct spi_mem_op *op)
 {
-   struct udevice *bus = dev->parent;
+   struct udevice *bus = spi->dev->parent;
struct rpc_spi_priv *priv = dev_get_priv(bus);
-   u32 wlen = dout ? (bitlen / 8) : 0;
-   u32 rlen = din ? (bitlen / 8) : 0;
-   u32 wloop = DIV_ROUND_UP(wlen, 4);
-   u32 smenr, smcr, offset;
+   const void *dout = op->data.buf.out ? op->data.buf.out : NULL;
+   void *din = op->data.buf.in ? op->data.buf.in : NULL;
int ret = 0;
-
-   if (!priv->cmdstarted) {
-   if (!wlen || rlen)
-   BUG();
-
-   memcpy(priv->cmdcopy, dout, wlen);
-   priv->cmdlen = wlen;
-
-   /* Command transfer start */
-   priv->cmdstarted = true;
-   if (!(flags & SPI_XFER_END))
-   return 0;
-   }
-
-   offset = (priv->cmdcopy[1] << 16) | (priv->cmdcopy[2] << 8) |
-(priv->cmdcopy[3] << 0);
+   u32 offset = 0;
+   u32 smenr, smcr;
 
smenr = 0;
+   offset = op->addr.val;
+
+   switch (op->data.dir) {
+   case SPI_MEM_DATA_IN:
+   rpc_spi_claim_bus(spi->dev, false);
+
+   writel(0, priv->regs + RPC_DRCMR);
+   writel(RPC_DRCMR_CMD(op->cmd.opcode), priv->regs + RPC_DRCMR);
+   smenr |= RPC_DRENR_CDE;
+
+   writel(0, priv->regs + RPC_DREAR);
+   if (op->addr.nbytes == 4) {
+   writel(RPC_DREAR_EAV(offset >> 25) | RPC_DREAR_EAC(1),
+  priv->regs + RPC_DREAR);
+   smenr |= RPC_DRENR_ADE(0xF);
+   } else if (op->addr.nbytes == 3) {
+   smenr |= RPC_DRENR_ADE(0x7);
+   } else {
+   smenr |= RPC_DRENR_ADE(0);
+   }
 
-   if (wlen || (!rlen && !wlen) || flags == SPI_XFER_ONCE) {
-   if (wlen && flags == SPI_XFER_END)
-   smenr = RPC_SMENR_SPIDE(0xf);
+   writel(0, priv->regs + RPC_DRDMCR);
+   if (op->dummy.nbytes) {
+   writel(8 * op->dummy.nbytes - 1, priv->regs + 
RPC_DRDMCR);
+   smenr |= RPC_DRENR_DME;
+   }
 
-   rpc_spi_claim_bus(dev, true);
+   writel(0, priv->regs + RPC_DROPR);
+   writel(smenr, priv->regs + RPC_DRENR);
 
-   writel(0, priv->regs + RPC_SMCR);
+   memcpy_fromio(din, (void *)(priv->extr + offset), 
op->data.nbytes);
 
-   if (priv->cmdlen >= 1) {/* Command(1) */
-   writel(RPC_SMCMR_CMD(priv->cmdcopy[0]),
-  priv->regs + RPC_SMCMR);
-   smenr |= RPC_SMENR_CDE;
-   } else {
-   writel(0, priv->regs + RPC_SMCMR);
-   }
+   rpc_spi_release_bus(spi->dev);
+   break;
+   case SPI_MEM_DATA_OUT:
+   case SPI_MEM_NO_DATA:
+   rpc_spi_claim_bus(spi->dev, true);
 
-   if (priv->cmdlen >= 4) {/* Address(3) */
-   writel(offset, priv->regs + RPC_SMADR);
-   smenr |= RPC_SMENR_ADE(7);
-   } else {
-   writel(0, priv->regs + RPC_SMADR);
-   }
+   writel(0, priv->regs + RPC_SMCR);
+   writel(0, priv->regs + RPC_SMCMR);
+   

[PATCH 3/4] mtd: spi: renesas: Add R-Car Gen4 support

[Marek Vasut]

From: Hai Pham 

Support RPC SPI on R-Car Gen4 R8A779F0 S4 and R8A779G0 V4H SoCs.

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut 
[Marek: Squash S4 and V4H patches, fix brackets around STRTIM2]
---
Cc: Jagan Teki 
Cc: Vignesh R 
---
 drivers/spi/renesas_rpc_spi.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
index 07ff2d29fd4..af1b368f69e 100644
--- a/drivers/spi/renesas_rpc_spi.c
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -140,6 +140,7 @@
 #define PRC_PHYCNT_EXDSBIT(21)
 #define RPC_PHYCNT_OCT BIT(20)
 #define RPC_PHYCNT_STRTIM(v)   (((v) & 0x7) << 15)
+#define RPC_PHYCNT_STRTIM2(v)  v) & 0x7) << 15) | (((v) & 0x8) << 24))
 #define RPC_PHYCNT_WBUF2   BIT(4)
 #define RPC_PHYCNT_WBUFBIT(2)
 #define RPC_PHYCNT_MEM(v)  (((v) & 0x3) << 0)
@@ -212,9 +213,13 @@ static u32 rpc_spi_get_strobe_delay(void)
 *   0: On H3 ES1.x (not supported in mainline U-Boot)
 *   6: On M3 ES1.x
 *   7: On other R-Car Gen3
+*  15: On R-Car Gen4
 */
if (cpu_type == RMOBILE_CPU_TYPE_R8A7796 && 
rmobile_get_cpu_rev_integer() == 1)
return RPC_PHYCNT_STRTIM(6);
+   else if (cpu_type == RMOBILE_CPU_TYPE_R8A779F0 ||
+cpu_type == RMOBILE_CPU_TYPE_R8A779G0)
+   return RPC_PHYCNT_STRTIM2(15);
else
 #endif
return RPC_PHYCNT_STRTIM(7);
-- 
2.39.2

[PATCH 2/4] mtd: spi: renesas: Enable SPI_FLASH_SFDP_SUPPORT

[Marek Vasut]

From: Hai Pham 

Enable support for parsing and auto discovery of parameters for
SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP)
tables as per JESD216 standard.

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Cong Dang 
Signed-off-by: Marek Vasut  # Make SFDP the 
default unconditionally
---
Cc: Jagan Teki 
Cc: Vignesh R 
---
 drivers/spi/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 4f435fd2681..453a5983b2a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -382,7 +382,7 @@ config SPI_QUP
 config RENESAS_RPC_SPI
bool "Renesas RPC SPI driver"
depends on RCAR_64 || RZA1
-   imply SPI_FLASH_BAR
+   imply SPI_FLASH_SFDP_SUPPORT
help
  Enable the Renesas RPC SPI driver, used to access SPI NOR flash
  on Renesas RCar Gen3 SoCs. This uses driver model and requires a
-- 
2.39.2

[PATCH 1/4] mtd: spi: renesas: Extract strobe delay setting code into separate function

[Marek Vasut]

From: Hai Pham 

Move strobe delay setting code into extra function and reflect the latest
setting in datasheet (R-Car Gen3 v2.20, R-Car V3U v0.50).
i.e. STRTIM[2:0] should be set to 110 (RCar M3-W) or 111 (Other products)

This is also a preparation for new R-Car Gen4 SoC which has 4-bits STRTIM

Reviewed-by: Marek Vasut 
Signed-off-by: Hai Pham 
Signed-off-by: Marek Vasut  # Fix for RZ/A1
---
Cc: Jagan Teki 
Cc: Vignesh R 
---
 drivers/spi/renesas_rpc_spi.c | 29 +
 1 file changed, 21 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
index cb2b8fb64de..07ff2d29fd4 100644
--- a/drivers/spi/renesas_rpc_spi.c
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -202,18 +202,31 @@ static void rpc_spi_flush_read_cache(struct udevice *dev)
 
 }
 
+static u32 rpc_spi_get_strobe_delay(void)
+{
+#ifndef CONFIG_RZA1
+   u32 cpu_type = rmobile_get_cpu_type();
+
+   /*
+* NOTE: RPC_PHYCNT_STRTIM value:
+*   0: On H3 ES1.x (not supported in mainline U-Boot)
+*   6: On M3 ES1.x
+*   7: On other R-Car Gen3
+*/
+   if (cpu_type == RMOBILE_CPU_TYPE_R8A7796 && 
rmobile_get_cpu_rev_integer() == 1)
+   return RPC_PHYCNT_STRTIM(6);
+   else
+#endif
+   return RPC_PHYCNT_STRTIM(7);
+}
+
 static int rpc_spi_claim_bus(struct udevice *dev, bool manual)
 {
struct udevice *bus = dev->parent;
struct rpc_spi_priv *priv = dev_get_priv(bus);
 
-   /*
-* NOTE: The 0x260 are undocumented bits, but they must be set.
-* NOTE: On H3 ES1.x (not supported in mainline U-Boot), the
-*   RPC_PHYCNT_STRTIM shall be 0, while on newer parts, the
-*   RPC_PHYCNT_STRTIM shall be 6.
-*/
-   writel(RPC_PHYCNT_CAL | RPC_PHYCNT_STRTIM(6) | 0x260,
+   /* NOTE: The 0x260 are undocumented bits, but they must be set. */
+   writel(RPC_PHYCNT_CAL | rpc_spi_get_strobe_delay() | 0x260,
   priv->regs + RPC_PHYCNT);
writel((manual ? RPC_CMNCR_MD : 0) | RPC_CMNCR_SFDE |
 RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | RPC_CMNCR_BSZ(0),
@@ -233,7 +246,7 @@ static int rpc_spi_release_bus(struct udevice *dev)
struct rpc_spi_priv *priv = dev_get_priv(bus);
 
/* NOTE: The 0x260 are undocumented bits, but they must be set. */
-   writel(RPC_PHYCNT_STRTIM(6) | 0x260, priv->regs + RPC_PHYCNT);
+   writel(rpc_spi_get_strobe_delay() | 0x260, priv->regs + RPC_PHYCNT);
 
rpc_spi_flush_read_cache(dev);
 
-- 
2.39.2

[PATCH] mtd: spi-nor-core: Add fixups for s25fs512s

[Marek Vasut]

From: Takahiro Kuwano 

This patch adds fixups for s25fs512s to address the following issues
from reading SFDP:

  - Non-uniform sectors by factory default. The setting needs to be
checked and assign erase hook as needed.
  - Page size is wrongly advertised in SFDP.
  - READ_1_1_2 (3Bh/3Ch), READ_1_1_4 (6Bh/6Ch), and PP_1_1_4 (32h/34h)
are not supported.
  - Bank Address Register (BAR) is not supported.

In addition, volatile version of Quad Enable is used for safety.

Based on patch by Takahiro Kuwano with s25fs_s_post_bfpt_fixup() updated
to use 4-byte address commands instead of extended address mode and the
page_size is fixed to 256

For future use, manufacturer code should be moved out from framework
code as same as in Linux.

Reviewed-by: Marek Vasut 
Signed-off-by: Takahiro Kuwano 
Signed-off-by: Hai Pham 
Signed-off-by: Cong Dang 
Signed-off-by: Marek Vasut 
---
Cc: Jagan Teki 
Cc: Takahiro Kuwano 
Cc: Vignesh R 
---
 drivers/mtd/spi/spi-nor-core.c | 85 ++
 1 file changed, 85 insertions(+)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 2c3116ee530..a107f71df80 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3199,6 +3199,87 @@ static int spi_nor_setup(struct spi_nor *nor, const 
struct flash_info *info,
 /* Use ID byte 4 to distinguish S25FS256T and S25Hx-T */
 #define S25FS256T_ID4  (0x08)
 
+/* Number of dummy cycle for Read Any Register (RDAR) op. */
+#define S25FS_S_RDAR_DUMMY 8
+
+static int s25fs_s_quad_enable(struct spi_nor *nor)
+{
+   return spansion_quad_enable_volatile(nor, 0, S25FS_S_RDAR_DUMMY);
+}
+
+static int s25fs_s_erase_non_uniform(struct spi_nor *nor, loff_t addr)
+{
+   /* Support 8 x 4KB sectors at bottom */
+   return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0, 
SZ_32K);
+}
+
+static int s25fs_s_setup(struct spi_nor *nor, const struct flash_info *info,
+const struct spi_nor_flash_parameter *params)
+{
+   int ret;
+   u8 cfr3v;
+
+   /* Bank Address Register is not supported */
+   if (CONFIG_IS_ENABLED(SPI_FLASH_BAR))
+   return -EOPNOTSUPP;
+
+   /*
+* Read CR3V to check if uniform sector is selected. If not, assign an
+* erase hook that supports non-uniform erase.
+*/
+   ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V,
+   S25FS_S_RDAR_DUMMY, );
+   if (ret)
+   return ret;
+   if (!(cfr3v & CFR3V_UNHYSA))
+   nor->erase = s25fs_s_erase_non_uniform;
+
+   return spi_nor_default_setup(nor, info, params);
+}
+
+static void s25fs_s_default_init(struct spi_nor *nor)
+{
+   nor->setup = s25fs_s_setup;
+}
+
+static int s25fs_s_post_bfpt_fixup(struct spi_nor *nor,
+  const struct sfdp_parameter_header *header,
+  const struct sfdp_bfpt *bfpt,
+  struct spi_nor_flash_parameter *params)
+{
+   /* The erase size is set to 4K from BFPT, but it's wrong. Fix it. */
+   nor->erase_opcode = SPINOR_OP_SE;
+   nor->mtd.erasesize = nor->info->sector_size;
+
+   /* The S25FS-S chip family reports 512-byte pages in BFPT but
+* in reality the write buffer still wraps at the safe default
+* of 256 bytes.  Overwrite the page size advertised by BFPT
+* to get the writes working.
+*/
+   params->page_size = 256;
+
+   return 0;
+}
+
+static void s25fs_s_post_sfdp_fixup(struct spi_nor *nor,
+   struct spi_nor_flash_parameter *params)
+{
+   /* READ_1_1_2 is not supported */
+   params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2;
+   /* READ_1_1_4 is not supported */
+   params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4;
+   /* PP_1_1_4 is not supported */
+   params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4;
+   /* Use volatile register to enable quad */
+   params->quad_enable = s25fs_s_quad_enable;
+}
+
+static struct spi_nor_fixups s25fs_s_fixups = {
+   .default_init = s25fs_s_default_init,
+   .post_bfpt = s25fs_s_post_bfpt_fixup,
+   .post_sfdp = s25fs_s_post_sfdp_fixup,
+};
+
 static int s25_mdp_ready(struct spi_nor *nor)
 {
u32 addr;
@@ -3897,6 +3978,10 @@ void spi_nor_set_fixups(struct spi_nor *nor)
if (CONFIG_IS_ENABLED(SPI_FLASH_BAR) &&
!strcmp(nor->info->name, "s25fl256l"))
nor->fixups = _fixups;
+
+   /* For FS-S (family ID = 0x81)  */
+   if (JEDEC_MFR(nor->info) == SNOR_MFR_SPANSION && nor->info->id[5] == 
0x81)
+   nor->fixups = _s_fixups;
 #endif
 
 #ifdef CONFIG_SPI_FLASH_MT35XU
-- 
2.39.2

Re: [GIT PULL] Please pull uu-boot-amlogic-20230417

[Tom Rini]

On Mon, Apr 17, 2023 at 05:24:59PM +0200, Neil Armstrong wrote:

> Hi Tom,
> 
> A big set of changes for the next release, it adds 7 new boards:
> - BPI-CM4IO
> - BananaPi M2-Pro
> - BananaPi M2S
> - Radxa Zero2
> - WeTek Hub
> - WeTek Play2
> - Beelink GT1 Ultimate
> with a welcome doc cleanup!
> Finally a simple change to use the right powerdomain driver for LibreTech-CC 
> v2 and WeTek Core2.
> 
> The CI job is at 
> https://source.denx.de/u-boot/custodians/u-boot-amlogic/pipelines/16023
> 
> Thanks,
> Neil
> 
> The following changes since commit 12c1e5782401abca1a8cff578d1911a9ca7d2e7d:
> 
>   Merge branch 'master' of 
> https://source.denx.de/u-boot/custodians/u-boot-marvell (2023-04-14 10:50:55 
> -0400)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-amlogic.git 
> tags/u-boot-amlogic-20230417
> 
> for you to fetch changes up to 411d6af8b6a278effbaf1d02aa51280b2f5f8008:
> 
>   doc: boards: amlogic: add documentation for Beelink GT1 Ultimate 
> (2023-04-17 11:06:08 +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Pull request for u-boot-nand-20230422

[Dario Binacchi]

Hi Tom,

The following changes since commit 5db4972a5bbdbf9e3af48ffc9bc4fec73b7b6a79:

  Merge tag 'u-boot-nand-20230417' of
https://source.denx.de/u-boot/custodians/u-boot-nand-flash (2023-04-17
10:47:33 -0400)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-nand-flash.git
tags/u-boot-nand-20230422

for you to fetch changes up to 770e77051ec50b46c2aed4c4a355bd79054cf274:

  mtd: rawnand: nand_base: Handle algorithm selection (2023-04-22
23:07:57 +0200)

Gitlab CI showed no issues:
https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/16082


Pull request for u-boot-nand-20230422

Replaces a patch by Linus Walleij merged with pull request
u-boot-nand-20230417, with a newer version that contains fixes for tests
run by Tom Rini.


Dario Binacchi (1):
  Revert "mtd: rawnand: nand_base: Handle algorithm selection"

Linus Walleij (1):
  mtd: rawnand: nand_base: Handle algorithm selection

 drivers/mtd/nand/raw/nand_base.c | 29 ++---
 1 file changed, 22 insertions(+), 7 deletions(-)

-- 
Dario Binacchi

Senior Embedded Linux Developer

dario.binac...@amarulasolutions.com

__


Amarula Solutions SRL

Via Le Canevare 30, 31100 Treviso, Veneto, IT

T. +39 042 243 5310
i...@amarulasolutions.com

www.amarulasolutions.com

Re: [PATCH v8 00/24] Fixes for Rockchip NFC driver part 1

[Johan Jonker]

On 4/21/23 17:34, Johan Jonker wrote:
> 
> 
> On 4/21/23 05:15, Kever Yang wrote:
>> Hi Johan,
>>
>>     I got below error report from CI test, I think it should be relate to 
>> this patch set.
>>
>> === FAILURES 
>> ===
>> 1107 
>> _
>>  test_ut[ut_dm_dm_test_fdt_get_addr_ptr_flat] _
>> 1108 
>> test/py/tests/test_ut.py:346:
>>  in test_ut
>> 1109 
>> assert
>>  output.endswith('Failures: 0')
>> 1110 
>> E
>>  AssertionError: assert False
>>  
>> E
>>  + where False = > 0x7f7089240c10>('Failures: 0')
>> 1112 
>> E
>>  + where  = 'Test: 
>> dm_test_fdt_get_addr_ptr_flat: test-fdt.c (flat 
>> tree)\r\r\ntest/dm/test-fdt.c:627, 
> 
> dm_test_fdt_get_addr_ptr_fla...xpected 8000, got 
> 10009000\r\r\nTest dm_test_fdt_get_addr_ptr_flat failed 1 
> times\r\r\nFailures: 1'.endswith
> 
> It turns out that the suggestion by Simon to use map_sysmem() doesn't work 
> with devfdt_get_addr_index_ptr() somehow.
> 
> To reproduce with this serie:
> make sandbox_defconfig all
> ./u-boot -T -c "ut dm fdt*"
> 
> Test: dm_test_fdt_get_addr_ptr_flat: test-fdt.c (flat tree)
> test/dm/test-fdt.c:627, dm_test_fdt_get_addr_ptr_flat(): (void *)0x8000 = 
> ptr: Expected 8000, got 10009000
> Test fdt* failed 1 times
> 
> ===
> 

> Could Simon have a look at the internal map_sysmem() stuff?

Question for Simon:

Comments:
Re: [PATCH v5 12/21] core: read: add dev_read_addr_index_ptr function
Please use map_sysmem() rather than a cast, so it can be used on sandbox.

Re: [PATCH v6 12/22] core: fdtaddr: add devfdt_get_addr_size_index_ptr function
Shouldn't this use map_to_sysmem()? We should not cast addresses to pointers.

> +   return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr;

Did you mean map_sysmem() instead of map_to_sysmem() as I used in [PATCH v8 
14/24]??

===
The test is looking for "(void *)0x8000", while devfdt_get_addr_ptr() points to 
a map_physmem() pointer now.
Either "(void *)0x8000" needs to be mapped too.

Do you agree?
===

>From /arch/sandbox/include/asm/io.h

/* For sandbox, we want addresses to point into our RAM buffer */
static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
{
return map_physmem(paddr, len, MAP_WRBACK);
}
===

>From /test/dm/test-fdt.c:

static int dm_test_fdt_get_addr_ptr_flat(struct unit_test_state *uts)
{
struct udevice *gpio, *dev;
void *ptr;

/* Test for missing reg property */
ut_assertok(uclass_first_device_err(UCLASS_GPIO, ));
ut_assertnull(devfdt_get_addr_ptr(gpio));

ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 0, ));

===
Change:

ptr = devfdt_get_addr_ptr(dev);
ut_asserteq_ptr((void *)0x8000, ptr);

To:
paddr = map_physmem(0x8000, 0, MAP_NOCACHE); // ??
ut_asserteq_ptr(paddr, ptr); // ??

Please advise what kind of test you like.

===
return 0;
}
DM_TEST(dm_test_fdt_get_addr_ptr_flat,
UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);


> 
> Will send 1 patch to replace:
> [PATCH v8 14/24] core: fdtaddr: add devfdt_get_addr_size_index_ptr function
> 
> for:
> 

> [PATCH v9] core: fdtaddr: add devfdt_get_addr_size_index_ptr function
> 

The use of map_sysmem() in a devfdt_get_addr_size_index_ptr must change the 
test as well in the same patch.
Is there a need for "[patch v10] core: fdtaddr: add 
devfdt_get_addr_size_index_ptr function" or is [patch v9] enough for now??

> Could Kever retest with the patch above replacement?


> 
> Johan
> 
>>
>>
>> Thanks,
>> - Kever
>> On 2023/3/13 08:23, Johan Jonker wrote:
>>> This serie contains fixes for the Rockchip NFC driver,
>>> which was ported to U-boot and merged with little review
>>> and testing it seems.
>>> Part 1 aims at passing the probe function without errors.
>>> Extended with tree wide function cleanup needed for 64bit DT parsing.
>>>
>>> Fixed are:
>>>   64bit FDT parsing
>>>   compatible string removal
>>>   add missing layout structure
>>>   add missing flash_node pointer
>>>   add missing chip ID
>>>
>>> Changed V8:
>>>   change comments
>>>   use uintptr_t size instead of phys_addr_t
>>>   add another fdt_addr_t fix
>>>
>>> Changed V7:
>>>   add proof of concept for syscon node with variable reg size handling
>>>   use another map_sysmem() function as cast
>>>   remove cast
>>>
>>> Changed V6:
>>>   use -EINVAL on return
>>>   drop cast
>>>   use 

Re: [PATCH v2] nand: brcmnand: add iproc support

[Tom Rini]

On Thu, Apr 20, 2023 at 10:51:20PM +0200, Linus Walleij wrote:
> On Wed, Apr 19, 2023 at 6:13 PM Dario Binacchi
>  wrote:
> > On Wed, Apr 19, 2023 at 4:00 PM Linus Walleij  
> > wrote:
> > >
> > > On Wed, Apr 19, 2023 at 3:19 PM Dario Binacchi
> > >  wrote:
> > > > On Wed, Apr 19, 2023 at 3:04 PM Linus Walleij 
> > > >  wrote:
> > > > >
> > > > > On Mon, Apr 17, 2023 at 10:37 AM Dario Binacchi
> > > > >  wrote:
> > > > >
> > > > > > Applied to nand-next ( as well as the patch "mtd: rawnand: 
> > > > > > nand_base:
> > > > > > Handle algorithm selection").
> > > > >
> > > > > 1) Sweet! Thanks.
> > > > >
> > > > > 2) Did you use the latest versions that I resent as part of the
> > > > > NorthStar support?
> > > >
> > > > I applied v2:
> > > > https://patchwork.ozlabs.org/project/uboot/patch/20230308214231.378013-1-linus.wall...@linaro.org/
> > > > https://patchwork.ozlabs.org/project/uboot/patch/20230308212851.370939-1-linus.wall...@linaro.org/
> > >
> > > The second patch will be problematic, can you switch it to the newer
> > > versions?
> >
> > This one?
> > https://patchwork.ozlabs.org/project/uboot/patch/20230308212851.370939-1-linus.wall...@linaro.org/
> > I can revert the commit
> > ff33d3c87c2a mtd: rawnand: nand_base: Handle algorithm selection
> > and apply your newer patch.
> > Do you agree?
> 
> Yes, thanks!
> 
> In patchwork the newer patch is this one:
> https://patchwork.ozlabs.org/project/uboot/patch/20230407134008.1939717-3-linus.wall...@linaro.org/

And since this has broken part of my test lab, please and thanks for a
quick PR with the fix in it.

-- 
Tom


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[PATCH 8/8] rockchip: rk356x: Update PCIe config, IO and memory regions

[Jonas Karlman]

Update config, IO and memory regions used based on [1] with pcie3x2
config reg size corrected from 16 to 1 MiB.

[1] https://lore.kernel.org/lkml/20221112114125.1637543-2-ahol...@omnom.net/

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3568.dtsi | 14 --
 arch/arm/dts/rk356x.dtsi |  7 ---
 2 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi
index ba67b58f05b7..f1be76a54ceb 100644
--- a/arch/arm/dts/rk3568.dtsi
+++ b/arch/arm/dts/rk3568.dtsi
@@ -94,9 +94,10 @@
power-domains = < RK3568_PD_PIPE>;
reg = <0x3 0xc040 0x0 0x0040>,
  <0x0 0xfe27 0x0 0x0001>,
- <0x3 0x7f00 0x0 0x0100>;
-   ranges = <0x0100 0x0 0x3ef0 0x3 0x7ef0 0x0 
0x0010>,
-<0x0200 0x0 0x 0x3 0x4000 0x0 
0x3ef0>;
+ <0x0 0xf200 0x0 0x0010>;
+   ranges = <0x0100 0x0 0xf210 0x0 0xf210 0x0 
0x0010>,
+<0x0200 0x0 0xf220 0x0 0xf220 0x0 
0x01e0>,
+<0x0300 0x0 0x4000 0x3 0x4000 0x0 
0x4000>;
reg-names = "dbi", "apb", "config";
resets = < SRST_PCIE30X1_POWERUP>;
reset-names = "pipe";
@@ -146,9 +147,10 @@
power-domains = < RK3568_PD_PIPE>;
reg = <0x3 0xc080 0x0 0x0040>,
  <0x0 0xfe28 0x0 0x0001>,
- <0x3 0xbf00 0x0 0x0100>;
-   ranges = <0x0100 0x0 0x3ef0 0x3 0xbef0 0x0 
0x0010>,
-<0x0200 0x0 0x 0x3 0x8000 0x0 
0x3ef0>;
+ <0x0 0xf000 0x0 0x0010>;
+   ranges = <0x0100 0x0 0xf010 0x0 0xf010 0x0 
0x0010>,
+<0x0200 0x0 0xf020 0x0 0xf020 0x0 
0x01e0>,
+<0x0300 0x0 0x4000 0x3 0x8000 0x0 
0x4000>;
reg-names = "dbi", "apb", "config";
resets = < SRST_PCIE30X2_POWERUP>;
reset-names = "pipe";
diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi
index 6492ace0de6b..e0591c194bec 100644
--- a/arch/arm/dts/rk356x.dtsi
+++ b/arch/arm/dts/rk356x.dtsi
@@ -951,7 +951,7 @@
compatible = "rockchip,rk3568-pcie";
reg = <0x3 0xc000 0x0 0x0040>,
  <0x0 0xfe26 0x0 0x0001>,
- <0x3 0x3f00 0x0 0x0100>;
+ <0x0 0xf400 0x0 0x0010>;
reg-names = "dbi", "apb", "config";
interrupts = ,
 ,
@@ -980,8 +980,9 @@
phys = < PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = < RK3568_PD_PIPE>;
-   ranges = <0x0100 0x0 0x3ef0 0x3 0x3ef0 0x0 
0x0010
- 0x0200 0x0 0x 0x3 0x 0x0 
0x3ef0>;
+   ranges = <0x0100 0x0 0xf410 0x0 0xf410 0x0 
0x0010>,
+<0x0200 0x0 0xf420 0x0 0xf420 0x0 
0x01e0>,
+<0x0300 0x0 0x4000 0x3 0x 0x0 
0x4000>;
resets = < SRST_PCIE20_POWERUP>;
reset-names = "pipe";
#address-cells = <3>;
-- 
2.40.0

[PATCH 7/8] rockchip: rk3568-rock-3a: Enable PCIe and NVMe support

[Jonas Karlman]

Add missing pinctrl and defconfig options to enable PCIe and NVMe
support on Radxa ROCK 3 Model A.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 14 ++
 configs/rock-3a-rk3568_defconfig|  4 
 2 files changed, 18 insertions(+)

diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 8abee24c02c3..f3ee50949cc0 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -19,6 +19,12 @@
 
  {
bootph-pre-ram;
+
+   pcie {
+   pcie3x2_reset_h: pcie3x2-reset-h {
+   rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO _pull_none>;
+   };
+   };
 };
 
 _pull_up {
@@ -73,6 +79,14 @@
bootph-pre-ram;
 };
 
+ {
+   pinctrl-0 = <_pins _reset_h>;
+};
+
+ {
+   pinctrl-0 = <_pins _reset_h>;
+};
+
  {
bootph-pre-ram;
u-boot,spl-sfc-no-dma;
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 64864a300153..9d725b82a96a 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -46,6 +46,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PMIC=y
@@ -70,6 +71,9 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_XTX=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
 CONFIG_SPL_PINCTRL=y
-- 
2.40.0

[PATCH 6/8] rockchip: clk: clk_rk3568: Add CLK_PCIEPHY2_REF support

[Jonas Karlman]

Add dummy support for the CLK_PCIEPHY2_REF clock.

Signed-off-by: Jonas Karlman 
---
 drivers/clk/rockchip/clk_rk3568.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk_rk3568.c 
b/drivers/clk/rockchip/clk_rk3568.c
index cefc263971a6..c8e688789e4c 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -427,6 +427,7 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong 
rate)
break;
case CLK_PCIEPHY0_REF:
case CLK_PCIEPHY1_REF:
+   case CLK_PCIEPHY2_REF:
return 0;
default:
return -ENOENT;
-- 
2.40.0

[PATCH 4/8] pci: pcie_dw_rockchip: Hide BARs of the root complex

[Jonas Karlman]

PCI Autoconfig read the Root Complex BARs and try to claim the entire
1 GiB memory region on RK3568, leaving no space for any attached device.

Return an invalid value during config read of Root Complex BARs during
autoconfig to work around such issue.

Signed-off-by: Jonas Karlman 
---
 drivers/pci/pcie_dw_rockchip.c | 28 +++-
 1 file changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index fd3da47272b3..924ecb93e963 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -146,6 +146,32 @@ static inline void rk_pcie_writel_apb(struct rk_pcie 
*rk_pcie, u32 reg,
__rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val);
 }
 
+/**
+ * The BARs of bridge should be hidden during enumeration to avoid
+ * allocation of the entire memory region by PCIe core on RK3568.
+ */
+static bool rk_pcie_hide_rc_bar(struct pcie_dw *pcie, pci_dev_t bdf,
+   uint offset)
+{
+   int bus = PCI_BUS(bdf) - pcie->first_busno;
+
+   return bus == 0 && PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+  offset >= PCI_BASE_ADDRESS_0 && offset <= PCI_BASE_ADDRESS_1;
+}
+
+static int rk_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
+  uint offset, ulong *valuep,
+  enum pci_size_t size)
+{
+   struct pcie_dw *pcie = dev_get_priv(bus);
+   int ret = pcie_dw_read_config(bus, bdf, offset, valuep, size);
+
+   if (!ret && rk_pcie_hide_rc_bar(pcie, bdf, offset))
+   *valuep = pci_get_ff(size);
+
+   return ret;
+}
+
 /**
  * rk_pcie_configure() - Configure link capabilities and speed
  *
@@ -476,7 +502,7 @@ rockchip_pcie_probe_err_init_port:
 }
 
 static const struct dm_pci_ops rockchip_pcie_ops = {
-   .read_config= pcie_dw_read_config,
+   .read_config= rk_pcie_read_config,
.write_config   = pcie_dw_write_config,
 };
 
-- 
2.40.0

[PATCH 5/8] regulator: fixed: Add support for gpios prop

[Jonas Karlman]

The commit 12df2c182ccb ("regulator: dt-bindings: fixed-regulator: allow
gpios property") in linux v6.3-rc1 added support for use of either a
gpios or gpio prop with a fixed-regulator.

This adds support for the new gpios prop to the fixed-regulator driver.

Signed-off-by: Jonas Karlman 
---
 drivers/power/regulator/fixed.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c
index ad3b4b98d667..fcfb467a46e3 100644
--- a/drivers/power/regulator/fixed.c
+++ b/drivers/power/regulator/fixed.c
@@ -25,6 +25,7 @@ static int fixed_regulator_of_to_plat(struct udevice *dev)
 {
struct dm_regulator_uclass_plat *uc_pdata;
struct regulator_common_plat *plat;
+   bool gpios;
 
plat = dev_get_plat(dev);
uc_pdata = dev_get_uclass_plat(dev);
@@ -33,7 +34,9 @@ static int fixed_regulator_of_to_plat(struct udevice *dev)
 
uc_pdata->type = REGULATOR_TYPE_FIXED;
 
-   return regulator_common_of_to_plat(dev, plat, "gpio");
+   gpios = dev_read_bool(dev, "gpios");
+   return regulator_common_of_to_plat(dev, plat,
+  gpios ? "gpios" : "gpio");
 }
 
 static int fixed_regulator_get_value(struct udevice *dev)
-- 
2.40.0

[PATCH 3/8] pci: pcie_dw_rockchip: Speed up link probe

[Jonas Karlman]

Use a similar pattern and delay values as the linux mainline driver to
speed up failing when nothing is connected.

Reduce fail speed from around 5+ seconds down to around one second on a
Radxa ROCK 3 Model A, where pcie2x1 is probed before pcie3x2 M2 slot.

Signed-off-by: Jonas Karlman 
---
 drivers/pci/pcie_dw_rockchip.c | 68 ++
 1 file changed, 37 insertions(+), 31 deletions(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index a5b900f95981..fd3da47272b3 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -61,9 +61,6 @@ struct rk_pcie {
 #define PCIE_CLIENT_DBG_TRANSITION_DATA0x
 #define PCIE_CLIENT_DBF_EN 0x0003
 
-/* Parameters for the waiting for #perst signal */
-#define MACRO_US   1000
-
 static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
 {
if ((uintptr_t)addr & (size - 1)) {
@@ -242,43 +239,46 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 
cap_speed)
/* DW pre link configurations */
rk_pcie_configure(priv, cap_speed);
 
-   /* Rest the device */
-   if (dm_gpio_is_valid(>rst_gpio)) {
-   dm_gpio_set_value(>rst_gpio, 0);
-   /*
-* Minimal is 100ms from spec but we see
-* some wired devices need much more, such as 600ms.
-* Add a enough delay to cover all cases.
-*/
-   udelay(MACRO_US * 1000);
-   dm_gpio_set_value(>rst_gpio, 1);
-   }
-
rk_pcie_disable_ltssm(priv);
rk_pcie_link_status_clear(priv);
rk_pcie_enable_debug(priv);
 
+   /* Reset the device */
+   if (dm_gpio_is_valid(>rst_gpio))
+   dm_gpio_set_value(>rst_gpio, 0);
+
/* Enable LTSSM */
rk_pcie_enable_ltssm(priv);
 
-   for (retries = 0; retries < 5; retries++) {
-   if (is_link_up(priv)) {
-   dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n",
-rk_pcie_readl_apb(priv, 
PCIE_CLIENT_LTSSM_STATUS));
-   rk_pcie_debug_dump(priv);
-   return 0;
-   }
-
-   dev_info(priv->dw.dev, "PCIe Linking... LTSSM is 0x%x\n",
-rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
-   rk_pcie_debug_dump(priv);
-   udelay(MACRO_US * 1000);
+   /*
+* PCIe requires the refclk to be stable for 100ms prior to releasing
+* PERST. See table 2-4 in section 2.6.2 AC Specifications of the PCI
+* Express Card Electromechanical Specification, 1.1. However, we don't
+* know if the refclk is coming from RC's PHY or external OSC. If it's
+* from RC, so enabling LTSSM is the just right place to release #PERST.
+*/
+   mdelay(100);
+   if (dm_gpio_is_valid(>rst_gpio))
+   dm_gpio_set_value(>rst_gpio, 1);
+
+   /* Check if the link is up or not */
+   for (retries = 0; retries < 10; retries++) {
+   if (is_link_up(priv))
+   break;
+
+   mdelay(100);
+   }
+
+   if (retries >= 10) {
+   dev_err(priv->dw.dev, "PCIe-%d Link Fail\n",
+   dev_seq(priv->dw.dev));
+   return -EIO;
}
 
-   dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", dev_seq(priv->dw.dev));
-   /* Link maybe in Gen switch recovery but we need to wait more 1s */
-   udelay(MACRO_US * 1000);
-   return -EIO;
+   dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n",
+rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
+   rk_pcie_debug_dump(priv);
+   return 0;
 }
 
 static int rockchip_pcie_init_port(struct udevice *dev)
@@ -287,6 +287,12 @@ static int rockchip_pcie_init_port(struct udevice *dev)
u32 val;
struct rk_pcie *priv = dev_get_priv(dev);
 
+   ret = reset_assert_bulk(>rsts);
+   if (ret) {
+   dev_err(dev, "failed to assert resets (ret=%d)\n", ret);
+   return ret;
+   }
+
/* Set power and maybe external ref clk input */
ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true);
if (ret && ret != -ENOSYS) {
-- 
2.40.0

[PATCH 2/8] pci: pcie_dw_rockchip: Use regulator_set_enable_if_allowed

[Jonas Karlman]

The vpcie3v3 regulator is typically a fixed regulator controlled using
gpio. Change to use enable and disable calls on the regulator instead
of trying to set a voltage value.

Signed-off-by: Jonas Karlman 
---
 drivers/pci/pcie_dw_rockchip.c | 17 +++--
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 225af400ba70..a5b900f95981 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -288,21 +288,16 @@ static int rockchip_pcie_init_port(struct udevice *dev)
struct rk_pcie *priv = dev_get_priv(dev);
 
/* Set power and maybe external ref clk input */
-   if (priv->vpcie3v3) {
-   ret = regulator_set_value(priv->vpcie3v3, 330);
-   if (ret) {
-   dev_err(priv->dw.dev, "failed to enable vpcie3v3 
(ret=%d)\n",
-   ret);
-   return ret;
-   }
+   ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true);
+   if (ret && ret != -ENOSYS) {
+   dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n", ret);
+   return ret;
}
 
-   udelay(MACRO_US * 1000);
-
ret = generic_phy_init(>phy);
if (ret) {
dev_err(dev, "failed to init phy (ret=%d)\n", ret);
-   return ret;
+   goto err_disable_regulator;
}
 
ret = generic_phy_power_on(>phy);
@@ -345,6 +340,8 @@ err_power_off_phy:
generic_phy_power_off(>phy);
 err_exit_phy:
generic_phy_exit(>phy);
+err_disable_regulator:
+   regulator_set_enable_if_allowed(priv->vpcie3v3, false);
 
return ret;
 }
-- 
2.40.0

[PATCH 0/8] rockchip: Fix PCIe and NVMe support on RK3568

[Jonas Karlman]

This series fixes and enables PCIe and NVMe support on RK3568.
It depends on prior series by Eugen Hristev, [1] and [2] that adds PCIe
support on RK3588 and also [3] that add basic reference counting to gpio
regulators.

Patch 1-2 fixes main issue in the driver to be usable on RK3568.
Patch 3 fixes a long wait time during probe when no device is attached.
Patch 4 hides BARs of the root complex that could claim the entire
memory region during PCI autoconfig.
Patch 5 adds support for the gpios prop to the fixed regulators driver.
Patch 6 adds a missing clock to the clock driver.
Patch 7 enables PCIe and NVMe support on rk3568-rock-3a.
Patch 8 updates the device tree with new reg and ranges values.

For a clean apply of patch 7, the series at [4] may be needed.

I have tested that a Samsung 970 EVO NVMe is detected on a ROCK 3A,

  BusDevFun  VendorId   DeviceId   Device Class   Sub-Class
  01.00.00   0x1d87 0x3566 Bridge device   0x04
  02.00.00   0x144d 0xa808 Mass storage controller 0x08

and I have also verified that the network controller continues to be
detected on a ROCK 5B.

  BusDevFun  VendorId   DeviceId   Device Class   Sub-Class
  00.00.00   0x1d87 0x3588 Bridge device   0x04
  01.00.00   0x10ec 0x8125 Network controller  0x00

This series can also be found at [5].

[1] 
https://patchwork.ozlabs.org/project/uboot/patch/20230413141103.268571-1-eugen.hris...@collabora.com/
[2] 
https://patchwork.ozlabs.org/project/uboot/patch/20230417091951.4640-1-eugen.hris...@collabora.com/
[3] 
https://patchwork.ozlabs.org/project/uboot/patch/20230419134526.128800-1-eugen.hris...@collabora.com/
[4] 
https://patchwork.ozlabs.org/project/uboot/cover/20230422012309.402799-1-jo...@kwiboo.se/
[5] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3568-pcie-v1

Jonas Karlman (8):
  pci: pcie_dw_rockchip: Get config region from reg prop
  pci: pcie_dw_rockchip: Use regulator_set_enable_if_allowed
  pci: pcie_dw_rockchip: Speed up link probe
  pci: pcie_dw_rockchip: Hide BARs of the root complex
  regulator: fixed: Add support for gpios prop
  rockchip: clk: clk_rk3568: Add CLK_PCIEPHY2_REF support
  rockchip: rk3568-rock-3a: Enable PCIe and NVMe support
  rockchip: rk356x: Update PCIe config, IO and memory regions

 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi |  14 +++
 arch/arm/dts/rk3568.dtsi|  14 +--
 arch/arm/dts/rk356x.dtsi|   7 +-
 configs/rock-3a-rk3568_defconfig|   4 +
 drivers/clk/rockchip/clk_rk3568.c   |   1 +
 drivers/pci/pcie_dw_common.c|  10 +-
 drivers/pci/pcie_dw_rockchip.c  | 128 +++-
 drivers/power/regulator/fixed.c |   5 +-
 8 files changed, 123 insertions(+), 60 deletions(-)

-- 
2.40.0

[PATCH 1/8] pci: pcie_dw_rockchip: Get config region from reg prop

[Jonas Karlman]

Get the config region to use from the reg prop. Also check the return
value from dev_read_addr_index correctly. And update the referenced
region index used in comment.

Signed-off-by: Jonas Karlman 
---
 drivers/pci/pcie_dw_common.c   | 10 ++
 drivers/pci/pcie_dw_rockchip.c | 15 +++
 2 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c
index 9f8b016d1149..74fb6df412c7 100644
--- a/drivers/pci/pcie_dw_common.c
+++ b/drivers/pci/pcie_dw_common.c
@@ -141,9 +141,9 @@ static uintptr_t set_cfg_address(struct pcie_dw *pcie,
 
/*
 * Not accessing root port configuration space?
-* Region #0 is used for Outbound CFG space access.
+* Region #1 is used for Outbound CFG space access.
 * Direction = Outbound
-* Region Index = 0
+* Region Index = 1
 */
d = PCI_MASK_BUS(d);
d = PCI_ADD_BUS(bus, d);
@@ -328,8 +328,10 @@ void pcie_dw_setup_host(struct pcie_dw *pci)
pci->prefetch.bus_start = hose->regions[ret].bus_start; 
 /* PREFETCH_bus_addr */
pci->prefetch.size = hose->regions[ret].size;   /* 
PREFETCH size */
} else if (hose->regions[ret].flags == PCI_REGION_SYS_MEMORY) {
-   pci->cfg_base = (void *)(pci->io.phys_start - 
pci->io.size);
-   pci->cfg_size = pci->io.size;
+   if (!pci->cfg_base) {
+   pci->cfg_base = (void *)(pci->io.phys_start - 
pci->io.size);
+   pci->cfg_size = pci->io.size;
+   }
} else {
dev_err(pci->dev, "invalid flags type!\n");
}
diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 60c74bea24b2..225af400ba70 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -355,17 +355,24 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
int ret;
 
priv->dw.dbi_base = (void *)dev_read_addr_index(dev, 0);
-   if (!priv->dw.dbi_base)
-   return -ENODEV;
+   if ((fdt_addr_t)priv->dw.dbi_base == FDT_ADDR_T_NONE)
+   return -EINVAL;
 
dev_dbg(dev, "DBI address is 0x%p\n", priv->dw.dbi_base);
 
priv->apb_base = (void *)dev_read_addr_index(dev, 1);
-   if (!priv->apb_base)
-   return -ENODEV;
+   if ((fdt_addr_t)priv->apb_base == FDT_ADDR_T_NONE)
+   return -EINVAL;
 
dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base);
 
+   priv->dw.cfg_base =
+   (void *)dev_read_addr_size_index(dev, 2, >dw.cfg_size);
+   if ((fdt_addr_t)priv->dw.cfg_base == FDT_ADDR_T_NONE)
+   return -EINVAL;
+
+   dev_dbg(dev, "CFG address is 0x%p\n", priv->dw.cfg_base);
+
ret = gpio_request_by_name(dev, "reset-gpios", 0,
   >rst_gpio, GPIOD_IS_OUT);
if (ret) {
-- 
2.40.0

Re: [PATCH 1/1] sandbox: mark sandbox_exit() as no return.

[Simon Glass]

On Sat, 1 Apr 2023 at 20:54, Heinrich Schuchardt <
heinrich.schucha...@canonical.com> wrote:
>
> Fix a -Wimplicit-fallthrough warning in sandbox_sysreset_request().
>
> Signed-off-by: Heinrich Schuchardt 
> ---
>  arch/sandbox/cpu/cpu.c| 2 +-
>  arch/sandbox/include/asm/u-boot-sandbox.h | 2 +-
>  drivers/sysreset/sysreset_sandbox.c   | 1 -
>  3 files changed, 2 insertions(+), 3 deletions(-)

Reviewed-by: Simon Glass 

Applied to u-boot-dm, thanks!

Re: [PATCH 1/1] sandbox: spi: sandbox_sf_process_cmd() missing fallthrough

[Simon Glass]

On Sat, 1 Apr 2023 at 20:38, Heinrich Schuchardt <
heinrich.schucha...@canonical.com> wrote:
>
> Add a missing fallthrough macro to avoid a -Wimplicit-fallthrough warning.
>
> Signed-off-by: Heinrich Schuchardt 
> ---
>  drivers/mtd/spi/sandbox.c | 1 +
>  1 file changed, 1 insertion(+)
>

Reviewed-by: Simon Glass 

Applied to u-boot-dm, thanks!

Re: [PATCH 1/1] sandbox: fix fall through in sandbox_flash_bulk()

[Simon Glass]

On Sat, 1 Apr 2023 at 19:25, Heinrich Schuchardt <
heinrich.schucha...@canonical.com> wrote:
>
> Handling of SANDBOX_FLASH_EP_OUT should never fall through to
> SANDBOX_FLASH_EP_IN.
>
> This addresses a warning shown when compiling with
> -Wimplicit-fallthrough.
>
> Signed-off-by: Heinrich Schuchardt 
> ---
>  drivers/usb/emul/sandbox_flash.c | 1 +
>  1 file changed, 1 insertion(+)
>

Reviewed-by: Simon Glass 

Applied to u-boot-dm, thanks!

Re: [PATCH 1/1] sandbox: fix sandbox_hub_submit_control_msg()

[Simon Glass]

On Sat, 1 Apr 2023 at 19:57, Heinrich Schuchardt <
heinrich.schucha...@canonical.com> wrote:
>
> Avoid incorrect fall through:
> A USB_RT_HUB request should not be treated as USB_RT_PORT.
>
> Simplify the coding:
> Avoid duplicate debug() statements.
>
> This fixes all -Wimplicit-fallthrough warnings.
>
> Signed-off-by: Heinrich Schuchardt 
> ---
>  drivers/usb/emul/sandbox_hub.c | 30 +-
>  1 file changed, 9 insertions(+), 21 deletions(-)

Reviewed-by: Simon Glass 

Applied to u-boot-dm, thanks!

Re: [PATCH] boot: vbe_simple: Fix vbe_simple_read_bootflow() dependency

[Simon Glass]

Hi Heinrich,

On Tue, 4 Apr 2023 at 16:50, Heinrich Schuchardt  wrote:
>
> On 4/3/23 05:40, Bin Meng wrote:
> > vbe_simple_read_bootflow() calls vbe_simple_read_bootflow_fw()
> > which is only available when BOOTMETH_VBE_SIMPLE_FW is on.
> >
> > Signed-off-by: Bin Meng 
> > ---
> >
> >   boot/vbe_simple.c | 12 +++-
> >   1 file changed, 7 insertions(+), 5 deletions(-)
> >
Applied to u-boot-dm, thanks!

Re: [PATCH 1/1] common: static fdt_simplefb_enable_existing_node()

[Simon Glass]

On Tue, 4 Apr 2023 at 06:47, Heinrich Schuchardt
 wrote:
>
> Function fdt_simplefb_enable_existing_node() should be static as it is not
> used outside common/fdt_simplefb.c.
>
> Signed-off-by: Heinrich Schuchardt 
> ---
>  common/fdt_simplefb.c  | 8 +++-
>  include/fdt_simplefb.h | 1 -
>  2 files changed, 7 insertions(+), 2 deletions(-)
>

Reviewed-by: Simon Glass 

Applied to u-boot-dm, thanks!

Re: [PATCH] binman: Use unsigned long over typedef ulong

[Simon Glass]

On Wed, 5 Apr 2023 at 06:45, Andrew Davis  wrote:
>
> The header binman_sym.h depends on ulong typedef but does not include
> types.h. This means the header must be included after including types.h
> or a header that includes it.
>
> We could include types.h but instead let's just switch from ulong
> to directly using unsigned long. This removes the need for typedef'ing
> it in some of the tests, so also remove those.
>
> Signed-off-by: Andrew Davis 
> ---
>  include/binman_sym.h| 8 
>  tools/binman/test/blob_syms.c   | 2 --
>  tools/binman/test/u_boot_binman_syms.c  | 2 --
>  tools/binman/test/u_boot_binman_syms_size.c | 2 --
>  4 files changed, 4 insertions(+), 10 deletions(-)
>

Reviewed-by: Simon Glass 

Applied to u-boot-dm, thanks!

Re: [PATCH 1/1] MAINTAINERS: assign include/os.h

[Simon Glass]

On Wed, 5 Apr 2023 at 21:27, Heinrich Schuchardt
 wrote:
>
> os.h is only used by the sandbox.
>
> Signed-off-by: Heinrich Schuchardt 
> ---
>  MAINTAINERS | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Simon Glass 

Applied to u-boot-dm, thanks!

Re: [PATCH v2 1/1] sandbox: fix return type of os_filesize()

[Simon Glass]

On Wed, 5 Apr 2023 at 21:34, Heinrich Schuchardt
 wrote:
>
> Given a file ../img of size 4294967296 with GPT partition table and
> partitions:
>
> => host bind 0 ../img
> => part list host 0
> Disk host-0.blk not ready
>
> The cause is os_filesize() returning int. File sizes must use off_t.
>
> Correct all uses of os_filesize() too.
>
> Signed-off-by: Heinrich Schuchardt 
> ---
> v2:
> avoid different signedness when comparing numbers
> ---
>  arch/sandbox/cpu/os.c| 8 ++--
>  drivers/block/host_dev.c | 3 ++-
>  include/os.h | 2 +-
>  3 files changed, 9 insertions(+), 4 deletions(-)

Reviewed-by: Simon Glass 

Applied to u-boot-dm, thanks!

Re: [PATCH] dm: core: Make aliases_lookup static

[Simon Glass]

On Thu, 6 Apr 2023 at 02:38, Bin Meng  wrote:
>
> aliases_lookup is only referenced in of_access.c
>
> Signed-off-by: Bin Meng 
> ---
>
>  drivers/core/of_access.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Simon Glass 

Applied to u-boot-dm, thanks!

Re: [PATCH] bootflow: Rework do_bootflow_menu() slightly

[Simon Glass]

On Fri, 7 Apr 2023 at 02:03, Tom Rini  wrote:
>
> When building this with clang, we get a warning such as:
> cmd/bootflow.c:412:27: warning: variable 'bflow' is uninitialized when used 
> here [-Wuninitialized]
> printf("Selected: %s\n", bflow->os_name ? bflow->os_name : 
> bflow->name);
>  ^
>
> And a suggestion to just initialize bflow to NULL. This would however
> would be ensuring a bad dereference. Instead, looking at the function we
> rework things so that when CONFIG_EXPO is not enabled (and so, no UI) we
> error early and would never reach this point in the code.  Simplify the
> rest slightly as well while at this.
>
> Signed-off-by: Tom Rini 
> ---
> Cc: Simon Glass 
> ---
>  cmd/bootflow.c | 24 
>  1 file changed, 12 insertions(+), 12 deletions(-)

Reviewed-by: Simon Glass 

Applied to u-boot-dm, thanks!

Re: [PATCH 1/1] sandbox: correct posix_types.h define

[Simon Glass]

On Mon, 17 Apr 2023 at 01:09, Heinrich Schuchardt
 wrote:
>
> arch/arm/include/asm/posix_types.h and
> arch/sandbox/include/asm/posix_types.h should use different defines.
>
> Add SPDX header.
>
> Signed-off-by: Heinrich Schuchardt 
> ---
>  arch/sandbox/include/asm/posix_types.h | 7 ---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>

Reviewed-by: Simon Glass 

Applied to u-boot-dm, thanks!

[PATCH] tools: Fall back to importlib_resources on Python 3.6

[Jan Kiszka]

From: Jan Kiszka 

importlib.resources became part of 3.7 only. Allow using distros with
3.6 and the importlib_resources backport.

Signed-off-by: Jan Kiszka 
---

Tested on OpenSUSE 15.4 with importlib_resources 1.1.0.

 tools/binman/control.py   | 6 +-
 tools/buildman/control.py | 6 +-
 tools/patman/__main__.py  | 6 +-
 3 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/tools/binman/control.py b/tools/binman/control.py
index 0febcb79a60..68597c4e779 100644
--- a/tools/binman/control.py
+++ b/tools/binman/control.py
@@ -7,7 +7,11 @@
 
 from collections import OrderedDict
 import glob
-import importlib.resources
+try:
+import importlib.resources
+except ImportError:
+# for Python 3.6
+import importlib_resources
 import os
 import pkg_resources
 import re
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index 35f44c0cf3d..09a11f25b3f 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -3,7 +3,11 @@
 #
 
 import multiprocessing
-import importlib.resources
+try:
+import importlib.resources
+except ImportError:
+# for Python 3.6
+import importlib_resources
 import os
 import shutil
 import subprocess
diff --git a/tools/patman/__main__.py b/tools/patman/__main__.py
index 48ffbc8eadf..8eba5d34864 100755
--- a/tools/patman/__main__.py
+++ b/tools/patman/__main__.py
@@ -7,7 +7,11 @@
 """See README for more information"""
 
 from argparse import ArgumentParser
-import importlib.resources
+try:
+import importlib.resources
+except ImportError:
+# for Python 3.6
+import importlib_resources
 import os
 import re
 import sys
-- 
2.35.3

[RESEND PATCH 3/3] imx6: clock: print real pixel clock rate

[Dario Binacchi]

Add debug messages to print the real pixel clock rate, which may not be
the requested one.

Signed-off-by: Dario Binacchi 

---

 arch/arm/mach-imx/mx6/clock.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
index 267d86ab4194..1bdc568f9b14 100644
--- a/arch/arm/mach-imx/mx6/clock.c
+++ b/arch/arm/mach-imx/mx6/clock.c
@@ -802,6 +802,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
}
 
enable_lcdif_clock(base_addr, 1);
+   debug("pixel clock = %u\n", mxc_get_clock(MXC_LCDIF1_CLK));
} else if (is_mx6sx()) {
/* Setting LCDIF2 for i.MX6SX */
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
@@ -823,6 +824,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
 
enable_lcdif_clock(base_addr, 1);
+   debug("pixel clock = %u\n", mxc_get_clock(MXC_LCDIF2_CLK));
}
 }
 
-- 
2.32.0

[RESEND PATCH 2/3] imx6: clock: add support to get LCD pixel clock rate

[Dario Binacchi]

Add the get_lcd_clk() function to get the LCD pixel clock rate.

The patch has been tested on imx6ul platform.

Signed-off-by: Dario Binacchi 
---

 arch/arm/include/asm/arch-mx6/clock.h |  2 +
 arch/arm/mach-imx/mx6/clock.c | 58 +++
 2 files changed, 60 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx6/clock.h 
b/arch/arm/include/asm/arch-mx6/clock.h
index 8ae49715789c..81af89c631f5 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -41,6 +41,8 @@ enum mxc_clock {
MXC_SATA_CLK,
MXC_NFC_CLK,
MXC_I2C_CLK,
+   MXC_LCDIF1_CLK,
+   MXC_LCDIF2_CLK,
 };
 
 enum ldb_di_clock {
diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
index 17d8dcd5c841..267d86ab4194 100644
--- a/arch/arm/mach-imx/mx6/clock.c
+++ b/arch/arm/mach-imx/mx6/clock.c
@@ -418,6 +418,60 @@ static u32 get_uart_clk(void)
return freq / (uart_podf + 1);
 }
 
+static u32 get_lcd_clk(unsigned int ifnum)
+{
+   u32 pll_rate;
+   u32 pred, postd;
+
+   if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
+   !is_mx6sll()) {
+   debug("This chip does't support lcd\n");
+   return 0;
+   }
+
+   pll_rate = decode_pll(PLL_VIDEO, MXC_HCLK);
+   if (ifnum == 1) {
+   if (!is_mx6sl()) {
+   pred = __raw_readl(_ccm->cscdr2);
+   pred &= MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK;
+   pred = pred >> MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET;
+
+   postd = readl(_ccm->cbcmr);
+   postd &= MXC_CCM_CBCMR_LCDIF1_PODF_MASK;
+   postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET;
+   } else {
+   pred = __raw_readl(_ccm->cscdr2);
+   pred &= MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK;
+   pred = pred >> MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET;
+
+   postd = readl(_ccm->cscmr1);
+   postd &= MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET;
+   postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET;
+   }
+   } else if (ifnum == 2) {
+   if (is_mx6sx()) {
+   pred = __raw_readl(_ccm->cscdr2);
+   pred &= MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK;
+   pred = pred >> MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET;
+
+   postd = readl(_ccm->cscmr1);
+   postd &= MXC_CCM_CSCMR1_LCDIF2_PODF_MASK;
+   postd = postd >> MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET;
+
+   } else {
+   goto if_err;
+   }
+   } else {
+   goto if_err;
+   }
+
+   return DIV_ROUND_UP_ULL((u64)pll_rate, (postd + 1) * (pred + 1));
+
+if_err:
+   debug("This chip not support lcd iterface %d\n", ifnum);
+   return 0;
+}
+
 static u32 get_cspi_clk(void)
 {
u32 reg, cspi_podf;
@@ -1273,6 +1327,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return get_usdhc_clk(3);
case MXC_SATA_CLK:
return get_ahb_clk();
+   case MXC_LCDIF1_CLK:
+   return get_lcd_clk(1);
+   case MXC_LCDIF2_CLK:
+   return get_lcd_clk(2);
default:
printf("Unsupported MXC CLK: %d\n", clk);
break;
-- 
2.32.0

[RESEND PATCH 1/3] imx6: clock: improve calculations to get the PLL video rate

[Dario Binacchi]

During some tests to check the pixel clock rate in the transition from
U-Boot to the Linux kernel, I noticed that with the same configuration
of the registers the debug messages reported different rates.

The same Linux kernel calculations are now used to get the PLL video
rate.

Signed-off-by: Dario Binacchi 
Reviewed-by: Michael Trimarchi 
---

 arch/arm/mach-imx/mx6/clock.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
index cb9d629be408..17d8dcd5c841 100644
--- a/arch/arm/mach-imx/mx6/clock.c
+++ b/arch/arm/mach-imx/mx6/clock.c
@@ -213,6 +213,7 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num)
 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 {
u32 div, test_div, pll_num, pll_denom;
+   u64 temp64;
 
switch (pll) {
case PLL_SYS:
@@ -272,7 +273,10 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
}
test_div = 1 << (2 - test_div);
 
-   return infreq * (div + pll_num / pll_denom) / test_div;
+   temp64 = (u64)infreq;
+   temp64 *= pll_num;
+   do_div(temp64, pll_denom);
+   return infreq * div + (unsigned long)temp64;
default:
return 0;
}
-- 
2.32.0

[RESEND PATCH 0/3] imx6: clock: add support to get LCD pixel clock rate

[Dario Binacchi]

The series adds a function to get the LCD pixel clock rate. Also
improves video PLLL rate calculation.


Dario Binacchi (3):
  imx6: clock: improve calculations to get the PLL video rate
  imx6: clock: add support to get LCD pixel clock rate
  imx6: clock: print real pixel clock rate

 arch/arm/include/asm/arch-mx6/clock.h |  2 +
 arch/arm/mach-imx/mx6/clock.c | 66 ++-
 2 files changed, 67 insertions(+), 1 deletion(-)

-- 
2.32.0

[PATCH] ARM: dts: stm32f769-disco: remove the dsi_host node

[Dario Binacchi]

The node has become useless, as described in the
commit 754815b854258 ("video: stm32: remove the compatible "synopsys, 
dw-mipi-dsi" support")

Signed-off-by: Dario Binacchi 
---

 arch/arm/dts/stm32f769-disco-u-boot.dtsi | 5 -
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi 
b/arch/arm/dts/stm32f769-disco-u-boot.dtsi
index b5198fddff7c..2c823cce98b4 100644
--- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi
@@ -28,11 +28,6 @@
button-gpio = < 0 0>;
};
 
-   dsi_host: dsi_host {
-   compatible = "synopsys,dw-mipi-dsi";
-   status = "okay";
-   };
-
led1 {
compatible = "st,led1";
led-gpio = < 5 0>;
-- 
2.32.0

[PATCH] configs: stm32f746-disco: remove a useless comment

[Dario Binacchi]

Commit 8fc78fc73b7f9d ("configs: migrate CONFIG_BMP_16/24/32BPP to defconfigs")
made the comment useless.

Signed-off-by: Dario Binacchi 
---

 include/configs/stm32f746-disco.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/include/configs/stm32f746-disco.h 
b/include/configs/stm32f746-disco.h
index 34856d300403..9bf01cac47a4 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -36,6 +36,4 @@
 #define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + \
 CONFIG_SPL_PAD_TO)
 
-/* For splashcreen */
-
 #endif /* __CONFIG_H */
-- 
2.32.0

[PATCH 4/4] test: bdinfo: Add test for command bdinfo

[Marek Vasut]

Add test for command bdinfo .

Signed-off-by: Marek Vasut 
---
Cc: Jason Liu 
Cc: Michal Simek 
Cc: Ovidiu Panait 
Cc: Simon Glass 
---
 include/test/suites.h |   1 +
 test/cmd/Makefile |   1 +
 test/cmd/bdinfo.c | 179 ++
 test/cmd_ut.c |   6 ++
 4 files changed, 187 insertions(+)
 create mode 100644 test/cmd/bdinfo.c

diff --git a/include/test/suites.h b/include/test/suites.h
index 7349ce5aa60..1c7dc65966a 100644
--- a/include/test/suites.h
+++ b/include/test/suites.h
@@ -28,6 +28,7 @@ int cmd_ut_category(const char *name, const char *prefix,
 
 int do_ut_addrmap(struct cmd_tbl *cmdtp, int flag, int argc,
  char *const argv[]);
+int do_ut_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const 
argv[]);
 int do_ut_bootm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
 int do_ut_bootstd(struct cmd_tbl *cmdtp, int flag, int argc,
  char *const argv[]);
diff --git a/test/cmd/Makefile b/test/cmd/Makefile
index 055adc65a25..a3cf983739e 100644
--- a/test/cmd/Makefile
+++ b/test/cmd/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_PAUSE) += test_pause.o
 endif
 obj-y += exit.o mem.o
 obj-$(CONFIG_CMD_ADDRMAP) += addrmap.o
+obj-$(CONFIG_CMD_BDI) += bdinfo.o
 obj-$(CONFIG_CMD_FDT) += fdt.o
 obj-$(CONFIG_CONSOLE_TRUETYPE) += font.o
 obj-$(CONFIG_CMD_LOADM) += loadm.o
diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c
new file mode 100644
index 000..2968955d8b2
--- /dev/null
+++ b/test/cmd/bdinfo.c
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Tests for bdinfo command
+ *
+ * Copyright 2023 Marek Vasut 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Declare a new bdinfo test */
+#define BDINFO_TEST(_name, _flags) UNIT_TEST(_name, _flags, bdinfo_test)
+
+static void bdinfo_test_num_l(struct unit_test_state *uts,
+ const char *name, ulong value)
+{
+   ut_assert_nextline("%-12s= 0x%0*lx", name, 2 * (int)sizeof(value), 
value);
+}
+
+static void bdinfo_test_num_ll(struct unit_test_state *uts,
+  const char *name, unsigned long long value)
+{
+   ut_assert_nextline("%-12s= 0x%.*llx", name, 2 * (int)sizeof(ulong), 
value);
+}
+
+static void test_eth(struct unit_test_state *uts)
+{
+   const int idx = eth_get_dev_index();
+   uchar enetaddr[6];
+   char name[10];
+   int ret;
+
+   if (idx)
+   sprintf(name, "eth%iaddr", idx);
+   else
+   strcpy(name, "ethaddr");
+
+   ret = eth_env_get_enetaddr_by_index("eth", idx, enetaddr);
+
+   ut_assert_nextline("current eth = %s", eth_get_name());
+   if (!ret)
+   ut_assert_nextline("%-12s= (not set)", name);
+   else
+   ut_assert_nextline("%-12s= %pM", name, enetaddr);
+   ut_assert_nextline("IP addr = %s", env_get("ipaddr"));
+}
+
+static void test_video_info(struct unit_test_state *uts)
+{
+   const struct udevice *dev;
+   struct uclass *uc;
+
+   uclass_id_foreach_dev(UCLASS_VIDEO, dev, uc) {
+   ut_assert_nextline("%-12s= %s %sactive", "Video", dev->name,
+  device_active(dev) ? "" : "in");
+   if (device_active(dev)) {
+   struct video_priv *upriv = dev_get_uclass_priv(dev);
+   struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+
+   bdinfo_test_num_ll(uts, "FB base", (ulong)upriv->fb);
+   if (upriv->copy_fb) {
+   bdinfo_test_num_ll(uts, "FB copy",
+  (ulong)upriv->copy_fb);
+   bdinfo_test_num_l(uts, " copy size",
+ plat->copy_size);
+   }
+   ut_assert_nextline("%-12s= %dx%dx%d", "FB size",
+  upriv->xsize, upriv->ysize,
+  1 << upriv->bpix);
+   }
+   }
+}
+
+static void lmb_test_dump_region(struct unit_test_state *uts,
+struct lmb_region *rgn, char *name)
+{
+   unsigned long long base, size, end;
+   enum lmb_flags flags;
+   int i;
+
+   ut_assert_nextline(" %s.cnt = 0x%lx / max = 0x%lx", name, rgn->cnt, 
rgn->max);
+
+   for (i = 0; i < rgn->cnt; i++) {
+   base = rgn->region[i].base;
+   size = rgn->region[i].size;
+   end = base + size - 1;
+   flags = rgn->region[i].flags;
+
+   ut_assert_nextline(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes 
flags: %x",
+  name, i, base, end, size, flags);
+   }
+}
+
+static void 

[PATCH 3/4] cmd: bdinfo: Print ethaddr of current MAC

[Marek Vasut]

Instead of always printing ethaddr of MAC 0, print eth%daddr of the current MAC.

Signed-off-by: Marek Vasut 
---
Cc: Jason Liu 
Cc: Michal Simek 
Cc: Ovidiu Panait 
Cc: Simon Glass 
---
 cmd/bdinfo.c | 20 +---
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 71a122466b0..365357ca545 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -42,19 +42,25 @@ void bdinfo_print_num_ll(const char *name, unsigned long 
long value)
printf("%-12s= 0x%.*llx\n", name, 2 * (int)sizeof(ulong), value);
 }
 
-static void print_eth(int idx)
+static void print_eth(void)
 {
-   char name[10], *val;
+   const int idx = eth_get_dev_index();
+   uchar enetaddr[6];
+   char name[10];
+   int ret;
+
if (idx)
sprintf(name, "eth%iaddr", idx);
else
strcpy(name, "ethaddr");
-   val = env_get(name);
-   if (!val)
-   val = "(not set)";
+
+   ret = eth_env_get_enetaddr_by_index("eth", idx, enetaddr);
 
printf("current eth = %s\n", eth_get_name());
-   printf("%-12s= %s\n", name, val);
+   if (!ret)
+   printf("%-12s= (not set)\n", name);
+   else
+   printf("%-12s= %pM\n", name, enetaddr);
printf("IP addr = %s\n", env_get("ipaddr"));
 }
 
@@ -128,7 +134,7 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, 
char *const argv[])
bdinfo_print_num_l("reloc off", gd->reloc_off);
printf("%-12s= %u-bit\n", "Build", (uint)sizeof(void *) * 8);
if (IS_ENABLED(CONFIG_CMD_NET))
-   print_eth(0);
+   print_eth();
bdinfo_print_num_l("fdt_blob", (ulong)map_to_sysmem(gd->fdt_blob));
bdinfo_print_num_l("new_fdt", (ulong)map_to_sysmem(gd->new_fdt));
bdinfo_print_num_l("fdt_size", (ulong)gd->fdt_size);
-- 
2.39.2

[PATCH 2/4] cmd: bdinfo: Wrap network information printing into print_eth()

[Marek Vasut]

Move all the network information printing into print_eth(),
no functional change.

Signed-off-by: Marek Vasut 
---
Cc: Jason Liu 
Cc: Michal Simek 
Cc: Ovidiu Panait 
Cc: Simon Glass 
---
 cmd/bdinfo.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 78cb41f0760..71a122466b0 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -52,7 +52,10 @@ static void print_eth(int idx)
val = env_get(name);
if (!val)
val = "(not set)";
+
+   printf("current eth = %s\n", eth_get_name());
printf("%-12s= %s\n", name, val);
+   printf("IP addr = %s\n", env_get("ipaddr"));
 }
 
 void bdinfo_print_mhz(const char *name, unsigned long hz)
@@ -124,11 +127,8 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, 
char *const argv[])
bdinfo_print_num_l("relocaddr", gd->relocaddr);
bdinfo_print_num_l("reloc off", gd->reloc_off);
printf("%-12s= %u-bit\n", "Build", (uint)sizeof(void *) * 8);
-   if (IS_ENABLED(CONFIG_CMD_NET)) {
-   printf("current eth = %s\n", eth_get_name());
+   if (IS_ENABLED(CONFIG_CMD_NET))
print_eth(0);
-   printf("IP addr = %s\n", env_get("ipaddr"));
-   }
bdinfo_print_num_l("fdt_blob", (ulong)map_to_sysmem(gd->fdt_blob));
bdinfo_print_num_l("new_fdt", (ulong)map_to_sysmem(gd->new_fdt));
bdinfo_print_num_l("fdt_size", (ulong)gd->fdt_size);
-- 
2.39.2

[PATCH 1/4] cmd: bdinfo: Map fdt_blob and new_fdt to sysmem

[Marek Vasut]

Map fdt_blob and new_fdt to sysmem, otherwise $fdtcontroladdr
and bdinfo output do not match and the bdinfo output address
is not a valid address accessible via sandbox memory accessors.

Signed-off-by: Marek Vasut 
---
Cc: Jason Liu 
Cc: Michal Simek 
Cc: Ovidiu Panait 
Cc: Simon Glass 
---
 cmd/bdinfo.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index f709904c516..78cb41f0760 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -128,8 +129,8 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, 
char *const argv[])
print_eth(0);
printf("IP addr = %s\n", env_get("ipaddr"));
}
-   bdinfo_print_num_l("fdt_blob", (ulong)gd->fdt_blob);
-   bdinfo_print_num_l("new_fdt", (ulong)gd->new_fdt);
+   bdinfo_print_num_l("fdt_blob", (ulong)map_to_sysmem(gd->fdt_blob));
+   bdinfo_print_num_l("new_fdt", (ulong)map_to_sysmem(gd->new_fdt));
bdinfo_print_num_l("fdt_size", (ulong)gd->fdt_size);
if (IS_ENABLED(CONFIG_VIDEO))
show_video_info();
-- 
2.39.2

[PATCH] test: fdt: Fix copyright message

[Marek Vasut]

Drop the map_to_sysmem() copy paste error. No functional change.

Signed-off-by: Marek Vasut 
---
Cc: Jason Liu 
Cc: Michal Simek 
Cc: Ovidiu Panait 
Cc: Simon Glass 
---
 test/cmd/fdt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/test/cmd/fdt.c b/test/cmd/fdt.c
index 7835da232d5..1f103a1d7eb 100644
--- a/test/cmd/fdt.c
+++ b/test/cmd/fdt.c
@@ -2,7 +2,7 @@
 /*
  * Tests for fdt command
  *
- * Copyright 2022 Google LLCmap_to_sysmem(fdt));
+ * Copyright 2022 Google LLC
  */
 
 #include 
-- 
2.39.2