Re: [RFC PATCH v1 5/5] board: amlogic: add support for AD401 board
On 24/04/2023 20:01, Igor Prusov wrote:
The AD401 board is the Amlogic A1 SoC reference board
Signed-off-by: Igor Prusov
---
MAINTAINERS | 1 +
arch/arm/mach-meson/Kconfig | 1 +
board/amlogic/ad401/Makefile | 4 +++
board/amlogic/ad401/ad401.c | 15 ++
configs/ad401_defconfig | 54
5 files changed, 75 insertions(+)
create mode 100644 board/amlogic/ad401/Makefile
create mode 100644 board/amlogic/ad401/ad401.c
create mode 100644 configs/ad401_defconfig
diff --git a/MAINTAINERS b/MAINTAINERS
index 02a5a8682f..6860309896 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -150,6 +150,7 @@ L: u-boot-amlo...@groups.io
T:git https://source.denx.de/u-boot/custodians/u-boot-amlogic.git
F:arch/arm/mach-meson/
F:arch/arm/include/asm/arch-meson/
+F: board/amlogic/
Boards MAINTAINERS are separate, so please add a separate MAINTAINERS
file in board/amlogic/ad401/, you can add me ad maintainer like other
boards.
F:cmd/meson/
F:drivers/clk/meson/
F:drivers/serial/serial_meson.c
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 519ed563c0..669ca09a00 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -75,6 +75,7 @@ config SYS_VENDOR
config SYS_BOARD
string "Board name"
+ default "ad401" if MESON_A1
default "p200" if MESON_GXBB
default "p212" if MESON_GXL
default "q200" if MESON_GXM
diff --git a/board/amlogic/ad401/Makefile b/board/amlogic/ad401/Makefile
new file mode 100644
index 00..e65c1215f6
--- /dev/null
+++ b/board/amlogic/ad401/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2023 SberDevices, Inc.
+
+obj-y := ad401.o
diff --git a/board/amlogic/ad401/ad401.c b/board/amlogic/ad401/ad401.c
new file mode 100644
index 00..356b2880bd
--- /dev/null
+++ b/board/amlogic/ad401/ad401.c
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023 SberDevices, Inc.
+ * Author: Igor Prusov
+ */
+
+#include
+#include
+
+int misc_init_r(void)
+{
+ meson_generate_serial_ethaddr();
+
+ return 0;
+}
diff --git a/configs/ad401_defconfig b/configs/ad401_defconfig
new file mode 100644
index 00..529e553bac
--- /dev/null
+++ b/configs/ad401_defconfig
@@ -0,0 +1,54 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x0020
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-a1-ad401"
+CONFIG_SYS_PROMPT="ad401 # "
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_MESON_A1=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SYS_LOAD_ADDR=0x0
+CONFIG_DEBUG_UART=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_LED=y
+CONFIG_MISC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_A1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_WDT=y
With MAINTAINERS file in board dir:
Reviewed-by: Neil Armstrong
Re: [RFC PATCH v1 4/5] pinctrl: meson: add pinctrl driver for Amlogic A1
On 24/04/2023 20:01, Igor Prusov wrote:
Based on Linux kernel commit:
dabad1ff85611 (pinctrl: meson: add pinctrl driver support for Meson-A1 SoC)
Signed-off-by: Igor Prusov
---
drivers/pinctrl/meson/Kconfig| 4 +
drivers/pinctrl/meson/Makefile | 1 +
drivers/pinctrl/meson/pinctrl-meson-a1.c | 867 +++
3 files changed, 872 insertions(+)
create mode 100644 drivers/pinctrl/meson/pinctrl-meson-a1.c
diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index ef02087ed2..97e574330f 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -29,4 +29,8 @@ config PINCTRL_MESON_G12A
bool "Amlogic Meson G12a SoC pinctrl driver"
select PINCTRL_MESON_AXG_PMX
+config PINCTRL_MESON_A1
+ bool "Amlogic Meson A1 SoC pinctrl driver"
+ select PINCTRL_MESON_AXG_PMX
+
endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index 80dba65e1b..8d10d027ac 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_PINCTRL_MESON_GXBB)+= pinctrl-meson-gxbb.o
obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
+obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson-a1.c
b/drivers/pinctrl/meson/pinctrl-meson-a1.c
new file mode 100644
index 00..30cf3bc0be
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-a1.c
@@ -0,0 +1,867 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Qianggui Song
+ * Copyright (C) 2023 SberDevices, Inc.
+ * Author: Igor Prusov
+ */
+
+#include
+#include
+#include
+#include
+
+#include "pinctrl-meson.h"
+#include "pinctrl-meson-axg.h"
+
+/* psram */
+static const unsigned int psram_clkn_pins[]= { GPIOP_0 };
+static const unsigned int psram_clkp_pins[]= { GPIOP_1 };
+static const unsigned int psram_ce_n_pins[]= { GPIOP_2 };
+static const unsigned int psram_rst_n_pins[] = { GPIOP_3 };
+static const unsigned int psram_adq0_pins[]= { GPIOP_4 };
+static const unsigned int psram_adq1_pins[]= { GPIOP_5 };
+static const unsigned int psram_adq2_pins[]= { GPIOP_6 };
+static const unsigned int psram_adq3_pins[]= { GPIOP_7 };
+static const unsigned int psram_adq4_pins[]= { GPIOP_8 };
+static const unsigned int psram_adq5_pins[]= { GPIOP_9 };
+static const unsigned int psram_adq6_pins[]= { GPIOP_10 };
+static const unsigned int psram_adq7_pins[]= { GPIOP_11 };
+static const unsigned int psram_dqs_dm_pins[] = { GPIOP_12 };
+
+/* sdcard */
+static const unsigned int sdcard_d0_b_pins[] = { GPIOB_0 };
+static const unsigned int sdcard_d1_b_pins[] = { GPIOB_1 };
+static const unsigned int sdcard_d2_b_pins[] = { GPIOB_2 };
+static const unsigned int sdcard_d3_b_pins[] = { GPIOB_3 };
+static const unsigned int sdcard_clk_b_pins[] = { GPIOB_4 };
+static const unsigned int sdcard_cmd_b_pins[] = { GPIOB_5 };
+
+static const unsigned int sdcard_d0_x_pins[] = { GPIOX_0 };
+static const unsigned int sdcard_d1_x_pins[] = { GPIOX_1 };
+static const unsigned int sdcard_d2_x_pins[] = { GPIOX_2 };
+static const unsigned int sdcard_d3_x_pins[] = { GPIOX_3 };
+static const unsigned int sdcard_clk_x_pins[] = { GPIOX_4 };
+static const unsigned int sdcard_cmd_x_pins[] = { GPIOX_5 };
+
+/* spif */
+static const unsigned int spif_mo_pins[] = { GPIOB_0 };
+static const unsigned int spif_mi_pins[] = { GPIOB_1 };
+static const unsigned int spif_wp_n_pins[] = { GPIOB_2 };
+static const unsigned int spif_hold_n_pins[] = { GPIOB_3 };
+static const unsigned int spif_clk_pins[] = { GPIOB_4 };
+static const unsigned int spif_cs_pins[] = { GPIOB_5 };
+
+/* i2c0 */
+static const unsigned int i2c0_sck_f9_pins[] = { GPIOF_9 };
+static const unsigned int i2c0_sda_f10_pins[] = { GPIOF_10 };
+static const unsigned int i2c0_sck_f11_pins[] = { GPIOF_11 };
+static const unsigned int i2c0_sda_f12_pins[] = { GPIOF_12 };
+
+/* i2c1 */
+static const unsigned int i2c1_sda_x_pins[]= { GPIOX_9 };
+static const unsigned int i2c1_sck_x_pins[]= { GPIOX_10 };
+static const unsigned int i2c1_sda_a_pins[]= { GPIOA_10 };
+static const unsigned int i2c1_sck_a_pins[]= { GPIOA_11 };
+
+/* i2c2 */
+static const unsigned int i2c2_sck_x0_pins[] = { GPIOX_0 };
+static const unsigned int i2c2_sda_x1_pins[] = { GPIOX_1 };
+static const
Re: [RFC PATCH v1 3/5] ARM: meson: add A1 support
On 24/04/2023 20:01, Igor Prusov wrote:
Add support for Amlogic A1 SoC family.
Signed-off-by: Igor Prusov
Signed-off-by: Evgeny Bachinin
---
arch/arm/include/asm/arch-meson/a1.h | 20 ++
arch/arm/mach-meson/Kconfig | 6 +++
arch/arm/mach-meson/Makefile | 1 +
arch/arm/mach-meson/board-a1.c | 59
include/configs/meson64.h| 3 ++
5 files changed, 89 insertions(+)
create mode 100644 arch/arm/include/asm/arch-meson/a1.h
create mode 100644 arch/arm/mach-meson/board-a1.c
diff --git a/arch/arm/include/asm/arch-meson/a1.h
b/arch/arm/include/asm/arch-meson/a1.h
new file mode 100644
index 00..86d1a68de8
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/a1.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2023 SberDevices, Inc.
+ * Author: Igor Prusov
+ */
+
+#ifndef __MESON_A1_H__
+#define __MESON_A1_H__
+
+#define A1_SYSCTRL_BASE0xfe005800
+
+/* SYSCTRL registers */
+#define A1_SYSCTRL_ADDR(off) (A1_SYSCTRL_BASE + ((off) << 2))
+
+#define A1_SYSCTRL_SEC_STATUS_REG4 A1_SYSCTRL_ADDR(0xc4)
+
+#define A1_SYSCTRL_MEM_SIZE_MASK 0x
+#define A1_SYSCTRL_MEM_SIZE_SHIFT 16
+
+#endif /* __MESON_A1_H__ */
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 6cba2c40dd..519ed563c0 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -51,6 +51,12 @@ config MESON_G12A
help
Select this if your SoC is an S905X/D2
+config MESON_A1
+ bool "A1"
+ select MESON64_COMMON
+ help
+ Select this if your SoC is an A113L
+
endchoice
config SYS_SOC
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
index a9e4046f80..535b0878b9 100644
--- a/arch/arm/mach-meson/Makefile
+++ b/arch/arm/mach-meson/Makefile
@@ -6,3 +6,4 @@ obj-y += board-common.o sm.o board-info.o
obj-$(CONFIG_MESON_GX) += board-gx.o
obj-$(CONFIG_MESON_AXG) += board-axg.o
obj-$(CONFIG_MESON_G12A) += board-g12a.o
+obj-$(CONFIG_MESON_A1) += board-a1.o
diff --git a/arch/arm/mach-meson/board-a1.c b/arch/arm/mach-meson/board-a1.c
new file mode 100644
index 00..967bb67182
--- /dev/null
+++ b/arch/arm/mach-meson/board-a1.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023 SberDevices, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+phys_size_t get_effective_memsize(void)
+{
+ return ((readl(A1_SYSCTRL_SEC_STATUS_REG4) & A1_SYSCTRL_MEM_SIZE_MASK)
+ >> A1_SYSCTRL_MEM_SIZE_SHIFT) * SZ_1M;
+}
+
+void meson_init_reserved_memory(__maybe_unused void *fdt)
+{
+}
+
+int meson_get_boot_device(void)
+{
+ return -ENOSYS;
+}
+
+static struct mm_region a1_mem_map[] = {
+ {
+ .virt = 0xUL,
+ .phys = 0xUL,
+ .size = 0x8000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x8000UL,
+ .phys = 0x8000UL,
+ .size = 0x7FE0UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /*
+* This mem region contains in/out shared memory with bl31,
+* hence it's marked as NORMAL memory type
+*/
+ .virt = 0xFFE0UL,
+ .phys = 0xFFE0UL,
+ .size = 0x0020UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = a1_mem_map;
diff --git a/include/configs/meson64.h b/include/configs/meson64.h
index 9244601284..801cdae470 100644
--- a/include/configs/meson64.h
+++ b/include/configs/meson64.h
@@ -11,6 +11,9 @@
#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
#define GICD_BASE 0xffc01000
#define GICC_BASE 0xffc02000
+#elif defined(CONFIG_MESON_A1)
+#define GICD_BASE 0xff901000
+#define GICC_BASE 0xff902000
#else /* MESON GXL and GXBB */
#define GICD_BASE 0xc4301000
#define GICC_BASE 0xc4302000
Reviewed-by: Neil Armstrong
Re: [RFC PATCH v1 2/5] ARM: dts: sync meson-a1-ad401 from Linux 6.3-rc7
On 24/04/2023 20:01, Igor Prusov wrote:
Add meson-a1-ad401.dts file from Linux 6.3-rc7
Signed-off-by: Igor Prusov
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/meson-a1-ad401.dts | 30 ++
2 files changed, 31 insertions(+)
create mode 100644 arch/arm/dts/meson-a1-ad401.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3385948d22..8de35c5454 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -185,6 +185,7 @@ dtb-$(CONFIG_ARCH_S5P4418) += \
s5p4418-nanopi2.dtb
dtb-$(CONFIG_ARCH_MESON) += \
+ meson-a1-ad401.dtb \
meson-axg-s400.dtb \
meson-axg-jethome-jethub-j100.dtb \
meson-gxbb-nanopi-k2.dtb \
diff --git a/arch/arm/dts/meson-a1-ad401.dts b/arch/arm/dts/meson-a1-ad401.dts
new file mode 100644
index 00..69c25c68c3
--- /dev/null
+++ b/arch/arm/dts/meson-a1-ad401.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-a1.dtsi"
+
+/ {
+ compatible = "amlogic,ad401", "amlogic,a1";
+ model = "Amlogic Meson A1 AD401 Development Board";
+
+ aliases {
+ serial0 = &uart_AO_B;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x800>;
+ };
+};
+
+&uart_AO_B {
+ status = "okay";
+};
Reviewed-by: Neil Armstrong
Re: [RFC PATCH v1 1/5] ARM: dts: Add Amlogic Meson A1 DT from Linux 6.3-rc7
On 24/04/2023 20:01, Igor Prusov wrote:
Import Linux 6.3-rc7 Device tree and necessary bindings for Amlogic A1
board from 6a8f57ae2eb0 ("Linux 6.3-rc7").
Signed-off-by: Igor Prusov
---
arch/arm/dts/meson-a1.dtsi | 161 +++
include/dt-bindings/gpio/meson-a1-gpio.h | 73 ++
2 files changed, 234 insertions(+)
create mode 100644 arch/arm/dts/meson-a1.dtsi
create mode 100644 include/dt-bindings/gpio/meson-a1-gpio.h
diff --git a/arch/arm/dts/meson-a1.dtsi b/arch/arm/dts/meson-a1.dtsi
new file mode 100644
index 00..6509329b85
--- /dev/null
+++ b/arch/arm/dts/meson-a1.dtsi
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include
+#include
+#include
+
+/ {
+ compatible = "amlogic,a1";
+
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x80>;
+ alignment = <0x0 0x40>;
+ linux,cma-default;
+ };
+ };
+
+ sm: secure-monitor {
+ compatible = "amlogic,meson-gxbb-sm";
+
+ pwrc: power-controller {
+ compatible = "amlogic,meson-a1-pwrc";
+ #power-domain-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ apb: bus@fe00 {
+ compatible = "simple-bus";
+ reg = <0x0 0xfe00 0x0 0x100>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xfe00 0x0 0x100>;
+
+ reset: reset-controller@0 {
+ compatible = "amlogic,meson-a1-reset";
+ reg = <0x0 0x0 0x0 0x8c>;
+ #reset-cells = <1>;
+ };
+
+ periphs_pinctrl: pinctrl@400 {
+ compatible = "amlogic,meson-a1-periphs-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio: bank@400 {
+ reg = <0x0 0x0400 0x0 0x003c>,
+ <0x0 0x0480 0x0 0x0118>;
+ reg-names = "mux", "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 0 62>;
+ };
+
+ };
+
+ uart_AO: serial@1c00 {
+ compatible = "amlogic,meson-gx-uart",
+"amlogic,meson-ao-uart";
+ reg = <0x0 0x1c00 0x0 0x18>;
+ interrupts = ;
+ clocks = <&xtal>, <&xtal>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+ status = "disabled";
+ };
+
+ uart_AO_B: serial@2000 {
+ compatible = "amlogic,meson-gx-uart",
+"amlogic,meson-ao-uart";
+ reg = <0x0 0x2000 0x0 0x18>;
+ interrupts = ;
+ clocks = <&xtal>, <&xt
Re: [PATCH 2/2] CI: Make use of buildman requirements.txt
Hi Tom On 04/05/23 18:32, Tom Rini wrote: On Thu, May 04, 2023 at 09:42:54AM +0530, Neha Malcom Francis wrote: Hi Tom, On 03/05/23 18:34, Tom Rini wrote: On Wed, May 03, 2023 at 11:27:20AM +0530, Neha Malcom Francis wrote: Hi Tom Thanks for these patches! On 27/04/23 01:14, Tom Rini wrote: Now that buildman has a requirements.txt file we need to make use of it. Signed-off-by: Tom Rini --- .azure-pipelines.yml | 3 +++ .gitlab-ci.yml | 4 2 files changed, 7 insertions(+) However, while trying to ensure CI/CD coverage, I'm running into this " error 'No module named 'jsonschema'" for am62ax [1], any idea why after building successfully for other devices? [1] https://dev.azure.com/u-boot/u-boot/_build/results?buildId=6236&view=logs&jobId=6fe7c803-7a3b-5b46-f057-c1c62fd89ba1&j=22dc4ac5-ae35-5978-08ac-5f386151834e&t=fae48c67-4bb5-5f06-119f-00d23f780e3c o We need to have the requirements.txt file installed in any job that's using this part of binman now and I guess my patch above wasn't complete? I didn't fully check what happened on Azure due to the other problems (ie iot2050 boards not building). Probably, I'm not sure about how to rectify this. Could you have a look if possible? Regarding iot2050, I have started working on it. I see it now. The "script" section at the bottom of .azure-pipelines.yml needs the pip install as well, I had missed that. Go ahead and take that up with your reposting of the series :) Thanks for catching that! Will add it in -- Thanking You Neha Malcom Francis
Re: [PATCH 1/1] arm64: dts: ti: k3-j721s2: Add reserved status in msmc
On 5/3/2023 8:21 PM, Nishanth Menon wrote: On 20:17-20230503, Udit Kumar wrote: Mark atf, l3-cache and tifs node as reserved. why? (I am not reading the cover-letter for a 1 patch) My bad , I should have description in patch itself. Thanks [...] 2.34.1
Re: [EXTERNAL] [PATCH v3 25/43] x86: Pass video settings from SPL to U-Boot proper
On 05/05/23 04:28, Simon Glass wrote: When video is set up in SPL, U-Boot proper needs to use the correct parameters so it can write to the display. Put these in a bloblist so they are available to U-Boot proper. Signed-off-by: Simon Glass --- Changes in v3: - Add a tag name for the blob common/bloblist.c | 1 + drivers/pci/pci_rom.c | 78 +++ include/bloblist.h| 1 + include/video.h | 24 + 4 files changed, 83 insertions(+), 21 deletions(-) Reviewed-by: Nikhil M Jain
[GIT PULL] please pull fsl-qoirq-2023-5-5
Hi Tom, Please pull fsl-qoirq-2023-5-5 -- fsl-ls1088a device tree update enable DM_SERIAL for ten64 check for crypto node first in fdt_fixup_remove_jr -- CI: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq/-/pipelines/16253 Thanks, Peng. The following changes since commit 7f30eec1779b8f641b9563a1dab6a6865916ec01: Merge branch '2023-05-03-assorted-updates-and-fixes' (2023-05-04 11:49:30 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git tags/fsl-qoirq-2023-5-5 for you to fetch changes up to fb9df2c7c50324abb0625140edfeb3ae72817a49: arm: dts: ten64: fix header typo and update copyright (2023-05-05 09:46:04 +0800) Mathew McBride (18): armv8: fsl-layerscape: check for crypto node first in fdt_fixup_remove_jr configs: ten64: enable DM_SERIAL arm: dts: fsl-ls1088a: move u-boot bootph tags into u-boot only files arm: dts: fsl-ls1088a: move memory node into U-Boot specific file pci: layerscape: add support for kernel/official fsl, ls1088a-pcie binding arm: dts: fsl-ls1088a: import and sync full SMMU nodes with Linux arm: dts: fsl-ls1088a: sync PCIe controller definition with Linux arm: dts: fsl-ls1088a: match Linux FDT by disabling PCIe by default arm: dts: fsl-ls1088a: import CPU definition from Linux kernel arm: dts: fsl-ls1088a: move GPIO controller under "soc" per Linux arm: dts: fsl-ls1088a: move I2C nodes under "soc" and syncronize with Linux arm: dts: fsl-ls1088a: sync usb controller nodes with Linux arm: dts: fsl-ls1088a: syncronise MDIO+PCS U-Boot definitions with Linux arm: dts: fsl-ls1088a: syncronise fsl-mc definition with Linux arm: dts: fsl-ls1088a: move and sync existing bindings to be under /soc arm: dts: fsl-ls1088a: copy all missing bindings from Linux arm: dts: ten64: syncronise device tree with Linux arm: dts: ten64: fix header typo and update copyright arch/arm/cpu/armv8/fsl-layerscape/fdt.c|4 + arch/arm/dts/fsl-ls1088a-qds-u-boot.dtsi |5 + arch/arm/dts/fsl-ls1088a-rdb-u-boot.dtsi |5 + arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi | 18 ++ arch/arm/dts/fsl-ls1088a-ten64.dts | 61 ++--- arch/arm/dts/fsl-ls1088a-u-boot.dtsi | 63 ++ arch/arm/dts/fsl-ls1088a.dtsi | 1216 +++--- configs/ten64_tfa_defconfig|4 +- drivers/pci/pcie_layerscape_rc.c |1 + 9 files changed, 1067 insertions(+), 310 deletions(-) create mode 100644 arch/arm/dts/fsl-ls1088a-qds-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-ls1088a-rdb-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-ls1088a-u-boot.dtsi
Re: Pull Request / Patch: Enable Usage of ECC with DDR on AM654x
On Thu, May 04, 2023 at 12:47:29PM +, Roytburd, Benjamin wrote: o > Hello, > > Recently, when working with the AM65x_GP_EVM development board, I found that > the U-boot source code (specifically the SPL), does not properly initialize > the DDRSS ram drivers for the AM6548. There are missing register writes that > are required from DDR to function with ECC on. > > I validated this by comparing what U-boot source code does to Texas > Instrument DDR test scripts (known as GEL scripts), and these GEL scripts > could properly initialize DDR with ECC while U-boot could not, this is due to > the missing register writes. The changes are shown here in this pull request: > https://github.com/u-boot/u-boot/pull/289 (made just to check CI). > > Should I submit a patch for this? I have not contributed to U-boot before and > would like to know if such a change would be accepted, or even reviewed, as a > submission. Yes, please submit a patch for it and cc the people that the scripts/get_maintainer.pl script suggests, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 3/3] configs: j7200: Merge the HS and non-HS defconfigs
On Thu, May 04, 2023 at 11:07:08AM +0530, Manorit Chawdhry wrote: > K3 devices have runtime type board detection. Make the default defconfig > include the secure configuration. Then remove the HS specific config. > > Non-HS devices will continue to boot due to runtime device type detection. > If TI_SECURE_DEV_PKG is not set the build will emit warnings, for non-HS > devices these can be ignored. > > Reviewed-by: Kamlesh Gurudasani > Signed-off-by: Manorit Chawdhry Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 2/3] Kconfig: j721s2: Change K3_MCU_SCRATCHPAD_BASE to non firewalled region
On Thu, May 04, 2023 at 11:07:07AM +0530, Manorit Chawdhry wrote: > On K3 HS-SE devices all the firewalls are locked by default > until sysfw comes up. Rom configures some of the firewall for its usage > along with the SRAM for R5 but the PSRAM region is still locked. > > The K3 MCU Scratchpad for j721s2 was set to a PSRAM region triggering the > firewall exception before sysfw came up. The exception started happening > after adding multi dtb support that accesses the scratchpad for reading > EEPROM contents. > > Old map: > ┌─┐ 0x41c0 > │ SPL │ > ├─┤ 0x41c61f20 (approx) > │STACK│ > ├─┤ 0x41c65f20 > │ Global data │ > │ sizeof(struct global_data) = 0xd8 │ > ├─┤ gd->malloc_base = 0x41c66000 > │HEAP │ > │ CONFIG_SYS_MALLOC_F_LEN = 0x1 │ > ├─┤ CONFIG_SPL_BSS_START_ADDR > │ SPL BSS │ (0x41c76000) > │ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │ > ├─┤ (0x41c8) > │ DM DATA │ > ├─┤ (0x41c84130) (approx) > │EMPTY│ > └─┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX > (0x41cffbfc) > > New map: > ┌─┐ 0x41c0 > │ SPL │ > ├─┤ 0x41c61f20 (approx) > │STACK│ > ├─┤ 0x41c65f20 > │ Global data │ > │ sizeof(struct global_data) = 0xd8 │ > ├─┤ gd->malloc_base = 0x41c66000 > │HEAP │ > │ CONFIG_SYS_MALLOC_F_LEN = 0x1 │ > ├─┤ CONFIG_SPL_BSS_START_ADDR > │ SPL BSS │ (0x41c76000) > │ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │ > ├─┤ (0x41c8) > │ DM DATA │ > ├─┤ (0x41c84130) (approx) > │EMPTY│ > ├─┤ SYS_K3_MCU_SCRATCHPAD_BASE > │ SCRATCHPAD │ (0x41cff9fc) > │ SYS_K3_MCU_SCRATCHPAD_SIZE = 0x200 │ > └─┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX > (0x41cffbfc) > > Reviewed-by: Kamlesh Gurudasani > Signed-off-by: Manorit Chawdhry Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 1/3] configs: j721s2: Merge the HS and non-HS defconfigs
On Thu, May 04, 2023 at 11:07:06AM +0530, Manorit Chawdhry wrote: > K3 devices have runtime type board detection. Make the default defconfig > include the secure configuration. Then remove the HS specific config. > > Non-HS devices will continue to boot due to runtime device type detection. > If TI_SECURE_DEV_PKG is not set the build will emit warnings, for non-HS > devices these can be ignored. > > Reviewed-by: Kamlesh Gurudasani > Signed-off-by: Manorit Chawdhry Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] arm: dts: iot2050: Include u-boot specific bits implicitly
On Tue, Apr 25, 2023 at 09:28:23PM +0200, Jan Kiszka wrote: > From: Jan Kiszka > > Create *-u-boot.dtsi files for each target dtb of the IOT2050 series so > that we can drop the #include deviations from upstream dts[i] files > here. > > Signed-off-by: Jan Kiszka Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] environment: ti: Add get_fit_config command to get FIT config string
On Tue, Apr 25, 2023 at 11:20:45AM -0500, Andrew Davis wrote: > When OE is packaging a dtb file into the FIT image it names the node based > on the dtb filename. Node names can't have "/" so it is turned into "_". > We select our FIT config using the "fdtfile" env var so we don't duplicate > the board_name to fdt logic. Result is fdtfile needs mangled when used to > select a config node from OE made FIT image. Do this here. > > Signed-off-by: Andrew Davis > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] configs: am62x: enable secure device configs by default
On Wed, Apr 05, 2023 at 05:40:47PM -0500, Praneeth Bajjuri wrote: > Enable the CONFIG_TI_SECURE_DEVICE by default > > Non-HS devices will continue to boot due to runtime device type detection. > > TI's security enforcing SoCs will authenticate each binary it loads by > comparing it's signature with keys etched into the SoC during the boot > up process. The am62x family of SoCs by default will have some level of > security enforcement checking. To keep things as simple as possible, > enable the CONFIG_TI_SECURE_DEVICE options by default so all levels of > secure SoCs will work out of the box > > Signed-off-by: Praneeth Bajjuri > Signed-off-by: Kamlesh Gurudasani > Signed-off-by: Bryan Brattlof Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 0/2] Update DDR configs to latest tested version
On Tue, 25 Apr 2023 18:39:26 +0530, Neha Malcom Francis wrote: > This series aims to update the DDR dtsi files that are generated by the > Jacinto 7 DDRSS Configuration tool. > > It updates J721E and J7200 to generated files of two different versions > of the same tool as these are the latest ones that have been thoroughly > tested with U-Boot on each device internally. Thus it is best to update to > that version for each instead of: A. sticking with the current old version > or B. updating to the very latest version that hasn't been tested on > U-Boot. > > [...] Applied to u-boot/master, thanks! -- Tom
Re: [PATCH] k3: pmic: Clear ESM masks
On Wed, Apr 05, 2023 at 04:24:35PM +0530, Neha Malcom Francis wrote: > ESM MCU masks must be set to 0h so that PMIC can handle errors > that require attention for example SYS_SAFETY_ERRn. The required bits > must be cleared: ESM_MCU_RST_MASK, ESM_MCU_FAIL_MASK, ESM_MCU_PIN_MASK. > > If PMIC expected to handle errors, make sure EVM is configured to > connect SOC_SAFETY_ERRz (Main) to the PMIC. > > Note that even though the User Guide for TPS65941 for J721E mentions > that these bits are reset to 0h; it is not reflected once board boots to > kernel, possibly due to NVM configurations. Eithercase, it is best to > account for this from R5 SPL side as well. > > Signed-off-by: Neha Malcom Francis Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH V9 00/14] Add splash screen support at u-boot SPL
On Thu, May 04, 2023 at 06:40:56PM -0600, Simon Glass wrote: > Hi, > > On Thu, 20 Apr 2023 at 06:11, Nikhil M Jain wrote: > > > > To enable splash screen at SPL stage move video driver and splash screen > > framework at SPL, which will bring up image on display very quickly and > > thus have early display support in SPL. > > > > Changes in V9 > > - Update as per review comments. > > - Add Reviewed-by tag in appropriate patch. > > > > Changes in V8 > > - Update as per review comments. > > > > Changes in V7 > > - Replace #ifdefs' and #ifs' with if in common/splash and common/bmp. > > - Add Reviewed-by and Tested-by tag in apprpriate patch. > > > > Changes in V6 > > - Fix commit messages. > > - Fix compile rules for video related files in patch > > drivers: video: Makefile: Rule to compile necessary video driver > > files. > > > > Changes in V5 > > - Drop patch cmd: Makefile: Rule to compile bmp_cmd. > > - Squash common: splash: Replace CONFIG_CMD_BMP patch into patches > > common: Enable splash functions at SPL > > include: Enable video related global data variable and splash at SPL > > - Fix merge issue for next branch. > > - Replace cmd/bmp_cmd with cmd/bmp. > > - Use CONFIG_$(SPL_TPL_) to compile files in > > drivers: video: Makefile: Rule to compile necessary video driver files. > > - Add Reviewed-by tag in appropriate patch. > > > > Changes in V4 > > - Add Reviewed-by tag in appropriate patch. > > > > Changes in V3 > > - Add separate video configs for SPL splash screen. > > - Add rule to compile video driver in drivers/Makefile at SPL. > > - Add rule to compile splash.c and splash_source.c. > > - Squash drivers: video: video-uclass: Disable u-boot logo at SPL into > > drivers: video: Use CONFIG_IS_ENABLED and CONFIG_VAL. > > - Split cmd/bmp.c to separate bmp functions and commands. > > - Add CONFIG_BMP and CONFIG_SPL_BMP. > > - Add rule to compile necessary files required for video driver. > > - Add rule to compile common/bmp.c. > > > > Changes in V2 > > - Removed artifacts from bad patch apply. > > > > Nikhil M Jain (14): > > drivers: video: Kconfig: Add configs for enabling video at SPL > > drivers: video: tidss: Kconfig: Configs to enable TIDSS at SPL > > drivers: Makefile: Add rule to compile video driver > > drivers: video: Makefile: Rule to compile necessary video driver files > > drivers: video: tidss: Makefile: Add condition to compile TIDSS at SPL > > common: Makefile: Add rule to compile splash and splash_source at SPL > > common: Kconfig: Add BMP configs > > cmd: bmp: Split bmp commands and functions > > common: Makefile: Rule to compile bmp.c > > drivers: video: Enable necessary video functions at SPL > > common: Enable splash functions at SPL > > include: Enable video related global data variable and splash at SPL > > board: ti: am62x: evm: OSPI support for splash screen > > common: Replace #ifdef and #if with if's > > > > board/ti/am62x/evm.c | 8 +- > > cmd/bmp.c | 162 +- > > common/Kconfig| 12 ++ > > common/Makefile | 3 + > > common/bmp.c | 149 > > common/splash.c | 20 +-- > > drivers/Makefile | 1 + > > drivers/video/Kconfig | 223 +- > > drivers/video/Makefile| 16 +-- > > drivers/video/console_core.c | 6 +- > > drivers/video/tidss/Kconfig | 6 + > > drivers/video/tidss/Makefile | 2 +- > > drivers/video/vidconsole-uclass.c | 2 +- > > drivers/video/video-uclass.c | 14 +- > > drivers/video/video_bmp.c | 8 +- > > include/asm-generic/global_data.h | 4 +- > > include/splash.h | 15 +- > > include/video.h | 8 ++ > > 18 files changed, 447 insertions(+), 212 deletions(-) > > create mode 100644 common/bmp.c > > > > -- > > 2.34.1 > > > > Can this be applied, please? We have rc1 out now so this should really > be in there by now. > > I have another series that depends on it, and it is also pending application. Anatolij ? -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 3/5] nvme: pci: Enable for SPL
On Thu, 4 May 2023 at 03:53, Mayuresh Chitale wrote: > > Enable NVME and PCI NVMe drivers for SPL builds. Also enable PCI_PNP > for SPL which is required to auto configure the PCIe devices. > > Signed-off-by: Mayuresh Chitale > --- > drivers/Makefile | 1 + > drivers/nvme/Makefile | 2 +- > drivers/pci/Kconfig | 7 +++ > 3 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/Makefile b/drivers/Makefile > index 58be410135..dc559ea7f7 100644 > --- a/drivers/Makefile > +++ b/drivers/Makefile > @@ -34,6 +34,7 @@ obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/ > obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/ > obj-$(CONFIG_$(SPL_)SYSINFO) += sysinfo/ > obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/ > +obj-$(CONFIG_$(SPL_)NVME) += nvme/ > obj-$(CONFIG_XEN) += xen/ > obj-$(CONFIG_$(SPL_)FPGA) += fpga/ > obj-y += bus/ > diff --git a/drivers/nvme/Makefile b/drivers/nvme/Makefile > index fa7b619446..fd3e68a91d 100644 > --- a/drivers/nvme/Makefile > +++ b/drivers/nvme/Makefile > @@ -4,4 +4,4 @@ > > obj-y += nvme-uclass.o nvme.o nvme_show.o > obj-$(CONFIG_NVME_APPLE) += nvme_apple.o > -obj-$(CONFIG_NVME_PCI) += nvme_pci.o > +obj-$(CONFIG_$(SPL_)NVME_PCI) += nvme_pci.o > diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig > index ef328d2652..ecab6ddc7e 100644 > --- a/drivers/pci/Kconfig > +++ b/drivers/pci/Kconfig > @@ -40,6 +40,13 @@ config PCI_PNP > help > Enable PCI memory and I/O space resource allocation and assignment. > > +config SPL_PCI_PNP > + bool "Enable Plug & Play support for PCI" > + default n Drop that as the default is n and it confuses people into thinking the default is y > + help > + Enable PCI memory and I/O space resource allocation and assignment. > + This is required to auto configure the enumerated devices. > + > config PCI_REGION_MULTI_ENTRY > bool "Enable Multiple entries of region type MEMORY in ranges for PCI" > help > -- > 2.34.1 > Regards, Simon
Re: [PATCH v2 2/3] X86: Add support for distro boot
Hi Mittelstaedt, On Wed, 3 May 2023 at 23:40, Mittelstaedt Thomas (XC-CT/EBV3) wrote: > > Hello Simon, > > I've tried out successfully the option (with BOOTSTD_FULL, with > BOOTSTD_DEFAULT it's not possible to boot) and will provide a changed patch > set soon. > Thank you for testing. What goes wrong without BOOTSTD_FULL? Regards, Simon > > > Mit freundlichen Grüßen / Best regards > > Thomas Mittelstaedt > > Cross-Domain Computing Solutions > > > > -Ursprüngliche Nachricht- > > Von: Simon Glass > > Gesendet: Dienstag, 2. Mai 2023 19:12 > > An: Heinrich Schuchardt > > Cc: Mittelstaedt Thomas (XC-CT/EBV3) ; > > u-boot@lists.denx.de; Niel Armstrong ; Patrick > > Delaunay ; Ramon Fried > > ; Marek Vasut ; Manuel Traut > > ; Bin Meng > > Betreff: Re: [PATCH v2 2/3] X86: Add support for distro boot > > > > Hi, > > > > On Tue, 2 May 2023 at 09:41, Heinrich Schuchardt wrote: > > > > > > > > > > > > Am 2. Mai 2023 17:21:29 MESZ schrieb thomas.mittelsta...@de.bosch.com: > > > >From: Thomas Mittelstaedt > > > > > > > >Enable distro boot feature for U-Boot at VirtualBox described at > > > >https://sou/ > > > >rce.denx.de%2Fu-boot%2Fu-boot%2F- > > %2Fblob%2Fmaster%2Fdoc%2Fdevelop%2Fd > > > > > >istro.rst&data=05%7C01%7Cthomas.mittelstaedt%40de.bosch.com%7Ca52180e > > > > > >e6e8f4087da4d08db4b306953%7C0ae51e1907c84e4bbb6d648ee58410f4%7C0% > > 7C0% > > > > > >7C638186443515155378%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAw > > MDAiLCJQ > > > > > >IjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata > > =4TSv > > > >yIZMiz4Tt7Wt36NxQR576tg%2F9cS%2FVyZS83xwN50%3D&reserved=0 > > > > > > > >Signed-off-by: Thomas Mittelstaedt > > > >--- > > > > configs/efi-x86_payload64_defconfig | 12 +--- > > > > include/configs/efi-x86_payload.h | 11 +++ > > > > 2 files changed, 12 insertions(+), 11 deletions(-) > > > > > > > >diff --git a/configs/efi-x86_payload64_defconfig > > > >b/configs/efi-x86_payload64_defconfig > > > >index 30a7f31dac..a4cfe95890 100644 > > > >--- a/configs/efi-x86_payload64_defconfig > > > >+++ b/configs/efi-x86_payload64_defconfig > > > >@@ -8,33 +8,23 @@ CONFIG_TARGET_EFI_PAYLOAD=y CONFIG_FIT=y > > > >CONFIG_FIT_SIGNATURE=y CONFIG_LEGACY_IMAGE_FORMAT=y > > > >+CONFIG_DISTRO_DEFAULTS=y > > > > CONFIG_SHOW_BOOT_PROGRESS=y > > > > CONFIG_USE_BOOTARGS=y > > > > CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" > > > >-CONFIG_USE_BOOTCOMMAND=y > > > > CONFIG_PRE_CONSOLE_BUFFER=y > > > > CONFIG_SYS_CONSOLE_INFO_QUIET=y > > > > CONFIG_DISPLAY_BOARDINFO_LATE=y > > > > CONFIG_LAST_STAGE_INIT=y > > > >-CONFIG_HUSH_PARSER=y > > > > CONFIG_SYS_PBSIZE=532 > > > > CONFIG_CMD_IDE=y > > > > CONFIG_CMD_MMC=y > > > >-CONFIG_CMD_PART=y > > > > CONFIG_CMD_USB=y > > > >-CONFIG_CMD_DHCP=y > > > > CONFIG_BOOTP_BOOTFILESIZE=y > > > > # CONFIG_CMD_NFS is not set > > > >-CONFIG_CMD_PING=y > > > > CONFIG_CMD_TIME=y > > > >-CONFIG_CMD_EXT2=y > > > >-CONFIG_CMD_EXT4=y > > > > CONFIG_CMD_EXT4_WRITE=y > > > >-CONFIG_CMD_FAT=y > > > >-CONFIG_CMD_FS_GENERIC=y > > > > CONFIG_MAC_PARTITION=y > > > >-CONFIG_ISO_PARTITION=y > > > >-CONFIG_EFI_PARTITION=y > > > > CONFIG_ENV_OVERWRITE=y > > > > CONFIG_ENV_IS_IN_FAT=y > > > > CONFIG_ENV_FAT_INTERFACE="scsi" > > > >diff --git a/include/configs/efi-x86_payload.h > > > >b/include/configs/efi-x86_payload.h > > > >index c72b067c36..e1cd8eb316 100644 > > > >--- a/include/configs/efi-x86_payload.h > > > >+++ b/include/configs/efi-x86_payload.h > > > >@@ -6,6 +6,17 @@ > > > > /* > > > > * board/config.h - configuration options, board specific > > > > */ > > > >+#ifndef CONFIG_SPL_BUILD > > > >+ > > > >+#define BOOT_TARGET_SCSI(func) \ > > > > > > Shouldn't NVMe be added here too? > > > > This is automatic if you use bootstd. > > > > > > > > Best regards > > > > > > Heinrich > > > > > > >+ func(SCSI, scsi, 0) > > > >+ > > > >+#define BOOT_TARGET_DEVICES(func) \ > > > >+ BOOT_TARGET_SCSI(func) > > > >+ > > > >+#include > > > >+ > > > >+#endif > > > > > > > > #ifndef __CONFIG_H > > > > #define __CONFIG_H > > > > Please can we use bootstd instead? > > > > You should just need to enable BOOTSTD_DEFAULTS and it will work. If not, > > please let me know. > > > > Please also see the various improvements in[1] available at [2]. There is > > also a > > new video driver [2]. > > > > Regards, > > Simon > > > > [1] > > https://patchwork.o/ > > zlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D351440&data=05%7C01 > > %7Cthomas.mittelstaedt%40de.bosch.com%7Ca52180ee6e8f4087da4d08db4b306 > > 953%7C0ae51e1907c84e4bbb6d648ee58410f4%7C0%7C0%7C6381864435151553 > > 78%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiL > > CJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=yjqyizWXqb > > YZmSuzfvqq4EfYvJYqXUf6irbLYhLo4qk%3D&reserved=0 > > [2] > > https://source.denx/ > > .de%2Fu-boot%2Fcustodians%2Fu-boot-dm%2F-%2Ftree%2Fbryc- > > working&data=05%7C01%7Cthomas.mittelstaedt%40de.bosch.com%7Ca52180ee > > 6e8f4087da4d08db4b306953%7C0ae51e19
Re: [PATCH v3 2/5] spl: blk: Support loading images from fs
Hi Mayuresh,
On Thu, 4 May 2023 at 03:53, Mayuresh Chitale wrote:
>
> Add a generic API to support loading of SPL payload from EXT or FAT
> filesystem on a given partition of a block device.
>
> Signed-off-by: Mayuresh Chitale
> ---
> common/spl/Makefile | 1 +
> common/spl/spl_blk_fs.c | 54 +
> drivers/block/Kconfig | 7 ++
> include/spl.h | 3 +++
> 4 files changed, 65 insertions(+)
> create mode 100644 common/spl/spl_blk_fs.c
>
> diff --git a/common/spl/Makefile b/common/spl/Makefile
> index 13db3df993..5210ad0248 100644
> --- a/common/spl/Makefile
> +++ b/common/spl/Makefile
> @@ -10,6 +10,7 @@ ifdef CONFIG_SPL_BUILD
> obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o
> obj-$(CONFIG_$(SPL_TPL_)BOOTROM_SUPPORT) += spl_bootrom.o
> obj-$(CONFIG_$(SPL_TPL_)LOAD_FIT) += spl_fit.o
> +obj-$(CONFIG_$(SPL_TPL_)BLK_FS) += spl_blk_fs.o
> obj-$(CONFIG_$(SPL_TPL_)LEGACY_IMAGE_FORMAT) += spl_legacy.o
> obj-$(CONFIG_$(SPL_TPL_)NOR_SUPPORT) += spl_nor.o
> obj-$(CONFIG_$(SPL_TPL_)XIP_SUPPORT) += spl_xip.o
> diff --git a/common/spl/spl_blk_fs.c b/common/spl/spl_blk_fs.c
> new file mode 100644
> index 00..fb2e8bbea7
> --- /dev/null
> +++ b/common/spl/spl_blk_fs.c
> @@ -0,0 +1,54 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2023
> + * Ventana Micro Systems Inc.
> + *
> + * Derived work from spl_sata.c
> + */
> +
> +#include
> +#include
> +
> +int spl_blk_load_image(struct spl_image_info *spl_image,
> + struct spl_boot_device *bootdev,
> + enum uclass_id uclass_id, int devnum)
> +{
> + int ret = -ENOSYS, part;
> + struct blk_desc *blk_desc;
> +
> + blk_desc = blk_get_devnum_by_uclass_id(uclass_id, devnum);
> + if (!blk_desc)
> + return ret;
> +
> + blk_show_device(uclass_id, devnum);
> +
> + if (IS_ENABLED(CONFIG_SPL_FS_EXT4)) {
Can you use the fs.h layer so it can work with any FS?
> + switch (uclass_id) {
> + case UCLASS_NVME:
> + part = CONFIG_SYS_NVME_EXT_BOOT_PARTITION;
> + break;
> + default:
> + return ret;
> + }
> + ret = spl_load_image_ext(spl_image, bootdev, blk_desc, part,
> +CONFIG_SPL_PAYLOAD);
> + if (!ret)
> + return ret;
> + }
> +
> + if (IS_ENABLED(CONFIG_SPL_FS_FAT)) {
> + switch (uclass_id) {
> + case UCLASS_NVME:
> + part = CONFIG_SYS_NVME_FAT_BOOT_PARTITION;
> + break;
> + default:
> + return ret;
> + }
> + ret = spl_load_image_fat(spl_image, bootdev, blk_desc, part,
> +CONFIG_SPL_PAYLOAD);
> + if (!ret)
> + return ret;
> + }
> +
> + return ret;
> +}
> diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
> index 5a1aeb3d2b..6baaa6f071 100644
> --- a/drivers/block/Kconfig
> +++ b/drivers/block/Kconfig
> @@ -107,6 +107,13 @@ config EFI_MEDIA
>
> For sandbox there is a test driver.
>
> +config SPL_BLK_FS
> + bool "Load images from filesystems on block devices"
> + depends on SPL_BLK
> + help
> + Use generic support to load images from fat/ext filesystems on
> + different types of block devices such as NVMe.
> +
> if EFI_MEDIA
>
> config EFI_MEDIA_SANDBOX
> diff --git a/include/spl.h b/include/spl.h
> index 7e0f5ac63b..4546648394 100644
> --- a/include/spl.h
> +++ b/include/spl.h
> @@ -672,6 +672,9 @@ int spl_load_image_ext(struct spl_image_info *spl_image,
> int spl_load_image_ext_os(struct spl_image_info *spl_image,
> struct spl_boot_device *bootdev,
> struct blk_desc *block_dev, int partition);
> +int spl_blk_load_image(struct spl_image_info *spl_image,
> + struct spl_boot_device *bootdev,
> + enum uclass_id uclass_id, int devnum);
>
> /**
> * spl_early_init() - Set up device tree and driver model in SPL if enabled
> --
> 2.34.1
>
Regards,
Simon
Re: [PATCH v3 1/5] spl: Add Kconfig options for NVME
On Thu, 4 May 2023 at 03:53, Mayuresh Chitale wrote: > > Add kconfig options to enable NVME and PCI NVMe support in SPL > > Signed-off-by: Mayuresh Chitale > --- > common/spl/Kconfig | 21 + > 1 file changed, 21 insertions(+) > > diff --git a/common/spl/Kconfig b/common/spl/Kconfig > index 2c042ad306..515e8f2c66 100644 > --- a/common/spl/Kconfig > +++ b/common/spl/Kconfig > @@ -1263,6 +1263,27 @@ config SPL_SATA_RAW_U_BOOT_SECTOR > Sector on the SATA disk to load U-Boot from, when the SATA disk is > being > used in raw mode. Units: SATA disk sectors (1 sector = 512 bytes). > Reviewed-by: Simon Glass > +config SPL_NVME > + bool "NVM Express device support" > + depends on BLK > + select HAVE_BLOCK_DEVICE > + select SPL_BLK_FS > + help > + This option enables support for NVM Express devices. > + It supports basic functions of NVMe (read/write). > + > +config SPL_NVME_PCI > + bool "NVM Express PCI device support for SPL" > + depends on SPL_PCI && SPL_NVME > + help > + This option enables support for NVM Express PCI devices. > + This allows use of NVMe devices for loading u-boot. > + > +config SPL_NVME_BOOT_DEVICE > + hex "NVMe boot device number" > + depends on SPL_NVME > + default 0x0 > + > config SPL_SERIAL > bool "Support serial" > select SPL_PRINTF > -- > 2.34.1 >
Re: [PATCH 1/2] kbuild: add dtc as dependency on .dtb files
On Thu, 4 May 2023 at 06:26, Rasmus Villemoes wrote: > > [Linux commit b8fc5b2157b1] > > If dtc is rebuilt, we should rebuild .dtb files with the new dtc. > > [Import notes: Back then there was no .dtbo rule in Linux's > Makefile.lib, but the current .dtbo rules in Linux also have the > $(DTC) dependency, so also add it to our .dtbo rule.] > > Signed-off-by: Rasmus Villemoes > --- > scripts/Makefile.lib | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > Reviewed-by: Simon Glass
Re: [PATCH v2 15/18] spl: Commit MTRRs only in board_init_f_r()
Hi Bin, On Thu, 4 May 2023 at 08:22, Bin Meng wrote: > > Hi Simon, > > On Tue, Apr 18, 2023 at 11:31 PM Simon Glass wrote: > > > > We don't need to commit the SPI-flash MTRR change immediately, since it is > > now done in the board_init_f_r(). Also this causes chromebook_link64 to > > hang. > > Could you add more details as to why this causes chromebook_link64 to hang? > > As I see the mtrr_commit() has been there since TPL was introduced on > day 1, there must be some other places changes that caused the > regression on chromebook_link64?? I went back a few years (2019.04 I think) and found that the regression has been there quite a while. The problem was that I had a test for link but not link64. So I think it silently broke and I didn't notice at the time. I'll update with a little more detail. [..] Regards, Simon
Re: [PATCH V9 00/14] Add splash screen support at u-boot SPL
Hi, On Thu, 20 Apr 2023 at 06:11, Nikhil M Jain wrote: > > To enable splash screen at SPL stage move video driver and splash screen > framework at SPL, which will bring up image on display very quickly and > thus have early display support in SPL. > > Changes in V9 > - Update as per review comments. > - Add Reviewed-by tag in appropriate patch. > > Changes in V8 > - Update as per review comments. > > Changes in V7 > - Replace #ifdefs' and #ifs' with if in common/splash and common/bmp. > - Add Reviewed-by and Tested-by tag in apprpriate patch. > > Changes in V6 > - Fix commit messages. > - Fix compile rules for video related files in patch > drivers: video: Makefile: Rule to compile necessary video driver > files. > > Changes in V5 > - Drop patch cmd: Makefile: Rule to compile bmp_cmd. > - Squash common: splash: Replace CONFIG_CMD_BMP patch into patches > common: Enable splash functions at SPL > include: Enable video related global data variable and splash at SPL > - Fix merge issue for next branch. > - Replace cmd/bmp_cmd with cmd/bmp. > - Use CONFIG_$(SPL_TPL_) to compile files in > drivers: video: Makefile: Rule to compile necessary video driver files. > - Add Reviewed-by tag in appropriate patch. > > Changes in V4 > - Add Reviewed-by tag in appropriate patch. > > Changes in V3 > - Add separate video configs for SPL splash screen. > - Add rule to compile video driver in drivers/Makefile at SPL. > - Add rule to compile splash.c and splash_source.c. > - Squash drivers: video: video-uclass: Disable u-boot logo at SPL into > drivers: video: Use CONFIG_IS_ENABLED and CONFIG_VAL. > - Split cmd/bmp.c to separate bmp functions and commands. > - Add CONFIG_BMP and CONFIG_SPL_BMP. > - Add rule to compile necessary files required for video driver. > - Add rule to compile common/bmp.c. > > Changes in V2 > - Removed artifacts from bad patch apply. > > Nikhil M Jain (14): > drivers: video: Kconfig: Add configs for enabling video at SPL > drivers: video: tidss: Kconfig: Configs to enable TIDSS at SPL > drivers: Makefile: Add rule to compile video driver > drivers: video: Makefile: Rule to compile necessary video driver files > drivers: video: tidss: Makefile: Add condition to compile TIDSS at SPL > common: Makefile: Add rule to compile splash and splash_source at SPL > common: Kconfig: Add BMP configs > cmd: bmp: Split bmp commands and functions > common: Makefile: Rule to compile bmp.c > drivers: video: Enable necessary video functions at SPL > common: Enable splash functions at SPL > include: Enable video related global data variable and splash at SPL > board: ti: am62x: evm: OSPI support for splash screen > common: Replace #ifdef and #if with if's > > board/ti/am62x/evm.c | 8 +- > cmd/bmp.c | 162 +- > common/Kconfig| 12 ++ > common/Makefile | 3 + > common/bmp.c | 149 > common/splash.c | 20 +-- > drivers/Makefile | 1 + > drivers/video/Kconfig | 223 +- > drivers/video/Makefile| 16 +-- > drivers/video/console_core.c | 6 +- > drivers/video/tidss/Kconfig | 6 + > drivers/video/tidss/Makefile | 2 +- > drivers/video/vidconsole-uclass.c | 2 +- > drivers/video/video-uclass.c | 14 +- > drivers/video/video_bmp.c | 8 +- > include/asm-generic/global_data.h | 4 +- > include/splash.h | 15 +- > include/video.h | 8 ++ > 18 files changed, 447 insertions(+), 212 deletions(-) > create mode 100644 common/bmp.c > > -- > 2.34.1 > Can this be applied, please? We have rc1 out now so this should really be in there by now. I have another series that depends on it, and it is also pending application. Regards, Simon
Re: [PATCH v3 3/3] X86: pxeboot: bugfix: Set variable for size of initrd
On Thu, 4 May 2023 at 07:43, wrote:
>
> From: Thomas Mittelstaedt
>
> The problem was, that zboot() didn't work because of missing
> ramdisc size.
>
> Signed-off-by: Thomas Mittelstaedt
> ---
> boot/pxe_utils.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Fixes: 085cbdafca9 ("pxe: simplify label_boot()")
Reviewed-by: Simon Glass
Re: [PATCH 2/2] kbuild: Allow DTB overlays to built from .dtso named source files
On Thu, 4 May 2023 at 06:26, Rasmus Villemoes wrote: > > [Linux commit 363547d2191c] > > Currently DTB Overlays (.dtbo) are build from source files with the same > extension (.dts) as the base DTs (.dtb). This may become confusing and > even lead to wrong results. For example, a composite DTB (created from a > base DTB and a set of overlays) might have the same name as one of the > overlays that create it. > > Different files should be generated from differently named sources. > .dtb <-> .dts > .dtbo <-> .dtso > > We do not remove the ability to compile DTBO files from .dts files here, > only add a new rule allowing the .dtso file name. The current .dts named > overlays can be renamed with time. After all have been renamed we can > remove the other rule. > > [Import notes: Adapt to U-Boot by using the cmd_dtco function instead > of cmd_dtc just like the current .dts -> .dtbo rule.] > > Signed-off-by: Rasmus Villemoes > --- > scripts/Makefile.lib | 3 +++ > 1 file changed, 3 insertions(+) > Reviewed-by: Simon Glass
Re: [PATCH v3 4/5] spl: Support loading a FIT from ext FS
Hi Mayuresh,
On Thu, 4 May 2023 at 03:53, Mayuresh Chitale wrote:
>
> Detect a FIT when loading from an ext File system and handle it using
> the FIT SPL support.
>
> Signed-off-by: Mayuresh Chitale
> ---
> common/spl/spl_ext.c | 33 +
> 1 file changed, 33 insertions(+)
>
> diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
> index f117c630bf..7b771c41e9 100644
> --- a/common/spl/spl_ext.c
> +++ b/common/spl/spl_ext.c
> @@ -8,6 +8,26 @@
> #include
> #include
> #include
> +#include
> +
> +static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
> + ulong size, void *buf)
> +{
> + loff_t filelen = (loff_t)load->priv, actlen;
> + char *filename = (char *)load->filename;
> + int ret;
> +
> + ret = ext4fs_read(buf, file_offset, filelen, &actlen);
If you use the fs_...() interface instead, can you make this function
generic for all filesystems?
> + if (ret < 0) {
> + if (IS_ENABLED(CONFIG_SPL_LIBCOMMON_SUPPORT)) {
> + printf("%s: error reading image %s, err - %d\n",
> + __func__, filename, ret);
I could be wrong, but I think printf() is silently dropped if that
option is not enabled, so maybe you don't need the if() checK?
> + }
> + return ret;
> + }
> +
> + return actlen;
> +}
>
> int spl_load_image_ext(struct spl_image_info *spl_image,
>struct spl_boot_device *bootdev,
> @@ -47,6 +67,19 @@ int spl_load_image_ext(struct spl_image_info *spl_image,
Really this should not be different from FAT and other filesystems.
I'm not sure what is involved in making it common, though.
> goto end;
> }
>
> + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
> + image_get_magic(header) == FDT_MAGIC) {
> + struct spl_load_info load;
> +
> + debug("Found FIT\n");
> + load.read = spl_fit_read;
> + load.bl_len = 1;
> + load.filename = (void *)filename;
> + load.priv = (void *)filelen;
> +
> + return spl_load_simple_fit(spl_image, &load, 0, header);
> + }
> +
> err = spl_parse_image_header(spl_image, bootdev, header);
> if (err < 0) {
> puts("spl: ext: failed to parse image header\n");
> --
> 2.34.1
>
Regards,
Simon
Re: [PATCH v3 5/5] common: spl: Add spl NVMe boot support
On Thu, 4 May 2023 at 03:53, Mayuresh Chitale wrote: > > Add support to load the next stage image from an NVMe disk which may > be formatted as an EXT or FAT filesystem. > > Signed-off-by: Mayuresh Chitale > --- > arch/riscv/include/asm/spl.h | 1 + > common/spl/Kconfig | 10 ++ > common/spl/Makefile | 1 + > common/spl/spl_nvme.c| 34 ++ > 4 files changed, 46 insertions(+) > create mode 100644 common/spl/spl_nvme.c > Reviewed-by: Simon Glass BTW you should also be able to add a test for this using sandbox_spl
Re: [PATCH v3 2/3] X86: Add bootstd support
On Thu, 4 May 2023 at 07:43, wrote: > > From: Thomas Mittelstaedt > > Enable bootstd support for U-Boot at VirtualBox described at > https://source.denx.de/u-boot/u-boot/-/blob/master/doc/develop/bootstd.rst > This is used to boot system images at Virtualbox via > - distroboot (extlinux.conf) > - boot script > > Signed-off-by: Thomas Mittelstaedt > --- > configs/efi-x86_payload64_defconfig | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Simon Glass Here you are enabling 'full' support which provides a few more features, mostly an enhanced command line.
Re: [PATCH v3 1/3] X86: Add support for SCSI devices
On Thu, 4 May 2023 at 07:43, wrote: > > From: Thomas Mittelstaedt > > U-Boot at VirtualBox must load Linux and boot configuration from disk devices. > Here the discs at AHCI (scsi) bus are used to load the need boot data. > > Signed-off-by: Thomas Mittelstaedt > --- > configs/efi-x86_payload64_defconfig | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > Reviewed-by: Simon Glass
Re: [PATCH] scripts/Makefile.dts: tweak logic for deciding which dtbs to build
On Thu, 4 May 2023 at 09:51, Tom Rini wrote: > > On Thu, May 04, 2023 at 01:33:08PM +0200, Rasmus Villemoes wrote: > > > The idea in 3609e1dc5f4d (dts: automatically build necessary .dtb > > files) was fine, but the implementation was suboptimal due to some > > misunderstandings on my part (and possibly defects in some defconfig > > files): > > > > - Sometimes DEFAULT_DEVICE_TREE is not included in OF_LIST or > > SPL_OF_LIST > > > > - SPL_OF_LIST is not always a subset of OF_LIST > > > > - While SPL_OF_LIST governs the list of dtbs relevant to SPL (i.e., > > may be built into an > > SPL-with-bunch-of-dtbs-to-choose-between-at-runtime), those dtbs are > > not actually _built_ during the SPL build phase, i.e. when $(SPL_) > > would expand to SPL_. fdtgrep runs on the artifacts produced during > > the ordinary U-Boot build. > > > > Tweak the logic so that we simply add the union of all dtbs mentioned > > in either DEFAULT_DEVICE_TREE, OF_LIST and SPL_OF_LIST to dtb-y. That > > should, for real, ensure that we always build all the dtbs that is > > relevant to the current board, and should in turn enable us to > > massively simplify arch/*/dts/Makefile. > > > > Signed-off-by: Rasmus Villemoes > > Tested-by: Tom Rini Reviewed-by: Simon Glass
Re: [PATCH 4/4] test: bdinfo: Add test for command bdinfo
Hi Marek, On Thu, 4 May 2023 at 10:01, Marek Vasut wrote: > > On 5/4/23 17:51, Tom Rini wrote: > > On Sat, Apr 22, 2023 at 03:01:34PM +0200, Marek Vasut wrote: > > > >> Add test for command bdinfo . > >> > >> Signed-off-by: Marek Vasut > >> Reviewed-by: Simon Glass > >> --- > >> Cc: Jason Liu > >> Cc: Michal Simek > >> Cc: Ovidiu Panait > >> Cc: Simon Glass > >> --- > >> include/test/suites.h | 1 + > >> test/cmd/Makefile | 1 + > >> test/cmd/bdinfo.c | 179 ++ > >> test/cmd_ut.c | 6 ++ > >> 4 files changed, 187 insertions(+) > >> create mode 100644 test/cmd/bdinfo.c > > > > This breaks building on "snow" which does not set CFG_SYS_SDRAM_SIZE > > seemingly. > > Isn't this macro mandatory ? > > Simon, can you elaborate what chromebook snow does with the DRAM there ? It detects it at runtime, so doesn't have that symbol. Regards, Simon
[PATCH] ARM: stm32: Fix OF_LIST on DHCOR
The ITS file used to build the images here lists three dtb files as being used. Today, these are built by the logic that will over-build dtb files based on SOC/etc symbols being set. To future proof this platform and be generally correct, we list all 3 of the device trees used here in OF_LIST. Cc: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Signed-off-by: Tom Rini --- configs/stm32mp15_dhcor_basic_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index b54ff9301461..d4786500271a 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -92,6 +92,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(fsbl1),256k(fsbl2),1408k(uboot),64k( # CONFIG_ISO_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_OF_LIVE=y +CONFIG_OF_LIST="stm32mp15xx-dhcor-avenger96 stm32mp15xx-dhcor-testbench stm32mp15xx-dhcor-drc-compact" CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -- 2.34.1
[PATCH v3 27/43] pci: Adjust video BIOS debugging to be SPL-friendly
A hex value is expected for the VGA mode. Drop the 0x prefix, which is
not supported in SPL.
Signed-off-by: Simon Glass
---
(no changes since v1)
drivers/pci/pci_rom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index ecb6da64c5c..62cfe60c0fb 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -319,7 +319,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int
(*int15_handler)(void),
defined(CONFIG_FRAMEBUFFER_VESA_MODE)
vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE;
#endif
- debug("Selected vesa mode %#x\n", vesa_mode);
+ debug("Selected vesa mode %x\n", vesa_mode);
if (exec_method & PCI_ROM_USE_NATIVE) {
#ifdef CONFIG_X86
@@ -370,7 +370,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int
(*int15_handler)(void),
log_debug("done\n");
#endif
}
- debug("Final vesa mode %#x\n", mode_info.video_mode);
+ debug("Final vesa mode %x\n", mode_info.video_mode);
ret = 0;
err:
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 22/43] pci: Allow the video BIOS to work in SPL with QEMU
QEMU emulates two common machines (Q35 and i440fx) which use mapping to
determine whether RAM is present below 1MB. In order to copy the video
BIOS to c we need to flip this mapping over to RAM. This does not
happen automatically until SPL has finished running.
Switch in RAM at these address so that the video BIOS can be loaded and
run. This fix was found in the seabios code base.
Signed-off-by: Simon Glass
---
(no changes since v1)
drivers/pci/pci_rom.c | 46 +++
include/pci_ids.h | 1 +
2 files changed, 47 insertions(+)
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index f0dfe631490..0f44238bbbc 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -141,6 +141,49 @@ static int pci_rom_probe(struct udevice *dev, struct
pci_rom_header **hdrp)
return 0;
}
+#define Q35_HOST_BRIDGE_PAM0 0x90
+#define I440FX_PAM00x59
+
+/**
+ * intel_set_writable_ram() - Set RAM to be writable
+ *
+ * This is needed for QEMU when using Q35 or I440FX emulation, since otherwise
+ * there is no RAM available at c
+ *
+ * See Intel 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet for
+ * information about the PAM0-PAM6 registers
+ */
+static void intel_set_writable_ram(void)
+{
+ struct udevice *dev;
+ int pam0 = -1;
+ int i;
+
+ for (pci_find_first_device(&dev); dev; pci_find_next_device(&dev)) {
+ const struct pci_child_plat *pdata = dev_get_parent_plat(dev);
+
+ if (pdata->vendor == PCI_VENDOR_ID_INTEL) {
+ if (pdata->device == PCI_DEVICE_ID_INTEL_Q35_MCH) {
+ pam0 = Q35_HOST_BRIDGE_PAM0;
+ break;
+ } else if (pdata->device == PCI_DEVICE_ID_INTEL_82441) {
+ pam0 = I440FX_PAM0;
+ break;
+ }
+ }
+ }
+
+ if (!dev)
+ return;
+
+ // Adjust RAM to be writable from c to f
+ for (i = 1; i <= 6; i++)
+ dm_pci_write_config8(dev, pam0 + i, 0x33);
+
+ // Also f-10
+ dm_pci_write_config8(dev, pam0, 0x30);
+}
+
/**
* pci_rom_load() - Load a ROM image and return a pointer to it
*
@@ -185,6 +228,9 @@ static int pci_rom_load(struct pci_rom_header *rom_header,
return -ENOMEM;
*allocedp = true;
#endif
+ /* QEMU hacks */
+ intel_set_writable_ram();
+
if (target != rom_header) {
ulong start = get_timer(0);
diff --git a/include/pci_ids.h b/include/pci_ids.h
index 88b0a640458..856d5326411 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -2870,6 +2870,7 @@
#define PCI_DEVICE_ID_INTEL_ICH9_7 0x2916
#define PCI_DEVICE_ID_INTEL_ICH9_8 0x2918
#define PCI_DEVICE_ID_INTEL_ICH9_AHCI 0x2922
+#define PCI_DEVICE_ID_INTEL_Q35_MCH0x29c0
#define PCI_DEVICE_ID_INTEL_I7_MCR 0x2c18
#define PCI_DEVICE_ID_INTEL_I7_MC_TAD 0x2c19
#define PCI_DEVICE_ID_INTEL_I7_MC_RAS 0x2c1a
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 43/43] efi: Use the installed ACPI tables
U-Boot sets up the ACPI tables during startup. Rather than creating a
new set, install the existing ones. Create a memory-map record to cover
the tables.
Signed-off-by: Simon Glass
---
(no changes since v2)
Changes in v2:
- Drop patch to set high bits of the mtrr base register, for now
lib/efi_loader/efi_acpi.c | 33 +++--
1 file changed, 19 insertions(+), 14 deletions(-)
diff --git a/lib/efi_loader/efi_acpi.c b/lib/efi_loader/efi_acpi.c
index 2ddc3502b5d..f755af76f86 100644
--- a/lib/efi_loader/efi_acpi.c
+++ b/lib/efi_loader/efi_acpi.c
@@ -10,6 +10,9 @@
#include
#include
#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
static const efi_guid_t acpi_guid = EFI_ACPI_TABLE_GUID;
@@ -20,26 +23,28 @@ static const efi_guid_t acpi_guid = EFI_ACPI_TABLE_GUID;
*/
efi_status_t efi_acpi_register(void)
{
- /* Map within the low 32 bits, to allow for 32bit ACPI tables */
- u64 acpi = U32_MAX;
+ ulong addr, start, end;
efi_status_t ret;
- ulong addr;
- /* Reserve 64kiB page for ACPI */
- ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
-EFI_ACPI_RECLAIM_MEMORY, 16, &acpi);
+ /* Mark space used for tables */
+ start = ALIGN_DOWN(gd->arch.table_start, EFI_PAGE_MASK);
+ end = ALIGN(gd->arch.table_end, EFI_PAGE_MASK);
+ ret = efi_add_memory_map(start, end - start, EFI_ACPI_RECLAIM_MEMORY);
if (ret != EFI_SUCCESS)
return ret;
+ if (gd->arch.table_start_high) {
+ start = ALIGN_DOWN(gd->arch.table_start_high, EFI_PAGE_MASK);
+ end = ALIGN(gd->arch.table_end_high, EFI_PAGE_MASK);
+ ret = efi_add_memory_map(start, end - start,
+EFI_ACPI_RECLAIM_MEMORY);
+ if (ret != EFI_SUCCESS)
+ return ret;
+ }
- /*
-* Generate ACPI tables - we know that efi_allocate_pages() returns
-* a 4k-aligned address, so it is safe to assume that
-* write_acpi_tables() will write the table at that address.
-*/
- addr = map_to_sysmem((void *)(ulong)acpi);
- write_acpi_tables(addr);
+ addr = gd_acpi_start();
+ printf("EFI using ACPI tables at %lx\n", addr);
/* And expose them to our EFI payload */
return efi_install_configuration_table(&acpi_guid,
- (void *)(uintptr_t)acpi);
+ (void *)(ulong)addr);
}
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 42/43] sandbox: Install ACPI tables on startup
With x86 we set up the ACPI tables on startup so they can be examined. Do
the same with sandbox, so it is consistent.
Signed-off-by: Simon Glass
---
(no changes since v1)
board/sandbox/sandbox.c | 16
1 file changed, 16 insertions(+)
diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c
index e72d8164ebf..2083eaa2dc5 100644
--- a/board/sandbox/sandbox.c
+++ b/board/sandbox/sandbox.c
@@ -15,7 +15,9 @@
#include
#include
#include
+#include
#include
+#include
#include
#include
#include
@@ -154,6 +156,8 @@ int extension_board_scan(struct list_head *extension_list)
int board_late_init(void)
{
struct udevice *dev;
+ ulong addr, end;
+ void *ptr;
int ret;
ret = uclass_first_device_err(UCLASS_CROS_EC, &dev);
@@ -166,6 +170,18 @@ int board_late_init(void)
panic("Cannot init cros-ec device");
return -1;
}
+
+ if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
+ /* Reserve 64K for ACPI tables, aligned to a 4K boundary */
+ ptr = memalign(SZ_4K, SZ_64K);
+ addr = map_to_sysmem(ptr);
+
+ /* Generate ACPI tables */
+ end = write_acpi_tables(addr);
+ gd->arch.table_start = addr;
+ gd->arch.table_end = addr;
+ }
+
return 0;
}
#endif
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 41/43] sandbox: Correct header order in board file
Fix the header order in this file. Signed-off-by: Simon Glass --- (no changes since v1) board/sandbox/sandbox.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index 2e44bdf0df3..e72d8164ebf 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -11,16 +11,16 @@ #include #include #include +#include #include #include +#include #include #include #include #include #include -#include - -#include +#include /* * Pointer to initial global data area -- 2.40.1.521.gf1e218fcd8-goog
[PATCH v3 34/43] x86: Refactor table-writing code a litlle
The implementation of write_tables() is confusing because it uses the
rom_table_start variable as the address pointer as it progresses.
Rename it to rom_addr to make the code clearer. Move the rom_table_end
variable into the block where it is used.
Also update logging to use the ACPI category, now that it is available.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add new patch to refactor table-writing code a ltitle
arch/x86/lib/tables.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index ea834a5035f..132c02ee80f 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -3,7 +3,7 @@
* Copyright (C) 2015, Bin Meng
*/
-#define LOG_CATEGORY LOGC_BOARD
+#define LOG_CATEGORY LOGC_ACPI
#include
#include
@@ -78,33 +78,33 @@ void table_fill_string(char *dest, const char *src, size_t
n, char pad)
int write_tables(void)
{
- u32 rom_table_start;
- u32 rom_table_end;
u32 high_table, table_size;
struct memory_area cfg_tables[ARRAY_SIZE(table_list) + 1];
+ u32 rom_addr;
int i;
- rom_table_start = ROM_TABLE_ADDR;
+ rom_addr = ROM_TABLE_ADDR;
- debug("Writing tables to %x:\n", rom_table_start);
+ debug("Writing tables to %x:\n", rom_addr);
for (i = 0; i < ARRAY_SIZE(table_list); i++) {
const struct table_info *table = &table_list[i];
int size = table->size ? : CONFIG_ROM_TABLE_SIZE;
+ u32 rom_table_end;
if (IS_ENABLED(CONFIG_BLOBLIST_TABLES) && table->tag) {
- rom_table_start = (ulong)bloblist_add(table->tag, size,
+ rom_addr = (ulong)bloblist_add(table->tag, size,
table->align);
- if (!rom_table_start)
+ if (!rom_addr)
return log_msg_ret("bloblist", -ENOBUFS);
}
- rom_table_end = table->write(rom_table_start);
+ rom_table_end = table->write(rom_addr);
if (!rom_table_end) {
log_err("Can't create configuration table %d\n", i);
return -EINTR;
}
if (IS_ENABLED(CONFIG_SEABIOS)) {
- table_size = rom_table_end - rom_table_start;
+ table_size = rom_table_end - rom_addr;
high_table = (u32)(ulong)high_table_malloc(table_size);
if (high_table) {
if (!table->write(high_table)) {
@@ -123,13 +123,13 @@ int write_tables(void)
}
debug("- wrote '%s' to %x, end %x\n", table->name,
- rom_table_start, rom_table_end);
- if (rom_table_end - rom_table_start > size) {
+ rom_addr, rom_table_end);
+ if (rom_table_end - rom_addr > size) {
log_err("Out of space for configuration tables: need
%x, have %x\n",
- rom_table_end - rom_table_start, size);
+ rom_table_end - rom_addr, size);
return log_msg_ret("bloblist", -ENOSPC);
}
- rom_table_start = rom_table_end;
+ rom_addr = rom_table_end;
}
if (IS_ENABLED(CONFIG_SEABIOS)) {
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 40/43] log: Support outputing function names in SPL
The output is garbled when tiny printf() is used. Correct this by adding
a special case.
Signed-off-by: Simon Glass
---
(no changes since v2)
Changes in v2:
- Add new patch to support outputing function names in SPL
common/log_console.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/common/log_console.c b/common/log_console.c
index f1dcc04b97c..bb091ce21a4 100644
--- a/common/log_console.c
+++ b/common/log_console.c
@@ -37,8 +37,14 @@ static int log_console_emit(struct log_device *ldev, struct
log_rec *rec)
printf("%s:", rec->file);
if (fmt & BIT(LOGF_LINE))
printf("%d-", rec->line);
- if (fmt & BIT(LOGF_FUNC))
- printf("%*s()", CONFIG_LOGF_FUNC_PAD, rec->func);
+ if (fmt & BIT(LOGF_FUNC)) {
+ if (CONFIG_IS_ENABLED(USE_TINY_PRINTF)) {
+ printf("%s()", rec->func);
+ } else {
+ printf("%*s()", CONFIG_LOGF_FUNC_PAD,
+ rec->func);
+ }
+ }
}
if (fmt & BIT(LOGF_MSG))
printf("%s%s", add_space ? " " : "", rec->msg);
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 39/43] x86: Make sure that the LPC is active before SDRAM init
Some boards need to access GPIOs to determine which SDRAM is fitted to the
board, for example chromebook_link. Probe this device (if it exists) to
make sure that this works as expected.
Signed-off-by: Simon Glass
---
(no changes since v2)
Changes in v2:
- Add new patch to make sure that the LPC is active before SDRAM init
arch/x86/lib/spl.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index 6886587f647..fb7dac68d7a 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -65,6 +65,8 @@ static int set_max_freq(void)
static int x86_spl_init(void)
{
+ struct udevice *dev;
+
#ifndef CONFIG_TPL
/*
* TODO(s...@chromium.org): We use this area of RAM for the stack
@@ -109,6 +111,13 @@ static int x86_spl_init(void)
return ret;
}
#endif
+ /* probe the LPC so we get the GPIO_BASE set up correctly */
+ ret = uclass_first_device_err(UCLASS_LPC, &dev);
+ if (ret && ret != -ENODEV) {
+ log_debug("lpc probe failed\n");
+ return ret;
+ }
+
ret = dram_init();
if (ret) {
log_debug("dram_init() failed (err=%d)\n", ret);
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 32/43] fs: fat: Support reading from a larger block size
At present it is not possible to read from some CDROM drives since the
FAT sector size does not match the media's block size. Add a conversion
option for this, so that reading is possible.
This does increase SPL size for read-only FAT support by 25 bytes but
all but 6 are covered by the previous patch. We could reduce the
overhead of this feature to 0 bytes by making the code uglier (using
a static variable).
Signed-off-by: Simon Glass
---
(no changes since v2)
Changes in v2:
- Use log_warning() for the warning
fs/fat/Kconfig | 13 ++
fs/fat/fat.c | 107 -
fs/fat/fat_write.c | 8 ++--
3 files changed, 114 insertions(+), 14 deletions(-)
diff --git a/fs/fat/Kconfig b/fs/fat/Kconfig
index 9bb11eac9f7..b0aa888c6cc 100644
--- a/fs/fat/Kconfig
+++ b/fs/fat/Kconfig
@@ -22,3 +22,16 @@ config FS_FAT_MAX_CLUSTSIZE
is the smallest amount of disk space that can be used to hold a
file. Unless you have an extremely tight memory memory constraints,
leave the default.
+
+config FAT_BLK_XLATE
+ bool "Enable FAT filesystem on a device with a larger block size"
+ depends on FS_FAT
+ help
+ This provides a simple translation mechanism for reading FAT
+ filesystems which don't use the same sector size as the underlying
+ media. For example, the FAT filesystem may use 512 bytes but the
+ media uses 2048, e.g. on a CDROM drive.
+
+ This only supports the case where the FAT filesystem's sector size is
+ smaller than the media's block size. It does not support creating or
+ writing files.
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index d1476aa433d..686b321163f 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -45,13 +45,93 @@ static struct disk_partition cur_part_info;
#define DOS_FS_TYPE_OFFSET 0x36
#define DOS_FS32_TYPE_OFFSET 0x52
-static int disk_read(__u32 block, __u32 nr_blocks, void *buf)
+/**
+ * disk_read_conv() - Read blocks and break them into smaller ones
+ *
+ * This is used when the FAT filesystem is hosted on a block device with a
+ * block size greated than 512 bytes, e.g. the 2048 bytes of a CDROM drive. It
+ * reads the blocks into a buffer and pulls out what is requested by the
calling
+ * function.
+ *
+ * It uses an internal 2KB buffer on the stack.
+ *
+ * @mydata: Filesystem information
+ * @block: Block number to read, in terms of mydata->sect_size
+ * @nr_blocks: Number of blocks to read, in terms of mydata->sect_size
+ * @buf: Buffer for data
+ */
+static int disk_read_conv(fsdata *mydata, __u32 block, __u32 nr_blocks,
+ void *buf)
+{
+ uint factor, whole, remain, upto;
+ ulong base, index;
+ uint to_copy;
+ u8 tbuf[2048];
+ int ret;
+
+ log_debug("mydata %x, cur_dev %lx, block %x, nr_block %x\n",
+ mydata->sect_size, cur_dev->blksz, block, nr_blocks);
+ if (mydata->sect_size > cur_dev->blksz ||
+ cur_dev->blksz > sizeof(tbuf)) {
+ log_err("Block size %lx not supported\n", cur_dev->blksz);
+ return -EIO;
+ }
+ factor = cur_dev->blksz / mydata->sect_size;
+
+ /* get the first partial block */
+ base = cur_part_info.start + block / factor;
+ index = block % factor;
+ log_debug("cur_part_info.start %llx, block %x, base %lx, index %lx\n",
+ (unsigned long long)cur_part_info.start, block, base, index);
+ ret = blk_dread(cur_dev, base, 1, tbuf);
+ if (ret != 1)
+ return -EIO;
+
+ to_copy = min((ulong)nr_blocks, factor - index);
+ log_debug("to_copy %x\n", to_copy);
+ memcpy(buf, tbuf + index * mydata->sect_size,
+ to_copy * mydata->sect_size);
+ upto = to_copy;
+
+ /* load any whole blocks */
+ remain = nr_blocks - upto;
+ whole = remain / factor;
+ log_debug("factor %x, whole %x, remain %x\n", factor, whole, remain);
+ if (whole) {
+ ret = blk_dread(cur_dev, base + 1, whole,
+ buf + upto * mydata->sect_size);
+ if (ret != whole)
+ return -EIO;
+ upto += whole * factor;
+ remain = nr_blocks - upto;
+ }
+
+ /* load any blocks at the end */
+ log_debug("end: remain %x\n", remain);
+ if (remain) {
+ ret = blk_dread(cur_dev, base + 1 + whole, 1, tbuf);
+ if (ret != 1)
+ return -EIO;
+ memcpy(buf + upto * mydata->sect_size, tbuf,
+ remain * mydata->sect_size);
+ upto += remain;
+ }
+
+ return upto;
+}
+
+static int disk_read(fsdata *mydata, __u32 block, __u32 nr_blocks, void *buf)
{
ulong ret;
if (!cur_dev)
return -1;
+ /* support converting from a larger block size */
+ if (IS_ENABLED(CONFIG
[PATCH v3 38/43] x86: link: Support Micron memory
Add the required tag so that micron memory can be set up correctly.
Signed-off-by: Simon Glass
---
(no changes since v2)
Changes in v2:
- Add new patch to support Micron memory
arch/x86/dts/chromebook_link.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 36956f40bd7..c904b7d0b69 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -314,6 +314,7 @@
00 00 00 00 00 00 00 00];
};
micron_4Gb_1600_1.35v_x16 {
+ bootph-all;
reg = <2>;
data = [92 11 0b 03 04 19 02 02
03 11 01 08 0a 00 fe 00
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 36/43] x86: Show the number of physical address bits
Add this information to global_data and show it with the 'bdinfo' command.
For now we use CONFIG_CPU_ADDR_BITS to control the number of bits, but
this could change if needed.
Signed-off-by: Simon Glass
---
(no changes since v2)
Changes in v2:
- Add new patch to show the number of physical address bits
arch/x86/cpu/i386/cpu.c| 2 ++
arch/x86/include/asm/global_data.h | 1 +
arch/x86/lib/bdinfo.c | 1 +
3 files changed, 4 insertions(+)
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index 91cd5d7c9e4..5c17d279092 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -468,6 +468,7 @@ int x86_cpu_init_f(void)
if (ll_boot_init())
setup_cpu_features();
setup_identity();
+ gd->arch.phys_bits = cpu_phys_address_size();
setup_mtrr();
setup_pci_ram_top();
@@ -483,6 +484,7 @@ int x86_cpu_reinit_f(void)
long addr;
setup_identity();
+ gd->arch.phys_bits = cpu_phys_address_size();
setup_pci_ram_top();
addr = locate_coreboot_table();
if (addr >= 0) {
diff --git a/arch/x86/include/asm/global_data.h
b/arch/x86/include/asm/global_data.h
index ea58259ad77..5b802f79d50 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -127,6 +127,7 @@ struct arch_global_data {
ulong table_end;/* End address of x86 tables */
ulong table_start_high; /* Start address of high x86 tables */
ulong table_end_high; /* End address of high x86 tables */
+ uint phys_bits; /* Number of physical address bits */
};
#endif
diff --git a/arch/x86/lib/bdinfo.c b/arch/x86/lib/bdinfo.c
index 9504e7fc293..c5fda22679a 100644
--- a/arch/x86/lib/bdinfo.c
+++ b/arch/x86/lib/bdinfo.c
@@ -27,6 +27,7 @@ void arch_print_bdinfo(void)
bdinfo_print_num_l("table end", gd->arch.table_end);
bdinfo_print_num_l(" high start", gd->arch.table_start_high);
bdinfo_print_num_l(" high end", gd->arch.table_end_high);
+ bdinfo_print_num_l("phys bits", gd->arch.phys_bits);
if (IS_ENABLED(CONFIG_EFI_STUB))
efi_show_bdinfo();
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 37/43] x86: Convert some debug statements to use logging
Move from using debug() to log_debug() so that we don't have to use the
__func__ parameter and can access other logging features.
Signed-off-by: Simon Glass
---
(no changes since v2)
Changes in v2:
- Add new patch to convert some debug statements to use logging
arch/x86/cpu/intel_common/mrc.c | 10 +-
arch/x86/cpu/ivybridge/sdram.c | 4 +++-
arch/x86/lib/mrccache.c | 6 --
arch/x86/lib/spl.c | 22 ++
drivers/gpio/intel_ich6_gpio.c | 5 +++--
drivers/pch/pch9.c | 6 --
6 files changed, 33 insertions(+), 20 deletions(-)
diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c
index 69405d740b4..2819bae02e3 100644
--- a/arch/x86/cpu/intel_common/mrc.c
+++ b/arch/x86/cpu/intel_common/mrc.c
@@ -3,6 +3,8 @@
* Copyright (c) 2016 Google, Inc
*/
+#define LOG_CATEGORY UCLASS_RAM
+
#include
#include
#include
@@ -144,12 +146,10 @@ int mrc_locate_spd(struct udevice *dev, int size, const
void **spd_datap)
ret = gpio_request_list_by_name(dev, "board-id-gpios", desc,
ARRAY_SIZE(desc), GPIOD_IS_IN);
- if (ret < 0) {
- debug("%s: gpio ret=%d\n", __func__, ret);
- return ret;
- }
+ if (ret < 0)
+ return log_msg_ret("gp", ret);
spd_index = dm_gpio_get_values_as_int(desc, ret);
- debug("spd index %d\n", spd_index);
+ log_debug("spd index %d\n", spd_index);
node = fdt_first_subnode(blob, dev_of_offset(dev));
if (node < 0)
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 1a0ec433e65..0718aefbb1f 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -9,6 +9,8 @@
* Copyright (C) 2011 Google Inc.
*/
+#define LOG_CATEGORY UCLASS_RAM
+
#include
#include
#include
@@ -213,7 +215,7 @@ static int copy_spd(struct udevice *dev, struct pei_data
*peid)
ret = mrc_locate_spd(dev, sizeof(peid->spd_data[0]), &data);
if (ret) {
- debug("%s: Could not locate SPD (ret=%d)\n", __func__, ret);
+ log_debug("Could not locate SPD (err=%d)\n", ret);
return ret;
}
diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index 2f6f6880003..6494b8d2634 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -6,6 +6,8 @@
* Copyright (C) 2015 Bin Meng
*/
+#define LOG_CATEGORY UCLASS_RAM
+
#include
#include
#include
@@ -197,8 +199,8 @@ static void mrccache_setup(struct mrc_output *mrc, void
*data)
cache->signature = MRC_DATA_SIGNATURE;
cache->data_size = mrc->len;
checksum = compute_ip_checksum(mrc->buf, cache->data_size);
- debug("Saving %d bytes for MRC output data, checksum %04x\n",
- cache->data_size, checksum);
+ log_debug("Saving %d bytes for MRC output data, checksum %04x\n",
+ cache->data_size, checksum);
cache->checksum = checksum;
cache->reserved = 0;
memcpy(cache->data, mrc->buf, cache->data_size);
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index 090fa718dbf..6886587f647 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -3,6 +3,8 @@
* Copyright (c) 2016 Google, Inc
*/
+#define LOG_CATEGORY LOGC_BOOT
+
#include
#include
#include
@@ -76,25 +78,25 @@ static int x86_spl_init(void)
#endif
int ret;
- debug("%s starting\n", __func__);
+ log_debug("x86 spl starting\n");
if (IS_ENABLED(TPL))
ret = x86_cpu_reinit_f();
else
ret = x86_cpu_init_f();
ret = spl_init();
if (ret) {
- debug("%s: spl_init() failed\n", __func__);
+ log_debug("spl_init() failed (err=%d)\n", ret);
return ret;
}
ret = arch_cpu_init();
if (ret) {
- debug("%s: arch_cpu_init() failed\n", __func__);
+ log_debug("arch_cpu_init() failed (err=%d)\n", ret);
return ret;
}
#ifndef CONFIG_TPL
ret = fsp_setup_pinctrl(NULL, NULL);
if (ret) {
- debug("%s: fsp_setup_pinctrl() failed\n", __func__);
+ log_debug("fsp_setup_pinctrl() failed (err=%d)\n", ret);
return ret;
}
#endif
@@ -103,23 +105,25 @@ static int x86_spl_init(void)
#if !defined(CONFIG_TPL) && !CONFIG_IS_ENABLED(CPU)
ret = print_cpuinfo();
if (ret) {
- debug("%s: print_cpuinfo() failed\n", __func__);
+ log_debug("print_cpuinfo() failed (err=%d)\n", ret);
return ret;
}
#endif
ret = dram_init();
if (ret) {
- debug("%s: dram_init() failed\n", __func__);
+ log_debug("dram_init() failed (err=%d)\n", ret);
return ret;
}
+ log_debug("mrc\n");
if (IS_ENABLED(CONFI
[PATCH v3 24/43] x86: Allow video-BIOS code to be built for SPL
With qemu-x86_64 we need to run the video BIOS while in 32-bit mode, i.e.
SPL. Add a Kconfig option for this, adjust the Makefile rules and use
CONFIG_IS_ENABLED() where needed.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/lib/Makefile | 7 ---
arch/x86/lib/bios.c | 2 +-
drivers/pci/pci_rom.c | 28 ++--
3 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index b0612ae6dd5..90a7618ecfd 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -4,16 +4,17 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
obj-y += bdinfo.o
-ifndef CONFIG_X86_64
-ifndef CONFIG_TPL_BUILD
+
+ifndef CONFIG_$(SPL_TPL_)X86_64
obj-y += bios.o
obj-y += bios_asm.o
obj-y += bios_interrupts.o
endif
-endif
+
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_X86_32BIT_INIT) += string.o
endif
+
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_CMD_BOOTM) += bootm.o
endif
diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c
index 8cc686fd146..e29cae78e50 100644
--- a/arch/x86/lib/bios.c
+++ b/arch/x86/lib/bios.c
@@ -23,7 +23,7 @@
static int (*int_handler[256])(void);
/* to have a common register file for interrupt handlers */
-#ifndef CONFIG_BIOSEMU
+#if !CONFIG_IS_ENABLED(BIOSEMU)
X86EMU_sysEnv _X86EMU_env;
#endif
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index dab0f197906..2d9a2a899ef 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -344,20 +344,20 @@ int dm_pci_run_vga_bios(struct udevice *dev, int
(*int15_handler)(void),
}
if (emulate) {
-#ifdef CONFIG_BIOSEMU
- BE_VGAInfo *info;
-
- log_debug("Running video BIOS with emulator...");
- ret = biosemu_setup(dev, &info);
- if (ret)
- goto err;
- biosemu_set_interrupt_handler(0x15, int15_handler);
- ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info,
- true, vesa_mode, &mode_info);
- log_debug("done\n");
- if (ret)
- goto err;
-#endif
+ if (CONFIG_IS_ENABLED(BIOSEMU)) {
+ BE_VGAInfo *info;
+
+ log_debug("Running video BIOS with emulator...");
+ ret = biosemu_setup(dev, &info);
+ if (ret)
+ goto err;
+ biosemu_set_interrupt_handler(0x15, int15_handler);
+ ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info,
+ true, vesa_mode, &mode_info);
+ log_debug("done\n");
+ if (ret)
+ goto err;
+ }
} else {
#if defined(CONFIG_X86) && (CONFIG_IS_ENABLED(X86_32BIT_INIT) || CONFIG_TPL)
log_debug("Running video BIOS...");
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 35/43] x86: Record the start and end of the tables
The ACPI tables are special in that they are passed to EFI as a separate
piece, independent of other tables.
Also they can be spread over two areas of memory, e.g. with QEMU we end
up with tables kept in high memory as well.
Add new global_data fields to hold this information and update the bdinfo
command to show the table areas.
Move the rom_table_end variable into the loop that uses it.
Signed-off-by: Simon Glass
---
Changes in v3:
- Adjust the code to handle qemu writing a pointer to tables in memory
Changes in v2:
- Handle the case where the tables are in the bloblist
arch/sandbox/include/asm/global_data.h | 4
arch/x86/include/asm/global_data.h | 4
arch/x86/lib/bdinfo.c | 4
arch/x86/lib/tables.c | 18 +-
drivers/misc/qfw.c | 8
5 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/arch/sandbox/include/asm/global_data.h
b/arch/sandbox/include/asm/global_data.h
index f4ce72d5660..f0ab3ba5c14 100644
--- a/arch/sandbox/include/asm/global_data.h
+++ b/arch/sandbox/include/asm/global_data.h
@@ -13,6 +13,10 @@
struct arch_global_data {
uint8_t *ram_buf; /* emulated RAM buffer */
void*text_base; /* pointer to base of text region */
+ ulong table_start; /* Start address of x86 tables */
+ ulong table_end;/* End address of x86 tables */
+ ulong table_start_high; /* Start address of high x86 tables */
+ ulong table_end_high; /* End address of high x86 tables */
};
#include
diff --git a/arch/x86/include/asm/global_data.h
b/arch/x86/include/asm/global_data.h
index 22d103df4ee..ea58259ad77 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -123,6 +123,10 @@ struct arch_global_data {
#endif
void *itss_priv;/* Private ITSS data pointer */
ulong coreboot_table; /* Address of coreboot table */
+ ulong table_start; /* Start address of x86 tables */
+ ulong table_end;/* End address of x86 tables */
+ ulong table_start_high; /* Start address of high x86 tables */
+ ulong table_end_high; /* End address of high x86 tables */
};
#endif
diff --git a/arch/x86/lib/bdinfo.c b/arch/x86/lib/bdinfo.c
index 0970efa4726..9504e7fc293 100644
--- a/arch/x86/lib/bdinfo.c
+++ b/arch/x86/lib/bdinfo.c
@@ -23,6 +23,10 @@ void arch_print_bdinfo(void)
bdinfo_print_str(" name", cpu_vendor_name(gd->arch.x86_vendor));
bdinfo_print_num_l("model", gd->arch.x86_model);
bdinfo_print_num_l("phys_addr", cpu_phys_address_size());
+ bdinfo_print_num_l("table start", gd->arch.table_start);
+ bdinfo_print_num_l("table end", gd->arch.table_end);
+ bdinfo_print_num_l(" high start", gd->arch.table_start_high);
+ bdinfo_print_num_l(" high end", gd->arch.table_end_high);
if (IS_ENABLED(CONFIG_EFI_STUB))
efi_show_bdinfo();
diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index 132c02ee80f..d95fdb20500 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -54,6 +54,10 @@ static struct table_info table_list[] = {
#ifdef CONFIG_GENERATE_MP_TABLE
{ "mp", write_mp_table, },
#endif
+ /*
+* tables which can go in the bloblist must be last in this list, so
+* that the calculation of gd->table_end works properly
+*/
#ifdef CONFIG_GENERATE_ACPI_TABLE
{ "acpi", write_acpi_tables, BLOBLISTT_ACPI_TABLES, 0x1, 0x1000},
#endif
@@ -80,10 +84,12 @@ int write_tables(void)
{
u32 high_table, table_size;
struct memory_area cfg_tables[ARRAY_SIZE(table_list) + 1];
+ bool use_high = false;
u32 rom_addr;
int i;
- rom_addr = ROM_TABLE_ADDR;
+ gd->arch.table_start = ROM_TABLE_ADDR;
+ rom_addr = gd->arch.table_start;
debug("Writing tables to %x:\n", rom_addr);
for (i = 0; i < ARRAY_SIZE(table_list); i++) {
@@ -92,10 +98,15 @@ int write_tables(void)
u32 rom_table_end;
if (IS_ENABLED(CONFIG_BLOBLIST_TABLES) && table->tag) {
+ if (!gd->arch.table_end)
+ gd->arch.table_end = rom_addr;
rom_addr = (ulong)bloblist_add(table->tag, size,
table->align);
if (!rom_addr)
return log_msg_ret("bloblist", -ENOBUFS);
+ use_high = true;
+ if (!gd->arch.table_start_high)
+ gd->arch.table_start_high = rom_addr;
}
rom_table_end = table->write(rom_addr);
if (!rom_table_end) {
@@ -132,6 +143,11 @@ int write_tables(void)
rom_addr = ro
[PATCH v3 33/43] x86: Enable useful options for qemu-86_64
This build can be used to boot standard distro builds, since these are mostly 64-bit these days. Enable some more options, so that all possible EFI UUIDs are decoded, we get a proper printf() in SPL, can search memory for tables, support the full set of standard-boot features, have full logging and can boot from CDROM media. Signed-off-by: Simon Glass --- (no changes since v1) configs/qemu-x86_64_defconfig | 8 1 file changed, 8 insertions(+) diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 371ca9de842..79ea3591857 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -19,6 +19,7 @@ CONFIG_GENERATE_MP_TABLE=y CONFIG_X86_OFFSET_U_BOOT=0xfff0 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTSTD_FULL=y CONFIG_SYS_MONITOR_BASE=0x0111 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTSTAGE=y @@ -27,6 +28,9 @@ CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_LOG=y +CONFIG_LOGF_FUNC=y +CONFIG_SPL_LOG=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_PCI_INIT_R=y @@ -46,12 +50,14 @@ CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEM_SEARCH=y CONFIG_CMD_IDE=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_BOOTFILESIZE=y # CONFIG_CMD_NFS is not set +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_CMD_QFW=y CONFIG_CMD_BOOTSTAGE=y @@ -83,5 +89,7 @@ CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_USER=y CONFIG_FRAMEBUFFER_VESA_MODE=0x144 CONFIG_CONSOLE_SCROLL_LINES=5 +CONFIG_FAT_BLK_XLATE=y +# CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_GENERATE_ACPI_TABLE=y # CONFIG_GZIP is not set -- 2.40.1.521.gf1e218fcd8-goog
[PATCH v3 31/43] fs: fat: Shrink the size of a few strings
To save a few bytes, replace Error with ** and try to use the same string
for multiple messages where possible.
Signed-off-by: Simon Glass
---
(no changes since v2)
Changes in v2:
- Drop ** in strings and use log_err() for messages
fs/fat/fat.c | 20 +++-
fs/fat/fat_write.c | 14 --
2 files changed, 15 insertions(+), 19 deletions(-)
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 2da93dae3cf..d1476aa433d 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -8,6 +8,8 @@
* 2003-03-10 - khar...@nexus-tech.net - ported to uboot
*/
+#define LOG_CATEGORY LOGC_FS
+
#include
#include
#include
@@ -97,8 +99,8 @@ int fat_register_device(struct blk_desc *dev_desc, int
part_no)
/* Read the partition table, if present */
if (part_get_info(dev_desc, part_no, &info)) {
if (part_no != 0) {
- printf("** Partition %d not valid on device %d **\n",
- part_no, dev_desc->devnum);
+ log_err("Partition %d invalid on device %d\n", part_no,
+ dev_desc->devnum);
return -1;
}
@@ -168,7 +170,7 @@ static __u32 get_fatent(fsdata *mydata, __u32 entry)
__u32 ret = 0x00;
if (CHECK_CLUST(entry, mydata->fatsize)) {
- printf("Error: Invalid FAT entry: 0x%08x\n", entry);
+ log_err("Invalid FAT entry: %#08x\n", entry);
return ret;
}
@@ -586,19 +588,19 @@ static int get_fs_info(fsdata *mydata)
mydata->sect_size = (bs.sector_size[1] << 8) + bs.sector_size[0];
mydata->clust_size = bs.cluster_size;
if (mydata->sect_size != cur_part_info.blksz) {
- printf("Error: FAT sector size mismatch (fs=%hu, dev=%lu)\n",
- mydata->sect_size, cur_part_info.blksz);
+ log_err("FAT sector size mismatch (fs=%u, dev=%lu)\n",
+ mydata->sect_size, cur_part_info.blksz);
return -1;
}
if (mydata->clust_size == 0) {
- printf("Error: FAT cluster size not set\n");
+ log_err("FAT cluster size not set\n");
return -1;
}
if ((unsigned int)mydata->clust_size * mydata->sect_size >
MAX_CLUSTSIZE) {
- printf("Error: FAT cluster size too big (cs=%u, max=%u)\n",
- (unsigned int)mydata->clust_size * mydata->sect_size,
- MAX_CLUSTSIZE);
+ log_err("FAT cluster size too big (cs=%u, max=%u)\n",
+ (uint)mydata->clust_size * mydata->sect_size,
+ MAX_CLUSTSIZE);
return -1;
}
diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
index 413fc432ebe..e2a9913f807 100644
--- a/fs/fat/fat_write.c
+++ b/fs/fat/fat_write.c
@@ -1571,8 +1571,9 @@ int fat_unlink(const char *filename)
char *filename_copy, *dirname, *basename;
filename_copy = strdup(filename);
- if (!filename_copy) {
- printf("Error: allocating memory\n");
+ itr = malloc_cache_aligned(sizeof(fat_itr));
+ if (!itr || !filename_copy) {
+ printf("Error: out of memory\n");
ret = -ENOMEM;
goto exit;
}
@@ -1584,13 +1585,6 @@ int fat_unlink(const char *filename)
goto exit;
}
- itr = malloc_cache_aligned(sizeof(fat_itr));
- if (!itr) {
- printf("Error: allocating memory\n");
- ret = -ENOMEM;
- goto exit;
- }
-
ret = fat_itr_root(itr, &fsdata);
if (ret)
goto exit;
@@ -1605,7 +1599,7 @@ int fat_unlink(const char *filename)
}
if (!find_directory_entry(itr, basename)) {
- printf("%s: doesn't exist\n", basename);
+ log_err("%s: doesn't exist (%d)\n", basename, -ENOENT);
ret = -ENOENT;
goto exit;
}
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 30/43] x86: Allow logging to be used in SPL reliably
When global_data is relocated, log_head moves in memory, meaning that
the items in that list point to the wrong place.
Disable logging when making the change, then reenable it afterwards, so
that logging works normally.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/lib/spl.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index 8d57f98f6c1..090fa718dbf 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -139,9 +139,22 @@ static int x86_spl_init(void)
*/
gd->new_gd = (struct global_data *)ptr;
memcpy(gd->new_gd, gd, sizeof(*gd));
+
+ /*
+* Make sure logging is disabled when we switch, since the log system
+* list head will move
+*/
+ gd->new_gd->flags &= ~GD_FLG_LOG_READY;
arch_setup_gd(gd->new_gd);
gd->start_addr_sp = (ulong)ptr;
+ /* start up logging again, with the new list-head location */
+ ret = log_init();
+ if (ret) {
+ log_debug("Log setup failed (err=%d)\n", ret);
+ return ret;
+ }
+
if (_LOG_DEBUG) {
ret = mtrr_list(mtrr_get_var_count(), MP_SELECT_BSP);
if (ret)
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 28/43] pci: Mask the ROM address in case it is already enabled
In some cases the video ROM may have been enabled previously, such as by
a previous firmware stage. Use the correct address in that case.
Signed-off-by: Simon Glass
---
(no changes since v1)
drivers/pci/pci_rom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index 62cfe60c0fb..ba2cf18d53e 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -93,6 +93,7 @@ static int pci_rom_probe(struct udevice *dev, struct
pci_rom_header **hdrp)
debug("%s: rom_address=%x\n", __func__, rom_address);
return -ENOENT;
}
+ rom_address &= PCI_ROM_ADDRESS_MASK;
/* Enable expansion ROM address decoding. */
dm_pci_write_config32(dev, PCI_ROM_ADDRESS,
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 29/43] x86: Enable display for QEMU 64-bit
Enable the various options needed for display to work on the qemu-x86_64 board. This includes expanding the available malloc() memory in SPL, since the PCI bus must be enumerated in order to find the video device. It also includes enabling a bloblist, so that the video parameters can be passed. This is placed at address 1 but is not needed after U-Boot proper reads the information there. Signed-off-by: Simon Glass --- (no changes since v1) configs/qemu-x86_64_defconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index f29a5aa0f81..371ca9de842 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -7,6 +7,7 @@ CONFIG_MAX_CPUS=2 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx" CONFIG_SPL_TEXT_BASE=0xfffd +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_X86_RUN_64BIT=y @@ -29,7 +30,10 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_PCI_INIT_R=y +CONFIG_BLOBLIST=y +CONFIG_BLOBLIST_ADDR=0x1 CONFIG_SPL_NO_BSS_LIMIT=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_CPU=y CONFIG_SPL_ENV_SUPPORT=y @@ -69,10 +73,12 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_NVME_PCI=y +CONFIG_SPL_PCI_PNP=y CONFIG_SPL_DM_RTC=y CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_KEYBOARD=y +CONFIG_SPL_VIDEO=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_USER=y CONFIG_FRAMEBUFFER_VESA_MODE=0x144 -- 2.40.1.521.gf1e218fcd8-goog
[PATCH v3 23/43] pci: Tidy up logging and reporting for video BIOS
When running the ROM the code is not very helpful when something goes
wrong. Add a little more debugging and some logging of return values to
improve this.
Signed-off-by: Simon Glass
---
(no changes since v1)
drivers/pci/pci_rom.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index 0f44238bbbc..dab0f197906 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -300,14 +300,16 @@ int dm_pci_run_vga_bios(struct udevice *dev, int
(*int15_handler)(void),
ret = pci_rom_probe(dev, &rom);
if (ret)
- return ret;
+ return log_msg_ret("pro", ret);
ret = pci_rom_load(rom, &ram, &alloced);
- if (ret)
+ if (ret) {
+ ret = log_msg_ret("ld", ret);
goto err;
+ }
if (!board_should_run_oprom(dev)) {
- ret = -ENXIO;
+ ret = log_msg_ret("run", -ENXIO);
goto err;
}
@@ -345,21 +347,25 @@ int dm_pci_run_vga_bios(struct udevice *dev, int
(*int15_handler)(void),
#ifdef CONFIG_BIOSEMU
BE_VGAInfo *info;
+ log_debug("Running video BIOS with emulator...");
ret = biosemu_setup(dev, &info);
if (ret)
goto err;
biosemu_set_interrupt_handler(0x15, int15_handler);
ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info,
true, vesa_mode, &mode_info);
+ log_debug("done\n");
if (ret)
goto err;
#endif
} else {
#if defined(CONFIG_X86) && (CONFIG_IS_ENABLED(X86_32BIT_INIT) || CONFIG_TPL)
+ log_debug("Running video BIOS...");
bios_set_interrupt_handler(0x15, int15_handler);
bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,
&mode_info);
+ log_debug("done\n");
#endif
}
debug("Final vesa mode %#x\n", mode_info.video_mode);
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 26/43] x86: Init video in SPL if enabled
When video is required in SPL, set this up ready for use. Ignore any
problems since it may be that video is not actually available and we
still want to continue on to U-Boot proper in that case.
Make sure that the SPL banner is only shown once.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/lib/spl.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index b9d23e6bfe1..8d57f98f6c1 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -97,7 +98,8 @@ static int x86_spl_init(void)
return ret;
}
#endif
- preloader_console_init();
+ if (!IS_ENABLED(CONFIG_SPL_BOARD_INIT))
+ preloader_console_init();
#if !defined(CONFIG_TPL) && !CONFIG_IS_ENABLED(CPU)
ret = print_cpuinfo();
if (ret) {
@@ -257,4 +259,12 @@ void spl_board_init(void)
#ifndef CONFIG_TPL
preloader_console_init();
#endif
+
+ if (CONFIG_IS_ENABLED(VIDEO)) {
+ struct udevice *dev;
+
+ /* Set up PCI video in SPL if required */
+ uclass_first_device_err(UCLASS_PCI, &dev);
+ uclass_first_device_err(UCLASS_VIDEO, &dev);
+ }
}
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 25/43] x86: Pass video settings from SPL to U-Boot proper
When video is set up in SPL, U-Boot proper needs to use the correct
parameters so it can write to the display.
Put these in a bloblist so they are available to U-Boot proper.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add a tag name for the blob
common/bloblist.c | 1 +
drivers/pci/pci_rom.c | 78 +++
include/bloblist.h| 1 +
include/video.h | 24 +
4 files changed, 83 insertions(+), 21 deletions(-)
diff --git a/common/bloblist.c b/common/bloblist.c
index 0d63b6e8817..2144b10e1d0 100644
--- a/common/bloblist.c
+++ b/common/bloblist.c
@@ -51,6 +51,7 @@ static struct tag_name {
/* BLOBLISTT_PROJECT_AREA */
{ BLOBLISTT_U_BOOT_SPL_HANDOFF, "SPL hand-off" },
+ { BLOBLISTT_U_BOOT_VIDEO, "SPL video handoff" },
/* BLOBLISTT_VENDOR_AREA */
};
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index 2d9a2a899ef..ecb6da64c5c 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -26,6 +26,7 @@
#include
#include
+#include
#include
#include
#include
@@ -34,6 +35,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -420,34 +422,68 @@ int vesa_setup_video(struct udevice *dev, int
(*int15_handler)(void))
printf("Not available (previous bootloader prevents it)\n");
return -EPERM;
}
- bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
- ret = dm_pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
- PCI_ROM_ALLOW_FALLBACK);
- bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
- if (ret) {
- debug("failed to run video BIOS: %d\n", ret);
- return ret;
- }
- ret = vesa_setup_video_priv(&mode_info.vesa,
- mode_info.vesa.phys_base_ptr, uc_priv,
- plat);
- if (ret) {
- if (ret == -ENFILE) {
- /*
-* See video-uclass.c for how to set up reserved memory
-* in your video driver
-*/
- log_err("CONFIG_VIDEO_COPY enabled but driver '%s' set
up no reserved memory\n",
- dev->driver->name);
+ /* In U-Boot proper, collect the information added by SPL (see below) */
+ if (IS_ENABLED(CONFIG_SPL_VIDEO) && spl_phase() > PHASE_SPL &&
+ CONFIG_IS_ENABLED(BLOBLIST)) {
+ struct video_handoff *ho;
+
+ ho = bloblist_find(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho));
+ if (!ho)
+ return log_msg_ret("blf", -ENOENT);
+ plat->base = ho->fb;
+ plat->size = ho->size;
+ uc_priv->xsize = ho->xsize;
+ uc_priv->ysize = ho->ysize;
+ uc_priv->line_length = ho->line_length;
+ uc_priv->bpix = ho->bpix;
+ } else {
+ bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
+ ret = dm_pci_run_vga_bios(dev, int15_handler,
+ PCI_ROM_USE_NATIVE |
+ PCI_ROM_ALLOW_FALLBACK);
+ bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
+ if (ret) {
+ debug("failed to run video BIOS: %d\n", ret);
+ return ret;
}
- debug("No video mode configured\n");
- return ret;
+ ret = vesa_setup_video_priv(&mode_info.vesa,
+ mode_info.vesa.phys_base_ptr,
+ uc_priv, plat);
+ if (ret) {
+ if (ret == -ENFILE) {
+ /*
+* See video-uclass.c for how to set up reserved
+* memory in your video driver
+*/
+ log_err("CONFIG_VIDEO_COPY enabled but driver
'%s' set up no reserved memory\n",
+ dev->driver->name);
+ }
+
+ debug("No video mode configured\n");
+ return ret;
+ }
}
printf("Video: %dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
mode_info.vesa.bits_per_pixel);
+ /* In SPL, store the information for use by U-Boot proper */
+ if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(BLOBLIST)) {
+ struct video_handoff *ho;
+
+ ho = bloblist_add(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho), 0);
+ if (!ho)
+ return log_msg_ret("blc", -ENOMEM);
+
+ ho->fb = plat->base;
+ ho->size = plat->size;
+ ho->xsize = uc_priv->xsize;
+ ho->ysiz
[PATCH v3 21/43] pci: Support autoconfig in SPL
Allow PCI autoconfig to be handled in SPL, so that we can set it up
correctly for boards which need to do this before U-Boot proper. This
includes qemu-x64_64 which needs to set up the video device while in
32-bit mode.
Signed-off-by: Simon Glass
---
(no changes since v1)
drivers/pci/Kconfig | 8
drivers/pci/pci-uclass.c | 10 +-
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ef328d26525..165f111a4f5 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -40,6 +40,14 @@ config PCI_PNP
help
Enable PCI memory and I/O space resource allocation and assignment.
+config SPL_PCI_PNP
+ bool "Enable Plug & Play support for PCI"
+ help
+ Enable PCI memory and I/O space resource allocation and assignment.
+ This is normally not done in SPL, but can be enabled if devices must
+ be set up in the SPL phase. Often it is enough to manually configure
+ one device, so this option can be disabled.
+
config PCI_REGION_MULTI_ENTRY
bool "Enable Multiple entries of region type MEMORY in ranges for PCI"
help
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 8d27e40338c..632c1a63cfc 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -722,6 +723,9 @@ static bool pci_need_device_pre_reloc(struct udevice *bus,
uint vendor,
u32 vendev;
int index;
+ if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(PCI_PNP))
+ return true;
+
for (index = 0;
!dev_read_u32_index(bus, "u-boot,pci-pre-reloc", index,
&vendev);
@@ -793,7 +797,9 @@ static int pci_find_and_bind_driver(struct udevice *parent,
* space is pretty limited (ie: using Cache As RAM).
*/
if (!(gd->flags & GD_FLG_RELOC) &&
- !(drv->flags & DM_FLAG_PRE_RELOC))
+ !(drv->flags & DM_FLAG_PRE_RELOC) &&
+ (!CONFIG_IS_ENABLED(PCI_PNP) ||
+spl_phase() != PHASE_SPL))
return log_msg_ret("pre", -EPERM);
/*
@@ -918,6 +924,8 @@ int pci_bind_bus_devices(struct udevice *bus)
}
ret = pci_find_and_bind_driver(bus, &find_id, bdf,
&dev);
+ } else {
+ debug("device: %s\n", dev->name);
}
if (ret == -EPERM)
continue;
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 20/43] nvme: Provide more useful debugging messages
When scanning fails it is useful to be able to decode what went wrong. Add
some debugging for this.
Signed-off-by: Simon Glass
---
(no changes since v1)
drivers/nvme/nvme.c | 36 ++--
1 file changed, 26 insertions(+), 10 deletions(-)
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index 74e7a5b0110..a7add66ab4d 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -578,17 +578,22 @@ static int nvme_set_queue_count(struct nvme_dev *dev, int
count)
return min(result & 0x, result >> 16) + 1;
}
-static void nvme_create_io_queues(struct nvme_dev *dev)
+static int nvme_create_io_queues(struct nvme_dev *dev)
{
unsigned int i;
+ int ret;
for (i = dev->queue_count; i <= dev->max_qid; i++)
if (!nvme_alloc_queue(dev, i, dev->q_depth))
- break;
+ return log_msg_ret("all", -ENOMEM);
- for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
- if (nvme_create_queue(dev->queues[i], i))
- break;
+ for (i = dev->online_queues; i <= dev->queue_count - 1; i++) {
+ ret = nvme_create_queue(dev->queues[i], i);
+ if (ret)
+ return log_msg_ret("cre", ret);
+ }
+
+ return 0;
}
static int nvme_setup_io_queues(struct nvme_dev *dev)
@@ -598,14 +603,18 @@ static int nvme_setup_io_queues(struct nvme_dev *dev)
nr_io_queues = 1;
result = nvme_set_queue_count(dev, nr_io_queues);
- if (result <= 0)
+ if (result <= 0) {
+ log_debug("Cannot set queue count (err=%dE)\n", result);
return result;
+ }
dev->max_qid = nr_io_queues;
/* Free previously allocated queues */
nvme_free_queues(dev, nr_io_queues + 1);
- nvme_create_io_queues(dev);
+ result = nvme_create_io_queues(dev);
+ if (result)
+ return result;
return 0;
}
@@ -683,8 +692,11 @@ int nvme_scan_namespace(void)
uclass_foreach_dev(dev, uc) {
ret = device_probe(dev);
- if (ret)
+ if (ret) {
+ log_err("Failed to probe '%s': err=%dE\n", dev->name,
+ ret);
return ret;
+ }
}
return 0;
@@ -842,8 +854,10 @@ int nvme_init(struct udevice *udev)
ndev->dbs = ((void __iomem *)ndev->bar) + 4096;
ret = nvme_configure_admin_queue(ndev);
- if (ret)
+ if (ret) {
+ log_debug("Unable to configure admin queue (err=%dE)\n", ret);
goto free_queue;
+ }
/* Allocate after the page size is known */
ndev->prp_pool = memalign(ndev->page_size, MAX_PRP_POOL);
@@ -855,8 +869,10 @@ int nvme_init(struct udevice *udev)
ndev->prp_entry_num = MAX_PRP_POOL >> 3;
ret = nvme_setup_io_queues(ndev);
- if (ret)
+ if (ret) {
+ log_debug("Unable to setup I/O queues(err=%dE)\n", ret);
goto free_queue;
+ }
nvme_get_info_from_identify(ndev);
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 18/43] x86: Improve the trampoline in 64-bit mode
At present this leaves the stack at the pre-relocation value. This is not
ideal since we want to have U-Boot running entirely from the top of
memory.
In addition, the new global_data pointer is not actually used, since
the global_data pointer itself is relocated, then the pre-relocation value
is changed, so the effective value (after relocation) does not update.
Adjust the implementation to follow the 32-bit code more closely, with a
trampoline function which is passed the new stack and global_data pointer.
This ensures that the correct values come through even when relocating.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/cpu/start64.S| 19 +++
arch/x86/include/asm/u-boot-x86.h | 11 +++
common/board_f.c | 12 +++-
3 files changed, 37 insertions(+), 5 deletions(-)
diff --git a/arch/x86/cpu/start64.S b/arch/x86/cpu/start64.S
index 7be834788b9..78e894d2a21 100644
--- a/arch/x86/cpu/start64.S
+++ b/arch/x86/cpu/start64.S
@@ -26,3 +26,22 @@ _start:
/* Should not return here */
jmp .
+
+.globl board_init_f_r_trampoline64
+.type board_init_f_r_trampoline64, @function
+board_init_f_r_trampoline64:
+ /*
+* SDRAM has been initialised, U-Boot code has been copied into
+* RAM, BSS has been cleared and relocation adjustments have been
+* made. It is now time to jump into the in-RAM copy of U-Boot
+*
+* %eax = Address of top of new stack
+*/
+
+ /* Stack grows down from top of SDRAM */
+ movq%rsi, %rsp
+
+ /* New gd is in rdi */
+
+ /* Re-enter U-Boot by calling board_init_f_r() */
+ callboard_init_f_r
diff --git a/arch/x86/include/asm/u-boot-x86.h
b/arch/x86/include/asm/u-boot-x86.h
index 1d8aa320f53..02a8b0f1527 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -117,6 +117,17 @@ void __noreturn board_init_f_r_trampoline(ulong sp);
*/
void __noreturn board_init_f_r(void);
+/*
+ * board_init_f_r_trampoline64() - jump to relocated address with new stack
+ *
+ * This is the 64-bit version
+ *
+ * @new_gd: New global_data pointer to use
+ * @sp: New stack pointer to pass on to board_init_r()
+ */
+void __noreturn board_init_f_r_trampoline64(struct global_data *new_gd,
+ ulong sp);
+
int arch_misc_init(void);
/* Read the time stamp counter */
diff --git a/common/board_f.c b/common/board_f.c
index 1688e27071f..abd589c9c99 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -731,8 +731,7 @@ static int fix_fdt(void)
#endif
/* ARM calls relocate_code from its crt0.S */
-#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
- !CONFIG_IS_ENABLED(X86_64)
+#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
static int jump_to_copy(void)
{
@@ -754,7 +753,11 @@ static int jump_to_copy(void)
* (CPU cache)
*/
arch_setup_gd(gd->new_gd);
- board_init_f_r_trampoline(gd->start_addr_sp);
+# if CONFIG_IS_ENABLED(X86_64)
+ board_init_f_r_trampoline64(gd->new_gd, gd->start_addr_sp);
+# else
+ board_init_f_r_trampoline(gd->start_addr_sp);
+# endif
#else
relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
#endif
@@ -969,8 +972,7 @@ static const init_fnc_t init_sequence_f[] = {
* watchdog device is not serviced is as small as possible.
*/
cyclic_unregister_all,
-#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
- !CONFIG_IS_ENABLED(X86_64)
+#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
jump_to_copy,
#endif
NULL,
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 19/43] Show the malloc base with the bdinfo command
It is useful to see the base of the malloc region. This is visible when
debugging but not in normal usage.
Add it to the global data so that it can be shown.
Signed-off-by: Simon Glass
---
(no changes since v1)
cmd/bdinfo.c | 1 +
common/board_r.c | 7 ---
include/asm-generic/global_data.h | 11 +++
3 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 4e0c763a709..f1f8d59673f 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -148,6 +148,7 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
if (IS_ENABLED(CONFIG_CMD_BDINFO_EXTRA)) {
bdinfo_print_num_ll("stack ptr", (ulong)&bd);
bdinfo_print_num_ll("ram_top ptr", (ulong)gd->ram_top);
+ bdinfo_print_num_l("malloc base", gd_malloc_start());
}
arch_print_bdinfo();
diff --git a/common/board_r.c b/common/board_r.c
index d798c00a80a..4aaa8940311 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -196,7 +196,7 @@ static int initr_barrier(void)
static int initr_malloc(void)
{
- ulong malloc_start;
+ ulong start;
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
debug("Pre-reloc malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr,
@@ -207,8 +207,9 @@ static int initr_malloc(void)
* This value MUST match the value of gd->start_addr_sp in board_f.c:
* reserve_noncached().
*/
- malloc_start = gd->relocaddr - TOTAL_MALLOC_LEN;
- mem_malloc_init((ulong)map_sysmem(malloc_start, TOTAL_MALLOC_LEN),
+ start = gd->relocaddr - TOTAL_MALLOC_LEN;
+ gd_set_malloc_start(start);
+ mem_malloc_init((ulong)map_sysmem(start, TOTAL_MALLOC_LEN),
TOTAL_MALLOC_LEN);
return 0;
}
diff --git a/include/asm-generic/global_data.h
b/include/asm-generic/global_data.h
index a1e1b9d6400..a5cf87f86b3 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -301,6 +301,10 @@ struct global_data {
* @timebase_l: low 32 bits of timer
*/
unsigned int timebase_l;
+ /**
+* @malloc_start: start of malloc() region
+*/
+ CONFIG_IS_ENABLED(CMD_BDINFO_EXTRA, (ulong malloc_start;))
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
/**
* @malloc_base: base address of early malloc()
@@ -560,6 +564,13 @@ static_assert(sizeof(struct global_data) == GD_SIZE);
#define gd_event_state() NULL
#endif
+#if CONFIG_IS_ENABLED(CMD_BDINFO_EXTRA)
+#define gd_malloc_start() gd->malloc_start
+#define gd_set_malloc_start(_val) gd->malloc_start = (_val)
+#else
+#define gd_malloc_start() 0
+#define gd_set_malloc_start(val)
+#endif
/**
* enum gd_flags - global data flags
*
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 15/43] video: Allow building video drivers for SPL
Update the Makefile rules to allow video drivers in SPL. This is useful for 64-bit QEMU on x86, since the video BIOS can only be run from 32-bit mode (i.e. in SPL). Signed-off-by: Simon Glass --- (no changes since v1) drivers/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/Makefile b/drivers/Makefile index c70466dbcbe..aae6a4667dc 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -38,6 +38,8 @@ obj-$(CONFIG_$(SPL_)SYSINFO) += sysinfo/ obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/ obj-$(CONFIG_XEN) += xen/ obj-$(CONFIG_$(SPL_)FPGA) += fpga/ +obj-$(CONFIG_$(SPL_TPL_)VIDEO) += video/ + obj-y += bus/ ifndef CONFIG_TPL_BUILD @@ -98,7 +100,6 @@ obj-y += rtc/ obj-y += scsi/ obj-y += sound/ obj-y += spmi/ -obj-y += video/ obj-y += watchdog/ obj-$(CONFIG_QE) += qe/ obj-$(CONFIG_U_QE) += qe/ -- 2.40.1.521.gf1e218fcd8-goog
[PATCH v3 17/43] efi: Show all known UUIDs with CONFIG_CMD_EFIDEBUG
The CMD_EFIDEBUG option enables debugging so it is reasonable to assume
that all effects should be made to decode the dreaded UUIDs favoured by
UEFI.
Update the table to show them all when CONFIG_CMD_EFIDEBUG is enabled.
Signed-off-by: Simon Glass
---
(no changes since v1)
lib/uuid.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/uuid.c b/lib/uuid.c
index 96e1af3c8b0..ab30fbf9152 100644
--- a/lib/uuid.c
+++ b/lib/uuid.c
@@ -255,7 +255,7 @@ static const struct {
EFI_CERT_TYPE_PKCS7_GUID,
},
#endif
-#ifdef CONFIG_EFI
+#if defined(CONFIG_CMD_EFIDEBUG) || defined(CONFIG_EFI)
{ "EFI_LZMA_COMPRESSED", EFI_LZMA_COMPRESSED },
{ "EFI_DXE_SERVICES", EFI_DXE_SERVICES },
{ "EFI_HOB_LIST", EFI_HOB_LIST },
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 12/43] part: Allow setting the partition-table type
Some devices have multiple partition types available on the same media.
It is sometimes useful to see these to check that everything is working
correctly.
Provide a way to manually set the partition-table type, avoiding the
auto-detection process.
Signed-off-by: Simon Glass
---
(no changes since v1)
cmd/part.c | 34 +++
disk/part.c| 16 +
doc/usage/cmd/part.rst | 74 ++
include/part.h | 9 +
4 files changed, 133 insertions(+)
diff --git a/cmd/part.c b/cmd/part.c
index 28f2b7ff9bb..0ce190005d3 100644
--- a/cmd/part.c
+++ b/cmd/part.c
@@ -182,6 +182,36 @@ static int do_part_number(int argc, char *const argv[])
return do_part_info(argc, argv, CMD_PART_INFO_NUMBER);
}
+static int do_part_set(int argc, char *const argv[])
+{
+ const char *devname, *partstr, *typestr;
+ struct blk_desc *desc;
+ int dev;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ /* Look up the device */
+ devname = argv[0];
+ partstr = argv[1];
+ typestr = argv[2];
+ dev = blk_get_device_by_str(devname, partstr, &desc);
+ if (dev < 0) {
+ printf("** Bad device specification %s %s **\n", devname,
+ partstr);
+ return CMD_RET_FAILURE;
+ }
+
+ desc->part_type = part_get_type_by_name(typestr);
+ if (!desc->part_type) {
+ printf("Unknown partition type '%s'\n", typestr);
+ return CMD_RET_FAILURE;
+ }
+ part_print(desc);
+
+ return 0;
+}
+
#ifdef CONFIG_PARTITION_TYPE_GUID
static int do_part_type(int argc, char *const argv[])
{
@@ -245,6 +275,8 @@ static int do_part(struct cmd_tbl *cmdtp, int flag, int
argc,
return do_part_number(argc - 2, argv + 2);
else if (!strcmp(argv[1], "types"))
return do_part_types(argc - 2, argv + 2);
+ else if (!strcmp(argv[1], "set"))
+ return do_part_set(argc - 2, argv + 2);
#ifdef CONFIG_PARTITION_TYPE_GUID
else if (!strcmp(argv[1], "type"))
return do_part_type(argc - 2, argv + 2);
@@ -279,6 +311,8 @@ U_BOOT_CMD(
#endif
"part type : \n"
"- set environment variable to partition type\n"
+ "part set type\n"
+ "- set partition type for a device\n"
"part types\n"
"- list supported partition table types"
);
diff --git a/disk/part.c b/disk/part.c
index 35300df5903..1d2117ab71e 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -54,6 +54,22 @@ static struct part_driver *part_driver_lookup_type(struct
blk_desc *dev_desc)
return NULL;
}
+int part_get_type_by_name(const char *name)
+{
+ struct part_driver *drv =
+ ll_entry_start(struct part_driver, part_driver);
+ const int n_ents = ll_entry_count(struct part_driver, part_driver);
+ struct part_driver *entry;
+
+ for (entry = drv; entry != drv + n_ents; entry++) {
+ if (!strcasecmp(name, entry->name))
+ return entry->part_type;
+ }
+
+ /* Not found */
+ return PART_TYPE_UNKNOWN;
+}
+
static struct blk_desc *get_dev_hwpart(const char *ifname, int dev, int hwpart)
{
struct blk_desc *dev_desc;
diff --git a/doc/usage/cmd/part.rst b/doc/usage/cmd/part.rst
index 8d2a2803912..8a594aaff27 100644
--- a/doc/usage/cmd/part.rst
+++ b/doc/usage/cmd/part.rst
@@ -13,6 +13,7 @@ Synopis
part start
part size
part number
+part set
part type : [varname]
part types
@@ -82,6 +83,18 @@ part must be specified as partition name.
varname
a variable to store the current partition number value into
+The 'part set' command sets the type of a partition. This is useful when
+autodetection fails or does not do the correct thing:
+
+interface
+interface for accessing the block device (mmc, sata, scsi, usb, )
+dev
+device number
+part
+partition number
+type
+partition type to use (see 'part types') to check available types
+
The 'part type' command prints or sets an environment variable to the
partition type UUID.
interface
@@ -147,6 +160,67 @@ Examples
=> part types
Supported partition tables: EFI, AMIGA, DOS, ISO, MAC
+This shows looking at a device with multiple partition tables::
+
+=> virtio scan
+=> part list virtio 0
+
+Partition Map for VirtIO device 0 -- Partition Type: EFI
+
+Part Start LBA End LBA Name
+Attributes
+Type GUID
+Partition GUID
+1 0x0040 0x0092b093 "ISO9660"
+attrs: 0x1001
+type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
+guid: a0891d7e-b930-4513-94d8-f629dbd637b2
+2 0x0092b094 0x0092d7e7 "Appended2"
+attrs: 0x000
[PATCH v3 14/43] log: Tidy up an ambiguous comment.
Add a a bit more detail so it is clear that multiple devices are
supported, but only one per driver.
Signed-off-by: Simon Glass
---
(no changes since v1)
common/log.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/log.c b/common/log.c
index 7cfc49bc28a..ec33b62e8a6 100644
--- a/common/log.c
+++ b/common/log.c
@@ -436,7 +436,7 @@ int log_init(void)
/*
* We cannot add runtime data to the driver since it is likely stored
* in rodata. Instead, set up a 'device' corresponding to each driver.
-* We only support having a single device.
+* We only support having a single device for each driver.
*/
INIT_LIST_HEAD((struct list_head *)&gd->log_head);
while (drv < end) {
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 16/43] qfw: Set the address of the ACPI tables
Once the ACPI tables have been set up, record their address so that it is possible to list them with 'acpi list'. Signed-off-by: Simon Glass --- (no changes since v1) drivers/misc/qfw.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c index 9ef95caa895..0a93feeb4b2 100644 --- a/drivers/misc/qfw.c +++ b/drivers/misc/qfw.c @@ -18,6 +18,7 @@ #include #include #include +#include #if defined(CONFIG_GENERATE_ACPI_TABLE) && !defined(CONFIG_SANDBOX) /* @@ -227,6 +228,9 @@ out: } free(table_loader); + + gd_set_acpi_start(acpi_get_rsdp_addr()); + return addr; } -- 2.40.1.521.gf1e218fcd8-goog
[PATCH v3 13/43] qfw: Show the file address if available
Some files have an associated address. Show this with the 'qfw list'
command so that it is possible to dump the data.
Signed-off-by: Simon Glass
---
(no changes since v1)
cmd/qfw.c | 2 +-
doc/usage/cmd/qfw.rst | 28
2 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/cmd/qfw.c b/cmd/qfw.c
index ae3c6a7a84e..d6ecfa60d5a 100644
--- a/cmd/qfw.c
+++ b/cmd/qfw.c
@@ -26,7 +26,7 @@ static int qemu_fwcfg_cmd_list_firmware(void)
for (file = qfw_file_iter_init(qfw_dev, &iter);
!qfw_file_iter_end(&iter);
file = qfw_file_iter_next(&iter)) {
- printf("%-56s\n", file->cfg.name);
+ printf("%08lx %-56s\n", file->addr, file->cfg.name);
}
return 0;
diff --git a/doc/usage/cmd/qfw.rst b/doc/usage/cmd/qfw.rst
index cc0e27c2779..76d74278a21 100644
--- a/doc/usage/cmd/qfw.rst
+++ b/doc/usage/cmd/qfw.rst
@@ -11,6 +11,7 @@ Synopsis
qfw list
qfw cpus
qfw load [kernel_addr [initrd_addr]]
+qfw list
Description
---
@@ -41,18 +42,21 @@ QEMU firmware files are listed via the *qfw list* command:
::
=> qfw list
-etc/boot-fail-wait
-etc/smbios/smbios-tables
-etc/smbios/smbios-anchor
-etc/e820
-genroms/kvmvapic.bin
-genroms/linuxboot.bin
-etc/system-states
-etc/acpi/tables
-etc/table-loader
-etc/tpm/log
-etc/acpi/rsdp
-bootorder
+ bios-geometry
+ bootorder
+000f0060 etc/acpi/rsdp
+bed14040 etc/acpi/tables
+ etc/boot-fail-wait
+ etc/e820
+ etc/smbios/smbios-anchor
+ etc/smbios/smbios-tables
+ etc/system-states
+ etc/table-loader
+ etc/tpm/log
+ genroms/kvmvapic.bin
+
+Where an address is shown, it indicates where the data is available for
+inspection, e.g. using the :doc:`md`.
The available CPUs can be shown via the *qfw cpus* command:
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 10/43] acpi: Add a comment to set the acpi tables
Sometimes a previous bootloader has written ACPI tables. It is useful to
be able to find and list these. Add an 'acpi set' command to set the
address for these tables.
Signed-off-by: Simon Glass
---
(no changes since v1)
cmd/acpi.c | 24 +---
doc/usage/cmd/acpi.rst | 29 +++--
test/dm/acpi.c | 38 ++
3 files changed, 86 insertions(+), 5 deletions(-)
diff --git a/cmd/acpi.c b/cmd/acpi.c
index e70913e40bf..ede9c8c7dcb 100644
--- a/cmd/acpi.c
+++ b/cmd/acpi.c
@@ -118,6 +118,22 @@ static int do_acpi_list(struct cmd_tbl *cmdtp, int flag,
int argc,
return 0;
}
+static int do_acpi_set(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong val;
+
+ if (argc < 2) {
+ printf("ACPI pointer: %lx\n", gd_acpi_start());
+ } else {
+ val = hextoul(argv[1], NULL);
+ printf("Setting ACPI pointer to %lx\n", val);
+ gd_set_acpi_start(val);
+ }
+
+ return 0;
+}
+
static int do_acpi_items(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -157,12 +173,14 @@ static int do_acpi_dump(struct cmd_tbl *cmdtp, int flag,
int argc,
#ifdef CONFIG_SYS_LONGHELP
static char acpi_help_text[] =
- "list - list ACPI tables\n"
- "acpi items [-d] - List/dump each piece of ACPI data from devices\n"
- "acpi dump - Dump ACPI table";
+ "list - list ACPI tables\n"
+ "acpi items [-d] - List/dump each piece of ACPI data from devices\n"
+ "acpi set [] - Set or show address of ACPI tables\n"
+ "acpi dump - Dump ACPI table";
#endif
U_BOOT_CMD_WITH_SUBCMDS(acpi, "ACPI tables", acpi_help_text,
U_BOOT_SUBCMD_MKENT(list, 1, 1, do_acpi_list),
U_BOOT_SUBCMD_MKENT(items, 2, 1, do_acpi_items),
+ U_BOOT_SUBCMD_MKENT(set, 2, 1, do_acpi_set),
U_BOOT_SUBCMD_MKENT(dump, 2, 1, do_acpi_dump));
diff --git a/doc/usage/cmd/acpi.rst b/doc/usage/cmd/acpi.rst
index 14bafc8e352..5aeb4f4b77b 100644
--- a/doc/usage/cmd/acpi.rst
+++ b/doc/usage/cmd/acpi.rst
@@ -11,12 +11,14 @@ Synopis
acpi list
acpi items [-d]
acpi dump
+acpi set
Description
---
-The *acpi* command is used to dump the ACPI tables generated by U-Boot for
passing
-to the operating systems.
+The *acpi* command is used to dump the ACPI tables generated by U-Boot for
+passing to the operating systems. It allow allows manually setting the address
+to take a look at existing ACPI tables.
ACPI tables can be generated by various output functions and even devices can
output material to include in the Differentiated System Description Table
(DSDT)
@@ -231,5 +233,28 @@ Example
: 44 53 44 54 ea 32 00 00 02 eb 55 2d 42 4f 4f 54 DSDT.2U-BOOT
0010: 55 2d 42 4f 4f 54 42 4c 25 07 11 20 49 4e 54 4c U-BOOTBL%.. INTL
+This shows searching for tables in a known area of memory, then setting the
+pointer::
+
+=> acpi list
+No ACPI tables present
+=> ms.s bff0 8 "RSD PTR"
+bff75000: 52 53 44 20 50 54 52 20 cf 42 4f 43 48 53 20 00 RSD PTR .BOCHS .
+1 match
+=> acpi set bff75000
+Setting ACPI pointer to bff75000
+=> acpi list
+Name Base Size Detail
+ - --
+RSDP bff75000 0 v00 BOCHS
+RSDT bff76a63 38 v01 BOCHS BXPC 1 BXPC 1
+FACP bff768ff 74 v01 BOCHS BXPC 1 BXPC 1
+DSDT bff75080 187f v01 BOCHS BXPC 1 BXPC 1
+FACS bff75040 40
+APIC bff76973 90 v01 BOCHS BXPC 1 BXPC 1
+HPET bff76a03 38 v01 BOCHS BXPC 1 BXPC 1
+WAET bff76a3b 28 v01 BOCHS BXPC 1 BXPC 1
+SSDT bff95040 c5 v02 COREv4 COREBOOT 2a CORE 20221020
+
.. _`ACPI specification`:
https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf
diff --git a/test/dm/acpi.c b/test/dm/acpi.c
index 9634fc2e900..1511336a5eb 100644
--- a/test/dm/acpi.c
+++ b/test/dm/acpi.c
@@ -611,3 +611,41 @@ static int dm_test_acpi_cmd_items(struct unit_test_state
*uts)
return 0;
}
DM_TEST(dm_test_acpi_cmd_items, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+/* Test 'acpi set' command */
+static int dm_test_acpi_cmd_set(struct unit_test_state *uts)
+{
+ struct acpi_ctx ctx;
+ ulong addr;
+ void *buf;
+
+ gd_set_acpi_start(0);
+
+ console_record_reset();
+ ut_asserteq(0, gd_acpi_start());
+ ut_assertok(run_command("acpi set", 0));
+ ut_assert_nextline("ACPI pointer: 0");
+
+ buf = memalign(16, BUF_SIZE);
+ ut_assertnonnull(buf);
+ addr = map_to_sysmem(buf);
+ ut_assertok(setup_ctx_and_base_tables(uts, &ctx, addr));
+
+ ut_assertok(acpi_write_dev_tables(&ctx));
+
+ ut_assertok(run_command("acpi set", 0));
+ ut_assert_nextline("ACPI pointer: %lx", addr);
+
+ ut_ass
[PATCH v3 11/43] bdinfo: Show the RAM top and approximate stack pointer
These are useful pieces of information when debugging. The RAM top shows
where U-Boot started allocating memory from, before it relocated. The
stack pointer can be checked to ensure it is in the correct region.
Signed-off-by: Simon Glass
---
(no changes since v1)
cmd/Kconfig | 8
cmd/bdinfo.c | 5 +
2 files changed, 13 insertions(+)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 56f5ab02239..26ad696c6a6 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -135,6 +135,14 @@ config CMD_BDI
help
Print board info
+config CMD_BDINFO_EXTRA
+ bool "bdinfo extra features"
+ default y if SANDBOX || X86
+ help
+ Show additional information about the board. This uses a little more
+ code space but provides more options, particularly those useful for
+ bringup, development and debugging.
+
config CMD_CONFIG
bool "config"
default SANDBOX
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index f709904c516..4e0c763a709 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -145,6 +145,11 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
printf("devicetree = %s\n", fdtdec_get_srcname());
}
+ if (IS_ENABLED(CONFIG_CMD_BDINFO_EXTRA)) {
+ bdinfo_print_num_ll("stack ptr", (ulong)&bd);
+ bdinfo_print_num_ll("ram_top ptr", (ulong)gd->ram_top);
+ }
+
arch_print_bdinfo();
return 0;
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 09/43] x86: Show an error when a BIOS exception occurs
Rather than silently hanging, show an error first. This can happen when
there is something wrong with the video BIOS.
Signed-off-by: Simon Glass
---
(no changes since v2)
Changes in v2:
- Fix BINS typo
- Drop the Ooops string
arch/x86/lib/bios.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c
index 94349ba8073..8cc686fd146 100644
--- a/arch/x86/lib/bios.c
+++ b/arch/x86/lib/bios.c
@@ -78,7 +78,7 @@ static int int_exception_handler(void)
};
struct eregs *regs = ®_info;
- debug("Oops, exception %d while executing option rom\n", regs->vector);
+ log_err("Exception %d while executing option rom\n", regs->vector);
cpu_hlt();
return 0;
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 07/43] x86: Show the CPU physical address size with bdinfo
This is useful information so show it with the bdinfo command.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/lib/bdinfo.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/lib/bdinfo.c b/arch/x86/lib/bdinfo.c
index 15390070fe8..0970efa4726 100644
--- a/arch/x86/lib/bdinfo.c
+++ b/arch/x86/lib/bdinfo.c
@@ -22,6 +22,7 @@ void arch_print_bdinfo(void)
bdinfo_print_num_l("vendor", gd->arch.x86_vendor);
bdinfo_print_str(" name", cpu_vendor_name(gd->arch.x86_vendor));
bdinfo_print_num_l("model", gd->arch.x86_model);
+ bdinfo_print_num_l("phys_addr", cpu_phys_address_size());
if (IS_ENABLED(CONFIG_EFI_STUB))
efi_show_bdinfo();
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 08/43] x86: Correct get_sp() implementation for 64-bit
Use an assembler implementation as is done for i386, so that the results
are equivalent.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/lib/bootm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index 61cb7bc6116..3196f9ddc2c 100644
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c
@@ -258,7 +258,7 @@ static ulong get_sp(void)
ulong ret;
#if CONFIG_IS_ENABLED(X86_64)
- ret = gd->start_addr_sp;
+ asm("mov %%rsp, %0" : "=r"(ret) : );
#else
asm("mov %%esp, %0" : "=r"(ret) : );
#endif
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 06/43] x86: Add a comment for board_init_f_r_trampoline()
Add a comment for this function in the header. Change the function (and the one after) to use __noreturn to keep checkpatch happy. Add docs to board_init_f_r() while we are here. Signed-off-by: Simon Glass --- (no changes since v2) Changes in v2: - Add docs to board_init_f_r() too arch/x86/include/asm/u-boot-x86.h | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 8f38c2d1c60..1d8aa320f53 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -102,8 +102,20 @@ int video_bios_init(void); */ int fsp_save_s3_stack(void); -void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn)); -void board_init_f_r(void) __attribute__ ((noreturn)); +/** + * board_init_f_r_trampoline() - jump to relocated address with new stack + * + * @sp: New stack pointer to use + */ +void __noreturn board_init_f_r_trampoline(ulong sp); + +/** + * board_init_f_r() - jump to relocated U-Boot + * + * This is used to jump from pre-relocation to post-relocation U-Boot. It + * enables the cache and jump to the new location. + */ +void __noreturn board_init_f_r(void); int arch_misc_init(void); -- 2.40.1.521.gf1e218fcd8-goog
[PATCH v3 05/43] x86: Tidy up EFI code in interrupt_init()
The ll_boot_init() check handles the EFI case so we don't need the rest of the code. Drop it. Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/cpu/i386/interrupt.c | 17 + 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c index fae2544c456..f3f3527237f 100644 --- a/arch/x86/cpu/i386/interrupt.c +++ b/arch/x86/cpu/i386/interrupt.c @@ -266,6 +266,10 @@ int interrupt_init(void) struct udevice *dev; int ret; + /* +* When running as an EFI application we are not in control of +* interrupts and should leave them alone. +*/ if (!ll_boot_init()) return 0; @@ -274,11 +278,6 @@ int interrupt_init(void) if (ret && ret != -ENODEV) return ret; - /* -* When running as an EFI application we are not in control of -* interrupts and should leave them alone. -*/ -#ifndef CONFIG_EFI_APP /* Just in case... */ disable_interrupts(); @@ -294,14 +293,8 @@ int interrupt_init(void) /* Initialize core interrupt and exception functionality of CPU */ cpu_init_interrupts(); - /* -* It is now safe to enable interrupts. -* -* TODO(s...@chromium.org): But we don't handle these correctly when -* booted from EFI. -*/ + /* It is now safe to enable interrupts */ enable_interrupts(); -#endif return 0; } -- 2.40.1.521.gf1e218fcd8-goog
[PATCH v3 04/43] bios_emulator: Drop VIDEO_IO_OFFSET
This is always zero in the source tree, so drop it.
While we are here, add a comment to _X86EMU_env since it the symbol is
actually defined twice, which can cause confusion when building.
Signed-off-by: Simon Glass
---
(no changes since v1)
drivers/bios_emulator/biosemui.h | 18 +-
drivers/bios_emulator/x86emu/sys.c| 1 +
include/configs/conga-qeval20-qa3-e3845.h | 2 --
include/configs/dfi-bt700.h | 2 --
include/configs/minnowmax.h | 2 --
include/configs/som-db5800-som-6867.h | 2 --
include/configs/theadorable-x86-common.h | 2 --
include/configs/x86-chromebook.h | 2 --
8 files changed, 10 insertions(+), 21 deletions(-)
diff --git a/drivers/bios_emulator/biosemui.h b/drivers/bios_emulator/biosemui.h
index 7853015c1e2..954cd883158 100644
--- a/drivers/bios_emulator/biosemui.h
+++ b/drivers/bios_emulator/biosemui.h
@@ -128,19 +128,19 @@ typedef struct {
u32 finalVal;
} BE_portInfo;
-#define PM_inpb(port) inb(port+VIDEO_IO_OFFSET)
-#define PM_inpw(port) inw(port+VIDEO_IO_OFFSET)
-#define PM_inpd(port) inl(port+VIDEO_IO_OFFSET)
-#define PM_outpb(port,val) outb(val,port+VIDEO_IO_OFFSET)
-#define PM_outpw(port,val) outw(val,port+VIDEO_IO_OFFSET)
-#define PM_outpd(port,val) outl(val,port+VIDEO_IO_OFFSET)
+#define PM_inpb(port) inb(port)
+#define PM_inpw(port) inw(port)
+#define PM_inpd(port) inl(port)
+#define PM_outpb(port, val)outb(val, port)
+#define PM_outpw(port, val)outw(val, port)
+#define PM_outpd(port, val)outl(val, port)
#define LOG_inpb(port) PM_inpb(port)
#define LOG_inpw(port) PM_inpw(port)
#define LOG_inpd(port) PM_inpd(port)
-#define LOG_outpb(port,val)PM_outpb(port,val)
-#define LOG_outpw(port,val)PM_outpw(port,val)
-#define LOG_outpd(port,val)PM_outpd(port,val)
+#define LOG_outpb(port, val) PM_outpb(port, val)
+#define LOG_outpw(port, val) PM_outpw(port, val)
+#define LOG_outpd(port, val) PM_outpd(port, val)
/*-- Function Prototypes --*/
diff --git a/drivers/bios_emulator/x86emu/sys.c
b/drivers/bios_emulator/x86emu/sys.c
index c2db1213fe6..882a8a34cc3 100644
--- a/drivers/bios_emulator/x86emu/sys.c
+++ b/drivers/bios_emulator/x86emu/sys.c
@@ -44,6 +44,7 @@
/*- Global Variables --*/
+/* Note: bios.c defines this if the emulator is not enabled */
X86EMU_sysEnv _X86EMU_env; /* Global emulator machine state */
X86EMU_intrFuncs _X86EMU_intrTab[256];
diff --git a/include/configs/conga-qeval20-qa3-e3845.h
b/include/configs/conga-qeval20-qa3-e3845.h
index 60617e6fec2..03c364f29fb 100644
--- a/include/configs/conga-qeval20-qa3-e3845.h
+++ b/include/configs/conga-qeval20-qa3-e3845.h
@@ -16,8 +16,6 @@
"stdout=serial\0" \
"stderr=serial\0"
-#define VIDEO_IO_OFFSET0
-
#undef CFG_EXTRA_ENV_SETTINGS
#define CFG_EXTRA_ENV_SETTINGS \
"kernel-ver=4.4.0-22\0" \
diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h
index 05389a435be..be095e28a1b 100644
--- a/include/configs/dfi-bt700.h
+++ b/include/configs/dfi-bt700.h
@@ -20,8 +20,6 @@
"stdout=serial\0" \
"stderr=serial\0"
-#define VIDEO_IO_OFFSET0
-
#undef CFG_EXTRA_ENV_SETTINGS
#define CFG_EXTRA_ENV_SETTINGS \
"kernel-ver=4.4.0-24\0" \
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 4a12c2f72c6..842672d5575 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -17,6 +17,4 @@
"stderr=vidconsole,serial\0" \
"usb_pgood_delay=40\0"
-#define VIDEO_IO_OFFSET0
-
#endif /* __CONFIG_H */
diff --git a/include/configs/som-db5800-som-6867.h
b/include/configs/som-db5800-som-6867.h
index b2e7aa1514c..5f7eabd3fc6 100644
--- a/include/configs/som-db5800-som-6867.h
+++ b/include/configs/som-db5800-som-6867.h
@@ -16,6 +16,4 @@
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
-#define VIDEO_IO_OFFSET0
-
#endif /* __CONFIG_H */
diff --git a/include/configs/theadorable-x86-common.h
b/include/configs/theadorable-x86-common.h
index b23b8783076..46aef238213 100644
--- a/include/configs/theadorable-x86-common.h
+++ b/include/configs/theadorable-x86-common.h
@@ -15,8 +15,6 @@
"stdout=serial\0" \
"stderr=serial\0"
-#define VIDEO_IO_OFFSET0
-
/*
[PATCH v3 03/43] bios_emulator: Add Kconfig and adjust Makefile for SPL
The Kconfig for this is currently inside a particular board. Move it into the correct place and allow use in SPL, so that video can be used there if needed. Signed-off-by: Simon Glass --- (no changes since v1) board/google/Kconfig | 7 --- drivers/Kconfig | 2 ++ drivers/Makefile | 2 +- drivers/bios_emulator/Kconfig | 10 ++ 4 files changed, 13 insertions(+), 8 deletions(-) create mode 100644 drivers/bios_emulator/Kconfig diff --git a/board/google/Kconfig b/board/google/Kconfig index a0f1a609764..e4f9b5b68aa 100644 --- a/board/google/Kconfig +++ b/board/google/Kconfig @@ -4,13 +4,6 @@ if VENDOR_GOOGLE -config BIOSEMU - bool - select X86EMU_RAW_IO - -config X86EMU_RAW_IO - bool - choice prompt "Mainboard model" optional diff --git a/drivers/Kconfig b/drivers/Kconfig index 75937fbb6d9..a25f6ae02fd 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -10,6 +10,8 @@ source "drivers/ata/Kconfig" source "drivers/axi/Kconfig" +source "drivers/bios_emulator/Kconfig" + source "drivers/bus/Kconfig" source "drivers/block/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 29be78a3f28..c70466dbcbe 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ +obj-$(CONFIG_$(SPL_TPL_)BIOSEMU) += bios_emulator/ obj-$(CONFIG_$(SPL_TPL_)BLK) += block/ obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/ obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/ @@ -79,7 +80,6 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) obj-y += adc/ obj-y += ata/ obj-$(CONFIG_DM_DEMO) += demo/ -obj-$(CONFIG_BIOSEMU) += bios_emulator/ obj-y += block/ obj-y += cache/ obj-$(CONFIG_CPU) += cpu/ diff --git a/drivers/bios_emulator/Kconfig b/drivers/bios_emulator/Kconfig new file mode 100644 index 000..3660576772d --- /dev/null +++ b/drivers/bios_emulator/Kconfig @@ -0,0 +1,10 @@ +config BIOSEMU + bool + select X86EMU_RAW_IO + +config SPL_BIOSEMU + bool + select X86EMU_RAW_IO + +config X86EMU_RAW_IO + bool -- 2.40.1.521.gf1e218fcd8-goog
[PATCH v3 02/43] x86: mtrr: Add documentation
Add documention for the x86 'mtrr' command. Signed-off-by: Simon Glass Suggested-by: Heinrich Schuchardt --- (no changes since v2) Changes in v2: - Add new patch with docs for mtrr command doc/usage/cmd/mtrr.rst | 151 + doc/usage/index.rst| 1 + 2 files changed, 152 insertions(+) create mode 100644 doc/usage/cmd/mtrr.rst diff --git a/doc/usage/cmd/mtrr.rst b/doc/usage/cmd/mtrr.rst new file mode 100644 index 000..1b79424112d --- /dev/null +++ b/doc/usage/cmd/mtrr.rst @@ -0,0 +1,151 @@ +.. SPDX-License-Identifier: GPL-2.0+: + +mtrr command + + +Synopis +--- + +mtrr [list] +mtrr set +mtrr disable +mtrr enable + + +Description +--- + +The *mtrr* command is used to dump the Memory Type Range Registers (MTRRs) on +an x86 machine. These register control cache behaviour in selected memory +ranges. + +Note that the number of registers can vary between CPUs. + + +mtrr [list] +~~~ + +List the MTRRs. The table shows the following information: + +Reg +Register number (the first is register 0) + +Valid +Shows Y if the register is valid (has bit 11 set), N if not + +Write-type +Shows the behaviour when writing to the memory region. The types are +abrievated to fit a reasonable line length. Valid types shown below. + +== == +Value TypeMeaning +== == +0 Uncacheable Skip cache and write directly to memory +1 Combine Multiple writes can be combined into one transaction +4 Through Update cache and also write to memory +5 Protect Writes are prohibited +6 BackUpdate cache but don't write to memory +== == + +Base +Base memory address from which the register controls behaviour + +Mask +Mask value, which also indicates the size + +Size +Length of memory region within which the register controls behaviour + + +mtrr set + + +This sets the value of a particular MTRR. Parameters are: + +reg +Register number to set, with 0 being the first + +type +Access type to set. See Write-type above for valid types. This uses the name +rather than its numeric value. + +start +Base memory address from which the register should control behaviour + +size +Length of memory region within which the register controls behaviour + + +mtrr disable + + +This disables a particular register, by clearing its `valid` bit (11). + + +mtrr enable +~~~ + +This enables a particular register, by setting its `valid` bit (11). + + +Example +--- + +This shows disabling and enabling an MTRR, as well as setting its type:: + +=> mtrr +CPU 0: +Reg Valid Write-type Base ||Mask ||Size || +0 Y Back 000f8000 8000 +1 Y Back 8000 000fe000 2000 +2 Y Back a000 000ff000 1000 +3 Y Uncacheable ad00 000fff00 0100 +4 Y Uncacheable ae00 000ffe00 0200 +5 Y Combine d000 000ff000 1000 +6 N Uncacheable 0010 +7 N Uncacheable 0010 +8 N Uncacheable 0010 +9 N Uncacheable 0010 +=> mtrr d 5 +=> mtrr +CPU 0: +Reg Valid Write-type Base ||Mask ||Size || +0 Y Back 000f8000 8000 +1 Y Back 8000 000fe000 2000 +2 Y Back a000 000ff000 1000 +3 Y Uncacheable ad00 000fff00 0100 +4 Y Uncacheable ae00 000ffe00 0200 +5 N Combine d000 000ff000 1000 +6 N Uncacheable 0010 +7 N Uncacheable 0010 +8 N Uncacheable 0010 +9 N Uncacheable 0010 +=> mtrr e 5 +=> mtrr +CPU 0: +Reg Valid Write-type Base ||Mask ||Size || +0 Y Back 000f8000 8000 +1 Y Back 8000 000fe000 2000 +
[PATCH v3 01/43] x86: Allow listing MTRRs in SPL
Move MTRR-listing code into a common file so it can be used from SPL.
Update the 'mtrr' command to call it.
Use this in SPL just before adjusting the MTRRs, so we can see the state
set up by the board. Only show it when debug is enabled.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/cpu/mtrr.c | 61 +
arch/x86/include/asm/mtrr.h | 20
arch/x86/lib/spl.c | 7 +
cmd/x86/mtrr.c | 60 +++-
4 files changed, 92 insertions(+), 56 deletions(-)
diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c
index c174dd9b3ad..40d24e6fb9b 100644
--- a/arch/x86/cpu/mtrr.c
+++ b/arch/x86/cpu/mtrr.c
@@ -30,6 +30,16 @@
DECLARE_GLOBAL_DATA_PTR;
+const char *const mtrr_type_name[MTRR_TYPE_COUNT] = {
+ "Uncacheable",
+ "Combine",
+ "2",
+ "3",
+ "Through",
+ "Protect",
+ "Back",
+};
+
/* Prepare to adjust MTRRs */
void mtrr_open(struct mtrr_state *state, bool do_caches)
{
@@ -324,3 +334,54 @@ int mtrr_set(int cpu_select, int reg, u64 base, u64 mask)
return mtrr_start_op(cpu_select, &oper);
}
+
+static void read_mtrrs_(void *arg)
+{
+ struct mtrr_info *info = arg;
+
+ mtrr_read_all(info);
+}
+
+int mtrr_list(int reg_count, int cpu_select)
+{
+ struct mtrr_info info;
+ int ret;
+ int i;
+
+ printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||",
+ "Mask ||", "Size ||");
+ memset(&info, '\0', sizeof(info));
+ ret = mp_run_on_cpus(cpu_select, read_mtrrs_, &info);
+ if (ret)
+ return log_msg_ret("run", ret);
+ for (i = 0; i < reg_count; i++) {
+ const char *type = "Invalid";
+ u64 base, mask, size;
+ bool valid;
+
+ base = info.mtrr[i].base;
+ mask = info.mtrr[i].mask;
+ size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1);
+ size |= (1 << 12) - 1;
+ size += 1;
+ valid = mask & MTRR_PHYS_MASK_VALID;
+ type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK];
+ printf("%d %-5s %-12s %016llx %016llx %016llx\n", i,
+ valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK,
+ mask & ~MTRR_PHYS_MASK_VALID, size);
+ }
+
+ return 0;
+}
+
+int mtrr_get_type_by_name(const char *typename)
+{
+ int i;
+
+ for (i = 0; i < MTRR_TYPE_COUNT; i++) {
+ if (*typename == *mtrr_type_name[i])
+ return i;
+ }
+
+ return -EINVAL;
+};
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
index ca2edc7878f..2e995f54061 100644
--- a/arch/x86/include/asm/mtrr.h
+++ b/arch/x86/include/asm/mtrr.h
@@ -190,6 +190,26 @@ int mtrr_set(int cpu_select, int reg, u64 base, u64 mask);
*/
int mtrr_get_var_count(void);
+/**
+ * mtrr_list() - List the MTRRs
+ *
+ * Shows a list of all the MTRRs including their values
+ *
+ * @reg_count: Number of registers to show. You can use mtrr_get_var_count()
for
+ * this
+ * @cpu_select: CPU to use. Use MP_SELECT_BSP for the boot CPU
+ * Returns: 0 if OK, -ve if the CPU was not found
+ */
+int mtrr_list(int reg_count, int cpu_select);
+
+/**
+ * mtrr_get_type_by_name() - Get the type of an MTRR given its type name
+ *
+ * @typename: Name to check
+ * Returns: MTRR type (MTRR_TYPE_...) or -EINVAL if invalid
+ */
+int mtrr_get_type_by_name(const char *typename);
+
#endif
#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index ca1645f9d68..b9d23e6bfe1 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -139,6 +140,12 @@ static int x86_spl_init(void)
arch_setup_gd(gd->new_gd);
gd->start_addr_sp = (ulong)ptr;
+ if (_LOG_DEBUG) {
+ ret = mtrr_list(mtrr_get_var_count(), MP_SELECT_BSP);
+ if (ret)
+ printf("mtrr_list failed\n");
+ }
+
/* Cache the SPI flash. Otherwise copying the code to RAM takes ages */
ret = mtrr_add_request(MTRR_TYPE_WRBACK,
(1ULL << 32) - CONFIG_XIP_ROM_SIZE,
diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c
index b1691d8b65a..6ad7a123a44 100644
--- a/cmd/x86/mtrr.c
+++ b/cmd/x86/mtrr.c
@@ -10,71 +10,19 @@
#include
#include
-static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = {
- "Uncacheable",
- "Combine",
- "2",
- "3",
- "Through",
- "Protect",
- "Back",
-};
-
-static void read_mtrrs(void *arg)
-{
- struct mtrr_info *info = arg;
-
- mtrr_read_all(info);
-}
-
-static int do_mtrr_list(int reg_count, int cpu_select)
-{
- struct mtrr_info info;
- int ret;
- int i;
-
- printf("Re
[PATCH v3 00/43] x86: Use qemu-x86_64 to boot EFI installers
This series adds various minor features so that qemu-x86_64 can boot the Ubuntu 2022.04 installer using a virtio device: qemu-system-x86_64 -M pc -drive format=raw,file=root.img -bios /tmp/b/qemu-x86_64/u-boot.rom -drive if=virtio,file=ubuntu-22.04.2-desktop-amd64.iso -smp 4 -m 4G -serial mon:stdio The main changes include: - Enable video in SPL while running in 32-bit mode - Drop the duplicate ACPI tables with EFI - Support PCI autoconfig in SPL - Support FAT on a CDROM filesystem - Improved bootstd rules around device tree and efi_set_bootdev() There are also quite a number of minor tweaks and fixes to make things easier to use. This series is based on an older version of the SPL-video series from Nikhil M Jain. It is available at u-boot-dm/bryc-working Changes in v3: - Add a tag name for the blob - Add new patch to refactor table-writing code a ltitle - Adjust the code to handle qemu writing a pointer to tables in memory Changes in v2: - Add new patch with docs for mtrr command - Add docs to board_init_f_r() too - Fix BINS typo - Drop the Ooops string - Drop ** in strings and use log_err() for messages - Use log_warning() for the warning - Handle the case where the tables are in the bloblist - Add new patch to show the number of physical address bits - Add new patch to convert some debug statements to use logging - Add new patch to support Micron memory - Add new patch to make sure that the LPC is active before SDRAM init - Add new patch to support outputing function names in SPL - Drop patch to set high bits of the mtrr base register, for now Simon Glass (43): x86: Allow listing MTRRs in SPL x86: mtrr: Add documentation bios_emulator: Add Kconfig and adjust Makefile for SPL bios_emulator: Drop VIDEO_IO_OFFSET x86: Tidy up EFI code in interrupt_init() x86: Add a comment for board_init_f_r_trampoline() x86: Show the CPU physical address size with bdinfo x86: Correct get_sp() implementation for 64-bit x86: Show an error when a BIOS exception occurs acpi: Add a comment to set the acpi tables bdinfo: Show the RAM top and approximate stack pointer part: Allow setting the partition-table type qfw: Show the file address if available log: Tidy up an ambiguous comment. video: Allow building video drivers for SPL qfw: Set the address of the ACPI tables efi: Show all known UUIDs with CONFIG_CMD_EFIDEBUG x86: Improve the trampoline in 64-bit mode Show the malloc base with the bdinfo command nvme: Provide more useful debugging messages pci: Support autoconfig in SPL pci: Allow the video BIOS to work in SPL with QEMU pci: Tidy up logging and reporting for video BIOS x86: Allow video-BIOS code to be built for SPL x86: Pass video settings from SPL to U-Boot proper x86: Init video in SPL if enabled pci: Adjust video BIOS debugging to be SPL-friendly pci: Mask the ROM address in case it is already enabled x86: Enable display for QEMU 64-bit x86: Allow logging to be used in SPL reliably fs: fat: Shrink the size of a few strings fs: fat: Support reading from a larger block size x86: Enable useful options for qemu-86_64 x86: Refactor table-writing code a litlle x86: Record the start and end of the tables x86: Show the number of physical address bits x86: Convert some debug statements to use logging x86: link: Support Micron memory x86: Make sure that the LPC is active before SDRAM init log: Support outputing function names in SPL sandbox: Correct header order in board file sandbox: Install ACPI tables on startup efi: Use the installed ACPI tables arch/sandbox/include/asm/global_data.h| 4 + arch/x86/cpu/i386/cpu.c | 2 + arch/x86/cpu/i386/interrupt.c | 17 +-- arch/x86/cpu/intel_common/mrc.c | 10 +- arch/x86/cpu/ivybridge/sdram.c| 4 +- arch/x86/cpu/mtrr.c | 61 arch/x86/cpu/start64.S| 19 +++ arch/x86/dts/chromebook_link.dts | 1 + arch/x86/include/asm/global_data.h| 5 + arch/x86/include/asm/mtrr.h | 20 +++ arch/x86/include/asm/u-boot-x86.h | 27 +++- arch/x86/lib/Makefile | 7 +- arch/x86/lib/bdinfo.c | 6 + arch/x86/lib/bios.c | 4 +- arch/x86/lib/bootm.c | 2 +- arch/x86/lib/mrccache.c | 6 +- arch/x86/lib/spl.c| 63 +++-- arch/x86/lib/tables.c | 42 -- board/google/Kconfig | 7 - board/sandbox/sandbox.c | 22 ++- cmd/Kconfig | 8 ++ cmd/acpi.c| 24 +++- cmd/bdinfo.c | 6 + cmd/part.c| 34 + cmd/qfw.c | 2 +- cmd/x86/mtrr.c| 60 +--- comm
[PATCH v4 16/16] coreboot: Enable ms command
This is useful when looking for tables in memory. Enable it for coreboot. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v2) Changes in v2: - Add new patch to enable ms command configs/coreboot_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index f6ffb518042..058caf008f9 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -24,6 +24,7 @@ CONFIG_LAST_STAGE_INIT=y CONFIG_PCI_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PBSIZE=532 +CONFIG_CMD_MEM_SEARCH=y CONFIG_CMD_IDE=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -- 2.40.1.521.gf1e218fcd8-goog
[PATCH v4 14/16] nvme: Enable PCI bus mastering
U-Boot sets up devices ready for use, but coreboot does not. Enable this so that NVMe works OK from coreboot. Signed-off-by: Simon Glass --- Changes in v4: - Split out patch to enable bus mastering drivers/nvme/nvme_pci.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/nvme/nvme_pci.c b/drivers/nvme/nvme_pci.c index 36bf9c5ffb7..5bb43d299fc 100644 --- a/drivers/nvme/nvme_pci.c +++ b/drivers/nvme/nvme_pci.c @@ -6,6 +6,7 @@ #include #include +#include #include #include "nvme.h" @@ -30,6 +31,10 @@ static int nvme_probe(struct udevice *udev) ndev->instance = trailing_strtol(udev->name); ndev->bar = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM); + + /* Turn on bus-mastering */ + dm_pci_clrset_config16(udev, PCI_COMMAND, 0, PCI_COMMAND_MASTER); + return nvme_init(udev); } -- 2.40.1.521.gf1e218fcd8-goog
[PATCH v4 15/16] x86: nvme: coreboot: Enable NVMe
Enable support for NVMe storage devices. Update the driver to enable the bus master bit, since coreboot does not do that automatically. Signed-off-by: Simon Glass --- Changes in v4: - Drop unnecessary CONFIG options - Drop patch to allow locating UARTs by device ID Changes in v2: - Drop patch 'usb: Quieten a debug message' since it was fixed elsewhere - Drop patch 'x86: coreboot: Use a memory-mapped UART' (not needed) configs/coreboot_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index 3030e5bf93b..f6ffb518042 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -59,6 +59,7 @@ CONFIG_SYS_ATA_ALT_OFFSET=0 CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y +CONFIG_NVME_PCI=y # CONFIG_PCI_PNP is not set CONFIG_SOUND=y CONFIG_SOUND_I8254=y -- 2.40.1.521.gf1e218fcd8-goog
[PATCH v4 13/16] x86: coreboot: Show unimplemented sysinfo tags
Sometimes coreboot adds new tags that U-Boot does not know about. These
are silently ignored, but it is useful to at least know what we are
missing.
Add a way to collect this information. For Brya it shows:
Unimpl. 38 41 37 34 42 40
These are:
LB_TAG_PLATFORM_BLOB_VERSION
LB_TAG_ACPI_CNVS
LB_TAG_FMAP
LB_TAG_VBOOT_WORKBUF
LB_TAG_TYPE_C_INFO
LB_TAG_BOARD_CONFIG
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
(no changes since v1)
arch/x86/include/asm/cb_sysinfo.h | 6 ++
arch/x86/lib/coreboot/cb_sysinfo.c | 2 ++
cmd/x86/cbsysinfo.c| 8
3 files changed, 16 insertions(+)
diff --git a/arch/x86/include/asm/cb_sysinfo.h
b/arch/x86/include/asm/cb_sysinfo.h
index 6b266149cf6..2c78b22d0d2 100644
--- a/arch/x86/include/asm/cb_sysinfo.h
+++ b/arch/x86/include/asm/cb_sysinfo.h
@@ -16,6 +16,8 @@
#define SYSINFO_MAX_GPIOS 8
/* Up to 10 MAC addresses */
#define SYSINFO_MAX_MACS 10
+/* Track the first 32 unimplemented tags */
+#define SYSINFO_MAX_UNIMPL 32
/**
* struct sysinfo_t - Information passed to U-Boot from coreboot
@@ -134,6 +136,8 @@
* @chromeos_vpd: Chromium OS Vital Product Data region, typically NULL,
meaning
* not used
* @rsdp: Pointer to ACPI RSDP table
+ * @unimpl_count: Number of entries in unimpl_map[]
+ * @unimpl: List of unimplemented IDs (bottom 8 bits only)
*/
struct sysinfo_t {
unsigned int cpu_khz;
@@ -213,6 +217,8 @@ struct sysinfo_t {
u32 mtc_size;
void*chromeos_vpd;
void *rsdp;
+ u32 unimpl_count;
+ u8 unimpl[SYSINFO_MAX_UNIMPL];
};
extern struct sysinfo_t lib_sysinfo;
diff --git a/arch/x86/lib/coreboot/cb_sysinfo.c
b/arch/x86/lib/coreboot/cb_sysinfo.c
index a11a2587f66..42cc3a128d9 100644
--- a/arch/x86/lib/coreboot/cb_sysinfo.c
+++ b/arch/x86/lib/coreboot/cb_sysinfo.c
@@ -439,6 +439,8 @@ static int cb_parse_header(void *addr, int len, struct
sysinfo_t *info)
cb_parse_acpi_rsdp(rec, info);
break;
default:
+ if (info->unimpl_count < SYSINFO_MAX_UNIMPL)
+ info->unimpl[info->unimpl_count++] = rec->tag;
cb_parse_unhandled(rec->tag, ptr);
break;
}
diff --git a/cmd/x86/cbsysinfo.c b/cmd/x86/cbsysinfo.c
index 07570b00c9a..2b8d3b0a435 100644
--- a/cmd/x86/cbsysinfo.c
+++ b/cmd/x86/cbsysinfo.c
@@ -364,6 +364,14 @@ static void show_table(struct sysinfo_t *info, bool
verbose)
print_ptr("Chrome OS VPD", info->chromeos_vpd);
print_ptr("RSDP", info->rsdp);
+ printf("%-12s: ", "Unimpl.");
+ if (info->unimpl_count) {
+ for (i = 0; i < info->unimpl_count; i++)
+ printf("%02x ", info->unimpl[i]);
+ printf("\n");
+ } else {
+ printf("(none)\n");
+ }
}
static int do_cbsysinfo(struct cmd_tbl *cmdtp, int flag, int argc,
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v4 12/16] x86: coreboot: Log function names and line numbers
Turn these options on to make it easier to debug things. Also enable dhrystone so we can get some measure of performance. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) configs/coreboot_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index 1bbb358a022..3030e5bf93b 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -16,6 +16,9 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="ext2load scsi 0:3 0100 /boot/vmlinuz; zboot 0100" CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_LOG=y +CONFIG_LOGF_LINE=y +CONFIG_LOGF_FUNC=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_PCI_INIT_R=y @@ -60,5 +63,6 @@ CONFIG_SYS_64BIT_LBA=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_CONSOLE_SCROLL_LINES=5 +CONFIG_CMD_DHRYSTONE=y # CONFIG_GZIP is not set CONFIG_SMBIOS_PARSER=y -- 2.40.1.521.gf1e218fcd8-goog
[PATCH v4 11/16] x86: coreboot: Scan PCI after relocation
Enable this so that PCI devices can be used correctly without needing to do a manual scan. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) configs/coreboot_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index fb4d1751108..1bbb358a022 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -18,6 +18,7 @@ CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y +CONFIG_PCI_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IDE=y -- 2.40.1.521.gf1e218fcd8-goog
[PATCH v4 10/16] x86: coreboot: Document how to enable the debug UART
This is not obvious so add a little note about how it works. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) doc/board/coreboot/coreboot.rst | 29 + 1 file changed, 29 insertions(+) diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst index 4a5f101cad2..0fe95af56d2 100644 --- a/doc/board/coreboot/coreboot.rst +++ b/doc/board/coreboot/coreboot.rst @@ -71,3 +71,32 @@ Memory map (typically redirects to 7ab10030 or similar) 500 Location of coreboot sysinfo table, used during startup == == + + +Debug UART +-- + +It is possible to enable the debug UART with coreboot. To do this, use the +info from the cbsysinfo command to locate the UART base. For example:: + + => cbsysinfo + ... + Serial I/O port: + base: + pointer : 767b51bc + type: 2 + base: fe03e000 + baud: 0d115200 + regwidth: 4 + input_hz: 0d1843200 + PCI addr: 0010 + ... + +Here you can see that the UART base is fe03e000, regwidth is 4 (1 << 2) and the +input clock is 1843200. So you can add the following CONFIG options:: + + CONFIG_DEBUG_UART=y + CONFIG_DEBUG_UART_BASE=fe03e000 + CONFIG_DEBUG_UART_CLOCK=1843200 + CONFIG_DEBUG_UART_SHIFT=2 + CONFIG_DEBUG_UART_ANNOUNCE=y -- 2.40.1.521.gf1e218fcd8-goog
[PATCH v4 09/16] x86: coreboot: Use a memory-mapped UART
This is much more common on modern hardware, so default to using it. This does not affect the normal UART, but does allow the debug UART to work, since it uses serial_out_shift(), etc. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v2) Changes in v2: - Expand commit message to explain this is for the debug UART - Update the defconfig instead configs/coreboot64_defconfig | 1 - configs/coreboot_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index ec672e59e89..60a1924e9e5 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -62,7 +62,6 @@ CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set -CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index 4db72899169..fb4d1751108 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -56,7 +56,6 @@ CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set -CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_CONSOLE_SCROLL_LINES=5 -- 2.40.1.521.gf1e218fcd8-goog
[PATCH v4 08/16] pci: coreboot: Don't read regions when booting
When U-Boot is the second-stage bootloader, PCI is already set up. We
cannot read the regions from the device tree. There is no point anyway,
since PCI devices have already been allocated according to the regions
and it is not safe for U-Boot to make any changes.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Fixes: f2ebaaa9f38d ("pci: Handle failed calloc in decode_regions()")
Tested-by: Christian Gmeiner
---
(no changes since v1)
drivers/pci/pci-uclass.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 9343cfc62a9..8d27e40338c 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -973,6 +973,10 @@ static int decode_regions(struct pci_controller *hose,
ofnode parent_node,
int len;
int i;
+ /* handle booting from coreboot, etc. */
+ if (!ll_boot_init())
+ return 0;
+
prop = ofnode_get_property(node, "ranges", &len);
if (!prop) {
debug("%s: Cannot decode regions\n", __func__);
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v4 07/16] x86: Allow locating the UART from ACPI tables
When coreboot does not pass a UART in its sysinfo struct, there is no
easy way to find it out.
Since coreboot does not actually init the serial device when serial is
disabled, it is not possible to make it add this information to the
sysinfo table.
Add a way to obtain this information from the DBG2 ACPI table, which is
normally set up by coreboot.
For now this only supports a memory-mapped 16550-style UART.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
(no changes since v3)
Changes in v3:
- Disable for coreboot64 since ACPI is not available
Changes in v2:
- Add new patch to allow locating the UART from ACPI tables
drivers/serial/Kconfig | 10 +++
drivers/serial/serial_coreboot.c | 114 ---
2 files changed, 116 insertions(+), 8 deletions(-)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 7faf6784442..f4767c838f9 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -669,6 +669,16 @@ config COREBOOT_SERIAL
a serial console on any platform without needing to change the
device tree, etc.
+config COREBOOT_SERIAL_FROM_DBG2
+ bool "Obtain UART from ACPI tables"
+ depends on COREBOOT_SERIAL
+ default y if !SPL
+ help
+ Select this to try to find a DBG2 record in the ACPI tables, in the
+ event that coreboot does not provide information about the UART in the
+ normal sysinfo tables. This provides a useful fallback when serial
+ is not enabled in coreboot.
+
config CORTINA_UART
bool "Cortina UART support"
depends on DM_SERIAL
diff --git a/drivers/serial/serial_coreboot.c b/drivers/serial/serial_coreboot.c
index de09c8681f5..23066e4d054 100644
--- a/drivers/serial/serial_coreboot.c
+++ b/drivers/serial/serial_coreboot.c
@@ -5,25 +5,123 @@
* Copyright 2019 Google LLC
*/
+#define LOG_CATGEGORY UCLASS_SERIAL
+
#include
#include
+#include
#include
#include
+#include
#include
+DECLARE_GLOBAL_DATA_PTR;
+
+static int read_dbg2(struct ns16550_plat *plat)
+{
+ struct acpi_table_header *tab;
+ struct acpi_dbg2_header *hdr;
+ struct acpi_dbg2_device *dbg;
+ struct acpi_gen_regaddr *addr;
+ u32 *addr_size;
+
+ log_debug("Looking for DBG2 in ACPI tables\n");
+ if (!gd->acpi_start) {
+ log_debug("No ACPI tables\n");
+ return -ENOENT;
+ }
+
+ tab = acpi_find_table("DBG2");
+ if (!tab) {
+ log_debug("No DBG2 table\n");
+ return -ENOENT;
+ }
+ hdr = container_of(tab, struct acpi_dbg2_header, header);
+
+ /* We only use the first device, but check that there is at least one */
+ if (!hdr->devices_count) {
+ log_debug("No devices\n");
+ return -ENOENT;
+ }
+ if (hdr->devices_offset >= tab->length) {
+ log_debug("Invalid offset\n");
+ return -EINVAL;
+ }
+ dbg = (void *)hdr + hdr->devices_offset;
+ if (dbg->revision) {
+ log_debug("Invalid revision %d\n", dbg->revision);
+ return -EINVAL;
+ }
+ if (!dbg->address_count) {
+ log_debug("No addresses\n");
+ return -EINVAL;
+ }
+ if (dbg->port_type != ACPI_DBG2_SERIAL_PORT) {
+ log_debug("Not a serial port\n");
+ return -EPROTOTYPE;
+ }
+ if (dbg->port_subtype != ACPI_DBG2_16550_COMPATIBLE) {
+ log_debug("Incompatible serial port\n");
+ return -EPROTOTYPE;
+ }
+ if (dbg->base_address_offset >= dbg->length ||
+ dbg->address_size_offset >= dbg->length) {
+ log_debug("Invalid base address/size offsets %d, %d\n",
+ dbg->base_address_offset, dbg->address_size_offset);
+ return -EINVAL;
+ }
+ addr_size = (void *)dbg + dbg->address_size_offset;
+ if (!*addr_size) {
+ log_debug("Zero address size\n");
+ return -EINVAL;
+ }
+ addr = (void *)dbg + dbg->base_address_offset;
+ if (addr->space_id != ACPI_ADDRESS_SPACE_MEMORY) {
+ log_debug("Incompatible space %d\n", addr->space_id);
+ return -EPROTOTYPE;
+ }
+
+ plat->base = addr->addrl;
+
+ /* ACPI_ACCESS_SIZE_DWORD_ACCESS is 3; we want 2 */
+ plat->reg_shift = addr->access_size - 1;
+ plat->reg_width = 4; /* coreboot sets bit_width to 0 */
+ plat->clock = 1843200;
+ plat->fcr = UART_FCR_DEFVAL;
+ plat->flags = 0;
+ log_debug("Collected UART from ACPI DBG2 table\n");
+
+ return 0;
+}
+
static int coreboot_of_to_plat(struct udevice *dev)
{
struct ns16550_plat *plat = dev_get_plat(dev);
struct cb_serial *cb_info = lib_sysinfo.serial;
+ int ret = -ENOENT;
- plat->base = cb_info->baseaddr;
- plat->reg_shift = cb_info->regwidth =
[PATCH v4 05/16] acpi: Move the table-finding functions into the libary
This is useful for other features. Move the function into library code
so it can be used outside just the 'acpi' command.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
(no changes since v3)
Changes in v3:
- Avoid a build error with the ASL compiler
Changes in v2:
- Add new patch to move acpi-table-finding functions into the library
cmd/acpi.c| 40 +-
include/acpi/acpi_table.h | 8 +++
lib/acpi/Makefile | 2 ++
lib/acpi/acpi.c | 45 +++
4 files changed, 56 insertions(+), 39 deletions(-)
create mode 100644 lib/acpi/acpi.c
diff --git a/cmd/acpi.c b/cmd/acpi.c
index 991b5235e28..e70913e40bf 100644
--- a/cmd/acpi.c
+++ b/cmd/acpi.c
@@ -36,49 +36,11 @@ static void dump_hdr(struct acpi_table_header *hdr)
}
}
-/**
- * find_table() - Look up an ACPI table
- *
- * @sig: Signature of table (4 characters, upper case)
- * Return: pointer to table header, or NULL if not found
- */
-struct acpi_table_header *find_table(const char *sig)
-{
- struct acpi_rsdp *rsdp;
- struct acpi_rsdt *rsdt;
- int len, i, count;
-
- rsdp = map_sysmem(gd_acpi_start(), 0);
- if (!rsdp)
- return NULL;
- rsdt = map_sysmem(rsdp->rsdt_address, 0);
- len = rsdt->header.length - sizeof(rsdt->header);
- count = len / sizeof(u32);
- for (i = 0; i < count; i++) {
- struct acpi_table_header *hdr;
-
- hdr = map_sysmem(rsdt->entry[i], 0);
- if (!memcmp(hdr->signature, sig, ACPI_NAME_LEN))
- return hdr;
- if (!memcmp(hdr->signature, "FACP", ACPI_NAME_LEN)) {
- struct acpi_fadt *fadt = (struct acpi_fadt *)hdr;
-
- if (!memcmp(sig, "DSDT", ACPI_NAME_LEN) && fadt->dsdt)
- return map_sysmem(fadt->dsdt, 0);
- if (!memcmp(sig, "FACS", ACPI_NAME_LEN) &&
- fadt->firmware_ctrl)
- return map_sysmem(fadt->firmware_ctrl, 0);
- }
- }
-
- return NULL;
-}
-
static int dump_table_name(const char *sig)
{
struct acpi_table_header *hdr;
- hdr = find_table(sig);
+ hdr = acpi_find_table(sig);
if (!hdr)
return -ENOENT;
printf("%.*s @ %08lx\n", ACPI_NAME_LEN, hdr->signature,
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index 4030d25c66a..7ed0443c821 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -923,6 +923,14 @@ int acpi_fill_csrt(struct acpi_ctx *ctx);
*/
ulong write_acpi_tables(ulong start);
+/**
+ * acpi_find_table() - Look up an ACPI table
+ *
+ * @sig: Signature of table (4 characters, upper case)
+ * Return: pointer to table header, or NULL if not found
+ */
+struct acpi_table_header *acpi_find_table(const char *sig);
+
#endif /* !__ACPI__*/
#include
diff --git a/lib/acpi/Makefile b/lib/acpi/Makefile
index 12337abaecf..c1c9675b5d2 100644
--- a/lib/acpi/Makefile
+++ b/lib/acpi/Makefile
@@ -1,6 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-y += acpi.o
+
ifdef CONFIG_$(SPL_TPL_)GENERATE_ACPI_TABLE
obj-$(CONFIG_$(SPL_)ACPIGEN) += acpigen.o
diff --git a/lib/acpi/acpi.c b/lib/acpi/acpi.c
new file mode 100644
index 000..14b15754f49
--- /dev/null
+++ b/lib/acpi/acpi.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Utility functions for ACPI
+ *
+ * Copyright 2023 Google LLC
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct acpi_table_header *acpi_find_table(const char *sig)
+{
+ struct acpi_rsdp *rsdp;
+ struct acpi_rsdt *rsdt;
+ int len, i, count;
+
+ rsdp = map_sysmem(gd_acpi_start(), 0);
+ if (!rsdp)
+ return NULL;
+ rsdt = map_sysmem(rsdp->rsdt_address, 0);
+ len = rsdt->header.length - sizeof(rsdt->header);
+ count = len / sizeof(u32);
+ for (i = 0; i < count; i++) {
+ struct acpi_table_header *hdr;
+
+ hdr = map_sysmem(rsdt->entry[i], 0);
+ if (!memcmp(hdr->signature, sig, ACPI_NAME_LEN))
+ return hdr;
+ if (!memcmp(hdr->signature, "FACP", ACPI_NAME_LEN)) {
+ struct acpi_fadt *fadt = (struct acpi_fadt *)hdr;
+
+ if (!memcmp(sig, "DSDT", ACPI_NAME_LEN) && fadt->dsdt)
+ return map_sysmem(fadt->dsdt, 0);
+ if (!memcmp(sig, "FACS", ACPI_NAME_LEN) &&
+ fadt->firmware_ctrl)
+ return map_sysmem(fadt->firmware_ctrl, 0);
+ }
+ }
+
+ return NULL;
+}
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v4 06/16] x86: coreboot: Collect the address of the ACPI tables
At present any ACPI tables created by prior-stage firmware are ignored.
It is useful to be able to view these in U-Boot.
Pick this up from the sysinfo tables and display it with the cbsysinfo
command. This allows the 'acpi list' command to work when booting from
coreboot.
Adjust the global_data condition so that acpi_start is available even if
table-generation is disabled.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
(no changes since v2)
Changes in v2:
- Use tab instead of space in header file
- Refactor two patches into one
arch/x86/include/asm/cb_sysinfo.h | 2 ++
arch/x86/include/asm/coreboot_tables.h | 2 ++
arch/x86/lib/coreboot/cb_sysinfo.c | 11 +++
cmd/x86/cbsysinfo.c| 1 +
include/asm-generic/global_data.h | 4 ++--
5 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/cb_sysinfo.h
b/arch/x86/include/asm/cb_sysinfo.h
index 0201ac6b03a..6b266149cf6 100644
--- a/arch/x86/include/asm/cb_sysinfo.h
+++ b/arch/x86/include/asm/cb_sysinfo.h
@@ -133,6 +133,7 @@
* @mtc_size: Size of MTC region
* @chromeos_vpd: Chromium OS Vital Product Data region, typically NULL,
meaning
* not used
+ * @rsdp: Pointer to ACPI RSDP table
*/
struct sysinfo_t {
unsigned int cpu_khz;
@@ -211,6 +212,7 @@ struct sysinfo_t {
u64 mtc_start;
u32 mtc_size;
void*chromeos_vpd;
+ void *rsdp;
};
extern struct sysinfo_t lib_sysinfo;
diff --git a/arch/x86/include/asm/coreboot_tables.h
b/arch/x86/include/asm/coreboot_tables.h
index f131de56a40..4de137fbab9 100644
--- a/arch/x86/include/asm/coreboot_tables.h
+++ b/arch/x86/include/asm/coreboot_tables.h
@@ -422,6 +422,8 @@ struct cb_tsc_info {
#define CB_TAG_SERIALNO0x002a
#define CB_MAX_SERIALNO_LENGTH 32
+#define CB_TAG_ACPI_RSDP 0x0043
+
#define CB_TAG_CMOS_OPTION_TABLE 0x00c8
struct cb_cmos_option_table {
diff --git a/arch/x86/lib/coreboot/cb_sysinfo.c
b/arch/x86/lib/coreboot/cb_sysinfo.c
index 748fa4ee53b..a11a2587f66 100644
--- a/arch/x86/lib/coreboot/cb_sysinfo.c
+++ b/arch/x86/lib/coreboot/cb_sysinfo.c
@@ -264,6 +264,13 @@ static void cb_parse_mrc_cache(void *ptr, struct sysinfo_t
*info)
info->mrc_cache = map_sysmem(cbmem->cbmem_tab, 0);
}
+static void cb_parse_acpi_rsdp(void *ptr, struct sysinfo_t *info)
+{
+ struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr;
+
+ info->rsdp = map_sysmem(cbmem->cbmem_tab, 0);
+}
+
__weak void cb_parse_unhandled(u32 tag, unsigned char *ptr)
{
}
@@ -428,6 +435,9 @@ static int cb_parse_header(void *addr, int len, struct
sysinfo_t *info)
case CB_TAG_MRC_CACHE:
cb_parse_mrc_cache(rec, info);
break;
+ case CB_TAG_ACPI_RSDP:
+ cb_parse_acpi_rsdp(rec, info);
+ break;
default:
cb_parse_unhandled(rec->tag, ptr);
break;
@@ -454,6 +464,7 @@ int get_coreboot_info(struct sysinfo_t *info)
if (!ret)
return -ENOENT;
gd->arch.coreboot_table = addr;
+ gd_set_acpi_start(map_to_sysmem(info->rsdp));
gd->flags |= GD_FLG_SKIP_LL_INIT;
return 0;
diff --git a/cmd/x86/cbsysinfo.c b/cmd/x86/cbsysinfo.c
index 34fdaf5b1b1..07570b00c9a 100644
--- a/cmd/x86/cbsysinfo.c
+++ b/cmd/x86/cbsysinfo.c
@@ -363,6 +363,7 @@ static void show_table(struct sysinfo_t *info, bool verbose)
print_hex("MTC size", info->mtc_size);
print_ptr("Chrome OS VPD", info->chromeos_vpd);
+ print_ptr("RSDP", info->rsdp);
}
static int do_cbsysinfo(struct cmd_tbl *cmdtp, int flag, int argc,
diff --git a/include/asm-generic/global_data.h
b/include/asm-generic/global_data.h
index 987fb66c17a..422e0cf4720 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -457,7 +457,7 @@ struct global_data {
*/
fdt_addr_t translation_offset;
#endif
-#ifdef CONFIG_GENERATE_ACPI_TABLE
+#ifdef CONFIG_ACPI
/**
* @acpi_ctx: ACPI context pointer
*/
@@ -536,7 +536,7 @@ static_assert(sizeof(struct global_data) == GD_SIZE);
#define gd_dm_priv_base() NULL
#endif
-#ifdef CONFIG_GENERATE_ACPI_TABLE
+#ifdef CONFIG_ACPI
#define gd_acpi_ctx() gd->acpi_ctx
#define gd_acpi_start()gd->acpi_start
#define gd_set_acpi_start(addr)gd->acpi_start = addr
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v4 04/16] acpi: Create a new Kconfig for ACPI
We have several Kconfig options for ACPI, but all relate to specific
functions, such as generating tables and AML code.
Add a new option which controls including basic ACPI library code,
including the lib/acpi directory. This will allow us to add functions
which are available even if table generation is not supported.
Adjust the command to avoid a build error when ACPIGEN is not enabled.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
(no changes since v3)
Changes in v3:
- Don't enable ACPI by default except on x86 and sandbox
Changes in v2:
- Add new patch to create a new Kconfig for ACPI
arch/Kconfig | 2 ++
cmd/Kconfig | 2 +-
cmd/acpi.c | 4
drivers/core/Kconfig | 1 +
lib/Kconfig | 10 +-
lib/Makefile | 2 +-
lib/acpi/Makefile| 4
7 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/arch/Kconfig b/arch/Kconfig
index 55b9a5eb8a5..c9a33592252 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -195,6 +195,7 @@ config SANDBOX
imply PHYLIB
imply DM_MDIO
imply DM_MDIO_MUX
+ imply ACPI
imply ACPI_PMC
imply ACPI_PMC_SANDBOX
imply CMD_PMC
@@ -261,6 +262,7 @@ config X86
imply PCH
imply PHYSMEM
imply RTC_MC146818
+ imply ACPI
imply ACPIGEN if !QEMU && !EFI_APP
imply SYSINFO if GENERATE_SMBIOS_TABLE
imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
diff --git a/cmd/Kconfig b/cmd/Kconfig
index e45b8847aef..56f5ab02239 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -109,7 +109,7 @@ menu "Info commands"
config CMD_ACPI
bool "acpi"
- depends on ACPIGEN
+ depends on ACPI
default y
help
List and dump ACPI tables. ACPI (Advanced Configuration and Power
diff --git a/cmd/acpi.c b/cmd/acpi.c
index d0fc062ef8c..991b5235e28 100644
--- a/cmd/acpi.c
+++ b/cmd/acpi.c
@@ -162,6 +162,10 @@ static int do_acpi_items(struct cmd_tbl *cmdtp, int flag,
int argc,
bool dump_contents;
dump_contents = argc >= 2 && !strcmp("-d", argv[1]);
+ if (!IS_ENABLED(CONFIG_ACPIGEN)) {
+ printf("Not supported (enable ACPIGEN)\n");
+ return CMD_RET_FAILURE;
+ }
acpi_dump_items(dump_contents ? ACPI_DUMP_CONTENTS : ACPI_DUMP_LIST);
return 0;
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index 0f755aa702e..f0d848f45d8 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -448,6 +448,7 @@ config OFNODE_MULTI_TREE_MAX
config ACPIGEN
bool "Support ACPI table generation in driver model"
+ depends on ACPI
default y if SANDBOX || (GENERATE_ACPI_TABLE && !QEMU)
select LIB_UUID
help
diff --git a/lib/Kconfig b/lib/Kconfig
index d8dac09ea84..c8b3ec1ec9c 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -281,9 +281,17 @@ config SUPPORT_ACPI
U-Boot can generate these tables and pass them to the Operating
System.
+config ACPI
+ bool "Enable support for ACPI libraries"
+ depends on SUPPORT_ACPI
+ help
+ Provides library functions for dealing with ACPI tables. This does
+ not necessarily include generation of tables
+ (see GENERATE_ACPI_TABLE), but allows for tables to be located.
+
config GENERATE_ACPI_TABLE
bool "Generate an ACPI (Advanced Configuration and Power Interface)
table"
- depends on SUPPORT_ACPI
+ depends on ACPI
select QFW if QEMU
help
The Advanced Configuration and Power Interface (ACPI) specification
diff --git a/lib/Makefile b/lib/Makefile
index 10aa7ac0298..8d8ccc8bbc3 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -66,7 +66,7 @@ obj-$(CONFIG_$(SPL_TPL_)CRC8) += crc8.o
obj-y += crypto/
-obj-$(CONFIG_$(SPL_TPL_)GENERATE_ACPI_TABLE) += acpi/
+obj-$(CONFIG_$(SPL_TPL_)ACPI) += acpi/
obj-$(CONFIG_$(SPL_)MD5) += md5.o
obj-$(CONFIG_ECDSA) += ecdsa/
obj-$(CONFIG_$(SPL_)RSA) += rsa/
diff --git a/lib/acpi/Makefile b/lib/acpi/Makefile
index 956b5a0d726..12337abaecf 100644
--- a/lib/acpi/Makefile
+++ b/lib/acpi/Makefile
@@ -1,6 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
+ifdef CONFIG_$(SPL_TPL_)GENERATE_ACPI_TABLE
+
obj-$(CONFIG_$(SPL_)ACPIGEN) += acpigen.o
obj-$(CONFIG_$(SPL_)ACPIGEN) += acpi_device.o
obj-$(CONFIG_$(SPL_)ACPIGEN) += acpi_dp.o
@@ -21,3 +23,5 @@ endif
obj-y += facs.o
obj-y += ssdt.o
endif
+
+endif # GENERATE_ACPI_TABLE
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v4 03/16] input: Flush the keyboard buffer before resetting it
If U-Boot is not the first-stage bootloader the keyboard may already be
set up. Make sure to flush any data before trying to reset it. This
avoids a long timeout / hang.
Add some comments and a log category while we are here.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
(no changes since v2)
Changes in v2:
- Flush the buffer instead of skipping the reset
drivers/input/i8042.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c
index 3563dc98838..e6070ca0152 100644
--- a/drivers/input/i8042.c
+++ b/drivers/input/i8042.c
@@ -6,6 +6,8 @@
/* i8042.c - Intel 8042 keyboard driver routines */
+#define LOG_CATEGORY UCLASS_KEYBOARD
+
#include
#include
#include
@@ -54,6 +56,14 @@ static unsigned char ext_key_map[] = {
0x00 /* map end */
};
+/**
+ * kbd_input_empty() - Wait until the keyboard is ready for a command
+ *
+ * Checks the IBF flag (input buffer full), waiting for it to indicate that
+ * any previous command has been processed.
+ *
+ * Return: true if ready, false if it timed out
+ */
static int kbd_input_empty(void)
{
int kbd_timeout = KBD_TIMEOUT * 1000;
@@ -64,6 +74,12 @@ static int kbd_input_empty(void)
return kbd_timeout != -1;
}
+/**
+ * kbd_output_full() - Wait until the keyboard has data available
+ *
+ * Checks the OBF flag (output buffer full), waiting for it to indicate that
+ * a response to a previous command is available
+ */
static int kbd_output_full(void)
{
int kbd_timeout = KBD_TIMEOUT * 1000;
@@ -127,6 +143,9 @@ static int kbd_reset(int quirk)
{
int config;
+ if (!kbd_input_empty())
+ goto err;
+
/* controller self test */
if (kbd_cmd_read(CMD_SELF_TEST) != KBC_TEST_OK)
goto err;
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v4 02/16] x86: Adjust search range for sysinfo table
Avoid searching starting at 0 since this memory may not be available,
e.g. if protection against NULL-pointer access is enabled. The table
cannot be there anyway, since the first 1KB of memory was originally
used for the interrupt table and coreboot avoids it.
Start at 0x400 instead.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
(no changes since v2)
Changes in v2:
- Update commit message with more detail
- Update code comment to mention that addresses <1KB are ignored
arch/x86/cpu/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 6fe6eaf6c84..281e966 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -351,8 +351,8 @@ long locate_coreboot_table(void)
{
long addr;
- /* We look for LBIO in the first 4K of RAM and again at 960KB */
- addr = detect_coreboot_table_at(0x0, 0x1000);
+ /* We look for LBIO from addresses 1K-4K and again at 960KB */
+ addr = detect_coreboot_table_at(0x400, 0xc00);
if (addr < 0)
addr = detect_coreboot_table_at(0xf, 0x1000);
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v4 01/16] mtrr: Don't show an invalid CPU number
When U-Boot did not do the MP init, we don't get an actual CPU number
here. Skip printing it in that case.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
(no changes since v2)
Changes in v2:
- Don't show an invalid CPU number on error
cmd/x86/mtrr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c
index b213a942fde..b1691d8b65a 100644
--- a/cmd/x86/mtrr.c
+++ b/cmd/x86/mtrr.c
@@ -148,7 +148,8 @@ static int do_mtrr(struct cmd_tbl *cmdtp, int flag, int
argc,
printf("CPU %d:\n", i);
ret = do_mtrr_list(reg_count, i);
if (ret) {
- printf("Failed to read CPU %d (err=%d)\n", i,
+ printf("Failed to read CPU %s (err=%d)\n",
+ i < MP_SELECT_ALL ? simple_itoa(i) : "",
ret);
return CMD_RET_FAILURE;
}
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v4 00/16] x86: Various minor enhancements for coreboot
This series includes some patches generated while getting U-Boot to boot more nicely on Brya, an Adler Lake Chromebook. This includes: - show the ACPI tables with 'acpi list' - get the UART to work even if coreboot doesn't enable it - show unimplemented sysinfo tags - fix for keyboard not working - fix for trying to set up PCI regions when the info is not available - fix for looking at inaccessible memory to find the sysinfo table Changes in v4: - Split out patch to enable bus mastering - Drop unnecessary CONFIG options - Drop patch to allow locating UARTs by device ID Changes in v3: - Don't enable ACPI by default except on x86 and sandbox - Avoid a build error with the ASL compiler - Disable for coreboot64 since ACPI is not available Changes in v2: - Don't show an invalid CPU number on error - Update commit message with more detail - Update code comment to mention that addresses <1KB are ignored - Flush the buffer instead of skipping the reset - Add new patch to create a new Kconfig for ACPI - Add new patch to move acpi-table-finding functions into the library - Use tab instead of space in header file - Refactor two patches into one - Add new patch to allow locating the UART from ACPI tables - Expand commit message to explain this is for the debug UART - Update the defconfig instead - Drop patch 'usb: Quieten a debug message' since it was fixed elsewhere - Drop patch 'x86: coreboot: Use a memory-mapped UART' (not needed) - Add new patch to enable ms command Simon Glass (16): mtrr: Don't show an invalid CPU number x86: Adjust search range for sysinfo table input: Flush the keyboard buffer before resetting it acpi: Create a new Kconfig for ACPI acpi: Move the table-finding functions into the libary x86: coreboot: Collect the address of the ACPI tables x86: Allow locating the UART from ACPI tables pci: coreboot: Don't read regions when booting x86: coreboot: Use a memory-mapped UART x86: coreboot: Document how to enable the debug UART x86: coreboot: Scan PCI after relocation x86: coreboot: Log function names and line numbers x86: coreboot: Show unimplemented sysinfo tags nvme: Enable PCI bus mastering x86: nvme: coreboot: Enable NVMe coreboot: Enable ms command arch/Kconfig | 2 + arch/x86/cpu/cpu.c | 4 +- arch/x86/include/asm/cb_sysinfo.h | 8 ++ arch/x86/include/asm/coreboot_tables.h | 2 + arch/x86/lib/coreboot/cb_sysinfo.c | 13 +++ cmd/Kconfig| 2 +- cmd/acpi.c | 44 ++ cmd/x86/cbsysinfo.c| 9 ++ cmd/x86/mtrr.c | 3 +- configs/coreboot64_defconfig | 1 - configs/coreboot_defconfig | 8 +- doc/board/coreboot/coreboot.rst| 29 +++ drivers/core/Kconfig | 1 + drivers/input/i8042.c | 19 + drivers/nvme/nvme_pci.c| 5 ++ drivers/pci/pci-uclass.c | 4 + drivers/serial/Kconfig | 10 +++ drivers/serial/serial_coreboot.c | 114 +++-- include/acpi/acpi_table.h | 8 ++ include/asm-generic/global_data.h | 4 +- lib/Kconfig| 10 ++- lib/Makefile | 2 +- lib/acpi/Makefile | 6 ++ lib/acpi/acpi.c| 45 ++ 24 files changed, 296 insertions(+), 57 deletions(-) create mode 100644 lib/acpi/acpi.c -- 2.40.1.521.gf1e218fcd8-goog
[PATCH v3 17/17] x86: samus: Adjust TPL start and pre-reloc memory size
Move the TPL up a little to make room for the refcode binary blob. Also increase the pre-relocation memory to make space for recent additions. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v2) Changes in v2: - Drop patch "x86: Add on to existing MTRRs in SPL" - Add various patches to resolve problems with chromebook_link64 configs/chromebook_samus_tpl_defconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig index 337768b45fd..4cfaf4bc5c7 100644 --- a/configs/chromebook_samus_tpl_defconfig +++ b/configs/chromebook_samus_tpl_defconfig @@ -1,6 +1,6 @@ CONFIG_X86=y CONFIG_TEXT_BASE=0xffed -CONFIG_SYS_MALLOC_F_LEN=0x1a00 +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x3F8000 @@ -8,7 +8,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus" CONFIG_SPL_TEXT_BASE=0xffe7 -CONFIG_TPL_TEXT_BASE=0xfffd8000 +CONFIG_TPL_TEXT_BASE=0xfffd8100 CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_DEBUG_UART_BOARD_INIT=y -- 2.40.1.521.gf1e218fcd8-goog
[PATCH v3 15/17] x86: Simplify cpu_jump_to_64bit_uboot()
This copies the cpu_call64() function to memory address and then jumps to
it. This seems to work correctly even when called from SPL, which is
running from SPI flash.
Drop the copy as it is not needed.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3:
- Fix 'call' typo
arch/x86/cpu/i386/cpu.c | 32 +---
1 file changed, 5 insertions(+), 27 deletions(-)
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index c7f6c5a013e..91cd5d7c9e4 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -572,6 +572,7 @@ int cpu_has_64bit(void)
has_long_mode();
}
+/* Base address for page tables used for 64-bit mode */
#define PAGETABLE_BASE 0x8
#define PAGETABLE_SIZE (6 * 4096)
@@ -614,43 +615,20 @@ int cpu_jump_to_64bit(ulong setup_base, ulong target)
}
/*
- * Jump from SPL to U-Boot
+ * cpu_jump_to_64bit_uboot() - Jump from SPL to U-Boot
*
- * This function is work-in-progress with many issues to resolve.
- *
- * It works by setting up several regions:
- * ptr - a place to put the code that jumps into 64-bit mode
- * gdt - a place to put the global descriptor table
- * pgtable - a place to put the page tables
- *
- * The cpu_call64() code is copied from ROM and then manually patched so that
- * it has the correct GDT address in RAM. U-Boot is copied from ROM into
- * its pre-relocation address. Then we jump to the cpu_call64() code in RAM,
- * which changes to 64-bit mode and starts U-Boot.
+ * It works by setting up page tables and calling the code to enter 64-bit long
+ * mode
*/
int cpu_jump_to_64bit_uboot(ulong target)
{
- typedef void (*func_t)(ulong pgtable, ulong setup_base, ulong target);
uint32_t *pgtable;
- func_t func;
- char *ptr;
pgtable = (uint32_t *)PAGETABLE_BASE;
-
build_pagetable(pgtable);
- extern long call64_stub_size;
- ptr = malloc(call64_stub_size);
- if (!ptr) {
- printf("Failed to allocate the cpu_call64 stub\n");
- return -ENOMEM;
- }
- memcpy(ptr, cpu_call64, call64_stub_size);
-
- func = (func_t)ptr;
-
/* Jump to U-Boot */
- func((ulong)pgtable, 0, (ulong)target);
+ cpu_call64(PAGETABLE_BASE, 0, (ulong)target);
return -EFAULT;
}
--
2.40.1.521.gf1e218fcd8-goog
[PATCH v3 16/17] x86: samus: Don't include audio and SATA in TPL
These are not used in TPL so disable the drivers to save space. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) arch/x86/cpu/broadwell/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile index 52d56c65be8..3e1f76d6118 100644 --- a/arch/x86/cpu/broadwell/Makefile +++ b/arch/x86/cpu/broadwell/Makefile @@ -2,7 +2,6 @@ # # Copyright (c) 2016 Google, Inc -obj-y += adsp.o obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += cpu.o obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += cpu_full.o @@ -14,6 +13,8 @@ obj-y += refcode.o endif ifndef CONFIG_SPL_BUILD # obj-y += cpu_from_spl.o +obj-y += adsp.o +obj-y += sata.o endif endif @@ -29,5 +30,4 @@ obj-y += pch.o obj-y += pinctrl_broadwell.o obj-y += power_state.o obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += refcode.o -obj-y += sata.o obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += sdram.o -- 2.40.1.521.gf1e218fcd8-goog
[PATCH v3 11/17] x86: Tidy up address for loading U-Boot from SPL
Use the binman symbols for this, to avoid hard-coding the value. We could
use CONFIG_X86_OFFSET_U_BOOT for the address, but it seems better to
obtain the offset and size through the same mechanism.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
(no changes since v2)
Changes in v2:
- Add new patch to tidy up address for loading U-Boot from SPL
arch/x86/lib/spl.c | 13 +++--
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index 5e47ffa7db7..479889aec6f 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -217,16 +217,9 @@ static int spl_board_load_image(struct spl_image_info
*spl_image,
spl_image->name = "U-Boot";
if (!IS_ENABLED(CONFIG_SYS_COREBOOT)) {
- /*
-* Copy U-Boot from ROM
-* TODO(s...@chromium.org): Figure out a way to get the text
base
-* correctly here, and in the device-tree binman definition.
-*
-* Also consider using FIT so we get the correct image length
-* and parameters.
-*/
- memcpy((char *)spl_image->load_addr, (char *)0xfff0,
- 0x10);
+ /* Copy U-Boot from ROM */
+ memcpy((void *)spl_image->load_addr,
+ (void *)spl_get_image_pos(), spl_get_image_size());
}
debug("Loading to %lx\n", spl_image->load_addr);
--
2.40.1.521.gf1e218fcd8-goog
