Re: [PATCH v4 02/16] arm: mach-k3: Add basic support for J784S4 SoC definition
Hi Nishanth,
On 11:01-20231002, Nishanth Menon wrote:
> > diff --git a/arch/arm/mach-k3/j784s4_init.c b/arch/arm/mach-k3/j784s4_init.c
[..]
> > +struct fwl_data infra_cbass0_fwls[] = {
> > + { "PSC0", 5, 1 },
> > + { "PLL_CTRL0", 6, 1 },
> > + { "PLL_MMR0", 8, 26 },
> > + { "CTRL_MMR0", 9, 16 },
> > + { "GPIO0", 16, 1 },
> > +}, wkup_cbass0_fwls[] = {
> > + { "WKUP_PSC0", 129, 1 },
> > + { "WKUP_PLL_CTRL0", 130, 1 },
> > + { "WKUP_CTRL_MMR0", 131, 16 },
> > + { "WKUP_GPIO0", 132, 1 },
> > + { "WKUP_I2C0", 144, 1 },
> > + { "WKUP_USART0", 160, 1 },
> > +}, mcu_cbass0_fwls[] = {
> > + { "MCU_R5FSS0_CORE0", 1024, 4 },
> > + { "MCU_R5FSS0_CORE0_CFG", 1025, 3 },
> > + { "MCU_R5FSS0_CORE1", 1028, 4 },
> > + { "MCU_R5FSS0_CORE1_CFG", 1029, 1 },
> > + { "MCU_FSS0_CFG", 1032, 12 },
> > + { "MCU_FSS0_S1", 1033, 8 },
> > + { "MCU_FSS0_S0", 1036, 8 },
> > + { "MCU_PSROM49152X32", 1048, 1 },
> > + { "MCU_MSRAM128KX64", 1050, 8 },
> > + { "MCU_MSRAM128KX64_CFG", 1051, 1 },
> > + { "MCU_TIMER0", 1056, 1 },
> > + { "MCU_TIMER9", 1065, 1 },
> > + { "MCU_USART0", 1120, 1 },
> > + { "MCU_I2C0", 1152, 1 },
> > + { "MCU_CTRL_MMR0", 1200, 8 },
> > + { "MCU_PLL_MMR0", 1201, 3 },
> > + { "MCU_CPSW0", 1220, 2 },
> > +}, cbass_rc_cfg0_fwls[] = {
> > + { "EMMCSD4SS0_CFG", 2400, 4 },
> > +}, cbass_hc2_fwls[] = {
> > + { "PCIE0", 2547, 24 },
> > +}, cbass_hc_cfg0_fwls[] = {
> > + { "PCIE0_CFG", 2577, 7 },
> > + { "EMMC8SS0_CFG", 2579, 4 },
> > + { "USB3SS0_CORE", 2580, 4 },
> > + { "USB3SS1_CORE", 2581, 1 },
> > +}, navss_cbass0_fwls[] = {
> > + { "NACSS_VIRT0", 6253, 1 },
> > +};
[..]
> > +void board_init_f(ulong dummy)
> > +{
[..]
> > +
> > + remove_fwl_configs(cbass_hc_cfg0_fwls,
> > ARRAY_SIZE(cbass_hc_cfg0_fwls));
> > + remove_fwl_configs(cbass_hc2_fwls, ARRAY_SIZE(cbass_hc2_fwls));
> > + remove_fwl_configs(cbass_rc_cfg0_fwls,
> > ARRAY_SIZE(cbass_rc_cfg0_fwls));
> > + remove_fwl_configs(infra_cbass0_fwls,
> > ARRAY_SIZE(infra_cbass0_fwls));
> > + remove_fwl_configs(mcu_cbass0_fwls,
> > ARRAY_SIZE(mcu_cbass0_fwls));
> > + remove_fwl_configs(wkup_cbass0_fwls,
> > ARRAY_SIZE(wkup_cbass0_fwls));
> > + remove_fwl_configs(navss_cbass0_fwls,
> > ARRAY_SIZE(navss_cbass0_fwls));
>
> Why do you need this? firewall configuration was coming in via OIDs in
> https://lore.kernel.org/all/CAPnjgZ14Uy+gBC8kgqVA7m9NXN_WiXFffu5Ob=vz=e76rmd...@mail.gmail.com/
>
These are required to remove the firewall configurations that are done
by ROM, those are not the ones that are being handled by OIDs. The
current series that is being worked on is to add additional firewalling
support with OIDs that TIFS will be handling. The above patch is
essentially added to have the same development experience on GP devices
similar to HS after the secure boot is done so that people don't end up
hitting random firewall exceptions that the ROM had configured.
Regards,
Manorit
>
> > + }
> > +
[..]
Re: [PATCH v4 1/3] binman: btool: Add Xilinx Bootgen btool
Hi, On Sat, 5 Aug 2023 at 13:51, Simon Glass wrote: > > On Thu, 3 Aug 2023 at 09:22, wrote: > > > > From: Lukas Funke > > > > Add the Xilinx Bootgen as bintool. Xilinx Bootgen is used to create > > bootable SPL (FSBL in Xilinx terms) images for Zynq/ZynqMP devices. The > > btool creates a signed version of the SPL. Additionally to signing the > > key source for the decryption engine can be passend to the boot image. > > > > Signed-off-by: Lukas Funke > > > > --- > > > > Changes in v4: > > - Fixed some typos > > > > Changes in v3: > > - Fixed an issue where the build result was not found > > - Fixed an issue where the version string was not reported correctly > > > > Changes in v2: > > - Pass additional 'keysrc_enc' parameter to Bootgen > > - Added more information and terms to documentation > > > > tools/binman/bintools.rst | 2 +- > > tools/binman/btool/bootgen.py | 137 ++ > > 2 files changed, 138 insertions(+), 1 deletion(-) > > create mode 100644 tools/binman/btool/bootgen.py > > > > Reviewed-by: Simon Glass > > Applied to u-boot-dm, thanks! On -next I see this: binman tool -f bootgen Fetch: bootgen - trying method: binary download - trying method: build from source - clone git repo 'https://github.com/Xilinx/bootgen' to '/tmp/binmanf.0bzta5ph' - build target 'a' Exception: Error 2 running 'make -C /tmp/binmanf.0bzta5ph -j 64 a': make: *** No rule to make target 'a'. Stop. - failed to fetch with all methods 2. There seems to be some test coverage missing: tools/binman/etype/xilinx_bootgen.py 72 199% The offending line is 216: data = tools.read_file(bootbin_fname) Please could you take a look? Regards, Simon
Re: [PATCH] scripts/Makefile.lib: also consider $(CONFIG_SYS_BOARD)-u-boot.dtsi
Hi Rasmus, On Mon, 2 Oct 2023 at 13:02, Rasmus Villemoes wrote: > > On 29/09/2023 18.02, Tom Rini wrote: > > On Fri, Sep 29, 2023 at 09:15:00AM -0600, Simon Glass wrote: > > >> Honestly at this point I've forgotten what this is all about. > > Fair enough, let me try to recap, though even a summary is a bit long. > > (1) I wanted to do what $subject says, and you seemed to be ok with that > > https://lore.kernel.org/u-boot/capnjgz1b+3v_5rcsbnugz6cvo4odjjdfes0rx3imw4vjxuo...@mail.gmail.com/ > > (2) Tom pointed out that, unfortunately, as-is, the patch caused a bunch > of build failures. With hindsight, that was inevitable. > > https://lore.kernel.org/u-boot/c3c94614-9916-7316-e009-04ddbdc20...@prevas.dk/ > > (3) I still very much would like the original patch to go in, and so I > pointed out that most of the current arch/*/dts/Makefile are actually > completely redundant, with the logic in scripts/Makefile.dts being in place. > > This is when the thread turned away from talking about the original > patch, but rather the cleanup of the makefile logic that turns out to be > a prerequisite for said patch to go anywhere. > > (4) Tom tested a patch that nuked most of the arch/arm/dts/Makefile, > which revealed a few defects, partly in Makefile.dts (got fixed in > 6923f49d3ac2) partly in a board defconfig (got fixed in 2d158d3c387d). > > >> Perhaps the easiest approach is to create a new Kconfig to control > >> whether a board-level .dtsi is included in the list of wildcard > >> searches. Then you can enable it for your board without affecting > >> others. > > > > That's getting things backwards, from what this cleanup does. Today we > > have messy lists of "build these device trees" and then don't use most > > of them, and some of the list is just Wrong (listing dts files as an > > output). > > (5) Then a few months passed. I'm still interested in the original > patch, and also the cleanup. So I pinged Tom to redo that build test > with most of the Makefile gone. While revisiting this and doing that > mechanical strip-down of the Makefile, I noticed that the Makefile has > grown not just one but two .dts files listed in dtb-y, which is of > course bogus, and nobody noticed or cared because the > scripts/Makefile.dts logic JustWorks. > > So, given that today, each board, in the form of the defconfig used to > build for it, in 99.9% of cases already includes all the information the > build system needs in order to ensure that all relevant .dtb files gets > built [because there's only one and that's DEFAULT_DEVICETREE, or > there's more and those are in OF_LIST or SPL_OF_LIST], and the Makefile > is error-prone to maintain and when adding a new board one chooses some > semi-random-list to add one's .dtbs (or .dts.) to, we want to simply > stop having all those lists in arch/arm/dts/Makefile (and the other > arch/*/dts/Makefile, but those are much smaller and can be handled > later). No TARGET lists, no SOC lists, no nothing. > > Yes, there may still be some 0.1%. We're trying to figure out if they > exist, which they are, and how best to handle them. An easy fix is to > drop the condition on when OF_LIST is settable to something different > from its default (which is DEFAULT_DEVICETREE). But without knowing just > exactly which boards and which .dtbs we're talking about, it's hard to > know what the best solution is or if there is actually anything that > needs to be done. Thanks for all the details. My memory for things that last across months is not good. It is clearer now. I don't really see any specific problem with this. It does seem duplicative though, in that each board (in a group that differ only in their DT) has to have the same list. Why not have it once, in the Makefile, based on ARCH_SOC...? Perhaps I am unrealistic in hoping that much of the C code for a board will go away, but we do see boards which don't have much / any code, but do have hardware differences. I would love to put a stake in the ground and say that boards that use the same SoC should be able to use the same C code and work correctly, just with a different DT. For example I think most/all rockchip boards are like that. Then we might head closer to the kernel which can boot on various boards with the same build. It seems to me that heading the way you describe, we are making it harder for people to do this, or even suggesting that it is not desirable. Anyway I will leave you and Tom to figure this out, since you seem very keen on this idea. Thank you again for explaining it all. Regards, Simon
Re: [PATCH 03/25] autoboot: Correct dependencies on CMDLINE
Hi Tom, On Sun, 24 Sept 2023 at 18:40, Tom Rini wrote: > > On Sun, Sep 24, 2023 at 02:39:21PM -0600, Simon Glass wrote: > > > Make AUTOBOOT depend on CMDLINE since it is mostly meaningless without it. > > > > Signed-off-by: Simon Glass > > --- > > > > boot/Kconfig | 23 ++- > > 1 file changed, 14 insertions(+), 9 deletions(-) > > > > diff --git a/boot/Kconfig b/boot/Kconfig > > index f74ac7e9cc72..41ec2c34bf74 100644 > > --- a/boot/Kconfig > > +++ b/boot/Kconfig > > @@ -1167,14 +1167,16 @@ menu "Autoboot options" > > > > config AUTOBOOT > > bool "Autoboot" > > + depends on CMDLINE > > default y > > help > > This enables the autoboot. See doc/README.autoboot for detail. > > This is fine and correct. > > > +if AUTOBOOT > > + > > config BOOTDELAY > > int "delay in seconds before automatically booting" > > default 2 > > - depends on AUTOBOOT > [snip] > > @@ -1322,6 +1324,9 @@ config AUTOBOOT_STOP_STR_SHA256 > > includes a ":", the portion prior to the ":" will be treated > > as a salt value. > > > > +endif # AUTOBOOT_KEYED > > +endif # AUTOBOOT > > So it's ~200 lines, yes, hiding this under an if, or perhaps a menu > makes sense, however... > > > config AUTOBOOT_USE_MENUKEY > > bool "Allow a specify key to run a menu from the environment" > > depends on !AUTOBOOT_KEYED > > It looks like there's more stuff to move under a menu/if here? Well this depends on !AUTOBOOT_KEYED so can't be in the 'if AUTOBOOT_KEYED'. But yes I can create a new 'if !AUTOBOOT_KEYED' for these two items. Normally we want 2-3 options to warrant an 'if', so I don't see this as a strong case. Regards, Simon
Re: [PATCH] Makefile: make u-boot-initial-env target depend explicitly on scripts_basic
On Tue, 3 Oct 2023 at 04:02, Rasmus Villemoes wrote: > > We're seeing sporadic errors like > > ENVCinclude/generated/env.txt > HOSTCC scripts/basic/fixdep > ENVPinclude/generated/env.in > ENVTinclude/generated/environment.h > HOSTCC tools/printinitialenv > /bin/sh: 1: scripts/basic/fixdep: not found > make[1]: *** [scripts/Makefile.host:95: tools/printinitialenv] Error 127 > make[1]: *** Deleting file 'tools/printinitialenv' > make: *** [Makefile:2446: u-boot-initial-env] Error 2 > make: *** Waiting for unfinished jobs > > where sometimes the "fixdep: not found" is instead "fixdep: Permission > denied" and the Error 127 becomes 126. > > This smells like a race condition, and indeed it is: Currently, > u-boot-initial-env is a prerequisite of the envtools target, which > also lists scripts_basic as a prerequisite: > > envtools: u-boot-initial-env scripts_basic $(version_h) $(timestamp_h) > tools/version.h > $(Q)$(MAKE) $(build)=tools/env > > However, the u-boot-initial-env rule involves building the > printinitialenv helper, which in turn is built using an if_changed_dep > rule. That means we must ensure scripts/basic/fixdep is built and > ready before trying to build printinitialenv, i.e. the > u-boot-initial-env rule itself must depend on the phony scripts_basic > target. > > Signed-off-by: Rasmus Villemoes > --- > Makefile | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Simon Glass I have wondered for a while if we could have a few tests of the form: - build sandbox - delete an output file - build again - check that the build succeeds and the file is there Regards, Simon
Re: [PATCH 2/2] mkimage: allow internalization of data-position
On Mon, 2 Oct 2023 at 02:01, Lars Feyaerts wrote: > > Make it possible for data that was externalized using a static external > position (-p) to be internalized. Enables the ability to convert > existing FIT images built with -p to be converted to a FIT image where the > data is internal, to be converted to a FIT image where the data is > external relative to the end of the FIT (-E) or change the initial > static external position to a different static external position (-p). > > Removing the original external-data-related properties ensures that > they're not present after conversion. Without this, they would still be > present in the resulting FIT even if the FIT has been, for example, > internalized. > > Signed-off-by: Lars Feyaerts > --- > > doc/mkimage.1 | 19 +++ > tools/fit_image.c | 26 +- > 2 files changed, 40 insertions(+), 5 deletions(-) > Reviewed-by: Simon Glass
Re: [PATCHv10 14/15] net/lwip: replace original net commands with lwip
Hi Sean,
On Tue, 3 Oct 2023 at 11:58, Sean Edmond wrote:
>
>
> On 2023-09-26 2:41 a.m., Maxim Uvarov wrote:
> > Replace original commands: ping, tftp, dhcp and wget.
> >
> > Signed-off-by: Maxim Uvarov
> > ---
> > boot/bootmeth_efi.c | 18 +++---
> > boot/bootmeth_pxe.c | 21 ++-
> > cmd/net.c | 86 +
> > cmd/pxe.c | 19 +-
> > include/net.h | 8 +++--
> > include/net/ulwip.h | 64 +
> > 6 files changed, 113 insertions(+), 103 deletions(-)
> > create mode 100644 include/net/ulwip.h
> >
> > diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c
> > index ae936c8daa..52399d627c 100644
> > --- a/boot/bootmeth_efi.c
> > +++ b/boot/bootmeth_efi.c
> > @@ -20,6 +20,8 @@
> > #include
> > #include
> > #include
> > +#include
> > +#include
> > #include
> > #include
> >
> > @@ -319,9 +321,7 @@ static int distro_efi_try_bootflow_files(struct udevice
> > *dev,
> >
> > static int distro_efi_read_bootflow_net(struct bootflow *bflow)
> > {
> > - char file_addr[17], fname[256];
> > - char *tftp_argv[] = {"tftp", file_addr, fname, NULL};
> > - struct cmd_tbl cmdtp = {}; /* dummy */
> > + char fname[256];
> > const char *addr_str, *fdt_addr_str;
> > int ret, arch, size;
> > ulong addr, fdt_addr;
> > @@ -368,7 +368,6 @@ static int distro_efi_read_bootflow_net(struct bootflow
> > *bflow)
> > if (!fdt_addr_str)
> > return log_msg_ret("fdt", -EINVAL);
> > fdt_addr = hextoul(fdt_addr_str, NULL);
> > - sprintf(file_addr, "%lx", fdt_addr);
> >
> > /* We only allow the first prefix with PXE */
> > ret = distro_efi_get_fdt_name(fname, sizeof(fname), 0);
> > @@ -379,7 +378,16 @@ static int distro_efi_read_bootflow_net(struct
> > bootflow *bflow)
> > if (!bflow->fdt_fname)
> > return log_msg_ret("fil", -ENOMEM);
> >
> > - if (!do_tftpb(, 0, 3, tftp_argv)) {
> > + ret = ulwip_init();
> > + if (ret)
> > + return log_msg_ret("ulwip_init", ret);
> > +
> > + ret = ulwip_tftp(fdt_addr, fname);
> > + if (ret)
> > + return log_msg_ret("ulwip_tftp", ret);
> > +
> > + ret = ulwip_loop();
> > + if (!ret) {
> > bflow->fdt_size = env_get_hex("filesize", 0);
> > bflow->fdt_addr = fdt_addr;
> > } else {
> > diff --git a/boot/bootmeth_pxe.c b/boot/bootmeth_pxe.c
> > index 8d489a11aa..fc6aabaa18 100644
> > --- a/boot/bootmeth_pxe.c
> > +++ b/boot/bootmeth_pxe.c
> > @@ -21,6 +21,8 @@
> > #include
> > #include
> > #include
> > +#include
> > +#include
> > #include
> >
> > static int extlinux_pxe_getfile(struct pxe_context *ctx, const char
> > *file_path,
> > @@ -116,18 +118,21 @@ static int extlinux_pxe_read_file(struct udevice
> > *dev, struct bootflow *bflow,
> > const char *file_path, ulong addr,
> > ulong *sizep)
> > {
> > - char *tftp_argv[] = {"tftp", NULL, NULL, NULL};
> > - struct pxe_context *ctx = dev_get_priv(dev);
> > - char file_addr[17];
> > ulong size;
> > int ret;
> >
> > - sprintf(file_addr, "%lx", addr);
> > - tftp_argv[1] = file_addr;
> > - tftp_argv[2] = (void *)file_path;
> > + ret = ulwip_init();
> > + if (ret)
> > + return log_msg_ret("ulwip_init", ret);
> > +
> > + ret = ulwip_tftp(addr, file_path);
> > + if (ret)
> > + return log_msg_ret("ulwip_tftp", ret);
> > +
> > + ret = ulwip_loop();
> > + if (ret)
> > + return log_msg_ret("ulwip_loop", ret);
> >
> > - if (do_tftpb(ctx->cmdtp, 0, 3, tftp_argv))
> > - return -ENOENT;
> > ret = pxe_get_file_size();
> > if (ret)
> > return log_msg_ret("tftp", ret);
> > diff --git a/cmd/net.c b/cmd/net.c
> > index d407d8320a..dc5a114309 100644
> > --- a/cmd/net.c
> > +++ b/cmd/net.c
> > @@ -22,6 +22,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > static int netboot_common(enum proto_t, struct cmd_tbl *, int, char *
> > const []);
> >
> > @@ -40,19 +41,9 @@ U_BOOT_CMD(
> > #endif
> >
> > #ifdef CONFIG_CMD_TFTPBOOT
> > -int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
> > -{
> > - int ret;
> > -
> > - bootstage_mark_name(BOOTSTAGE_KERNELREAD_START, "tftp_start");
> > - ret = netboot_common(TFTPGET, cmdtp, argc, argv);
> > - bootstage_mark_name(BOOTSTAGE_KERNELREAD_STOP, "tftp_done");
> > - return ret;
> > -}
> > -
> > #if IS_ENABLED(CONFIG_IPV6)
> > U_BOOT_CMD(
> > - tftpboot, 4, 1, do_tftpb,
> > + tftpboot, 4, 1, do_lwip_tftp,
>
> It looks like LWIP doesn't support TFTP with IPv6 addressing. Perhaps
> we need to fall back onto the existing TFTP implementation until LWIP
> supports it?
>
> Note, that currently, IPv6 TFTP
Re: [PATCH] linker_list: Fix ll_entry_get alignment
Hi Sean,
On Sun, 1 Oct 2023 at 19:43, Sean Anderson wrote:
>
> On 10/1/23 21:16, Simon Glass wrote:
> > Hi Sean,
> >
> > On Sat, 30 Sept 2023 at 09:23, Sean Anderson wrote:
> >>
> >> On 9/30/23 10:36, Sean Anderson wrote:
> >>> When ll_entry_get is used on a list entry ll_entry_declare'd in the same
> >>> file, the lack of alignment on the access will override the
> >>> ll_entry_declare alignment. This causes GCC to use the default section
> >>> alignment of 32 bytes. As list entries are not necessarily 32-byte
> >>> aligned,
> >>> this will cause a gap in the linker list, corrupting further entries.
> >>>
> >>> As a specific example, get_fs_loader uses DM_DRIVER_GET(fs_loader) in the
> >>> same file where U_BOOT_DRIVER(fs_loader) is present. This causes a crash
> >>> when walking the driver list.
> >>>
> >>> Fix this by adding appropriate alignment to all accesses.
> >>>
> >>> Fixes: 42ebaae3a33 ("common: Implement support for linker-generated
> >>> arrays")
> >>> Signed-off-by: Sean Anderson
> >>> ---
> >>>
> >>>include/linker_lists.h | 5 +++--
> >>>1 file changed, 3 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/include/linker_lists.h b/include/linker_lists.h
> >>> index f9a2ee0c762..e0c8a01b9ba 100644
> >>> --- a/include/linker_lists.h
> >>> +++ b/include/linker_lists.h
> >>> @@ -209,7 +209,8 @@
> >>> */
> >>>#define ll_entry_get(_type, _name, _list) \
> >>>({ \
> >>> - extern _type _u_boot_list_2_##_list##_2_##_name;\
> >>> + extern _type __aligned(4) \
> >>> + _u_boot_list_2_##_list##_2_##_name; \
> >>>_type *_ll_result = \
> >>>&_u_boot_list_2_##_list##_2_##_name;\
> >>>_ll_result; \
> >>> @@ -229,7 +230,7 @@
> >>> * @_list: name of the list
> >>> */
> >>>#define ll_entry_ref(_type, _name, _list) \
> >>> - ((_type *)&_u_boot_list_2_##_list##_2_##_name)
> >>> + ((_type __aligned(4) *)&_u_boot_list_2_##_list##_2_##_name)
> >>
> >> OK, so this causes an error in clang. And it isn't really necessary
> >> because the entry is already declared at this point.
> >>
> >> So I guess the right fix is to replace DM_DRIVER_GET with DM_DRIVER_REF in
> >> get_fs_loader. But this seems like a really big footgun. You can use the
> >> wrong one and there are no errors except at runtime. I wonder if we can add
> >> a warning of some kind?
> >
> > I can imagine having a runtime check, something like:
> >
> > ll_check(sizeof(struct something))
> >
> > which checks that the linker list (end - start) is a multiple of the
> > struct size. Do you think that would find the problem?
>
> Most of the time, yes.
>
> > If so, then it could be perhaps be turned into a link-time check. This
> > produces a list of the linker lists along with their individual
> > members:
> >
> > or ll in $(nm /tmp/b/coreboot/u-boot |grep u_boot_list_2 |sed
> > 's/.*_u_boot_list_2_\(.*\)_2_.*/\1/' |uniq); do echo; echo "linker
> > list: %ll"; nm /tmp/b/coreboot/u-boot |grep $ll; done
> >
> > ...
> > linker list: ut_str_test
> > 011a9a20 D _u_boot_list_2_ut_str_test_2_str_dectoul
> > 011a9a30 D _u_boot_list_2_ut_str_test_2_str_hextoul
> > 011a9a40 D _u_boot_list_2_ut_str_test_2_str_itoa
> > 011a9a50 D _u_boot_list_2_ut_str_test_2_str_simple_strtoul
> > 011a9a60 D _u_boot_list_2_ut_str_test_2_str_simple_strtoull
> > 011a9a70 D _u_boot_list_2_ut_str_test_2_str_trailing
> > 011a9a80 D _u_boot_list_2_ut_str_test_2_str_upper
> > 011a9a90 D _u_boot_list_2_ut_str_test_2_str_xtoa
> > 011a9aa0 D _u_boot_list_2_ut_str_test_2_test_str_to_list
> > ...
> >
> > Then you can check that the address of each one increments by the same
> > amount.
> >
> > Maybe.
>
> Yeah, this would be the best way to find errors in the current system.
>
> But maybe ll_entry_get should look like
>
> #define ll_entry_get(_type, _name, _list) \
> ({ \
> ll_entry_declare(_type, _name, _list); \
> _type *_ll_result = \
> &_u_boot_list_2_##_list##_2_##_name;\
> _ll_result; \
> })
>
> (untested)
>
> Regardless, I think a link-time check would be a good sanity check.
OK, well if you take a crack at it, you have a failing case to test with!
Regards,
Simon
Re: [PATCH v3 1/1] input: avoid NULL dereference
On Mon, 2 Oct 2023 at 19:09, Heinrich Schuchardt
wrote:
>
> Before using the result of env_get("stdin") we must check if it is NULL.
>
> Avoid #if. This resolves the -Wunused-but-set-variable issue and we don't
> need a dummy assignment in the else branch. Anyway this warning is
> disabled in the Makefile.
>
> For sake of readability use an early return after the configuration check.
>
> Checking CONFIG_SPL_BUILD is incorrect as env_get() is only defined if
> CONFIG_$(SPL_TPL)ENV_SUPPORT=y.
>
> Fixes: 985ca3945fa3 ("spl: input: Allow input in SPL and TPL")
> Signed-off-by: Heinrich Schuchardt
> ---
> v2:
> avoid #if
>
> v3:
> use an early return after configuration check
> remove CONFIG_SPL_BUILD check
> ---
> drivers/input/input.c | 25 +++--
> 1 file changed, 15 insertions(+), 10 deletions(-)
Reviewed-by: Simon Glass
Re: [PATCH v2 30/32] fdt: Allow the devicetree to come from a bloblist
Hi Ilias,
On Mon, 2 Oct 2023 at 01:33, Ilias Apalodimas
wrote:
>
> Hi Simon
>
> On Mon, 2 Oct 2023 at 04:23, Simon Glass wrote:
> >
> > Hi Ilias,
> >
> > On Tue, 26 Sept 2023 at 07:13, Ilias Apalodimas
> > wrote:
> > >
> > > Hi Simon,
> > >
> > > [...]
> > >
> > > > > > >
> > > > > > > So, instead of adding OF_BLOBLIST, just move this code under
> > > > > > > OF_BOARD,
> > > > > > > inside an IS_ENABLED(BLOBLIST) check. If a bloblist is required
> > > > > > > and
> > > > > > > the previous stage loader is supposed to provide a DT we can just
> > > > > > > throw an error and stop booting
> > > > > >
> > > > > > This is the bit I don't get.
> > > > > >
> > > > > > The OF_BOARD thing is a hack, in that the board can do what it
> > > > > > likes.
> > > > > > It is our way of handling board-specific mechanisms.
> > > > > >
> > > > > > But I am wanting a standard mechanism, i.e. like 'standard
> > > > > > passage', a
> > > > > > way of passing the DT through the phases.
> > > > > >
> > > > > > If I put this under OF_BOARD, then the board gets to override the
> > > > > > mechanism, so which is it?
> > > > >
> > > > > No, it's the other way around in my head. OF_BOARD description is 'a
> > > > > previous stage loader hands me over the DT', which is a superset of
> > > > > the bloblist.
> > > > > Whether it comes in a firmware handoff format, or a hacky register the
> > > > > previous bootloader filled in is a detail we have to deal with and we
> > > > > need to keep backwards compatibility.
> > > > >
> > > > > Maybe adding a coding snip would help
> > > > > if (IS_ENABLED(CONFIG_OF_BOARD)) {
> > > > > if (CONFIG_IS_ENABLED(BLOBLIST)) { <- This instead of OF_BLOBLIST
> > > > > ret = bloblist_maybe_init();
> > > > > if (ret)
> > > > > return ret;
> > > > > /* Dynamically scan for a DT in the bloblist. */
> > > > > gd->fdt_blob = bloblist_find(BLOBLISTT_CONTROL_FDT, 0);
> > > > > if (!gd->fdt_blob) {
> > > > > printf("Not FDT found in bloblist\n");
> > > > > bloblist_show_list();
> > > > >// We can choose to not return an error here and keep
> > > > > scanning in case the DT is in a register, but I am fine with both
> > > > > return -ENOENT;
> > > > > }
> > > > >gd->fdt_src = FDTSRC_BLOBLIST;
> > > > >bloblist_show_list();
> > > > >log_debug("Devicetree is in bloblist at %p\n", gd->fdt_blob);
> > > > > // We can also bail out of this entirely if we do find a DT via
> > > > > a bloblist.
> > > > > } else {
> > > > > gd->fdt_blob = board_fdt_blob_setup();
> > > > > if (ret)
> > > > > return ret;
> > > > > gd->fdt_src = FDTSRC_BOARD;
> > > > > }
> > > > > }
> > > > >
> > > > > I haven't even compiled the code above, but it should give you a
> > > > > better idea of what I am suggesting
> > > >
> > > > OK I see...yes that is along the lines of what I thought you meant.
> > > >
> > > > But OF_BOARD does not mean 'previous stage loader hands me over the
> > > > DT'. I means call board_fdt_blob_setup() which could do anything. If
> > > > some boards use that function to implement getting a DT from the prior
> > > > stage, that's fine, but it isn't limited to that.
> > >
> > > I think it is limited. The help message says 'Provider of DTB for DT
> > > control' and OF_BOARD help message is 'Provided by the board (e.g a
> > > previous loader) at runtime '.
> > > In fact, that's exactly what I tried to clean up with commit
> > > e7fb789612e39. Sandbox had its special OF_HOSTFILE for the DT. We
> > > cleaned that up and then reintroduced it with a different name in
> > > commit 275b4832f6bf91c.
> >
> > That commit adds HAS_PRIOR_STATE, though, not anything to do with sandbox.
> >
> > OK. Perhaps it is just the OF_BOARD name that I object to?
> >
> > >
> > > In any case, if people want to do 'more' we have
> > > CONFIG_OF_BOARD_SETUP/FIXUP which should be used instead for other
> > > platform-specific stuff. While at it OF_PRIOR_STAGE is a much better
> > > name that OF_BOARD. So we could get rid of OF_PRIOR_STAGE and rename
> > > OF_BOARD to that.
> >
> > To do that, we have to work out what to do with board-specific setup.
> >
> > >
> > > The function name that is called in the setup phase is
> > > board_fdt_blob_setup(), so it's explicitly targeting the fdt setup, or
> > > at least that's what the name suggets. Grepping for CONFIG_OF_BOARD
> > > matches in
> > > board/AndesTech/ae350/ae350.c
> > > board/armltd/vexpress64/vexpress64.c
> > > board/raspberrypi/rpi/rpi.c
> > > board/sifive/unleashed/unleashed.c
> > > board/sifive/unmatched/unmatched.c
> > > board/starfive/visionfive2/starfive_visionfive2.c
> > > board/xilinx/common/board.c:
> > > All these just use it to setup the DT, apart from the rpi which
> > > additionally sets up some memory for the DT.
> > >
> > > Apart from that it's used on a few platform drivers to setup
Re: [PATCH 1/1] sandbox: fix spl_board_init
On Mon, 2 Oct 2023 at 19:00, Heinrich Schuchardt wrote: > > sandbox_spl_defconfig with CONFIG_SPL_UNIT_TEST=n fails to build. > > in function `spl_board_init': > arch/sandbox/cpu/spl.c:134:(.text.spl_board_init+0x4a): > undefined reference to `ut_run_list' > > Add the missing configuration check. > > Signed-off-by: Heinrich Schuchardt > --- > arch/sandbox/cpu/spl.c | 3 +++ > 1 file changed, 3 insertions(+) Reviewed-by: Simon Glass
Re: [PATCH v4 3/4] power: regulator: Perform regulator setup inside uclass
Hi Svyatoslav, On Tue, 3 Oct 2023 at 00:21, Svyatoslav Ryhel wrote: > > Regulators initial setup was previously dependent on board call. > To move from this behaviour next solution is proposed: on post_bind > boot-on/always-on properties are checked, all regulators with > such props will be probed just after binding which ensures that > essential regulators are set, then in the post probe regulator > autoset is called so that correct regulator state according to > device tree is reached. We need a way to do this later, after all devices are probed. i.e. we must not probe things as we go. There might be other dependencies not yet bound. It may also take some time. This is not following driver model design, sorry. So please think of a way to do this properly. One option would be to add a new phase in dm_init_and_scan() which probes devices that want to be probed early. > > Signed-off-by: Svyatoslav Ryhel > [jo...@kwiboo.se: use autoset func, only probe with always/boot-on prop] > Signed-off-by: Jonas Karlman > --- > drivers/power/regulator/regulator-uclass.c | 30 ++ > 1 file changed, 25 insertions(+), 5 deletions(-) > Regards, Simon
Re: [PATCH] timer: starfive: Add Starfive timer support
On Tue, 19 Sept 2023 at 06:08, Kuan Lim Lee
wrote:
>
> Add timer driver in Starfive SoC. It is an timer that outside
> of CPU core and inside Starfive SoC.
>
> Signed-off-by: Kuan Lim Lee
> Reviewed-by: Wei Liang Lim
> ---
> drivers/timer/Kconfig | 7 +++
> drivers/timer/Makefile | 1 +
> drivers/timer/starfive-timer.c | 94 ++
> 3 files changed, 102 insertions(+)
> create mode 100644 drivers/timer/starfive-timer.c
Reviewed-by: Simon Glass
nits below
>
> diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
> index 915b2af160..a98be9dfae 100644
> --- a/drivers/timer/Kconfig
> +++ b/drivers/timer/Kconfig
> @@ -326,4 +326,11 @@ config XILINX_TIMER
> Select this to enable support for the timer found on
> any Xilinx boards (axi timer).
>
> +config STARFIVE_TIMER
> + bool "Starfive timer support"
> + depends on TIMER
> + help
> + Select this to enable support for the timer found on
> + Starfive SoC.
What resolution is the timer? How is it clocked? Is there only one channel?
> +
> endmenu
> diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
> index 1ca74805fd..1ef814970b 100644
> --- a/drivers/timer/Makefile
> +++ b/drivers/timer/Makefile
> @@ -34,3 +34,4 @@ obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
> obj-$(CONFIG_MCHP_PIT64B_TIMER)+= mchp-pit64b-timer.o
> obj-$(CONFIG_IMX_GPT_TIMER)+= imx-gpt-timer.o
> obj-$(CONFIG_XILINX_TIMER) += xilinx-timer.o
> +obj-$(CONFIG_STARFIVE_TIMER) += starfive-timer.o
> diff --git a/drivers/timer/starfive-timer.c b/drivers/timer/starfive-timer.c
> new file mode 100644
> index 00..816402fdbf
> --- /dev/null
> +++ b/drivers/timer/starfive-timer.c
> @@ -0,0 +1,94 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2022 StarFive, Inc. All rights reserved.
> + * Author: Lee Kuan Lim
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#defineSTF_TIMER_INT_STATUS0x00
> +#define STF_TIMER_CTL 0x04
> +#define STF_TIMER_LOAD 0x08
> +#define STF_TIMER_ENABLE 0x10
> +#define STF_TIMER_RELOAD 0x14
> +#define STF_TIMER_VALUE0x18
> +#define STF_TIMER_INT_CLR 0x20
> +#define STF_TIMER_INT_MASK 0x24
> +
> +struct starfive_timer_priv {
> + void __iomem *base;
> + u32 timer_size;
> +};
> +
> +static u64 notrace starfive_get_count(struct udevice *dev)
> +{
> + struct starfive_timer_priv *priv = dev_get_priv(dev);
> +
> + /* Read decrement timer value and convert to increment value */
> + return priv->timer_size - readl(priv->base + STF_TIMER_VALUE);
> +}
As an enhancement, you could provide a timer_early_get_count()
function and an easly setup, so you can use bootstage.
> +
> +static const struct timer_ops starfive_ops = {
> + .get_count = starfive_get_count,
> +};
> +
> +static int starfive_probe(struct udevice *dev)
> +{
> + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> + struct starfive_timer_priv *priv = dev_get_priv(dev);
> + int timer_channel;
> + struct clk clk;
> + int ret;
> +
> + priv->base = dev_read_addr_ptr(dev);
> + if (IS_ERR(priv->base))
if (!priv->base)
return -EINVAL
> + return PTR_ERR(priv->base);
> +
> + timer_channel = dev_read_u32_default(dev, "channel", 0);
> + priv->base = priv->base + (0x40 * timer_channel);
> +
> + /* Get clock rate from channel selectecd*/
> + ret = clk_get_by_index(dev, timer_channel, );
> + if (ret)
> + return ret;
> +
> + ret = clk_enable();
> + if (ret)
> + return ret;
> + uc_priv->clock_rate = clk_get_rate();
> +
> + /* Initiate timer, channel 0 */
> + /* Unmask Interrupt Mask */
multi-line comment style is:
/*
* line 1
* line 2
*/
> + writel(0, priv->base + STF_TIMER_INT_MASK);
> + /* Single run mode Setting */
> + if (dev_read_bool(dev, "single-run"))
> + writel(1, priv->base + STF_TIMER_CTL);
> + /* Set Reload value */
> + priv->timer_size = dev_read_u32_default(dev, "timer-size",
> 0x);
-1U ?
> + writel(priv->timer_size, priv->base + STF_TIMER_LOAD);
> + /* Enable to start timer */
> + writel(1, priv->base + STF_TIMER_ENABLE);
> +
> + return 0;
> +}
> +
> +static const struct udevice_id starfive_ids[] = {
> + { .compatible = "starfive,jh8100-timers" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(jh8100_starfive_timer) = {
> + .name = "jh8100_starfive_timer",
What is jh8100 ? Do you need that?
> + .id = UCLASS_TIMER,
> + .of_match = starfive_ids,
> + .probe = starfive_probe,
> + .ops= _ops,
> + .priv_auto = sizeof(struct starfive_timer_priv),
> +};
>
Re: [RFC PATCH v2 2/8] binman: ti-secure: Add support for firewalling entities
Hi Manorit, On Tue, 3 Oct 2023 at 05:21, Manorit Chawdhry wrote: > > Hi Simon, > > On 19:17-20231001, Simon Glass wrote: > > Hi Manorit, > > > > On Tue, 26 Sept 2023 at 01:58, Manorit Chawdhry wrote: > > > > > > We can now firewall entities while loading them through our secure > > > entity TIFS, the required information should be present in the > > > certificate that is being parsed by TIFS. > > > > > > The following commit adds the support to enable the certificates to be > > > generated if the firewall configurations are present in the binman dtsi > > > nodes. > > > > > > Signed-off-by: Manorit Chawdhry > > > --- > > > tools/binman/btool/openssl.py | 16 +++- > > > tools/binman/etype/ti_secure.py | 85 > > > + > > > tools/binman/etype/x509_cert.py | 3 +- > > > 3 files changed, 101 insertions(+), 3 deletions(-) > > > > > > > Please do check that you have 100% test coverage here (binman test -T) > > > > NameStmts Miss Cover > --- > [snip] > tools/binman/btool/openssl.py 42 0 100% > tools/binman/etype/ti_secure.py57 0 100% > tools/binman/etype/x509_cert.py70 0 100% > [snip] > --- > TOTAL558813498% > > I did check that, did you notice something else that I might've missed? > I just checked for the files that I have changed, I am not sure if there > are any dependencies that I also have to keep in mind. Do let me know if > I missed something. Yes it seems to be a problem with a Xilinx tool. I sent an email about it, so don't worry about this. Regards, iSimon
Re: [PATCH v1 3/3] arm: npcm8xx: support dcache off
Hi Tom Thanks for your reply. I will create another thread for this topic. Best regards, Jim On Mon, Oct 2, 2023 at 7:04 AM Tom Rini wrote: > > On Mon, Oct 02, 2023 at 12:40:54AM -0700, Jim Liu wrote: > > > Hi Tom > > > > I followed your suggestion to modify the code. > > but still have errors. > > Should I use my workaround? > > No, please figure out the errors, or at least post what you've got, > thanks. > > > > > Best regards, > > Jim > > > > On Thu, Sep 28, 2023 at 9:17 AM Tom Rini wrote: > > > > > > On Thu, Sep 28, 2023 at 10:32:51PM +0800, Jim Liu wrote: > > > > Hi Tom > > > > > > > > Thanks for your understanding. > > > > but this patch is an incomplete patch. > > > > After I applied this patch I had another error. > > > > > > > > arch/arm/cpu/armv8/cache_v8.c:773:2: error: #error Please describe > > > > your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache. > > > > 773 | #error Please describe your MMU layout in CONFIG_SYS_MEM_MAP > > > > and enable dcache. > > > > > > > > This error is the same as that link. > > > > > > Please use that patch as a starting point (and also possibly needing to > > > grab > > > https://patchwork.ozlabs.org/project/uboot/patch/20230822075112.717992-2-bhupesh.sha...@linaro.org/ > > > as that's how I'd like to proceed with addressing this generic armv8 > > > issue, thanks! > > > > > > > > > > > Best regards, > > > > Jim > > > > > > > > On Thu, Sep 28, 2023 at 8:23 PM Tom Rini wrote: > > > > > > > > > > On Thu, Sep 28, 2023 at 08:49:23AM +0800, Jim Liu wrote: > > > > > > Hi Tom > > > > > > > > > > > > Thanks for the quick review. > > > > > > > > > > > > if we set the CONFIG_SYS_DCACHE_OFF the armv8 will build error. > > > > > > So we added a workaround for our bmc uboot. > > > > > > > > > > > > the error message as below: > > > > > > > > > > > > CONFIG_SYS_DCACHE_OFF can't be enabled on armv8, or the following > > > > > > build error would happen. > > > > > > > > > > > > arch/arm/cpu/armv8/cpu.o: in function `cleanup_before_linux': > > > > > > arch/arm/cpu/armv8/cpu.c:60: undefined reference to `icache_disable' > > > > > > arch/arm/cpu/armv8/cpu.c:68: undefined reference to `dcache_disable' > > > > > > arch/arm/cpu/armv8/cpu.c:69: undefined reference to > > > > > > `invalidate_dcache_all' > > > > > > > > > > OK, so you need > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20230811054228.3721455-1-bhupesh.sha...@linaro.org/ > > > > > to be applied, as-is, yes? Thanks! > > > > > > > > > > > > > > > > > Best regards, > > > > > > Jim > > > > > > > > > > > > On Tue, Sep 26, 2023 at 9:48 PM Tom Rini wrote: > > > > > > > > > > > > > > On Tue, Sep 26, 2023 at 04:56:50PM +0800, Jim Liu wrote: > > > > > > > > > > > > > > > do not enable dcache by setting CONFIG_SYS_NPCM_DCACHE_OFF=y > > > > > > > > > > > > > > > > Signed-off-by: Jim Liu > > > > > > > > --- > > > > > > > > arch/arm/mach-npcm/npcm8xx/Kconfig | 4 > > > > > > > > arch/arm/mach-npcm/npcm8xx/cpu.c | 12 +++- > > > > > > > > 2 files changed, 15 insertions(+), 1 deletion(-) > > > > > > > > > > > > > > > > diff --git a/arch/arm/mach-npcm/npcm8xx/Kconfig > > > > > > > > b/arch/arm/mach-npcm/npcm8xx/Kconfig > > > > > > > > index 5f4a0506dc..163e7e7d48 100644 > > > > > > > > --- a/arch/arm/mach-npcm/npcm8xx/Kconfig > > > > > > > > +++ b/arch/arm/mach-npcm/npcm8xx/Kconfig > > > > > > > > @@ -6,6 +6,10 @@ config SYS_CPU > > > > > > > > config SYS_SOC > > > > > > > > default "npcm8xx" > > > > > > > > > > > > > > > > +config SYS_NPCM_DCACHE_OFF > > > > > > > > + bool "Do not enable dcache" > > > > > > > > + default n > > > > > > > > + > > > > > > > > config TARGET_ARBEL_EVB > > > > > > > > bool "Arbel Evaluation Board" > > > > > > > > help > > > > > > > > > > > > > > Why do we need a new Kconfig option here on top of the existing > > > > > > > generic > > > > > > > ones to control cache? > > > > > > > > > > > > > > -- > > > > > > > Tom > > > > > > > > > > -- > > > > > Tom > > > > > > -- > > > Tom > > -- > Tom
[PATCH v2] i2c: nuvoton: remove standard mode only
first version is only support standard mode.
remove this judgment to support standard/fast/fast plus mode.
Signed-off-by: Jim Liu
Changes for v2:
- add commit message
---
drivers/i2c/npcm_i2c.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/i2c/npcm_i2c.c b/drivers/i2c/npcm_i2c.c
index ea4ef53256..b867b6c8e9 100644
--- a/drivers/i2c/npcm_i2c.c
+++ b/drivers/i2c/npcm_i2c.c
@@ -517,11 +517,6 @@ static int npcm_i2c_init_clk(struct npcm_i2c_bus *bus, u32
bus_freq)
u32 sclfrq;
u8 hldt, val;
- if (bus_freq > I2C_FREQ_100K) {
- printf("Support standard mode only\n");
- return -EINVAL;
- }
-
/* SCLFRQ = T(SCL)/4/T(CLK) = FREQ(CLK)/4/FREQ(SCL) */
sclfrq = freq / (bus_freq * 4);
if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX)
--
2.25.1
[PATCH v2] pico-pi-imx7d: Unselect CONFIG_CONSOLE_MUX
From: Fabio Estevam Unselect CONFIG_CONSOLE_MUX to fix the following error for the input, output and error interfaces: U-Boot 2023.10 (Oct 03 2023 - 21:23:18 -0300) ... In:No input devices available! Out: No output devices available! Err: No error devices available! Net: eth0: ethernet@30be Hit any key to stop autoboot: 0 Signed-off-by: Fabio Estevam --- Changes since v1: - Apply for all pico-imx7 defconfigs. configs/pico-dwarf-imx7d_defconfig | 1 + configs/pico-hobbit-imx7d_defconfig | 1 + configs/pico-imx7d_bl33_defconfig | 1 + configs/pico-imx7d_defconfig| 1 + configs/pico-nymph-imx7d_defconfig | 1 + configs/pico-pi-imx7d_defconfig | 1 + 6 files changed, 6 insertions(+) diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 2cd906a63da0..8a99b813daee 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -22,6 +22,7 @@ CONFIG_BOARD_SIZE_LIMIT=715776 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb" +# CONFIG_CONSOLE_MUX is not set CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x10 diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index b63281e53322..9a51a958a686 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -22,6 +22,7 @@ CONFIG_BOARD_SIZE_LIMIT=715776 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-hobbit.dtb" +# CONFIG_CONSOLE_MUX is not set CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x10 diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index 546e1e6545d3..b5eedec82757 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -24,6 +24,7 @@ CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run distro_bootcmd" +# CONFIG_CONSOLE_MUX is not set CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x10 diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index f11e1f4ef413..02af6533e37a 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -22,6 +22,7 @@ CONFIG_BOARD_SIZE_LIMIT=715776 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="ask" +# CONFIG_CONSOLE_MUX is not set CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x10 diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 2cd906a63da0..8a99b813daee 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -22,6 +22,7 @@ CONFIG_BOARD_SIZE_LIMIT=715776 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb" +# CONFIG_CONSOLE_MUX is not set CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x10 diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 3e26aae40053..5b479818d88e 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -22,6 +22,7 @@ CONFIG_BOARD_SIZE_LIMIT=715776 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb" +# CONFIG_CONSOLE_MUX is not set CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x10 -- 2.34.1
[PATCH] pico-pi-imx7d: Unselect CONFIG_CONSOLE_MUX
From: Fabio Estevam Unselect CONFIG_CONSOLE_MUX to fix the following error for the input, output and error interfaces: U-Boot 2023.10 (Oct 03 2023 - 21:23:18 -0300) CPU: Freescale i.MX7D rev1.2 1000 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 42C Reset cause: POR Model: TechNexion PICO-IMX7D Board and PI baseboard Board: i.MX7D PICOSOM DRAM: 512 MiB Core: 75 devices, 16 uclasses, devicetree: separate PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11 MMC: FSL_SDHC: 3, FSL_SDHC: 1, FSL_SDHC: 0 Loading Environment from MMC... OK In:No input devices available! Out: No output devices available! Err: No error devices available! Net: eth0: ethernet@30be Hit any key to stop autoboot: 0 Signed-off-by: Fabio Estevam --- configs/pico-pi-imx7d_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 3e26aae40053..5b479818d88e 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -22,6 +22,7 @@ CONFIG_BOARD_SIZE_LIMIT=715776 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb" +# CONFIG_CONSOLE_MUX is not set CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x10 -- 2.34.1
Re: [PATCHv10 14/15] net/lwip: replace original net commands with lwip
On 2023-10-03 2:58 p.m., Peter Robinson wrote:
On Tue, Oct 3, 2023 at 6:58 PM Sean Edmond
wrote:
On 2023-09-26 2:41 a.m., Maxim Uvarov wrote:
Replace original commands: ping, tftp, dhcp and wget.
Signed-off-by: Maxim Uvarov
---
boot/bootmeth_efi.c | 18 +++---
boot/bootmeth_pxe.c | 21 ++-
cmd/net.c | 86 +
cmd/pxe.c | 19 +-
include/net.h | 8 +++--
include/net/ulwip.h | 64 +
6 files changed, 113 insertions(+), 103 deletions(-)
create mode 100644 include/net/ulwip.h
diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c
index ae936c8daa..52399d627c 100644
--- a/boot/bootmeth_efi.c
+++ b/boot/bootmeth_efi.c
@@ -20,6 +20,8 @@
#include
#include
#include
+#include
+#include
#include
#include
@@ -319,9 +321,7 @@ static int distro_efi_try_bootflow_files(struct udevice
*dev,
static int distro_efi_read_bootflow_net(struct bootflow *bflow)
{
- char file_addr[17], fname[256];
- char *tftp_argv[] = {"tftp", file_addr, fname, NULL};
- struct cmd_tbl cmdtp = {}; /* dummy */
+ char fname[256];
const char *addr_str, *fdt_addr_str;
int ret, arch, size;
ulong addr, fdt_addr;
@@ -368,7 +368,6 @@ static int distro_efi_read_bootflow_net(struct bootflow
*bflow)
if (!fdt_addr_str)
return log_msg_ret("fdt", -EINVAL);
fdt_addr = hextoul(fdt_addr_str, NULL);
- sprintf(file_addr, "%lx", fdt_addr);
/* We only allow the first prefix with PXE */
ret = distro_efi_get_fdt_name(fname, sizeof(fname), 0);
@@ -379,7 +378,16 @@ static int distro_efi_read_bootflow_net(struct bootflow
*bflow)
if (!bflow->fdt_fname)
return log_msg_ret("fil", -ENOMEM);
- if (!do_tftpb(, 0, 3, tftp_argv)) {
+ ret = ulwip_init();
+ if (ret)
+ return log_msg_ret("ulwip_init", ret);
+
+ ret = ulwip_tftp(fdt_addr, fname);
+ if (ret)
+ return log_msg_ret("ulwip_tftp", ret);
+
+ ret = ulwip_loop();
+ if (!ret) {
bflow->fdt_size = env_get_hex("filesize", 0);
bflow->fdt_addr = fdt_addr;
} else {
diff --git a/boot/bootmeth_pxe.c b/boot/bootmeth_pxe.c
index 8d489a11aa..fc6aabaa18 100644
--- a/boot/bootmeth_pxe.c
+++ b/boot/bootmeth_pxe.c
@@ -21,6 +21,8 @@
#include
#include
#include
+#include
+#include
#include
static int extlinux_pxe_getfile(struct pxe_context *ctx, const char
*file_path,
@@ -116,18 +118,21 @@ static int extlinux_pxe_read_file(struct udevice *dev,
struct bootflow *bflow,
const char *file_path, ulong addr,
ulong *sizep)
{
- char *tftp_argv[] = {"tftp", NULL, NULL, NULL};
- struct pxe_context *ctx = dev_get_priv(dev);
- char file_addr[17];
ulong size;
int ret;
- sprintf(file_addr, "%lx", addr);
- tftp_argv[1] = file_addr;
- tftp_argv[2] = (void *)file_path;
+ ret = ulwip_init();
+ if (ret)
+ return log_msg_ret("ulwip_init", ret);
+
+ ret = ulwip_tftp(addr, file_path);
+ if (ret)
+ return log_msg_ret("ulwip_tftp", ret);
+
+ ret = ulwip_loop();
+ if (ret)
+ return log_msg_ret("ulwip_loop", ret);
- if (do_tftpb(ctx->cmdtp, 0, 3, tftp_argv))
- return -ENOENT;
ret = pxe_get_file_size();
if (ret)
return log_msg_ret("tftp", ret);
diff --git a/cmd/net.c b/cmd/net.c
index d407d8320a..dc5a114309 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
static int netboot_common(enum proto_t, struct cmd_tbl *, int, char * const
[]);
@@ -40,19 +41,9 @@ U_BOOT_CMD(
#endif
#ifdef CONFIG_CMD_TFTPBOOT
-int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- int ret;
-
- bootstage_mark_name(BOOTSTAGE_KERNELREAD_START, "tftp_start");
- ret = netboot_common(TFTPGET, cmdtp, argc, argv);
- bootstage_mark_name(BOOTSTAGE_KERNELREAD_STOP, "tftp_done");
- return ret;
-}
-
#if IS_ENABLED(CONFIG_IPV6)
U_BOOT_CMD(
- tftpboot, 4, 1, do_tftpb,
+ tftpboot, 4, 1, do_lwip_tftp,
It looks like LWIP doesn't support TFTP with IPv6 addressing. Perhaps we need
to fall back onto the existing TFTP implementation until LWIP supports it?
Is it that LWIP upstream doesn't support IPv6 with TFTP or it just
hasn't been dealt with in this patch set? If the former might be
useful to reference details.
Apologies for the misleading comment, LWIP does support IPv6 addressing,
it just hasn't been dealt with in this patch.
Note, that currently, IPv6 TFTP is enabled using the "-ipv6" argument. The intention is that
netboot_common() sees the argument and sets the "use_ip6" variable. It looks like the new
implementation in do_lwip_tftp() doesn't re-use the argument parsing in netboot_common() and that it doesn't
handle the addition of the "-ipv6" flag.
Is there a reason why there's a need of an explicit argument for IPv6?
I would have thought if there was a local IPv6 address assigned that
you would automatically try IPv6 and if it fails for back to v4, or
even better do a DNS lookup and use what ever gets returned. Having to
know what to use by manually
Re: [PATCHv10 14/15] net/lwip: replace original net commands with lwip
On Tue, Oct 3, 2023 at 6:58 PM Sean Edmond
wrote:
>
>
> On 2023-09-26 2:41 a.m., Maxim Uvarov wrote:
>
> Replace original commands: ping, tftp, dhcp and wget.
>
> Signed-off-by: Maxim Uvarov
> ---
> boot/bootmeth_efi.c | 18 +++---
> boot/bootmeth_pxe.c | 21 ++-
> cmd/net.c | 86 +
> cmd/pxe.c | 19 +-
> include/net.h | 8 +++--
> include/net/ulwip.h | 64 +
> 6 files changed, 113 insertions(+), 103 deletions(-)
> create mode 100644 include/net/ulwip.h
>
> diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c
> index ae936c8daa..52399d627c 100644
> --- a/boot/bootmeth_efi.c
> +++ b/boot/bootmeth_efi.c
> @@ -20,6 +20,8 @@
> #include
> #include
> #include
> +#include
> +#include
> #include
> #include
>
> @@ -319,9 +321,7 @@ static int distro_efi_try_bootflow_files(struct udevice
> *dev,
>
> static int distro_efi_read_bootflow_net(struct bootflow *bflow)
> {
> - char file_addr[17], fname[256];
> - char *tftp_argv[] = {"tftp", file_addr, fname, NULL};
> - struct cmd_tbl cmdtp = {}; /* dummy */
> + char fname[256];
> const char *addr_str, *fdt_addr_str;
> int ret, arch, size;
> ulong addr, fdt_addr;
> @@ -368,7 +368,6 @@ static int distro_efi_read_bootflow_net(struct bootflow
> *bflow)
> if (!fdt_addr_str)
> return log_msg_ret("fdt", -EINVAL);
> fdt_addr = hextoul(fdt_addr_str, NULL);
> - sprintf(file_addr, "%lx", fdt_addr);
>
> /* We only allow the first prefix with PXE */
> ret = distro_efi_get_fdt_name(fname, sizeof(fname), 0);
> @@ -379,7 +378,16 @@ static int distro_efi_read_bootflow_net(struct bootflow
> *bflow)
> if (!bflow->fdt_fname)
> return log_msg_ret("fil", -ENOMEM);
>
> - if (!do_tftpb(, 0, 3, tftp_argv)) {
> + ret = ulwip_init();
> + if (ret)
> + return log_msg_ret("ulwip_init", ret);
> +
> + ret = ulwip_tftp(fdt_addr, fname);
> + if (ret)
> + return log_msg_ret("ulwip_tftp", ret);
> +
> + ret = ulwip_loop();
> + if (!ret) {
> bflow->fdt_size = env_get_hex("filesize", 0);
> bflow->fdt_addr = fdt_addr;
> } else {
> diff --git a/boot/bootmeth_pxe.c b/boot/bootmeth_pxe.c
> index 8d489a11aa..fc6aabaa18 100644
> --- a/boot/bootmeth_pxe.c
> +++ b/boot/bootmeth_pxe.c
> @@ -21,6 +21,8 @@
> #include
> #include
> #include
> +#include
> +#include
> #include
>
> static int extlinux_pxe_getfile(struct pxe_context *ctx, const char
> *file_path,
> @@ -116,18 +118,21 @@ static int extlinux_pxe_read_file(struct udevice *dev,
> struct bootflow *bflow,
>const char *file_path, ulong addr,
>ulong *sizep)
> {
> - char *tftp_argv[] = {"tftp", NULL, NULL, NULL};
> - struct pxe_context *ctx = dev_get_priv(dev);
> - char file_addr[17];
> ulong size;
> int ret;
>
> - sprintf(file_addr, "%lx", addr);
> - tftp_argv[1] = file_addr;
> - tftp_argv[2] = (void *)file_path;
> + ret = ulwip_init();
> + if (ret)
> + return log_msg_ret("ulwip_init", ret);
> +
> + ret = ulwip_tftp(addr, file_path);
> + if (ret)
> + return log_msg_ret("ulwip_tftp", ret);
> +
> + ret = ulwip_loop();
> + if (ret)
> + return log_msg_ret("ulwip_loop", ret);
>
> - if (do_tftpb(ctx->cmdtp, 0, 3, tftp_argv))
> - return -ENOENT;
> ret = pxe_get_file_size();
> if (ret)
> return log_msg_ret("tftp", ret);
> diff --git a/cmd/net.c b/cmd/net.c
> index d407d8320a..dc5a114309 100644
> --- a/cmd/net.c
> +++ b/cmd/net.c
> @@ -22,6 +22,7 @@
> #include
> #include
> #include
> +#include
>
> static int netboot_common(enum proto_t, struct cmd_tbl *, int, char * const
> []);
>
> @@ -40,19 +41,9 @@ U_BOOT_CMD(
> #endif
>
> #ifdef CONFIG_CMD_TFTPBOOT
> -int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
> -{
> - int ret;
> -
> - bootstage_mark_name(BOOTSTAGE_KERNELREAD_START, "tftp_start");
> - ret = netboot_common(TFTPGET, cmdtp, argc, argv);
> - bootstage_mark_name(BOOTSTAGE_KERNELREAD_STOP, "tftp_done");
> - return ret;
> -}
> -
> #if IS_ENABLED(CONFIG_IPV6)
> U_BOOT_CMD(
> - tftpboot, 4, 1, do_tftpb,
> + tftpboot, 4, 1, do_lwip_tftp,
>
> It looks like LWIP doesn't support TFTP with IPv6 addressing. Perhaps we
> need to fall back onto the existing TFTP implementation until LWIP supports
> it?
Is it that LWIP upstream doesn't support IPv6 with TFTP or it just
hasn't been dealt with in this patch set? If the former might be
useful to reference details.
> Note, that currently, IPv6 TFTP is enabled using the "-ipv6" argument. The
> intention is that netboot_common() sees the argument and sets the "use_ip6"
> variable. It looks like the new implementation in do_lwip_tftp() doesn't
> re-use the argument parsing in netboot_common() and that it doesn't handle
> the addition of the "-ipv6" flag.
Is there a reason why there's a need of an explicit argument for IPv6?
I would have thought if there was a local IPv6 address assigned that
you would automatically try IPv6 and if it fails for back to v4, or
even better do a DNS lookup and
[PATCH] arm: mach-imx: Makefile: Extend u-boot-nand.imx padding
From: Hiago De Franco Extend the padding process of u-boot-nand.imx target by adding 10k bytes of zeros to the end of the binary using the 'dd' command. The existing padding method did not generate a functional binary, as discussed in more detail in this thread [1]. Instead, we adopt the end-padding calculation method documented in 'board/doc/colibri_imx7.rst' as a reference, which is relevant for iMX7 with NAND storage. Adding 10k bytes of zeros provides an approximate value that makes the proper padding for these NAND devices. [1] https://lore.kernel.org/all/cac4tdfuqffqzrqfv5age_xtbfy1agr2sepn_fzedexhwjdr...@mail.gmail.com/ Signed-off-by: Hiago De Franco --- arch/arm/mach-imx/Makefile | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index aebfa6517b..6904cf3880 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -142,7 +142,9 @@ u-boot.imx: u-boot.bin u-boot.cfgout $(PLUGIN).bin FORCE $(call if_changed,mkimage) quiet_cmd_u-boot-nand_imx = GEN $@ -cmd_u-boot-nand_imx = (dd bs=1024 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@ +cmd_u-boot-nand_imx = (dd bs=1024 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@.zero-padded ; \ + (dd bs=10k count=1 if=/dev/zero 2>/dev/null) | cat $@.zero-padded - > $@ ; \ + rm -f $@.zero-padded u-boot-nand.imx: u-boot.imx FORCE $(call if_changed,u-boot-nand_imx) -- 2.40.1
[PATCH v1 2/2] ARM: amlogic: ad401: enable SPIFC
From: Igor Prusov Enable Amlogic A1 SPI FLash Controller support. Signed-off-by: Igor Prusov --- configs/ad401_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/ad401_defconfig b/configs/ad401_defconfig index 31752cc7f5..9a88e20a6a 100644 --- a/configs/ad401_defconfig +++ b/configs/ad401_defconfig @@ -51,4 +51,5 @@ CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_MESON_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_MESON_SPIFC_A1=y CONFIG_WDT=y -- 2.34.1
[PATCH v1 1/2] spi: add support for Amlogic A1 SPI Flash Controller
From: Igor Prusov Add A1 SPIFC driver from Linux. Slightly modified to use u-boot driver framework and accommodate to lack of ioread32_rep/iowrite32_rep. Based on Linux version 6.6-rc4 Signed-off-by: Igor Prusov Signed-off-by: Martin Kurbanov --- drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/meson_spifc_a1.c | 384 +++ 3 files changed, 393 insertions(+) create mode 100644 drivers/spi/meson_spifc_a1.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 854b8b88da..dedb366370 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -251,6 +251,14 @@ config MICROCHIP_COREQSPI Enable the QSPI driver for Microchip FPGA QSPI controllers. This driver can be used on Polarfire SoC. +config MESON_SPIFC_A1 + bool "Amlogic Meson A1 SPI Flash Controller driver" + depends on ARCH_MESON + help + Enable the Amlogic A1 SPI Flash Controller (SPIFC) driver. + This driver can be used to access the SPI NOR/NAND flash chips on + Amlogic A1 SoC. + config MPC8XX_SPI bool "MPC8XX SPI Driver" depends on MPC8xx diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index c27b3327c3..14bdb97f18 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o +obj-$(CONFIG_MESON_SPIFC_A1) += meson_spifc_a1.o obj-$(CONFIG_MICROCHIP_COREQSPI) += microchip_coreqspi.o obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o diff --git a/drivers/spi/meson_spifc_a1.c b/drivers/spi/meson_spifc_a1.c new file mode 100644 index 00..4b840c4634 --- /dev/null +++ b/drivers/spi/meson_spifc_a1.c @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for Amlogic A1 SPI flash controller (SPIFC) + * + * Copyright (c) 2023, SberDevices. All Rights Reserved. + * + * Author: Martin Kurbanov + * + * Ported to u-boot: + * Author: Igor Prusov + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SPIFC_A1_AHB_CTRL_REG 0x0 +#define SPIFC_A1_AHB_BUS_ENBIT(31) + +#define SPIFC_A1_USER_CTRL0_REG0x200 +#define SPIFC_A1_USER_REQUEST_ENABLE BIT(31) +#define SPIFC_A1_USER_REQUEST_FINISH BIT(30) +#define SPIFC_A1_USER_DATA_UPDATED BIT(0) + +#define SPIFC_A1_USER_CTRL1_REG0x204 +#define SPIFC_A1_USER_CMD_ENABLE BIT(30) +#define SPIFC_A1_USER_CMD_MODE GENMASK(29, 28) +#define SPIFC_A1_USER_CMD_CODE GENMASK(27, 20) +#define SPIFC_A1_USER_ADDR_ENABLE BIT(19) +#define SPIFC_A1_USER_ADDR_MODEGENMASK(18, 17) +#define SPIFC_A1_USER_ADDR_BYTES GENMASK(16, 15) +#define SPIFC_A1_USER_DOUT_ENABLE BIT(14) +#define SPIFC_A1_USER_DOUT_MODEGENMASK(11, 10) +#define SPIFC_A1_USER_DOUT_BYTES GENMASK(9, 0) + +#define SPIFC_A1_USER_CTRL2_REG0x208 +#define SPIFC_A1_USER_DUMMY_ENABLE BIT(31) +#define SPIFC_A1_USER_DUMMY_MODE GENMASK(30, 29) +#define SPIFC_A1_USER_DUMMY_CLK_SYCLES GENMASK(28, 23) + +#define SPIFC_A1_USER_CTRL3_REG0x20c +#define SPIFC_A1_USER_DIN_ENABLE BIT(31) +#define SPIFC_A1_USER_DIN_MODE GENMASK(28, 27) +#define SPIFC_A1_USER_DIN_BYTESGENMASK(25, 16) + +#define SPIFC_A1_USER_ADDR_REG 0x210 + +#define SPIFC_A1_AHB_REQ_CTRL_REG 0x214 +#define SPIFC_A1_AHB_REQ_ENABLEBIT(31) + +#define SPIFC_A1_ACTIMING0_REG (0x0088 << 2) +#define SPIFC_A1_TSLCH GENMASK(31, 30) +#define SPIFC_A1_TCLSH GENMASK(29, 28) +#define SPIFC_A1_TSHWL GENMASK(20, 16) +#define SPIFC_A1_TSHSL2GENMASK(15, 12) +#define SPIFC_A1_TSHSL1GENMASK(11, 8) +#define SPIFC_A1_TWHSL GENMASK(7, 0) + +#define SPIFC_A1_DBUF_CTRL_REG 0x240 +#define SPIFC_A1_DBUF_DIR BIT(31) +#define SPIFC_A1_DBUF_AUTO_UPDATE_ADDR BIT(30) +#define SPIFC_A1_DBUF_ADDR GENMASK(7, 0) + +#define SPIFC_A1_DBUF_DATA_REG 0x244 + +#define SPIFC_A1_USER_DBUF_ADDR_REG0x248 + +#define SPIFC_A1_BUFFER_SIZE 512U + +#define SPIFC_A1_MAX_HZ2 +#define SPIFC_A1_MIN_HZ100 + +#define SPIFC_A1_USER_CMD(op) ( \ + SPIFC_A1_USER_CMD_ENABLE | \ + FIELD_PREP(SPIFC_A1_USER_CMD_CODE, (op)->cmd.opcode) | \ + FIELD_PREP(SPIFC_A1_USER_CMD_MODE, ilog2((op)->cmd.buswidth))) + +#define SPIFC_A1_USER_ADDR(op) ( \ + SPIFC_A1_USER_ADDR_ENABLE | \ + FIELD_PREP(SPIFC_A1_USER_ADDR_MODE, ilog2((op)->addr.buswidth)) | \ + FIELD_PREP(SPIFC_A1_USER_ADDR_BYTES, (op)->addr.nbytes - 1)) + +#define
[PATCH v1 0/2] ARM: amlogic: Add A1 SPIFC support
A1 family boards have new version of SPIFC controller, that is incompatible with meson_spifc driver. This series ports A1 SPIFC driver from Linux and enables it for ad401 board. Igor Prusov (2): spi: add support for Amlogic A1 SPI Flash Controller ARM: amlogic: ad401: enable SPIFC configs/ad401_defconfig | 1 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/meson_spifc_a1.c | 384 +++ 4 files changed, 394 insertions(+) create mode 100644 drivers/spi/meson_spifc_a1.c -- 2.34.1
Re: [PATCH v5] board: rockchip: Add Bananapi R2Pro Board
Hi Frank, On 2023-09-20 20:40, Frank Wunderlich wrote: > From: Frank Wunderlich > > Add Bananapi R2 Pro board. > > tested: > - sdcard > - both front usb-ports > - sata > - wan-port > > lan-ports are connected to mt7531 switch where driver needs to be > separated from mtk ethernet-driver. > > Signed-off-by: Frank Wunderlich > --- > because iodomain is different to evb and now iodomain driver is sent as > patch we need to separate between EVB and R2Pro else board can be bricked. > > ethernet support depends on these series from jonas: > > rockchip: Port IO-domain driver for RK3568 from linux > https://patchwork.ozlabs.org/project/uboot/cover/20230821223020.3918620-1-jo...@kwiboo.se/ > and > rockchip: Add GMAC support for RK3568 and RK3588 > https://patchwork.ozlabs.org/project/uboot/cover/20230807000817.1701012-1-jo...@kwiboo.se/ > --- > v5: > - add line break in description > - reorder in makefile > - drop special dts-handling > (deletion of switchnode, disable of usb and gmac0) > - add MAINTAINERS entry > - changes to defconfig suggested by jonas > - remove "pinctrl-0 pinctrl-names" from CONFIG_OF_SPL_REMOVE_PROPS > - add CONFIG_SPL_DM_SEQ_ALIAS=y > - add CONFIG_SPL_PINCTRL=y > - remove CONFIG_USB_UHCI_HCD > - enable EFI_LOADER (defaults to y) > - drop CONFIG_SYSRESET_PSCI (reset works without) > > v4: > - add r2pro board to readme > - update r2pro dts to linux version > - remove switch node from linux dts > - disable gmac0 because switch driver does not work yet > to solve timeout error: > ethernet@fe2a Waiting for PHY auto negotiation to complete. > TIMEOUT! > phy_startup() failed: -110FAILED: -110ethernet@fe01 Waiting for PHY > auto nee > - cleanup r2pro u-boot.dtsi like jonas suggests > - update and reorder defconfig based on jonas suggestions > - dts: disable usb_host0_ohci because of error on usb-start > scanning bus usb@fd84 for devices... > ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) > or did > not provide a handshake (OUT) (5) > unable to get device descriptor (error=-1) > - pcie is not yet working, so not adding these options > rockchip_pcie3phy phy@fe8c: lock failed 0x689 > rockchip_pcie3phy phy@fe8c: PHY: Failed to init phy@fe8c: -110. > pcie_dw_rockchip pcie@fe27: failed to init phy (ret=-110) > rockchip_pcie3phy phy@fe8c: lock failed 0x689 > rockchip_pcie3phy phy@fe8c: PHY: Failed to init phy@fe8c: -110. > pcie_dw_rockchip pcie@fe28: failed to init phy (ret=-110) > - emmc not tested as it is empty on my board because it breaks sdcard boot > - rename dts and defconfig (add minus sign) > - enable efi_loader in defconfig > > v3: > - disable gmac0 as switch-driver is not yet ready to attach to the mac > > v2: > - drop switch-node for now as u-boot driver works differently to linux > --- > arch/arm/dts/Makefile | 1 + > arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi | 19 + > arch/arm/dts/rk3568-bpi-r2-pro.dts | 852 + > board/rockchip/evb_rk3568/MAINTAINERS | 7 + > configs/bpi-r2-pro-rk3568_defconfig| 94 +++ > doc/board/rockchip/rockchip.rst| 1 + > 6 files changed, 974 insertions(+) > create mode 100644 arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi > create mode 100644 arch/arm/dts/rk3568-bpi-r2-pro.dts > create mode 100644 configs/bpi-r2-pro-rk3568_defconfig > [...] > diff --git a/board/rockchip/evb_rk3568/MAINTAINERS > b/board/rockchip/evb_rk3568/MAINTAINERS > index cc9eb432a8b5..8c506162c01e 100644 > --- a/board/rockchip/evb_rk3568/MAINTAINERS > +++ b/board/rockchip/evb_rk3568/MAINTAINERS > @@ -7,6 +7,13 @@ F: configs/evb-rk3568_defconfig > F: arch/arm/dts/rk3568-evb-u-boot.dtsi > F: arch/arm/dts/rk3568-evb.dts > > +Banana Pi BPI-R2 Pro Maintainer entries are typically in upper case. get_maintainer.pl does not seem to mind, but use of uppercase seem to be the norm. > +M: Frank Wunderlich > +S: Maintained > +F: configs/bpi-r2-pro-rk3568_defconfig > +F: arch/arm/dts/rk3568-bpi-r2-pro.dts > +F: arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi > + > LUBANCAT-2 > M: Andy Yan > S: Maintained > diff --git a/configs/bpi-r2-pro-rk3568_defconfig > b/configs/bpi-r2-pro-rk3568_defconfig > new file mode 100644 > index ..5989eab569b8 > --- /dev/null > +++ b/configs/bpi-r2-pro-rk3568_defconfig > @@ -0,0 +1,94 @@ > +CONFIG_ARM=y > +CONFIG_SKIP_LOWLEVEL_INIT=y > +CONFIG_COUNTER_FREQUENCY=2400 > +CONFIG_ARCH_ROCKCHIP=y > +CONFIG_TEXT_BASE=0x00a0 > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > +CONFIG_NR_DRAM_BANKS=2 > +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y > +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0 > +CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2-pro" > +CONFIG_SYS_PROMPT="BPI-R2PRO> " Very few Rockchip boards use a custom prompt, is this needed? > +CONFIG_ROCKCHIP_RK3568=y > +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y >
[PATCH] arm: dts: k3-am625-beagleplay: Fix boot
From: Jan Kiszka
Since commit [1] A53 u-boot proper is broken. This is because nodes
marked as 'bootph-pre-ram' are not available at u-boot proper before
relocation.
To fix this we mark all nodes as 'bootph-all'.
[1] 9e644284ab812 ("dm: core: Report bootph-pre-ram/sram node as pre-reloc
after relocation")
Signed-off-by: Jan Kiszka
---
This may overshoot, but at least the board boots again. Could it be that
[1] broke even more boards?
arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi | 70 ++--
arch/arm/dts/k3-am625-r5-beagleplay.dts | 12 ++--
2 files changed, 41 insertions(+), 41 deletions(-)
diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
index f8c04e8a300..d6c6baa5518 100644
--- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
@@ -14,143 +14,143 @@
};
memory@8000 {
- bootph-pre-ram;
+ bootph-all;
};
/* Keep the LEDs on by default to indicate life */
leds {
- bootph-pre-ram;
+ bootph-all;
led-0 {
default-state = "on";
- bootph-pre-ram;
+ bootph-all;
};
led-1 {
default-state = "on";
- bootph-pre-ram;
+ bootph-all;
};
led-2 {
default-state = "on";
- bootph-pre-ram;
+ bootph-all;
};
led-3 {
default-state = "on";
- bootph-pre-ram;
+ bootph-all;
};
led-4 {
default-state = "on";
- bootph-pre-ram;
+ bootph-all;
};
};
};
_main {
- bootph-pre-ram;
+ bootph-all;
};
_timer0 {
clock-frequency = <2500>;
- bootph-pre-ram;
+ bootph-all;
};
{
- bootph-pre-ram;
+ bootph-all;
};
_proxy_main {
- bootph-pre-ram;
+ bootph-all;
};
{
- bootph-pre-ram;
+ bootph-all;
};
_pds {
- bootph-pre-ram;
+ bootph-all;
};
_clks {
- bootph-pre-ram;
+ bootph-all;
};
_reset {
- bootph-pre-ram;
+ bootph-all;
};
{
- bootph-pre-ram;
+ bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- bootph-pre-ram;
+ bootph-all;
};
};
_conf {
- bootph-pre-ram;
+ bootph-all;
};
{
- bootph-pre-ram;
+ bootph-all;
};
_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
_mcu {
- bootph-pre-ram;
+ bootph-all;
};
_wakeup {
- bootph-pre-ram;
+ bootph-all;
};
_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
_i2c0 {
- bootph-pre-ram;
+ bootph-all;
};
_i2c_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
_gpio0 {
- bootph-pre-ram;
+ bootph-all;
};
_gpio1 {
- bootph-pre-ram;
+ bootph-all;
};
{
/* EMMC */
- bootph-pre-ram;
+ bootph-all;
};
_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
_pins_default {
- bootph-pre-ram;
+ bootph-all;
/* Force to use SDCD card detect pin */
pinctrl-single,pins = <
AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
@@ -164,11 +164,11 @@
};
{
- bootph-pre-ram;
+ bootph-all;
};
{
- bootph-pre-ram;
+ bootph-all;
};
#ifdef CONFIG_TARGET_AM625_A53_EVM
diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts
b/arch/arm/dts/k3-am625-r5-beagleplay.dts
index 9c9d0570592..ac5461a32c0 100644
--- a/arch/arm/dts/k3-am625-r5-beagleplay.dts
+++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts
@@ -31,7 +31,7 @@
ti,sci = <>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
- bootph-pre-ram;
+ bootph-all;
};
dm_tifs: dm-tifs {
@@ -41,7 +41,7 @@
mbox-names = "rx", "tx";
mboxes= <_proxy_main 22>,
<_proxy_main 23>;
- bootph-pre-ram;
+ bootph-all;
};
};
@@ -55,11 +55,11 @@
};
_esm {
- bootph-pre-ram;
+ bootph-all;
};
_proxy_sa3 {
- bootph-pre-ram;
+ bootph-all;
/* We require this for boot handshake */
status = "okay";
};
@@ -69,12 +69,12 @@
compatible = "ti,am654-system-controller";
mboxes= <_proxy_main
Re: [PATCH 2/3] net: bootp: BOOTP/DHCPv4 retransmission improvements
On 2023-09-26 9:11 p.m., Lothar Waßmann wrote:
Hi,
On Mon, 25 Sep 2023 13:29:34 -0700 seanedm...@linux.microsoft.com wrote:
From: Sean Edmond
This patch introduces 3 improvements to align with RFC 951:
- retransmission backoff interval maximum is configurable
- initial retranmission backoff interval is configurable
- transaction ID is kept the same for each BOOTP/DHCPv4 request
In applications where thousands of nodes are serviced by a single DHCP
server, maximizing the retransmission backoff interval at 2 seconds (the
current u-boot default) exerts high pressure on the DHCP server and
network layer.
RFC 951 “7.2. Client Retransmission Strategy” states that the
retransmission backoff interval should maximize at 60 seconds. This
patch allows the interval to be configurable using the environment
variable "bootpretransmitperiodmax"
The initial retranmission backoff period defaults to 250ms, which is
also too small for these scenarios with many clients. This patch makes
the initial retransmission interval to be configurable using the
environment variable "bootpretransmitperiodinit".
Also, on a retransmission it is not expected for the transaction ID to
change (only the 'secs' field should be updated). Let's save the
transaction ID and use the same transaction ID for each BOOTP/DHCPv4
exchange.
Signed-off-by: Sean Edmond
---
net/bootp.c | 63 +++--
1 file changed, 47 insertions(+), 16 deletions(-)
diff --git a/net/bootp.c b/net/bootp.c
index 013d54c7ed..7248536cc4 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -42,6 +42,17 @@
*/
#define TIMEOUT_MS((3 + (CONFIG_NET_RETRY_COUNT * 5)) * 1000)
+/*
+ * According to rfc951 : 7.2. Client Retransmission Strategy
+ * "After the 'average' backoff reaches about 60 seconds, it should be
+ * increased no further, but still randomized."
+ *
+ * U-Boot has saturated this backoff at 2 seconds for a long time.
+ * To modify, set the environment variable "bootpretransmitperiodmax"
+ */
+#define RETRANSMIT_PERIOD_MAX_MS 2000
+#define RETRANSMIT_PERIOD_INIT_MS 250
+
#define PORT_BOOTPS 67 /* BOOTP server UDP port */
#define PORT_BOOTPC 68 /* BOOTP client UDP port */
@@ -56,6 +67,7 @@
u32 bootp_ids[CFG_BOOTP_ID_CACHE_SIZE];
unsigned int bootp_num_ids;
int bootp_try;
+u32bootp_id;
ulong bootp_start;
ulong bootp_timeout;
char net_nis_domain[32] = {0,}; /* Our NIS domain */
@@ -63,6 +75,7 @@ char net_hostname[32] = {0,}; /* Our hostname */
char net_root_path[CONFIG_BOOTP_MAX_ROOT_PATH_LEN] = {0,}; /* Our bootpath */
static ulong time_taken_max;
+static u32 retransmit_period_max_ms;
#if defined(CONFIG_CMD_DHCP)
static dhcp_state_t dhcp_state = INIT;
@@ -417,8 +430,8 @@ static void bootp_timeout_handler(void)
}
} else {
bootp_timeout *= 2;
- if (bootp_timeout > 2000)
- bootp_timeout = 2000;
+ if (bootp_timeout > retransmit_period_max_ms)
+ bootp_timeout = retransmit_period_max_ms;
net_set_timeout_handler(bootp_timeout, bootp_timeout_handler);
bootp_request();
}
@@ -714,10 +727,18 @@ static int bootp_extended(u8 *e)
void bootp_reset(void)
{
+ char *ep; /* Environment pointer */
+
bootp_num_ids = 0;
bootp_try = 0;
bootp_start = get_timer(0);
- bootp_timeout = 250;
+
+ ep = env_get("bootpretransmitperiodinit");
+ if (ep)
+ bootp_timeout = dectoul(ep, NULL);
+ else
+ bootp_timeout = RETRANSMIT_PERIOD_INIT_MS;
+
bootp_timeout = env_get_ulong("bootpretransmitperiodinit", 0,
RETRANSMIT_PERIOD_INIT_MS);
does the same...
Thanks for the suggestion, will fix in v2.
}
void bootp_request(void)
@@ -729,7 +750,6 @@ void bootp_request(void)
#ifdef CONFIG_BOOTP_RANDOM_DELAY
ulong rand_ms;
#endif
- u32 bootp_id;
struct in_addr zero_ip;
struct in_addr bcast_ip;
char *ep; /* Environment pointer */
@@ -745,6 +765,12 @@ void bootp_request(void)
else
time_taken_max = TIMEOUT_MS;
+ ep = env_get("bootpretransmitperiodmax");
+ if (ep)
+ retransmit_period_max_ms = dectoul(ep, NULL);
+ else
+ retransmit_period_max_ms = RETRANSMIT_PERIOD_MAX_MS;
+
see above
Lothar Waßmann
Re: [PATCH 0/3] BOOTP/DHCPv4 enhancements
On 2023-09-26 9:45 a.m., Peter Robinson wrote: Hi Sean, In our datacenter application, a single DHCP server is servicing 36000+ clients. Improvements are required to the DHCPv4 retransmission behavior to align with RFC and ensure less pressure is exerted on the server: - retransmission backoff interval maximum is configurable (environment variable bootpretransmitperiodmax) - initial retransmission backoff interval is configurable (environment variable bootpretransmitperiodinit) - transaction ID is kept the same for each BOOTP/DHCPv4 request (not recreated on each retry) Might be also worth looking at the series adding LWIP support [1] and see what impact that may have on this too. Peter [1]https://lists.denx.de/pipermail/u-boot/2023-September/531716.html I'm aware of the LWIP addition but haven't made any attempt to characterize the retransmission behavior. My understanding is that LWIP doesn't support DHCPv6 or TFTP with IPv6 yet. Our preference would be to stick with the u-boot networking stack for now until LWIP adds full support for IPv6. Given the importance of the retransmission behavior is for our use-case (36000+ clients pers server), we would have to qualify/validate LWIP before transitioning. For our application we'll use: - bootpretransmitperiodmax=16000 - bootpretransmitperiodinit=2000 A new configuration BOOTP_RANDOM_XID has been added to enable a randomized BOOTP/DHCPv4 transaction ID. Add functionality for DHCPv4 sending/parsing option 209 (PXE config file). Enabled with Kconfig BOOTP_PXE_DHCP_OPTION. Note, this patch was submitted previously but this latest version has been enhanced to avoid a possible double free(). Sean Edmond (3): net: Get pxe config file from dhcp option 209 net: bootp: BOOTP/DHCPv4 retransmission improvements net: bootp: add config option BOOTP_RANDOM_XID cmd/Kconfig | 11 +++ cmd/pxe.c | 10 +++ net/bootp.c | 85 +++-- 3 files changed, 91 insertions(+), 15 deletions(-) -- 2.40.0
Re: [PATCHv10 14/15] net/lwip: replace original net commands with lwip
On 2023-09-26 2:41 a.m., Maxim Uvarov wrote:
Replace original commands: ping, tftp, dhcp and wget.
Signed-off-by: Maxim Uvarov
---
boot/bootmeth_efi.c | 18 +++---
boot/bootmeth_pxe.c | 21 ++-
cmd/net.c | 86 +
cmd/pxe.c | 19 +-
include/net.h | 8 +++--
include/net/ulwip.h | 64 +
6 files changed, 113 insertions(+), 103 deletions(-)
create mode 100644 include/net/ulwip.h
diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c
index ae936c8daa..52399d627c 100644
--- a/boot/bootmeth_efi.c
+++ b/boot/bootmeth_efi.c
@@ -20,6 +20,8 @@
#include
#include
#include
+#include
+#include
#include
#include
@@ -319,9 +321,7 @@ static int distro_efi_try_bootflow_files(struct udevice *dev,
static int distro_efi_read_bootflow_net(struct bootflow *bflow)
{
- char file_addr[17], fname[256];
- char *tftp_argv[] = {"tftp", file_addr, fname, NULL};
- struct cmd_tbl cmdtp = {}; /* dummy */
+ char fname[256];
const char *addr_str, *fdt_addr_str;
int ret, arch, size;
ulong addr, fdt_addr;
@@ -368,7 +368,6 @@ static int distro_efi_read_bootflow_net(struct bootflow
*bflow)
if (!fdt_addr_str)
return log_msg_ret("fdt", -EINVAL);
fdt_addr = hextoul(fdt_addr_str, NULL);
- sprintf(file_addr, "%lx", fdt_addr);
/* We only allow the first prefix with PXE */
ret = distro_efi_get_fdt_name(fname, sizeof(fname), 0);
@@ -379,7 +378,16 @@ static int distro_efi_read_bootflow_net(struct bootflow
*bflow)
if (!bflow->fdt_fname)
return log_msg_ret("fil", -ENOMEM);
- if (!do_tftpb(, 0, 3, tftp_argv)) {
+ ret = ulwip_init();
+ if (ret)
+ return log_msg_ret("ulwip_init", ret);
+
+ ret = ulwip_tftp(fdt_addr, fname);
+ if (ret)
+ return log_msg_ret("ulwip_tftp", ret);
+
+ ret = ulwip_loop();
+ if (!ret) {
bflow->fdt_size = env_get_hex("filesize", 0);
bflow->fdt_addr = fdt_addr;
} else {
diff --git a/boot/bootmeth_pxe.c b/boot/bootmeth_pxe.c
index 8d489a11aa..fc6aabaa18 100644
--- a/boot/bootmeth_pxe.c
+++ b/boot/bootmeth_pxe.c
@@ -21,6 +21,8 @@
#include
#include
#include
+#include
+#include
#include
static int extlinux_pxe_getfile(struct pxe_context *ctx, const char *file_path,
@@ -116,18 +118,21 @@ static int extlinux_pxe_read_file(struct udevice *dev,
struct bootflow *bflow,
const char *file_path, ulong addr,
ulong *sizep)
{
- char *tftp_argv[] = {"tftp", NULL, NULL, NULL};
- struct pxe_context *ctx = dev_get_priv(dev);
- char file_addr[17];
ulong size;
int ret;
- sprintf(file_addr, "%lx", addr);
- tftp_argv[1] = file_addr;
- tftp_argv[2] = (void *)file_path;
+ ret = ulwip_init();
+ if (ret)
+ return log_msg_ret("ulwip_init", ret);
+
+ ret = ulwip_tftp(addr, file_path);
+ if (ret)
+ return log_msg_ret("ulwip_tftp", ret);
+
+ ret = ulwip_loop();
+ if (ret)
+ return log_msg_ret("ulwip_loop", ret);
- if (do_tftpb(ctx->cmdtp, 0, 3, tftp_argv))
- return -ENOENT;
ret = pxe_get_file_size();
if (ret)
return log_msg_ret("tftp", ret);
diff --git a/cmd/net.c b/cmd/net.c
index d407d8320a..dc5a114309 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
static int netboot_common(enum proto_t, struct cmd_tbl *, int, char * const []);
@@ -40,19 +41,9 @@ U_BOOT_CMD(
#endif
#ifdef CONFIG_CMD_TFTPBOOT
-int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- int ret;
-
- bootstage_mark_name(BOOTSTAGE_KERNELREAD_START, "tftp_start");
- ret = netboot_common(TFTPGET, cmdtp, argc, argv);
- bootstage_mark_name(BOOTSTAGE_KERNELREAD_STOP, "tftp_done");
- return ret;
-}
-
#if IS_ENABLED(CONFIG_IPV6)
U_BOOT_CMD(
- tftpboot, 4, 1, do_tftpb,
+ tftpboot, 4, 1, do_lwip_tftp,
It looks like LWIP doesn't support TFTP with IPv6 addressing. Perhaps
we need to fall back onto the existing TFTP implementation until LWIP
supports it?
Note, that currently, IPv6 TFTP is enabled using the "-ipv6" argument.
The intention is that netboot_common() sees the argument and sets the
"use_ip6" variable. It looks like the new implementation in
do_lwip_tftp() doesn't re-use the argument parsing in netboot_common()
and that it doesn't handle the addition of the "-ipv6" flag.
I support the addition of LWIP, but I'm concerned about how abrupt
changes like this one will be for existing users. The underlying stack
will change, with no easy way for the user to revert to
[PATCH v3] arm64: versal: Add SelectMAP boot mode identification
The SelectMAP configuration interface provides an 8-bit, 16-bit or
32-bit bidirectional data bus interface to the Versal FPGA
configuration logic that can be used for both configuration and
readback.
A connected microcontoller to the SelectMAP interface can load boot
image with bitstream, TF-A (ARM Trusted Firmware) and U-Boot.
This commit adds the missing identification of the SelectMAP mode.
Signed-off-by: Polak, Leszek
Reviewed-by: Stefan Roese
Cc: Michal Simek
Cc: Stefan Roese
---
v2:
- Drop assignment of 'mode' as selectmap is not be supported
by distro boot
v3:
- Changed E-Mail/Name to be the same as git setup
---
arch/arm/mach-versal-net/include/mach/hardware.h | 1 +
arch/arm/mach-versal/include/mach/hardware.h | 1 +
board/xilinx/versal-net/board.c | 3 +++
board/xilinx/versal/board.c | 4
4 files changed, 9 insertions(+)
diff --git a/arch/arm/mach-versal-net/include/mach/hardware.h
b/arch/arm/mach-versal-net/include/mach/hardware.h
index 9bddb8b007..767cdd3686 100644
--- a/arch/arm/mach-versal-net/include/mach/hardware.h
+++ b/arch/arm/mach-versal-net/include/mach/hardware.h
@@ -66,6 +66,7 @@ struct crp_regs {
#define EMMC_MODE 0x0006
#define USB_MODE0x0007
#define OSPI_MODE 0x0008
+#define SELECTMAP_MODE 0x000A
#define SD1_LSHFT_MODE 0x000E /* SD1 Level shifter */
#define JTAG_MODE 0x
#define BOOT_MODE_USE_ALT 0x100
diff --git a/arch/arm/mach-versal/include/mach/hardware.h
b/arch/arm/mach-versal/include/mach/hardware.h
index 000af974e8..9d1c2f0dcf 100644
--- a/arch/arm/mach-versal/include/mach/hardware.h
+++ b/arch/arm/mach-versal/include/mach/hardware.h
@@ -82,6 +82,7 @@ struct crp_regs {
#define EMMC_MODE 0x0006
#define USB_MODE0x0007
#define OSPI_MODE 0x0008
+#define SELECTMAP_MODE 0x000A
#define SD1_LSHFT_MODE 0x000E /* SD1 Level shifter */
#define JTAG_MODE 0x
#define BOOT_MODE_USE_ALT 0x100
diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c
index f0d2224b33..651b7d24d7 100644
--- a/board/xilinx/versal-net/board.c
+++ b/board/xilinx/versal-net/board.c
@@ -260,6 +260,9 @@ int board_late_init(void)
mode = "mmc";
bootseq = dev_seq(dev);
break;
+ case SELECTMAP_MODE:
+ puts("SELECTMAP_MODE\n");
+ break;
case SD_MODE:
puts("SD_MODE\n");
if (uclass_get_device_by_name(UCLASS_MMC,
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index 60bf37d3c9..26b4c7bf39 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -182,6 +182,9 @@ int board_late_init(void)
mode = "mmc";
bootseq = dev_seq(dev);
break;
+ case SELECTMAP_MODE:
+ puts("SELECTMAP_MODE\n");
+ break;
case SD_MODE:
puts("SD_MODE\n");
if (uclass_get_device_by_name(UCLASS_MMC,
@@ -298,6 +301,7 @@ enum env_location env_get_location(enum env_operation op,
int prio)
return ENVL_SPI_FLASH;
return ENVL_NOWHERE;
case JTAG_MODE:
+ case SELECTMAP_MODE:
default:
return ENVL_NOWHERE;
}
--
2.34.1
Re: [PATCH] board: rockchip: add Pine64 QuartzPro64 RK3588 board
Tom Fitzhenry writes: > QuartzPro64 is a Rockchip RK3588 based SBC by Pine64. > > UART and booting over SD card are tested to work. I've found a few issues with this patch, incl. confusion over the relationship between rk3588-quartzpro64.dts and rk3588-quartzpro64-u-boot.dtsi . I will rework this patch as a v2, and include eMMC support too.
Re: [PATCH RFC 10/10] board: ti: j721e: Enable ESM initialization for J7200
On Tue, Oct 03, 2023 at 07:57:04PM +0530, Kumar, Udit wrote:
>
> On 10/3/2023 1:40 PM, Keerthy wrote:
> > Enable ESM initialization for J7200
> >
> > Signed-off-by: Keerthy
> > ---
> > board/ti/j721e/evm.c | 6 --
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
> > index 42fa94b7a5..070b28326f 100644
> > --- a/board/ti/j721e/evm.c
> > +++ b/board/ti/j721e/evm.c
> > @@ -543,7 +543,8 @@ void spl_board_init(void)
> > }
> > #ifdef CONFIG_ESM_K3
> > - if (board_ti_k3_is("J721EX-PM2-SOM")) {
> > + if ((board_ti_k3_is("J721EX-PM2-SOM")) ||
> > + IS_ENABLED(CONFIG_TARGET_J7200_R5_EVM)) {
>
>
> Could we align on one kind of check, For J721E check is done against
> board-id, whereas for J7200 checking
We should look at figuring out how to split this file in two. One for
"generic J721E systems" and one for "TI EVMs", as I've mentioned in
other threads, so that it's easier for custom platforms to drop code
they don' require.
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH RFC 10/10] board: ti: j721e: Enable ESM initialization for J7200
On 10/3/2023 1:40 PM, Keerthy wrote:
Enable ESM initialization for J7200
Signed-off-by: Keerthy
---
board/ti/j721e/evm.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 42fa94b7a5..070b28326f 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -543,7 +543,8 @@ void spl_board_init(void)
}
#ifdef CONFIG_ESM_K3
- if (board_ti_k3_is("J721EX-PM2-SOM")) {
+ if ((board_ti_k3_is("J721EX-PM2-SOM")) ||
+ IS_ENABLED(CONFIG_TARGET_J7200_R5_EVM)) {
Could we align on one kind of check, For J721E check is done against
board-id, whereas for J7200 checking
for config option.
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(k3_esm), );
if (ret)
@@ -557,7 +558,8 @@ void spl_board_init(void)
#endif
#ifdef CONFIG_ESM_PMIC
- if (board_ti_k3_is("J721EX-PM2-SOM")) {
+ if ((board_ti_k3_is("J721EX-PM2-SOM")) ||
+ IS_ENABLED(CONFIG_TARGET_J7200_R5_EVM)) {
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(pmic_esm),
);
Re: [PATCH v4 3/4] power: regulator: Perform regulator setup inside uclass
On 2023-10-03 08:21, Svyatoslav Ryhel wrote:
> Regulators initial setup was previously dependent on board call.
> To move from this behaviour next solution is proposed: on post_bind
> boot-on/always-on properties are checked, all regulators with
> such props will be probed just after binding which ensures that
> essential regulators are set, then in the post probe regulator
> autoset is called so that correct regulator state according to
> device tree is reached.
>
> Signed-off-by: Svyatoslav Ryhel
> [jo...@kwiboo.se: use autoset func, only probe with always/boot-on prop]
> Signed-off-by: Jonas Karlman
> ---
> drivers/power/regulator/regulator-uclass.c | 30 ++
> 1 file changed, 25 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/power/regulator/regulator-uclass.c
> b/drivers/power/regulator/regulator-uclass.c
> index 4b2c6c2964..69d6d6428d 100644
> --- a/drivers/power/regulator/regulator-uclass.c
> +++ b/drivers/power/regulator/regulator-uclass.c
> @@ -473,6 +473,7 @@ static int regulator_post_bind(struct udevice *dev)
> {
> struct dm_regulator_uclass_plat *uc_pdata;
> const char *property = "regulator-name";
> + int ret;
>
> uc_pdata = dev_get_uclass_plat(dev);
>
> @@ -486,13 +487,20 @@ static int regulator_post_bind(struct udevice *dev)
> return -EINVAL;
> }
>
> - if (regulator_name_is_unique(dev, uc_pdata->name))
> - return 0;
> + ret = regulator_name_is_unique(dev, uc_pdata->name);
> + if (!ret) {
> + debug("'%s' of dev: '%s', has nonunique value: '%s'\n",
> + property, dev->name, uc_pdata->name);
> + return -EINVAL;
> + }
>
> - debug("'%s' of dev: '%s', has nonunique value: '%s\n",
> - property, dev->name, uc_pdata->name);
> + uc_pdata->always_on = dev_read_bool(dev, "regulator-always-on");
> + uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on");
>
> - return -EINVAL;
> + if (uc_pdata->always_on || uc_pdata->boot_on)
> + dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
> +
> + return 0;
> }
>
> static int regulator_pre_probe(struct udevice *dev)
> @@ -546,6 +554,17 @@ static int regulator_pre_probe(struct udevice *dev)
> return 0;
> }
>
> +static int regulator_post_probe(struct udevice *dev)
> +{
> + int ret;
> +
> + ret = regulator_autoset(dev);
> + if (ret == -EMEDIUMTYPE || ret == -ENOSYS)
Would be good to also check for || ret == -EALREADY here.
Following pending patch extend regulator_autoset to also return
-EALREADY when it has already been called for a regulator.
power: regulator: Only run autoset once for each regulator
https://patchwork.ozlabs.org/patch/1823770/
Regards,
Jonas
> + return 0;
> +
> + return ret;
> +}
> +
> int regulators_enable_boot_on(bool verbose)
> {
> struct udevice *dev;
> @@ -603,5 +622,6 @@ UCLASS_DRIVER(regulator) = {
> .name = "regulator",
> .post_bind = regulator_post_bind,
> .pre_probe = regulator_pre_probe,
> + .post_probe = regulator_post_probe,
> .per_device_plat_auto = sizeof(struct dm_regulator_uclass_plat),
> };
Re: [PATCH v4 1/4] power: regulator: expand basic reference counter onto all uclass
On 2023-10-03 08:21, Svyatoslav Ryhel wrote:
> Commit is based on 4fcba5d ("regulator: implement basic reference
> counter") but expands the idea to all regulators instead of just
> fixed/gpio regulators.
>
> Signed-off-by: Svyatoslav Ryhel
> Reviewed-by: Simon Glass
> ---
> drivers/power/regulator/regulator-uclass.c | 41 ++
> drivers/power/regulator/regulator_common.c | 22
> drivers/power/regulator/regulator_common.h | 21 ---
> include/power/regulator.h | 2 ++
> 4 files changed, 43 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/power/regulator/regulator-uclass.c
> b/drivers/power/regulator/regulator-uclass.c
> index d5a79d861c..4b2c6c2964 100644
> --- a/drivers/power/regulator/regulator-uclass.c
> +++ b/drivers/power/regulator/regulator-uclass.c
> @@ -159,6 +159,25 @@ int regulator_get_enable(struct udevice *dev)
> return ops->get_enable(dev);
> }
>
> +/*
> + * Enable or Disable a regulator
> + *
> + * This is a reentrant function and subsequent calls that enable will
> + * increase an internal counter, and disable calls will decrease the counter.
> + * The actual resource will be enabled when the counter gets to 1 coming
> from 0,
> + * and disabled when it reaches 0 coming from 1.
> + *
> + * @dev: regulator device
> + * @enable: bool indicating whether to enable or disable the regulator
> + * @return:
> + * 0 on Success
> + * -EBUSY if the regulator cannot be disabled because it's requested by
> + *another device
> + * -EALREADY if the regulator has already been enabled or has already been
> + *disabled
> + * -EACCES if there is no possibility to enable/disable the regulator
> + * -ve on different error situation
> + */
Maybe better to replace the existing comment for this function in
include/power/regulator.h ?
Regards,
Jonas
> int regulator_set_enable(struct udevice *dev, bool enable)
> {
> const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
> @@ -172,6 +191,23 @@ int regulator_set_enable(struct udevice *dev, bool
> enable)
> if (!enable && uc_pdata->always_on)
> return -EACCES;
>
> + /* If previously enabled, increase count */
> + if (enable && uc_pdata->enable_count > 0) {
> + uc_pdata->enable_count++;
> + return -EALREADY;
> + }
> +
> + if (!enable) {
> + if (uc_pdata->enable_count > 1) {
> + /* If enabled multiple times, decrease count */
> + uc_pdata->enable_count--;
> + return -EBUSY;
> + } else if (!uc_pdata->enable_count) {
> + /* If already disabled, do nothing */
> + return -EALREADY;
> + }
> + }
> +
> if (uc_pdata->ramp_delay)
> old_enable = regulator_get_enable(dev);
>
> @@ -187,6 +223,11 @@ int regulator_set_enable(struct udevice *dev, bool
> enable)
> }
> }
>
> + if (enable)
> + uc_pdata->enable_count++;
> + else
> + uc_pdata->enable_count--;
> +
> return ret;
> }
>
> diff --git a/drivers/power/regulator/regulator_common.c
> b/drivers/power/regulator/regulator_common.c
> index 0116fa01bb..62d06bf616 100644
> --- a/drivers/power/regulator/regulator_common.c
> +++ b/drivers/power/regulator/regulator_common.c
> @@ -74,23 +74,6 @@ int regulator_common_set_enable(const struct udevice *dev,
> return 0;
> }
>
> - /* If previously enabled, increase count */
> - if (enable && plat->enable_count > 0) {
> - plat->enable_count++;
> - return -EALREADY;
> - }
> -
> - if (!enable) {
> - if (plat->enable_count > 1) {
> - /* If enabled multiple times, decrease count */
> - plat->enable_count--;
> - return -EBUSY;
> - } else if (!plat->enable_count) {
> - /* If already disabled, do nothing */
> - return -EALREADY;
> - }
> - }
> -
> ret = dm_gpio_set_value(>gpio, enable);
> if (ret) {
> pr_err("Can't set regulator : %s gpio to: %d\n", dev->name,
> @@ -105,10 +88,5 @@ int regulator_common_set_enable(const struct udevice *dev,
> if (!enable && plat->off_on_delay_us)
> udelay(plat->off_on_delay_us);
>
> - if (enable)
> - plat->enable_count++;
> - else
> - plat->enable_count--;
> -
> return 0;
> }
> diff --git a/drivers/power/regulator/regulator_common.h
> b/drivers/power/regulator/regulator_common.h
> index d4962899d8..15f1fa4c93 100644
> --- a/drivers/power/regulator/regulator_common.h
> +++ b/drivers/power/regulator/regulator_common.h
> @@ -13,7 +13,6 @@ struct regulator_common_plat {
> struct gpio_desc gpio; /* GPIO for regulator enable control */
> unsigned int startup_delay_us;
> unsigned int
Re: [PATCH 16/16] board: rzg2l: Add RZ/G2L SMARC EVK board
On 9/20/23 14:42, Paul Barker wrote:
The Renesas RZ/G2L SMARC Evaluation Board Kit consists of the RZ/G2L
System-on-Module (SOM) based on the R9A07G044L2 SoC, and a common SMARC
carrier board.
The ARM TrustedFirmware code for the Renesas RZ/G2L SoC family passes a
devicetree blob to the bootloader as an argument in the same was
previous R-Car gen3/gen4 SoCs. This blob contains a compatible string
which can be used to identify the particular SoC we are running on and
this is used to select the appropriate device tree to load.
The configuration renesas_rzg2l_smarc_defconfig is added to support
building for this target. In the future this defconfig will be extended
to support other SoCs and evaluation boards from the RZ/G2L family.
Signed-off-by: Paul Barker
Reviewed-by: Biju Das
Reviewed-by: Lad Prabhakar
---
arch/arm/mach-rmobile/Kconfig.rzg2l | 14 +
board/renesas/rzg2l/Kconfig | 18 +++
board/renesas/rzg2l/MAINTAINERS | 6 +++
board/renesas/rzg2l/Makefile | 4 ++
board/renesas/rzg2l/rzg2l.c | 76 +++
configs/renesas_rzg2l_smarc_defconfig | 52 ++
include/configs/rzg2l-smarc.h | 14 +
7 files changed, 184 insertions(+)
create mode 100644 board/renesas/rzg2l/Kconfig
create mode 100644 board/renesas/rzg2l/MAINTAINERS
create mode 100644 board/renesas/rzg2l/Makefile
create mode 100644 board/renesas/rzg2l/rzg2l.c
create mode 100644 configs/renesas_rzg2l_smarc_defconfig
create mode 100644 include/configs/rzg2l-smarc.h
diff --git a/arch/arm/mach-rmobile/Kconfig.rzg2l
b/arch/arm/mach-rmobile/Kconfig.rzg2l
index 7d268e8c366a..1fe49e323300 100644
--- a/arch/arm/mach-rmobile/Kconfig.rzg2l
+++ b/arch/arm/mach-rmobile/Kconfig.rzg2l
@@ -9,6 +9,20 @@ config R9A07G044L
help
Enable support for the R9A07G044L SoC used in the RZ/G2L.
+choice
+ prompt "Renesas RZ/G2L Family Board selection"
+ default TARGET_RZG2L_SMARC_EVK
+
+config TARGET_RZG2L_SMARC_EVK
+ bool "Renesas RZ/G2L SMARC EVK"
+ imply R9A07G044L
+ help
+ Enable support for the RZ/G2L SMARC evaluation board.
+
+source "board/renesas/rzg2l/Kconfig"
+
+endchoice
+
config MULTI_DTB_FIT_UNCOMPRESS_SZ
default 0x8 if TARGET_RZG2L_SMARC_EVK
diff --git a/board/renesas/rzg2l/Kconfig b/board/renesas/rzg2l/Kconfig
new file mode 100644
index ..1335fc7ae806
--- /dev/null
+++ b/board/renesas/rzg2l/Kconfig
@@ -0,0 +1,18 @@
+# Copyright (C) 2023 Renesas Electronics Corporation
+# SPDX-License-Identifier: GPL-2.0+
+
+if TARGET_RZG2L_SMARC_EVK
+
+config SYS_SOC
+ default "rmobile"
+
+config SYS_BOARD
+ default "rzg2l"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "rzg2l-smarc"
+
+endif
diff --git a/board/renesas/rzg2l/MAINTAINERS b/board/renesas/rzg2l/MAINTAINERS
new file mode 100644
index ..0a51391c1fc9
--- /dev/null
+++ b/board/renesas/rzg2l/MAINTAINERS
@@ -0,0 +1,6 @@
+RENESAS RZG2L BOARD FAMILY
+M: Paul Barker
+S: Supported
+F: arch/arm/dts/rz-smarc-common.dtsi
I suspect there should be more files here, right ?
You likely want to be CCed on things like rzg2l clock, scif, and so on.
+N: rzg2l
+N: r9a07g044
diff --git a/board/renesas/rzg2l/Makefile b/board/renesas/rzg2l/Makefile
new file mode 100644
index ..466935fc8158
--- /dev/null
+++ b/board/renesas/rzg2l/Makefile
@@ -0,0 +1,4 @@
+# Copyright (C) 2023 Renesas Electronics Corporation
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := rzg2l.o
diff --git a/board/renesas/rzg2l/rzg2l.c b/board/renesas/rzg2l/rzg2l.c
new file mode 100644
index ..2b1bb3546c26
--- /dev/null
+++ b/board/renesas/rzg2l/rzg2l.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * RZ/G2L board support.
+ * Copyright (C) 2023 Renesas Electronics Corporation
+ */
+
+#include
+#include
+#include
+
+#if IS_ENABLED(CONFIG_MULTI_DTB_FIT)
+/* If the firmware passed a device tree, use it for board identification. */
+extern u64 rcar_atf_boot_args[];
+
+static bool is_rzg2l_board(const char *board_name)
+{
+ void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+
+ return fdt_node_check_compatible(atf_fdt_blob, 0, board_name) == 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+
+ if (fdt_magic(atf_fdt_blob) != FDT_MAGIC)
+ return -1;
+
+ if (is_rzg2l_board("renesas,r9a07g044l2"))
+ return strcmp(name, "r9a07g044l2-smarc");
+
+ return -1;
+}
+#endif
+
+static void apply_atf_overlay(void *fdt_blob)
+{
+ void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+
+ if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
+ fdt_overlay_apply_node(fdt_blob, 0, atf_fdt_blob, 0);
+}
+
+int fdtdec_board_setup(const void *fdt_blob)
+{
+ apply_atf_overlay((void *)fdt_blob);
+
+
Re: [PATCH 15/16] arm: dts: Import RZ/G2L SMARC EVK device tree
On 9/20/23 14:42, Paul Barker wrote: The Renesas RZ/G2L SMARC Evaluation Board Kit consists of the RZ/G2L System-on-Module (SOM) based on the R9A07G044L2 SoC, and a common SMARC carrier board. This patch is based on the corresponding Linux v6.5 device tree. Signed-off-by: Paul Barker Reviewed-by: Marek Vasut
Re: [PATCH 14/16] arm: rmobile: Support RZ/G2L memory map
On 9/20/23 14:42, Paul Barker wrote:
The memory map for the RZ/G2L family differs from that of previous R-Car
gen3/gen4 SoCs.
Gen3 / Gen4
A high level memory map can be seen in figure 5.2 (section 5.2.1) of the
RZ/G2L data sheet rev 1.30 published May 12, 2023. A summary is included
here (note that this is a 34-bit address space):
* 0x0__ - 0x0_0002_ SRAM area
* 0x0_0003_ - 0x0_0FFF_ Reserved area
* 0x0_1000_ - 0x0_1FFF_ I/O register area
* 0x0_2000_ - 0x0_2FFF_ SPI Multi area
* 0x0_3000_ - 0x0_3FFF_ Reserved area
* 0x0_4000_ - 0x1_3FFF_ DDR area (4 GiB)
* 0x1_4000_ - 0x3__ Reserved area
Within the DDR area, the first 128 MiB are reserved by TrustedFirmware.
Signed-off-by: Paul Barker
Reviewed-by: Biju Das
Reviewed-by: Lad Prabhakar
---
arch/arm/mach-rmobile/Makefile | 8 +-
arch/arm/mach-rmobile/memmap-rzg2l.c | 115 +++
2 files changed, 119 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/mach-rmobile/memmap-rzg2l.c
diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 45d6a0e2a28a..ff8b0c7bae25 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -10,11 +10,11 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
-obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o memmap-gen3.o
-obj-$(CONFIG_RCAR_GEN3) += cpu_info-rcar.o
-obj-$(CONFIG_RCAR_GEN4) += cpu_info-rcar.o
+obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o
+obj-$(CONFIG_RCAR_GEN3) += cpu_info-rcar.o memmap-gen3.o
+obj-$(CONFIG_RCAR_GEN4) += cpu_info-rcar.o memmap-gen3.o
obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o
-obj-$(CONFIG_RZG2L) += cpu_info-rzg2l.o
+obj-$(CONFIG_RZG2L) += cpu_info-rzg2l.o memmap-rzg2l.o
ifneq ($(CONFIG_R8A779A0),)
obj-$(CONFIG_ARMV8_PSCI) += psci-r8a779a0.o
diff --git a/arch/arm/mach-rmobile/memmap-rzg2l.c
b/arch/arm/mach-rmobile/memmap-rzg2l.c
new file mode 100644
index ..d0509424fb73
--- /dev/null
+++ b/arch/arm/mach-rmobile/memmap-rzg2l.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Renesas RZ/G2L family memory map tables
+ *
+ * Copyright (C) 2017 Marek Vasut
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ */
+
+#include
+#include
+#include
+#include
+
+#define RZG2L_NR_REGIONS 16
+
+/*
+ * RZ/G2L supports up to 4 GiB RAM starting at 0x4000, of
+ * which the first 128 MiB is reserved by TF-A.
+ */
Are those 4 GiB continuous , or is there some "low" mem alias and then
full "high" mem above the 32bit barrier ?
+static struct mm_region rzg2l_mem_map[RZG2L_NR_REGIONS] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x4000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x4000UL,
+ .phys = 0x4000UL,
+ .size = 0x03F0UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x47E0UL,
What's this part about ?
+ .phys = 0x47E0UL,
+ .size = 0xF820UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = rzg2l_mem_map;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define debug_memmap(i, map) \
+ debug("memmap %d: virt 0x%llx -> phys 0x%llx, size=0x%llx,
attrs=0x%llx\n", \
+ i, map[i].virt, map[i].phys, map[i].size, map[i].attrs)
+
+void enable_caches(void)
+{
+ unsigned int bank, i = 0;
+ u64 start, size;
+
+ /* Create map for register access */
+ rzg2l_mem_map[i].virt = 0x0ULL;
+ rzg2l_mem_map[i].phys = 0x0ULL;
+ rzg2l_mem_map[i].size = 0x4000ULL;
+ rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+ debug_memmap(i, rzg2l_mem_map);
+ i++;
+
+ /* Generate entries for DRAM in 32bit address space */
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start = gd->bd->bi_dram[bank].start;
+ size = gd->bd->bi_dram[bank].size;
+
+ /* Skip empty DRAM banks */
+ if (!size)
+ continue;
+
+ /* Mark memory reserved by ATF as cacheable too. */
+ if (start == 0x4800) {
+ /* Unmark protection area (0x43F0 to 0x47DF) */
+
Re: [PATCH 13/16] arm: rmobile: Add CPU detection for RZ/G2L
On 9/20/23 14:42, Paul Barker wrote: The ARM TrustedFirmware code for the Renesas RZ/G2L SoC family passes a devicetree blob to the bootloader as an argument in the same was same way (typo) previous R-Car gen3/gen4 SoCs. Gen3 / Gen4 This blob contains a compatible string which can be used to identify the particular SoC we are running on. Why not read the PRR ? [...]
Re: [PATCH 12/16] arm: rmobile: Include in header
On 9/20/23 14:42, Paul Barker wrote: We don't want to rely on source files including before . What kind of error does this solve ?
Re: [PATCH 11/16] mmc: renesas-sdhi: Initialize module on RZ/G2L
On 9/20/23 14:42, Paul Barker wrote:
On the Renesas RZ/G2L SoC family, we must ensure that the required clock
signals are enabled and the reset signal is de-asserted before we try to
communicate with the SDHI module.
Signed-off-by: Paul Barker
Reviewed-by: Biju Das
Reviewed-by: Lad Prabhakar
---
drivers/mmc/renesas-sdhi.c | 61 ++
1 file changed, 61 insertions(+)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 8e716f74491f..170c5dcc2ebe 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include "tmio-common.h"
@@ -964,6 +965,8 @@ static int renesas_sdhi_probe(struct udevice *dev)
u32 quirks = dev_get_driver_data(dev);
struct fdt_resource reg_res;
DECLARE_GLOBAL_DATA_PTR;
+ struct clk imclk2, aclk;
+ struct reset_ctl rst;
int ret;
priv->clk_get_rate = renesas_sdhi_clk_get_rate;
@@ -1012,6 +1015,49 @@ static int renesas_sdhi_probe(struct udevice *dev)
goto err_clkh;
}
+ if (IS_ENABLED(CONFIG_RZG2L)) {
+ /*
+* On members of the RZ/G2L SoC family, we need to enable
+* additional chip detect and bus clocks, then release the SDHI
+* module from reset.
+*/
This could use a separate function, and then, use bulk clock API via
clk_get_bulk() and co .
+ ret = clk_get_by_name(dev, "cd", );
+ if (ret < 0) {
+ dev_err(dev, "failed to get imclk2 (chip detect
clk)\n");
+ goto err_get_imclk2;
+ }
[...]
Re: [PATCH 10/16] serial: sh: Add RZ/G2L SCIF support
On 9/20/23 14:42, Paul Barker wrote:
Extend the existing driver to support the SCIF serial ports on the
Renesas RZ/G2L (R9A07G044) SoC. This also requires us to ensure that the
relevant reset signal is de-asserted before we try to talk to the SCIF
module.
Signed-off-by: Paul Barker
Reviewed-by: Biju Das
Reviewed-by: Lad Prabhakar
---
arch/arm/mach-rmobile/Kconfig | 1 +
drivers/serial/serial_sh.c| 32 ++--
drivers/serial/serial_sh.h| 19 ++-
3 files changed, 49 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 973e84fcf7ba..0ab22356aee5 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -77,6 +77,7 @@ config RZG2L
imply RENESAS_SDHI
imply CLK_RZG2L
imply PINCTRL_RZG2L
+ imply SCIF_CONSOLE
help
Enable support for the Renesas RZ/G2L family of SoCs, including the
the RZ/G2L itself (based on the R9A07G044 SoC).
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 5e543dbf3d58..a2e9a57137a6 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -17,6 +17,8 @@
#include
#include
#include
+#include
+#include
#include "serial_sh.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -79,8 +81,16 @@ sh_serial_setbrg_generic(struct uart_port *port, int clk,
int baudrate)
static void handle_error(struct uart_port *port)
{
- sci_in(port, SCxSR);
- sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
+ /* The RZ/G2L datasheet says that error conditions are cleared by
+* resetting the error bits in the FSR register to zero.
Can you be more specific here ?
It doesn't seem Linux sh-sci.c driver does anything special for G2L, so
is this special case really needed ?
+*/
+ if (IS_ENABLED(CONFIG_RZG2L)) {
+ unsigned short status = sci_in(port, SCxSR);
+ sci_out(port, SCxSR, status & ~SCIF_ERRORS);
+ } else {
+ sci_in(port, SCxSR);
+ sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
+ }
sci_in(port, SCLSR);
sci_out(port, SCLSR, 0x00);
}
@@ -193,6 +203,23 @@ static int sh_serial_probe(struct udevice *dev)
priv->type = plat->type;
priv->clk_mode = plat->clk_mode;
+ if (IS_ENABLED(CONFIG_RZG2L)) {
+ struct reset_ctl rst;
+ int ret;
+
+ ret = reset_get_by_index(dev, 0, );
+ if (ret < 0) {
+ dev_err(dev, "failed to get reset line\n");
+ return ret;
+ }
+
+ ret = reset_deassert();
+ if (ret < 0) {
+ dev_err(dev, "failed to de-assert reset line\n");
+ return ret;
+ }
+ }
devm_reset_control_get_optional() or something should do here too , right ?
Note that R-Car does have SCIF reset too, so this can be generic code.
Re: [PATCH 09/16] pinctrl: renesas: Add RZ/G2L PFC driver
On 9/20/23 14:42, Paul Barker wrote:
This driver provides pinctrl and gpio control for the Renesas RZ/G2L
(R9A07G044) SoC.
This patch is based on the corresponding Linux v6.5 driver.
Signed-off-by: Paul Barker
Reviewed-by: Biju Das
Reviewed-by: Lad Prabhakar
---
arch/arm/mach-rmobile/Kconfig | 1 +
drivers/pinctrl/renesas/Kconfig | 9 +
drivers/pinctrl/renesas/Makefile| 1 +
drivers/pinctrl/renesas/rzg2l-pfc.c | 906
4 files changed, 917 insertions(+)
create mode 100644 drivers/pinctrl/renesas/rzg2l-pfc.c
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 91f544c78337..973e84fcf7ba 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -76,6 +76,7 @@ config RZG2L
imply SYS_MALLOC_F
imply RENESAS_SDHI
imply CLK_RZG2L
+ imply PINCTRL_RZG2L
Keep the list sorted
[...]
Drop the parenthesis around values please, fix globally and in other
patches too.
+#define PWPR (0x3014)
+#define SD_CH(n) (0x3000 + (n) * 4)
+#define QSPI (0x3008)
+
+#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
+#define PVDD_3300 0 /* I/O domain voltage >= 3.3V */
+
+#define PWPR_B0WI BIT(7) /* Bit Write Disable */
+#define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */
+
+#define PM_MASK0x03
+#define PVDD_MASK 0x01
+#define PFC_MASK 0x07
+#define IEN_MASK 0x01
+#define IOLH_MASK 0x03
+
+#define PM_HIGH_Z 0x0
+#define PM_INPUT 0x1
+#define PM_OUTPUT 0x2
+#define PM_OUTPUT_IEN 0x3
+
+struct rzg2l_pfc_driver_data {
+ uint num_dedicated_pins;
+ uint num_ports;
+ const u32 *gpio_configs;
+};
+
+struct rzg2l_pfc_data {
+ void __iomem *base;
+ uint num_dedicated_pins;
+ uint num_ports;
+ uint num_pins;
+ const u32 *gpio_configs;
+ bool pfc_enabled;
+};
+
+struct rzg2l_dedicated_configs {
+ const char *name;
+ u32 config;
+};
+
+/*
+ * We need to ensure that the module clock is enabled and all resets are
+ * de-asserted before using either the gpio or pinctrl functionality. Error
+ * handling can be quite simple here as if the PFC cannot be enabled then we
+ * will not be able to progress with the boot anyway.
+ */
+static int rzg2l_pfc_enable(struct udevice *dev)
+{
+ struct rzg2l_pfc_data *data =
+ (struct rzg2l_pfc_data *)dev_get_driver_data(dev);
+ struct reset_ctl_bulk rsts;
+ struct clk clk;
+ int ret;
+
+ if (data->pfc_enabled)
When does this get triggered ?
+ return 0;
[...]
+static int rzg2l_gpio_set_value(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ struct rzg2l_pfc_data *data =
+ (struct rzg2l_pfc_data *)dev_get_driver_data(dev);
+ u32 port = RZG2L_PINMUX_TO_PORT(offset);
+ u8 pin = RZG2L_PINMUX_TO_PIN(offset);
A lot of this can also be const
+ rzg2l_gpio_set(data, port, pin, (bool)value);
+ return 0;
+}
+
+static void rzg2l_gpio_set_direction(struct rzg2l_pfc_data *data,
+u32 port, u8 pin, bool output)
+{
+ u16 reg16;
+
+ reg16 = readw(data->base + PM(port));
+ reg16 &= ~(PM_MASK << (pin * 2));
See clrsetbits_le32() function and co .
+ reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (pin * 2);
+ writew(reg16, data->base + PM(port));
+}
+
+static int rzg2l_gpio_direction_input(struct udevice *dev, unsigned int offset)
+{
+ struct rzg2l_pfc_data *data =
+ (struct rzg2l_pfc_data *)dev_get_driver_data(dev);
+ u32 port = RZG2L_PINMUX_TO_PORT(offset);
+ u8 pin = RZG2L_PINMUX_TO_PIN(offset);
+
+ rzg2l_gpio_set_direction(data, port, pin, false);
+ return 0;
+}
+
+static int rzg2l_gpio_direction_output(struct udevice *dev, unsigned int
offset,
+ int value)
+{
+ struct rzg2l_pfc_data *data =
+ (struct rzg2l_pfc_data *)dev_get_driver_data(dev);
+ u32 port = RZG2L_PINMUX_TO_PORT(offset);
+ u8 pin = RZG2L_PINMUX_TO_PIN(offset);
+
+ rzg2l_gpio_set(data, port, pin, (bool)value);
+ rzg2l_gpio_set_direction(data, port, pin, true);
+ return 0;
+}
+
+static int rzg2l_gpio_request(struct udevice *dev, unsigned int offset,
+ const char *label)
+{
+ struct rzg2l_pfc_data *data =
+ (struct rzg2l_pfc_data *)dev_get_driver_data(dev);
+ u32 port = RZG2L_PINMUX_TO_PORT(offset);
+ u8 pin = RZG2L_PINMUX_TO_PIN(offset);
+ u8 reg8;
+
+ if (!rzg2l_port_validate(data, port, pin)) {
+ dev_err(dev, "Invalid GPIO %u:%u\n", port, pin);
+ return -EINVAL;
+
Re: [PATCH 08/16] arm: rmobile: Restrict PINCTRL_PFC selection to R-Car gen3/gen4
On 9/20/23 14:42, Paul Barker wrote: The RZ/G2L family uses CONFIG_RCAR_64 but does not share a common PFC driver with the R-Car gen3 & gen4 boards. Signed-off-by: Paul Barker Reviewed-by: Biju Das Reviewed-by: Lad Prabhakar --- arch/arm/mach-rmobile/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index fc37f6c79e50..91f544c78337 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -9,7 +9,6 @@ config RCAR_64 select PHY select PINCONF select PINCTRL - select PINCTRL_PFC select POSITION_INDEPENDENT imply CMD_FS_UUID imply CMD_GPT @@ -29,6 +28,7 @@ config RCAR_GEN3 bool "Renesas ARM SoCs R-Car Gen3 (64bit)" select RCAR_64 select SUPPORT_SPL + select PINCTRL_PFC imply SPL imply SPL_BOARD_INIT imply SPL_GZIP @@ -43,6 +43,7 @@ config RCAR_GEN3 config RCAR_GEN4 bool "Renesas ARM SoCs R-Car Gen4 (64bit)" select RCAR_64 + select PINCTRL_PFC Reviewed-by: Marek Vasut
Re: [PATCH 07/16] clk: renesas: Add RZ/G2L CPG driver
On 9/20/23 14:42, Paul Barker wrote:
This driver provides clock and reset control for the Renesas RZ/G2L
(R9A07G044) SoC. It consists of two parts:
* driver code which is applicable to all SoCs in the RZ/G2L family
* static data describing the clocks and resets which are specific to the
R9A07G044 SoC.
clk_set_rate() and clk_get_rate() are implemented only for the clocks
that are actually used in u-boot.
The CPG driver is marked with DM_FLAG_PRE_RELOC to ensure that its bind
function is called before the SCIF (serial port) driver is probed. This
is required so that we can de-assert the relevant reset signal during
the serial driver probe function.
This patch is based on the corresponding Linux v6.5 driver.
Same thing as 02/16..04/16 applies here.
Signed-off-by: Paul Barker
Reviewed-by: Biju Das
Reviewed-by: Lad Prabhakar
---
arch/arm/mach-rmobile/Kconfig | 1 +
arch/arm/mach-rmobile/Kconfig.rzg2l | 1 +
drivers/clk/renesas/Kconfig | 9 +
drivers/clk/renesas/Makefile| 2 +
drivers/clk/renesas/r9a07g044-cpg.c | 384 +
drivers/clk/renesas/rzg2l-cpg.c | 502
drivers/clk/renesas/rzg2l-cpg.h | 318 ++
7 files changed, 1217 insertions(+)
create mode 100644 drivers/clk/renesas/r9a07g044-cpg.c
create mode 100644 drivers/clk/renesas/rzg2l-cpg.c
create mode 100644 drivers/clk/renesas/rzg2l-cpg.h
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index fd240832d83d..fc37f6c79e50 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -74,6 +74,7 @@ config RZG2L
imply MULTI_DTB_FIT_USER_DEFINED_AREA
imply SYS_MALLOC_F
imply RENESAS_SDHI
+ imply CLK_RZG2L
Keep the list sorted
help
Enable support for the Renesas RZ/G2L family of SoCs, including the
the RZ/G2L itself (based on the R9A07G044 SoC).
diff --git a/arch/arm/mach-rmobile/Kconfig.rzg2l
b/arch/arm/mach-rmobile/Kconfig.rzg2l
index 266f82c18085..7d268e8c366a 100644
--- a/arch/arm/mach-rmobile/Kconfig.rzg2l
+++ b/arch/arm/mach-rmobile/Kconfig.rzg2l
@@ -5,6 +5,7 @@ if RZG2L
config R9A07G044L
bool "Renesas R9A07G044L SoC"
+ imply CLK_R9A07G044
Why not CLK_R9A07G044L (with L at the end) ?
help
Enable support for the R9A07G044L SoC used in the RZ/G2L.
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 437a82cd48be..927d62cf99a3 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -156,3 +156,12 @@ config CLK_R9A06G032
depends on CLK_RENESAS
help
Enable this to support the clocks on Renesas R9A06G032 SoC.
+
+config CLK_RZG2L
+ bool "Renesas RZ/G2L family clock support"
+ depends on CLK_RENESAS
+ select DM_RESET
+
+config CLK_R9A07G044
+ bool "RZ/G2L (R9A07G044L) clock support"
+ depends on CLK_RZG2L
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 48373e61b901..df7e225e9ca4 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -23,3 +23,5 @@ obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
+obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o
+obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c
b/drivers/clk/renesas/r9a07g044-cpg.c
new file mode 100644
index ..e215db7caf15
--- /dev/null
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -0,0 +1,384 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G2L CPG driver
+ *
+ * Copyright (C) 2021-2023 Renesas Electronics Corp.
+ */
+
+#include
+#include
+#include
+#include
+
+#include "rzg2l-cpg.h"
+
+/* Divider tables */
+static const struct clk_div_table dtable_1_8[] = {
+ {0, 1},
+ {1, 2},
+ {2, 4},
+ {3, 8},
+ {0, 0},
+};
+
+static const struct clk_div_table dtable_1_32[] = {
+ {0, 1},
+ {1, 2},
+ {2, 4},
+ {3, 8},
+ {4, 32},
+ {0, 0},
+};
+
+static const struct clk_div_table dtable_16_128[] = {
+ {0, 16},
+ {1, 32},
+ {2, 64},
+ {3, 128},
+ {0, 0},
+};
+
+/* Mux clock tables */
+static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
+static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv",
".pll5_fout1ph0" };
+static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
Is this mixed tabs and spaces here ?
(please fix this in Linux too)
+static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
+static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
[...]
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
[...]
+static int rzg2l_cpg_clk_set(struct clk *clk, bool enable)
+{
+
Re: [PATCH 06/16] arm: rmobile: Add basic R9A07G044L SoC support
On 9/20/23 14:42, Paul Barker wrote: Add a config option for the R9A07G044L SoC used in the RZ/G2L so that we can make use of this in the subsequent driver patches. Signed-off-by: Paul Barker Reviewed-by: Biju Das Reviewed-by: Lad Prabhakar --- arch/arm/mach-rmobile/Kconfig.rzg2l | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-rmobile/Kconfig.rzg2l b/arch/arm/mach-rmobile/Kconfig.rzg2l index 37ff6cd34160..266f82c18085 100644 --- a/arch/arm/mach-rmobile/Kconfig.rzg2l +++ b/arch/arm/mach-rmobile/Kconfig.rzg2l @@ -3,6 +3,11 @@ if RZG2L +config R9A07G044L + bool "Renesas R9A07G044L SoC" + help + Enable support for the R9A07G044L SoC used in the RZ/G2L. I was under the impression that RZ/G2L is a SoC family, so the R9A07G044L is part of that SoC family ? Maybe just reword this paragraph and the commit message a bit to make it less confusing.
Re: [PATCH 05/16] arm: rmobile: Add basic RZ/G2L family support
On 9/20/23 14:42, Paul Barker wrote: The Renesas RZ/G2L family includes the following ARM SoCs: * RZ/G2L (r9a07g044l) * RZ/G2LC (r9a07g044c) * RZ/G2UL (r9a07g043u) * RZ/V2L (r9a07g054l) Support for individual SoCs and evaluation boards will be added in separate patches. Signed-off-by: Paul Barker Reviewed-by: Biju Das Reviewed-by: Lad Prabhakar --- arch/arm/mach-rmobile/Kconfig| 13 + arch/arm/mach-rmobile/Kconfig.rzg2l | 12 arch/arm/mach-rmobile/include/mach/rmobile.h | 2 ++ arch/arm/mach-rmobile/include/mach/rzg2l.h | 13 + 4 files changed, 40 insertions(+) create mode 100644 arch/arm/mach-rmobile/Kconfig.rzg2l create mode 100644 arch/arm/mach-rmobile/include/mach/rzg2l.h diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index 3061ccd34c8b..fd240832d83d 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -66,6 +66,18 @@ config RZN1 select SYSRESET_SYSCON imply CMD_DM +config RZG2L + prompt "Renesas RZ/G2L Family ARM SoCs" + select RCAR_64 + select GICV3 + imply MULTI_DTB_FIT + imply MULTI_DTB_FIT_USER_DEFINED_AREA + imply SYS_MALLOC_F + imply RENESAS_SDHI Keep the list sorted + help + Enable support for the Renesas RZ/G2L family of SoCs, including the + the RZ/G2L itself (based on the R9A07G044 SoC). Including the RZ/G2L itself ... and what else (you likely want to add answer to that into this paragraph) ? endchoice config SYS_SOC @@ -75,5 +87,6 @@ source "arch/arm/mach-rmobile/Kconfig.32" source "arch/arm/mach-rmobile/Kconfig.64" source "arch/arm/mach-rmobile/Kconfig.rza1" source "arch/arm/mach-rmobile/Kconfig.rzn1" +source "arch/arm/mach-rmobile/Kconfig.rzg2l" endif With that fixed: Reviewed-by: Marek Vasut
Re: [PATCH 04/16] dt-bindings: Add RZ/G2L IRQC bindings
On 9/20/23 14:42, Paul Barker wrote:
Import bindings for the Interrupt Controller (IRQC) module in the
Renesas RZ/G2L SoC family.
This patch is based on the dt-bindings in Linux v6.5.
Please also include the exact commit ID in the remote project when
importing files from it, see example in e.g.:
a7be3fb54a65 ("ARM: dts: renesas: Synchronize R-Car R8A77990 E3 DTs with
Linux 6.5.3")
With that fixed:
Reviewed-by: Marek Vasut
Re: [PATCH 03/16] dt-bindings: Add RZ/G2L PFC bindings
On 9/20/23 14:41, Paul Barker wrote:
Import bindings for the Port Function Control (PFC) module in the
Renesas RZ/G2L SoC family.
This patch is based on the dt-bindings in Linux v6.5.
Signed-off-by: Paul Barker
Reviewed-by: Biju Das
Reviewed-by: Lad Prabhakar
Please also include the exact commit ID in the remote project when
importing files from it, see example in e.g.:
a7be3fb54a65 ("ARM: dts: renesas: Synchronize R-Car R8A77990 E3 DTs with
Linux 6.5.3")
With that fixed:
Reviewed-by: Marek Vasut
Re: [PATCH 02/16] dt-bindings: Add RZ/G2L CPG bindings
On 9/20/23 14:41, Paul Barker wrote:
Import bindings for the Clock Pulse Generator (CPG) module in the
Renesas RZ/G2L SoC family.
This patch is based on the dt-bindings in Linux v6.5.
Please also include the exact commit ID in the remote project when
importing files from it, see example in e.g.:
a7be3fb54a65 ("ARM: dts: renesas: Synchronize R-Car R8A77990 E3 DTs with
Linux 6.5.3")
With that fixed:
Reviewed-by: Marek Vasut
Re: [PATCH 01/16] serial: sh: Fix compile error when lacking HSCIF support
On 9/20/23 14:41, Paul Barker wrote:
If we attempt to compile serial_sh.c for a system which lacks HSCIF
support (e.g. R8A7740), we see the following compilation error:
In file included from drivers/serial/serial_sh.c:20:
drivers/serial/serial_sh.c: In function ‘sh_serial_init_generic’:
drivers/serial/serial_sh.h:429:35: warning: implicit declaration of
function ‘sci_HSSRR_out’; did you mean ‘sci_SCSCR_out’?
[-Wimplicit-function-declaration]
429 | #define sci_out(port, reg, value) sci_##reg##_out(port, value)
| ^~~~
drivers/serial/serial_sh.c:62:17: note: in expansion of macro ‘sci_out’
62 | sci_out(port, HSSRR, HSSRR_SRE | HSSRR_SRCYC8);
| ^~~
To fix this, only try to support access to the HSSRR register for SoCs
where it actually exists.
Fixes: bbe36e29ca2c ('serial: sh: Add HSCIF support for R-Car SoC')
Signed-off-by: Paul Barker
Reviewed-by: Biju Das
Cc: Hai Pham
Cc: Marek Vasut
Cc: Simon Glass
---
drivers/serial/serial_sh.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 20cda5dbe272..5e543dbf3d58 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -58,8 +58,10 @@ static void sh_serial_init_generic(struct uart_port *port)
sci_out(port, SCSPTR, 0x0003);
#endif
+#if IS_ENABLED(CONFIG_RCAR_GEN2) || IS_ENABLED(CONFIG_RCAR_GEN3) || IS_ENABLED(CONFIG_RCAR_GEN4)
There should be CONFIG_RCAR_64 for GEN3+GEN4, please use it.
With that fixed:
Reviewed-by: Marek Vasut
Re: [PATCH] board: synquacer: set actual gd->ram_top and gd->ram_size
On Mon, 2 Oct 2023 at 21:31, Masahisa Kojima wrote:
>
> Current gd->ram_size and gd->ram_top reflect only the
> first DRAM bank even if the SynQuacer Developerbox could
> have up to three DRAM banks.
> With the commit 06d514d77c37 ("lmb: consider EFI memory map"),
> the first DRAM bank indicates <4GB address, so whole >4GB memory
> is marked as EFI_BOOT_SERVICES_DATA and it results that
> U-Boot can not access >4GB memory.
>
> Since 64-bits DRAM address is fully available on the SynQuacer
> Developerbox, let's set the installed DIMM information to
> gd->ram_top and gd->ram_size.
>
> Signed-off-by: Masahisa Kojima
Acked-by: Jassi Brar
Re: [PATCH v2 8/8] ad401: enable USB stack
On 03/10/2023 13:28, Alexey Romanov wrote: Currently we have all drivers for use USB stack on A1-series SoC's. Let's enable USB options for the Amlogic AD401 reference A1 SoC board. Signed-off-by: Alexey Romanov --- configs/ad401_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/ad401_defconfig b/configs/ad401_defconfig index 529e553bac..b02ff47b7a 100644 --- a/configs/ad401_defconfig +++ b/configs/ad401_defconfig @@ -51,4 +51,7 @@ CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_MESON_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_GADGET=y CONFIG_WDT=y Reviewed-by: Neil Armstrong
Re: [PATCH v2 6/8] a1: clk: Add missing USB_PHY_IN and USB_PHY gates
On 03/10/2023 13:28, Alexey Romanov wrote:
From: Igor Prusov
We use this clocks in dwc3 driver.
Signed-off-by: Igor Prusov
Signed-off-by: Alexey Romanov
---
drivers/clk/meson/a1.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c
index 3aec42f33b..1075ba7333 100644
--- a/drivers/clk/meson/a1.c
+++ b/drivers/clk/meson/a1.c
@@ -238,6 +238,12 @@ static const struct meson_clk_info *meson_clocks[] = {
[CLKID_FIXPLL_IN] = CLK_GATE("fixpll_in", A1_SYS_OSCIN_CTRL, 1,
EXTERNAL_XTAL
),
+ [CLKID_USB_PHY_IN] = CLK_GATE("usb_phy_in", A1_SYS_OSCIN_CTRL, 2,
+ EXTERNAL_XTAL
+ ),
+ [CLKID_USB_PHY] = CLK_GATE("usb_phy", A1_SYS_CLK_EN0, 27,
+ CLKID_SYS
+ ),
[CLKID_SARADC] = CLK_GATE("saradc", A1_SAR_ADC_CLK_CTR, 8,
-ENOENT
),
Reviewed-by: Neil Armstrong
Re: [PATCH v2 5/8] phy: support Amlogic A1 family
On 03/10/2023 13:28, Alexey Romanov wrote:
Setting G12A and A1 is similar, so we can use G12A phy
driver with little changes.
Signed-off-by: Alexey Romanov
---
drivers/phy/Kconfig | 2 +-
drivers/phy/meson-g12a-usb2.c | 79 ---
2 files changed, 66 insertions(+), 15 deletions(-)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index cf4d5908d7..60be62907d 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -190,7 +190,7 @@ config MESON_GXL_USB_PHY
config MESON_G12A_USB_PHY
bool "Amlogic Meson G12A USB PHYs"
- depends on PHY && ARCH_MESON && MESON_G12A
+ depends on PHY && ARCH_MESON && (MESON_G12A || MESON_A1)
imply REGMAP
help
This is the generic phy driver for the Amlogic Meson G12A
diff --git a/drivers/phy/meson-g12a-usb2.c b/drivers/phy/meson-g12a-usb2.c
index 7b028784a0..90053dbea3 100644
--- a/drivers/phy/meson-g12a-usb2.c
+++ b/drivers/phy/meson-g12a-usb2.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
@@ -146,18 +147,28 @@
#define RESET_COMPLETE_TIME 1000
#define PLL_RESET_COMPLETE_TIME 100
+enum meson_soc_id {
+ MESON_SOC_A1,
+ MESON_SOC_G12A,
+};
+
struct phy_meson_g12a_usb2_priv {
struct regmap *regmap;
#if CONFIG_IS_ENABLED(CLK)
struct clk clk;
#endif
struct reset_ctlreset;
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+ struct power_domain pwrdm;
+#endif
+ int soc_id;
};
static int phy_meson_g12a_usb2_init(struct phy *phy)
{
struct udevice *dev = phy->dev;
struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
+ u32 value;
int ret;
#if CONFIG_IS_ENABLED(CLK)
@@ -196,8 +207,7 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) |
FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9));
- regmap_write(priv->regmap, PHY_CTRL_R18,
- FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
+ value = FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) |
FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) |
FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) |
@@ -209,6 +219,11 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) |
PHY_CTRL_R18_MPLL_ACG_RANGE;
+ if (priv->soc_id == MESON_SOC_A1)
+ value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL;
+
+ regmap_write(priv->regmap, PHY_CTRL_R18, value);
+
udelay(PLL_RESET_COMPLETE_TIME);
/* UnReset PLL */
@@ -231,13 +246,19 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R20_USB2_BGR_VREF_4_0, 0) |
FIELD_PREP(PHY_CTRL_R20_USB2_BGR_DBG_1_0, 0));
- regmap_write(priv->regmap, PHY_CTRL_R4,
- FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
- FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
- FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
- PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
- FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
- FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
+ if (priv->soc_id == MESON_SOC_G12A)
+ regmap_write(priv->regmap, PHY_CTRL_R4,
+ FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
+ FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
+ FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
+ PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
+ FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
+ FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
+ else if (priv->soc_id == MESON_SOC_A1)
+ regmap_write(priv->regmap, PHY_CTRL_R21,
+ PHY_CTRL_R21_USB2_CAL_ACK_EN |
+ PHY_CTRL_R21_USB2_TX_STRG_PD |
+ FIELD_PREP(PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0, 2));
/* Tuning Disconnect Threshold */
regmap_write(priv->regmap, PHY_CTRL_R3,
@@ -246,10 +267,15 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R3_DISC_THRESH, 3));
/* Analog Settings */
- regmap_write(priv->regmap, PHY_CTRL_R14, 0);
- regmap_write(priv->regmap, PHY_CTRL_R13,
- PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
- FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
+ if (priv->soc_id == MESON_SOC_G12A) {
+ regmap_write(priv->regmap, PHY_CTRL_R14, 0);
+ regmap_write(priv->regmap, PHY_CTRL_R13,
+ PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
+ FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET,
[PATCH] test/py: net: Add a test for 'pxe get' command
Execute the 'pxe get' command to download a pxe configuration file from
the TFTP server and validate its interpretation.
Signed-off-by: Love Kumar
---
test/py/tests/test_net.py | 66 +++
1 file changed, 66 insertions(+)
diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py
index cd4b4dc53cbc..b2241ae6a482 100644
--- a/test/py/tests/test_net.py
+++ b/test/py/tests/test_net.py
@@ -6,6 +6,7 @@
import pytest
import u_boot_utils
+import uuid
"""
Note: This test relies on boardenv_* containing configuration values to define
@@ -61,6 +62,16 @@ env__net_nfs_readable_file = {
'crc32': 'c2244b26',
}
+# Details regarding a file that may be read from a TFTP server. This variable
+# may be omitted or set to None if PXE testing is not possible or desired.
+env__net_pxe_readable_file = {
+'fn': 'default',
+'addr': 0x200,
+'size': 74,
+'timeout': 5,
+'pattern': 'Linux',
+}
+
# True if a router advertisement service is connected to the network, and
should
# be tested. If router advertisement testing is not possible or desired, this
variable may be omitted or set to False.
@@ -260,3 +271,58 @@ def test_net_nfs(u_boot_console):
output = u_boot_console.run_command('crc32 %x $filesize' % addr)
assert expected_crc in output
+
+@pytest.mark.buildconfigspec("cmd_net")
+@pytest.mark.buildconfigspec("cmd_pxe")
+def test_net_pxe_get(u_boot_console):
+"""Test the pxe get command.
+
+A pxe configuration file is downloaded from the TFTP server and interpreted
+to boot the images mentioned in pxe configuration file.
+
+The details of the file to download are provided by the boardenv_* file;
+see the comment at the beginning of this file.
+"""
+
+if not net_set_up:
+pytest.skip("Network not initialized")
+
+test_net_setup_static(u_boot_console)
+
+f = u_boot_console.config.env.get("env__net_pxe_readable_file", None)
+if not f:
+pytest.skip("No PXE readable file to read")
+
+addr = f.get("addr", None)
+timeout = f.get("timeout", u_boot_console.p.timeout)
+
+pxeuuid = uuid.uuid1()
+u_boot_console.run_command(f"setenv pxeuuid {pxeuuid}")
+expected_text_uuid = f"Retrieving file: pxelinux.cfg/{pxeuuid}"
+
+ethaddr = u_boot_console.run_command("echo $ethaddr")
+ethaddr = ethaddr.replace(':', '-')
+expected_text_ethaddr = f"Retrieving file: pxelinux.cfg/01-{ethaddr}"
+
+ip = u_boot_console.run_command("echo $ipaddr")
+ip = ip.split('.')
+ipaddr_file = "".join(['%02x' % int(x) for x in ip]).upper()
+expected_text_ipaddr = f"Retrieving file: pxelinux.cfg/{ipaddr_file}"
+expected_text_default = f"Retrieving file: pxelinux.cfg/default"
+
+with u_boot_console.temporary_timeout(timeout):
+output = u_boot_console.run_command("pxe get")
+
+assert "TIMEOUT" not in output
+assert expected_text_uuid in output
+assert expected_text_ethaddr in output
+assert expected_text_ipaddr in output
+
+i = 1
+for i in range(0, len(ipaddr_file) - 1):
+expected_text_ip = f"Retrieving file: pxelinux.cfg/{ipaddr_file[:-i]}"
+assert expected_text_ip in output
+i += 1
+
+assert expected_text_default in output
+assert "Config file 'default.boot' found" in output
--
2.25.1
[PATCH] test/py: net: Add dhcp abort test
Abort the dhcp request in the middle by pressing ctrl + c on u-boot
prompt and validate the abort status.
Signed-off-by: Love Kumar
---
test/py/tests/test_net.py | 44 +++
1 file changed, 44 insertions(+)
diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py
index cd4b4dc53cbc..1e8eb0357eef 100644
--- a/test/py/tests/test_net.py
+++ b/test/py/tests/test_net.py
@@ -6,6 +6,7 @@
import pytest
import u_boot_utils
+import re
"""
Note: This test relies on boardenv_* containing configuration values to define
@@ -104,6 +105,49 @@ def test_net_dhcp(u_boot_console):
global net_set_up
net_set_up = True
+@pytest.mark.buildconfigspec("cmd_dhcp")
+def test_net_dhcp_abort(u_boot_console):
+"""Test the dhcp command by pressing ctrl+c in the middle of dhcp request
+
+The boardenv_* file may be used to enable/disable this test; see the
+comment at the beginning of this file.
+"""
+
+test_dhcp = u_boot_console.config.env.get("env__net_dhcp_server", False)
+if not test_dhcp:
+pytest.skip("No DHCP server available")
+
+u_boot_console.run_command("setenv autoload no")
+
+# Phy reset before running dhcp command
+output = u_boot_console.run_command("mii device")
+eth_num = re.search(r"Current device: '(.+?)'", output).groups()[0]
+u_boot_console.run_command(f"mii device {eth_num}")
+output = u_boot_console.run_command("mii info")
+eth_addr = hex(int(re.search(r"PHY (.+?):", output).groups()[0], 16))
+u_boot_console.run_command(f"mii modify {eth_addr} 0 0x8000 0x8000")
+
+u_boot_console.run_command("dhcp", wait_for_prompt=False)
+try:
+u_boot_console.wait_for("Waiting for PHY auto negotiation to complete")
+except:
+pytest.skip("Timeout waiting for PHY auto negotiation to complete")
+
+u_boot_console.wait_for("done")
+
+# Sending Ctrl-C
+output = u_boot_console.run_command(
+chr(3), wait_for_echo=False, send_nl=False
+)
+
+assert "TIMEOUT" not in output
+assert "DHCP client bound to address " not in output
+assert "Abort" in output
+
+# Provide a time to recover from Abort - if it is not performed
+# There is message like: ethernet@ff0e: No link.
+u_boot_console.run_command("sleep 1")
+
@pytest.mark.buildconfigspec('cmd_dhcp6')
def test_net_dhcp6(u_boot_console):
"""Test the dhcp6 command.
--
2.25.1
[PATCH v2 7/8] dwc3: add support for Amlogic A1 family
Now the driver supports also A1 phy layer.
Signed-off-by: Alexey Romanov
Reviewed-by: Neil Armstrong
---
drivers/usb/dwc3/dwc3-meson-g12a.c | 73 ++
1 file changed, 63 insertions(+), 10 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c
b/drivers/usb/dwc3/dwc3-meson-g12a.c
index 195670e4ca..5433ac0dca 100644
--- a/drivers/usb/dwc3/dwc3-meson-g12a.c
+++ b/drivers/usb/dwc3/dwc3-meson-g12a.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
/* USB2 Ports Control Registers */
@@ -102,10 +103,22 @@ enum {
PHY_COUNT,
};
-static const char *phy_names[PHY_COUNT] = {
+static const char *const dwc3_meson_g12a_phy_names[] = {
"usb2-phy0", "usb2-phy1", "usb3-phy0",
};
+static const char *const dwc3_meson_a1_phy_names[] = {
+ "usb2-phy0", "usb2-phy1"
+};
+
+struct dwc3_meson_g12a;
+
+struct dwc3_meson_g12a_drvdata {
+ const char *const *phy_names;
+ unsigned int phy_cnt;
+ int (*clk_init)(struct dwc3_meson_g12a *priv);
+};
+
struct dwc3_meson_g12a {
struct udevice *dev;
struct regmap *regmap;
@@ -119,6 +132,7 @@ struct dwc3_meson_g12a {
#if CONFIG_IS_ENABLED(DM_REGULATOR)
struct udevice *vbus_supply;
#endif
+ struct dwc3_meson_g12a_drvdata *drvdata;
};
#define U2P_REG_SIZE 0x20
@@ -293,10 +307,11 @@ int dwc3_meson_g12a_force_mode(struct udevice *dev, enum
usb_dr_mode mode)
static int dwc3_meson_g12a_get_phys(struct dwc3_meson_g12a *priv)
{
+ struct dwc3_meson_g12a_drvdata *data = priv->drvdata;
int i, ret;
- for (i = 0 ; i < PHY_COUNT ; ++i) {
- ret = generic_phy_get_by_name(priv->dev, phy_names[i],
+ for (i = 0 ; i < data->phy_cnt; ++i) {
+ ret = generic_phy_get_by_name(priv->dev, data->phy_names[i],
>phys[i]);
if (ret == -ENOENT || ret == -ENODATA)
continue;
@@ -354,18 +369,36 @@ static int dwc3_meson_g12a_clk_init(struct
dwc3_meson_g12a *priv)
return 0;
}
+static int dwc3_meson_a1_clk_init(struct dwc3_meson_g12a *priv)
+{
+ int ret;
+
+ ret = clk_get_by_name(priv->dev, "usb_bus", >clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(>clk);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static int dwc3_meson_g12a_probe(struct udevice *dev)
{
struct dwc3_meson_g12a *priv = dev_get_plat(dev);
+ struct dwc3_meson_g12a_drvdata *data =
+ (struct dwc3_meson_g12a_drvdata *)dev_get_driver_data(dev);
int ret, i;
+ priv->drvdata = data;
priv->dev = dev;
ret = regmap_init_mem(dev_ofnode(dev), >regmap);
if (ret)
return ret;
- ret = dwc3_meson_g12a_clk_init(priv);
+ ret = data->clk_init(priv);
if (ret)
return ret;
@@ -398,7 +431,7 @@ static int dwc3_meson_g12a_probe(struct udevice *dev)
if (ret)
return ret;
- for (i = 0 ; i < PHY_COUNT ; ++i) {
+ for (i = 0 ; i < data->phy_cnt; ++i) {
if (!priv->phys[i].dev)
continue;
@@ -407,7 +440,7 @@ static int dwc3_meson_g12a_probe(struct udevice *dev)
goto err_phy_init;
}
- for (i = 0; i < PHY_COUNT; ++i) {
+ for (i = 0; i < data->phy_cnt; ++i) {
if (!priv->phys[i].dev)
continue;
@@ -419,7 +452,7 @@ static int dwc3_meson_g12a_probe(struct udevice *dev)
return 0;
err_phy_init:
- for (i = 0 ; i < PHY_COUNT ; ++i) {
+ for (i = 0 ; i < data->phy_cnt ; ++i) {
if (!priv->phys[i].dev)
continue;
@@ -432,20 +465,21 @@ err_phy_init:
static int dwc3_meson_g12a_remove(struct udevice *dev)
{
struct dwc3_meson_g12a *priv = dev_get_plat(dev);
+ struct dwc3_meson_g12a_drvdata *data = priv->drvdata;
int i;
reset_release_all(>reset, 1);
clk_release_all(>clk, 1);
- for (i = 0; i < PHY_COUNT; ++i) {
+ for (i = 0; i < data->phy_cnt; ++i) {
if (!priv->phys[i].dev)
continue;
generic_phy_power_off(>phys[i]);
}
- for (i = 0 ; i < PHY_COUNT ; ++i) {
+ for (i = 0 ; i < data->phy_cnt; ++i) {
if (!priv->phys[i].dev)
continue;
@@ -461,11 +495,20 @@ static const struct dwc3_meson_g12a_drvdata
meson_g12a_drvdata = {
.clk_init = dwc3_meson_g12a_clk_init,
};
+static const struct dwc3_meson_g12a_drvdata meson_a1_drvdata = {
+ .phy_names = dwc3_meson_a1_phy_names,
+ .phy_cnt = ARRAY_SIZE(dwc3_meson_a1_phy_names),
+ .clk_init = dwc3_meson_a1_clk_init,
+};
+
static int dwc3_meson_g12a_child_pre_probe(struct udevice *dev)
{
if
[PATCH v2 6/8] a1: clk: Add missing USB_PHY_IN and USB_PHY gates
From: Igor Prusov
We use this clocks in dwc3 driver.
Signed-off-by: Igor Prusov
Signed-off-by: Alexey Romanov
---
drivers/clk/meson/a1.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c
index 3aec42f33b..1075ba7333 100644
--- a/drivers/clk/meson/a1.c
+++ b/drivers/clk/meson/a1.c
@@ -238,6 +238,12 @@ static const struct meson_clk_info *meson_clocks[] = {
[CLKID_FIXPLL_IN] = CLK_GATE("fixpll_in", A1_SYS_OSCIN_CTRL, 1,
EXTERNAL_XTAL
),
+ [CLKID_USB_PHY_IN] = CLK_GATE("usb_phy_in", A1_SYS_OSCIN_CTRL, 2,
+ EXTERNAL_XTAL
+ ),
+ [CLKID_USB_PHY] = CLK_GATE("usb_phy", A1_SYS_CLK_EN0, 27,
+ CLKID_SYS
+ ),
[CLKID_SARADC] = CLK_GATE("saradc", A1_SAR_ADC_CLK_CTR, 8,
-ENOENT
),
--
2.25.1
[PATCH v2 8/8] ad401: enable USB stack
Currently we have all drivers for use USB stack on A1-series SoC's. Let's enable USB options for the Amlogic AD401 reference A1 SoC board. Signed-off-by: Alexey Romanov --- configs/ad401_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/ad401_defconfig b/configs/ad401_defconfig index 529e553bac..b02ff47b7a 100644 --- a/configs/ad401_defconfig +++ b/configs/ad401_defconfig @@ -51,4 +51,7 @@ CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_MESON_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_GADGET=y CONFIG_WDT=y -- 2.25.1
[PATCH v2 4/8] phy: move clk enable/disable in init/exit
It is better to place clk_enable() in phy_meson_g12a_usb2_init()
and clk_disable() in phy_meson_g12a_usb2_exit().
For more detailed information, please see comments in the review of
a similar driver in the Linux Kernel:
https://lore.kernel.org/all/CAFBinCCEhobbyKHuKDWzTYCQWgNT1-e8=7hmhq1mvt6cueo...@mail.gmail.com/
Signed-off-by: Alexey Romanov
Reviewed-by: Neil Armstrong
---
drivers/phy/meson-g12a-usb2.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/phy/meson-g12a-usb2.c b/drivers/phy/meson-g12a-usb2.c
index 2e366b16ae..7b028784a0 100644
--- a/drivers/phy/meson-g12a-usb2.c
+++ b/drivers/phy/meson-g12a-usb2.c
@@ -160,6 +160,14 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
int ret;
+#if CONFIG_IS_ENABLED(CLK)
+ ret = clk_enable(>clk);
+ if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+ pr_err("failed to enable PHY clock\n");
+ return ret;
+ }
+#endif
+
ret = reset_assert(>reset);
udelay(1);
ret |= reset_deassert(>reset);
@@ -252,6 +260,10 @@ static int phy_meson_g12a_usb2_exit(struct phy *phy)
struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
int ret;
+#if CONFIG_IS_ENABLED(CLK)
+ clk_disable(>clk);
+#endif
+
ret = reset_assert(>reset);
if (ret)
return ret;
@@ -289,13 +301,6 @@ int meson_g12a_usb2_phy_probe(struct udevice *dev)
ret = clk_get_by_index(dev, 0, >clk);
if (ret < 0)
return ret;
-
- ret = clk_enable(>clk);
- if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
- pr_err("failed to enable PHY clock\n");
- clk_free(>clk);
- return ret;
- }
#endif
return 0;
--
2.25.1
[PATCH v2 5/8] phy: support Amlogic A1 family
Setting G12A and A1 is similar, so we can use G12A phy
driver with little changes.
Signed-off-by: Alexey Romanov
---
drivers/phy/Kconfig | 2 +-
drivers/phy/meson-g12a-usb2.c | 79 ---
2 files changed, 66 insertions(+), 15 deletions(-)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index cf4d5908d7..60be62907d 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -190,7 +190,7 @@ config MESON_GXL_USB_PHY
config MESON_G12A_USB_PHY
bool "Amlogic Meson G12A USB PHYs"
- depends on PHY && ARCH_MESON && MESON_G12A
+ depends on PHY && ARCH_MESON && (MESON_G12A || MESON_A1)
imply REGMAP
help
This is the generic phy driver for the Amlogic Meson G12A
diff --git a/drivers/phy/meson-g12a-usb2.c b/drivers/phy/meson-g12a-usb2.c
index 7b028784a0..90053dbea3 100644
--- a/drivers/phy/meson-g12a-usb2.c
+++ b/drivers/phy/meson-g12a-usb2.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
@@ -146,18 +147,28 @@
#define RESET_COMPLETE_TIME1000
#define PLL_RESET_COMPLETE_TIME100
+enum meson_soc_id {
+ MESON_SOC_A1,
+ MESON_SOC_G12A,
+};
+
struct phy_meson_g12a_usb2_priv {
struct regmap *regmap;
#if CONFIG_IS_ENABLED(CLK)
struct clk clk;
#endif
struct reset_ctlreset;
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+ struct power_domain pwrdm;
+#endif
+ int soc_id;
};
static int phy_meson_g12a_usb2_init(struct phy *phy)
{
struct udevice *dev = phy->dev;
struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
+ u32 value;
int ret;
#if CONFIG_IS_ENABLED(CLK)
@@ -196,8 +207,7 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) |
FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9));
- regmap_write(priv->regmap, PHY_CTRL_R18,
- FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
+ value = FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) |
FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) |
FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) |
@@ -209,6 +219,11 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) |
PHY_CTRL_R18_MPLL_ACG_RANGE;
+ if (priv->soc_id == MESON_SOC_A1)
+ value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL;
+
+ regmap_write(priv->regmap, PHY_CTRL_R18, value);
+
udelay(PLL_RESET_COMPLETE_TIME);
/* UnReset PLL */
@@ -231,13 +246,19 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R20_USB2_BGR_VREF_4_0, 0) |
FIELD_PREP(PHY_CTRL_R20_USB2_BGR_DBG_1_0, 0));
- regmap_write(priv->regmap, PHY_CTRL_R4,
- FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
- FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
- FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
- PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
- FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
- FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
+ if (priv->soc_id == MESON_SOC_G12A)
+ regmap_write(priv->regmap, PHY_CTRL_R4,
+ FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
+ FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
+ FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
+ PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
+ FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
+ FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
+ else if (priv->soc_id == MESON_SOC_A1)
+ regmap_write(priv->regmap, PHY_CTRL_R21,
+ PHY_CTRL_R21_USB2_CAL_ACK_EN |
+ PHY_CTRL_R21_USB2_TX_STRG_PD |
+ FIELD_PREP(PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0, 2));
/* Tuning Disconnect Threshold */
regmap_write(priv->regmap, PHY_CTRL_R3,
@@ -246,10 +267,15 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R3_DISC_THRESH, 3));
/* Analog Settings */
- regmap_write(priv->regmap, PHY_CTRL_R14, 0);
- regmap_write(priv->regmap, PHY_CTRL_R13,
- PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
- FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
+ if (priv->soc_id == MESON_SOC_G12A) {
+ regmap_write(priv->regmap, PHY_CTRL_R14, 0);
+ regmap_write(priv->regmap, PHY_CTRL_R13,
+ PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
+ FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
+ } else if (priv->soc_id ==
[PATCH v2 3/8] phy: get rid of raw hex values
It is better to use defines instead of write raw hex values in regmap. Signed-off-by: Alexey Romanov Reviewed-by: Neil Armstrong --- drivers/phy/meson-g12a-usb2.c | 161 -- 1 file changed, 153 insertions(+), 8 deletions(-) diff --git a/drivers/phy/meson-g12a-usb2.c b/drivers/phy/meson-g12a-usb2.c index 650b88bd18..2e366b16ae 100644 --- a/drivers/phy/meson-g12a-usb2.c +++ b/drivers/phy/meson-g12a-usb2.c @@ -23,12 +23,28 @@ #include #include +#include #define PHY_CTRL_R00x0 #define PHY_CTRL_R10x4 #define PHY_CTRL_R20x8 + #define PHY_CTRL_R30xc + #define PHY_CTRL_R3_SQUELCH_REF GENMASK(1, 0) + #define PHY_CTRL_R3_HSDIC_REF GENMASK(3, 2) + #define PHY_CTRL_R3_DISC_THRESH GENMASK(7, 4) + #define PHY_CTRL_R40x10 + #define PHY_CTRL_R4_CALIB_CODE_7_0 GENMASK(7, 0) + #define PHY_CTRL_R4_CALIB_CODE_15_8 GENMASK(15, 8) + #define PHY_CTRL_R4_CALIB_CODE_23_16GENMASK(23, 16) + #define PHY_CTRL_R4_I_C2L_CAL_ENBIT(24) + #define PHY_CTRL_R4_I_C2L_CAL_RESET_N BIT(25) + #define PHY_CTRL_R4_I_C2L_CAL_DONE BIT(26) + #define PHY_CTRL_R4_TEST_BYPASS_MODE_EN BIT(27) + #define PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0 GENMASK(29, 28) + #define PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2 GENMASK(31, 30) + #define PHY_CTRL_R50x14 #define PHY_CTRL_R60x18 #define PHY_CTRL_R70x1c @@ -37,15 +53,93 @@ #define PHY_CTRL_R10 0x28 #define PHY_CTRL_R11 0x2c #define PHY_CTRL_R12 0x30 + #define PHY_CTRL_R13 0x34 + #define PHY_CTRL_R13_CUSTOM_PATTERN_19 GENMASK(7, 0) + #define PHY_CTRL_R13_LOAD_STAT BIT(14) + #define PHY_CTRL_R13_UPDATE_PMA_SIGNALS BIT(15) + #define PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET GENMASK(20, 16) + #define PHY_CTRL_R13_CLEAR_HOLD_HS_DISCONNECT BIT(21) + #define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_VAL BIT(22) + #define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_EN BIT(23) + #define PHY_CTRL_R13_I_C2L_HS_ENBIT(24) + #define PHY_CTRL_R13_I_C2L_FS_ENBIT(25) + #define PHY_CTRL_R13_I_C2L_LS_ENBIT(26) + #define PHY_CTRL_R13_I_C2L_HS_OEBIT(27) + #define PHY_CTRL_R13_I_C2L_FS_OEBIT(28) + #define PHY_CTRL_R13_I_C2L_HS_RX_EN BIT(29) + #define PHY_CTRL_R13_I_C2L_FSLS_RX_EN BIT(30) + #define PHY_CTRL_R14 0x38 #define PHY_CTRL_R15 0x3c + #define PHY_CTRL_R16 0x40 + #define PHY_CTRL_R16_MPLL_M GENMASK(8, 0) + #define PHY_CTRL_R16_MPLL_N GENMASK(14, 10) + #define PHY_CTRL_R16_MPLL_TDC_MODE BIT(20) + #define PHY_CTRL_R16_MPLL_SDM_ENBIT(21) + #define PHY_CTRL_R16_MPLL_LOAD BIT(22) + #define PHY_CTRL_R16_MPLL_DCO_SDM_ENBIT(23) + #define PHY_CTRL_R16_MPLL_LOCK_LONG GENMASK(25, 24) + #define PHY_CTRL_R16_MPLL_LOCK_FBIT(26) + #define PHY_CTRL_R16_MPLL_FAST_LOCK BIT(27) + #define PHY_CTRL_R16_MPLL_ENBIT(28) + #define PHY_CTRL_R16_MPLL_RESET BIT(29) + #define PHY_CTRL_R16_MPLL_LOCK BIT(30) + #define PHY_CTRL_R16_MPLL_LOCK_DIG BIT(31) + #define PHY_CTRL_R17 0x44 + #define PHY_CTRL_R17_MPLL_FRAC_IN GENMASK(13, 0) + #define PHY_CTRL_R17_MPLL_FIX_ENBIT(16) + #define PHY_CTRL_R17_MPLL_LAMBDA1 GENMASK(19, 17) + #define PHY_CTRL_R17_MPLL_LAMBDA0 GENMASK(22, 20) + #define PHY_CTRL_R17_MPLL_FILTER_MODE BIT(23) + #define PHY_CTRL_R17_MPLL_FILTER_PVT2 GENMASK(27, 24) +
[PATCH v2 2/8] reset: add support for Amlogic A1 family
This patch adds reset support for the Amlogic A1 family.
We add the structure meson_reset_drvdata, which in the future
will allow this driver to be used for other families by declaring
only the correct parameters reg_count and level_offset.
Signed-off-by: Alexey Romanov
Reviewed-by: Neil Armstrong
---
drivers/reset/reset-meson.c | 42 +++--
1 file changed, 36 insertions(+), 6 deletions(-)
diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
index 64bc696f13..9d0c8b354f 100644
--- a/drivers/reset/reset-meson.c
+++ b/drivers/reset/reset-meson.c
@@ -13,18 +13,26 @@
#include
#include
#include
+#include
-#define REG_COUNT 8
#define BITS_PER_REG 32
-#define LEVEL_OFFSET 0x7c
+
+struct meson_reset_drvdata {
+ unsigned int reg_count;
+ unsigned int level_offset;
+};
struct meson_reset_priv {
struct regmap *regmap;
+ struct meson_reset_drvdata *drvdata;
};
static int meson_reset_request(struct reset_ctl *reset_ctl)
{
- if (reset_ctl->id > (REG_COUNT * BITS_PER_REG))
+ struct meson_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ struct meson_reset_drvdata *data = priv->drvdata;
+
+ if (reset_ctl->id > (data->reg_count * BITS_PER_REG))
return -EINVAL;
return 0;
@@ -33,9 +41,10 @@ static int meson_reset_request(struct reset_ctl *reset_ctl)
static int meson_reset_level(struct reset_ctl *reset_ctl, bool assert)
{
struct meson_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ struct meson_reset_drvdata *data = priv->drvdata;
uint bank = reset_ctl->id / BITS_PER_REG;
uint offset = reset_ctl->id % BITS_PER_REG;
- uint reg_offset = LEVEL_OFFSET + (bank << 2);
+ uint reg_offset = data->level_offset + (bank << 2);
uint val;
regmap_read(priv->regmap, reg_offset, );
@@ -64,15 +73,36 @@ struct reset_ops meson_reset_ops = {
.rst_deassert = meson_reset_deassert,
};
+static const struct meson_reset_drvdata meson_gxbb_data = {
+ .reg_count = 8,
+ .level_offset = 0x7c,
+};
+
+static const struct meson_reset_drvdata meson_a1_data = {
+ .reg_count = 3,
+ .level_offset = 0x40,
+};
+
static const struct udevice_id meson_reset_ids[] = {
- { .compatible = "amlogic,meson-gxbb-reset" },
- { .compatible = "amlogic,meson-axg-reset" },
+ {
+ .compatible = "amlogic,meson-gxbb-reset",
+ .data = (ulong)_gxbb_data,
+ },
+ {
+ .compatible = "amlogic,meson-axg-reset",
+ .data = (ulong)_gxbb_data,
+ },
+ {
+ .compatible = "amlogic,meson-a1-reset",
+ .data = (ulong)_a1_data,
+ },
{ }
};
static int meson_reset_probe(struct udevice *dev)
{
struct meson_reset_priv *priv = dev_get_priv(dev);
+ priv->drvdata = (struct meson_reset_drvdata *)dev_get_driver_data(dev);
return regmap_init_mem(dev_ofnode(dev), >regmap);
}
--
2.25.1
[PATCH v2 1/8] dt-bindings: reset: add Meson A1 reset bindings
Get this from Linux 6.6-rc3. Signed-off-by: Alexey Romanov Reviewed-by: Neil Armstrong --- .../reset/amlogic,meson-a1-reset.h| 76 +++ 1 file changed, 76 insertions(+) create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-reset.h diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h new file mode 100644 index 00..2c749c655e --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-a1-reset.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen + * + * Copyright (c) 2023, SberDevices, Inc. + * Author: Alexey Romanov + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H + +/* RESET0 */ +/* 0 */ +#define RESET_AM2AXI_VAD 1 +/* 2-3 */ +#define RESET_PSRAM4 +#define RESET_PAD_CTRL 5 +/* 6 */ +#define RESET_TEMP_SENSOR 7 +#define RESET_AM2AXI_DEV 8 +/* 9 */ +#define RESET_SPICC_A 10 +#define RESET_MSR_CLK 11 +#define RESET_AUDIO12 +#define RESET_ANALOG_CTRL 13 +#define RESET_SAR_ADC 14 +#define RESET_AUDIO_VAD15 +#define RESET_CEC 16 +#define RESET_PWM_EF 17 +#define RESET_PWM_CD 18 +#define RESET_PWM_AB 19 +/* 20 */ +#define RESET_IR_CTRL 21 +#define RESET_I2C_S_A 22 +/* 23 */ +#define RESET_I2C_M_D 24 +#define RESET_I2C_M_C 25 +#define RESET_I2C_M_B 26 +#define RESET_I2C_M_A 27 +#define RESET_I2C_PROD_AHB 28 +#define RESET_I2C_PROD 29 +/* 30-31 */ + +/* RESET1 */ +#define RESET_ACODEC 32 +#define RESET_DMA 33 +#define RESET_SD_EMMC_A34 +/* 35 */ +#define RESET_USBCTRL 36 +/* 37 */ +#define RESET_USBPHY 38 +/* 39-41 */ +#define RESET_RSA 42 +#define RESET_DMC 43 +/* 44 */ +#define RESET_IRQ_CTRL 45 +/* 46 */ +#define RESET_NIC_VAD 47 +#define RESET_NIC_AXI 48 +#define RESET_RAMA 49 +#define RESET_RAMB 50 +/* 51-52 */ +#define RESET_ROM 53 +#define RESET_SPIFC54 +#define RESET_GIC 55 +#define RESET_UART_C 56 +#define RESET_UART_B 57 +#define RESET_UART_A 58 +#define RESET_OSC_RING 59 +/* 60-63 */ + +/* RESET2 */ +/* 64-95 */ + +#endif -- 2.25.1
[PATCH v2 0/8] Support USB for Meson A1
Hello! This patchset adds USB stack support for Amlogic A1 SoC's series. Made reset / phy / dwc3 drivers more flexible and added support for A1 board. V2: - Made power domain for PHY optional. - Add missing CLKID_USB_PHY gate. - Drop patch with USB stack initialization in board-a1.c. Instead of, enable CONFIG_DM_USB_GADGET for AD401 board. - Support A1 in g12a_child_pre_probe/post_remove functions in dwc3 driver. Alexey Romanov (7): dt-bindings: reset: add Meson A1 reset bindings reset: add support for Amlogic A1 family phy: get rid of raw hex values phy: move clk enable/disable in init/exit phy: support Amlogic A1 family dwc3: add support for Amlogic A1 family ad401: enable USB stack Igor Prusov (1): a1: clk: Add missing USB_PHY_IN and USB_PHY gates configs/ad401_defconfig | 3 + drivers/clk/meson/a1.c| 6 + drivers/phy/Kconfig | 2 +- drivers/phy/meson-g12a-usb2.c | 235 -- drivers/reset/reset-meson.c | 42 +++- drivers/usb/dwc3/dwc3-meson-g12a.c| 73 +- .../reset/amlogic,meson-a1-reset.h| 76 ++ 7 files changed, 403 insertions(+), 34 deletions(-) create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-reset.h -- 2.25.1
[PATCH v1 1/1] board: xen: introduce virtio-blk support
Added new xenguest_arm64_virtio_defconfig which
enables support for virtio-blk using various types
of transport like virtio-pci, vrtio-mmio. Currently
supported: up to 2 PCI host bridges and 10 MMIO devices.
Note: DT parsing code was partly taken from pci-uclass.c
Limitation: All memory regions should be
below 4GB address space.
Signed-off-by: Andrii Chepurnyi
---
board/xen/xenguest_arm64/xenguest_arm64.c | 108 +-
configs/xenguest_arm64_virtio_defconfig | 63 +
doc/board/xen/xenguest_arm64.rst | 2 +
include/configs/xenguest_arm64.h | 10 +-
4 files changed, 180 insertions(+), 3 deletions(-)
create mode 100644 configs/xenguest_arm64_virtio_defconfig
diff --git a/board/xen/xenguest_arm64/xenguest_arm64.c
b/board/xen/xenguest_arm64/xenguest_arm64.c
index 6e10bba76b..244070a242 100644
--- a/board/xen/xenguest_arm64/xenguest_arm64.c
+++ b/board/xen/xenguest_arm64/xenguest_arm64.c
@@ -8,12 +8,15 @@
*/
#include
+#include
#include
#include
#include
#include
#include
#include
+#include
+#include
#include
#include
@@ -49,7 +52,14 @@ void *board_fdt_blob_setup(int *err)
return (void *)rom_pointer[0];
}
-#define MAX_MEM_MAP_REGIONS 5
+/*
+ * MAX_MEM_MAP_REGIONS should respect to:
+ * 3 Xen related regions
+ * 6 regions for 2 PCI Host bridges
+ * 10 regions for MMIO devices
+ * 2 memory regions
+ */
+#define MAX_MEM_MAP_REGIONS 22
static struct mm_region xen_mem_map[MAX_MEM_MAP_REGIONS];
struct mm_region *mem_map = xen_mem_map;
@@ -63,6 +73,93 @@ static int get_next_memory_node(const void *blob, int mem)
return mem;
}
+#ifdef CONFIG_VIRTIO_BLK
+#ifdef CONFIG_VIRTIO_PCI
+static void add_pci_mem_map(const void *blob, int *cnt)
+{
+ struct fdt_resource reg_res;
+ int node = -1, len = 0, cells_per_record = 0, max_regions = 0;
+ int pci_addr_cells = 0, addr_cells = 0, size_cells = 0;
+
+ while ((node = fdt_node_offset_by_prop_value(blob, node, "compatible",
+"pci-host-ecam-generic",
+
sizeof("pci-host-ecam-generic"))) >= 0) {
+ if ((*cnt) >= MAX_MEM_MAP_REGIONS ||
+ fdt_get_resource(blob, node, "reg", 0, _res) < 0)
+ return;
+
+ xen_mem_map[*cnt].virt = reg_res.start;
+ xen_mem_map[*cnt].phys = reg_res.start;
+ xen_mem_map[*cnt].size = fdt_resource_size(_res);
+ xen_mem_map[*cnt].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+
PTE_BLOCK_INNER_SHARE);
+ (*cnt)++;
+
+ const u32 *prop = fdt_getprop(blob, node, "ranges", );
+
+ if (!prop)
+ return;
+
+ pci_addr_cells = fdt_address_cells(blob, node);
+ addr_cells = fdt_address_cells(blob, 0);
+ size_cells = fdt_size_cells(blob, node);
+
+ /* PCI addresses are always 3-cells */
+ len /= sizeof(u32);
+ cells_per_record = pci_addr_cells + addr_cells + size_cells;
+ max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS;
+
+ for (int i = 0; i < max_regions; i++, len -= cells_per_record) {
+ u64 pci_addr, addr, size;
+ int space_code;
+ u32 flags;
+
+ if (((*cnt) >= MAX_MEM_MAP_REGIONS) || len <
cells_per_record)
+ return;
+
+ flags = fdt32_to_cpu(prop[0]);
+ space_code = (flags >> 24) & 3;
+ pci_addr = fdtdec_get_number(prop + 1, 2);
+ prop += pci_addr_cells;
+ addr = fdtdec_get_number(prop, addr_cells);
+ prop += addr_cells;
+ size = fdtdec_get_number(prop, size_cells);
+ prop += size_cells;
+
+ xen_mem_map[*cnt].virt = addr;
+ xen_mem_map[*cnt].phys = addr;
+ xen_mem_map[*cnt].size = size;
+ xen_mem_map[*cnt].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL)
|
+ PTE_BLOCK_INNER_SHARE);
+ (*cnt)++;
+ }
+ }
+}
+#endif
+
+#ifdef CONFIG_VIRTIO_MMIO
+static void add_mmio_mem_map(const void *blob, int *cnt)
+{
+ int node = -1;
+ struct fdt_resource reg_res;
+
+ if ((*cnt) >= MAX_MEM_MAP_REGIONS)
+ return;
+ while ((node = fdt_node_offset_by_prop_value(blob, node, "compatible",
"virtio,mmio",
+sizeof("virtio,mmio"))) >=
0) {
+ if (fdt_get_resource(blob, node, "reg", 0, _res) < 0)
+ return;
+
[PATCH v1 0/1] virtio-blk support for xen board
Hello. This patch adds the ability to use virtio-blk in the guest domain under Xen hypervisor. To do such you need to build U-boot with xenguest_arm64_virtio_defconfig. The patch was tested on a specific build for rcar-gen3 hardware, with multiple Linux domains running under Xen and QEMU as a block backend. Andrii Chepurnyi (1): board: xen: introduce virtio-blk support board/xen/xenguest_arm64/xenguest_arm64.c | 108 +- configs/xenguest_arm64_virtio_defconfig | 63 + doc/board/xen/xenguest_arm64.rst | 2 + include/configs/xenguest_arm64.h | 10 +- 4 files changed, 180 insertions(+), 3 deletions(-) create mode 100644 configs/xenguest_arm64_virtio_defconfig -- 2.25.1
RE: [PATCH] timer: starfive: Add Starfive timer support
Can anyone help review this patch please?
> -Original Message-
> From: KuanLim.Lee
> Sent: Tuesday, September 19, 2023 3:31 PM
> To: u-boot@lists.denx.de
> Cc: WeiLiang Lim ; KuanLim.Lee
>
> Subject: [PATCH] timer: starfive: Add Starfive timer support
>
> Add timer driver in Starfive SoC. It is an timer that outside of CPU core and
> inside Starfive SoC.
>
> Signed-off-by: Kuan Lim Lee
> Reviewed-by: Wei Liang Lim
> ---
> drivers/timer/Kconfig | 7 +++
> drivers/timer/Makefile | 1 +
> drivers/timer/starfive-timer.c | 94
> ++
> 3 files changed, 102 insertions(+)
> create mode 100644 drivers/timer/starfive-timer.c
>
> diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index
> 915b2af160..a98be9dfae 100644
> --- a/drivers/timer/Kconfig
> +++ b/drivers/timer/Kconfig
> @@ -326,4 +326,11 @@ config XILINX_TIMER
> Select this to enable support for the timer found on
> any Xilinx boards (axi timer).
>
> +config STARFIVE_TIMER
> + bool "Starfive timer support"
> + depends on TIMER
> + help
> + Select this to enable support for the timer found on
> + Starfive SoC.
> +
> endmenu
> diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index
> 1ca74805fd..1ef814970b 100644
> --- a/drivers/timer/Makefile
> +++ b/drivers/timer/Makefile
> @@ -34,3 +34,4 @@ obj-$(CONFIG_MTK_TIMER) +=
> mtk_timer.o
> obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o
> obj-$(CONFIG_IMX_GPT_TIMER) += imx-gpt-timer.o
> obj-$(CONFIG_XILINX_TIMER) += xilinx-timer.o
> +obj-$(CONFIG_STARFIVE_TIMER) += starfive-timer.o
> diff --git a/drivers/timer/starfive-timer.c b/drivers/timer/starfive-timer.c
> new
> file mode 100644 index 00..816402fdbf
> --- /dev/null
> +++ b/drivers/timer/starfive-timer.c
> @@ -0,0 +1,94 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2022 StarFive, Inc. All rights reserved.
> + * Author: Lee Kuan Lim
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define STF_TIMER_INT_STATUS0x00
> +#define STF_TIMER_CTL0x04
> +#define STF_TIMER_LOAD 0x08
> +#define STF_TIMER_ENABLE 0x10
> +#define STF_TIMER_RELOAD 0x14
> +#define STF_TIMER_VALUE 0x18
> +#define STF_TIMER_INT_CLR0x20
> +#define STF_TIMER_INT_MASK 0x24
> +
> +struct starfive_timer_priv {
> + void __iomem *base;
> + u32 timer_size;
> +};
> +
> +static u64 notrace starfive_get_count(struct udevice *dev) {
> + struct starfive_timer_priv *priv = dev_get_priv(dev);
> +
> + /* Read decrement timer value and convert to increment value */
> + return priv->timer_size - readl(priv->base + STF_TIMER_VALUE); }
> +
> +static const struct timer_ops starfive_ops = {
> + .get_count = starfive_get_count,
> +};
> +
> +static int starfive_probe(struct udevice *dev) {
> + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> + struct starfive_timer_priv *priv = dev_get_priv(dev);
> + int timer_channel;
> + struct clk clk;
> + int ret;
> +
> + priv->base = dev_read_addr_ptr(dev);
> + if (IS_ERR(priv->base))
> + return PTR_ERR(priv->base);
> +
> + timer_channel = dev_read_u32_default(dev, "channel", 0);
> + priv->base = priv->base + (0x40 * timer_channel);
> +
> + /* Get clock rate from channel selectecd*/
> + ret = clk_get_by_index(dev, timer_channel, );
> + if (ret)
> + return ret;
> +
> + ret = clk_enable();
> + if (ret)
> + return ret;
> + uc_priv->clock_rate = clk_get_rate();
> +
> + /* Initiate timer, channel 0 */
> + /* Unmask Interrupt Mask */
> + writel(0, priv->base + STF_TIMER_INT_MASK);
> + /* Single run mode Setting */
> + if (dev_read_bool(dev, "single-run"))
> + writel(1, priv->base + STF_TIMER_CTL);
> + /* Set Reload value */
> + priv->timer_size = dev_read_u32_default(dev, "timer-size", 0x);
> + writel(priv->timer_size, priv->base + STF_TIMER_LOAD);
> + /* Enable to start timer */
> + writel(1, priv->base + STF_TIMER_ENABLE);
> +
> + return 0;
> +}
> +
> +static const struct udevice_id starfive_ids[] = {
> + { .compatible = "starfive,jh8100-timers" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(jh8100_starfive_timer) = {
> + .name = "jh8100_starfive_timer",
> + .id = UCLASS_TIMER,
> + .of_match = starfive_ids,
> + .probe = starfive_probe,
> + .ops= _ops,
> + .priv_auto = sizeof(struct starfive_timer_priv),
> +};
> --
> 2.34.1
Re: [PATCH 2/4] arm: dts: Add support for AM62x LP SK
On 16:11-20231003, Nitin Yadav wrote: [...] > >>> > >>> NAK. should come from board.dts. > >> > >> am62sip support is also in the queue where we have only 512M of RAM. > >> That's why I'm adding this node in r5-sk.dts > > > > NAK. > > > > Do this cleanup in the context of the new platform addition - when you > > get it in the kernel first. > > I haven't planned to have a kernel dt for am62sip as there is only > difference is DDR size which will be taken care by U-boot. We can cross that bridge when we get to it - but overall, that sounds Assumption is wrong. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
Re: [RFC PATCH v2 4/8] binman: k3: add k3-security.h and include it in k3-binman.dtsi
Hi Simon,
On 19:17-20231001, Simon Glass wrote:
> Hi Manorit,
>
> On Tue, 26 Sept 2023 at 01:59, Manorit Chawdhry wrote:
> >
> > For readability during configuring firewalls, adding k3-security.h file
> > and including it in k3-binman.dtsi to be accessible across K3 SoCs
> >
> > Signed-off-by: Manorit Chawdhry
> > ---
> > arch/arm/dts/k3-binman.dtsi | 2 ++
> > arch/arm/dts/k3-security.h | 58
> > +
> > 2 files changed, 60 insertions(+)
> >
>
> Reviewed-by: Simon Glass
>
> nits below
>
> > diff --git a/arch/arm/dts/k3-binman.dtsi b/arch/arm/dts/k3-binman.dtsi
> > index 2ea2dd18a12b..71ffa998a59f 100644
> > --- a/arch/arm/dts/k3-binman.dtsi
> > +++ b/arch/arm/dts/k3-binman.dtsi
> > @@ -3,6 +3,8 @@
> > * Copyright (C) 2022-2023 Texas Instruments Incorporated -
> > https://www.ti.com/
> > */
> >
> > +#include "k3-security.h"
> > +
> > / {
> > binman: binman {
> > multiple-images;
> > diff --git a/arch/arm/dts/k3-security.h b/arch/arm/dts/k3-security.h
> > new file mode 100644
> > index ..e012b7afaf94
> > --- /dev/null
> > +++ b/arch/arm/dts/k3-security.h
> > @@ -0,0 +1,58 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
> > + */
> > +
> > +#ifndef DTS_ARM64_TI_K3_FIREWALL_H
> > +#define DTS_ARM64_TI_K3_FIREWALL_H
> > +
> > +#define FWPRIVID_ALL(0xc3)
> > +#define FWPRIVID_ARMV8 (1)
> > +#define FWPRIVID_SHIFT (16)
>
> drop () on those three and the next one
>
Would fix those in next revision. Thanks for the reviews!
Regards,
Manorit
> > +
> > +#define FWCTRL_EN (0xA)
> > +#define FWCTRL_LOCK (1 << 4)
> > +#define FWCTRL_BG (1 << 8)
> > +#define FWCTRL_CACHE (1 << 9)
> > +
> > +#define FWPERM_SECURE_PRIV_WRITE (1 << 0)
> > +#define FWPERM_SECURE_PRIV_READ (1 << 1)
> > +#define FWPERM_SECURE_PRIV_CACHEABLE (1 << 2)
> > +#define FWPERM_SECURE_PRIV_DEBUG (1 << 3)
> > +
> > +#define FWPERM_SECURE_PRIV_RWCD (FWPERM_SECURE_PRIV_READ | \
> > + FWPERM_SECURE_PRIV_WRITE | \
> > + FWPERM_SECURE_PRIV_CACHEABLE | \
> > + FWPERM_SECURE_PRIV_DEBUG)
> > +
> > +#define FWPERM_SECURE_USER_WRITE (1 << 4)
> > +#define FWPERM_SECURE_USER_READ (1 << 5)
> > +#define FWPERM_SECURE_USER_CACHEABLE (1 << 6)
> > +#define FWPERM_SECURE_USER_DEBUG (1 << 7)
> > +
> > +#define FWPERM_SECURE_USER_RWCD (FWPERM_SECURE_USER_READ | \
> > + FWPERM_SECURE_USER_WRITE | \
> > + FWPERM_SECURE_USER_CACHEABLE | \
> > + FWPERM_SECURE_USER_DEBUG)
> > +
> > +#define FWPERM_NON_SECURE_PRIV_WRITE (1 << 8)
> > +#define FWPERM_NON_SECURE_PRIV_READ (1 << 9)
> > +#define FWPERM_NON_SECURE_PRIV_CACHEABLE (1 << 10)
> > +#define FWPERM_NON_SECURE_PRIV_DEBUG (1 << 11)
> > +
> > +#define FWPERM_NON_SECURE_PRIV_RWCD (FWPERM_NON_SECURE_PRIV_READ | \
> > + FWPERM_NON_SECURE_PRIV_WRITE | \
> > +
> > FWPERM_NON_SECURE_PRIV_CACHEABLE | \
> > + FWPERM_NON_SECURE_PRIV_DEBUG)
> > +
> > +#define FWPERM_NON_SECURE_USER_WRITE (1 << 12)
> > +#define FWPERM_NON_SECURE_USER_READ (1 << 13)
> > +#define FWPERM_NON_SECURE_USER_CACHEABLE (1 << 14)
> > +#define FWPERM_NON_SECURE_USER_DEBUG (1 << 15)
> > +
> > +#define FWPERM_NON_SECURE_USER_RWCD (FWPERM_NON_SECURE_USER_READ | \
> > + FWPERM_NON_SECURE_USER_WRITE | \
> > +
> > FWPERM_NON_SECURE_USER_CACHEABLE | \
> > + FWPERM_NON_SECURE_USER_DEBUG)
> > +
> > +#endif
> >
> > --
> > 2.41.0
> >
>
> Regards,
> Simon
Re: [RFC PATCH v2 2/8] binman: ti-secure: Add support for firewalling entities
Hi Simon, On 19:17-20231001, Simon Glass wrote: > Hi Manorit, > > On Tue, 26 Sept 2023 at 01:58, Manorit Chawdhry wrote: > > > > We can now firewall entities while loading them through our secure > > entity TIFS, the required information should be present in the > > certificate that is being parsed by TIFS. > > > > The following commit adds the support to enable the certificates to be > > generated if the firewall configurations are present in the binman dtsi > > nodes. > > > > Signed-off-by: Manorit Chawdhry > > --- > > tools/binman/btool/openssl.py | 16 +++- > > tools/binman/etype/ti_secure.py | 85 > > + > > tools/binman/etype/x509_cert.py | 3 +- > > 3 files changed, 101 insertions(+), 3 deletions(-) > > > > Please do check that you have 100% test coverage here (binman test -T) > NameStmts Miss Cover --- [snip] tools/binman/btool/openssl.py 42 0 100% tools/binman/etype/ti_secure.py57 0 100% tools/binman/etype/x509_cert.py70 0 100% [snip] --- TOTAL558813498% I did check that, did you notice something else that I might've missed? I just checked for the files that I have changed, I am not sure if there are any dependencies that I also have to keep in mind. Do let me know if I missed something. Regards, Manorit > Regards, > Simon
Re: [PATCH 2/4] arm: dts: Add support for AM62x LP SK
On 28/09/23 20:00, Nishanth Menon wrote:
> On 15:00-20230928, Nitin Yadav wrote:
>> Hi,
>>
>> On 27/09/23 17:22, Nishanth Menon wrote:
>>> On 13:51-20230927, Nitin Yadav wrote:
The AM62x LP SK board is similar to the AM62x SK board,
but has some significant changes that requires different
device tree.
The differences are mainly:
- AM62x SoC in the AMC package that meets AECQ100 automotive standard.
- LPDDR4 versus DDR4 on the AM62x SK.
- TPS65219 PMIC instead of discrete regulators.
- IO expander pin names are wired differently.
- Second ethernet port is currently disabled as the boards do not have
the part physically installed.
- OSPI NAND vs OSPI NOR.
- No WLAN chip instead a SDIO M.2 connector.
Signed-off-by: Nitin Yadav
---
arch/arm/dts/Makefile |2 +
arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi|9 +
arch/arm/dts/k3-am62-lp-sk.dts| 231 ++
>>>
arch/arm/dts/k3-am62-r5-lp-sk.dts | 21 +
arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi | 2190 +
5 files changed, 2453 insertions(+)
create mode 100644 arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
create mode 100644 arch/arm/dts/k3-am62-lp-sk.dts
create mode 100644 arch/arm/dts/k3-am62-r5-lp-sk.dts
create mode 100644 arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bde2176ec7..72ea57885f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1337,6 +1337,8 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
k3-am625-r5-sk.dtb \
+k3-am62-lp-sk.dtb \
+k3-am62-r5-lp-sk.dtb \
k3-am625-beagleplay.dtb \
k3-am625-r5-beagleplay.dtb \
k3-am625-verdin-wifi-dev.dtb \
diff --git a/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
b/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
new file mode 100644
index 00..7da94fe4b6
--- /dev/null
+++ b/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM62x LP SK dts file for SPLs
+ * Copyright (C) 2021-2023 Texas Instruments Incorporated -
https://www.ti.com/
+ */
+
+#include "k3-am62x-sk-common-u-boot.dtsi"
+
+#include "k3-am62-lp-sk-binman.dtsi"
>>>
>>> Are you sure you don't need the dt phase properties for regulators for
>>> mmc to work?
>>>
diff --git a/arch/arm/dts/k3-am62-lp-sk.dts
b/arch/arm/dts/k3-am62-lp-sk.dts
>>>
>>> Is this coming in from v6.6-rc1 if so document that in commit message.
>>>
>>> [...]
>>>
diff --git a/arch/arm/dts/k3-am62-r5-lp-sk.dts
b/arch/arm/dts/k3-am62-r5-lp-sk.dts
new file mode 100644
index 00..ed2c028bad
--- /dev/null
+++ b/arch/arm/dts/k3-am62-r5-lp-sk.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM62x LP SK dts file for R5 SPL
+ * Copyright (C) 2021-2023 Texas Instruments Incorporated -
https://www.ti.com/
+ */
+
+#include "k3-am62-lp-sk.dts"
+#include "k3-am62x-ddr-lp4-50-800-800.dtsi"
+#include "k3-am62-ddr.dtsi"
+
+#include "k3-am62-lp-sk-u-boot.dtsi"
+#include "k3-am62x-r5-sk-common.dtsi"
+
+/ {
+ memory@8000 {
+ device_type = "memory";
+ /* 2G RAM */
+ reg = <0x 0x8000 0x 0x8000>;
+ bootph-pre-ram;
+ };
+};
>>>
>>> NAK. should come from board.dts.
>>
>> am62sip support is also in the queue where we have only 512M of RAM.
>> That's why I'm adding this node in r5-sk.dts
>
> NAK.
>
> Do this cleanup in the context of the new platform addition - when you
> get it in the kernel first.
I haven't planned to have a kernel dt for am62sip as there is only
difference is DDR size which will be taken care by U-boot.
>
> Side note: I don't see anything in ti.com for the search text.
>
>
--
Regards,
Nitin
Re: [RFC PATCH v2 1/8] dtoc: openssl: Add GetHexOctet method
Hi Simon,
On 19:17-20231001, Simon Glass wrote:
> Hi Manorit,
>
> On Tue, 26 Sept 2023 at 01:58, Manorit Chawdhry wrote:
> >
> > HexOctet format is used by openssl for FORMAT:HEX,OCT property in x509
> > certificates. Add a helper function to extract the integer numbers in
> > HEX,OCT format to pass to openssl directly.
> >
> > Signed-off-by: Manorit Chawdhry
> > ---
> > tools/dtoc/fdt_util.py | 20
> > 1 file changed, 20 insertions(+)
> >
> > diff --git a/tools/dtoc/fdt_util.py b/tools/dtoc/fdt_util.py
> > index f1f70568cfef..d51dbf5633d0 100644
> > --- a/tools/dtoc/fdt_util.py
> > +++ b/tools/dtoc/fdt_util.py
> > @@ -100,6 +100,26 @@ def EnsureCompiled(fname, tmpdir=None,
> > capture_stderr=False):
> > command.run(dtc, *args, capture_stderr=capture_stderr)
> > return dtb_output
> >
> > +def GetHexOctet(node, propname, default=None):
>
> What is a hex octet?
>
It is actually a Hex number in Octet form, basically using 0x0a instead
of 0xa type of thing.
OpenSSL has complained when we use FORMAT:HEX,OCT:0 type of string
instead of FORMAT:HEX,OCT:00. Tbvh I still haven't been able to find a
clear documentation for this but this is what I have been able to figure
out based on my tests.
> > +"""Get an integer from a property in hex octet form required by openssl
> > +
>
> You should mention what size property is permitted.
>
> > +Args:
> > +node: Node object to read from
> > +propname: property name to read
> > +default: Default value to use if the node/property do not exist
> > +
> > +Returns:
> > +Integer value read as a String in Hex Octet Form
> > +"""
> > +prop = node.props.get(propname)
> > +if not isinstance(prop.value, list) or len(prop.value) != 2:
> > +value = GetInt(node, propname)
> > +elif isinstance(prop.value, list) and len(prop.value) == 2:
> > +value = GetInt64(node, propname)
>
> What if it is neither of those?
>
> > +
> > +hex_value = '%x' % (value)
> > +return ('0' * (len(hex_value) & 1)) + hex_value
>
> Can you do:
>
> return f'{value:02x}'
>
With the following suggestion I don't think I need the patch at all
anymore given that no one else seems to be requiring this HEX,OCT just
yet and am still in the process of finding a clear documentation for it.
Will be dropping that patch after testing if not required to be generic.
Thanks!
Regards,
Manorit
> ?
>
>
> > +
> > def GetInt(node, propname, default=None):
> > """Get an integer from a property
> >
> >
> > --
> > 2.41.0
> >
[PATCH] Makefile: make u-boot-initial-env target depend explicitly on scripts_basic
We're seeing sporadic errors like ENVCinclude/generated/env.txt HOSTCC scripts/basic/fixdep ENVPinclude/generated/env.in ENVTinclude/generated/environment.h HOSTCC tools/printinitialenv /bin/sh: 1: scripts/basic/fixdep: not found make[1]: *** [scripts/Makefile.host:95: tools/printinitialenv] Error 127 make[1]: *** Deleting file 'tools/printinitialenv' make: *** [Makefile:2446: u-boot-initial-env] Error 2 make: *** Waiting for unfinished jobs where sometimes the "fixdep: not found" is instead "fixdep: Permission denied" and the Error 127 becomes 126. This smells like a race condition, and indeed it is: Currently, u-boot-initial-env is a prerequisite of the envtools target, which also lists scripts_basic as a prerequisite: envtools: u-boot-initial-env scripts_basic $(version_h) $(timestamp_h) tools/version.h $(Q)$(MAKE) $(build)=tools/env However, the u-boot-initial-env rule involves building the printinitialenv helper, which in turn is built using an if_changed_dep rule. That means we must ensure scripts/basic/fixdep is built and ready before trying to build printinitialenv, i.e. the u-boot-initial-env rule itself must depend on the phony scripts_basic target. Signed-off-by: Rasmus Villemoes --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 8af1fa9468..069c03696a 100644 --- a/Makefile +++ b/Makefile @@ -2447,7 +2447,7 @@ cmd_genenv = \ sed -e '/^\s*$$/d' | \ sort -t '=' -k 1,1 -s -o $@ -u-boot-initial-env: $(env_h) FORCE +u-boot-initial-env: scripts_basic $(env_h) FORCE $(Q)$(MAKE) $(build)=tools $(objtree)/tools/printinitialenv $(call if_changed,genenv) -- 2.40.1.1.g1c60b9335d
Re: [PATCH 1/1] sunxi: dram: Fix incorrect ram size detection for some H6 boards
On Mon, 02 Oct 2023 20:50:49 +0200
Jernej Škrabec wrote:
Hi,
> Dne ponedeljek, 02. oktober 2023 ob 13:26:26 CEST je Andre Przywara
> napisal(a):
> > On Sun, 1 Oct 2023 21:43:32 +0530
> > Gunjan Gupta wrote:
> >
> > (fixing Jernej's email)
> >
> > Hi Gunjan,
> >
> > thanks for sending a patch!
> >
> > > On some H6 boards like Orange Pi 3 LTS, some times U-Boot fails to detect
> > > ram size correctly. Instead of 2GB thats available, it detects 4GB of ram
> > > and then SPL just hangs there making board not to boot further.
> > >
> > > On debugging, I found that the rows value were being determined correctly,
> > > but columns were sometimes off by one value. I found that adding some
> > > delay after the mctl_core_init call along with making use of dsb in the
> > > start of the mctl_mem_matches solves the issue.
> > >
> > > Signed-off-by: Gunjan Gupta
> > > ---
> > >
> > > arch/arm/mach-sunxi/dram_helpers.c | 1 +
> > > arch/arm/mach-sunxi/dram_sun50i_h6.c | 2 ++
> > > 2 files changed, 3 insertions(+)
> > >
> > > diff --git a/arch/arm/mach-sunxi/dram_helpers.c
> > > b/arch/arm/mach-sunxi/dram_helpers.c
> > > index cdf2750f1c..5758c58e07 100644
> > > --- a/arch/arm/mach-sunxi/dram_helpers.c
> > > +++ b/arch/arm/mach-sunxi/dram_helpers.c
> > > @@ -32,6 +32,7 @@ void mctl_await_completion(u32 *reg, u32 mask, u32 val)
> > > #ifndef CONFIG_MACH_SUNIV
> > > bool mctl_mem_matches(u32 offset)
> > > {
> > > + dsb();
> >
> > This looks a bit odd, do you have an explanation for that? And are you
> > sure that is really needed?
> > I understand why we need the DSB after the writel's below, but before that?
> > The only thing I could think of is that we are missing a barrier in
> > mctl_core_init() - which is the function called before mctl_mem_matches().
> > Can you move that dsb(); into mctl_auto_detect_dram_size(), right after
> > the mctl_core_init() call (where you add the udelay() below)? And I wonder
> > if a dmb() would already be sufficient? I noticed recently that the
> > clr/setbit_le32() functions don't have a barrier at all, maybe that should
> > be fixed instead?
>
> Looking at original BSP DRAM code, there is no data barriers that I can find.
> Cache shouldn't be a thing before DRAM is initialized, right?
With the *MMU off* every memory access is "device nGnRnE", so
definitely not cached. But a Cortex-A53 still has a store buffer which
is in effect even for device accesses.
> Conversely,
> I suggest adding memory barriers before each udelay(), as it is there for a
> reason.
Talking to a colleague and looking at the ARM ARM and other
documentation, including [1]:
A DMB memory barrier (__iowmb() in U-Boot and Linux), as used in
readl/writel, just ensures ordering, it does not force completion.
For just programming the DRAM controller, this is what we want.
A DSB does everything that a DMB does, plus ensures "completion" of
memory accesses (plus other things like TLBs and CMOs, which we
don't care about in this case). In a Cortex-A53, this seems to include
flushing the store buffer, which is probably the culprit here.
So I don't know if the delays in the BSP DRAM driver are really
pauses that the DRAM controller needs. In this case we would need at
least a DSB before the udelay(), if not a device-read-back, though I
just assume that the DRAM controller registers do not have another
buffer on the hardware side. Check 27:47 onward of [1].
Another possibility is that the delays are just crude measures to paper
over missing barriers, hoping that the buffer is drained after the
time. But since the delays don't really hurt here, we should just assume
they are meaningful and keep them.
Also we pretty surely need a DSB after we setup the DRAM controller,
but before we use the DRAM array: the controller registers and the array
are separate devices, on different AXI buses. So that aspect of this patch
seems actually to be alright, and the fact that Gunjan needed the DSB
supports that.
I will try to come up with a patch that implements these ideas.
Cheers,
Andre
P.S. Please note that above statements are an application of the
architecture rules to the A53 and the MMU-off/single core situation in the
SPL. The situation is more complex when running Linux, especially on more
modern cores that do speculation and out-of-order execution.
[1] https://www.youtube.com/watch?v=i6DayghhA8Q
>
> >
> > > /* Try to write different values to RAM at two addresses */
> > > writel(0, CFG_SYS_SDRAM_BASE);
> > > writel(0xaa55aa55, (ulong)CFG_SYS_SDRAM_BASE + offset);
> > > diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c
> > > b/arch/arm/mach-sunxi/dram_sun50i_h6.c
> > > index bff2e42513..a031a845f5 100644
> > > --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
> > > +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
> > > @@ -623,6 +623,8 @@ static void mctl_auto_detect_dram_size(struct
> > > dram_para *para)
> > > para->cols = 11;
> > > mctl_core_init(para);
> > >
> > > + udelay(50);
>
Re: [PATCH] arm: dts: k3-am625-beagleplay: Fix Boot
On 02/10/2023 18:00, Nishanth Menon wrote:
> Since commit [1] A53 u-boot proper is broken. This is because nodes
> marked as 'bootph-pre-ram' are not available at u-boot proper before
> relocation.
>
> To fix this we mark all nodes in u-boot.dtsi as 'bootph-all'.
>
> [1]
> 9e644284ab812 ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after
> relocation")
>
> Reported-by: Roger Quadros
> Signed-off-by: Nishanth Menon
Reviewed-by: Roger Quadros
> ---
>
> Based on Roger's series:
> https://lore.kernel.org/all/20230929134646.214781-1-rog...@kernel.org/
>
> Based on:
> next e29b932aa07f Merge branch
> '2023-09-30-Kconfig-updates' into next
>
> See discussion thread:
> https://lore.kernel.org/all/capnjgz3mgwx8t0a0sofpher_xd77pe3hte9dnye1rubveb9...@mail.gmail.com/
>
--
cheers,
-roger
[PATCH] test/py: net: Add a TFTP put test
Execute tftpput command for uploading files to a server and validate its
size & CRC32.
Signed-off-by: Love Kumar
---
test/py/tests/test_net.py | 69 +++
1 file changed, 69 insertions(+)
diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py
index cd4b4dc53cbc..f69e3ea2dbba 100644
--- a/test/py/tests/test_net.py
+++ b/test/py/tests/test_net.py
@@ -6,6 +6,7 @@
import pytest
import u_boot_utils
+import datetime
"""
Note: This test relies on boardenv_* containing configuration values to define
@@ -50,6 +51,7 @@ env__net_tftp_readable_file = {
'addr': 0x1000,
'size': 5058624,
'crc32': 'c2244b26',
+'timeout': 5,
}
# Details regarding a file that may be read from a NFS server. This variable
@@ -260,3 +262,70 @@ def test_net_nfs(u_boot_console):
output = u_boot_console.run_command('crc32 %x $filesize' % addr)
assert expected_crc in output
+
+@pytest.mark.buildconfigspec("cmd_crc32")
+@pytest.mark.buildconfigspec("cmd_net")
+def test_net_tftpput(u_boot_console):
+"""Test the tftpput command.
+A file is downloaded from the TFTP server and then uploaded to the TFTP
+server, its size and its CRC32 are validated.
+The details of the file to download are provided by the boardenv_* file;
+see the comment at the beginning of this file.
+"""
+
+if not net_set_up:
+pytest.skip("Network not initialized")
+
+f = u_boot_console.config.env.get("env__net_tftp_readable_file", None)
+if not f:
+pytest.skip("No TFTP readable file to read")
+
+addr = f.get("addr", None)
+if not addr:
+addr = u_boot_utils.find_ram_base(u_boot_console)
+
+sz = f.get("size", None)
+timeout = f.get("timeout", u_boot_console.p.timeout)
+fn = f["fn"]
+fnu = "_".join([datetime.datetime.now().strftime("%y%m%d%H%M%S"), fn])
+expected_text = "Bytes transferred = "
+if sz:
+expected_text += "%d" % sz
+
+with u_boot_console.temporary_timeout(timeout):
+output = u_boot_console.run_command("tftpboot %x %s" % (addr, fn))
+
+assert "TIMEOUT" not in output
+assert expected_text in output
+
+expected_tftpb_crc = f.get("crc32", None)
+
+output = u_boot_console.run_command("crc32 $fileaddr $filesize")
+assert expected_tftpb_crc in output
+
+with u_boot_console.temporary_timeout(timeout):
+output = u_boot_console.run_command(
+"tftpput $fileaddr $filesize $serverip:%s" % (fnu)
+)
+
+expected_text = "Bytes transferred = "
+if sz:
+expected_text += "%d" % sz
+addr = addr + sz
+assert "TIMEOUT" not in output
+assert "Access violation" not in output
+assert expected_text in output
+
+with u_boot_console.temporary_timeout(timeout):
+output = u_boot_console.run_command("tftpboot %x %s" % (addr, fnu))
+
+expected_text = "Bytes transferred = "
+if sz:
+expected_text += "%d" % sz
+assert "TIMEOUT" not in output
+assert expected_text in output
+
+expected_tftpp_crc = expected_tftpb_crc
+
+output = u_boot_console.run_command("crc32 $fileaddr $filesize")
+assert expected_tftpp_crc in output
--
2.25.1
[PATCH v2] wdt: nuvoton: fix reset/expire function error
fix npcm845 watchdog halt for reset function and expire function.
reset function is restart wdt.
Signed-off-by: Jim Liu
Changes for v2:
- add commit message
- fix no empty line problem
- remove dts
---
drivers/watchdog/npcm_wdt.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c
index e56aa0ebe1..22d7fc45dd 100644
--- a/drivers/watchdog/npcm_wdt.c
+++ b/drivers/watchdog/npcm_wdt.c
@@ -70,14 +70,21 @@ static int npcm_wdt_reset(struct udevice *dev)
{
struct npcm_wdt_priv *priv = dev_get_priv(dev);
- writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, priv->regs);
+ u32 val;
+
+ val = readl(priv->regs);
+ writel(val | NPCM_WTR, priv->regs);
return 0;
}
static int npcm_wdt_expire_now(struct udevice *dev, ulong flags)
{
- return npcm_wdt_reset(dev);
+ struct npcm_wdt_priv *priv = dev_get_priv(dev);
+
+ writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, priv->regs);
+
+ return 0;
}
static int npcm_wdt_of_to_plat(struct udevice *dev)
--
2.25.1
Re: [PATCH v1] i2c: nuvoton: add support fast mode
Hi Heiko
Thanks for your review.
Our bmc HW can support standard / fast / fast plus mode
but our first uboot version 2019 is only run on standard mode.
so the first upstream version is the same as before.
Now, some customer need to test other mode on uboot.
So remove this judgment to support other mode.
I will add a commit message in the next version.
Best regards,
Jim
On Mon, Oct 2, 2023 at 9:37 PM Heiko Schocher wrote:
>
> Hello Jim,
>
> On 26.09.23 11:08, Jim Liu wrote:
> > Signed-off-by: Jim Liu
> > ---
> > drivers/i2c/npcm_i2c.c | 5 -
> > 1 file changed, 5 deletions(-)
> >
> > diff --git a/drivers/i2c/npcm_i2c.c b/drivers/i2c/npcm_i2c.c
> > index ea4ef53256..b867b6c8e9 100644
> > --- a/drivers/i2c/npcm_i2c.c
> > +++ b/drivers/i2c/npcm_i2c.c
> > @@ -517,11 +517,6 @@ static int npcm_i2c_init_clk(struct npcm_i2c_bus *bus,
> > u32 bus_freq)
> > u32 sclfrq;
> > u8 hldt, val;
> >
> > - if (bus_freq > I2C_FREQ_100K) {
> > - printf("Support standard mode only\n");
> > - return -EINVAL;
> > - }
> > -
>
> Is it so easy to enable fast mode? As original code explicitely
> says "Support standard mode only" and returns -EINVAL?
>
> And please add some text into commit message, may you can explain
> why current driver supports fast mode?
>
> Thanks!
>
> bye,
> Heiko
> --
> DENX Software Engineering GmbH, Managing Director: Erika Unter
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
[PATCH RFC 10/10] board: ti: j721e: Enable ESM initialization for J7200
Enable ESM initialization for J7200
Signed-off-by: Keerthy
---
board/ti/j721e/evm.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 42fa94b7a5..070b28326f 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -543,7 +543,8 @@ void spl_board_init(void)
}
#ifdef CONFIG_ESM_K3
- if (board_ti_k3_is("J721EX-PM2-SOM")) {
+ if ((board_ti_k3_is("J721EX-PM2-SOM")) ||
+ IS_ENABLED(CONFIG_TARGET_J7200_R5_EVM)) {
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(k3_esm), );
if (ret)
@@ -557,7 +558,8 @@ void spl_board_init(void)
#endif
#ifdef CONFIG_ESM_PMIC
- if (board_ti_k3_is("J721EX-PM2-SOM")) {
+ if ((board_ti_k3_is("J721EX-PM2-SOM")) ||
+ IS_ENABLED(CONFIG_TARGET_J7200_R5_EVM)) {
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(pmic_esm),
);
--
2.17.1
[PATCH RFC 09/10] configs: j7200_evm_r5_defconfig: Enable the ESM configs
Enable the ESM configs. Signed-off-by: Keerthy --- configs/j7200_evm_r5_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index c4dd33627b..7adc230fc1 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -101,6 +101,8 @@ CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_FS_LOADER=y CONFIG_SPL_FS_LOADER=y +CONFIG_ESM_K3=y +CONFIG_ESM_PMIC=y CONFIG_K3_AVS0=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPL_MMC_HS400_SUPPORT=y -- 2.17.1
[PATCH RFC 08/10] arm: dts: k3-j7200-r5-common-proc-board: Add PMIC ESM node
Enable the TPS659413 has the ESM PMIC.
Signed-off-by: Keerthy
---
arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index e62f9218e8..4e5e4a08f8 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -271,6 +271,20 @@
};
};
+ tps659413: tps659413@48 {
+ compatible = "ti,tps659413";
+ reg = <0x48>;
+ bootph-pre-ram;
+
+ regulators_a: regulators {
+ bootph-pre-ram;
+ };
+
+ esm: esm {
+ compatible = "ti,tps659413-esm";
+ bootph-pre-ram;
+ };
+ };
};
_vtm0 {
--
2.17.1
[PATCH RFC 07/10] configs: j721s2_evm_r5_defconfig: Enable ESM & PMIC ESM configs
Enable ESM & PMIC ESM configs Signed-off-by: Keerthy --- configs/j721s2_evm_r5_defconfig | 7 +++ 1 file changed, 7 insertions(+) diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 1e66ac23d0..b9ac56f34d 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -112,6 +112,8 @@ CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_FS_LOADER=y CONFIG_SPL_FS_LOADER=y +CONFIG_ESM_K3=y +CONFIG_ESM_PMIC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_MMC_SDHCI=y @@ -142,6 +144,11 @@ CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_POWER_DOMAIN=y CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_TPS65941=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_TPS65941=y CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y -- 2.17.1
[PATCH RFC 06/10] board: ti: j721s2: Initialize the ESM & PMIC ESM
Initialize the ESM & PMIC ESM
Signed-off-by: Keerthy
---
board/ti/j721s2/evm.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index 7795300abc..effa52ff5a 100644
--- a/board/ti/j721s2/evm.c
+++ b/board/ti/j721s2/evm.c
@@ -319,4 +319,31 @@ int board_late_init(void)
void spl_board_init(void)
{
+ struct udevice *dev;
+ int ret;
+
+ if (IS_ENABLED(CONFIG_ESM_K3)) {
+ ret = uclass_get_device_by_name(UCLASS_MISC, "esm@70",
+ );
+ if (ret)
+ printf("MISC init for esm@70 failed: %d\n", ret);
+
+ ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4080",
+ );
+ if (ret)
+ printf("MISC init for esm@4080 failed: %d\n", ret);
+
+ ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4208",
+ );
+ if (ret)
+ printf("MISC init for esm@4208 failed: %d\n", ret);
+ }
+
+ if (IS_ENABLED(CONFIG_ESM_PMIC)) {
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(pmic_esm),
+ );
+ if (ret)
+ printf("ESM PMIC init failed: %d\n", ret);
+ }
}
--
2.17.1
[PATCH RFC 05/10] board: ti: j721e: Initialize MCU ESM
Initialize MCU ESM. This is needed to propagate MAIN domain
events to the PMIC.
Signed-off-by: Keerthy
---
board/ti/j721e/evm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 38fe447d8f..42fa94b7a5 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -548,7 +548,12 @@ void spl_board_init(void)
DM_DRIVER_GET(k3_esm), );
if (ret)
printf("ESM init failed: %d\n", ret);
+
+ ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4080",
);
+ if (ret)
+ printf("MISC init for esm@4080 failed: %d\n", ret);
}
+
#endif
#ifdef CONFIG_ESM_PMIC
--
2.17.1
[PATCH RFC 04/10] arm64: dts: ti: k3-j721e: Add MCU domain ESM instance
Patch adds the ESM instance for MCU domian of j721e.
Signed-off-by: Keerthy
---
arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
index 22166c7942..66fdd6443f 100644
--- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
@@ -408,4 +408,11 @@
ti,loczrama = <1>;
};
};
+
+ mcu_esm: esm@4080 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x4080 0x00 0x1000>;
+ ti,esm-pins = <95>;
+ bootph-pre-ram;
+ };
};
--
2.17.1
[PATCH RFC 03/10] arm: dts: k3-j721s2-r5-common-proc-board: Add ESM PMIC and dependent nodes
PMIC ESM is part of tps6594x PMIC and connected to WKUP_I2C instance.
Signed-off-by: Keerthy
---
.../dts/k3-j721s2-r5-common-proc-board.dts| 39 +++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
index c74e8e58ae..629706aaf1 100644
--- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
@@ -142,6 +142,14 @@
J721S2_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (D27)
WKUP_UART0_TXD */
>;
};
+
+ wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ bootph-pre-ram;
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (H24)
WKUP_I2C0_SCL */
+ J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (H27)
WKUP_I2C0_SDA */
+ >;
+ };
};
{
@@ -197,4 +205,35 @@
ti,sci = <_tifs>;
};
+_i2c0 {
+ bootph-pre-ram;
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c0_pins_default>;
+ clock-frequency = <40>;
+
+ tps659413: tps659413@48 {
+ compatible = "ti,tps659413";
+ reg = <0x48>;
+ bootph-pre-ram;
+
+ regulators: regulators {
+ bootph-pre-ram;
+ buck1234_reg: buck1234 {
+ /*VDD_CPU_AVS*/
+ regulator-name = "buck1234";
+ regulator-min-microvolt = <60>;
+ regulator-max-microvolt = <90>;
+ regulator-always-on;
+ regulator-boot-on;
+ bootph-pre-ram;
+ };
+ };
+
+ esm: esm {
+ compatible = "ti,tps659413-esm";
+ bootph-pre-ram;
+ };
+ };
+};
+
#include "k3-j721s2-common-proc-board-u-boot.dtsi"
--
2.17.1
[PATCH RFC 02/10] arm64: dts: ti: k3-j7200: Add MCU domain ESM instance
Patch adds the ESM instance for MCU domian of j7200.
Signed-off-by: Keerthy
---
arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
index 1044ec6c4b..2b185fa350 100644
--- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
@@ -375,4 +375,11 @@
ti,loczrama = <1>;
};
};
+
+ mcu_esm: esm@4080 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x4080 0x00 0x1000>;
+ ti,esm-pins = <95>;
+ bootph-pre-ram;
+ };
};
--
2.17.1
[PATCH RFC 01/10] arm64: dts: ti: k3-j721s2: Add ESM instances
Patch adds the ESM instances for j721s2. It has 3 instances.
One in the main domain and two in the mcu-wakeup domian.
Signed-off-by: Keerthy
---
arch/arm/dts/k3-j721s2-main.dtsi | 7 +++
arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi | 14 ++
2 files changed, 21 insertions(+)
diff --git a/arch/arm/dts/k3-j721s2-main.dtsi b/arch/arm/dts/k3-j721s2-main.dtsi
index 976ba1e95a..859b5124ae 100644
--- a/arch/arm/dts/k3-j721s2-main.dtsi
+++ b/arch/arm/dts/k3-j721s2-main.dtsi
@@ -934,4 +934,11 @@
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
+
+ main_esm: esm@70 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x70 0x00 0x1000>;
+ ti,esm-pins = <688>, <689>;
+ bootph-pre-ram;
+ };
};
diff --git a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
b/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
index 7521963719..f28cf7df50 100644
--- a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
@@ -299,4 +299,18 @@
ti,cpts-periodic-outputs = <2>;
};
};
+
+ mcu_esm: esm@4080 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x4080 0x00 0x1000>;
+ ti,esm-pins = <95>;
+ bootph-pre-ram;
+ };
+
+ wkup_esm: esm@4208 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x4208 0x00 0x1000>;
+ ti,esm-pins = <63>;
+ bootph-pre-ram;
+ };
};
--
2.17.1
[PATCH RFC 00/10] arm: dts: j7200/j721s2: Enable the ESM and PMIC ESM
This patch series is RFC. This is enabling ESM/PMIC_ESM modules needed for watchdog functionality. Keerthy (10): arm64: dts: ti: k3-j721s2: Add ESM instances arm64: dts: ti: k3-j7200: Add MCU domain ESM instance arm: dts: k3-j721s2-r5-common-proc-board: Add ESM PMIC and dependent nodes arm64: dts: ti: k3-j721e: Add MCU domain ESM instance board: ti: j721e: Initialize MCU ESM board: ti: j721s2: Initialize the ESM & PMIC ESM configs: j721s2_evm_r5_defconfig: Enable ESM & PMIC ESM configs arm: dts: k3-j7200-r5-common-proc-board: Add PMIC ESM node configs: j7200_evm_r5_defconfig: Enable the ESM configs board: ti: j721e: Enable ESM initialization for J7200 arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 7 .../arm/dts/k3-j7200-r5-common-proc-board.dts | 14 +++ arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 7 arch/arm/dts/k3-j721s2-main.dtsi | 7 arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi| 14 +++ .../dts/k3-j721s2-r5-common-proc-board.dts| 39 +++ board/ti/j721e/evm.c | 11 +- board/ti/j721s2/evm.c | 27 + configs/j7200_evm_r5_defconfig| 2 + configs/j721s2_evm_r5_defconfig | 7 10 files changed, 133 insertions(+), 2 deletions(-) -- 2.17.1
Re: [PATCH v1 7/8] dwc3: add support for Amlogic A1 family
On 02/10/2023 18:58, Alexey Romanov wrote:
Now the driver supports also A1 phy layer.
Signed-off-by: Alexey Romanov
---
drivers/usb/dwc3/dwc3-meson-g12a.c | 73 ++
1 file changed, 63 insertions(+), 10 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c
b/drivers/usb/dwc3/dwc3-meson-g12a.c
index 90418ddc1d..550e6682a2 100644
--- a/drivers/usb/dwc3/dwc3-meson-g12a.c
+++ b/drivers/usb/dwc3/dwc3-meson-g12a.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
/* USB2 Ports Control Registers */
@@ -102,10 +103,22 @@ enum {
PHY_COUNT,
};
-static const char *phy_names[PHY_COUNT] = {
+static const char *const dwc3_meson_g12a_phy_names[] = {
"usb2-phy0", "usb2-phy1", "usb3-phy0",
};
+static const char *const dwc3_meson_a1_phy_names[] = {
+ "usb2-phy0", "usb2-phy1"
+};
+
+struct dwc3_meson_g12a;
+
+struct dwc3_meson_g12a_drvdata {
+ const char *const *phy_names;
+ unsigned int phy_cnt;
+ int (*clk_init)(struct dwc3_meson_g12a *priv);
+};
+
struct dwc3_meson_g12a {
struct udevice *dev;
struct regmap *regmap;
@@ -119,6 +132,7 @@ struct dwc3_meson_g12a {
#if CONFIG_IS_ENABLED(DM_REGULATOR)
struct udevice *vbus_supply;
#endif
+ struct dwc3_meson_g12a_drvdata *drvdata;
};
#define U2P_REG_SIZE 0x20
@@ -293,10 +307,11 @@ int dwc3_meson_g12a_force_mode(struct udevice *dev, enum
usb_dr_mode mode)
static int dwc3_meson_g12a_get_phys(struct dwc3_meson_g12a *priv)
{
+ struct dwc3_meson_g12a_drvdata *data = priv->drvdata;
int i, ret;
- for (i = 0 ; i < PHY_COUNT ; ++i) {
- ret = generic_phy_get_by_name(priv->dev, phy_names[i],
+ for (i = 0 ; i < data->phy_cnt; ++i) {
+ ret = generic_phy_get_by_name(priv->dev, data->phy_names[i],
>phys[i]);
if (ret == -ENOENT || ret == -ENODATA)
continue;
@@ -354,18 +369,36 @@ static int dwc3_meson_g12a_clk_init(struct
dwc3_meson_g12a *priv)
return 0;
}
+static int dwc3_meson_a1_clk_init(struct dwc3_meson_g12a *priv)
+{
+ int ret;
+
+ ret = clk_get_by_name(priv->dev, "usb_bus", >clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(>clk);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static int dwc3_meson_g12a_probe(struct udevice *dev)
{
struct dwc3_meson_g12a *priv = dev_get_plat(dev);
+ struct dwc3_meson_g12a_drvdata *data =
+ (struct dwc3_meson_g12a_drvdata *)dev_get_driver_data(dev);
int ret, i;
+ priv->drvdata = data;
priv->dev = dev;
ret = regmap_init_mem(dev_ofnode(dev), >regmap);
if (ret)
return ret;
- ret = dwc3_meson_g12a_clk_init(priv);
+ ret = data->clk_init(priv);
if (ret)
return ret;
@@ -398,7 +431,7 @@ static int dwc3_meson_g12a_probe(struct udevice *dev)
if (ret)
return ret;
- for (i = 0 ; i < PHY_COUNT ; ++i) {
+ for (i = 0 ; i < data->phy_cnt; ++i) {
if (!priv->phys[i].dev)
continue;
@@ -407,7 +440,7 @@ static int dwc3_meson_g12a_probe(struct udevice *dev)
goto err_phy_init;
}
- for (i = 0; i < PHY_COUNT; ++i) {
+ for (i = 0; i < data->phy_cnt; ++i) {
if (!priv->phys[i].dev)
continue;
@@ -419,7 +452,7 @@ static int dwc3_meson_g12a_probe(struct udevice *dev)
return 0;
err_phy_init:
- for (i = 0 ; i < PHY_COUNT ; ++i) {
+ for (i = 0 ; i < data->phy_cnt ; ++i) {
if (!priv->phys[i].dev)
continue;
@@ -432,20 +465,21 @@ err_phy_init:
static int dwc3_meson_g12a_remove(struct udevice *dev)
{
struct dwc3_meson_g12a *priv = dev_get_plat(dev);
+ struct dwc3_meson_g12a_drvdata *data = priv->drvdata;
int i;
reset_release_all(>reset, 1);
clk_release_all(>clk, 1);
- for (i = 0; i < PHY_COUNT; ++i) {
+ for (i = 0; i < data->phy_cnt; ++i) {
if (!priv->phys[i].dev)
continue;
generic_phy_power_off(>phys[i]);
}
- for (i = 0 ; i < PHY_COUNT ; ++i) {
+ for (i = 0 ; i < data->phy_cnt; ++i) {
if (!priv->phys[i].dev)
continue;
@@ -455,8 +489,27 @@ static int dwc3_meson_g12a_remove(struct udevice *dev)
return dm_scan_fdt_dev(dev);
}
+static const struct dwc3_meson_g12a_drvdata meson_g12a_drvdata = {
+ .phy_names = dwc3_meson_g12a_phy_names,
+ .phy_cnt = ARRAY_SIZE(dwc3_meson_g12a_phy_names),
+ .clk_init = dwc3_meson_g12a_clk_init,
+};
+
+static const struct dwc3_meson_g12a_drvdata meson_a1_drvdata = {
+ .phy_names = dwc3_meson_a1_phy_names,
+
Re: [PATCH v1 6/8] a1: clk: Add missing CLKID_USB_PHY_IN gate
On 02/10/2023 18:58, Alexey Romanov wrote:
From: Igor Prusov
We use this clock in dwc3 driver.
Signed-off-by: Igor Prusov
---
drivers/clk/meson/a1.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c
index 3aec42f33b..1540e1875b 100644
--- a/drivers/clk/meson/a1.c
+++ b/drivers/clk/meson/a1.c
@@ -238,6 +238,9 @@ static const struct meson_clk_info *meson_clocks[] = {
[CLKID_FIXPLL_IN] = CLK_GATE("fixpll_in", A1_SYS_OSCIN_CTRL, 1,
EXTERNAL_XTAL
),
+ [CLKID_USB_PHY_IN] = CLK_GATE("usb_phy_in", A1_SYS_OSCIN_CTRL, 2,
+ EXTERNAL_XTAL
+ ),
[CLKID_SARADC] = CLK_GATE("saradc", A1_SAR_ADC_CLK_CTR, 8,
-ENOENT
),
Reviewed-by: Neil Armstrong
Re: [PATCH v1 5/8] phy: support Amlogic A1 family
On 02/10/2023 18:58, Alexey Romanov wrote:
Setting G12A and A1 is similar, so we can use G12A phy
driver with little changes.
Signed-off-by: Alexey Romanov
---
drivers/phy/Kconfig | 2 +-
drivers/phy/meson-g12a-usb2.c | 77 ---
2 files changed, 64 insertions(+), 15 deletions(-)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index cf4d5908d7..60be62907d 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -190,7 +190,7 @@ config MESON_GXL_USB_PHY
config MESON_G12A_USB_PHY
bool "Amlogic Meson G12A USB PHYs"
- depends on PHY && ARCH_MESON && MESON_G12A
+ depends on PHY && ARCH_MESON && (MESON_G12A || MESON_A1)
imply REGMAP
help
This is the generic phy driver for the Amlogic Meson G12A
diff --git a/drivers/phy/meson-g12a-usb2.c b/drivers/phy/meson-g12a-usb2.c
index 7b028784a0..c1b9baa7b7 100644
--- a/drivers/phy/meson-g12a-usb2.c
+++ b/drivers/phy/meson-g12a-usb2.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
@@ -146,18 +147,28 @@
#define RESET_COMPLETE_TIME 1000
#define PLL_RESET_COMPLETE_TIME 100
+enum meson_soc_id {
+ MESON_SOC_A1,
+ MESON_SOC_G12A,
+};
+
struct phy_meson_g12a_usb2_priv {
struct regmap *regmap;
#if CONFIG_IS_ENABLED(CLK)
struct clk clk;
#endif
struct reset_ctlreset;
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+ struct power_domain pwrdm;
+#endif
+ int soc_id;
};
static int phy_meson_g12a_usb2_init(struct phy *phy)
{
struct udevice *dev = phy->dev;
struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
+ u32 value;
int ret;
#if CONFIG_IS_ENABLED(CLK)
@@ -196,8 +207,7 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) |
FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9));
- regmap_write(priv->regmap, PHY_CTRL_R18,
- FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
+ value = FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) |
FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) |
FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) |
@@ -209,6 +219,11 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) |
PHY_CTRL_R18_MPLL_ACG_RANGE;
+ if (priv->soc_id == MESON_SOC_A1)
+ value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL;
+
+ regmap_write(priv->regmap, PHY_CTRL_R18, value);
+
udelay(PLL_RESET_COMPLETE_TIME);
/* UnReset PLL */
@@ -231,13 +246,19 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R20_USB2_BGR_VREF_4_0, 0) |
FIELD_PREP(PHY_CTRL_R20_USB2_BGR_DBG_1_0, 0));
- regmap_write(priv->regmap, PHY_CTRL_R4,
- FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
- FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
- FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
- PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
- FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
- FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
+ if (priv->soc_id == MESON_SOC_G12A)
+ regmap_write(priv->regmap, PHY_CTRL_R4,
+ FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
+ FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
+ FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
+ PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
+ FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
+ FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
+ else if (priv->soc_id == MESON_SOC_A1)
+ regmap_write(priv->regmap, PHY_CTRL_R21,
+ PHY_CTRL_R21_USB2_CAL_ACK_EN |
+ PHY_CTRL_R21_USB2_TX_STRG_PD |
+ FIELD_PREP(PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0, 2));
/* Tuning Disconnect Threshold */
regmap_write(priv->regmap, PHY_CTRL_R3,
@@ -246,10 +267,15 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R3_DISC_THRESH, 3));
/* Analog Settings */
- regmap_write(priv->regmap, PHY_CTRL_R14, 0);
- regmap_write(priv->regmap, PHY_CTRL_R13,
- PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
- FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
+ if (priv->soc_id == MESON_SOC_G12A) {
+ regmap_write(priv->regmap, PHY_CTRL_R14, 0);
+ regmap_write(priv->regmap, PHY_CTRL_R13,
+ PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
+ FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET,
Re: [PATCH v1 4/8] phy: move clk enable/disable in init/exit
On 02/10/2023 18:58, Alexey Romanov wrote:
It is better to place clk_enable() in phy_meson_g12a_usb2_init()
and clk_disable() in phy_meson_g12a_usb2_exit().
For more detailed information, please see comments in the review of
a similar driver in the Linux Kernel:
https://lore.kernel.org/all/CAFBinCCEhobbyKHuKDWzTYCQWgNT1-e8=7hmhq1mvt6cueo...@mail.gmail.com/
Signed-off-by: Alexey Romanov
---
drivers/phy/meson-g12a-usb2.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/phy/meson-g12a-usb2.c b/drivers/phy/meson-g12a-usb2.c
index 2e366b16ae..7b028784a0 100644
--- a/drivers/phy/meson-g12a-usb2.c
+++ b/drivers/phy/meson-g12a-usb2.c
@@ -160,6 +160,14 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
int ret;
+#if CONFIG_IS_ENABLED(CLK)
+ ret = clk_enable(>clk);
+ if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+ pr_err("failed to enable PHY clock\n");
+ return ret;
+ }
+#endif
+
ret = reset_assert(>reset);
udelay(1);
ret |= reset_deassert(>reset);
@@ -252,6 +260,10 @@ static int phy_meson_g12a_usb2_exit(struct phy *phy)
struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
int ret;
+#if CONFIG_IS_ENABLED(CLK)
+ clk_disable(>clk);
+#endif
+
ret = reset_assert(>reset);
if (ret)
return ret;
@@ -289,13 +301,6 @@ int meson_g12a_usb2_phy_probe(struct udevice *dev)
ret = clk_get_by_index(dev, 0, >clk);
if (ret < 0)
return ret;
-
- ret = clk_enable(>clk);
- if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
- pr_err("failed to enable PHY clock\n");
- clk_free(>clk);
- return ret;
- }
#endif
return 0;
Reviewed-by: Neil Armstrong
Re: [PATCH v1 3/8] phy: get rid of raw hex values
On 02/10/2023 18:58, Alexey Romanov wrote: It is better to use defines instead of write raw hex values in regmap. Signed-off-by: Alexey Romanov --- drivers/phy/meson-g12a-usb2.c | 161 -- 1 file changed, 153 insertions(+), 8 deletions(-) diff --git a/drivers/phy/meson-g12a-usb2.c b/drivers/phy/meson-g12a-usb2.c index 650b88bd18..2e366b16ae 100644 --- a/drivers/phy/meson-g12a-usb2.c +++ b/drivers/phy/meson-g12a-usb2.c @@ -23,12 +23,28 @@ #include #include +#include #define PHY_CTRL_R0 0x0 #define PHY_CTRL_R1 0x4 #define PHY_CTRL_R2 0x8 + #define PHY_CTRL_R3 0xc + #define PHY_CTRL_R3_SQUELCH_REF GENMASK(1, 0) + #define PHY_CTRL_R3_HSDIC_REF GENMASK(3, 2) + #define PHY_CTRL_R3_DISC_THRESH GENMASK(7, 4) + #define PHY_CTRL_R4 0x10 + #define PHY_CTRL_R4_CALIB_CODE_7_0 GENMASK(7, 0) + #define PHY_CTRL_R4_CALIB_CODE_15_8 GENMASK(15, 8) + #define PHY_CTRL_R4_CALIB_CODE_23_16GENMASK(23, 16) + #define PHY_CTRL_R4_I_C2L_CAL_ENBIT(24) + #define PHY_CTRL_R4_I_C2L_CAL_RESET_N BIT(25) + #define PHY_CTRL_R4_I_C2L_CAL_DONE BIT(26) + #define PHY_CTRL_R4_TEST_BYPASS_MODE_EN BIT(27) + #define PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0 GENMASK(29, 28) + #define PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2 GENMASK(31, 30) + #define PHY_CTRL_R5 0x14 #define PHY_CTRL_R6 0x18 #define PHY_CTRL_R7 0x1c @@ -37,15 +53,93 @@ #define PHY_CTRL_R10 0x28 #define PHY_CTRL_R11 0x2c #define PHY_CTRL_R12 0x30 + #define PHY_CTRL_R13 0x34 + #define PHY_CTRL_R13_CUSTOM_PATTERN_19 GENMASK(7, 0) + #define PHY_CTRL_R13_LOAD_STAT BIT(14) + #define PHY_CTRL_R13_UPDATE_PMA_SIGNALS BIT(15) + #define PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET GENMASK(20, 16) + #define PHY_CTRL_R13_CLEAR_HOLD_HS_DISCONNECT BIT(21) + #define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_VAL BIT(22) + #define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_EN BIT(23) + #define PHY_CTRL_R13_I_C2L_HS_ENBIT(24) + #define PHY_CTRL_R13_I_C2L_FS_ENBIT(25) + #define PHY_CTRL_R13_I_C2L_LS_ENBIT(26) + #define PHY_CTRL_R13_I_C2L_HS_OEBIT(27) + #define PHY_CTRL_R13_I_C2L_FS_OEBIT(28) + #define PHY_CTRL_R13_I_C2L_HS_RX_EN BIT(29) + #define PHY_CTRL_R13_I_C2L_FSLS_RX_EN BIT(30) + #define PHY_CTRL_R14 0x38 #define PHY_CTRL_R15 0x3c + #define PHY_CTRL_R16 0x40 + #define PHY_CTRL_R16_MPLL_M GENMASK(8, 0) + #define PHY_CTRL_R16_MPLL_N GENMASK(14, 10) + #define PHY_CTRL_R16_MPLL_TDC_MODE BIT(20) + #define PHY_CTRL_R16_MPLL_SDM_ENBIT(21) + #define PHY_CTRL_R16_MPLL_LOAD BIT(22) + #define PHY_CTRL_R16_MPLL_DCO_SDM_ENBIT(23) + #define PHY_CTRL_R16_MPLL_LOCK_LONG GENMASK(25, 24) + #define PHY_CTRL_R16_MPLL_LOCK_FBIT(26) + #define PHY_CTRL_R16_MPLL_FAST_LOCK BIT(27) + #define PHY_CTRL_R16_MPLL_ENBIT(28) + #define PHY_CTRL_R16_MPLL_RESET BIT(29) + #define PHY_CTRL_R16_MPLL_LOCK BIT(30) + #define PHY_CTRL_R16_MPLL_LOCK_DIG BIT(31) + #define PHY_CTRL_R17 0x44 + #define PHY_CTRL_R17_MPLL_FRAC_IN GENMASK(13, 0) + #define PHY_CTRL_R17_MPLL_FIX_ENBIT(16) + #define PHY_CTRL_R17_MPLL_LAMBDA1 GENMASK(19, 17) + #define PHY_CTRL_R17_MPLL_LAMBDA0 GENMASK(22, 20) + #define PHY_CTRL_R17_MPLL_FILTER_MODE BIT(23) + #define PHY_CTRL_R17_MPLL_FILTER_PVT2 GENMASK(27, 24) + #define
Re: [PATCH v1 2/8] reset: add support for Amlogic A1 family
On 02/10/2023 18:58, Alexey Romanov wrote:
This patch adds reset support for the Amlogic A1 family.
We add the structure meson_reset_drvdata, which in the future
will allow this driver to be used for other families by declaring
only the correct parameters reg_count and level_offset.
Signed-off-by: Alexey Romanov
---
drivers/reset/reset-meson.c | 42 +++--
1 file changed, 36 insertions(+), 6 deletions(-)
diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
index 64bc696f13..9d0c8b354f 100644
--- a/drivers/reset/reset-meson.c
+++ b/drivers/reset/reset-meson.c
@@ -13,18 +13,26 @@
#include
#include
#include
+#include
-#define REG_COUNT 8
#define BITS_PER_REG 32
-#define LEVEL_OFFSET 0x7c
+
+struct meson_reset_drvdata {
+ unsigned int reg_count;
+ unsigned int level_offset;
+};
struct meson_reset_priv {
struct regmap *regmap;
+ struct meson_reset_drvdata *drvdata;
};
static int meson_reset_request(struct reset_ctl *reset_ctl)
{
- if (reset_ctl->id > (REG_COUNT * BITS_PER_REG))
+ struct meson_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ struct meson_reset_drvdata *data = priv->drvdata;
+
+ if (reset_ctl->id > (data->reg_count * BITS_PER_REG))
return -EINVAL;
return 0;
@@ -33,9 +41,10 @@ static int meson_reset_request(struct reset_ctl *reset_ctl)
static int meson_reset_level(struct reset_ctl *reset_ctl, bool assert)
{
struct meson_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ struct meson_reset_drvdata *data = priv->drvdata;
uint bank = reset_ctl->id / BITS_PER_REG;
uint offset = reset_ctl->id % BITS_PER_REG;
- uint reg_offset = LEVEL_OFFSET + (bank << 2);
+ uint reg_offset = data->level_offset + (bank << 2);
uint val;
regmap_read(priv->regmap, reg_offset, );
@@ -64,15 +73,36 @@ struct reset_ops meson_reset_ops = {
.rst_deassert = meson_reset_deassert,
};
+static const struct meson_reset_drvdata meson_gxbb_data = {
+ .reg_count = 8,
+ .level_offset = 0x7c,
+};
+
+static const struct meson_reset_drvdata meson_a1_data = {
+ .reg_count = 3,
+ .level_offset = 0x40,
+};
+
static const struct udevice_id meson_reset_ids[] = {
- { .compatible = "amlogic,meson-gxbb-reset" },
- { .compatible = "amlogic,meson-axg-reset" },
+ {
+ .compatible = "amlogic,meson-gxbb-reset",
+ .data = (ulong)_gxbb_data,
+ },
+ {
+ .compatible = "amlogic,meson-axg-reset",
+ .data = (ulong)_gxbb_data,
+ },
+ {
+ .compatible = "amlogic,meson-a1-reset",
+ .data = (ulong)_a1_data,
+ },
{ }
};
static int meson_reset_probe(struct udevice *dev)
{
struct meson_reset_priv *priv = dev_get_priv(dev);
+ priv->drvdata = (struct meson_reset_drvdata *)dev_get_driver_data(dev);
return regmap_init_mem(dev_ofnode(dev), >regmap);
}
Reviewed-by: Neil Armstrong
Re: [PATCH v1 1/8] dt-bindings: reset: add Meson A1 reset bindings
On 02/10/2023 18:58, Alexey Romanov wrote: Get this from Linux 6.6-rc3. Signed-off-by: Alexey Romanov --- .../reset/amlogic,meson-a1-reset.h| 76 +++ 1 file changed, 76 insertions(+) create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-reset.h diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h new file mode 100644 index 00..2c749c655e --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-a1-reset.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen + * + * Copyright (c) 2023, SberDevices, Inc. + * Author: Alexey Romanov + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H + +/* RESET0 */ +/* 0 */ +#define RESET_AM2AXI_VAD 1 +/* 2-3 */ +#define RESET_PSRAM4 +#define RESET_PAD_CTRL 5 +/* 6 */ +#define RESET_TEMP_SENSOR 7 +#define RESET_AM2AXI_DEV 8 +/* 9 */ +#define RESET_SPICC_A 10 +#define RESET_MSR_CLK 11 +#define RESET_AUDIO12 +#define RESET_ANALOG_CTRL 13 +#define RESET_SAR_ADC 14 +#define RESET_AUDIO_VAD15 +#define RESET_CEC 16 +#define RESET_PWM_EF 17 +#define RESET_PWM_CD 18 +#define RESET_PWM_AB 19 +/* 20 */ +#define RESET_IR_CTRL 21 +#define RESET_I2C_S_A 22 +/* 23 */ +#define RESET_I2C_M_D 24 +#define RESET_I2C_M_C 25 +#define RESET_I2C_M_B 26 +#define RESET_I2C_M_A 27 +#define RESET_I2C_PROD_AHB 28 +#define RESET_I2C_PROD 29 +/* 30-31 */ + +/* RESET1 */ +#define RESET_ACODEC 32 +#define RESET_DMA 33 +#define RESET_SD_EMMC_A34 +/* 35 */ +#define RESET_USBCTRL 36 +/* 37 */ +#define RESET_USBPHY 38 +/* 39-41 */ +#define RESET_RSA 42 +#define RESET_DMC 43 +/* 44 */ +#define RESET_IRQ_CTRL 45 +/* 46 */ +#define RESET_NIC_VAD 47 +#define RESET_NIC_AXI 48 +#define RESET_RAMA 49 +#define RESET_RAMB 50 +/* 51-52 */ +#define RESET_ROM 53 +#define RESET_SPIFC54 +#define RESET_GIC 55 +#define RESET_UART_C 56 +#define RESET_UART_B 57 +#define RESET_UART_A 58 +#define RESET_OSC_RING 59 +/* 60-63 */ + +/* RESET2 */ +/* 64-95 */ + +#endif Reviewed-by: Neil Armstrong
Re: [PATCH v1 8/8] arch: a1: introduce USB initialization functionality
Hi,
On 02/10/2023 18:58, Alexey Romanov wrote:
This is entrypoint for USB stack initialization. Function
board_usb_init will be called from cmd/fastboot.c code.
This should not be needed anymore, using DM_USB_GADGET should work,
look how it was changed for G12A/SM1 and GXL/AXG:
https://lore.kernel.org/all/20221024-meson-dm-usb-v1-0-2ab077a50...@baylibre.com
and
https://lore.kernel.org/all/20230117-u-boot-usb-gxl-otg-dm-v1-0-2853f6d75...@linaro.org
Neil
Signed-off-by: Alexey Romanov
---
arch/arm/mach-meson/board-a1.c | 89 ++
1 file changed, 89 insertions(+)
diff --git a/arch/arm/mach-meson/board-a1.c b/arch/arm/mach-meson/board-a1.c
index 967bb67182..781d5cfb33 100644
--- a/arch/arm/mach-meson/board-a1.c
+++ b/arch/arm/mach-meson/board-a1.c
@@ -4,12 +4,17 @@
*/
#include
+#include
+#include
#include
#include
#include
#include
#include
#include
+#include
+#include
+#include
phys_size_t get_effective_memsize(void)
{
@@ -57,3 +62,87 @@ static struct mm_region a1_mem_map[] = {
};
struct mm_region *mem_map = a1_mem_map;
+
+#if CONFIG_IS_ENABLED(USB_DWC3_MESON_G12A) && \
+ CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
+
+static struct dwc2_plat_otg_data meson_a1_dwc2_data;
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int node, dwc2_node;
+ const void *blob = gd->fdt_blob;
+ struct udevice *dev;
+ int ret;
+
+ node = fdt_node_offset_by_compatible(blob, -1,
+"amlogic,meson-a1-usb-ctrl");
+ if (node < 0) {
+ pr_err("not found usb-control node\n");
+ return -ENODEV;
+ }
+
+ if (!fdtdec_get_is_enabled(blob, node)) {
+ pr_err("usb is disabled in the device tree\n");
+ return -ENODEV;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, );
+ if (ret) {
+ pr_err("not found usb-control device\n");
+ return ret;
+ }
+
+ dwc2_node = fdt_node_offset_by_compatible(blob, node,
+ "amlogic,meson-a1-usb");
+ if (dwc2_node < 0) {
+ pr_err("not found dwc2 node\n");
+ return -ENODEV;
+ }
+
+ if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
+ pr_err("dwc2 is disabled in the device tree\n");
+ return -ENODEV;
+ }
+
+ meson_a1_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
+ if (meson_a1_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
+ pr_err("can't get base address\n");
+ return -ENODATA;
+ }
+
+ meson_a1_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
+ "g-rx-fifo-size", 0);
+ if (meson_a1_dwc2_data.rx_fifo_sz < 0) {
+ pr_err("failed to get g-rx-fifo-size value\n");
+ return -ENODATA;
+ }
+
+ meson_a1_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
+ "g-np-tx-fifo-size", 0);
+ if (meson_a1_dwc2_data.np_tx_fifo_sz < 0) {
+ pr_err("failed to get g-np-tx-fifo-size value\n");
+ return -ENODATA;
+ }
+
+ meson_a1_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
+ "g-tx-fifo-size", 0);
+ if (meson_a1_dwc2_data.tx_fifo_sz < 0) {
+ pr_err("failed to get g-tx-fifo-size value\n");
+ return -ENODATA;
+ }
+
+ ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_PERIPHERAL);
+ if (ret) {
+ pr_err("failed to force usb mode to peripheral\n");
+ return ret;
+ }
+
+ return dwc2_udc_probe(_a1_dwc2_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ return 0;
+}
+#endif
[PATCH] mmc: sdhci-cadence: Add support for Cadence sdmmc v6
From: Kuan Lim Lee
Cadence SDMMC v6 controller has a lot of changes on initialize
compared to v4 controller. PHY is needed by v6 controller.
Signed-off-by: Kuan Lim Lee
Reviewed-by: Alex Soo
Reviewed-by: Wei Liang Lim
---
drivers/mmc/Kconfig | 13 ++
drivers/mmc/Makefile | 1 +
drivers/mmc/sdhci-cadence.c | 63 ++-
drivers/mmc/sdhci-cadence.h | 68 +++
drivers/mmc/sdhci-cadence6-phy.c | 302 +++
5 files changed, 396 insertions(+), 51 deletions(-)
create mode 100644 drivers/mmc/sdhci-cadence.h
create mode 100644 drivers/mmc/sdhci-cadence6-phy.c
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index de01b9687b..cec881d862 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -573,6 +573,19 @@ config MMC_SDHCI_CADENCE
If unsure, say N.
+config MMC_SDHCI_CADENCE_V6
+ bool "SDHCI support for the Cadence SD/SDIO/eMMC controller & driver
version 6"
+ depends on BLK && DM_MMC
+ depends on MMC_SDHCI
+ depends on OF_CONTROL
+ select MMC_SDHCI_CADENCE
+ help
+ This selects the Cadence SD/SDIO/eMMC driver version 6.
+
+ If you have a controller with this interface, say Y here.
+
+ If unsure, say N.
+
config MMC_SDHCI_AM654
bool "SDHCI Controller on TI's Am654 devices"
depends on ARCH_K3
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 2c65c4765a..cdcce55b8b 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_MMC_SDHCI_ATMEL) += atmel_sdhci.o
obj-$(CONFIG_MMC_SDHCI_BCM2835)+= bcm2835_sdhci.o
obj-$(CONFIG_MMC_SDHCI_BCMSTB) += bcmstb_sdhci.o
obj-$(CONFIG_MMC_SDHCI_CADENCE)+= sdhci-cadence.o
+obj-$(CONFIG_MMC_SDHCI_CADENCE_V6) += sdhci-cadence6-phy.o
obj-$(CONFIG_MMC_SDHCI_AM654) += am654_sdhci.o
obj-$(CONFIG_MMC_SDHCI_IPROC) += iproc_sdhci.o
obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o
diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c
index 327a05ad11..d7a270e74c 100644
--- a/drivers/mmc/sdhci-cadence.c
+++ b/drivers/mmc/sdhci-cadence.c
@@ -17,56 +17,7 @@
#include
#include
#include
-
-/* HRS - Host Register Set (specific to Cadence) */
-#define SDHCI_CDNS_HRS04 0x10/* PHY access port */
-#define SDHCI_CDNS_HRS04_ACK BIT(26)
-#define SDHCI_CDNS_HRS04_RD BIT(25)
-#define SDHCI_CDNS_HRS04_WR BIT(24)
-#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)
-#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)
-#define SDHCI_CDNS_HRS04_ADDRGENMASK(5, 0)
-
-#define SDHCI_CDNS_HRS06 0x18/* eMMC control */
-#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
-#define SDHCI_CDNS_HRS06_TUNEGENMASK(13, 8)
-#define SDHCI_CDNS_HRS06_MODEGENMASK(2, 0)
-#define SDHCI_CDNS_HRS06_MODE_SD 0x0
-#define SDHCI_CDNS_HRS06_MODE_MMC_SDR0x2
-#define SDHCI_CDNS_HRS06_MODE_MMC_DDR0x3
-#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4
-#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
-#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES0x6
-
-/* SRS - Slot Register Set (SDHCI-compatible) */
-#define SDHCI_CDNS_SRS_BASE0x200
-
-/* PHY */
-#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
-#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
-#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
-#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
-#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
-#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
-#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
-#define SDHCI_CDNS_PHY_DLY_EMMC_SDR0x07
-#define SDHCI_CDNS_PHY_DLY_EMMC_DDR0x08
-#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b
-#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c
-#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d
-
-/*
- * The tuned val register is 6 bit-wide, but not the whole of the range is
- * available. The range 0-42 seems to be available (then 43 wraps around to 0)
- * but I am not quite sure if it is official. Use only 0 to 39 for safety.
- */
-#define SDHCI_CDNS_MAX_TUNING_LOOP 40
-
-struct sdhci_cdns_plat {
- struct mmc_config cfg;
- struct mmc mmc;
- void __iomem *hrs_addr;
-};
+#include "sdhci-cadence.h"
struct sdhci_cdns_phy_cfg {
const char *property;
@@ -112,8 +63,11 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat
*plat,
}
static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat,
- const void *fdt, int nodeoffset)
+ const void *fdt, int nodeoffset)
{
+ if (IS_ENABLED(CONFIG_MMC_SDHCI_CADENCE_V6))
+ return sdhci_cdns6_phy_init(plat, SDHCI_CDNS_HRS06_MODE_SD);
+
const fdt32_t *prop;
int ret, i;
@@ -163,6 +117,9 @@
