Re: [PATCH] watchdog: Correct watchdog timeout print message
On 11/27/23 02:05, Chanho Park wrote:
The wdt_start function takes timeout_ms as a parameter and starts the
watchdog with this value. However, when you output the message, it shows
the default timeout value for the watchdog device.
So this patch fixes that part to output the correct timeout value.
Before -->
StarFive # wdt start 3000
WDT: Started watchdog@1307 without servicing (60s timeout)
After -->
StarFive # wdt start 3000
WDT: Started watchdog@1307 without servicing (3s timeout)
Fixes: c2fd0ca1a822 ("watchdog: Integrate watchdog triggering into the cyclic
framework")
Signed-off-by: Chanho Park
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/watchdog/wdt-uclass.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c
index ed329284decb..65a4bc1f90ed 100644
--- a/drivers/watchdog/wdt-uclass.c
+++ b/drivers/watchdog/wdt-uclass.c
@@ -141,7 +141,7 @@ int wdt_start(struct udevice *dev, u64 timeout_ms, ulong
flags)
printf("WDT: Started %s with%s servicing %s (%ds timeout)\n",
dev->name, IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out",
- str, priv->timeout);
+ str, (u32)(timeout_ms / 1000));
}
return ret;
Viele Grüße,
Stefan Roese
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
[PATCH v2] arm: apple: t602x: Add missing MMIO regions to memmap
From: Janne Grunau
The memory maps for Apple's M2 Pro/Max/Ultra left MMIO space out which
was not used by any driver at the time. The display out exposed as
simple-framebuffer use a power-domain controlled by a device in an
unmapped region.
Add a map covering this region as well as another MMIO region in the
range 0x4'' - 0x5''. The added regions cover all MMIO
annotated in Apple's device tree in this range.
Signed-off-by: Janne Grunau
---
Changes in v2:
- use SZ_1G as block size
- Link to v1:
https://lore.kernel.org/r/20231130-apple_t602x_extend_memmap-v1-1-cd96b251d...@jannau.net
---
arch/arm/mach-apple/board.c | 48 +
1 file changed, 48 insertions(+)
diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c
index 47393babbc..7a6151a972 100644
--- a/arch/arm/mach-apple/board.c
+++ b/arch/arm/mach-apple/board.c
@@ -370,6 +370,22 @@ static struct mm_region t6020_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x4,
+ .phys = 0x4,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x48000,
+ .phys = 0x48000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x58000,
@@ -471,6 +487,22 @@ static struct mm_region t6022_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x4,
+ .phys = 0x4,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x48000,
+ .phys = 0x48000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x58000,
@@ -551,6 +583,22 @@ static struct mm_region t6022_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x24,
+ .phys = 0x24,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x248000,
+ .phys = 0x248000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x258000,
---
base-commit: 43f2873fa98b1da6eb56d756315c7bd7db63db27
change-id: 20231130-apple_t602x_extend_memmap-c82c522ca8c0
Best regards,
--
Janne Grunau
Re: [PATCH 1/4] tools: mkeficapsule: Add support for parsing capsule params from config file
hi Simon, On Thu, 30 Nov 2023 at 08:16, Simon Glass wrote: > > Hi Sughosh, > > On Wed, 22 Nov 2023 at 00:40, Sughosh Ganu wrote: > > > > hi Ilias, > > > > On Wed, 22 Nov 2023 at 13:06, Ilias Apalodimas > > wrote: > > > > > > Hi all, > > > > > > On Wed, 22 Nov 2023 at 07:23, Sughosh Ganu > > > wrote: > > > > > > > > hi Simon, > > > > > > > > On Wed, 22 Nov 2023 at 03:42, Simon Glass wrote: > > > > > > > > > > Hi Sughosh, > > > > > > > > > > On Tue, 21 Nov 2023 at 00:02, Sughosh Ganu > > > > > wrote: > > > > > > > > > > > > Add support for specifying the parameters needed for capsule > > > > > > generation through a config file, instead of passing them through > > > > > > command-line. Parameters for more than a single capsule file can be > > > > > > specified, resulting in generation of multiple capsules through a > > > > > > single invocation of the command. > > > > > > > > > > > > The config file can then be passed to the mkeficapsule tool in such > > > > > > manner > > > > > > > > > > > > $ ./tools/mkeficapsule -f > > > > > > > > > > > > Signed-off-by: Sughosh Ganu > > > > > > --- > > > > > > tools/Kconfig | 15 ++ > > > > > > tools/Makefile | 1 + > > > > > > tools/eficapsule.h | 114 > > > > > > tools/mkeficapsule.c | 87 + > > > > > > tools/mkeficapsule_parse.c | 352 > > > > > > + > > > > > > 5 files changed, 538 insertions(+), 31 deletions(-) > > > > > > create mode 100644 tools/mkeficapsule_parse.c > > > > > > > > > > This patch keeps coming back :-) > > > > > > > > > > Can we not add multiple capsules in the binman description? Why do we > > > > > need a new file format? How can binman decode images produced in this > > > > > way? > > > > > > > > So as Tom mentions, this brings parity with respect to the other > > > > capsule generation tool in EDKII that generates capsules. IIRC, this > > > > is something which even Xilix was interested in, and Michal had kind > > > > of gone through these patches earlier. Lastly, it would be good to > > > > have support in U-Boot's mkeficapsule tool for generating a single > > > > capsule file with multiple payloads, and having support for this > > > > functionality helps in that goal. > > > > > > > > Also, you might have noticed that, since your objection to the last > > > > series, I have removed putting this in binman. So now, this aspect of > > > > the capsule generation would only be supported through the > > > > command-line invocation of the tool. > > > > > > I think that overall the approach is sane. mkeficapsule is currently > > > supported and compiled for distros, so the multiple payload support is > > > useful. If we want to add support to binman, instead of rewriting this > > > in python, we could just call that tool for parsing and creating > > > capsules > > > > Given the amount of time these patches have been under review(also > > number of iterations), I would request that this series be reviewed > > and merged first. I think there is general consensus that there is > > value to have this functionality in the mkeficapsule tool. If it is > > deemed fit to support this through binman as well, that task can be > > taken up separately. Thanks. > > The point you are missing is that it is the entire goal of 'skirting > around' binman which is suspect. > > If there is a need to generate an output file from the build, we > should support it in binman. If people start creating configuration > files all over the place, then they are not using binman, right? > > I understand that there are pre-existing vendor-specific config files, > etc. that the EFI thing is a grey area, but I cannot imagine that this > patch would lead to a good outcome. > > The goal of binman is to bring order to the chaos of firmware > packaging...we cannot do that if it is not actually used. > > So let's figure out what is missing from binman's capsule generation > (multiple capsules? accept/reject capsules?) and how best to add it. I think I need to jog your memory back a bit. For context, I have jotted down the points. * The mkeficapsule tool generates capsules in U-Boot. * Currently, when the tool is invoked from the command-line, the capsules are generated by passing the capsule parameters as cmd-line options. * I had earlier added support for generating the capsules as part of U-Boot build, through binman. This support has been merged. * I had followed these patches up with another series [1] which generates capsules by parsing the capsule parameters through a config file instead of cmd-line options. * This series also had patches which were attempting to integrate this functionality into binman [2]. * As part of reviewing the patch series, you had objected to adding this support in binman, primarily because this way of specifying the capsule parameters goes against the normal way of image description in binman [3]. * I have described in this mail thread about
Re: [PATCH v5 12/17] arm: dts: Introduce j784s4 u-boot dts files
Hi Andrew,
On 09:11-20231130, Andrew Davis wrote:
> On 11/30/23 5:55 AM, Apurva Nandan wrote:
> > Introduce the base dts files needed for u-boot or to augment the linux
> > dtbs for use in the u-boot-spl and u-boot binaries.
> >
> > Signed-off-by: Hari Nagalla
> > [ add binman and ddr dtsi files ]
> > Signed-off-by: Neha Malcom Francis
> > Signed-off-by: Dasnavis Sabiya
> > Signed-off-by: Apurva Nandan
> > ---
> > arch/arm/dts/Makefile|3 +-
> > arch/arm/dts/k3-j784s4-binman.dtsi | 346 +
> > arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi | 8757 +
> > arch/arm/dts/k3-j784s4-ddr.dtsi | 8858 ++
> > arch/arm/dts/k3-j784s4-evm-u-boot.dtsi | 25 +
> > arch/arm/dts/k3-j784s4-r5-evm.dts| 105 +
> > 6 files changed, 18093 insertions(+), 1 deletion(-)
> > create mode 100644 arch/arm/dts/k3-j784s4-binman.dtsi
> > create mode 100644 arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
> > create mode 100644 arch/arm/dts/k3-j784s4-ddr.dtsi
> > create mode 100644 arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
> > create mode 100644 arch/arm/dts/k3-j784s4-r5-evm.dts
> >
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index 1a63ccba8e..b73f8a9230 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -1409,7 +1409,8 @@ dtb-$(CONFIG_SOC_K3_J721S2) +=
> > k3-am68-sk-base-board.dtb\
> >k3-j721s2-common-proc-board.dtb\
> >k3-j721s2-r5-common-proc-board.dtb
> > dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-sk.dtb\
> > - k3-j784s4-evm.dtb
> > + k3-j784s4-evm.dtb\
> > + k3-j784s4-r5-evm.dtb
> > dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
> > k3-am642-r5-evm.dtb \
> > k3-am642-sk.dtb \
> > diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi
> > b/arch/arm/dts/k3-j784s4-binman.dtsi
> > new file mode 100644
> > index 00..7349c2ba38
> > --- /dev/null
> > +++ b/arch/arm/dts/k3-j784s4-binman.dtsi
> > @@ -0,0 +1,346 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
> > + */
> > +
> > +#include "k3-binman.dtsi"
> > +
> > +#ifdef CONFIG_TARGET_J784S4_R5_EVM
> > +
> > +_yaml_tifs {
> > + config = "tifs-rm-cfg.yaml";
> > +};
> > +
> > + {
> > + tiboot3-j784s4-hs-evm.bin {
> > + filename = "tiboot3-j784s4-hs-evm.bin";
> > +
> > + ti-secure-rom {
> > + content = <_boot_spl>, <_fs_enc>,
> > <_tifs_cfg>,
> > + <_dm_cfg>, <_inner_cert>;
> > + combined;
> > + dm-data;
> > + sysfw-inner-cert;
> > + keyfile = "custMpk.pem";
> > + sw-rev = <1>;
> > + content-sbl = <_boot_spl>;
> > + content-sysfw = <_fs_enc>;
> > + content-sysfw-data = <_tifs_cfg>;
> > + content-sysfw-inner-cert = <_inner_cert>;
> > + content-dm-data = <_dm_cfg>;
> > + load = <0x41c0>;
> > + load-sysfw = <0x4>;
> > + load-sysfw-data = <0x66800>;
> > + load-dm-data = <0x41c8>;
> > + };
> > +
> > + u_boot_spl: u-boot-spl {
> > + no-expanded;
> > + };
> > +
> > + ti_fs_enc: ti-fs-enc.bin {
> > + filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin";
> > + type = "blob-ext";
> > + optional;
> > + };
> > +
> > + combined_tifs_cfg: combined-tifs-cfg.bin {
> > + filename = "combined-tifs-cfg.bin";
> > + type = "blob-ext";
> > + };
> > +
> > + sysfw_inner_cert: sysfw-inner-cert {
> > + filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin";
> > + type = "blob-ext";
> > + optional;
> > + };
&
[PATCH v5 4/6] spi: spi-uclass: Read chipselect and restrict capabilities
From: Ashok Reddy Soma
Read chipselect properties from DT which are populated using 'reg'
property and save it in plat->cs[] array for later use.
Also read multi chipselect capability which is used for
parallel-memories and return errors if they are passed on using DT but
driver is not capable of handling it.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/mtd/spi/sandbox.c| 2 +-
drivers/spi/altera_spi.c | 4 ++--
drivers/spi/atcspi200_spi.c | 2 +-
drivers/spi/ath79_spi.c | 2 +-
drivers/spi/atmel_spi.c | 6 +++---
drivers/spi/bcm63xx_hsspi.c | 42 ++--
drivers/spi/bcm63xx_spi.c| 6 +++---
drivers/spi/bcmbca_hsspi.c | 34 ++---
drivers/spi/cf_spi.c | 6 +++---
drivers/spi/davinci_spi.c| 6 +++---
drivers/spi/fsl_dspi.c | 18
drivers/spi/fsl_espi.c | 4 ++--
drivers/spi/fsl_qspi.c | 4 ++--
drivers/spi/gxp_spi.c| 2 +-
drivers/spi/mpc8xx_spi.c | 4 ++--
drivers/spi/mpc8xxx_spi.c| 10 -
drivers/spi/mscc_bb_spi.c| 4 ++--
drivers/spi/mxc_spi.c| 6 +++---
drivers/spi/npcm_fiu_spi.c | 14 ++--
drivers/spi/nxp_fspi.c | 2 +-
drivers/spi/octeon_spi.c | 2 +-
drivers/spi/omap3_spi.c | 4 ++--
drivers/spi/pic32_spi.c | 2 +-
drivers/spi/rk_spi.c | 4 ++--
drivers/spi/rockchip_sfc.c | 2 +-
drivers/spi/spi-aspeed-smc.c | 28
drivers/spi/spi-mxic.c | 6 +++---
drivers/spi/spi-qup.c| 4 ++--
drivers/spi/spi-sifive.c | 6 +++---
drivers/spi/spi-sn-f-ospi.c | 2 +-
drivers/spi/spi-sunxi.c | 6 +++---
drivers/spi/spi-synquacer.c | 4 ++--
drivers/spi/spi-uclass.c | 23 +++-
drivers/spi/stm32_qspi.c | 2 +-
drivers/spi/stm32_spi.c | 4 ++--
drivers/spi/ti_qspi.c| 14 ++--
drivers/spi/xilinx_spi.c | 4 ++--
drivers/spi/zynq_qspi.c | 6 +++---
drivers/spi/zynq_spi.c | 6 +++---
include/spi.h| 8 ++-
lib/acpi/acpi_device.c | 2 +-
41 files changed, 168 insertions(+), 149 deletions(-)
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index 4fe547171a..72036d5a88 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -139,7 +139,7 @@ static int sandbox_sf_probe(struct udevice *dev)
return ret;
}
slave_plat = dev_get_parent_plat(dev);
- cs = slave_plat->cs;
+ cs = slave_plat->cs[0];
debug("found at cs %d\n", cs);
if (!pdata->filename) {
diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c
index 989679e881..48782f81c1 100644
--- a/drivers/spi/altera_spi.c
+++ b/drivers/spi/altera_spi.c
@@ -96,7 +96,7 @@ static int altera_spi_xfer(struct udevice *dev, unsigned int
bitlen,
uint32_t reg, data, start;
debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
- dev_seq(bus), slave_plat->cs, bitlen, bytes, flags);
+ dev_seq(bus), slave_plat->cs[0], bitlen, bytes, flags);
if (bitlen == 0)
goto done;
@@ -111,7 +111,7 @@ static int altera_spi_xfer(struct udevice *dev, unsigned
int bitlen,
readl(>rxdata);
if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(dev, slave_plat->cs);
+ spi_cs_activate(dev, slave_plat->cs[0]);
while (bytes--) {
if (txp)
diff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c
index de9c14837c..acee743653 100644
--- a/drivers/spi/atcspi200_spi.c
+++ b/drivers/spi/atcspi200_spi.c
@@ -321,7 +321,7 @@ static int atcspi200_spi_claim_bus(struct udevice *dev)
struct udevice *bus = dev->parent;
struct nds_spi_slave *ns = dev_get_priv(bus);
- if (slave_plat->cs >= ns->num_cs) {
+ if (slave_plat->cs[0] >= ns->num_cs) {
printf("Invalid SPI chipselect\n");
return -EINVAL;
}
diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c
index 205567ef54..ad10cec2a6 100644
--- a/drivers/spi/ath79_spi.c
+++ b/drivers/spi/ath79_spi.c
@@ -74,7 +74,7 @@ static int ath79_spi_xfer(struct udevice *dev, unsigned int
bitlen,
if (restbits)
bytes++;
- out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs));
+ out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs[0]));
while (bytes > 0) {
bytes--;
curbyte = 0;
diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index aec6f4eca9..e2de39d1ef 100644
--- a/drivers/spi/atmel_spi.c
+++ b/drivers/spi/atmel_spi.c
@@ -126,7 +126,7 @@ static int atmel_spi_claim_bus(struct udevice *dev)
struct atmel_spi_priv *priv = dev_get_priv(bus);
struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
struct at91_spi
[PATCH v5 5/6] spi: zynqmp_gqspi: Add parallel memories support in GQSPI driver
Add support for parallel memories in zynqmp_gqspi.c driver. In case of
parallel memories STRIPE bit is set and sent to the qspi ip, which will
send data bits to both the flashes in parallel. However for few commands
we should not use stripe, instead send same data to both the flashes.
Those commands are exclueded by using zynqmp_qspi_update_stripe().
Also update copyright info for this file.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/spi/zynqmp_gqspi.c | 141 -
include/spi.h | 4 ++
2 files changed, 129 insertions(+), 16 deletions(-)
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index a323994fb2..20e9914ea2 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2018 Xilinx
- *
+ * (C) Copyright 2013 - 2022, Xilinx, Inc.
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
* Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only)
*/
@@ -25,6 +25,8 @@
#include
#include
#include
+#include
+#include "../mtd/spi/sf_internal.h"
#include
#define GQSPI_GFIFO_STRT_MODE_MASK BIT(29)
@@ -88,6 +90,9 @@
#define SPI_XFER_ON_LOWER 1
#define SPI_XFER_ON_UPPER 2
+#define GQSPI_SELECT_LOWER_CS BIT(0)
+#define GQSPI_SELECT_UPPER_CS BIT(1)
+
#define GQSPI_DMA_ALIGN0x4
#define GQSPI_MAX_BAUD_RATE_VAL7
#define GQSPI_DFLT_BAUD_RATE_VAL 2
@@ -183,13 +188,14 @@ struct zynqmp_qspi_priv {
int bytes_to_transfer;
int bytes_to_receive;
const struct spi_mem_op *op;
+ unsigned int is_parallel;
+ unsigned int u_page;
+ unsigned int bus;
+ unsigned int stripe;
+ unsigned int flags;
+ u32 max_hz;
};
-__weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32
value)
-{
- return 0;
-}
-
static int zynqmp_qspi_of_to_plat(struct udevice *bus)
{
struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
@@ -234,8 +240,30 @@ static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv
*priv)
{
u32 gqspi_fifo_reg = 0;
- gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
-GQSPI_GFIFO_CS_LOWER;
+ if (priv->is_parallel) {
+ if (priv->bus == SPI_XFER_ON_BOTH)
+ gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
+GQSPI_GFIFO_UP_BUS |
+GQSPI_GFIFO_CS_UPPER |
+GQSPI_GFIFO_CS_LOWER;
+ else if (priv->bus == SPI_XFER_ON_LOWER)
+ gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
+GQSPI_GFIFO_CS_UPPER |
+GQSPI_GFIFO_CS_LOWER;
+ else if (priv->bus == SPI_XFER_ON_UPPER)
+ gqspi_fifo_reg = GQSPI_GFIFO_UP_BUS |
+GQSPI_GFIFO_CS_LOWER |
+GQSPI_GFIFO_CS_UPPER;
+ else
+ debug("Wrong Bus selection:0x%x\n", priv->bus);
+ } else {
+ if (priv->u_page)
+ gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
+GQSPI_GFIFO_CS_UPPER;
+ else
+ gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
+GQSPI_GFIFO_CS_LOWER;
+ }
return gqspi_fifo_reg;
}
@@ -295,8 +323,15 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv
*priv, int is_on)
gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI |
GQSPI_IMD_DATA_CS_ASSERT;
} else {
- gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS;
- gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT;
+ if (priv->is_parallel)
+ gqspi_fifo_reg = GQSPI_GFIFO_UP_BUS |
+GQSPI_GFIFO_LOW_BUS;
+ else if (priv->u_page)
+ gqspi_fifo_reg = GQSPI_GFIFO_UP_BUS;
+ else {
+ gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS;
+ gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT;
+ }
}
zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
@@ -366,12 +401,13 @@ static int zynqmp_qspi_set_speed(struct udevice *bus,
uint speed)
log_debug("%s, Speed: %d, Max: %d\n", __func__, speed, plat->frequency);
- if (speed > plat->frequency)
- speed = plat->frequency;
+ /*
+* If speed == 0 or speed > max freq, then set speed to highest
+*/
+ if (!speed || speed > priv->max_hz)
+ speed = priv->max_hz;
if (plat->speed_hz != speed) {
- /* Set the clock
[PATCH v5 6/6] spi: zynq_qspi: Add parallel memories support in QSPI driver
Add support for parallel memories in zynq_qspi.c driver. In case of
parallel memories STRIPE bit is set and sent to the qspi ip, which will
send data bits to both the flashes in parallel. However for few commands
we should not use stripe, instead send same data to both the flashes.
Those commands are exclueded by using zynqmp_qspi_update_stripe().
Also update copyright info for this file.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/spi/zynq_qspi.c | 114
1 file changed, 103 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 069d2a77de..90c94b1393 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -1,7 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2013 Xilinx, Inc.
+ * (C) Copyright 2013 - 2022, Xilinx, Inc.
* (C) Copyright 2015 Jagan Teki
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
*
* Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
*/
@@ -13,10 +14,12 @@
#include
#include
#include
+#include
#include
#include
#include
#include
+#include "../mtd/spi/sf_internal.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -42,6 +45,21 @@ DECLARE_GLOBAL_DATA_PTR;
#define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80/* Transmit 1-byte inst */
#define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84/* Transmit 2-byte inst */
#define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88/* Transmit 3-byte inst */
+#define ZYNQ_QSPI_FR_QOUT_CODE 0x6B/* read instruction code */
+
+#define QSPI_SELECT_LOWER_CSBIT(0)
+#define QSPI_SELECT_UPPER_CSBIT(1)
+
+/*
+ * QSPI Linear Configuration Register
+ *
+ * It is named Linear Configuration but it controls other modes when not in
+ * linear mode also.
+ */
+#define ZYNQ_QSPI_LCFG_TWO_MEM_MASK 0x4000 /* QSPI Enable Bit Mask */
+#define ZYNQ_QSPI_LCFG_SEP_BUS_MASK 0x2000 /* QSPI Enable Bit Mask */
+#define ZYNQ_QSPI_LCFG_U_PAGE 0x1000 /* QSPI Upper memory set */
+#define ZYNQ_QSPI_LCFG_DUMMY_SHIFT 8
#define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/
#define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */
@@ -101,7 +119,11 @@ struct zynq_qspi_priv {
int bytes_to_transfer;
int bytes_to_receive;
unsigned int is_inst;
+ unsigned int is_parallel;
+ unsigned int is_stacked;
+ unsigned int u_page;
unsigned cs_change:1;
+ unsigned is_strip:1;
};
static int zynq_qspi_of_to_plat(struct udevice *bus)
@@ -112,7 +134,6 @@ static int zynq_qspi_of_to_plat(struct udevice *bus)
plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
node, "reg");
-
return 0;
}
@@ -147,6 +168,9 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
/* Disable Interrupts */
writel(ZYNQ_QSPI_IXR_ALL_MASK, >idr);
+ /* Disable linear mode as the boot loader may have used it */
+ writel(0x0, >lqspicfg);
+
/* Clear the TX and RX threshold reg */
writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, >txftr);
writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, >rxftr);
@@ -164,12 +188,11 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
ZYNQ_QSPI_CR_MSTREN_MASK;
- writel(confr, >cr);
- /* Disable the LQSPI feature */
- confr = readl(>lqspicfg);
- confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
- writel(confr, >lqspicfg);
+ if (priv->is_stacked)
+ confr |= 0x10;
+
+ writel(confr, >cr);
/* Enable SPI */
writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, >enr);
@@ -181,6 +204,7 @@ static int zynq_qspi_child_pre_probe(struct udevice *bus)
struct zynq_qspi_priv *priv = dev_get_priv(bus->parent);
priv->max_hz = slave->max_hz;
+ slave->multi_cs_cap = true;
return 0;
}
@@ -363,8 +387,8 @@ static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv
*priv, u32 size)
unsigned len, offset;
struct zynq_qspi_regs *regs = priv->regs;
static const unsigned offsets[4] = {
- ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
- ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };
+ ZYNQ_QSPI_TXD_00_01_OFFSET, ZYNQ_QSPI_TXD_00_10_OFFSET,
+ ZYNQ_QSPI_TXD_00_11_OFFSET, ZYNQ_QSPI_TXD_00_00_OFFSET };
while ((fifocount < size) &&
(priv->bytes_to_transfer > 0)) {
@@ -386,7 +410,11 @@ static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv
*priv, u32 size)
return;
len = priv->bytes_to_transfer;
zynq_qspi_write_data(priv, , len);
-
[PATCH v5 3/6] mtd: spi-nor: Add parallel and stacked memories support in read_bar and write_bar
From: Ashok Reddy Soma
Add support for parallel memories and stacked memories configuration
in read_bar and write_bar functions.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/mtd/spi/spi-nor-core.c | 55 +-
1 file changed, 47 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 0e29b3020c..5c3ffc80eb 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -885,12 +885,32 @@ static int clean_bar(struct spi_nor *nor)
static int write_bar(struct spi_nor *nor, u32 offset)
{
- u8 cmd, bank_sel;
+ u8 cmd, bank_sel, upage_curr;
int ret;
+ struct mtd_info *mtd = >mtd;
+
+ /* Wait until previous write command is finished */
+ if (spi_nor_wait_till_ready(nor))
+ return 1;
+
+ if (nor->flags & (SNOR_F_HAS_PARALLEL | SNOR_F_HAS_STACKED) &&
+ mtd->size <= SZ_32M)
+ return 0;
+
+ if (mtd->size <= SZ_16M)
+ return 0;
+
+ offset = offset % (u32)mtd->size;
+ bank_sel = offset >> 24;
- bank_sel = offset / SZ_16M;
- if (bank_sel == nor->bank_curr)
- goto bar_end;
+ upage_curr = nor->spi->flags & SPI_XFER_U_PAGE;
+
+ if (!(nor->flags & SNOR_F_HAS_STACKED) && bank_sel == nor->bank_curr)
+ return 0;
+ else if (upage_curr == nor->upage_prev && bank_sel == nor->bank_curr)
+ return 0;
+ else
+ nor->upage_prev = upage_curr;
cmd = nor->bank_write_cmd;
write_enable(nor);
@@ -900,15 +920,19 @@ static int write_bar(struct spi_nor *nor, u32 offset)
return ret;
}
-bar_end:
nor->bank_curr = bank_sel;
- return nor->bank_curr;
+
+ return write_disable(nor);
}
static int read_bar(struct spi_nor *nor, const struct flash_info *info)
{
u8 curr_bank = 0;
int ret;
+ struct mtd_info *mtd = >mtd;
+
+ if (mtd->size <= SZ_16M)
+ return 0;
switch (JEDEC_MFR(info)) {
case SNOR_MFR_SPANSION:
@@ -920,15 +944,30 @@ static int read_bar(struct spi_nor *nor, const struct
flash_info *info)
nor->bank_write_cmd = SPINOR_OP_WREAR;
}
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ nor->spi->flags |= SPI_XFER_LOWER;
+
ret = nor->read_reg(nor, nor->bank_read_cmd,
- _bank, 1);
+ _bank, 1);
if (ret) {
debug("SF: fail to read bank addr register\n");
return ret;
}
nor->bank_curr = curr_bank;
- return 0;
+ // Make sure both chips use the same BAR
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ write_enable(nor);
+ ret = nor->write_reg(nor, nor->bank_write_cmd, _bank, 1);
+ if (ret)
+ return ret;
+
+ ret = write_disable(nor);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
}
#endif
--
2.25.1
[PATCH v5 2/6] mtd: spi-nor: Add parallel memories support for read_sr and read_fsr
From: Ashok Reddy Soma
Add support for parallel memories flash configuration in read status
register and read flag status register functions.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/mtd/spi/spi-nor-core.c | 50 --
1 file changed, 36 insertions(+), 14 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 4e2d8c8231..0e29b3020c 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -438,8 +438,9 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor,
loff_t to, size_t len,
}
/*
- * Read the status register, returning its value in the location
- * Return the status register value.
+ * Return the status register value. If the chip is parallel, then the
+ * read will be striped, so we should read 2 bytes to get the sr
+ * register value from both of the parallel chips.
* Returns negative if error occurred.
*/
static int read_sr(struct spi_nor *nor)
@@ -471,18 +472,29 @@ static int read_sr(struct spi_nor *nor)
if (spi_nor_protocol_is_dtr(nor->reg_proto))
op.data.nbytes = 2;
- ret = spi_nor_read_write_reg(nor, , val);
- if (ret < 0) {
- pr_debug("error %d reading SR\n", (int)ret);
- return ret;
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ op.data.nbytes = 2;
+ ret = spi_nor_read_write_reg(nor, , [0]);
+ if (ret < 0) {
+ pr_debug("error %d reading SR\n", (int)ret);
+ return ret;
+ }
+ val[0] |= val[1];
+ } else {
+ ret = spi_nor_read_write_reg(nor, , [0]);
+ if (ret < 0) {
+ pr_debug("error %d reading SR\n", (int)ret);
+ return ret;
+ }
}
- return *val;
+ return val[0];
}
/*
- * Read the flag status register, returning its value in the location
- * Return the status register value.
+ * Return the flag status register value. If the chip is parallel, then
+ * the read will be striped, so we should read 2 bytes to get the fsr
+ * register value from both of the parallel chips.
* Returns negative if error occurred.
*/
static int read_fsr(struct spi_nor *nor)
@@ -514,13 +526,23 @@ static int read_fsr(struct spi_nor *nor)
if (spi_nor_protocol_is_dtr(nor->reg_proto))
op.data.nbytes = 2;
- ret = spi_nor_read_write_reg(nor, , val);
- if (ret < 0) {
- pr_debug("error %d reading FSR\n", ret);
- return ret;
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ op.data.nbytes = 2;
+ ret = spi_nor_read_write_reg(nor, , [0]);
+ if (ret < 0) {
+ pr_debug("error %d reading SR\n", (int)ret);
+ return ret;
+ }
+ val[0] &= val[1];
+ } else {
+ ret = spi_nor_read_write_reg(nor, , [0]);
+ if (ret < 0) {
+ pr_debug("error %d reading FSR\n", ret);
+ return ret;
+ }
}
- return *val;
+ return val[0];
}
/*
--
2.25.1
[PATCH v5 1/6] mtd: spi-nor: Add parallel and stacked memories support
From: Ashok Reddy Soma
In parallel mode, the current implementation assumes that a maximum of
two flashes are connected. The QSPI controller splits the data evenly
between both the flashes so, both the flashes that are connected in
parallel mode should be identical.
During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in
nor->flags.
In stacked mode the current implementation assumes that a maximum of two
flashes are connected and both the flashes are of same make but can
differ in sizes. So, except the sizes all other flash parameters of both
the flashes are identical
Spi-nor will pass on the appropriate flash select flag to low level
driver, and it will select pass all the data to that particular flash.
Write operation in parallel mode are performed in page size * 2 chunks as
each write operation results in writing both the flashes. For doubling
the address space each operation is performed at addr/2 flash offset,
where addr is the address specified by the user.
Similarly for read and erase operations it will read from both flashes,
so size and offset are divided by 2 and send to flash.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/mtd/spi/spi-nor-core.c | 285 +
include/linux/mtd/spi-nor.h| 13 ++
include/spi.h | 12 ++
3 files changed, 282 insertions(+), 28 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 9a1801ba93..4e2d8c8231 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -639,12 +639,17 @@ static u8 spi_nor_convert_3to4_erase(u8 opcode)
static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
const struct flash_info *info)
{
+ bool shift = 0;
+
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ shift = 1;
+
/* Do some manufacturer fixups first */
switch (JEDEC_MFR(info)) {
case SNOR_MFR_SPANSION:
/* No small sector erase for 4-byte command set */
nor->erase_opcode = SPINOR_OP_SE;
- nor->mtd.erasesize = info->sector_size;
+ nor->mtd.erasesize = info->sector_size << shift;
break;
default:
@@ -965,8 +970,8 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32
addr)
static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
+ u32 addr, len, rem, offset;
bool addr_known = false;
- u32 addr, len, rem;
int ret, err;
dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
@@ -991,6 +996,19 @@ static int spi_nor_erase(struct mtd_info *mtd, struct
erase_info *instr)
ret = -EINTR;
goto erase_err;
}
+
+ offset = addr;
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ offset /= 2;
+
+ if (nor->flags & SNOR_F_HAS_STACKED) {
+ if (offset >= (mtd->size / 2)) {
+ offset = offset - (mtd->size / 2);
+ nor->spi->flags |= SPI_XFER_U_PAGE;
+ } else {
+ nor->spi->flags &= ~SPI_XFER_U_PAGE;
+ }
+ }
#ifdef CONFIG_SPI_FLASH_BAR
ret = write_bar(nor, addr);
if (ret < 0)
@@ -1396,6 +1414,9 @@ static const struct flash_info *spi_nor_read_id(struct
spi_nor *nor)
u8 id[SPI_NOR_MAX_ID_LEN];
const struct flash_info *info;
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ nor->spi->flags |= SPI_XFER_LOWER;
+
tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
if (tmp < 0) {
dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
@@ -1420,28 +1441,57 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t
from, size_t len,
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
int ret;
+ u32 offset = from;
+ u32 stack_shift = 0;
+ u32 read_len = 0;
+ u32 rem_bank_len = 0;
+ u8 bank;
+ u8 is_ofst_odd = 0;
dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
- while (len) {
- loff_t addr = from;
- size_t read_len = len;
+ if ((nor->flags & SNOR_F_HAS_PARALLEL) && (offset & 1)) {
+ /* We can hit this case when we use file system like ubifs */
+ from = (loff_t)(from - 1);
+ len = (size_t)(len + 1);
+ is_ofst_odd = 1;
+ }
-#ifdef CONFIG_SPI_FLASH_BAR
- u32 remain_len;
+ while (len) {
+ if (nor->addr_width == 3) {
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ bank = (u32)from / (SZ_16M << 0x01);
[PATCH v5 0/6] spi-nor: Add parallel and stacked memories support
This series adds support for Xilinx qspi parallel and stacked memeories. In parallel mode, the current implementation assumes that a maximum of two flashes are connected. The QSPI controller splits the data evenly between both the flashes so, both the flashes that are connected in parallel mode should be identical. During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in nor->flags. In stacked mode the current implementation assumes that a maximum of two flashes are connected and both the flashes are of same make but can differ in sizes. So, except the sizes all other flash parameters of both the flashes are identical. Spi-nor will pass on the appropriate flash select flag to low level driver, and it will select pass all the data to that particular flash. Write operation in parallel mode are performed in page size * 2 chunks as each write operation results in writing both the flashes. For doubling the address space each operation is performed at addr/2 flash offset, where addr is the address specified by the user. Similarly for read and erase operations it will read from both flashes, so size and offset are divided by 2 and send to flash. Changes in v2: - Fixed the compilation issues. Changes in v3: - Fixed the CI issues. Changes in v4: - Removed the dio,dummy_bytes variables from zynq_qspi driver. - Fix the compilation issue by including the DM_SERIAL config. Changes in v5: - Fixed the issue reported by buildman. Ashok Reddy Soma (4): mtd: spi-nor: Add parallel and stacked memories support mtd: spi-nor: Add parallel memories support for read_sr and read_fsr mtd: spi-nor: Add parallel and stacked memories support in read_bar and write_bar spi: spi-uclass: Read chipselect and restrict capabilities Venkatesh Yadav Abbarapu (2): spi: zynqmp_gqspi: Add parallel memories support in GQSPI driver spi: zynq_qspi: Add parallel memories support in QSPI driver drivers/mtd/spi/sandbox.c | 2 +- drivers/mtd/spi/spi-nor-core.c | 390 - drivers/spi/altera_spi.c | 4 +- drivers/spi/atcspi200_spi.c| 2 +- drivers/spi/ath79_spi.c| 2 +- drivers/spi/atmel_spi.c| 6 +- drivers/spi/bcm63xx_hsspi.c| 42 ++-- drivers/spi/bcm63xx_spi.c | 6 +- drivers/spi/bcmbca_hsspi.c | 34 +-- drivers/spi/cf_spi.c | 6 +- drivers/spi/davinci_spi.c | 6 +- drivers/spi/fsl_dspi.c | 18 +- drivers/spi/fsl_espi.c | 4 +- drivers/spi/fsl_qspi.c | 4 +- drivers/spi/gxp_spi.c | 2 +- drivers/spi/mpc8xx_spi.c | 4 +- drivers/spi/mpc8xxx_spi.c | 10 +- drivers/spi/mscc_bb_spi.c | 4 +- drivers/spi/mxc_spi.c | 6 +- drivers/spi/npcm_fiu_spi.c | 14 +- drivers/spi/nxp_fspi.c | 2 +- drivers/spi/octeon_spi.c | 2 +- drivers/spi/omap3_spi.c| 4 +- drivers/spi/pic32_spi.c| 2 +- drivers/spi/rk_spi.c | 4 +- drivers/spi/rockchip_sfc.c | 2 +- drivers/spi/spi-aspeed-smc.c | 28 +-- drivers/spi/spi-mxic.c | 6 +- drivers/spi/spi-qup.c | 4 +- drivers/spi/spi-sifive.c | 6 +- drivers/spi/spi-sn-f-ospi.c| 2 +- drivers/spi/spi-sunxi.c| 6 +- drivers/spi/spi-synquacer.c| 4 +- drivers/spi/spi-uclass.c | 23 +- drivers/spi/stm32_qspi.c | 2 +- drivers/spi/stm32_spi.c| 4 +- drivers/spi/ti_qspi.c | 14 +- drivers/spi/xilinx_spi.c | 4 +- drivers/spi/zynq_qspi.c| 120 -- drivers/spi/zynq_spi.c | 6 +- drivers/spi/zynqmp_gqspi.c | 141 ++-- include/linux/mtd/spi-nor.h| 13 ++ include/spi.h | 24 +- lib/acpi/acpi_device.c | 2 +- 44 files changed, 765 insertions(+), 226 deletions(-) -- 2.25.1
Re: [PATCH v7 2/2] arm64: boot: Support Flat Image Tree
Hello Simon, On 30.11.23 21:30, Simon Glass wrote: > On Wed, 29 Nov 2023 at 12:54, Ahmad Fatoum wrote: >> On 29.11.23 20:44, Simon Glass wrote: >>> On Wed, 29 Nov 2023 at 12:33, Ahmad Fatoum wrote: On 29.11.23 20:27, Simon Glass wrote: > On Wed, 29 Nov 2023 at 12:15, Ahmad Fatoum > wrote: >> On 29.11.23 20:02, Simon Glass wrote: >>> On Wed, 29 Nov 2023 at 11:59, Ahmad Fatoum >>> wrote: The specification says that this is the root U-Boot compatible, which I presume to mean the top-level compatible, which makes sense to me. The code here though adds all compatible strings from the device tree though, is this intended? >>> >>> Yes, since it saves needing to read in each DT just to get the >>> compatible stringlist. >> >> The spec reads as if only one string (root) is supposed to be in the >> list. >> The script adds all compatibles though. This is not really useful as a >> bootloader >> that's compatible with e.g. fsl,imx8mm would just take the first device >> tree >> with that SoC, which is most likely to be wrong. It would be better to >> just >> specify the top-level compatible, so the bootloader fails instead of >> taking >> the first DT it finds. > > We do need to have a list, since we have to support different board revs, > etc. Can you give me an example? The way I see it, a bootloader with compatible "vendor,board" and a FIT with configuration with compatibles: "vendor,board-rev-a", "vendor,board" "vendor,board-rev-b", "vendor,board" would just result in the bootloader booting the first configuration, even if the device is actually rev-b. >>> >>> You need to find the best match, not just any match. This is >>> documented in the function comment for fit_conf_find_compat(). >> >> In my above example, both configuration are equally good. >> Can you give me an example where it makes sense to have multiple >> compatibles automatically extracted from the device tree compatible? >> >> The way I see it having more than one compatible here just has >> downsides. > > I don't have an example to hand, but this is the required mechanism of > FIT. This feature has been in place for many years and is used by > ChromeOS, at least. I see the utility of a FIT configuration with compatible = "vendor,board-rev-a", "vendor,board-rev-b"; I fail to see a utility for a configuration with compatible = "vendor,board", "vendor,SoM", "vendor,SoC"; Any configuration that ends up being booted because "vendor,SoC" was matched is most likely doomed to fail. Therefore, I would suggest that only the top level configuration is written into the FIT configurations automatically. Cheers, Ahmad -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
[PATCH v6 5/5] fdt: Fix compile error for !OFNODE_MULTI_TREE
Required to fix the following compile error when building sandbox:
/tmp/cci9ibby.ltrans21.ltrans.o: In function `do_cedit_load':
:(.text+0x601d): undefined reference to `oftree_dispose'
Signed-off-by: Sean Edmond
Reviewed-by: Simon Glass
---
(no changes since v3)
Changes in v3:
- fix compile error for sandbox for !OFNODE_MULTI_TREE
drivers/core/ofnode.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 557a4a1b969..f4af184a476 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -135,12 +135,6 @@ int oftree_new(oftree *treep)
return 0;
}
-void oftree_dispose(oftree tree)
-{
- if (of_live_active())
- of_live_free(tree.np);
-}
-
void *ofnode_lookup_fdt(ofnode node)
{
if (gd->flags & GD_FLG_RELOC) {
@@ -243,6 +237,12 @@ int oftree_new(oftree *treep)
#endif /* OFNODE_MULTI_TREE */
+void oftree_dispose(oftree tree)
+{
+ if (of_live_active())
+ of_live_free(tree.np);
+}
+
int oftree_to_fdt(oftree tree, struct abuf *buf)
{
int ret;
--
2.42.0
[PATCH v6 4/5] dm: core: Modify default for OFNODE_MULTI_TREE
There is a preference to use the "ofnode" API for FDT fixups moving forward. The FDT fixup will usually be for the kernel FDT. To fixup the kernel FDT with the ofnode API, it's required to set the OFNODE_MULTI_TREE option. To ensure existing users of kaslr fdt fixup are not impacted, Let's modify the default value for OFNODE_MULTI_TREE to ensure it's always set. This will cause a 1007 byte increase in the code size. Signed-off-by: Sean Edmond Reviewed-by: Simon Glass --- (no changes since v5) Changes in v5: - Always enable OFNODE_MULTI_TREE Changes in v4: - Fix compile issue when CONFIG_OF_CONTROL not set Changes in v2: - Change default config for OFNODE_MULTI_TREE (y if !OF_LIVE) drivers/core/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 737d4590d5b..c01a8dc7e0a 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -423,7 +423,8 @@ config DM_DEV_READ_INLINE config OFNODE_MULTI_TREE bool "Allow the ofnode interface to access any tree" - default y if EVENT && !DM_DEV_READ_INLINE && !DM_INLINE_OFNODE + depends on OF_CONTROL + default y help Normally U-Boot makes use of its control FDT, the one used to bind devices and provide options. In some cases, U-Boot must also process -- 2.42.0
[PATCH v6 0/5] Populate kaslr seed with RNG
This patch series creates a common API (fdt_fixup_kaslr_seed()) for populating the kaslr seed in the DTB. Existing users (kaslrseed, and ARMv8 sec firmware) have been updated to use this common API. New functionality has been introduced to populate the kaslr using the RNG. This can be enabled with CONFIG_RNG_TPM_SEED. Changes in v6: - root_ofnode_from_fdt()->ofnode_root_from_fdt() - Enclose fdt_rng_kaslr_seed() in "#if defined(CONFIG_KASLR_RNG_SEED)" Changes in v5: - include dm/ofnode-decl.h instead of dm/ofnode.h - cast buffer to (u8 *) in kaslrseed.c - Always enable OFNODE_MULTI_TREE Changes in v4: - Fix compile issue when CONFIG_OF_CONTROL not set Changes in v3: - Use event spy to do the FDT fixup - Populate with RNG device instead of TPM device (this is a more generic solution) - fix compile error for sandbox for !OFNODE_MULTI_TREE Changes in v2: - fdt_fixup_kaslr_seed() uses the ofnode API - Add root_ofnode_from_fdt() to get the root node from an FDT and perform error checking on the oftree - add comments to exported functions - Add error checking in image_setup_libfdt() for return from fdt_tpm_kaslr_seed() - uclass_get_device() -> uclass_first_device_err() - Change default config for OFNODE_MULTI_TREE (y if !OF_LIVE) Dhananjay Phadke (2): fdt: common API to populate kaslr seed fdt: kaslr seed from RNG device Sean Edmond (3): cmd: kaslrseed: Use common API to fixup FDT dm: core: Modify default for OFNODE_MULTI_TREE fdt: Fix compile error for !OFNODE_MULTI_TREE arch/arm/cpu/armv8/sec_firmware.c | 39 -- boot/fdt_support.c| 54 +++ cmd/kaslrseed.c | 20 configs/sandbox_defconfig | 2 +- drivers/core/Kconfig | 3 +- drivers/core/ofnode.c | 29 + include/dm/ofnode.h | 12 +++ include/fdt_support.h | 9 ++ lib/Kconfig | 7 9 files changed, 129 insertions(+), 46 deletions(-) -- 2.42.0
[PATCH v6 3/5] cmd: kaslrseed: Use common API to fixup FDT
Use the newly introduced common API fdt_fixup_kaslr_seed() in the
kaslrseed command.
Signed-off-by: Sean Edmond
Reviewed-by: Simon Glass
---
Changes in v6:
- root_ofnode_from_fdt()->ofnode_root_from_fdt()
- "goto CMD_RET_FAILURE" -> "return CMD_RET_FAILURE"
Changes in v5:
- cast buffer to (u8 *) in kaslrseed.c
cmd/kaslrseed.c | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/cmd/kaslrseed.c b/cmd/kaslrseed.c
index 9acb8e16386..9339d82649b 100644
--- a/cmd/kaslrseed.c
+++ b/cmd/kaslrseed.c
@@ -19,7 +19,7 @@ static int do_kaslr_seed(struct cmd_tbl *cmdtp, int flag, int
argc, char *const
size_t n = 0x8;
struct udevice *dev;
u64 *buf;
- int nodeoffset;
+ ofnode root;
int ret = CMD_RET_SUCCESS;
if (uclass_get_device(UCLASS_RNG, 0, ) || !dev) {
@@ -45,21 +45,15 @@ static int do_kaslr_seed(struct cmd_tbl *cmdtp, int flag,
int argc, char *const
return CMD_RET_FAILURE;
}
- ret = fdt_check_header(working_fdt);
- if (ret < 0) {
- printf("fdt_chosen: %s\n", fdt_strerror(ret));
+ ret = ofnode_root_from_fdt(working_fdt, );
+ if (ret) {
+ printf("ERROR: Unable to get root ofnode\n");
return CMD_RET_FAILURE;
}
- nodeoffset = fdt_find_or_add_subnode(working_fdt, 0, "chosen");
- if (nodeoffset < 0) {
- printf("Reading chosen node failed\n");
- return CMD_RET_FAILURE;
- }
-
- ret = fdt_setprop(working_fdt, nodeoffset, "kaslr-seed", buf,
sizeof(buf));
- if (ret < 0) {
- printf("Unable to set kaslr-seed on chosen node: %s\n",
fdt_strerror(ret));
+ ret = fdt_fixup_kaslr_seed(root, (u8 *)buf, sizeof(buf));
+ if (ret) {
+ printf("ERROR: failed to add kaslr-seed to fdt\n");
return CMD_RET_FAILURE;
}
--
2.42.0
[PATCH v6 2/5] fdt: kaslr seed from RNG device
From: Dhananjay Phadke
Add support for KASLR seed from the RNG device. Invokes dm_rng_read()
API to read 8-bytes of random bytes. Performs the FDT fixup using event
spy. To enable use CONFIG_KASLR_RNG_SEED
Signed-off-by: Dhananjay Phadke
Signed-off-by: Drew Kluemke
Signed-off-by: Sean Edmond
Reviewed-by: Simon Glass
BAH
---
Changes in v6:
- Enclose fdt_rng_kaslr_seed() in "#if defined(CONFIG_KASLR_RNG_SEED)"
Changes in v3:
- Populate with RNG device instead of TPM device (this is a more generic
solution)
Changes in v2:
- Add error checking in image_setup_libfdt() for return from
fdt_tpm_kaslr_seed()
- uclass_get_device() -> uclass_first_device_err()
boot/fdt_support.c| 35 +++
configs/sandbox_defconfig | 2 +-
lib/Kconfig | 7 +++
3 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/boot/fdt_support.c b/boot/fdt_support.c
index 49d14a949be..b51154f83a5 100644
--- a/boot/fdt_support.c
+++ b/boot/fdt_support.c
@@ -12,7 +12,10 @@
#include
#include
#include
+#include
#include
+#include
+#include
#include
#include
#include
@@ -650,6 +653,38 @@ int fdt_fixup_kaslr_seed(ofnode node, const u8 *seed, int
len)
return 0;
}
+#if defined(CONFIG_KASLR_RNG_SEED)
+int fdt_rng_kaslr_seed(void *ctx, struct event *event)
+{
+ u8 rand[8] = {0};
+ struct udevice *dev;
+ int ret;
+ oftree tree = event->data.ft_fixup.tree;
+ ofnode root_node = oftree_root(tree);
+
+ ret = uclass_first_device_err(UCLASS_RNG, );
+ if (ret) {
+ printf("ERROR: Failed to find RNG device\n");
+ return ret;
+ }
+
+ ret = dm_rng_read(dev, rand, sizeof(rand));
+ if (ret) {
+ printf("ERROR: RNG read failed, ret=%d\n", ret);
+ return ret;
+ }
+
+ ret = fdt_fixup_kaslr_seed(root_node, rand, sizeof(rand));
+ if (ret) {
+ printf("ERROR: failed to add kaslr-seed to fdt\n");
+ return ret;
+ }
+
+ return 0;
+}
+EVENT_SPY_FULL(EVT_FT_FIXUP, fdt_rng_kaslr_seed);
+#endif
+
int fdt_record_loadable(void *blob, u32 index, const char *name,
uintptr_t load_addr, u32 size, uintptr_t entry_point,
const char *type, const char *os, const char *arch)
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index bc5bcb2a623..b71790e1532 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -348,4 +348,4 @@ CONFIG_EFI_SECURE_BOOT=y
CONFIG_TEST_FDTDEC=y
CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
-CONFIG_UT_DM=y
+CONFIG_UT_DM=y
\ No newline at end of file
diff --git a/lib/Kconfig b/lib/Kconfig
index 19649517a39..4f5dfc00d6f 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -477,6 +477,13 @@ config VPL_TPM
for the low-level TPM interface, but only one TPM is supported at
a time by the TPM library.
+config KASLR_RNG_SEED
+ bool "Use RNG driver for KASLR random seed"
+ depends on DM_RNG
+ help
+ This enables support for using the RNG driver as entropy source for
+ KASLR seed populated in kernel's device tree.
+
endmenu
menu "Android Verified Boot"
--
2.42.0
[PATCH v6 1/5] fdt: common API to populate kaslr seed
From: Dhananjay Phadke
fdt_fixup_kaslr_seed() will update given ofnode with random seed value.
Source for random seed can be TPM or RNG driver in u-boot or sec
firmware (ARM).
Signed-off-by: Dhananjay Phadke
Signed-off-by: Sean Edmond
Signed-off-by: Sean Edmond
---
Changes in v6:
- root_ofnode_from_fdt()->ofnode_root_from_fdt()
Changes in v5:
- include dm/ofnode-decl.h instead of dm/ofnode.h
Changes in v3:
- Use event spy to do the FDT fixup
Changes in v2:
- fdt_fixup_kaslr_seed() uses the ofnode API
- Add root_ofnode_from_fdt() to get the root node from an FDT and
perform error checking on the oftree
- add comments to exported functions
arch/arm/cpu/armv8/sec_firmware.c | 39 +++
boot/fdt_support.c| 19 +++
drivers/core/ofnode.c | 17 ++
include/dm/ofnode.h | 12 ++
include/fdt_support.h | 9 +++
5 files changed, 71 insertions(+), 25 deletions(-)
diff --git a/arch/arm/cpu/armv8/sec_firmware.c
b/arch/arm/cpu/armv8/sec_firmware.c
index c0e8726346f..5f256939277 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -411,46 +411,35 @@ int sec_firmware_init(const void *sec_firmware_img,
/*
* fdt_fix_kaslr - Add kalsr-seed node in Device tree
* @fdt: Device tree
- * @eret: 0 in case of error, 1 for success
+ * @eret: 0 for success
*/
int fdt_fixup_kaslr(void *fdt)
{
- int nodeoffset;
- int err, ret = 0;
- u8 rand[8];
+ int ret = 0;
#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT)
+ u8 rand[8];
+ ofnode root;
+
/* Check if random seed generation is supported */
if (sec_firmware_support_hwrng() == false) {
printf("WARNING: SEC firmware not running, no kaslr-seed\n");
- return 0;
+ return -EOPNOTSUPP;
}
- err = sec_firmware_get_random(rand, 8);
- if (err < 0) {
+ ret = sec_firmware_get_random(rand, 8);
+ if (ret < 0) {
printf("WARNING: No random number to set kaslr-seed\n");
- return 0;
+ return ret;
}
- err = fdt_check_header(fdt);
- if (err < 0) {
- printf("fdt_chosen: %s\n", fdt_strerror(err));
- return 0;
+ ret = ofnode_root_from_fdt(fdt, );
+ if (ret < 0) {
+ printf("WARNING: Unable to get root ofnode\n");
+ return ret;
}
- /* find or create "/chosen" node. */
- nodeoffset = fdt_find_or_add_subnode(fdt, 0, "chosen");
- if (nodeoffset < 0)
- return 0;
-
- err = fdt_setprop(fdt, nodeoffset, "kaslr-seed", rand,
- sizeof(rand));
- if (err < 0) {
- printf("WARNING: can't set kaslr-seed %s.\n",
- fdt_strerror(err));
- return 0;
- }
- ret = 1;
+ ret = fdt_fixup_kaslr_seed(root, rand, sizeof(rand));
#endif
return ret;
diff --git a/boot/fdt_support.c b/boot/fdt_support.c
index b15d07765fe..49d14a949be 100644
--- a/boot/fdt_support.c
+++ b/boot/fdt_support.c
@@ -631,6 +631,25 @@ void fdt_fixup_ethernet(void *fdt)
}
}
+int fdt_fixup_kaslr_seed(ofnode node, const u8 *seed, int len)
+{
+ ofnode chosen;
+ int ret;
+
+ /* find or create "/chosen" node. */
+ ret = ofnode_add_subnode(node, "chosen", );
+ if (ret && ret != -EEXIST)
+ return -ENOENT;
+
+ ret = ofnode_write_prop(chosen, "kaslr-seed", seed, len, true);
+ if (ret) {
+ printf("WARNING: can't set kaslr-seed\n");
+ return ret;
+ }
+
+ return 0;
+}
+
int fdt_record_loadable(void *blob, u32 index, const char *name,
uintptr_t load_addr, u32 size, uintptr_t entry_point,
const char *type, const char *os, const char *arch)
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index f72ea416cf1..557a4a1b969 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -966,6 +966,23 @@ ofnode oftree_path(oftree tree, const char *path)
}
}
+int ofnode_root_from_fdt(void *fdt, ofnode *root_node)
+{
+ oftree tree;
+ /* If OFNODE_MULTI_TREE is not set, and if fdt is not the control FDT,
+* oftree_from_fdt() will return NULL
+*/
+ tree = oftree_from_fdt(fdt);
+
+ if (!oftree_valid(tree)) {
+ printf("Cannot create oftree\n");
+ return -EINVAL;
+ }
+ *root_node = oftree_root(tree);
+
+ return 0;
+}
+
const void *ofnode_read_chosen_prop(const char *propname, int *sizep)
{
ofnode chosen_node;
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index 5795115c490..b3bb133df19 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -936,6 +936,18 @@ ofnode
Re: mdt_debug write
Hi Stephen, On 30/11/2023 01:13, Stephen Graf wrote: Is the attached patch file going in the right direction? yes, thanks, the change itself looks alright, but it needs to be: - in a separate email, with a descriptive subject, prefixed by [PATCH] - have the diff inline, not as an attachment (to allow easy commenting in an email thread) - have a Signed-off-by: tag with your name and email address. This is to signify that the change is an original one made by you and you are happy to submit this under the (GPL) license conditions. - an explanation *why* this change is required (mtd_debug write being not reliable, etc) - sent to the U-Boot list and the maintainer (me) Look at the U-Boot mailing list (archive) for examples. "git format-patch" creates everything in the right format (mbox), and "git send-email" will send this via an SMTP server you point it to. Or you import this into your client. If you could try this (with the Signed-off-by being the most important change), I am happy to submit this with the next push. Thanks, Andre On 2023-11-29 3:57 p.m., Andre Przywara wrote: Hi Stephen, On 28/11/2023 20:07, Stephen Graf wrote: Below is the console log from trying to use mtd_debug write. It returned immediately with a strange success message. root@orangepizero3:~# mtd_debug write /dev/mtd0 0 0xf /home/sysadmin/u-boot-sunxi-with-spl.bin file_to_flash: fread, size 0xf, n 0xf fread(): Success interesting, I was under the impression that "mtd_debug write" would be the way to write to flash. In hindsight, the "debug" in that name should have probably put me off. Anyway, "cat" is probably not a good choice, "dd" is better, but it looks like "flashcp" (also part of mtdutils) is the go-to tool, since it does the required erasing automatically and also reportedly does some error detection. Can you please test this? # flashcp u-boot-sunxi-with-spl.bin /dev/mtd0 I would test this on my end ASAP as well. Do you feel like sending a patch to the U-Boot documentation to get this changed then? Thanks, Andre
Re: [PATCH] arm: apple: t602x: Add missing MMIO regions to memmap
> Date: Thu, 30 Nov 2023 23:04:36 +0100 > From: "Janne Grunau" > > Hej Mark, > > On Thu, Nov 30, 2023, at 21:45, Mark Kettenis wrote: > >> From: Janne Grunau via B4 Relay > >> Date: Thu, 30 Nov 2023 13:42:22 +0100 > >> > >> From: Janne Grunau > >> > >> The memory maps for Apple's M2 Pro/Max/Ultra left MMIO space out which > >> was not used by any driver at the time. The display out exposed as > >> simple-framebuffer use a power-domain controlled by a device in an > >> unmapped region. > >> Add a map covering this region as well as another MMIO region in the > >> range 0x4'' - 0x5''. The added regions cover all MMIO > >> annotated in Apple's device tree in this range. > >> > >> Signed-off-by: Janne Grunau > >> --- > >> arch/arm/mach-apple/board.c | 48 > >> + > >> 1 file changed, 48 insertions(+) > > > > Hi Janne, > > > > Is there a reason why you can't use a SZ_1G mapping for the blocks > > where you're using a SZ_512M mapping? With SZ_1G the mapping code > > will use a 1G block descriptor which avoids another level of page > > tables. > > no reason except that SZ_512M was sufficient to cover all devices in > Apple DT. Shall I resend the patch? Yes please!
Re: [PATCH v3 2/3] efi_vars: Implement SPI Flash store
Hi Shantur
I have a few remarks on the architecture.
Up to now, we are supporting
1. Variables on a file
2. Variables on an RPMB
The reason those two are in different files is that we generally
expect to use different bootime services and few differences in
efi_variables_boot_exit_notify() and efi_init_variables().
Whatever is common, for example the runtime functions are common
across those two since they both implement variable runtime service
via the memory backend, goes into efi_var_common.c, the memory backend
operations should go in efi_var_mem.c.
Since the SPI and file storage are similar -- and probably any storage
medium controlled by the non-secure world, I am fine treating treat
efi_variable.c as the variable management for the non-secure world and
see if that needs changing in the future.
As Heinrich pointed out the functions you are moving are better off
moved into efi_var_mem.c.
[...]
> diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
> index adc5ac6a80..f73fb40061 100644
> --- a/lib/efi_loader/efi_variable.c
> +++ b/lib/efi_loader/efi_variable.c
> @@ -354,14 +354,16 @@ efi_status_t efi_set_variable_int(const u16
> *variable_name,
> ret = EFI_SUCCESS;
>
> /*
> -* Write non-volatile EFI variables to file
> +* Write non-volatile EFI variables to file or SPI Flash
> * TODO: check if a value change has occured to avoid superfluous
> writes
> */
> -#if CONFIG_IS_ENABLED(EFI_VARIABLE_FILE_STORE)
> if (attributes & EFI_VARIABLE_NON_VOLATILE) {
> +#if CONFIG_IS_ENABLED(EFI_VARIABLE_FILE_STORE)
> efi_var_to_file();
> - }
> +#elif CONFIG_IS_ENABLED(EFI_VARIABLE_SF_STORE)
> + efi_var_to_sf();
> #endif
> + }
>
> return EFI_SUCCESS;
> }
> @@ -471,9 +473,14 @@ efi_status_t efi_init_variables(void)
>
> #if CONFIG_IS_ENABLED(EFI_VARIABLE_FILE_STORE)
> ret = efi_var_from_file();
> +#elif CONFIG_IS_ENABLED(EFI_VARIABLE_SF_STORE)
> + ret = efi_var_from_sf();
> +#else
> + ret = EFI_SUCCESS;
> +#endif
Instead of those ifdefs can we do something different?
Define a structure with two function callbacks for read/write(). Add
the same function in both efi_var_file.c and efi_var_sp.c which fills
in those callbacks and have an efi_init_variable() call to that
function (obviously the SPI and file will be mutually exclusive)
Thanks
/Ilias
> +
> if (ret != EFI_SUCCESS)
> return ret;
> -#endif
>
> if (IS_ENABLED(CONFIG_EFI_VARIABLES_PRESEED)) {
> ret = efi_var_restore((struct efi_var_file *)
> --
> 2.40.1
>
Re: [PATCH] arm: apple: t602x: Add missing MMIO regions to memmap
Hej Mark, On Thu, Nov 30, 2023, at 21:45, Mark Kettenis wrote: >> From: Janne Grunau via B4 Relay >> Date: Thu, 30 Nov 2023 13:42:22 +0100 >> >> From: Janne Grunau >> >> The memory maps for Apple's M2 Pro/Max/Ultra left MMIO space out which >> was not used by any driver at the time. The display out exposed as >> simple-framebuffer use a power-domain controlled by a device in an >> unmapped region. >> Add a map covering this region as well as another MMIO region in the >> range 0x4'' - 0x5''. The added regions cover all MMIO >> annotated in Apple's device tree in this range. >> >> Signed-off-by: Janne Grunau >> --- >> arch/arm/mach-apple/board.c | 48 >> + >> 1 file changed, 48 insertions(+) > > Hi Janne, > > Is there a reason why you can't use a SZ_1G mapping for the blocks > where you're using a SZ_512M mapping? With SZ_1G the mapping code > will use a 1G block descriptor which avoids another level of page > tables. no reason except that SZ_512M was sufficient to cover all devices in Apple DT. Shall I resend the patch? Janne
Re: [PATCH] arm: apple: t602x: Add missing MMIO regions to memmap
> From: Janne Grunau via B4 Relay
> Date: Thu, 30 Nov 2023 13:42:22 +0100
>
> From: Janne Grunau
>
> The memory maps for Apple's M2 Pro/Max/Ultra left MMIO space out which
> was not used by any driver at the time. The display out exposed as
> simple-framebuffer use a power-domain controlled by a device in an
> unmapped region.
> Add a map covering this region as well as another MMIO region in the
> range 0x4'' - 0x5''. The added regions cover all MMIO
> annotated in Apple's device tree in this range.
>
> Signed-off-by: Janne Grunau
> ---
> arch/arm/mach-apple/board.c | 48
> +
> 1 file changed, 48 insertions(+)
Hi Janne,
Is there a reason why you can't use a SZ_1G mapping for the blocks
where you're using a SZ_512M mapping? With SZ_1G the mapping code
will use a 1G block descriptor which avoids another level of page
tables.
> diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c
> index 47393babbc..e05ec431bc 100644
> --- a/arch/arm/mach-apple/board.c
> +++ b/arch/arm/mach-apple/board.c
> @@ -370,6 +370,22 @@ static struct mm_region t6020_mem_map[] = {
> .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
>PTE_BLOCK_NON_SHARE |
>PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + /* I/O */
> + .virt = 0x4,
> + .phys = 0x4,
> + .size = SZ_512M,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + /* I/O */
> + .virt = 0x48000,
> + .phys = 0x48000,
> + .size = SZ_1G,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> }, {
> /* I/O */
> .virt = 0x58000,
> @@ -471,6 +487,22 @@ static struct mm_region t6022_mem_map[] = {
> .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
>PTE_BLOCK_NON_SHARE |
>PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + /* I/O */
> + .virt = 0x4,
> + .phys = 0x4,
> + .size = SZ_512M,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + /* I/O */
> + .virt = 0x48000,
> + .phys = 0x48000,
> + .size = SZ_1G,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> }, {
> /* I/O */
> .virt = 0x58000,
> @@ -551,6 +583,22 @@ static struct mm_region t6022_mem_map[] = {
> .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
>PTE_BLOCK_NON_SHARE |
>PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + /* I/O */
> + .virt = 0x24,
> + .phys = 0x24,
> + .size = SZ_512M,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + /* I/O */
> + .virt = 0x248000,
> + .phys = 0x248000,
> + .size = SZ_1G,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> }, {
> /* I/O */
> .virt = 0x258000,
>
> ---
> base-commit: 43f2873fa98b1da6eb56d756315c7bd7db63db27
> change-id: 20231130-apple_t602x_extend_memmap-c82c522ca8c0
>
> Best regards,
> --
> Janne Grunau
>
>
[PATCH] net: phy: realtek: Add support for LED configuration
From: Jakub Klama
Introduce an ability to configure LED and Fiber LEDs found in RTL8211F
PHYs. This is achieved through two optional Device Tree properties:
* rtl,lcr for LED control
* rtl,flcr for Fiber LED control
Signed-off-by: Jakub Klama
Signed-off-by: Artur Rojek
---
drivers/net/phy/realtek.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 396cac76d6..d078f41bee 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -59,6 +59,7 @@
#define MIIM_RTL8211F_TX_DELAY 0x100
#define MIIM_RTL8211F_RX_DELAY 0x8
#define MIIM_RTL8211F_LCR 0x10
+#define MIIM_RTL8211F_FLCR 0x12
#define RTL8201F_RMSR 0x10
@@ -220,6 +221,8 @@ default_delay:
static int rtl8211f_config(struct phy_device *phydev)
{
+ ofnode node = phy_get_ofnode(phydev);
+ u32 lcr, flcr;
u16 reg;
if (phydev->flags & PHY_RTL8211F_FORCE_EEE_RXC_ON) {
@@ -254,14 +257,17 @@ static int rtl8211f_config(struct phy_device *phydev)
reg &= ~MIIM_RTL8211F_RX_DELAY;
phy_write(phydev, MDIO_DEVAD_NONE, 0x15, reg);
- /* restore to default page 0 */
- phy_write(phydev, MDIO_DEVAD_NONE,
- MIIM_RTL8211F_PAGE_SELECT, 0x0);
-
- /* Set green LED for Link, yellow LED for Active */
phy_write(phydev, MDIO_DEVAD_NONE,
MIIM_RTL8211F_PAGE_SELECT, 0xd04);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x617f);
+
+ if (ofnode_valid(node) && !ofnode_read_u32(node, "rtl,lcr", ))
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_LCR, lcr);
+ else /* Set green LED for Link, yellow LED for Active */
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_LCR, 0x617f);
+
+ if (ofnode_valid(node) && !ofnode_read_u32(node, "rtl,flcr", ))
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_FLCR, flcr);
+
phy_write(phydev, MDIO_DEVAD_NONE,
MIIM_RTL8211F_PAGE_SELECT, 0x0);
--
2.34.1
[PATCH v8 2/2] arm64: boot: Support Flat Image Tree
Add a script which produces a Flat Image Tree (FIT), a single file containing the built kernel and associated devicetree files. Compression defaults to gzip which gives a good balance of size and performance. The files compress from about 86MB to 24MB using this approach. The FIT can be used by bootloaders which support it, such as U-Boot and Linuxboot. It permits automatic selection of the correct devicetree, matching the compatible string of the running board with the closest compatible string in the FIT. There is no need for filenames or other workarounds. Add a 'make image.fit' build target for arm64, as well. The FIT can be examined using 'dumpimage -l'. This features requires pylibfdt (use 'pip install libfdt'). It also requires compression utilities for the algorithm being used. Supported compression options are the same as the Image.xxx files. For now there is no way to change the compression other than by editing the rule for $(obj)/image.fit While FIT supports a ramdisk / initrd, no attempt is made to support this here, since it must be built separately from the Linux build. Signed-off-by: Simon Glass --- Changes in v8: - Drop compatible string in FDT node - Correct sorting of MAINTAINERS to before ARM64 PORT - Turn compress part of the make_fit.py comment in to a sentence - Add two blank lines before parse_args() and setup_fit() - Use 'image.fit: dtbs' instead of BUILD_DTBS var - Use '$(https://docs.u-boot.org/en/latest/build/tools.html#building-tools-for-linux + System utilities diff --git a/MAINTAINERS b/MAINTAINERS index 14587be87a33..9f3eb476ece4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3037,6 +3037,13 @@ F: drivers/mmc/host/sdhci-of-arasan.c N: zynq N: xilinx +ARM64 FIT SUPPORT +M: Simon Glass +L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: arch/arm64/boot/Makefile +F: scripts/make_fit.py + ARM64 PORT (AARCH64 ARCHITECTURE) M: Catalin Marinas M: Will Deacon diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile index 1bd4fae6e806..6b893dc454b7 100644 --- a/arch/arm64/Makefile +++ b/arch/arm64/Makefile @@ -150,7 +150,7 @@ libs-$(CONFIG_EFI_STUB) += $(objtree)/drivers/firmware/efi/libstub/lib.a # Default target when executing plain make boot := arch/arm64/boot -BOOT_TARGETS := Image vmlinuz.efi +BOOT_TARGETS := Image vmlinuz.efi image.fit PHONY += $(BOOT_TARGETS) @@ -162,7 +162,9 @@ endif all: $(notdir $(KBUILD_IMAGE)) -vmlinuz.efi: Image +image.fit: dtbs + +vmlinuz.efi image.fit: Image $(BOOT_TARGETS): vmlinux $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ @@ -215,6 +217,7 @@ virtconfig: define archhelp echo '* Image.gz - Compressed kernel image (arch/$(ARCH)/boot/Image.gz)' echo ' Image - Uncompressed kernel image (arch/$(ARCH)/boot/Image)' + echo ' image.fit - Flat Image Tree (arch/$(ARCH)/boot/image.fit)' echo ' install - Install uncompressed kernel' echo ' zinstall - Install compressed kernel' echo ' Install using (your) ~/bin/installkernel or' diff --git a/arch/arm64/boot/.gitignore b/arch/arm64/boot/.gitignore index af5dc61f8b43..abaae9de1bdd 100644 --- a/arch/arm64/boot/.gitignore +++ b/arch/arm64/boot/.gitignore @@ -2,3 +2,4 @@ Image Image.gz vmlinuz* +image.fit diff --git a/arch/arm64/boot/Makefile b/arch/arm64/boot/Makefile index 1761f5972443..62efb533a9bc 100644 --- a/arch/arm64/boot/Makefile +++ b/arch/arm64/boot/Makefile @@ -16,7 +16,8 @@ OBJCOPYFLAGS_Image :=-O binary -R .note -R .note.gnu.build-id -R .comment -S -targets := Image Image.bz2 Image.gz Image.lz4 Image.lzma Image.lzo Image.zst +targets := Image Image.bz2 Image.gz Image.lz4 Image.lzma Image.lzo \ + Image.zst image.fit $(obj)/Image: vmlinux FORCE $(call if_changed,objcopy) @@ -39,6 +40,12 @@ $(obj)/Image.lzo: $(obj)/Image FORCE $(obj)/Image.zst: $(obj)/Image FORCE $(call if_changed,zstd) +# Use this to override the compression algorithm +FIT_COMPRESS ?= gzip + +$(obj)/image.fit: $(obj)/Image FORCE + $(call cmd,fit,$(FIT_COMPRESS)) + EFI_ZBOOT_PAYLOAD := Image EFI_ZBOOT_BFD_TARGET := elf64-littleaarch64 EFI_ZBOOT_MACH_TYPE:= ARM64 diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 1a965fe68e01..41b360b11552 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -496,6 +496,19 @@ quiet_cmd_uimage = UIMAGE $@ -a $(UIMAGE_LOADADDR) -e $(UIMAGE_ENTRYADDR) \ -n '$(UIMAGE_NAME)' -d $< $@ +# Flat Image Tree (FIT) +# This allows for packaging of a kernel and all devicetrees files, using +# compression. +# --- + +MAKE_FIT := $(srctree)/scripts/make_fit.py + +quiet_cmd_fit = FIT $@ + cmd_fit = $(MAKE_FIT) -f $@ --arch $(UIMAGE_ARCH) --os linux \ + --name
[PATCH v8 1/2] arm64: Add BOOT_TARGETS variable
Add a new variable containing a list of possible targets. Mark them as phony. This matches the approach taken for arch/arm Signed-off-by: Simon Glass --- (no changes since v7) Changes in v7: - Drop the kbuild tag Changes in v6: - Drop the unwanted .gz suffix arch/arm64/Makefile | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile index 9a2d3723cd0f..1bd4fae6e806 100644 --- a/arch/arm64/Makefile +++ b/arch/arm64/Makefile @@ -150,6 +150,10 @@ libs-$(CONFIG_EFI_STUB) += $(objtree)/drivers/firmware/efi/libstub/lib.a # Default target when executing plain make boot := arch/arm64/boot +BOOT_TARGETS := Image vmlinuz.efi + +PHONY += $(BOOT_TARGETS) + ifeq ($(CONFIG_EFI_ZBOOT),) KBUILD_IMAGE := $(boot)/Image.gz else @@ -159,7 +163,7 @@ endif all: $(notdir $(KBUILD_IMAGE)) vmlinuz.efi: Image -Image vmlinuz.efi: vmlinux +$(BOOT_TARGETS): vmlinux $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ Image.%: Image -- 2.43.0.rc2.451.g8631bc7472-goog
[PATCH v8 0/2] arm64: Add a build target for Flat Image Tree
Flat Image Tree (FIT) is a widely used file format for packaging a kernel and associated devicetree files[1]. It is not specific to any one bootloader, as it is supported by U-Boot, coreboot, Linuxboot, Tianocore and Barebox. This series adds support for building a FIT as part of the kernel build. This makes it easy to try out the kernel - just load the FIT onto your tftp server and it will run automatically on any supported arm64 board. The script is written in Python, since it is easy to build a FIT using the Python libfdt bindings. For now, no attempt is made to compress files in parallel, so building the 900-odd files takes a while, about 6 seconds with my testing. The series also includes a few minor clean-up patches. [1] https://github.com/open-source-firmware/flat-image-tree Changes in v8: - Drop compatible string in FDT node - Correct sorting of MAINTAINERS to before ARM64 PORT - Turn compress part of the make_fit.py comment in to a sentence - Add two blank lines before parse_args() and setup_fit() - Use 'image.fit: dtbs' instead of BUILD_DTBS var - Use '$(
Re: [PATCH v7 2/2] arm64: boot: Support Flat Image Tree
Hi Masahiro, On Thu, 30 Nov 2023 at 08:39, Masahiro Yamada wrote: > > On Thu, Nov 30, 2023 at 2:22 AM Simon Glass wrote: > > > > Add a script which produces a Flat Image Tree (FIT), a single file > > containing the built kernel and associated devicetree files. > > Compression defaults to gzip which gives a good balance of size and > > performance. > > > > The files compress from about 86MB to 24MB using this approach. > > > > The FIT can be used by bootloaders which support it, such as U-Boot > > and Linuxboot. It permits automatic selection of the correct > > devicetree, matching the compatible string of the running board with > > the closest compatible string in the FIT. There is no need for > > filenames or other workarounds. > > > > Add a 'make image.fit' build target for arm64, as well. > > > > The FIT can be examined using 'dumpimage -l'. > > > > This features requires pylibfdt (use 'pip install libfdt'). It also > > requires compression utilities for the algorithm being used. Supported > > compression options are the same as the Image.xxx files. For now there > > is no way to change the compression other than by editing the rule for > > $(obj)/image.fit > > > > While FIT supports a ramdisk / initrd, no attempt is made to support > > this here, since it must be built separately from the Linux build. > > > > Signed-off-by: Simon Glass > > --- > > > > Changes in v7: > > - Add Image as a dependency of image.fit > > - Drop kbuild tag > > - Add dependency on dtbs > > - Drop unnecessary path separator for dtbs > > - Rebase to -next > > > > Changes in v5: > > - Drop patch previously applied > > - Correct compression rule which was broken in v4 > > > > Changes in v4: > > - Use single quotes for UIMAGE_NAME > > > > Changes in v3: > > - Drop temporary file image.itk > > - Drop patch 'Use double quotes for image name' > > - Drop double quotes in use of UIMAGE_NAME > > - Drop unnecessary CONFIG_EFI_ZBOOT condition for help > > - Avoid hard-coding "arm64" for the DT architecture > > > > Changes in v2: > > - Drop patch previously applied > > - Add .gitignore file > > - Move fit rule to Makefile.lib using an intermediate file > > - Drop dependency on CONFIG_EFI_ZBOOT > > - Pick up .dtb files separately from the kernel > > - Correct pylint too-many-args warning for write_kernel() > > - Include the kernel image in the file count > > - Add a pointer to the FIT spec and mention of its wide industry usage > > - Mention the kernel version in the FIT description > > > > MAINTAINERS| 7 + > > arch/arm64/Makefile| 9 +- > > arch/arm64/boot/.gitignore | 1 + > > arch/arm64/boot/Makefile | 6 +- > > scripts/Makefile.lib | 13 ++ > > scripts/make_fit.py| 289 + > > 6 files changed, 322 insertions(+), 3 deletions(-) > > create mode 100755 scripts/make_fit.py > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 14587be87a33..d609f0e8deb3 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -1585,6 +1585,13 @@ F: Documentation/process/maintainer-soc*.rst > > F: arch/arm/boot/dts/Makefile > > F: arch/arm64/boot/dts/Makefile > > > > +ARM64 FIT SUPPORT > > +M: Simon Glass > > +L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) > > +S: Maintained > > +F: arch/arm64/boot/Makefile > > +F: scripts/make_fit.py > > + > > ARM ARCHITECTED TIMER DRIVER > > M: Mark Rutland > > M: Marc Zyngier > > diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile > > index 1bd4fae6e806..18e092de7cdb 100644 > > --- a/arch/arm64/Makefile > > +++ b/arch/arm64/Makefile > > @@ -36,6 +36,8 @@ ifeq ($(CONFIG_BROKEN_GAS_INST),y) > > $(warning Detected assembler with broken .inst; disassembly will be > > unreliable) > > endif > > > > +KBUILD_DTBS := dtbs > > > Please remove this, and hard-code > > image.fit: dtbs OK > > > > > > > $(obj)/Image: vmlinux FORCE > > $(call if_changed,objcopy) > > @@ -39,6 +40,9 @@ $(obj)/Image.lzo: $(obj)/Image FORCE > > $(obj)/Image.zst: $(obj)/Image FORCE > > $(call if_changed,zstd) > > > > +$(obj)/image.fit: $(obj)/Image FORCE > > + $(call cmd,fit,gzip) > > > The gzip parameter is not used. > Please do > > $(call cmd,fit) I do want to be able to control the compression algo. I added a FIT_COMPRESS for that, so that this arg is used. > > In the python script, functions are separated with two blank lines, > but there is only one blank line between parse_args() and setup_fit(). > > > I do not mind either way because it does not contain any class, > but please keep consistency. OK Regards, Simon
Re: [PATCH v7 2/2] arm64: boot: Support Flat Image Tree
Hi Ahmad, On Wed, 29 Nov 2023 at 12:54, Ahmad Fatoum wrote: > > Hello Simon, > > On 29.11.23 20:44, Simon Glass wrote: > > Hi Ahmad, > > > > On Wed, 29 Nov 2023 at 12:33, Ahmad Fatoum wrote: > >> > >> On 29.11.23 20:27, Simon Glass wrote: > >>> On Wed, 29 Nov 2023 at 12:15, Ahmad Fatoum > >>> wrote: > On 29.11.23 20:02, Simon Glass wrote: > > On Wed, 29 Nov 2023 at 11:59, Ahmad Fatoum > > wrote: > >> The specification says that this is the root U-Boot compatible, > >> which I presume to mean the top-level compatible, which makes sense to > >> me. > >> > >> The code here though adds all compatible strings from the device tree > >> though, > >> is this intended? > > > > Yes, since it saves needing to read in each DT just to get the > > compatible stringlist. > > The spec reads as if only one string (root) is supposed to be in the > list. > The script adds all compatibles though. This is not really useful as a > bootloader > that's compatible with e.g. fsl,imx8mm would just take the first device > tree > with that SoC, which is most likely to be wrong. It would be better to > just > specify the top-level compatible, so the bootloader fails instead of > taking > the first DT it finds. > >>> > >>> We do need to have a list, since we have to support different board revs, > >>> etc. > >> > >> Can you give me an example? The way I see it, a bootloader with > >> compatible "vendor,board" and a FIT with configuration with compatibles: > >> > >> "vendor,board-rev-a", "vendor,board" > >> "vendor,board-rev-b", "vendor,board" > >> > >> would just result in the bootloader booting the first configuration, even > >> if > >> the device is actually rev-b. > > > > You need to find the best match, not just any match. This is > > documented in the function comment for fit_conf_find_compat(). > > In my above example, both configuration are equally good. > Can you give me an example where it makes sense to have multiple > compatibles automatically extracted from the device tree compatible? > > The way I see it having more than one compatible here just has > downsides. I don't have an example to hand, but this is the required mechanism of FIT. This feature has been in place for many years and is used by ChromeOS, at least. > > >> The configuration already has a compatible entry. What extra use is the > >> compatible > >> entry in the FDT node? > > > > It allows seeing the compatible stringlist without having to read the > > FDT itself. I don't believe it is necessary though, so long as we are > > scanning the configurations and not the FDT nodes. > > I think it's better to drop this if it has no use. OK. I cannot think of a use for it. Regards, Simon
Re: [PATCH v7 2/2] arm64: boot: Support Flat Image Tree
Hi Ahmad, On Wed, 29 Nov 2023 at 11:35, Ahmad Fatoum wrote: > > Hello Simon, > > On 29.11.23 18:21, Simon Glass wrote: > > Add a script which produces a Flat Image Tree (FIT), a single file > > containing the built kernel and associated devicetree files. > > Compression defaults to gzip which gives a good balance of size and > > performance. > > Thanks for working on this. I think it's useful to have the kernel > generate a FIT image out of the box. More complex use cases are always > free to call mkimage with a custom ITS. > > > > The files compress from about 86MB to 24MB using this approach. > > > > The FIT can be used by bootloaders which support it, such as U-Boot > > and Linuxboot. It permits automatic selection of the correct > > devicetree, matching the compatible string of the running board with > > the closest compatible string in the FIT. There is no need for > > filenames or other workarounds. > > > > Add a 'make image.fit' build target for arm64, as well. > > not that it matters much, but should this maybe called Image.fit > as the other Image types are capitalized too? I missed this comment earlier. I believe Image is intended to refer to a raw image, with the other extensions being compressed versions of these. So I believe it would be confusing for the FIT version to have a capital I. > > > EFI_ZBOOT_PAYLOAD:= Image > > EFI_ZBOOT_BFD_TARGET := elf64-littleaarch64 > > EFI_ZBOOT_MACH_TYPE := ARM64 > > diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib > > index 1a965fe68e01..e1c06ca3c847 100644 > > --- a/scripts/Makefile.lib > > +++ b/scripts/Makefile.lib > > @@ -496,6 +496,19 @@ quiet_cmd_uimage = UIMAGE $@ > > -a $(UIMAGE_LOADADDR) -e $(UIMAGE_ENTRYADDR) \ > > -n '$(UIMAGE_NAME)' -d $< $@ > > Doesn't hardcoding a load address and entry address here defeat the point > of having FIT as generic portable image format? > > At least barebox will try to place the kernel image at physical address 0 and > will exit with an error message if no SDRAM is located at that address. > The recommendation in that case is to omit load and entry address altogether > to have barebox find a suitable location, but I see now that the FIT > specification > requires a load and entry address. What would happen if U-Boot tries to load > this > FIT image on a board that has no DRAM at address 0? > > Please Cc me on subsequent revisions. I am interested in testing that this > works for barebox > too. I have added you. Regards, Simon
[PATCH v5 9/9] pmic: qcom: dont use dev_read_addr to get USID
Linux DTs stuff a value indicating if the USID is a USID or a GSID in the
reg property, the Linux SPMI driver then reads the two address cells
separately. U-boot's dev_read_addr() doesn't know how to handle this, so
use ofnode_read_u32_index() to get just the USID.
The Qcom pmic driver doesn't have support for GSID handling, so just
ignore the second value for now.
Signed-off-by: Caleb Connolly
---
doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt | 94
drivers/power/pmic/pmic_qcom.c | 13 +++-
2 files changed, 10 insertions(+), 97 deletions(-)
diff --git a/doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt
b/doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt
deleted file mode 100644
index eb78e3ae7703..
--- a/doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt
+++ /dev/null
@@ -1,94 +0,0 @@
- Qualcomm SPMI PMICs multi-function device bindings
-
-The Qualcomm SPMI series presently includes PM8941, PM8841 and PMA8084
-PMICs. These PMICs use a QPNP scheme through SPMI interface.
-QPNP is effectively a partitioning scheme for dividing the SPMI extended
-register space up into logical pieces, and set of fixed register
-locations/definitions within these regions, with some of these regions
-specifically used for interrupt handling.
-
-The QPNP PMICs are used with the Qualcomm Snapdragon series SoCs, and are
-interfaced to the chip via the SPMI (System Power Management Interface) bus.
-Support for multiple independent functions are implemented by splitting the
-16-bit SPMI slave address space into 256 smaller fixed-size regions, 256 bytes
-each. A function can consume one or more of these fixed-size register regions.
-
-Required properties:
-- compatible: Should contain one of:
- "qcom,pm660",
- "qcom,pm660l",
- "qcom,pm7325",
- "qcom,pm8004",
- "qcom,pm8005",
- "qcom,pm8019",
- "qcom,pm8028",
- "qcom,pm8110",
- "qcom,pm8150",
- "qcom,pm8150b",
- "qcom,pm8150c",
- "qcom,pm8150l",
- "qcom,pm8226",
- "qcom,pm8350c",
- "qcom,pm8841",
- "qcom,pm8901",
- "qcom,pm8909",
- "qcom,pm8916",
- "qcom,pm8941",
- "qcom,pm8950",
- "qcom,pm8953",
- "qcom,pm8994",
- "qcom,pm8998",
- "qcom,pma8084",
- "qcom,pmd9635",
- "qcom,pmi8950",
- "qcom,pmi8962",
- "qcom,pmi8994",
- "qcom,pmi8998",
- "qcom,pmk8002",
- "qcom,pmk8350",
- "qcom,pmr735a",
- "qcom,smb2351",
- or generalized "qcom,spmi-pmic".
-- reg: Specifies the SPMI USID slave address for this device.
- For more information see:
- Documentation/devicetree/bindings/spmi/spmi.yaml
-
-Required properties for peripheral child nodes:
-- compatible: Should contain "qcom,xxx", where "xxx" is a peripheral name.
-
-Optional properties for peripheral child nodes:
-- interrupts: Interrupts are specified as a 4-tuple. For more information
- see:
-
Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml
-- interrupt-names: Corresponding interrupt name to the interrupts property
-
-Each child node of SPMI slave id represents a function of the PMIC. In the
-example below the rtc device node represents a peripheral of pm8941
-SID = 0. The regulator device node represents a peripheral of pm8941 SID = 1.
-
-Example:
-
- spmi {
- compatible = "qcom,spmi-pmic-arb";
-
- pm8941@0 {
- compatible = "qcom,pm8941", "qcom,spmi-pmic";
- reg = <0x0 SPMI_USID>;
-
- rtc {
- compatible = "qcom,rtc";
- interrupts = <0x0 0x61 0x1
IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "alarm";
- };
- };
-
- pm8941@1 {
- compatible = "qcom,pm8941", "qcom,spmi-pmic";
- reg = <0x1 SPMI_USID>;
-
- regulator {
- compatible = "qcom,regulator";
- regulator-name = "8941_boost";
- };
- };
- };
diff --git a/drivers/power/pmic/pmic_qcom.c b/drivers/power/pmic/pmic_qcom.c
index ad8daf43f06f..f2ac6494811d 100644
--- a/drivers/power/pmic/pmic_qcom.c
+++ b/drivers/power/pmic/pmic_qcom.c
@@ -66,12 +66,19 @@ static const struct udevice_id pmic_qcom_ids[] = {
static int
[PATCH v5 8/9] spmi: msm: fix register range names
The core and chnl register ranges were swapped on SDM845. Fix it, and
fetch the register ranges by name instead of by index.
Drop the cosmetic "version" variable and clean up the debug logging.
Signed-off-by: Caleb Connolly
---
arch/arm/dts/qcs404-evb.dts| 7 +++--
arch/arm/dts/sdm845.dtsi | 2 +-
doc/device-tree-bindings/spmi/spmi-msm.txt | 26 -
drivers/spmi/spmi-msm.c| 46 --
4 files changed, 23 insertions(+), 58 deletions(-)
diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts
index 3bb580ba4e17..cf41e5a33dbe 100644
--- a/arch/arm/dts/qcs404-evb.dts
+++ b/arch/arm/dts/qcs404-evb.dts
@@ -362,9 +362,10 @@
spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
- reg = <0x200f000 0x1000
- 0x240 0x40
- 0x2c0 0x40>;
+ reg = <0x200f000 0x001000>,
+ <0x240 0x80>,
+ <0x2c0 0x80>;
+ reg-names = "core", "chnls", "obsrvr";
#address-cells = <0x1>;
#size-cells = <0x1>;
diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
index a26e9f411ee0..96c9749a52c0 100644
--- a/arch/arm/dts/sdm845.dtsi
+++ b/arch/arm/dts/sdm845.dtsi
@@ -63,7 +63,7 @@
reg = <0xc44 0x1100>,
<0xc60 0x200>,
<0xe60 0x10>;
- reg-names = "cnfg", "core", "obsrvr";
+ reg-names = "core", "chnls", "obsrvr";
#address-cells = <0x1>;
#size-cells = <0x1>;
diff --git a/doc/device-tree-bindings/spmi/spmi-msm.txt
b/doc/device-tree-bindings/spmi/spmi-msm.txt
deleted file mode 100644
index ae47673b768b..
--- a/doc/device-tree-bindings/spmi/spmi-msm.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Qualcomm SPMI arbiter/bus driver
-
-This is bus driver for Qualcomm chips that use SPMI to communicate with PMICs.
-
-Required properties:
-- compatible: "qcom,spmi-pmic-arb"
-- reg: Register block adresses and sizes for various parts of device:
- 1) PMIC arbiter channel mapping base (PMIC_ARB_REG_CHNLn)
- 2) SPMI write command (master) registers (PMIC_ARB_CORE_SW_DEC_CHANNELS)
- 3) SPMI read command (observer) registers (PMIC_ARB_CORE_REGISTERS_OBS)
-
-Optional properties (if not set by parent):
-- #address-cells: 0x1 - childs slave ID address
-- #size-cells: 0x1
-
-All PMICs should be placed as a child nodes of bus arbiter.
-Automatic detection of childs is currently not supported.
-
-Example:
-
-spmi@200f000 {
- compatible = "qcom,spmi-pmic-arb";
- reg = <0x200f800 0x200 0x240 0x40 0x2c0 0x40>;
- #address-cells = <0x1>;
- #size-cells = <0x1>;
-};
diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
index 27a035c0a595..5fe8a70abca7 100644
--- a/drivers/spmi/spmi-msm.c
+++ b/drivers/spmi/spmi-msm.c
@@ -70,7 +70,7 @@ enum pmic_arb_channel {
struct msm_spmi_priv {
phys_addr_t arb_chnl; /* ARB channel mapping base */
- phys_addr_t spmi_core; /* SPMI core */
+ phys_addr_t spmi_chnls; /* SPMI channels */
phys_addr_t spmi_obs; /* SPMI observer */
/* SPMI channel map */
uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
@@ -95,10 +95,10 @@ static int msm_spmi_write(struct udevice *dev, int usid,
int pid, int off,
/* Disable IRQ mode for the current channel*/
writel(0x0,
- priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
+ priv->spmi_chnls + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
/* Write single byte */
- writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
+ writel(val, priv->spmi_chnls + SPMI_CH_OFFSET(channel) +
SPMI_REG_WDATA);
/* Prepare write command */
reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
@@ -113,12 +113,12 @@ static int msm_spmi_write(struct udevice *dev, int usid,
int pid, int off,
ch_offset = SPMI_CH_OFFSET(channel);
/* Send write command */
- writel(reg, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
+ writel(reg, priv->spmi_chnls + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
/* Wait till CMD DONE status */
reg = 0;
while (!reg) {
- reg = readl(priv->spmi_core + SPMI_CH_OFFSET(channel) +
+ reg = readl(priv->spmi_chnls + SPMI_CH_OFFSET(channel) +
SPMI_REG_STATUS);
}
@@ -186,47 +186,37 @@ static struct dm_spmi_ops msm_spmi_ops = {
static int msm_spmi_probe(struct udevice *dev)
{
struct msm_spmi_priv *priv = dev_get_priv(dev);
- phys_addr_t
[PATCH v5 6/9] dts: qcom: adjust pmic gpio to use upstream bindings
Use the upstream gpio-ranges property instead of gpio-count, and drop the bank-name property for Qualcomm boards. Signed-off-by: Caleb Connolly --- arch/arm/dts/dragonboard410c.dts | 3 +-- arch/arm/dts/dragonboard820c.dts | 3 +-- arch/arm/dts/qcs404-evb.dts | 2 +- arch/arm/dts/sdm845.dtsi | 3 +-- 4 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts index c41fee977813..6a4e3ccf17b1 100644 --- a/arch/arm/dts/dragonboard410c.dts +++ b/arch/arm/dts/dragonboard410c.dts @@ -170,9 +170,8 @@ compatible = "qcom,pm8916-gpio"; reg = <0xc000 0x400>; gpio-controller; - gpio-count = <4>; + gpio-ranges = <_gpios 0 0 4>; #gpio-cells = <2>; - gpio-bank-name="pmic"; }; }; diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts index 0d9c9f7a4922..146a0af8aafe 100644 --- a/arch/arm/dts/dragonboard820c.dts +++ b/arch/arm/dts/dragonboard820c.dts @@ -132,9 +132,8 @@ compatible = "qcom,pm8994-gpio"; reg = <0xc000 0x400>; gpio-controller; - gpio-count = <24>; + gpio-ranges = <_gpios 0 0 22>; #gpio-cells = <2>; - gpio-bank-name="pm8994."; }; }; diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts index 84224a8a3d39..3bb580ba4e17 100644 --- a/arch/arm/dts/qcs404-evb.dts +++ b/arch/arm/dts/qcs404-evb.dts @@ -378,7 +378,7 @@ compatible = "qcom,pms405-gpio"; reg = <0xc000 0x400>; gpio-controller; - gpio-count = <12>; + gpio-ranges = <_gpios 0 0 12>; #gpio-cells = <2>; gpio-bank-name="pmic"; }; diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi index cd5d890e9a45..a26e9f411ee0 100644 --- a/arch/arm/dts/sdm845.dtsi +++ b/arch/arm/dts/sdm845.dtsi @@ -103,9 +103,8 @@ compatible = "qcom,pm8998-gpio"; reg = <0xc000 0x1a00>; gpio-controller; - gpio-count = <21>; + gpio-ranges = <_gpios 0 0 26>; #gpio-cells = <2>; - gpio-bank-name = "pm8998."; }; }; -- 2.42.1
[PATCH v5 7/9] gpio: qcom_pmic: drop gpio-count property
This property is not part of the dt bindings and all boards use the new
gpio-ranges property instead. Drop support for this.
Signed-off-by: Caleb Connolly
---
doc/device-tree-bindings/gpio/pm8916_gpio.txt | 48 ---
drivers/gpio/qcom_pmic_gpio.c | 13 +++-
2 files changed, 5 insertions(+), 56 deletions(-)
diff --git a/doc/device-tree-bindings/gpio/pm8916_gpio.txt
b/doc/device-tree-bindings/gpio/pm8916_gpio.txt
deleted file mode 100644
index 58185b833524..
--- a/doc/device-tree-bindings/gpio/pm8916_gpio.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-Driver for part of pm8916 PMIC - gpio and power/reset keys
-
-This device should be child of SPMI pmic.
-
-1) GPIO driver
-
-Required properties:
-- compatible: "qcom,pm8916-gpio"
-- reg: peripheral ID, size of register block
-- gpio-controller
-- gpio-count: number of GPIOs
-- #gpio-cells: 2
-
-Optional properties:
-- gpio-bank-name: name of bank (as default "pm8916" is used)
-
-Example:
-
-pmic_gpios: gpios@c000 {
- compatible = "qcom,pm8916-gpio";
- reg = <0xc000 0x400>;
- gpio-controller;
- gpio-count = <4>;
- #gpio-cells = <2>;
- gpio-bank-name="pmic";
-};
-
-
-2) Power/Reset key driver
-
-Required properties:
-- compatible: "qcom,pm8916-pwrkey"
-- reg: peripheral ID, size of register block
-- gpio-controller
-- #gpio-cells: 2
-
-Optional properties:
-- gpio-bank-name: name of bank (as default "pm8916_key" is used)
-
-
-Example:
-
-pmic_pon: pon@800 {
- compatible = "qcom,pm8916-pwrkey";
- reg = <0x800 0x96>;
- #gpio-cells = <2>;
- gpio-controller;
-};
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index 54f4dbd2b84e..1adc6566a36d 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -268,14 +268,11 @@ static int qcom_gpio_of_to_plat(struct udevice *dev)
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
int ret;
- uc_priv->gpio_count = dev_read_u32_default(dev, "gpio-count", 0);
- if (!uc_priv->gpio_count) {
- ret = qcom_gpio_of_parse_ranges(dev);
- if (ret > 0)
- uc_priv->gpio_count = ret;
- else
- return ret;
- }
+ ret = qcom_gpio_of_parse_ranges(dev);
+ if (ret > 0)
+ uc_priv->gpio_count = ret;
+ else
+ return ret;
uc_priv->bank_name = "pmic";
--
2.42.1
[PATCH v5 5/9] gpio: qcom_pmic: support upstream DT
Upstream uses the gpio-ranges property to define the number of GPIOs,
support for parsing this when gpio-count is unspecified
Additionally, drop the bank-name property as it isn't used in upstream,
and we can just hardcode the bank name instead.
Signed-off-by: Caleb Connolly
---
drivers/gpio/qcom_pmic_gpio.c | 39 ---
1 file changed, 32 insertions(+), 7 deletions(-)
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index 7b83c67fa464..54f4dbd2b84e 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -245,23 +245,48 @@ static int qcom_gpio_probe(struct udevice *dev)
return 0;
}
+/*
+ * Parse basic GPIO count specified via the gpio-ranges property
+ * as specified in Linux devicetrees
+ * Returns < 0 on error, otherwise gpio count
+ */
+static int qcom_gpio_of_parse_ranges(struct udevice *dev)
+{
+ int ret;
+ struct ofnode_phandle_args args;
+
+ ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "gpio-ranges",
+NULL, 3, 0, );
+ if (ret)
+ return log_msg_ret("gpio-ranges", ret);
+
+ return args.args[2];
+}
+
static int qcom_gpio_of_to_plat(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ int ret;
uc_priv->gpio_count = dev_read_u32_default(dev, "gpio-count", 0);
- uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
- if (uc_priv->bank_name == NULL)
- uc_priv->bank_name = "qcom_pmic";
+ if (!uc_priv->gpio_count) {
+ ret = qcom_gpio_of_parse_ranges(dev);
+ if (ret > 0)
+ uc_priv->gpio_count = ret;
+ else
+ return ret;
+ }
+
+ uc_priv->bank_name = "pmic";
return 0;
}
static const struct udevice_id qcom_gpio_ids[] = {
- { .compatible = "qcom,pm8916-gpio" },
- { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
- { .compatible = "qcom,pm8998-gpio" },
- { .compatible = "qcom,pms405-gpio" },
+ { .compatible = "qcom,pm8916-gpio", },
+ { .compatible = "qcom,pm8994-gpio", },
+ { .compatible = "qcom,pm8998-gpio", },
+ { .compatible = "qcom,pms405-gpio", },
{ }
};
--
2.42.1
[PATCH v5 4/9] gpio: qcom_pmic: drop pon GPIO driver
Remove the (now unused) GPIO driver for the power and resin buttons on
the PMIC.
Signed-off-by: Caleb Connolly
---
drivers/gpio/Kconfig | 3 +-
drivers/gpio/qcom_pmic_gpio.c | 104 --
2 files changed, 2 insertions(+), 105 deletions(-)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index ba42b0768e12..fbf77673c5e0 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -309,12 +309,13 @@ config CMD_PCA953X
config QCOM_PMIC_GPIO
bool "Qualcomm generic PMIC GPIO/keypad driver"
depends on DM_GPIO && PMIC_QCOM
+ select BUTTON
help
Support for GPIO pins and power/reset buttons found on
Qualcomm SoCs PMIC.
Default name for GPIO bank is "pm8916".
Power and reset buttons are placed in "pwkey_qcom" bank and
- have gpio numbers 0 and 1 respectively.
+ have gpio numbers 0 and 1 respectively.
config PCF8575_GPIO
bool "PCF8575 I2C GPIO Expander driver"
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index e5841f502953..7b83c67fa464 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -275,107 +275,3 @@ U_BOOT_DRIVER(qcom_pmic_gpio) = {
.priv_auto = sizeof(struct qcom_gpio_bank),
};
-
-/* Add pmic buttons as GPIO as well - there is no generic way for now */
-#define PON_INT_RT_STS0x10
-#define KPDPWR_ON_INT_BIT 0
-#define RESIN_ON_INT_BIT 1
-
-static int qcom_pwrkey_get_function(struct udevice *dev, unsigned offset)
-{
- return GPIOF_INPUT;
-}
-
-static int qcom_pwrkey_get_value(struct udevice *dev, unsigned offset)
-{
- struct qcom_gpio_bank *priv = dev_get_priv(dev);
-
- int reg = pmic_reg_read(dev->parent, priv->pid + PON_INT_RT_STS);
-
- if (reg < 0)
- return 0;
-
- switch (offset) {
- case 0: /* Power button */
- return (reg & BIT(KPDPWR_ON_INT_BIT)) != 0;
- break;
- case 1: /* Reset button */
- default:
- return (reg & BIT(RESIN_ON_INT_BIT)) != 0;
- break;
- }
-}
-
-/*
- * Since pmic buttons modelled as GPIO, we need empty direction functions
- * to trick u-boot button driver
- */
-static int qcom_pwrkey_direction_input(struct udevice *dev, unsigned int
offset)
-{
- return 0;
-}
-
-static int qcom_pwrkey_direction_output(struct udevice *dev, unsigned int
offset, int value)
-{
- return -EOPNOTSUPP;
-}
-
-static const struct dm_gpio_ops qcom_pwrkey_ops = {
- .get_value = qcom_pwrkey_get_value,
- .get_function = qcom_pwrkey_get_function,
- .direction_input= qcom_pwrkey_direction_input,
- .direction_output = qcom_pwrkey_direction_output,
-};
-
-static int qcom_pwrkey_probe(struct udevice *dev)
-{
- struct qcom_gpio_bank *priv = dev_get_priv(dev);
- int reg;
- u64 pid;
-
- pid = dev_read_addr(dev);
- if (pid == FDT_ADDR_T_NONE)
- return log_msg_ret("bad address", -EINVAL);
-
- priv->pid = pid;
-
- /* Do a sanity check */
- reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE);
- if (reg != 0x1)
- return log_msg_ret("bad type", -ENXIO);
-
- reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
- if ((reg & 0x5) == 0)
- return log_msg_ret("bad subtype", -ENXIO);
-
- return 0;
-}
-
-static int qcom_pwrkey_of_to_plat(struct udevice *dev)
-{
- struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-
- uc_priv->gpio_count = 2;
- uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
- if (uc_priv->bank_name == NULL)
- uc_priv->bank_name = "pwkey_qcom";
-
- return 0;
-}
-
-static const struct udevice_id qcom_pwrkey_ids[] = {
- { .compatible = "qcom,pm8916-pwrkey" },
- { .compatible = "qcom,pm8994-pwrkey" },
- { .compatible = "qcom,pm8998-pwrkey" },
- { }
-};
-
-U_BOOT_DRIVER(pwrkey_qcom) = {
- .name = "pwrkey_qcom",
- .id = UCLASS_GPIO,
- .of_match = qcom_pwrkey_ids,
- .of_to_plat = qcom_pwrkey_of_to_plat,
- .probe = qcom_pwrkey_probe,
- .ops= _pwrkey_ops,
- .priv_auto = sizeof(struct qcom_gpio_bank),
-};
--
2.42.1
[PATCH v5 3/9] mach-snapdragon: switch to PMIC button driver
The PMIC button driver is a much better representation of the hardware
here, adjust the boards to use upstream DT and the PMIC button driver
instead of exposing the buttons as GPIOs and relying on the GPIO-button
driver.
Signed-off-by: Caleb Connolly
---
arch/arm/dts/dragonboard410c-uboot.dtsi | 11 --
arch/arm/dts/dragonboard410c.dts | 22 +---
arch/arm/dts/dragonboard820c-uboot.dtsi | 12 ---
arch/arm/dts/dragonboard820c.dts | 23
arch/arm/dts/dragonboard845c-uboot.dtsi | 11 --
arch/arm/dts/dragonboard845c.dts | 4 +++
arch/arm/dts/sdm845.dtsi | 23 +---
arch/arm/dts/starqltechn-uboot.dtsi | 10 --
arch/arm/dts/starqltechn.dts | 20 +++
arch/arm/mach-snapdragon/Kconfig | 3 ++
arch/arm/mach-snapdragon/init_sdm845.c | 45 +---
board/qualcomm/dragonboard410c/dragonboard410c.c | 31 ++--
board/qualcomm/dragonboard820c/dragonboard820c.c | 29 +--
13 files changed, 91 insertions(+), 153 deletions(-)
diff --git a/arch/arm/dts/dragonboard410c-uboot.dtsi
b/arch/arm/dts/dragonboard410c-uboot.dtsi
index 3b0bd0ed0a1b..cec64bf80f99 100644
--- a/arch/arm/dts/dragonboard410c-uboot.dtsi
+++ b/arch/arm/dts/dragonboard410c-uboot.dtsi
@@ -42,14 +42,3 @@
gpios = <_gpios 3 0>;
};
};
-
-
-_pon {
- key_vol_down {
- gpios = <_pon 1 0>;
- };
-
- key_power {
- gpios = <_pon 0 0>;
- };
-};
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index 9230dd3fd96c..c41fee977813 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -147,11 +147,23 @@
#address-cells = <0x1>;
#size-cells = <0x1>;
- pm8916_pon: pm8916_pon@800 {
- compatible = "qcom,pm8916-pwrkey";
- reg = <0x800 0x96>;
- #gpio-cells = <2>;
- gpio-controller;
+ pon@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x800 0x100>;
+ mode-bootloader = <0x2>;
+ mode-recovery = <0x1>;
+
+ pwrkey {
+ compatible =
"qcom,pm8941-pwrkey";
+ debounce = <15625>;
+ bias-pull-up;
+ };
+
+ pm8916_resin: resin {
+ compatible =
"qcom,pm8941-resin";
+ debounce = <15625>;
+ bias-pull-up;
+ };
};
pm8916_gpios: pm8916_gpios@c000 {
diff --git a/arch/arm/dts/dragonboard820c-uboot.dtsi
b/arch/arm/dts/dragonboard820c-uboot.dtsi
index 457728a43ecb..d93c7c1fbdee 100644
--- a/arch/arm/dts/dragonboard820c-uboot.dtsi
+++ b/arch/arm/dts/dragonboard820c-uboot.dtsi
@@ -30,15 +30,3 @@
};
};
};
-
-_pon {
- key_vol_down {
- gpios = <_pon 1 0>;
- label = "key_vol_down";
- };
-
- key_power {
- gpios = <_pon 0 0>;
- label = "key_power";
- };
-};
diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
index ad201d48749c..0d9c9f7a4922 100644
--- a/arch/arm/dts/dragonboard820c.dts
+++ b/arch/arm/dts/dragonboard820c.dts
@@ -109,12 +109,23 @@
#address-cells = <0x1>;
#size-cells = <0x1>;
- pm8994_pon: pm8994_pon@800 {
- compatible = "qcom,pm8994-pwrkey";
- reg = <0x800 0x96>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-bank-name="pm8994_key.";
+ pm8994_pon: pon@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x800 0x100>;
+ mode-bootloader = <0x2>;
+ mode-recovery = <0x1>;
+
+ pwrkey {
+ compatible =
"qcom,pm8941-pwrkey";
+
[PATCH v5 2/9] button: qcom-pmic: introduce Qualcomm PMIC button driver
Qualcomm PMICs include a "pon" function which handles two buttons, the
power button and "resin" button (usually volume down). Introduce a new
driver following upstream Linux DT to enable these and map them to Enter
and Down respectively to enable use in boot menus.
Signed-off-by: Caleb Connolly
---
MAINTAINERS | 1 +
drivers/button/Kconfig| 9 +++
drivers/button/Makefile | 1 +
drivers/button/button-qcom-pmic.c | 165 ++
4 files changed, 176 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f6d63c8ab563..8cd102eaa070 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -572,6 +572,7 @@ M: Neil Armstrong
R: Sumit Garg
S: Maintained
F: arch/arm/mach-snapdragon/
+F: drivers/button/button-qcom-pmic.c
F: drivers/clk/qcom/
F: drivers/gpio/msm_gpio.c
F: drivers/mmc/msm_sdhci.c
diff --git a/drivers/button/Kconfig b/drivers/button/Kconfig
index 8ce2de37d62a..097b05f822e7 100644
--- a/drivers/button/Kconfig
+++ b/drivers/button/Kconfig
@@ -27,4 +27,13 @@ config BUTTON_GPIO
The GPIO driver must used driver model. Buttons are configured using
the device tree.
+config BUTTON_QCOM_PMIC
+ bool "Qualcomm power button"
+ depends on BUTTON
+ depends on PMIC_QCOM
+ help
+ Enable support for the power and "resin" (usually volume down) buttons
+ on Qualcomm SoCs. These will be configured as the Enter and Down keys
+ respectively, allowing navigation of bootmenu with buttons on device.
+
endmenu
diff --git a/drivers/button/Makefile b/drivers/button/Makefile
index bbd18af14940..68555081a47a 100644
--- a/drivers/button/Makefile
+++ b/drivers/button/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_BUTTON) += button-uclass.o
obj-$(CONFIG_BUTTON_ADC) += button-adc.o
obj-$(CONFIG_BUTTON_GPIO) += button-gpio.o
+obj-$(CONFIG_BUTTON_QCOM_PMIC) += button-qcom-pmic.o
\ No newline at end of file
diff --git a/drivers/button/button-qcom-pmic.c
b/drivers/button/button-qcom-pmic.c
new file mode 100644
index ..34a976d1e6c6
--- /dev/null
+++ b/drivers/button/button-qcom-pmic.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm generic pmic gpio driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski
+ * (C) Copyright 2023 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define REG_TYPE 0x4
+#define REG_SUBTYPE0x5
+
+struct qcom_pmic_btn_priv {
+ u32 base;
+ u32 status_bit;
+ int code;
+ struct udevice *pmic;
+};
+
+#define PON_INT_RT_STS0x10
+#define KPDPWR_ON_INT_BIT 0
+#define RESIN_ON_INT_BIT 1
+
+#define NODE_IS_PWRKEY(node) (!strncmp(ofnode_get_name(node), "pwrkey",
strlen("pwrkey")))
+#define NODE_IS_RESIN(node) (!strncmp(ofnode_get_name(node), "resin",
strlen("resin")))
+
+static enum button_state_t qcom_pwrkey_get_state(struct udevice *dev)
+{
+ struct qcom_pmic_btn_priv *priv = dev_get_priv(dev);
+
+ int reg = pmic_reg_read(priv->pmic, priv->base + PON_INT_RT_STS);
+
+ if (reg < 0)
+ return 0;
+
+ return (reg & BIT(priv->status_bit)) != 0;
+}
+
+static int qcom_pwrkey_get_code(struct udevice *dev)
+{
+ struct qcom_pmic_btn_priv *priv = dev_get_priv(dev);
+
+ return priv->code;
+}
+
+static int qcom_pwrkey_probe(struct udevice *dev)
+{
+ struct button_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+ struct qcom_pmic_btn_priv *priv = dev_get_priv(dev);
+ ofnode node = dev_ofnode(dev);
+ int ret;
+ u64 base;
+
+ /* Ignore the top-level pon node */
+ if (!uc_plat->label)
+ return 0;
+
+ /* the pwrkey and resin nodes are children of the "pon" node, get the
+* PMIC device to use in pmic_reg_* calls.
+*/
+ priv->pmic = dev->parent->parent;
+
+ /* Get the address of the parent pon node */
+ base = dev_read_addr(dev->parent);
+ if (base == FDT_ADDR_T_NONE) {
+ printf("%s: Can't find address\n", dev->name);
+ return -EINVAL;
+ }
+
+ priv->base = base;
+
+ /* Do a sanity check */
+ ret = pmic_reg_read(priv->pmic, priv->base + REG_TYPE);
+ if (ret != 0x1 && ret != 0xb) {
+ printf("%s: unexpected PMIC function type %d\n", dev->name,
ret);
+ return -ENXIO;
+ }
+
+ ret = pmic_reg_read(priv->pmic, priv->base + REG_SUBTYPE);
+ if ((ret & 0x7) == 0) {
+ printf("%s: unexpected PMCI function subtype %d\n", dev->name,
ret);
+ return -ENXIO;
+ }
+
+ if (NODE_IS_PWRKEY(node)) {
+ priv->status_bit = 0;
+ priv->code = KEY_ENTER;
+ } else if (NODE_IS_RESIN(node)) {
+ priv->status_bit = 1;
+ priv->code =
[PATCH v5 0/9] Qualcomm PMIC fixes
This series addresses some long-standing issues with the SPMI arb
driver, the PMIC, and the PMIC GPIO. It fixes compatibility with
upstream Linux devicetrees, and simplifies pwrkey/resin support by
rewriting the pon driver to be a button driver rather than a GPIO
driver.
Existing users are adjusted to use the new button driver in their
oard init code.
This series is based on the pinctrl [1] and clock [2] cleanup series.
There may be some DTS conflicts applying it standalone.
[1]:
https://lore.kernel.org/u-boot/20231106-b4-qcom-pinctrl-v2-0-406e8d868...@linaro.org/
[2]:
https://lore.kernel.org/u-boot/20231103-b4-qcom-clk-v3-0-8d2d460ec...@linaro.org/
---
Changes in v5:
- Split "rework pwrkey driver into a button driver" into multiple
commits
- Split "qcom_pmic: fix support for upstream DT" into multiple commits
- Link to v4:
https://lore.kernel.org/r/20231128-b4-qcom-dt-compat-v4-0-949d0982d...@linaro.org
Changes in v4:
* Remove some now unsupported DT binding docs
* Fix qcs404 SPMI arb dts
* Link to v3:
https://lore.kernel.org/r/20231114-b4-qcom-dt-compat-v3-0-88a92f8f0...@linaro.org
Changes in v3:
* Remove now-unneeded header includes in dragonboard{410,820}c-uboot.dtsi
* Drop non-standard DTS support from PMIC GPIO driver
* Also remove old gpio-keys nodes from starqltechn-uboot.dtsi
* Link to v2:
https://lore.kernel.org/r/20231108-b4-qcom-dt-compat-v2-0-713233c72...@linaro.org
Changes in v2:
* Avoid using non-standard "label" and "linux,code" properties for
buttons
* Add missing sdm845 DTS parts
* Put button driver in drivers/button
* Link to v1:
https://lore.kernel.org/r/20231106-b4-qcom-dt-compat-v1-0-0ccbb7841...@linaro.org
---
Caleb Connolly (9):
gpio: qcom_pmic: fix silent dev_read_addr downcast
button: qcom-pmic: introduce Qualcomm PMIC button driver
mach-snapdragon: switch to PMIC button driver
gpio: qcom_pmic: drop pon GPIO driver
gpio: qcom_pmic: support upstream DT
dts: qcom: adjust pmic gpio to use upstream bindings
gpio: qcom_pmic: drop gpio-count property
spmi: msm: fix register range names
pmic: qcom: dont use dev_read_addr to get USID
MAINTAINERS | 1 +
arch/arm/dts/dragonboard410c-uboot.dtsi | 11 --
arch/arm/dts/dragonboard410c.dts | 25 +++-
arch/arm/dts/dragonboard820c-uboot.dtsi | 12 --
arch/arm/dts/dragonboard820c.dts | 26 ++--
arch/arm/dts/dragonboard845c-uboot.dtsi | 11 --
arch/arm/dts/dragonboard845c.dts | 4 +
arch/arm/dts/qcs404-evb.dts | 9 +-
arch/arm/dts/sdm845.dtsi | 28 ++--
arch/arm/dts/starqltechn-uboot.dtsi | 10 --
arch/arm/dts/starqltechn.dts | 20 +--
arch/arm/mach-snapdragon/Kconfig | 3 +
arch/arm/mach-snapdragon/init_sdm845.c | 45 ++-
board/qualcomm/dragonboard410c/dragonboard410c.c | 31 ++---
board/qualcomm/dragonboard820c/dragonboard820c.c | 29 ++--
doc/device-tree-bindings/gpio/pm8916_gpio.txt| 48 ---
doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt | 94 -
doc/device-tree-bindings/spmi/spmi-msm.txt | 26
drivers/button/Kconfig | 9 ++
drivers/button/Makefile | 1 +
drivers/button/button-qcom-pmic.c| 165 +++
drivers/gpio/Kconfig | 3 +-
drivers/gpio/qcom_pmic_gpio.c| 146 +---
drivers/power/pmic/pmic_qcom.c | 13 +-
drivers/spmi/spmi-msm.c | 46 +++
25 files changed, 341 insertions(+), 475 deletions(-)
---
base-commit: 4d5dd7090b5ad770974a377f704907893469ebb3
// Caleb (they/them)
[PATCH v5 1/9] gpio: qcom_pmic: fix silent dev_read_addr downcast
priv->pid is uint32_t, but dev_read_addr() returns a uint64_t on arm64,
with the upper bits being used for error codes. Do error checking before
downcasting to u32 to prevent errors being silently ignored.
Reviewed-by: Sumit Garg
Signed-off-by: Caleb Connolly
---
drivers/gpio/qcom_pmic_gpio.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index 65feb453ebc3..e5841f502953 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -221,11 +221,14 @@ static int qcom_gpio_probe(struct udevice *dev)
{
struct qcom_gpio_bank *priv = dev_get_priv(dev);
int reg;
+ u64 pid;
- priv->pid = dev_read_addr(dev);
- if (priv->pid == FDT_ADDR_T_NONE)
+ pid = dev_read_addr(dev);
+ if (pid == FDT_ADDR_T_NONE)
return log_msg_ret("bad address", -EINVAL);
+ priv->pid = pid;
+
/* Do a sanity check */
reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE);
if (reg != REG_TYPE_VAL)
@@ -328,11 +331,14 @@ static int qcom_pwrkey_probe(struct udevice *dev)
{
struct qcom_gpio_bank *priv = dev_get_priv(dev);
int reg;
+ u64 pid;
- priv->pid = dev_read_addr(dev);
- if (priv->pid == FDT_ADDR_T_NONE)
+ pid = dev_read_addr(dev);
+ if (pid == FDT_ADDR_T_NONE)
return log_msg_ret("bad address", -EINVAL);
+ priv->pid = pid;
+
/* Do a sanity check */
reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE);
if (reg != 0x1)
--
2.42.1
[PATCH 7/7] pinctrl: exynos: Convert to use livetree API for fdt access
Use counterpart dev_read_* functions instead of fdt* ones. It fixes
checkpatch warnings like this:
WARNING: Use the livetree API (dev_read_...)
#54: FILE: drivers/pinctrl/exynos/pinctrl-exynos.c:137:
pinvals[idx] = fdtdec_get_int(fdt, node,
and also makes it possible to avoid using the global data pointer in the
driver.
No functional change.
Signed-off-by: Sam Protsenko
---
drivers/pinctrl/exynos/pinctrl-exynos.c | 20
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c
b/drivers/pinctrl/exynos/pinctrl-exynos.c
index b6af3befbf9b..8a045cdf7aa8 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.c
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.c
@@ -9,12 +9,9 @@
#include
#include
#include
-#include
#include
#include "pinctrl-exynos.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/* CON, DAT, PUD, DRV */
const struct samsung_pin_bank_type bank_type_alive = {
.fld_width = { 4, 1, 2, 2, },
@@ -118,8 +115,6 @@ static void exynos_pinctrl_set_pincfg(unsigned long
reg_base, u32 pin_num,
int exynos_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
- const void *fdt = gd->fdt_blob;
- int node = dev_of_offset(config);
unsigned int count, idx;
unsigned int pinvals[PINCFG_TYPE_NUM];
@@ -127,13 +122,13 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
* refer to the following document for the pinctrl bindings
* linux/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
*/
- count = fdt_stringlist_count(fdt, node, "samsung,pins");
+ count = dev_read_string_count(config, "samsung,pins");
if (count <= 0)
return -EINVAL;
for (idx = 0; idx < PINCFG_TYPE_NUM; ++idx) {
- pinvals[idx] = fdtdec_get_int(fdt, node,
- exynos_pinctrl_props[idx], -1);
+ pinvals[idx] = dev_read_u32_default(config,
+ exynos_pinctrl_props[idx], -1);
}
pinvals[PINCFG_TYPE_DAT] = -1; /* ignore GPIO data register */
@@ -142,12 +137,13 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
unsigned int pin_num;
char bank_name[10];
unsigned long reg;
- const char *name;
- int pincfg;
+ const char *name = NULL;
+ int pincfg, err;
- name = fdt_stringlist_get(fdt, node, "samsung,pins", idx, NULL);
- if (!name)
+ err = dev_read_string_index(config, "samsung,pins", idx, );
+ if (err || !name)
continue;
+
parse_pin(name, _num, bank_name);
bank = get_bank(dev, bank_name);
reg = priv->base + bank->offset;
--
2.39.2
[PATCH 6/7] pinctrl: exynos: Reduce variables scope
Pull some variables declared in exynos_pinctrl_set_state() into its
loop, to reduce their scope. Style commit, no functional change.
Signed-off-by: Sam Protsenko
---
drivers/pinctrl/exynos/pinctrl-exynos.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c
b/drivers/pinctrl/exynos/pinctrl-exynos.c
index e79ce5113d84..b6af3befbf9b 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.c
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.c
@@ -120,10 +120,8 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(config);
- unsigned int count, idx, pin_num;
+ unsigned int count, idx;
unsigned int pinvals[PINCFG_TYPE_NUM];
- unsigned long reg;
- const char *name;
/*
* refer to the following document for the pinctrl bindings
@@ -141,7 +139,10 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
for (idx = 0; idx < count; idx++) {
const struct samsung_pin_bank_data *bank;
+ unsigned int pin_num;
char bank_name[10];
+ unsigned long reg;
+ const char *name;
int pincfg;
name = fdt_stringlist_get(fdt, node, "samsung,pins", idx, NULL);
--
2.39.2
[PATCH 5/7] pinctrl: exynos: Refactor handling the pin related dt properties
All pin related dt properties (pin-function, pin-pud and pin-drv) are
handled in a very similar way. Get rid of that code duplication by
extracting the corresponding data knowledge into an actual data
structure (array), and then just iterating over it.
No functional change, it's a refactoring commit.
Signed-off-by: Sam Protsenko
---
drivers/pinctrl/exynos/pinctrl-exynos.c | 35 ++---
1 file changed, 19 insertions(+), 16 deletions(-)
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c
b/drivers/pinctrl/exynos/pinctrl-exynos.c
index 9a51653be864..e79ce5113d84 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.c
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.c
@@ -21,6 +21,13 @@ const struct samsung_pin_bank_type bank_type_alive = {
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
};
+static const char * const exynos_pinctrl_props[PINCFG_TYPE_NUM] = {
+ [PINCFG_TYPE_FUNC] = "samsung,pin-function",
+ [PINCFG_TYPE_DAT] = "samsung,pin-val",
+ [PINCFG_TYPE_PUD] = "samsung,pin-pud",
+ [PINCFG_TYPE_DRV] = "samsung,pin-drv",
+};
+
/**
* exynos_pinctrl_setup_peri: setup pinctrl for a peripheral.
* conf: soc specific pin configuration data array
@@ -114,7 +121,7 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(config);
unsigned int count, idx, pin_num;
- unsigned int pinfunc, pinpud, pindrv;
+ unsigned int pinvals[PINCFG_TYPE_NUM];
unsigned long reg;
const char *name;
@@ -126,13 +133,16 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
if (count <= 0)
return -EINVAL;
- pinfunc = fdtdec_get_int(fdt, node, "samsung,pin-function", -1);
- pinpud = fdtdec_get_int(fdt, node, "samsung,pin-pud", -1);
- pindrv = fdtdec_get_int(fdt, node, "samsung,pin-drv", -1);
+ for (idx = 0; idx < PINCFG_TYPE_NUM; ++idx) {
+ pinvals[idx] = fdtdec_get_int(fdt, node,
+ exynos_pinctrl_props[idx], -1);
+ }
+ pinvals[PINCFG_TYPE_DAT] = -1; /* ignore GPIO data register */
for (idx = 0; idx < count; idx++) {
const struct samsung_pin_bank_data *bank;
char bank_name[10];
+ int pincfg;
name = fdt_stringlist_get(fdt, node, "samsung,pins", idx, NULL);
if (!name)
@@ -141,19 +151,12 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
bank = get_bank(dev, bank_name);
reg = priv->base + bank->offset;
- if (pinfunc != -1) {
- exynos_pinctrl_set_pincfg(reg, pin_num, pinfunc,
- PINCFG_TYPE_FUNC, bank->type);
- }
-
- if (pinpud != -1) {
- exynos_pinctrl_set_pincfg(reg, pin_num, pinpud,
- PINCFG_TYPE_PUD, bank->type);
- }
+ for (pincfg = 0; pincfg < PINCFG_TYPE_NUM; ++pincfg) {
+ unsigned int val = pinvals[pincfg];
- if (pindrv != -1) {
- exynos_pinctrl_set_pincfg(reg, pin_num, pindrv,
- PINCFG_TYPE_DRV, bank->type);
+ if (val != -1)
+ exynos_pinctrl_set_pincfg(reg, pin_num, val,
+ pincfg, bank->type);
}
}
--
2.39.2
[PATCH 4/7] pinctrl: exynos: Support different register types in pin banks
Get rid of hard-coded register offsets and widths. Instead provide a way
for pinctrl drivers to specify different pin bank register offsets and
widths. This in turn makes it possible to add support for new SoCs that
have registers with offset/width values different than generic ones
already available in pinctrl-exynos driver.
Offset constants (now unused in pinctrl-exynos.c) are moved to
pinctrl-exynos7420 driver, which is the single user of those constants.
The design of this patch follows Linux kernel pinctrl-exynos driver
design, in terms of added data structures and types. This patch doesn't
add support for any new SoCs and shouldn't introduce any functional
changes.
Signed-off-by: Sam Protsenko
---
drivers/pinctrl/exynos/pinctrl-exynos.c | 42 ++---
drivers/pinctrl/exynos/pinctrl-exynos.h | 34 +++--
drivers/pinctrl/exynos/pinctrl-exynos7420.c | 2 +
3 files changed, 61 insertions(+), 17 deletions(-)
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c
b/drivers/pinctrl/exynos/pinctrl-exynos.c
index d908927135b6..9a51653be864 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.c
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.c
@@ -15,6 +15,12 @@
DECLARE_GLOBAL_DATA_PTR;
+/* CON, DAT, PUD, DRV */
+const struct samsung_pin_bank_type bank_type_alive = {
+ .fld_width = { 4, 1, 2, 2, },
+ .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
+};
+
/**
* exynos_pinctrl_setup_peri: setup pinctrl for a peripheral.
* conf: soc specific pin configuration data array
@@ -81,6 +87,22 @@ static const struct samsung_pin_bank_data *get_bank(struct
udevice *dev,
return NULL;
}
+static void exynos_pinctrl_set_pincfg(unsigned long reg_base, u32 pin_num,
+ u32 val, enum pincfg_type pincfg,
+ const struct samsung_pin_bank_type *type)
+{
+ u32 width = type->fld_width[pincfg];
+ u32 reg_offset = type->reg_offset[pincfg];
+ u32 mask = (1 << width) - 1;
+ u32 shift = pin_num * width;
+ u32 data;
+
+ data = readl(reg_base + reg_offset);
+ data &= ~(mask << shift);
+ data |= val << shift;
+ writel(data, reg_base + reg_offset);
+}
+
/**
* exynos_pinctrl_set_state: configure a pin state.
* dev: the pinctrl device to be configured.
@@ -93,7 +115,7 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
int node = dev_of_offset(config);
unsigned int count, idx, pin_num;
unsigned int pinfunc, pinpud, pindrv;
- unsigned long reg, value;
+ unsigned long reg;
const char *name;
/*
@@ -120,24 +142,18 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
reg = priv->base + bank->offset;
if (pinfunc != -1) {
- value = readl(reg + PIN_CON);
- value &= ~(0xf << (pin_num << 2));
- value |= (pinfunc << (pin_num << 2));
- writel(value, reg + PIN_CON);
+ exynos_pinctrl_set_pincfg(reg, pin_num, pinfunc,
+ PINCFG_TYPE_FUNC, bank->type);
}
if (pinpud != -1) {
- value = readl(reg + PIN_PUD);
- value &= ~(0x3 << (pin_num << 1));
- value |= (pinpud << (pin_num << 1));
- writel(value, reg + PIN_PUD);
+ exynos_pinctrl_set_pincfg(reg, pin_num, pinpud,
+ PINCFG_TYPE_PUD, bank->type);
}
if (pindrv != -1) {
- value = readl(reg + PIN_DRV);
- value &= ~(0x3 << (pin_num << 1));
- value |= (pindrv << (pin_num << 1));
- writel(value, reg + PIN_DRV);
+ exynos_pinctrl_set_pincfg(reg, pin_num, pindrv,
+ PINCFG_TYPE_DRV, bank->type);
}
}
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.h
b/drivers/pinctrl/exynos/pinctrl-exynos.h
index 6b19f196bc3a..743bb5573091 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.h
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.h
@@ -8,25 +8,51 @@
#ifndef __PINCTRL_EXYNOS_H_
#define __PINCTRL_EXYNOS_H_
-#define PIN_CON0x00/* Offset of pin function register */
-#define PIN_DAT0x04/* Offset of pin data register */
-#define PIN_PUD0x08/* Offset of pin pull up/down config
register */
-#define PIN_DRV0x0C/* Offset of pin drive strength
register */
+/**
+ * enum pincfg_type - possible pin configuration types supported.
+ * @PINCFG_TYPE_FUNC: Function configuration.
+ * @PINCFG_TYPE_DAT: Pin value configuration.
+ * @PINCFG_TYPE_PUD: Pull up/down configuration.
+ *
[PATCH 3/7] pinctrl: exynos: Rework pin_to_bank_base() to obtain data by name
Rework pin_to_bank_base() function to obtain bank data structure by bank
name instead of getting bank base address by pin name, and rename it to
get_bank() to reflect this change. This in turn leads to the extraction
of parse_pin(), so the caller has to use it before calling get_bank().
No functional change. This is a refactoring commit which prepares
pinctrl driver code for handling different sizes of register fields,
which will be added next.
Signed-off-by: Sam Protsenko
---
drivers/pinctrl/exynos/pinctrl-exynos.c | 27 +
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c
b/drivers/pinctrl/exynos/pinctrl-exynos.c
index 2d194ba0a4b5..d908927135b6 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.c
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.c
@@ -50,17 +50,14 @@ static void parse_pin(const char *pin_name, u32 *pin, char
*bank_name)
*pin = pin_name[++idx] - '0';
}
-/* given a pin-name, return the address of pin config registers */
-static unsigned long pin_to_bank_base(struct udevice *dev, const char
*pin_name,
- u32 *pin)
+/* given a bank name, find out the pin bank structure */
+static const struct samsung_pin_bank_data *get_bank(struct udevice *dev,
+ const char *bank_name)
{
struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
const struct samsung_pin_ctrl *pin_ctrl_array = priv->pin_ctrl;
const struct samsung_pin_bank_data *bank_data;
- u32 nr_banks, pin_ctrl_idx = 0, idx = 0, bank_base;
- char bank[10];
-
- parse_pin(pin_name, pin, bank);
+ u32 nr_banks, pin_ctrl_idx = 0, idx = 0;
/* lookup the pin bank data using the pin bank name */
while (true) {
@@ -75,15 +72,13 @@ static unsigned long pin_to_bank_base(struct udevice *dev,
const char *pin_name,
for (idx = 0; idx < nr_banks; idx++) {
debug("pinctrl[%d] bank_data[%d] name is: %s\n",
pin_ctrl_idx, idx, bank_data[idx].name);
- if (!strcmp(bank, bank_data[idx].name)) {
- bank_base = priv->base + bank_data[idx].offset;
- break;
- }
+ if (!strcmp(bank_name, bank_data[idx].name))
+ return _data[idx];
}
pin_ctrl_idx++;
}
- return bank_base;
+ return NULL;
}
/**
@@ -93,6 +88,7 @@ static unsigned long pin_to_bank_base(struct udevice *dev,
const char *pin_name,
*/
int exynos_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
+ struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(config);
unsigned int count, idx, pin_num;
@@ -113,10 +109,15 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
pindrv = fdtdec_get_int(fdt, node, "samsung,pin-drv", -1);
for (idx = 0; idx < count; idx++) {
+ const struct samsung_pin_bank_data *bank;
+ char bank_name[10];
+
name = fdt_stringlist_get(fdt, node, "samsung,pins", idx, NULL);
if (!name)
continue;
- reg = pin_to_bank_base(dev, name, _num);
+ parse_pin(name, _num, bank_name);
+ bank = get_bank(dev, bank_name);
+ reg = priv->base + bank->offset;
if (pinfunc != -1) {
value = readl(reg + PIN_CON);
--
2.39.2
[PATCH 2/7] pinctrl: exynos: Extract pin parsing code into a separate function
Next commits are going to re-design the pin_to_bank_base() function and
its usage in a way that the pin parsing code will be called separately.
Extract it into a separate function first, as a refactoring commit.
No functional change.
Signed-off-by: Sam Protsenko
---
drivers/pinctrl/exynos/pinctrl-exynos.c | 27 -
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c
b/drivers/pinctrl/exynos/pinctrl-exynos.c
index 995a3a0ee5fd..2d194ba0a4b5 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.c
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.c
@@ -34,6 +34,22 @@ void exynos_pinctrl_setup_peri(struct
exynos_pinctrl_config_data *conf,
}
}
+static void parse_pin(const char *pin_name, u32 *pin, char *bank_name)
+{
+ u32 idx = 0;
+
+ /*
+* The format of the pin name is -.
+* Example: gpa0-4 (gpa0 is the bank_name name and 4 is the pin number.
+*/
+ while (pin_name[idx] != '-') {
+ bank_name[idx] = pin_name[idx];
+ idx++;
+ }
+ bank_name[idx] = '\0';
+ *pin = pin_name[++idx] - '0';
+}
+
/* given a pin-name, return the address of pin config registers */
static unsigned long pin_to_bank_base(struct udevice *dev, const char
*pin_name,
u32 *pin)
@@ -44,16 +60,7 @@ static unsigned long pin_to_bank_base(struct udevice *dev,
const char *pin_name,
u32 nr_banks, pin_ctrl_idx = 0, idx = 0, bank_base;
char bank[10];
- /*
-* The format of the pin name is -.
-* Example: gpa0-4 (gpa0 is the bank name and 4 is the pin number.
-*/
- while (pin_name[idx] != '-') {
- bank[idx] = pin_name[idx];
- idx++;
- }
- bank[idx] = '\0';
- *pin = pin_name[++idx] - '0';
+ parse_pin(pin_name, pin, bank);
/* lookup the pin bank data using the pin bank name */
while (true) {
--
2.39.2
[PATCH 1/7] pinctrl: exynos: Improve coding style
Style commit, no functional change.
Signed-off-by: Sam Protsenko
---
drivers/pinctrl/exynos/pinctrl-exynos.c | 3 ++-
drivers/pinctrl/exynos/pinctrl-exynos.h | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c
b/drivers/pinctrl/exynos/pinctrl-exynos.c
index 898185479ba3..995a3a0ee5fd 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.c
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.c
@@ -57,7 +57,8 @@ static unsigned long pin_to_bank_base(struct udevice *dev,
const char *pin_name,
/* lookup the pin bank data using the pin bank name */
while (true) {
- const struct samsung_pin_ctrl *pin_ctrl =
_ctrl_array[pin_ctrl_idx];
+ const struct samsung_pin_ctrl *pin_ctrl =
+ _ctrl_array[pin_ctrl_idx];
nr_banks = pin_ctrl->nr_banks;
if (!nr_banks)
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.h
b/drivers/pinctrl/exynos/pinctrl-exynos.h
index cbc5174b48cb..6b19f196bc3a 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.h
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.h
@@ -27,7 +27,7 @@ struct samsung_pin_bank_data {
#define EXYNOS_PIN_BANK(pins, reg, id) \
{ \
- .offset = reg, \
+ .offset = reg, \
.nr_pins= pins, \
.name = id\
}
--
2.39.2
[PATCH 0/7] pinctrl: exynos: Prepare for other SoCs support
Some Exynos SoCs (not supported by pinctrl-exynos driver yet) have different offsets and widths of pin bank registers (i.e. PIN_CON, PIN_PUD and PIN_DRV registers). Rework pinctrl-exynos driver so it allows for different offsets and widths of those registers by adding the corresponding API. That makes it possible to add the support for new Exynos SoCs in pinctrl-exynos driver. The main patch in this series is: pinctrl: exynos: Support different register types in pin banks Other patches are just related cleanups and refactoring commits, required for the clean implementation of the main patch. Sam Protsenko (7): pinctrl: exynos: Improve coding style pinctrl: exynos: Extract pin parsing code into a separate function pinctrl: exynos: Rework pin_to_bank_base() to obtain data by name pinctrl: exynos: Support different register types in pin banks pinctrl: exynos: Refactor handling the pin related dt properties pinctrl: exynos: Reduce variables scope pinctrl: exynos: Convert to use livetree API for fdt access drivers/pinctrl/exynos/pinctrl-exynos.c | 125 drivers/pinctrl/exynos/pinctrl-exynos.h | 36 +- drivers/pinctrl/exynos/pinctrl-exynos7420.c | 2 + 3 files changed, 108 insertions(+), 55 deletions(-) -- 2.39.2
Re: [PATCH v1] cmd: mtd: OTP access support
On 30.11.2023 16:35, Michael Walle wrote:
>> +static int do_mtd_otp_write(struct cmd_tbl *cmdtp, int flag, int argc,
>> + char *const argv[])
>> +{
> ..
>
>> + printf("Caution! OTP data bits can't be erased! Continue (y/n)?\n");
>
> Please note, that with current SPI-NOR flashes this is not true and
> there is usually some kind of erase command for the OTP bits. Only
> the region lock is permanent and with that set, no more write or erase
> is possible.
I see, so may be just rephrase this message, like just "Continue? (y/n)?"
Thanks, Arseniy
>
> -michael
Re: Please pull u-boot-tegra staging
On Thu, Nov 30, 2023 at 09:50:36AM +0200, Svyatoslav Ryhel wrote: > Dear Tom, > > The following changes since commit acae7eb5fe063dcfe2dbdb1e1804cf3e12cc2f3f: > > i2c: Bugfix in i2c_get_chip_by_phandle() (2023-11-27 18:54:56 -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-tegra.git staging > > for you to fetch changes up to e22d5799dc86298ad8388ddcb3b759e166c142b7: > > ARM: dts: tegra30: enable USB PHY node on some devices (2023-11-28 09:17:18 > +0200) > Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v7 2/2] arm64: boot: Support Flat Image Tree
On Thu, Nov 30, 2023 at 2:22 AM Simon Glass wrote: > > Add a script which produces a Flat Image Tree (FIT), a single file > containing the built kernel and associated devicetree files. > Compression defaults to gzip which gives a good balance of size and > performance. > > The files compress from about 86MB to 24MB using this approach. > > The FIT can be used by bootloaders which support it, such as U-Boot > and Linuxboot. It permits automatic selection of the correct > devicetree, matching the compatible string of the running board with > the closest compatible string in the FIT. There is no need for > filenames or other workarounds. > > Add a 'make image.fit' build target for arm64, as well. > > The FIT can be examined using 'dumpimage -l'. > > This features requires pylibfdt (use 'pip install libfdt'). It also > requires compression utilities for the algorithm being used. Supported > compression options are the same as the Image.xxx files. For now there > is no way to change the compression other than by editing the rule for > $(obj)/image.fit > > While FIT supports a ramdisk / initrd, no attempt is made to support > this here, since it must be built separately from the Linux build. > > Signed-off-by: Simon Glass > --- > > Changes in v7: > - Add Image as a dependency of image.fit > - Drop kbuild tag > - Add dependency on dtbs > - Drop unnecessary path separator for dtbs > - Rebase to -next > > Changes in v5: > - Drop patch previously applied > - Correct compression rule which was broken in v4 > > Changes in v4: > - Use single quotes for UIMAGE_NAME > > Changes in v3: > - Drop temporary file image.itk > - Drop patch 'Use double quotes for image name' > - Drop double quotes in use of UIMAGE_NAME > - Drop unnecessary CONFIG_EFI_ZBOOT condition for help > - Avoid hard-coding "arm64" for the DT architecture > > Changes in v2: > - Drop patch previously applied > - Add .gitignore file > - Move fit rule to Makefile.lib using an intermediate file > - Drop dependency on CONFIG_EFI_ZBOOT > - Pick up .dtb files separately from the kernel > - Correct pylint too-many-args warning for write_kernel() > - Include the kernel image in the file count > - Add a pointer to the FIT spec and mention of its wide industry usage > - Mention the kernel version in the FIT description > > MAINTAINERS| 7 + > arch/arm64/Makefile| 9 +- > arch/arm64/boot/.gitignore | 1 + > arch/arm64/boot/Makefile | 6 +- > scripts/Makefile.lib | 13 ++ > scripts/make_fit.py| 289 + > 6 files changed, 322 insertions(+), 3 deletions(-) > create mode 100755 scripts/make_fit.py > > diff --git a/MAINTAINERS b/MAINTAINERS > index 14587be87a33..d609f0e8deb3 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1585,6 +1585,13 @@ F: Documentation/process/maintainer-soc*.rst > F: arch/arm/boot/dts/Makefile > F: arch/arm64/boot/dts/Makefile > > +ARM64 FIT SUPPORT > +M: Simon Glass > +L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) > +S: Maintained > +F: arch/arm64/boot/Makefile > +F: scripts/make_fit.py > + > ARM ARCHITECTED TIMER DRIVER > M: Mark Rutland > M: Marc Zyngier > diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile > index 1bd4fae6e806..18e092de7cdb 100644 > --- a/arch/arm64/Makefile > +++ b/arch/arm64/Makefile > @@ -36,6 +36,8 @@ ifeq ($(CONFIG_BROKEN_GAS_INST),y) > $(warning Detected assembler with broken .inst; disassembly will be > unreliable) > endif > > +KBUILD_DTBS := dtbs Please remove this, and hard-code image.fit: dtbs > > $(obj)/Image: vmlinux FORCE > $(call if_changed,objcopy) > @@ -39,6 +40,9 @@ $(obj)/Image.lzo: $(obj)/Image FORCE > $(obj)/Image.zst: $(obj)/Image FORCE > $(call if_changed,zstd) > > +$(obj)/image.fit: $(obj)/Image FORCE > + $(call cmd,fit,gzip) The gzip parameter is not used. Please do $(call cmd,fit) In the python script, functions are separated with two blank lines, but there is only one blank line between parse_args() and setup_fit(). I do not mind either way because it does not contain any class, but please keep consistency. -- Best Regards Masahiro Yamada
Re: [PATCH v5 17/17] board: ti: j784s4: Add MAINTAINERS file
On 11/30/23 5:55 AM, Apurva Nandan wrote: Add maintainership for new J784S4 files added. Signed-off-by: Apurva Nandan --- board/ti/j784s4/MAINTAINERS | 25 + 1 file changed, 25 insertions(+) create mode 100644 board/ti/j784s4/MAINTAINERS diff --git a/board/ti/j784s4/MAINTAINERS b/board/ti/j784s4/MAINTAINERS new file mode 100644 index 00..d3f0e50391 --- /dev/null +++ b/board/ti/j784s4/MAINTAINERS @@ -0,0 +1,25 @@ +J784S4 BOARD +M: Apurva Nandan +S: Maintained +F: board/ti/j784s4 +F: arch/arm/mach-k3/j784s4 The arch/arm/mach-k3/j784s4 files are not related to the board, other boards and board vendors can have different maintainers, and the SoC maintainer doesn't need to be a maintainer of any set of boards. I wonder if we should move the SoC level maintainer lines up into the main MAINTAINERS file, or add arch/arm/mach-k3/MAINTAINERS. Leaving only the board specific files in the board/**/MAINTAINERS file. Andrew +F: include/configs/j784s4_evm.h +F: configs/j784s4_evm_r5_defconfig +F: configs/j784s4_evm_a72_defconfig +F: arch/arm/dts/k3-j784s4.dtsi +F: arch/arm/dts/k3-j784s4-main.dtsi +F: arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi +F: arch/arm/dts/k3-j784s4-thermal.dtsi +F: arch/arm/dts/k3-j784s4-evm.dts +F: arch/arm/dts/k3-j784s4-evm-u-boot.dtsi +F: arch/arm/dts/k3-j784s4-r5-evm.dts +F: arch/arm/dts/k3-j784s4-ddr.dtsi +F: arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi +F: doc/board/ti/j784s4_evm.rst + +AM69 BOARD +F: arch/arm/dts/k3-am69-sk.dts +F: arch/arm/dts/k3-am69-sk-u-boot.dtsi +F: arch/arm/dts/k3-am69-r5-sk.dts +F: configs/am69_sk_r5.config +F: configs/am69_sk_a72.config
Re: [PATCH v7 2/2] arm64: boot: Support Flat Image Tree
On Thu, Nov 30, 2023 at 5:26 PM Nicolas Schier wrote: > > Simon, > > thanks for the patch! Below are some nitpicks and bike-shedding > questions. > > On Wed 29 Nov 2023 10:21:53 GMT, Simon Glass wrote: > > Add a script which produces a Flat Image Tree (FIT), a single file > > containing the built kernel and associated devicetree files. > > Compression defaults to gzip which gives a good balance of size and > > performance. > > > > The files compress from about 86MB to 24MB using this approach. > > > > The FIT can be used by bootloaders which support it, such as U-Boot > > and Linuxboot. It permits automatic selection of the correct > > devicetree, matching the compatible string of the running board with > > the closest compatible string in the FIT. There is no need for > > filenames or other workarounds. > > Have you thought about updating the arch/mips ITB rules to also use the > new scripts/make_fit.py? Or is the FIT/ITB format for mips different > from the one for arm64? I recommend not touching MIPS at this moment because this tool simply picks up *.dtb files that exist under arch/*/boot/dts/, some of which may be stale files. Think of this scenario: [1] Enable CONFIG_ARCH_FOO and build foo.dtb will be created. [2] Next, disable CONFIG_ARCH_FOO and enable CONFIG_ARCH_BAR, and build. bar.dtb will be created. This script will pick up both foo.dtb and bar.dtb although foo.dtb is a left-over from the previous build. Without cleaning, stale *.dtb will accumulate and unwanted files will be included in image.fit. Currently, MIPS hard-codes its files. It always works in a deterministic way. I do not request Simon to implement everything perfectly because I know that would require much more effort. We could do something like modules.order to list out the dtb files from the current build, but I am not asking for it in this patchset. But, you are right. This tool is not arm64-specific at all (and that is the reason why I think the MAINTAINERS entry is a little odd) Perhaps it can be applicable to MIPS after everything works correctly. > > ARM ARCHITECTED TIMER DRIVER > > M: Mark Rutland > > M: Marc Zyngier > > diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile > > index 1bd4fae6e806..18e092de7cdb 100644 > > --- a/arch/arm64/Makefile > > +++ b/arch/arm64/Makefile > > @@ -36,6 +36,8 @@ ifeq ($(CONFIG_BROKEN_GAS_INST),y) > > $(warning Detected assembler with broken .inst; disassembly will be > > unreliable) > > endif > > > > +KBUILD_DTBS := dtbs > > Might you want to use tabs here as in the lines below? This should not exist in the first place. image.fit: dtbs is better. -- Best Regards Masahiro Yamada
Re: [PATCH v5 12/17] arm: dts: Introduce j784s4 u-boot dts files
On 11/30/23 5:55 AM, Apurva Nandan wrote:
Introduce the base dts files needed for u-boot or to augment the linux
dtbs for use in the u-boot-spl and u-boot binaries.
Signed-off-by: Hari Nagalla
[ add binman and ddr dtsi files ]
Signed-off-by: Neha Malcom Francis
Signed-off-by: Dasnavis Sabiya
Signed-off-by: Apurva Nandan
---
arch/arm/dts/Makefile|3 +-
arch/arm/dts/k3-j784s4-binman.dtsi | 346 +
arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi | 8757 +
arch/arm/dts/k3-j784s4-ddr.dtsi | 8858 ++
arch/arm/dts/k3-j784s4-evm-u-boot.dtsi | 25 +
arch/arm/dts/k3-j784s4-r5-evm.dts| 105 +
6 files changed, 18093 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/k3-j784s4-binman.dtsi
create mode 100644 arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
create mode 100644 arch/arm/dts/k3-j784s4-ddr.dtsi
create mode 100644 arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
create mode 100644 arch/arm/dts/k3-j784s4-r5-evm.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1a63ccba8e..b73f8a9230 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1409,7 +1409,8 @@ dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\
k3-j721s2-common-proc-board.dtb\
k3-j721s2-r5-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-sk.dtb\
- k3-j784s4-evm.dtb
+ k3-j784s4-evm.dtb\
+ k3-j784s4-r5-evm.dtb
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
k3-am642-r5-evm.dtb \
k3-am642-sk.dtb \
diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi
b/arch/arm/dts/k3-j784s4-binman.dtsi
new file mode 100644
index 00..7349c2ba38
--- /dev/null
+++ b/arch/arm/dts/k3-j784s4-binman.dtsi
@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-binman.dtsi"
+
+#ifdef CONFIG_TARGET_J784S4_R5_EVM
+
+_yaml_tifs {
+ config = "tifs-rm-cfg.yaml";
+};
+
+ {
+ tiboot3-j784s4-hs-evm.bin {
+ filename = "tiboot3-j784s4-hs-evm.bin";
+
+ ti-secure-rom {
+ content = <_boot_spl>, <_fs_enc>,
<_tifs_cfg>,
+ <_dm_cfg>, <_inner_cert>;
+ combined;
+ dm-data;
+ sysfw-inner-cert;
+ keyfile = "custMpk.pem";
+ sw-rev = <1>;
+ content-sbl = <_boot_spl>;
+ content-sysfw = <_fs_enc>;
+ content-sysfw-data = <_tifs_cfg>;
+ content-sysfw-inner-cert = <_inner_cert>;
+ content-dm-data = <_dm_cfg>;
+ load = <0x41c0>;
+ load-sysfw = <0x4>;
+ load-sysfw-data = <0x66800>;
+ load-dm-data = <0x41c8>;
+ };
+
+ u_boot_spl: u-boot-spl {
+ no-expanded;
+ };
+
+ ti_fs_enc: ti-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+
+ combined_tifs_cfg: combined-tifs-cfg.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+
+ sysfw_inner_cert: sysfw-inner-cert {
+ filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+
+ combined_dm_cfg: combined-dm-cfg.bin {
+ filename = "combined-dm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+};
+
+ {
+ tiboot3-j784s4-hs-fs-evm.bin {
+ filename = "tiboot3-j784s4-hs-fs-evm.bin";
+
+ ti-secure-rom {
+ content = <_boot_spl_fs>, <_fs_enc_fs>,
<_tifs_cfg_fs>,
+ <_dm_cfg_fs>, <_inner_cert_fs>;
+ combined;
+ dm-data;
+ sysfw-inner-cert;
+ keyfile = "custMpk.pem";
+ sw-rev = <1>;
+ content-sbl = <_boot_spl_fs>;
+ content-sysfw = <_fs_enc_fs>;
+ content-sysfw-data = <_tifs_cfg_fs>;
+ content-sysfw-inner-cert = <_inner_cert_fs>;
+ content-dm-data = <_dm_cfg_fs>;
+ load = <0x41c0>;
+ load-sysfw = <0x4>;
+
Re: [PATCH v5 10/17] board: ti: j748s4: Add board config yaml files
On 11/30/23 5:55 AM, Apurva Nandan wrote: Add board-cfg, rm-cfg, pm-cfg, sec-cfg, tifs-rm-cfg yaml for buidling u-boot sysfw data. Signed-off-by: Apurva Nandan --- board/ti/j784s4/board-cfg.yaml | 37 + board/ti/j784s4/pm-cfg.yaml | 13 + board/ti/j784s4/rm-cfg.yaml | 3058 ++ board/ti/j784s4/sec-cfg.yaml | 380 board/ti/j784s4/tifs-rm-cfg.yaml | 2656 ++ 5 files changed, 6144 insertions(+) create mode 100644 board/ti/j784s4/board-cfg.yaml create mode 100644 board/ti/j784s4/pm-cfg.yaml create mode 100644 board/ti/j784s4/rm-cfg.yaml create mode 100644 board/ti/j784s4/sec-cfg.yaml create mode 100644 board/ti/j784s4/tifs-rm-cfg.yaml diff --git a/board/ti/j784s4/board-cfg.yaml b/board/ti/j784s4/board-cfg.yaml new file mode 100644 index 00..049105062c --- /dev/null +++ b/board/ti/j784s4/board-cfg.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for J784S4 +# + +--- + +board-cfg: +rev: +boardcfg_abi_maj: 0x0 +boardcfg_abi_min: 0x1 +control: +subhdr: +magic: 0xC1D3 +size: 7 +main_isolation_enable: 0x5A +main_isolation_hostid: 0x2 +secproxy: +subhdr: +magic: 0x1207 +size: 7 +scaling_factor: 0x1 +scaling_profile: 0x1 +disable_main_nav_secure_proxy: 0 +msmc: +subhdr: +magic: 0xA5C3 +size: 5 +msmc_cache_size: 0x8 +debug_cfg: +subhdr: +magic: 0x020C +size: 8 +trace_dst_enables: 0x00 +trace_src_enables: 0x00 \ No newline at end of file Does checkpatch not complain about this no newline? Andrew
Re: [PATCH v5 09/17] board: ti: j784s4: Add board support for J784S4 EVM
On 11/30/23 5:55 AM, Apurva Nandan wrote:
Add board files for J784S4 EVM.
Signed-off-by: Hari Nagalla
[ add env and board specific yaml files for binman ]
Signed-off-by: Neha Malcom Francis
[ cleaned up the env files ]
Signed-off-by: Manorit Chawdhry
Signed-off-by: Dasnavis Sabiya
Signed-off-by: Apurva Nandan
---
arch/arm/mach-k3/Kconfig| 1 +
arch/arm/mach-k3/j784s4/Kconfig | 35 ++
board/ti/j784s4/Makefile| 7 ++
board/ti/j784s4/evm.c | 38 +
include/configs/j784s4_evm.h| 20 +
5 files changed, 101 insertions(+)
create mode 100644 arch/arm/mach-k3/j784s4/Kconfig
create mode 100644 board/ti/j784s4/Makefile
create mode 100644 board/ti/j784s4/evm.c
create mode 100644 include/configs/j784s4_evm.h
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 150d0bfa14..445b49e245 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -157,5 +157,6 @@ source "arch/arm/mach-k3/am62x/Kconfig"
source "arch/arm/mach-k3/am62ax/Kconfig"
source "arch/arm/mach-k3/j721e/Kconfig"
source "arch/arm/mach-k3/j721s2/Kconfig"
+source "arch/arm/mach-k3/j784s4/Kconfig"
endif
diff --git a/arch/arm/mach-k3/j784s4/Kconfig b/arch/arm/mach-k3/j784s4/Kconfig
new file mode 100644
index 00..03d3f91371
--- /dev/null
+++ b/arch/arm/mach-k3/j784s4/Kconfig
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Hari Nagalla
+
+if SOC_K3_J784S4
+
+choice
+ prompt "K3 J784S4 board"
+ optional
+
+config TARGET_J784S4_A72_EVM
+ bool "TI K3 based J784S4 EVM running on A72"
+ select ARM64
+ select BOARD_LATE_INIT
+ select SYS_DISABLE_DCACHE_OPS
+ select BINMAN
+
+config TARGET_J784S4_R5_EVM
+ bool "TI K3 based J784S4 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+
+endchoice
+
+source "board/ti/j784s4/Kconfig"
+
+endif
+
diff --git a/board/ti/j784s4/Makefile b/board/ti/j784s4/Makefile
new file mode 100644
index 00..3fc70eb8fb
--- /dev/null
+++ b/board/ti/j784s4/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Hari Nagalla
+#
+
+obj-y += evm.o
diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c
new file mode 100644
index 00..4857c9d2f6
--- /dev/null
+++ b/board/ti/j784s4/evm.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Board specific initialization for J784S4 EVM
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Hari Nagalla
+ *
+ */
+
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+void spl_board_init(void)
+{
+}
diff --git a/include/configs/j784s4_evm.h b/include/configs/j784s4_evm.h
new file mode 100644
index 00..1b780134ca
--- /dev/null
+++ b/include/configs/j784s4_evm.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Configuration header file for K3 J784S4 EVM
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Hari Nagalla
+ */
+
+#ifndef __CONFIG_J784S4_EVM_H
+#define __CONFIG_J784S4_EVM_H
+
+#include
Is this include needed?
+
+/* DDR Configuration */
+#define CFG_SYS_SDRAM_BASE10x88000
Do you need this? It should always be the same, no need to
make a per-SoC definition for it. I just sent out a patch
fixing the same for other K3[0].
Andrew
[0] https://lists.denx.de/pipermail/u-boot/2023-November/539024.html
+
+/* Now for the remaining common defines */
+#include
+
+#endif /* __CONFIG_J784S4_EVM_H */
[PATCH] board: ti: k3: Remove need for CFG_SYS_SDRAM_BASE
The base address of extended DDR does not change across the K3 family.
Setting this per SoC is not needed. Remove this definition to help
remove the last bits from K3 include/configs/*.h files.
Signed-off-by: Andrew Davis
---
board/ti/am65x/evm.c | 4 ++--
board/ti/j721e/evm.c | 4 ++--
board/ti/j721s2/evm.c| 4 ++--
include/configs/am62ax_evm.h | 4
include/configs/am65x_evm.h | 3 ---
include/configs/j721e_evm.h | 2 --
include/configs/j721s2_evm.h | 3 ---
7 files changed, 6 insertions(+), 18 deletions(-)
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index 975eb17946f..df209021c1b 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -73,13 +73,13 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = 0x8000;
gd->bd->bi_dram[0].size = 0x8000;
gd->ram_size = 0x8000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
- gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
+ gd->bd->bi_dram[1].start = 0x88000;
gd->bd->bi_dram[1].size = 0x8000;
gd->ram_size = 0x1;
#endif
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 0768385f40c..c541880107e 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -61,13 +61,13 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = 0x8000;
gd->bd->bi_dram[0].size = 0x8000;
gd->ram_size = 0x8000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
- gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
+ gd->bd->bi_dram[1].start = 0x88000;
gd->bd->bi_dram[1].size = 0x8000;
gd->ram_size = 0x1;
#endif
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index db717390771..1220cd84519 100644
--- a/board/ti/j721s2/evm.c
+++ b/board/ti/j721s2/evm.c
@@ -56,13 +56,13 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = 0x8000;
gd->bd->bi_dram[0].size = 0x7fff;
gd->ram_size = 0x8000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
- gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
+ gd->bd->bi_dram[1].start = 0x88000;
gd->bd->bi_dram[1].size = 0x37fff;
gd->ram_size = 0x4;
#endif
diff --git a/include/configs/am62ax_evm.h b/include/configs/am62ax_evm.h
index 57003f120f9..496d1c2348f 100644
--- a/include/configs/am62ax_evm.h
+++ b/include/configs/am62ax_evm.h
@@ -12,10 +12,6 @@
#include
#include
-/* DDR Configuration */
-#define CFG_SYS_SDRAM_BASE10x88000
-
-
/* Now for the remaining common defines */
#include
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
index 811dc0ff1a8..64458ebb4b8 100644
--- a/include/configs/am65x_evm.h
+++ b/include/configs/am65x_evm.h
@@ -14,9 +14,6 @@
#include
#include
-/* DDR Configuration */
-#define CFG_SYS_SDRAM_BASE10x88000
-
/* Now for the remaining common defines */
#include
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index ea39d1bf824..c26438c8684 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -11,8 +11,6 @@
#include
-/* DDR Configuration */
-#define CFG_SYS_SDRAM_BASE10x88000
/* FLASH Configuration */
#define CFG_SYS_FLASH_BASE 0x0
diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h
index 692c6bb5e42..846cfa7531c 100644
--- a/include/configs/j721s2_evm.h
+++ b/include/configs/j721s2_evm.h
@@ -12,9 +12,6 @@
#include
#include
-/* DDR Configuration */
-#define CFG_SYS_SDRAM_BASE10x88000
-
/* SPL Loader Configuration */
#if defined(CONFIG_TARGET_J721S2_A72_EVM)
#define CFG_SYS_UBOOT_BASE 0x5028
--
2.39.2
Re: TPM SPI issue
Hi Niek,
On 11/29/23 18:58, niek.nooij...@omron.com wrote:
Hi Fabio
I'm using the socfpga_cyclone5 with the designwire_spi driver.
I added the TPM to the devicetree as so:
{
status = "okay";
num-cs = <2>;
mram0@0 {
compatible = "spi-dev";
reg = <0>;
spi-max-frequency = <100>;
};
tpm@1 { // slm9670 - U144
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <1>;
spi-max-frequency = <100>;
};
};
The DW SPI device does not support holding the CS low between separate
reads/writes.
The easiest fix is to use a GPIO CS. However, you can also rewrite the SPI slave
driver to use mem_ops, which will ensure that the CS stays high for a
transaction.
However, this may not be possible for all slaves. For more info, have a look at
commit fec7bf0460d ("spi: dw: Add mem_ops").
--Sean
NIek
差出人: Fabio Estevam
送信日時: 2023年11月29日 22:17
宛先: Niek Nooijens / OC-IAB PBD-C DEVEL 1-1
CC: u-boot@lists.denx.de
件名: Re: TPM SPI issue
[feste...@gmail.com
からのメールを受け取る頻度は高くありません。これが問題である可能性の理由については、https://aka.ms/LearnAboutSenderIdentification
をご覧ください。]
Hi Niek,
On Wed, Nov 29, 2023 at 9:51 AM niek.nooij...@omron.com
wrote:
Hi there
I have the same issue as here:
https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fcommunity.infineon.com%2Ft5%2FOPTIGA-TPM%2FI-MX8-TPM-SLB9670-SPI-Com-Error%2Ftd-p%2F472533=05%7C01%7Cniek.nooijens%40omron.com%7C0ed9342c6f4e4d14dbbe08dbf0dd80b5%7C0ecff5a94bef4a7b96eca96579b4ac37%7C0%7C0%7C638368606354451409%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C=D3f09RUX4i0EcgQiUC4rv3y1VP3A5Ka3ozAR8dXden8%3D=0
apparently the CS is released in between responses. Can you help me solve this?
Which SoC are you using?
In case you are using drivers/spi/mxc_spi.c, there was a commit in the
kernel driver that
allowed to put the CS line in low when idle:
https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fstable%2Flinux.git%2Fcommit%2F%3Fh%3Dv6.6.3%26id%3D6a983ff5102ff0d859df05ca3f5cf2f6a17c0fad=05%7C01%7Cniek.nooijens%40omron.com%7C0ed9342c6f4e4d14dbbe08dbf0dd80b5%7C0ecff5a94bef4a7b96eca96579b4ac37%7C0%7C0%7C638368606354458890%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C=Q3feQjDcyArxhwoehGB3D%2Fwnq0phPPs3pb8jdmkdaSg%3D=0
[RESEND RFC PATCH v2 5/5] board: stm32f469-disco: add splash screen with stmicroelectronics logo
Display the STMicroelectronics logo with features VIDEO_LOGO and
SPLASH_SCREEN on stm32f469-disco board.
Signed-off-by: Dario Binacchi
---
Changes in v2:
- Add Patrice Chotard's Reviewed-by tag to patches 1, 2 and 3 of the series.
- Fix frame buffer allocation for stm32f469 discovery board.
configs/stm32f469-discovery_defconfig | 3 +++
include/configs/stm32f469-discovery.h | 2 ++
tools/logos/stm32f469-discovery.bmp | Bin 0 -> 18532 bytes
3 files changed, 5 insertions(+)
create mode 100644 tools/logos/stm32f469-discovery.bmp
diff --git a/configs/stm32f469-discovery_defconfig
b/configs/stm32f469-discovery_defconfig
index 85e795e83e7d..b7e35aeae200 100644
--- a/configs/stm32f469-discovery_defconfig
+++ b/configs/stm32f469-discovery_defconfig
@@ -42,12 +42,15 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_VIDEO=y
+CONFIG_VIDEO_LOGO=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
CONFIG_VIDEO_STM32=y
CONFIG_VIDEO_STM32_DSI=y
CONFIG_VIDEO_STM32_MAX_XRES=480
CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y
diff --git a/include/configs/stm32f469-discovery.h
b/include/configs/stm32f469-discovery.h
index 62a7e9af0c56..75bb9cd8d06f 100644
--- a/include/configs/stm32f469-discovery.h
+++ b/include/configs/stm32f469-discovery.h
@@ -31,6 +31,8 @@
"scriptaddr=0x00418000\0" \
"pxefile_addr_r=0x00428000\0" \
"ramdisk_addr_r=0x00438000\0" \
+ "splashimage=0x00448000\0" \
+ "splashpos=m,m\0" \
BOOTENV
#endif /* __CONFIG_H */
diff --git a/tools/logos/stm32f469-discovery.bmp
b/tools/logos/stm32f469-discovery.bmp
new file mode 100644
index
..ecc8d984218fb13fddf0ba9cf68f2cfad829e289
GIT binary patch
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[RESEND RFC PATCH v2 4/5] ARM: dts: stm32: support display on stm32f469-disco board
Add support to Orise Tech OTM8009A display on stm32f469-disco board.
It was necessary to retrieve the framebuffer address from the device tree
because the address returned by the video-uclass driver pointed to a memory
area that was not usable.
Furthermore, unlike Linux, the DSI driver requires the LTDC clock to be
properly probed. Hence, the changes made to the DSI node in
stm32f469-disco-u-boot.dtsi.
Signed-off-by: Dario Binacchi
---
Changes in v2:
- Add DRAM_SIZE macro.
- Fix frame buffer allocation function so that it is backward compatible
with boards other than the one it was introduced for (i. e. stm32f469-disco).
Tested on stm32f469-disco and stm32mp157f-dk2 boards.
arch/arm/dts/stm32f469-disco-u-boot.dtsi | 4 +++
configs/stm32f469-discovery_defconfig| 13 ++
drivers/video/stm32/stm32_ltdc.c | 31
3 files changed, 48 insertions(+)
diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi
b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
index 8e781c5a7b23..47ba9fa4a783 100644
--- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
@@ -92,7 +92,9 @@
{
clocks = < 0 STM32F4_APB2_CLOCK(DSI)>,
+< 0 STM32F4_APB2_CLOCK(LTDC)>,
<_hse>;
+ clock-names = "pclk", "px_clk", "ref";
};
{
@@ -140,6 +142,8 @@
};
{
+ bootph-all;
+
clocks = < 0 STM32F4_APB2_CLOCK(LTDC)>;
};
diff --git a/configs/stm32f469-discovery_defconfig
b/configs/stm32f469-discovery_defconfig
index 21c5498466cd..85e795e83e7d 100644
--- a/configs/stm32f469-discovery_defconfig
+++ b/configs/stm32f469-discovery_defconfig
@@ -21,6 +21,7 @@ CONFIG_CMD_GPT=y
# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIMER=y
# CONFIG_ISO_PARTITION is not set
@@ -40,3 +41,15 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
+CONFIG_VIDEO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
+CONFIG_VIDEO_STM32=y
+CONFIG_VIDEO_STM32_DSI=y
+CONFIG_VIDEO_STM32_MAX_XRES=480
+CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index 6fd90e33919d..9054db1d78b3 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -495,6 +495,33 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv
*priv, ulong fb_addr)
setbits_le32(priv->regs + LTDC_L1CR, LXCR_LEN);
}
+#if IS_ENABLED(CONFIG_TARGET_STM32F469_DISCOVERY)
+static int stm32_ltdc_alloc_fb(struct udevice *dev)
+{
+#define SDRAM_SIZE 0x100 /* 128Mbit = 16 Mbyte = 0x100 */
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+ phys_addr_t cpu;
+ dma_addr_t bus;
+ u64 dma_size;
+ int ret;
+
+ ret = dev_get_dma_range(dev, , , _size);
+ if (ret) {
+ dev_err(dev, "failed to get dma address\n");
+ return ret;
+ }
+
+ uc_plat->base = bus + SDRAM_SIZE - ALIGN(uc_plat->size, uc_plat->align);
+ return 0;
+}
+#else
+static inline int stm32_ltdc_alloc_fb(struct udevice *dev)
+{
+ /* Delegate framebuffer allocation to video-uclass */
+ return 0;
+}
+#endif
+
static int stm32_ltdc_probe(struct udevice *dev)
{
struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
@@ -605,6 +632,10 @@ static int stm32_ltdc_probe(struct udevice *dev)
priv->crop_h = timings.vactive.typ;
priv->alpha = 0xFF;
+ ret = stm32_ltdc_alloc_fb(dev);
+ if (ret)
+ return ret;
+
dev_dbg(dev, "%dx%d %dbpp frame buffer at 0x%lx\n",
timings.hactive.typ, timings.vactive.typ,
VNBITS(priv->l2bpp), uc_plat->base);
--
2.43.0
[RESEND RFC PATCH v2 3/5] ARM: dts: stm32: make the DSI clock usable by the clock driver
As described in [1], the "clocks" property contains "a phandle to the
clock device node, an index selecting between gated clocks (0) and other
clocks (1), and an index specifying the clock to use." The current version
of the clock driver, unlike the kernel, is currently able to properly
handle nodes with "clocks" properties with an index set to 0.
This patch is preparatory for future developments that require the use
of the DSI clock.
[1] Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
Signed-off-by: Dario Binacchi
Reviewed-by: Patrice Chotard
---
Changes in v2:
- Add Patrice Chotard's Reviewed-by tag.
arch/arm/dts/stm32f469-disco-u-boot.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi
b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
index dcc70369cd0d..8e781c5a7b23 100644
--- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
@@ -90,6 +90,11 @@
bootph-all;
};
+ {
+ clocks = < 0 STM32F4_APB2_CLOCK(DSI)>,
+<_hse>;
+};
+
{
bootph-all;
};
--
2.43.0
[RESEND RFC PATCH v2 2/5] ARM: dts: stm32: make the LTDC clock usable by the clock driver
As described in [1], the "clocks" property contains "a phandle to the
clock device node, an index selecting between gated clocks (0) and other
clocks (1), and an index specifying the clock to use." The current version
of the clock driver, unlike the kernel, is currently able to properly
handle nodes with "clocks" properties with an index set to 0.
This patch is preparatory for future developments that require the use
of the LTDC clock.
[1] Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
Signed-off-by: Dario Binacchi
Reviewed-by: Patrice Chotard
---
Changes in v2:
- Add Patrice Chotard's Reviewed-by tag.
arch/arm/dts/stm32f469-disco-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi
b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
index c07e2022e4a8..dcc70369cd0d 100644
--- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
@@ -134,6 +134,10 @@
bootph-all;
};
+ {
+ clocks = < 0 STM32F4_APB2_CLOCK(LTDC)>;
+};
+
{
bootph-all;
--
2.43.0
[RESEND RFC PATCH v2 1/5] ARM: dts: stm32f469-disco: sync with Linux 6.5
Sync the devicetree with linux 6.5 for stm32f746-disco board.
Signed-off-by: Dario Binacchi
Reviewed-by: Patrice Chotard
---
Changes in v2:
- Add Patrice Chotard's Reviewed-by tag.
arch/arm/dts/stm32f469-disco.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/stm32f469-disco.dts b/arch/arm/dts/stm32f469-disco.dts
index 6e0ffc1903be..c9acabf0f530 100644
--- a/arch/arm/dts/stm32f469-disco.dts
+++ b/arch/arm/dts/stm32f469-disco.dts
@@ -119,7 +119,7 @@
};
};
- panel-dsi@0 {
+ panel@0 {
compatible = "orisetech,otm8009a";
reg = <0>; /* dsi virtual channel (0..3) */
reset-gpios = < 7 GPIO_ACTIVE_LOW>;
@@ -138,7 +138,7 @@
status = "okay";
port {
- ltdc_out_dsi: endpoint@0 {
+ ltdc_out_dsi: endpoint {
remote-endpoint = <_in>;
};
};
--
2.43.0
[RESEND RFC PATCH v2 0/5] Support display on stm32f469-disco board
The series adds support for the Orise Tech OTM8009A display on the stm32f469-disco board. Substantial differences in the drivers for clock management, LTDC and DSI compared to Linux, made it necessary to modify the device tree. These changes were made in stm32f469-disco-uboot.dtsi to avoid altering the Linux device tree. It is therefore desirable, as soon as possible, to add these drivers the functionalities so that they do not require device tree properties that deviate from those present in the Linux version. Changes in v2: - Add Patrice Chotard's Reviewed-by tag to patches 1, 2 and 3 of the series. - Fix frame buffer allocation for stm32f469 discovery board. Dario Binacchi (5): ARM: dts: stm32f469-disco: sync with Linux 6.5 ARM: dts: stm32: make the LTDC clock usable by the clock driver ARM: dts: stm32: make the DSI clock usable by the clock driver ARM: dts: stm32: support display on stm32f469-disco board board: stm32f469-disco: add splash screen with stmicroelectronics logo arch/arm/dts/stm32f469-disco-u-boot.dtsi | 13 ++ arch/arm/dts/stm32f469-disco.dts | 4 +-- configs/stm32f469-discovery_defconfig| 16 drivers/video/stm32/stm32_ltdc.c | 31 +++ include/configs/stm32f469-discovery.h| 2 ++ tools/logos/stm32f469-discovery.bmp | Bin 0 -> 18532 bytes 6 files changed, 64 insertions(+), 2 deletions(-) create mode 100644 tools/logos/stm32f469-discovery.bmp -- 2.43.0
Re: [PATCH 00/21] Qualcomm generic board support
On Thu, Nov 30, 2023 at 01:02:25PM +0530, Sumit Garg wrote: > On Wed, 29 Nov 2023 at 22:06, Neil Armstrong > wrote: > > > > On 29/11/2023 16:34, Caleb Connolly wrote: > > > > > > > > > On 23/11/2023 07:04, Sumit Garg wrote: > > >> On Wed, 22 Nov 2023 at 21:34, Caleb Connolly > > >> wrote: > > >>> > > >>> > > >>> > > >>> On 22/11/2023 14:27, Tom Rini wrote: > > On Wed, Nov 22, 2023 at 07:44:09PM +0530, Sumit Garg wrote: > > > On Wed, 22 Nov 2023 at 19:31, Tom Rini wrote: > > >> > > >> On Wed, Nov 22, 2023 at 11:51:29AM +0530, Sumit Garg wrote: > > >>> Hi Caleb, > > >>> > > >>> On Tue, 21 Nov 2023 at 22:39, Caleb Connolly > > >>> wrote: > > >> [snip] > > == DT loading == > > > > Previously, boards used the FDT blob embedded into U-Boot (via > > OF_SEPARATE). However, most Qualcomm boards run U-Boot as a > > secondary > > bootloader, so we can instead rely on the first-stage bootloader to > > populate some useful FDT properties for us (notably the /memory > > node and > > KASLR seed) and fetch the DTB that it provides. Combined with the > > memory > > map changes above, this let's us entirely avoid configuring the > > memory > > map explicitly. > > >>> > > >>> Since with this change, we don't need to embed FDT blob in the > > >>> u-boot > > >>> binary, so I was thinking if we really need to import DTs from Linux > > >>> for different platforms and then play a catchup game? > > >>> > > >>> For now, yes. > > >> > > >> But why? Is there any value added by larger u-boot specific DT (most > > >> of the nodes being unused by u-boot) than what currently u-boot > > >> supports? The more important part is to get alignment with Linux DT > > >> bindings. If you need to have memory/reserved-memory nodes in u-boot > > >> DT for generalization purposes then you should import those particular > > >> nodes only. > > > > > > I've been thinking about and hacking on this for the last week or so, > > > sorry for the delayed reply here. > > > > > > The value is in preventing any of the existing bindings from regressing, > > That is actually best addressed in Linux by checking the DTS against > yaml DT bindings. We don't have that testing available in u-boot and > only depend on careful reviews. I would absolutely love for someone to make another attempt at updating our kbuild infrastucture so that we can run the validation targets. -- Tom signature.asc Description: PGP signature
Re: [PATCH 00/21] Qualcomm generic board support
> Since with this change, we don't need to embed FDT blob in the u-boot > binary, so I was thinking if we really need to import DTs from Linux > for different platforms and then play a catchup game? > > For now, yes. But why? Is there any value added by larger u-boot specific DT (most of the nodes being unused by u-boot) than what currently u-boot supports? The more important part is to get alignment with Linux DT bindings. If you need to have memory/reserved-memory nodes in u-boot DT for generalization purposes then you should import those particular nodes only. >>> >>> I've been thinking about and hacking on this for the last week or so, >>> sorry for the delayed reply here. >>> >>> The value is in preventing any of the existing bindings from regressing, > > That is actually best addressed in Linux by checking the DTS against > yaml DT bindings. We don't have that testing available in u-boot and > only depend on careful reviews. Sorry, I didn't explain myself very well here. By having .dtsi files be identical to Linux, we ensure that U-Boot drivers will remain compatible with them. Just as an argument not to use custom SoC dts in U-Boot (which is what we do currently). > >>> and simplifying the bringup process for new platforms (just copy >>> SoC/PMIC DTSI and write a minimal board DTS to enable the needed hardware). > There are quite a few features which aren't handled by > U-Boot that it shouldn't need to handle (rpm/h resources for example). > Also the fixed-regulator / regulator-gpio binding differences. IMO, we should fix them first and then use Linux DT as it is. >>> >>> The biggest blocker here is USB, on sdm845 and the 4 new platforms I >>> have working, I only support USB high speed, this requires removing the >>> superspeed phy and adding a DTS property. >>> >>> I tried using OF_BOARD_SETUP to make this changes during boot but this >>> approach really isn't scalable (and I couldn't find a way to make it >>> work anyway). > > Okay so let's try an alternative intermediate step then. We import the > Linux DT files *as it is* and then keep the u-boot specific custom > changes in -u-boot.dtsi file which is included by the board DTS > file. This has been the approach that other u-boot platforms follow > and allow us to easily sync them with Linux while reducing custom > u-boot specific bits. Eventually we should target at dropping u-boot > specific custom bits and then directly pick up DTB from Linux and boot > it. Ok, I think this is a reasonable approach. Will do that for the next revision > >>> > > I would definitely like to move towards supporting Linux DT directly, > but this approach gives us a nice middleground of minimising the U-Boot > specific DT parts. I don't see any real benefits here apart from the maintenance burden. If it had been an actual Linux DT then that can be passed to Linux as it is. However, the current modified import you are trying to do doesn't solve that purpose as well. >>> >>> Ensuring that we don't introduce non-standard bindings (by using Linux >>> DTSI) is one benefit, simplifying new platform bringup is another. >>> >>> The amount of work required to switch to upstream DT is too much to >>> block this series on. We can work on improving the situation there once >>> we have these Qualcomm improvements upstream and new boards added. I do >>> admit that this is quite an awkward middle-ground, and I would not like >>> it to last for too long. >> >> I'm a real supporter of targeting support of unmodified (or very slighly) >> Linux DT, having a reduced version of the Linux DT will be a pain at each >> sync, and you'll need to do this manually. > > We have to choose the middle-ground carefully here. It shouldn't give > the impression that it is an actual Linux DT that you can pass > directly to Linux via EFI. As otherwise users will hit problems due to > the partially modified DTs in u-boot. > >> >> Simply having to copy the Linux DT without any changes will make sure you >> are in sync with Linux's bindings, and will help making sure you'll boot >> unchanged Linux DTBs you get from previous loaders. > > Once we have the previous loaders (ABL or LK) providing u-boot fully > fledged DTB then we don't need to maintain Linux DT copy in u-boot > which is always a pain to keep in sync. Yes > >> >> And in bonus, you'll be able to chain it to the next loader like EFI. >> >> So I don't see why any work toward this goal is useless, and if an >> intermediate step is needed, let's do it. > > See the side effects of an intermediate step mentioned above. Having > -u-boot.dtsi clearly separates the changes we have to make for > u-boot. Sounds good. Thanks, > > -Sumit > >> >> Neil >> >>> -Sumit > > IMO, the build command would look like following if we import > pre-built FDT blob from Linux:
Re: [PATCH v7 2/2] arm64: boot: Support Flat Image Tree
Simon, thanks for the patch! Below are some nitpicks and bike-shedding questions. On Wed 29 Nov 2023 10:21:53 GMT, Simon Glass wrote: > Add a script which produces a Flat Image Tree (FIT), a single file > containing the built kernel and associated devicetree files. > Compression defaults to gzip which gives a good balance of size and > performance. > > The files compress from about 86MB to 24MB using this approach. > > The FIT can be used by bootloaders which support it, such as U-Boot > and Linuxboot. It permits automatic selection of the correct > devicetree, matching the compatible string of the running board with > the closest compatible string in the FIT. There is no need for > filenames or other workarounds. Have you thought about updating the arch/mips ITB rules to also use the new scripts/make_fit.py? Or is the FIT/ITB format for mips different from the one for arm64? > Add a 'make image.fit' build target for arm64, as well. > > The FIT can be examined using 'dumpimage -l'. > > This features requires pylibfdt (use 'pip install libfdt'). It also > requires compression utilities for the algorithm being used. Supported > compression options are the same as the Image.xxx files. For now there > is no way to change the compression other than by editing the rule for > $(obj)/image.fit > > While FIT supports a ramdisk / initrd, no attempt is made to support > this here, since it must be built separately from the Linux build. > > Signed-off-by: Simon Glass > --- > > Changes in v7: > - Add Image as a dependency of image.fit > - Drop kbuild tag > - Add dependency on dtbs > - Drop unnecessary path separator for dtbs > - Rebase to -next > > Changes in v5: > - Drop patch previously applied > - Correct compression rule which was broken in v4 > > Changes in v4: > - Use single quotes for UIMAGE_NAME > > Changes in v3: > - Drop temporary file image.itk > - Drop patch 'Use double quotes for image name' > - Drop double quotes in use of UIMAGE_NAME > - Drop unnecessary CONFIG_EFI_ZBOOT condition for help > - Avoid hard-coding "arm64" for the DT architecture > > Changes in v2: > - Drop patch previously applied > - Add .gitignore file > - Move fit rule to Makefile.lib using an intermediate file > - Drop dependency on CONFIG_EFI_ZBOOT > - Pick up .dtb files separately from the kernel > - Correct pylint too-many-args warning for write_kernel() > - Include the kernel image in the file count > - Add a pointer to the FIT spec and mention of its wide industry usage > - Mention the kernel version in the FIT description > > MAINTAINERS| 7 + > arch/arm64/Makefile| 9 +- > arch/arm64/boot/.gitignore | 1 + > arch/arm64/boot/Makefile | 6 +- > scripts/Makefile.lib | 13 ++ > scripts/make_fit.py| 289 + > 6 files changed, 322 insertions(+), 3 deletions(-) > create mode 100755 scripts/make_fit.py > > diff --git a/MAINTAINERS b/MAINTAINERS > index 14587be87a33..d609f0e8deb3 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1585,6 +1585,13 @@ F: Documentation/process/maintainer-soc*.rst > F: arch/arm/boot/dts/Makefile > F: arch/arm64/boot/dts/Makefile > > +ARM64 FIT SUPPORT > +M: Simon Glass > +L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) > +S: Maintained > +F: arch/arm64/boot/Makefile > +F: scripts/make_fit.py > + I'm afraid that the location does not match the requested sorting, it should be right before "ARM64 PORT". > ARM ARCHITECTED TIMER DRIVER > M: Mark Rutland > M: Marc Zyngier > diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile > index 1bd4fae6e806..18e092de7cdb 100644 > --- a/arch/arm64/Makefile > +++ b/arch/arm64/Makefile > @@ -36,6 +36,8 @@ ifeq ($(CONFIG_BROKEN_GAS_INST),y) > $(warning Detected assembler with broken .inst; disassembly will be > unreliable) > endif > > +KBUILD_DTBS := dtbs Might you want to use tabs here as in the lines below? > + > KBUILD_CFLAGS+= -mgeneral-regs-only \ > $(compat_vdso) $(cc_has_k_constraint) > KBUILD_CFLAGS+= $(call cc-disable-warning, psabi) > @@ -150,7 +152,7 @@ libs-$(CONFIG_EFI_STUB) += > $(objtree)/drivers/firmware/efi/libstub/lib.a > # Default target when executing plain make > boot := arch/arm64/boot > > -BOOT_TARGETS := Image vmlinuz.efi > +BOOT_TARGETS := Image vmlinuz.efi image.fit > > PHONY += $(BOOT_TARGETS) > > @@ -162,7 +164,9 @@ endif > > all: $(notdir $(KBUILD_IMAGE)) > > -vmlinuz.efi: Image > +image.fit: $(KBUILD_DTBS) > + > +vmlinuz.efi image.fit: Image > $(BOOT_TARGETS): vmlinux > $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ > > @@ -215,6 +219,7 @@ virtconfig: > define archhelp >echo '* Image.gz - Compressed kernel image > (arch/$(ARCH)/boot/Image.gz)' >echo ' Image - Uncompressed kernel image > (arch/$(ARCH)/boot/Image)' > + echo ' image.fit - Flat Image Tree
Re: TPM SPI issue
Hi Fabio
I'm using the socfpga_cyclone5 with the designwire_spi driver.
I added the TPM to the devicetree as so:
{
status = "okay";
num-cs = <2>;
mram0@0 {
compatible = "spi-dev";
reg = <0>;
spi-max-frequency = <100>;
};
tpm@1 { // slm9670 - U144
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <1>;
spi-max-frequency = <100>;
};
};
NIek
差出人: Fabio Estevam
送信日時: 2023年11月29日 22:17
宛先: Niek Nooijens / OC-IAB PBD-C DEVEL 1-1
CC: u-boot@lists.denx.de
件名: Re: TPM SPI issue
[feste...@gmail.com
からのメールを受け取る頻度は高くありません。これが問題である可能性の理由については、https://aka.ms/LearnAboutSenderIdentification
をご覧ください。]
Hi Niek,
On Wed, Nov 29, 2023 at 9:51 AM niek.nooij...@omron.com
wrote:
>
> Hi there
>
> I have the same issue as here:
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fcommunity.infineon.com%2Ft5%2FOPTIGA-TPM%2FI-MX8-TPM-SLB9670-SPI-Com-Error%2Ftd-p%2F472533=05%7C01%7Cniek.nooijens%40omron.com%7C0ed9342c6f4e4d14dbbe08dbf0dd80b5%7C0ecff5a94bef4a7b96eca96579b4ac37%7C0%7C0%7C638368606354451409%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C=D3f09RUX4i0EcgQiUC4rv3y1VP3A5Ka3ozAR8dXden8%3D=0
>
> apparently the CS is released in between responses. Can you help me solve
> this?
Which SoC are you using?
In case you are using drivers/spi/mxc_spi.c, there was a commit in the
kernel driver that
allowed to put the CS line in low when idle:
https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fstable%2Flinux.git%2Fcommit%2F%3Fh%3Dv6.6.3%26id%3D6a983ff5102ff0d859df05ca3f5cf2f6a17c0fad=05%7C01%7Cniek.nooijens%40omron.com%7C0ed9342c6f4e4d14dbbe08dbf0dd80b5%7C0ecff5a94bef4a7b96eca96579b4ac37%7C0%7C0%7C638368606354458890%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C=Q3feQjDcyArxhwoehGB3D%2Fwnq0phPPs3pb8jdmkdaSg%3D=0
[PATCH v1] arm: dts: meson: add NAND controller node for AXG
Signed-off-by: Arseniy Krasnov
---
arch/arm/dts/meson-axg.dtsi | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/dts/meson-axg.dtsi b/arch/arm/dts/meson-axg.dtsi
index 3f5254eeb4..c01ace3ff1 100644
--- a/arch/arm/dts/meson-axg.dtsi
+++ b/arch/arm/dts/meson-axg.dtsi
@@ -430,6 +430,27 @@
};
};
+ nand_all_pins: nand_all_pins {
+ mux {
+ groups = "emmc_nand_d0",
+"emmc_nand_d1",
+"emmc_nand_d2",
+"emmc_nand_d3",
+"emmc_nand_d4",
+"emmc_nand_d5",
+"emmc_nand_d6",
+"emmc_nand_d7",
+"nand_ce0",
+"nand_ale",
+"nand_cle",
+"nand_wen_clk",
+"nand_ren_wr";
+ function = "nand";
+ input-enable;
+ bias-pull-up;
+ };
+ };
+
emmc_ds_pins: emmc_ds {
mux {
groups = "emmc_ds";
@@ -1906,6 +1927,20 @@
resets = < RESET_SD_EMMC_C>;
};
+ nfc: nand-controller@7800 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ pinctrl-0 = <_all_pins>;
+ pinctrl-names = "default";
+ compatible = "amlogic,meson-axg-nfc";
+ status = "okay";
+ reg = <0x0 0x7800 0x0 0x100>,
+ <0x0 0x7000 0x0 0x800>;
+ clocks = < CLKID_SD_EMMC_C>,
+< CLKID_FCLK_DIV2>;
+ clock-names = "core", "device";
+ };
+
usb2_phy1: phy@9020 {
compatible = "amlogic,meson-gxl-usb2-phy";
#phy-cells = <0>;
--
2.35.0
[PATCH v5 01/17] arm: dts: Introduce j784s4 dts from linux kernel
Introduce the basic j784s4 SoC dts from the v6.7-rc1 tag of the
linux kernel.
Signed-off-by: Hari Nagalla
Signed-off-by: Apurva Nandan
---
arch/arm/dts/Makefile |1 +
arch/arm/dts/k3-j784s4-evm.dts | 981 +++
arch/arm/dts/k3-j784s4-main.dtsi | 2068
arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi | 743 +
arch/arm/dts/k3-j784s4-thermal.dtsi| 101 ++
arch/arm/dts/k3-j784s4.dtsi| 294
6 files changed, 4188 insertions(+)
create mode 100644 arch/arm/dts/k3-j784s4-evm.dts
create mode 100644 arch/arm/dts/k3-j784s4-main.dtsi
create mode 100644 arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
create mode 100644 arch/arm/dts/k3-j784s4-thermal.dtsi
create mode 100644 arch/arm/dts/k3-j784s4.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ea420db1b8..23ee65114b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1408,6 +1408,7 @@ dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\
k3-am68-sk-r5-base-board.dtb\
k3-j721s2-common-proc-board.dtb\
k3-j721s2-r5-common-proc-board.dtb
+dtb-$(CONFIG_SOC_K3_J784S4) += k3-j784s4-evm.dtb
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
k3-am642-r5-evm.dtb \
k3-am642-sk.dtb \
diff --git a/arch/arm/dts/k3-j784s4-evm.dts b/arch/arm/dts/k3-j784s4-evm.dts
new file mode 100644
index 00..f1f4c8634a
--- /dev/null
+++ b/arch/arm/dts/k3-j784s4-evm.dts
@@ -0,0 +1,981 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458
+ */
+
+/dts-v1/;
+
+#include
+#include
+#include "k3-j784s4.dtsi"
+
+/ {
+ compatible = "ti,j784s4-evm", "ti,j784s4";
+ model = "Texas Instruments J784S4 EVM";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ aliases {
+ serial0 = _uart0;
+ serial1 = _uart0;
+ serial2 = _uart8;
+ mmc0 = _sdhci0;
+ mmc1 = _sdhci1;
+ i2c0 = _i2c0;
+ i2c3 = _i2c0;
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ /* 32G RAM */
+ reg = <0x00 0x8000 0x00 0x8000>,
+ <0x08 0x8000 0x07 0x8000>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e80 {
+ reg = <0x00 0x9e80 0x00 0x0180>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa000 0x00 0x10>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: r5f-memory@a010 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa010 0x00 0xf0>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a100 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa100 0x00 0x10>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_memory_region: r5f-memory@a110 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa110 0x00 0xf0>;
+ no-map;
+ };
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a200 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa200 0x00 0x10>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a210 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa210 0x00 0xf0>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a300 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa300 0x00 0x10>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a310 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa310 0x00 0xf0>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a400 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa400 0x00 0x10>;
[PATCH v1] cmd: mtd: OTP access support
Add access to OTP region. It supports info, dump, write and lock
operations.
Signed-off-by: Arseniy Krasnov
---
cmd/Kconfig | 1 +
cmd/mtd.c | 224
2 files changed, 225 insertions(+)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 90e4ef93e0..c47523a03b 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1354,6 +1354,7 @@ config CMD_MTD
bool "mtd"
depends on MTD
select MTD_PARTITIONS
+ select HEXDUMP
help
MTD commands support.
diff --git a/cmd/mtd.c b/cmd/mtd.c
index eb6e2d6892..3ad15b0f8f 100644
--- a/cmd/mtd.c
+++ b/cmd/mtd.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -202,6 +203,219 @@ static bool mtd_oob_write_is_empty(struct mtd_oob_ops *op)
return true;
}
+static int do_mtd_otp_read(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct mtd_info *mtd;
+ size_t retlen;
+ off_t from;
+ size_t len;
+ bool user;
+ int ret;
+ u8 *buf;
+
+ if (argc != 5)
+ return CMD_RET_USAGE;
+
+ if (!strcmp(argv[2], "u"))
+ user = true;
+ else if (!strcmp(argv[2], "f"))
+ user = false;
+ else
+ return CMD_RET_USAGE;
+
+ mtd = get_mtd_by_name(argv[1]);
+ if (IS_ERR_OR_NULL(mtd))
+ return CMD_RET_FAILURE;
+
+ from = simple_strtoul(argv[3], NULL, 0);
+ len = simple_strtoul(argv[4], NULL, 0);
+
+ ret = CMD_RET_FAILURE;
+
+ buf = malloc(len);
+ if (!buf)
+ goto put_mtd;
+
+ printf("Reading %s OTP from 0x%lx, %lu bytes\n",
+ user ? "user" : "factory", from, len);
+
+ if (user)
+ ret = mtd_read_user_prot_reg(mtd, from, len, , buf);
+ else
+ ret = mtd_read_fact_prot_reg(mtd, from, len, , buf);
+ if (ret) {
+ free(buf);
+ pr_err("OTP read failed: %d\n", ret);
+ ret = CMD_RET_FAILURE;
+ goto put_mtd;
+ }
+
+ if (retlen != len)
+ pr_err("OTP read returns %zu, but %zu expected\n",
+ retlen, len);
+
+ print_hex_dump("", 0, 16, 1, buf, retlen, true);
+
+ free(buf);
+
+ ret = CMD_RET_SUCCESS;
+
+put_mtd:
+ put_mtd_device(mtd);
+
+ return ret;
+}
+
+static int do_mtd_otp_lock(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct mtd_info *mtd;
+ off_t from;
+ size_t len;
+ int ret;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
+ mtd = get_mtd_by_name(argv[1]);
+ if (IS_ERR_OR_NULL(mtd))
+ return CMD_RET_FAILURE;
+
+ from = simple_strtoul(argv[2], NULL, 0);
+ len = simple_strtoul(argv[3], NULL, 0);
+
+ ret = mtd_lock_user_prot_reg(mtd, from, len);
+ if (ret) {
+ pr_err("OTP lock failed: %d\n", ret);
+ ret = CMD_RET_FAILURE;
+ goto put_mtd;
+ }
+
+ ret = CMD_RET_SUCCESS;
+
+put_mtd:
+ put_mtd_device(mtd);
+
+ return ret;
+}
+
+static int do_mtd_otp_write(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct mtd_info *mtd;
+ size_t retlen;
+ size_t binlen;
+ u8 *binbuf;
+ off_t from;
+ int ret;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
+ mtd = get_mtd_by_name(argv[1]);
+ if (IS_ERR_OR_NULL(mtd))
+ return CMD_RET_FAILURE;
+
+ from = simple_strtoul(argv[2], NULL, 0);
+ binlen = strlen(argv[3]) / 2;
+
+ ret = CMD_RET_FAILURE;
+ binbuf = malloc(binlen);
+ if (!binbuf)
+ goto put_mtd;
+
+ hex2bin(binbuf, argv[3], binlen);
+
+ printf("Will write:\n");
+
+ print_hex_dump("", 0, 16, 1, binbuf, binlen, true);
+
+ printf("to 0x%zx\n", from);
+
+ printf("Caution! OTP data bits can't be erased! Continue (y/n)?\n");
+
+ if (confirm_yesno() != 1) {
+ pr_err("OTP write canceled\n");
+ ret = CMD_RET_SUCCESS;
+ goto put_mtd;
+ }
+
+ ret = mtd_write_user_prot_reg(mtd, from, binlen, , binbuf);
+ if (ret) {
+ pr_err("OTP write failed: %d\n", ret);
+ ret = CMD_RET_FAILURE;
+ goto put_mtd;
+ }
+
+ if (retlen != binlen)
+ pr_err("OTP write returns %zu, but %zu expected\n",
+ retlen, binlen);
+
+ ret = CMD_RET_SUCCESS;
+
+put_mtd:
+ free(binbuf);
+ put_mtd_device(mtd);
+
+ return ret;
+}
+
+static int do_mtd_otp_info(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct otp_info otp_info;
+ struct mtd_info *mtd;
+
[PATCH v1] mtd: rawnand: macronix: OTP access for MX30LFxG18AC
Support for OTP area access on MX30LFxG18AC chip series.
Signed-off-by: Arseniy Krasnov
---
drivers/mtd/nand/raw/nand_macronix.c | 170 +++
1 file changed, 170 insertions(+)
diff --git a/drivers/mtd/nand/raw/nand_macronix.c
b/drivers/mtd/nand/raw/nand_macronix.c
index dc972e5909..4c6ddd9233 100644
--- a/drivers/mtd/nand/raw/nand_macronix.c
+++ b/drivers/mtd/nand/raw/nand_macronix.c
@@ -16,13 +16,183 @@
* GNU General Public License for more details.
*/
+#include
#include
+#define ONFI_FEATURE_ADDR_30LFXG18AC_OTP 0x90
+#define MACRONIX_30LFXG18AC_OTP_START_PAGE 2
+#define MACRONIX_30LFXG18AC_OTP_PAGES 30
+#define MACRONIX_30LFXG18AC_OTP_PAGE_SIZE 2112
+#define MACRONIX_30LFXG18AC_OTP_SIZE_BYTES \
+ (MACRONIX_30LFXG18AC_OTP_PAGES *\
+MACRONIX_30LFXG18AC_OTP_PAGE_SIZE)
+
+#define MACRONIX_30LFXG18AC_OTP_EN BIT(0)
+
+static int macronix_30lfxg18ac_get_otp_info(struct mtd_info *mtd, size_t len,
+ size_t *retlen,
+ struct otp_info *buf)
+{
+ if (len < sizeof(*buf))
+ return -EINVAL;
+
+ /* Always report that OTP is unlocked. Reason is that this
+* type of flash chip doesn't provide way to check that OTP
+* is locked or not: subfeature parameter is implemented as
+* volatile register. Technically OTP region could be locked
+* and become readonly, but as there is no way to check it,
+* don't allow to lock it ('_lock_user_prot_reg' callback
+* always returns -EOPNOTSUPP) and thus we report that OTP
+* is unlocked.
+*/
+ buf->locked = 0;
+ buf->start = 0;
+ buf->length = MACRONIX_30LFXG18AC_OTP_SIZE_BYTES;
+
+ *retlen = sizeof(*buf);
+
+ return 0;
+}
+
+static int macronix_30lfxg18ac_otp_enable(struct nand_chip *nand)
+{
+ u8 feature_buf[ONFI_SUBFEATURE_PARAM_LEN] = { 0 };
+ struct mtd_info *mtd;
+
+ mtd = nand_to_mtd(nand);
+ feature_buf[0] = MACRONIX_30LFXG18AC_OTP_EN;
+
+ return nand->onfi_set_features(mtd, nand,
ONFI_FEATURE_ADDR_30LFXG18AC_OTP, feature_buf);
+}
+
+static int macronix_30lfxg18ac_otp_disable(struct nand_chip *nand)
+{
+ u8 feature_buf[ONFI_SUBFEATURE_PARAM_LEN] = { 0 };
+ struct mtd_info *mtd;
+
+ mtd = nand_to_mtd(nand);
+ return nand->onfi_set_features(mtd, nand,
ONFI_FEATURE_ADDR_30LFXG18AC_OTP, feature_buf);
+}
+
+static int __macronix_30lfxg18ac_rw_otp(struct mtd_info *mtd,
+ loff_t offs_in_flash,
+ size_t len, size_t *retlen,
+ u_char *buf, bool write)
+{
+ struct nand_chip *nand;
+ size_t bytes_handled;
+ off_t offs_in_page;
+ u64 page;
+ int ret;
+
+ nand = mtd_to_nand(mtd);
+ nand->select_chip(mtd, 0);
+
+ ret = macronix_30lfxg18ac_otp_enable(nand);
+ if (ret)
+ goto out_otp;
+
+ page = offs_in_flash;
+ /* 'page' will be result of division. */
+ offs_in_page = do_div(page, MACRONIX_30LFXG18AC_OTP_PAGE_SIZE);
+ bytes_handled = 0;
+
+ while (bytes_handled < len &&
+ page < MACRONIX_30LFXG18AC_OTP_PAGES) {
+ size_t bytes_to_handle;
+ u64 phys_page = page + MACRONIX_30LFXG18AC_OTP_START_PAGE;
+
+ bytes_to_handle = min_t(size_t, len - bytes_handled,
+ MACRONIX_30LFXG18AC_OTP_PAGE_SIZE -
+ offs_in_page);
+
+ if (write)
+ ret = nand_prog_page_op(nand, phys_page, offs_in_page,
+ [bytes_handled],
bytes_to_handle);
+ else
+ ret = nand_read_page_op(nand, phys_page, offs_in_page,
+ [bytes_handled],
bytes_to_handle);
+ if (ret)
+ goto out_otp;
+
+ bytes_handled += bytes_to_handle;
+ offs_in_page = 0;
+ page++;
+ }
+
+ *retlen = bytes_handled;
+
+out_otp:
+ if (ret)
+ dev_err(mtd->dev, "failed to perform OTP IO: %i\n", ret);
+
+ ret = macronix_30lfxg18ac_otp_disable(nand);
+ if (ret)
+ dev_err(mtd->dev, "failed to leave OTP mode after %s\n",
+ write ? "write" : "read");
+
+ nand->select_chip(mtd, -1);
+
+ return ret;
+}
+
+static int macronix_30lfxg18ac_write_otp(struct mtd_info *mtd, loff_t to,
+size_t len, size_t *rlen,
+u_char *buf)
+{
+ return __macronix_30lfxg18ac_rw_otp(mtd, to, len, rlen, (u_char *)buf,
+ true);
+}
+
+static int
[PATCH v1] mtd: rawnand: Meson NAND controller support
Basic support for Amlogic Meson NAND controller on AXG. Signed-off-by: Arseniy Krasnov --- drivers/mtd/nand/raw/Kconfig |9 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/meson_nand.c | 1231 + 3 files changed, 1241 insertions(+) create mode 100644 drivers/mtd/nand/raw/meson_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index d624589a89..7b7b0226ab 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -488,6 +488,15 @@ config NAND_ARASAN controller. This uses the hardware ECC for read and write operations. +config NAND_MESON + bool "Meson NAND support" + select SYS_NAND_SELF_INIT + depends on DM_MTD && ARCH_MESON + imply CMD_NAND + help + This enables Nand driver support for Meson raw NAND flash + controller. + config NAND_MXC bool "MXC NAND support" depends on CPU_ARM926EJS || CPU_ARM1136 || MX5 diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index add2b4cf65..5b4efd52c9 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o +obj-$(CONFIG_NAND_MESON) += meson_nand.o obj-$(CONFIG_NAND_MXC) += mxc_nand.o obj-$(CONFIG_NAND_MXS) += mxs_nand.o obj-$(CONFIG_NAND_MXS_DT) += mxs_nand_dt.o diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c new file mode 100644 index 00..f1d49887ee --- /dev/null +++ b/drivers/mtd/nand/raw/meson_nand.c @@ -0,0 +1,1231 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Amlogic Meson Nand Flash Controller Driver + * + * Copyright (c) 2023 SaluteDevices, Inc. + * Author: Arseniy Krasnov + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NFC_CMD_IDLE (0xc << 14) +#define NFC_CMD_CLE(0x5 << 14) +#define NFC_CMD_ALE(0x6 << 14) +#define NFC_CMD_DWR(0x4 << 14) +#define NFC_CMD_DRD(0x8 << 14) +#define NFC_CMD_ADL((0 << 16) | (3 << 20)) +#define NFC_CMD_ADH((1 << 16) | (3 << 20)) +#define NFC_CMD_AIL((2 << 16) | (3 << 20)) +#define NFC_CMD_AIH((3 << 16) | (3 << 20)) +#define NFC_CMD_SEED ((8 << 16) | (3 << 20)) +#define NFC_CMD_M2N((0 << 17) | (2 << 20)) +#define NFC_CMD_N2M((1 << 17) | (2 << 20)) +#define NFC_CMD_RB BIT(20) +#define NFC_CMD_SCRAMBLER_ENABLE BIT(19) +#define NFC_CMD_SCRAMBLER_DISABLE 0 +#define NFC_CMD_SHORTMODE_DISABLE 0 +#define NFC_CMD_RB_INT BIT(14) +#define NFC_CMD_RB_INT_NO_PIN ((0xb << 10) | BIT(18) | BIT(16)) + +#define NFC_CMD_GET_SIZE(x)(((x) >> 22) & GENMASK(4, 0)) + +#define NFC_REG_CMD0x00 +#define NFC_REG_CFG0x04 +#define NFC_REG_DADR 0x08 +#define NFC_REG_IADR 0x0c +#define NFC_REG_BUF0x10 +#define NFC_REG_INFO 0x14 +#define NFC_REG_DC 0x18 +#define NFC_REG_ADR0x1c +#define NFC_REG_DL 0x20 +#define NFC_REG_DH 0x24 +#define NFC_REG_CADR 0x28 +#define NFC_REG_SADR 0x2c +#define NFC_REG_PINS 0x30 +#define NFC_REG_VER0x38 + +#define CMDRWGEN(cmd_dir, ran, bch, short_mode, page_size, pages) \ + ( \ + (cmd_dir) | \ + ((ran) << 19) | \ + ((bch) << 14) | \ + ((short_mode) << 13)| \ + (((page_size) & 0x7f) << 6) | \ + ((pages) & 0x3f)\ + ) + +#define GENCMDDADDRL(adl, addr)((adl) | ((addr) & 0x)) +#define GENCMDDADDRH(adh, addr)((adh) | (((addr) >> 16) & 0x)) +#define GENCMDIADDRL(ail, addr)((ail) | ((addr) & 0x)) +#define GENCMDIADDRH(aih, addr)((aih) | (((addr) >> 16) & 0x)) + +#define DMA_DIR(dir) ((dir) ? NFC_CMD_N2M : NFC_CMD_M2N) + +#define ECC_CHECK_RETURN_FF-1 + +#define NAND_CE0 (0xe << 10) +#define NAND_CE1 (0xd << 10) + +#define DMA_BUSY_TIMEOUT_US100 +#define CMD_DRAIN_TIMEOUT_US 1000 +#define ECC_POLL_TIMEOUT_US15 + +#define MAX_CE_NUM
Upgrade u-boot to use a redundant environment
Hi, We are using u-boot and until now we are using a single env storage on the eMMC. We want to change to using a redundant environment, and the way to do that is well documented (thanks for that). The problem we are facing is transitioning from one single to redundant, as the format of the env storage is different (redund has one byte flags right ater the 4 bytes CRC, at offset 4). After the updating the u-boot binary and restarting the machine, u-boot CRC check will fail and all environment will be lost, due to the format change. What is the ussual way to deal with this? Is there a tool to upgrade the environment blob format? Best regards, Adrien
RE: [PATCH 0/4] board: ti: Update to latest board configuration
> On 13:40-20231128, Vishal Mahaveer wrote: > > This patch series brings in the latest board configurations for > > am62 and am62a device. > > > > Patch "board: ti: am62x/am62ax: Update virtual interrupt allocations > > in board config" is needed for booting with the latest TIFS and DM > > firmware [1]. > > > > [1] > > https://git.ti.com/cgit/processor-firmware/ti-linux-firmware/log/?h=ti > > -linux-firmware > > SHA: e891ddc65c55bfa7111e4f45834b7c26444dff72 > > > > > > U-boot boot log - > > https://gist.github.com/vishalmti/6b38fb80d557478131d5aaed5aeb3596 > > > > > > Vishal Mahaveer (4): > > board: ti: am62x/am62ax: Formatting updates to board config files > > board: ti: am62ax: Add C7x resource allocation entries to board config > > board: ti: am62x/am62ax: Update MCU GPIO interrupt allocation in board > > config > > board: ti: am62x/am62ax: Update virtual interrupt allocations in board > > config > > > > board/ti/am62ax/rm-cfg.yaml | 522 > > +++- > > board/ti/am62x/rm-cfg.yaml | 481 + > > 2 files changed, 396 insertions(+), 607 deletions(-) > > > Sorry, but this is completely confusing. There is no documentation to > indicate there is backward compatibility break in firmware. do all users > need to upgrade firmware along with board config updates?? what is the > minimum firmware version that is supported? is there an ABI version check > that should be enforced? > > Is there absolutely no way for people to use the new firmware and keep > their old u-boot? Rather disappointing to see backward compatible breakage > occurring this stage of the device. This is not appreciated. > > Please see if you can fix your firmware to maintain compatibility (as has > been the case for year+ now) Understood the concern. Sorry about that. Will send a V2 with the virtual interrupt patch dropped. The firmware will be updated to have the change reverted that causes backward compatibility issue. > > -- > Regards, > Nishanth Menon > Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 > DDB5 849D 1736 249D
Re: [PATCH v1] cmd: mtd: OTP access support
+static int do_mtd_otp_write(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
..
+ printf("Caution! OTP data bits can't be erased! Continue (y/n)?\n");
Please note, that with current SPI-NOR flashes this is not true and
there is usually some kind of erase command for the OTP bits. Only
the region lock is permanent and with that set, no more write or erase
is possible.
-michael
Re: [PATHv11 00/43] net/lwip: add lwip library for the network stack
On Thu, Nov 30, 2023 at 10:14 AM Maxim Uvarov wrote: > I will test that. smsc95xx_eth included in some CI tests and it worked. So > some differences on real hardware... > Log says that a ping packet was sent, but no packet on rx. > Might be the start function of smsc95xx_eth called wrongly Please note that on the board I tested there is no smsc95xx involved. It is an i.MX8MN board with the FEC Ethernet controller and an 88E6320 switch.
Re: [PATHv11 00/43] net/lwip: add lwip library for the network stack
On Thu, 30 Nov 2023 at 19:00, Fabio Estevam wrote: > Hi Maxim, > > On Thu, Nov 30, 2023 at 5:39 AM Maxim Uvarov > wrote: > > > If networking for some reason doesn't work on that board (I tested only > virtual board). Please try to compile with: > > Could you also try on a real board? > > Tom tested on a Raspberry Pi3 and it failed too: > > https://lore.kernel.org/u-boot/20231127185953.GW2513409@bill-the-cat/ > > > CONFIG_LWIP_LIB_DEBUG=y > > #CONFIG_LWIP_LIB_NOASSERT is not set > > > > It should make network activity more verbose. In many cases I saw issues > that physically MAC address do not match to lwip initialized value, > > and lwip drops such packets. > > The ping response with: > > CONFIG_LWIP_LIB_DEBUG=y > #CONFIG_LWIP_LIB_NOASSERT is not set > > u-boot=> ping 192.168.0.16 > init already done for eth1 > Using eth1 device > pinging addr: 192.168.0.16 > ping: send 192.168.0.16 > ip4_output_if: 0IP header: > +---+ > | 4 | 5 | 0x00 |60 | (v, hl, tos, len) > +---+ > | 40 |000| 0 | (id, flags, offset) > +---+ > | 255 |1 |0x3994 | (ttl, proto, chksum) > +---+ > | 192 | 168 |0 | 164 | (src) > +---+ > | 192 | 168 |0 | 16 | (dest) > +---+ > ip4_output_if: call netif->output() > etharp_find_entry: found matching entry 0 > etharp_query: queued packet bdf03e70 on ARP entry 0 > ping_tmo: ping failed; host 192.168.0.16 is not alive > u-boot=> > I will test that. smsc95xx_eth included in some CI tests and it worked. So some differences on real hardware... Log says that a ping packet was sent, but no packet on rx. Might be the start function of smsc95xx_eth called wrongly BR, Maxim.
Re: [PATHv11 00/43] net/lwip: add lwip library for the network stack
On Thu, 30 Nov 2023 at 17:09, Peter Robinson wrote: > Hi Maxim, > > > Please find updated version of lwip patches. Changes are in the > > changelog bellow. > > > > Thank you, > > Maxim. > > > > changelog: > > v11: - v11 is mosly respin of v10 patches with CI error fixes. > > Gitlab CI: > > > https://source.denx.de/u-boot/custodians/u-boot-tpm/-/pipelines/18368 > > Azure CI: > > > https://dev.azure.com/u-boot/u-boot/_build/results?buildId=7366=results > > (Azure CI, which is connected to github. Sometime I can > see > > tftp timeout after some part of download there, but > that can not be > > reproduced locally. While Gitblab CI is stable. Because > of num tries in > > CI I suspect this CI was not always reliable.) > > Azure and Gitlab also have different toolchains and I > > would say Gitlab generates bigger code then Azure CI. > > > > Also many boards have a binary limit size of 800k (even > > qemu has limits). And increased limits to fit all the > code. Specially did it > > patch by board config to show which boards are failing > to build. There I have > > a question if we really want to support new > functionality for old boards (mips, > > arm32 and etc...). I hope board owners can help me if > > it's valid to increase these limits. > > > > In this version I used git submodules and friend CI with > > submodules. But I don't mind if you decide to maintain > it in a different > > way. > > > > > > v10: - fix ping with following tftp command issue with incorrect > > ping timeout clear. > > - Makefile on make will init submodules and if needed will > >do git clone. > > - wget - some minor code style changes. > > v9: - added first patch describing git submodule for lwip. So > > the build procedure is: > > git submodule init > > git submodule update > > make > > - reworked a little bit dhcp cmd state polling > > - fixed review comments for v8 > > v8: - comments for previous review > > - removed lwip timeout callback pointer > > - made lwip timeouts works, that also allowed to remove > > static vars. > > - setenv for filesize tftp and wget has to be in hex. > > - Makefile changes always compile it tftp,dns,wget,ping due > > to it can be used not only by CONFIG_CMD_. > > - Kconfig changes - simplify lwIP settings and support only > > one configuration. > > - tested with mini debian.iso load over http or tftp, mount > > and boot it (qemu, arm64). > > v7: - more review fixes. > > - support of multiply eth devices, were "ethact" selects the > > active device. > > v6: - fixed review comments for v5 (thanks Ilias and Simon). > > v5: - fixed Iliases comments and split big patch on the small > > ones. > > v4: - tested with tests/py/ did some minor fixes (out of tree > > build, variables set after downloads). > > - accounted review comments for documentation. > > - implemented dns command > > - corrected wget command to not use serverip variable and > use just > > url string. > > v3: - use lwip commands for ping,tftp,wget,dhcp if this patch > > applied. Drop CONFIG_LIB_LWIP_REPLACE_ option. > > - docs: use rst variant and drop references to RFC. > > > > Maxim Uvarov (43): > > submodule: add lwIP as git submodule > > net/lwip: add doc/develop/net_lwip.rst > > net/lwip: integrate lwIP library > > net/lwip: implement dns cmd > > net/lwip: implement dhcp cmd > > net/lwip: implement tftp cmd > > net/lwip: implement wget cmd > > net/lwip: implement ping cmd > > net/lwip: add lwIP configuration > > net/lwip: implement lwIP port to U-Boot > > net/lwip: update .gitignore with lwIP > > net/lwip: connection between cmd and lwip apps > > net/lwip: replace original net commands with lwip > > net/lwip: split net.h to net.h, arp.h and eth.h > > I think the patches below likely make sense to be split out, either > into individual patches or a fixes/cleanup series that the LWIP series > depends upon. A bunch of the patches below look like they would even > be reasonable fixes for the current release cycle. > > Peter > Yes, Peter, some fixes are not related to lwip, but somehow they triggered failures. I will send them as a separate patchset. What I'm trying to do now is disable TCP for lwip and remove original tftp,ping and dns code. In my calculations this
Re: [PATHv11 00/43] net/lwip: add lwip library for the network stack
Hi Maxim, On Thu, Nov 30, 2023 at 5:39 AM Maxim Uvarov wrote: > If networking for some reason doesn't work on that board (I tested only > virtual board). Please try to compile with: Could you also try on a real board? Tom tested on a Raspberry Pi3 and it failed too: https://lore.kernel.org/u-boot/20231127185953.GW2513409@bill-the-cat/ > CONFIG_LWIP_LIB_DEBUG=y > #CONFIG_LWIP_LIB_NOASSERT is not set > > It should make network activity more verbose. In many cases I saw issues that > physically MAC address do not match to lwip initialized value, > and lwip drops such packets. The ping response with: CONFIG_LWIP_LIB_DEBUG=y #CONFIG_LWIP_LIB_NOASSERT is not set u-boot=> ping 192.168.0.16 init already done for eth1 Using eth1 device pinging addr: 192.168.0.16 ping: send 192.168.0.16 ip4_output_if: 0IP header: +---+ | 4 | 5 | 0x00 |60 | (v, hl, tos, len) +---+ | 40 |000| 0 | (id, flags, offset) +---+ | 255 |1 |0x3994 | (ttl, proto, chksum) +---+ | 192 | 168 |0 | 164 | (src) +---+ | 192 | 168 |0 | 16 | (dest) +---+ ip4_output_if: call netif->output() etharp_find_entry: found matching entry 0 etharp_query: queued packet bdf03e70 on ARP entry 0 ping_tmo: ping failed; host 192.168.0.16 is not alive u-boot=>
[PATCH] arm: apple: t602x: Add missing MMIO regions to memmap
From: Janne Grunau
The memory maps for Apple's M2 Pro/Max/Ultra left MMIO space out which
was not used by any driver at the time. The display out exposed as
simple-framebuffer use a power-domain controlled by a device in an
unmapped region.
Add a map covering this region as well as another MMIO region in the
range 0x4'' - 0x5''. The added regions cover all MMIO
annotated in Apple's device tree in this range.
Signed-off-by: Janne Grunau
---
arch/arm/mach-apple/board.c | 48 +
1 file changed, 48 insertions(+)
diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c
index 47393babbc..e05ec431bc 100644
--- a/arch/arm/mach-apple/board.c
+++ b/arch/arm/mach-apple/board.c
@@ -370,6 +370,22 @@ static struct mm_region t6020_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x4,
+ .phys = 0x4,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x48000,
+ .phys = 0x48000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x58000,
@@ -471,6 +487,22 @@ static struct mm_region t6022_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x4,
+ .phys = 0x4,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x48000,
+ .phys = 0x48000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x58000,
@@ -551,6 +583,22 @@ static struct mm_region t6022_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x24,
+ .phys = 0x24,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x248000,
+ .phys = 0x248000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x258000,
---
base-commit: 43f2873fa98b1da6eb56d756315c7bd7db63db27
change-id: 20231130-apple_t602x_extend_memmap-c82c522ca8c0
Best regards,
--
Janne Grunau
[PATCH v2 2/6] siemens: eeprom: simplify setup & read
Since we have boards using the driver model or not for i2c, use abstraction
function to probe the i2c, check the EEPROM and read from EEPROM.
Signed-off-by: Enrico Leto
---
board/siemens/common/board.c | 50 --
board/siemens/common/board.h | 3 ++
board/siemens/common/factoryset.c | 58 +--
board/siemens/draco/board.c | 23
board/siemens/pxm2/board.c| 2 +-
board/siemens/rut/board.c | 2 +-
6 files changed, 67 insertions(+), 71 deletions(-)
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index f3e3c340b38..ddbb92811cf 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -39,6 +39,50 @@
DECLARE_GLOBAL_DATA_PTR;
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+static struct udevice *i2c_dev;
+#endif
+
+/* Probe I2C and set-up EEPROM */
+int siemens_ee_setup(void)
+{
+#if CONFIG_IS_ENABLED(DM_I2C)
+ struct udevice *bus;
+ int ret;
+
+ ret = uclass_get_device_by_seq(UCLASS_I2C, SIEMENS_EE_I2C_BUS, );
+ if (ret)
+ goto err;
+
+ ret = dm_i2c_probe(bus, SIEMENS_EE_I2C_ADDR, 0, _dev);
+ if (ret)
+ goto err;
+ if (i2c_set_chip_offset_len(i2c_dev, 2))
+ goto err;
+#else
+ i2c_set_bus_num(SIEMENS_EE_I2C_BUS);
+ if (i2c_probe(SIEMENS_EE_I2C_ADDR))
+ goto err;
+#endif
+ return 0;
+
+err:
+ printf("Could not probe the EEPROM; something fundamentally wrong on
the I2C bus.\n");
+ return 1;
+}
+
+/* Read data from EEPROM */
+int siemens_ee_read_data(uint address, uchar *buffer, int len)
+{
+#if CONFIG_IS_ENABLED(DM_I2C)
+ return dm_i2c_read(i2c_dev, address, buffer, len);
+#else
+ return i2c_read(SIEMENS_EE_I2C_ADDR, address, 2, buffer, len);
+#endif
+}
+
+
#ifdef CONFIG_SPL_BUILD
void set_uart_mux_conf(void)
{
@@ -49,12 +93,13 @@ void set_mux_conf_regs(void)
{
/* Initalize the board header */
enable_i2c0_pin_mux();
- i2c_set_bus_num(0);
/* enable early the console */
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
gd->have_console = 1;
+
+ siemens_ee_setup();
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
@@ -79,8 +124,7 @@ int board_init(void)
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif /* defined(CONFIG_HW_WATCHDOG) */
- i2c_set_bus_num(0);
- if (read_eeprom() < 0)
+ if (siemens_ee_setup() < 0)
puts("Could not get board ID.\n");
#ifdef CONFIG_MACH_TYPE
gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
diff --git a/board/siemens/common/board.h b/board/siemens/common/board.h
index 0d5b369028f..2b49348919a 100644
--- a/board/siemens/common/board.h
+++ b/board/siemens/common/board.h
@@ -18,4 +18,7 @@
#define SIEMENS_EE_ADDR_CHIP 0x120
#define SIEMENS_EE_ADDR_FACTORYSET 0x400
+int siemens_ee_setup(void);
+int siemens_ee_read_data(uint address, uchar *buffer, int len);
+
#endif /* _BOARD_COMMON_H_ */
diff --git a/board/siemens/common/factoryset.c
b/board/siemens/common/factoryset.c
index 94c671389dc..8f5cf04 100644
--- a/board/siemens/common/factoryset.c
+++ b/board/siemens/common/factoryset.c
@@ -148,39 +148,14 @@ int factoryset_read_eeprom(int i2c_addr)
int i, pages = 0, size = 0;
unsigned char eeprom_buf[0x3c00], hdr[4], buf[MAX_STRING_LENGTH];
unsigned char *cp, *cp1;
-#if CONFIG_IS_ENABLED(DM_I2C)
- struct udevice *bus, *dev;
- int ret;
-#endif
#if defined(CONFIG_DFU_OVER_USB)
factory_dat.usb_vendor_id = CONFIG_USB_GADGET_VENDOR_NUM;
factory_dat.usb_product_id = CONFIG_USB_GADGET_PRODUCT_NUM;
#endif
-#if CONFIG_IS_ENABLED(DM_I2C)
- ret = uclass_get_device_by_seq(UCLASS_I2C, SIEMENS_EE_I2C_BUS, );
- if (ret)
- goto err;
-
- ret = dm_i2c_probe(bus, i2c_addr, 0, );
- if (ret)
- goto err;
-
- ret = i2c_set_chip_offset_len(dev, 2);
- if (ret)
- goto err;
-
- ret = dm_i2c_read(dev, SIEMENS_EE_ADDR_FACTORYSET, hdr, sizeof(hdr));
- if (ret)
- goto err;
-#else
- if (i2c_probe(i2c_addr))
- goto err;
-
- if (i2c_read(i2c_addr, SIEMENS_EE_ADDR_FACTORYSET, 2, hdr, sizeof(hdr)))
+ if (siemens_ee_read_data(SIEMENS_EE_ADDR_FACTORYSET, hdr, sizeof(hdr)))
goto err;
-#endif
if ((hdr[0] != 0x99) || (hdr[1] != 0x80)) {
printf("FactorySet is not right in eeprom.\n");
@@ -201,33 +176,16 @@ int factoryset_read_eeprom(int i2c_addr)
* data after every time we got a record from eeprom
*/
debug("Read eeprom page :\n");
- for (i = 0; i < pages; i++) {
-#if CONFIG_IS_ENABLED(DM_I2C)
- ret = dm_i2c_read(dev, (OFF_PG + i) * EEPR_PG_SZ,
- eeprom_buf + (i * EEPR_PG_SZ),
[PATCH v2 1/6] siemens: eeprom: clean up definitions
Move the I2C and EEPROM address definitions in common board header.
Reviewed-by: Alexander Sverdlin
Signed-off-by: Enrico Leto
---
board/siemens/capricorn/board.c | 5 ++---
board/siemens/common/board.c | 6 +++---
board/siemens/common/board.h | 21 +
board/siemens/common/factoryset.c | 12 ++--
board/siemens/draco/board.c | 13 +
include/configs/draco-etamin.h| 3 ---
include/configs/draco-rastaban.h | 3 ---
include/configs/draco-thuban.h| 3 ---
8 files changed, 37 insertions(+), 29 deletions(-)
create mode 100644 board/siemens/common/board.h
diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c
index 924c88e8fab..81fa340ca42 100644
--- a/board/siemens/capricorn/board.c
+++ b/board/siemens/capricorn/board.c
@@ -28,6 +28,7 @@
#include
#endif
#include
+#include "../common/board.h"
#include "../common/factoryset.h"
#define GPIO_PAD_CTRL \
@@ -337,13 +338,11 @@ void board_late_mmc_env_init(void)
}
#ifndef CONFIG_SPL_BUILD
-int factoryset_read_eeprom(int i2c_addr);
-
static int load_parameters_from_factoryset(void)
{
int ret;
- ret = factoryset_read_eeprom(EEPROM_I2C_ADDR);
+ ret = factoryset_read_eeprom(SIEMENS_EE_I2C_ADDR);
if (ret)
return ret;
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index 8fa9197a6df..f3e3c340b38 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -34,7 +34,8 @@
#include
#include
#include
-#include "../common/factoryset.h"
+#include "board.h"
+#include "factoryset.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -70,7 +71,6 @@ void sdram_init(void)
#endif /* #ifdef CONFIG_SPL_BUILD */
#ifndef CONFIG_SPL_BUILD
-#define FACTORYSET_EEPROM_ADDR 0x50
/*
* Basic board specific setup. Pinmux has been handled already.
*/
@@ -88,7 +88,7 @@ int board_init(void)
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_FACTORYSET
- factoryset_read_eeprom(FACTORYSET_EEPROM_ADDR);
+ factoryset_read_eeprom(SIEMENS_EE_I2C_ADDR);
#endif
gpmc_init();
diff --git a/board/siemens/common/board.h b/board/siemens/common/board.h
new file mode 100644
index 000..0d5b369028f
--- /dev/null
+++ b/board/siemens/common/board.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright Siemens AG 2023
+ *
+ * Common board definitions for siemens boards
+ */
+
+#ifndef _BOARD_COMMON_H_
+#define _BOARD_COMMON_H_
+
+/* EEPROM @ I2C */
+#define SIEMENS_EE_I2C_BUS 0
+#define SIEMENS_EE_I2C_ADDR0x50
+
+/* EEPROM mapping */
+#define SIEMENS_EE_ADDR_NAND_GEO 0x80
+#define SIEMENS_EE_ADDR_DDR3 0x90
+#define SIEMENS_EE_ADDR_CHIP 0x120
+#define SIEMENS_EE_ADDR_FACTORYSET 0x400
+
+#endif /* _BOARD_COMMON_H_ */
diff --git a/board/siemens/common/factoryset.c
b/board/siemens/common/factoryset.c
index 4e36a6f3199..94c671389dc 100644
--- a/board/siemens/common/factoryset.c
+++ b/board/siemens/common/factoryset.c
@@ -22,11 +22,11 @@
#include
#include
#include
+#include "board.h"
#include "factoryset.h"
-#define EEPR_PG_SZ 0x80
-#define EEPROM_FATORYSET_OFFSET0x400
-#define OFF_PGEEPROM_FATORYSET_OFFSET/EEPR_PG_SZ
+#define EEPR_PG_SZ 0x80
+#define OFF_PG (SIEMENS_EE_ADDR_FACTORYSET / EEPR_PG_SZ)
/* Global variable that contains necessary information from FactorySet */
struct factorysetcontainer factory_dat;
@@ -159,7 +159,7 @@ int factoryset_read_eeprom(int i2c_addr)
#endif
#if CONFIG_IS_ENABLED(DM_I2C)
- ret = uclass_get_device_by_seq(UCLASS_I2C, EEPROM_I2C_BUS, );
+ ret = uclass_get_device_by_seq(UCLASS_I2C, SIEMENS_EE_I2C_BUS, );
if (ret)
goto err;
@@ -171,14 +171,14 @@ int factoryset_read_eeprom(int i2c_addr)
if (ret)
goto err;
- ret = dm_i2c_read(dev, EEPROM_FATORYSET_OFFSET, hdr, sizeof(hdr));
+ ret = dm_i2c_read(dev, SIEMENS_EE_ADDR_FACTORYSET, hdr, sizeof(hdr));
if (ret)
goto err;
#else
if (i2c_probe(i2c_addr))
goto err;
- if (i2c_read(i2c_addr, EEPROM_FATORYSET_OFFSET, 2, hdr, sizeof(hdr)))
+ if (i2c_read(i2c_addr, SIEMENS_EE_ADDR_FACTORYSET, 2, hdr, sizeof(hdr)))
goto err;
#endif
diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c
index 8874659013f..6e61236ce22 100644
--- a/board/siemens/draco/board.c
+++ b/board/siemens/draco/board.c
@@ -37,6 +37,7 @@
#include
#include
#include "board.h"
+#include "../common/board.h"
#include "../common/factoryset.h"
#include
@@ -132,16 +133,12 @@ struct am335x_nand_geometry {
u8 nand_bus;
};
-#define EEPROM_ADDR0x50
-#define EEPROM_ADDR_DDR3 0x90
-#define EEPROM_ADDR_CHIP 0x120
-
static int draco_read_nand_geometry(void)
{
struct am335x_nand_geometry geo;
[PATCH v2 6/6] siemens: factoryset: use correct config for soc specific implementation
Adding the capricorn board family some parts diverge from draco family.
The switches used were not pertinent and need to be enhanced for each new
board of the capricorn family. Replace them through the SOC name 'AM33XX'
and 'IMX8'.
Signed-off-by: Enrico Leto
---
board/siemens/common/factoryset.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/siemens/common/factoryset.c
b/board/siemens/common/factoryset.c
index 9adc42ce0b7..6d773a87075 100644
--- a/board/siemens/common/factoryset.c
+++ b/board/siemens/common/factoryset.c
@@ -11,7 +11,7 @@
#include
#include
#include
-#if !CONFIG_IS_ENABLED(TARGET_GIEDI) && !CONFIG_IS_ENABLED(TARGET_DENEB)
+#if CONFIG_IS_ENABLED(AM33XX)
#include
#endif
#include "board.h"
@@ -197,7 +197,7 @@ int factoryset_read_eeprom(int i2c_addr)
cp1 += 3;
}
-#if CONFIG_IS_ENABLED(TARGET_GIEDI) || CONFIG_IS_ENABLED(TARGET_DENEB)
+#if CONFIG_IS_ENABLED(IMX8)
/* get mac address for WLAN */
ret = get_factory_record_val(cp, size, (uchar *)"WLAN1", (uchar *)"mac",
buf, MAX_STRING_LENGTH);
@@ -305,7 +305,7 @@ static int factoryset_mac_env_set(void)
eth_env_set_enetaddr("ethaddr", mac_addr);
-#if CONFIG_IS_ENABLED(TARGET_GIEDI) || CONFIG_IS_ENABLED(TARGET_DENEB)
+#if CONFIG_IS_ENABLED(IMX8)
eth_env_set_enetaddr("eth1addr", mac_addr);
/* wlan mac */
--
2.30.2
[PATCH v2 5/6] siemens: board: clean up includes
Many includes were not removed when code parts were moved or removed.
Signed-off-by: Enrico Leto
---
board/siemens/common/board.c | 24 +++-
board/siemens/common/factoryset.c | 12 ++--
board/siemens/draco/board.c | 23 +--
board/siemens/draco/mux.c | 4 +---
board/siemens/pxm2/board.c| 22 --
board/siemens/pxm2/mux.c | 4 +---
board/siemens/rut/board.c | 21 +++--
board/siemens/rut/mux.c | 4 +---
8 files changed, 20 insertions(+), 94 deletions(-)
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index 981ffe4e69a..d3e5b83e30f 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -8,30 +8,12 @@
* (C) Heiko Schocher, DENX Software Engineering, h...@denx.de.
*/
-#include
#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
+#include
#include
-#include
-#include
#include
+#include
+#include
#include
#include "board.h"
#include "factoryset.h"
diff --git a/board/siemens/common/factoryset.c
b/board/siemens/common/factoryset.c
index 8f5cf04..9adc42ce0b7 100644
--- a/board/siemens/common/factoryset.c
+++ b/board/siemens/common/factoryset.c
@@ -7,21 +7,13 @@
#if !defined(CONFIG_SPL_BUILD)
-#include
#include
-#include
-#include
-#include
-#include
+#include
+#include
#include
#if !CONFIG_IS_ENABLED(TARGET_GIEDI) && !CONFIG_IS_ENABLED(TARGET_DENEB)
#include
#endif
-#include
-#include
-#include
-#include
-#include
#include "board.h"
#include "factoryset.h"
diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c
index 821da67e0ba..6a59eaddc24 100644
--- a/board/siemens/draco/board.c
+++ b/board/siemens/draco/board.c
@@ -12,30 +12,17 @@
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*/
-#include
#include
+#include
#include
-#include
#include
-#include
-#include
-#include
-#include
-#include
-#include
+#include
+#include
#include
-#include
-#include
+#include
#include
-#include
-#include
-#include
#include
-#include
-#include
-#include
-#include
-#include
+#include
#include "board.h"
#include "../common/board_am335x.h"
#include "../common/factoryset.h"
diff --git a/board/siemens/draco/mux.c b/board/siemens/draco/mux.c
index 1bf0fa961aa..13228039bb7 100644
--- a/board/siemens/draco/mux.c
+++ b/board/siemens/draco/mux.c
@@ -10,12 +10,10 @@
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*/
-#include
+#include
#include
#include
#include
-#include
-#include
#include "../common/board_am335x.h"
static struct module_pin_mux uart0_pin_mux[] = {
diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c
index f26e3d8945f..959184008a8 100644
--- a/board/siemens/pxm2/board.c
+++ b/board/siemens/pxm2/board.c
@@ -12,32 +12,18 @@
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*/
-#include
+#include
#include
-#include
+#include
#include
-#include
-#include
+#include
#include
-#include
-#include
-#include
-#include
-#include
#include
-#include
-#include
+#include
#include
#include
-#include
#include
-#include
-#include
-#include
-#include
#include "pmic.h"
-#include
-#include
#include "../common/board_am335x.h"
#include "../common/factoryset.h"
diff --git a/board/siemens/pxm2/mux.c b/board/siemens/pxm2/mux.c
index 50ef657de10..6f4e64c523c 100644
--- a/board/siemens/pxm2/mux.c
+++ b/board/siemens/pxm2/mux.c
@@ -11,12 +11,10 @@
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*/
-#include
+#include
#include
#include
#include
-#include
-#include
#include "../common/board_am335x.h"
static struct module_pin_mux uart0_pin_mux[] = {
diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c
index 7dd527349a2..3f79502c247 100644
--- a/board/siemens/rut/board.c
+++ b/board/siemens/rut/board.c
@@ -10,31 +10,16 @@
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*/
-#include
+#include
#include
-#include
#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
+#include
+#include
#include
#include
-#include
-#include
#include
#include
-#include
#include
-#include
-#include
-#include
-#include
-#include
-#include
#include "../common/board_am335x.h"
#include "../common/factoryset.h"
diff --git a/board/siemens/rut/mux.c b/board/siemens/rut/mux.c
index ff752b676a3..c226d299526 100644
--- a/board/siemens/rut/mux.c
+++ b/board/siemens/rut/mux.c
@@ -11,12 +11,10 @@
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*/
-#include
+#include
#include
#include
#include
[PATCH v2 4/6] siemens: board: clean up draco products vs common
The common folder was initialially created for the common parts of the
products based on draco-am355x board family. These are the product
lines 'pxm2', 'rut' and the base line named 'draco'!
Adding the new capricorn-imx8 board family, common was enhanced without
cleanup.
Move all am355x specifics to a new file 'board_am335x'.
Reviewed-by: Alexander Sverdlin
Signed-off-by: Enrico Leto
---
board/siemens/common/board.c| 54 +++
board/siemens/common/board_am335x.c | 58 +
board/siemens/common/board_am335x.h | 38 +++
board/siemens/draco/Makefile| 2 +
board/siemens/draco/board.c | 10 ++---
board/siemens/draco/board.h | 32 +++-
board/siemens/draco/mux.c | 2 +-
board/siemens/pxm2/MAINTAINERS | 2 +-
board/siemens/pxm2/Makefile | 2 +
board/siemens/pxm2/board.c | 10 ++---
board/siemens/pxm2/board.h | 21 ---
board/siemens/pxm2/mux.c| 2 +-
board/siemens/rut/MAINTAINERS | 2 +-
board/siemens/rut/Makefile | 2 +
board/siemens/rut/board.c | 10 ++---
board/siemens/rut/board.h | 21 ---
board/siemens/rut/mux.c | 1 +
17 files changed, 129 insertions(+), 140 deletions(-)
create mode 100644 board/siemens/common/board_am335x.c
create mode 100644 board/siemens/common/board_am335x.h
delete mode 100644 board/siemens/pxm2/board.h
delete mode 100644 board/siemens/rut/board.h
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index ddbb92811cf..981ffe4e69a 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -1,12 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Common board functions for siemens AM335X based boards
+ * Common board functions for siemens based boards
+ *
+ * TI am335x specifics moved to board_am335x.c
+ *
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, h...@denx.de.
- *
- * Based on:
- * U-Boot file:/board/ti/am335x/board.c
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*/
#include
@@ -39,7 +38,6 @@
DECLARE_GLOBAL_DATA_PTR;
-
#if CONFIG_IS_ENABLED(DM_I2C)
static struct udevice *i2c_dev;
#endif
@@ -82,39 +80,6 @@ int siemens_ee_read_data(uint address, uchar *buffer, int
len)
#endif
}
-
-#ifdef CONFIG_SPL_BUILD
-void set_uart_mux_conf(void)
-{
- enable_uart0_pin_mux();
-}
-
-void set_mux_conf_regs(void)
-{
- /* Initalize the board header */
- enable_i2c0_pin_mux();
-
- /* enable early the console */
- gd->baudrate = CONFIG_BAUDRATE;
- serial_init();
- gd->have_console = 1;
-
- siemens_ee_setup();
- if (read_eeprom() < 0)
- puts("Could not get board ID.\n");
-
- enable_board_pin_mux();
-}
-
-void sdram_init(void)
-{
- spl_siemens_board_init();
- board_init_ddr();
-
- return;
-}
-#endif /* #ifdef CONFIG_SPL_BUILD */
-
#ifndef CONFIG_SPL_BUILD
/*
* Basic board specific setup. Pinmux has been handled already.
@@ -145,15 +110,6 @@ int board_init(void)
}
#endif /* #ifndef CONFIG_SPL_BUILD */
-#define OSC(V_OSCK/100)
-const struct dpll_params dpll_ddr = {
- DDR_PLL_FREQ, OSC-1, 1, -1, -1, -1, -1};
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
- return _ddr;
-}
-
#ifndef CONFIG_SPL_BUILD
#define MAX_NR_LEDS10
@@ -232,7 +188,7 @@ U_BOOT_CMD(
* defines the startup state of the led, S1 the special state of the led when
* it enters e.g. dfu mode.
*/
-void set_env_gpios(unsigned char state)
+static void set_env_gpios(unsigned char state)
{
char *ptr_env;
char str_tmp[5];/* must contain "ledX"*/
diff --git a/board/siemens/common/board_am335x.c
b/board/siemens/common/board_am335x.c
new file mode 100644
index 000..c44b09a21e3
--- /dev/null
+++ b/board/siemens/common/board_am335x.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Common board functions for siemens AM335X based boards
+ * (C) Copyright Siemens AG 2013
+ * (C) Heiko Schocher, DENX Software Engineering, h...@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/board/ti/am335x/board.c
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#include
+#include
+#include
+#include "board_am335x.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ /* Initalize the board header */
+ enable_i2c0_pin_mux();
+
+ /* enable early the console */
+ gd->baudrate = CONFIG_BAUDRATE;
+ serial_init();
+ gd->have_console = 1;
+
+ siemens_ee_setup();
+ if (siemens_read_eeprom() < 0)
+ puts("Could not get board ID.\n");
+
+ enable_board_pin_mux();
+}
+
+void sdram_init(void)
+{
+
[PATCH v2 3/6] siemens draco: i2c: use driver model for u-boot
Add support for driver model where EEPROM data are read in draco board. Reviewed-by: Alexander Sverdlin Signed-off-by: Enrico Leto --- configs/draco-etamin_defconfig | 4 +++- configs/draco-rastaban_defconfig | 4 +++- configs/draco-thuban_defconfig | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/configs/draco-etamin_defconfig b/configs/draco-etamin_defconfig index eade2297229..8a860a73aab 100644 --- a/configs/draco-etamin_defconfig +++ b/configs/draco-etamin_defconfig @@ -86,8 +86,10 @@ CONFIG_CLK=y CONFIG_CLK_TI_CTRL=y CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x10 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y +# CONFIG_SPL_DM_I2C is not set CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y # CONFIG_SPL_DM_MMC is not set CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/draco-rastaban_defconfig b/configs/draco-rastaban_defconfig index 252cbe3d78e..c95e54be2ee 100644 --- a/configs/draco-rastaban_defconfig +++ b/configs/draco-rastaban_defconfig @@ -84,8 +84,10 @@ CONFIG_CLK=y CONFIG_CLK_TI_CTRL=y CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x10 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y +# CONFIG_SPL_DM_I2C is not set CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/draco-thuban_defconfig b/configs/draco-thuban_defconfig index d8b80b83f10..0b6b488d0fe 100644 --- a/configs/draco-thuban_defconfig +++ b/configs/draco-thuban_defconfig @@ -84,8 +84,10 @@ CONFIG_CLK=y CONFIG_CLK_TI_CTRL=y CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x10 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y +# CONFIG_SPL_DM_I2C is not set CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y -- 2.30.2
[PATCH v2 0/6] board: siemens: clean up subfolders
This serie depends on the serie: [PATCH 0/6] siemens,am335x: clean up the draco board family The common folder was initialially created for the common parts of the products based on draco-am355x board family. We have the product lines 'pxm2', 'rut' and the base line unfortunately named 'draco'! Adding the new capricorn-imx8 board family, the files were enhanced without cleanup. Simplify first EEPROM probe and access that implements both i2c with & without driver model. Use abstraction functions for this. Move all am355x specifics to a new file 'board_am335x'. Clean-up includes, config checks, maintainer. Signed-off-by: Enrico Leto --- Changes for v2: - fix wrong value in CONFIG_IS_ENABLED Enrico Leto (6): siemens: eeprom: clean up definitions siemens: eeprom: simplify setup & read siemens draco: i2c: use driver model for u-boot siemens: board: clean up draco products vs common siemens: board: clean up includes siemens: factoryset: use correct config for soc specific implementation board/siemens/capricorn/board.c | 5 +- board/siemens/common/board.c| 110 board/siemens/common/board.h| 24 ++ board/siemens/common/board_am335x.c | 58 +++ board/siemens/common/board_am335x.h | 38 ++ board/siemens/common/factoryset.c | 82 - board/siemens/draco/Makefile| 2 + board/siemens/draco/board.c | 59 --- board/siemens/draco/board.h | 32 ++-- board/siemens/draco/mux.c | 6 +- board/siemens/pxm2/MAINTAINERS | 2 +- board/siemens/pxm2/Makefile | 2 + board/siemens/pxm2/board.c | 34 +++-- board/siemens/pxm2/board.h | 21 -- board/siemens/pxm2/mux.c| 6 +- board/siemens/rut/MAINTAINERS | 2 +- board/siemens/rut/Makefile | 2 + board/siemens/rut/board.c | 33 ++--- board/siemens/rut/board.h | 21 -- board/siemens/rut/mux.c | 5 +- configs/draco-etamin_defconfig | 4 +- configs/draco-rastaban_defconfig| 4 +- configs/draco-thuban_defconfig | 4 +- include/configs/draco-etamin.h | 3 - include/configs/draco-rastaban.h| 3 - include/configs/draco-thuban.h | 3 - 26 files changed, 245 insertions(+), 320 deletions(-) create mode 100644 board/siemens/common/board.h create mode 100644 board/siemens/common/board_am335x.c create mode 100644 board/siemens/common/board_am335x.h delete mode 100644 board/siemens/pxm2/board.h delete mode 100644 board/siemens/rut/board.h -- 2.30.2
[PATCH V2 2/2] configs: andes: add watchdog support fot andes ae350
It adds the ATCWDT200 support for Andes AE350 platform. It also enables wdt command support. Signed-off-by: CL Wang Signed-off-by: Randolph --- configs/ae350_rv32_defconfig | 4 configs/ae350_rv32_spl_defconfig | 4 configs/ae350_rv32_spl_xip_defconfig | 4 configs/ae350_rv32_xip_defconfig | 4 configs/ae350_rv64_defconfig | 4 configs/ae350_rv64_spl_defconfig | 4 configs/ae350_rv64_spl_xip_defconfig | 4 configs/ae350_rv64_xip_defconfig | 4 8 files changed, 32 insertions(+) diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 06cd972a0d..eb4dd90311 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -48,3 +49,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index f469d5bb2b..e09f878329 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -57,3 +58,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 9672a19c23..850e67a0d9 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -58,3 +59,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index b90200a97e..fa0b52f686 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -49,3 +50,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index a4b9ad6162..e67c9cbf93 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -48,3 +49,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 834a0fbbdd..1a3c294b16 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -57,3 +58,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index b52b8d78d7..f8db0a1a85 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -58,3 +59,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index cc5e751c9b..51509e76c5 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y
[PATCH V2 1/2] drivers: watchdog: add andes atcwdt200 support
This patch adds an implementation of the Andes watchdog ATCWDT200 driver.
Signed-off-by: CL Wang
Signed-off-by: Randolph
---
drivers/watchdog/Kconfig | 6 +
drivers/watchdog/Makefile| 1 +
drivers/watchdog/atcwdt200_wdt.c | 220 +++
3 files changed, 227 insertions(+)
create mode 100644 drivers/watchdog/atcwdt200_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 07fc4940e9..6b0f77dd3f 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -130,6 +130,12 @@ config WDT_AT91
Select this to enable Microchip watchdog timer, which can be found on
some AT91 devices.
+config WDT_ATCWDT200
+ bool "Andes watchdog timer support"
+ depends on WDT
+ help
+ Select this to enable Andes ATCWDT200 watchdog timer
+
config WDT_BCM6345
bool "BCM6345 watchdog timer support"
depends on WDT && (ARCH_BMIPS || BCM6856 || \
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index eef786f5e7..1750ebbb1f 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_WDT_ARM_SMC) += arm_smc_wdt.o
obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o
+obj-$(CONFIG_WDT_ATCWDT200) += atcwdt200_wdt.o
obj-$(CONFIG_WDT_BCM2835) += bcm2835_wdt.o
obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o
diff --git a/drivers/watchdog/atcwdt200_wdt.c b/drivers/watchdog/atcwdt200_wdt.c
new file mode 100644
index 00..2a456d7a46
--- /dev/null
+++ b/drivers/watchdog/atcwdt200_wdt.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Andes Technology Corporation.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define NODE_NOT_FOUND 0x
+
+#define WDT_WP_MAGIC 0x5aa5
+#define WDT_RESTART_MAGIC 0xcafe
+
+/* Control Register */
+#define REG_WDT_ID 0x00
+#define REG_WDT_CFG0x10
+#define REG_WDT_RS 0x14
+#define REG_WDT_WE 0x18
+#define REG_WDT_STA0x1C
+
+#define RST_TIME_OFF 8
+#define RST_TIME_MSK (0x7 << RST_TIME_OFF)
+#define RST_CLK_128(0 << RST_TIME_OFF)
+#define RST_CLK_256(1 << RST_TIME_OFF)
+#define RST_CLK_512(2 << RST_TIME_OFF)
+#define RST_CLK_1024 (3 << RST_TIME_OFF)
+#define INT_TIME_OFF 4
+#define INT_TIME_MSK (0xf << INT_TIME_OFF)
+#define INT_CLK_2_6(0 << INT_TIME_OFF) /* clk period*2^6 */
+#define INT_CLK_2_8(1 << INT_TIME_OFF) /* clk period*2^8 */
+#define INT_CLK_2_10 (2 << INT_TIME_OFF) /* clk period*2^10 */
+#define INT_CLK_2_11 (3 << INT_TIME_OFF) /* clk period*2^11 */
+#define INT_CLK_2_12 (4 << INT_TIME_OFF) /* clk period*2^12 */
+#define INT_CLK_2_13 (5 << INT_TIME_OFF) /* clk period*2^13 */
+#define INT_CLK_2_14 (6 << INT_TIME_OFF) /* clk period*2^14 */
+#define INT_CLK_2_15 (7 << INT_TIME_OFF) /* clk period*2^15 */
+#define INT_CLK_2_17 (8 << INT_TIME_OFF) /* clk period*2^17 */
+#define INT_CLK_2_19 (9 << INT_TIME_OFF) /* clk period*2^19 */
+#define INT_CLK_2_21 (10 << INT_TIME_OFF) /* clk period*2^21 */
+#define INT_CLK_2_23 (11 << INT_TIME_OFF) /* clk period*2^23 */
+#define INT_CLK_2_25 (12 << INT_TIME_OFF) /* clk period*2^25 */
+#define INT_CLK_2_27 (13 << INT_TIME_OFF) /* clk period*2^27 */
+#define INT_CLK_2_29 (14 << INT_TIME_OFF) /* clk period*2^29 */
+#define INT_CLK_2_31 (15 << INT_TIME_OFF) /* clk period*2^31 */
+#define INT_CLK_MIN0x0
+#define INT_CLK_MAX_16B0x7
+#define INT_CLK_MAX_32B0xF
+#define RST_EN BIT(3)
+#define INT_EN BIT(2)
+#define CLK_PCLK BIT(1)
+#define WDT_EN BIT(0)
+#define INT_EXPIREDBIT(0)
+
+#define INT_TIME_ARRAY 16
+#define RST_TIME_ARRAY 8
+
+struct wdt_priv {
+ void __iomem *base;
+ u32 wdt_clk_src;
+ u32 clk_freq;
+ u8 max_clk;
+};
+
+static inline u8 atcwdt_get_2_power_of_n(u8 index, u8 type)
+{
+ const u8 div_int[INT_TIME_ARRAY] = {6, 8, 10, 11, 12, 13, 14, 15,
+ 17, 19, 21, 23, 25, 27, 29, 31};
+ const u8 div_rst[RST_TIME_ARRAY] = {7, 8, 9, 10, 11, 12, 13, 14};
+ u8 *pdiv;
+
+ if (type == RST_TIME_ARRAY)
+ pdiv = div_rst;
+ else
+ pdiv = div_int;
+
+ if (index >= type)
+ index = type - 1;
+
+ return pdiv[index];
+}
+
+static u8 atwdt_search_msb(u64 freq_ms, u8 type)
+{
+ u64 result;
+ u64 freq_sec;
+ u8 index;
+
+ freq_sec = freq_ms / 1000;
+ for (index = 0; index < type; index++) {
+ result = freq_sec >> atcwdt_get_2_power_of_n(index, type);
+
+ if (result <= 1)
+ break;
+ }
+
[PATCH v5 17/17] board: ti: j784s4: Add MAINTAINERS file
Add maintainership for new J784S4 files added. Signed-off-by: Apurva Nandan --- board/ti/j784s4/MAINTAINERS | 25 + 1 file changed, 25 insertions(+) create mode 100644 board/ti/j784s4/MAINTAINERS diff --git a/board/ti/j784s4/MAINTAINERS b/board/ti/j784s4/MAINTAINERS new file mode 100644 index 00..d3f0e50391 --- /dev/null +++ b/board/ti/j784s4/MAINTAINERS @@ -0,0 +1,25 @@ +J784S4 BOARD +M: Apurva Nandan +S: Maintained +F: board/ti/j784s4 +F: arch/arm/mach-k3/j784s4 +F: include/configs/j784s4_evm.h +F: configs/j784s4_evm_r5_defconfig +F: configs/j784s4_evm_a72_defconfig +F: arch/arm/dts/k3-j784s4.dtsi +F: arch/arm/dts/k3-j784s4-main.dtsi +F: arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi +F: arch/arm/dts/k3-j784s4-thermal.dtsi +F: arch/arm/dts/k3-j784s4-evm.dts +F: arch/arm/dts/k3-j784s4-evm-u-boot.dtsi +F: arch/arm/dts/k3-j784s4-r5-evm.dts +F: arch/arm/dts/k3-j784s4-ddr.dtsi +F: arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi +F: doc/board/ti/j784s4_evm.rst + +AM69 BOARD +F: arch/arm/dts/k3-am69-sk.dts +F: arch/arm/dts/k3-am69-sk-u-boot.dtsi +F: arch/arm/dts/k3-am69-r5-sk.dts +F: configs/am69_sk_r5.config +F: configs/am69_sk_a72.config -- 2.34.1
[PATCH v5 16/17] doc: board: ti: k3: Add J784S4 EVM and AM69 SK documentation
TI K3 J784S4 and AM69 are new additions to the K3 SoC family. Add documentation about the J784S4 EVM and AM69 SK. Signed-off-by: Dasnavis Sabiya Signed-off-by: Apurva Nandan --- doc/board/ti/j784s4_evm.rst | 303 doc/board/ti/k3.rst | 1 + 2 files changed, 304 insertions(+) create mode 100644 doc/board/ti/j784s4_evm.rst diff --git a/doc/board/ti/j784s4_evm.rst b/doc/board/ti/j784s4_evm.rst new file mode 100644 index 00..bb7ed0b031 --- /dev/null +++ b/doc/board/ti/j784s4_evm.rst @@ -0,0 +1,303 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +.. sectionauthor:: Apurva Nandan + +J784S4 and AM69 Platforms += + +Introduction + +The J784S4 SoC belongs to the K3 Multicore SoC architecture +platform, providing advanced system integration in automotive, +ADAS and industrial applications requiring AI at the network edge. +This SoC extends the K3 Jacinto 7 family of SoCs with focus on +raising performance and integration while providing interfaces, +memory architecture and compute performance for multi-sensor, high +concurrency applications. + +The device is partitioned into three functional domains, each containing +specific processing cores and peripherals: + +1. Wake-up (WKUP) domain +* ARM Cortex-M4F processor, runs TI Foundational Security (TIFS) + +2. Microcontroller (MCU) domain +* Dual core ARM Cortex-R5F processor, runs device management + and SoC early boot + +3. MAIN domain +* Two clusters of quad core 64-bit ARM Cortex-A72, runs HLOS +* Dual core ARM Cortex-R5F processor used for RTOS applications +* Four C7x DSPs used for Machine Learning applications. + + +More info can be found in TRM: http://www.ti.com/lit/zip/spruj52 + +Platform information: + +* https://www.ti.com/tool/J784S4XEVM +* https://www.ti.com/tool/SK-AM69 + +Boot Flow +- +Below is the pictorial representation of boot flow: + +.. image:: img/boot_diagram_k3_current.svg +:alt: K3 boot flow + +- On this platform, "TI Foundational Security (TIFS)" functions as the + security enclave master. While "Device Manager (DM)", also known as the + "TISCI server" in TI terminology, offers all the essential services. + +- As illustrated in the diagram above, R5 SPL manages power and clock + services independently before handing over control to DM. The A72 or + the C7x (Aux core) software components request TIFS/DM to handle + security or device management services. + +Sources +--- + +.. include:: k3.rst +:start-after: .. k3_rst_include_start_boot_sources +:end-before: .. k3_rst_include_end_boot_sources + +Build procedure +--- +0. Setup the environment variables: + +.. include:: k3.rst +:start-after: .. k3_rst_include_start_common_env_vars_desc +:end-before: .. k3_rst_include_end_common_env_vars_desc + +.. include:: k3.rst +:start-after: .. k3_rst_include_start_board_env_vars_desc +:end-before: .. k3_rst_include_end_board_env_vars_desc + +Set the variables corresponding to this platform: + +.. include:: k3.rst +:start-after: .. k3_rst_include_start_common_env_vars_defn +:end-before: .. k3_rst_include_end_common_env_vars_defn +.. code-block:: bash + + $ export UBOOT_CFG_CORTEXR=j784s4_evm_r5_defconfig + $ export UBOOT_CFG_CORTEXA=j784s4_evm_a72_defconfig + $ export TFA_BOARD=j784s4 + $ export TFA_EXTRA_ARGS="K3_USART=0x8" + $ export OPTEE_PLATFORM=k3-j784s4 + $ export OPTEE_EXTRA_ARGS="CFG_CONSOLE_UART=0x8" + +.. j784s4_evm_rst_include_start_build_steps + +1. Trusted Firmware-A + +.. include:: k3.rst +:start-after: .. k3_rst_include_start_build_steps_tfa +:end-before: .. k3_rst_include_end_build_steps_tfa + + +2. OP-TEE + +.. include:: k3.rst +:start-after: .. k3_rst_include_start_build_steps_optee +:end-before: .. k3_rst_include_end_build_steps_optee + +3. U-Boot + +.. _j784s4_evm_rst_u_boot_r5: + +* 3.1 R5 + +.. include:: k3.rst +:start-after: .. k3_rst_include_start_build_steps_spl_r5 +:end-before: .. k3_rst_include_end_build_steps_spl_r5 + +.. _j784s4_evm_rst_u_boot_a72: + +* 3.2 A72 + +.. include:: k3.rst +:start-after: .. k3_rst_include_start_build_steps_uboot +:end-before: .. k3_rst_include_end_build_steps_uboot +.. j784s4_evm_rst_include_end_build_steps + +Target Images +- +In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC +variant (GP, HS-FS, HS-SE) requires a different source for these files. + + - GP + +* tiboot3-j784s4-gp-evm.bin from :ref:`step 3.1 ` +* tispl.bin_unsigned, u-boot.img_unsigned from :ref:`step 3.2 ` + + - HS-FS + +* tiboot3-j784s4-hs-fs-evm.bin from :ref:`step 3.1 ` +* tispl.bin, u-boot.img from :ref:`step 3.2 ` + + - HS-SE + +* tiboot3-j784s4-hs-evm.bin from :ref:`step 3.1 ` +* tispl.bin, u-boot.img from :ref:`step 3.2 ` + +Image formats +- + +- tiboot3.bin + +.. image:: img/multi_cert_tiboot3.bin.svg +:alt:
[PATCH v5 15/17] configs: Add am69_sk_* defconfig fragments
From: Dasnavis Sabiya Add config fragments for am69_sk A72 and R5 configuration. This applies on to: j784s4_evm_a72_defconfig -> am69_sk_a72.config j784s4_evm_r5_defconfig -> am69_sk_r5.config The usage model (with the fragment) would be: make j784s4_evm_a72_defconfig am69_sk_a72.config make OR make j784s4_evm_r5_defconfig am69_sk_r5.config make Signed-off-by: Dasnavis Sabiya Signed-off-by: Apurva Nandan --- configs/am69_sk_a72.config | 3 +++ configs/am69_sk_r5.config | 3 +++ 2 files changed, 6 insertions(+) create mode 100644 configs/am69_sk_a72.config create mode 100644 configs/am69_sk_r5.config diff --git a/configs/am69_sk_a72.config b/configs/am69_sk_a72.config new file mode 100644 index 00..5668e23b37 --- /dev/null +++ b/configs/am69_sk_a72.config @@ -0,0 +1,3 @@ +# Defconfig fragment to apply on top of j784s4_evm_a72_defconfig + +CONFIG_DEFAULT_DEVICE_TREE="k3-am69-sk" diff --git a/configs/am69_sk_r5.config b/configs/am69_sk_r5.config new file mode 100644 index 00..9194694393 --- /dev/null +++ b/configs/am69_sk_r5.config @@ -0,0 +1,3 @@ +# Defconfig fragment to apply on top of j784s4_evm_r5_defconfig + +CONFIG_DEFAULT_DEVICE_TREE="k3-am69-r5-sk" -- 2.34.1
[PATCH v5 14/17] configs: j784s4_evm: Add defconfig for j784s4 evm board
Add defconfigs for building R5 U-Boot SPL and A72 U-Boot. Signed-off-by: Hari Nagalla Signed-off-by: Apurva Nandan --- configs/j784s4_evm_a72_defconfig | 180 +++ configs/j784s4_evm_r5_defconfig | 163 2 files changed, 343 insertions(+) create mode 100644 configs/j784s4_evm_a72_defconfig create mode 100644 configs/j784s4_evm_r5_defconfig diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig new file mode 100644 index 00..ae392f51cd --- /dev/null +++ b/configs/j784s4_evm_a72_defconfig @@ -0,0 +1,180 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_J784S4=y +CONFIG_TARGET_J784S4_A72_EVM=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8048 +CONFIG_SF_DEFAULT_SPEED=2500 +CONFIG_ENV_SIZE=0x2 +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="k3-j784s4-evm" +CONFIG_SPL_TEXT_BASE=0x8008 +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x8200 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +# CONFIG_PSCI_RESET is not set +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100 +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" +CONFIG_LOGLEVEL=7 +CONFIG_SPL_MAX_SIZE=0xc +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a0 +CONFIG_SPL_BSS_MAX_SIZE=0x8 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x28 +CONFIG_SPL_THERMAL=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=64 +CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_UFS=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_UBI=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_OF_LIST="k3-j784s4-evm k3-am69-sk" +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_CCF=y +CONFIG_CLK_TI_SCI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x4 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x80 +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_MULTIPLEXER=y +CONFIG_MUX_MMIO=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_FIXED=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y +CONFIG_PHY_CADENCE_TORRENT=y +CONFIG_PHY_J721E_WIZ=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_REMOTEPROC_TI_K3_DSP=y +CONFIG_REMOTEPROC_TI_K3_R5F=y +CONFIG_RESET_TI_SCI=y
[PATCH v5 13/17] arm: dts: Introduce am69-sk u-boot dts files
From: Dasnavis Sabiya
Introduce the base dts files needed for u-boot or to augment the linux
dtbs for use in the u-boot-spl and u-boot binaries.
Signed-off-by: Dasnavis Sabiya
Signed-off-by: Apurva Nandan
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/k3-am69-r5-sk.dts | 105
arch/arm/dts/k3-am69-sk-u-boot.dtsi | 25 +++
arch/arm/dts/k3-j784s4-binman.dtsi | 89 +++
4 files changed, 220 insertions(+)
create mode 100644 arch/arm/dts/k3-am69-r5-sk.dts
create mode 100644 arch/arm/dts/k3-am69-sk-u-boot.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b73f8a9230..d966869779 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1409,6 +1409,7 @@ dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\
k3-j721s2-common-proc-board.dtb\
k3-j721s2-r5-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-sk.dtb\
+ k3-am69-r5-sk.dtb\
k3-j784s4-evm.dtb\
k3-j784s4-r5-evm.dtb
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
diff --git a/arch/arm/dts/k3-am69-r5-sk.dts b/arch/arm/dts/k3-am69-r5-sk.dts
new file mode 100644
index 00..d2e73bd1bf
--- /dev/null
+++ b/arch/arm/dts/k3-am69-r5-sk.dts
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am69-sk.dts"
+#include "k3-j784s4-ddr-evm-lp4-4266.dtsi"
+#include "k3-j784s4-ddr.dtsi"
+#include "k3-am69-sk-u-boot.dtsi"
+
+/ {
+ chosen {
+ tick-timer = _timer0;
+ };
+
+ aliases {
+ remoteproc0 =
+ remoteproc1 = _0;
+ };
+
+ a72_0: a72@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x0 0x00a9 0x0 0x10>;
+ power-domains = <_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <_pds 202 TI_SCI_PD_EXCLUSIVE>;
+ resets = <_reset 202 0>;
+ clocks = <_clks 61 0>;
+ assigned-clocks = <_clks 61 0>, <_clks 202 0>;
+ assigned-clock-parents = <_clks 61 2>;
+ assigned-clock-rates = <2>, <20>;
+ ti,sci = <>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ bootph-pre-ram;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <_proxy_mcu 21>, <_proxy_mcu 23>;
+ bootph-pre-ram;
+ };
+};
+
+_timer0 {
+ status = "okay";
+ clock-frequency = <25000>;
+ bootph-pre-ram;
+};
+
+_proxy_sa3 {
+ status = "okay";
+ bootph-pre-ram;
+};
+
+_proxy_mcu {
+ status = "okay";
+ bootph-pre-ram;
+};
+
+_mcu_wakeup {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <_proxy_mcu 4>,
+ <_proxy_mcu 5>,
+ <_proxy_sa3 5>;
+ mbox-names = "tx", "rx", "boot_notify";
+ bootph-pre-ram;
+ };
+};
+
+ {
+ mboxes= <_proxy_mcu 8>, <_proxy_mcu 6>,
<_proxy_mcu 5>;
+ mbox-names = "tx", "rx", "notify";
+ ti,host-id = <4>;
+ ti,secure-host;
+ bootph-pre-ram;
+};
+
+_uart0 {
+ bootph-pre-ram;
+ status = "okay";
+};
+
+ {
+ reg = <0x0 0x4704 0x0 0x100>,
+ <0x0 0x5000 0x0 0x800>;
+};
+
+ {
+ reg = <0x0 0x4705 0x0 0x100>,
+ <0x0 0x5800 0x0 0x800>;
+};
+
+_ringacc {
+ ti,sci = <_tifs>;
+};
+
+_udmap {
+ ti,sci = <_tifs>;
+};
diff --git a/arch/arm/dts/k3-am69-sk-u-boot.dtsi
b/arch/arm/dts/k3-am69-sk-u-boot.dtsi
new file mode 100644
index 00..d1623b6bbe
--- /dev/null
+++ b/arch/arm/dts/k3-am69-sk-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-j784s4-binman.dtsi"
+
+_udmap {
+ reg = <0x0 0x285c 0x0 0x100>,
+ <0x0 0x284c 0x0 0x4000>,
+ <0x0 0x2a80 0x0 0x4>,
+ <0x0 0x284a 0x0 0x4000>,
+ <0x0 0x2aa0 0x0 0x4>,
+ <0x0 0x2840 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
+ bootph-pre-ram;
+};
+
+ {
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ bootph-pre-ram;
+ };
+};
diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi
b/arch/arm/dts/k3-j784s4-binman.dtsi
index 7349c2ba38..cb699424b9 100644
---
[PATCH v5 11/17] board: ti: j784s4: Add boot environment variables
Add env file with necessary boot variables.
Signed-off-by: Apurva Nandan
---
board/ti/j784s4/j784s4.env | 19 +++
1 file changed, 19 insertions(+)
create mode 100644 board/ti/j784s4/j784s4.env
diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env
new file mode 100644
index 00..203122970b
--- /dev/null
+++ b/board/ti/j784s4/j784s4.env
@@ -0,0 +1,19 @@
+#include
+#include
+#include
+#include
+#include
+
+name_kern=Image
+console=ttyS2,115200n8
+args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x0288
+ ${mtdparts}
+run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+
+boot_targets=mmc1 mmc0 usb pxe dhcp
+boot=mmc
+mmcdev=1
+bootpart=1:2
+bootdir=/boot
+rd_spec=-
+
--
2.34.1
[PATCH v5 09/17] board: ti: j784s4: Add board support for J784S4 EVM
Add board files for J784S4 EVM.
Signed-off-by: Hari Nagalla
[ add env and board specific yaml files for binman ]
Signed-off-by: Neha Malcom Francis
[ cleaned up the env files ]
Signed-off-by: Manorit Chawdhry
Signed-off-by: Dasnavis Sabiya
Signed-off-by: Apurva Nandan
---
arch/arm/mach-k3/Kconfig| 1 +
arch/arm/mach-k3/j784s4/Kconfig | 35 ++
board/ti/j784s4/Makefile| 7 ++
board/ti/j784s4/evm.c | 38 +
include/configs/j784s4_evm.h| 20 +
5 files changed, 101 insertions(+)
create mode 100644 arch/arm/mach-k3/j784s4/Kconfig
create mode 100644 board/ti/j784s4/Makefile
create mode 100644 board/ti/j784s4/evm.c
create mode 100644 include/configs/j784s4_evm.h
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 150d0bfa14..445b49e245 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -157,5 +157,6 @@ source "arch/arm/mach-k3/am62x/Kconfig"
source "arch/arm/mach-k3/am62ax/Kconfig"
source "arch/arm/mach-k3/j721e/Kconfig"
source "arch/arm/mach-k3/j721s2/Kconfig"
+source "arch/arm/mach-k3/j784s4/Kconfig"
endif
diff --git a/arch/arm/mach-k3/j784s4/Kconfig b/arch/arm/mach-k3/j784s4/Kconfig
new file mode 100644
index 00..03d3f91371
--- /dev/null
+++ b/arch/arm/mach-k3/j784s4/Kconfig
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Hari Nagalla
+
+if SOC_K3_J784S4
+
+choice
+ prompt "K3 J784S4 board"
+ optional
+
+config TARGET_J784S4_A72_EVM
+ bool "TI K3 based J784S4 EVM running on A72"
+ select ARM64
+ select BOARD_LATE_INIT
+ select SYS_DISABLE_DCACHE_OPS
+ select BINMAN
+
+config TARGET_J784S4_R5_EVM
+ bool "TI K3 based J784S4 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+
+endchoice
+
+source "board/ti/j784s4/Kconfig"
+
+endif
+
diff --git a/board/ti/j784s4/Makefile b/board/ti/j784s4/Makefile
new file mode 100644
index 00..3fc70eb8fb
--- /dev/null
+++ b/board/ti/j784s4/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Hari Nagalla
+#
+
+obj-y += evm.o
diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c
new file mode 100644
index 00..4857c9d2f6
--- /dev/null
+++ b/board/ti/j784s4/evm.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Board specific initialization for J784S4 EVM
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Hari Nagalla
+ *
+ */
+
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+void spl_board_init(void)
+{
+}
diff --git a/include/configs/j784s4_evm.h b/include/configs/j784s4_evm.h
new file mode 100644
index 00..1b780134ca
--- /dev/null
+++ b/include/configs/j784s4_evm.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Configuration header file for K3 J784S4 EVM
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Hari Nagalla
+ */
+
+#ifndef __CONFIG_J784S4_EVM_H
+#define __CONFIG_J784S4_EVM_H
+
+#include
+
+/* DDR Configuration */
+#define CFG_SYS_SDRAM_BASE10x88000
+
+/* Now for the remaining common defines */
+#include
+
+#endif /* __CONFIG_J784S4_EVM_H */
--
2.34.1
[PATCH v5 08/17] drivers: dma: Add support for J784S4 SoC
Add support for DMA in J784S4 SoC.
Signed-off-by: Jayesh Choudhary
Signed-off-by: Hari Nagalla
Signed-off-by: Apurva Nandan
---
drivers/dma/ti/Makefile | 1 +
drivers/dma/ti/k3-psil-j784s4.c | 166 ++
drivers/dma/ti/k3-psil-priv.h | 1 +
drivers/dma/ti/k3-psil.c | 2 +
drivers/firmware/ti_sci_static_data.h | 34 ++
drivers/ram/Kconfig | 2 +-
6 files changed, 205 insertions(+), 1 deletion(-)
create mode 100644 drivers/dma/ti/k3-psil-j784s4.c
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index f4e0271efb..9e0b13e8c0 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -9,3 +9,4 @@ k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o
k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o
k3-psil-data-$(CONFIG_SOC_K3_AM62A7) += k3-psil-am62a.o
+k3-psil-data-$(CONFIG_SOC_K3_J784S4) += k3-psil-j784s4.o
diff --git a/drivers/dma/ti/k3-psil-j784s4.c b/drivers/dma/ti/k3-psil-j784s4.c
new file mode 100644
index 00..7f06a1f307
--- /dev/null
+++ b/drivers/dma/ti/k3-psil-j784s4.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com
+ */
+#include
+
+#include "k3-psil-priv.h"
+
+#define PSIL_PDMA_XY_TR(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ }, \
+ }
+
+#define PSIL_PDMA_XY_PKT(x)\
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .pkt_mode = 1, \
+ }, \
+ }
+
+#define PSIL_PDMA_MCASP(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .pdma_acc32 = 1,\
+ .pdma_burst = 1,\
+ }, \
+ }
+
+#define PSIL_ETHERNET(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1,\
+ .psd_size = 16, \
+ }, \
+ }
+
+#define PSIL_SA2UL(x, tx) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1,\
+ .psd_size = 64, \
+ .notdpkt = tx, \
+ }, \
+ }
+
+/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
+static struct psil_ep j784s4_src_ep_map[] = {
+ /* PDMA_MCASP - McASP0-4 */
+ PSIL_PDMA_MCASP(0x4400),
+ PSIL_PDMA_MCASP(0x4401),
+ PSIL_PDMA_MCASP(0x4402),
+ PSIL_PDMA_MCASP(0x4403),
+ PSIL_PDMA_MCASP(0x4404),
+ /* PDMA_SPI_G0 - SPI0-3 */
+ PSIL_PDMA_XY_PKT(0x4600),
+ PSIL_PDMA_XY_PKT(0x4601),
+ PSIL_PDMA_XY_PKT(0x4602),
+ PSIL_PDMA_XY_PKT(0x4603),
+ PSIL_PDMA_XY_PKT(0x4604),
+ PSIL_PDMA_XY_PKT(0x4605),
+ PSIL_PDMA_XY_PKT(0x4606),
+ PSIL_PDMA_XY_PKT(0x4607),
+ PSIL_PDMA_XY_PKT(0x4608),
+ PSIL_PDMA_XY_PKT(0x4609),
+ PSIL_PDMA_XY_PKT(0x460a),
+ PSIL_PDMA_XY_PKT(0x460b),
+ PSIL_PDMA_XY_PKT(0x460c),
+ PSIL_PDMA_XY_PKT(0x460d),
+ PSIL_PDMA_XY_PKT(0x460e),
+ PSIL_PDMA_XY_PKT(0x460f),
+ /* PDMA_SPI_G1 - SPI4-7 */
+ PSIL_PDMA_XY_PKT(0x4610),
+ PSIL_PDMA_XY_PKT(0x4611),
+ PSIL_PDMA_XY_PKT(0x4612),
+ PSIL_PDMA_XY_PKT(0x4613),
+ PSIL_PDMA_XY_PKT(0x4614),
+ PSIL_PDMA_XY_PKT(0x4615),
+ PSIL_PDMA_XY_PKT(0x4616),
+ PSIL_PDMA_XY_PKT(0x4617),
+ PSIL_PDMA_XY_PKT(0x4618),
+
[PATCH v5 07/17] arm: mach-k3: j784s4: Add clk and power support
Add clk and device data which can be used by respective drivers
to configure clocks and PSC.
Signed-off-by: Hari Nagalla
Signed-off-by: Apurva Nandan
---
arch/arm/mach-k3/r5/j784s4/Makefile| 7 +
arch/arm/mach-k3/r5/j784s4/clk-data.c | 428 +
arch/arm/mach-k3/r5/j784s4/dev-data.c | 98 ++
drivers/clk/ti/clk-k3.c| 6 +
drivers/power/domain/ti-power-domain.c | 6 +
include/k3-clk.h | 1 +
include/k3-dev.h | 1 +
7 files changed, 547 insertions(+)
create mode 100644 arch/arm/mach-k3/r5/j784s4/Makefile
create mode 100644 arch/arm/mach-k3/r5/j784s4/clk-data.c
create mode 100644 arch/arm/mach-k3/r5/j784s4/dev-data.c
diff --git a/arch/arm/mach-k3/r5/j784s4/Makefile
b/arch/arm/mach-k3/r5/j784s4/Makefile
new file mode 100644
index 00..23e1ce51ac
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j784s4/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c
b/arch/arm/mach-k3/r5/j784s4/clk-data.c
new file mode 100644
index 00..d3fac38dd6
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c
@@ -0,0 +1,428 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * J784S4 specific clock platform data
+ *
+ * This file is auto generated. Please do not hand edit and report any issues
+ * to Bryan Brattlof .
+ *
+ * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+ "osc_19_2_mhz",
+ "osc_20_mhz",
+ "osc_24_mhz",
+ "osc_25_mhz",
+ "osc_26_mhz",
+ "osc_27_mhz",
+};
+
+static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
+ "board_0_mcu_ospi0_dqs_out",
+ "fss_mcu_0_ospi_0_ospi_oclk_clk",
+};
+
+static const char * const mcu_ospi1_iclk_sel_out0_parents[] = {
+ "board_0_mcu_ospi1_dqs_out",
+ "fss_mcu_0_ospi_1_ospi_oclk_clk",
+};
+
+static const char * const wkup_fref_clksel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
+ "wkup_fref_clksel_out0",
+ "hsdiv1_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout4_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout4_clk",
+};
+
+static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout4_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout4_clk",
+};
+
+static const char * const wkup_gpio0_clksel_out0_parents[] = {
+ "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+ "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+ "j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
+ "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const mcu_usart_clksel_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+ "postdiv3_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_i2c_mcupll_bypass_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+ "gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out1_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out12_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out19_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out2_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out26_0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out27_0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out28_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out3_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out7_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out8_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const
[PATCH v5 06/17] soc: ti: k3-socinfo: Add entry for J784S4 SoC
Add support for J784S4 SoC Identification. Signed-off-by: Hari Nagalla Signed-off-by: Apurva Nandan --- arch/arm/mach-k3/include/mach/hardware.h | 1 + drivers/soc/soc_ti_k3.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 7e143c6bdc..74692b745a 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -50,6 +50,7 @@ #define JTAG_ID_PARTNO_J7200 0xbb6d #define JTAG_ID_PARTNO_J721E 0xbb64 #define JTAG_ID_PARTNO_J721S2 0xbb75 +#define JTAG_ID_PARTNO_J784S4 0xbb80 #define K3_SOC_ID(id, ID) \ static inline bool soc_is_##id(void) \ diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c index 355a5368dd..d176980915 100644 --- a/drivers/soc/soc_ti_k3.c +++ b/drivers/soc/soc_ti_k3.c @@ -45,6 +45,9 @@ static const char *get_family_string(u32 idreg) case JTAG_ID_PARTNO_AM62AX: family = "AM62AX"; break; + case JTAG_ID_PARTNO_J784S4: + family = "J784S4"; + break; default: family = "Unknown Silicon"; }; -- 2.34.1
