Re: [PATCH v4] board: phytec: phycore-imx93: Add phyBOARD-Segin-i.MX93 support
On Tue, 2024-01-30 at 15:50 +0100, Mathieu Othacehe wrote: > Add initial support for the PHYTEC phyBOARD-Segin-i.MX93 board based on > the PHYTEC phyCORE-i.MX93 SoM. > > Supported features: > - 1GB LPDDR4 RAM > - eMMC > - external SD > - FEC Ethernet > - debug UART > - watchdog > > Signed-off-by: Mathieu Othacehe Reviewed-by: Yannic Moog > --- > Hello, > > This new revision fixes the remarks of Primoz. The configuration is now > aligned on the savedefconfig output. The FEC Ethernet is also tested to be > working if this patch is in: > > https://patchwork.ozlabs.org/project/uboot/patch/20240130124337.497748-1-primoz.fi...@norik.com/ > > The proposed patch has been rebased on top of 6faba41. > > Thanks, > > Mathieu > > v3: https://lists.denx.de/pipermail/u-boot/2024-January/544493.html > > arch/arm/dts/Makefile | 3 +- > arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi | 293 > arch/arm/dts/imx93-phyboard-segin.dts | 117 ++ > arch/arm/dts/imx93-phycore-som.dtsi | 126 ++ > arch/arm/mach-imx/imx9/Kconfig | 6 + > board/phytec/phycore_imx93/Kconfig | 13 + > board/phytec/phycore_imx93/MAINTAINERS | 10 + > board/phytec/phycore_imx93/Makefile | 14 + > board/phytec/phycore_imx93/lpddr4_timing.c | 1546 + > board/phytec/phycore_imx93/phycore-imx93.c | 42 + > board/phytec/phycore_imx93/phycore_imx93.env | 73 + > board/phytec/phycore_imx93/spl.c | 148 ++ > configs/imx93-phyboard-segin_defconfig | 138 ++ > doc/board/phytec/imx93-phyboard-segin.rst | 61 + > doc/board/phytec/index.rst | 1 + > include/configs/phycore_imx93.h | 28 + > 16 files changed, 2618 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi > create mode 100644 arch/arm/dts/imx93-phyboard-segin.dts > create mode 100644 arch/arm/dts/imx93-phycore-som.dtsi > create mode 100644 board/phytec/phycore_imx93/Kconfig > create mode 100644 board/phytec/phycore_imx93/MAINTAINERS > create mode 100644 board/phytec/phycore_imx93/Makefile > create mode 100644 board/phytec/phycore_imx93/lpddr4_timing.c > create mode 100644 board/phytec/phycore_imx93/phycore-imx93.c > create mode 100644 board/phytec/phycore_imx93/phycore_imx93.env > create mode 100644 board/phytec/phycore_imx93/spl.c > create mode 100644 configs/imx93-phyboard-segin_defconfig > create mode 100644 doc/board/phytec/imx93-phyboard-segin.rst > create mode 100644 include/configs/phycore_imx93.h > >
Re: [PATCH 3/3] rockchip: rk3588: Enable eMMC HS200 mode
On Sat, Jan 27, 2024 at 7:27 AM Jonas Karlman wrote: > > Writing to eMMC using HS200 mode work more reliably then other modes on > RK3588 boards. > > Enable MMC_HS200_SUPPORT Kconfig option to prefer use of HS200 mode. > > Signed-off-by: Jonas Karlman Reviewed-by: Weizhao Ouyang BR, Weizhao > --- > configs/evb-rk3588_defconfig | 2 ++ > configs/nanopc-t6-rk3588_defconfig | 2 ++ > configs/neu6a-io-rk3588_defconfig| 2 ++ > configs/neu6b-io-rk3588_defconfig| 2 ++ > configs/orangepi-5-plus-rk3588_defconfig | 2 ++ > configs/quartzpro64-rk3588_defconfig | 2 ++ > configs/rock5a-rk3588s_defconfig | 2 ++ > configs/rock5b-rk3588_defconfig | 2 ++ > configs/turing-rk1-rk3588_defconfig | 2 ++ > 9 files changed, 18 insertions(+) > > diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig > index 0b7b4f2f627a..2dfdc71259f7 100644 > --- a/configs/evb-rk3588_defconfig > +++ b/configs/evb-rk3588_defconfig > @@ -53,6 +53,8 @@ CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_MISC=y > CONFIG_SUPPORT_EMMC_RPMB=y > +CONFIG_MMC_HS200_SUPPORT=y > +CONFIG_SPL_MMC_HS200_SUPPORT=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_MMC_SDHCI=y > diff --git a/configs/nanopc-t6-rk3588_defconfig > b/configs/nanopc-t6-rk3588_defconfig > index 760993220929..26dcf3aae21c 100644 > --- a/configs/nanopc-t6-rk3588_defconfig > +++ b/configs/nanopc-t6-rk3588_defconfig > @@ -66,6 +66,8 @@ CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_MISC=y > CONFIG_SUPPORT_EMMC_RPMB=y > +CONFIG_MMC_HS200_SUPPORT=y > +CONFIG_SPL_MMC_HS200_SUPPORT=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_MMC_SDHCI=y > diff --git a/configs/neu6a-io-rk3588_defconfig > b/configs/neu6a-io-rk3588_defconfig > index d5301c630b2a..a6549420c01e 100644 > --- a/configs/neu6a-io-rk3588_defconfig > +++ b/configs/neu6a-io-rk3588_defconfig > @@ -48,6 +48,8 @@ CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_MISC=y > CONFIG_SUPPORT_EMMC_RPMB=y > +CONFIG_MMC_HS200_SUPPORT=y > +CONFIG_SPL_MMC_HS200_SUPPORT=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_MMC_SDHCI=y > diff --git a/configs/neu6b-io-rk3588_defconfig > b/configs/neu6b-io-rk3588_defconfig > index b13c9b5db1b0..b5739de147d8 100644 > --- a/configs/neu6b-io-rk3588_defconfig > +++ b/configs/neu6b-io-rk3588_defconfig > @@ -48,6 +48,8 @@ CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_MISC=y > CONFIG_SUPPORT_EMMC_RPMB=y > +CONFIG_MMC_HS200_SUPPORT=y > +CONFIG_SPL_MMC_HS200_SUPPORT=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_MMC_SDHCI=y > diff --git a/configs/orangepi-5-plus-rk3588_defconfig > b/configs/orangepi-5-plus-rk3588_defconfig > index a58f96d57798..e5325158d2af 100644 > --- a/configs/orangepi-5-plus-rk3588_defconfig > +++ b/configs/orangepi-5-plus-rk3588_defconfig > @@ -69,6 +69,8 @@ CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_MISC=y > CONFIG_SUPPORT_EMMC_RPMB=y > +CONFIG_MMC_HS200_SUPPORT=y > +CONFIG_SPL_MMC_HS200_SUPPORT=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_MMC_SDHCI=y > diff --git a/configs/quartzpro64-rk3588_defconfig > b/configs/quartzpro64-rk3588_defconfig > index 85af4c4ff955..fd8304debdbb 100644 > --- a/configs/quartzpro64-rk3588_defconfig > +++ b/configs/quartzpro64-rk3588_defconfig > @@ -53,6 +53,8 @@ CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_MISC=y > CONFIG_SUPPORT_EMMC_RPMB=y > +CONFIG_MMC_HS200_SUPPORT=y > +CONFIG_SPL_MMC_HS200_SUPPORT=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_MMC_SDHCI=y > diff --git a/configs/rock5a-rk3588s_defconfig > b/configs/rock5a-rk3588s_defconfig > index efa7bcbdcda6..10d6f6580490 100644 > --- a/configs/rock5a-rk3588s_defconfig > +++ b/configs/rock5a-rk3588s_defconfig > @@ -56,6 +56,8 @@ CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_MISC=y > CONFIG_SUPPORT_EMMC_RPMB=y > +CONFIG_MMC_HS200_SUPPORT=y > +CONFIG_SPL_MMC_HS200_SUPPORT=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_MMC_SDHCI=y > diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig > index a0678ff1290c..76f57340df5a 100644 > --- a/configs/rock5b-rk3588_defconfig > +++ b/configs/rock5b-rk3588_defconfig > @@ -71,6 +71,8 @@ CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_MISC=y > CONFIG_SUPPORT_EMMC_RPMB=y > +CONFIG_MMC_HS200_SUPPORT=y > +CONFIG_SPL_MMC_HS200_SUPPORT=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_MMC_SDHCI=y > diff --git a/configs/turing-rk1-rk3588_defconfig > b/configs/turing-rk1-rk3588_defconfig > index 289f2da775c5..0d6c34d468e3 100644 > --- a/configs/turing-rk1-rk3588_defconfig > +++ b/configs/turing-rk1-rk3588_defconfig > @@ -75,6 +75,8 @@ CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_MISC=y > CONFIG_SUPPORT_EMMC_RPMB=y > +CONFIG_MMC_HS200_SUPPORT=y > +CONFIG_SPL_MMC_HS200_SUPPORT=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y >
Re: [PATCH 2/3] rockchip: rk356x: Enable eMMC HS200 mode
On Sat, Jan 27, 2024 at 10:32 AM Jonas Karlman wrote: > > Writing to eMMC using HS200 mode work more reliably then other modes on > RK356x boards. > > Enable MMC_HS200_SUPPORT Kconfig option to prefer use of HS200 mode. > > Signed-off-by: Jonas Karlman Reviewed-by: Weizhao Ouyang BR, Weizhao > --- > configs/anbernic-rgxx3-rk3566_defconfig | 2 ++ > configs/bpi-r2-pro-rk3568_defconfig | 2 ++ > configs/evb-rk3568_defconfig | 2 ++ > configs/lubancat-2-rk3568_defconfig | 2 ++ > configs/odroid-m1-rk3568_defconfig| 2 ++ > configs/quartz64-a-rk3566_defconfig | 2 ++ > configs/quartz64-b-rk3566_defconfig | 2 ++ > configs/radxa-cm3-io-rk3566_defconfig | 2 ++ > configs/rock-3a-rk3568_defconfig | 2 ++ > configs/soquartz-blade-rk3566_defconfig | 2 ++ > configs/soquartz-cm4-rk3566_defconfig | 2 ++ > configs/soquartz-model-a-rk3566_defconfig | 2 ++ > 12 files changed, 24 insertions(+) > > diff --git a/configs/anbernic-rgxx3-rk3566_defconfig > b/configs/anbernic-rgxx3-rk3566_defconfig > index ed6643d9d4fa..295c0bd3fc61 100644 > --- a/configs/anbernic-rgxx3-rk3566_defconfig > +++ b/configs/anbernic-rgxx3-rk3566_defconfig > @@ -61,6 +61,8 @@ CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_MISC=y > CONFIG_SUPPORT_EMMC_RPMB=y > +CONFIG_MMC_HS200_SUPPORT=y > +CONFIG_SPL_MMC_HS200_SUPPORT=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_MMC_SDHCI=y > diff --git a/configs/bpi-r2-pro-rk3568_defconfig > b/configs/bpi-r2-pro-rk3568_defconfig > index e6e0e6fc6fa6..c9e1cd2c2c85 100644 > --- a/configs/bpi-r2-pro-rk3568_defconfig > +++ b/configs/bpi-r2-pro-rk3568_defconfig > @@ -60,6 +60,8 @@ CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_MISC=y > CONFIG_SUPPORT_EMMC_RPMB=y > CONFIG_SUPPORT_EMMC_BOOT=y > +CONFIG_MMC_HS200_SUPPORT=y > +CONFIG_SPL_MMC_HS200_SUPPORT=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_MMC_SDHCI=y > diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig > index cb9b87ff12cb..19eab9bf00ac 100644 > --- a/configs/evb-rk3568_defconfig > +++ b/configs/evb-rk3568_defconfig > @@ -54,6 +54,8 @@ CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_MISC=y > CONFIG_SUPPORT_EMMC_RPMB=y > +CONFIG_MMC_HS200_SUPPORT=y > +CONFIG_SPL_MMC_HS200_SUPPORT=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_MMC_SDHCI=y > diff --git a/configs/lubancat-2-rk3568_defconfig > b/configs/lubancat-2-rk3568_defconfig > index 80ae6ec3a2e9..c06a447fda26 100644 > --- a/configs/lubancat-2-rk3568_defconfig > +++ b/configs/lubancat-2-rk3568_defconfig > @@ -55,6 +55,8 @@ CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_MISC=y > CONFIG_SUPPORT_EMMC_RPMB=y > +CONFIG_MMC_HS200_SUPPORT=y > +CONFIG_SPL_MMC_HS200_SUPPORT=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_MMC_SDHCI=y > diff --git a/configs/odroid-m1-rk3568_defconfig > b/configs/odroid-m1-rk3568_defconfig > index 3130e341e776..7fed6e7da597 100644 > --- a/configs/odroid-m1-rk3568_defconfig > +++ b/configs/odroid-m1-rk3568_defconfig > @@ -72,6 +72,8 @@ CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_MISC=y > CONFIG_SUPPORT_EMMC_RPMB=y > +CONFIG_MMC_HS200_SUPPORT=y > +CONFIG_SPL_MMC_HS200_SUPPORT=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_MMC_SDHCI=y > diff --git a/configs/quartz64-a-rk3566_defconfig > b/configs/quartz64-a-rk3566_defconfig > index ade08867f60f..fd6b0e528834 100644 > --- a/configs/quartz64-a-rk3566_defconfig > +++ b/configs/quartz64-a-rk3566_defconfig > @@ -71,6 +71,8 @@ CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_MISC=y > CONFIG_SUPPORT_EMMC_RPMB=y > +CONFIG_MMC_HS200_SUPPORT=y > +CONFIG_SPL_MMC_HS200_SUPPORT=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_MMC_SDHCI=y > diff --git a/configs/quartz64-b-rk3566_defconfig > b/configs/quartz64-b-rk3566_defconfig > index 8d01db54407d..ec7a677fd3d3 100644 > --- a/configs/quartz64-b-rk3566_defconfig > +++ b/configs/quartz64-b-rk3566_defconfig > @@ -69,6 +69,8 @@ CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_MISC=y > CONFIG_SUPPORT_EMMC_RPMB=y > +CONFIG_MMC_HS200_SUPPORT=y > +CONFIG_SPL_MMC_HS200_SUPPORT=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_MMC_SDHCI=y > diff --git a/configs/radxa-cm3-io-rk3566_defconfig > b/configs/radxa-cm3-io-rk3566_defconfig > index 4b606dcb8e94..10626acfdea2 100644 > --- a/configs/radxa-cm3-io-rk3566_defconfig > +++ b/configs/radxa-cm3-io-rk3566_defconfig > @@ -55,6 +55,8 @@ CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_MISC=y > CONFIG_SUPPORT_EMMC_RPMB=y > +CONFIG_MMC_HS200_SUPPORT=y > +CONFIG_SPL_MMC_HS200_SUPPORT=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_MMC_SDHCI=y > diff --git a/configs/rock-3a-rk3568_defconfig > b/configs/rock-3a-rk3568_defconfig > index 18372a570eb7..2b944163f5a9 100644 > --- a/configs/rock-3a-rk3568_defconfig > +++ b/configs/rock-3a-rk3568_defconfig > @@ -68,6 +68,8 @@
Re: [PATCH v4] board: phytec: phycore-imx93: Add phyBOARD-Segin-i.MX93 support
Hi Mathieu, Thanks for v4. I have no more remarks. Also tested your v4 on the board. Everything works, even eMMC booting which you were not able to test. With that my Tested-by: can be applied. Tested-by: Primoz Fiser BR, Primoz On 30. 01. 24 15:50, Mathieu Othacehe wrote: > Add initial support for the PHYTEC phyBOARD-Segin-i.MX93 board based on > the PHYTEC phyCORE-i.MX93 SoM. > > Supported features: > - 1GB LPDDR4 RAM > - eMMC > - external SD > - FEC Ethernet > - debug UART > - watchdog > > Signed-off-by: Mathieu Othacehe > --- > Hello, > > This new revision fixes the remarks of Primoz. The configuration is now > aligned on the savedefconfig output. The FEC Ethernet is also tested to be > working if this patch is in: > > https://patchwork.ozlabs.org/project/uboot/patch/20240130124337.497748-1-primoz.fi...@norik.com/ > > The proposed patch has been rebased on top of 6faba41. > > Thanks, > > Mathieu > > v3: https://lists.denx.de/pipermail/u-boot/2024-January/544493.html > > arch/arm/dts/Makefile |3 +- > arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi | 293 > arch/arm/dts/imx93-phyboard-segin.dts | 117 ++ > arch/arm/dts/imx93-phycore-som.dtsi | 126 ++ > arch/arm/mach-imx/imx9/Kconfig|6 + > board/phytec/phycore_imx93/Kconfig| 13 + > board/phytec/phycore_imx93/MAINTAINERS| 10 + > board/phytec/phycore_imx93/Makefile | 14 + > board/phytec/phycore_imx93/lpddr4_timing.c| 1546 + > board/phytec/phycore_imx93/phycore-imx93.c| 42 + > board/phytec/phycore_imx93/phycore_imx93.env | 73 + > board/phytec/phycore_imx93/spl.c | 148 ++ > configs/imx93-phyboard-segin_defconfig| 138 ++ > doc/board/phytec/imx93-phyboard-segin.rst | 61 + > doc/board/phytec/index.rst|1 + > include/configs/phycore_imx93.h | 28 + > 16 files changed, 2618 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi > create mode 100644 arch/arm/dts/imx93-phyboard-segin.dts > create mode 100644 arch/arm/dts/imx93-phycore-som.dtsi > create mode 100644 board/phytec/phycore_imx93/Kconfig > create mode 100644 board/phytec/phycore_imx93/MAINTAINERS > create mode 100644 board/phytec/phycore_imx93/Makefile > create mode 100644 board/phytec/phycore_imx93/lpddr4_timing.c > create mode 100644 board/phytec/phycore_imx93/phycore-imx93.c > create mode 100644 board/phytec/phycore_imx93/phycore_imx93.env > create mode 100644 board/phytec/phycore_imx93/spl.c > create mode 100644 configs/imx93-phyboard-segin_defconfig > create mode 100644 doc/board/phytec/imx93-phyboard-segin.rst > create mode 100644 include/configs/phycore_imx93.h >
Re: [PATCH 06/18] rockchip: pine64: pinebook: migrate to rockchip_early_misc_init_r
Hello Kever and Quentin,
On 2024-02-01 03:48, Kever Yang wrote:
On 2024/1/23 22:49, Quentin Schulz wrote:
From: Quentin Schulz
Compared to the original misc_init_r from Rockchip mach code,
setup_iodomain() is added and rockchip_setup_macaddr() is not called.
It is assumed adding rockchip_setup_macaddr() back is fine.
Let's use rockchip_early_misc_init_r instead of reimplementing the
whole
misc_init_r from Rockchip (the side effect being that
rockchip_setup_macaddr() is back).
We might actually introduce some issues with this change. I'll get
back later with a more detailed explanation, together with a proposed
fix, after I check it all in detail.
This applies to some other patches in this series as well.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c | 18
++
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
index 4ad780767ea..2408a367305 100644
--- a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
+++ b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
@@ -11,7 +11,6 @@
#include
#include
#include
-#include
#include
#include
@@ -54,23 +53,10 @@ static void setup_iodomain(void)
rk_setreg(>soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
}
-int misc_init_r(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
setup_iodomain();
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length,
cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- return ret;
+ return 0;
}
#endif
Re: [PATCH] rockchip: rk3588-quartzpro64: Enable AHCI, PCI and USB
On 2024/1/27 07:39, Jonas Karlman wrote: Enable Kconfig options to support AHCI, PCI and USB features. This help keep rk3588-quartzpro64 in sync with other RK3588 boards. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Thanks, - Kever --- Please note that this has not been runtime tested, this enables features that are defines in the device tree and work on other RK3588 boards. This patch may depend on the series "rockchip: rk35xx: Sync device tree with linux v6.8-rc1" [1]. [1] https://patchwork.ozlabs.org/cover/1891669/ --- configs/quartzpro64-rk3588_defconfig | 25 + 1 file changed, 25 insertions(+) diff --git a/configs/quartzpro64-rk3588_defconfig b/configs/quartzpro64-rk3588_defconfig index fd8304debdbb..bbbd2770f364 100644 --- a/configs/quartzpro64-rk3588_defconfig +++ b/configs/quartzpro64-rk3588_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x00a0 @@ -18,7 +19,9 @@ CONFIG_SPL_STACK=0x40 CONFIG_DEBUG_UART_BASE=0xFEB5 CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y @@ -39,15 +42,21 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -63,11 +72,27 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_PHY_REALTEK=y CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y +CONFIG_SCSI=y CONFIG_BAUDRATE=150 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_ERRNO_STR=y
Re: [PATCH v2 5/6] rockchip: rv1126: select SPL_OPTEE_IMAGE
On 2024/1/24 11:26, Tim Lunn wrote: rv1126 requires OPTEE as it provides pcsi support. Mainline Linux kernel will fail to boot without this. Select SPL_OPTEE_IMAGE when building FIT image. TEE must be provided when building. Signed-off-by: Tim Lunn Reviewed-by: Kever Yang Thanks, - Kever --- (no changes since v1) arch/arm/mach-rockchip/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6ff0aa6911..cce118a004 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -359,6 +359,7 @@ config ROCKCHIP_RV1126 select PMIC_RK8XX select BOARD_LATE_INIT imply ROCKCHIP_COMMON_BOARD + select SPL_OPTEE_IMAGE if SPL_FIT imply OF_LIBFDT_OVERLAY imply ROCKCHIP_OTP imply MISC_INIT_R
Re: [PATCH v2 6/6] rockchip: rv1126: Move RAM disk address
On 2024/1/24 11:26, Tim Lunn wrote: OPTEE gets loaded into a memory region overlapping with the ram disk. Fix the ramdisk address so it doesn't overlap with the OPTEE memory region. Signed-off-by: Tim Lunn Reviewed-by: Kever Yang Thanks, - Kever --- (no changes since v1) include/configs/rv1126_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/rv1126_common.h b/include/configs/rv1126_common.h index 168cd8b167..ea290f763c 100644 --- a/include/configs/rv1126_common.h +++ b/include/configs/rv1126_common.h @@ -26,7 +26,7 @@ "fdt_addr_r=0x0830\0" \ "fdtoverlay_addr_r=0x0200\0" \ "kernel_addr_r=0x02008000\0" \ - "ramdisk_addr_r=0x0a20\0" + "ramdisk_addr_r=0x0a40\0" #define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x0fff\0" \
Re: [PATCH v2 4/6] board: rockchip: Add Sonoff iHost board
On 2024/1/24 11:26, Tim Lunn wrote:
Sonoff iHost is gateway device designed to provide a Smart Home Hub,
it is based on Rockchip RV1126. There is also a version with 2GB RAM
based off the RV1109 dual core SoC however this works with the same
config as the RV1126 for uboot purposes.
Features:
- Rockchip RV1126
- 4GB DDR4
- 8GB eMMC
- microSD slot
- RMII Ethernet PHY
- 1x USB 2.0 Host
- 1x USB 2.0 OTG
- Realtek RTL8723DS WiFi/BT
- EFR32MG21 Silabs Zigbee radio
- Speaker/Microphone
Signed-off-by: Tim Lunn
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes in v2:
- Remove board config not required with standard boot
arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi | 13 +
arch/arm/mach-rockchip/rv1126/Kconfig| 8 +++
board/itead/sonoff-ihost/Kconfig | 16 ++
board/itead/sonoff-ihost/MAINTAINERS | 6 ++
configs/sonoff-ihost-rv1126_defconfig| 60
doc/board/rockchip/rockchip.rst | 1 +
include/configs/sonoff-ihost.h | 10
7 files changed, 114 insertions(+)
create mode 100644 arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi
create mode 100644 board/itead/sonoff-ihost/Kconfig
create mode 100644 board/itead/sonoff-ihost/MAINTAINERS
create mode 100644 configs/sonoff-ihost-rv1126_defconfig
create mode 100644 include/configs/sonoff-ihost.h
diff --git a/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi
b/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi
new file mode 100644
index 00..a625660d58
--- /dev/null
+++ b/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rv1126-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", ,
+ };
+};
+
+ {
+ status = "disabled";
+};
diff --git a/arch/arm/mach-rockchip/rv1126/Kconfig
b/arch/arm/mach-rockchip/rv1126/Kconfig
index a6e2b5903c..55b1112120 100644
--- a/arch/arm/mach-rockchip/rv1126/Kconfig
+++ b/arch/arm/mach-rockchip/rv1126/Kconfig
@@ -14,6 +14,13 @@ config TARGET_RV1126_NEU2
IO board and Neu2 needs to mount on top of this IO board in order to
create complete Edgeble Neural Compute Module 2(Neu2) IO platform.
+config TARGET_RV1126_SONOFF_IHOST
+ bool "Sonoff iHost smart home hub"
+ help
+ Sonoff iHost is a smart home gateway based on Rockchip RV1126 SoC.
+ It features Wifi, Bluetooth and Zigbee radios that are used by many
+ smart home devices.
+
config SOC_SPECIFIC_OPTIONS # dummy
def_bool y
select HAS_CUSTOM_SYS_INIT_SP_ADDR
@@ -58,5 +65,6 @@ config TEXT_BASE
default 0x60
source board/edgeble/neural-compute-module-2/Kconfig
+source board/itead/sonoff-ihost/Kconfig
endif
diff --git a/board/itead/sonoff-ihost/Kconfig b/board/itead/sonoff-ihost/Kconfig
new file mode 100644
index 00..30d9a6b3e6
--- /dev/null
+++ b/board/itead/sonoff-ihost/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_RV1126_SONOFF_IHOST
+
+config SYS_BOARD
+ default "sonoff-ihost"
+
+config SYS_VENDOR
+ default "itead"
+
+config SYS_CONFIG_NAME
+ default "sonoff-ihost"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select RAM_ROCKCHIP_DDR4
+
+endif
diff --git a/board/itead/sonoff-ihost/MAINTAINERS
b/board/itead/sonoff-ihost/MAINTAINERS
new file mode 100644
index 00..eff9274bea
--- /dev/null
+++ b/board/itead/sonoff-ihost/MAINTAINERS
@@ -0,0 +1,6 @@
+RV1126-SONOFF-IHOST
+M: Tim Lunn
+S: Maintained
+F: board/itead/sonoff-ihost
+F: include/configs/sonoff-ihost.h
+F: configs/sonoff-ihost-rv1126_defconfig
diff --git a/configs/sonoff-ihost-rv1126_defconfig
b/configs/sonoff-ihost-rv1126_defconfig
new file mode 100644
index 00..fe99bd92f9
--- /dev/null
+++ b/configs/sonoff-ihost-rv1126_defconfig
@@ -0,0 +1,60 @@
+CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_SYS_ARCH_TIMER=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="rv1126-sonoff-ihost"
+CONFIG_SYS_MONITOR_LEN=614400
+CONFIG_ROCKCHIP_RV1126=y
+CONFIG_TARGET_RV1126_SONOFF_IHOST=y
+CONFIG_DEBUG_UART_BASE=0xff57
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SYS_LOAD_ADDR=0xe00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_DEFAULT_FDT_FILE="rv1126-sonoff-ihost.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_NO_BSS_LIMIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
Re: [PATCH v2 3/6] rockchip: Convert rv1126 to standard boot
On 2024/1/24 11:25, Tim Lunn wrote: RV1126 soc appears to have been missed with the conversion of rockchip socs to standard boot. Remove remnants of distro boot for rv1126 common and the one existing board. Signed-off-by: Tim Lunn Link: https://lore.kernel.org/all/20230407223645.v8.8.I4cf7708a1ba953b9abd81375d93af34665c7b251@changeid/ Reviewed-by: Kever Yang Thanks, - Kever --- Changes in v2: - New patch to clean up distro boot from rv1126_common.h include/configs/neural-compute-module-2.h | 6 -- include/configs/rv1126_common.h | 3 +-- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/include/configs/neural-compute-module-2.h b/include/configs/neural-compute-module-2.h index f0934ae00c..43a560906a 100644 --- a/include/configs/neural-compute-module-2.h +++ b/include/configs/neural-compute-module-2.h @@ -12,10 +12,4 @@ #include -#undef BOOT_TARGET_DEVICES - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) - #endif /* __NEURAL_COMPUTE_MODULE_2_H */ diff --git a/include/configs/rv1126_common.h b/include/configs/rv1126_common.h index a64c0c6364..168cd8b167 100644 --- a/include/configs/rv1126_common.h +++ b/include/configs/rv1126_common.h @@ -28,7 +28,6 @@ "kernel_addr_r=0x02008000\0" \ "ramdisk_addr_r=0x0a20\0" -#include #define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x0fff\0" \ "initrd_high=0x0fff\0" \ @@ -36,6 +35,6 @@ "partitions=" PARTS_DEFAULT \ ENV_MEM_LAYOUT_SETTINGS \ ROCKCHIP_DEVICE_SETTINGS \ - BOOTENV + "boot_targets=" BOOT_TARGETS "\0" #endif /* __CONFIG_RV1126_COMMON_H */
Re: [PATCH v2 2/6] ram: rockchip: Add rv1126 ddr4 support
On 2024/1/24 11:25, Tim Lunn wrote:
Add support for ddr4 on rv1126. Timing detection files are imported
from downstream Rockchip BSP u-boot. Allow selecting ddr4 ram with
define CONFIG_RAM_ROCKCHIP_DDR4.
Signed-off-by: Tim Lunn
Reviewed-by: Kever Yang
Thanks,
- Kever
---
(no changes since v1)
.../sdram-rv1126-ddr4-detect-1056.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-328.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-396.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-528.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-664.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-784.inc | 75 +++
.../rockchip/sdram-rv1126-ddr4-detect-924.inc | 75 +++
drivers/ram/rockchip/sdram_rv1126.c | 8 ++
8 files changed, 533 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-328.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-396.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-528.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-664.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-784.inc
create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-924.inc
diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc
b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc
new file mode 100644
index 00..295b0871e0
--- /dev/null
+++ b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc
@@ -0,0 +1,75 @@
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x2,
+ .bw = 0x1,
+ .dbw = 0x0,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x11,
+ .cs1_row = 0x0,
+ .cs0_high16bit_row = 0x11,
+ .cs1_high16bit_row = 0x0,
+ .ddrconfig = 0
+ },
+ {
+ {0x561d1219},
+ {0x10030703},
+ {0x0002},
+ {0x},
+ {0x000c},
+ {0x034b},
+ 0x00ff
+ }
+ },
+ {
+ .ddr_freq = 1056, /* clock rate(MHz) */
+ .dramtype = DDR4,
+ .num_channels = 1,
+ .stride = 0,
+ .odt = 1
+ },
+ {
+ {
+ {0x, 0x43041010}, /* MSTR */
+ {0x0064, 0x008000b9}, /* RFSHTMG */
+ {0x00d0, 0x00020103}, /* INIT0 */
+ {0x00d4, 0x0069}, /* INIT1 */
+ {0x00d8, 0x0100}, /* INIT2 */
+ {0x00dc, 0x07340401}, /* INIT3 */
+ {0x00e0, 0x0010}, /* INIT4 */
+ {0x00e4, 0x0011}, /* INIT5 */
+ {0x00e8, 0x0420}, /* INIT6 */
+ {0x00ec, 0x0800}, /* INIT7 */
+ {0x00f4, 0x000f011f}, /* RANKCTL */
+ {0x0100, 0x0f102411}, /* DRAMTMG0 */
+ {0x0104, 0x0004041a}, /* DRAMTMG1 */
+ {0x0108, 0x0608060d}, /* DRAMTMG2 */
+ {0x010c, 0x0040400c}, /* DRAMTMG3 */
+ {0x0110, 0x08030409}, /* DRAMTMG4 */
+ {0x0114, 0x06060403}, /* DRAMTMG5 */
+ {0x0120, 0x07070d07}, /* DRAMTMG8 */
+ {0x0124, 0x00020309}, /* DRAMTMG9 */
+ {0x0180, 0x0140}, /* ZQCTL0 */
+ {0x0184, 0x}, /* ZQCTL1 */
+ {0x0190, 0x07060004}, /* DFITMG0 */
+ {0x0198, 0x07000101}, /* DFILPCFG0 */
+ {0x01a0, 0xc043}, /* DFIUPD0 */
+ {0x0240, 0x06000614}, /* ODTCFG */
+ {0x0244, 0x0201}, /* ODTMAP */
+ {0x0250, 0x1f00}, /* SCHED */
+ {0x0490, 0x0001}, /* PCTRL_0 */
+ {0x, 0x}
+ }
+ },
+ {
+ {
+ {0x0004, 0x008c}, /* PHYREG01 */
+ {0x0014, 0x0010}, /* PHYREG05 */
+ {0x0018, 0x}, /*
Re: [PATCH v2 1/6] arm: dts: rockchip: Sync rv1126 dts from linux 6.8-rc1
On 2024/1/24 11:25, Tim Lunn wrote:
Sync linux dts files for rv1126 boards from linux v6.8-rc1 tag. Includes
the newly added dts for Sonoff iHost.
Signed-off-by: Tim Lunn
Reviewed-by: Kever Yang
Thanks,
- Kever
---
(no changes since v1)
arch/arm/dts/rv1126-edgeble-neu2-io.dts | 70
arch/arm/dts/rv1126-edgeble-neu2.dtsi | 27 +-
arch/arm/dts/rv1126-pinctrl.dtsi| 130
arch/arm/dts/rv1126-sonoff-ihost.dts| 29 ++
arch/arm/dts/rv1126-sonoff-ihost.dtsi | 404
arch/arm/dts/rv1126.dtsi| 185 +++
6 files changed, 835 insertions(+), 10 deletions(-)
create mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dts
create mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dtsi
diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io.dts
b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
index dded0a12f0..0c2396b8f8 100644
--- a/arch/arm/dts/rv1126-edgeble-neu2-io.dts
+++ b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
@@ -20,6 +20,76 @@
chosen {
stdout-path = "serial2:150n8";
};
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_dcin>;
+ };
+
+ v3v3_sys: v3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "v3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <_sys>;
+ };
+};
+
+ {
+ assigned-clocks = < CLK_GMAC_SRC>, < CLK_GMAC_TX_RX>,
+ < CLK_GMAC_ETHERNET_OUT>;
+ assigned-clock-parents = < CLK_GMAC_SRC_M1>, < RGMII_MODE_CLK>;
+ assigned-clock-rates = <12500>, <0>, <2500>;
+ clock_in_out = "input";
+ phy-handle = <>;
+ phy-mode = "rgmii";
+ phy-supply = <_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_miim _bus2 _bus4
_out_ethernetm1_pins>;
+ tx_delay = <0x2a>;
+ rx_delay = <0x1a>;
+ status = "okay";
+};
+
+ {
+ phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id001c.c916",
+"ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_phy_rst>;
+ reset-assert-us = <2>;
+ reset-deassert-us = <10>;
+ reset-gpios = < RK_PB6 GPIO_ACTIVE_LOW>;
+ };
+};
+
+ {
+ ethernet {
+ eth_phy_rst: eth-phy-rst {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO _pull_down>;
+ };
+ };
+};
+
+ {
+ status = "okay";
};
{
diff --git a/arch/arm/dts/rv1126-edgeble-neu2.dtsi
b/arch/arm/dts/rv1126-edgeble-neu2.dtsi
index cc64ba4be3..7ea8d7d16f 100644
--- a/arch/arm/dts/rv1126-edgeble-neu2.dtsi
+++ b/arch/arm/dts/rv1126-edgeble-neu2.dtsi
@@ -11,15 +11,6 @@
mmc0 =
};
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- };
-
vccio_flash: vccio-flash-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -52,7 +43,7 @@
bus-width = <8>;
non-removable;
pinctrl-names = "default";
- pinctrl-0 = <_bus8 _cmd _clk _rstnout>;
+ pinctrl-0 = <_bus8 _cmd _clk>;
rockchip,default-sample-phase = <90>;
vmmc-supply = <_3v3>;
vqmmc-supply = <_flash>;
@@ -301,6 +292,22 @@
status = "okay";
};
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <5000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
{
bus-width = <4>;
cap-sd-highspeed;
diff --git a/arch/arm/dts/rv1126-pinctrl.dtsi b/arch/arm/dts/rv1126-pinctrl.dtsi
index 28d8d29942..f84f5f2d96 100644
---
Re: [PATCH 2/2] board: rockchip: Add support for rk3588 based Cool Pi CM5 EVB
On 2024/1/20 19:36, Andy Yan wrote:
Cool Pi CM5 EVB works as a mother board connect with CM5.
CM5 Specification:
- Rockchip RK3588
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet x 1 with PHY YT8531
- Gigabit ethernet x 1 drived by PCIE with YT6801S
CM5 EVB Specification:
- HDMI Type A out x 2
- HDMI Type D in x 1
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- PCIE M.2 E Key for Wireless connection
- PCIE M.2 M Key for NVME connection
- 40 pin header
The dts is from linux-6.8 rc1.
Signed-off-by: Andy Yan
Reviewed-by: Kever Yang
Thanks,
- Kever
---
.../arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi | 30 +
arch/arm/dts/rk3588-coolpi-cm5-evb.dts| 214 ++
arch/arm/dts/rk3588-coolpi-cm5.dtsi | 650 ++
board/rockchip/evb_rk3588/MAINTAINERS | 8 +
configs/coolpi-cm5-evb-rk3588_defconfig | 105 +++
5 files changed, 1007 insertions(+)
create mode 100644 arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3588-coolpi-cm5-evb.dts
create mode 100644 arch/arm/dts/rk3588-coolpi-cm5.dtsi
create mode 100644 configs/coolpi-cm5-evb-rk3588_defconfig
diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
new file mode 100644
index 000..6b69ff424fa
--- /dev/null
+++ b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", ,
+ };
+};
+
+_pins {
+ bootph-all;
+};
+
+ {
+ bootph-pre-ram;
+ u-boot,spl-sfc-no-dma;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+
+ flash@0 {
+ bootph-pre-ram;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <2400>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb.dts
b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts
new file mode 100644
index 000..d4c70835e0f
--- /dev/null
+++ b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include
+#include "rk3588-coolpi-cm5.dtsi"
+
+/ {
+ model = "RK3588 CoolPi CM5 EVB";
+ compatible = "coolpi,pi-cm5-evb", "coolpi,pi-cm5", "rockchip,rk3588";
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ enable-gpios = < RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_en>;
+ power-supply = <_dcin>;
+ pwms = < 0 25000 0>;
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+
+ green_led: led-0 {
+ color = ;
+ function = LED_FUNCTION_STATUS;
+ gpios = < RK_PB7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_dcin>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <_dcin>;
+ };
+
+ vcc3v3_lcd: vcc3v3-lcd-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_lcd";
+ enable-active-high;
+ gpio = < RK_PC4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_en>;
+ vin-supply = <_sys>;
+ };
+
+ vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ regulator-boot-on;
+ regulator-always-on;
+ enable-active-high;
+ regulator-min-microvolt =
Re: [PATCH 1/2] board: rockchip: Add support for rk3588s based Cool Pi 4B
On 2024/1/20 19:36, Andy Yan wrote:
CoolPi 4B is a rk3588s based SBC.
Specification:
- Rockchip RK3588S
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet drived by PCIE with RTL8111HS
- HDMI Type D out
- Mini DP out
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- WIFI/BT module AIC8800
- 40 pin header
The dts is from linux-6.8 rc1.
Signed-off-by: Andy Yan
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi | 30 +
arch/arm/dts/rk3588s-coolpi-4b.dts | 813 +
board/rockchip/evb_rk3588/MAINTAINERS | 7 +
configs/coolpi-4b-rk3588s_defconfig| 105 +++
5 files changed, 956 insertions(+)
create mode 100644 arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3588s-coolpi-4b.dts
create mode 100644 configs/coolpi-4b-rk3588s_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b5c588c3363..a3d0cad3471 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -189,6 +189,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
+ rk3588s-coolpi-4b.dts \
rk3588-edgeble-neu6a-io.dtb \
rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
diff --git a/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
new file mode 100644
index 000..6b69ff424fa
--- /dev/null
+++ b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", ,
+ };
+};
+
+_pins {
+ bootph-all;
+};
+
+ {
+ bootph-pre-ram;
+ u-boot,spl-sfc-no-dma;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+
+ flash@0 {
+ bootph-pre-ram;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <2400>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
diff --git a/arch/arm/dts/rk3588s-coolpi-4b.dts
b/arch/arm/dts/rk3588s-coolpi-4b.dts
new file mode 100644
index 000..a15c8e8fa6d
--- /dev/null
+++ b/arch/arm/dts/rk3588s-coolpi-4b.dts
@@ -0,0 +1,813 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction
+ *
+ */
+
+/dts-v1/;
+
+#include
+#include
+#include
+#include "rk3588s.dtsi"
+
+/ {
+ model = "RK3588S CoolPi 4 Model B";
+ compatible = "coolpi,pi-4b", "rockchip,rk3588s";
+
+ aliases {
+ mmc0 =
+ mmc1 =
+ mmc2 =
+ serial2 =
+ };
+
+ analog-sound {
+ compatible = "audio-graph-card";
+ dais = <_8ch_p0>;
+ label = "rk3588-es8316";
+ routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+ widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+ };
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <_leds>;
+
+ led0: led-green {
+ color = ;
+ function = LED_FUNCTION_STATUS;
+ gpios = < RK_PD0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led1: led-red {
+ color = ;
+ default-state = "off";
+ function = LED_FUNCTION_WLAN;
+ gpios = < RK_PC4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx";
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <_enable_h>;
+ /*
+* On the module itself this is one of these (depending
+* on the actual card populated):
+* - SDIO_RESET_L_WL_REG_ON
+* - PDN (power down when low)
+*/
+ post-power-on-delay-ms = <200>;
+ reset-gpios = < RK_PC7 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+
Re: [PATCH 2/2] rockchip: rk3328-rock-pi-e: Enable DM_ETH_PHY and PHY_REALTEK
On 2024/1/18 15:19, Jonas Karlman wrote: Enable the DM_ETH_PHY and PHY_REALTEK now that the designware ethernet driver call eth_phy_set_mdio_bus() to assist with resetting the eth PHY during probe. Fixes ethernet on the v1.21 hw revision of Radxa ROCK Pi E: => mdio list ethernet@ff54: 1 - RealTek RTL8211F <--> ethernet@ff54 => net list eth0 : ethernet@ff54 86:e0:c0:ea:fa:a9 active eth1 : ethernet@ff55 86:e0:c0:ea:fa:a8 => dhcp Speed: 1000, full duplex BOOTP broadcast 1 BOOTP broadcast 2 BOOTP broadcast 3 DHCP client bound to address 192.168.1.114 (1004 ms) Reported-by: Trevor Woerner Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Thanks, - Kever --- configs/rock-pi-e-rk3328_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index c0375beffec3..6dda900a9b42 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -76,6 +76,8 @@ CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y
Re: [PATCH 1/2] net: designware: Reset eth phy before phy connect
On 2024/1/18 15:19, Jonas Karlman wrote: Some ethernet PHY require being reset before a phy-id can be read back on the MDIO bus. This can result in the following message being show on e.g. a Radxa ROCK Pi E v1.21 with a RTL8211F ethernet PHY. Could not get PHY for ethernet@ff54: addr -1 Add support to designware ethernet driver to reset eth phy by calling the eth phy uclass function eth_phy_set_mdio_bus(). The call use NULL as bus parameter to not set a shared mdio bus reference that would be freed when probe fails. Also add a eth_phy_get_addr() call to try and get the phy addr from DT when DM_MDIO is disabled. This help fix ethernet on Radxa ROCK Pi E v1.21: => mdio list ethernet@ff54: 1 - RealTek RTL8211F <--> ethernet@ff54 Reported-by: Trevor Woerner Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Thanks, - Kever --- drivers/net/designware.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index a174344b3ef5..9aa5d8a1409e 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -576,6 +577,9 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev) struct phy_device *phydev; int ret; + if (IS_ENABLED(CONFIG_DM_ETH_PHY)) + eth_phy_set_mdio_bus(dev, NULL); + #if IS_ENABLED(CONFIG_DM_MDIO) phydev = dm_eth_phy_connect(dev); if (!phydev) @@ -583,6 +587,9 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev) #else int phy_addr = -1; + if (IS_ENABLED(CONFIG_DM_ETH_PHY)) + phy_addr = eth_phy_get_addr(dev); + #ifdef CONFIG_PHY_ADDR phy_addr = CONFIG_PHY_ADDR; #endif
[PATCH v2 03/13] arm: mach-k3: am62px: introduce clock and device files for wkup spl
Include the clock and lpsc tree files needed for the wkup spl to
initialize the proper PLLs and power domains to boot the SoC.
Signed-off-by: Bryan Brattlof
---
arch/arm/mach-k3/r5/Makefile | 1 +
arch/arm/mach-k3/r5/am62px/Makefile| 6 +
arch/arm/mach-k3/r5/am62px/clk-data.c | 325 +
arch/arm/mach-k3/r5/am62px/dev-data.c | 71 ++
drivers/clk/ti/clk-k3.c| 6 +
drivers/power/domain/ti-power-domain.c | 6 +
include/k3-clk.h | 1 +
include/k3-dev.h | 1 +
8 files changed, 417 insertions(+)
create mode 100644 arch/arm/mach-k3/r5/am62px/Makefile
create mode 100644 arch/arm/mach-k3/r5/am62px/clk-data.c
create mode 100644 arch/arm/mach-k3/r5/am62px/dev-data.c
diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile
index b99199d337411..d1cd96d459bc4 100644
--- a/arch/arm/mach-k3/r5/Makefile
+++ b/arch/arm/mach-k3/r5/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_SOC_K3_J721E) += j7200/
obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
obj-$(CONFIG_SOC_K3_AM625) += am62x/
obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
+obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
obj-y += lowlevel_init.o
obj-y += r5_mpu.o
diff --git a/arch/arm/mach-k3/r5/am62px/Makefile
b/arch/arm/mach-k3/r5/am62px/Makefile
new file mode 100644
index 0..50b0df20a3d1a
--- /dev/null
+++ b/arch/arm/mach-k3/r5/am62px/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/r5/am62px/clk-data.c
b/arch/arm/mach-k3/r5/am62px/clk-data.c
new file mode 100644
index 0..4b9892fe05167
--- /dev/null
+++ b/arch/arm/mach-k3/r5/am62px/clk-data.c
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * AM62PX specific clock platform data
+ *
+ * This file is auto generated. Please do not hand edit and report any issues
+ * to Bryan Brattlof .
+ *
+ * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+ NULL,
+ NULL,
+ "osc_24_mhz",
+ "osc_25_mhz",
+ "osc_26_mhz",
+ NULL,
+};
+
+static const char * const clk_32k_rc_sel_out0_parents[] = {
+ "gluelogic_rcosc_clk_1p0v_97p65k",
+ "gluelogic_hfosc0_clkout",
+ "gluelogic_rcosc_clk_1p0v_97p65k",
+ "gluelogic_lfosc0_clkout",
+};
+
+static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
+ "board_0_mmc1_clklb_out",
+ "board_0_mmc1_clk_out",
+};
+
+static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
+ "board_0_ospi0_dqs_out",
+ "board_0_ospi0_lbclko_out",
+};
+
+static const char * const main_usb0_refclk_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "postdiv4_16ff_main_0_hsdivout8_clk",
+};
+
+static const char * const main_usb1_refclk_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "postdiv4_16ff_main_0_hsdivout8_clk",
+};
+
+static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] =
{
+ "gluelogic_hfosc0_clkout",
+ "hsdiv4_16fft_main_0_hsdivout0_clk",
+};
+
+static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "hsdiv4_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const clkout0_ctrl_out0_parents[] = {
+ "hsdiv4_16fft_main_2_hsdivout1_clk",
+ "hsdiv4_16fft_main_2_hsdivout1_clk",
+};
+
+static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_0_hsdivout5_clk",
+ "hsdiv4_16fft_main_2_hsdivout2_clk",
+};
+
+static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_0_hsdivout5_clk",
+ "hsdiv4_16fft_main_2_hsdivout2_clk",
+};
+
+static const char * const main_gtcclk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_2_hsdivout5_clk",
+ "postdiv4_16ff_main_0_hsdivout6_clk",
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ NULL,
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
+ "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
+ "hsdiv4_16fft_main_0_hsdivout1_clk",
+ "postdiv1_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const main_timerclkn_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "clk_32k_rc_sel_out0",
+ "postdiv4_16ff_main_0_hsdivout7_clk",
+ "gluelogic_rcosc_clkout",
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ NULL,
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ "hsdiv4_16fft_main_1_hsdivout3_clk",
+ "postdiv4_16ff_main_2_hsdivout6_clk",
+ NULL,
+
[PATCH v2 06/13] arch: mach-k3: introduce basic files to support the am62px SoC family
Introduce the basic functions and definitions needed to properly
initialize TI's am62p family of SoCs
Signed-off-by: Bryan Brattlof
---
arch/arm/mach-k3/Kconfig | 7 +-
arch/arm/mach-k3/am62p5_init.c| 280 ++
arch/arm/mach-k3/am62px/Kconfig | 32 ++
.../arm/mach-k3/include/mach/am62p_hardware.h | 83 ++
arch/arm/mach-k3/include/mach/am62p_spl.h | 49 +++
arch/arm/mach-k3/include/mach/hardware.h | 4 +
arch/arm/mach-k3/include/mach/spl.h | 4 +
7 files changed, 458 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-k3/am62p5_init.c
create mode 100644 arch/arm/mach-k3/am62px/Kconfig
create mode 100644 arch/arm/mach-k3/include/mach/am62p_hardware.h
create mode 100644 arch/arm/mach-k3/include/mach/am62p_spl.h
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 0574e81075e6d..02a9c423ecdb8 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -22,6 +22,9 @@ config SOC_K3_AM625
config SOC_K3_AM62A7
bool "TI's K3 based AM62A7 SoC Family Support"
+config SOC_K3_AM62P5
+ bool "TI's K3 based AM62P5 SoC Family Support"
+
endchoice
if SOC_K3_J721E
@@ -34,7 +37,7 @@ config SYS_SOC
config SYS_K3_NON_SECURE_MSRAM_SIZE
hex
- default 0x8 if SOC_K3_AM654
+ default 0x8 if SOC_K3_AM654 || SOC_K3_AM62P5
default 0x10 if SOC_K3_J721E || SOC_K3_J721S2
default 0x1c if SOC_K3_AM642
default 0x3c000 if SOC_K3_AM625 || SOC_K3_AM62A7
@@ -78,6 +81,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
default 0x43c3f290 if SOC_K3_AM625
default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R
default 0x7000f290 if SOC_K3_AM62A7 && ARM64
+ default 0x43c4f290 if SOC_K3_AM62P5
help
Address at which ROM stores the value which determines if SPL
is booted up by primary boot media or secondary boot media.
@@ -153,6 +157,7 @@ source "arch/arm/mach-k3/am65x/Kconfig"
source "arch/arm/mach-k3/am64x/Kconfig"
source "arch/arm/mach-k3/am62x/Kconfig"
source "arch/arm/mach-k3/am62ax/Kconfig"
+source "arch/arm/mach-k3/am62px/Kconfig"
source "arch/arm/mach-k3/j721e/Kconfig"
source "arch/arm/mach-k3/j721s2/Kconfig"
diff --git a/arch/arm/mach-k3/am62p5_init.c b/arch/arm/mach-k3/am62p5_init.c
new file mode 100644
index 0..5b6795cc7d246
--- /dev/null
+++ b/arch/arm/mach-k3/am62p5_init.c
@@ -0,0 +1,280 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM62P5: SoC specific initialization
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include
+#include
+#include
+#include "sysfw-loader.h"
+#include "common.h"
+#include
+#include
+#include
+
+struct fwl_data cbass_main_fwls[] = {
+ { "FSS_DAT_REG3", 7, 8 },
+};
+
+/*
+ * This uninitialized global variable would normal end up in the .bss section,
+ * but the .bss is cleared between writing and reading this variable, so move
+ * it to the .data section.
+ */
+u32 bootindex __section(".data");
+static struct rom_extended_boot_data bootdata __section(".data");
+
+static void store_boot_info_from_rom(void)
+{
+ bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
+ memcpy(, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
+ sizeof(struct rom_extended_boot_data));
+}
+
+static void ctrl_mmr_unlock(void)
+{
+ /* Unlock all WKUP_CTRL_MMR0 module registers */
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 5);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
+
+ /* Unlock all CTRL_MMR0 module registers */
+ mmr_unlock(CTRL_MMR0_BASE, 0);
+ mmr_unlock(CTRL_MMR0_BASE, 1);
+ mmr_unlock(CTRL_MMR0_BASE, 2);
+ mmr_unlock(CTRL_MMR0_BASE, 4);
+ mmr_unlock(CTRL_MMR0_BASE, 5);
+ mmr_unlock(CTRL_MMR0_BASE, 6);
+
+ /* Unlock all MCU_CTRL_MMR0 module registers */
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
+
+ /* Unlock PADCFG_CTRL_MMR padconf registers */
+ mmr_unlock(PADCFG_MMR0_BASE, 1);
+ mmr_unlock(PADCFG_MMR1_BASE, 1);
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (IS_ENABLED(CONFIG_CPU_V7R))
+ setup_k3_mpu_regions();
+
+ /*
+* Cannot delay this further as there is a chance that
+* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
+*/
+ store_boot_info_from_rom();
+
+ ctrl_mmr_unlock();
+
+ /* Init DM early
[PATCH v2 07/13] board: ti: introduce basic board files for the am62px family
Introduce the basic files needed to support the am62px family of SoCs
Co-developed-by: Hari Hagalla
Signed-off-by: Hari Hagalla
Signed-off-by: Bryan Brattlof
---
board/ti/am62px/Kconfig | 26 +
board/ti/am62px/MAINTAINERS | 9 +
board/ti/am62px/Makefile | 7 +
board/ti/am62px/am62px.env | 16 +
board/ti/am62px/board-cfg.yaml | 37 ++
board/ti/am62px/evm.c| 29 +
board/ti/am62px/pm-cfg.yaml | 12 +
board/ti/am62px/rm-cfg.yaml | 987 +++
board/ti/am62px/sec-cfg.yaml | 378
board/ti/am62px/tifs-rm-cfg.yaml | 879 +++
10 files changed, 2380 insertions(+)
create mode 100644 board/ti/am62px/Kconfig
create mode 100644 board/ti/am62px/MAINTAINERS
create mode 100644 board/ti/am62px/Makefile
create mode 100644 board/ti/am62px/am62px.env
create mode 100644 board/ti/am62px/board-cfg.yaml
create mode 100644 board/ti/am62px/evm.c
create mode 100644 board/ti/am62px/pm-cfg.yaml
create mode 100644 board/ti/am62px/rm-cfg.yaml
create mode 100644 board/ti/am62px/sec-cfg.yaml
create mode 100644 board/ti/am62px/tifs-rm-cfg.yaml
diff --git a/board/ti/am62px/Kconfig b/board/ti/am62px/Kconfig
new file mode 100644
index 0..9d95ffd9b2908
--- /dev/null
+++ b/board/ti/am62px/Kconfig
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+
+if TARGET_AM62P5_R5_EVM || TARGET_AM62P5_A53_EVM
+
+config SYS_BOARD
+ default "am62px"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "am62px_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_AM62P5_R5_EVM
+
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+endif
diff --git a/board/ti/am62px/MAINTAINERS b/board/ti/am62px/MAINTAINERS
new file mode 100644
index 0..57c86ddbc4aef
--- /dev/null
+++ b/board/ti/am62px/MAINTAINERS
@@ -0,0 +1,9 @@
+AM62Px BOARD
+M: Vignesh Raghavendra
+M: Bryan Brattlof
+M: Tom Rini
+S: Maintained
+F: board/ti/am62px/
+F: include/configs/am62p5_evm.h
+F: configs/am62px_evm_r5_defconfig
+F: configs/am62px_evm_a53_defconfig
diff --git a/board/ti/am62px/Makefile b/board/ti/am62px/Makefile
new file mode 100644
index 0..921afdff27a24
--- /dev/null
+++ b/board/ti/am62px/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += evm.o
diff --git a/board/ti/am62px/am62px.env b/board/ti/am62px/am62px.env
new file mode 100644
index 0..e982c8104c192
--- /dev/null
+++ b/board/ti/am62px/am62px.env
@@ -0,0 +1,16 @@
+#include
+#include
+#include
+
+name_kern=Image
+console=ttyS2,115200n8
+args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x0280
+ ${mtdparts}
+run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+
+boot_targets=mmc1 pxe dhcp
+boot=mmc
+mmcdev=1
+bootpart=1:2
+bootdir=/boot
+rd_spec=-
diff --git a/board/ti/am62px/board-cfg.yaml b/board/ti/am62px/board-cfg.yaml
new file mode 100644
index 0..d539011aff9f3
--- /dev/null
+++ b/board/ti/am62px/board-cfg.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for AM62Px SoCs
+#
+
+---
+
+board-cfg:
+rev:
+boardcfg_abi_maj: 0x0
+boardcfg_abi_min: 0x1
+control:
+subhdr:
+magic: 0xC1D3
+size: 7
+main_isolation_enable: 0x5A
+main_isolation_hostid: 0x2
+secproxy:
+subhdr:
+magic: 0x1207
+size: 7
+scaling_factor: 0x1
+scaling_profile: 0x1
+disable_main_nav_secure_proxy: 0
+msmc:
+subhdr:
+magic: 0xA5C3
+size: 5
+msmc_cache_size: 0x10
+debug_cfg:
+subhdr:
+magic: 0x020C
+size: 8
+trace_dst_enables: 0x00
+trace_src_enables: 0x00
diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c
new file mode 100644
index 0..97a95ce8cc2d5
--- /dev/null
+++ b/board/ti/am62px/evm.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for AM62Px platforms
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
diff --git a/board/ti/am62px/pm-cfg.yaml b/board/ti/am62px/pm-cfg.yaml
new file mode 100644
index 0..3ff27ce702c26
--- /dev/null
+++ b/board/ti/am62px/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright
[PATCH v2 05/13] arm: mach-k3: invert logic for split DM firmware config
Currently, for the K3 generation of SoCs, there are more SoCs that utilize the split firmware approach than the combined DMSC firmware. Invert the logic to avoid adding more and more SoCs to this list. Signed-off-by: Bryan Brattlof --- arch/arm/mach-k3/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 03898424c9546..0574e81075e6d 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -130,7 +130,7 @@ config K3_ATF_LOAD_ADDR config K3_DM_FW bool "Separate DM firmware image" - depends on CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN + depends on CPU_V7R && ARCH_K3 && !SOC_K3_AM642 && !SOC_K3_AM654 && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN default y help Enabling this will indicate that the system has separate DM -- 2.43.0
[PATCH v2 11/13] Makefile: remove hardcoded device tree source directory
Some boards that choose to utilize the OF_UPSTREAM directory for their device tree files will need to specify that directory instead of the traditional arch/$(ARCH)/dts/* path. Include the correct path to the board's dtbs depending on if OF_UPSTREAM is selected or not. Signed-off-by: Bryan Brattlof --- Makefile | 18 ++ scripts/Makefile.spl | 17 + 2 files changed, 27 insertions(+), 8 deletions(-) diff --git a/Makefile b/Makefile index 996a43c8624ae..f81d09c892b80 100644 --- a/Makefile +++ b/Makefile @@ -1184,6 +1184,16 @@ dt_binding_check: scripts_dtc quiet_cmd_copy = COPY$@ cmd_copy = cp $< $@ +ifeq ($(CONFIG_OF_UPSTREAM),y) +ifeq ($(CONFIG_ARM64),y) +dt_dir := dts/upstream/src/arm64 +else +dt_dir := dts/upstream/src/$(ARCH) +endif +else +dt_dir := arch/$(ARCH)/dts +endif + ifeq ($(CONFIG_MULTI_DTB_FIT),y) ifeq ($(CONFIG_MULTI_DTB_FIT_LZO),y) @@ -1209,7 +1219,7 @@ endif MKIMAGEFLAGS_fit-dtb.blob = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ -a 0 -e 0 -E \ - $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -d /dev/null + $(patsubst %,-b $(dt_dir)/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -d /dev/null MKIMAGEFLAGS_fit-dtb.blob += -B 0x8 @@ -1407,9 +1417,9 @@ MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ -p $(CONFIG_FIT_EXTERNAL_OFFSET) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ - $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(DEVICE_TREE))) \ - $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) \ - $(patsubst %,-b arch/$(ARCH)/dts/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST))) + $(patsubst %,-b $(dt_dir)/%.dtb,$(subst ",,$(DEVICE_TREE))) \ + $(patsubst %,-b $(dt_dir)/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) \ + $(patsubst %,-b $(dt_dir)/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST))) else MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 407fc52376a50..d074ba2350065 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -559,9 +559,15 @@ FORCE: $(obj)/dts/dt-$(SPL_NAME).dtb: dts/dt.dtb $(Q)$(MAKE) $(build)=$(obj)/dts spl_dtbs -PHONY += dts_dir -dts_dir: - $(shell [ -d $(obj)/dts ] || mkdir -p $(obj)/dts) +ifeq ($(CONFIG_OF_UPSTREAM),y) +ifeq ($(CONFIG_ARM64),y) +dt_dir := dts/upstream/src/arm64 +else +dt_dir := dts/upstream/src/$(ARCH) +endif +else +dt_dir := arch/$(ARCH)/dts +endif # Declare the contents of the .PHONY variable as phony. We keep that # information in a variable so we can use it in if_changed and friends. @@ -569,8 +575,11 @@ dts_dir: SPL_OF_LIST_TARGETS = $(patsubst %,dts/%.dtb,$(subst ",,$(CONFIG_SPL_OF_LIST))) SHRUNK_ARCH_DTB = $(addprefix $(obj)/,$(SPL_OF_LIST_TARGETS)) +$(dir $(SHRUNK_ARCH_DTB)): + $(shell [ -d $@ ] || mkdir -p $@) + .SECONDEXPANSION: -$(SHRUNK_ARCH_DTB): $$(patsubst $(obj)/dts/%, arch/$(ARCH)/dts/%, $$@) dts_dir +$(SHRUNK_ARCH_DTB): $$(patsubst $(obj)/dts/%, $(dt_dir)/%, $$@) $(dir $(SHRUNK_ARCH_DTB)) $(call if_changed,fdtgrep) targets += $(SPL_OF_LIST_TARGETS) -- 2.43.0
[PATCH v2 08/13] firmware: ti_sci_static_data: add static DMA channel data
From: Hari Nagalla
Include the static DMA channel data for ti_sci
Signed-off-by: Hari Nagalla
Signed-off-by: Bryan Brattlof
---
drivers/firmware/ti_sci_static_data.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/firmware/ti_sci_static_data.h
b/drivers/firmware/ti_sci_static_data.h
index 567ce8911a7da..135ec01bda460 100644
--- a/drivers/firmware/ti_sci_static_data.h
+++ b/drivers/firmware/ti_sci_static_data.h
@@ -84,7 +84,8 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
};
#endif /* CONFIG_SOC_K3_J721S2 */
-#if IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM62A7)
+#if IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM62A7) || \
+ IS_ENABLED(CONFIG_SOC_K3_AM62P5)
static struct ti_sci_resource_static_data rm_static_data[] = {
/* BC channels */
{
@@ -95,7 +96,7 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
},
{ },
};
-#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
+#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 || CONFIG_SOC_K3_AM62P5
*/
#else
static struct ti_sci_resource_static_data rm_static_data[] = {
--
2.43.0
[PATCH v2 09/13] dma: ti: k3-udma: Add DMA PSIL mappings for AM62P and J722S
From: Vignesh Raghavendra
Add PSIL data for the AM62P and the J722S SoC family. The PSIL mapping
for the J722S is the same except for the extra instances of the CSI-RX.
So let's reuse the same file for both the AM62P and J722S.
Signed-off-by: Vignesh Raghavendra
Signed-off-by: Ravi Gunasekaran
Signed-off-by: Vaishnav Achath
Signed-off-by: Jayesh Choudhary
[b...@ti.com: rebased to U-Boot v2024.01]
Signed-off-by: Bryan Brattlof
---
drivers/dma/ti/Makefile| 2 +
drivers/dma/ti/k3-psil-am62p.c | 325 +
drivers/dma/ti/k3-psil-priv.h | 1 +
drivers/dma/ti/k3-psil.c | 4 +
4 files changed, 332 insertions(+)
create mode 100644 drivers/dma/ti/k3-psil-am62p.c
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index f4e0271efbf32..17223b20432da 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -9,3 +9,5 @@ k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o
k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o
k3-psil-data-$(CONFIG_SOC_K3_AM62A7) += k3-psil-am62a.o
+k3-psil-data-$(CONFIG_SOC_K3_AM62P5) += k3-psil-am62p.o
+k3-psil-data-$(CONFIG_SOC_K3_J722S) += k3-psil-am62p.o
diff --git a/drivers/dma/ti/k3-psil-am62p.c b/drivers/dma/ti/k3-psil-am62p.c
new file mode 100644
index 0..8739bf41b5b7c
--- /dev/null
+++ b/drivers/dma/ti/k3-psil-am62p.c
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#include
+
+#include "k3-psil-priv.h"
+
+#define PSIL_PDMA_XY_TR(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .mapped_channel_id = -1,\
+ .default_flow_id = -1, \
+ }, \
+ }
+
+#define PSIL_PDMA_XY_PKT(x)\
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .mapped_channel_id = -1,\
+ .default_flow_id = -1, \
+ .pkt_mode = 1, \
+ }, \
+ }
+
+#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1,\
+ .psd_size = 16, \
+ .mapped_channel_id = ch,\
+ .flow_start = flow_base,\
+ .flow_num = flow_cnt, \
+ .default_flow_id = flow_base, \
+ }, \
+ }
+
+#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx)\
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1,\
+ .psd_size = 64, \
+ .mapped_channel_id = ch,\
+ .flow_start = flow_base,\
+ .flow_num = flow_cnt, \
+ .default_flow_id = default_flow,\
+ .notdpkt = tx, \
+ }, \
+ }
+
+#define PSIL_PDMA_MCASP(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .pdma_acc32 = 1,\
+ .pdma_burst = 1,\
+ },
[PATCH v2 13/13] doc: board: ti: introduce am62px documentation
Introduce basic documentation for the am62p family of SoCs. Signed-off-by: Bryan Brattlof --- doc/board/ti/am62px_sk.rst | 289 + doc/board/ti/k3.rst| 1 + 2 files changed, 290 insertions(+) create mode 100644 doc/board/ti/am62px_sk.rst diff --git a/doc/board/ti/am62px_sk.rst b/doc/board/ti/am62px_sk.rst new file mode 100644 index 0..1f2982c36f9e4 --- /dev/null +++ b/doc/board/ti/am62px_sk.rst @@ -0,0 +1,289 @@ +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +.. sectionauthor:: Bryan Brattlof + +AM62Px Platforms + + +The AM62Px is an extension of the existing Sitara AM62x low-cost family +of application processors built for Automotive and Linux Application +development. Scalable Arm Cortex-A53 performance and embedded features, +such as: multi high-definition display support, 3D-graphics +acceleration, 4K video acceleration, and extensive peripherals make the +AM62Px well-suited for a broad range of automation and industrial +application, including automotive digital instrumentation, automotive +displays, industrial HMI, and more. + +Some highlights of AM62P SoC are: + +* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. + Dual/Single core variants are provided in the same package to allow HW + compatible designs. + +* One Device manager Cortex-R5F for system power and resource + management, and one Cortex-R5F for Functional Safety or + general-purpose usage. + +* One 3D GPU up to 50 GLFOPS + +* H.264/H.265 Video Encode/Decode. + +* Display support: 3x display support over OLDI/LVDS (1x OLDI-DL, 1x or + 2x OLDI-SL), DSI, or DPI. Up to 3840x1080 @ 60fps resolution + +* Integrated Giga-bit Ethernet switch supporting up to a total of two + external ports (TSN capable). + +* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3xMMC and SD, GPMC for + NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, + 1xCSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. + +* Dedicated Centralized Hardware Security Module with support for secure + boot, debug security and crypto acceleration and trusted execution + environment. + +* One 32-bit DDR Subsystem that supports LPDDR4, DDR4 memory types. + +* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, + enabling battery powered system design. + +For those interested, more details about this SoC can be found in the +Technical Reference Manual here: https://www.ti.com/lit/pdf/spruj83 + +Boot Flow: +-- + +The bootflow is exactly the same as all SoCs in the am62xxx extended SoC +family. Below is the pictorial representation: + +.. image:: img/boot_diagram_k3_current.svg + :alt: Boot flow diagram + +- Here TIFS acts as master and provides all the critical services. R5/A53 + requests TIFS to get these services done as shown in the above diagram. + +Sources: + + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_boot_sources +:end-before: .. k3_rst_include_end_boot_sources + +Build procedure: + + +0. Setup the environment variables: + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_common_env_vars_desc +:end-before: .. k3_rst_include_end_common_env_vars_desc + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_board_env_vars_desc +:end-before: .. k3_rst_include_end_board_env_vars_desc + +Set the variables corresponding to this platform: + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_common_env_vars_defn +:end-before: .. k3_rst_include_end_common_env_vars_defn + +.. code-block:: bash + + $ export UBOOT_CFG_CORTEXR=am62px_evm_r5_defconfig + $ export UBOOT_CFG_CORTEXA=am62px_evm_a53_defconfig + $ export TFA_BOARD=lite + $ # we dont use any extra TFA parameters + $ unset TFA_EXTRA_ARGS + $ export OPTEE_PLATFORM=k3-am62x + $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y" + +.. am62px_evm_rst_include_start_build_steps + +1. Trusted Firmware-A: + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_build_steps_tfa +:end-before: .. k3_rst_include_end_build_steps_tfa + + +2. OP-TEE: + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_build_steps_optee +:end-before: .. k3_rst_include_end_build_steps_optee + +3. U-Boot: + +* 3.1 R5: + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_build_steps_spl_r5 +:end-before: .. k3_rst_include_end_build_steps_spl_r5 + +* 3.2 A53: + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_build_steps_uboot +:end-before: .. k3_rst_include_end_build_steps_uboot +.. am62px_evm_rst_include_end_build_steps + +Target Images +-- + +In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC +variant (HS-FS, HS-SE) requires a different source for these files. + + - HS-FS + +* tiboot3-am62px-hs-fs-evm.bin from step 3.1 +* tispl.bin, u-boot.img from step
[PATCH v2 02/13] power: domain: ti: use IS_ENABLED macro
Cleanup this list and standardize on using the IS_ENABLED macro for the
power domain data list.
Signed-off-by: Bryan Brattlof
---
drivers/power/domain/ti-power-domain.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/power/domain/ti-power-domain.c
b/drivers/power/domain/ti-power-domain.c
index b34c982f4f5fa..dc5d74539edcf 100644
--- a/drivers/power/domain/ti-power-domain.c
+++ b/drivers/power/domain/ti-power-domain.c
@@ -81,19 +81,20 @@ static const struct soc_attr ti_k3_soc_pd_data[] = {
.family = "J7200",
.data = _pd_platdata,
},
-#elif CONFIG_SOC_K3_J721S2
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_J721S2)
{
.family = "J721S2",
.data = _pd_platdata,
},
#endif
-#ifdef CONFIG_SOC_K3_AM625
+#if IS_ENABLED(CONFIG_SOC_K3_AM625)
{
.family = "AM62X",
.data = _pd_platdata,
},
#endif
-#ifdef CONFIG_SOC_K3_AM62A7
+#if IS_ENABLED(CONFIG_SOC_K3_AM62A7)
{
.family = "AM62AX",
.data = _pd_platdata,
--
2.43.0
[PATCH v2 00/13] Introduce basic support for TI's AM62Px SoC family
Hello Again Everyone! **Note:** This series depends on the OF_UPSTREAM work from Sumit [0]. Patch #11 was added to fix some Makefile.spl targets to allow SPL builds to complete with the OF_UPSTREAM series. The AM62Px is an extension of the existing Sitara AM62x low-cost family of application processors built for Automotive and Linux Application development. Scalable Arm Cortex-A53 performance and embedded features, such as: multi high-definition display support, 3D-graphics acceleration, 4K video acceleration, and extensive peripherals make the AM62Px well-suited for a broad range of automation and industrial application, including automotive digital instrumentation, automotive displays, industrial HMI, and more. Some highlights of AM62P SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single core variants are provided in the same package to allow HW compatible designs. * One Device manager Cortex-R5F for system power and resource management, and one Cortex-R5F for Functional Safety or general-purpose usage. * One 3D GPU up to 50 GLFOPS * H.264/H.265 Video Encode/Decode. * Display support: 3x display support over OLDI/LVDS (1x OLDI-DL, 1x or 2x OLDI-SL), DSI, or DPI. Up to 3840x1080 @ 60fps resolution * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3xMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1xCSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized Hardware Security Module with support for secure boot, debug security and crypto acceleration and trusted execution environment. * One 32-bit DDR Subsystem that supports LPDDR4, DDR4 memory types. * Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling battery powered system design. For those interested, more details about this SoC can be found in the Technical Reference Manual here: https://www.ti.com/lit/pdf/spruj83 Proof-of-Life: https://paste.sr.ht/~bryanb/af2ac108a9362549aa326f182e87918d52bf2d71 Currently, while more peripherals are being added in Linux[0], this series will only support UART boot. Thanks for reviewing! ~Bryan Changes from v1: [1] - squashed all clk and lpsc tree updates into a single commit - corrected SOC_K3_AM642 typo with DM firmware Kconfig option - updated RM configs and dma nodes to enable IP that need DMA - added the dtb targets to the dts/Makefile - rebased the series on top of v2024.01-rc1 - switched to bootstd rather than use distro boot scripts. - enabled OF_UPSTREAM instead of using the arch/arm/dts directory [0] https://lore.kernel.org/u-boot/20240110103547.719757-1-sumit.g...@linaro.org/ [1] https://lore.kernel.org/all/20231012230616.2101992-13...@ti.com/ Bryan Brattlof (11): soc: add info to identify the am62p SoC family power: domain: ti: use IS_ENABLED macro arm: mach-k3: am62px: introduce clock and device files for wkup spl ram: k3-ddrss: enable the am62ax's DDR controller for am62px arm: mach-k3: invert logic for split DM firmware config arch: mach-k3: introduce basic files to support the am62px SoC family board: ti: introduce basic board files for the am62px family arm: dts: introduce am62p5 uboot dts files Makefile: remove hardcoded device tree source directory configs: introduce configs needed for the am62px doc: board: ti: introduce am62px documentation Hari Nagalla (1): firmware: ti_sci_static_data: add static DMA channel data Vignesh Raghavendra (1): dma: ti: k3-udma: Add DMA PSIL mappings for AM62P and J722S Makefile | 18 +- arch/arm/dts/Makefile |2 + arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi| 2800 + arch/arm/dts/k3-am62p-sk-binman.dtsi | 173 + arch/arm/dts/k3-am62p5-r5-sk.dts | 101 + arch/arm/dts/k3-am62p5-sk-u-boot.dtsi | 49 + arch/arm/mach-k3/Kconfig |9 +- arch/arm/mach-k3/Makefile |1 + arch/arm/mach-k3/am62p5_init.c| 280 ++ arch/arm/mach-k3/am62px/Kconfig | 32 + .../arm/mach-k3/include/mach/am62p_hardware.h | 83 + arch/arm/mach-k3/include/mach/am62p_spl.h | 49 + arch/arm/mach-k3/include/mach/hardware.h |6 + arch/arm/mach-k3/include/mach/spl.h |4 + arch/arm/mach-k3/r5/Makefile |1 + arch/arm/mach-k3/r5/am62px/Makefile |6 + arch/arm/mach-k3/r5/am62px/clk-data.c | 325 ++ arch/arm/mach-k3/r5/am62px/dev-data.c | 71 + board/ti/am62px/Kconfig | 26 + board/ti/am62px/MAINTAINERS |9 + board/ti/am62px/Makefile |7 + board/ti/am62px/am62px.env| 16 + board/ti/am62px/board-cfg.yaml| 37 + board/ti/am62px/evm.c
[PATCH v2 01/13] soc: add info to identify the am62p SoC family
Include the part number for TI's am62px family of SoCs so we can properly identify it during boot Signed-off-by: Bryan Brattlof --- arch/arm/mach-k3/include/mach/hardware.h | 2 ++ drivers/soc/soc_ti_k3.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index a1a9dfbde66c8..040288150b12f 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -46,6 +46,7 @@ #define JTAG_ID_PARTNO_J721S2 0xbb75 #define JTAG_ID_PARTNO_AM62X 0xbb7e #define JTAG_ID_PARTNO_AM62AX 0xbb8d +#define JTAG_ID_PARTNO_AM62PX 0xbb9d #define K3_SOC_ID(id, ID) \ static inline bool soc_is_##id(void) \ @@ -61,6 +62,7 @@ K3_SOC_ID(am64x, AM64X) K3_SOC_ID(j721s2, J721S2) K3_SOC_ID(am62x, AM62X) K3_SOC_ID(am62ax, AM62AX) +K3_SOC_ID(am62px, AM62PX) #define K3_SEC_MGR_SYS_STATUS 0x44234100 #define SYS_STATUS_DEV_TYPE_SHIFT 0 diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c index 355a5368dd45a..d7d0152b115fa 100644 --- a/drivers/soc/soc_ti_k3.c +++ b/drivers/soc/soc_ti_k3.c @@ -45,6 +45,9 @@ static const char *get_family_string(u32 idreg) case JTAG_ID_PARTNO_AM62AX: family = "AM62AX"; break; + case JTAG_ID_PARTNO_AM62PX: + family = "AM62PX"; + break; default: family = "Unknown Silicon"; }; -- 2.43.0
[PATCH v2 12/13] configs: introduce configs needed for the am62px
Introduce the initial configs needed to support the am62px SoC family Signed-off-by: Bryan Brattlof --- configs/am62px_evm_a53_defconfig | 178 +++ configs/am62px_evm_r5_defconfig | 137 include/configs/am62px_evm.h | 14 +++ 3 files changed, 329 insertions(+) create mode 100644 configs/am62px_evm_a53_defconfig create mode 100644 configs/am62px_evm_r5_defconfig create mode 100644 include/configs/am62px_evm.h diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig new file mode 100644 index 0..bd8002108b10c --- /dev/null +++ b/configs/am62px_evm_a53_defconfig @@ -0,0 +1,178 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_AM62P5=y +CONFIG_K3_ATF_LOAD_ADDR=0x9e78 +CONFIG_TARGET_AM62P5_A53_EVM=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8048 +CONFIG_SF_DEFAULT_SPEED=2500 +CONFIG_ENV_SIZE=0x4 +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_OF_UPSTREAM=y +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am62p5-sk" +CONFIG_SPL_TEXT_BASE=0x8008 +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x8200 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100 +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" +CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a0 +CONFIG_SPL_BSS_MAX_SIZE=0x8 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x28 +CONFIG_SPL_THERMAL=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=64 +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_DEVICE_REMOVE=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_MTD=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x4 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x80 +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0xC000 +CONFIG_FASTBOOT_BUF_SIZE=0x2F00 +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_SPL_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_I2C_EEPROM=y +CONFIG_SPL_I2C_EEPROM=y +CONFIG_FS_LOADER=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y +CONFIG_PHY_TI_DP83867=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_REMOTEPROC_TI_K3_DSP=y +CONFIG_REMOTEPROC_TI_K3_R5F=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y
[PATCH] arm: dts: k3-am62p5: enable the wkup i2c bus
The PMIC for the am62p5-sk is connected to the i2c bus on the wakeup
island. While we do not have a driver yet, enable it anyway so we can
begin development of the driver and characterization of the board.
Signed-off-by: Bryan Brattlof
---
arch/arm/dts/k3-am62p5-sk.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/dts/k3-am62p5-sk.dts b/arch/arm/dts/k3-am62p5-sk.dts
index 9e4479aa78886..77298d31a986f 100644
--- a/arch/arm/dts/k3-am62p5-sk.dts
+++ b/arch/arm/dts/k3-am62p5-sk.dts
@@ -790,6 +790,13 @@
_pmx0 {
bootph-all;
+ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_MCU_IOPAD(0x04c, PIN_INPUT, 0) /* (A13)
WKUP_I2C0_SCL */
+ AM62PX_MCU_IOPAD(0x050, PIN_INPUT, 0) /* (C11)
WKUP_I2C0_SDA */
+ >;
+ };
+
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
AM62PX_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7)
WKUP_UART0_CTSn */
@@ -801,6 +808,13 @@
};
};
+_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c0_pins_default>;
+ clock-frequency = <40>;
+};
+
_uart0 {
/* WKUP UART0 is used by DM firmware */
pinctrl-names = "default";
base-commit: b0d717b732ee28e446baf94522b3491e590f7fbb
--
2.43.0
[PATCH v2 04/13] ram: k3-ddrss: enable the am62ax's DDR controller for am62px
The am62px family of SoCs uses the same DDR controller as found on the am62ax family. Enable this option when building for the am62px family Signed-off-by: Bryan Brattlof --- drivers/ram/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 5b07e92030142..56391058567bb 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -65,7 +65,7 @@ choice default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 default K3_AM64_DDRSS if SOC_K3_AM642 default K3_AM64_DDRSS if SOC_K3_AM625 - default K3_AM62A_DDRSS if SOC_K3_AM62A7 + default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5 config K3_J721E_DDRSS bool "Enable J721E DDRSS support" -- 2.43.0
Re: [PATCH 3/3] rockchip: rk3588: Enable eMMC HS200 mode
On 2024/1/27 07:26, Jonas Karlman wrote: Writing to eMMC using HS200 mode work more reliably then other modes on RK3588 boards. Enable MMC_HS200_SUPPORT Kconfig option to prefer use of HS200 mode. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Thanks, - Kever --- configs/evb-rk3588_defconfig | 2 ++ configs/nanopc-t6-rk3588_defconfig | 2 ++ configs/neu6a-io-rk3588_defconfig| 2 ++ configs/neu6b-io-rk3588_defconfig| 2 ++ configs/orangepi-5-plus-rk3588_defconfig | 2 ++ configs/quartzpro64-rk3588_defconfig | 2 ++ configs/rock5a-rk3588s_defconfig | 2 ++ configs/rock5b-rk3588_defconfig | 2 ++ configs/turing-rk1-rk3588_defconfig | 2 ++ 9 files changed, 18 insertions(+) diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig index 0b7b4f2f627a..2dfdc71259f7 100644 --- a/configs/evb-rk3588_defconfig +++ b/configs/evb-rk3588_defconfig @@ -53,6 +53,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/nanopc-t6-rk3588_defconfig b/configs/nanopc-t6-rk3588_defconfig index 760993220929..26dcf3aae21c 100644 --- a/configs/nanopc-t6-rk3588_defconfig +++ b/configs/nanopc-t6-rk3588_defconfig @@ -66,6 +66,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig index d5301c630b2a..a6549420c01e 100644 --- a/configs/neu6a-io-rk3588_defconfig +++ b/configs/neu6a-io-rk3588_defconfig @@ -48,6 +48,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig index b13c9b5db1b0..b5739de147d8 100644 --- a/configs/neu6b-io-rk3588_defconfig +++ b/configs/neu6b-io-rk3588_defconfig @@ -48,6 +48,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/orangepi-5-plus-rk3588_defconfig b/configs/orangepi-5-plus-rk3588_defconfig index a58f96d57798..e5325158d2af 100644 --- a/configs/orangepi-5-plus-rk3588_defconfig +++ b/configs/orangepi-5-plus-rk3588_defconfig @@ -69,6 +69,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/quartzpro64-rk3588_defconfig b/configs/quartzpro64-rk3588_defconfig index 85af4c4ff955..fd8304debdbb 100644 --- a/configs/quartzpro64-rk3588_defconfig +++ b/configs/quartzpro64-rk3588_defconfig @@ -53,6 +53,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig index efa7bcbdcda6..10d6f6580490 100644 --- a/configs/rock5a-rk3588s_defconfig +++ b/configs/rock5a-rk3588s_defconfig @@ -56,6 +56,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index a0678ff1290c..76f57340df5a 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -71,6 +71,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/turing-rk1-rk3588_defconfig b/configs/turing-rk1-rk3588_defconfig index 289f2da775c5..0d6c34d468e3 100644 --- a/configs/turing-rk1-rk3588_defconfig +++ b/configs/turing-rk1-rk3588_defconfig @@ -75,6 +75,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y
Re: [PATCH 2/3] rockchip: rk356x: Enable eMMC HS200 mode
On 2024/1/27 07:26, Jonas Karlman wrote: Writing to eMMC using HS200 mode work more reliably then other modes on RK356x boards. Enable MMC_HS200_SUPPORT Kconfig option to prefer use of HS200 mode. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Thanks, - Kever --- configs/anbernic-rgxx3-rk3566_defconfig | 2 ++ configs/bpi-r2-pro-rk3568_defconfig | 2 ++ configs/evb-rk3568_defconfig | 2 ++ configs/lubancat-2-rk3568_defconfig | 2 ++ configs/odroid-m1-rk3568_defconfig| 2 ++ configs/quartz64-a-rk3566_defconfig | 2 ++ configs/quartz64-b-rk3566_defconfig | 2 ++ configs/radxa-cm3-io-rk3566_defconfig | 2 ++ configs/rock-3a-rk3568_defconfig | 2 ++ configs/soquartz-blade-rk3566_defconfig | 2 ++ configs/soquartz-cm4-rk3566_defconfig | 2 ++ configs/soquartz-model-a-rk3566_defconfig | 2 ++ 12 files changed, 24 insertions(+) diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig index ed6643d9d4fa..295c0bd3fc61 100644 --- a/configs/anbernic-rgxx3-rk3566_defconfig +++ b/configs/anbernic-rgxx3-rk3566_defconfig @@ -61,6 +61,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/bpi-r2-pro-rk3568_defconfig b/configs/bpi-r2-pro-rk3568_defconfig index e6e0e6fc6fa6..c9e1cd2c2c85 100644 --- a/configs/bpi-r2-pro-rk3568_defconfig +++ b/configs/bpi-r2-pro-rk3568_defconfig @@ -60,6 +60,8 @@ CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig index cb9b87ff12cb..19eab9bf00ac 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -54,6 +54,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig index 80ae6ec3a2e9..c06a447fda26 100644 --- a/configs/lubancat-2-rk3568_defconfig +++ b/configs/lubancat-2-rk3568_defconfig @@ -55,6 +55,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig index 3130e341e776..7fed6e7da597 100644 --- a/configs/odroid-m1-rk3568_defconfig +++ b/configs/odroid-m1-rk3568_defconfig @@ -72,6 +72,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/quartz64-a-rk3566_defconfig b/configs/quartz64-a-rk3566_defconfig index ade08867f60f..fd6b0e528834 100644 --- a/configs/quartz64-a-rk3566_defconfig +++ b/configs/quartz64-a-rk3566_defconfig @@ -71,6 +71,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig index 8d01db54407d..ec7a677fd3d3 100644 --- a/configs/quartz64-b-rk3566_defconfig +++ b/configs/quartz64-b-rk3566_defconfig @@ -69,6 +69,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig index 4b606dcb8e94..10626acfdea2 100644 --- a/configs/radxa-cm3-io-rk3566_defconfig +++ b/configs/radxa-cm3-io-rk3566_defconfig @@ -55,6 +55,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig index 18372a570eb7..2b944163f5a9 100644 --- a/configs/rock-3a-rk3568_defconfig +++ b/configs/rock-3a-rk3568_defconfig @@ -68,6 +68,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git
Re: [PATCH 1/3] rockchip: rk35xx: Remove use of eMMC DDR52 mode
On 2024/1/27 07:26, Jonas Karlman wrote:
Writing to eMMC using DDR52 mode does not work reliably or at all on
RK356x and RK3588 boards.
Fix this by removing the mmc-ddr-1_8v prop from sdhci nodes.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 1 -
arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi | 1 -
arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 1 -
arch/arm/dts/rk3566-soquartz-u-boot.dtsi | 1 -
arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi | 1 -
arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 1 -
arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi| 1 -
arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi| 1 -
arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 1 -
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 1 -
arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi | 1 -
arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi | 1 -
12 files changed, 12 deletions(-)
diff --git a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
index 11976fd3a6e0..930d660868bb 100644
--- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
@@ -8,7 +8,6 @@
{
cap-mmc-highspeed;
- mmc-ddr-1_8v;
pinctrl-names = "default";
pinctrl-0 = <_bus8 _clk _cmd _datastrobe>;
};
diff --git a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
index 8de9d1535efb..c235b4357f7d 100644
--- a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
@@ -4,7 +4,6 @@
{
cap-mmc-highspeed;
- mmc-ddr-1_8v;
pinctrl-names = "default";
pinctrl-0 = <_bus8 _clk _cmd _datastrobe>;
};
diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
index 158f652cb3b1..e0e501deccfe 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
@@ -7,5 +7,4 @@
{
cap-mmc-highspeed;
- mmc-ddr-1_8v;
};
diff --git a/arch/arm/dts/rk3566-soquartz-u-boot.dtsi
b/arch/arm/dts/rk3566-soquartz-u-boot.dtsi
index f65f4067f3e9..5e46a2422d60 100644
--- a/arch/arm/dts/rk3566-soquartz-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-soquartz-u-boot.dtsi
@@ -4,7 +4,6 @@
{
cap-mmc-highspeed;
- mmc-ddr-1_8v;
pinctrl-names = "default";
pinctrl-0 = <_bus8 _clk _cmd _datastrobe>;
};
diff --git a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
index a44ac35bdacd..1597473017ed 100644
--- a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
@@ -8,7 +8,6 @@
{
cap-mmc-highspeed;
- mmc-ddr-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
pinctrl-0 = <_bus8 _clk _cmd _datastrobe>;
diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
index 62f572c4cf9f..64c43374c042 100644
--- a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
@@ -14,7 +14,6 @@
{
cap-mmc-highspeed;
- mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
diff --git a/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
index ecba91aa30f5..1fc71faa9e07 100644
--- a/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
@@ -8,7 +8,6 @@
{
cap-mmc-highspeed;
- mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
index caf524443079..74755a44eaee 100644
--- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
@@ -16,7 +16,6 @@
{
cap-mmc-highspeed;
- mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 46ebb77283f1..5b823fcca5fb 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -20,7 +20,6 @@
{
cap-mmc-highspeed;
- mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index e99e60185ebe..9ee9dd051e32 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -31,7 +31,6 @@
{
cap-mmc-highspeed;
- mmc-ddr-1_8v;
mmc-hs200-1_8v;
};
diff --git a/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi b/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi
index 471508a9ed74..ca2a684f3541 100644
---
Re: [PATCH 7/7] rockchip: rk35xx: Remove unnecessary status props
On 2024/1/27 06:14, Jonas Karlman wrote:
Remove unnecessary status props from rk35xx u-boot.dtsi files, regular
device tree files or default value already enable the affected nodes.
Also reorder bootph-pre-ram and clock-frequency props alphabetically in
rk3588s-u-boot.dtsi uart2 node.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk356x-u-boot.dtsi| 7 ---
arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi | 1 -
arch/arm/dts/rk3588s-u-boot.dtsi | 7 +--
3 files changed, 1 insertion(+), 14 deletions(-)
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index cacd45348a49..d347080577d9 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -19,7 +19,6 @@
dmc: dmc {
compatible = "rockchip,rk3568-dmc";
bootph-all;
- status = "okay";
};
otp: nvmem@fe38c000 {
@@ -27,7 +26,6 @@
reg = <0x0 0xfe38c000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
- status = "okay";
cpu_id: id@a {
reg = <0x0a 0x10>;
@@ -37,27 +35,22 @@
{
bootph-all;
- status = "okay";
};
{
bootph-all;
- status = "okay";
};
{
bootph-all;
- status = "okay";
};
{
bootph-all;
- status = "okay";
};
{
bootph-all;
- status = "okay";
};
{
diff --git a/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi
b/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi
index e791b572b6bf..471508a9ed74 100644
--- a/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi
@@ -15,5 +15,4 @@
{
bootph-pre-ram;
clock-frequency = <2400>;
- status = "okay";
};
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 945b2d62a75e..bf3b1ea8a3c6 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -17,7 +17,6 @@
dmc {
compatible = "rockchip,rk3588-dmc";
bootph-all;
- status = "okay";
};
usb_host0_xhci: usb@fc00 {
@@ -165,17 +164,14 @@
{
bootph-all;
- status = "okay";
};
{
bootph-pre-ram;
- status = "okay";
};
_grf {
bootph-pre-ram;
- status = "okay";
};
{
@@ -217,9 +213,8 @@
};
{
- clock-frequency = <2400>;
bootph-pre-ram;
- status = "okay";
+ clock-frequency = <2400>;
};
_xfer {
Re: [PATCH 6/7] rockchip: rk3588: Add default u-boot,spl-boot-order prop
On 2024/1/27 06:14, Jonas Karlman wrote:
Add a default u-boot,spl-boot-order prop to rk3588s-u-boot.dtsi and
remove the prop from board u-boot.dtsi files using the default value.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi | 6 --
arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi | 6 --
arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi | 6 --
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 4
arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi | 6 --
arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi| 6 --
arch/arm/dts/rk3588s-u-boot.dtsi| 4
7 files changed, 4 insertions(+), 34 deletions(-)
diff --git a/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi
b/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi
index 87831c9d432a..60494bb8485f 100644
--- a/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi
@@ -6,12 +6,6 @@
#include "rk3588-u-boot.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", ,
- };
-};
-
_pins {
bootph-all;
};
diff --git a/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi
b/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi
index b0f5c667197c..5d5fa6ffb214 100644
--- a/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi
@@ -2,12 +2,6 @@
#include "rk3588-u-boot.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", ,
- };
-};
-
_pins {
bootph-all;
};
diff --git a/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi
b/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi
index 191ec988c459..7b937943a53c 100644
--- a/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi
@@ -4,9 +4,3 @@
*/
#include "rk3588-u-boot.dtsi"
-
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", ,
- };
-};
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 5fa20cecc044..e99e60185ebe 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -7,10 +7,6 @@
#include
/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", ,
- };
-
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
diff --git a/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi
b/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi
index 06c6f327c14b..e791b572b6bf 100644
--- a/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi
@@ -6,12 +6,6 @@
#include "rk3588-u-boot.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", ,
- };
-};
-
{
cap-mmc-highspeed;
mmc-ddr-1_8v;
diff --git a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
index 584476f77b13..9a6a353088df 100644
--- a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
@@ -5,12 +5,6 @@
#include "rk3588s-u-boot.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", ,
- };
-};
-
{
cap-mmc-highspeed;
mmc-ddr-1_8v;
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index d251a210b313..945b2d62a75e 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -10,6 +10,10 @@
spi5 =
};
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", ,
+ };
+
dmc {
compatible = "rockchip,rk3588-dmc";
bootph-all;
Re: [PATCH 5/7] rockchip: rk3588: Sync device tree from linux v6.8-rc1
Seems Quentin also sync rk3588 with v6.8-rc1 in his patch.
Hi Quentin,
Could you update your patchset base on this patch set ?
Thanks,
- Kever
On 2024/1/27 06:14, Jonas Karlman wrote:
Sync rk3588 device tree from linux v6.8-rc1.
Signed-off-by: Jonas Karlman
---
arch/arm/dts/rk3588-edgeble-neu6a-io.dts | 4 -
arch/arm/dts/rk3588-edgeble-neu6b-io.dts | 6 +-
arch/arm/dts/rk3588-evb1-v10.dts | 99 ++-
arch/arm/dts/rk3588-nanopc-t6.dts| 10 +-
arch/arm/dts/rk3588-orangepi-5-plus.dts | 1 -
arch/arm/dts/rk3588-quartzpro64.dts | 2 +-
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 8 --
arch/arm/dts/rk3588-rock-5b.dts | 13 ++-
arch/arm/dts/rk3588-turing-rk1.dtsi | 2 -
arch/arm/dts/rk3588s-orangepi-5.dts | 7 +-
arch/arm/dts/rk3588s-rock-5a.dts | 10 +-
arch/arm/dts/rk3588s-u-boot.dtsi | 5 -
arch/arm/dts/rk3588s.dtsi| 116 +++
include/dt-bindings/soc/rockchip,vop2.h | 4 +
14 files changed, 251 insertions(+), 36 deletions(-)
diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io.dts
b/arch/arm/dts/rk3588-edgeble-neu6a-io.dts
index b51543892078..be6a4f4f90f6 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6a-io.dts
+++ b/arch/arm/dts/rk3588-edgeble-neu6a-io.dts
@@ -12,10 +12,6 @@
compatible = "edgeble,neural-compute-module-6a-io",
"edgeble,neural-compute-module-6a", "rockchip,rk3588";
- aliases {
- serial2 =
- };
-
chosen {
stdout-path = "serial2:150n8";
};
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts
b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts
index 9933765e4097..070baeb63431 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts
+++ b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts
@@ -9,13 +9,9 @@
/ {
model = "Edgeble Neu6B IO Board";
- compatible = "edgeble,neural-compute-module-6b-io",
+ compatible = "edgeble,neural-compute-module-6a-io",
"edgeble,neural-compute-module-6b", "rockchip,rk3588";
- aliases {
- serial2 =
- };
-
chosen {
stdout-path = "serial2:150n8";
};
diff --git a/arch/arm/dts/rk3588-evb1-v10.dts b/arch/arm/dts/rk3588-evb1-v10.dts
index b9d789d57862..ac7c677b0fb9 100644
--- a/arch/arm/dts/rk3588-evb1-v10.dts
+++ b/arch/arm/dts/rk3588-evb1-v10.dts
@@ -16,8 +16,8 @@
compatible = "rockchip,rk3588-evb1-v10", "rockchip,rk3588";
aliases {
+ ethernet0 =
mmc0 =
- serial2 =
};
chosen {
@@ -56,6 +56,63 @@
};
};
+ analog-sound {
+ compatible = "simple-audio-card";
+ pinctrl-names = "default";
+ pinctrl-0 = <_detect>;
+ simple-audio-card,name = "RK3588 EVB1 Audio";
+ simple-audio-card,aux-devs = <_headphone>, <_speaker>;
+ simple-audio-card,bitclock-master = <>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <>;
+ simple-audio-card,hp-det-gpio = < RK_PD5 GPIO_ACTIVE_LOW>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,pin-switches = "Headphones", "Speaker";
+ simple-audio-card,routing =
+ "Speaker Amplifier INL", "LOUT2",
+ "Speaker Amplifier INR", "ROUT2",
+ "Speaker", "Speaker Amplifier OUTL",
+ "Speaker", "Speaker Amplifier OUTR",
+ "Headphones Amplifier INL", "LOUT1",
+ "Headphones Amplifier INR", "ROUT1",
+ "Headphones", "Headphones Amplifier OUTL",
+ "Headphones", "Headphones Amplifier OUTR",
+ "LINPUT1", "Onboard Microphone",
+ "RINPUT1", "Onboard Microphone",
+ "LINPUT2", "Microphone Jack",
+ "RINPUT2", "Microphone Jack";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Microphone", "Onboard Microphone",
+ "Headphone", "Headphones",
+ "Speaker", "Speaker";
+
+ simple-audio-card,cpu {
+ sound-dai = <_8ch>;
+ };
+
+ masterdai: simple-audio-card,codec {
+ sound-dai = <>;
+ system-clock-frequency = <12288000>;
+ };
+ };
+
+ amp_headphone: headphone-amplifier {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = < RK_PD2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_amplifier_en>;
+ sound-name-prefix = "Headphones Amplifier";
+ };
+
+
Re: [PATCH 3/7] rockchip: rk356x: Move common uart2 props to rk356x-u-boot.dtsi
On 2024/1/27 06:14, Jonas Karlman wrote:
Move uart2 bootph-pre-ram and clock-frequency props from board to SoC
u-boot.dtsi. Regular board device tree already enables the uart2 node,
so status prop is dropped from u-boot.dtsi file.
Also remove unnecessary stdout-path = , regular board device tree
already provide a stdout-path = "serial2:" value.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 7 ---
arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 12
arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi | 12
arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 12
arch/arm/dts/rk3566-soquartz-u-boot.dtsi | 12
arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi | 13 -
arch/arm/dts/rk3568-evb-u-boot.dtsi| 17 -
arch/arm/dts/rk3568-generic-u-boot.dtsi| 11 ---
arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi | 12
arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 12
arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi | 12
arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 12
arch/arm/dts/rk3568-rock-3a-u-boot.dtsi| 12
arch/arm/dts/rk356x-u-boot.dtsi| 5 +
14 files changed, 5 insertions(+), 156 deletions(-)
diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
index f986e1941e7f..fa3df73c33db 100644
--- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
@@ -4,7 +4,6 @@
/ {
chosen {
- stdout-path =
u-boot,spl-boot-order = "same-as-spl", ,
};
@@ -88,9 +87,3 @@
vqmmc-supply = <_1v8>;
status = "okay";
};
-
- {
- clock-frequency = <2400>;
- bootph-all;
- status = "okay";
-};
diff --git a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
index 06cc15ed21b8..11976fd3a6e0 100644
--- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
@@ -2,12 +2,6 @@
#include "rk356x-u-boot.dtsi"
-/ {
- chosen {
- stdout-path =
- };
-};
-
{
bootph-all;
};
@@ -28,12 +22,6 @@
};
};
- {
- bootph-all;
- clock-frequency = <2400>;
- status = "okay";
-};
-
/*
* U-Boot does not support multiple regulators using the same gpio,
* use vcc5v0_usb20_host to fix use of USB 2.0 port
diff --git a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
index 3c2c54e94183..8de9d1535efb 100644
--- a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
@@ -2,12 +2,6 @@
#include "rk356x-u-boot.dtsi"
-/ {
- chosen {
- stdout-path =
- };
-};
-
{
cap-mmc-highspeed;
mmc-ddr-1_8v;
@@ -24,12 +18,6 @@
};
};
- {
- bootph-all;
- clock-frequency = <2400>;
- status = "okay";
-};
-
_host0_xhci {
dr_mode = "host";
};
diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
index c925439f71cd..158f652cb3b1 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
@@ -5,19 +5,7 @@
#include "rk356x-u-boot.dtsi"
-/ {
- chosen {
- stdout-path =
- };
-};
-
{
cap-mmc-highspeed;
mmc-ddr-1_8v;
};
-
- {
- clock-frequency = <2400>;
- bootph-all;
- status = "okay";
-};
diff --git a/arch/arm/dts/rk3566-soquartz-u-boot.dtsi
b/arch/arm/dts/rk3566-soquartz-u-boot.dtsi
index 793cca2ceaca..f65f4067f3e9 100644
--- a/arch/arm/dts/rk3566-soquartz-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-soquartz-u-boot.dtsi
@@ -2,12 +2,6 @@
#include "rk356x-u-boot.dtsi"
-/ {
- chosen {
- stdout-path =
- };
-};
-
{
cap-mmc-highspeed;
mmc-ddr-1_8v;
@@ -15,12 +9,6 @@
pinctrl-0 = <_bus8 _clk _cmd _datastrobe>;
};
- {
- bootph-all;
- clock-frequency = <2400>;
- status = "okay";
-};
-
_host0_xhci {
dr_mode = "host";
};
diff --git a/arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi
b/arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi
index 60a3b21f2d45..5f4f14b3bdae 100644
--- a/arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi
@@ -4,16 +4,3 @@
*/
#include "rk356x-u-boot.dtsi"
-
-/ {
- chosen {
- stdout-path =
- };
-};
-
- {
- clock-frequency = <2400>;
- bootph-pre-ram;
- status = "okay";
-};
-
diff --git a/arch/arm/dts/rk3568-evb-u-boot.dtsi
b/arch/arm/dts/rk3568-evb-u-boot.dtsi
index 382a52a28b10..5f4f14b3bdae
Re: [PATCH 2/7] rockchip: rk356x: Sync device tree from linux v6.8-rc1
On 2024/1/27 06:14, Jonas Karlman wrote:
Sync rk356x device tree from linux v6.8-rc1.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3566-quartz64-a.dts | 5 +++--
arch/arm/dts/rk3566-radxa-cm3-io.dts | 1 +
arch/arm/dts/rk3566-soquartz-blade.dts | 4
arch/arm/dts/rk3566-soquartz-cm4.dts | 4
arch/arm/dts/rk3566-soquartz-model-a.dts | 4
arch/arm/dts/rk3566-soquartz.dtsi| 1 -
6 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/rk3566-quartz64-a.dts
b/arch/arm/dts/rk3566-quartz64-a.dts
index 854d02b46e6f..59843a7a199c 100644
--- a/arch/arm/dts/rk3566-quartz64-a.dts
+++ b/arch/arm/dts/rk3566-quartz64-a.dts
@@ -31,8 +31,9 @@
fan: gpio_fan {
compatible = "gpio-fan";
gpios = < RK_PD5 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = <00
- 4500 1>;
+ gpio-fan,speed-map =
+ < 0 0>,
+ <4500 1>;
pinctrl-names = "default";
pinctrl-0 = <_en_h>;
#cooling-cells = <2>;
diff --git a/arch/arm/dts/rk3566-radxa-cm3-io.dts
b/arch/arm/dts/rk3566-radxa-cm3-io.dts
index 1b1c67d5b1ef..3ae24e39450a 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io.dts
+++ b/arch/arm/dts/rk3566-radxa-cm3-io.dts
@@ -14,6 +14,7 @@
compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566";
aliases {
+ ethernet0 =
mmc1 =
};
diff --git a/arch/arm/dts/rk3566-soquartz-blade.dts b/arch/arm/dts/rk3566-soquartz-blade.dts
index 4e49bebf548b..fdbf1c783242 100644
--- a/arch/arm/dts/rk3566-soquartz-blade.dts
+++ b/arch/arm/dts/rk3566-soquartz-blade.dts
@@ -13,6 +13,10 @@
model = "PINE64 RK3566 SOQuartz on Blade carrier board";
compatible = "pine64,soquartz-blade", "pine64,soquartz",
"rockchip,rk3566";
+ aliases {
+ ethernet0 =
+ };
+
/* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */
vcc3v0_sd: vcc3v0-sd-regulator {
compatible = "regulator-fixed";
diff --git a/arch/arm/dts/rk3566-soquartz-cm4.dts
b/arch/arm/dts/rk3566-soquartz-cm4.dts
index cddf6cd2fecb..6ed3fa4aee34 100644
--- a/arch/arm/dts/rk3566-soquartz-cm4.dts
+++ b/arch/arm/dts/rk3566-soquartz-cm4.dts
@@ -8,6 +8,10 @@
model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board";
compatible = "pine64,soquartz-cm4io", "pine64,soquartz",
"rockchip,rk3566";
+ aliases {
+ ethernet0 =
+ };
+
/* labeled +12v in schematic */
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
diff --git a/arch/arm/dts/rk3566-soquartz-model-a.dts
b/arch/arm/dts/rk3566-soquartz-model-a.dts
index 2208dbfb7f0a..f2095dfa4eaf 100644
--- a/arch/arm/dts/rk3566-soquartz-model-a.dts
+++ b/arch/arm/dts/rk3566-soquartz-model-a.dts
@@ -8,6 +8,10 @@
model = "PINE64 RK3566 SOQuartz on Model A carrier board";
compatible = "pine64,soquartz-model-a", "pine64,soquartz",
"rockchip,rk3566";
+ aliases {
+ ethernet0 =
+ };
+
/* labeled DCIN_12V in schematic */
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
diff --git a/arch/arm/dts/rk3566-soquartz.dtsi
b/arch/arm/dts/rk3566-soquartz.dtsi
index 63bae36b8f7e..bfb7b952f4c5 100644
--- a/arch/arm/dts/rk3566-soquartz.dtsi
+++ b/arch/arm/dts/rk3566-soquartz.dtsi
@@ -12,7 +12,6 @@
compatible = "pine64,soquartz", "rockchip,rk3566";
aliases {
- ethernet0 =
mmc0 =
mmc1 =
mmc2 =
Re: [PATCH 1/7] rockchip: rk356x: Sync device tree from linux v6.7
On 2024/1/27 06:14, Jonas Karlman wrote:
Sync rk356x device tree from linux v6.7.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3566-anbernic-rgxx3.dtsi | 42 +
arch/arm/dts/rk3566-quartz64-a.dts | 2 --
arch/arm/dts/rk3566-quartz64-b.dts | 2 --
arch/arm/dts/rk3566-radxa-cm3-io.dts| 4 +--
arch/arm/dts/rk3566-soquartz.dtsi | 3 --
arch/arm/dts/rk3568-evb.dts | 3 --
arch/arm/dts/rk3568-lubancat-2.dts | 3 --
arch/arm/dts/rk3568-nanopi-r5s.dtsi | 3 --
arch/arm/dts/rk3568-odroid-m1.dts | 3 --
arch/arm/dts/rk3568-radxa-cm3i.dtsi | 3 --
arch/arm/dts/rk3568-rock-3a.dts | 7 +++--
arch/arm/dts/rk356x.dtsi| 20 +++-
include/dt-bindings/clock/rk3568-cru.h | 1 +
13 files changed, 48 insertions(+), 48 deletions(-)
diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dtsi
b/arch/arm/dts/rk3566-anbernic-rgxx3.dtsi
index ad43fa199ca5..8cbf3d9a4f22 100644
--- a/arch/arm/dts/rk3566-anbernic-rgxx3.dtsi
+++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dtsi
@@ -191,30 +191,30 @@
};
};
- leds: gpio-leds {
- compatible = "gpio-leds";
- pinctrl-0 = <_pins>;
- pinctrl-names = "default";
+ leds: pwm-leds {
+ compatible = "pwm-leds";
green_led: led-0 {
color = ;
default-state = "on";
function = LED_FUNCTION_POWER;
- gpios = < RK_PC5 GPIO_ACTIVE_HIGH>;
+ max-brightness = <255>;
+ pwms = < 0 25000 0>;
};
amber_led: led-1 {
color = ;
function = LED_FUNCTION_CHARGING;
- gpios = < RK_PC6 GPIO_ACTIVE_HIGH>;
- retain-state-suspended;
+ max-brightness = <255>;
+ pwms = < 0 25000 0>;
};
red_led: led-2 {
color = ;
default-state = "off";
function = LED_FUNCTION_STATUS;
- gpios = < RK_PC7 GPIO_ACTIVE_HIGH>;
+ max-brightness = <255>;
+ pwms = < 0 25000 0>;
};
};
@@ -356,7 +356,6 @@
regulator-boot-on;
regulator-min-microvolt = <50>;
regulator-max-microvolt = <135>;
- regulator-init-microvolt = <90>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_logic";
@@ -371,7 +370,6 @@
regulator-boot-on;
regulator-min-microvolt = <50>;
regulator-max-microvolt = <135>;
- regulator-init-microvolt = <90>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_gpu";
@@ -533,7 +531,6 @@
regulator-boot-on;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <139>;
- regulator-init-microvolt = <90>;
regulator-name = "vdd_cpu";
regulator-ramp-delay = <2300>;
vin-supply = <_sys>;
@@ -597,15 +594,6 @@
};
};
- gpio-led {
- led_pins: led-pins {
- rockchip,pins =
- <0 RK_PC5 RK_FUNC_GPIO _pull_none>,
- <0 RK_PC6 RK_FUNC_GPIO _pull_none>,
- <0 RK_PC7 RK_FUNC_GPIO _pull_none>;
- };
- };
-
joy-mux {
joy_mux_en: joy-mux-en {
rockchip,pins =
@@ -654,10 +642,24 @@
vccio7-supply = <_3v3>;
};
+ {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
{
status = "okay";
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
{
vref-supply = <_1v8>;
status = "okay";
diff --git a/arch/arm/dts/rk3566-quartz64-a.dts
b/arch/arm/dts/rk3566-quartz64-a.dts
index 25a8c781f4e7..854d02b46e6f 100644
--- a/arch/arm/dts/rk3566-quartz64-a.dts
+++ b/arch/arm/dts/rk3566-quartz64-a.dts
@@ -366,7 +366,6 @@
regulator-boot-on;
regulator-min-microvolt = <50>;
regulator-max-microvolt = <135>;
- regulator-init-microvolt = <90>;
Re: [PATCH] board: rockchip: Add Hardkernel ODROID-M1S
Hi, On 1/25/24 22:50, Jonas Karlman wrote: + pinctrl-0 = <_bus8 _clk _cmd _datastrobe>; +}; Because this device tree is not yet in linux, hopefully correct props can be applied to device tree and u-boot do not need any overrides. I suppose this pinctrl override was copied from Odroid-M1 where the emmc_rst pin is shared with SPI flash. That is not the case on Odroid-M1S which doesnt have SPI flash. So should be ok to drop this override. Regards Tim
Re: [PATCH 16/18] rockchip: include asm/io.h directly in asm/arch-rockchip/hardware.h
On 2024/1/23 22:49, Quentin Schulz wrote: From: Quentin Schulz The different macros use writel which is defined in asm/io.h, so let's include the header so users of hardware.h do not need to include asm/io.h as well. While at it, remove asm/io.h includes wherever asm/arch-rockchip/hardware.h is included already. Cc: Quentin Schulz Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- arch/arm/include/asm/arch-rockchip/hardware.h| 2 ++ arch/arm/mach-rockchip/cpu-info.c| 1 - arch/arm/mach-rockchip/px30/px30.c | 1 - arch/arm/mach-rockchip/rk3036/rk3036.c | 1 - arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 1 - arch/arm/mach-rockchip/rk3066/rk3066.c | 1 - arch/arm/mach-rockchip/rk3188/rk3188.c | 1 - arch/arm/mach-rockchip/rk322x/rk322x.c | 1 - arch/arm/mach-rockchip/rk3288/rk3288.c | 1 - arch/arm/mach-rockchip/rk3308/rk3308.c | 1 - arch/arm/mach-rockchip/rk3328/rk3328.c | 1 - arch/arm/mach-rockchip/rk3368/rk3368.c | 1 - arch/arm/mach-rockchip/rk3399/rk3399.c | 1 - arch/arm/mach-rockchip/rk3568/rk3568.c | 1 - arch/arm/mach-rockchip/rk3588/rk3588.c | 1 - arch/arm/mach-rockchip/rv1126/rv1126.c | 1 - board/elgin/elgin_rv1108/elgin_rv1108.c | 1 - board/firefly/firefly-rk3308/roc_cc_rk3308.c | 1 - board/google/gru/gru.c | 1 - board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c | 1 - board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c | 1 - board/pine64/rockpro64_rk3399/rockpro64-rk3399.c | 1 - board/rockchip/evb_rv1108/evb_rv1108.c | 1 - board/theobroma-systems/puma_rk3399/puma-rk3399.c| 1 - board/vamrs/rock960_rk3399/rock960-rk3399.c | 1 - drivers/clk/rockchip/clk_pll.c | 1 - drivers/clk/rockchip/clk_px30.c | 1 - drivers/clk/rockchip/clk_rk3036.c| 1 - drivers/clk/rockchip/clk_rk3066.c| 1 - drivers/clk/rockchip/clk_rk3128.c| 1 - drivers/clk/rockchip/clk_rk3188.c| 1 - drivers/clk/rockchip/clk_rk322x.c| 1 - drivers/clk/rockchip/clk_rk3288.c| 1 - drivers/clk/rockchip/clk_rk3308.c| 1 - drivers/clk/rockchip/clk_rk3328.c| 1 - drivers/clk/rockchip/clk_rk3368.c| 1 - drivers/clk/rockchip/clk_rk3399.c| 1 - drivers/clk/rockchip/clk_rk3568.c| 1 - drivers/clk/rockchip/clk_rk3588.c| 1 - drivers/clk/rockchip/clk_rv1108.c| 1 - drivers/clk/rockchip/clk_rv1126.c| 1 - drivers/gpio/rk_gpio.c | 1 - drivers/net/gmac_rockchip.c | 1 - drivers/ram/rockchip/dmc-rk3368.c| 1 - drivers/ram/rockchip/sdram_px30.c| 1 - drivers/ram/rockchip/sdram_rk3066.c | 1 - drivers/ram/rockchip/sdram_rk3188.c | 1 - drivers/ram/rockchip/sdram_rk322x.c | 1 - drivers/ram/rockchip/sdram_rk3288.c | 1 - drivers/ram/rockchip/sdram_rk3399.c | 1 - drivers/ram/rockchip/sdram_rv1126.c | 1 - drivers/rng/rockchip_rng.c | 1 - drivers/sysreset/sysreset_rockchip.c | 1 - drivers/video/rockchip/dw_mipi_dsi_rockchip.c| 1 - drivers/video/rockchip/rk3288_hdmi.c | 1 - drivers/video/rockchip/rk3288_mipi.c | 1 - drivers/video/rockchip/rk3288_vop.c | 1 - drivers/video/rockchip/rk3399_hdmi.c | 1 - drivers/video/rockchip/rk3399_mipi.c | 1 - drivers/video/rockchip/rk3399_vop.c | 1 - drivers/video/rockchip/rk_edp.c | 1 - drivers/video/rockchip/rk_hdmi.c | 1 - drivers/video/rockchip/rk_lvds.c | 1 - 63 files changed, 2 insertions(+), 62 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/hardware.h b/arch/arm/include/asm/arch-rockchip/hardware.h index 62e8bed8f31..e4662a2d52d 100644 --- a/arch/arm/include/asm/arch-rockchip/hardware.h +++ b/arch/arm/include/asm/arch-rockchip/hardware.h @@ -6,6 +6,8 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H +#include + #define RK_CLRSETBITS(clr, set) clr) | (set)) << 16) | (set))
Re: [PATCH 14/18] rockchip: rk3588: add constants for some register address spaces
On 2024/1/23 22:49, Quentin Schulz wrote:
From: Quentin Schulz
It's one thing to have the register mapped via a well-defined struct but
it's another to be able to make use of it. For that to happen, one needs
to cast the physical address memory of the beginning of the register
address space with the struct. Since this cannot change, let's hardcode
it in the include files so that users do not need to duplicate this line
of code in their own implementation.
Usually only one place using these base address when the dts is not
using, so it's not a
big issue to define at where it's used.
Reviewed-by: Kever Yang
Thanks,
- Kever
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
arch/arm/include/asm/arch-rockchip/cru_rk3588.h | 2 ++
arch/arm/include/asm/arch-rockchip/ioc_rk3588.h | 6 ++
arch/arm/mach-rockchip/rk3588/rk3588.c | 4
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
index 7f4a9085392..a4507e5fdd7 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
@@ -63,6 +63,8 @@ struct rk3588_pll {
unsigned int reserved0[3];
};
+#define CRU_BASE 0xfd7c
+
struct rk3588_cru {
struct rk3588_pll pll[18];
unsigned int reserved0[16];/* Address Offset: 0x0240 */
diff --git a/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
index 5a656f850c7..7ad98466c39 100644
--- a/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
@@ -5,6 +5,8 @@
#ifndef _ASM_ARCH_IOC_RK3588_H
#define _ASM_ARCH_IOC_RK3588_H
+#define BUS_IOC_BASE 0xfd5f8000
+
struct rk3588_bus_ioc {
unsigned int reserved[3]; /* Address Offset: 0x */
unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x000C */
@@ -48,6 +50,8 @@ struct rk3588_bus_ioc {
check_member(rk3588_bus_ioc, gpio4d_iomux_sel_h, 0x009C);
+#define PMU1_IOC_BASE 0xfd5f
+
struct rk3588_pmu1_ioc {
unsigned int gpio0a_iomux_sel_l; /* Address Offset: 0x */
unsigned int gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */
@@ -70,6 +74,8 @@ struct rk3588_pmu1_ioc {
check_member(rk3588_pmu1_ioc, xin_con, 0x0040);
+#define PMU2_IOC_BASE 0xfd5f4000
+
struct rk3588_pmu2_ioc {
unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x */
unsigned int gpio0c_iomux_sel_l; /* Address Offset: 0x0004 */
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c
b/arch/arm/mach-rockchip/rk3588/rk3588.c
index c5eeda9d751..53ee9f1cebc 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -26,10 +26,6 @@
#define FW_SYSM_MST26_REG 0xa8
#define FW_SYSM_MST27_REG 0xac
-#define PMU1_IOC_BASE 0xfd5f
-#define PMU2_IOC_BASE 0xfd5f4000
-
-#define BUS_IOC_BASE 0xfd5f8000
#define BUS_IOC_GPIO2A_IOMUX_SEL_L0x40
#define BUS_IOC_GPIO2B_IOMUX_SEL_L0x48
#define BUS_IOC_GPIO2D_IOMUX_SEL_L0x58
Re: [PATCH 12/18] rockchip: transform rockchip_capsule_update_board_setup into a weak function symbol
On 2024/1/23 22:49, Quentin Schulz wrote:
From: Quentin Schulz
There's only one user of rockchip_capsule_update_board_setup, which is
in board.c, and only one board defines it, so instead of having a header
only for one function symbol, let's just use a weak symbol instead.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/include/asm/arch-rockchip/misc.h | 9 -
arch/arm/mach-rockchip/board.c| 5 -
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/misc.h
b/arch/arm/include/asm/arch-rockchip/misc.h
deleted file mode 100644
index ef37ff1661a..000
--- a/arch/arm/include/asm/arch-rockchip/misc.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * RK3399: Architecture common definitions
- *
- * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/
- * Rohan Garg
- */
-
-void rockchip_capsule_update_board_setup(void);
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 80b4514852f..4f666aee706 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -32,7 +32,6 @@
#include
#include
#include
-#include
#include
#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION)
@@ -148,6 +147,10 @@ void set_dfu_alt_info(char *interface, char *devstr)
env_set("dfu_alt_info", buf);
}
+__weak void rockchip_capsule_update_board_setup(void)
+{
+}
+
static void gpt_capsule_update_setup(void)
{
int p, i, ret;
Re: [PATCH 10/18] rockchip: theobroma-systems: ringneck: migrate to rockchip_early_misc_init_r
On 2024/1/23 22:49, Quentin Schulz wrote:
From: Quentin Schulz
Only setup_boottargets differs from the original misc_init_r from
Rockchip mach code, so let's use rockchip_early_misc_init_r instead of
reimplementing the whole misc_init_r from Rockchip.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
.../theobroma-systems/ringneck_px30/ringneck-px30.c | 20 +---
1 file changed, 1 insertion(+), 19 deletions(-)
diff --git a/board/theobroma-systems/ringneck_px30/ringneck-px30.c
b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
index ff7e414303d..bfebfe5136d 100644
--- a/board/theobroma-systems/ringneck_px30/ringneck-px30.c
+++ b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
@@ -4,29 +4,11 @@
*/
#include
-#include
#include
#include "../common/common.h"
-int misc_init_r(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- ret = rockchip_setup_macaddr();
- if (ret)
- return ret;
-
setup_boottargets();
return 0;
Re: [PATCH 11/18] rockchip: merge misc.c into board.c
On 2024/1/23 22:49, Quentin Schulz wrote:
From: Quentin Schulz
The functions aren't used anywhere else than in board.c, therefore,
let's not expose them anymore at all.
This merges misc.c and board.c together and removes the functions from
the misc.h header file.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/include/asm/arch-rockchip/misc.h | 5 --
arch/arm/mach-rockchip/Makefile | 1 -
arch/arm/mach-rockchip/board.c| 125 +++
arch/arm/mach-rockchip/misc.c | 135 --
4 files changed, 125 insertions(+), 141 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/misc.h
b/arch/arm/include/asm/arch-rockchip/misc.h
index 4155af8c3b0..ef37ff1661a 100644
--- a/arch/arm/include/asm/arch-rockchip/misc.h
+++ b/arch/arm/include/asm/arch-rockchip/misc.h
@@ -6,9 +6,4 @@
* Rohan Garg
*/
-int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
- const u32 cpuid_length,
- u8 *cpuid);
-int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length);
-int rockchip_setup_macaddr(void);
void rockchip_capsule_update_board_setup(void);
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 1dc92066bbf..c07bdaee4c3 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -23,7 +23,6 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
# meaning "turn it off".
obj-y += boot_mode.o
obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
-obj-$(CONFIG_MISC_INIT_R) += misc.o
endif
ifeq ($(CONFIG_TPL_BUILD),)
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index d5cb59c10fa..80b4514852f 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -1,20 +1,32 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd.
+ *
+ * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/
+ * Rohan Garg
+ *
+ * Based on puma-rk3399.c:
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*/
#include
#include
#include
+#include
#include
#include
#include
+#include
#include
#include
#include
+#include
+#include
#include
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -297,6 +309,119 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason
reason)
#endif
#ifdef CONFIG_MISC_INIT_R
+int rockchip_setup_macaddr(void)
+{
+#if CONFIG_IS_ENABLED(HASH) && CONFIG_IS_ENABLED(SHA256)
+ int ret;
+ const char *cpuid = env_get("cpuid#");
+ u8 hash[SHA256_SUM_LEN];
+ int size = sizeof(hash);
+ u8 mac_addr[6];
+
+ /* Only generate a MAC address, if none is set in the environment */
+ if (env_get("ethaddr"))
+ return 0;
+
+ if (!cpuid) {
+ debug("%s: could not retrieve 'cpuid#'\n", __func__);
+ return -1;
+ }
+
+ ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, );
+ if (ret) {
+ debug("%s: failed to calculate SHA256\n", __func__);
+ return -1;
+ }
+
+ /* Copy 6 bytes of the hash to base the MAC address on */
+ memcpy(mac_addr, hash, 6);
+
+ /* Make this a valid MAC address and set it */
+ mac_addr[0] &= 0xfe; /* clear multicast bit */
+ mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+
+ /* Make a valid MAC address for ethernet1 */
+ mac_addr[5] ^= 0x01;
+ eth_env_set_enetaddr("eth1addr", mac_addr);
+#endif
+ return 0;
+}
+
+int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
+ const u32 cpuid_length,
+ u8 *cpuid)
+{
+#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) || IS_ENABLED(CONFIG_ROCKCHIP_OTP)
+ struct udevice *dev;
+ int ret;
+
+ /* retrieve the device */
+#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE)
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(rockchip_efuse), );
+#elif IS_ENABLED(CONFIG_ROCKCHIP_OTP)
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(rockchip_otp), );
+#endif
+ if (ret) {
+ debug("%s: could not find efuse device\n", __func__);
+ return -1;
+ }
+
+ /* read the cpu_id range from the efuses */
+ ret = misc_read(dev, cpuid_offset, cpuid, cpuid_length);
+ if (ret < 0) {
+ debug("%s: reading cpuid from the efuses failed\n",
+ __func__);
+ return -1;
+ }
+#endif
+ return 0;
+}
+
+int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length)
+{
+
Re: [PATCH 09/18] rockchip: theobroma-systems: puma: migrate to rockchip_early_misc_init_r
On 2024/1/23 22:49, Quentin Schulz wrote:
From: Quentin Schulz
Only setup_iodomain() and setup_boottargets differ from the original
misc_init_r from Rockchip mach code, so let's use
rockchip_early_misc_init_r instead of reimplementing the whole
misc_init_r from Rockchip.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
board/theobroma-systems/puma_rk3399/puma-rk3399.c | 20 +---
1 file changed, 1 insertion(+), 19 deletions(-)
diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c
b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
index a82f97b2d54..98a818b135d 100644
--- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c
+++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
@@ -10,7 +10,6 @@
#include
#include
#include
-#include
#include "../common/common.h"
static void setup_iodomain(void)
@@ -27,25 +26,8 @@ static void setup_iodomain(void)
rk_setreg(>io_vsel, 1 << GRF_IO_VSEL_GPIO4CD_SHIFT);
}
-int misc_init_r(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- ret = rockchip_setup_macaddr();
- if (ret)
- return ret;
-
setup_iodomain();
setup_boottargets();
Re: [PATCH 08/18] rockchip: pine64: rockpro64: migrate to rockchip_early_misc_init_r
On 2024/1/23 22:49, Quentin Schulz wrote:
From: Quentin Schulz
Only setup_iodomain() differs from the original misc_init_r from
Rockchip mach code, so let's use rockchip_early_misc_init_r instead of
reimplementing the whole misc_init_r from Rockchip.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
board/pine64/rockpro64_rk3399/rockpro64-rk3399.c | 20 ++--
1 file changed, 2 insertions(+), 18 deletions(-)
diff --git a/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c
b/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c
index d79084614f1..d0a694ead1d 100644
--- a/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c
+++ b/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c
@@ -11,7 +11,6 @@
#include
#include
#include
-#include
#define GRF_IO_VSEL_BT565_SHIFT 0
#define PMUGRF_CON0_VSEL_SHIFT 8
@@ -31,26 +30,11 @@ static void setup_iodomain(void)
rk_setreg(>soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
}
-int misc_init_r(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
setup_iodomain();
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- ret = rockchip_setup_macaddr();
-
- return ret;
+ return 0;
}
#endif
Re: [PATCH 07/18] rockchip: pine64: pinephone: migrate to rockchip_early_misc_init_r
On 2024/1/23 22:49, Quentin Schulz wrote:
From: Quentin Schulz
Compared to the original misc_init_r from Rockchip mach code,
setup_iodomain() is added and rockchip_setup_macaddr() is not called.
It is assumed adding rockchip_setup_macaddr() back is fine.
Let's use rockchip_early_misc_init_r instead of reimplementing the whole
misc_init_r from Rockchip (the side effect being that
rockchip_setup_macaddr() is back).
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
.../pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c | 17 ++---
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
index b6ccbb9c1c4..de75ee329d8 100644
--- a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
+++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
@@ -12,7 +12,6 @@
#include
#include
#include
-#include
#include
#define GRF_IO_VSEL_BT565_GPIO2AB 1
@@ -56,23 +55,11 @@ static void setup_iodomain(void)
rk_setreg(>soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
}
-int misc_init_r(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
setup_iodomain();
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
+ return 0;
- return ret;
}
#endif
Re: [PATCH 06/18] rockchip: pine64: pinebook: migrate to rockchip_early_misc_init_r
On 2024/1/23 22:49, Quentin Schulz wrote:
From: Quentin Schulz
Compared to the original misc_init_r from Rockchip mach code,
setup_iodomain() is added and rockchip_setup_macaddr() is not called.
It is assumed adding rockchip_setup_macaddr() back is fine.
Let's use rockchip_early_misc_init_r instead of reimplementing the whole
misc_init_r from Rockchip (the side effect being that
rockchip_setup_macaddr() is back).
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c | 18 ++
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
index 4ad780767ea..2408a367305 100644
--- a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
+++ b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
@@ -11,7 +11,6 @@
#include
#include
#include
-#include
#include
#include
@@ -54,23 +53,10 @@ static void setup_iodomain(void)
rk_setreg(>soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
}
-int misc_init_r(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
setup_iodomain();
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- return ret;
+ return 0;
}
#endif
Re: [PATCH 05/18] rockchip: google: gru: migrate to rockchip_early_misc_init_r
On 2024/1/23 22:49, Quentin Schulz wrote:
From: Quentin Schulz
Only setup_iodomain() differs from the original misc_init_r from
Rockchip mach code, so let's use rockchip_early_misc_init_r instead of
reimplementing the whole misc_init_r from Rockchip.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
board/google/gru/gru.c | 20 ++--
1 file changed, 2 insertions(+), 18 deletions(-)
diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c
index fbcf845e87d..ecbf702b035 100644
--- a/board/google/gru/gru.c
+++ b/board/google/gru/gru.c
@@ -11,7 +11,6 @@
#include
#include
#include
-#include
#define GRF_IO_VSEL_BT656_SHIFT 0
#define GRF_IO_VSEL_AUDIO_SHIFT 1
@@ -85,24 +84,9 @@ static void setup_iodomain(void)
1 << PMUGRF_CON0_VOL_SHIFT));
}
-int misc_init_r(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
setup_iodomain();
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- ret = rockchip_setup_macaddr();
-
- return ret;
+ return 0;
}
Re: [PATCH 04/18] rockchip: add weak function symbol called at the beginning of misc_init_r
On 2024/1/23 22:49, Quentin Schulz wrote:
From: Quentin Schulz
Most Rockchip boards who override misc_init_r do it only to call another
function and keep the rest unchanged. Therefore to allow for less
duplication, let's just add a weak function symbol that is called inside
misc_init_r.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/mach-rockchip/board.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 2620530e03f..d5cb59c10fa 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -297,6 +297,11 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason
reason)
#endif
#ifdef CONFIG_MISC_INIT_R
+__weak int rockchip_early_misc_init_r(void)
+{
+ return 0;
+}
+
__weak int misc_init_r(void)
{
const u32 cpuid_offset = CFG_CPUID_OFFSET;
@@ -304,6 +309,10 @@ __weak int misc_init_r(void)
u8 cpuid[cpuid_length];
int ret;
+ ret = rockchip_early_misc_init_r();
+ if (ret)
+ return ret;
+
ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
if (ret)
return ret;
Re: [PATCH 03/18] rockchip: avoid out-of-bounds when computing cpuid
On 2024/1/23 22:49, Quentin Schulz wrote:
From: Quentin Schulz
The expected length of the cpuid, as passed with cpuid_length,
determines the size of cpuid_str string. Therefore, care should be taken
to make sure nothing is accessing data out-of-bounds.
Instead of using hardcoded values, derive them from cpuid_length.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/mach-rockchip/misc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c
index 7d03f0c2b67..15397cff009 100644
--- a/arch/arm/mach-rockchip/misc.c
+++ b/arch/arm/mach-rockchip/misc.c
@@ -102,7 +102,7 @@ int rockchip_cpuid_set(const u8 *cpuid, const u32
cpuid_length)
int i;
memset(cpuid_str, 0, sizeof(cpuid_str));
- for (i = 0; i < 16; i++)
+ for (i = 0; i < cpuid_length; i++)
sprintf(_str[i * 2], "%02x", cpuid[i]);
debug("cpuid: %s\n", cpuid_str);
@@ -111,13 +111,13 @@ int rockchip_cpuid_set(const u8 *cpuid, const u32
cpuid_length)
* Mix the cpuid bytes using the same rules as in
* ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c
*/
- for (i = 0; i < 8; i++) {
+ for (i = 0; i < cpuid_length / 2; i++) {
low[i] = cpuid[1 + (i << 1)];
high[i] = cpuid[i << 1];
}
- serialno = crc32_no_comp(0, low, 8);
- serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
+ serialno = crc32_no_comp(0, low, cpuid_length / 2);
+ serialno |= (u64)crc32_no_comp(serialno, high, cpuid_length / 2) << 32;
snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno);
oldid = env_get("cpuid#");
Re: [PATCH 02/18] rockchip: rk3588: sync rk3588s dtsi from v6.8-rc1
On 2024/1/23 22:49, Quentin Schulz wrote:
From: Heiko Stuebner
This brings the real host2_xhci node as well as the pmu1grf node and
spi0 to spi4 aliases from the next-20240110 Linux kernel. So also
adapt/remove the nodes and aliases in rk3588s-u-boot.dtsi
Signed-off-by: Heiko Stuebner
[sync with v6.8-rc1]
[remove spi0 to spi4 aliases from rk3588s-u-boot.dtsi]
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3588s-u-boot.dtsi | 36 ++
arch/arm/dts/rk3588s.dtsi| 152 +++
2 files changed, 156 insertions(+), 32 deletions(-)
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 9a5ffec926e..960ac4abda3 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -7,11 +7,6 @@
/ {
aliases {
- spi0 =
- spi1 =
- spi2 =
- spi3 =
- spi4 =
spi5 =
};
@@ -43,33 +38,6 @@
status = "disabled";
};
- usb_host2_xhci: usb@fcd0 {
- compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3",
"snps,dwc3";
- reg = <0x0 0xfcd0 0x0 0x40>;
- interrupts = ;
- clocks = < REF_CLK_USB3OTG2>, < SUSPEND_CLK_USB3OTG2>,
-< ACLK_USB3OTG2>, < CLK_UTMI_OTG2>,
-< CLK_PIPEPHY2_PIPE_U3_G>;
- clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi",
"pipe";
- dr_mode = "host";
- phys = <_psu PHY_TYPE_USB3>;
- phy-names = "usb3-phy";
- phy_type = "utmi_wide";
- resets = < SRST_A_USB3OTG2>;
- snps,dis_enblslpm_quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis-del-phy-power-chg-quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- snps,dis_rxdet_inp3_quirk;
- status = "disabled";
- };
-
- pmu1_grf: syscon@fd58a000 {
- bootph-all;
- compatible = "rockchip,rk3588-pmugrf", "syscon";
- reg = <0x0 0xfd58a000 0x0 0x2000>;
- };
-
usbdpphy0_grf: syscon@fd5c8000 {
compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
reg = <0x0 0xfd5c8000 0x0 0x4000>;
@@ -201,6 +169,10 @@
status = "okay";
};
+ {
+ bootph-all;
+};
+
_grf {
bootph-pre-ram;
status = "okay";
diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi
index 61a9a11c3bb..36b1b7acfe6 100644
--- a/arch/arm/dts/rk3588s.dtsi
+++ b/arch/arm/dts/rk3588s.dtsi
@@ -18,6 +18,38 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ gpio0 =
+ gpio1 =
+ gpio2 =
+ gpio3 =
+ gpio4 =
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ i2c4 =
+ i2c5 =
+ i2c6 =
+ i2c7 =
+ i2c8 =
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
+ serial4 =
+ serial5 =
+ serial6 =
+ serial7 =
+ serial8 =
+ serial9 =
+ spi0 =
+ spi1 =
+ spi2 =
+ spi3 =
+ spi4 =
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -362,6 +394,11 @@
#clock-cells = <0>;
};
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <_out>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = ,
@@ -443,11 +480,47 @@
status = "disabled";
};
+ usb_host2_xhci: usb@fcd0 {
+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+ reg = <0x0 0xfcd0 0x0 0x40>;
+ interrupts = ;
+ clocks = < REF_CLK_USB3OTG2>, < SUSPEND_CLK_USB3OTG2>,
+< ACLK_USB3OTG2>, < CLK_UTMI_OTG2>,
+< CLK_PIPEPHY2_PIPE_U3_G>;
+ clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi",
"pipe";
+ dr_mode = "host";
+ phys = <_psu PHY_TYPE_USB3>;
+ phy-names = "usb3-phy";
+ phy_type = "utmi_wide";
+ resets = < SRST_A_USB3OTG2>;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ snps,dis_rxdet_inp3_quirk;
+ status = "disabled";
+ };
+
+
Re: [PATCH 01/18] rockchip: rk3588: use mainline pmu-grf compatible
On 2024/1/23 22:49, Quentin Schulz wrote:
From: Heiko Stuebner
The compatible for the pmugrf in the mainline kernel is dfferent from the
one currently used in u-boot. Adapt the -u-boot.dtsi and syscon driver
to use the correct compatible.
Signed-off-by: Heiko Stuebner
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3588s-u-boot.dtsi | 2 +-
arch/arm/mach-rockchip/rk3588/syscon_rk3588.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index c0fd16c4022..9a5ffec926e 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -66,7 +66,7 @@
pmu1_grf: syscon@fd58a000 {
bootph-all;
- compatible = "rockchip,rk3588-pmu1-grf", "syscon";
+ compatible = "rockchip,rk3588-pmugrf", "syscon";
reg = <0x0 0xfd58a000 0x0 0x2000>;
};
diff --git a/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c
index e8772d3a382..7b2cf37d9da 100644
--- a/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c
@@ -10,7 +10,7 @@
static const struct udevice_id rk3588_syscon_ids[] = {
{ .compatible = "rockchip,rk3588-sys-grf", .data = ROCKCHIP_SYSCON_GRF
},
- { .compatible = "rockchip,rk3588-pmu1-grf", .data =
ROCKCHIP_SYSCON_PMUGRF },
+ { .compatible = "rockchip,rk3588-pmugrf", .data =
ROCKCHIP_SYSCON_PMUGRF },
{ .compatible = "rockchip,rk3588-vop-grf", .data =
ROCKCHIP_SYSCON_VOP_GRF },
{ .compatible = "rockchip,rk3588-vo-grf", .data =
ROCKCHIP_SYSCON_VO_GRF },
{ .compatible = "rockchip,pcie30-phy-grf", .data =
ROCKCHIP_SYSCON_PCIE30_PHY_GRF },
Re: [PATCH 18/18] board: rockchip: add Theobroma-Systems RK3588 Jaguar SBC
On 2024/1/23 22:49, Quentin Schulz wrote:
From: Quentin Schulz
JAGUAR is a Single-Board Computer (SBC) based around the rk3588 SoC and
is targeting Autonomous Mobile Robots (AMR).
It features:
* LPDDR4X (up to 16GB)
* 1Gbps Ethernet on RJ45 connector (KSZ9031 or KSZ9131)
* PCIe 3.0 4-lane on M.2 M-key connector
* PCIe 2.1 1-lane on M.2 E-key
* USB 2.0 on M.2 E-key
* 2x USB3 OTG type-c ports with DP Alt-Mode
* USB2 host port
* HDMI output
* 2x camera connectors, each exposing:
* 2-lane MIPI-CSI
* 1v2, 1v8, 2v8 power rails
* I2C bus
* GPIOs
* PPS input
* CAN
* RS485 UART
* FAN connector
* SD card slot
* eMMC (up to 256GB)
* RTC backup battery
* Companion microcontroller
* ISL1208 RTC emulation
* AMC6821 PWM emulation
* On/off buzzer control
* Secure Element
* 80-pin Mezzanine connector for daughterboards:
* GPIOs
* 1Gbps Ethernet
* PCIe 2.1 1-lane
* 2x 2-lane MIPI-CSI
* ADC channel
* I2C bus
* PWM
* UART
* SPI
* SDIO
* CAN
* I2S
* 1v8, 3v3, 5v0, dc-in (12-24V) power rails
The Device Tree comes from next-20240110 Linux kernel.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
arch/arm/dts/rk3588-jaguar-u-boot.dtsi | 32 +
arch/arm/dts/rk3588-jaguar.dts | 803 +
arch/arm/mach-rockchip/rk3588/Kconfig | 28 +
board/theobroma-systems/jaguar_rk3588/Kconfig | 16 +
board/theobroma-systems/jaguar_rk3588/MAINTAINERS | 12 +
board/theobroma-systems/jaguar_rk3588/Makefile | 10 +
board/theobroma-systems/jaguar_rk3588/README | 118 +++
One thing you need to update is that, Tom is asking the document to
convert to RsT format,
so it would be better to move the board README to doc/board/ in .rst
format.
Thanks,
- Kever
.../jaguar_rk3588/jaguar_rk3588.c | 52 ++
configs/jaguar-rk3588_defconfig| 115 +++
include/configs/jaguar_rk3588.h| 15 +
10 files changed, 1201 insertions(+)
diff --git a/arch/arm/dts/rk3588-jaguar-u-boot.dtsi
b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi
new file mode 100644
index 000..59a3f9b41a9
--- /dev/null
+++ b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include "rk3588-u-boot.dtsi"
+#include
+#include
+#include
+#include
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", ,
+ };
+};
+
+_pwrseq {
+ bootph-all;
+};
+
+_reset {
+ bootph-all;
+};
+
+ {
+ bootph-all;
+};
+
+ {
+ bootph-all;
+};
diff --git a/arch/arm/dts/rk3588-jaguar.dts b/arch/arm/dts/rk3588-jaguar.dts
new file mode 100644
index 000..4ce70fb75a3
--- /dev/null
+++ b/arch/arm/dts/rk3588-jaguar.dts
@@ -0,0 +1,803 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+/dts-v1/;
+#include
+#include
+#include
+#include
+#include
+#include "rk3588.dtsi"
+
+/ {
+ model = "Theobroma Systems RK3588-SBC Jaguar";
+ compatible = "tsd,rk3588-jaguar", "rockchip,rk3588";
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = < 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <180>;
+ poll-interval = <100>;
+
+ /* Can be controlled through SW2 but also GPIO1 on CP2102 on
P20 */
+ button-bios-disable {
+ label = "BIOS_DISABLE";
+ linux,code = ;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
+ aliases {
+ ethernet0 =
+ mmc0 =
+ mmc1 =
+ rtc0 = _twi;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ /* DCIN is 12-24V but standard is 12V */
+ dc_12v: dc-12v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ pinctrl-0 = <_reset>;
+ pinctrl-names = "default";
+ reset-gpios = < RK_PA3 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ status = "okay";
+
+ /* LED1 on PCB */
+ led-1 {
+ gpios = < RK_PD4 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_HEARTBEAT;
+
Re: [PATCH 17/18] rockchip: rk3588: bind MMC controllers in U-Boot proper pre-reloc
On 2024/2/1 01:55, Quentin Schulz wrote:
Hi Kever,
On 1/29/24 11:35, Kever Yang wrote:
Hi Quentin,
On 2024/1/27 00:18, Quentin Schulz wrote:
Hi Kever,
On 1/26/24 11:56, Kever Yang wrote:
Hi Quentin,
On 2024/1/26 17:32, Quentin Schulz wrote:
Hi Kever,
On 1/26/24 09:58, Kever Yang wrote:
Hi Quentin,
On 2024/1/24 19:04, Quentin Schulz wrote:
Hi Kever,
On 1/24/24 11:35, Kever Yang wrote:
Hi Quentin,
On 2024/1/23 22:49, Quentin Schulz wrote:
From: Quentin Schulz
Since commit 9e644284ab81 ("dm: core: Report
bootph-pre-ram/sram node as
pre-reloc after relocation"), bootph-pre-ram doesn't make
U-Boot proper
bind the device before relocation.
While this is usually not much of an issue, it is when there's
a lookup
for devices by code running before the relocation. Such is the
case of
env_init() which calls env_driver_lookup() which calls
env_get_location() which is a weak symbol and may call
arch_env_get_location() also a weak symbol. Those are two
functions that
may traverse UCLASS to find some devices (e.g.
board/theobroma-systems/common/common.c:arch_env_get_location()).
This sounds like we need to update arch_env_get_location()
instead of enable mmc driver
before relocate, because you we don't really need the mmc
driver works here, there is no
access requirement to mmc at this point, right?
All Rockchip SoCs except RK3588(S) and RK356x have it done this
way, a little bit of consistency wouldn't hurt :)
My point is not about you can not enabe the emmc before relocate,
maybe I'm not clear enough for the reason.
All the driver bind/probed before the relocation will have to do
the init sequence again later after relocation.
The emmc driver cost pretty much time at init, we should avoid to
duplicate the init process if possible.
For this patch, you want to make it pre-relocate because you want
to make sure the emmc is available for ENVL_MMC,
but there is no read or write requirement to the emmc at this
point, which means we don't have to init the emmc at this point,
maybe we can check if the driver is enable if enough.
Now I need to know which SoC we are booting at build time so I can
check which drivers are supposed to be built, check those symbols
are enabled, then traverse the Device Tree with hardcoded DT node
to locations of MMC, SPI flash controllers, check if those are
enabled and finger-cross that those drivers will actually
bind/probe properly later on. That's A LOT of checks to be made.
This is not what I want to say.
What I mean is something like this for arch_env_get_location() is
enough, you don't have to bind/probe the emmc for env.
1623 if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC) &&
IS_ENABLED(CONFIG_MMC))
1624 return ENVL_MMC;
I do need to know if the device we loaded U-Boot proper from is an
MMC device or a SPI flash, so this is not enough for
arch_env_get_location().
I could do it in a hack-ish way though and check if the U-Boot
proper load medium DT node name starts with /mmc, or /spi and if
neither, then return NOWHERE, but then we lose the ability of
returning NOWHERE if the driver wasn't compiled in or the device
didn't bind in pre-reloc, we're missing some failsafe mechanism I
could have with this patch :)
[...]
For the feature record "spl-boot-device" in SPL and read in out
in U-Boot proper, and then Swap mmc0 and mmc1 in boot_targets if
booted from SD-Card.
It's OK for Theobroma-Systems's board to enable it, but seems not
also required by other boards.
Usually we consider the system in two stage: bootloader/BIOS
stage(including all firmware before kernel) and OS
stage(including kernel and Linux/Android OS),
and for those boards(eg. PC like) do have two different storage
medium, they put bootloader in SPI flash and put OS firmware in
other storage like emmc/SSD/SDcard.
In this case the U-Boot boot target does not need to know where
it's from;
in another case which supports firmware update from SD card, the
U-Boot boot target needs to set SDCard as highest priority, also
no need to know where the U-Boot from.
So... this means we need a different U-Boot if we're booting from
SD card so it can know which boot target to use by default? Or a
different environment for SD card? or requiring the user to stop
the boot process and manually change the priority? Or what are you
suggesting?
No, we don't need a different U-Boot, we can always set SD card
boot first in boot target in all case, if SD card don't have an
available firmware it will fall back to use eMMC, this works for
the board I have.
Maybe I didn't understand correctly why you have to do "Swap mmc0
and mmc1 in boot_targets if booted from SD-Card"?
I think I got things mixed up and this was not a necessary
discussion. But since we're here, I will try to explain what we want
to do with the whole process on Theobroma's boards.
arch_env_get_location() is the only one impacted by
Re: [PATCH] rockchip: board: Add minimal generic RK3588S/RK3588 board
Hi Jonas,
On 2024/2/1 06:08, Jonas Karlman wrote:
Add a minimal generic RK3588S/RK3588 board that only have eMMC and SDMMC
enabled. This defconfig can be used to boot from eMMC or SD-card on most
RK3588S/RK3588 boards that follow reference board design.
For rk3399, the evb-rk3399 is used as generic board because almost all
the boards which
follow the rockchip reference design can boot with evb-rk3399_defconfig.
For rk3588, I think we can still use evb-rk3588 as generic board instead
of a new generic-rk3588?
Since the board level dts will have to relate to IO, regulator, key and
so on, a virtual board
may not able to decide which IO/Hardware to use.
Thanks,
- Kever
Also fix the alphabetical order of RK3588 boards listed in Makefile and
documentation.
Signed-off-by: Jonas Karlman
---
This patch depend on the series "rockchip: rk35xx: Sync device tree
with linux v6.8-rc1" [1].
[1] https://patchwork.ozlabs.org/cover/1891669/
---
arch/arm/dts/Makefile | 5 +-
arch/arm/dts/rk3588-generic-u-boot.dtsi | 3 ++
arch/arm/dts/rk3588-generic.dts | 44
board/rockchip/evb_rk3588/MAINTAINERS | 7 +++
configs/generic-rk3588_defconfig| 68 +
doc/board/rockchip/rockchip.rst | 3 +-
6 files changed, 127 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/dts/rk3588-generic-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3588-generic.dts
create mode 100644 configs/generic-rk3588_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0fcae77cefe3..6361bc5abc37 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -193,13 +193,14 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-edgeble-neu6a-io.dtb \
rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
+ rk3588-generic.dtb \
rk3588-nanopc-t6.dtb \
rk3588s-orangepi-5.dtb \
rk3588-orangepi-5-plus.dtb \
rk3588-quartzpro64.dtb \
- rk3588-turing-rk1.dtb \
rk3588s-rock-5a.dtb \
- rk3588-rock-5b.dtb
+ rk3588-rock-5b.dtb \
+ rk3588-turing-rk1.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
diff --git a/arch/arm/dts/rk3588-generic-u-boot.dtsi
b/arch/arm/dts/rk3588-generic-u-boot.dtsi
new file mode 100644
index ..853ed58cfe58
--- /dev/null
+++ b/arch/arm/dts/rk3588-generic-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3588-generic.dts b/arch/arm/dts/rk3588-generic.dts
new file mode 100644
index ..e4721d97a87d
--- /dev/null
+++ b/arch/arm/dts/rk3588-generic.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Minimal generic DT for RK3588S/RK3588 with eMMC and SD-card enabled
+ */
+
+/dts-v1/;
+#include "rk3588s.dtsi"
+
+/ {
+ model = "Generic RK3588S/RK3588";
+ compatible = "rockchip,rk3588";
+
+ aliases {
+ mmc0 =
+ mmc1 =
+ };
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+};
+
+ {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ status = "okay";
+};
+
+ {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ no-mmc;
+ no-sdio;
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
diff --git a/board/rockchip/evb_rk3588/MAINTAINERS
b/board/rockchip/evb_rk3588/MAINTAINERS
index 2bd44bc58728..eb771da7b7a0 100644
--- a/board/rockchip/evb_rk3588/MAINTAINERS
+++ b/board/rockchip/evb_rk3588/MAINTAINERS
@@ -7,6 +7,13 @@ F: configs/evb-rk3588_defconfig
F:arch/arm/dts/rk3588-evb1-v10.dts
F:arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi
+GENERIC-RK3588
+M: Jonas Karlman
+S: Maintained
+F: configs/generic-rk3588_defconfig
+F: arch/arm/dts/rk3588-generic.dts
+F: arch/arm/dts/rk3588-generic-u-boot.dtsi
+
ORANGEPI-5-RK3588
M:Jonas Karlman
S:Maintained
diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig
new file mode 100644
index ..4755b27c1dea
--- /dev/null
+++ b/configs/generic-rk3588_defconfig
@@ -0,0 +1,68 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a0
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
+CONFIG_DEFAULT_DEVICE_TREE="rk3588-generic"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x60
+CONFIG_TARGET_EVB_RK3588=y
+CONFIG_SPL_STACK=0x40
+CONFIG_DEBUG_UART_BASE=0xFEB5
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
Re: [PATCH v9 2/2] arm64: boot: Support Flat Image Tree
On Thu, Feb 1, 2024 at 7:03 AM Rob Herring wrote: > > On Tue, Jan 30, 2024 at 3:16 AM Masahiro Yamada wrote: > > > > On Fri, Jan 26, 2024 at 1:04 AM Simon Glass wrote: > > > > > > Hi, > > > > > > On Wed, 17 Jan 2024 at 06:14, Simon Glass wrote: > > > > > > > > Hi Masahiro, Tom, > > > > > > > > On Tue, 9 Jan 2024 at 07:33, Tom Rini wrote: > > > > > > > > > > On Tue, Jan 09, 2024 at 11:01:42PM +0900, Masahiro Yamada wrote: > > > > > > Hi Simon, > > > > > > > > > > > > > > > > > > On Wed, Jan 3, 2024 at 8:47 AM Simon Glass > > > > > > wrote: > > > > > > > > > > > > > > Hi Masahiro, > > > > > > > > > > > > > > On Wed, Dec 13, 2023 at 5:14 AM Will Deacon > > > > > > > wrote: > > > > > > > > > > > > > > > > On Fri, Dec 01, 2023 at 08:54:42PM -0700, Simon Glass wrote: > > > > > > > > > Add a script which produces a Flat Image Tree (FIT), a single > > > > > > > > > file > > > > > > > > > containing the built kernel and associated devicetree files. > > > > > > > > > Compression defaults to gzip which gives a good balance of > > > > > > > > > size and > > > > > > > > > performance. > > > > > > > > > > > > > > > > > > The files compress from about 86MB to 24MB using this > > > > > > > > > approach. > > > > > > > > > > > > > > > > > > The FIT can be used by bootloaders which support it, such as > > > > > > > > > U-Boot > > > > > > > > > and Linuxboot. It permits automatic selection of the correct > > > > > > > > > devicetree, matching the compatible string of the running > > > > > > > > > board with > > > > > > > > > the closest compatible string in the FIT. There is no need for > > > > > > > > > filenames or other workarounds. > > > > > > > > > > > > > > > > > > Add a 'make image.fit' build target for arm64, as well. Use > > > > > > > > > FIT_COMPRESSION to select a different algorithm. > > > > > > > > > > > > > > > > > > The FIT can be examined using 'dumpimage -l'. > > > > > > > > > > > > > > > > > > This features requires pylibfdt (use 'pip install libfdt'). > > > > > > > > > It also > > > > > > > > > requires compression utilities for the algorithm being used. > > > > > > > > > Supported > > > > > > > > > compression options are the same as the Image.xxx files. For > > > > > > > > > now there > > > > > > > > > is no way to change the compression other than by editing the > > > > > > > > > rule for > > > > > > > > > $(obj)/image.fit > > > > > > > > > > > > > > > > > > While FIT supports a ramdisk / initrd, no attempt is made to > > > > > > > > > support > > > > > > > > > this here, since it must be built separately from the Linux > > > > > > > > > build. > > > > > > > > > > > > > > > > > > Signed-off-by: Simon Glass > > > > > > > > > --- > > > > > > > > > > > > > > > > > > Changes in v9: > > > > > > > > > - Move the compression control into Makefile.lib > > > > > > > > > > > > > > > > > > Changes in v8: > > > > > > > > > - Drop compatible string in FDT node > > > > > > > > > - Correct sorting of MAINTAINERS to before ARM64 PORT > > > > > > > > > - Turn compress part of the make_fit.py comment in to a > > > > > > > > > sentence > > > > > > > > > - Add two blank lines before parse_args() and setup_fit() > > > > > > > > > - Use 'image.fit: dtbs' instead of BUILD_DTBS var > > > > > > > > > - Use '$( > > > > > > > > - Add 'mkimage' details Documentation/process/changes.rst > > > > > > > > > - Allow changing the compression used > > > > > > > > > - Tweak cover letter since there is only one clean-up patch > > > > > > > > > > > > > > > > > > Changes in v7: > > > > > > > > > - Add Image as a dependency of image.fit > > > > > > > > > - Drop kbuild tag > > > > > > > > > - Add dependency on dtbs > > > > > > > > > - Drop unnecessary path separator for dtbs > > > > > > > > > - Rebase to -next > > > > > > > > > > > > > > > > > > Changes in v5: > > > > > > > > > - Drop patch previously applied > > > > > > > > > - Correct compression rule which was broken in v4 > > > > > > > > > > > > > > > > > > Changes in v4: > > > > > > > > > - Use single quotes for UIMAGE_NAME > > > > > > > > > > > > > > > > > > Changes in v3: > > > > > > > > > - Drop temporary file image.itk > > > > > > > > > - Drop patch 'Use double quotes for image name' > > > > > > > > > - Drop double quotes in use of UIMAGE_NAME > > > > > > > > > - Drop unnecessary CONFIG_EFI_ZBOOT condition for help > > > > > > > > > - Avoid hard-coding "arm64" for the DT architecture > > > > > > > > > > > > > > > > > > Changes in v2: > > > > > > > > > - Drop patch previously applied > > > > > > > > > - Add .gitignore file > > > > > > > > > - Move fit rule to Makefile.lib using an intermediate file > > > > > > > > > - Drop dependency on CONFIG_EFI_ZBOOT > > > > > > > > > - Pick up .dtb files separately from the kernel > > > > > > > > > - Correct pylint too-many-args warning for write_kernel() > > > > > > > > > - Include the kernel image in the file count > > > > > > > > > - Add a pointer to the FIT spec and mention of its wide > > > > > > > > > industry usage > >
[PATCH 3/3] smbios: correctly name Structure Table Maximum Size field
In the SMBIOS 3 entry point the Structure Table Maximum Size field was
incorrectly named max_struct_size. A Maximum Structure Size field only
exists in the SMBIOS 2.1 entry point and has a different meaning.
Call the Structure Table Length field table_maximum_size.
Signed-off-by: Heinrich Schuchardt
---
cmd/smbios.c| 2 +-
drivers/misc/qfw_smbios.c | 2 +-
include/smbios.h| 2 +-
lib/efi_loader/efi_tcg2.c | 4 ++--
lib/efi_loader/smbiosdump.c | 6 +++---
lib/smbios-parser.c | 2 +-
lib/smbios.c| 2 +-
7 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/cmd/smbios.c b/cmd/smbios.c
index e2d82be163..66f6b76137 100644
--- a/cmd/smbios.c
+++ b/cmd/smbios.c
@@ -142,7 +142,7 @@ static int do_smbios(struct cmd_tbl *cmdtp, int flag, int
argc,
entry3->major_ver, entry3->minor_ver, entry3->doc_rev);
table = (void *)(uintptr_t)entry3->struct_table_address;
size = entry3->length;
- table_maximum_size = entry3->max_struct_size;
+ table_maximum_size = entry3->table_maximum_size;
} else if (!memcmp(entry, smbios_sig, sizeof(smbios_sig) - 1)) {
struct smbios_entry *entry2 = entry;
diff --git a/drivers/misc/qfw_smbios.c b/drivers/misc/qfw_smbios.c
index a898cb4eea..c3e8c310d0 100644
--- a/drivers/misc/qfw_smbios.c
+++ b/drivers/misc/qfw_smbios.c
@@ -90,7 +90,7 @@ static int qfw_parse_smbios_anchor(struct udevice *dev,
entry->length = sizeof(struct smbios3_entry);
entry->major_ver = entry2->major_ver;
entry->minor_ver = entry2->minor_ver;
- entry->max_struct_size = entry2->struct_table_length;
+ entry->table_maximum_size = entry2->struct_table_length;
} else {
ret = -ENOENT;
goto out;
diff --git a/include/smbios.h b/include/smbios.h
index e2b7f69584..3df8827b60 100644
--- a/include/smbios.h
+++ b/include/smbios.h
@@ -75,7 +75,7 @@ struct __packed smbios3_entry {
/** @reserved: reserved */
u8 reserved;
/** maximum size of SMBIOS table */
- u32 max_struct_size;
+ u32 table_maximum_size;
/** @struct_table_address: 64-bit physical starting address */
u64 struct_table_address;
};
diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c
index b5d4aa7be5..b07e0099c2 100644
--- a/lib/efi_loader/efi_tcg2.c
+++ b/lib/efi_loader/efi_tcg2.c
@@ -1098,7 +1098,7 @@ tcg2_measure_smbios(struct udevice *dev,
*/
event_size = sizeof(struct smbios_handoff_table_pointers2) +
FIELD_SIZEOF(struct efi_configuration_table, guid) +
-entry->max_struct_size;
+entry->table_maximum_size;
event = calloc(1, event_size);
if (!event) {
ret = EFI_OUT_OF_RESOURCES;
@@ -1113,7 +1113,7 @@ tcg2_measure_smbios(struct udevice *dev,
smbios_copy = (struct smbios_header
*)((uintptr_t)>table_entry[0].table);
memcpy(>table_entry[0].table,
(void *)((uintptr_t)entry->struct_table_address),
- entry->max_struct_size);
+ entry->table_maximum_size);
smbios_prepare_measurement(entry, smbios_copy);
diff --git a/lib/efi_loader/smbiosdump.c b/lib/efi_loader/smbiosdump.c
index f0b901897e..2f0b91a353 100644
--- a/lib/efi_loader/smbiosdump.c
+++ b/lib/efi_loader/smbiosdump.c
@@ -329,7 +329,7 @@ efi_status_t do_check(void)
return EFI_LOAD_ERROR;
}
table = (void *)(uintptr_t)smbios3_anchor->struct_table_address;
- len = smbios3_anchor->max_struct_size;
+ len = smbios3_anchor->table_maximum_size;
} else {
struct smbios_entry *smbios_anchor;
int r;
@@ -469,7 +469,7 @@ static efi_status_t do_save(u16 *filename)
smbios3_anchor = get_config_table(_guid);
if (smbios3_anchor) {
- size = 0x20 + smbios3_anchor->max_struct_size;
+ size = 0x20 + smbios3_anchor->table_maximum_size;
ret = bs->allocate_pool(EFI_LOADER_DATA, size, (void **));
if (ret != EFI_SUCCESS) {
error(u"Out of memory\n");
@@ -480,7 +480,7 @@ static efi_status_t do_save(u16 *filename)
memcpy(buf, smbios3_anchor, smbios3_anchor->length);
memcpy(buf + 0x20,
(void *)(uintptr_t)smbios3_anchor->struct_table_address,
- smbios3_anchor->max_struct_size);
+ smbios3_anchor->table_maximum_size);
smbios3_anchor = (struct smbios3_entry *)buf;
smbios3_anchor->struct_table_address = 0x20;
diff --git a/lib/smbios-parser.c b/lib/smbios-parser.c
index 0d1ac781b3..9a62b3c760 100644
--- a/lib/smbios-parser.c
+++ b/lib/smbios-parser.c
@@ -230,7 +230,7 @@ void
[PATCH 1/3] cmd: smbios: show correct table size for SMBIOS2.1 entry point
The SMBIOS table size for SMBIOS2.1 entry points is in field 'Structure
Table Length' (offset 0x16) and not in field 'Maximum Structure Size'
(offset 0x08).
Rename the receiving variable max_struct_size to table_maximum_size
to avoid future confusion.
Signed-off-by: Heinrich Schuchardt
---
cmd/smbios.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/cmd/smbios.c b/cmd/smbios.c
index 95bdff6026..e2d82be163 100644
--- a/cmd/smbios.c
+++ b/cmd/smbios.c
@@ -126,7 +126,7 @@ static int do_smbios(struct cmd_tbl *cmdtp, int flag, int
argc,
static const char smbios_sig[] = "_SM_";
static const char smbios3_sig[] = "_SM3_";
size_t count = 0;
- u32 max_struct_size;
+ u32 table_maximum_size;
addr = gd_smbios_start();
if (!addr) {
@@ -142,7 +142,7 @@ static int do_smbios(struct cmd_tbl *cmdtp, int flag, int
argc,
entry3->major_ver, entry3->minor_ver, entry3->doc_rev);
table = (void *)(uintptr_t)entry3->struct_table_address;
size = entry3->length;
- max_struct_size = entry3->max_struct_size;
+ table_maximum_size = entry3->max_struct_size;
} else if (!memcmp(entry, smbios_sig, sizeof(smbios_sig) - 1)) {
struct smbios_entry *entry2 = entry;
@@ -150,7 +150,7 @@ static int do_smbios(struct cmd_tbl *cmdtp, int flag, int
argc,
entry2->major_ver, entry2->minor_ver);
table = (void *)(uintptr_t)entry2->struct_table_address;
size = entry2->length;
- max_struct_size = entry2->max_struct_size;
+ table_maximum_size = entry2->struct_table_length;
} else {
log_err("Unknown SMBIOS anchor format\n");
return CMD_RET_FAILURE;
@@ -163,7 +163,7 @@ static int do_smbios(struct cmd_tbl *cmdtp, int flag, int
argc,
for (struct smbios_header *pos = table; pos; pos = next_table(pos))
++count;
- printf("%zd structures occupying %d bytes\n", count, max_struct_size);
+ printf("%zd structures occupying %d bytes\n", count,
table_maximum_size);
printf("Table at 0x%llx\n", (unsigned long long)map_to_sysmem(table));
for (struct smbios_header *pos = table; pos; pos = next_table(pos)) {
--
2.43.0
[PATCH 2/3] smbios: do not determine maximum structure size
Only the SMBIOS 2.1 entry point has a field for the maximum structure size.
As we have switched to an SMBIOS 3 entry point remove the superfluous
calculation.
Signed-off-by: Heinrich Schuchardt
---
lib/smbios.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/lib/smbios.c b/lib/smbios.c
index cd750cc218..327f78c8b0 100644
--- a/lib/smbios.c
+++ b/lib/smbios.c
@@ -566,7 +566,6 @@ ulong write_smbios_table(ulong addr)
struct smbios_ctx ctx;
ulong tables;
int len = 0;
- int max_struct_size = 0;
int handle = 0;
int i;
@@ -588,7 +587,6 @@ ulong write_smbios_table(ulong addr)
/* populate minimum required tables */
for (i = 0; i < ARRAY_SIZE(smbios_write_funcs); i++) {
const struct smbios_write_method *method;
- int tmp;
method = _write_funcs[i];
ctx.subnode_name = NULL;
@@ -598,10 +596,7 @@ ulong write_smbios_table(ulong addr)
ctx.node = ofnode_find_subnode(parent_node,
method->subnode_name);
}
- tmp = method->write((ulong *), handle++, );
-
- max_struct_size = max(max_struct_size, tmp);
- len += tmp;
+ len += method->write((ulong *), handle++, );
}
/*
--
2.43.0
[PATCH 0/3] smbios: correct handling of table size
* In the smbios command show the orrect table size for SMBIOS 2.1 entry point. * The SMBIOS 3 entry point has not field for the maximum structure size. Avoid to determine it needlessly. * Name Structure Table Maximum Size field in the SMBIOS 3 entry point structure accordance to its meaning. Heinrich Schuchardt (3): cmd: smbios: show correct table size for SMBIOS2.1 entry point smbios: do not determine maximum structure size smbios: correctly name Structure Table Maximum Size field cmd/smbios.c| 8 drivers/misc/qfw_smbios.c | 2 +- include/smbios.h| 2 +- lib/efi_loader/efi_tcg2.c | 4 ++-- lib/efi_loader/smbiosdump.c | 6 +++--- lib/smbios-parser.c | 2 +- lib/smbios.c| 9 ++--- 7 files changed, 14 insertions(+), 19 deletions(-) -- 2.43.0
Re: [PATCH v8 15/16] configs: Add am69_sk_* defconfig fragments
On 1/29/24 12:26 PM, Apurva Nandan wrote: On 23/01/24 20:31, Andrew Davis wrote: On 1/23/24 8:39 AM, Apurva Nandan wrote: Hi Andrew, On 20/01/24 00:43, Andrew Davis wrote: On 1/19/24 11:50 AM, Apurva Nandan wrote: From: Dasnavis Sabiya Add config fragments for am69_sk A72 and R5 configuration. This applies on to: j784s4_evm_a72_defconfig -> am69_sk_a72.config j784s4_evm_r5_defconfig -> am69_sk_r5.config The usage model (with the fragment) would be: make j784s4_evm_a72_defconfig am69_sk_a72.config make OR make j784s4_evm_r5_defconfig am69_sk_r5.config make Signed-off-by: Dasnavis Sabiya Signed-off-by: Apurva Nandan --- board/ti/j784s4/MAINTAINERS | 2 ++ configs/am69_sk_a72.config | 5 + configs/am69_sk_r5.config | 5 + 3 files changed, 12 insertions(+) create mode 100644 configs/am69_sk_a72.config create mode 100644 configs/am69_sk_r5.config diff --git a/board/ti/j784s4/MAINTAINERS b/board/ti/j784s4/MAINTAINERS index 4433ead66b..69be13f533 100644 --- a/board/ti/j784s4/MAINTAINERS +++ b/board/ti/j784s4/MAINTAINERS @@ -20,3 +20,5 @@ AM69 SK BOARD F: arch/arm/dts/k3-am69-sk.dts F: arch/arm/dts/k3-am69-sk-u-boot.dtsi F: arch/arm/dts/k3-am69-r5-sk.dts +F: configs/am69_sk_r5.config +F: configs/am69_sk_a72.config diff --git a/configs/am69_sk_a72.config b/configs/am69_sk_a72.config new file mode 100644 index 00..03e74a8a56 --- /dev/null +++ b/configs/am69_sk_a72.config Just going to ignore the comments on v7 about putting this in board/ti/..? Sorry, somehow this got missed. Thanks for bringing up. Anyway, we can now do includes in defconfigs, so no config fragments needed, you can just add `configs/am69_evm_a72_defconfig` with the content: ``` #include CONFIG_ARM=y CONFIG_ARCH_K3=y CONFIG_SOC_K3_J784S4=y CONFIG_TARGET_J784S4_A72_EVM=y CONFIG_DEFAULT_DEVICE_TREE="k3-am69-sk" CONFIG_SPL_OF_LIST="k3-am69-sk" CONFIG_OF_LIST="k3-am69-sk" ``` (note we need to duplicate the _ARM/_TARGET currently to not confuse buildman which seems to directly parse the configs for arch detection). I tried it, but I don't think this works as '#' signifies a comment in defconfig, isn't that true? The ability to do this was just added recently, try it again :) Andrew Actually, I tried on the latest uboot next, but I still don't see things being included from j784s4_evm_a72_defconfig Can you point to the commit where this was introduced? https://source.denx.de/u-boot/u-boot/-/commit/2027e99e61aab6fd8b06e2d752e0e538cff26eb6 Andrew Andrew @@ -0,0 +1,5 @@ +# Defconfig fragment to apply on top of j784s4_evm_a72_defconfig + +CONFIG_DEFAULT_DEVICE_TREE="k3-am69-sk" +CONFIG_SPL_OF_LIST="k3-am69-sk" +CONFIG_OF_LIST="k3-am69-sk" diff --git a/configs/am69_sk_r5.config b/configs/am69_sk_r5.config new file mode 100644 index 00..c42b6f3380 --- /dev/null +++ b/configs/am69_sk_r5.config @@ -0,0 +1,5 @@ +# Defconfig fragment to apply on top of j784s4_evm_r5_defconfig + +CONFIG_DEFAULT_DEVICE_TREE="k3-am69-sk" +CONFIG_SPL_OF_LIST="k3-am69-r5-sk" +CONFIG_OF_LIST="k3-am69-r5-sk"
[PATCH] rockchip: board: Add minimal generic RK3588S/RK3588 board
Add a minimal generic RK3588S/RK3588 board that only have eMMC and SDMMC
enabled. This defconfig can be used to boot from eMMC or SD-card on most
RK3588S/RK3588 boards that follow reference board design.
Also fix the alphabetical order of RK3588 boards listed in Makefile and
documentation.
Signed-off-by: Jonas Karlman
---
This patch depend on the series "rockchip: rk35xx: Sync device tree
with linux v6.8-rc1" [1].
[1] https://patchwork.ozlabs.org/cover/1891669/
---
arch/arm/dts/Makefile | 5 +-
arch/arm/dts/rk3588-generic-u-boot.dtsi | 3 ++
arch/arm/dts/rk3588-generic.dts | 44
board/rockchip/evb_rk3588/MAINTAINERS | 7 +++
configs/generic-rk3588_defconfig| 68 +
doc/board/rockchip/rockchip.rst | 3 +-
6 files changed, 127 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/dts/rk3588-generic-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3588-generic.dts
create mode 100644 configs/generic-rk3588_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0fcae77cefe3..6361bc5abc37 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -193,13 +193,14 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-edgeble-neu6a-io.dtb \
rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
+ rk3588-generic.dtb \
rk3588-nanopc-t6.dtb \
rk3588s-orangepi-5.dtb \
rk3588-orangepi-5-plus.dtb \
rk3588-quartzpro64.dtb \
- rk3588-turing-rk1.dtb \
rk3588s-rock-5a.dtb \
- rk3588-rock-5b.dtb
+ rk3588-rock-5b.dtb \
+ rk3588-turing-rk1.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
diff --git a/arch/arm/dts/rk3588-generic-u-boot.dtsi
b/arch/arm/dts/rk3588-generic-u-boot.dtsi
new file mode 100644
index ..853ed58cfe58
--- /dev/null
+++ b/arch/arm/dts/rk3588-generic-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3588-generic.dts b/arch/arm/dts/rk3588-generic.dts
new file mode 100644
index ..e4721d97a87d
--- /dev/null
+++ b/arch/arm/dts/rk3588-generic.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Minimal generic DT for RK3588S/RK3588 with eMMC and SD-card enabled
+ */
+
+/dts-v1/;
+#include "rk3588s.dtsi"
+
+/ {
+ model = "Generic RK3588S/RK3588";
+ compatible = "rockchip,rk3588";
+
+ aliases {
+ mmc0 =
+ mmc1 =
+ };
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+};
+
+ {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ status = "okay";
+};
+
+ {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ no-mmc;
+ no-sdio;
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
diff --git a/board/rockchip/evb_rk3588/MAINTAINERS
b/board/rockchip/evb_rk3588/MAINTAINERS
index 2bd44bc58728..eb771da7b7a0 100644
--- a/board/rockchip/evb_rk3588/MAINTAINERS
+++ b/board/rockchip/evb_rk3588/MAINTAINERS
@@ -7,6 +7,13 @@ F: configs/evb-rk3588_defconfig
F: arch/arm/dts/rk3588-evb1-v10.dts
F: arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi
+GENERIC-RK3588
+M: Jonas Karlman
+S: Maintained
+F: configs/generic-rk3588_defconfig
+F: arch/arm/dts/rk3588-generic.dts
+F: arch/arm/dts/rk3588-generic-u-boot.dtsi
+
ORANGEPI-5-RK3588
M: Jonas Karlman
S: Maintained
diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig
new file mode 100644
index ..4755b27c1dea
--- /dev/null
+++ b/configs/generic-rk3588_defconfig
@@ -0,0 +1,68 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a0
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
+CONFIG_DEFAULT_DEVICE_TREE="rk3588-generic"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x60
+CONFIG_TARGET_EVB_RK3588=y
+CONFIG_SPL_STACK=0x40
+CONFIG_DEBUG_UART_BASE=0xFEB5
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-generic.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x400
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
[PATCH] rockchip: rk3568-generic: Enable eMMC HS200 mode
Writing to eMMC using HS200 mode work more reliably then other modes on
RK356x boards.
Add device tree props and enable Kconfig options for eMMC HS200 mode on
the generic RK3566/RK3568 board. Also enable the pinctrl driver in SPL
and add missing rk3568-generic.dtb to Makefile.
Signed-off-by: Jonas Karlman
---
This patch depends on the following series:
- rockchip: rk35xx: Sync device tree with linux v6.8-rc1 [1]
- rockchip: rk35xx: Fix writing to eMMC [2]
[1] https://patchwork.ozlabs.org/cover/1891669/
[2] https://patchwork.ozlabs.org/cover/1891692/
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/rk3568-generic.dts | 12 +++-
configs/generic-rk3568_defconfig | 5 -
3 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 50f35e3db3f0..0fcae77cefe3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -181,6 +181,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-soquartz-model-a.dtb \
rk3568-bpi-r2-pro.dtb \
rk3568-evb.dtb \
+ rk3568-generic.dtb \
rk3568-lubancat-2.dtb \
rk3568-nanopi-r5c.dtb \
rk3568-nanopi-r5s.dtb \
diff --git a/arch/arm/dts/rk3568-generic.dts b/arch/arm/dts/rk3568-generic.dts
index 1006ea55bb98..88eb1bfd2aab 100644
--- a/arch/arm/dts/rk3568-generic.dts
+++ b/arch/arm/dts/rk3568-generic.dts
@@ -10,7 +10,12 @@
model = "Generic RK3566/RK3568";
compatible = "rockchip,rk3568";
- chosen: chosen {
+ aliases {
+ mmc0 =
+ mmc1 =
+ };
+
+ chosen {
stdout-path = "serial2:150n8";
};
};
@@ -18,6 +23,9 @@
{
bus-width = <8>;
cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ no-sd;
+ no-sdio;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <_bus8 _clk _cmd>;
@@ -28,6 +36,8 @@
bus-width = <4>;
cap-sd-highspeed;
disable-wp;
+ no-mmc;
+ no-sdio;
pinctrl-names = "default";
pinctrl-0 = <_bus4 _clk _cmd>;
status = "okay";
diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig
index 8f0a9c8c449f..18a62b0033a0 100644
--- a/configs/generic-rk3568_defconfig
+++ b/configs/generic-rk3568_defconfig
@@ -42,7 +42,7 @@ CONFIG_CMD_MMC=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks
assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
@@ -51,11 +51,14 @@ CONFIG_ROCKCHIP_GPIO=y
CONFIG_MISC=y
# CONFIG_ROCKCHIP_IODOMAIN is not set
CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPL_PINCTRL=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=150
CONFIG_DEBUG_UART_SHIFT=2
--
2.43.0
Re: [PATCH v9 2/2] arm64: boot: Support Flat Image Tree
On Tue, Jan 30, 2024 at 3:16 AM Masahiro Yamada wrote: > > On Fri, Jan 26, 2024 at 1:04 AM Simon Glass wrote: > > > > Hi, > > > > On Wed, 17 Jan 2024 at 06:14, Simon Glass wrote: > > > > > > Hi Masahiro, Tom, > > > > > > On Tue, 9 Jan 2024 at 07:33, Tom Rini wrote: > > > > > > > > On Tue, Jan 09, 2024 at 11:01:42PM +0900, Masahiro Yamada wrote: > > > > > Hi Simon, > > > > > > > > > > > > > > > On Wed, Jan 3, 2024 at 8:47 AM Simon Glass wrote: > > > > > > > > > > > > Hi Masahiro, > > > > > > > > > > > > On Wed, Dec 13, 2023 at 5:14 AM Will Deacon wrote: > > > > > > > > > > > > > > On Fri, Dec 01, 2023 at 08:54:42PM -0700, Simon Glass wrote: > > > > > > > > Add a script which produces a Flat Image Tree (FIT), a single > > > > > > > > file > > > > > > > > containing the built kernel and associated devicetree files. > > > > > > > > Compression defaults to gzip which gives a good balance of size > > > > > > > > and > > > > > > > > performance. > > > > > > > > > > > > > > > > The files compress from about 86MB to 24MB using this approach. > > > > > > > > > > > > > > > > The FIT can be used by bootloaders which support it, such as > > > > > > > > U-Boot > > > > > > > > and Linuxboot. It permits automatic selection of the correct > > > > > > > > devicetree, matching the compatible string of the running board > > > > > > > > with > > > > > > > > the closest compatible string in the FIT. There is no need for > > > > > > > > filenames or other workarounds. > > > > > > > > > > > > > > > > Add a 'make image.fit' build target for arm64, as well. Use > > > > > > > > FIT_COMPRESSION to select a different algorithm. > > > > > > > > > > > > > > > > The FIT can be examined using 'dumpimage -l'. > > > > > > > > > > > > > > > > This features requires pylibfdt (use 'pip install libfdt'). It > > > > > > > > also > > > > > > > > requires compression utilities for the algorithm being used. > > > > > > > > Supported > > > > > > > > compression options are the same as the Image.xxx files. For > > > > > > > > now there > > > > > > > > is no way to change the compression other than by editing the > > > > > > > > rule for > > > > > > > > $(obj)/image.fit > > > > > > > > > > > > > > > > While FIT supports a ramdisk / initrd, no attempt is made to > > > > > > > > support > > > > > > > > this here, since it must be built separately from the Linux > > > > > > > > build. > > > > > > > > > > > > > > > > Signed-off-by: Simon Glass > > > > > > > > --- > > > > > > > > > > > > > > > > Changes in v9: > > > > > > > > - Move the compression control into Makefile.lib > > > > > > > > > > > > > > > > Changes in v8: > > > > > > > > - Drop compatible string in FDT node > > > > > > > > - Correct sorting of MAINTAINERS to before ARM64 PORT > > > > > > > > - Turn compress part of the make_fit.py comment in to a sentence > > > > > > > > - Add two blank lines before parse_args() and setup_fit() > > > > > > > > - Use 'image.fit: dtbs' instead of BUILD_DTBS var > > > > > > > > - Use '$( > > > > > > > - Add 'mkimage' details Documentation/process/changes.rst > > > > > > > > - Allow changing the compression used > > > > > > > > - Tweak cover letter since there is only one clean-up patch > > > > > > > > > > > > > > > > Changes in v7: > > > > > > > > - Add Image as a dependency of image.fit > > > > > > > > - Drop kbuild tag > > > > > > > > - Add dependency on dtbs > > > > > > > > - Drop unnecessary path separator for dtbs > > > > > > > > - Rebase to -next > > > > > > > > > > > > > > > > Changes in v5: > > > > > > > > - Drop patch previously applied > > > > > > > > - Correct compression rule which was broken in v4 > > > > > > > > > > > > > > > > Changes in v4: > > > > > > > > - Use single quotes for UIMAGE_NAME > > > > > > > > > > > > > > > > Changes in v3: > > > > > > > > - Drop temporary file image.itk > > > > > > > > - Drop patch 'Use double quotes for image name' > > > > > > > > - Drop double quotes in use of UIMAGE_NAME > > > > > > > > - Drop unnecessary CONFIG_EFI_ZBOOT condition for help > > > > > > > > - Avoid hard-coding "arm64" for the DT architecture > > > > > > > > > > > > > > > > Changes in v2: > > > > > > > > - Drop patch previously applied > > > > > > > > - Add .gitignore file > > > > > > > > - Move fit rule to Makefile.lib using an intermediate file > > > > > > > > - Drop dependency on CONFIG_EFI_ZBOOT > > > > > > > > - Pick up .dtb files separately from the kernel > > > > > > > > - Correct pylint too-many-args warning for write_kernel() > > > > > > > > - Include the kernel image in the file count > > > > > > > > - Add a pointer to the FIT spec and mention of its wide > > > > > > > > industry usage > > > > > > > > - Mention the kernel version in the FIT description > > > > > > > > > > > > > > > > Documentation/process/changes.rst | 9 + > > > > > > > > MAINTAINERS | 7 + > > > > > > > > arch/arm64/Makefile | 7 +- > > > > > > > > arch/arm64/boot/.gitignore| 1 + > > > > > > > >
Re: [PATCH v2] smbios: Fix table when no string is present
On 4/7/21 18:14, Simon Glass wrote:
Hi Matthias,
On Tue, 6 Apr 2021 at 21:04, wrote:
From: Matthias Brugger
When no string is present in a table, next_ptr points to the same
location as eos. When calculating the string table length, we would only
reserve one \0. By spec a SMBIOS table has to end with two \0\0 when no
strings a present.
Signed-off-by: Matthias Brugger
---
Changes in v2:
- check in smbios_string_table_len if no string present and return value
accordingly
This looks like a better idea to me. But where are the \0 bytes
actually written? Perhaps that should be in smbios_set_eos()?
We have defined SMBIOS_STRUCT_EOS_BYTES as 2 and we have an array
char eos[SMBIOS_STRUCT_EOS_BYTES];
at the end of each SMBIOS structure.
We call memset(t, 0, sizeof(struct smbios_typeX)); for each table.
This is enough to ensure two zero bytes exist if there are no strings.
Reviewed-by: Heinrich Schuchardt
lib/smbios.c | 4
1 file changed, 4 insertions(+)
diff --git a/lib/smbios.c b/lib/smbios.c
index 9eb226ec9f..fd57d8694f 100644
--- a/lib/smbios.c
+++ b/lib/smbios.c
@@ -191,6 +191,10 @@ int smbios_update_version(const char *version)
*/
static int smbios_string_table_len(const struct smbios_ctx *ctx)
{
+ /* In case no string is defined we have to return two \0 */
+ if (ctx->next_ptr == ctx->eos)
+ return 2;
+
/* Allow for the final \0 after all strings */
return (ctx->next_ptr + 1) - ctx->eos;
}
--
2.30.2
Regards,
Simon
Re: [PATCH 4/7] smbios: string table always needs two terminating NUL bytes
On 31.01.24 18:15, Matthias Brugger wrote:
On Mon, Jan 29, 2024 at 10:04:50PM +0100, Heinrich Schuchardt wrote:
The string section of the different SMBIOS structures is always terminated
by two NUL bytes even if there is no string at all. This is described in
section 6.1.3 "Text string" of the SMBIOS 3.7.0 specification.
Signed-off-by: Heinrich Schuchardt
I send the very same patch some years ago [1], unfortunately it got
somehow lost. Happy to see you trying to fix the same problem, so:
Reviewed-by: Matthias Brugger
[1]
https://patchwork.ozlabs.org/project/uboot/patch/20210406090435.19357-1-matthias@kernel.org/
Thanks for the pointer. I assume not answering Simon's question lead to
your patch not being merged.
To answer it:
>> But where are the \0 bytes
>> actually written? Perhaps that should be in smbios_set_eos()?
We have defined SMBIOS_STRUCT_EOS_BYTES as 2 and we have an array
char eos[SMBIOS_STRUCT_EOS_BYTES];
at the end of each SMBIOS structure.
We call memset(t, 0, sizeof(struct smbios_typeX)); for each table.
This is enough to ensure two zero bytes exist if there are no strings.
Best regards
Heinrich
---
lib/smbios.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/smbios.c b/lib/smbios.c
index 7bd9805fec0..81908e89610 100644
--- a/lib/smbios.c
+++ b/lib/smbios.c
@@ -311,6 +311,9 @@ int smbios_update_version(const char *version)
*/
static int smbios_string_table_len(const struct smbios_ctx *ctx)
{
+ /* If the structure contains no string it is followed by two NUL bytes
*/
+ if (ctx->next_ptr == ctx->eos)
+ return 2;
/* Allow for the final \0 after all strings */
return (ctx->next_ptr + 1) - ctx->eos;
}
--
2.43.0
Re: [PATCH 17/18] rockchip: rk3588: bind MMC controllers in U-Boot proper pre-reloc
Hi Kever,
On 1/29/24 11:35, Kever Yang wrote:
Hi Quentin,
On 2024/1/27 00:18, Quentin Schulz wrote:
Hi Kever,
On 1/26/24 11:56, Kever Yang wrote:
Hi Quentin,
On 2024/1/26 17:32, Quentin Schulz wrote:
Hi Kever,
On 1/26/24 09:58, Kever Yang wrote:
Hi Quentin,
On 2024/1/24 19:04, Quentin Schulz wrote:
Hi Kever,
On 1/24/24 11:35, Kever Yang wrote:
Hi Quentin,
On 2024/1/23 22:49, Quentin Schulz wrote:
From: Quentin Schulz
Since commit 9e644284ab81 ("dm: core: Report bootph-pre-ram/sram
node as
pre-reloc after relocation"), bootph-pre-ram doesn't make U-Boot
proper
bind the device before relocation.
While this is usually not much of an issue, it is when there's a
lookup
for devices by code running before the relocation. Such is the
case of
env_init() which calls env_driver_lookup() which calls
env_get_location() which is a weak symbol and may call
arch_env_get_location() also a weak symbol. Those are two
functions that
may traverse UCLASS to find some devices (e.g.
board/theobroma-systems/common/common.c:arch_env_get_location()).
This sounds like we need to update arch_env_get_location()
instead of enable mmc driver
before relocate, because you we don't really need the mmc driver
works here, there is no
access requirement to mmc at this point, right?
All Rockchip SoCs except RK3588(S) and RK356x have it done this
way, a little bit of consistency wouldn't hurt :)
My point is not about you can not enabe the emmc before relocate,
maybe I'm not clear enough for the reason.
All the driver bind/probed before the relocation will have to do
the init sequence again later after relocation.
The emmc driver cost pretty much time at init, we should avoid to
duplicate the init process if possible.
For this patch, you want to make it pre-relocate because you want
to make sure the emmc is available for ENVL_MMC,
but there is no read or write requirement to the emmc at this
point, which means we don't have to init the emmc at this point,
maybe we can check if the driver is enable if enough.
Now I need to know which SoC we are booting at build time so I can
check which drivers are supposed to be built, check those symbols
are enabled, then traverse the Device Tree with hardcoded DT node to
locations of MMC, SPI flash controllers, check if those are enabled
and finger-cross that those drivers will actually bind/probe
properly later on. That's A LOT of checks to be made.
This is not what I want to say.
What I mean is something like this for arch_env_get_location() is
enough, you don't have to bind/probe the emmc for env.
1623 if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC) &&
IS_ENABLED(CONFIG_MMC))
1624 return ENVL_MMC;
I do need to know if the device we loaded U-Boot proper from is an MMC
device or a SPI flash, so this is not enough for arch_env_get_location().
I could do it in a hack-ish way though and check if the U-Boot proper
load medium DT node name starts with /mmc, or /spi and if neither,
then return NOWHERE, but then we lose the ability of returning NOWHERE
if the driver wasn't compiled in or the device didn't bind in
pre-reloc, we're missing some failsafe mechanism I could have with
this patch :)
[...]
For the feature record "spl-boot-device" in SPL and read in out in
U-Boot proper, and then Swap mmc0 and mmc1 in boot_targets if
booted from SD-Card.
It's OK for Theobroma-Systems's board to enable it, but seems not
also required by other boards.
Usually we consider the system in two stage: bootloader/BIOS
stage(including all firmware before kernel) and OS stage(including
kernel and Linux/Android OS),
and for those boards(eg. PC like) do have two different storage
medium, they put bootloader in SPI flash and put OS firmware in
other storage like emmc/SSD/SDcard.
In this case the U-Boot boot target does not need to know where
it's from;
in another case which supports firmware update from SD card, the
U-Boot boot target needs to set SDCard as highest priority, also no
need to know where the U-Boot from.
So... this means we need a different U-Boot if we're booting from SD
card so it can know which boot target to use by default? Or a
different environment for SD card? or requiring the user to stop the
boot process and manually change the priority? Or what are you
suggesting?
No, we don't need a different U-Boot, we can always set SD card boot
first in boot target in all case, if SD card don't have an available
firmware it will fall back to use eMMC, this works for the board I have.
Maybe I didn't understand correctly why you have to do "Swap mmc0 and
mmc1 in boot_targets if booted from SD-Card"?
I think I got things mixed up and this was not a necessary discussion.
But since we're here, I will try to explain what we want to do with
the whole process on Theobroma's boards.
arch_env_get_location() is the only one impacted by this patch (as far
as I could tell).
[PATCH] toradex: tdx-cfg-block: add 0086 i.mx8m mini sku
From: Joao Paulo Goncalves
Add new product id 0086 Verdin iMX8M Mini DualLite 2GB IT.
Signed-off-by: Joao Paulo Goncalves
---
Hello,
The change was based on u-boot-imx/master-next because of [1].
[1]
https://lore.kernel.org/u-boot/20240122200930.673447-1-jpaulo.silvagoncal...@gmail.com/
Best Regards,
Joao Paulo Goncalves
board/toradex/common/tdx-cfg-block.c | 1 +
board/toradex/common/tdx-cfg-block.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/board/toradex/common/tdx-cfg-block.c
b/board/toradex/common/tdx-cfg-block.c
index 3f2f6b94391..4a7de5483d2 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -156,6 +156,7 @@ const struct toradex_som toradex_modules[] = {
[83] = { "Apalis iMX6Q 1GB",
TARGET_IS_ENABLED(APALIS_IMX6) },
[84] = { "Apalis iMX6D 1GB IT",
TARGET_IS_ENABLED(APALIS_IMX6) },
[85] = { "Apalis iMX6Q 2GB IT",
TARGET_IS_ENABLED(APALIS_IMX6) },
+ [86] = { "Verdin iMX8M Mini DualLite 2GB IT",
TARGET_IS_ENABLED(VERDIN_IMX8MM) },
};
struct pid4list {
diff --git a/board/toradex/common/tdx-cfg-block.h
b/board/toradex/common/tdx-cfg-block.h
index b783537ce76..021cc21b5e2 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -111,6 +111,7 @@ enum {
APALIS_IMX6Q_NOWINCE,
APALIS_IMX6D_IT_NOWINCE,
APALIS_IMX6Q_IT_NOWINCE, /* 85 */
+ VERDIN_IMX8MMDL_2G_IT,
};
enum {
--
2.34.1
Re: [PATCH 4/7] smbios: string table always needs two terminating NUL bytes
On Mon, Jan 29, 2024 at 10:04:50PM +0100, Heinrich Schuchardt wrote:
> The string section of the different SMBIOS structures is always terminated
> by two NUL bytes even if there is no string at all. This is described in
> section 6.1.3 "Text string" of the SMBIOS 3.7.0 specification.
>
> Signed-off-by: Heinrich Schuchardt
I send the very same patch some years ago [1], unfortunately it got
somehow lost. Happy to see you trying to fix the same problem, so:
Reviewed-by: Matthias Brugger
[1]
https://patchwork.ozlabs.org/project/uboot/patch/20210406090435.19357-1-matthias@kernel.org/
> ---
> lib/smbios.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/lib/smbios.c b/lib/smbios.c
> index 7bd9805fec0..81908e89610 100644
> --- a/lib/smbios.c
> +++ b/lib/smbios.c
> @@ -311,6 +311,9 @@ int smbios_update_version(const char *version)
> */
> static int smbios_string_table_len(const struct smbios_ctx *ctx)
> {
> + /* If the structure contains no string it is followed by to NUL bytes */
> + if (ctx->next_ptr == ctx->eos)
> + return 2;
> /* Allow for the final \0 after all strings */
> return (ctx->next_ptr + 1) - ctx->eos;
> }
> --
> 2.43.0
Re: [PATCH v3 3/3] cmd: rng: Add rng list command
On Wed, Jan 31, 2024 at 02:14:26PM +, Weizhao Ouyang wrote:
> The 'rng list' command probes all RNG devices and list those devices
> that are successfully probed. Also update the help info.
>
> Reviewed-by: Heinrich Schuchardt
> Signed-off-by: Weizhao Ouyang
Reviewed-by: Matthias Brugger
> ---
> cmd/rng.c | 23 ++-
> 1 file changed, 18 insertions(+), 5 deletions(-)
>
> diff --git a/cmd/rng.c b/cmd/rng.c
> index 52f722c7af..b073a6c849 100644
> --- a/cmd/rng.c
> +++ b/cmd/rng.c
> @@ -19,6 +19,22 @@ static int do_rng(struct cmd_tbl *cmdtp, int flag, int
> argc, char *const argv[])
> struct udevice *dev;
> int ret = CMD_RET_SUCCESS;
>
> + if (argc == 2 && !strcmp(argv[1], "list")) {
> + int idx = 0;
> +
> + uclass_foreach_dev_probe(UCLASS_RNG, dev) {
> + idx++;
> + printf("RNG #%d - %s\n", dev->seq_, dev->name);
> + }
> +
> + if (!idx) {
> + log_err("No RNG device\n");
> + return CMD_RET_FAILURE;
> + }
> +
> + return CMD_RET_SUCCESS;
> + }
> +
> switch (argc) {
> case 1:
> devnum = 0;
> @@ -56,12 +72,9 @@ static int do_rng(struct cmd_tbl *cmdtp, int flag, int
> argc, char *const argv[])
> return ret;
> }
>
> -U_BOOT_LONGHELP(rng,
> - "[dev [n]]\n"
> - " - print n random bytes(max 64) read from dev\n");
> -
> U_BOOT_CMD(
> rng, 3, 0, do_rng,
> "print bytes from the hardware random number generator",
> - rng_help_text
> + "list - list all the probed rng devices\n"
> + "rng [dev] [n]- print n random bytes(max 64) read from dev\n"
> );
> --
> 2.39.2
Re: [PATCH v3 2/3] driver: rng: Fix SMCCC TRNG crash
On Wed, Jan 31, 2024 at 02:14:25PM +, Weizhao Ouyang wrote:
> Fix a SMCCC TRNG null pointer crash due to a failed smccc feature
> binding.
>
> Fixes: 53355bb86c25 ("drivers: rng: add smccc trng driver")
> Reviewed-by: Heinrich Schuchardt
> Signed-off-by: Weizhao Ouyang
Reviewed-by: Matthias Brugger
> ---
> v3: add Fixes tag
> ---
> drivers/rng/smccc_trng.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/rng/smccc_trng.c b/drivers/rng/smccc_trng.c
> index 3a4bb33941..3087cb991a 100644
> --- a/drivers/rng/smccc_trng.c
> +++ b/drivers/rng/smccc_trng.c
> @@ -166,7 +166,7 @@ static int smccc_trng_probe(struct udevice *dev)
> struct smccc_trng_priv *priv = dev_get_priv(dev);
> struct arm_smccc_res res;
>
> - if (!(smccc_trng_is_supported(smccc->invoke_fn)))
> + if (!smccc || !(smccc_trng_is_supported(smccc->invoke_fn)))
> return -ENODEV;
>
> /* At least one of 64bit and 32bit interfaces is available */
> --
> 2.39.2
[GIT PULL] rpi: updates for v2024.04
Hi Tom, Here come a small set of patches for v2024.04 for the RaspberryPi. It adds basic support for RPi5 to be able to boot on a SD card. You can find the passing tests here: https://source.denx.de/u-boot/custodians/u-boot-raspberrypi/-/pipelines/19512 It's the same commit ID as the tag, although it's not the same test-run. Regards, Matthias --- The following changes since commit 6faba41927bdc8973b59678649ef83c564cc421e: Prepare v2024.04-rc1 (2024-01-29 20:53:19 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-raspberrypi.git tags/rpi-next-2024.04 for you to fetch changes up to 12d479d01849c164020e17c3ae921f974b96372d: configs: rpi_arm64: build position independent code (2024-01-30 17:40:13 +0100) Add RaspberryPi5 basic support. Dmitry Malkin (2): rpi5: add initial memory map for bcm2712 rpi5: Use devicetree as alternative way to read IO base addresses Ivan T. Ivanov (5): rpi5: Use devicetree to retrieve board revision bcm2835: Dynamically calculate bytes per pixel parameter mmc: bcmstb: Add support for bcm2712 SD controller configs: rpi_arm64: enable SDHCI BCMSTB driver configs: rpi_arm64: build position independent code arch/arm/mach-bcm283x/include/mach/base.h | 5 +- arch/arm/mach-bcm283x/include/mach/mbox.h | 3 +- arch/arm/mach-bcm283x/include/mach/sdhci.h | 3 +- arch/arm/mach-bcm283x/include/mach/timer.h | 3 +- arch/arm/mach-bcm283x/include/mach/wdog.h | 3 +- arch/arm/mach-bcm283x/init.c | 74 ++ board/raspberrypi/rpi/rpi.c| 22 +++-- configs/rpi_arm64_defconfig| 3 +- drivers/mmc/bcmstb_sdhci.c | 64 -- drivers/video/bcm2835.c| 18 +++- 10 files changed, 171 insertions(+), 27 deletions(-)
Re: [PULL] u-boot-at91-2024.04-a
On Wed, Jan 31, 2024 at 05:43:49PM +0200, Eugen Hristev wrote: > Hello Tom, > > Please pull tag u-boot-at91-2024.04-a , the first set of at91 features > for 2024.04 cycle. > > This set includes some DT alignments and solves a compile issue for custom > nand > defconfigs. > > Thanks, > Eugen > > The following changes since commit 3c04fcf3137d5f694d52b8f355373e4baabe5f78: > > Merge patch series "k3-j721e: beagleboneai: Fix USB" (2024-01-20 11:39:13 > -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-at91.git > tags/u-boot-at91-2024.04-a > > for you to fetch changes up to a1c6b08274e18e4afc0f78a2f63609880aa7ef08: > > mtd: nand: raw: atmel: Remove duplicate definitions (2024-01-22 06:05:26 > +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v1] qemu-arm: round down memory to multiple of 2MB
Hello Ard,
Just a quick follow-up for this old thread,
I've again stumbled upon the same issue recently and it turned out
that I've already sent a fix for that here :)
Considering Heinrich's comment about memory granularity, does it still make
sense to land this patch? If not, what objections/suggestions do you
have in mind?
Thanks!
Regards,
Igor
On Thu, Feb 11, 2021 at 4:39 PM Igor Opaniuk wrote:
>
> Hi Heinrich,
>
> On Thu, Feb 11, 2021 at 5:34 PM Heinrich Schuchardt
> wrote:
> >
> > On 11.02.21 15:56, Ard Biesheuvel wrote:
> > > On Thu, 11 Feb 2021 at 15:18, Heinrich Schuchardt
> > > wrote:
> > >>
> > >> On 11.02.21 13:04, Igor Opaniuk wrote:
> > >>> From: Igor Opaniuk
> > >>>
> > >>> When LPAE is enabled, 1:1 mapping is created using 2 MB blocks.
> > >>> In case amount of memory provided to QEMU is not multiple
> > >>> of 2 MB, round down the amount of available memory to avoid hang
> > >>> during MMU initialization.
> > >>>
> > >>> How to reproduce:
> > >>> qemu-system-arm -machine virt -m 1058 -nographic -bios u-boot.bin -
> > >>> boots
> > >>> qemu-system-arm -machine virt -m 1057 -nographic -bios u-boot.bin -
> > >>> hangs
> > >>>
> > >>> DRAM: 1 GiB
> > >>> initcall: 60011df8
> > >>> initcall: 60011904
> > >>> New Stack Pointer is: 80fffe90
> > >>> initcall: 60011a20
> > >>> initcall: 60011bcc
> > >>> initcall: 60011bd4
> > >>> initcall: 600119b4
> > >>> Relocation Offset is: 22042000
> > >>> Relocating to 82042000, new gd at 81001ed0, sp at 80fffe90
> > >>> initcall: 60011b8c
> > >>> initcall: 82053ea0
> > >>> initcall: 82053ea8
> > >>> initcall: 60012040 (relocated to 82054040)
> > >>> dram_bank_mmu_setup: bank: 0
> > >>> --- hang here during mmu init ---
> > >>>
> > >>> Fixes: 3fa914af82("arm: qemu: implement enable_caches()")
> > >>> Signed-off-by: Igor Opaniuk
> > >>>
> > >>> ---
> > >>>
> > >>> board/emulation/qemu-arm/qemu-arm.c | 12
> > >>> 1 file changed, 12 insertions(+)
> > >>>
> > >>> diff --git a/board/emulation/qemu-arm/qemu-arm.c
> > >>> b/board/emulation/qemu-arm/qemu-arm.c
> > >>> index aa68bef469..841dd7af0e 100644
> > >>> --- a/board/emulation/qemu-arm/qemu-arm.c
> > >>> +++ b/board/emulation/qemu-arm/qemu-arm.c
> > >>> @@ -84,6 +84,18 @@ int dram_init(void)
> > >>> if (fdtdec_setup_mem_size_base() != 0)
> > >>> return -EINVAL;
> > >>>
> > >>> + /*
> > >>> + * When LPAE is enabled (ARMv7),
> > >>> + * 1:1 mapping is created using 2 MB blocks.
> > >>> + *
> > >>> + * In case amount of memory provided to QEMU
> > >>> + * is not multiple of 2 MB, round down the amount
> > >>> + * of available memory to avoid hang during MMU
> > >>> + * initialization.
> > >>> + */
> > >>> + if (CONFIG_IS_ENABLED(ARMV7_LPAE))
> > >>> + gd->ram_size -= (gd->ram_size % 0x20);
> > >>
> > >> Is the problem LPAE specific?
> > >> Couldn't you provoke same problem using an odd memory size without LPAE,
> > >> e.g qemu-system-arm -m 536870908 (512 MiB - 4)?
> > >>
> > >
> > > The above value means 512 GiB - 4 MiB, so that shouldn't be a problem.
> > > I don't think QEMU's -m option takes fractional megabyte values.
> > >
> >
> > $ qemu-system-arm -machine virt -cpu cortex-a15 -m 15k \
> > -bios denx/u-boot.bin -nographic
> >
> > => fdt addr $fdt_addr
> > => fdt print /memory@4000
> > memory@4000 {
> > reg = <0x 0x4000 0x 0x061aa000>;
> > device_type = "memory";
> > };
> >
> > Granularity seems to be 0x2000 = 8 KiB.
> I've just run some tests (including the mem=15k ) with LPAE disabled
> and haven't faced any issues:
>
> $ cat .config | grep LPAE
> # CONFIG_ARMV7_LPAE is not set
>
> $ qemu-system-arm -machine virt -m 1057 -nographic -bios u-boot.bin
> U-Boot 2021.04-rc1-01218-g85e959f09c-dirty (Feb 11 2021 - 17:31:31 +0200)
>
> DRAM: 1 GiB
> Flash: 128 MiB
> ...
> =>
>
> $ qemu-system-arm -machine virt -m 1058 -nographic -bios u-boot.bin
>
> U-Boot 2021.04-rc1-01218-g85e959f09c-dirty (Feb 11 2021 - 17:31:31 +0200)
>
> DRAM: 1 GiB
> Flash: 128 MiB
> ...
> =>
>
> $ qemu-system-arm -machine virt -m 15k -nographic -bios u-boot.bin
>
> U-Boot 2021.04-rc1-01218-g85e959f09c-dirty (Feb 11 2021 - 17:31:31 +0200)
> DRAM: 97.7 MiB
> Flash: 128 MiB
> ...
> =>
>
> >
> > Best regards
> >
> > Heinrich
>
> Regards,
> Igor
>
> --
> Best regards - Freundliche Grüsse - Meilleures salutations
>
> Igor Opaniuk
> Embedded Software Engineer
> T: +380 938364067
> E: igor.opan...@foundries.io
> W: www.foundries.io
--
Best regards - Freundliche Grüsse - Meilleures salutations
Igor Opaniuk
Senior Software Engineer, Embedded & Security
E: igor.opan...@foundries.io
W: www.foundries.io
[PULL] u-boot-at91-2024.04-a
Hello Tom, Please pull tag u-boot-at91-2024.04-a , the first set of at91 features for 2024.04 cycle. This set includes some DT alignments and solves a compile issue for custom nand defconfigs. Thanks, Eugen The following changes since commit 3c04fcf3137d5f694d52b8f355373e4baabe5f78: Merge patch series "k3-j721e: beagleboneai: Fix USB" (2024-01-20 11:39:13 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-at91.git tags/u-boot-at91-2024.04-a for you to fetch changes up to a1c6b08274e18e4afc0f78a2f63609880aa7ef08: mtd: nand: raw: atmel: Remove duplicate definitions (2024-01-22 06:05:26 +0200) First set of u-boot-at91 features for the 2024.04 cycle Alexander Dahl (4): ARM: dts: at91: sama5d2: Move sfr node ARM: dts: at91: sama5d2: Port ebi/nand nodes from linux ARM: dts: at91: sama5d2: Align more node names with Linux mtd: nand: raw: atmel: Remove duplicate definitions arch/arm/dts/sama5d2.dtsi | 74 +- drivers/mtd/nand/raw/atmel/pmecc.c | 3 -- 2 files changed, 65 insertions(+), 12 deletions(-)
Re: [PATCH 06/13] clk/qcom: sdm845: add USB clocks
On Wed, Jan 31, 2024 at 03:16:58PM +, Caleb Connolly wrote:
> @@ -121,6 +130,26 @@ static int sdm845_clk_enable(struct clk *clk)
>
> debug("%s: clk %s\n", __func__, sdm845_clks[clk->id].name);
>
> + switch (clk->id) {
> + case GCC_USB30_PRIM_MASTER_CLK:
> + gdsc_enable(priv->base + USB30_PRIM_GDSCR);
> + qcom_gate_clk_en(priv, GCC_USB_PHY_CFG_AHB2PHY_CLK);
> + /* These numbers are just pulled from the frequency tables in
> the Linux driver */
> + clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
> + (4.5 * 2) - 1, 0, 0, 1 << 8, 8);
> + clk_rcg_set_rate_mnd(priv->base,
> USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR,
> + 1, 0, 0, 0, 8);
> + clk_rcg_set_rate_mnd(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR,
> + 1, 0, 0, 0, 8);
> + case GCC_USB30_SEC_MASTER_CLK:
Is this supposed to break? Otherwise can we add a "fallthrough;"
annotation?
> + gdsc_enable(priv->base + USB30_SEC_GDSCR);
> + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK);
> +
> + qcom_gate_clk_en(priv, GCC_USB3_SEC_CLKREF_CLK);
> + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
> + break;
> + }
regards,
dan carpenter
Re: [PATCH 07/13] gpio: msm_gpio: add .set_flags op
On Wed, Jan 31, 2024 at 03:16:59PM +, Caleb Connolly wrote:
> diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
> index 80cd28bb231f..0230305af299 100644
> --- a/drivers/gpio/msm_gpio.c
> +++ b/drivers/gpio/msm_gpio.c
> @@ -72,6 +72,23 @@ static int msm_gpio_direction_output(struct udevice *dev,
> unsigned int gpio,
> return 0;
> }
>
> +static int msm_gpio_set_flags(struct udevice *dev, unsigned int gpio, ulong
> flags)
> +{
> + if (flags & GPIOD_IS_OUT_ACTIVE) {
> + return msm_gpio_direction_output(dev, gpio, 1);
> + } else if (flags & GPIOD_IS_OUT) {
> + return msm_gpio_direction_output(dev, gpio, 0);
> + } else if (flags & GPIOD_IS_IN) {
> + return msm_gpio_direction_input(dev, gpio);
^^
> + if (flags & GPIOD_PULL_UP)
> + return msm_gpio_set_value(dev, gpio, 1);
> + else if (flags & GPIOD_PULL_DOWN)
> + return msm_gpio_set_value(dev, gpio, 0);
These lines are unreachable code.
> + }
> +
> + return 0;
> +}
regards,
dan carpenter
[PATCH 13/13] qcom_defconfig: enable USB
Enable support for the DWC3 USB controller and required dependencies for Qualcomm boards, specifically the DB845c: * IOMMU / SMMU * USB high-speed PHYs * Mass storage and ACM gadgets Signed-off-by: Caleb Connolly --- configs/qcom_defconfig | 15 +++ 1 file changed, 15 insertions(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 3935fe2ef59f..dedd5f20b719 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -13,6 +13,7 @@ CONFIG_BOOTSTD_FULL=y CONFIG_BOOTDELAY=1 CONFIG_USE_PREBOOT=y CONFIG_SYS_CBSIZE=512 +# CONFIG_SYS_DEVICE_NULLDEV is not set CONFIG_LOG_MAX_LEVEL=9 CONFIG_LOG_DEFAULT_LEVEL=4 # CONFIG_DISPLAY_CPUINFO is not set @@ -26,6 +27,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_UFS=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y CONFIG_CMD_CAT=y CONFIG_CMD_BMP=y CONFIG_CMD_FAT=y @@ -35,6 +38,7 @@ CONFIG_EFI_PARTITION=y CONFIG_OF_LIVE=y # CONFIG_NET is not set # CONFIG_OFNODE_MULTI_TREE is not set +CONFIG_DM_WARN=y CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y CONFIG_CLK_QCOM_QCS404=y @@ -43,14 +47,21 @@ CONFIG_MSM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y CONFIG_DM_KEYBOARD=y CONFIG_BUTTON_KEYBOARD=y +CONFIG_IOMMU=y +CONFIG_QCOM_HYP_SMMU=y +CONFIG_MISC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_MSM=y CONFIG_PHY=y +CONFIG_PHY_QCOM_QUSB2=y +CONFIG_PHY_QCOM_USB_HS_7NM=y CONFIG_PINCTRL=y CONFIG_PINCTRL_QCOM_QCS404=y CONFIG_PINCTRL_QCOM_SDM845=y CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_SCSI=y CONFIG_MSM_SERIAL=y CONFIG_MSM_GENI_SERIAL=y @@ -61,7 +72,11 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ACM=y CONFIG_UFS=y CONFIG_VIDEO=y # CONFIG_VIDEO_FONT_8X16 is not set -- 2.43.0
[PATCH 12/13] qcom_defconfig: enable livetree
Qualcomm FDTs are on the larger size, and with the addition of DT modifications during board_init() it makes sense to enable OF_LIVE globally. The cost of building the tree should be offset by the increased efficiency at which we can walk it. Some rough measurements with CONFIG_BOOTSTAGE suggests that this might add 0.1-0.2ms to the boot-to-console time. However the reset-to-reset timer difference is in the range of 0.5ms so this could just be noise. Suffice to say, no significant slow down. Signed-off-by: Caleb Connolly --- configs/qcom_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 659775852c07..3935fe2ef59f 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -32,7 +32,9 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_LOG=y CONFIG_EFI_PARTITION=y +CONFIG_OF_LIVE=y # CONFIG_NET is not set +# CONFIG_OFNODE_MULTI_TREE is not set CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y CONFIG_CLK_QCOM_QCS404=y -- 2.43.0
[PATCH 11/13] qcom_defconfig: regenerate with savedefconfig
Prepare to enable some additional features. Signed-off-by: Caleb Connolly --- configs/qcom_defconfig | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 3c6bdc2071b2..659775852c07 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -12,13 +12,13 @@ CONFIG_BOOTSTD_FULL=y # CONFIG_BOOTMETH_SCRIPT is not set CONFIG_BOOTDELAY=1 CONFIG_USE_PREBOOT=y +CONFIG_SYS_CBSIZE=512 CONFIG_LOG_MAX_LEVEL=9 CONFIG_LOG_DEFAULT_LEVEL=4 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_CBSIZE=512 CONFIG_CMD_BOOTMENU=y CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y @@ -33,6 +33,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_LOG=y CONFIG_EFI_PARTITION=y # CONFIG_NET is not set +CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y CONFIG_CLK_QCOM_QCS404=y CONFIG_CLK_QCOM_SDM845=y @@ -40,7 +41,6 @@ CONFIG_MSM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y CONFIG_DM_KEYBOARD=y CONFIG_BUTTON_KEYBOARD=y -CONFIG_BUTTON_QCOM_PMIC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_MSM=y CONFIG_PHY=y @@ -50,7 +50,6 @@ CONFIG_PINCTRL_QCOM_SDM845=y CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y CONFIG_SCSI=y -CONFIG_DM_SCSI=y CONFIG_MSM_SERIAL=y CONFIG_MSM_GENI_SERIAL=y CONFIG_SPMI_MSM=y -- 2.43.0
[PATCH 10/13] dts: sdm845-db845c: add u-boot fixups
The USB VBUS supply for the type-A port is enabled via a GPIO regulator.
This is incorrectly modelled in Linux where only the PCIe dependency is
expressed. Add a U-Boot specific dtsi snippet so that this supply will
get enabled when initialising USB.
Signed-off-by: Caleb Connolly
---
arch/arm/dts/sdm845-db845c-u-boot.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/sdm845-db845c-u-boot.dtsi
b/arch/arm/dts/sdm845-db845c-u-boot.dtsi
new file mode 100644
index ..3c83e21251c4
--- /dev/null
+++ b/arch/arm/dts/sdm845-db845c-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* This GPIO must be turned on to enable the 5v VBUS
+ * supply on the USB port.
+ */
+_2_dwc3 {
+ vbus-supply = <_3p3v_dual>;
+};
--
2.43.0
[PATCH 09/13] mach-snapdragon: fixup USB nodes
We don't support USB super-speed in U-Boot yet, we lack the SS PHY
drivers, however from my testing even with a PHY driver there seem to be
other issues when talking to super-speed peripherals.
In pursuit of maintaining upstream DT compatibility, and simplifying
porting for new devices, let's implement the DT fixups necessary to
configure USB in high-speed only mode at runtime. The pattern is
identical for all Qualcomm boards that use the Synaptics DWC3
controller:
* Add an additional property on the Qualcomm wrapper node
* Remove the super-speed phy phandle and phy-name entries.
Signed-off-by: Caleb Connolly
---
arch/arm/mach-snapdragon/board.c | 88
1 file changed, 88 insertions(+)
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index ca300dc843a9..44925e369d8e 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -146,6 +146,93 @@ int board_usb_init(int index, enum usb_init_type init)
return 0;
}
+/* U-Boot only supports USB high-speed mode on Qualcomm platforms with DWC3
+ * USB controllers. Rather than requiring source level DT changes, we fix up
+ * DT here. This improves compatibility with upstream DT and simplifies the
+ * porting process for new devices.
+ */
+#if CONFIG_IS_ENABLED(OF_LIVE)
+static int fixup_qcom_dwc3(struct device_node *glue_np)
+{
+ struct device_node *dwc3;
+ int ret, len, hsphy_idx = 1;
+ const __be32 *phandles;
+ const char *second_phy_name;
+
+ debug("Fixing up %s\n", glue_np->name);
+
+ /* Tell the glue driver to configure the wrapper for high-speed only
operation */
+ ret = of_write_prop(glue_np, "qcom,select-utmi-as-pipe-clk", NULL, 0);
+ if (ret) {
+ log_err("Failed to add property 'qcom,select-utmi-as-pipe-clk':
%d\n", ret);
+ return ret;
+ }
+
+ /* Find the DWC3 node itself */
+ dwc3 = of_find_compatible_node(glue_np, NULL, "snps,dwc3");
+ if (!dwc3) {
+ log_err("Failed to find dwc3 node\n");
+ return -ENOENT;
+ }
+
+ phandles = of_get_property(dwc3, "phys", );
+ len /= sizeof(*phandles);
+ if (len == 1) {
+ log_debug("Only one phy, not a superspeed controller\n");
+ return 0;
+ }
+
+ /* Figure out if the superspeed phy is present and if so then which phy
is it? */
+ ret = of_property_read_string_index(dwc3, "phy-names", 1,
_phy_name);
+ if (ret == -ENODATA) {
+ log_debug("Only one phy, not a super-speed controller\n");
+ return 0;
+ } else if (ret) {
+ log_err("Failed to read second phy name: %d\n", ret);
+ return ret;
+ }
+
+ if (!strncmp("usb3-phy", second_phy_name, strlen("usb3-phy"))) {
+ log_debug("Second phy isn't superspeed (is '%s') assuming first
phy is SS\n",
+ second_phy_name);
+ hsphy_idx = 0;
+ }
+
+ /* Overwrite the "phys" property to only contain the high-speed phy */
+ ret = of_write_prop(dwc3, "phys", sizeof(*phandles), phandles +
hsphy_idx);
+ if (ret) {
+ log_err("Failed to overwrite 'phys' property: %d\n", ret);
+ return ret;
+ }
+
+ /* Overwrite "phy-names" to only contain a single entry */
+ ret = of_write_prop(dwc3, "phy-names", strlen("usb2-phy"), "usb2-phy");
+ if (ret) {
+ log_err("Failed to overwrite 'phy-names' property: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void fixup_usb_nodes(void)
+{
+ struct device_node *glue_np = NULL;
+ int ret;
+
+ while ((glue_np = of_find_compatible_node(glue_np, NULL, "qcom,dwc3")))
{
+ ret = fixup_qcom_dwc3(glue_np);
+ if (ret)
+ log_warning("Failed to fixup node %s: %d\n",
glue_np->name, ret);
+ }
+}
+#else
+static void fixup_usb_nodes(void)
+{
+ log_debug("Unable to dynamically fixup USB nodes, please enable
CONFIG_OF_LIVE\n");
+}
+#endif
+
/*
* Some boards still need board specific init code, they can implement that by
* overriding this function.
@@ -159,6 +246,7 @@ void __weak qcom_board_init(void)
int board_init(void)
{
show_psci_version();
+ fixup_usb_nodes();
qcom_board_init();
return 0;
}
--
2.43.0
[PATCH 08/13] serial: msm-geni: support livetree
When using OF_LIVE, the debug UART driver won't be probed if it's a
subnode of the geni-se-qup controller. Add a NOP driver for the
controller to correctly discover its child nodes.
Signed-off-by: Caleb Connolly
---
drivers/serial/serial_msm_geni.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index e5c3dcffc1c6..6455b0fff63c 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -606,6 +606,19 @@ U_BOOT_DRIVER(serial_msm_geni) = {
.flags = DM_FLAG_PRE_RELOC,
};
+static const struct udevice_id geniqup_ids[] = {
+ { .compatible = "qcom,geni-se-qup" },
+ { }
+};
+
+U_BOOT_DRIVER(geni_se_qup) = {
+ .name = "geni-se-qup",
+ .id = UCLASS_NOP,
+ .of_match = geniqup_ids,
+ .bind = dm_scan_fdt_dev,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
#ifdef CONFIG_DEBUG_UART_MSM_GENI
static struct msm_serial_data init_serial_data = {
--
2.43.0
[PATCH 06/13] clk/qcom: sdm845: add USB clocks
Most devices only initialise the USB clocks for us if we boot via
"fastboot boot", add the missing clock configuration to get both USB
ports working regardless of the bootloader state.
Signed-off-by: Caleb Connolly
---
drivers/clk/qcom/clock-sdm845.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
index 5d6c0cdaeee5..e5033cacb216 100644
--- a/drivers/clk/qcom/clock-sdm845.c
+++ b/drivers/clk/qcom/clock-sdm845.c
@@ -21,6 +21,13 @@
#define SE9_UART_APPS_CMD_RCGR 0x18148
+#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf018
+#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf030
+#define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf05c
+
+#define USB30_PRIM_GDSCR 0xf004
+#define USB30_SEC_GDSCR 0x10004
+
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
@@ -57,6 +64,8 @@ static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate)
}
static const struct gate_clk sdm845_clks[] = {
+ GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK,0x82020, 0x0001),
+ GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x05030, 0x0001),
GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK,0x5200c, 0x0400),
GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK,0x5200c, 0x0800),
GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK,0x5200c, 0x1000),
@@ -121,6 +130,26 @@ static int sdm845_clk_enable(struct clk *clk)
debug("%s: clk %s\n", __func__, sdm845_clks[clk->id].name);
+ switch (clk->id) {
+ case GCC_USB30_PRIM_MASTER_CLK:
+ gdsc_enable(priv->base + USB30_PRIM_GDSCR);
+ qcom_gate_clk_en(priv, GCC_USB_PHY_CFG_AHB2PHY_CLK);
+ /* These numbers are just pulled from the frequency tables in
the Linux driver */
+ clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
+(4.5 * 2) - 1, 0, 0, 1 << 8, 8);
+ clk_rcg_set_rate_mnd(priv->base,
USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR,
+1, 0, 0, 0, 8);
+ clk_rcg_set_rate_mnd(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR,
+1, 0, 0, 0, 8);
+ case GCC_USB30_SEC_MASTER_CLK:
+ gdsc_enable(priv->base + USB30_SEC_GDSCR);
+ qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK);
+
+ qcom_gate_clk_en(priv, GCC_USB3_SEC_CLKREF_CLK);
+ qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
+ break;
+ }
+
qcom_gate_clk_en(priv, clk->id);
return 0;
--
2.43.0
[PATCH 07/13] gpio: msm_gpio: add .set_flags op
The .direction_input and .direction_output ops are deprecated, and don't
seem to behave properly for us. Implement our own .set_flags op to
handle this correctly.
Signed-off-by: Caleb Connolly
---
drivers/gpio/msm_gpio.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
index 80cd28bb231f..0230305af299 100644
--- a/drivers/gpio/msm_gpio.c
+++ b/drivers/gpio/msm_gpio.c
@@ -72,6 +72,23 @@ static int msm_gpio_direction_output(struct udevice *dev,
unsigned int gpio,
return 0;
}
+static int msm_gpio_set_flags(struct udevice *dev, unsigned int gpio, ulong
flags)
+{
+ if (flags & GPIOD_IS_OUT_ACTIVE) {
+ return msm_gpio_direction_output(dev, gpio, 1);
+ } else if (flags & GPIOD_IS_OUT) {
+ return msm_gpio_direction_output(dev, gpio, 0);
+ } else if (flags & GPIOD_IS_IN) {
+ return msm_gpio_direction_input(dev, gpio);
+ if (flags & GPIOD_PULL_UP)
+ return msm_gpio_set_value(dev, gpio, 1);
+ else if (flags & GPIOD_PULL_DOWN)
+ return msm_gpio_set_value(dev, gpio, 0);
+ }
+
+ return 0;
+}
+
static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
@@ -90,10 +107,8 @@ static int msm_gpio_get_function(struct udevice *dev,
unsigned int gpio)
}
static const struct dm_gpio_ops gpio_msm_ops = {
- .direction_input= msm_gpio_direction_input,
- .direction_output = msm_gpio_direction_output,
+ .set_flags = msm_gpio_set_flags,
.get_value = msm_gpio_get_value,
- .set_value = msm_gpio_set_value,
.get_function = msm_gpio_get_function,
};
--
2.43.0
[PATCH 04/13] clk/qcom: use offsets for RCG registers
The RCG registers always have the same offsets, so only store the base
CMD register address and calculate the others relative to that.
Signed-off-by: Caleb Connolly
---
drivers/clk/qcom/clock-apq8016.c | 39 +
drivers/clk/qcom/clock-apq8096.c | 28 +
drivers/clk/qcom/clock-qcom.c| 22 +++
drivers/clk/qcom/clock-qcom.h| 16 +++---
drivers/clk/qcom/clock-qcs404.c | 121 +--
drivers/clk/qcom/clock-sdm845.c | 16 +-
6 files changed, 39 insertions(+), 203 deletions(-)
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index 9de0ad5ed32d..67d2d108326c 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -23,11 +23,7 @@
#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
#define SDCC_BCR(n)((n * 0x1000) + 0x41000)
-#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004)
-#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008)
-#define SDCC_M(n) ((n * 0x1000) + 0x4100C)
-#define SDCC_N(n) ((n * 0x1000) + 0x41010)
-#define SDCC_D(n) ((n * 0x1000) + 0x41014)
+#define SDCC_CMD_RCGR(n) (((n + 1) * 0x1000) + 0x41004)
#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018)
#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C)
@@ -38,31 +34,10 @@
#define BLSP1_UART2_BCR(0x3028)
#define BLSP1_UART2_APPS_CBCR (0x302C)
#define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
-#define BLSP1_UART2_APPS_CFG_RCGR (0x3038)
-#define BLSP1_UART2_APPS_M (0x303C)
-#define BLSP1_UART2_APPS_N (0x3040)
-#define BLSP1_UART2_APPS_D (0x3044)
/* GPLL0 clock control registers */
#define GPLL0_STATUS_ACTIVE BIT(17)
-static const struct bcr_regs sdc_regs[] = {
- {
- .cfg_rcgr = SDCC_CFG_RCGR(1),
- .cmd_rcgr = SDCC_CMD_RCGR(1),
- .M = SDCC_M(1),
- .N = SDCC_N(1),
- .D = SDCC_D(1),
- },
- {
- .cfg_rcgr = SDCC_CFG_RCGR(2),
- .cmd_rcgr = SDCC_CMD_RCGR(2),
- .M = SDCC_M(2),
- .N = SDCC_N(2),
- .D = SDCC_D(2),
- }
-};
-
static struct pll_vote_clk gpll0_vote_clk = {
.status = GPLL0_STATUS,
.status_bit = GPLL0_STATUS_ACTIVE,
@@ -86,7 +61,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot,
uint rate)
clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot));
/* 800Mhz/div, gpll0 */
- clk_rcg_set_rate_mnd(priv->base, _regs[slot], div, 0, 0,
+ clk_rcg_set_rate_mnd(priv->base, SDCC_CMD_RCGR(slot), div, 0, 0,
CFG_CLK_SRC_GPLL0, 8);
clk_enable_gpll0(priv->base, _vote_clk);
clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
@@ -94,14 +69,6 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot,
uint rate)
return rate;
}
-static const struct bcr_regs uart2_regs = {
- .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
- .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
- .M = BLSP1_UART2_APPS_M,
- .N = BLSP1_UART2_APPS_N,
- .D = BLSP1_UART2_APPS_D,
-};
-
/* UART: 115200 */
static int clk_init_uart(struct msm_clk_priv *priv)
{
@@ -109,7 +76,7 @@ static int clk_init_uart(struct msm_clk_priv *priv)
clk_enable_vote_clk(priv->base, _blsp1_ahb_clk);
/* 7372800 uart block clock @ GPLL0 */
- clk_rcg_set_rate_mnd(priv->base, _regs, 1, 144, 15625,
+ clk_rcg_set_rate_mnd(priv->base, BLSP1_UART2_APPS_CMD_RCGR, 1, 144,
15625,
CFG_CLK_SRC_GPLL0, 16);
/* Vote for gpll0 clock */
diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
index a4731613c5e0..479f9771a464 100644
--- a/drivers/clk/qcom/clock-apq8096.c
+++ b/drivers/clk/qcom/clock-apq8096.c
@@ -26,31 +26,15 @@
#define SDCC2_APPS_CBCR(0x14004) /* branch control */
#define SDCC2_AHB_CBCR (0x14008)
#define SDCC2_CMD_RCGR (0x14010)
-#define SDCC2_CFG_RCGR (0x14014)
-#define SDCC2_M(0x14018)
-#define SDCC2_N(0x1401C)
-#define SDCC2_D(0x14020)
#define BLSP2_AHB_CBCR (0x25004)
#define BLSP2_UART2_APPS_CBCR (0x29004)
#define BLSP2_UART2_APPS_CMD_RCGR (0x2900C)
-#define BLSP2_UART2_APPS_CFG_RCGR (0x29010)
-#define BLSP2_UART2_APPS_M (0x29014)
-#define BLSP2_UART2_APPS_N (0x29018)
-#define BLSP2_UART2_APPS_D (0x2901C)
/* GPLL0 clock control registers */
#define GPLL0_STATUS_ACTIVEBIT(30)
#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
-static const struct bcr_regs sdc_regs = {
- .cfg_rcgr = SDCC2_CFG_RCGR,
- .cmd_rcgr = SDCC2_CMD_RCGR,
- .M = SDCC2_M,
- .N = SDCC2_N,
- .D = SDCC2_D,
-};
-
[PATCH 05/13] clk/qcom: add gdsc_enable helper
Global Distributed Switch Controllers are per-domain switches which are
used to toggle power and clocks to an entire subsystem. They live under
the GCC block and might need to be enabled before certain clocks, so
handle them as part of the clock driver.
Linux models these as power domains, however this additional complexity
doesn't offer much benefit to us in U-Boot. For now they can be turned
on as-needed when a relevant clock is enabled.
In the future, we can add a power-domain driver to model these properly.
Signed-off-by: Caleb Connolly
---
drivers/clk/qcom/clock-qcom.c | 18 ++
drivers/clk/qcom/clock-qcom.h | 4
2 files changed, 22 insertions(+)
diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
index d912b673d0d8..0e89e7fe429e 100644
--- a/drivers/clk/qcom/clock-qcom.c
+++ b/drivers/clk/qcom/clock-qcom.c
@@ -39,6 +39,24 @@ void clk_enable_cbc(phys_addr_t cbcr)
;
}
+/* Global Distributed Switch Controller - these are
+ * breaker switches for entire peripherals like USB,
+ * they control power and clocks and must be turned on
+ * before configuring clocks or accessing the peripheral.
+ */
+void gdsc_enable(phys_addr_t gdscr)
+{
+ u32 count;
+
+ clrbits_le32(gdscr, GDSC_SW_COLLAPSE);
+ for (count = 0; count < 1500; count++) {
+ if (readl(gdscr) & GDSC_PWR_ON)
+ break;
+ udelay(1);
+ }
+ WARN(count == 1500, "WARNING: GDSC @ %#llx stuck at off\n", gdscr);
+}
+
void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0)
{
if (readl(base + gpll0->status) & gpll0->status_bit)
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index 7eb26369cd8f..2e074d0401c4 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -12,6 +12,9 @@
#define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
#define CFG_CLK_SRC_MASK (7 << 8)
+#define GDSC_PWR_ONBIT(31)
+#define GDSC_SW_COLLAPSE BIT(0)
+
#define RCG_CFG_REG0x4
#define RCG_M_REG 0x8
#define RCG_N_REG 0xc
@@ -78,6 +81,7 @@ int qcom_cc_bind(struct udevice *parent);
void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0);
void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
void clk_enable_cbc(phys_addr_t cbcr);
+void gdsc_enable(phys_addr_t gdscr);
void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk);
const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate);
void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr,
--
2.43.0
[PATCH 03/13] phy: qcom: Add USB HS 7nm PHY driver
From: Bhupesh Sharma
Some Qualcomm SoCs newer than SDM845 feature a so-called "7nm phy"
driver, notable the SM8250 SoC which will gain U-Boot support in
upcoming patches.
Introduce a driver based on the Linux driver.
Signed-off-by: Bhupesh Sharma
[code cleanup, switch to clk/reset_bulk APIs]
Signed-off-by: Caleb Connolly
---
drivers/phy/qcom/Kconfig | 8 +
drivers/phy/qcom/Makefile | 1 +
drivers/phy/qcom/phy-qcom-usb-hs-7nm.c | 295 +
3 files changed, 304 insertions(+)
diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig
index 361dfb6e1126..3fc59dc65650 100644
--- a/drivers/phy/qcom/Kconfig
+++ b/drivers/phy/qcom/Kconfig
@@ -19,6 +19,14 @@ config PHY_QCOM_QUSB2
Enable this to support the Super-Speed USB transceiver on various
Qualcomm chipsets.
+config PHY_QCOM_USB_HS_7NM
+ tristate "Qualcomm 7nm High-Speed PHY"
+ depends on PHY && ARCH_SNAPDRAGON
+ help
+ Enable this to support the Qualcomm Synopsys DesignWare Core 7nm
+ High-Speed PHY driver. This driver supports the Hi-Speed PHY which
+ is usually paired with Synopsys DWC3 USB IPs on MSM SOCs.
+
config PHY_QCOM_USB_HS_28NM
tristate "Qualcomm 28nm High-Speed PHY"
depends on PHY && ARCH_SNAPDRAGON
diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile
index f6af985666a4..39219ecd24aa 100644
--- a/drivers/phy/qcom/Makefile
+++ b/drivers/phy/qcom/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
+obj-$(CONFIG_PHY_QCOM_USB_HS_7NM) += phy-qcom-usb-hs-7nm.o
obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o
diff --git a/drivers/phy/qcom/phy-qcom-usb-hs-7nm.c
b/drivers/phy/qcom/phy-qcom-usb-hs-7nm.c
new file mode 100644
index ..65128b45937b
--- /dev/null
+++ b/drivers/phy/qcom/phy-qcom-usb-hs-7nm.c
@@ -0,0 +1,295 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Bhupesh Sharma
+ *
+ * Based on Linux driver
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c)
+#define SLEEPM BIT(0)
+#define OPMODE_MASK GENMASK(4, 3)
+#define OPMODE_NORMAL (0x00)
+#define OPMODE_NONDRIVING BIT(3)
+#define TERMSEL BIT(5)
+
+#define USB2_PHY_USB_PHY_UTMI_CTRL1 (0x40)
+#define XCVRSEL BIT(0)
+
+#define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50)
+#define POR BIT(1)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
+#define SIDDQ BIT(2)
+#define RETENABLEN BIT(3)
+#define FSEL_MASK GENMASK(6, 4)
+#define FSEL_DEFAULT (0x3 << 4)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58)
+#define VBUSVLDEXTSEL0 BIT(4)
+#define PLLBTUNE BIT(5)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c)
+#define VREGBYPASS BIT(0)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60)
+#define VBUSVLDEXT0 BIT(0)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64)
+#define USB2_AUTO_RESUME BIT(0)
+#define USB2_SUSPEND_N BIT(2)
+#define USB2_SUSPEND_N_SEL BIT(3)
+
+#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0 (0x6c)
+#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1 (0x70)
+#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2 (0x74)
+#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X3 (0x78)
+#define PARAM_OVRD_MASK 0xFF
+
+#define USB2_PHY_USB_PHY_CFG0 (0x94)
+#define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0)
+#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1)
+
+#define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0)
+#define REFCLK_SEL_MASK GENMASK(1, 0)
+#define REFCLK_SEL_DEFAULT (0x2 << 0)
+
+#define HS_DISCONNECT_MASK GENMASK(2, 0)
+#define SQUELCH_DETECTOR_MASK GENMASK(7, 5)
+
+#define HS_AMPLITUDE_MASK GENMASK(3, 0)
+#define PREEMPHASIS_DURATION_MASK BIT(5)
+#define PREEMPHASIS_AMPLITUDE_MASK GENMASK(7, 6)
+
+#define HS_RISE_FALL_MASK GENMASK(1, 0)
+#define HS_CROSSOVER_VOLTAGE_MASK GENMASK(3, 2)
+#define HS_OUTPUT_IMPEDANCE_MASK GENMASK(5, 4)
+
+#define LS_FS_OUTPUT_IMPEDANCE_MASK GENMASK(3, 0)
+
+#define SNPS_HS_NUM_VREGS ARRAY_SIZE(hs_7nm_vreg_names)
+
+struct override_param {
+ s32 value;
+ u8 reg_val;
+};
+
+struct override_param_map {
+ const char *prop_name;
+ const struct override_param *param_table;
+ u8 table_size;
+ u8 reg_offset;
+ u8 param_mask;
+};
+
+struct phy_override_seq {
+ bool need_update;
+ u8 offset;
+ u8 value;
+ u8 mask;
+};
+
+#define NUM_HSPHY_TUNING_PARAMS (9)
+
+/* struct hs_7nm_phy_cfg - per-PHY initialization config */
+struct hs_7nm_phy_cfg {
+ /* resets to be requested */
+ struct reset_ctl *resets;
+ int num_resets;
+
+ struct override_param_map *map_cfg;
+ struct phy_override_seq update_seq_cfg[NUM_HSPHY_TUNING_PARAMS];
+};
+
+/**
+ * struct hs_7nm_phy_priv - snps hs phy
[PATCH 01/13] mailmap: update Bhupesh's email address
Update Bhupesh's email to his new one. Signed-off-by: Caleb Connolly --- Cc: Bhupesh Sharma --- .mailmap | 1 + 1 file changed, 1 insertion(+) diff --git a/.mailmap b/.mailmap index d1f08f3eca8a..f6e0847b2168 100644 --- a/.mailmap +++ b/.mailmap @@ -30,6 +30,7 @@ Atish Patra Bharat Kumar Gogada Bharat Kumar Gogada Bhargava Sreekantappa Gayathri +Bhupesh Sharma Bin Meng Boris Brezillon Boris Brezillon -- 2.43.0
[PATCH 02/13] phy: qcom: add Qualcomm QUSB2 USB PHY driver
From: Bhupesh Sharma
The Snapdragon 845 and several other Qualcomm SoCs feature this
USB high-speed phy. Add a driver for it based on the Linux driver, with
support for the SDM845, and the QCM2290 and SM6115 SoCs which will gain
support in U-Boot in future patches.
Signed-off-by: Bhupesh Sharma
[code cleanup, switch to clk_bulk]
Signed-off-by: Caleb Connolly
---
drivers/phy/qcom/Kconfig | 7 +
drivers/phy/qcom/Makefile | 1 +
drivers/phy/qcom/phy-qcom-qusb2.c | 468 ++
3 files changed, 476 insertions(+)
diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig
index f4ca174805a4..361dfb6e1126 100644
--- a/drivers/phy/qcom/Kconfig
+++ b/drivers/phy/qcom/Kconfig
@@ -12,6 +12,13 @@ config PHY_QCOM_IPQ4019_USB
help
Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
+config PHY_QCOM_QUSB2
+ tristate "Qualcomm USB QUSB2 PHY driver"
+ depends on PHY && ARCH_SNAPDRAGON
+ help
+ Enable this to support the Super-Speed USB transceiver on various
+ Qualcomm chipsets.
+
config PHY_QCOM_USB_HS_28NM
tristate "Qualcomm 28nm High-Speed PHY"
depends on PHY && ARCH_SNAPDRAGON
diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile
index 2113f178c0c7..f6af985666a4 100644
--- a/drivers/phy/qcom/Makefile
+++ b/drivers/phy/qcom/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
+obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o
diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c
b/drivers/phy/qcom/phy-qcom-qusb2.c
new file mode 100644
index ..5b654403a181
--- /dev/null
+++ b/drivers/phy/qcom/phy-qcom-qusb2.c
@@ -0,0 +1,468 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Bhupesh Sharma
+ *
+ * Based on Linux driver
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define QUSB2PHY_PLL 0x0
+#define QUSB2PHY_PLL_TEST 0x04
+#define CLK_REF_SEL BIT(7)
+
+#define QUSB2PHY_PLL_TUNE 0x08
+#define QUSB2PHY_PLL_USER_CTL1 0x0c
+#define QUSB2PHY_PLL_USER_CTL2 0x10
+#define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c
+#define QUSB2PHY_PLL_PWR_CTRL 0x18
+
+/* QUSB2PHY_PLL_STATUS register bits */
+#define PLL_LOCKED BIT(5)
+
+/* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */
+#define CORE_READY_STATUS BIT(0)
+
+/* QUSB2PHY_PORT_POWERDOWN register bits */
+#define CLAMP_N_EN BIT(5)
+#define FREEZIO_N BIT(1)
+#define POWER_DOWN BIT(0)
+
+/* QUSB2PHY_PWR_CTRL1 register bits */
+#define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5)
+#define PWR_CTRL1_CLAMP_N_EN BIT(1)
+
+#define QUSB2PHY_REFCLK_ENABLE BIT(0)
+
+#define PHY_CLK_SCHEME_SEL BIT(0)
+
+/* QUSB2PHY_INTR_CTRL register bits */
+#define DMSE_INTR_HIGH_SEL BIT(4)
+#define DPSE_INTR_HIGH_SEL BIT(3)
+#define CHG_DET_INTR_EN BIT(2)
+#define DMSE_INTR_EN BIT(1)
+#define DPSE_INTR_EN BIT(0)
+
+/* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */
+#define CORE_PLL_EN_FROM_RESET BIT(4)
+#define CORE_RESET BIT(5)
+#define CORE_RESET_MUX BIT(6)
+
+/* QUSB2PHY_IMP_CTRL1 register bits */
+#define IMP_RES_OFFSET_MASK GENMASK(5, 0)
+#define IMP_RES_OFFSET_SHIFT 0x0
+
+/* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */
+#define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0)
+#define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0
+
+/* QUSB2PHY_CHG_CONTROL_2 register bits */
+#define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4)
+#define CHG_CTRL2_OFFSET_SHIFT 0x4
+
+/* QUSB2PHY_PORT_TUNE1 register bits */
+#define HSTX_TRIM_MASK GENMASK(7, 4)
+#define HSTX_TRIM_SHIFT 0x4
+#define PREEMPH_WIDTH_HALF_BIT BIT(2)
+#define PREEMPHASIS_EN_MASK GENMASK(1, 0)
+#define PREEMPHASIS_EN_SHIFT 0x0
+
+/* QUSB2PHY_PORT_TUNE2 register bits */
+#define HSDISC_TRIM_MASK GENMASK(1, 0)
+#define HSDISC_TRIM_SHIFT 0x0
+
+#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04
+#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c
+#define QUSB2PHY_PLL_CMODE 0x2c
+#define QUSB2PHY_PLL_LOCK_DELAY 0x184
+#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4
+#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194
+#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198
+#define QUSB2PHY_PWR_CTRL2 0x214
+#define QUSB2PHY_IMP_CTRL1 0x220
+#define QUSB2PHY_IMP_CTRL2 0x224
+#define QUSB2PHY_CHG_CTRL2 0x23c
+
+struct qusb2_phy_init_tbl {
+ unsigned int offset;
+ unsigned int val;
+ /*
+* register part of layout ?
+* if yes, then offset gives index in the reg-layout
+*/
+ int in_layout;
+};
+
+struct qusb2_phy_cfg {
+ const struct qusb2_phy_init_tbl *tbl;
+ /* number of entries in the table */
+ unsigned int tbl_num;
+ /* offset to PHY_CLK_SCHEME register in TCSR map */
+ unsigned int clk_scheme_offset;
+
+ /* array of registers with different offsets */
+ const unsigned int *regs;
+ unsigned int mask_core_ready;
+
[PATCH 00/13] Qualcomm platform USB support
This series enables USB on Qualcomm SDM845 platforms and lays the
foundation for future SoCs as well.
It introduces two new high-speed PHY drivers, one for SDM845 and one for
an upcoming platform. The SDM845 clock driver gains support for
configuring the USB clocks, and the GPIO driver is updated to use .set_flags
which fixes a strange bug where GPIOs would also be configured as input.
Support for super-speed USB modes is not currently available, however
configuring the device to be high-speed only requires modifications to
DT.
To improve compatibility with upstream DT, we switch Qualcomm platforms
over to OF_LIVE and apply fixups to the tree to remove references to the
super-speed phy, as well as configure the Qualcomm glue for high-speed
only mode.
The db845c requires a vbus-supply to be hooked up for its usb type-A
port. A U-Boot dtsi file is added to configure this.
With these patches, it is now also possible to run U-Boot on some SDM845
phones like the OnePlus 6 using a dtb from Linux, and access the U-Boot
shell via the CDC ACM USB serial gadget.
This series depends on the ("Qualcomm generic board support") series [1]
switching to upstream DT, as well as the ("Qualcomm DWC3 USB support")
series [2]. A feature branch based on qcom-next with the necessary
dependencies for testing the Dragonboard845c can be found at [3].
I think most of these can go through the Qualcomm tree, but I'm not
exactly sure. I'd appreciate any suggestions on if/how to split this
series up further.
[1]:
https://lore.kernel.org/u-boot/20240130-b4-qcom-common-target-v3-0-e523cbf9e...@linaro.org/
[2]:
https://lore.kernel.org/u-boot/20240131-b4-qcom-usb-v1-0-6438b2a22...@linaro.org/
[3]: https://git.codelinaro.org/linaro/qcomlt/u-boot/-/tree/b4/dwc3-qcom
---
Bhupesh Sharma (2):
phy: qcom: add Qualcomm QUSB2 USB PHY driver
phy: qcom: Add USB HS 7nm PHY driver
Caleb Connolly (11):
mailmap: update Bhupesh's email address
clk/qcom: use offsets for RCG registers
clk/qcom: add gdsc_enable helper
clk/qcom: sdm845: add USB clocks
gpio: msm_gpio: add .set_flags op
serial: msm-geni: support livetree
mach-snapdragon: fixup USB nodes
dts: sdm845-db845c: add u-boot fixups
qcom_defconfig: regenerate with savedefconfig
qcom_defconfig: enable livetree
qcom_defconfig: enable USB
.mailmap | 1 +
arch/arm/dts/sdm845-db845c-u-boot.dtsi | 8 +
arch/arm/mach-snapdragon/board.c | 88 +++
configs/qcom_defconfig | 22 +-
drivers/clk/qcom/clock-apq8016.c | 39 +--
drivers/clk/qcom/clock-apq8096.c | 28 +-
drivers/clk/qcom/clock-qcom.c | 40 ++-
drivers/clk/qcom/clock-qcom.h | 20 +-
drivers/clk/qcom/clock-qcs404.c| 121 ++---
drivers/clk/qcom/clock-sdm845.c| 45 ++--
drivers/gpio/msm_gpio.c| 21 +-
drivers/phy/qcom/Kconfig | 15 ++
drivers/phy/qcom/Makefile | 2 +
drivers/phy/qcom/phy-qcom-qusb2.c | 468 +
drivers/phy/qcom/phy-qcom-usb-hs-7nm.c | 295 +
drivers/serial/serial_msm_geni.c | 13 +
16 files changed, 1017 insertions(+), 209 deletions(-)
---
base-commit: b5195aca8b5b30071fda8e60bb56013032e06d18
// Caleb (they/them)
Re: [PATCH 1/1] sunxi: sun4i: Reduce cpu clock at SPL initialization to 144 MHz
On Wed, 31 Jan 2024 14:26:02 +0100 Ludwig Kormann wrote: Hi, > thanks for your feedback! thanks for the quick reply! > Am 31.01.24 um 13:36 schrieb Andre Przywara: > > On Wed, 31 Jan 2024 11:49:43 +0100 > > Ludwig Kormann wrote: > > > > Hi Ludwig, > > > > thanks for taking care and sending a patch, though I scratch my head about > > this a bit. My main concern is why this would be an issue *now*, 11 years > > after the A20's release, and with tons of boards out there in operation. > > Also 144 MHz seem a somewhat drastic reduction? > > > We began seeing this issue beginning in early 2023 and it seems to affect > only a very small percentage of the units. We had to introduce this > patch for > our customers and wanted to also share it with the community. Thanks for that, much appreciated. > >> Up until now cpu clock gets initialized at 384 MHz, which is > >> the highest supported cpu clock. > > What do you mean with "highest supported"? Surely the A20 goes up to > > 960 MHz? > You're right, I must have mixed something up there. > > > Also please note that 384 MHz is the PLL1 reset configuration, so it's not > > something we came up with, but probably some safe value that Allwinner > > burned into their chips. > > > >> Recent A20 batches show an increased percentage of modules > >> reacting very sensitive to operating conditions outside the > >> specifications. > > What are those specifications, exactly? Do you have any more reliable > > data? The datasheet is very quiet on those conditions, it seems. > > In particular, I couldn't find any official frequency/voltage > > combinations, it seems like the values in the DTs are just passed on from > > some BSP drop? > Yes, it's hard/impossible to find any reliable information on this. > Our main reference have been the values in the DTs. > > > > >> The cpu dies very shortly after PLLs, core frequency or cpu > >> voltage are missconfigured. E.g.: > >> - uboot SPL selects 384 MHz as cpu clock which requires a cpu > >>voltage of at least 1.1 V. > >> - Linux CPU Frequency scaling with most sun7i dts will reduce > >>cpu voltage down to 1.0 V. > > How so? The mainline DT suggests 1.1V for anything above 312 MHz, and > > even above 144 MHz for the BananaPi. Are you using any OPs that differ > > from that? > > > >> - When intiating a reboot or reset from linux the cpu voltage > >>may keep the 1.0 V configuration and the cpu dies during SPL > >>initialization. > > Ah, so you mean we run (in Linux) on a 1.0V OP, probably at a very low CPU > > frequency, and then the CPU cores reset, leaving the PMIC at 1.0V? And > > then the SPL programs 384 MHz, which is too high, even for the brief period > > until we program DCDC2 to 1.4V? > Yes, the CPU dies before the voltage gets updated. > > If you have evidence (those "newer batches"? A20 batches in 2024?) for > > that, what about 312 MHz? Does that work? > The batches are actually from 2022+. We went for 144MHz as it's the lowest > of the "default" speeds, that also ensures we're "low enough" to (hopefully) > never trigger the issue again. > It seems like there's some variation in A20 production that triggers the > issue > and as we don't know any "official" voltage/frequency limits it's better > to have > some safety margin. > > > > >> Therefore reduce cpu clock at uboot SPL initialization down > >> to 144 MHz from 384 MHz. > > I am bit concerned about slowing down the initial SPL phase that much, for > > *all* A20 users. We run the DRAM init with that initial clock, even though > > the voltage is already up at this point. > In my opinion the impact / additional delay for the initial SPL phase > should not > be in a very relevant range actually, as it usually only takes a few > hundred milliseconds. Well, I heard in the past about users that care a lot about boot times, and were looking for ways to shave of a few dozen milliseconds from the boot. So a "few hundred ms" would probably upset them. And while I personally don't really care about this range either, there are a lot of A20 users out there, so I want to keep the disturbance as low as possible. > But you're right of course, this would force the lower value onto all > A20 users. > > > > > So if you see issues with those "newer batches" only(?), and since I > > haven't heard about any issues about that before, can we make this a > > Kconfig choice? We could make it simple, forcing K to 1, so we just need > > to divide the frequency by 24 and shift by 8 to get to the register value? > I will try to look into this and provide an update. > >> Signed-off-by: Ludwig Kormann > >> --- > >> arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 2 +- > >> arch/arm/mach-sunxi/clock_sun4i.c | 2 ++ > >> 2 files changed, 3 insertions(+), 1 deletion(-) > >> > >> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h > >> b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h > >> index 2cec91cb20..252c4c693e
[PATCH 5/5] iommu: qcom-smmu: fix debugging
The priv struct was wrong in dump_boot_mappings(). Causing errors when
compiling with -DDEBUG. Fix this.
Signed-off-by: Caleb Connolly
---
drivers/iommu/qcom-hyp-smmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/qcom-hyp-smmu.c b/drivers/iommu/qcom-hyp-smmu.c
index 8e5cdb581550..f2b39de56f4a 100644
--- a/drivers/iommu/qcom-hyp-smmu.c
+++ b/drivers/iommu/qcom-hyp-smmu.c
@@ -319,7 +319,7 @@ static int qcom_smmu_connect(struct udevice *dev)
}
#ifdef DEBUG
-static inline void dump_boot_mappings(struct arm_smmu_priv *priv)
+static inline void dump_boot_mappings(struct qcom_smmu_priv *priv)
{
u32 val;
int i;
--
2.43.0
[PATCH 4/5] usb: gadget: UMS: support multiple sector sizes
UFS storage often uses a 4096-byte sector size, add support for dynamic
sector sizes based loosely on the Linux implementation.
Signed-off-by: Caleb Connolly
---
cmd/usb_mass_storage.c | 4 --
drivers/usb/gadget/f_mass_storage.c | 101
drivers/usb/gadget/storage_common.c | 12 +++--
include/usb_mass_storage.h | 1 -
4 files changed, 65 insertions(+), 53 deletions(-)
diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
index a8ddeb494628..751701fe73af 100644
--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
@@ -88,10 +88,6 @@ static int ums_init(const char *devtype, const char
*devnums_part_str)
if (!strchr(devnum_part_str, ':'))
partnum = 0;
- /* f_mass_storage.c assumes SECTOR_SIZE sectors */
- if (block_dev->blksz != SECTOR_SIZE)
- goto cleanup;
-
ums_new = realloc(ums, (ums_count + 1) * sizeof(*ums));
if (!ums_new)
goto cleanup;
diff --git a/drivers/usb/gadget/f_mass_storage.c
b/drivers/usb/gadget/f_mass_storage.c
index c725aed3f626..d880928044f4 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -724,12 +724,13 @@ static int do_read(struct fsg_common *common)
curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
return -EINVAL;
}
- file_offset = ((loff_t) lba) << 9;
+ file_offset = ((loff_t)lba) << curlun->blkbits;
/* Carry out the file reads */
amount_left = common->data_size_from_cmnd;
- if (unlikely(amount_left == 0))
+ if (unlikely(amount_left == 0)) {
return -EIO;/* No default reply */
+ }
for (;;) {
@@ -768,13 +769,13 @@ static int do_read(struct fsg_common *common)
/* Perform the read */
rc = ums[common->lun].read_sector([common->lun],
- file_offset / SECTOR_SIZE,
- amount / SECTOR_SIZE,
+ file_offset / curlun->blksize,
+ amount / curlun->blksize,
(char __user *)bh->buf);
if (!rc)
return -EIO;
- nread = rc * SECTOR_SIZE;
+ nread = rc * curlun->blksize;
VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
(unsigned long long) file_offset,
@@ -787,7 +788,7 @@ static int do_read(struct fsg_common *common)
} else if (nread < amount) {
LDBG(curlun, "partial file read: %d/%u\n",
(int) nread, amount);
- nread -= (nread & 511); /* Round down to a block */
+ nread -= (nread & (curlun->blksize - 1)); /*
Round down to a block */
}
file_offset += nread;
amount_left -= nread;
@@ -861,7 +862,7 @@ static int do_write(struct fsg_common *common)
/* Carry out the file writes */
get_some_more = 1;
- file_offset = usb_offset = ((loff_t) lba) << 9;
+ file_offset = usb_offset = ((loff_t)lba) << curlun->blkbits;
amount_left_to_req = common->data_size_from_cmnd;
amount_left_to_write = common->data_size_from_cmnd;
@@ -893,7 +894,7 @@ static int do_write(struct fsg_common *common)
curlun->info_valid = 1;
continue;
}
- amount -= (amount & 511);
+ amount -= (amount & (curlun->blksize - 1));
if (amount == 0) {
/* Why were we were asked to transfer a
@@ -942,12 +943,12 @@ static int do_write(struct fsg_common *common)
/* Perform the write */
rc = ums[common->lun].write_sector([common->lun],
- file_offset / SECTOR_SIZE,
- amount / SECTOR_SIZE,
+ file_offset / curlun->blksize,
+ amount / curlun->blksize,
(char __user *)bh->buf);
if (!rc)
return -EIO;
- nwritten = rc * SECTOR_SIZE;
+ nwritten = rc * curlun->blksize;
VLDBG(curlun, "file write %u @ %llu -> %d\n", amount,
(unsigned long long) file_offset,
@@ -960,7 +961,7 @@ static int do_write(struct fsg_common *common)
} else if (nwritten < amount) {
[PATCH 3/5] usb: gadget: CDC ACM: call usb_gadget_initialize
To actually use the gadget the peripheral driver must be probed and we
must call g_dnl_clear_detach(). Otherwise acm_stdio_start() will always
fail to find a UDC on DT platforms.
Signed-off-by: Caleb Connolly
---
drivers/usb/gadget/f_acm.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/usb/gadget/f_acm.c b/drivers/usb/gadget/f_acm.c
index de42e0189e8d..ba216128ab27 100644
--- a/drivers/usb/gadget/f_acm.c
+++ b/drivers/usb/gadget/f_acm.c
@@ -623,12 +623,21 @@ static void acm_stdio_puts(struct stdio_dev *dev, const
char *str)
static int acm_stdio_start(struct stdio_dev *dev)
{
+ struct udevice *udc;
int ret;
if (dev->priv) { /* function already exist */
return 0;
}
+ ret = udc_device_get_by_index(0, );
+ if (ret) {
+ pr_err("USB init failed: %d\n", ret);
+ return ret;
+ }
+
+ g_dnl_clear_detach();
+
ret = g_dnl_register("usb_serial_acm");
if (ret)
return ret;
--
2.43.0
[PATCH 1/5] usb: dwc3-generic: implement Qualcomm wrapper
The Qualcomm specific dwc3 wrapper isn't hugely complicated, implemented
the missing initialisation for host and gadget mode.
Signed-off-by: Caleb Connolly
---
drivers/usb/dwc3/dwc3-generic.c | 99 -
1 file changed, 98 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 48da621ba966..1119cdecd26d 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -419,6 +419,99 @@ struct dwc3_glue_ops ti_ops = {
.glue_configure = dwc3_ti_glue_configure,
};
+/* USB QSCRATCH Hardware registers */
+#define QSCRATCH_HS_PHY_CTRL 0x10
+#define UTMI_OTG_VBUS_VALID BIT(20)
+#define SW_SESSVLD_SEL BIT(28)
+
+#define QSCRATCH_SS_PHY_CTRL 0x30
+#define LANE0_PWR_PRESENT BIT(24)
+
+#define QSCRATCH_GENERAL_CFG 0x08
+#define PIPE_UTMI_CLK_SEL BIT(0)
+#define PIPE3_PHYSTATUS_SW BIT(3)
+#define PIPE_UTMI_CLK_DIS BIT(8)
+
+#define PWR_EVNT_IRQ_STAT_REG 0x58
+#define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
+#define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
+
+#define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
+#define SDM845_QSCRATCH_SIZE 0x400
+#define SDM845_DWC3_CORE_SIZE 0xcd00
+static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
+{
+ u32 reg;
+
+ reg = readl(base + offset);
+ reg |= val;
+ writel(reg, base + offset);
+
+ /* ensure that above write is through */
+ readl(base + offset);
+}
+
+static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val)
+{
+ u32 reg;
+
+ reg = readl(base + offset);
+ reg &= ~val;
+ writel(reg, base + offset);
+
+ /* ensure that above write is through */
+ readl(base + offset);
+}
+
+static void dwc3_qcom_vbus_override_enable(void __iomem *qscratch_base, bool
enable)
+{
+ if (enable) {
+ dwc3_qcom_setbits(qscratch_base, QSCRATCH_SS_PHY_CTRL,
+ LANE0_PWR_PRESENT);
+ dwc3_qcom_setbits(qscratch_base, QSCRATCH_HS_PHY_CTRL,
+ UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
+ } else {
+ dwc3_qcom_clrbits(qscratch_base, QSCRATCH_SS_PHY_CTRL,
+ LANE0_PWR_PRESENT);
+ dwc3_qcom_clrbits(qscratch_base, QSCRATCH_HS_PHY_CTRL,
+ UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
+ }
+}
+
+/* For controllers running without superspeed PHYs */
+static void dwc3_qcom_select_utmi_clk(void __iomem *qscratch_base)
+{
+ /* Configure dwc3 to use UTMI clock as PIPE clock not present */
+ dwc3_qcom_setbits(qscratch_base, QSCRATCH_GENERAL_CFG,
+ PIPE_UTMI_CLK_DIS);
+
+ udelay(500);
+
+ dwc3_qcom_setbits(qscratch_base, QSCRATCH_GENERAL_CFG,
+ PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
+
+ udelay(500);
+
+ dwc3_qcom_clrbits(qscratch_base, QSCRATCH_GENERAL_CFG,
+ PIPE_UTMI_CLK_DIS);
+}
+
+static void dwc3_qcom_glue_configure(struct udevice *dev, int index,
+enum usb_dr_mode mode)
+{
+ void __iomem *qscratch_base = (void __iomem *)dev_read_addr(dev);
+
+ if (dev_read_bool(dev, "qcom,select-utmi-as-pipe-clk"))
+ dwc3_qcom_select_utmi_clk(qscratch_base);
+
+ if (mode != USB_DR_MODE_HOST)
+ dwc3_qcom_vbus_override_enable(qscratch_base, true);
+}
+
+struct dwc3_glue_ops qcom_ops = {
+ .glue_configure = dwc3_qcom_glue_configure,
+};
+
static int dwc3_rk_glue_get_ctrl_dev(struct udevice *dev, ofnode *node)
{
*node = dev_ofnode(dev);
@@ -506,6 +599,10 @@ static int dwc3_glue_reset_init(struct udevice *dev,
else if (ret)
return ret;
+ if (device_is_compatible(dev, "qcom,dwc3")) {
+ reset_assert_bulk(>resets);
+ udelay(500);
+ }
ret = reset_deassert_bulk(>resets);
if (ret) {
reset_release_bulk(>resets);
@@ -623,7 +720,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "rockchip,rk3568-dwc3", .data = (ulong)_ops },
{ .compatible = "rockchip,rk3588-dwc3", .data = (ulong)_ops },
- { .compatible = "qcom,dwc3" },
+ { .compatible = "qcom,dwc3", .data = (ulong)_ops },
{ .compatible = "fsl,imx8mp-dwc3", .data = (ulong)_ops },
{ .compatible = "fsl,imx8mq-dwc3" },
{ .compatible = "intel,tangier-dwc3" },
--
2.43.0
[PATCH 2/5] usb: dwc3: select DM_USB_GADGET
DWC3 platforms depend on DM_USB_GADGET for gadget drivers to work, otherwise compilation fails due to no implementation of dm_usb_gadget_handle_interrupts(). Signed-off-by: Caleb Connolly --- drivers/usb/dwc3/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index c0c8c16fd9c2..8a70bc682322 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -11,6 +11,7 @@ config USB_DWC3_GADGET bool "USB Gadget support for DWC3" default y depends on USB_GADGET + select DM_USB_GADGET select USB_GADGET_DUALSPEED comment "Platform Glue Driver Support" -- 2.43.0
[PATCH 0/5] Qualcomm DWC3 USB support
This series enables support for Qualcomm platforms in the DWC3 driver, adds support for arbitrary sector sizes to the USB mass storage gadget, and fixes an issue with the CDC ACM driver where it wouldn't initialise the USB device. Additionally, it fixes a syntax bug in the Qualcomm SMMU driver, and makes USB_DWC3_GADGET select DM_USB_GADGET to fix compilation with gadget mode. This is part of a larger series enabling DWC3 USB support on Qualcomm platforms, a feature branch with all patches can be found at [1]. [1]: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/tree/b4/dwc3-qcom --- Caleb Connolly (5): usb: dwc3-generic: implement Qualcomm wrapper usb: dwc3: select DM_USB_GADGET usb: gadget: CDC ACM: call usb_gadget_initialize usb: gadget: UMS: support multiple sector sizes iommu: qcom-smmu: fix debugging cmd/usb_mass_storage.c | 4 -- drivers/iommu/qcom-hyp-smmu.c | 2 +- drivers/usb/dwc3/Kconfig| 1 + drivers/usb/dwc3/dwc3-generic.c | 99 ++- drivers/usb/gadget/f_acm.c | 9 drivers/usb/gadget/f_mass_storage.c | 101 drivers/usb/gadget/storage_common.c | 12 +++-- include/usb_mass_storage.h | 1 - 8 files changed, 174 insertions(+), 55 deletions(-) --- base-commit: 16d331e8f1581de1ac6283365774a57dc1403cbd // Caleb (they/them)
