Re: [PATCH v3 07/11] phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
On 3/12/24 8:03 AM, Sumit Garg wrote:
Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
PHY initialization moved to this standalone PHY driver.
Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver
reference commit 7559e7572c03 ("phy: Explicitly include correct DT
includes").
[...]
+static int imx8_pcie_phy_probe(struct udevice *dev)
+{
+ struct imx8_pcie_phy *imx8_phy = dev_get_priv(dev);
+ ofnode gpr;
+ int ret = 0;
+
+ imx8_phy->drvdata = (void *)dev_get_driver_data(dev);
+ imx8_phy->base = dev_read_addr(dev);
+ if (!imx8_phy->base)
+ return -EINVAL;
+
+ /* get PHY refclk pad mode */
+ dev_read_u32(dev, "fsl,refclk-pad-mode", _phy->refclk_pad_mode);
+
+ imx8_phy->tx_deemph_gen1 = dev_read_u32_default(dev,
+ "fsl,tx-deemph-gen1",
+ 0);
+ imx8_phy->tx_deemph_gen2 = dev_read_u32_default(dev,
+ "fsl,tx-deemph-gen2",
+ 0);
+ imx8_phy->clkreq_unused = dev_read_bool(dev, "fsl,clkreq-unsupported");
+
+ /* Grab GPR config register range */
+ gpr = ofnode_by_compatible(ofnode_null(), imx8_phy->drvdata->gpr);
+ if (ofnode_equal(gpr, ofnode_null())) {
+ dev_err(dev, "unable to find GPR node\n");
+ return -ENODEV;
+ }
+
+ imx8_phy->iomuxc_gpr = syscon_node_to_regmap(gpr);
+ if (IS_ERR(imx8_phy->iomuxc_gpr)) {
+ dev_err(dev, "unable to find iomuxc registers\n");
+ return PTR_ERR(imx8_phy->iomuxc_gpr);
+ }
syscon_regmap_lookup_by_compatible() should simplify these two steps ^ .
With that fixed:
Reviewed-by: Marek Vasut
[...]
Re: [PATCH v3 08/11] pci: Add DW PCIe controller support for iMX8MP SoC
On 3/12/24 8:03 AM, Sumit Garg wrote:
pcie_imx doesn't seem to share any useful code for iMX8 SoC and it is
tied to quite old port of pcie_designware driver from Linux which
suffices only iMX6 specific needs.
But currently we have the common DWC specific bits which alligns pretty
well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
add support for other iMX8 variants to this driver.
iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
can reuse the generic PHY infrastructure to power on PCIe PHY.
Tested-by: Tim Harvey #imx8mp-venice*
Tested-by: Adam Ford #imx8mp-beacon-kit
Signed-off-by: Sumit Garg
[...]
+static int pcie_dw_imx_of_to_plat(struct udevice *dev)
+{
+ struct pcie_dw_imx *priv = dev_get_priv(dev);
+ ofnode gpr;
+ int ret;
+
+ /* Get the controller base address */
+ priv->dw.dbi_base = (void *)dev_read_addr_name(dev, "dbi");
+ if ((fdt_addr_t)priv->dw.dbi_base == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get dbi_base address\n");
+ return -EINVAL;
+ }
+
+ /* Get the config space base address and size */
+ priv->dw.cfg_base = (void *)dev_read_addr_size_name(dev, "config",
+ >dw.cfg_size);
+ if ((fdt_addr_t)priv->dw.cfg_base == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get cfg_base address\n");
+ return -EINVAL;
+ }
+
+ ret = clk_get_bulk(dev, >clks);
+ if (ret) {
+ dev_err(dev, "failed to get PCIe clks\n");
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, "apps", >apps_reset);
+ if (ret) {
+ dev_err(dev,
+ "Failed to get PCIe apps reset control\n");
+ goto err_reset;
+ }
+
+ ret = gpio_request_by_name(dev, "reset-gpio", 0, >reset_gpio,
+ (GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE));
The extra parenthesis () is not needed.
With that fixed:
Reviewed-by: Marek Vasut
Re: [PATCH v3 06/11] imx8mp: power-domain: Expose high performance PLL clock
On 3/12/24 8:03 AM, Sumit Garg wrote:
Expose the high performance PLL as a regular Linux clock
... as clock framework clock ...
, so the
PCIe PHY can use it when there is no external refclock provided.
Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/pmdomain/imx/imx8mp-blk-ctrl.c. Use last Linux kernel driver
reference commit 7476ddfd36ac ("pmdomain: imx8mp-blk-ctrl: Convert to
platform remove callback returning void").
With that fixed:
Reviewed-by: Marek Vasut
Re: [PATCH v3 05/11] imx8mp: power-domain: Add PCIe support
On 3/12/24 8:03 AM, Sumit Garg wrote: Add support for GPCv2 power domains and clock handling for PCIe and PCIe PHY. Tested-by: Tim Harvey #imx8mp-venice* Tested-by: Adam Ford #imx8mp-beacon-kit Signed-off-by: Sumit Garg Reviewed-by: Marek Vasut
Re: [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus
On 3/12/24 8:03 AM, Sumit Garg wrote:
power_domain_on/off() isn't refcounted and power domain bus shouldn't be
turned off for a single peripheral domain as it would negatively affect
other peripheral domains. So lets just skip turning off bus power
domain.
What exactly is the issue and how did you trigger it ?
Details please.
Fixes: 898e7610c62a ("imx: power-domain: Add i.MX8MP HSIOMIX driver")
Signed-off-by: Sumit Garg
---
drivers/power/domain/imx8mp-hsiomix.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/power/domain/imx8mp-hsiomix.c
b/drivers/power/domain/imx8mp-hsiomix.c
index e2d772c5ec7..448746432a2 100644
--- a/drivers/power/domain/imx8mp-hsiomix.c
+++ b/drivers/power/domain/imx8mp-hsiomix.c
@@ -50,7 +50,7 @@ static int imx8mp_hsiomix_on(struct power_domain
*power_domain)
ret = power_domain_on(domain);
if (ret)
- goto err_pd;
+ return ret;
ret = clk_enable(>clk_usb);
if (ret)
@@ -63,8 +63,6 @@ static int imx8mp_hsiomix_on(struct power_domain
*power_domain)
err_clk:
power_domain_off(domain);
-err_pd:
- power_domain_off(>pd_bus);
return ret;
Why not add counter into imx8mp_hsiomix_priv structure in this driver ?
Re: [PATCH v3 03/11] reset: imx: Add support for i.MX8MP reset controller
On 3/12/24 8:03 AM, Sumit Garg wrote:
Add support for i.MX8MP reset controller, it has same reset IP inside
as the other iMX7 and iMX8 variants but with different module layout.
iMX8M , iMX8 is a different SoC .
Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/reset/reset-imx7.c. Use last Linux kernel driver reference
commit bad8a8afe19f ("reset: Explicitly include correct DT includes").
Tested-by: Tim Harvey #imx8mp-venice*
Tested-by: Adam Ford #imx8mp-beacon-kit
Signed-off-by: Sumit Garg
---
drivers/reset/reset-imx7.c | 101 +
1 file changed, 101 insertions(+)
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index 4c7fa19d495..90d3d75255e 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
Keep the list sorted (P is before Q).
#include
#include
#include
@@ -252,6 +253,102 @@ static int imx8mq_reset_assert(struct reset_ctl *rst)
return 0;
}
+enum imx8mp_src_registers {
+ SRC_SUPERMIX_RCR= 0x0018,
+ SRC_AUDIOMIX_RCR= 0x001c,
+ SRC_MLMIX_RCR = 0x0028,
+ SRC_GPU2D_RCR = 0x0038,
+ SRC_GPU3D_RCR = 0x003c,
+ SRC_VPU_G1_RCR = 0x0048,
+ SRC_VPU_G2_RCR = 0x004c,
+ SRC_VPUVC8KE_RCR= 0x0050,
+ SRC_NOC_RCR = 0x0054,
+};
+
+static const struct imx7_src_signal imx8mp_src_signals[IMX8MP_RESET_NUM] = {
+ [IMX8MP_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
+ [IMX8MP_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
+ [IMX8MP_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
+ [IMX8MP_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
+ [IMX8MP_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
+ [IMX8MP_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
+ [IMX8MP_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
+ [IMX8MP_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
+ [IMX8MP_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
+ [IMX8MP_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
+ [IMX8MP_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
+ [IMX8MP_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
+ [IMX8MP_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
+ [IMX8MP_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
+ [IMX8MP_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
+ [IMX8MP_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
+ [IMX8MP_RESET_A53_SOC_DBG_RESET]= { SRC_A53RCR0, BIT(20) },
+ [IMX8MP_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
+ [IMX8MP_RESET_SW_NON_SCLR_M7C_RST] = { SRC_M4RCR, BIT(0) },
+ [IMX8MP_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
+ [IMX8MP_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
+ [IMX8MP_RESET_SUPERMIX_RESET] = { SRC_SUPERMIX_RCR, BIT(0) },
+ [IMX8MP_RESET_AUDIOMIX_RESET] = { SRC_AUDIOMIX_RCR, BIT(0) },
+ [IMX8MP_RESET_MLMIX_RESET] = { SRC_MLMIX_RCR, BIT(0) },
+ [IMX8MP_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) },
+ [IMX8MP_RESET_PCIEPHY_PERST]= { SRC_PCIEPHY_RCR, BIT(3) },
+ [IMX8MP_RESET_PCIE_CTRL_APPS_EN]= { SRC_PCIEPHY_RCR, BIT(6) },
+ [IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
+ [IMX8MP_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
+ [IMX8MP_RESET_MEDIA_RESET] = { SRC_DISP_RCR, BIT(0) },
+ [IMX8MP_RESET_GPU2D_RESET] = { SRC_GPU2D_RCR, BIT(0) },
+ [IMX8MP_RESET_GPU3D_RESET] = { SRC_GPU3D_RCR, BIT(0) },
+ [IMX8MP_RESET_GPU_RESET]= { SRC_GPU_RCR, BIT(0) },
+ [IMX8MP_RESET_VPU_RESET]= { SRC_VPU_RCR, BIT(0) },
+ [IMX8MP_RESET_VPU_G1_RESET] = { SRC_VPU_G1_RCR, BIT(0) },
+ [IMX8MP_RESET_VPU_G2_RESET] = { SRC_VPU_G2_RCR, BIT(0) },
+ [IMX8MP_RESET_VPUVC8KE_RESET] = { SRC_VPUVC8KE_RCR, BIT(0) },
+ [IMX8MP_RESET_NOC_RESET]= { SRC_NOC_RCR, BIT(0) },
+};
+
+static int imx8mp_reset_set(struct reset_ctl *rst, bool assert)
+{
+ struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
It wouldn't hurt to rename imx7_reset_priv to imx_reset_priv in 2/11 too.
With the include sorting fixed:
Reviewed-by: Marek Vasut
Re: [PATCH v3 02/11] reset: imx: Refactor driver to simplify function names
On 3/12/24 8:03 AM, Sumit Garg wrote:
imx7_reset_{deassert/assert}_imx* are a bit more confusing when compared
with imx*_reset_{deassert/assert}. So refactor driver to use function
names easier to understand. This shouldn't affect the functionality
though.
Suggested-by: Marek Vasut
Signed-off-by: Sumit Garg
---
drivers/reset/reset-imx7.c | 24
You could even rename the driver itself now, but that would be separate
patch.
1 file changed, 12 insertions(+), 12 deletions(-)
Reviewed-by: Marek Vasut
Re: [PATCH v3 01/11] clk: imx8mp: Add support for PCIe clocks
On 3/12/24 8:03 AM, Sumit Garg wrote: Add support for PCIe clocks required to enable PCIe support on iMX8MP SoC. Tested-by: Tim Harvey #imx8mp-venice* Tested-by: Adam Ford #imx8mp-beacon-kit Signed-off-by: Sumit Garg Reviewed-by: Marek Vasut
Re: [PATCH v2 15/15] rockchip: rk3328-orangepi-r1-plus: Enable boot from SPI NOR flash
On 2024/2/17 08:22, Jonas Karlman wrote:
Add Kconfig options to enable support for booting from SPI NOR flash on
Orange Pi R1 Plus boards.
The generated bootable u-boot-rockchip-spi.bin can be written to 0x0 of
SPI NOR flash. The FIT image is loaded from 0x6, same as on RK35xx
boards.
=> sf probe
SF: Detected zb25vq128 with page size 256 Bytes, erase size 4 KiB, total 16
MiB
=> load mmc 1:1 1000 u-boot-rockchip-spi.bin
1376768 bytes read in 66 ms (19.9 MiB/s)
=> sf update ${fileaddr} 0 ${filesize}
device 0 offset 0x0, size 0x150200
1126912 bytes written, 249856 bytes skipped in 14.22s, speed 100542 B/s
Signed-off-by: Jonas Karlman
Reviewed-by: Tianling Shen
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2:
- Include SPI flash pinctrl nodes in SPL
- Enable SPI_FLASH_XMC and SPI_FLASH_ZBIT, zb25vq128 was reported on my
R1 Plus LTS board.
---
.../dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 16
arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi | 16
configs/orangepi-r1-plus-lts-rk3328_defconfig| 10 ++
configs/orangepi-r1-plus-rk3328_defconfig| 10 ++
4 files changed, 52 insertions(+)
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
index 7cdf6913795d..0dbe5a01f986 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
@@ -17,6 +17,22 @@
};
};
+_clk {
+ bootph-pre-ram;
+};
+
+_cs0 {
+ bootph-pre-ram;
+};
+
+_rx {
+ bootph-pre-ram;
+};
+
+_tx {
+ bootph-pre-ram;
+};
+
_sd {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
index 35baeb2464bc..1af75ada1a62 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
@@ -17,6 +17,22 @@
};
};
+_clk {
+ bootph-pre-ram;
+};
+
+_cs0 {
+ bootph-pre-ram;
+};
+
+_rx {
+ bootph-pre-ram;
+};
+
+_tx {
+ bootph-pre-ram;
+};
+
_sd {
bootph-pre-ram;
};
diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig
b/configs/orangepi-r1-plus-lts-rk3328_defconfig
index 96d563bb4fc5..18dcf6cd4fa6 100644
--- a/configs/orangepi-r1-plus-lts-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
@@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x60
@@ -20,6 +21,8 @@ CONFIG_SPL_STACK=0x40
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_DEBUG_UART_BASE=0xFF13
CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
@@ -41,6 +44,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_POWER=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
@@ -77,7 +82,12 @@ CONFIG_MISC=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_ZBIT=y
CONFIG_PHY_MOTORCOMM=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_MDIO=y
diff --git a/configs/orangepi-r1-plus-rk3328_defconfig
b/configs/orangepi-r1-plus-rk3328_defconfig
index dfb05f176553..1078f2ff886f 100644
--- a/configs/orangepi-r1-plus-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
@@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x60
@@ -20,6 +21,8 @@ CONFIG_SPL_STACK=0x40
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_DEBUG_UART_BASE=0xFF13
CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
@@ -41,6 +44,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_POWER=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
@@ -77,7 +82,12 @@ CONFIG_MISC=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
Re: [PATCH v2 14/15] rockchip: rk3328-rock64: Enable boot from SPI NOR flash
On 2024/2/17 08:22, Jonas Karlman wrote:
Add Kconfig options to enable support for booting from SPI NOR flash on
Pine64 Rock64.
The generated bootable u-boot-rockchip-spi.bin can be written to 0x0 of
SPI NOR flash. The FIT image is loaded from 0x6, same as on RK35xx
boards.
=> sf probe
SF: Detected gd25q128 with page size 256 Bytes, erase size 4 KiB, total 16
MiB
=> load mmc 1:1 1000 u-boot-rockchip-spi.bin
1359872 bytes read in 65 ms (20 MiB/s)
=> sf update ${fileaddr} 0 ${filesize}
device 0 offset 0x0, size 0x14c000
1118208 bytes written, 241664 bytes skipped in 8.516s, speed 163516 B/s
Signed-off-by: Jonas Karlman
Reviewed-by: Dragan Simic
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2:
- Include SPI flash pinctrl nodes in SPL
- Enable SPI_FLASH_XTX
- Collect r-b tag
---
arch/arm/dts/rk3328-rock64-u-boot.dtsi | 16
configs/rock64-rk3328_defconfig| 9 +
2 files changed, 25 insertions(+)
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi
b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
index 9de645d8d7ab..85426495c3d8 100644
--- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
@@ -39,6 +39,22 @@
};
};
+_clk {
+ bootph-pre-ram;
+};
+
+_cs0 {
+ bootph-pre-ram;
+};
+
+_rx {
+ bootph-pre-ram;
+};
+
+_tx {
+ bootph-pre-ram;
+};
+
_sd {
bootph-pre-ram;
};
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
index feda87014286..0c640d7eaadc 100644
--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig
@@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x60
@@ -20,6 +21,8 @@ CONFIG_SPL_STACK=0x40
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_DEBUG_UART_BASE=0xFF13
CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
@@ -41,6 +44,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_POWER=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
@@ -78,7 +83,11 @@ CONFIG_MISC=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
Re: [PATCH v2 13/15] rockchip: rk3328: Add support to build bootable SPI image
On 2024/2/17 08:22, Jonas Karlman wrote:
Similar to RK35xx the BootRom in RK3328 can read all data and look for
idbloader at 0x8000, same as it does for SD and eMMC.
Use the rksd format and modify the mkimage offset to generate a bootable
u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2:
- No change
---
arch/arm/dts/rk3328-u-boot.dtsi| 11 +++
arch/arm/mach-rockchip/rk3328/rk3328.c | 1 +
2 files changed, 12 insertions(+)
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
index a030f1a5e51d..4d43fe2fb51a 100644
--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -133,3 +133,14 @@
_otg {
hnp-srp-disable;
};
+
+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+ {
+ simple-bin-spi {
+ mkimage {
+ args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+ offset = <0x8000>;
+ };
+ };
+};
+#endif
diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c
b/arch/arm/mach-rockchip/rk3328/rk3328.c
index b591d38fe412..b82b209de9e2 100644
--- a/arch/arm/mach-rockchip/rk3328/rk3328.c
+++ b/arch/arm/mach-rockchip/rk3328/rk3328.c
@@ -36,6 +36,7 @@
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/mmc@ff52",
+ [BROM_BOOTSOURCE_SPINOR] = "/spi@ff19/flash@0",
[BROM_BOOTSOURCE_SD] = "/mmc@ff50",
};
Re: [PATCH v2 12/15] Revert "rockchip: Allow booting from SPI"
On 2024/2/17 08:22, Jonas Karlman wrote:
This reverts commit 3523c07867b403d5b3b68812aebac8a5afa5be4c.
Booting from SPI was already allowed before this commit was first
introduced. A few lines further down the exact same code already existed
and still does.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2:
- No change
---
arch/arm/mach-rockchip/spl-boot-order.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/mach-rockchip/spl-boot-order.c
b/arch/arm/mach-rockchip/spl-boot-order.c
index 2c39a215c107..79c856d2a0ac 100644
--- a/arch/arm/mach-rockchip/spl-boot-order.c
+++ b/arch/arm/mach-rockchip/spl-boot-order.c
@@ -65,9 +65,6 @@ static int spl_node_to_boot_device(int node)
default:
return -ENOSYS;
}
- } else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node,
- )) {
- return BOOT_DEVICE_SPI;
}
/*
Re: [PATCH v2 11/15] rockchip: rk3328: Sync device tree from linux v6.8-rc1
On 2024/2/17 08:22, Jonas Karlman wrote:
Sync rk3328 device tree from linux v6.8-rc1.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2:
- No change
---
arch/arm/dts/rk3328-evb.dts | 1 +
arch/arm/dts/rk3328-nanopi-r2s.dts | 3 +-
arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts | 4 +-
arch/arm/dts/rk3328-orangepi-r1-plus.dts | 1 +
arch/arm/dts/rk3328-roc-cc.dts | 3 +-
arch/arm/dts/rk3328-rock-pi-e.dts| 55 +
arch/arm/dts/rk3328-rock64.dts | 1 +
arch/arm/dts/rk3328-u-boot.dtsi | 6 --
arch/arm/dts/rk3328.dtsi | 64 +++-
9 files changed, 112 insertions(+), 26 deletions(-)
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index ff6b466e0e07..1eef5504445f 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -11,6 +11,7 @@
compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
aliases {
+ ethernet0 =
mmc0 =
mmc1 =
mmc2 =
diff --git a/arch/arm/dts/rk3328-nanopi-r2s.dts
b/arch/arm/dts/rk3328-nanopi-r2s.dts
index 3857d487ab84..a4399da7d8b1 100644
--- a/arch/arm/dts/rk3328-nanopi-r2s.dts
+++ b/arch/arm/dts/rk3328-nanopi-r2s.dts
@@ -14,6 +14,7 @@
compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
aliases {
+ ethernet0 =
ethernet1 =
mmc0 =
};
@@ -34,7 +35,7 @@
pinctrl-0 = <_button_pin>;
pinctrl-names = "default";
- reset {
+ key-reset {
label = "reset";
gpios = < RK_PA0 GPIO_ACTIVE_LOW>;
linux,code = ;
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
index 5d7d567283e5..4237f2ee8fee 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
@@ -26,9 +26,11 @@
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
+ motorcomm,auto-sleep-disabled;
motorcomm,clk-out-frequency-hz = <12500>;
motorcomm,keep-pll-enabled;
- motorcomm,auto-sleep-disabled;
+ motorcomm,rx-clk-drv-microamp = <5020>;
+ motorcomm,rx-data-drv-microamp = <5020>;
pinctrl-0 = <_phy_reset_pin>;
pinctrl-names = "default";
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus.dts
b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
index dc83d74045a3..f20662929c77 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus.dts
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
@@ -15,6 +15,7 @@
compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
aliases {
+ ethernet0 =
ethernet1 =
mmc0 =
};
diff --git a/arch/arm/dts/rk3328-roc-cc.dts b/arch/arm/dts/rk3328-roc-cc.dts
index aa22a0c22265..414897a57e75 100644
--- a/arch/arm/dts/rk3328-roc-cc.dts
+++ b/arch/arm/dts/rk3328-roc-cc.dts
@@ -11,6 +11,7 @@
compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
aliases {
+ ethernet0 =
mmc0 =
mmc1 =
};
@@ -96,7 +97,6 @@
linux,default-trigger = "heartbeat";
gpios = < 1 GPIO_ACTIVE_LOW>;
default-state = "on";
- mode = <0x23>;
};
user_led: led-1 {
@@ -104,7 +104,6 @@
linux,default-trigger = "mmc1";
gpios = < 0 GPIO_ACTIVE_LOW>;
default-state = "off";
- mode = <0x05>;
};
};
};
diff --git a/arch/arm/dts/rk3328-rock-pi-e.dts
b/arch/arm/dts/rk3328-rock-pi-e.dts
index 018a3a5075c7..3cda6c627b68 100644
--- a/arch/arm/dts/rk3328-rock-pi-e.dts
+++ b/arch/arm/dts/rk3328-rock-pi-e.dts
@@ -21,6 +21,8 @@
compatible = "radxa,rockpi-e", "rockchip,rk3328";
aliases {
+ ethernet0 =
+ ethernet1 =
mmc0 =
mmc1 =
};
@@ -180,6 +182,59 @@
status = "okay";
};
+ {
+ gpio-line-names =
+ /* GPIO0_A0 - A7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO0_B0 - B7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO0_C0 - C7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO0_D0 - D7 */
+ "", "", "", "pin-15 [GPIO0_D3]", "", "", "", "";
+};
+
+ {
+ gpio-line-names =
+ /* GPIO1_A0 - A7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO1_B0 - B7 */
+ "", "", "",
Re: [PATCH v2 10/15] rng: rockchip: Use same compatible as linux
On 2024/2/17 08:22, Jonas Karlman wrote:
Replace the rockchip,cryptov1-rng compatible with compatibles used in
the linux device tree for RK3288, RK3328 and RK3399 to ease sync of SoC
device tree from linux.
Signed-off-by: Jonas Karlman
Reviewed-by: Heinrich Schuchardt
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2:
- No change
- Collect r-b tag
---
arch/arm/dts/rk3328-u-boot.dtsi | 2 +-
arch/arm/dts/rk3399-u-boot.dtsi | 2 +-
drivers/rng/rockchip_rng.c | 10 +-
3 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
index 687c16da5135..ea34bf6b78bb 100644
--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -28,7 +28,7 @@
};
rng: rng@ff06 {
- compatible = "rockchip,cryptov1-rng";
+ compatible = "rockchip,rk3328-crypto";
reg = <0x0 0xff06 0x0 0x4000>;
status = "okay";
};
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index 3423b882c437..87b173e59579 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -30,7 +30,7 @@
};
rng: rng@ff8b8000 {
- compatible = "rockchip,cryptov1-rng";
+ compatible = "rockchip,rk3399-crypto";
reg = <0x0 0xff8b8000 0x0 0x1000>;
status = "okay";
};
diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c
index 705b424cf3dd..e82b5572fec5 100644
--- a/drivers/rng/rockchip_rng.c
+++ b/drivers/rng/rockchip_rng.c
@@ -302,7 +302,15 @@ static const struct dm_rng_ops rockchip_rng_ops = {
static const struct udevice_id rockchip_rng_match[] = {
{
- .compatible = "rockchip,cryptov1-rng",
+ .compatible = "rockchip,rk3288-crypto",
+ .data = (ulong)_cryptov1_soc_data,
+ },
+ {
+ .compatible = "rockchip,rk3328-crypto",
+ .data = (ulong)_cryptov1_soc_data,
+ },
+ {
+ .compatible = "rockchip,rk3399-crypto",
.data = (ulong)_cryptov1_soc_data,
},
{
Re: [PATCH v2 08/15] rockchip: rk3328: Fix loading FIT from SD-card when booting from eMMC
On 2024/2/17 08:22, Jonas Karlman wrote:
When RK3328 boards run SPL from eMMC and fail to load FIT from eMMC due
to it being missing or checksum validation fails there is a fallback to
read FIT from SD-card. However, without proper pinctrl configuration
reading FIT from SD-card will fail:
U-Boot SPL 2024.04-rc1 (Feb 05 2024 - 22:18:22 +)
Trying to boot from MMC1
mmc_load_image_raw_sector: mmc block read error
Trying to boot from MMC2
Card did not respond to voltage select! : -110
spl: mmc init failed with error: -95
Trying to boot from MMC1
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Fix this by tagging related emmc and sdmmc pinctrl nodes with bootph
props. Also sort and move common nodes shared by all boards to the SoC
u-boot.dtsi.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2:
- Add missing UART2 pinctrl nodes to soc u-boot.dtsi
- Mark the pinctrl node to be included in U-Boot proper pre-reloc phase
- Add SD-card IO-voltage related nodes to nanopi-r2 u-boot.dtsi
---
arch/arm/dts/rk3328-evb-u-boot.dtsi | 4 +
arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi| 13 +--
.../rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 25 ++---
.../dts/rk3328-orangepi-r1-plus-u-boot.dtsi | 25 ++---
arch/arm/dts/rk3328-roc-cc-u-boot.dtsi| 17
arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi | 17
arch/arm/dts/rk3328-rock64-u-boot.dtsi| 25 ++---
arch/arm/dts/rk3328-u-boot.dtsi | 91 +--
8 files changed, 107 insertions(+), 110 deletions(-)
diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi
b/arch/arm/dts/rk3328-evb-u-boot.dtsi
index 12b68df1ac67..38ad3cc16d09 100644
--- a/arch/arm/dts/rk3328-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi
@@ -44,3 +44,7 @@
/* Integrated PHY unsupported by U-Boot */
status = "broken";
};
+
+_sd {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
index 0a1152e8b52d..cca4f06145cf 100644
--- a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
@@ -7,23 +7,18 @@
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr4-666.dtsi"
- {
+ {
bootph-pre-ram;
};
- {
- bootph-pre-ram;
-};
-
-_pin {
- bootph-pre-ram;
+_vcc_pin {
+ bootph-all;
};
-_pull_up_4ma {
+_io_sdio {
bootph-pre-ram;
};
-/* Need this and all the pinctrl/gpio stuff above to set pinmux */
_sd {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
index 8a4189c6f1cc..7cdf6913795d 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
@@ -7,29 +7,16 @@
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-lpddr3-666.dtsi"
- {
- bootph-pre-ram;
-};
-
- {
- bootph-pre-ram;
-};
-
-_pin {
+ {
bootph-pre-ram;
-};
+ bootph-some-ram;
-_pull_up_4ma {
- bootph-pre-ram;
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
};
-/* Need this and all the pinctrl/gpio stuff above to set pinmux */
_sd {
bootph-pre-ram;
};
-
- {
- spi_flash: spiflash@0 {
- bootph-all;
- };
-};
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
index 2e3b6a77a268..35baeb2464bc 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
@@ -7,29 +7,16 @@
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr4-666.dtsi"
- {
- bootph-pre-ram;
-};
-
- {
- bootph-pre-ram;
-};
-
-_pin {
+ {
bootph-pre-ram;
-};
+ bootph-some-ram;
-_pull_up_4ma {
- bootph-pre-ram;
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
};
-/* Need this and all the pinctrl/gpio stuff above to set pinmux */
_sd {
bootph-pre-ram;
};
-
- {
- spi_flash: spiflash@0 {
- bootph-all;
- };
-};
diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
index 8bc2f134f8f4..47d74964fd0c 100644
--- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
@@ -29,23 +29,6 @@
};
};
- {
- bootph-pre-ram;
-};
-
- {
- bootph-pre-ram;
-};
-
-_pin {
- bootph-pre-ram;
-};
-
-_pull_up_4ma {
- bootph-pre-ram;
-};
-
-/* Need this and all the pinctrl/gpio stuff above to set pinmux */
_sd {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
index 1f220c6dcd0f..9ed0aef1ecc9
Re: [PATCH v2 09/15] gpio: rockchip: Use gpio alias id as gpio bank id
On 2024/2/17 08:22, Jonas Karlman wrote:
The U-Boot driver try to base the gpio bank id on the gpio-ranges prop
and fall back to base the bank id on the node name. However, the linux
driver try to base the bank id on the gpio alias id and fall back on
node order.
This can cause issues when SoC DT is synced from linux and gpioX@ nodes
has been renamed to gpio@ and gpio-ranges or a SoC specific alias has
not been assigned.
Try to use the gpio alias id as first fallback when a gpio-ranges prop
is missing to ease sync of updated SoC DT. Keep the current fallback on
node name as a third fallback to not affect any existing unsynced DT.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2:
- No change
---
drivers/gpio/rk_gpio.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index 4a6ae554bf78..24fedd456353 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -201,8 +201,11 @@ static int rockchip_gpio_probe(struct udevice *dev)
priv->bank = args.args[1] / ROCKCHIP_GPIOS_PER_BANK;
} else {
uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
- end = strrchr(dev->name, '@');
- priv->bank = trailing_strtoln(dev->name, end);
+ ret = dev_read_alias_seq(dev, >bank);
+ if (ret) {
+ end = strrchr(dev->name, '@');
+ priv->bank = trailing_strtoln(dev->name, end);
+ }
}
priv->name[0] = 'A' + priv->bank;
Re: [PATCH v2 07/15] rockchip: rk3328-orangepi-r1-plus: Update defconfig
On 2024/2/17 08:22, Jonas Karlman wrote:
Update defconfig for rk3328-orangepi-r1-plus boards with new defaults.
Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep
support for scripts.
Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is
not included in the SPL fdt.
Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator
commands.
Add ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and
eth1addr is set based on cpuid read from eFUSE.
Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL.
Add DM_ETH_PHY=y, PHY_GIGE=y, PHY_MOTORCOMM=y, PHY_REALTEK=y and remove
to support reset of onboard ethernet PHYs. Also add DM_MDIO=y
to ensure device tree props is used by motorcomm PHY driver.
Add PHY_ROCKCHIP_INNO_USB2=y option to support the onboard USB PHY.
Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used.
Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random
generator.
Also add missing device tree files to MAINTAINERS file.
Signed-off-by: Jonas Karlman
Reviewed-by: Tianling Shen
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2:
- Add CMD_GPIO, CMD_REGULATOR, DM_MDIO and PHY_GIGE
- Remove SPL_I2C, SPL_PMIC_RK8XX and REGULATOR_PWM
- Collect r-b tag
---
.../rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 6 --
.../dts/rk3328-orangepi-r1-plus-u-boot.dtsi | 6 --
board/rockchip/evb_rk3328/MAINTAINERS | 2 ++
configs/orangepi-r1-plus-lts-rk3328_defconfig | 19 ++-
configs/orangepi-r1-plus-rk3328_defconfig | 19 ++-
doc/board/rockchip/rockchip.rst | 2 ++
6 files changed, 32 insertions(+), 22 deletions(-)
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
index 5aaa5ccb15c1..8a4189c6f1cc 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
@@ -28,12 +28,6 @@
bootph-pre-ram;
};
- {
- snps,reset-gpio = < RK_PC2 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 1 5>;
-};
-
{
spi_flash: spiflash@0 {
bootph-all;
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
index 6d3db86dce6a..2e3b6a77a268 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
@@ -28,12 +28,6 @@
bootph-pre-ram;
};
- {
- snps,reset-gpio = < RK_PC2 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 1 5>;
-};
-
{
spi_flash: spiflash@0 {
bootph-all;
diff --git a/board/rockchip/evb_rk3328/MAINTAINERS
b/board/rockchip/evb_rk3328/MAINTAINERS
index b88727acad26..675b72dd060c 100644
--- a/board/rockchip/evb_rk3328/MAINTAINERS
+++ b/board/rockchip/evb_rk3328/MAINTAINERS
@@ -32,12 +32,14 @@ ORANGEPI-R1-PLUS-RK3328
M: Tianling Shen
S: Maintained
F: configs/orangepi-r1-plus-rk3328_defconfig
+F: arch/arm/dts/rk3328-orangepi-r1-plus.dts
F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
ORANGEPI-R1-PLUS-LTS-RK3328
M: Tianling Shen
S: Maintained
F: configs/orangepi-r1-plus-lts-rk3328_defconfig
+F: arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
F: arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
ROC-RK3328-CC
diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig
b/configs/orangepi-r1-plus-lts-rk3328_defconfig
index d3d9417509e9..96d563bb4fc5 100644
--- a/configs/orangepi-r1-plus-lts-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
@@ -15,7 +15,6 @@ CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x60
CONFIG_SPL_STACK=0x40
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
@@ -26,7 +25,9 @@ CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -39,17 +40,18 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
-CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
#
Re: [PATCH v2 05/15] rockchip: rk3328-rock-pi-e: Update defconfig
On 2024/2/17 08:22, Jonas Karlman wrote: Update defconfig for rk3328-rock-pi-e with new defaults. Remove the xPL_DRIVERS_MISC=y option, no misc driver is used in xPL. Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep support for scripts. Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is not included in the SPL fdt. Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator commands. Add ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on cpuid read from eFUSE. Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL. Add DM_MDIO=y to ensure device tree props can be used by PHY driver. Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used. Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random generator. Also add myself as a reviewer for this board. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Thanks, - Kever --- v2: - Add CMD_GPIO, CMD_REGULATOR, DM_MDIO and PHY_GIGE - Remove SPL_I2C, SPL_PMIC_RK8XX and REGULATOR_PWM --- board/rockchip/evb_rk3328/MAINTAINERS | 1 + configs/rock-pi-e-rk3328_defconfig| 17 ++--- doc/board/rockchip/rockchip.rst | 2 +- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 09488eaf083f..47fd05d2ea8b 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -57,6 +57,7 @@ F: arch/arm/dts/rk3328-rock64-u-boot.dtsi ROCKPIE-RK3328 M: Banglang Huang +R: Jonas Karlman S: Maintained F: configs/rock-pi-e-rk3328_defconfig F: arch/arm/dts/rk3328-rock-pi-e.dts diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index 6dda900a9b42..35caad764551 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -15,7 +15,6 @@ CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x400 CONFIG_SPL_STACK=0x40 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 @@ -27,7 +26,9 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -41,17 +42,17 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1 -CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL_SYS_MALLOC_SIMPLE=y -CONFIG_TPL_DRIVERS_MISC=y CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" @@ -59,8 +60,8 @@ CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_TPL_REGMAP=y @@ -74,10 +75,13 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -85,9 +89,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y -CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y @@ -95,9 +97,10 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=150 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 23c2d0254ba2..becd0bfe801d 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -62,7 +62,7 @@ List of mainline supported Rockchip boards: - Rockchip Evb-RK3328 (evb-rk3328) - Firefly ROC-RK3328-CC (roc-cc-rk3328) - Pine64 Rock64 (rock64-rk3328) - - Radxa Rockpi E (rock-pi-e-rk3328) + - Radxa ROCK Pi E
Re: [PATCH v2 06/15] rockchip: rk3328-nanopi-r2: Update defconfig
On 2024/2/17 08:22, Jonas Karlman wrote:
Update defconfig for rk3328-nanopi-r2* boards with new defaults.
Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep
support for scripts.
Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is
not included in the SPL fdt.
Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator
commands.
Add ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and
eth1addr is set based on cpuid read from eFUSE.
Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL.
Add DM_ETH_PHY=y, PHY_GIGE=y, PHY_MOTORCOMM=y, PHY_REALTEK=y and remove
to support reset of onboard ethernet PHYs. Also add DM_MDIO=y
to ensure device tree props is used by motorcomm PHY driver.
Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used.
Add DM_REGULATOR_GPIO=y and SPL_DM_REGULATOR_GPIO=y to support the
regulator-gpio compatible.
Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random
generator.
Also add missing device tree files to MAINTAINERS file.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2:
- Add CMD_GPIO, CMD_REGULATOR, DM_MDIO, PHY_GIGE, DM_REGULATOR_GPIO and
SPL_DM_REGULATOR_GPIO
- Remove SPL_I2C, SPL_PMIC_RK8XX and REGULATOR_PWM
---
arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 6 --
board/rockchip/evb_rk3328/MAINTAINERS | 2 ++
configs/nanopi-r2c-plus-rk3328_defconfig | 20 +++-
configs/nanopi-r2c-rk3328_defconfig| 20 +++-
configs/nanopi-r2s-rk3328_defconfig| 20 +++-
doc/board/rockchip/rockchip.rst| 3 +++
6 files changed, 50 insertions(+), 21 deletions(-)
diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
index d969b008775e..0a1152e8b52d 100644
--- a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
@@ -27,9 +27,3 @@
_sd {
bootph-pre-ram;
};
-
- {
- snps,reset-gpio = < RK_PC2 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 1 5>;
-};
diff --git a/board/rockchip/evb_rk3328/MAINTAINERS
b/board/rockchip/evb_rk3328/MAINTAINERS
index 47fd05d2ea8b..b88727acad26 100644
--- a/board/rockchip/evb_rk3328/MAINTAINERS
+++ b/board/rockchip/evb_rk3328/MAINTAINERS
@@ -11,12 +11,14 @@ NANOPI-R2C-RK3328
M: Tianling Shen
S: Maintained
F: configs/nanopi-r2c-rk3328_defconfig
+F: arch/arm/dts/rk3328-nanopi-r2c.dts
F: arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
NANOPI-R2C-PLUS-RK3328
M: Tianling Shen
S: Maintained
F: configs/nanopi-r2c-plus-rk3328_defconfig
+F: arch/arm/dts/rk3328-nanopi-r2c-plus.dts
F: arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
NANOPI-R2S-RK3328
diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig
b/configs/nanopi-r2c-plus-rk3328_defconfig
index 320ed8b434a8..7a7b0342629f 100644
--- a/configs/nanopi-r2c-plus-rk3328_defconfig
+++ b/configs/nanopi-r2c-plus-rk3328_defconfig
@@ -15,7 +15,6 @@ CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x60
CONFIG_SPL_STACK=0x40
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
@@ -26,7 +25,9 @@ CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -39,17 +40,18 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
-CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks
assigned-clock-rates assigned-clock-parents"
@@ -57,8 +59,8 @@ CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
@@ -72,8 +74,14 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
Re: [PATCH v2 04/15] rockchip: rk3328-roc-cc: Update defconfig
On 2024/2/17 08:22, Jonas Karlman wrote: Update defconfig for rk3328-roc-cc with new defaults. Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL. Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep support for scripts. Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is not included in the SPL fdt. Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator commands. Also add CMD_POWEROFF=y to be able to use the poweroff command. Add ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on cpuid read from eFUSE. Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL. Add DM_ETH_PHY=y, PHY_MOTORCOMM=y and PHY_REALTEK=y to support common ethernet PHYs. Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used. Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random generator. Also add missing device tree file to MAINTAINERS and add myself as a reviewer for this board. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Thanks, - Kever --- v2: - Add CMD_GPIO, CMD_POWEROFF, CMD_REGULATOR and PHY_GIGE - Remove SPL_I2C, SPL_PMIC_RK8XX and REGULATOR_PWM --- board/rockchip/evb_rk3328/MAINTAINERS | 2 ++ configs/roc-cc-rk3328_defconfig | 15 ++- doc/board/rockchip/rockchip.rst | 2 +- 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 419bc8ded375..09488eaf083f 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -41,8 +41,10 @@ F: arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi ROC-RK3328-CC M: Loic Devulder M: Chen-Yu Tsai +R: Jonas Karlman S: Maintained F: configs/roc-cc-rk3328_defconfig +F: arch/arm/dts/rk3328-roc-cc.dts F: arch/arm/dts/rk3328-roc-cc-u-boot.dtsi ROCK64-RK3328 diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 4ac3c9403b02..c4abc06092f7 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -15,7 +15,6 @@ CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x60 CONFIG_SPL_STACK=0x40 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 @@ -26,7 +25,9 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-roc-cc.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -39,18 +40,20 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" @@ -58,8 +61,8 @@ CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_TPL_REGMAP=y @@ -73,9 +76,11 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y @@ -84,9 +89,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y -CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y @@ -95,6 +98,8 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=150 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index e23ca4231cc1..23c2d0254ba2 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -60,8 +60,8 @@ List of mainline supported Rockchip boards: - ODROID-GO Advance (odroid-go2) * rk3328 -
Re: [PATCH v2 05/15] rockchip: rk3328-rock-pi-e: Update defconfig
On 2024/2/17 08:22, Jonas Karlman wrote: Update defconfig for rk3328-rock-pi-e with new defaults. Remove the xPL_DRIVERS_MISC=y option, no misc driver is used in xPL. Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep support for scripts. Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is not included in the SPL fdt. Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator commands. Add ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on cpuid read from eFUSE. Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL. Add DM_MDIO=y to ensure device tree props can be used by PHY driver. Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used. Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random generator. Also add myself as a reviewer for this board. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Thanks, - Kever --- v2: - Add CMD_GPIO, CMD_REGULATOR, DM_MDIO and PHY_GIGE - Remove SPL_I2C, SPL_PMIC_RK8XX and REGULATOR_PWM --- board/rockchip/evb_rk3328/MAINTAINERS | 1 + configs/rock-pi-e-rk3328_defconfig| 17 ++--- doc/board/rockchip/rockchip.rst | 2 +- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 09488eaf083f..47fd05d2ea8b 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -57,6 +57,7 @@ F: arch/arm/dts/rk3328-rock64-u-boot.dtsi ROCKPIE-RK3328 M: Banglang Huang +R: Jonas Karlman S: Maintained F: configs/rock-pi-e-rk3328_defconfig F: arch/arm/dts/rk3328-rock-pi-e.dts diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index 6dda900a9b42..35caad764551 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -15,7 +15,6 @@ CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x400 CONFIG_SPL_STACK=0x40 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 @@ -27,7 +26,9 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -41,17 +42,17 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1 -CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL_SYS_MALLOC_SIMPLE=y -CONFIG_TPL_DRIVERS_MISC=y CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" @@ -59,8 +60,8 @@ CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_TPL_REGMAP=y @@ -74,10 +75,13 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -85,9 +89,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y -CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y @@ -95,9 +97,10 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=150 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 23c2d0254ba2..becd0bfe801d 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -62,7 +62,7 @@ List of mainline supported Rockchip boards: - Rockchip Evb-RK3328 (evb-rk3328) - Firefly ROC-RK3328-CC (roc-cc-rk3328) - Pine64 Rock64 (rock64-rk3328) - - Radxa Rockpi E (rock-pi-e-rk3328) + - Radxa ROCK Pi E
Re: [PATCH v2 03/15] rockchip: rk3328-rock64: Update defconfig
On 2024/2/17 08:22, Jonas Karlman wrote: Update defconfig for rk3328-rock64 with new defaults. Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL. Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep support for scripts. Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is not included in the SPL fdt. Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator commands. Also add CMD_POWEROFF=y to be able to use the poweroff command. Remove the NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is set based on cpuid read from eFUSE. Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL. Add DM_ETH_PHY=y and PHY_REALTEK=y to support onboard ethernet PHY. Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used. Also add missing device tree file to MAINTAINERS and add myself as a reviewer for this board. Signed-off-by: Jonas Karlman Reviewed-by: Dragan Simic Reviewed-by: Kever Yang Thanks, - Kever --- v2: - Add CMD_GPIO, CMD_POWEROFF, CMD_REGULATOR and PHY_GIGE - Remove SPL_I2C, SPL_PMIC_RK8XX and REGULATOR_PWM - Collect r-b tag --- board/rockchip/evb_rk3328/MAINTAINERS | 2 ++ configs/rock64-rk3328_defconfig | 14 +- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index dc750bd69426..419bc8ded375 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -47,8 +47,10 @@ F: arch/arm/dts/rk3328-roc-cc-u-boot.dtsi ROCK64-RK3328 M: Matwey V. Kornilov +R: Jonas Karlman S: Maintained F: configs/rock64-rk3328_defconfig +F: arch/arm/dts/rk3328-rock64.dts F: arch/arm/dts/rk3328-rock64-u-boot.dtsi ROCKPIE-RK3328 diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 0297d098761e..feda87014286 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -15,7 +15,6 @@ CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x60 CONFIG_SPL_STACK=0x40 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 @@ -26,7 +25,9 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -39,17 +40,19 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" @@ -57,8 +60,8 @@ CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_TPL_REGMAP=y @@ -76,6 +79,9 @@ CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -83,9 +89,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y -CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y
Re: [PATCH v2 02/15] rockchip: rk3328-evb: Update defconfig
On 2024/2/17 08:22, Jonas Karlman wrote: Update defconfig for rk3328-evb with new defaults. Add DM_RESET=y to support using reset signals. Remove the xPL_DRIVERS_MISC=y option, no misc driver is used in xPL. Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep support for scripts. Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator commands. Add MISC_INIT_R=y, ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on cpuid read from eFUSE. Remove pinctrl-0 and pinctrl-names from CONFIG_OF_SPL_REMOVE_PROPS, SPL need to configure pinctrl for e.g. SD-card. Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL. Add DM_ETH_PHY=y, PHY_MOTORCOMM=y and PHY_REALTEK=y to support common ethernet PHYs. Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used. Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random generator. Add SYSINFO=y to support the sysinfo uclass. Also add missing device tree files to MAINTAINERS and remove the obsolete README file. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Thanks, - Kever --- v2: - Add DM_RESET, CMD_GPIO, CMD_REGULATOR, PHY_GIGE and SYSINFO - Remove REGULATOR_PWM --- board/rockchip/evb_rk3328/MAINTAINERS | 2 + board/rockchip/evb_rk3328/README | 70 --- configs/evb-rk3328_defconfig | 22 ++--- 3 files changed, 18 insertions(+), 76 deletions(-) delete mode 100644 board/rockchip/evb_rk3328/README diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 5fc114a63f6c..dc750bd69426 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -4,6 +4,8 @@ S: Maintained F: board/rockchip/evb_rk3328 F: include/configs/evb_rk3328.h F: configs/evb-rk3328_defconfig +F: arch/arm/dts/rk3328-evb.dts +F: arch/arm/dts/rk3328-evb-u-boot.dtsi NANOPI-R2C-RK3328 M: Tianling Shen diff --git a/board/rockchip/evb_rk3328/README b/board/rockchip/evb_rk3328/README deleted file mode 100644 index 6cbb66a4cf87.. --- a/board/rockchip/evb_rk3328/README +++ /dev/null @@ -1,70 +0,0 @@ -Introduction - - -RK3328 key features we might use in U-Boot: -* CPU: ARMv8 64bit quad-core Cortex-A53 -* IRAM: 36KB -* DRAM: 4GB-16MB dual-channel -* eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50 -* SD/MMC: support SD 3.0, MMC 4.51 -* USB: USB2.0 EHCI host port *2 -* Display: RGB/HDMI/DP/MIPI/EDP - -evb key features: -* regulator: pwm regulator for CPU B/L -* PMIC: rk808 -* debug console: UART2 - -In order to support Arm Trust Firmware(ATF), we need to use the -miniloader from rockchip which: -* do DRAM init -* load and verify ATF image -* load and verify U-Boot image - -Here is the step-by-step to boot to U-Boot on rk3328. - -Get the Source and prebuild binary -== - - > mkdir ~/evb_rk3328 - > cd ~/evb_rk3328 - > git clone https://github.com/ARM-software/arm-trusted-firmware.git - > git clone https://github.com/rockchip-linux/rkbin - > git clone https://github.com/rockchip-linux/rkflashtool - -Compile ATF -=== - - > cd arm-trusted-firmware - > make realclean - > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3328 bl31 - -Compile U-Boot -== - - > cd ../u-boot - > make CROSS_COMPILE=aarch64-linux-gnu- evb-rk3328_defconfig all - -Compile rkflashtool -=== - - > cd ../rkflashtool - > make - -Package image for miniloader - - > cd .. - > cp arm-trusted-firmware/build/rk3328/release/bl31.bin rkbin/rk33 - > ./rkbin/tools/trust_merger rkbin/tools/RK3328TRUST.ini - > ./rkbin/tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img - > mkdir image - > mv trust.img ./image/ - > mv uboot.img ./image/rk3328evb-uboot.bin - -Flash image -=== -Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: - - > ./rkflashtool/rkflashloader rk3328evb - -You should be able to get U-Boot log message in console/UART2 now. diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index b9c541a92a1f..5a5f59c04b3b 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -9,11 +9,11 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x30 CONFIG_SF_DEFAULT_SPEED=2000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x400 CONFIG_SPL_STACK=0x40 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 @@ -25,10 +25,13 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set
Re: [PATCH v2 01/15] rockchip: rk3328: Update default u-boot,spl-boot-order prop
On 2024/2/17 08:22, Jonas Karlman wrote:
Change to use a common FIT load order, same-as-spl > SD-card > eMMC on
RK3328 boards. Only EVB and Radxa ROCK Pi E is affected by this change.
Signed-off-by: Jonas Karlman
Reviewed-by: Dragan Simic
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2:
- No change
- Collect r-b tag
---
arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi | 6 --
arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 5 -
arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 5 -
arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi | 5 -
arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 5 +
arch/arm/dts/rk3328-rock64-u-boot.dtsi | 5 +
arch/arm/dts/rk3328-u-boot.dtsi | 2 +-
7 files changed, 3 insertions(+), 30 deletions(-)
diff --git a/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
b/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
index f8adb9e5e1ff..1dc3c022c504 100644
--- a/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
@@ -1,9 +1,3 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include "rk3328-nanopi-r2c-u-boot.dtsi"
-
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", ,
- };
-};
diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
index 78d37ab47558..d969b008775e 100644
--- a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
@@ -6,11 +6,6 @@
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr4-666.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", ,
- };
-};
{
bootph-pre-ram;
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
index ebe33e48cb9c..5aaa5ccb15c1 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
@@ -6,11 +6,6 @@
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-lpddr3-666.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", ,
- };
-};
{
bootph-pre-ram;
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
index 637c70adf194..6d3db86dce6a 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
@@ -6,11 +6,6 @@
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr4-666.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", ,
- };
-};
{
bootph-pre-ram;
diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
index 2062f34bf825..8bc2f134f8f4 100644
--- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
@@ -5,11 +5,8 @@
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr4-666.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", ,
- };
+/ {
smbios {
compatible = "u-boot,sysinfo-smbios";
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
index 6904515b9693..bfe506fd2249 100644
--- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
@@ -5,11 +5,8 @@
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-lpddr3-1600.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", ,
- };
+/ {
smbios {
compatible = "u-boot,sysinfo-smbios";
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
index a9f2536de2a2..a12be7876db0 100644
--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -13,7 +13,7 @@
};
chosen {
- u-boot,spl-boot-order = ,
+ u-boot,spl-boot-order = "same-as-spl", ,
};
dmc: dmc {
Re: [PATCH v6 1/3] dt-bindings: mtd: partitions: Add binman compatible
Hi Miquel, On Wed, 13 Mar 2024 at 20:35, Miquel Raynal wrote: > > Hi Simon, > > s...@chromium.org wrote on Wed, 13 Mar 2024 11:25:42 +1300: > > > Hi Miquel, > > > > On Fri, 8 Mar 2024 at 20:42, Miquel Raynal > > wrote: > > > > > > Hi Simon, > > > > > > s...@chromium.org wrote on Fri, 8 Mar 2024 15:44:25 +1300: > > > > > > > Hi Miquel, > > > > > > > > On Tue, 6 Feb 2024 at 01:17, Miquel Raynal > > > > wrote: > > > > > > > > > > Hi Simon, > > > > > > > > > > > > > > > > > > > > > > +description: | > > > > > > > > > > > > > > > > > + The binman node provides a layout for > > > > > > > > > > > > > > > > > firmware, used when packaging firmware > > > > > > > > > > > > > > > > > + from multiple projects. It is based on > > > > > > > > > > > > > > > > > fixed-partitions, with some > > > > > > > > > > > > > > > > > + extensions, but uses 'compatible' to > > > > > > > > > > > > > > > > > indicate the contents of the node, to > > > > > > > > > > > > > > > > > + avoid perturbing or confusing existing > > > > > > > > > > > > > > > > > installations which use 'label' for a > > > > > > > > > > > > > > > > > + particular purpose. > > > > > > > > > > > > > > > > > + > > > > > > > > > > > > > > > > > + Binman supports properties used as inputs > > > > > > > > > > > > > > > > > to the firmware-packaging process, > > > > > > > > > > > > > > > > > + such as those which control alignment of > > > > > > > > > > > > > > > > > partitions. This binding addresses > > > > > > > > > > > > > > > > > + these 'input' properties. For example, it > > > > > > > > > > > > > > > > > is common for the 'reg' property > > > > > > > > > > > > > > > > > + (an 'output' property) to be set by > > > > > > > > > > > > > > > > > Binman, based on the alignment requested > > > > > > > > > > > > > > > > > + in the input. > > > > > > > > > > > > > > > > > + > > > > > > > > > > > > > > > > > + Once processing is complete, input > > > > > > > > > > > > > > > > > properties have mostly served their > > > > > > > > > > > > > > > > > + purpose, at least until the firmware is > > > > > > > > > > > > > > > > > repacked later, e.g. due to a > > > > > > > > > > > > > > > > > + firmware update. The 'fixed-partitions' > > > > > > > > > > > > > > > > > binding should provide enough > > > > > > > > > > > > > > > > > + information to read the firmware at > > > > > > > > > > > > > > > > > runtime, including decompression if > > > > > > > > > > > > > > > > > + needed. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > How is this going to work exactly? binman reads > > > > > > > > > > > > > > > > these nodes and then > > > > > > > > > > > > > > > > writes out 'fixed-partitions' nodes. But then > > > > > > > > > > > > > > > > you've lost the binman > > > > > > > > > > > > > > > > specifc parts needed for repacking. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > No, they are the same node. I do want the extra > > > > > > > > > > > > > > > information to stick > > > > > > > > > > > > > > > around. So long as it is compatible with > > > > > > > > > > > > > > > fixed-partition as well, this > > > > > > > > > > > > > > > should work OK. > > > > > > > > > > > > > > > > > > > > > > > > > > > > How can it be both? The partitions node compatible > > > > > > > > > > > > > > can be either > > > > > > > > > > > > > > 'fixed-partitions' or 'binman'. > > > > > > > > > > > > > > > > > > > > > > > > > > Can we not allow it to be both? I have tried to > > > > > > > > > > > > > adjust things in > > > > > > > > > > > > > response to feedback but perhaps the feedback was > > > > > > > > > > > > > leading me down the > > > > > > > > > > > > > wrong path? > > > > > > > > > > > > > > > > > > > > > > > > Sure, but then the schema has to and that means > > > > > > > > > > > > extending > > > > > > > > > > > > fixed-partitions. > > > > > > > > > > > > > > > > > > > > > > Can we cross that bridge later? There might be resistance > > > > > > > > > > > to it. I'm > > > > > > > > > > > not sure. For now, perhaps just a binman compatible works > > > > > > > > > > > well enough > > > > > > > > > > > to make progress. > > > > > > > > > > > > > > > > > > > > Is there any way to make progress on this? I would like to > > > > > > > > > > have > > > > > > > > > > software which doesn't understand the binman compatible to > > > > > > > > > > at least be > > > > > > > > > > able to understand the fixed-partition compatible. Is that > > > > > > > > > > acceptable? > > > > > > > > > > > > > > > > > > There's only 2 ways that it can work. Either binman writes out > > > > > > > > > fixed-partition nodes dropping/replacing anything only > > > > > > > > > defined for > > > > > > > > > binman or fixed-partition is extended to include what binman > > > > > > > > > needs. > > > > > > > > > > > > > > > > OK, then I suppose the best way is to add a new binman > > > > > > > > compatible, as > > > > > > > > is done with this v6 series. People then
Re: [PATCH v3 2/7] arm: clean up v7 and v8 linker scripts for bss_start/end
On Wed, Mar 13, 2024 at 04:57:57PM -0600, Sam Edwards wrote: [snip] > Still really excited for this to land! I'm going to have to blow the dust > off of my Clang/LLD support series here soon. :) Please tell me that includes updates to the Clang support in general copied over from the Linux kernel :) -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 3/3] cli: compile history code if and only if history config is selected
On Tue, Mar 05, 2024 at 03:37:37PM +0800, Hanyuan Zhao wrote: > This commit allows user to determine whether to have history recording > in command-line. Previously to this commit, the CMD_HISTORY only sets > the compiling of cmd/history.c, and the history code in cli_readline.c > is always compiled and will take a lot of space to store history even if > we say N to CMD_HISTORY. > > > Signed-off-by: Hanyuan Zhao This part of your series breaks some riscv platforms: https://source.denx.de/u-boot/u-boot/-/jobs/798333 https://source.denx.de/u-boot/u-boot/-/jobs/798334 -- Tom signature.asc Description: PGP signature
Re: [PATCH v2] test: dm: add button_cmd test
On Tue, Mar 05, 2024 at 02:51:03PM +, Caleb Connolly wrote:
> Add a test for the button_cmd feature. This validates that commands can
> be mapped to two buttons, that the correct command runs based on which
> button is pressed, that only 1 command is run, and that no command runs
> if button_cmd_0_name is wrong or unset.
>
> Additionally, fix a potential uninitialised variable use caught by these
> tests, the btn variable in get_button_cmd() is assumed to be null if
> button_get_by_label() fails, but it's actually used uninitialised in
> that case.
>
> CONFIG_BUTTON is now enabled automatically and was removed when running
> save_defconfig.
>
> Signed-off-by: Caleb Connolly
> Fixes: e761035b6423 ("boot: add support for button commands")
This still leads to CI failures:
https://source.denx.de/u-boot/u-boot/-/jobs/798332
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH] stv0991: Remove stv0991 board and architecture code
On Fri, Mar 08, 2024 at 02:38:13PM -0500, Tom Rini wrote: > This architecture and related board are unmaintained currently and have > been for a long time. Remove them. > > Signed-off-by: Tom Rini Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] Makefile: Improve generated_defconfig file handling
On Thu, Mar 07, 2024 at 09:38:22PM -0600, Sam Protsenko wrote:
> Commit 2027e99e61aa ("Makefile: Run defconfig files through the C
> preprocessor") adds `generated_defconfig' file, but fails to clean that
> up. It might be useful to have that file around after `make' is done,
> but it's better to clean that up on `make clean'. Also we probably want
> to hide it in `git status' list. This patch makes the described changes,
> and also adds `-P' parameter to the CPP command that produces the
> `generated_defconfig' to avoid generating linemarkers.
>
> Signed-off-by: Sam Protsenko
> Fixes: 2027e99e61aa ("Makefile: Run defconfig files through the C
> preprocessor")
> Acked-by: Andrew Davis
Applied to u-boot/next, thanks!
--
Tom
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Description: PGP signature
Re: [PATCH v5] cmd: add FDT setup for bootelf by flag
On Fri, Mar 08, 2024 at 12:29:14AM +0300, Maxim Moskalets wrote: > From: Maxim Moskalets > > Added the ability to use FDT for ELF applications, required to run some > OS. To make FDT setup, you need to set the -d fdt_addr_r cmd option for > bootelf command. Enable by selecting CMD_ELF_FDT_SETUP. > > Signed-off-by: Maxim Moskalets Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] board: developerbox: fix mem_map setup timing
On Wed, Mar 06, 2024 at 03:11:10PM +0900, Masahisa Kojima wrote:
> The setup of global variable mem_map was moved into enable_caches()
> by commit a70c75cabae1 ("board: developerbox: move mem_map setup later")
> since U-Boot was directly booted from NOR flash in XIP
> and bss is not yet available in dram_init() at that time.
> This has a problem, mem_map variable is used by
> the get_page_table_size() to calculate the page table size,
> but get_page_table_size() is called earlier than enable_caches()
> which fills mem_map variable. With that, U-Boot fails to boot when
> 64GB DIMM is installed.
>
> Currently U-Boot on the Developerbox board is not booted in XIP
> and bss is available in dram_init(), let's move mem_map setup
> in dram_init().
>
> Signed-off-by: Masahisa Kojima
Applied to u-boot/next, thanks!
--
Tom
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Description: PGP signature
Re: [PATCH v2] arm: dts: k3-am64: Move to OF_UPSTREAM
On Tue, Mar 05, 2024 at 10:19:37AM -0600, Andrew Davis wrote: > Enable OF_UPSTREAM for AM64-EVM and SK-AM64 boards. Remove DT files that > are now available in dts/upstream. Update the appended files based on > version of latest OF_UPSTREAM sync point (v6.7-rc7). > > Signed-off-by: Andrew Davis Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v2] initcall: break loop immediately on failure
On Tue, Mar 05, 2024 at 02:55:13PM +, Caleb Connolly wrote: > The current ordering always results in func pointing to the next > function in the init_sequence. e.g. if fdtdec_setup() fails, ret will > be set to the error code, then func will be updated to point to > initf_malloc(), only then is ret checked and the loop broken. The end > result of this is that the "initcall failed at ..." error will point you > to initf_malloc(), when the error actually occured in fdtdec_setup()! > > This can be quite confusing and result in a lot of time wasted debugging > code that has nothing to do with the failure (ask me how I know :P). > > Adjust the for loop to check ret immediately after the call and break > early so that func will correctly reference the failed function. > > Signed-off-by: Caleb Connolly > Reviewed-by: Dan Carpenter Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] boards: Remove empty BOARD_SPECIFIC_OPTIONS
On Mon, Mar 04, 2024 at 10:26:17AM -0500, Tom Rini wrote: > While there are currently uses for a stanza of "config BOARD_SPECIFIC_OPTIONS" > followed by "def_bool y" and a series of select/imply statements, having > this option set followed by nothing else doesn't provide anything. > Remove these stanzas. > > Signed-off-by: Tom Rini Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 2/3] cli: allow users to determine history buffer allocation method
On Tue, Mar 05, 2024 at 03:37:35PM +0800, Hanyuan Zhao wrote: > This commit allows users to choose the appropriate memory > allocation method between static allocated and dynamically > calloc. The previous static-array way will not obviously > contribute to the final binary size since it is uninitialized, > and might have better performance than the dynamical one. > Now we provide the users with both the two options. > > Signed-off-by: Hanyuan Zhao Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 1/3] cli: panic when failed to allocate memory for the history buffer
On Tue, Mar 05, 2024 at 03:37:33PM +0800, Hanyuan Zhao wrote: > This commit simply modifies the history initialize function, > replacing the return value by panic with reasons. The calling > chains of hist_init don't have steps explicitly throwing or > dealing with the ENOMEM error, and once the init fails, the > whole system is died. Using panic here to provide error > information instead. > > Signed-off-by: Hanyuan Zhao Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 3/3] cmd: rng: Add rng list command
On Mon, Mar 04, 2024 at 02:42:42PM +, Weizhao Ouyang wrote: > The 'rng list' command probes all RNG devices and list those devices > that are successfully probed. Also update the help info. > > Reviewed-by: Heinrich Schuchardt > Signed-off-by: Weizhao Ouyang Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 2/3] driver: rng: Fix SMCCC TRNG crash
On Mon, Mar 04, 2024 at 02:42:41PM +, Weizhao Ouyang wrote:
> Fix a SMCCC TRNG null pointer crash due to a failed smccc feature
> binding.
>
> Fixes: 53355bb86c25 ("drivers: rng: add smccc trng driver")
> Reviewed-by: Heinrich Schuchardt
> Signed-off-by: Weizhao Ouyang
Applied to u-boot/next, thanks!
--
Tom
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Description: PGP signature
Re: [PATCH v4 1/3] firmware: psci: Fix bind_smccc_features psci check
On Mon, Mar 04, 2024 at 02:42:40PM +, Weizhao Ouyang wrote: > According to PSCI specification DEN0022F, PSCI_FEATURES is used to check > whether the SMCCC is implemented by discovering SMCCC_VERSION. > > Signed-off-by: Weizhao Ouyang Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 2/2] arm64: Enable CONFIG_64BIT for static analysis
On Mon, Mar 04, 2024 at 10:04:29AM +0300, Dan Carpenter wrote: > In the Makefile there is a line that says this: > > # the checker needs the correct machine size > CHECKFLAGS += $(if $(CONFIG_64BIT),-m64,-m32) > > Set CONFIG_64BIT for ARM64 so that we pass -m64 to the static checkers > instead of -m32. > > Signed-off-by: Dan Carpenter Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 1/2] Kconfig: move CONFIG_32/64BIT to arch/Kconfig
On Mon, Mar 04, 2024 at 10:04:15AM +0300, Dan Carpenter wrote: > These configs are used in multiple places so put them in a shared > Kconfig file. > > Signed-off-by: Dan Carpenter > Reviewed-by: Tom Rini Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] fdt: Fix bootm_low handling
On Sat, Mar 02, 2024 at 11:54:02PM +0100, Marek Vasut wrote: > According to README CFG_SYS_BOOTMAPSZ section, in case both "bootm_low" and > "bootm_size" variables are defined, "bootm_mapsize" variable is not defined > and CFG_SYS_BOOTMAPSZ macro is not defined, all data for the Linux kernel > must be between "bootm_low" and "bootm_low" + "bootm_size". > > Currently, for systems with DRAM between 0x4000_..0x7fff_ and with > e.g. bootm_low=0x6000 and bootm_size=0x1000, the code will attempt > to reserve memory from 0x4000_..0x4fff_, which is incorrect. This > is because "bootm_low" is not taken into consideration correctly. > > The last parameter of lmb_alloc_base() is the maximum physical address of > the to be reserved LMB area. Currently this is the start of DRAM bank that > is considered for LMB area reservation + min(DRAM bank size, bootm_size). > In case bootm_low is set to non-zero, this maximum physical address has to > be shifted upward, to min(DRAM bank start + size, bootm_low + bootm_size), > otherwise the reserved memory may be below bootm_low address. > > In case of multiple DRAM banks, the current change reserves top part of > the first bank, and reserves the rest of memory in the follow up banks. > > Signed-off-by: Marek Vasut Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/2] sandbox: select CONFIG_64BIT for X86_64
On Tue, Mar 05, 2024 at 06:16:29PM +0300, Dan Carpenter wrote: > Select CONFIG_64BIT so that we pass the -m64 option (instead of -m32) to > static analysis tools. > > Signed-off-by: Dan Carpenter For v2 of this series, the subject on this one is wrong as it's x86 and not sandbox. -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 05/16] power: rk8xx: add support for RK806
Hi Quentin,
This patch build fail in CI:
Building current source for 1 boards (1 thread, 32 jobs per thread)
sandbox: + sandbox64
+drivers/power/pmic/rk8xx.c:141:10: error: implicit truncation from
'int' to a one-bit wide bit-field changes value from 1 to -1
[-Werror,-Wsingle-bit-bitfield-constant-conversion]
+ .op = 1,
+ ^
+1 error generated.
+make[4]: *** [scripts/Makefile.build:256: drivers/power/pmic/rk8xx.o]
Error 1
+make[3]: *** [scripts/Makefile.build:397: drivers/power/pmic] Error 2
+make[2]: *** [scripts/Makefile.build:397: drivers/power] Error 2
+make[1]: *** [Makefile:1887: drivers] Error 2
+make: *** [Makefile:177: sub-make] Error 2
0 0 1 /1 sandbox64
Thanks,
- Kever
On 2024/3/4 19:29, Quentin Schulz wrote:
From: Quentin Schulz
This adds support for RK806, only the SPI variant has been tested.
The communication "protocol" over SPI is the following:
- write three bytes:
- 1 byte: [0:3] length of the payload, [6] Enable CRC, [7] Write
- 1 byte: LSB register address
- 1 byte: MSB register address
- write/read length of payload
The CRC is always disabled for now.
The RK806 technically supports I2C as well, and this should be able to
support it without any change, but it wasn't tested.
The DT node name prefix for the buck converters has changed in the
Device Tree and is now dcdc-reg. The logic for buck converters is
however manageable within the current logic inside the rk8xx regulator
driver. The same cannot be said for the NLDO and PLDO.
Because pmic_bind_children() parses the DT nodes and extracts the LDO
index from the DT node name, NLDO and PLDO will have overlapping
indices. Therefore, we need a separate logic from the already-existing
ldo callbacks. Let's reuse as much as possible though.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
drivers/power/pmic/rk8xx.c | 91 +++
drivers/power/regulator/rk8xx.c | 514 +++-
include/power/rk8xx_pmic.h | 19 ++
3 files changed, 622 insertions(+), 2 deletions(-)
diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c
index 4e3a17337ee..82b5e0cbe32 100644
--- a/drivers/power/pmic/rk8xx.c
+++ b/drivers/power/pmic/rk8xx.c
@@ -9,8 +9,10 @@
#include
#include
#include
+#include
#include
#include
+#include
#include
static int rk8xx_sysreset_request(struct udevice *dev, enum sysreset_t type)
@@ -32,6 +34,10 @@ static int rk8xx_sysreset_request(struct udevice *dev, enum
sysreset_t type)
pmic_clrsetbits(dev->parent, RK817_REG_SYS_CFG3, 0,
BIT(0));
break;
+ case RK806_ID:
+ pmic_clrsetbits(dev->parent, RK806_REG_SYS_CFG3, 0,
+ BIT(0));
+ break;
default:
printf("Unknown PMIC RK%x: Cannot shutdown\n",
priv->variant);
@@ -83,6 +89,11 @@ void rk8xx_off_for_plugin(struct udevice *dev)
}
}
+static struct reg_data rk806_init_reg[] = {
+ /* RST_FUN */
+ { RK806_REG_SYS_CFG3, GENMASK(7, 6), BIT(7)},
+};
+
static struct reg_data rk817_init_reg[] = {
/* enable the under-voltage protection,
* the under-voltage protection will shutdown the LDO3 and reset the PMIC
@@ -92,7 +103,10 @@ static struct reg_data rk817_init_reg[] = {
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "DCDC_REG", .driver = "rk8xx_buck"},
+ { .prefix = "dcdc-reg", .driver = "rk8xx_buck"},
{ .prefix = "LDO_REG", .driver = "rk8xx_ldo"},
+ { .prefix = "nldo-reg", .driver = "rk8xx_nldo"},
+ { .prefix = "pldo-reg", .driver = "rk8xx_pldo"},
{ .prefix = "SWITCH_REG", .driver = "rk8xx_switch"},
{ },
};
@@ -102,11 +116,51 @@ static int rk8xx_reg_count(struct udevice *dev)
return RK808_NUM_OF_REGS;
}
+#if CONFIG_IS_ENABLED(SPI) && CONFIG_IS_ENABLED(DM_SPI)
+struct rk806_cmd {
+ charlen: 4; /* Payload size in bytes - 1 */
+ charreserved: 2;
+ charcrc_en: 1;
+ charop: 1; /* READ=0; WRITE=1; */
+ charreg_l;
+#define REG_L_MASK GENMASK(7, 0)
+ charreg_h;
+#define REG_H_MASK GENMASK(15, 8)
+};
+#endif
+
static int rk8xx_write(struct udevice *dev, uint reg, const uint8_t *buff,
int len)
{
int ret;
+#if CONFIG_IS_ENABLED(SPI) && CONFIG_IS_ENABLED(DM_SPI)
+ if (device_get_uclass_id(dev->parent) == UCLASS_SPI) {
+ struct spi_slave *spi = dev_get_parent_priv(dev);
+ struct rk806_cmd cmd = {
+ .op = 1,
+ .len = len - 1,
+ .reg_l = FIELD_GET(REG_L_MASK, reg),
+ .reg_h = FIELD_GET(REG_H_MASK, reg),
+ };
+
+ ret = dm_spi_claim_bus(dev);
+
Pull request efi-2024-04-rc5
Dear Tom, The following changes since commit f3c979dd0053c082d2df170446923e7ce5edbc2d: Prepare v2024.04-rc4 (2024-03-11 13:11:46 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-efi.git tags/efi-2024-04-rc5 for you to fetch changes up to c8a2567475508156f4f43ea2caf3532790d47f8e: doc: fix incorrect path Documentation (2024-03-13 08:16:16 +0100) Gitlab CI showed no issues: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/19917 Pull request efi-2024-04-rc5 Documentation: * fix Python string escapes * develop: commands: Fix function prototype * fix incorrect path Documentation * fix mistyped "env flags" command * board: phytec: phycore-am62x: Update artifact names UEFI: * Invoke ft_board_setup() before efi_carve_out_dt_rsv() Alexander Dahl (1): doc: develop: commands: Fix function prototype Benjamin Gray (1): doc/sphinx: fix Python string escapes Heinrich Schuchardt (1): doc: fix incorrect path Documentation Mark Kettenis (1): efi_loader: Don't carve out memory reservations too early Thomas Weißschuh (1): doc: fix mistyped "env flags" command Wadim Egorov (1): doc: board: phytec: phycore-am62x: Update artifact names doc/board/phytec/phycore-am62x.rst | 6 +++--- doc/develop/commands.rst | 2 +- doc/sphinx/cdomain.py | 2 +- doc/sphinx/kernel_abi.py | 2 +- doc/sphinx/kerneldoc.py| 2 +- doc/sphinx/maintainers_include.py | 14 +++--- doc/usage/cmd/env.rst | 2 +- lib/efi_loader/efi_helper.c| 11 +++ 8 files changed, 22 insertions(+), 19 deletions(-)
Re: [PATCH v3 2/7] arm: clean up v7 and v8 linker scripts for bss_start/end
On 3/13/24 10:23, Ilias Apalodimas wrote:
commit 3ebd1cbc49f0 ("arm: make __bss_start and __bss_end__ compiler-generated")
and
commit f84a7b8f54db ("ARM: Fix __bss_start and __bss_end in linker scripts")
were moving the bss_start/end on c generated variables that were
injected in their own sections. The reason was that we needed relative
relocations for position independent code and linker bugs back then
prevented us from doing so [0].
However, the linker documentation pages states that symbols that are
defined within a section definition will create a relocatable type with
the value being a fixed offset from the base of a section [1].
So let's start cleaning this up starting with the bss_start and bss_end
variables. Convert them into symbols within the .bss section definition.
[0] binutils commit 6b3b0ab89663 ("Make linker assigned symbol dynamic only for
shared object")
[1] https://sourceware.org/binutils/docs/ld/Expression-Section.html
Tested-by: Caleb Connolly # Qualcomm sdm845
Signed-off-by: Ilias Apalodimas
---
arch/arm/cpu/armv8/u-boot-spl.lds| 18 +++---
arch/arm/cpu/armv8/u-boot.lds| 16
arch/arm/cpu/u-boot.lds | 22 +++---
arch/arm/lib/sections.c | 2 --
arch/arm/mach-rockchip/u-boot-tpl-v8.lds | 15 ---
arch/arm/mach-zynq/u-boot.lds| 22 +++---
6 files changed, 29 insertions(+), 66 deletions(-)
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds
b/arch/arm/cpu/armv8/u-boot-spl.lds
index 7cb9d731246d..692414fe46fb 100644
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -63,18 +63,11 @@ SECTIONS
_image_binary_end = .;
- .bss_start (NOLOAD) : {
- . = ALIGN(8);
- KEEP(*(.__bss_start));
- } >.sdram
-
- .bss (NOLOAD) : {
+ .bss : {
+ __bss_start = .;
*(.bss*)
-. = ALIGN(8);
- } >.sdram
-
- .bss_end (NOLOAD) : {
- KEEP(*(.__bss_end));
+ . = ALIGN(8);
+ __bss_end = .;
} >.sdram
/DISCARD/ : { *(.rela*) }
@@ -89,3 +82,6 @@ SECTIONS
#include "linux-kernel-image-header-vars.h"
#endif
}
+ASSERT(CONFIG_SPL_BSS_START_ADDR % 8 == 0, \
+ "CONFIG_SPL_BSS_START_ADDR must be 8-byte aligned");
+
Git complains about this added blank line at the end of the file. (My
personal preference would be a blank line before the ASSERT, if the
ASSERT is truly necessary.)
But beyond that:
Tested-by: Sam Edwards # Binary output identical
Still really excited for this to land! I'm going to have to blow the
dust off of my Clang/LLD support series here soon. :)
Best,
Sam
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index fb6a30c922f7..9640cc7a04b8 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -149,19 +149,11 @@ SECTIONS
_end = .;
- . = ALIGN(8);
-
- .bss_start : {
- KEEP(*(.__bss_start));
- }
-
- .bss : {
+ .bss ALIGN(8): {
+ __bss_start = .;
*(.bss*)
-. = ALIGN(8);
- }
-
- .bss_end : {
- KEEP(*(.__bss_end));
+ . = ALIGN(8);
+ __bss_end = .;
}
/DISCARD/ : { *(.dynsym) }
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 7724c9332c3b..0dfe5f633b16 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -207,23 +207,15 @@ SECTIONS
}
/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
+ * These sections occupy the same memory, but their lifetimes do
+ * not overlap: U-Boot initializes .bss only after applying dynamic
+ * relocations and therefore after it doesn't need .rel.dyn any more.
*/
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
+ .bss ADDR(.rel.dyn) (OVERLAY): {
+ __bss_start = .;
*(.bss*)
-. = ALIGN(4);
-__bss_limit = .;
- }
-
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
+ . = ALIGN(4);
+ __bss_end = .;
}
.dynsym _image_binary_end : { *(.dynsym) }
diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c
index 857879711c6a..8e8bd5797e16 100644
--- a/arch/arm/lib/sections.c
+++ b/arch/arm/lib/sections.c
@@ -19,8 +19,6 @@
* aliasing warnings.
*/
-char __bss_start[0] __section(".__bss_start");
-char __bss_end[0] __section(".__bss_end");
char __image_copy_start[0] __section(".__image_copy_start");
char __image_copy_end[0] __section(".__image_copy_end");
char __rel_dyn_start[0]
Re: [PATCH v3 2/7] arm: clean up v7 and v8 linker scripts for bss_start/end
On 3/13/24 11:43, Ilias Apalodimas wrote:
Hi Richard,
On Wed, 13 Mar 2024 at 22:19, Richard Henderson
wrote:
On 3/13/24 06:23, Ilias Apalodimas wrote:
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -63,18 +63,11 @@ SECTIONS
_image_binary_end = .;
- .bss_start (NOLOAD) : {
- . = ALIGN(8);
- KEEP(*(.__bss_start));
- } >.sdram
-
- .bss (NOLOAD) : {
+ .bss : {
+ __bss_start = .;
*(.bss*)
- . = ALIGN(8);
- } >.sdram
-
- .bss_end (NOLOAD) : {
- KEEP(*(.__bss_end));
+ . = ALIGN(8);
+ __bss_end = .;
Still missing the alignment on .bss, previously in .bss_start.
Since this is emitted in .sdram memory I can't define it as
.bss ALIGN(8) : {} since the calculated memory will be outside the
sdram-defined region
I could define it as
.bss : {
. = ALIGN(8);
__bss_start = .;
..
}
But instead, I added an assert at the bottom which will break the
linking if the __bss_start is not 8byte aligned.
I think it would be clearer to assert on __bss_start address rather than
CONFIG_SPL_BSS_START_ADDR, if that's possible. If not, then the constant will have to do.
r~
Re: [PATCH v3 2/7] arm: clean up v7 and v8 linker scripts for bss_start/end
Hi Richard,
On Wed, 13 Mar 2024 at 22:19, Richard Henderson
wrote:
>
> On 3/13/24 06:23, Ilias Apalodimas wrote:
> > +++ b/arch/arm/cpu/armv8/u-boot-spl.lds
> > @@ -63,18 +63,11 @@ SECTIONS
> >
> > _image_binary_end = .;
> >
> > - .bss_start (NOLOAD) : {
> > - . = ALIGN(8);
> > - KEEP(*(.__bss_start));
> > - } >.sdram
> > -
> > - .bss (NOLOAD) : {
> > + .bss : {
> > + __bss_start = .;
> > *(.bss*)
> > - . = ALIGN(8);
> > - } >.sdram
> > -
> > - .bss_end (NOLOAD) : {
> > - KEEP(*(.__bss_end));
> > + . = ALIGN(8);
> > + __bss_end = .;
>
> Still missing the alignment on .bss, previously in .bss_start.
Since this is emitted in .sdram memory I can't define it as
.bss ALIGN(8) : {} since the calculated memory will be outside the
sdram-defined region
I could define it as
.bss : {
. = ALIGN(8);
__bss_start = .;
..
}
But instead, I added an assert at the bottom which will break the
linking if the __bss_start is not 8byte aligned.
Looking at the output for xilinx_zynqmp_kria_defconfig (which is a v8
board & SPL) looks identical and correct since
CONFIG_SPL_BSS_START_ADDR=0x1000 for that board.
$~ readelf -sW spl/u-boot-spl | grep bss_start
1550: 1000 0 NOTYPE GLOBAL DEFAULT6 __bss_start
Isn't the assert enough? Or do you think adding the . = ALIGN(8) in
the section definition is better?
Thanks
/Ilias
>
> With that fixed,
> Reviewed-by: Richard Henderson
>
> r~
[PULL] u-boot-mips fixes for v2024.04
Hi Tom, please pull two bugfixes for MIPS, thanks. CI: https://source.denx.de/u-boot/custodians/u-boot-mips/-/pipelines/19933 The following changes since commit f3c979dd0053c082d2df170446923e7ce5edbc2d: Prepare v2024.04-rc4 (2024-03-11 13:11:46 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-mips.git/ tags/mips-fixes-for-v2024.04 for you to fetch changes up to 6806a133cde6f99777925953ee046bf2f050d4ef: mips: fix change_k0_cca() (2024-03-13 21:15:40 +0100) - mips: implement __udivdi3 to fix building of SquashFS - mips: fix bug in cache init on MIPS32r2 or later Daniel Schwierzeck (1): mips: fix change_k0_cca() Linus Walleij (1): mips: implement __udivdi3 arch/mips/lib/Makefile | 2 +- arch/mips/lib/cache_init.S | 4 ++-- arch/mips/lib/udivdi3.c| 17 + 3 files changed, 20 insertions(+), 3 deletions(-) create mode 100644 arch/mips/lib/udivdi3.c
Re: [PATCH v3 7/7] arm: remove redundant section alignments
On 3/13/24 06:23, Ilias Apalodimas wrote:
Previous patches cleaning up linker symbols, also merged any explicit
. = ALIGN(x); into section definitions -- e.g
.bss ALIGN(x) : instead of
. = ALIGN(x);
. bss : {...}
However, if the output address is not specified then one will be chosen
for the section. This address will be adjusted to fit the alignment
requirement of the output section following the strictest alignment of
any input section contained within the output section. So let's get rid
of the redundant ALIGN directives when they are not needed.
While at add comments for the alignment of __bss_start/end since our
C runtime setup assembly assumes that __bss_start - __bss_end will be
a multiple of 4/8 for armv7 and armv8 respectively.
It's worth noting that the alignment is preserved on .rel.dyn for
mach-zynq which was explicitly aligning that section on an 8b
boundary instead of 4b one.
Signed-off-by: Ilias Apalodimas
---
arch/arm/cpu/armv8/u-boot.lds | 9 ++---
arch/arm/cpu/u-boot.lds | 8 ++--
arch/arm/mach-zynq/u-boot.lds | 4 ++--
3 files changed, 14 insertions(+), 7 deletions(-)
Reviewed-by: Richard Henderson
r~
Re: [PATCH v3 2/7] arm: clean up v7 and v8 linker scripts for bss_start/end
On 3/13/24 06:23, Ilias Apalodimas wrote:
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -63,18 +63,11 @@ SECTIONS
_image_binary_end = .;
- .bss_start (NOLOAD) : {
- . = ALIGN(8);
- KEEP(*(.__bss_start));
- } >.sdram
-
- .bss (NOLOAD) : {
+ .bss : {
+ __bss_start = .;
*(.bss*)
-. = ALIGN(8);
- } >.sdram
-
- .bss_end (NOLOAD) : {
- KEEP(*(.__bss_end));
+ . = ALIGN(8);
+ __bss_end = .;
Still missing the alignment on .bss, previously in .bss_start.
With that fixed,
Reviewed-by: Richard Henderson
r~
Re: [PATCH] starfive: visionfive2: switch to standard boot
On Wed, 2024-02-21 at 13:00, Nam Cao wrote: > Distro boot scripts are deprecated. Use standard boot instead. I had to enable 'CONFIG_CMD_SYSBOOT=y' in configs/starfive_visionfive2_defconfig because it doesn't boot without it. With this option it boots fine with this patch. Tested on u-boot version 2024.04-rc4-dirty > Signed-off-by: Nam Cao > Reviewed-by: Leo Yu-Chi Liang Tested-by: Milan P. Stanić > --- > configs/starfive_visionfive2_defconfig | 2 +- > include/configs/starfive-visionfive2.h | 14 +- > 2 files changed, 2 insertions(+), 14 deletions(-) > > diff --git a/configs/starfive_visionfive2_defconfig > b/configs/starfive_visionfive2_defconfig > index b11be7ac86..aec751f871 100644 > --- a/configs/starfive_visionfive2_defconfig > +++ b/configs/starfive_visionfive2_defconfig > @@ -31,8 +31,8 @@ CONFIG_RISCV_SMODE=y > # CONFIG_OF_BOARD_FIXUP is not set > # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set > CONFIG_FIT=y > +CONFIG_BOOTSTD_DEFAULTS=y > CONFIG_SYS_BOOTM_LEN=0x400 > -CONFIG_DISTRO_DEFAULTS=y > CONFIG_BOOTSTAGE=y > CONFIG_QSPI_BOOT=y > CONFIG_SD_BOOT=y > diff --git a/include/configs/starfive-visionfive2.h > b/include/configs/starfive-visionfive2.h > index 29c74470c7..049b0a0630 100644 > --- a/include/configs/starfive-visionfive2.h > +++ b/include/configs/starfive-visionfive2.h > @@ -15,17 +15,6 @@ > > #define __io > > -/* Environment options */ > - > -#define BOOT_TARGET_DEVICES(func) \ > - func(NVME, nvme, 0) \ > - func(USB, usb, 0) \ > - func(MMC, mmc, 0) \ > - func(MMC, mmc, 1) \ > - func(DHCP, dhcp, na) > - > -#include > - > #define TYPE_GUID_SPL"2E54B353-1271-4842-806F-E436D6AF6985" > #define TYPE_GUID_UBOOT "BC13C2FF-59E6-4262-A352-B275FD6F7172" > #define TYPE_GUID_SYSTEM "EBD0A0A2-B9E5-4433-87C0-68B6B72699C7" > @@ -48,7 +37,6 @@ > "type_guid_gpt_loader2=" TYPE_GUID_UBOOT "\0" \ > "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ > "partitions=" PARTS_DEFAULT "\0" \ > - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ > - BOOTENV > + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" > > #endif /* _STARFIVE_VISIONFIVE2_H */
Re: [PATCH 1/5] usb: dwc3-generic: implement Qualcomm wrapper
Hi Marek,
On 06/02/2024 20:36, Marek Vasut wrote:
> On 1/31/24 15:57, Caleb Connolly wrote:
>> The Qualcomm specific dwc3 wrapper isn't hugely complicated, implemented
>> the missing initialisation for host and gadget mode.
>>
>> Signed-off-by: Caleb Connolly
>> ---
>> drivers/usb/dwc3/dwc3-generic.c | 99
>> -
>> 1 file changed, 98 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/usb/dwc3/dwc3-generic.c
>> b/drivers/usb/dwc3/dwc3-generic.c
>> index 48da621ba966..1119cdecd26d 100644
>> --- a/drivers/usb/dwc3/dwc3-generic.c
>> +++ b/drivers/usb/dwc3/dwc3-generic.c
>> @@ -419,6 +419,99 @@ struct dwc3_glue_ops ti_ops = {
>> .glue_configure = dwc3_ti_glue_configure,
>> };
>> +/* USB QSCRATCH Hardware registers */
>> +#define QSCRATCH_HS_PHY_CTRL 0x10
>> +#define UTMI_OTG_VBUS_VALID BIT(20)
>> +#define SW_SESSVLD_SEL BIT(28)
>> +
>> +#define QSCRATCH_SS_PHY_CTRL 0x30
>> +#define LANE0_PWR_PRESENT BIT(24)
>> +
>> +#define QSCRATCH_GENERAL_CFG 0x08
>> +#define PIPE_UTMI_CLK_SEL BIT(0)
>> +#define PIPE3_PHYSTATUS_SW BIT(3)
>> +#define PIPE_UTMI_CLK_DIS BIT(8)
>> +
>> +#define PWR_EVNT_IRQ_STAT_REG 0x58
>> +#define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
>> +#define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
>> +
>> +#define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
>> +#define SDM845_QSCRATCH_SIZE 0x400
>> +#define SDM845_DWC3_CORE_SIZE 0xcd00
>
> Newline here please
>
>> +static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset,
>> u32 val)
>> +{
>> + u32 reg;
>> +
>> + reg = readl(base + offset);
>> + reg |= val;
>> + writel(reg, base + offset);
>
> Use setbits_le32() .
>
>> + /* ensure that above write is through */
>> + readl(base + offset);
>
> Is this needed ?
I honestly don't know, this is copied from the Linux driver and it seems
to be very defensively written. I doubt it's strictly necessary.
>
>> +}
>> +
>> +static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset,
>> u32 val)
>> +{
>> + u32 reg;
>> +
>> + reg = readl(base + offset);
>> + reg &= ~val;
>> + writel(reg, base + offset);
>
> clrbits_le32()
>
>> + /* ensure that above write is through */
>> + readl(base + offset);
>> +}
>> +
>> +static void dwc3_qcom_vbus_override_enable(void __iomem
>> *qscratch_base, bool enable)
>> +{
>> + if (enable) {
>> + dwc3_qcom_setbits(qscratch_base, QSCRATCH_SS_PHY_CTRL,
>> + LANE0_PWR_PRESENT);
>> + dwc3_qcom_setbits(qscratch_base, QSCRATCH_HS_PHY_CTRL,
>> + UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
>> + } else {
>> + dwc3_qcom_clrbits(qscratch_base, QSCRATCH_SS_PHY_CTRL,
>> + LANE0_PWR_PRESENT);
>> + dwc3_qcom_clrbits(qscratch_base, QSCRATCH_HS_PHY_CTRL,
>> + UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
>> + }
>> +}
>> +
>> +/* For controllers running without superspeed PHYs */
>> +static void dwc3_qcom_select_utmi_clk(void __iomem *qscratch_base)
>> +{
>> + /* Configure dwc3 to use UTMI clock as PIPE clock not present */
>> + dwc3_qcom_setbits(qscratch_base, QSCRATCH_GENERAL_CFG,
>> + PIPE_UTMI_CLK_DIS);
>> +
>> + udelay(500);
>
> Isn't there some possibility to poll for completion instead of fixed
> delay ? If so, use wait_for_bit or some such .
Not that I'm aware of, no. I think this hardware just has a blanket
"writes take X bus cycles to complete" rule or something. It's totally
possible that this code was originally written this way to work around
some issues on an FPGA prototype or something. Everything seems to still
work if I remove the delays so I'll drop them...
>
>> + dwc3_qcom_setbits(qscratch_base, QSCRATCH_GENERAL_CFG,
>> + PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
>> +
>> + udelay(500);
>> +
>> + dwc3_qcom_clrbits(qscratch_base, QSCRATCH_GENERAL_CFG,
>> + PIPE_UTMI_CLK_DIS);
>> +}
>> +
>> +static void dwc3_qcom_glue_configure(struct udevice *dev, int index,
>> + enum usb_dr_mode mode)
>> +{
>> + void __iomem *qscratch_base = (void __iomem *)dev_read_addr(dev);
>
> Can this be NULL ? If yes, add check for != NULL .
Will do.
>
>> + if (dev_read_bool(dev, "qcom,select-utmi-as-pipe-clk"))
>> + dwc3_qcom_select_utmi_clk(qscratch_base);
>> +
>> + if (mode != USB_DR_MODE_HOST)
>> + dwc3_qcom_vbus_override_enable(qscratch_base, true);
>> +}
>> +
>> +struct dwc3_glue_ops qcom_ops = {
>> + .glue_configure = dwc3_qcom_glue_configure,
>> +};
>> +
>> static int dwc3_rk_glue_get_ctrl_dev(struct udevice *dev, ofnode *node)
>> {
>> *node = dev_ofnode(dev);
>> @@ -506,6 +599,10 @@ static int dwc3_glue_reset_init(struct udevice *dev,
>> else if (ret)
>> return ret;
>> + if (device_is_compatible(dev, "qcom,dwc3")) {
>> + reset_assert_bulk(>resets);
>> + udelay(500);
>
> Why this delay here ?
According to the docs, the reset should be asserted for at least 6 sleep
clock
Re: [PATCH v4 2/2] android_ab: Fix ANDROID_AB_BACKUP_OFFSET
Hi Colin,
On Tue, Mar 12, 2024 at 4:19 PM Mattijs Korpershoek <
mkorpersh...@baylibre.com> wrote:
> Hi Colin,
>
> Thank you for the patch.
>
> On mar., mars 12, 2024 at 07:57, Colin McAllister
> wrote:
>
> Sam also gave his review here:
>
> https://lore.kernel.org/all/CAPLW+4kHmPtfACyND4Vc2p0ZrsyGY=+bRU=fdub4k1ux5p3...@mail.gmail.com/
>
> Please include his review tag in the next submission.
>
> I will add it at the appropriate place below:
>
>
> > From: Colin McAllister
> >
> > Currently, setting CONFIG_AB_BACKUP_OFFSET in a target's defconfig will
> > not actually enable the #if protected code in android_ab.c. This is
> > because "CONFIG_" should have been prepended to the config macro, or the
> > macros defined in kconfig.h could have been used.
> >
> > The code included by ANDROID_AB_BACKUP_OFFSET has been refactored to no
> > longer be conditionally compiled by preprocessor conditionals and
> > instead use C conditionals. This better aligns with the Linux kernel
> > style guide.
> >
> > Fixes: 3430f24bc6 ("android_ab: Try backup booloader_message")
> > Signed-off-by: Colin McAllister
> > Cc: Joshua Watt
> > Cc: Simon Glass
> > Signed-off-by: Colin McAllister
> Reviewed-by: Sam Protsenko
>
> > ---
> > v2:
> > - Replaced #if conditionals with C if conditionals
> > - Opted to use CONFIG_ANDROID_AB_BACKUP_OFFSET directly instead of
> > macros in kconfig.h as CONFIG_ANDROID_AB_BACKUP_OFFSET is not a
> > boolean or tristate value and doesn't have different values when
> > building SPL or TPL.
> > v3:
> > - Added "Fixes:" tag
> > v4:
> > - No changes
> >
> > boot/android_ab.c | 97 ++-
> > 1 file changed, 45 insertions(+), 52 deletions(-)
> >
> > diff --git a/boot/android_ab.c b/boot/android_ab.c
> > index 9a3d15ec60..f547aa64e4 100644
> > --- a/boot/android_ab.c
> > +++ b/boot/android_ab.c
> > @@ -187,13 +187,12 @@ int ab_select_slot(struct blk_desc *dev_desc,
> struct disk_partition *part_info,
> > bool dec_tries)
> > {
> > struct bootloader_control *abc = NULL;
> > + struct bootloader_control *backup_abc = NULL;
> > u32 crc32_le;
> > int slot, i, ret;
> > bool store_needed = false;
> > + bool valid_backup = false;
> > char slot_suffix[4];
> > -#if ANDROID_AB_BACKUP_OFFSET
> > - struct bootloader_control *backup_abc = NULL;
> > -#endif
> >
> > ret = ab_control_create_from_disk(dev_desc, part_info, , 0);
> > if (ret < 0) {
> > @@ -205,53 +204,49 @@ int ab_select_slot(struct blk_desc *dev_desc,
> struct disk_partition *part_info,
> > return ret;
> > }
> >
> > -#if ANDROID_AB_BACKUP_OFFSET
> > - ret = ab_control_create_from_disk(dev_desc, part_info, _abc,
> > - ANDROID_AB_BACKUP_OFFSET);
> > - if (ret < 0) {
> > - free(abc);
> > - return ret;
> > + if (CONFIG_ANDROID_AB_BACKUP_OFFSET) {
> > + ret = ab_control_create_from_disk(dev_desc, part_info,
> _abc,
> > +
> CONFIG_ANDROID_AB_BACKUP_OFFSET);
> > + if (ret < 0) {
> > + free(abc);
> > + return ret;
> > + }
> > }
> > -#endif
> >
> > crc32_le = ab_control_compute_crc(abc);
> > if (abc->crc32_le != crc32_le) {
> > log_err("ANDROID: Invalid CRC-32 (expected %.8x, found
> %.8x),",
> > crc32_le, abc->crc32_le);
> > -#if ANDROID_AB_BACKUP_OFFSET
> > - crc32_le = ab_control_compute_crc(backup_abc);
> > - if (backup_abc->crc32_le != crc32_le) {
> > - log_err("ANDROID: Invalid backup CRC-32 ");
> > - log_err("expected %.8x, found %.8x),",
> > - crc32_le, backup_abc->crc32_le);
> > -#endif
> > -
> > - log_err("re-initializing A/B metadata.\n");
> > + if (CONFIG_ANDROID_AB_BACKUP_OFFSET) {
> > + crc32_le = ab_control_compute_crc(backup_abc);
> > + if (backup_abc->crc32_le != crc32_le) {
> > + log_err(" ANDROID: Invalid backup CRC-32
> ");
> > + log_err("(expected %.8x, found %.8x),",
> > + crc32_le, backup_abc->crc32_le);
> > + } else {
> > + valid_backup = true;
> > + log_info(" copying A/B metadata from
> backup.\n");
> > + memcpy(abc, backup_abc, sizeof(*abc));
> > + }
> > + }
> >
> > + if (!valid_backup) {
> > + log_err(" re-initializing A/B metadata.\n");
> > ret = ab_control_default(abc);
> > if (ret < 0) {
> > -#if ANDROID_AB_BACKUP_OFFSET
> > - free(backup_abc);
> > -#endif
> > +
Re: [PATCH v4 1/2] android_ab: Add missing semicolon
Hi Colin,
On Tue, Mar 12, 2024 at 1:57 PM Colin McAllister
wrote:
> From: Colin McAllister
>
> Found a missing semicolon in code protected by a #if that will never
> evaluate to true due to a separate issue. Fixing this issue before
> addressing the #if.
>
> Fixes: 3430f24bc6 ("android_ab: Try backup booloader_message")
> Signed-off-by: Colin McAllister
> Cc: Joshua Watt
> Cc: Simon Glass
> Signed-off-by: Colin McAllister
> ---
> v2: No changes
> v3: Added "Fixes:" tag
> v4: No changes
>
> boot/android_ab.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/boot/android_ab.c b/boot/android_ab.c
> index c9df6d2b4b..9a3d15ec60 100644
> --- a/boot/android_ab.c
> +++ b/boot/android_ab.c
> @@ -221,7 +221,7 @@ int ab_select_slot(struct blk_desc *dev_desc, struct
> disk_partition *part_info,
> #if ANDROID_AB_BACKUP_OFFSET
> crc32_le = ab_control_compute_crc(backup_abc);
> if (backup_abc->crc32_le != crc32_le) {
> - log_err("ANDROID: Invalid backup CRC-32 ")
> + log_err("ANDROID: Invalid backup CRC-32 ");
> log_err("expected %.8x, found %.8x),",
> crc32_le, backup_abc->crc32_le);
> #endif
> --
> 2.34.1
>
>
Reviewed-by: Igor Opaniuk
--
Best regards - Atentamente - Meilleures salutations
Igor Opaniuk
mailto: igor.opan...@gmail.com
skype: igor.opanyuk
https://www.linkedin.com/in/iopaniuk
Re: [PATCH v3 3/4] clk: qcom: add support for power domains uclass
On 11/03/2024 21:33, Volodymyr Babchuk wrote:
> Now sub-drivers for particular SoCs can register them as power domain
> drivers. This is needed for upcoming SM8150 support, because it needs
> to power up the Ethernet module.
>
> Signed-off-by: Volodymyr Babchuk
>
> ---
> Caleb suggested to use "imply POWER_DOMAIN", not "depends
> POWER_DOMAIN" in the Kconfig, but this does not work:
> $ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=arm
> scripts/kconfig/conf --syncconfig Kconfig
> drivers/clk/Kconfig:3:error: recursive dependency detected!
> drivers/clk/Kconfig:3: symbol CLK is selected by IMX8M_POWER_DOMAIN
> drivers/power/domain/Kconfig:35:symbol IMX8M_POWER_DOMAIN depends on
> POWER_DOMAIN
> drivers/power/domain/Kconfig:3: symbol POWER_DOMAIN is implied by CLK_QCOM
> drivers/clk/qcom/Kconfig:3: symbol CLK_QCOM depends on CLK
> For a resolution refer to Documentation/kbuild/kconfig-language.txt
> subsection "Kconfig recursive dependency limitations"
>
>
> Changes in v3:
> - Added "depends POWER_DOMAIN" to Kconfig (see note)
> - Use readl_poll_timeout() instead of open coded wait loop
> - Print warning if power domain can't be enabled/disabled
>
> Changes in v2:
> - Reworked qcom_cc_bind() function
> - Added timeout to qcom_power_set()
> - Minor fixes in register names and formatting
>
> drivers/clk/qcom/Kconfig | 2 +-
> drivers/clk/qcom/clock-qcom.c | 132 ++
> drivers/clk/qcom/clock-qcom.h | 6 ++
> 3 files changed, 126 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 0df0d1881a..8dae635ac2 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -2,7 +2,7 @@ if ARCH_SNAPDRAGON || ARCH_IPQ40XX
>
> config CLK_QCOM
> bool
> - depends on CLK && DM_RESET
> + depends on CLK && DM_RESET && POWER_DOMAIN
This results in a similar dependency error to the one above unless
CONFIG_POWER_DOMAIN is enabled in the defconfig. I think we'll just add
"select POWER_DOMAIN" to ARCH_SNAPDRAGON, same as we have for DM_RESET.
I'll do then when picking this series up, just a note to self.
> def_bool n
>
> menu "Qualcomm clock drivers"
> diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
> index 729d190c54..7a5938a06a 100644
> --- a/drivers/clk/qcom/clock-qcom.c
> +++ b/drivers/clk/qcom/clock-qcom.c
> @@ -22,7 +22,9 @@
> #include
> #include
> #include
> +#include
> #include
> +#include
>
> #include "clock-qcom.h"
>
> @@ -30,6 +32,13 @@
> #define CBCR_BRANCH_ENABLE_BIT BIT(0)
> #define CBCR_BRANCH_OFF_BIT BIT(31)
>
> +#define GDSC_SW_COLLAPSE_MASKBIT(0)
> +#define GDSC_POWER_DOWN_COMPLETE BIT(15)
> +#define GDSC_POWER_UP_COMPLETE BIT(16)
> +#define GDSC_PWR_ON_MASK BIT(31)
> +#define CFG_GDSCR_OFFSET 0x4
> +#define GDSC_STATUS_POLL_TIMEOUT_US 1500
> +
> /* Enable clock controlled by CBC soft macro */
> void clk_enable_cbc(phys_addr_t cbcr)
> {
> @@ -223,7 +232,7 @@ U_BOOT_DRIVER(qcom_clk) = {
> int qcom_cc_bind(struct udevice *parent)
> {
> struct msm_clk_data *data = (struct msm_clk_data
> *)dev_get_driver_data(parent);
> - struct udevice *clkdev, *rstdev;
> + struct udevice *clkdev = NULL, *rstdev = NULL, *pwrdev;
> struct driver *drv;
> int ret;
>
> @@ -238,20 +247,41 @@ int qcom_cc_bind(struct udevice *parent)
> if (ret)
> return ret;
>
> - /* Bail out early if resets are not specified for this platform */
> - if (!data->resets)
> - return ret;
> + if (data->resets) {
> + /* Get a handle to the common reset handler */
> + drv = lists_driver_lookup_name("qcom_reset");
> + if (!drv) {
> + ret = -ENOENT;
> + goto unbind_clkdev;
> + }
> +
> + /* Register the reset controller */
> + ret = device_bind_with_driver_data(parent, drv, "qcom_reset",
> (ulong)data,
> +dev_ofnode(parent), );
> + if (ret)
> + goto unbind_clkdev;
> + }
>
> - /* Get a handle to the common reset handler */
> - drv = lists_driver_lookup_name("qcom_reset");
> - if (!drv)
> - return -ENOENT;
> + if (data->power_domains) {
> + /* Get a handle to the common power domain handler */
> + drv = lists_driver_lookup_name("qcom_power");
> + if (!drv) {
> + ret = -ENOENT;
> + goto unbind_rstdev;
> + }
> + /* Register the power domain controller */
> + ret = device_bind_with_driver_data(parent, drv, "qcom_power",
> (ulong)data,
> +dev_ofnode(parent), );
> + if (ret)
> + goto unbind_rstdev;
> + }
Re: [PATCH v3 3/4] clk: qcom: add support for power domains uclass
Hi Volodymyr,
On 11/03/2024 21:33, Volodymyr Babchuk wrote:
> Now sub-drivers for particular SoCs can register them as power domain
> drivers. This is needed for upcoming SM8150 support, because it needs
> to power up the Ethernet module.
>
Thanks again for working on this.
I've been trying to rework my SDM845 USB support patches based on this,
and I've run into quite a few issues with CONFIG_POWER_DOMAIN.
Basically, it boils down to the RPM(h)PD, with no driver a bunch of
stuff breaks (including UART). I tried writing a no-op PD driver for it
but this didn't seem to work super well, and wouldn't scale (every soc
has it's own rpm(h)pd compatible).
In the end, I think supporting CONFIG_POWER_DOMAIN is the right approach
here. I have been able to get things working by leveraging OF_LIVE and
modifying the livetree during boot, similarly to how I plan to do for
USB. See [1].
Even with this, all the drivers we probe pre-relocation (like UART) need
the DM_FLAG_DEFAULT_PD_CTRL_OFF flag if they reference the RPM(h)PD, as
the of_fixup stuff doesn't happen until after relocation. I have a patch
which fixes that for sdm845 here [2].
I'll test this on the other boards and then re-send my USB patches
(including the two below) rebased on your series.
I'm a little worried this might come back to bite us later, but I think
by then it'll be worth trying to find a way to have U-Boot handle these
"safe to ignore" devices directly.
[1]:
https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/8af7731445721adab2206839d6df2d0f4f5f32d9
[2]:
https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/33b094103fb7e856cff6c08345a16ef8231ffaea
> Signed-off-by: Volodymyr Babchuk
>
> ---
> Caleb suggested to use "imply POWER_DOMAIN", not "depends
> POWER_DOMAIN" in the Kconfig, but this does not work:
> $ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=arm
> scripts/kconfig/conf --syncconfig Kconfig
> drivers/clk/Kconfig:3:error: recursive dependency detected!
> drivers/clk/Kconfig:3: symbol CLK is selected by IMX8M_POWER_DOMAIN
> drivers/power/domain/Kconfig:35:symbol IMX8M_POWER_DOMAIN depends on
> POWER_DOMAIN
> drivers/power/domain/Kconfig:3: symbol POWER_DOMAIN is implied by CLK_QCOM
> drivers/clk/qcom/Kconfig:3: symbol CLK_QCOM depends on CLK
> For a resolution refer to Documentation/kbuild/kconfig-language.txt
> subsection "Kconfig recursive dependency limitations"
>
>
> Changes in v3:
> - Added "depends POWER_DOMAIN" to Kconfig (see note)
> - Use readl_poll_timeout() instead of open coded wait loop
> - Print warning if power domain can't be enabled/disabled
>
> Changes in v2:
> - Reworked qcom_cc_bind() function
> - Added timeout to qcom_power_set()
> - Minor fixes in register names and formatting
>
> drivers/clk/qcom/Kconfig | 2 +-
> drivers/clk/qcom/clock-qcom.c | 132 ++
> drivers/clk/qcom/clock-qcom.h | 6 ++
> 3 files changed, 126 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 0df0d1881a..8dae635ac2 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -2,7 +2,7 @@ if ARCH_SNAPDRAGON || ARCH_IPQ40XX
>
> config CLK_QCOM
> bool
> - depends on CLK && DM_RESET
> + depends on CLK && DM_RESET && POWER_DOMAIN
> def_bool n
>
> menu "Qualcomm clock drivers"
> diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
> index 729d190c54..7a5938a06a 100644
> --- a/drivers/clk/qcom/clock-qcom.c
> +++ b/drivers/clk/qcom/clock-qcom.c
> @@ -22,7 +22,9 @@
> #include
> #include
> #include
> +#include
> #include
> +#include
>
> #include "clock-qcom.h"
>
> @@ -30,6 +32,13 @@
> #define CBCR_BRANCH_ENABLE_BIT BIT(0)
> #define CBCR_BRANCH_OFF_BIT BIT(31)
>
> +#define GDSC_SW_COLLAPSE_MASKBIT(0)
> +#define GDSC_POWER_DOWN_COMPLETE BIT(15)
> +#define GDSC_POWER_UP_COMPLETE BIT(16)
> +#define GDSC_PWR_ON_MASK BIT(31)
> +#define CFG_GDSCR_OFFSET 0x4
> +#define GDSC_STATUS_POLL_TIMEOUT_US 1500
> +
> /* Enable clock controlled by CBC soft macro */
> void clk_enable_cbc(phys_addr_t cbcr)
> {
> @@ -223,7 +232,7 @@ U_BOOT_DRIVER(qcom_clk) = {
> int qcom_cc_bind(struct udevice *parent)
> {
> struct msm_clk_data *data = (struct msm_clk_data
> *)dev_get_driver_data(parent);
> - struct udevice *clkdev, *rstdev;
> + struct udevice *clkdev = NULL, *rstdev = NULL, *pwrdev;
> struct driver *drv;
> int ret;
>
> @@ -238,20 +247,41 @@ int qcom_cc_bind(struct udevice *parent)
> if (ret)
> return ret;
>
> - /* Bail out early if resets are not specified for this platform */
> - if (!data->resets)
> - return ret;
> + if (data->resets) {
> + /* Get a handle to the common reset handler */
> + drv = lists_driver_lookup_name("qcom_reset");
> + if (!drv) {
>
Help: Marvell Armada 3720 board verified boot function as non-verified
Hi List Our project already several years develop for Marvell Armada 3720 board Recently we decided to implement verified boot. I modified uboot configuration to support FIT image format and verify signature kernel . I compiled uboot and added public key to u-boot.bin I also created signed kernel image and ensured with fit_check_signed it indeed signed. The problem is that Marvell required to use ATF tools and A3700 utils to produce flash image. I applied same command to ATF to make flash image as we used before for non-verified before. ATF made flash image with no glitch, After transferring resulting flash to board, u-boot continues to boot non-signed kernel and iminfo command reports error “unknown image format” on the loaded signed kernel, i.e. it does not recognize FIT partition. Can anyone help me ASAP? Regards LEV
[PATCH] gpio: mcp230xx: Add support for models with SPI interface.
Signed-off-by: Piotr Wojtaszczyk
---
drivers/gpio/Kconfig | 3 +
drivers/gpio/Makefile| 2 +-
drivers/gpio/mcp230xx_gpio.c | 144 ++-
3 files changed, 144 insertions(+), 5 deletions(-)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 2df3dc42d0..a7fb1eb3f4 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -256,6 +256,9 @@ config MCP230XX_GPIO
- MCP23008
- MCP23017
- MCP23018
+ - MCP23S08
+ - MCP23S17
+ - MCP23S18
config MSCC_SGPIO
bool "Microsemi Serial GPIO driver"
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index da3da5da2b..90711702a6 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -23,7 +23,7 @@ obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o
obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o
obj-$(CONFIG_IPROC_GPIO) += iproc_gpio.o
obj-$(CONFIG_KIRKWOOD_GPIO)+= kw_gpio.o
-obj-$(CONFIG_MCP230XX_GPIO)+= mcp230xx_gpio.o
+obj-$(CONFIG_$(SPL_TPL_)MCP230XX_GPIO) += mcp230xx_gpio.o
obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o
obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o
obj-$(CONFIG_NPCM_GPIO)+= npcm_gpio.o
diff --git a/drivers/gpio/mcp230xx_gpio.c b/drivers/gpio/mcp230xx_gpio.c
index 9f02fd42b3..df99fde566 100644
--- a/drivers/gpio/mcp230xx_gpio.c
+++ b/drivers/gpio/mcp230xx_gpio.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -20,6 +21,13 @@ enum mcp230xx_type {
MCP23008,
MCP23017,
MCP23018,
+ MCP23S08,
+ MCP23S17,
+ MCP23S18,
+};
+
+struct mcp230xx_info {
+ uint dev_addr;
};
#define MCP230XX_IODIR 0x00
@@ -29,29 +37,136 @@ enum mcp230xx_type {
#define BANKSIZE 8
+#define MCP230XX_ADDR 0x20
+
+static int mcp230xx_read_spi(struct udevice *dev, uint reg_addr)
+{
+ struct mcp230xx_info *info = dev_get_plat(dev);
+ uint dev_addr, value = 0;
+ int ret;
+
+ /* set R/W bit for reading */
+ dev_addr = (info->dev_addr << 1) | 1;
+
+ ret = dm_spi_claim_bus(dev);
+ if (ret)
+ return ret;
+
+ ret = dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_BEGIN);
+ if (ret < 0)
+ goto fail;
+ udelay(1);
+
+ ret = dm_spi_xfer(dev, 8, _addr, NULL, 0);
+ if (ret < 0)
+ goto fail;
+
+ ret = dm_spi_xfer(dev, 8, _addr, NULL, 0);
+ if (ret < 0)
+ goto fail;
+
+ ret = dm_spi_xfer(dev, 8, NULL, , 0);
+
+fail:
+ dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END);
+ dm_spi_release_bus(dev);
+ if (ret < 0)
+ return ret;
+ return value;
+}
+
static int mcp230xx_read(struct udevice *dev, uint reg, uint offset)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
int bank = offset / BANKSIZE;
int mask = 1 << (offset % BANKSIZE);
int shift = (uc_priv->gpio_count / BANKSIZE) - 1;
- int ret;
+ int reg_addr = (reg << shift) | bank;
+ int ret = 0;
+
+ switch (dev_get_driver_data(dev)) {
+ case MCP23008:
+ case MCP23017:
+ case MCP23018:
+ ret = dm_i2c_reg_read(dev, reg_addr);
+ break;
+ case MCP23S08:
+ case MCP23S17:
+ case MCP23S18:
+ ret = mcp230xx_read_spi(dev, reg_addr);
+ break;
+ default:
+ return -ENODEV;
+ }
- ret = dm_i2c_reg_read(dev, (reg << shift) | bank);
if (ret < 0)
return ret;
return !!(ret & mask);
}
+static int mcp230xx_clrset_spi(struct udevice *dev, uint reg_addr, uint clr,
uint set)
+{
+ struct mcp230xx_info *info = dev_get_plat(dev);
+ int dev_addr, value;
+ int ret;
+
+ /* R/W bit = 0 for writing */
+ dev_addr = (info->dev_addr << 1);
+
+ ret = mcp230xx_read_spi(dev, reg_addr);
+ if (ret < 0)
+ return ret;
+
+ value = ret;
+ value &= ~clr;
+ value |= set;
+
+ ret = dm_spi_claim_bus(dev);
+ if (ret)
+ return ret;
+
+ ret = dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_BEGIN);
+ if (ret < 0)
+ goto fail;
+ udelay(1);
+
+ ret = dm_spi_xfer(dev, 8, _addr, NULL, 0);
+ if (ret < 0)
+ goto fail;
+
+ ret = dm_spi_xfer(dev, 8, _addr, NULL, 0);
+ if (ret < 0)
+ goto fail;
+
+ ret = dm_spi_xfer(dev, 8, , NULL, 0);
+
+fail:
+ dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END);
+ dm_spi_release_bus(dev);
+ return ret;
+}
+
static int mcp230xx_write(struct udevice *dev, uint reg, uint offset, bool val)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
int bank = offset / BANKSIZE;
int mask = 1 << (offset % BANKSIZE);
int shift = (uc_priv->gpio_count / BANKSIZE) - 1;
+ int
Re: [PATCH] imx8m*_venice: move venice to OF_UPSTREAM
On Wed, Mar 13, 2024 at 6:20 AM Sumit Garg wrote:
>
> On Wed, 13 Mar 2024 at 06:46, Fabio Estevam wrote:
> >
> > Hi Tim,
> >
> > On Tue, Mar 12, 2024 at 4:05 PM Tim Harvey wrote:
> > >
> > > Move to imx8m{m,n,p}-venice to OF_UPSTREAM:
> > > - replace the non-upstream generic imx8m{m,n,p}-venice dt with one of the
> > >dt's from the OF_LIST
> > > - handle the fact that dtbs now have a 'freescale/' prefix
> > > - imply OF_UPSTREAM
> > > - remove rudundant files from arch/arm/dts leaving only the
> > >*-u-boot.dtsi files
> > >
> > > Signed-off-by: Tim Harvey
> > ...
> > > 33 files changed, 13 insertions(+), 10658 deletions(-)
> >
> > This diff looks great :-)
>
> +1
>
> Reviewed-by: Sumit Garg
>
Hi Sumit,
Thanks for your work on this - I imagine over time this will
de-duplicate a lot of work!
I have a couple of questions about OF_UPSTREAM I haven't found the
answer to yet:
1. how do you determine what the last sync point was in dts/upstream?
(ie what kernel version is it currently sync'd with)
2. how often will dts/upstream get re-synced (not the
devicetree-rebasing.git but u-boot dts/upstream), who do you suspect
will do be doing it?
3. how would one go about adding a new feature via dt to uboot when
the same feature has not yet landed in dts upstream? perhaps the
answer is it must land upstream first or do you suspect it would be ok
to put something in a u-boot.dtsi that can later get removed as
redundant? I ask mainly for being able to add things quickly to a
downstream U-Boot repo that lags behind upstream U-Boot
Best Regards,
Tim
Re: [PATCH] colibri-imx8x: Fix sc_misc_otp_fuse_read() error check
On 13.03.2024 08:09, Marcel Ziswiler wrote:
> Hi Fabio
>
> Thanks!
>
> On Tue, 2024-03-12 at 21:36 -0300, Fabio Estevam wrote:
> > Commit aa6e698a7acd ("imx: toradex/colibri-imx8x: correct SCU API usage")
> > made an incorrect logic change in the error code check of
> > sc_misc_otp_fuse_read():
> >
> > - if (sc_err == SC_ERR_NONE) {
> > + if (sc_err) {
> > /* DX has two A35 cores disabled */
> > return (val & 0xf) != 0x0;
> > }
> >
> > The other changes in this commit are correct.
> >
> > sc_misc_otp_fuse_read() returns 0 on a successful fuse read.
> >
> > This inversion causes board_mem_get_layout() to report incorrect RAM size.
> >
> > Go back the original error check logic to fix the problem.
> >
> > Fixes: aa6e698a7acd ("imx: toradex/colibri-imx8x: correct SCU API usage")
> > Reported-by: Hiago De Franco
> > Signed-off-by: Fabio Estevam
>
> Acked-by: Marcel Ziswiler
>
Tested-by: Hiago De Franco # Toradex Colibri iMX8X
1GB
> > diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c
> > b/board/toradex/colibri-imx8x/colibri-imx8x.c
> > index 2c673a4a6b06..6fc8076163c6 100644
> > --- a/board/toradex/colibri-imx8x/colibri-imx8x.c
> > +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c
> > @@ -46,7 +46,7 @@ static int is_imx8dx(void)
> > u32 val = 0;
> > int sc_err = sc_misc_otp_fuse_read(-1, 6, );
> >
> > - if (sc_err) {
> > + if (!sc_err) {
> > /* DX has two A35 cores disabled */
> > return (val & 0xf) != 0x0;
> > }
>
> Cheers
>
> Marcel
[PATCH v3 7/7] arm: remove redundant section alignments
Previous patches cleaning up linker symbols, also merged any explicit
. = ALIGN(x); into section definitions -- e.g
.bss ALIGN(x) : instead of
. = ALIGN(x);
. bss : {...}
However, if the output address is not specified then one will be chosen
for the section. This address will be adjusted to fit the alignment
requirement of the output section following the strictest alignment of
any input section contained within the output section. So let's get rid
of the redundant ALIGN directives when they are not needed.
While at add comments for the alignment of __bss_start/end since our
C runtime setup assembly assumes that __bss_start - __bss_end will be
a multiple of 4/8 for armv7 and armv8 respectively.
It's worth noting that the alignment is preserved on .rel.dyn for
mach-zynq which was explicitly aligning that section on an 8b
boundary instead of 4b one.
Signed-off-by: Ilias Apalodimas
---
arch/arm/cpu/armv8/u-boot.lds | 9 ++---
arch/arm/cpu/u-boot.lds | 8 ++--
arch/arm/mach-zynq/u-boot.lds | 4 ++--
3 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index 147a6e8028d5..857f44412e07 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -115,7 +115,7 @@ SECTIONS
KEEP(*(SORT(__u_boot_list*)));
}
- .efi_runtime_rel ALIGN(8) : {
+ .efi_runtime_rel : {
__efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
*(.rel*.efi_runtime.*)
@@ -125,7 +125,7 @@ SECTIONS
. = ALIGN(8);
__image_copy_end = .;
- .rela.dyn ALIGN(8) : {
+ .rela.dyn : {
__rel_dyn_start = .;
*(.rela*)
__rel_dyn_end = .;
@@ -133,7 +133,10 @@ SECTIONS
_end = .;
- .bss ALIGN(8): {
+ /*
+* arch/arm/lib/crt0_64.S assumes __bss_start - __bss_end % 8 == 0
+*/
+ .bss ALIGN(8) : {
__bss_start = .;
*(.bss*)
. = ALIGN(8);
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 798858e3ed6e..707b19795f08 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -43,7 +43,7 @@ SECTIONS
}
/* This needs to come before *(.text*) */
- .efi_runtime ALIGN(4) : {
+ .efi_runtime : {
__efi_runtime_start = .;
*(.text.efi_runtime*)
*(.rodata.efi_runtime*)
@@ -146,7 +146,7 @@ SECTIONS
KEEP(*(SORT(__u_boot_list*)));
}
- .efi_runtime_rel ALIGN(4) : {
+ .efi_runtime_rel : {
__efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
*(.rel*.efi_runtime.*)
@@ -156,6 +156,10 @@ SECTIONS
. = ALIGN(4);
__image_copy_end = .;
+ /*
+* if CONFIG_USE_ARCH_MEMSET is not selected __bss_end - __bss_start
+* needs to be a multiple of 4 and we overlay .bss with .rel.dyn
+*/
.rel.dyn ALIGN(4) : {
__rel_dyn_start = .;
*(.rel*)
diff --git a/arch/arm/mach-zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds
index f6c99a8ce218..3e0c96c50556 100644
--- a/arch/arm/mach-zynq/u-boot.lds
+++ b/arch/arm/mach-zynq/u-boot.lds
@@ -22,7 +22,7 @@ SECTIONS
}
/* This needs to come before *(.text*) */
- .efi_runtime ALIGN(4) : {
+ .efi_runtime : {
__efi_runtime_start = .;
*(.text.efi_runtime*)
*(.rodata.efi_runtime*)
@@ -52,7 +52,7 @@ SECTIONS
KEEP(*(SORT(__u_boot_list*)));
}
- .efi_runtime_rel ALIGN(4) : {
+ .efi_runtime_rel : {
__efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
*(.rel*.efi_runtime.*)
--
2.37.2
[PATCH v3 6/7] arm: move image_copy_start/end to linker symbols
image_copy_start/end are defined as c variables in order to force the
compiler emit relative references. However, defining those within a section
definition will do the same thing since [0].
So let's remove the special sections from the linker scripts, the
variable definitions from sections.c and define them as a symbols within
a section.
[0] binutils commit 6b3b0ab89663 ("Make linker assigned symbol dynamic only for
shared object")
Suggested-by: Sam Edwards
Reviewed-by: Richard Henderson
Tested-by: Sam Edwards # Binary output identical
Signed-off-by: Ilias Apalodimas
---
arch/arm/cpu/armv8/u-boot-spl.lds | 8 +++-
arch/arm/cpu/armv8/u-boot.lds | 8 ++--
arch/arm/cpu/u-boot-spl.lds | 2 +-
arch/arm/cpu/u-boot.lds | 8 ++--
arch/arm/lib/sections.c | 2 --
arch/arm/mach-aspeed/ast2600/u-boot-spl.lds | 2 +-
arch/arm/mach-rockchip/u-boot-tpl-v8.lds| 8 +++-
arch/arm/mach-zynq/u-boot-spl.lds | 2 +-
arch/arm/mach-zynq/u-boot.lds | 7 ++-
9 files changed, 15 insertions(+), 32 deletions(-)
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds
b/arch/arm/cpu/armv8/u-boot-spl.lds
index 692414fe46fb..2e61f759ee6b 100644
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -21,9 +21,9 @@ OUTPUT_ARCH(aarch64)
ENTRY(_start)
SECTIONS
{
+ __image_copy_start = ADDR(.text);
.text : {
. = ALIGN(8);
- __image_copy_start = .;
CPUDIR/start.o (.text*)
*(.text*)
} >.sram
@@ -51,10 +51,8 @@ SECTIONS
KEEP(*(SORT(__u_boot_list*)));
} >.sram
- .image_copy_end : {
- . = ALIGN(8);
- *(.__image_copy_end)
- } >.sram
+ . = ALIGN(8);
+ __image_copy_end = .;
.end : {
. = ALIGN(8);
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index 5ba54dcedf24..147a6e8028d5 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -21,9 +21,9 @@ SECTIONS
. = 0x;
. = ALIGN(8);
+ __image_copy_start = ADDR(.text);
.text :
{
- *(.__image_copy_start)
CPUDIR/start.o (.text*)
}
@@ -123,11 +123,7 @@ SECTIONS
}
. = ALIGN(8);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
+ __image_copy_end = .;
.rela.dyn ALIGN(8) : {
__rel_dyn_start = .;
diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds
index fb2189d50dea..9ed62395a9c5 100644
--- a/arch/arm/cpu/u-boot-spl.lds
+++ b/arch/arm/cpu/u-boot-spl.lds
@@ -14,9 +14,9 @@ SECTIONS
. = 0x;
. = ALIGN(4);
+ __image_copy_start = ADDR(.text);
.text :
{
- __image_copy_start = .;
*(.vectors)
CPUDIR/start.o (.text*)
*(.text*)
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 6813d8aeb838..798858e3ed6e 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -35,9 +35,9 @@ SECTIONS
. = 0x;
. = ALIGN(4);
+ __image_copy_start = ADDR(.text);
.text :
{
- *(.__image_copy_start)
*(.vectors)
CPUDIR/start.o (.text*)
}
@@ -154,11 +154,7 @@ SECTIONS
}
. = ALIGN(4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
+ __image_copy_end = .;
.rel.dyn ALIGN(4) : {
__rel_dyn_start = .;
diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c
index a4d4202e99f5..db5463b2bbbc 100644
--- a/arch/arm/lib/sections.c
+++ b/arch/arm/lib/sections.c
@@ -19,8 +19,6 @@
* aliasing warnings.
*/
-char __image_copy_start[0] __section(".__image_copy_start");
-char __image_copy_end[0] __section(".__image_copy_end");
char __secure_start[0] __section(".__secure_start");
char __secure_end[0] __section(".__secure_end");
char __secure_stack_start[0] __section(".__secure_stack_start");
diff --git a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
index 37f0ccd92201..ada6570d9712 100644
--- a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
+++ b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
@@ -22,9 +22,9 @@ SECTIONS
. = 0x;
. = ALIGN(4);
+ __image_copy_start = ADDR(.text);
.text :
{
- __image_copy_start = .;
*(.vectors)
CPUDIR/start.o (.text*)
*(.text*)
diff --git a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
index 712c485d4d0b..ad32654085b3 100644
--- a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
+++ b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
@@ -22,9 +22,9 @@ SECTIONS
{
[PATCH v3 5/7] arm: fix __efi_runtime_start/end definitions
__efi_runtime_start/end are defined as c variables for arm7 only in
order to force the compiler emit relative references. However, defining
those within a section definition will do the same thing since [0].
On top of that the v8 linker scripts define it as a symbol.
So let's remove the special sections from the linker scripts, the
variable definitions from sections.c and define them as a symbols within
the correct section.
[0] binutils commit 6b3b0ab89663 ("Make linker assigned symbol dynamic only for
shared object")
Suggested-by: Sam Edwards
Reviewed-by: Sam Edwards
Reviewed-by: Richard Henderson
Tested-by: Sam Edwards # Binary output identical
Signed-off-by: Ilias Apalodimas
---
arch/arm/cpu/u-boot.lds| 12 +++-
arch/arm/lib/sections.c| 2 --
arch/arm/mach-zynq/u-boot.lds | 12 +++-
include/asm-generic/sections.h | 1 +
4 files changed, 7 insertions(+), 20 deletions(-)
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 0682d34207fa..6813d8aeb838 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -43,18 +43,12 @@ SECTIONS
}
/* This needs to come before *(.text*) */
- .__efi_runtime_start : {
- *(.__efi_runtime_start)
- }
-
- .efi_runtime : {
+ .efi_runtime ALIGN(4) : {
+ __efi_runtime_start = .;
*(.text.efi_runtime*)
*(.rodata.efi_runtime*)
*(.data.efi_runtime*)
- }
-
- .__efi_runtime_stop : {
- *(.__efi_runtime_stop)
+ __efi_runtime_stop = .;
}
.text_rest :
diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c
index 1ee3dd3667ba..a4d4202e99f5 100644
--- a/arch/arm/lib/sections.c
+++ b/arch/arm/lib/sections.c
@@ -25,6 +25,4 @@ char __secure_start[0] __section(".__secure_start");
char __secure_end[0] __section(".__secure_end");
char __secure_stack_start[0] __section(".__secure_stack_start");
char __secure_stack_end[0] __section(".__secure_stack_end");
-char __efi_runtime_start[0] __section(".__efi_runtime_start");
-char __efi_runtime_stop[0] __section(".__efi_runtime_stop");
char _end[0] __section(".__end");
diff --git a/arch/arm/mach-zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds
index 3b1f0d349356..9eac7de0dcbd 100644
--- a/arch/arm/mach-zynq/u-boot.lds
+++ b/arch/arm/mach-zynq/u-boot.lds
@@ -22,18 +22,12 @@ SECTIONS
}
/* This needs to come before *(.text*) */
- .__efi_runtime_start : {
- *(.__efi_runtime_start)
- }
-
- .efi_runtime : {
+ .efi_runtime ALIGN(4) : {
+ __efi_runtime_start = .;
*(.text.efi_runtime*)
*(.rodata.efi_runtime*)
*(.data.efi_runtime*)
- }
-
- .__efi_runtime_stop : {
- *(.__efi_runtime_stop)
+ __efi_runtime_stop = .;
}
.text_rest :
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 60949200dd93..b6bca53db10d 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -35,6 +35,7 @@ extern char __priv_data_start[], __priv_data_end[];
extern char __ctors_start[], __ctors_end[];
extern char __efi_runtime_rel_start[], __efi_runtime_rel_stop[];
+extern char __efi_runtime_start[], __efi_runtime_stop[];
/* function descriptor handling (if any). Override
* in asm/sections.h */
--
2.37.2
[PATCH v3 4/7] arm: clean up v7 and v8 linker scripts for __rel_dyn_start/end
commit 47bd65ef057f ("arm: make __rel_dyn_{start, end} compiler-generated")
were moving the __rel_dyn_start/end on c generated variables that were
injected in their own sections. The reason was that we needed relative
relocations for position independent code and linker bugs back then
prevented us from doing so [0].
However, the linker documentation pages states that symbols that are
defined within a section definition will create a relocatable
type with the value being a fixed offset from the base of a section [1].
[0] binutils commit 6b3b0ab89663 ("Make linker assigned symbol dynamic only for
shared object")
[1] https://sourceware.org/binutils/docs/ld/Expression-Section.html
Suggested-by: Sam Edwards
Reviewed-by: Sam Edwards
Reviewed-by: Richard Henderson
Tested-by: Sam Edwards # Binary output identical
Signed-off-by: Ilias Apalodimas
---
arch/arm/cpu/armv8/u-boot.lds | 16 +++-
arch/arm/cpu/u-boot.lds | 14 +++---
arch/arm/lib/sections.c | 2 --
arch/arm/mach-zynq/u-boot.lds | 14 +++---
4 files changed, 9 insertions(+), 37 deletions(-)
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index 8561e1b3142e..5ba54dcedf24 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -129,20 +129,10 @@ SECTIONS
*(.__image_copy_end)
}
- . = ALIGN(8);
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rela.dyn : {
+ .rela.dyn ALIGN(8) : {
+ __rel_dyn_start = .;
*(.rela*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
+ __rel_dyn_end = .;
}
_end = .;
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index f19f2812ee91..0682d34207fa 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -166,18 +166,10 @@ SECTIONS
*(.__image_copy_end)
}
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
+ .rel.dyn ALIGN(4) : {
+ __rel_dyn_start = .;
*(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
+ __rel_dyn_end = .;
}
.end :
diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c
index ddfde52163fc..1ee3dd3667ba 100644
--- a/arch/arm/lib/sections.c
+++ b/arch/arm/lib/sections.c
@@ -21,8 +21,6 @@
char __image_copy_start[0] __section(".__image_copy_start");
char __image_copy_end[0] __section(".__image_copy_end");
-char __rel_dyn_start[0] __section(".__rel_dyn_start");
-char __rel_dyn_end[0] __section(".__rel_dyn_end");
char __secure_start[0] __section(".__secure_start");
char __secure_end[0] __section(".__secure_end");
char __secure_stack_start[0] __section(".__secure_stack_start");
diff --git a/arch/arm/mach-zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds
index bb0e0ceb32ec..3b1f0d349356 100644
--- a/arch/arm/mach-zynq/u-boot.lds
+++ b/arch/arm/mach-zynq/u-boot.lds
@@ -71,18 +71,10 @@ SECTIONS
*(.__image_copy_end)
}
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
+ .rel.dyn ALIGN(8) : {
+ __rel_dyn_start = .;
*(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
+ __rel_dyn_end = .;
}
.end :
--
2.37.2
[PATCH v3 3/7] arm: fix __efi_runtime_rel_start/end definitions
__efi_runtime_rel_start/end are defined as c variables for arm7 only in
order to force the compiler emit relative references. However, defining
those within a section definition will do the same thing since [0].
On top of that the v8 linker scripts define it as a symbol.
So let's remove the special sections from the linker scripts, the
variable definitions from sections.c and define them as a symbols within
the correct section.
[0] binutils commit 6b3b0ab89663 ("Make linker assigned symbol dynamic only for
shared object")
Suggested-by: Sam Edwards
Reviewed-by: Sam Edwards
Tested-by: Sam Edwards # Binary output identical
Reviewed-by: Richard Henderson
Signed-off-by: Ilias Apalodimas
---
arch/arm/cpu/armv8/u-boot.lds | 4 +---
arch/arm/cpu/u-boot.lds| 16 +++-
arch/arm/lib/sections.c| 2 --
arch/arm/mach-zynq/u-boot.lds | 16 +++-
include/asm-generic/sections.h | 2 ++
lib/efi_loader/efi_runtime.c | 1 +
6 files changed, 10 insertions(+), 31 deletions(-)
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index 9640cc7a04b8..8561e1b3142e 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -115,9 +115,7 @@ SECTIONS
KEEP(*(SORT(__u_boot_list*)));
}
- . = ALIGN(8);
-
- .efi_runtime_rel : {
+ .efi_runtime_rel ALIGN(8) : {
__efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
*(.rel*.efi_runtime.*)
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 0dfe5f633b16..f19f2812ee91 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -152,21 +152,11 @@ SECTIONS
KEEP(*(SORT(__u_boot_list*)));
}
- . = ALIGN(4);
-
- .efi_runtime_rel_start :
- {
- *(.__efi_runtime_rel_start)
- }
-
- .efi_runtime_rel : {
+ .efi_runtime_rel ALIGN(4) : {
+ __efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
*(.rel*.efi_runtime.*)
- }
-
- .efi_runtime_rel_stop :
- {
- *(.__efi_runtime_rel_stop)
+ __efi_runtime_rel_stop = .;
}
. = ALIGN(4);
diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c
index 8e8bd5797e16..ddfde52163fc 100644
--- a/arch/arm/lib/sections.c
+++ b/arch/arm/lib/sections.c
@@ -29,6 +29,4 @@ char __secure_stack_start[0]
__section(".__secure_stack_start");
char __secure_stack_end[0] __section(".__secure_stack_end");
char __efi_runtime_start[0] __section(".__efi_runtime_start");
char __efi_runtime_stop[0] __section(".__efi_runtime_stop");
-char __efi_runtime_rel_start[0] __section(".__efi_runtime_rel_start");
-char __efi_runtime_rel_stop[0] __section(".__efi_runtime_rel_stop");
char _end[0] __section(".__end");
diff --git a/arch/arm/mach-zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds
index 3c5008b57392..bb0e0ceb32ec 100644
--- a/arch/arm/mach-zynq/u-boot.lds
+++ b/arch/arm/mach-zynq/u-boot.lds
@@ -58,21 +58,11 @@ SECTIONS
KEEP(*(SORT(__u_boot_list*)));
}
- . = ALIGN(4);
-
- .efi_runtime_rel_start :
- {
- *(.__efi_runtime_rel_start)
- }
-
- .efi_runtime_rel : {
+ .efi_runtime_rel ALIGN(4) : {
+ __efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
*(.rel*.efi_runtime.*)
- }
-
- .efi_runtime_rel_stop :
- {
- *(.__efi_runtime_rel_stop)
+ __efi_runtime_rel_stop = .;
}
. = ALIGN(8);
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 1e1657a01673..60949200dd93 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -34,6 +34,8 @@ extern char __priv_data_start[], __priv_data_end[];
/* Start and end of .ctors section - used for constructor calls. */
extern char __ctors_start[], __ctors_end[];
+extern char __efi_runtime_rel_start[], __efi_runtime_rel_stop[];
+
/* function descriptor handling (if any). Override
* in asm/sections.h */
#ifndef dereference_function_descriptor
diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index 18da6892e796..9185f1894c47 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
/* For manual relocation support */
DECLARE_GLOBAL_DATA_PTR;
--
2.37.2
[PATCH v3 2/7] arm: clean up v7 and v8 linker scripts for bss_start/end
commit 3ebd1cbc49f0 ("arm: make __bss_start and __bss_end__ compiler-generated")
and
commit f84a7b8f54db ("ARM: Fix __bss_start and __bss_end in linker scripts")
were moving the bss_start/end on c generated variables that were
injected in their own sections. The reason was that we needed relative
relocations for position independent code and linker bugs back then
prevented us from doing so [0].
However, the linker documentation pages states that symbols that are
defined within a section definition will create a relocatable type with
the value being a fixed offset from the base of a section [1].
So let's start cleaning this up starting with the bss_start and bss_end
variables. Convert them into symbols within the .bss section definition.
[0] binutils commit 6b3b0ab89663 ("Make linker assigned symbol dynamic only for
shared object")
[1] https://sourceware.org/binutils/docs/ld/Expression-Section.html
Tested-by: Caleb Connolly # Qualcomm sdm845
Signed-off-by: Ilias Apalodimas
---
arch/arm/cpu/armv8/u-boot-spl.lds| 18 +++---
arch/arm/cpu/armv8/u-boot.lds| 16
arch/arm/cpu/u-boot.lds | 22 +++---
arch/arm/lib/sections.c | 2 --
arch/arm/mach-rockchip/u-boot-tpl-v8.lds | 15 ---
arch/arm/mach-zynq/u-boot.lds| 22 +++---
6 files changed, 29 insertions(+), 66 deletions(-)
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds
b/arch/arm/cpu/armv8/u-boot-spl.lds
index 7cb9d731246d..692414fe46fb 100644
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -63,18 +63,11 @@ SECTIONS
_image_binary_end = .;
- .bss_start (NOLOAD) : {
- . = ALIGN(8);
- KEEP(*(.__bss_start));
- } >.sdram
-
- .bss (NOLOAD) : {
+ .bss : {
+ __bss_start = .;
*(.bss*)
-. = ALIGN(8);
- } >.sdram
-
- .bss_end (NOLOAD) : {
- KEEP(*(.__bss_end));
+ . = ALIGN(8);
+ __bss_end = .;
} >.sdram
/DISCARD/ : { *(.rela*) }
@@ -89,3 +82,6 @@ SECTIONS
#include "linux-kernel-image-header-vars.h"
#endif
}
+ASSERT(CONFIG_SPL_BSS_START_ADDR % 8 == 0, \
+ "CONFIG_SPL_BSS_START_ADDR must be 8-byte aligned");
+
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index fb6a30c922f7..9640cc7a04b8 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -149,19 +149,11 @@ SECTIONS
_end = .;
- . = ALIGN(8);
-
- .bss_start : {
- KEEP(*(.__bss_start));
- }
-
- .bss : {
+ .bss ALIGN(8): {
+ __bss_start = .;
*(.bss*)
-. = ALIGN(8);
- }
-
- .bss_end : {
- KEEP(*(.__bss_end));
+ . = ALIGN(8);
+ __bss_end = .;
}
/DISCARD/ : { *(.dynsym) }
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 7724c9332c3b..0dfe5f633b16 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -207,23 +207,15 @@ SECTIONS
}
/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
+ * These sections occupy the same memory, but their lifetimes do
+ * not overlap: U-Boot initializes .bss only after applying dynamic
+ * relocations and therefore after it doesn't need .rel.dyn any more.
*/
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
+ .bss ADDR(.rel.dyn) (OVERLAY): {
+ __bss_start = .;
*(.bss*)
-. = ALIGN(4);
-__bss_limit = .;
- }
-
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
+ . = ALIGN(4);
+ __bss_end = .;
}
.dynsym _image_binary_end : { *(.dynsym) }
diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c
index 857879711c6a..8e8bd5797e16 100644
--- a/arch/arm/lib/sections.c
+++ b/arch/arm/lib/sections.c
@@ -19,8 +19,6 @@
* aliasing warnings.
*/
-char __bss_start[0] __section(".__bss_start");
-char __bss_end[0] __section(".__bss_end");
char __image_copy_start[0] __section(".__image_copy_start");
char __image_copy_end[0] __section(".__image_copy_end");
char __rel_dyn_start[0] __section(".__rel_dyn_start");
diff --git a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
index 74618eba591b..712c485d4d0b 100644
--- a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
+++ b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
@@ -56,18 +56,11 @@ SECTIONS
_image_binary_end = .;
- .bss_start (NOLOAD) : {
- . = ALIGN(8);
- KEEP(*(.__bss_start));
- }
-
[PATCH v3 1/7] arm: baltos: remove custom linker script
commit 3d74a0977f514 ("ti: am335x: Remove unused linker script") removed
the linker script for the TI variant. This linker script doesn't seem to
do anything special and on top of that, has no definitions for the EFI
runtime sections.
So let's get rid of it and use the generic linker script which defines
those correctly
Signed-off-by: Ilias Apalodimas
Reviewed-by: Tom Rini
---
board/vscom/baltos/u-boot.lds | 128 --
1 file changed, 128 deletions(-)
delete mode 100644 board/vscom/baltos/u-boot.lds
diff --git a/board/vscom/baltos/u-boot.lds b/board/vscom/baltos/u-boot.lds
deleted file mode 100644
index cb2ee6769753..
--- a/board/vscom/baltos/u-boot.lds
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering,
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x;
-
- . = ALIGN(4);
- .text :
- {
- *(.__image_copy_start)
- *(.vectors)
- CPUDIR/start.o (.text*)
- board/vscom/baltos/built-in.o (.text*)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- . = .;
-
- . = ALIGN(4);
- __u_boot_list : {
- KEEP(*(SORT(__u_boot_list*)));
- }
-
- . = ALIGN(4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- .hash : { *(.hash*) }
-
- .end :
- {
- *(.__end)
- }
-
- _image_binary_end = .;
-
- /*
-* Deprecated: this MMU section is used by pxa at present but
-* should not be used by new boards/CPUs.
-*/
- . = ALIGN(4096);
- .mmutable : {
- *(.mmutable)
- }
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
-. = ALIGN(4);
-__bss_limit = .;
- }
-
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _image_binary_end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .gnu.hash : { *(.gnu.hash) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
--
2.37.2
[PATCH v3 0/7] Clean up arm linker scripts
The arm linker scripts had a mix of symbols and C defined variables in an effort to emit relative references instead of absolute ones e.g [0]. A linker bug prevented us from doing so [1] -- fixed since 2016. This has led to confusion over the years, ending up with mixed section definitions. Some sections are defined with overlays and different definitions between v7 and v8 architectures. For example __efi_runtime_rel_start/end is defined as a linker symbol for armv8 and a C variable in armv7. Linker scripts nowadays can emit relative references, as long as the symbol definition is contained within the section definition. So let's switch most of the C defined variables and clean up the arm sections.c file. There's still a few symbols remaining -- __secure_start/end, __secure_stack_start/end and __end which can be cleaned up in a followup series. For both QEMU v7/v8 bloat-o-meter shows now size difference $~ ./scripts/bloat-o-meter u-boot u-boot.new add/remove: 0/0 grow/shrink: 0/0 up/down: 0/0 (0) Function old new delta Total: Before=798861, After=798861, chg +0.00% The symbols seem largely unchanged apart from a difference in .bss as well as the emited sections and object types of the affected variables. On the output below the first value is from -next and the second comes from -next + this patchset. The .bss_start/end sections have disappeared from the newer binaries. # For example on QEMU v8: efi_runtime_start 7945: 0178 0 OBJECT GLOBAL DEFAULT2 __efi_runtime_start 7942: 0178 0 NOTYPE GLOBAL DEFAULT2 __efi_runtime_start efi_runtime_stop 9050: 0d38 0 OBJECT GLOBAL DEFAULT2 __efi_runtime_stop 9047: 0d38 0 NOTYPE GLOBAL DEFAULT2 __efi_runtime_stop __efi_runtime_rel_start 7172: 000dc2f0 0 OBJECT GLOBAL DEFAULT 10 __efi_runtime_rel_start 7169: 000dc2f0 0 NOTYPE GLOBAL DEFAULT 10 __efi_runtime_rel_start __efi_runtime_rel_stop 7954: 000dc4a0 0 OBJECT GLOBAL DEFAULT 10 __efi_runtime_rel_stop 7951: 000dc4a0 0 NOTYPE GLOBAL DEFAULT 10 __efi_runtime_rel_stop __rel_dyn_start 7030: 000dc4a0 0 OBJECT GLOBAL DEFAULT 11 __rel_dyn_start 7027: 000dc4a0 0 NOTYPE GLOBAL DEFAULT 11 __rel_dyn_start __rel_dyn_end 8959: 00102b10 0 OBJECT GLOBAL DEFAULT 12 __rel_dyn_end 8956: 00102b10 0 NOTYPE GLOBAL DEFAULT 11 __rel_dyn_end image_copy_start 9051: 0 OBJECT GLOBAL DEFAULT1 __image_copy_start 9048: 0 NOTYPE GLOBAL DEFAULT1 __image_copy_start image_copy_end 7467: 000dc4a0 0 OBJECT GLOBAL DEFAULT 11 __image_copy_end 7464: 000dc4a0 0 NOTYPE GLOBAL DEFAULT 11 __image_copy_end bss_start 12: 00102b10 0 SECTION LOCAL DEFAULT 12 .bss_start 8087: 0018 0 NOTYPE GLOBAL DEFAULT1 _bss_start_ofs 8375: 00102b10 0 OBJECT GLOBAL DEFAULT 12 __bss_start 8084: 0018 0 NOTYPE GLOBAL DEFAULT1 _bss_start_ofs 8372: 00102b10 0 NOTYPE GLOBAL DEFAULT 12 __bss_start bss_end 14: 0010bc30 0 SECTION LOCAL DEFAULT 14 .bss_end 7683: 0010bc30 0 OBJECT GLOBAL DEFAULT 14 __bss_end 8479: 0020 0 NOTYPE GLOBAL DEFAULT1 _bss_end_ofs 7680: 0010bbb0 0 NOTYPE GLOBAL DEFAULT 12 __bss_end 8476: 0020 0 NOTYPE GLOBAL DEFAULT1 _bss_end_ofs # For QEMU v7: efi_runtime_start 10703: 03bc 0 OBJECT GLOBAL DEFAULT2 __efi_runtime_start 10699: 03c0 0 NOTYPE GLOBAL DEFAULT2 __efi_runtime_start efi_runtime_stop 11796: 12ec 0 OBJECT GLOBAL DEFAULT2 __efi_runtime_stop 11792: 12ec 0 NOTYPE GLOBAL DEFAULT2 __efi_runtime_stop __efi_runtime_rel_start 9937: 000c40dc 0 OBJECT GLOBAL DEFAULT8 __efi_runtime_rel_start 9935: 000c40dc 0 NOTYPE GLOBAL DEFAULT9 __efi_runtime_rel_start __efi_runtime_rel_stop 10712: 000c41dc 0 OBJECT GLOBAL DEFAULT 10 __efi_runtime_rel_stop 10708: 000c41dc 0 NOTYPE GLOBAL DEFAULT9 __efi_runtime_rel_stop __rel_dyn_start 9791: 000c41dc 0 OBJECT GLOBAL DEFAULT 10 __rel_dyn_start 9789: 000c41dc 0 NOTYPE GLOBAL DEFAULT 10 __rel_dyn_start __rel_dyn_end 11708: 000da5f4 0 OBJECT GLOBAL DEFAULT 10 __rel_dyn_end 11704: 000da5f4 0 NOTYPE GLOBAL DEFAULT 10 __rel_dyn_end image_copy_start 448: 177c 0 NOTYPE LOCAL DEFAULT3 _image_copy_start_ofs 11797: 0 OBJECT GLOBAL DEFAULT1 __image_copy_start 445: 177c 0 NOTYPE LOCAL DEFAULT3 _image_copy_start_ofs 11793: 0 NOTYPE GLOBAL DEFAULT1 __image_copy_start image_copy_end 450: 1780 0 NOTYPE LOCAL DEFAULT3 _image_copy_end_ofs 10225: 000c41dc 0 OBJECT GLOBAL DEFAULT
Re: [PATCH v2 4/4] rockchip: Migrate to use DM_USB_GADGET on RK3328
Hi Kever,
On 2024-03-13 11:45, Kever Yang wrote:
> Hi Jonas,
>
> Again, not able to apply changes for rk3328 defconfig.
As mentioned in the cover letter, this series depends on the "rockchip:
rk3328: Update defconfigs, DTs and enable boot from SPI" [1] series for
a clean apply.
That series should also fix the following build error [2] seen in your
for-next branch:
aarch64-linux-ld.bfd: drivers/misc/rockchip-efuse.o: in function
`rockchip_efuse_of_to_plat':
drivers/misc/rockchip-efuse.c:273:(.text.rockchip_efuse_of_to_plat+0x1c):
undefined reference to `dev_read_addr_ptr'
drivers/misc/rockchip-efuse.c:273:(.text.rockchip_efuse_of_to_plat+0x1c):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
`dev_read_addr_ptr'
[1] https://patchwork.ozlabs.org/cover/1900345/
[2] https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/jobs/797813
Regards,
Jonas
>
>
> Thanks,
>
> - Kever
>
> On 2024/3/11 02:51, Jonas Karlman wrote:
>> USB gadget is not working fully as expected on RK3328, it uses a
>> board_usb_init() function to initialize the DWC2 OTG port.
>>
>> The board_usb_init() function does not intgrate with the generic phy
>> framework and as a result the USB phy is not properly configured before
>> or after USB gadget use.
>>
>> Having both USB_DWC2 and DWC2_OTG enabled for the same board is also
>> causing some issues.
>>
>> Trying to use rockusb or ums command after usb stop result in a freeze
>> due to usb stop is putting the phy in a suspended state.
>>
>>=> usb start
>>=> usb stop
>>=> ums 0 mmc 0
>>--> freeze due to usb phy is suspended <--
>>
>> Fix this by only using one of USB_DWC2 (host) or DWC2_OTG (peripheral)
>> depending on the most likely usage of the otg port and by migrating to
>> use DM_USB_GADGET instead of a board_usb_init() function.
>>
>> The nanopi-r2 and orangepi-r1-plus variants share OTG and power using a
>> Type-C connector, mark these boards dr_mode as peripheral, the most
>> likely usage is for recovery and image download.
>>
>> The rock64 and roc-cc currently use dr_mode as host, remove the DWC2_OTG
>> driver from these boards to ensure that the USB_DWC2 driver is used.
>>
>> The rock-pi-e board does not enable the usb20_otg node so both USB_DWC2
>> and DWC2_OTG is removed from this board.
>>
>> Enable RockUSB and UMS on all boards with a otg port in peripheral mode.
>>
>> Also with the migration to DM_USB_GADGET completed the U-Boot specific
>> change to reorder usb nodes in the soc device tree can be reverted.
>>
>> Signed-off-by: Jonas Karlman
>> Reviewed-by: Kever Yang
>> ---
>> v2:
>> - Drop use of DWC3_GENERIC and revert to use XHCI_DWC3 for USB 3.0 host
>>for devices using another port with otg/peripheral dr_mode to work
>>around build errors when mixing DWC3_GENERIC and DWC2_OTG.
>> - Collect r-b tag
>> ---
>> arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi| 4 ++
>> .../rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 4 ++
>> .../dts/rk3328-orangepi-r1-plus-u-boot.dtsi | 4 ++
>> arch/arm/dts/rk3328-roc-cc-u-boot.dtsi| 4 ++
>> arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi | 9
>> arch/arm/dts/rk3328-rock64-u-boot.dtsi| 4 ++
>> arch/arm/dts/rk3328-u-boot.dtsi | 4 --
>> arch/arm/dts/rk3328.dtsi | 41 ---
>> configs/evb-rk3328_defconfig | 7 +++-
>> configs/nanopi-r2c-plus-rk3328_defconfig | 7 +++-
>> configs/nanopi-r2c-rk3328_defconfig | 7 +++-
>> configs/nanopi-r2s-rk3328_defconfig | 7 +++-
>> configs/orangepi-r1-plus-lts-rk3328_defconfig | 7 +++-
>> configs/orangepi-r1-plus-rk3328_defconfig | 7 +++-
>> configs/roc-cc-rk3328_defconfig | 7
>> configs/rock-pi-e-rk3328_defconfig| 7
>> configs/rock64-rk3328_defconfig | 6 ---
>> 17 files changed, 75 insertions(+), 61 deletions(-)
>>
>> diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
>> b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
>> index cca4f06145cf..4fa170eeaf8d 100644
>> --- a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
>> +++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
>> @@ -15,6 +15,10 @@
>> bootph-all;
>> };
>>
>> +_otg {
>> +dr_mode = "peripheral";
>> +};
>> +
>> _io_sdio {
>> bootph-pre-ram;
>> };
>> diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
>> b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
>> index 0dbe5a01f986..0a9423cd9c7e 100644
>> --- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
>> +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
>> @@ -33,6 +33,10 @@
>> bootph-pre-ram;
>> };
>>
>> +_otg {
>> +dr_mode = "peripheral";
>> +};
>> +
>> _sd {
>> bootph-pre-ram;
>> };
>> diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
>> b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
>> index 1af75ada1a62..1096821fc5d3 100644
>> ---
Re: [PATCH v2 3/5] rockchip: rk3328: regenerate defconfigs
Hi Kever and Chen-Yu, On 2024-03-13 15:43, Chen-Yu Tsai wrote: > Hi, > > On Wed, Mar 13, 2024 at 6:29 PM Kever Yang wrote: >> >> Hi Chen-Yu, >> >> On 2024/2/12 21:51, Chen-Yu Tsai wrote: >> >> From: Chen-Yu Tsai >> >> Regenerate RK3328 defconfigs after adding imply statements. >> >> Signed-off-by: Chen-Yu Tsai >> Reviewed-by: Christopher Obbard >> Reviewed-by: Dragan Simic >> --- >> configs/evb-rk3328_defconfig | 3 --- >> configs/nanopi-r2c-plus-rk3328_defconfig | 3 --- >> configs/nanopi-r2c-rk3328_defconfig | 3 --- >> configs/nanopi-r2s-rk3328_defconfig | 3 --- >> configs/orangepi-r1-plus-lts-rk3328_defconfig | 3 --- >> configs/orangepi-r1-plus-rk3328_defconfig | 3 --- >> configs/roc-cc-rk3328_defconfig | 3 --- >> configs/rock-pi-e-rk3328_defconfig| 3 --- >> configs/rock64-rk3328_defconfig | 3 --- >> 9 files changed, 27 deletions(-) >> >> diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig >> index 995bfd0558b1..c3bde3e5c457 100644 >> --- a/configs/evb-rk3328_defconfig >> +++ b/configs/evb-rk3328_defconfig >> @@ -30,7 +30,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y >> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb" >> # CONFIG_DISPLAY_CPUINFO is not set >> CONFIG_DISPLAY_BOARDINFO_LATE=y >> -CONFIG_MISC_INIT_R=y >> CONFIG_SPL_MAX_SIZE=0x4 >> CONFIG_SPL_PAD_TO=0x7f8000 >> CONFIG_SPL_HAS_BSS_LINKER_SECTION=y >> @@ -70,8 +69,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 >> CONFIG_FASTBOOT_CMD_OEM_FORMAT=y >> CONFIG_ROCKCHIP_GPIO=y >> CONFIG_SYS_I2C_ROCKCHIP=y >> -CONFIG_MISC=y >> -CONFIG_ROCKCHIP_EFUSE=y >> >> There is no this config in the all these boards when I check the code on >> next, >> >> which cause the conflict when apply this patch. > > I can respin, but should I still base my patches on Jonas's series? > I don't see them in next. The series "rockchip: rk3328: Update defconfigs, DTs and enable boot from SPI" [1] that this and some of the other patches depends on is missing in your for-next branch. Should we rebase on your for-next or will you pick that series? :-) [1] https://patchwork.ozlabs.org/cover/1900345/ Regards, Jonas > > ChenYu > >> >> Thanks, >> >> - Kever >> >> CONFIG_MMC_DW=y >> CONFIG_MMC_DW_ROCKCHIP=y >> CONFIG_PHY_MOTORCOMM=y >> diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig >> b/configs/nanopi-r2c-plus-rk3328_defconfig >> index 1cb0ed855398..1b0fa27ced16 100644 >> --- a/configs/nanopi-r2c-plus-rk3328_defconfig >> +++ b/configs/nanopi-r2c-plus-rk3328_defconfig >> @@ -31,7 +31,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y >> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb" >> # CONFIG_DISPLAY_CPUINFO is not set >> CONFIG_DISPLAY_BOARDINFO_LATE=y >> -CONFIG_MISC_INIT_R=y >> CONFIG_SPL_MAX_SIZE=0x4 >> CONFIG_SPL_PAD_TO=0x7f8000 >> CONFIG_SPL_HAS_BSS_LINKER_SECTION=y >> @@ -72,8 +71,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 >> CONFIG_FASTBOOT_CMD_OEM_FORMAT=y >> CONFIG_ROCKCHIP_GPIO=y >> CONFIG_SYS_I2C_ROCKCHIP=y >> -CONFIG_MISC=y >> -CONFIG_ROCKCHIP_EFUSE=y >> CONFIG_MMC_DW=y >> CONFIG_MMC_DW_ROCKCHIP=y >> CONFIG_PHY_MOTORCOMM=y >> diff --git a/configs/nanopi-r2c-rk3328_defconfig >> b/configs/nanopi-r2c-rk3328_defconfig >> index 59801328deda..edf24623da2a 100644 >> --- a/configs/nanopi-r2c-rk3328_defconfig >> +++ b/configs/nanopi-r2c-rk3328_defconfig >> @@ -31,7 +31,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y >> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb" >> # CONFIG_DISPLAY_CPUINFO is not set >> CONFIG_DISPLAY_BOARDINFO_LATE=y >> -CONFIG_MISC_INIT_R=y >> CONFIG_SPL_MAX_SIZE=0x4 >> CONFIG_SPL_PAD_TO=0x7f8000 >> CONFIG_SPL_HAS_BSS_LINKER_SECTION=y >> @@ -72,8 +71,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 >> CONFIG_FASTBOOT_CMD_OEM_FORMAT=y >> CONFIG_ROCKCHIP_GPIO=y >> CONFIG_SYS_I2C_ROCKCHIP=y >> -CONFIG_MISC=y >> -CONFIG_ROCKCHIP_EFUSE=y >> CONFIG_MMC_DW=y >> CONFIG_MMC_DW_ROCKCHIP=y >> CONFIG_PHY_MOTORCOMM=y >> diff --git a/configs/nanopi-r2s-rk3328_defconfig >> b/configs/nanopi-r2s-rk3328_defconfig >> index 61914b1650d2..32c99dfecb86 100644 >> --- a/configs/nanopi-r2s-rk3328_defconfig >> +++ b/configs/nanopi-r2s-rk3328_defconfig >> @@ -31,7 +31,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y >> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb" >> # CONFIG_DISPLAY_CPUINFO is not set >> CONFIG_DISPLAY_BOARDINFO_LATE=y >> -CONFIG_MISC_INIT_R=y >> CONFIG_SPL_MAX_SIZE=0x4 >> CONFIG_SPL_PAD_TO=0x7f8000 >> CONFIG_SPL_HAS_BSS_LINKER_SECTION=y >> @@ -72,8 +71,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 >> CONFIG_FASTBOOT_CMD_OEM_FORMAT=y >> CONFIG_ROCKCHIP_GPIO=y >> CONFIG_SYS_I2C_ROCKCHIP=y >> -CONFIG_MISC=y >> -CONFIG_ROCKCHIP_EFUSE=y >> CONFIG_MMC_DW=y >> CONFIG_MMC_DW_ROCKCHIP=y >> CONFIG_PHY_MOTORCOMM=y >> diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig >> b/configs/orangepi-r1-plus-lts-rk3328_defconfig >> index 968110c8cd6f..f554a284d930 100644 >> --- a/configs/orangepi-r1-plus-lts-rk3328_defconfig
Re: [PATCH v2 3/5] rockchip: rk3328: regenerate defconfigs
Hi, On Wed, Mar 13, 2024 at 6:29 PM Kever Yang wrote: > > Hi Chen-Yu, > > On 2024/2/12 21:51, Chen-Yu Tsai wrote: > > From: Chen-Yu Tsai > > Regenerate RK3328 defconfigs after adding imply statements. > > Signed-off-by: Chen-Yu Tsai > Reviewed-by: Christopher Obbard > Reviewed-by: Dragan Simic > --- > configs/evb-rk3328_defconfig | 3 --- > configs/nanopi-r2c-plus-rk3328_defconfig | 3 --- > configs/nanopi-r2c-rk3328_defconfig | 3 --- > configs/nanopi-r2s-rk3328_defconfig | 3 --- > configs/orangepi-r1-plus-lts-rk3328_defconfig | 3 --- > configs/orangepi-r1-plus-rk3328_defconfig | 3 --- > configs/roc-cc-rk3328_defconfig | 3 --- > configs/rock-pi-e-rk3328_defconfig| 3 --- > configs/rock64-rk3328_defconfig | 3 --- > 9 files changed, 27 deletions(-) > > diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig > index 995bfd0558b1..c3bde3e5c457 100644 > --- a/configs/evb-rk3328_defconfig > +++ b/configs/evb-rk3328_defconfig > @@ -30,7 +30,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y > CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb" > # CONFIG_DISPLAY_CPUINFO is not set > CONFIG_DISPLAY_BOARDINFO_LATE=y > -CONFIG_MISC_INIT_R=y > CONFIG_SPL_MAX_SIZE=0x4 > CONFIG_SPL_PAD_TO=0x7f8000 > CONFIG_SPL_HAS_BSS_LINKER_SECTION=y > @@ -70,8 +69,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 > CONFIG_FASTBOOT_CMD_OEM_FORMAT=y > CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > -CONFIG_MISC=y > -CONFIG_ROCKCHIP_EFUSE=y > > There is no this config in the all these boards when I check the code on next, > > which cause the conflict when apply this patch. I can respin, but should I still base my patches on Jonas's series? I don't see them in next. ChenYu > > Thanks, > > - Kever > > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_PHY_MOTORCOMM=y > diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig > b/configs/nanopi-r2c-plus-rk3328_defconfig > index 1cb0ed855398..1b0fa27ced16 100644 > --- a/configs/nanopi-r2c-plus-rk3328_defconfig > +++ b/configs/nanopi-r2c-plus-rk3328_defconfig > @@ -31,7 +31,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y > CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb" > # CONFIG_DISPLAY_CPUINFO is not set > CONFIG_DISPLAY_BOARDINFO_LATE=y > -CONFIG_MISC_INIT_R=y > CONFIG_SPL_MAX_SIZE=0x4 > CONFIG_SPL_PAD_TO=0x7f8000 > CONFIG_SPL_HAS_BSS_LINKER_SECTION=y > @@ -72,8 +71,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 > CONFIG_FASTBOOT_CMD_OEM_FORMAT=y > CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > -CONFIG_MISC=y > -CONFIG_ROCKCHIP_EFUSE=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_PHY_MOTORCOMM=y > diff --git a/configs/nanopi-r2c-rk3328_defconfig > b/configs/nanopi-r2c-rk3328_defconfig > index 59801328deda..edf24623da2a 100644 > --- a/configs/nanopi-r2c-rk3328_defconfig > +++ b/configs/nanopi-r2c-rk3328_defconfig > @@ -31,7 +31,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y > CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb" > # CONFIG_DISPLAY_CPUINFO is not set > CONFIG_DISPLAY_BOARDINFO_LATE=y > -CONFIG_MISC_INIT_R=y > CONFIG_SPL_MAX_SIZE=0x4 > CONFIG_SPL_PAD_TO=0x7f8000 > CONFIG_SPL_HAS_BSS_LINKER_SECTION=y > @@ -72,8 +71,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 > CONFIG_FASTBOOT_CMD_OEM_FORMAT=y > CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > -CONFIG_MISC=y > -CONFIG_ROCKCHIP_EFUSE=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_PHY_MOTORCOMM=y > diff --git a/configs/nanopi-r2s-rk3328_defconfig > b/configs/nanopi-r2s-rk3328_defconfig > index 61914b1650d2..32c99dfecb86 100644 > --- a/configs/nanopi-r2s-rk3328_defconfig > +++ b/configs/nanopi-r2s-rk3328_defconfig > @@ -31,7 +31,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y > CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb" > # CONFIG_DISPLAY_CPUINFO is not set > CONFIG_DISPLAY_BOARDINFO_LATE=y > -CONFIG_MISC_INIT_R=y > CONFIG_SPL_MAX_SIZE=0x4 > CONFIG_SPL_PAD_TO=0x7f8000 > CONFIG_SPL_HAS_BSS_LINKER_SECTION=y > @@ -72,8 +71,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 > CONFIG_FASTBOOT_CMD_OEM_FORMAT=y > CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > -CONFIG_MISC=y > -CONFIG_ROCKCHIP_EFUSE=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_PHY_MOTORCOMM=y > diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig > b/configs/orangepi-r1-plus-lts-rk3328_defconfig > index 968110c8cd6f..f554a284d930 100644 > --- a/configs/orangepi-r1-plus-lts-rk3328_defconfig > +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig > @@ -34,7 +34,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y > CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb" > # CONFIG_DISPLAY_CPUINFO is not set > CONFIG_DISPLAY_BOARDINFO_LATE=y > -CONFIG_MISC_INIT_R=y > CONFIG_SPL_MAX_SIZE=0x4 > CONFIG_SPL_PAD_TO=0x7f8000 > CONFIG_SPL_HAS_BSS_LINKER_SECTION=y > @@ -77,8 +76,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 > CONFIG_FASTBOOT_CMD_OEM_FORMAT=y > CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y
Re: [PATCH] imx8m*_venice: move venice to OF_UPSTREAM
On Wed, 13 Mar 2024 at 06:46, Fabio Estevam wrote:
>
> Hi Tim,
>
> On Tue, Mar 12, 2024 at 4:05 PM Tim Harvey wrote:
> >
> > Move to imx8m{m,n,p}-venice to OF_UPSTREAM:
> > - replace the non-upstream generic imx8m{m,n,p}-venice dt with one of the
> >dt's from the OF_LIST
> > - handle the fact that dtbs now have a 'freescale/' prefix
> > - imply OF_UPSTREAM
> > - remove rudundant files from arch/arm/dts leaving only the
> >*-u-boot.dtsi files
> >
> > Signed-off-by: Tim Harvey
> ...
> > 33 files changed, 13 insertions(+), 10658 deletions(-)
>
> This diff looks great :-)
+1
Reviewed-by: Sumit Garg
-Sumit
>
> Reviewed-by: Fabio Estevam
>
> I will queue it to u-boot-imx/next soon.
Re: [PATCH v2 5/5] board: add support for Schneider HMIBSC board
On Wed, 13 Mar 2024 at 16:59, Stephan Gerhold wrote:
>
> On Wed, Mar 13, 2024 at 12:08:58PM +0530, Sumit Garg wrote:
> > On Mon, 11 Mar 2024 at 20:07, Stephan Gerhold wrote:
> > > On Mon, Mar 11, 2024 at 04:40:26PM +0530, Sumit Garg wrote:
> > > > Support for Schneider Electric HMIBSC. Features:
> > > > - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
> > > > - 2GiB RAM
> > > > - 64GiB eMMC, SD slot
> > > > - WiFi and Bluetooth
> > > > - 2x Host, 1x Device USB port
> > > > - HDMI
> > > > - Discrete TPM2 chip over SPI
> > > >
> > > > Features enabled in U-Boot:
> > > > - RAUC updates
> > > > - Environment protection
> > > > - USB based ethernet adaptors
> > > >
> > > > Signed-off-by: Sumit Garg
> > >
> > [...]
> > > > + gpio_rs232_high: gpio_rs232_high {
> > >
> > > Pretty sure DT schema checks would complain about this node name (need
> > > -state suffix, no underscores).
> >
> > We have the dtbs_check in U-Boot too. I will use that before posting
> > the next version.
> >
> > >
> > > > + bootph-all;
> > > > + pins = "gpio99";
> > > > + function = "gpio";
> > > > +
> > > > + drive-strength = <16>;
> > > > + bias-disable;
> > > > + output-high;
> > > > + };
> > > > +
> > > > + gpio_rs232_low: gpio_rs232_low {
> > >
> > > Same here.
> > >
> > > Also, since I'm looking at this a bit more closely now, are there maybe
> > > more clear label/node names you could use here, or a comment you could
> > > add what exactly these pins do? I guess this enables something about
> > > RS232 but it's not clear what exactly.
> >
> > Actually these GPIOs are a mux to select among different UART modes
> > (RS232/422/485). This configuration allows you to select RS232 mode.
> > How about following label/node names?
> >
> > uart1_mux0_rs232_high: uart1-mux0-rs232-state
> >
> > uart1_mux1_rs232_low: uart1-mux1-rs232-state
> >
>
> Hm, is it a 2 bit mux selector like
>
> gpio99 gpio100 UART mode
> 0 0 ?
> 0 1 ?
> 1 0 RS232
> 1 1 ?
>
> and the others are RS422 and RS485?
Yeah, just to complete that table:
gpio100 gpio99 UART mode
0 0loopback
0 1RS-232
1 0RS-485
1 1RS-422
> If yes, a comment with the table of
> the function assignments would help a lot for clarity.
Sure I will add that.
> With that,
> precise naming would not be that important anymore. :-)
>
I will keep the updated naming too.
-Sumit
> Thanks,
> Stephan
Re: [PATCH v2 5/5] board: add support for Schneider HMIBSC board
On Wed, Mar 13, 2024 at 12:08:58PM +0530, Sumit Garg wrote:
> On Mon, 11 Mar 2024 at 20:07, Stephan Gerhold wrote:
> > On Mon, Mar 11, 2024 at 04:40:26PM +0530, Sumit Garg wrote:
> > > Support for Schneider Electric HMIBSC. Features:
> > > - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
> > > - 2GiB RAM
> > > - 64GiB eMMC, SD slot
> > > - WiFi and Bluetooth
> > > - 2x Host, 1x Device USB port
> > > - HDMI
> > > - Discrete TPM2 chip over SPI
> > >
> > > Features enabled in U-Boot:
> > > - RAUC updates
> > > - Environment protection
> > > - USB based ethernet adaptors
> > >
> > > Signed-off-by: Sumit Garg
> >
> [...]
> > > + gpio_rs232_high: gpio_rs232_high {
> >
> > Pretty sure DT schema checks would complain about this node name (need
> > -state suffix, no underscores).
>
> We have the dtbs_check in U-Boot too. I will use that before posting
> the next version.
>
> >
> > > + bootph-all;
> > > + pins = "gpio99";
> > > + function = "gpio";
> > > +
> > > + drive-strength = <16>;
> > > + bias-disable;
> > > + output-high;
> > > + };
> > > +
> > > + gpio_rs232_low: gpio_rs232_low {
> >
> > Same here.
> >
> > Also, since I'm looking at this a bit more closely now, are there maybe
> > more clear label/node names you could use here, or a comment you could
> > add what exactly these pins do? I guess this enables something about
> > RS232 but it's not clear what exactly.
>
> Actually these GPIOs are a mux to select among different UART modes
> (RS232/422/485). This configuration allows you to select RS232 mode.
> How about following label/node names?
>
> uart1_mux0_rs232_high: uart1-mux0-rs232-state
>
> uart1_mux1_rs232_low: uart1-mux1-rs232-state
>
Hm, is it a 2 bit mux selector like
gpio99 gpio100 UART mode
0 0 ?
0 1 ?
1 0 RS232
1 1 ?
and the others are RS422 and RS485? If yes, a comment with the table of
the function assignments would help a lot for clarity. With that,
precise naming would not be that important anymore. :-)
Thanks,
Stephan
[PATCH next v1 1/1] arm: dts: ast2600-x4tf: Add new dts for ASUS X4TF
This is the new bmc dts for ASUS X4TF server.
Signed-off-by: Kelly Hung
---
V1: Add a new bmc dts for ASUS X4TF server.
---
arch/arm/dts/Makefile | 4 +-
arch/arm/dts/ast2600-x4tf.dts | 161 ++
2 files changed, 164 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/ast2600-x4tf.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 784192125d..ebbc0b21fc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1359,7 +1359,9 @@ dtb-$(CONFIG_BCM6878) += \
bcm96878.dtb
dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
-dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
+dtb-$(CONFIG_ASPEED_AST2600) += \
+ ast2600-evb.dtb \
+ ast2600-x4tf.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
diff --git a/arch/arm/dts/ast2600-x4tf.dts b/arch/arm/dts/ast2600-x4tf.dts
new file mode 100644
index 00..4bf4b66a9c
--- /dev/null
+++ b/arch/arm/dts/ast2600-x4tf.dts
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright 2024 ASUS Corp.
+/dts-v1/;
+
+#include "ast2600-u-boot.dtsi"
+
+/ {
+ model = "AST2600 ASUS X4TF";
+ compatible = "aspeed,ast2600-asus", "aspeed,ast2600";
+
+ memory {
+ device_type = "memory";
+ reg = <0x8000 0x2000>;
+ };
+
+ chosen {
+ stdout-path =
+ };
+
+ aliases {
+ spi0 =
+ ethernet0 =
+ ethernet1 =
+ };
+
+ cpus {
+ cpu@0 {
+ clock-frequency = <8>;
+ };
+
+ cpu@1 {
+ clock-frequency = <8>;
+ };
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ clock-frequency = <4>;
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <_rmii3_default>;
+};
+
+ {
+ status = "okay";
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <_rmii4_default>;
+};
+
+ {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor", "macronix,mx66l2g45g";
+ status = "okay";
+ spi-max-frequency = <2500>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ };
+
+ flash@1 {
+ compatible = "spi-flash", "sst,w25q256";
+ status = "okay";
+ spi-max-frequency = <2500>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "disabled";
+};
+
+ {
+ status = "disabled";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+_port {
+ status = "okay";
+};
--
2.25.1
[PATCH next v1 0/1] Add new bmc dts for ASUS X4TF server
Add bmc dts to ASUS X4TF server, we also submitted dts to linux place. Please refer to here, https://lore.kernel.org/lkml/?q=x4tf. Kelly Hung (1): arm: dts: ast2600-x4tf: Add new dts for ASUS X4TF arch/arm/dts/Makefile | 4 +- arch/arm/dts/ast2600-x4tf.dts | 161 ++ 2 files changed, 164 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/ast2600-x4tf.dts -- 2.25.1
[PATCH v1 1/1] arm: dts: ast2600-x4tf: Add new dts for ASUS X4TF
This is the new bmc dts for ASUS X4TF server.
Signed-off-by: Kelly Hung
---
V1: Add a new bmc dts for ASUS X4TF server.
---
arch/arm/dts/Makefile | 4 +-
arch/arm/dts/ast2600-x4tf.dts | 161 ++
2 files changed, 164 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/ast2600-x4tf.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b102ffb5f6..d91b71e109 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1366,7 +1366,9 @@ dtb-$(CONFIG_BCM6878) += \
bcm96878.dtb
dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
-dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
+dtb-$(CONFIG_ASPEED_AST2600) += \
+ ast2600-evb.dtb \
+ ast2600-x4tf.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
diff --git a/arch/arm/dts/ast2600-x4tf.dts b/arch/arm/dts/ast2600-x4tf.dts
new file mode 100644
index 00..4bf4b66a9c
--- /dev/null
+++ b/arch/arm/dts/ast2600-x4tf.dts
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright 2024 ASUS Corp.
+/dts-v1/;
+
+#include "ast2600-u-boot.dtsi"
+
+/ {
+ model = "AST2600 ASUS X4TF";
+ compatible = "aspeed,ast2600-asus", "aspeed,ast2600";
+
+ memory {
+ device_type = "memory";
+ reg = <0x8000 0x2000>;
+ };
+
+ chosen {
+ stdout-path =
+ };
+
+ aliases {
+ spi0 =
+ ethernet0 =
+ ethernet1 =
+ };
+
+ cpus {
+ cpu@0 {
+ clock-frequency = <8>;
+ };
+
+ cpu@1 {
+ clock-frequency = <8>;
+ };
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ clock-frequency = <4>;
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <_rmii3_default>;
+};
+
+ {
+ status = "okay";
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <_rmii4_default>;
+};
+
+ {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor", "macronix,mx66l2g45g";
+ status = "okay";
+ spi-max-frequency = <2500>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ };
+
+ flash@1 {
+ compatible = "spi-flash", "sst,w25q256";
+ status = "okay";
+ spi-max-frequency = <2500>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "disabled";
+};
+
+ {
+ status = "disabled";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+_port {
+ status = "okay";
+};
--
2.25.1
[PATCH v1 0/1] Add new bmc dts for ASUS X4TF server
Add bmc dts to ASUS X4TF server, we also submitted dts to linux place. Please refer to here, https://lore.kernel.org/lkml/?q=x4tf. Kelly Hung (1): arm: dts: ast2600-x4tf: Add new dts for ASUS X4TF arch/arm/dts/Makefile | 4 +- arch/arm/dts/ast2600-x4tf.dts | 161 ++ 2 files changed, 164 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/ast2600-x4tf.dts -- 2.25.1
[PATCH-V2] arm:suniv:complete the serial port configuration of Suniv
From: lhdjply
Due to the different serial ports used by each board,
the serial IO configuration needs to be improved.
Signed-off-by: lhdjply
---
arch/arm/mach-sunxi/board.c | 4 ++--
include/sunxi_gpio.h| 6 ++
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index f4dbb2a740..b91c9629e4 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -151,8 +151,8 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6);
sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV)
- sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPA_UART1);
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPA_UART1);
sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
index db3742c039..51258e3dd9 100644
--- a/include/sunxi_gpio.h
+++ b/include/sunxi_gpio.h
@@ -108,6 +108,8 @@ enum sunxi_gpio_number {
#define SUN8I_H3_GPA_UART0 2
#define SUN8I_H3_GPA_UART2 2
+#define SUNIV_GPA_UART15
+
#define SUN4I_GPB_PWM 2
#define SUN4I_GPB_TWI0 2
#define SUN4I_GPB_TWI1 2
@@ -130,12 +132,16 @@ enum sunxi_gpio_number {
#define SUNXI_GPD_LCD0 2
#define SUNXI_GPD_LVDS03
+#define SUNIV_GPD_UART13
+#define SUNIV_GPD_UART23
#define SUNIV_GPE_UART05
+#define SUNIV_GPE_UART23
#define SUNXI_GPF_SDC0 2
#define SUNXI_GPF_UART04
#define SUN8I_GPF_UART03
+#define SUNIV_GPF_UART03
#define SUN4I_GPG_SDC1 4
#define SUN5I_GPG_SDC1 2
--
2.34.1
[PATCH] arm:suniv:complete the serial port configuration of Suniv
From: lhdjply
111
Signed-off-by: lhdjply
---
arch/arm/mach-sunxi/board.c | 4 ++--
include/sunxi_gpio.h| 6 ++
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index f4dbb2a740..b91c9629e4 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -151,8 +151,8 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6);
sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV)
- sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPA_UART1);
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPA_UART1);
sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
index db3742c039..51258e3dd9 100644
--- a/include/sunxi_gpio.h
+++ b/include/sunxi_gpio.h
@@ -108,6 +108,8 @@ enum sunxi_gpio_number {
#define SUN8I_H3_GPA_UART0 2
#define SUN8I_H3_GPA_UART2 2
+#define SUNIV_GPA_UART15
+
#define SUN4I_GPB_PWM 2
#define SUN4I_GPB_TWI0 2
#define SUN4I_GPB_TWI1 2
@@ -130,12 +132,16 @@ enum sunxi_gpio_number {
#define SUNXI_GPD_LCD0 2
#define SUNXI_GPD_LVDS03
+#define SUNIV_GPD_UART13
+#define SUNIV_GPD_UART23
#define SUNIV_GPE_UART05
+#define SUNIV_GPE_UART23
#define SUNXI_GPF_SDC0 2
#define SUNXI_GPF_UART04
#define SUN8I_GPF_UART03
+#define SUNIV_GPF_UART03
#define SUN4I_GPG_SDC1 4
#define SUN5I_GPG_SDC1 2
--
2.34.1
Re: [PATCH v2 4/4] rockchip: Migrate to use DM_USB_GADGET on RK3328
Hi Jonas,
Again, not able to apply changes for rk3328 defconfig.
Thanks,
- Kever
On 2024/3/11 02:51, Jonas Karlman wrote:
USB gadget is not working fully as expected on RK3328, it uses a
board_usb_init() function to initialize the DWC2 OTG port.
The board_usb_init() function does not intgrate with the generic phy
framework and as a result the USB phy is not properly configured before
or after USB gadget use.
Having both USB_DWC2 and DWC2_OTG enabled for the same board is also
causing some issues.
Trying to use rockusb or ums command after usb stop result in a freeze
due to usb stop is putting the phy in a suspended state.
=> usb start
=> usb stop
=> ums 0 mmc 0
--> freeze due to usb phy is suspended <--
Fix this by only using one of USB_DWC2 (host) or DWC2_OTG (peripheral)
depending on the most likely usage of the otg port and by migrating to
use DM_USB_GADGET instead of a board_usb_init() function.
The nanopi-r2 and orangepi-r1-plus variants share OTG and power using a
Type-C connector, mark these boards dr_mode as peripheral, the most
likely usage is for recovery and image download.
The rock64 and roc-cc currently use dr_mode as host, remove the DWC2_OTG
driver from these boards to ensure that the USB_DWC2 driver is used.
The rock-pi-e board does not enable the usb20_otg node so both USB_DWC2
and DWC2_OTG is removed from this board.
Enable RockUSB and UMS on all boards with a otg port in peripheral mode.
Also with the migration to DM_USB_GADGET completed the U-Boot specific
change to reorder usb nodes in the soc device tree can be reverted.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
---
v2:
- Drop use of DWC3_GENERIC and revert to use XHCI_DWC3 for USB 3.0 host
for devices using another port with otg/peripheral dr_mode to work
around build errors when mixing DWC3_GENERIC and DWC2_OTG.
- Collect r-b tag
---
arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi| 4 ++
.../rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 4 ++
.../dts/rk3328-orangepi-r1-plus-u-boot.dtsi | 4 ++
arch/arm/dts/rk3328-roc-cc-u-boot.dtsi| 4 ++
arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi | 9
arch/arm/dts/rk3328-rock64-u-boot.dtsi| 4 ++
arch/arm/dts/rk3328-u-boot.dtsi | 4 --
arch/arm/dts/rk3328.dtsi | 41 ---
configs/evb-rk3328_defconfig | 7 +++-
configs/nanopi-r2c-plus-rk3328_defconfig | 7 +++-
configs/nanopi-r2c-rk3328_defconfig | 7 +++-
configs/nanopi-r2s-rk3328_defconfig | 7 +++-
configs/orangepi-r1-plus-lts-rk3328_defconfig | 7 +++-
configs/orangepi-r1-plus-rk3328_defconfig | 7 +++-
configs/roc-cc-rk3328_defconfig | 7
configs/rock-pi-e-rk3328_defconfig| 7
configs/rock64-rk3328_defconfig | 6 ---
17 files changed, 75 insertions(+), 61 deletions(-)
diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
index cca4f06145cf..4fa170eeaf8d 100644
--- a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
@@ -15,6 +15,10 @@
bootph-all;
};
+_otg {
+ dr_mode = "peripheral";
+};
+
_io_sdio {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
index 0dbe5a01f986..0a9423cd9c7e 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
@@ -33,6 +33,10 @@
bootph-pre-ram;
};
+_otg {
+ dr_mode = "peripheral";
+};
+
_sd {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
index 1af75ada1a62..1096821fc5d3 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
@@ -33,6 +33,10 @@
bootph-pre-ram;
};
+_otg {
+ dr_mode = "peripheral";
+};
+
_sd {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
index 47d74964fd0c..582d6ba49b4e 100644
--- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
@@ -29,6 +29,10 @@
};
};
+_otg {
+ hnp-srp-disable;
+};
+
_sd {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
index 9ed0aef1ecc9..d314bfad6fc0 100644
--- a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
@@ -29,6 +29,15 @@
};
};
+_host {
+ phy-supply = <_host_5v>;
+};
+
+_host_5v {
+ /delete-property/ regulator-always-on;
+ /delete-property/ regulator-boot-on;
+};
+
_sd {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi
Re: [PATCH v2 1/4] rockchip: Update the default USB Product ID value
On 2024/3/11 02:50, Jonas Karlman wrote: RK3036 is using the USB product id normally used by RK3066B, and RK3328 is using the product id normally used by RK3368. Fix this and update the default USB_GADGET_PRODUCT_NUM Kconfig option for remaining supported Rockchip SoCs to match the product id used in Maskrom mode. Also remove a reference to an undefined ROCKCHIP_RK3229 Kconfig symbol. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Thanks, - Kever --- v2: - Update commit message --- drivers/usb/gadget/Kconfig | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index c72a8047635c..4621a6fd5e64 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -70,12 +70,21 @@ config USB_GADGET_PRODUCT_NUM hex "Product ID of the USB device" default 0x701a if ARCH_TEGRA default 0x1010 if ARCH_SUNXI - default 0x310a if ROCKCHIP_RK3036 + default 0x110a if ROCKCHIP_RV1108 + default 0x110b if ROCKCHIP_RV1126 default 0x300a if ROCKCHIP_RK3066 + default 0x301a if ROCKCHIP_RK3036 + default 0x310b if ROCKCHIP_RK3188 default 0x310c if ROCKCHIP_RK3128 - default 0x320a if ROCKCHIP_RK3229 || ROCKCHIP_RK3288 - default 0x330a if ROCKCHIP_RK3328 + default 0x320a if ROCKCHIP_RK3288 + default 0x320b if ROCKCHIP_RK322X + default 0x320c if ROCKCHIP_RK3328 + default 0x330a if ROCKCHIP_RK3368 default 0x330c if ROCKCHIP_RK3399 + default 0x330d if ROCKCHIP_PX30 + default 0x330e if ROCKCHIP_RK3308 + default 0x350a if ROCKCHIP_RK3568 + default 0x350b if ROCKCHIP_RK3588 default 0x0 help Product ID of the USB device emulated, reported to the host device.
Re: [PATCH v4] board: rockchip: add Rockchip Toybrick TB-RK3588X board
On 2024/3/11 11:57, Elon Zhang wrote:
TB-RK3588X board is a Rockchip Toybrick RK3588 based development board.
Specification:
Rockchip Rk3588 SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
8/16GB Memory LPDDR4x
Mali G610MC4 GPU
2× MIPI-CSI0 Connector
1x 2Lanes PCIe3.0 Connector
1x SATA3.0 Connector
32GB eMMC Module
2x USB 2.0, 2x USB 3.0
1x HDMI Output, 1x HDMI Input
2x Ethernet Port
Functions work normally:
[1] USB2.0 Host
[2] Ethernet0 with PHY RTL8211F
More information can be obtained from the following websites:
[1] https://t.rock-chips.com/en/wiki/EN/tb-rk3588x_en/index.html
[2] http://t.rock-chips.com/
Kernel commits:
8ffe365f8dc7 ("arm64: dts: rockchip: Add devicetree support for TB-RK3588X
board")
7140387ff49d ("dt-bindings: arm: rockchip: Add Toybrick TB-RK3588X")
Reviewed-by: Weizhao Ouyang
Signed-off-by: Elon Zhang
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes since v3:
- unsigned int ret -> int ret of fdtdec_add_reserved_memory()
Changes since v2:
- Sync dts file from upstream linux kernel
Changes since v1:
- Remove BOARD_SPECIFIC_OPTIONS in board Kconfig
---
arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi | 12 +
arch/arm/dts/rk3588-toybrick-x0.dts | 688 ++
arch/arm/mach-rockchip/rk3588/Kconfig | 25 +
board/rockchip/toybrick_rk3588/Kconfig| 12 +
board/rockchip/toybrick_rk3588/MAINTAINERS| 8 +
board/rockchip/toybrick_rk3588/Makefile | 6 +
.../toybrick_rk3588/toybrick-rk3588.c | 39 +
configs/toybrick-rk3588_defconfig | 82 +++
doc/board/rockchip/rockchip.rst | 1 +
include/configs/toybrick_rk3588.h | 15 +
10 files changed, 888 insertions(+)
create mode 100644 arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3588-toybrick-x0.dts
create mode 100644 board/rockchip/toybrick_rk3588/Kconfig
create mode 100644 board/rockchip/toybrick_rk3588/MAINTAINERS
create mode 100644 board/rockchip/toybrick_rk3588/Makefile
create mode 100644 board/rockchip/toybrick_rk3588/toybrick-rk3588.c
create mode 100644 configs/toybrick-rk3588_defconfig
create mode 100644 include/configs/toybrick_rk3588.h
diff --git a/arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi
b/arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi
new file mode 100644
index 00..1aeb5410e4
--- /dev/null
+++ b/arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl",
+ };
+};
diff --git a/arch/arm/dts/rk3588-toybrick-x0.dts
b/arch/arm/dts/rk3588-toybrick-x0.dts
new file mode 100644
index 00..9090c5c99f
--- /dev/null
+++ b/arch/arm/dts/rk3588-toybrick-x0.dts
@@ -0,0 +1,688 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include
+#include
+#include
+#include "rk3588.dtsi"
+
+/ {
+ model = "Rockchip Toybrick TB-RK3588X Board";
+ compatible = "rockchip,rk3588-toybrick-x0", "rockchip,rk3588";
+
+ aliases {
+ mmc0 =
+ };
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = < 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <180>;
+ poll-interval = <100>;
+
+ button-vol-up {
+ label = "Volume Up";
+ linux,code = ;
+ press-threshold-microvolt = <17000>;
+ };
+
+ button-vol-down {
+ label = "Volume Down";
+ linux,code = ;
+ press-threshold-microvolt = <417000>;
+ };
+
+ button-menu {
+ label = "Menu";
+ linux,code = ;
+ press-threshold-microvolt = <89>;
+ };
+
+ button-escape {
+ label = "Escape";
+ linux,code = ;
+ press-threshold-microvolt = <1235000>;
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ power-supply = <_dcin>;
+ pwms = < 0 25000 0>;
+ };
+
+ pcie20_avdd0v85: pcie20-avdd0v85-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie20_avdd0v85";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <85>;
+
Re: [PATCH 1/4] rockchip: Update the default USB Product ID value
On 2024/2/27 07:08, Jonas Karlman wrote: RK3036 is using the USB product id normally used by RK3066B, and RK3328 is using the product id normally used by RK3368. Fix this and update the default USB_GADGET_PRODUCT_NUM Kconfig option for remaining supported Rockchip SoCs to match the product id used in Mask ROM mode. Also remove a reference to the unknown ROCKCHIP_RK3229 symbol. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Thanks, - Kever --- drivers/usb/gadget/Kconfig | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index c72a8047635c..4621a6fd5e64 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -70,12 +70,21 @@ config USB_GADGET_PRODUCT_NUM hex "Product ID of the USB device" default 0x701a if ARCH_TEGRA default 0x1010 if ARCH_SUNXI - default 0x310a if ROCKCHIP_RK3036 + default 0x110a if ROCKCHIP_RV1108 + default 0x110b if ROCKCHIP_RV1126 default 0x300a if ROCKCHIP_RK3066 + default 0x301a if ROCKCHIP_RK3036 + default 0x310b if ROCKCHIP_RK3188 default 0x310c if ROCKCHIP_RK3128 - default 0x320a if ROCKCHIP_RK3229 || ROCKCHIP_RK3288 - default 0x330a if ROCKCHIP_RK3328 + default 0x320a if ROCKCHIP_RK3288 + default 0x320b if ROCKCHIP_RK322X + default 0x320c if ROCKCHIP_RK3328 + default 0x330a if ROCKCHIP_RK3368 default 0x330c if ROCKCHIP_RK3399 + default 0x330d if ROCKCHIP_PX30 + default 0x330e if ROCKCHIP_RK3308 + default 0x350a if ROCKCHIP_RK3568 + default 0x350b if ROCKCHIP_RK3588 default 0x0 help Product ID of the USB device emulated, reported to the host device.
Re: [PATCH v3 3/6] rockchip: Use common bss and stack addresses on RK3328
Hi Jonas, This patch does not able to apply on next, could you help to take a look. And also add document of memory layout in rockchip.rst if possible. Thanks, - Kever On 2024/3/3 03:16, Jonas Karlman wrote: With the stack and text base used by U-Boot SPL and proper on RK3328 there is a high likelihood of overlapping when U-Boot proper + FDT nears or exceeded 1 MiB in size. Currently the following memory layout is typically used on RK3328: [0, 256K) - SPL binary [ 256K, 2M) - TF-A / reserved [ 2M, +X) - U-Boot proper binary (TEXT_BASE) [ -X, 3M) - U-Boot proper pre-reloc stack (CUSTOM_SYS_INIT_SP_ADDR) [ -8K, 3M) - pre-reloc malloc heap (SYS_MALLOC_F_LEN) [ -X, 4M) - SPL pre-reloc stack (SPL_STACK) [ -8K, 4M) - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN) [ -X, 6M) - SPL reloc stack (SPL_STACK_R_ADDR) [ 5M, 6M) - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN) [ 32M, +8K) - SPL bss (SPL_BSS_START_ADDR, SPL_BSS_MAX_SIZE) SPL can safely load U-Boot proper + FDT to [2M, 4M-8K) with this layout. However, the stack at [-X, 3M) used during U-Boot proper pre-reloc is restricting the safe size of U-Boot proper + FDT to be less than 1 MiB. Migrate to use common bss, stack and malloc heap size and addresses to fix this restriction and allow for a larger U-Boot proper image size. Signed-off-by: Jonas Karlman --- arch/arm/mach-rockchip/rk3328/Kconfig | 11 --- configs/evb-rk3328_defconfig | 17 - configs/nanopi-r2c-plus-rk3328_defconfig | 15 --- configs/nanopi-r2c-rk3328_defconfig | 15 --- configs/nanopi-r2s-rk3328_defconfig | 15 --- configs/orangepi-r1-plus-lts-rk3328_defconfig | 15 --- configs/orangepi-r1-plus-rk3328_defconfig | 15 --- configs/roc-cc-rk3328_defconfig | 15 --- configs/rock-pi-e-rk3328_defconfig| 17 - configs/rock64-rk3328_defconfig | 15 --- 10 files changed, 4 insertions(+), 146 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index d5cb649ae6ba..70770da5fdf2 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -21,13 +21,7 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3328" -config SYS_MALLOC_F_LEN - default 0x2000 - -config SPL_LIBCOMMON_SUPPORT - default y - -config SPL_LIBGENERIC_SUPPORT +config ROCKCHIP_COMMON_STACK_ADDR default y config TPL_LDSCRIPT @@ -39,6 +33,9 @@ config TPL_TEXT_BASE config TPL_STACK default 0xff098000 +config TPL_SYS_MALLOC_F_LEN + default 0x800 + source "board/rockchip/evb_rk3328/Kconfig" endif diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index da422c8ba4e7..4fa8a7d365a4 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -2,22 +2,12 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x0020 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x30 CONFIG_SF_DEFAULT_SPEED=2000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y -CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x400 -CONFIG_SPL_STACK=0x40 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 -CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000 CONFIG_DEBUG_UART_BASE=0xFF13 CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -33,16 +23,9 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x4 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x200 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig b/configs/nanopi-r2c-plus-rk3328_defconfig index 25850328f8b8..5302fd91a0f5 100644 --- a/configs/nanopi-r2c-plus-rk3328_defconfig +++ b/configs/nanopi-r2c-plus-rk3328_defconfig @@ -2,22 +2,13 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x0020 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x30 CONFIG_SF_DEFAULT_SPEED=2000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c-plus" CONFIG_DM_RESET=y
Re: [PATCH 2/2] phy: rockchip-inno-usb2: Limit changes made to regs
On 2024/2/26 06:10, Jonas Karlman wrote:
The USB2PHY regs already contain working default reset values for RK3328
and RK35xx as evidenced by the fact that this driver never has changed a
single value for these SoCs.
Reduce to only configure utmi_suspend_n and utmi_sel bits similar to
what is currently done on RK3399. Also add missing clkout_ctl for RK3588.
When enabled utmi_suspend_n is changed to normal mode and utmi_sel to
use otg/host controller utmi interface to phy. When disabled
utmi_suspend_n is changed to suspend mode and utmi_sel to use GRF utmi
interface to phy.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 117 +++---
1 file changed, 14 insertions(+), 103 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 7317128d135e..d392aed2d4de 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -35,16 +35,6 @@ struct usb2phy_reg {
struct rockchip_usb2phy_port_cfg {
struct usb2phy_reg phy_sus;
- struct usb2phy_reg bvalid_det_en;
- struct usb2phy_reg bvalid_det_st;
- struct usb2phy_reg bvalid_det_clr;
- struct usb2phy_reg ls_det_en;
- struct usb2phy_reg ls_det_st;
- struct usb2phy_reg ls_det_clr;
- struct usb2phy_reg utmi_avalid;
- struct usb2phy_reg utmi_bvalid;
- struct usb2phy_reg utmi_ls;
- struct usb2phy_reg utmi_hstdet;
};
struct rockchip_usb2phy_cfg {
@@ -131,7 +121,6 @@ static int rockchip_usb2phy_init(struct phy *phy)
{
struct udevice *parent = dev_get_parent(phy->dev);
struct rockchip_usb2phy *priv = dev_get_priv(parent);
- const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
int ret;
ret = clk_enable(>phyclk);
@@ -140,14 +129,6 @@ static int rockchip_usb2phy_init(struct phy *phy)
return ret;
}
- if (phy->id == USB2PHY_PORT_OTG) {
- property_enable(priv->reg_base, _cfg->bvalid_det_clr,
true);
- property_enable(priv->reg_base, _cfg->bvalid_det_en, true);
- } else if (phy->id == USB2PHY_PORT_HOST) {
- property_enable(priv->reg_base, _cfg->bvalid_det_clr,
true);
- property_enable(priv->reg_base, _cfg->bvalid_det_en, true);
- }
-
return 0;
}
@@ -351,27 +332,13 @@ bind_fail:
static const struct rockchip_usb2phy_cfg rk3328_usb2phy_cfgs[] = {
{
.reg = 0x100,
- .clkout_ctl = { 0x108, 4, 4, 1, 0 },
+ .clkout_ctl = { 0x0108, 4, 4, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
- .phy_sus= { 0x0100, 15, 0, 0, 0x1d1 },
- .bvalid_det_en = { 0x0110, 3, 2, 0, 3 },
- .bvalid_det_st = { 0x0114, 3, 2, 0, 3 },
- .bvalid_det_clr = { 0x0118, 3, 2, 0, 3 },
- .ls_det_en = { 0x0110, 0, 0, 0, 1 },
- .ls_det_st = { 0x0114, 0, 0, 0, 1 },
- .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
- .utmi_avalid= { 0x0120, 10, 10, 0, 1 },
- .utmi_bvalid= { 0x0120, 9, 9, 0, 1 },
- .utmi_ls= { 0x0120, 5, 4, 0, 1 },
+ .phy_sus= { 0x0100, 1, 0, 2, 1 },
},
[USB2PHY_PORT_HOST] = {
- .phy_sus= { 0x104, 15, 0, 0, 0x1d1 },
- .ls_det_en = { 0x110, 1, 1, 0, 1 },
- .ls_det_st = { 0x114, 1, 1, 0, 1 },
- .ls_det_clr = { 0x118, 1, 1, 0, 1 },
- .utmi_ls= { 0x120, 17, 16, 0, 1 },
- .utmi_hstdet= { 0x120, 19, 19, 0, 1 }
+ .phy_sus= { 0x0104, 1, 0, 2, 1 },
}
},
},
@@ -385,19 +352,9 @@ static const struct rockchip_usb2phy_cfg
rk3399_usb2phy_cfgs[] = {
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
.phy_sus= { 0xe454, 1, 0, 2, 1 },
- .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
- .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
- .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
- .utmi_avalid= { 0xe2ac, 7, 7, 0, 1 },
- .utmi_bvalid= { 0xe2ac, 12, 12, 0, 1 },
},
Re: [PATCH v3 01/16] rockchip: spi: rk_spi: do not write bytes when in read-only mode
On 2024/3/4 19:29, Quentin Schulz wrote:
From: Quentin Schulz
The read-only mode is currently supported but only for 16b-aligned
buffers. For unaligned buffers, the last byte will be read in RW mode
right now, which isn't what is desired. Instead, let's put the
controller back into RO mode for that last byte and skip any write in
the xfer loop.
This is required for 3-wire SPI mode where PICO/POCI lanes are shorted
on HW level. This incidentally the recommended design for RK806 PMIC for
RK3588 products.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/spi/rk_spi.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 7de943356ad..c8694fdff95 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -453,8 +453,17 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned
int bitlen,
* case of read-only transfers by using the full 16bits of each
* FIFO element.
*/
- if (!out)
+ if (!out) {
ret = rockchip_spi_16bit_reader(dev, , );
+ /*
+* If "in" isn't 16b-aligned, we need to send the last byte
+* ourselves. We however need to have the controller in RO mode
+* which differs from the default.
+*/
+ clrsetbits_le32(>ctrlr0,
+ TMOD_MASK << TMOD_SHIFT,
+ TMOD_RO << TMOD_SHIFT);
+ }
/* This is the original 8bit reader/writer code */
while (len > 0) {
@@ -465,12 +474,13 @@ static int rockchip_spi_xfer(struct udevice *dev,
unsigned int bitlen,
rkspi_enable_chip(regs, true);
toread = todo;
- towrite = todo;
+ /* Only write if we have something to write */
+ towrite = out ? todo : 0;
while (toread || towrite) {
u32 status = readl(>sr);
if (towrite && !(status & SR_TF_FULL)) {
- writel(out ? *out++ : 0, regs->txdr);
+ writel(*out++, regs->txdr);
towrite--;
}
if (toread && !(status & SR_RF_EMPT)) {
@@ -501,6 +511,10 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned
int bitlen,
spi_cs_deactivate(dev, slave_plat->cs);
rkspi_enable_chip(regs, false);
+ if (!out)
+ clrsetbits_le32(>ctrlr0,
+ TMOD_MASK << TMOD_SHIFT,
+ TMOD_TR << TMOD_SHIFT);
return ret;
}
Re: [PATCH v2 3/5] rockchip: rk3328: regenerate defconfigs
Hi Chen-Yu, On 2024/2/12 21:51, Chen-Yu Tsai wrote: From: Chen-Yu Tsai Regenerate RK3328 defconfigs after adding imply statements. Signed-off-by: Chen-Yu Tsai Reviewed-by: Christopher Obbard Reviewed-by: Dragan Simic --- configs/evb-rk3328_defconfig | 3 --- configs/nanopi-r2c-plus-rk3328_defconfig | 3 --- configs/nanopi-r2c-rk3328_defconfig | 3 --- configs/nanopi-r2s-rk3328_defconfig | 3 --- configs/orangepi-r1-plus-lts-rk3328_defconfig | 3 --- configs/orangepi-r1-plus-rk3328_defconfig | 3 --- configs/roc-cc-rk3328_defconfig | 3 --- configs/rock-pi-e-rk3328_defconfig| 3 --- configs/rock64-rk3328_defconfig | 3 --- 9 files changed, 27 deletions(-) diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 995bfd0558b1..c3bde3e5c457 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -30,7 +30,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x4 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -70,8 +69,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y There is no this config in the all these boards when I check the code on next, which cause the conflict when apply this patch. Thanks, - Kever CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY_MOTORCOMM=y diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig b/configs/nanopi-r2c-plus-rk3328_defconfig index 1cb0ed855398..1b0fa27ced16 100644 --- a/configs/nanopi-r2c-plus-rk3328_defconfig +++ b/configs/nanopi-r2c-plus-rk3328_defconfig @@ -31,7 +31,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x4 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -72,8 +71,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY_MOTORCOMM=y diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig index 59801328deda..edf24623da2a 100644 --- a/configs/nanopi-r2c-rk3328_defconfig +++ b/configs/nanopi-r2c-rk3328_defconfig @@ -31,7 +31,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x4 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -72,8 +71,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY_MOTORCOMM=y diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 61914b1650d2..32c99dfecb86 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -31,7 +31,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x4 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -72,8 +71,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY_MOTORCOMM=y diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig index 968110c8cd6f..f554a284d930 100644 --- a/configs/orangepi-r1-plus-lts-rk3328_defconfig +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig @@ -34,7 +34,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x4 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -77,8 +76,6 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig index 7038f09f202c..162032460fe0 100644 --- a/configs/orangepi-r1-plus-rk3328_defconfig +++ b/configs/orangepi-r1-plus-rk3328_defconfig
Re: [PATCH v2 12/12] rockchip: board: Move gpt_capsule_update_setup() call
On 2024/3/13 07:36, Jonas Karlman wrote:
Move the call to gpt_capsule_update_setup() from the weak function
rk_board_late_init() into the main board_late_init() function.
Also change to use IS_ENABLED() instead for defined().
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2:
- New patch, split from "board: rockchip: Add a common ROCK Pi 4 target"
---
arch/arm/mach-rockchip/board.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 4f666aee706f..dea5805c4665 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION)
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) &&
IS_ENABLED(CONFIG_EFI_PARTITION)
#define DFU_ALT_BUF_LEN SZ_1K
@@ -185,10 +185,6 @@ static void gpt_capsule_update_setup(void)
__weak int rk_board_late_init(void)
{
-#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION)
- gpt_capsule_update_setup();
-#endif
-
return 0;
}
@@ -196,6 +192,10 @@ int board_late_init(void)
{
setup_boot_mode();
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION)
+ gpt_capsule_update_setup();
+#endif
+
return rk_board_late_init();
}
Re: [PATCH v2 01/12] board: rockchip: rk3399: Add device tree files to MAINTAINERS
On 2024/3/13 07:36, Jonas Karlman wrote: Update MAINTAINERS files for RK3399 boards to include related device tree files. Also correct a few filenames. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Thanks, - Kever --- v2: - Use glob pattern where appropriate --- board/firefly/roc-pc-rk3399/MAINTAINERS | 1 + board/pine64/pinebook-pro-rk3399/MAINTAINERS | 5 ++- board/pine64/pinephone-pro-rk3399/MAINTAINERS | 5 ++- board/pine64/rockpro64_rk3399/MAINTAINERS | 2 +- board/rockchip/evb_rk3399/MAINTAINERS | 35 ++- board/vamrs/rock960_rk3399/MAINTAINERS| 2 ++ 6 files changed, 27 insertions(+), 23 deletions(-) diff --git a/board/firefly/roc-pc-rk3399/MAINTAINERS b/board/firefly/roc-pc-rk3399/MAINTAINERS index 68a5b757d1df..2c0de4432fa8 100644 --- a/board/firefly/roc-pc-rk3399/MAINTAINERS +++ b/board/firefly/roc-pc-rk3399/MAINTAINERS @@ -6,3 +6,4 @@ F: board/firefly/roc-pc-rk3399 F:include/configs/roc-pc-rk3399.h F:configs/roc-pc-rk3399_defconfig F:configs/roc-pc-mezzanine-rk3399_defconfig +F: arch/arm/dts/rk3399-roc-pc* diff --git a/board/pine64/pinebook-pro-rk3399/MAINTAINERS b/board/pine64/pinebook-pro-rk3399/MAINTAINERS index 7300ca1b1b81..287ed4346050 100644 --- a/board/pine64/pinebook-pro-rk3399/MAINTAINERS +++ b/board/pine64/pinebook-pro-rk3399/MAINTAINERS @@ -2,7 +2,6 @@ PINEBOOK_PRO M:Peter Robinson S:Maintained F:board/pine64/pinebook-pro-rk3399/ -F: include/configs/rk3399-pinebook-pro.h -F: arch/arm/dts/rk3399-pinebook-pro.dts -F: arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +F: include/configs/pinebook-pro-rk3399.h +F: arch/arm/dts/rk3399-pinebook-pro* F:configs/pinebook-pro-rk3399_defconfig diff --git a/board/pine64/pinephone-pro-rk3399/MAINTAINERS b/board/pine64/pinephone-pro-rk3399/MAINTAINERS index bc2dcdd8d423..959566a877ec 100644 --- a/board/pine64/pinephone-pro-rk3399/MAINTAINERS +++ b/board/pine64/pinephone-pro-rk3399/MAINTAINERS @@ -2,7 +2,6 @@ PINEPHONE_PRO M:Peter Robinson S:Maintained F:board/pine64/pinephone-pro-rk3399/ -F: include/configs/rk3399-pinephone-pro.h -F: arch/arm/dts/rk3399-pinephone-pro.dts -F: arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +F: include/configs/pinephone-pro-rk3399.h +F: arch/arm/dts/rk3399-pinephone-pro* F:configs/pinephone-pro-rk3399_defconfig diff --git a/board/pine64/rockpro64_rk3399/MAINTAINERS b/board/pine64/rockpro64_rk3399/MAINTAINERS index 220ee21f230f..d9e11f4bab34 100644 --- a/board/pine64/rockpro64_rk3399/MAINTAINERS +++ b/board/pine64/rockpro64_rk3399/MAINTAINERS @@ -3,5 +3,5 @@ M: Jagan Teki S:Maintained F:board/pine64/rockpro64_rk3399 F:include/configs/rockpro64_rk3399.h -F: arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +F: arch/arm/dts/rk3399-rockpro64* F:configs/rockpro64-rk3399_defconfig diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index acdb840f2093..f45f81623a3a 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -4,48 +4,53 @@ S: Maintained F: board/rockchip/evb_rk3399 F: include/configs/evb_rk3399.h F: configs/evb-rk3399_defconfig +F: arch/arm/dts/rk3399-evb* F: configs/firefly-rk3399_defconfig +F: arch/arm/dts/rk3399-firefly* EAIDK-610 M: Andy Yan S: Maintained F:configs/eaidk-610-rk3399_defconfig -F: arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi +F: arch/arm/dts/rk3399-eaidk-610* KHADAS-EDGE M:Nick Xie S:Maintained F:configs/khadas-edge-rk3399_defconfig +F: arch/arm/dts/rk3399-khadas-edge.dts +F: arch/arm/dts/rk3399-khadas-edge.dtsi F:arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi KHADAS-EDGE-CAPTAIN M:Nick Xie S:Maintained F:configs/khadas-edge-captain-rk3399_defconfig -F: arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi +F: arch/arm/dts/rk3399-khadas-edge-captain* KHADAS-EDGE-V M:Nick Xie S:Maintained F:configs/khadas-edge-v-rk3399_defconfig -F: arch/arm/dts/rk3399-khadas-edge-v-u-boot.dtsi +F: arch/arm/dts/rk3399-khadas-edge-v* LEEZ-P710 M:Andy Yan S: Maintained -F: arch/arm/dts/rk3399-leez-p710-u-boot.dtsi +F: arch/arm/dts/rk3399-leez-p710* F:configs/leez-rk3399_defconfig NANOPC-T4 M:Jagan Teki S:Maintained F:configs/nanopc-t4-rk3399_defconfig -F: arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi +F: arch/arm/dts/rk3399-nanopc-t4* NANOPI-M4 M:Jagan Teki S:Maintained F:configs/nanopi-m4-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopi-m4.dts F:arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi NANOPI-M4-2GB @@ -53,55 +58,53 @@ M: Jagan Teki M:Deepak Das S:Maintained F:configs/nanopi-m4-2gb-rk3399_defconfig -F:
Re: [PATCH 01/19] spi: cadence_qspi: Add support for DDR PHY mode
> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> index faf02c7778..5895b5de09 100644
> --- a/drivers/mtd/spi/spi-nor-core.c
> +++ b/drivers/mtd/spi/spi-nor-core.c
> @@ -1511,8 +1511,10 @@ static const struct flash_info *spi_nor_read_id(struct
> spi_nor *nor)
> info = spi_nor_ids;
> for (; info->name; info++) {
> if (info->id_len) {
> - if (!memcmp(info->id, id, info->id_len))
> + if ((!memcmp(info->id, id, info->id_len)) &&
> + memcpy(nor->spi->device_id, id,
> SPI_NOR_MAX_ID_LEN)) {
Please, don't put a memcpy() into a condition. It looks like a memcmp()
to the eye.
> return info;
> + }
if (!memcmp(info->id, id, info->id_len)) {
memcpy(nor->spi->device_id, id, SPI_NOR_MAX_ID_LEN);
return info;
}
> }
> }
>
[ snip ]
> static int cadence_spi_mem_exec_op(struct spi_slave *spi,
> const struct spi_mem_op *op)
> {
> @@ -353,6 +649,9 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi,
> break;
> }
>
> + if (op->cmd.dtr)
> + err = cadence_spi_setup_ddrmode(spi, op);
> +
> return err;
I think there should be another if (err) return err after the end of the
switch statement.
> }
>
regards,
dan carpenter
Re: [PATCH] colibri-imx8x: Fix sc_misc_otp_fuse_read() error check
Hi Fabio
Thanks!
On Tue, 2024-03-12 at 21:36 -0300, Fabio Estevam wrote:
> Commit aa6e698a7acd ("imx: toradex/colibri-imx8x: correct SCU API usage")
> made an incorrect logic change in the error code check of
> sc_misc_otp_fuse_read():
>
> - if (sc_err == SC_ERR_NONE) {
> + if (sc_err) {
> /* DX has two A35 cores disabled */
> return (val & 0xf) != 0x0;
> }
>
> The other changes in this commit are correct.
>
> sc_misc_otp_fuse_read() returns 0 on a successful fuse read.
>
> This inversion causes board_mem_get_layout() to report incorrect RAM size.
>
> Go back the original error check logic to fix the problem.
>
> Fixes: aa6e698a7acd ("imx: toradex/colibri-imx8x: correct SCU API usage")
> Reported-by: Hiago De Franco
> Signed-off-by: Fabio Estevam
Acked-by: Marcel Ziswiler
> diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c
> b/board/toradex/colibri-imx8x/colibri-imx8x.c
> index 2c673a4a6b06..6fc8076163c6 100644
> --- a/board/toradex/colibri-imx8x/colibri-imx8x.c
> +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c
> @@ -46,7 +46,7 @@ static int is_imx8dx(void)
> u32 val = 0;
> int sc_err = sc_misc_otp_fuse_read(-1, 6, );
>
> - if (sc_err) {
> + if (!sc_err) {
> /* DX has two A35 cores disabled */
> return (val & 0xf) != 0x0;
> }
Cheers
Marcel
Re: [PATCH] apalis-imx8: Fix sc_misc_otp_fuse_read() error check
Hi Fabio
Thanks!
On Tue, 2024-03-12 at 21:59 -0300, Fabio Estevam wrote:
> Commit bfb3409d676f ("imx: toradex/apalis-imx8: correct SCU API usage")
> made an incorrect logic change in the error code check of
> sc_misc_otp_fuse_read():
>
> - if (scierr == SC_ERR_NONE) {
> + if (scierr) {
> /* QP has one A72 core disabled */
> is_quadplus = ((val >> 4) & 0x3) != 0x0;
> }
>
> The other changes in this commit are correct.
>
> sc_misc_otp_fuse_read() returns 0 on a successful fuse read.
>
> This inversion causes board_mem_get_layout() to report incorrect RAM size.
>
> Go back the original error check logic to fix the problem.
>
> Fixes: bfb3409d676f ("imx: toradex/apalis-imx8: correct SCU API usage")
> Signed-off-by: Fabio Estevam
Acked-by: Marcel Ziswiler
> ---
> board/toradex/apalis-imx8/apalis-imx8.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/board/toradex/apalis-imx8/apalis-imx8.c
> b/board/toradex/apalis-imx8/apalis-imx8.c
> index 2483a63c6733..49719f2f5533 100644
> --- a/board/toradex/apalis-imx8/apalis-imx8.c
> +++ b/board/toradex/apalis-imx8/apalis-imx8.c
> @@ -133,7 +133,7 @@ void board_mem_get_layout(u64 *phys_sdram_1_start,
> struct tdx_user_fuses tdxramfuses;
> int scierr = sc_misc_otp_fuse_read(-1, 6, );
>
> - if (scierr) {
> + if (!scierr) {
> /* QP has one A72 core disabled */
> is_quadplus = ((val >> 4) & 0x3) != 0x0;
> }
Cheers
Marcel
Re: [PATCH v6 1/3] dt-bindings: mtd: partitions: Add binman compatible
Hi Simon, s...@chromium.org wrote on Wed, 13 Mar 2024 11:25:42 +1300: > Hi Miquel, > > On Fri, 8 Mar 2024 at 20:42, Miquel Raynal wrote: > > > > Hi Simon, > > > > s...@chromium.org wrote on Fri, 8 Mar 2024 15:44:25 +1300: > > > > > Hi Miquel, > > > > > > On Tue, 6 Feb 2024 at 01:17, Miquel Raynal > > > wrote: > > > > > > > > Hi Simon, > > > > > > > > > > > > > > > > > > > > +description: | > > > > > > > > > > > > > > > > + The binman node provides a layout for > > > > > > > > > > > > > > > > firmware, used when packaging firmware > > > > > > > > > > > > > > > > + from multiple projects. It is based on > > > > > > > > > > > > > > > > fixed-partitions, with some > > > > > > > > > > > > > > > > + extensions, but uses 'compatible' to > > > > > > > > > > > > > > > > indicate the contents of the node, to > > > > > > > > > > > > > > > > + avoid perturbing or confusing existing > > > > > > > > > > > > > > > > installations which use 'label' for a > > > > > > > > > > > > > > > > + particular purpose. > > > > > > > > > > > > > > > > + > > > > > > > > > > > > > > > > + Binman supports properties used as inputs to > > > > > > > > > > > > > > > > the firmware-packaging process, > > > > > > > > > > > > > > > > + such as those which control alignment of > > > > > > > > > > > > > > > > partitions. This binding addresses > > > > > > > > > > > > > > > > + these 'input' properties. For example, it is > > > > > > > > > > > > > > > > common for the 'reg' property > > > > > > > > > > > > > > > > + (an 'output' property) to be set by Binman, > > > > > > > > > > > > > > > > based on the alignment requested > > > > > > > > > > > > > > > > + in the input. > > > > > > > > > > > > > > > > + > > > > > > > > > > > > > > > > + Once processing is complete, input > > > > > > > > > > > > > > > > properties have mostly served their > > > > > > > > > > > > > > > > + purpose, at least until the firmware is > > > > > > > > > > > > > > > > repacked later, e.g. due to a > > > > > > > > > > > > > > > > + firmware update. The 'fixed-partitions' > > > > > > > > > > > > > > > > binding should provide enough > > > > > > > > > > > > > > > > + information to read the firmware at runtime, > > > > > > > > > > > > > > > > including decompression if > > > > > > > > > > > > > > > > + needed. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > How is this going to work exactly? binman reads > > > > > > > > > > > > > > > these nodes and then > > > > > > > > > > > > > > > writes out 'fixed-partitions' nodes. But then > > > > > > > > > > > > > > > you've lost the binman > > > > > > > > > > > > > > > specifc parts needed for repacking. > > > > > > > > > > > > > > > > > > > > > > > > > > > > No, they are the same node. I do want the extra > > > > > > > > > > > > > > information to stick > > > > > > > > > > > > > > around. So long as it is compatible with > > > > > > > > > > > > > > fixed-partition as well, this > > > > > > > > > > > > > > should work OK. > > > > > > > > > > > > > > > > > > > > > > > > > > How can it be both? The partitions node compatible > > > > > > > > > > > > > can be either > > > > > > > > > > > > > 'fixed-partitions' or 'binman'. > > > > > > > > > > > > > > > > > > > > > > > > Can we not allow it to be both? I have tried to adjust > > > > > > > > > > > > things in > > > > > > > > > > > > response to feedback but perhaps the feedback was > > > > > > > > > > > > leading me down the > > > > > > > > > > > > wrong path? > > > > > > > > > > > > > > > > > > > > > > Sure, but then the schema has to and that means extending > > > > > > > > > > > fixed-partitions. > > > > > > > > > > > > > > > > > > > > Can we cross that bridge later? There might be resistance > > > > > > > > > > to it. I'm > > > > > > > > > > not sure. For now, perhaps just a binman compatible works > > > > > > > > > > well enough > > > > > > > > > > to make progress. > > > > > > > > > > > > > > > > > > Is there any way to make progress on this? I would like to > > > > > > > > > have > > > > > > > > > software which doesn't understand the binman compatible to at > > > > > > > > > least be > > > > > > > > > able to understand the fixed-partition compatible. Is that > > > > > > > > > acceptable? > > > > > > > > > > > > > > > > There's only 2 ways that it can work. Either binman writes out > > > > > > > > fixed-partition nodes dropping/replacing anything only defined > > > > > > > > for > > > > > > > > binman or fixed-partition is extended to include what binman > > > > > > > > needs. > > > > > > > > > > > > > > OK, then I suppose the best way is to add a new binman > > > > > > > compatible, as > > > > > > > is done with this v6 series. People then need to choose it > > > > > > > instead of > > > > > > > fixed-partition. > > > > > > > > > > > > I'm sorry this is not at all what Rob suggested, or did I totally > > > > > > misunderstand his answer? > > > > > > > > > > > > In both cases the solution is to
Re: [PATCH v2] cmd: mtd: OTP access support
On 13.03.2024 09:48, Michael Nazzareno Trimarchi wrote:
> Hi
>
> On Wed, Mar 13, 2024 at 7:43 AM Arseniy Krasnov
> wrote:
>>
>> Sorry, please ping
>>
>> Thanks, Arseniy
>>
>>
>> On 11.02.2024 02:16, Arseniy Krasnov wrote:
>>> Sorry, pls ping
>>>
>>> Thanks, Arseniy
>>>
>>> On 08.01.2024 21:33, Arseniy Krasnov wrote:
Sorry, pls ping
Thanks, Arseniy
On 20.12.2023 22:36, Arseniy Krasnov wrote:
> Add access to OTP region. It supports info, dump, write and lock
> operations.
>
> Signed-off-by: Arseniy Krasnov
> ---
>
> Please extend the commit message with some example of the usage otherwise
Done in v3
Thanks, Arseniy
>
> Reviewed-by: Michael Trimarchi
>
> Changelog:
> v1 -> v2:
> * Remove warning that OTP can't be erased after write.
>
> cmd/Kconfig | 1 +
> cmd/mtd.c | 224
> 2 files changed, 225 insertions(+)
>
> diff --git a/cmd/Kconfig b/cmd/Kconfig
> index 90e4ef93e0..c47523a03b 100644
> --- a/cmd/Kconfig
> +++ b/cmd/Kconfig
> @@ -1354,6 +1354,7 @@ config CMD_MTD
> bool "mtd"
> depends on MTD
> select MTD_PARTITIONS
> + select HEXDUMP
> help
> MTD commands support.
>
> diff --git a/cmd/mtd.c b/cmd/mtd.c
> index eb6e2d6892..1ab69b108b 100644
> --- a/cmd/mtd.c
> +++ b/cmd/mtd.c
> @@ -11,6 +11,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -202,6 +203,219 @@ static bool mtd_oob_write_is_empty(struct
> mtd_oob_ops *op)
> return true;
> }
>
> +static int do_mtd_otp_read(struct cmd_tbl *cmdtp, int flag, int argc,
> + char *const argv[])
> +{
> + struct mtd_info *mtd;
> + size_t retlen;
> + off_t from;
> + size_t len;
> + bool user;
> + int ret;
> + u8 *buf;
> +
> + if (argc != 5)
> + return CMD_RET_USAGE;
> +
> + if (!strcmp(argv[2], "u"))
> + user = true;
> + else if (!strcmp(argv[2], "f"))
> + user = false;
> + else
> + return CMD_RET_USAGE;
> +
> + mtd = get_mtd_by_name(argv[1]);
> + if (IS_ERR_OR_NULL(mtd))
> + return CMD_RET_FAILURE;
> +
> + from = simple_strtoul(argv[3], NULL, 0);
> + len = simple_strtoul(argv[4], NULL, 0);
> +
> + ret = CMD_RET_FAILURE;
> +
> + buf = malloc(len);
> + if (!buf)
> + goto put_mtd;
> +
> + printf("Reading %s OTP from 0x%lx, %lu bytes\n",
> + user ? "user" : "factory", from, len);
> +
> + if (user)
> + ret = mtd_read_user_prot_reg(mtd, from, len, , buf);
> + else
> + ret = mtd_read_fact_prot_reg(mtd, from, len, , buf);
> + if (ret) {
> + free(buf);
> + pr_err("OTP read failed: %d\n", ret);
> + ret = CMD_RET_FAILURE;
> + goto put_mtd;
> + }
> +
> + if (retlen != len)
> + pr_err("OTP read returns %zu, but %zu expected\n",
> + retlen, len);
> +
> + print_hex_dump("", 0, 16, 1, buf, retlen, true);
> +
> + free(buf);
> +
> + ret = CMD_RET_SUCCESS;
> +
> +put_mtd:
> + put_mtd_device(mtd);
> +
> + return ret;
> +}
> +
> +static int do_mtd_otp_lock(struct cmd_tbl *cmdtp, int flag, int argc,
> + char *const argv[])
> +{
> + struct mtd_info *mtd;
> + off_t from;
> + size_t len;
> + int ret;
> +
> + if (argc != 4)
> + return CMD_RET_USAGE;
> +
> + mtd = get_mtd_by_name(argv[1]);
> + if (IS_ERR_OR_NULL(mtd))
> + return CMD_RET_FAILURE;
> +
> + from = simple_strtoul(argv[2], NULL, 0);
> + len = simple_strtoul(argv[3], NULL, 0);
> +
> + ret = mtd_lock_user_prot_reg(mtd, from, len);
> + if (ret) {
> + pr_err("OTP lock failed: %d\n", ret);
> + ret = CMD_RET_FAILURE;
> + goto put_mtd;
> + }
> +
> + ret = CMD_RET_SUCCESS;
> +
> +put_mtd:
> + put_mtd_device(mtd);
> +
> + return ret;
> +}
> +
> +static int do_mtd_otp_write(struct cmd_tbl *cmdtp, int flag, int argc,
> + char *const argv[])
> +{
> + struct mtd_info *mtd;
> + size_t retlen;
> + size_t binlen;
> + u8 *binbuf;
> + off_t from;
> + int ret;
> +
> + if (argc != 4)
> + return CMD_RET_USAGE;
> +
> + mtd = get_mtd_by_name(argv[1]);
> + if (IS_ERR_OR_NULL(mtd))
> + return CMD_RET_FAILURE;
> +
> + from = simple_strtoul(argv[2], NULL, 0);
> + binlen
[PATCH v3] cmd: mtd: OTP access support
Add access to OTP region. It supports info, dump, write and lock
operations. Usage example:
'mtd otpread nand0 u 0 1024' - dump 1024 bytes of user area starting
from offset 0 of device 'nand0'.
'mtd otpwrite nand0 10 11223344' - write binary data 0x11, 0x22, 0x33,
0x44 to offset 10 to user area of device 'nand0'.
'mtd otplock nand0 0 1024' - lock 1024 bytes of user area starting
from offset 0 of device 'nand0'.
'mtd otpinfo nand0 f' - show info about factory area of device 'nand0'.
Signed-off-by: Arseniy Krasnov
Reviewed-by: Michael Trimarchi
---
Changelog:
v1 -> v2:
* Remove warning that OTP can't be erased after write.
v2 -> v3:
* Commit message updated by adding usage.
* R-b added.
cmd/Kconfig | 1 +
cmd/mtd.c | 224
2 files changed, 225 insertions(+)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 90e4ef93e0..c47523a03b 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1354,6 +1354,7 @@ config CMD_MTD
bool "mtd"
depends on MTD
select MTD_PARTITIONS
+ select HEXDUMP
help
MTD commands support.
diff --git a/cmd/mtd.c b/cmd/mtd.c
index eb6e2d6892..1ab69b108b 100644
--- a/cmd/mtd.c
+++ b/cmd/mtd.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -202,6 +203,219 @@ static bool mtd_oob_write_is_empty(struct mtd_oob_ops *op)
return true;
}
+static int do_mtd_otp_read(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct mtd_info *mtd;
+ size_t retlen;
+ off_t from;
+ size_t len;
+ bool user;
+ int ret;
+ u8 *buf;
+
+ if (argc != 5)
+ return CMD_RET_USAGE;
+
+ if (!strcmp(argv[2], "u"))
+ user = true;
+ else if (!strcmp(argv[2], "f"))
+ user = false;
+ else
+ return CMD_RET_USAGE;
+
+ mtd = get_mtd_by_name(argv[1]);
+ if (IS_ERR_OR_NULL(mtd))
+ return CMD_RET_FAILURE;
+
+ from = simple_strtoul(argv[3], NULL, 0);
+ len = simple_strtoul(argv[4], NULL, 0);
+
+ ret = CMD_RET_FAILURE;
+
+ buf = malloc(len);
+ if (!buf)
+ goto put_mtd;
+
+ printf("Reading %s OTP from 0x%lx, %lu bytes\n",
+ user ? "user" : "factory", from, len);
+
+ if (user)
+ ret = mtd_read_user_prot_reg(mtd, from, len, , buf);
+ else
+ ret = mtd_read_fact_prot_reg(mtd, from, len, , buf);
+ if (ret) {
+ free(buf);
+ pr_err("OTP read failed: %d\n", ret);
+ ret = CMD_RET_FAILURE;
+ goto put_mtd;
+ }
+
+ if (retlen != len)
+ pr_err("OTP read returns %zu, but %zu expected\n",
+ retlen, len);
+
+ print_hex_dump("", 0, 16, 1, buf, retlen, true);
+
+ free(buf);
+
+ ret = CMD_RET_SUCCESS;
+
+put_mtd:
+ put_mtd_device(mtd);
+
+ return ret;
+}
+
+static int do_mtd_otp_lock(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct mtd_info *mtd;
+ off_t from;
+ size_t len;
+ int ret;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
+ mtd = get_mtd_by_name(argv[1]);
+ if (IS_ERR_OR_NULL(mtd))
+ return CMD_RET_FAILURE;
+
+ from = simple_strtoul(argv[2], NULL, 0);
+ len = simple_strtoul(argv[3], NULL, 0);
+
+ ret = mtd_lock_user_prot_reg(mtd, from, len);
+ if (ret) {
+ pr_err("OTP lock failed: %d\n", ret);
+ ret = CMD_RET_FAILURE;
+ goto put_mtd;
+ }
+
+ ret = CMD_RET_SUCCESS;
+
+put_mtd:
+ put_mtd_device(mtd);
+
+ return ret;
+}
+
+static int do_mtd_otp_write(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct mtd_info *mtd;
+ size_t retlen;
+ size_t binlen;
+ u8 *binbuf;
+ off_t from;
+ int ret;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
+ mtd = get_mtd_by_name(argv[1]);
+ if (IS_ERR_OR_NULL(mtd))
+ return CMD_RET_FAILURE;
+
+ from = simple_strtoul(argv[2], NULL, 0);
+ binlen = strlen(argv[3]) / 2;
+
+ ret = CMD_RET_FAILURE;
+ binbuf = malloc(binlen);
+ if (!binbuf)
+ goto put_mtd;
+
+ hex2bin(binbuf, argv[3], binlen);
+
+ printf("Will write:\n");
+
+ print_hex_dump("", 0, 16, 1, binbuf, binlen, true);
+
+ printf("to 0x%zx\n", from);
+
+ printf("Continue (y/n)?\n");
+
+ if (confirm_yesno() != 1) {
+ pr_err("OTP write canceled\n");
+ ret = CMD_RET_SUCCESS;
+ goto put_mtd;
+ }
+
+ ret = mtd_write_user_prot_reg(mtd, from, binlen, , binbuf);
+ if (ret) {
+ pr_err("OTP write
Re: [PATCH 7/7 v2] arm: remove redundant section alignments
Hi Richard,
Pasting some of the discussions we had over IRC for completeness.
On Tue, 12 Mar 2024 at 19:00, Richard Henderson
wrote:
>
> On 3/12/24 04:08, Ilias Apalodimas wrote:
> > index 33f4624b561d..ccdd1966cfbc 100644
> > --- a/arch/arm/cpu/armv8/u-boot.lds
> > +++ b/arch/arm/cpu/armv8/u-boot.lds
> > @@ -132,7 +132,7 @@ SECTIONS
> >
> > _end = .;
> >
> > - .bss ALIGN(8): {
> > + .bss : {
> > __bss_start = .;
> > *(.bss*)
> > __bss_end = .;
>
> The code in arch/arm/lib/crt0_64.S assumes __bss_end - __bss_start is a
> multiple of 8.
> But that could probably be replaced by a proper call to memset fairly easily.
>
> > diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
> > index b6b19a4174fe..a9fcbbf22e96 100644
> > --- a/arch/arm/cpu/u-boot.lds
> > +++ b/arch/arm/cpu/u-boot.lds
> > @@ -155,7 +155,7 @@ SECTIONS
> >
> > __image_copy_end = .;
> >
> > - .rel.dyn ALIGN(4) : {
> > + .rel.dyn : {
> > __rel_dyn_start = .;
> > *(.rel*)
> > __rel_dyn_end = .;
>
> Because of the overlay, this affects .bss too.
>
> The code in arch/arm/lib/crt0.S may or may not be configured to use memset.
> When it
> isn't, it requires __bss_end - __bss_start to be a multiple of 4. Why does
> this not
> always use memset?
I think it's due to size restrictions in SPL. Since I can't test all
affected platforms, I prefer leaving it as is at least for now.
I'll explicitly align sections to 4/8 bytes in v3. Once we get this
merged we can try and clean those up as you suggested on a followup
patchset
Thanks
/Ilias
>
>
> r~
Re: [PATCH] arm64: zynqmp: Do not describe u-boot.itb if SPL is disabled
On Wed, 13 Mar 2024 at 08:42, Michal Simek wrote:
>
>
>
> On 3/12/24 20:12, Ilias Apalodimas wrote:
> > On Tue, 12 Mar 2024 at 17:55, Michal Simek wrote:
> >>
> >>
> >>
> >> On 3/12/24 07:14, Ilias Apalodimas wrote:
> >>> Hi Michal
> >>>
> >>> Apologies for the late reply
> >>>
> >>> On Wed, 6 Mar 2024 at 09:48, Michal Simek wrote:
>
>
>
> On 3/5/24 16:47, Ilias Apalodimas wrote:
> > On Fri, Feb 23, 2024 at 05:18:42PM +0100, Michal Simek wrote:
> >> There is no reason to describe u-boot.itb on system without SPL. Pretty
> >> much this is cover all systems which are using only boot.bin which
> >> contains
> >> all images inside.
> >>
> >> Signed-off-by: Michal Simek
> >> ---
> >>
> >> board/xilinx/common/board.c | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
> >> index 9641ed307b75..4f38b7d27684 100644
> >> --- a/board/xilinx/common/board.c
> >> +++ b/board/xilinx/common/board.c
> >> @@ -43,7 +43,7 @@ struct efi_fw_image fw_images[] = {
> >>.image_index = 1,
> >>},
> >> #endif
> >> -#if defined(XILINX_UBOOT_IMAGE_GUID)
> >> +#if defined(XILINX_UBOOT_IMAGE_GUID) &&
> >> defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME)
> >
> > What happens if this is defined with CONFIG_SPL_FS_LOAD_PAYLOAD_NAME=""
> > ?
>
> Your comment is valid but I am not aware about any CONFIG_IS, etc which
> checks
> that string is not empty. If name is "" it will return yes and second
> image is
> doing to be defined.
>
> But I found handling in the code like this.
>
> 36 #ifdef CONFIG_DEFAULT_FDT_FILE
> 37 if (strlen(CONFIG_DEFAULT_FDT_FILE)) {
>
> which can be used in my second patch not to describe second image in
> set_dfu_alt_info() if string is empty.
> >>>
> >>> Yes, I think that's ok. The problem is that if we merge this as-is, we
> >>> would have to disable CONFIG_SPL_FS_FAT to make this work, which is a
> >>> bit misleading
> >>
> >> As Heinrich said not just this if you want to do it like this.
> >> I think you will simply disable the whole SPL which will disable this
> >> symbol too.
> >> But from my perspective SPL payload name is driving this option. Data can
> >> end up
> >> on partition or in raw mode but for dfu you need to use the name.
> >
> > Yes, but isn't SPL selected by the Kconfig automatically? I can't seem
> > to be able to disable it for the kria platforms
>
> Not in upstream but via your/AMD build in meta-ts.
>
> Thanks,
> Michal
>
Reviewed-by: Ilias Apalodimas
