[PATCH 4/4] configs: j721s2_evm_*_defconfig: Enable OSPI configs

[Manorit Chawdhry]

Enable OSPI related configs to boot using OSPI

Signed-off-by: Manorit Chawdhry 
---
 configs/j721s2_evm_a72_defconfig | 3 +++
 configs/j721s2_evm_r5_defconfig  | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index 92f69413fa40..6e7e161fa359 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -50,6 +50,7 @@ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
 CONFIG_SPL_I2C=y
 CONFIG_SPL_DM_MAILBOX=y
 CONFIG_SPL_MTD=y
+CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_DM_RESET=y
@@ -58,6 +59,8 @@ CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=2500
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x28
 CONFIG_SPL_THERMAL=y
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index cb6b4a44864f..197b3284c12d 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -57,6 +57,7 @@ CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_I2C=y
 CONFIG_SPL_DM_MAILBOX=y
 CONFIG_SPL_MTD=y
+CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_DM_RESET=y
@@ -66,6 +67,8 @@ CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_REMOTEPROC=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=2500
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x8
 CONFIG_SPL_THERMAL=y

-- 
2.43.2

[PATCH 3/4] arch: arm: dts: k3-j721s2-*-u-boot.dtsi: Enable the ospi0 node

[Manorit Chawdhry]

Enable ospi0 node for all boot stages

Signed-off-by: Manorit Chawdhry 
---
 arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi 
b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
index a3ebf5996eac..132cd5a456ba 100644
--- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
@@ -110,7 +110,9 @@
 };
 
  {
-   status = "disabled";
+   flash@0 {
+   bootph-all;
+   };
 };
 
  {

-- 
2.43.2

[PATCH 2/4] arch: arm: dts: k3-j721s2-r5: Override ospi and fss for 32-bit mode

[Manorit Chawdhry]

R5 being a 32-bit processor can't understand the 64-bit mapping being
done in ospi node. Override the ospi node for 32-bit register ranges and
the fss node ( the parent node of ospi ) to map the ranges for the
updated child node correctly.

Signed-off-by: Manorit Chawdhry 
---
 arch/arm/dts/k3-j721s2-r5-common-proc-board.dts | 13 +
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts 
b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
index 03bd680f4421..5c4b34915ccf 100644
--- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
@@ -86,3 +86,16 @@
 _udmap {
ti,sci = <_tifs>;
 };
+
+ {
+   reg = <0x0 0x4704 0x0 0x100>,
+ <0x0 0x5000 0x0 0x800>;
+};
+
+ {
+   /* fss node has 64 bit address regions mapped to it and since the ospi
+* nodes is being override, override the fss node ranges as well
+*/
+   ranges = <0x0 0x4700 0x0 0x4700 0x0 0x00068400>,
+<0x0 0x5000 0x0 0x5000 0x0 0x0800>;
+};

-- 
2.43.2

[PATCH 1/4] mtd: spi-nor-core: Do not start or end writes at odd address in DTR mode

[Manorit Chawdhry]

From: Pratyush Yadav 

On DTR capable flashes like Micron Xcella the writes cannot start or end
at an odd address in DTR mode. Extra 0xff bytes need to be prepended or
appended respectively to make sure both the start and end addresses are
even.

Signed-off-by: Pratyush Yadav 
Reviewed-by: Vignesh Raghavendra 
Signed-off-by: Apurva Nandan 
Signed-off-by: Vignesh Raghavendra 
Signed-off-by: Manorit Chawdhry 
---
 drivers/mtd/spi/spi-nor-core.c | 59 +++---
 1 file changed, 55 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index f86003ca8c06..2b000151c97d 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -1805,11 +1805,62 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t 
to, size_t len,
if (ret < 0)
return ret;
 #endif
+
write_enable(nor);
-   ret = nor->write(nor, addr, page_remain, buf + i);
-   if (ret < 0)
-   goto write_err;
-   written = ret;
+
+   /*
+* On DTR capable flashes like Micron Xcella the writes cannot
+* start or end at an odd address in DTR mode. So we need to
+* append or prepend extra 0xff bytes to make sure the start
+* address and end address are even.
+*/
+   if (spi_nor_protocol_is_dtr(nor->write_proto) &&
+   ((addr | page_remain) & 1)) {
+   u_char *tmp;
+   size_t extra_bytes = 0;
+
+   tmp = kmalloc(nor->page_size, 0);
+   if (!tmp) {
+   ret = -ENOMEM;
+   goto write_err;
+   }
+
+   /* Prepend a 0xff byte if the start address is odd. */
+   if (addr & 1) {
+   tmp[0] = 0xff;
+   memcpy(tmp + 1, buf + i, page_remain);
+   addr--;
+   page_remain++;
+   extra_bytes++;
+   } else {
+   memcpy(tmp, buf + i, page_remain);
+   }
+
+   /* Append a 0xff byte if the end address is odd. */
+   if ((addr + page_remain) & 1) {
+   tmp[page_remain + extra_bytes] = 0xff;
+   extra_bytes++;
+   page_remain++;
+   }
+
+   ret = nor->write(nor, addr, page_remain, tmp);
+
+   kfree(tmp);
+
+   if (ret < 0)
+   goto write_err;
+
+   /*
+* We write extra bytes but they are not part of the
+* original write.
+*/
+   written = ret - extra_bytes;
+   } else {
+   ret = nor->write(nor, addr, page_remain, buf + i);
+   if (ret < 0)
+   goto write_err;
+   written = ret;
+   }
 
ret = spi_nor_wait_till_ready(nor);
if (ret)

-- 
2.43.2

[PATCH 0/4] Enable OSPI boot for j721s2

[Manorit Chawdhry]

The series enables ospi boot for j721s2.

Test logs: https://gist.github.com/manorit2001/6bb91885c608e3a8cb0267ab2c614781

Signed-off-by: Manorit Chawdhry 
---
Manorit Chawdhry (3):
  arch: arm: dts: k3-j721s2-r5: Override ospi and fss for 32-bit mode
  arch: arm: dts: k3-j721s2-*-u-boot.dtsi: Enable the ospi0 node
  configs: j721s2_evm_*_defconfig: Enable OSPI configs

Pratyush Yadav (1):
  mtd: spi-nor-core: Do not start or end writes at odd address in DTR mode

 .../dts/k3-j721s2-common-proc-board-u-boot.dtsi|  4 +-
 arch/arm/dts/k3-j721s2-r5-common-proc-board.dts| 13 +
 configs/j721s2_evm_a72_defconfig   |  3 ++
 configs/j721s2_evm_r5_defconfig|  3 ++
 drivers/mtd/spi/spi-nor-core.c | 59 --
 5 files changed, 77 insertions(+), 5 deletions(-)
---
base-commit: ab8d9ca3044acf51d8ff3bf3c4718c48f30ad606
change-id: 20240322-b4-upstream-j721s2-ospi-support-d45dfaa926dc

Best regards,
-- 
Manorit Chawdhry 

Re: [PATCH v5 15/16] qcom_defconfig: enable USB

[Sumit Garg]

On Thu, 28 Mar 2024 at 23:29, Caleb Connolly  wrote:
>
> Enable support for the DWC3 USB controller and required dependencies for
> Qualcomm boards, specifically the DB845c:
> * IOMMU / SMMU
> * USB high-speed PHYs
> * Mass storage and ACM gadgets
>
> Signed-off-by: Caleb Connolly 
> ---
>  configs/qcom_defconfig | 52 
> --
>  1 file changed, 29 insertions(+), 23 deletions(-)
>

Reviewed-by: Sumit Garg 

-Sumit

> diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
> index 8c4402e8f780..1abb57345ff1 100644
> --- a/configs/qcom_defconfig
> +++ b/configs/qcom_defconfig
> @@ -17,10 +17,16 @@ CONFIG_LOG_MAX_LEVEL=9
>  CONFIG_LOG_DEFAULT_LEVEL=4
>  # CONFIG_DISPLAY_CPUINFO is not set
>  CONFIG_DISPLAY_BOARDINFO_LATE=y
>  CONFIG_CMD_BOOTMENU=y
> +CONFIG_CMD_EEPROM=y
> +CONFIG_SYS_I2C_EEPROM_BUS=2
> +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
> +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
> +# CONFIG_CMD_BIND is not set
>  CONFIG_CMD_CLK=y
>  CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
>  CONFIG_CMD_MMC=y
>  CONFIG_CMD_UFS=y
>  CONFIG_CMD_USB=y
>  CONFIG_CMD_CAT=y
> @@ -32,20 +38,39 @@ CONFIG_CLK=y
>  CONFIG_CLK_QCOM_QCS404=y
>  CONFIG_CLK_QCOM_SDM845=y
>  CONFIG_MSM_GPIO=y
>  CONFIG_QCOM_PMIC_GPIO=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_QUP=y
> +CONFIG_I2C_MUX=y
>  CONFIG_DM_KEYBOARD=y
>  CONFIG_BUTTON_KEYBOARD=y
> +CONFIG_IOMMU=y
> +CONFIG_QCOM_HYP_SMMU=y
> +CONFIG_MISC=y
> +CONFIG_NVMEM=y
> +CONFIG_I2C_EEPROM=y
>  CONFIG_MMC_HS200_SUPPORT=y
>  CONFIG_MMC_SDHCI=y
>  CONFIG_MMC_SDHCI_ADMA=y
>  CONFIG_MMC_SDHCI_MSM=y
> +CONFIG_PHY_MICREL=y
> +CONFIG_PHY_MICREL_KSZ90X1=y
> +CONFIG_DM_MDIO=y
> +CONFIG_DM_ETH_PHY=y
> +CONFIG_DWC_ETH_QOS=y
> +CONFIG_DWC_ETH_QOS_QCOM=y
> +CONFIG_RGMII=y
>  CONFIG_PHY=y
> +CONFIG_PHY_QCOM_QUSB2=y
> +CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y
>  CONFIG_PINCTRL=y
>  CONFIG_PINCTRL_QCOM_QCS404=y
>  CONFIG_PINCTRL_QCOM_SDM845=y
>  CONFIG_DM_PMIC=y
>  CONFIG_PMIC_QCOM=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
>  CONFIG_SCSI=y
>  CONFIG_MSM_SERIAL=y
>  CONFIG_MSM_GENI_SERIAL=y
>  CONFIG_SPMI_MSM=y
> @@ -54,8 +79,12 @@ CONFIG_SYSINFO_SMBIOS=y
>  CONFIG_USB=y
>  CONFIG_USB_XHCI_HCD=y
>  CONFIG_USB_XHCI_DWC3=y
>  CONFIG_USB_DWC3=y
> +CONFIG_USB_DWC3_GENERIC=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_DOWNLOAD=y
> +CONFIG_USB_FUNCTION_MASS_STORAGE=y
>  CONFIG_UFS=y
>  CONFIG_VIDEO=y
>  # CONFIG_VIDEO_FONT_8X16 is not set
>  CONFIG_VIDEO_FONT_16X32=y
> @@ -64,27 +93,4 @@ CONFIG_NO_FB_CLEAR=y
>  CONFIG_VIDEO_SIMPLE=y
>  CONFIG_HEXDUMP=y
>  # CONFIG_GENERATE_SMBIOS_TABLE is not set
>  CONFIG_LMB_MAX_REGIONS=64
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_EEPROM=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_PING=y
> -CONFIG_DM_ETH=y
> -CONFIG_DM_ETH_PHY=y
> -CONFIG_DM_MDIO=y
> -CONFIG_DWC_ETH_QOS=y
> -CONFIG_DWC_ETH_QOS_QCOM=y
> -CONFIG_RGMII=y
> -CONFIG_PHY_MICREL=y
> -CONFIG_PHY_MICREL_KSZ90X1=y
> -CONFIG_MISC=y
> -CONFIG_NVMEM=y
> -CONFIG_DM_I2C=y
> -CONFIG_I2C_SUPPORT=y
> -CONFIG_I2C_MUX=y
> -CONFIG_I2C_EEPROM=y
> -CONFIG_SYS_I2C=y
> -CONFIG_SYS_I2C_QUP=y
> -CONFIG_SYS_I2C_EEPROM_BUS=2
> -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
> -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
>
> --
> 2.44.0
>

Re: [PATCH v5 14/16] qcom_defconfig: enable livetree

[Sumit Garg]

On Thu, 28 Mar 2024 at 23:29, Caleb Connolly  wrote:
>
> Qualcomm FDTs are on the larger size, and with the addition of DT
> modifications during board_init() it makes sense to enable OF_LIVE
> globally. The cost of building the tree should be offset by the
> increased efficiency at which we can walk it.
>
> Some rough measurements with CONFIG_BOOTSTAGE suggests that this might
> add 0.1-0.2ms to the boot-to-console time. However the reset-to-reset
> timer difference is in the range of 0.5ms so this could just be noise.
>
> Suffice to say, no significant slow down.
>
> Reviewed-by: Neil Armstrong 
> Signed-off-by: Caleb Connolly 
> ---
>  configs/qcom_defconfig | 1 +
>  1 file changed, 1 insertion(+)
>

Acked-by: Sumit Garg 

-Sumit

> diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
> index cbc612b44bd9..8c4402e8f780 100644
> --- a/configs/qcom_defconfig
> +++ b/configs/qcom_defconfig
> @@ -25,8 +25,9 @@ CONFIG_CMD_UFS=y
>  CONFIG_CMD_USB=y
>  CONFIG_CMD_CAT=y
>  CONFIG_CMD_BMP=y
>  CONFIG_CMD_LOG=y
> +CONFIG_OF_LIVE=y
>  CONFIG_BUTTON_QCOM_PMIC=y
>  CONFIG_CLK=y
>  CONFIG_CLK_QCOM_QCS404=y
>  CONFIG_CLK_QCOM_SDM845=y
>
> --
> 2.44.0
>

Re: [PATCH v5 13/16] dts: sdm845-db845c: add u-boot fixups

[Sumit Garg]

On Thu, 28 Mar 2024 at 23:29, Caleb Connolly  wrote:
>
> The USB VBUS supply for the type-A port is enabled via a GPIO regulator.
> This is incorrectly modelled in Linux where only the PCIe dependency is
> expressed. The correct way to handle this will be through a
> usb-connector node, but for now we'll just mark the regulator as
> always-on so that it will be enabled automatically during boot.
>
> Signed-off-by: Caleb Connolly 
> ---
>  arch/arm/dts/sdm845-db845c-u-boot.dtsi | 9 +
>  1 file changed, 9 insertions(+)
>

Reviewed-by: Sumit Garg 

-Sumit

> diff --git a/arch/arm/dts/sdm845-db845c-u-boot.dtsi 
> b/arch/arm/dts/sdm845-db845c-u-boot.dtsi
> new file mode 100644
> index ..906f9faa5451
> --- /dev/null
> +++ b/arch/arm/dts/sdm845-db845c-u-boot.dtsi
> @@ -0,0 +1,9 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/* Needed for Linux to boot from USB, otherwise if PCIe driver is not in 
> initramfs
> + * the VBUS supply will never get turned on.
> + * 
> https://lore.kernel.org/linux-arm-msm/20240320122515.3243711-1-caleb.conno...@linaro.org/
> + */
> +_3p3v_dual {
> +   regulator-always-on;
> +};
>
> --
> 2.44.0
>

Re: [PATCH v5 12/16] mach-snapdragon: call regulators_enable_boot_on()

[Sumit Garg]

On Thu, 28 Mar 2024 at 23:29, Caleb Connolly  wrote:
>
> Make sure we power on any boot-on or always-on regulators. These are
> used for peripherals like USB on some platforms.
>
> Signed-off-by: Caleb Connolly 
> ---
>  arch/arm/mach-snapdragon/board.c | 2 ++
>  1 file changed, 2 insertions(+)
>

Reviewed-by: Sumit Garg 

-Sumit

> diff --git a/arch/arm/mach-snapdragon/board.c 
> b/arch/arm/mach-snapdragon/board.c
> index 65e4c61e866a..3d5994c87886 100644
> --- a/arch/arm/mach-snapdragon/board.c
> +++ b/arch/arm/mach-snapdragon/board.c
> @@ -15,8 +15,9 @@
>  #include 
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
>  #include 
> @@ -160,8 +161,9 @@ void __weak qcom_board_init(void)
>  }
>
>  int board_init(void)
>  {
> +   regulators_enable_boot_on(false);
> show_psci_version();
> qcom_of_fixup_nodes();
> qcom_board_init();
> return 0;
>
> --
> 2.44.0
>

Re: [PATCH v5 11/16] mach-snapdragon: fixup power-domains

[Sumit Garg]

On Thu, 28 Mar 2024 at 23:29, Caleb Connolly  wrote:
>
> We don't support the RPM(h)PD power domains in U-Boot, and we don't need
> to - the necessary resources are on, and we aren't going to enter any
> low power modes.
>
> We could try using a no-op device, but this requires adding a compatible
> for every platform, and just pollutes the driver model. So instead let's
> just remove every "power-domains" property that references the RPM(h)pd
> power controller. This takes <1ms as we're using OF_LIVE.
>
> Of note, this only applies to drivers which are loading post-relocation.
> Drivers loaded pre-reloc that reference the rpm(h)pd still need
> DM_FLAG_DEFAULT_PD_CTRL_OFF in their flags.
>
> Signed-off-by: Caleb Connolly 
> ---
>  arch/arm/mach-snapdragon/of_fixup.c | 32 
>  1 file changed, 32 insertions(+)
>

Acked-by: Sumit Garg 

-Sumit

> diff --git a/arch/arm/mach-snapdragon/of_fixup.c 
> b/arch/arm/mach-snapdragon/of_fixup.c
> index 4fdfed2dff16..3f7ac227bd09 100644
> --- a/arch/arm/mach-snapdragon/of_fixup.c
> +++ b/arch/arm/mach-snapdragon/of_fixup.c
> @@ -21,8 +21,9 @@
>  #include 
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>
>  /* U-Boot only supports USB high-speed mode on Qualcomm platforms with DWC3
>   * USB controllers. Rather than requiring source level DT changes, we fix up
> @@ -109,8 +110,38 @@ static void fixup_usb_nodes(void)
> log_warning("Failed to fixup node %s: %d\n", 
> glue_np->name, ret);
> }
>  }
>
> +/* Remove all references to the rpmhpd device */
> +static void fixup_power_domains(void)
> +{
> +   struct device_node *pd = NULL, *np = NULL;
> +   struct property *prop;
> +   const __be32 *val;
> +
> +   /* All Qualcomm platforms name the rpm(h)pd "power-controller" */
> +   for_each_of_allnodes(pd) {
> +   if (pd->name && !strcmp("power-controller", pd->name))
> +   break;
> +   }
> +
> +   /* Sanity check that this is indeed a power domain controller */
> +   if (!of_find_property(pd, "#power-domain-cells", NULL)) {
> +   log_err("Found power-controller but it doesn't have 
> #power-domain-cells\n");
> +   return;
> +   }
> +
> +   /* Remove all references to the power domain controller */
> +   for_each_of_allnodes(np) {
> +   if (!(prop = of_find_property(np, "power-domains", NULL)))
> +   continue;
> +
> +   val = prop->value;
> +   if (val[0] == cpu_to_fdt32(pd->phandle))
> +   of_remove_property(np, prop);
> +   }
> +}
> +
>  #define time_call(func, ...) \
> do { \
> u64 start = timer_get_us(); \
> func(__VA_ARGS__); \
> @@ -119,5 +150,6 @@ static void fixup_usb_nodes(void)
>
>  void qcom_of_fixup_nodes(void)
>  {
> time_call(fixup_usb_nodes);
> +   time_call(fixup_power_domains);
>  }
>
> --
> 2.44.0
>

Re: [PATCH v5 10/16] mach-snapdragon: fixup USB nodes

[Sumit Garg]

On Thu, 28 Mar 2024 at 23:29, Caleb Connolly  wrote:
>
> We don't support USB super-speed in U-Boot yet, we lack the SS PHY
> drivers, however from my testing even with a PHY driver there seem to be
> other issues when talking to super-speed peripherals.
>
> In pursuit of maintaining upstream DT compatibility, and simplifying
> porting for new devices, let's implement the DT fixups necessary to
> configure USB in high-speed only mode at runtime. The pattern is
> identical for all Qualcomm boards that use the Synaptics DWC3
> controller:
>
> * Add an additional property on the Qualcomm wrapper node
> * Remove the super-speed phy phandle and phy-name entries.
>
> Signed-off-by: Caleb Connolly 
> ---
>  arch/arm/mach-snapdragon/Makefile|   1 +
>  arch/arm/mach-snapdragon/board.c |   3 +
>  arch/arm/mach-snapdragon/of_fixup.c  | 123 
> +++
>  arch/arm/mach-snapdragon/qcom-priv.h |  20 ++
>  4 files changed, 147 insertions(+)
>

Acked-by: Sumit Garg 

-Sumit

> diff --git a/arch/arm/mach-snapdragon/Makefile 
> b/arch/arm/mach-snapdragon/Makefile
> index 857171e593da..7a4495c8108f 100644
> --- a/arch/arm/mach-snapdragon/Makefile
> +++ b/arch/arm/mach-snapdragon/Makefile
> @@ -2,4 +2,5 @@
>  #
>  # (C) Copyright 2015 Mateusz Kulikowski 
>
>  obj-y += board.o
> +obj-$(CONFIG_OF_LIVE) += of_fixup.o
> diff --git a/arch/arm/mach-snapdragon/board.c 
> b/arch/arm/mach-snapdragon/board.c
> index 6f762fc948bf..65e4c61e866a 100644
> --- a/arch/arm/mach-snapdragon/board.c
> +++ b/arch/arm/mach-snapdragon/board.c
> @@ -27,8 +27,10 @@
>  #include 
>  #include 
>  #include 
>
> +#include "qcom-priv.h"
> +
>  DECLARE_GLOBAL_DATA_PTR;
>
>  static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } };
>
> @@ -159,8 +161,9 @@ void __weak qcom_board_init(void)
>
>  int board_init(void)
>  {
> show_psci_version();
> +   qcom_of_fixup_nodes();
> qcom_board_init();
> return 0;
>  }
>
> diff --git a/arch/arm/mach-snapdragon/of_fixup.c 
> b/arch/arm/mach-snapdragon/of_fixup.c
> new file mode 100644
> index ..4fdfed2dff16
> --- /dev/null
> +++ b/arch/arm/mach-snapdragon/of_fixup.c
> @@ -0,0 +1,123 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * OF_LIVE devicetree fixup.
> + *
> + * This file implements runtime fixups for Qualcomm DT to improve
> + * compatibility with U-Boot. This includes adjusting the USB nodes
> + * to only use USB high-speed, as well as remapping volume buttons
> + * to behave as up/down for navigating U-Boot.
> + *
> + * We use OF_LIVE for this rather than early FDT fixup for a couple
> + * of reasons: it has a much nicer API, is most likely more efficient,
> + * and our changes are only applied to U-Boot. This allows us to use a
> + * DT designed for Linux, run U-Boot with a modified version, and then
> + * boot Linux with the original FDT.
> + *
> + * Copyright (c) 2024 Linaro Ltd.
> + *   Author: Caleb Connolly 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/* U-Boot only supports USB high-speed mode on Qualcomm platforms with DWC3
> + * USB controllers. Rather than requiring source level DT changes, we fix up
> + * DT here. This improves compatibility with upstream DT and simplifies the
> + * porting process for new devices.
> + */
> +static int fixup_qcom_dwc3(struct device_node *glue_np)
> +{
> +   struct device_node *dwc3;
> +   int ret, len, hsphy_idx = 1;
> +   const __be32 *phandles;
> +   const char *second_phy_name;
> +
> +   debug("Fixing up %s\n", glue_np->name);
> +
> +   /* Tell the glue driver to configure the wrapper for high-speed only 
> operation */
> +   ret = of_write_prop(glue_np, "qcom,select-utmi-as-pipe-clk", 0, NULL);
> +   if (ret) {
> +   log_err("Failed to add property 
> 'qcom,select-utmi-as-pipe-clk': %d\n", ret);
> +   return ret;
> +   }
> +
> +   /* Find the DWC3 node itself */
> +   dwc3 = of_find_compatible_node(glue_np, NULL, "snps,dwc3");
> +   if (!dwc3) {
> +   log_err("Failed to find dwc3 node\n");
> +   return -ENOENT;
> +   }
> +
> +   phandles = of_get_property(dwc3, "phys", );
> +   len /= sizeof(*phandles);
> +   if (len == 1) {
> +   log_debug("Only one phy, not a superspeed controller\n");
> +   return 0;
> +   }
> +
> +   /* Figure out if the superspeed phy is present and if so then which 
> phy is it? */
> +   ret = of_property_read_string_index(dwc3, "phy-names", 1, 
> _phy_name);
> +   if (ret == -ENODATA) {
> +   log_debug("Only one phy, not a super-speed controller\n");
> +   return 0;
> +   } else if (ret) {
> +   log_err("Failed to read second phy name: %d\n", ret);
> +   return ret;
> +   }
> +
> +   if (!strncmp("usb3-phy", second_phy_name, strlen("usb3-phy"))) {
> +   

Re: [PATCH v5 03/16] phy: qcom: Add SNPS femto v2 USB HS phy

[Sumit Garg]

On Thu, 28 Mar 2024 at 23:29, Caleb Connolly  wrote:
>
> From: Bhupesh Sharma 
>
> Some Qualcomm SoCs newer than SDM845 feature a so-called "7nm phy"
> driver, notable the SM8250 SoC which will gain U-Boot support in
> upcoming patches.
>
> Introduce a driver based on the Linux driver.
>
> Signed-off-by: Bhupesh Sharma 
> [code cleanup, align symbol names with Linux, switch to clk/reset_bulk APIs]
> Signed-off-by: Caleb Connolly 
> ---
>  drivers/phy/qcom/Kconfig  |   8 ++
>  drivers/phy/qcom/Makefile |   1 +
>  drivers/phy/qcom/phy-qcom-snps-femto-v2.c | 207 
> ++
>  3 files changed, 216 insertions(+)
>
> diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig
> index 361dfb6e1126..b9fe608c2798 100644
> --- a/drivers/phy/qcom/Kconfig
> +++ b/drivers/phy/qcom/Kconfig
> @@ -18,8 +18,16 @@ config PHY_QCOM_QUSB2
> help
>   Enable this to support the Super-Speed USB transceiver on various
>   Qualcomm chipsets.
>
> +config PHY_QCOM_USB_SNPS_FEMTO_V2
> +   tristate "Qualcomm SNPS FEMTO USB HS PHY v2"
> +   depends on PHY && ARCH_SNAPDRAGON
> +   help
> + Enable this to support the Qualcomm Synopsys DesignWare Core 7nm
> + High-Speed PHY driver. This driver supports the Hi-Speed PHY which
> + is usually paired with Synopsys DWC3 USB IPs on MSM SOCs.
> +
>  config PHY_QCOM_USB_HS_28NM
> tristate "Qualcomm 28nm High-Speed PHY"
> depends on PHY && ARCH_SNAPDRAGON
> help
> diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile
> index f6af985666a4..5f4db4a53788 100644
> --- a/drivers/phy/qcom/Makefile
> +++ b/drivers/phy/qcom/Makefile
> @@ -1,5 +1,6 @@
>  obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
>  obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
>  obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
> +obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2) += phy-qcom-snps-femto-v2.o
>  obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
>  obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o
> diff --git a/drivers/phy/qcom/phy-qcom-snps-femto-v2.c 
> b/drivers/phy/qcom/phy-qcom-snps-femto-v2.c
> new file mode 100644
> index ..58eb01972402
> --- /dev/null
> +++ b/drivers/phy/qcom/phy-qcom-snps-femto-v2.c
> @@ -0,0 +1,207 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + * Copyright (C) 2023 Bhupesh Sharma 
> + *
> + * Based on Linux driver
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c)
> +#define SLEEPM BIT(0)
> +#define OPMODE_MASK GENMASK(4, 3)
> +#define OPMODE_NORMAL (0x00)
> +#define OPMODE_NONDRIVING BIT(3)
> +#define TERMSEL BIT(5)
> +
> +#define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50)
> +#define POR BIT(1)
> +
> +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
> +#define SIDDQ BIT(2)
> +#define RETENABLEN BIT(3)
> +#define FSEL_MASK GENMASK(6, 4)
> +#define FSEL_DEFAULT (0x3 << 4)
> +
> +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58)
> +#define VBUSVLDEXTSEL0 BIT(4)
> +#define PLLBTUNE BIT(5)
> +
> +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c)
> +#define VREGBYPASS BIT(0)
> +
> +#define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60)
> +#define VBUSVLDEXT0 BIT(0)
> +
> +#define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64)
> +#define USB2_AUTO_RESUME BIT(0)
> +#define USB2_SUSPEND_N BIT(2)
> +#define USB2_SUSPEND_N_SEL BIT(3)
> +
> +#define USB2_PHY_USB_PHY_CFG0 (0x94)
> +#define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0)
> +#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1)
> +
> +#define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0)
> +#define REFCLK_SEL_MASK GENMASK(1, 0)
> +#define REFCLK_SEL_DEFAULT (0x2 << 0)
> +
> +struct qcom_snps_hsphy {
> +   void __iomem *base;
> +   struct clk_bulk clks;
> +   struct reset_ctl_bulk resets;
> +};
> +
> +static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset,
> + u32 mask, u32 val)
> +{
> +   u32 reg;
> +
> +   reg = readl_relaxed(base + offset);
> +
> +   reg &= ~mask;
> +   reg |= val & mask;
> +   writel_relaxed(reg, base + offset);
> +
> +   /* Ensure above write is completed */
> +   readl_relaxed(base + offset);

It looks like you have missed addressing comments related to this API.
Again, why do we need this special handling in U-Boot? Why not just
clrsetbits_le32()?

-Sumit

> +}
> +
> +static int qcom_snps_hsphy_usb_init(struct phy *phy)
> +{
> +   struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev);
> +
> +   qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_CFG0,
> +  UTMI_PHY_CMN_CTRL_OVERRIDE_EN,
> +  UTMI_PHY_CMN_CTRL_OVERRIDE_EN);
> +   

Re: [PATCH v5 02/16] phy: qcom: add Qualcomm QUSB2 USB PHY driver

[Sumit Garg]

On Thu, 28 Mar 2024 at 23:29, Caleb Connolly  wrote:
>
> From: Bhupesh Sharma 
>
> The Snapdragon 845 and several other Qualcomm SoCs feature this
> USB high-speed phy. Add a driver for it based on the Linux driver, with
> support for the SDM845, and the QCM2290 and SM6115 SoCs which will gain
> support in U-Boot in future patches.
>
> Signed-off-by: Bhupesh Sharma 
> [code cleanup, switch to clk_bulk]
> Signed-off-by: Caleb Connolly 
> ---
>  drivers/phy/qcom/Kconfig  |   7 +
>  drivers/phy/qcom/Makefile |   1 +
>  drivers/phy/qcom/phy-qcom-qusb2.c | 429 
> ++
>  3 files changed, 437 insertions(+)
>

Acked-by: Sumit Garg 

-Sumit

> diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig
> index f4ca174805a4..361dfb6e1126 100644
> --- a/drivers/phy/qcom/Kconfig
> +++ b/drivers/phy/qcom/Kconfig
> @@ -11,8 +11,15 @@ config PHY_QCOM_IPQ4019_USB
> depends on PHY && ARCH_IPQ40XX
> help
>   Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
>
> +config PHY_QCOM_QUSB2
> +   tristate "Qualcomm USB QUSB2 PHY driver"
> +   depends on PHY && ARCH_SNAPDRAGON
> +   help
> + Enable this to support the Super-Speed USB transceiver on various
> + Qualcomm chipsets.
> +
>  config PHY_QCOM_USB_HS_28NM
> tristate "Qualcomm 28nm High-Speed PHY"
> depends on PHY && ARCH_SNAPDRAGON
> help
> diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile
> index 2113f178c0c7..f6af985666a4 100644
> --- a/drivers/phy/qcom/Makefile
> +++ b/drivers/phy/qcom/Makefile
> @@ -1,4 +1,5 @@
>  obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
>  obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
> +obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
>  obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
>  obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o
> diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c 
> b/drivers/phy/qcom/phy-qcom-qusb2.c
> new file mode 100644
> index ..c91ba18c4ab1
> --- /dev/null
> +++ b/drivers/phy/qcom/phy-qcom-qusb2.c
> @@ -0,0 +1,429 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2023 Bhupesh Sharma 
> + *
> + * Based on Linux driver
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +#define QUSB2PHY_PLL 0x0
> +#define QUSB2PHY_PLL_TEST 0x04
> +#define CLK_REF_SEL BIT(7)
> +
> +#define QUSB2PHY_PLL_TUNE 0x08
> +#define QUSB2PHY_PLL_USER_CTL1 0x0c
> +#define QUSB2PHY_PLL_USER_CTL2 0x10
> +#define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c
> +#define QUSB2PHY_PLL_PWR_CTRL 0x18
> +
> +/* QUSB2PHY_PLL_STATUS register bits */
> +#define PLL_LOCKED BIT(5)
> +
> +/* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */
> +#define CORE_READY_STATUS BIT(0)
> +
> +/* QUSB2PHY_PORT_POWERDOWN register bits */
> +#define CLAMP_N_EN BIT(5)
> +#define FREEZIO_N BIT(1)
> +#define POWER_DOWN BIT(0)
> +
> +/* QUSB2PHY_PWR_CTRL1 register bits */
> +#define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5)
> +#define PWR_CTRL1_CLAMP_N_EN BIT(1)
> +
> +#define QUSB2PHY_REFCLK_ENABLE BIT(0)
> +
> +#define PHY_CLK_SCHEME_SEL BIT(0)
> +
> +/* QUSB2PHY_INTR_CTRL register bits */
> +#define DMSE_INTR_HIGH_SEL BIT(4)
> +#define DPSE_INTR_HIGH_SEL BIT(3)
> +#define CHG_DET_INTR_EN BIT(2)
> +#define DMSE_INTR_EN BIT(1)
> +#define DPSE_INTR_EN BIT(0)
> +
> +/* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */
> +#define CORE_PLL_EN_FROM_RESET BIT(4)
> +#define CORE_RESET BIT(5)
> +#define CORE_RESET_MUX BIT(6)
> +
> +/* QUSB2PHY_IMP_CTRL1 register bits */
> +#define IMP_RES_OFFSET_MASK GENMASK(5, 0)
> +#define IMP_RES_OFFSET_SHIFT 0x0
> +
> +/* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */
> +#define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0)
> +#define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0
> +
> +/* QUSB2PHY_CHG_CONTROL_2 register bits */
> +#define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4)
> +#define CHG_CTRL2_OFFSET_SHIFT 0x4
> +
> +/* QUSB2PHY_PORT_TUNE1 register bits */
> +#define HSTX_TRIM_MASK GENMASK(7, 4)
> +#define HSTX_TRIM_SHIFT 0x4
> +#define PREEMPH_WIDTH_HALF_BIT BIT(2)
> +#define PREEMPHASIS_EN_MASK GENMASK(1, 0)
> +#define PREEMPHASIS_EN_SHIFT 0x0
> +
> +/* QUSB2PHY_PORT_TUNE2 register bits */
> +#define HSDISC_TRIM_MASK GENMASK(1, 0)
> +#define HSDISC_TRIM_SHIFT 0x0
> +
> +#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04
> +#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c
> +#define QUSB2PHY_PLL_CMODE 0x2c
> +#define QUSB2PHY_PLL_LOCK_DELAY 0x184
> +#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4
> +#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194
> +#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198
> +#define QUSB2PHY_PWR_CTRL2 0x214
> +#define QUSB2PHY_IMP_CTRL1 0x220
> +#define QUSB2PHY_IMP_CTRL2 0x224
> +#define QUSB2PHY_CHG_CTRL2 0x23c
> +
> +struct qusb2_phy_init_tbl {
> +   unsigned int offset;
> +   unsigned int val;
> +   /*
> +* register part of layout ?
> +* if yes, then offset gives index in 

[PATCH v2 1/1] xilinx: zynq: add FDT_FIXUP_PARTITIONS support

[James Hilliard]

There are situations where we may want to let U-Boot modify the FDT
nand partitions for the kernel, such as when supporting multiple
sizes of NAND chips.

Signed-off-by: James Hilliard 
---
Changes v1 -> v2:
  - move partition fixups to board/xilinx/common/board.c
---
 board/xilinx/common/board.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 9641ed307b..20a6f00e45 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -20,6 +21,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "board.h"
 #include 
 #include 
@@ -693,6 +695,13 @@ int ft_board_setup(void *blob, struct bd_info *bd)
u8 buf[MAX_RAND_SIZE];
int nodeoffset, ret;
 
+   static const struct node_info nodes[] = {
+   { "arm,pl353-nand-r2p1", MTD_DEV_TYPE_NAND, },
+   };
+
+   if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS) && 
IS_ENABLED(CONFIG_NAND_ZYNQ))
+   fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+
if (uclass_get_device(UCLASS_RNG, 0, ) || !dev) {
debug("No RNG device\n");
return 0;
-- 
2.34.1

[PATCH v2 2/2] arm: imx9: Call imx9_probe_mu for DM post in board_r

[Ye Li]

This event callback imx9_probe_mu needs to be called in board_r
as well, because many ELE APIs depending on this MU probed

Signed-off-by: Ye Li 
---
No changes in v2

 arch/arm/mach-imx/imx9/soc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index f06339f..15e87b8 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -622,6 +622,7 @@ int imx9_probe_mu(void)
return 0;
 }
 EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx9_probe_mu);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_R, imx9_probe_mu);
 
 int timer_init(void)
 {
-- 
2.7.4

[PATCH v2 1/2] arm: imx9: Correct imx9_probe_mu prototype

[Ye Li]

Since the event callback imx9_probe_mu is re-defined, update
its prototype.

Signed-off-by: Ye Li 
---
Changes in v2:
 Fix imx93_var_som and phycore_imx93 as well

 arch/arm/include/asm/arch-imx9/mu.h | 2 +-
 board/freescale/imx93_evk/spl.c | 2 +-
 board/phytec/phycore_imx93/spl.c| 2 +-
 board/variscite/imx93_var_som/spl.c | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx9/mu.h 
b/arch/arm/include/asm/arch-imx9/mu.h
index b860499..649b8a6 100644
--- a/arch/arm/include/asm/arch-imx9/mu.h
+++ b/arch/arm/include/asm/arch-imx9/mu.h
@@ -8,6 +8,6 @@
 
 #include 
 
-int imx9_probe_mu(void *ctx, struct event *event);
+int imx9_probe_mu(void);
 
 #endif
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index 2fd5559..7331a20 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -116,7 +116,7 @@ void board_init_f(ulong dummy)
 
preloader_console_init();
 
-   ret = imx9_probe_mu(NULL, NULL);
+   ret = imx9_probe_mu();
if (ret) {
printf("Fail to init Sentinel API\n");
} else {
diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c
index 16303fc..f03bfee 100644
--- a/board/phytec/phycore_imx93/spl.c
+++ b/board/phytec/phycore_imx93/spl.c
@@ -122,7 +122,7 @@ void board_init_f(ulong dummy)
 
preloader_console_init();
 
-   ret = imx9_probe_mu(NULL, NULL);
+   ret = imx9_probe_mu();
if (ret) {
printf("Fail to init ELE API\n");
} else {
diff --git a/board/variscite/imx93_var_som/spl.c 
b/board/variscite/imx93_var_som/spl.c
index 36e1721..71f346c 100644
--- a/board/variscite/imx93_var_som/spl.c
+++ b/board/variscite/imx93_var_som/spl.c
@@ -121,7 +121,7 @@ void board_init_f(ulong dummy)
 
preloader_console_init();
 
-   ret = imx9_probe_mu(NULL, NULL);
+   ret = imx9_probe_mu();
if (ret) {
printf("Fail to init ELE API\n");
} else {
-- 
2.7.4

Re: [PATCH v2] arm: imx9: Correct imx9_probe_mu prototype

[Fabio Estevam]

Hi Ye Li,

On Sun, Mar 31, 2024 at 10:33 PM Ye Li  wrote:
>
> Since the event callback imx9_probe_mu is re-defined, update
> its prototype.
>
> Signed-off-by: Ye Li 
> ---
> Changes in v2:
>  Fix imx93_var_som and phycore_imx93 as well

Thanks for the fix, but please submit it as part of a series along with
[PATCH 2/2] arm: imx9: Call imx9_probe_mu for DM post in board_r
that you have sent previously.

[PATCH v2] arm: imx9: Correct imx9_probe_mu prototype

[Ye Li]

Since the event callback imx9_probe_mu is re-defined, update
its prototype.

Signed-off-by: Ye Li 
---
Changes in v2:
 Fix imx93_var_som and phycore_imx93 as well

 arch/arm/include/asm/arch-imx9/mu.h | 2 +-
 board/freescale/imx93_evk/spl.c | 2 +-
 board/phytec/phycore_imx93/spl.c| 2 +-
 board/variscite/imx93_var_som/spl.c | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx9/mu.h 
b/arch/arm/include/asm/arch-imx9/mu.h
index b860499..649b8a6 100644
--- a/arch/arm/include/asm/arch-imx9/mu.h
+++ b/arch/arm/include/asm/arch-imx9/mu.h
@@ -8,6 +8,6 @@
 
 #include 
 
-int imx9_probe_mu(void *ctx, struct event *event);
+int imx9_probe_mu(void);
 
 #endif
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index 2fd5559..7331a20 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -116,7 +116,7 @@ void board_init_f(ulong dummy)
 
preloader_console_init();
 
-   ret = imx9_probe_mu(NULL, NULL);
+   ret = imx9_probe_mu();
if (ret) {
printf("Fail to init Sentinel API\n");
} else {
diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c
index 16303fc..f03bfee 100644
--- a/board/phytec/phycore_imx93/spl.c
+++ b/board/phytec/phycore_imx93/spl.c
@@ -122,7 +122,7 @@ void board_init_f(ulong dummy)
 
preloader_console_init();
 
-   ret = imx9_probe_mu(NULL, NULL);
+   ret = imx9_probe_mu();
if (ret) {
printf("Fail to init ELE API\n");
} else {
diff --git a/board/variscite/imx93_var_som/spl.c 
b/board/variscite/imx93_var_som/spl.c
index 36e1721..71f346c 100644
--- a/board/variscite/imx93_var_som/spl.c
+++ b/board/variscite/imx93_var_som/spl.c
@@ -121,7 +121,7 @@ void board_init_f(ulong dummy)
 
preloader_console_init();
 
-   ret = imx9_probe_mu(NULL, NULL);
+   ret = imx9_probe_mu();
if (ret) {
printf("Fail to init ELE API\n");
} else {
-- 
2.7.4

Re: [PATCH 28/31] rockchip: rk3399-rock-pi-4: Sync device tree from linux v6.8

[Dragan Simic]

On 2024-04-01 01:41, Jonas Karlman wrote:

On 2024-04-01 01:30, Dragan Simic wrote:

On 2024-04-01 01:14, Jonas Karlman wrote:

On 2024-04-01 00:53, Dragan Simic wrote:

Please see my comments below.

On 2024-03-31 22:28, Jonas Karlman wrote:

Sync rk3399-rock-pi-4 related device tree from linux v6.8.

Add SPI flash related options to support booting from SPI flash.

Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA
boot.


As we know, these boards have no standard connectors for PCI Express
expansion cards, which makes me wonder how many users actually use 
M.2

PCI Express modules with SATA controllers on them with these boards,
and need support for them in U-Boot?

I mean, it can't hurt, but frankly, I'm not 100% sure about it.


With the M.2 Extension Board [1] and a M.2 to PCIe X4 adapter it is
very
easy to convert the M.2 slot into a standard PCIe X4 slot and use it
with a PCIe SATA card. At least that is how I have tested and used
this.


I was aware of the M.2 extension board sold by Radxa, but frankly,
using it together with another adapter (M.2 to standard PCIe x4 slot)
is a cumbersome setup.  The whole thing becomes at least three times
the size of the SBC, with cables and a dangling PCIe card. :)


I know, it is not ideal, but works for my testing and development
proposes :-)

I had in mind an M.2 module with a PCIe SATA controller. [2]  
Something

like that, used together with the M.2 extension board, would actually
make a rather neat setup.


I guess the Radxa Penta SATA HAT [3] is most likely use case for having
PCIe AHCI enabled.


Ah, thanks for reminding me about this hat!  I saw it once or twice,
but I somehow forgot about it.  Yes, that's very nice, and surely a use
case for having AHCI support enabled.


[3] https://radxa.com/products/accessories/penta-sata-hat/

Regards,
Jonas



[2]
https://www.reddit.com/r/selfhosted/comments/s0bf1d/m2_sata_expansion_anyone_use_something_like_this/


I do think there will be many users of PCIe AHCI/SATA, but with this
series I try to get all boards to have same feature set as long as
there
is some way to use a feature.


I guess it can't hurt in the end.


[1] https://radxa.com/products/accessories/m2-extension-board


Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.

Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.

Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.

Remove SPL_TINY_MEMSET=y to use full memset in SPL.

Signed-off-by: Jonas Karlman 


Otherwise, looking good to me.

Reviewed-by: Dragan Simic 


Thanks!

Regards,
Jonas


---
 arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 12 ++
 arch/arm/dts/rk3399-rock-4c-plus.dts |  1 +
 arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 ++
 arch/arm/dts/rk3399-rock-pi-4.dtsi   |  4 +++-
 arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi   |  7 ++
 arch/arm/dts/rk3399-rock-pi-4c.dts   | 10 
 configs/rock-4c-plus-rk3399_defconfig| 24
+++-
 configs/rock-4se-rk3399_defconfig| 23
+--
 configs/rock-pi-4-rk3399_defconfig   |  8 +++
 configs/rock-pi-4c-rk3399_defconfig  | 24
++--
 10 files changed, 114 insertions(+), 11 deletions(-)


[snip]

Re: [PATCH 28/31] rockchip: rk3399-rock-pi-4: Sync device tree from linux v6.8

[Jonas Karlman]

On 2024-04-01 01:30, Dragan Simic wrote:
> On 2024-04-01 01:14, Jonas Karlman wrote:
>> On 2024-04-01 00:53, Dragan Simic wrote:
>>> Please see my comments below.
>>>
>>> On 2024-03-31 22:28, Jonas Karlman wrote:
 Sync rk3399-rock-pi-4 related device tree from linux v6.8.

 Add SPI flash related options to support booting from SPI flash.

 Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA
 boot.
>>>
>>> As we know, these boards have no standard connectors for PCI Express
>>> expansion cards, which makes me wonder how many users actually use M.2
>>> PCI Express modules with SATA controllers on them with these boards,
>>> and need support for them in U-Boot?
>>>
>>> I mean, it can't hurt, but frankly, I'm not 100% sure about it.
>>
>> With the M.2 Extension Board [1] and a M.2 to PCIe X4 adapter it is 
>> very
>> easy to convert the M.2 slot into a standard PCIe X4 slot and use it
>> with a PCIe SATA card. At least that is how I have tested and used 
>> this.
> 
> I was aware of the M.2 extension board sold by Radxa, but frankly,
> using it together with another adapter (M.2 to standard PCIe x4 slot)
> is a cumbersome setup.  The whole thing becomes at least three times
> the size of the SBC, with cables and a dangling PCIe card. :)

I know, it is not ideal, but works for my testing and development
proposes :-)

> 
> I had in mind an M.2 module with a PCIe SATA controller. [2]  Something
> like that, used together with the M.2 extension board, would actually
> make a rather neat setup.

I guess the Radxa Penta SATA HAT [3] is most likely use case for having
PCIe AHCI enabled.

[3] https://radxa.com/products/accessories/penta-sata-hat/

Regards,
Jonas

> 
> [2] 
> https://www.reddit.com/r/selfhosted/comments/s0bf1d/m2_sata_expansion_anyone_use_something_like_this/
> 
>> I do think there will be many users of PCIe AHCI/SATA, but with this
>> series I try to get all boards to have same feature set as long as 
>> there
>> is some way to use a feature.
> 
> I guess it can't hurt in the end.
> 
>> [1] https://radxa.com/products/accessories/m2-extension-board
>>
 Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.

 Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.

 Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.

 Remove SPL_TINY_MEMSET=y to use full memset in SPL.

 Signed-off-by: Jonas Karlman 
>>>
>>> Otherwise, looking good to me.
>>>
>>> Reviewed-by: Dragan Simic 
>>
>> Thanks!
>>
>> Regards,
>> Jonas
>>
 ---
  arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 12 ++
  arch/arm/dts/rk3399-rock-4c-plus.dts |  1 +
  arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 ++
  arch/arm/dts/rk3399-rock-pi-4.dtsi   |  4 +++-
  arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi   |  7 ++
  arch/arm/dts/rk3399-rock-pi-4c.dts   | 10 
  configs/rock-4c-plus-rk3399_defconfig| 24 
 +++-
  configs/rock-4se-rk3399_defconfig| 23 
 +--
  configs/rock-pi-4-rk3399_defconfig   |  8 +++
  configs/rock-pi-4c-rk3399_defconfig  | 24 
 ++--
  10 files changed, 114 insertions(+), 11 deletions(-)

>> [snip]

Re: [PATCH 28/31] rockchip: rk3399-rock-pi-4: Sync device tree from linux v6.8

[Dragan Simic]

On 2024-04-01 01:14, Jonas Karlman wrote:

On 2024-04-01 00:53, Dragan Simic wrote:

Please see my comments below.

On 2024-03-31 22:28, Jonas Karlman wrote:

Sync rk3399-rock-pi-4 related device tree from linux v6.8.

Add SPI flash related options to support booting from SPI flash.

Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA
boot.


As we know, these boards have no standard connectors for PCI Express
expansion cards, which makes me wonder how many users actually use M.2
PCI Express modules with SATA controllers on them with these boards,
and need support for them in U-Boot?

I mean, it can't hurt, but frankly, I'm not 100% sure about it.


With the M.2 Extension Board [1] and a M.2 to PCIe X4 adapter it is 
very

easy to convert the M.2 slot into a standard PCIe X4 slot and use it
with a PCIe SATA card. At least that is how I have tested and used 
this.


I was aware of the M.2 extension board sold by Radxa, but frankly,
using it together with another adapter (M.2 to standard PCIe x4 slot)
is a cumbersome setup.  The whole thing becomes at least three times
the size of the SBC, with cables and a dangling PCIe card. :)

I had in mind an M.2 module with a PCIe SATA controller. [2]  Something
like that, used together with the M.2 extension board, would actually
make a rather neat setup.

[2] 
https://www.reddit.com/r/selfhosted/comments/s0bf1d/m2_sata_expansion_anyone_use_something_like_this/



I do think there will be many users of PCIe AHCI/SATA, but with this
series I try to get all boards to have same feature set as long as 
there

is some way to use a feature.


I guess it can't hurt in the end.


[1] https://radxa.com/products/accessories/m2-extension-board


Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.

Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.

Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.

Remove SPL_TINY_MEMSET=y to use full memset in SPL.

Signed-off-by: Jonas Karlman 


Otherwise, looking good to me.

Reviewed-by: Dragan Simic 


Thanks!

Regards,
Jonas


---
 arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 12 ++
 arch/arm/dts/rk3399-rock-4c-plus.dts |  1 +
 arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 ++
 arch/arm/dts/rk3399-rock-pi-4.dtsi   |  4 +++-
 arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi   |  7 ++
 arch/arm/dts/rk3399-rock-pi-4c.dts   | 10 
 configs/rock-4c-plus-rk3399_defconfig| 24 
+++-
 configs/rock-4se-rk3399_defconfig| 23 
+--

 configs/rock-pi-4-rk3399_defconfig   |  8 +++
 configs/rock-pi-4c-rk3399_defconfig  | 24 
++--

 10 files changed, 114 insertions(+), 11 deletions(-)


[snip]

Re: [PATCH 28/31] rockchip: rk3399-rock-pi-4: Sync device tree from linux v6.8

[Jonas Karlman]

Hi Dragan,

On 2024-04-01 00:53, Dragan Simic wrote:
> Hello Jonas,
> 
> Please see my comments below.
> 
> On 2024-03-31 22:28, Jonas Karlman wrote:
>> Sync rk3399-rock-pi-4 related device tree from linux v6.8.
>>
>> Add SPI flash related options to support booting from SPI flash.
>>
>> Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA 
>> boot.
> 
> As we know, these boards have no standard connectors for PCI Express
> expansion cards, which makes me wonder how many users actually use M.2
> PCI Express modules with SATA controllers on them with these boards,
> and need support for them in U-Boot?
> 
> I mean, it can't hurt, but frankly, I'm not 100% sure about it.

With the M.2 Extension Board [1] and a M.2 to PCIe X4 adapter it is very
easy to convert the M.2 slot into a standard PCIe X4 slot and use it
with a PCIe SATA card. At least that is how I have tested and used this.

I do think there will be many users of PCIe AHCI/SATA, but with this
series I try to get all boards to have same feature set as long as there
is some way to use a feature.

[1] https://radxa.com/products/accessories/m2-extension-board

> 
>> Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.
>>
>> Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
>>
>> Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
>>
>> Remove SPL_TINY_MEMSET=y to use full memset in SPL.
>>
>> Signed-off-by: Jonas Karlman 
> 
> Otherwise, looking good to me.
> 
> Reviewed-by: Dragan Simic 

Thanks!

Regards,
Jonas

> 
>> ---
>>  arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 12 ++
>>  arch/arm/dts/rk3399-rock-4c-plus.dts |  1 +
>>  arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 ++
>>  arch/arm/dts/rk3399-rock-pi-4.dtsi   |  4 +++-
>>  arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi   |  7 ++
>>  arch/arm/dts/rk3399-rock-pi-4c.dts   | 10 
>>  configs/rock-4c-plus-rk3399_defconfig| 24 +++-
>>  configs/rock-4se-rk3399_defconfig| 23 +--
>>  configs/rock-pi-4-rk3399_defconfig   |  8 +++
>>  configs/rock-pi-4c-rk3399_defconfig  | 24 ++--
>>  10 files changed, 114 insertions(+), 11 deletions(-)
>>
[snip]

Re: [PATCH 28/31] rockchip: rk3399-rock-pi-4: Sync device tree from linux v6.8

[Dragan Simic]

Hello Jonas,

Please see my comments below.

On 2024-03-31 22:28, Jonas Karlman wrote:

Sync rk3399-rock-pi-4 related device tree from linux v6.8.

Add SPI flash related options to support booting from SPI flash.

Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA 
boot.


As we know, these boards have no standard connectors for PCI Express
expansion cards, which makes me wonder how many users actually use M.2
PCI Express modules with SATA controllers on them with these boards,
and need support for them in U-Boot?

I mean, it can't hurt, but frankly, I'm not 100% sure about it.


Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.

Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.

Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.

Remove SPL_TINY_MEMSET=y to use full memset in SPL.

Signed-off-by: Jonas Karlman 


Otherwise, looking good to me.

Reviewed-by: Dragan Simic 


---
 arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 12 ++
 arch/arm/dts/rk3399-rock-4c-plus.dts |  1 +
 arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 ++
 arch/arm/dts/rk3399-rock-pi-4.dtsi   |  4 +++-
 arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi   |  7 ++
 arch/arm/dts/rk3399-rock-pi-4c.dts   | 10 
 configs/rock-4c-plus-rk3399_defconfig| 24 +++-
 configs/rock-4se-rk3399_defconfig| 23 +--
 configs/rock-pi-4-rk3399_defconfig   |  8 +++
 configs/rock-pi-4c-rk3399_defconfig  | 24 ++--
 10 files changed, 114 insertions(+), 11 deletions(-)

diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
index 9785b97b9eea..b5ee644a83dd 100644
--- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
@@ -11,3 +11,15 @@
 _pull_up_8ma {
bootph-pre-ram;
 };
+
+ {
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   bootph-some-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <1000>;
+   };
+};
diff --git a/arch/arm/dts/rk3399-rock-4c-plus.dts
b/arch/arm/dts/rk3399-rock-4c-plus.dts
index 8bfd5f88d1ef..7baf9d1b22fd 100644
--- a/arch/arm/dts/rk3399-rock-4c-plus.dts
+++ b/arch/arm/dts/rk3399-rock-4c-plus.dts
@@ -15,6 +15,7 @@
compatible = "radxa,rock-4c-plus", "rockchip,rk3399";

aliases {
+   ethernet0 = 
mmc0 = 
mmc1 = 
};
diff --git a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
index 85ee5770add0..2213d0093052 100644
--- a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
@@ -4,3 +4,15 @@
  */

 #include "rk3399-rock-pi-4-u-boot.dtsi"
+
+ {
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   bootph-some-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <1000>;
+   };
+};
diff --git a/arch/arm/dts/rk3399-rock-pi-4.dtsi
b/arch/arm/dts/rk3399-rock-pi-4.dtsi
index b1b7f4ffb1d4..281a12180703 100644
--- a/arch/arm/dts/rk3399-rock-pi-4.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4.dtsi
@@ -12,6 +12,7 @@

 / {
aliases {
+   ethernet0 = 
mmc0 = 
mmc1 = 
};
@@ -44,7 +45,7 @@
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = < 1>;
-   clock-names = "ext_clock";
+   clock-names = "lpo";
pinctrl-names = "default";
pinctrl-0 = <_enable_h>;
reset-gpios = < RK_PB2 GPIO_ACTIVE_LOW>;
@@ -492,6 +493,7 @@

  {
pinctrl-0 = <_2ch_bus>;
+   pinctrl-1 = <_2ch_bus_bclk_off>;
rockchip,capture-channels = <2>;
rockchip,playback-channels = <2>;
status = "okay";
diff --git a/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi
b/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi
index 85ee5770add0..38385621deb1 100644
--- a/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi
@@ -4,3 +4,10 @@
  */

 #include "rk3399-rock-pi-4-u-boot.dtsi"
+
+ {
+   flash@0 {
+   bootph-pre-ram;
+   bootph-some-ram;
+   };
+};
diff --git a/arch/arm/dts/rk3399-rock-pi-4c.dts
b/arch/arm/dts/rk3399-rock-pi-4c.dts
index d32efab74e94..de2ebe4cb4f3 100644
--- a/arch/arm/dts/rk3399-rock-pi-4c.dts
+++ b/arch/arm/dts/rk3399-rock-pi-4c.dts
@@ -43,6 +43,16 @@
hp-det-gpio = < RK_PA0 GPIO_ACTIVE_HIGH>;
 };

+ {
+   status = "okay";
+
+   flash@0 {
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <1000>;
+   };
+};
+
  {
status = "okay";

diff --git a/configs/rock-4c-plus-rk3399_defconfig

Re: [PATCH 31/31] rockchip: rk3399-pinephone-pro: Sync device tree from linux v6.8

[Dragan Simic]

On 2024-03-31 22:28, Jonas Karlman wrote:

Sync rk3399-pinephone-pro device tree from linux v6.8.

Add SPI flash related node and options to support booting from SPI 
flash.


Remove REGULATOR_PWM=y, board does not use pwm-regulator compatible.

Add SYS_NS16550_MEM32=y to use readl/writel for serial console.

Remove SPL_TINY_MEMSET=y to use full memset in SPL.

Signed-off-by: Jonas Karlman 


Looking good to me.

Reviewed-by: Dragan Simic 


---
 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi |  12 ++
 arch/arm/dts/rk3399-pinephone-pro.dts | 147 ++
 configs/pinephone-pro-rk3399_defconfig|   8 +-
 3 files changed, 163 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
index dcfcec4f3072..6a248691e29d 100644
--- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
@@ -13,3 +13,15 @@
  {
max-frequency = <2000>;
 };
+
+ {
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   bootph-some-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <1000>;
+   };
+};
diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts
b/arch/arm/dts/rk3399-pinephone-pro.dts
index 04403a76238b..61f3fec5a8b1 100644
--- a/arch/arm/dts/rk3399-pinephone-pro.dts
+++ b/arch/arm/dts/rk3399-pinephone-pro.dts
@@ -10,6 +10,7 @@
  */

 /dts-v1/;
+#include 
 #include 
 #include "rk3399.dtsi"
 #include "rk3399-opp.dtsi"
@@ -29,6 +30,31 @@
stdout-path = "serial2:115200n8";
};

+   adc-keys {
+   compatible = "adc-keys";
+   io-channels = < 1>;
+   io-channel-names = "buttons";
+   keyup-threshold-microvolt = <160>;
+   poll-interval = <100>;
+
+   button-up {
+   label = "Volume Up";
+   linux,code = ;
+   press-threshold-microvolt = <10>;
+   };
+
+   button-down {
+   label = "Volume Down";
+   linux,code = ;
+   press-threshold-microvolt = <60>;
+   };
+   };
+
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   pwms = < 0 5 0>;
+   };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -102,6 +128,37 @@
/* WL_REG_ON on module */
reset-gpios = < RK_PB2 GPIO_ACTIVE_LOW>;
};
+
+   /* MIPI DSI panel 1.8v supply */
+   vcc1v8_lcd: vcc1v8-lcd {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   regulator-name = "vcc1v8_lcd";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   vin-supply = <_sys>;
+   gpio = < RK_PA5 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   };
+
+   /* MIPI DSI panel 2.8v supply */
+   vcc2v8_lcd: vcc2v8-lcd {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   regulator-name = "vcc2v8_lcd";
+   regulator-min-microvolt = <280>;
+   regulator-max-microvolt = <280>;
+   vin-supply = <_sys>;
+   gpio = < RK_PA1 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   };
+};
+
+_alert0 {
+   temperature = <65000>;
+};
+_alert1 {
+   temperature = <68000>;
 };

 _l0 {
@@ -132,6 +189,11 @@
status = "okay";
 };

+ {
+   mali-supply = <_gpu>;
+   status = "okay";
+};
+
  {
clock-frequency = <40>;
i2c-scl-rising-time-ns = <168>;
@@ -326,6 +388,25 @@
};
 };

+ {
+   i2c-scl-rising-time-ns = <450>;
+   i2c-scl-falling-time-ns = <15>;
+   status = "okay";
+
+   touchscreen@14 {
+   compatible = "goodix,gt1158";
+   reg = <0x14>;
+   interrupt-parent = <>;
+   interrupts = ;
+   irq-gpios = < RK_PB5 GPIO_ACTIVE_HIGH>;
+   reset-gpios = < RK_PB4 GPIO_ACTIVE_HIGH>;
+   AVDD28-supply = <_touch>;
+   VDDIO-supply = <_touch>;
+   touchscreen-size-x = <720>;
+   touchscreen-size-y = <1440>;
+   };
+};
+
 _opp {
opp04 {
status = "disabled";
@@ -355,6 +436,39 @@
status = "okay";
 };

+_dsi {
+   status = "okay";
+   clock-master;
+
+   ports {
+   mipi_out: port@1 {
+   #address-cells = <0>;
+   #size-cells = <0>;
+   reg = <1>;
+
+   mipi_out_panel: endpoint {
+   remote-endpoint = <_in_panel>;
+   };
+

Re: [PATCH 30/31] rockchip: rk3399-pinebook-pro: Sync device tree from linux v6.8

[Dragan Simic]

On 2024-03-31 22:28, Jonas Karlman wrote:

Sync rk3399-pinebook-pro device tree from linux v6.8.

Add SF_DEFAULT_SPEED=1000 and SPI_FLASH_SFDP_SUPPORT=y to improve
support for booting from SPI flash.

Add CMD_POWEROFF=y to support poweroff using cmdline and power on using
the pwr button on the board.

Remove SPL_TINY_MEMSET=y to use full memset in SPL.

Signed-off-by: Jonas Karlman 


Looking good to me.

Reviewed-by: Dragan Simic 


---
 arch/arm/dts/rk3399-pinebook-pro.dts  | 24 +++-
 configs/pinebook-pro-rk3399_defconfig |  6 --
 2 files changed, 11 insertions(+), 19 deletions(-)

diff --git a/arch/arm/dts/rk3399-pinebook-pro.dts
b/arch/arm/dts/rk3399-pinebook-pro.dts
index d6b68d77d63a..054c6a4d1a45 100644
--- a/arch/arm/dts/rk3399-pinebook-pro.dts
+++ b/arch/arm/dts/rk3399-pinebook-pro.dts
@@ -50,19 +50,9 @@
pinctrl-0 = <_en_pin>;
power-supply = <_panel>;

-   ports {
-   #address-cells = <1>;
-   #size-cells = <0>;
-
-   port@0 {
-   reg = <0>;
-   #address-cells = <1>;
-   #size-cells = <0>;
-
-   panel_in_edp: endpoint@0 {
-   reg = <0>;
-   remote-endpoint = <_out_panel>;
-   };
+   port {
+   panel_in_edp: endpoint {
+   remote-endpoint = <_out_panel>;
};
};
};
@@ -76,7 +66,7 @@
pinctrl-names = "default";
pinctrl-0 = <_pin>;

-   lid {
+   switch-lid {
debounce-interval = <20>;
gpios = < RK_PA1 GPIO_ACTIVE_LOW>;
label = "Lid";
@@ -92,7 +82,7 @@
pinctrl-names = "default";
pinctrl-0 = <_pin>;

-   power {
+   key-power {
debounce-interval = <20>;
gpios = < RK_PA5 GPIO_ACTIVE_LOW>;
label = "Power";
@@ -675,7 +665,7 @@
i2c-scl-rising-time-ns = <168>;
status = "okay";

-   es8316: es8316@11 {
+   es8316: audio-codec@11 {
compatible = "everest,es8316";
reg = <0x11>;
clocks = < SCLK_I2S_8CH_OUT>;
@@ -943,7 +933,7 @@
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <_clk _cmd _bus4>;
-   sd-uhs-sdr104;
+   sd-uhs-sdr50;
vmmc-supply = <_sd>;
vqmmc-supply = <_sdio>;
status = "okay";
diff --git a/configs/pinebook-pro-rk3399_defconfig
b/configs/pinebook-pro-rk3399_defconfig
index dd8bc2b72cc3..8ac6ddd49dea 100644
--- a/configs/pinebook-pro-rk3399_defconfig
+++ b/configs/pinebook-pro-rk3399_defconfig
@@ -4,7 +4,7 @@ CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SPL_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_SF_DEFAULT_SPEED=2000
+CONFIG_SF_DEFAULT_SPEED=1000
 CONFIG_ENV_SIZE=0x8000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro"
@@ -36,6 +36,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
@@ -64,7 +65,9 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_NVME_PCI=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -98,5 +101,4 @@ CONFIG_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_DISPLAY_ROCKCHIP_EDP=y
-CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y

Re: [PATCH 29/31] rockchip: rk3399-rockpro64: Sync device tree from linux v6.8

[Dragan Simic]

On 2024-03-31 22:28, Jonas Karlman wrote:

Sync rk3399-rockpro64 device tree from linux v6.8.

Add SF_DEFAULT_SPEED=1000 and SPI_FLASH_SFDP_SUPPORT=y to improve
support for booting from SPI flash.

Remove USE_PREBOOT=y to speed up booting, standard boot will init USB
after faster boot media has been evaluated.

Add CMD_POWEROFF=y to support poweroff using cmdline and power on using
the pwr button on the board.

Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.

Remove SPL_TINY_MEMSET=y to use full memset in SPL.

Signed-off-by: Jonas Karlman 


Looking good to me.  Thank you for all these nice cleanups!

Reviewed-by: Dragan Simic 


---
 arch/arm/dts/rk3399-rockpro64.dtsi | 98 --
 configs/rockpro64-rk3399_defconfig |  7 ++-
 2 files changed, 97 insertions(+), 8 deletions(-)

diff --git a/arch/arm/dts/rk3399-rockpro64.dtsi
b/arch/arm/dts/rk3399-rockpro64.dtsi
index 6bff8db7d33e..f30b82a10ca3 100644
--- a/arch/arm/dts/rk3399-rockpro64.dtsi
+++ b/arch/arm/dts/rk3399-rockpro64.dtsi
@@ -11,6 +11,7 @@

 / {
aliases {
+   ethernet0 = 
mmc0 = 
mmc1 = 
mmc2 = 
@@ -20,6 +21,15 @@
stdout-path = "serial2:150n8";
};

+   /* enable for panel backlight support */
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   brightness-levels = <0 4 8 16 32 64 128 255>;
+   default-brightness-level = <5>;
+   pwms = < 0 100 0>;
+   status = "disabled";
+   };
+
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <12500>;
@@ -33,7 +43,7 @@
pinctrl-names = "default";
pinctrl-0 = <>;

-   power {
+   key-power {
debounce-interval = <100>;
gpios = < RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
@@ -69,6 +79,7 @@

fan: pwm-fan {
compatible = "pwm-fan";
+   cooling-levels = <0 100 150 200 255>;
#cooling-cells = <2>;
fan-supply = <_dcin>;
pwms = < 0 5 0>;
@@ -106,6 +117,14 @@
};
};

+   avdd: avdd-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "avdd";
+   regulator-min-microvolt = <1100>;
+   regulator-max-microvolt = <1100>;
+   vin-supply = <_s0>;
+   };
+
vcc12v_dcin: vcc12v-dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
@@ -212,12 +231,12 @@
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = < 0 25000 1>;
+   pwm-supply = <_sys>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <80>;
regulator-max-microvolt = <170>;
-   vin-supply = <_sys>;
};
 };

@@ -245,6 +264,34 @@
cpu-supply = <_cpu_b>;
 };

+_thermal {
+   trips {
+   cpu_warm: cpu_warm {
+   temperature = <55000>;
+   hysteresis = <2000>;
+   type = "active";
+   };
+
+   cpu_hot: cpu_hot {
+   temperature = <65000>;
+   hysteresis = <2000>;
+   type = "active";
+   };
+   };
+
+   cooling-maps {
+   map2 {
+   trip = <_warm>;
+   cooling-device = < THERMAL_NO_LIMIT 1>;
+   };
+
+   map3 {
+   trip = <_hot>;
+   cooling-device = < 2 THERMAL_NO_LIMIT>;
+   };
+   };
+};
+
 _phy {
status = "okay";
 };
@@ -371,8 +418,6 @@

vcc3v0_touch: LDO_REG2 {
regulator-name = "vcc3v0_touch";
-   regulator-always-on;
-   regulator-boot-on;
regulator-min-microvolt = <300>;
regulator-max-microvolt = <300>;
regulator-state-mem {
@@ -461,8 +506,6 @@

vcc3v3_s0: SWITCH_REG2 {
regulator-name = "vcc3v3_s0";
-   regulator-always-on;
-   regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
@@ -536,6 +579,19 @@
vbus-supply = <_typec>;
status = "okay";
};
+
+   /* enable for pine64 touch screen 

[PATCH 9/9] mcheck: let mcheck_abortfunc_t print the pointer

[Eugene Uriev]

Signed-off-by: Eugene Uriev 

---

 common/mcheck_core.inc.h | 16 
 include/mcheck.h |  2 +-
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/common/mcheck_core.inc.h b/common/mcheck_core.inc.h
index 2f11ac567f..6902140992 100644
--- a/common/mcheck_core.inc.h
+++ b/common/mcheck_core.inc.h
@@ -90,7 +90,7 @@ struct mcheck_hdr {
mcheck_canary canary; /* Magic number to check header integrity.  */
 };
 
-static void mcheck_default_abort(enum mcheck_status status)
+static void mcheck_default_abort(enum mcheck_status status, const void *p)
 {
const char *msg;
 
@@ -111,7 +111,7 @@ static void mcheck_default_abort(enum mcheck_status status)
msg = "bogus mcheck_status, library is buggy\n";
break;
}
-   printf("\n\nmcheck: %s!!! [%zu]\n\n", msg, mcheck_chunk_count_max);
+   printf("\n\nmcheck: %p:%s!!! [%zu]\n\n", p, msg, 
mcheck_chunk_count_max);
 }
 
 static mcheck_abortfunc_t mcheck_abortfunc = _default_abort;
@@ -124,9 +124,9 @@ static inline size_t allign_size_up(size_t sz, size_t grain)
 #define mcheck_allign_customer_size(SZ) allign_size_up(SZ, sizeof(mcheck_elem))
 #define mcheck_evaluate_memalign_prefix_size(ALIGN) 
allign_size_up(sizeof(struct mcheck_hdr), ALIGN)
 
-static enum mcheck_status mcheck_OnNok(enum mcheck_status status)
+static enum mcheck_status mcheck_OnNok(enum mcheck_status status, const void 
*p)
 {
-   (*mcheck_abortfunc)(status);
+   (*mcheck_abortfunc)(status, p);
return status;
 }
 
@@ -136,11 +136,11 @@ static enum mcheck_status mcheck_checkhdr(const struct 
mcheck_hdr *hdr)
 
for (i = 0; i < CANARY_DEPTH; ++i)
if (hdr->canary.elems[i] == MAGICFREE)
-   return mcheck_OnNok(MCHECK_FREE);
+   return mcheck_OnNok(MCHECK_FREE, hdr + 1);
 
for (i = 0; i < CANARY_DEPTH; ++i)
if (hdr->canary.elems[i] != MAGICWORD)
-   return mcheck_OnNok(MCHECK_HEAD);
+   return mcheck_OnNok(MCHECK_HEAD, hdr + 1);
 
const size_t payload_size = hdr->size;
const size_t payload_size_aligned = 
mcheck_allign_customer_size(payload_size);
@@ -150,13 +150,13 @@ static enum mcheck_status mcheck_checkhdr(const struct 
mcheck_hdr *hdr)
 
for (i = 0; i < padd_size; ++i)
if (payload[payload_size + i] != PADDINGFLOOD)
-   return mcheck_OnNok(MCHECK_TAIL);
+   return mcheck_OnNok(MCHECK_TAIL, hdr + 1);
 
const mcheck_canary *tail = (const mcheck_canary 
*)[payload_size_aligned];
 
for (i = 0; i < CANARY_DEPTH; ++i)
if (tail->elems[i] != MAGICTAIL)
-   return mcheck_OnNok(MCHECK_TAIL);
+   return mcheck_OnNok(MCHECK_TAIL, hdr + 1);
return MCHECK_OK;
 }
 
diff --git a/include/mcheck.h b/include/mcheck.h
index f4c9b7e61c..bd506ae629 100644
--- a/include/mcheck.h
+++ b/include/mcheck.h
@@ -29,7 +29,7 @@ enum mcheck_status {
MCHECK_TAIL   /* Memory after the block was clobbered.  
*/
 };
 
-typedef void (*mcheck_abortfunc_t)(enum mcheck_status);
+typedef void (*mcheck_abortfunc_t)(enum mcheck_status, const void *p);
 
 int mcheck(mcheck_abortfunc_t func);
 
-- 
2.25.1

[PATCH 8/9] mcheck: add stats, add a comment with test results

[Eugene Uriev]

My tests have been run on an U-Boot (of older version)
for ARM (64bits).

Signed-off-by: Eugene Uriev 
---

 common/mcheck_core.inc.h | 18 +-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/common/mcheck_core.inc.h b/common/mcheck_core.inc.h
index bade03598f..2f11ac567f 100644
--- a/common/mcheck_core.inc.h
+++ b/common/mcheck_core.inc.h
@@ -48,6 +48,13 @@
  * rather in compile-time, by MCHECK_HEAP_PROTECTION macro. That guarantees 
that
  * we haven't missed first malloc.
  */
+
+/*
+ * Testing
+ *  This library had been successfully tested for U-Boot @ ARM SoC chip / 
64bits.
+ *  Proven for both default and pedantic mode: confirms U-Boot to be clean, 
and catches
+ *  intentional/testing corruptions. Working with malloc_trim is not tested.
+ */
 #ifndef _MCHECKCORE_INC_H
 #define _MCHECKCORE_INC_H  1
 #include "mcheck.h"
@@ -70,6 +77,8 @@
 // avoid problems with BSS at early stage:
 static char mcheck_pedantic_flag __section(".data") = 0;
 static void *mcheck_registry[REGISTRY_SZ] __section(".data") = {0};
+static size_t mcheck_chunk_count __section(".data") = 0;
+static size_t mcheck_chunk_count_max __section(".data") = 0;
 
 typedef unsigned long long mcheck_elem;
 typedef struct {
@@ -102,7 +111,7 @@ static void mcheck_default_abort(enum mcheck_status status)
msg = "bogus mcheck_status, library is buggy\n";
break;
}
-   printf("\n\nmcheck: %s!!!\n\n", msg);
+   printf("\n\nmcheck: %s!!! [%zu]\n\n", msg, mcheck_chunk_count_max);
 }
 
 static mcheck_abortfunc_t mcheck_abortfunc = _default_abort;
@@ -173,6 +182,7 @@ static void *mcheck_free_helper(void *ptr, int 
clean_content)
break;
}
 
+   --mcheck_chunk_count;
return (char *)hdr - hdr->aln_skip;
 }
 
@@ -212,6 +222,10 @@ static void *mcheck_allocated_helper(void 
*altoghether_ptr, size_t customer_sz,
for (i = 0; i < CANARY_DEPTH; ++i)
tail->elems[i] = MAGICTAIL;
 
+   ++mcheck_chunk_count;
+   if (mcheck_chunk_count > mcheck_chunk_count_max)
+   mcheck_chunk_count_max = mcheck_chunk_count;
+
for (i = 0; i < REGISTRY_SZ; ++i)
if (!mcheck_registry[i]) {
mcheck_registry[i] = hdr;
@@ -283,6 +297,8 @@ void mcheck_on_ramrelocation(size_t offset)
printf("mcheck, WRN: forgetting %p chunk\n", p);
mcheck_registry[i] = 0;
}
+
+   mcheck_chunk_count = 0;
 }
 #endif
 #endif
-- 
2.25.1

[PATCH 7/9] mcheck: introduce mcheck_on_ramrelocation(.)

[Eugene Uriev]

The using of pre-reloc/malloc_simple heap is
too hard to follow after the relocation.

So lets drop it from the pedantic registry
and switch to dlmalloc, when moved.

The offset is ignored, but kept in the API
for the probable case, when that early
heap is relocated too.

Signed-off-by: Eugene Uriev 
---

 common/board_f.c |  4 
 common/mcheck_core.inc.h | 11 +++
 2 files changed, 15 insertions(+)

diff --git a/common/board_f.c b/common/board_f.c
index 442b8349d0..ca4d5291a9 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -719,6 +719,7 @@ static int reloc_bloblist(void)
return 0;
 }
 
+void mcheck_on_ramrelocation(size_t offset);
 static int setup_reloc(void)
 {
if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
@@ -744,6 +745,9 @@ static int setup_reloc(void)
if (gd->flags & GD_FLG_SKIP_RELOC) {
debug("Skipping relocation due to flag\n");
} else {
+#ifdef MCHECK_HEAP_PROTECTION
+   mcheck_on_ramrelocation(gd->reloc_off);
+#endif
debug("Relocation Offset is: %08lx\n", gd->reloc_off);
debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
  gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
diff --git a/common/mcheck_core.inc.h b/common/mcheck_core.inc.h
index 85a34de295..bade03598f 100644
--- a/common/mcheck_core.inc.h
+++ b/common/mcheck_core.inc.h
@@ -273,5 +273,16 @@ static void mcheck_initialize(mcheck_abortfunc_t new_func, 
char pedantic_flag)
mcheck_pedantic_flag = pedantic_flag;
 }
 
+void mcheck_on_ramrelocation(size_t offset)
+{
+   char *p;
+   int i;
+   // Simple, but inaccurate strategy: drop the pre-reloc heap
+   for (i = 0; i < REGISTRY_SZ; ++i)
+   if ((p = mcheck_registry[i]) != NULL ) {
+   printf("mcheck, WRN: forgetting %p chunk\n", p);
+   mcheck_registry[i] = 0;
+   }
+}
 #endif
 #endif
-- 
2.25.1

[PATCH 6/9] mcheck: add pedantic mode support

[Eugene Uriev]

The pedantic mode is run-time contolled, so
appropriate registry take place everytime.

Maybe it's worth to use compile-time control only.
So, the registry could be optimized out by an #ifdef.

Signed-off-by: Eugene Uriev 
---

 common/dlmalloc.c| 12 
 common/mcheck_core.inc.h | 41 
 include/mcheck.h |  9 +
 3 files changed, 62 insertions(+)

diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 73c04af2a3..a0616217d4 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -2233,6 +2233,7 @@ void cfree(mem) Void_t *mem;
 
 Void_t *mALLOc(size_t bytes)
 {
+   mcheck_pedantic_prehook();
size_t fullsz = mcheck_alloc_prehook(bytes);
void *p = mALLOc_impl(fullsz);
 
@@ -2245,6 +2246,7 @@ void fREe(Void_t *mem) { 
fREe_impl(mcheck_free_prehook(mem)); }
 
 Void_t *rEALLOc(Void_t *oldmem, size_t bytes)
 {
+   mcheck_pedantic_prehook();
if (bytes == 0) {
if (oldmem)
fREe(oldmem);
@@ -2265,6 +2267,7 @@ Void_t *rEALLOc(Void_t *oldmem, size_t bytes)
 
 Void_t *mEMALIGn(size_t alignment, size_t bytes)
 {
+   mcheck_pedantic_prehook();
size_t fullsz = mcheck_memalign_prehook(alignment, bytes);
void *p = mEMALIGn_impl(alignment, fullsz);
 
@@ -2277,6 +2280,7 @@ Void_t *mEMALIGn(size_t alignment, size_t bytes)
 
 Void_t *cALLOc(size_t n, size_t elem_size)
 {
+   mcheck_pedantic_prehook();
// NB: here is no overflow check.
size_t fullsz = mcheck_alloc_prehook(n * elem_size);
void *p = cALLOc_impl(1, fullsz);
@@ -2287,12 +2291,20 @@ Void_t *cALLOc(size_t n, size_t elem_size)
 }
 
 // mcheck API {
+int mcheck_pedantic(mcheck_abortfunc_t f)
+{
+   mcheck_initialize(f, 1);
+   return 0;
+}
+
 int mcheck(mcheck_abortfunc_t f)
 {
mcheck_initialize(f, 0);
return 0;
 }
 
+void mcheck_check_all(void) { mcheck_pedantic_check(); }
+
 enum mcheck_status mprobe(void *__ptr) { return mcheck_mprobe(__ptr); }
 // mcheck API }
 #endif
diff --git a/common/mcheck_core.inc.h b/common/mcheck_core.inc.h
index b038bb0539..85a34de295 100644
--- a/common/mcheck_core.inc.h
+++ b/common/mcheck_core.inc.h
@@ -30,6 +30,8 @@
  * Unlike glibc-clients, U-Boot has limited malloc-usage, and only one thread.
  * So it's better to make the protection heavier.
  * Thus overflow canary here is greater, than glibc's one. Underflow canary is 
bigger too.
+ * U-Boot also allows to use fixed-size heap-registry, instead of 
double-linked list in glibc.
+ *
  * Heavy canary allows to catch not only memset(..)-errors,
  * but overflow/underflow of struct-array access:
  * {
@@ -61,8 +63,14 @@
 #define FREEFLOOD  ((char)0xf5)
 #define PADDINGFLOOD   ((char)0x58)
 
+// my normal run demands 4427-6449 chunks:
+#define REGISTRY_SZ6608
 #define CANARY_DEPTH   2
 
+// avoid problems with BSS at early stage:
+static char mcheck_pedantic_flag __section(".data") = 0;
+static void *mcheck_registry[REGISTRY_SZ] __section(".data") = {0};
+
 typedef unsigned long long mcheck_elem;
 typedef struct {
mcheck_elem elems[CANARY_DEPTH];
@@ -159,6 +167,12 @@ static void *mcheck_free_helper(void *ptr, int 
clean_content)
if (clean_content)
mcheck_flood(ptr, FREEFLOOD, 
mcheck_allign_customer_size(hdr->size));
 
+   for (i = 0; i < REGISTRY_SZ; ++i)
+   if (mcheck_registry[i] == hdr) {
+   mcheck_registry[i] = 0;
+   break;
+   }
+
return (char *)hdr - hdr->aln_skip;
 }
 
@@ -197,6 +211,17 @@ static void *mcheck_allocated_helper(void 
*altoghether_ptr, size_t customer_sz,
 
for (i = 0; i < CANARY_DEPTH; ++i)
tail->elems[i] = MAGICTAIL;
+
+   for (i = 0; i < REGISTRY_SZ; ++i)
+   if (!mcheck_registry[i]) {
+   mcheck_registry[i] = hdr;
+   return payload; // normal end
+   }
+
+   static char *overflow_msg = "\n\n\nERROR: mcheck registry overflow, 
pedantic check would be incomplete!!\n\n\n\n";
+
+   printf("%s", overflow_msg);
+   overflow_msg = "(mcheck registry full)";
return payload;
 }
 
@@ -227,9 +252,25 @@ static enum mcheck_status mcheck_mprobe(void *ptr)
return mcheck_checkhdr(hdr);
 }
 
+static void mcheck_pedantic_check(void)
+{
+   int i;
+
+   for (i = 0; i < REGISTRY_SZ; ++i)
+   if (mcheck_registry[i])
+   mcheck_checkhdr(mcheck_registry[i]);
+}
+
+static void mcheck_pedantic_prehook(void)
+{
+   if (mcheck_pedantic_flag)
+   mcheck_pedantic_check();
+}
+
 static void mcheck_initialize(mcheck_abortfunc_t new_func, char pedantic_flag)
 {
mcheck_abortfunc = (new_func) ? new_func : _default_abort;
+   mcheck_pedantic_flag = pedantic_flag;
 }
 
 #endif
diff --git a/include/mcheck.h b/include/mcheck.h
index a049745e4e..f4c9b7e61c 100644
--- 

[PATCH 5/9] mcheck: support memalign

[Eugene Uriev]

Signed-off-by: Eugene Uriev 
---

 common/dlmalloc.c|  7 ++-
 common/mcheck_core.inc.h | 20 ++--
 2 files changed, 24 insertions(+), 3 deletions(-)

diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 8de15d7193..73c04af2a3 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -2265,7 +2265,12 @@ Void_t *rEALLOc(Void_t *oldmem, size_t bytes)
 
 Void_t *mEMALIGn(size_t alignment, size_t bytes)
 {
-   return NULL;
+   size_t fullsz = mcheck_memalign_prehook(alignment, bytes);
+   void *p = mEMALIGn_impl(alignment, fullsz);
+
+   if (!p)
+   return p;
+   return mcheck_memalign_posthook(alignment, p, bytes);
 }
 
 // pvALLOc, vALLOc - redirect to mEMALIGn, defined here, so they need no 
wrapping.
diff --git a/common/mcheck_core.inc.h b/common/mcheck_core.inc.h
index 6f26ef00d9..b038bb0539 100644
--- a/common/mcheck_core.inc.h
+++ b/common/mcheck_core.inc.h
@@ -69,6 +69,7 @@ typedef struct {
 } mcheck_canary;
 struct mcheck_hdr {
size_t size; /* Exact size requested by user.  */
+   size_t aln_skip; /* Ignored bytes, before the mcheck_hdr, to fulfill 
alignment */
mcheck_canary canary; /* Magic number to check header integrity.  */
 };
 
@@ -104,6 +105,7 @@ static inline size_t allign_size_up(size_t sz, size_t grain)
 }
 
 #define mcheck_allign_customer_size(SZ) allign_size_up(SZ, sizeof(mcheck_elem))
+#define mcheck_evaluate_memalign_prefix_size(ALIGN) 
allign_size_up(sizeof(struct mcheck_hdr), ALIGN)
 
 static enum mcheck_status mcheck_OnNok(enum mcheck_status status)
 {
@@ -156,7 +158,8 @@ static void *mcheck_free_helper(void *ptr, int 
clean_content)
 
if (clean_content)
mcheck_flood(ptr, FREEFLOOD, 
mcheck_allign_customer_size(hdr->size));
-   return hdr;
+
+   return (char *)hdr - hdr->aln_skip;
 }
 
 static void *mcheck_free_prehook(void *ptr) { return mcheck_free_helper(ptr, 
CLEAN_CONTENT); }
@@ -171,10 +174,13 @@ static size_t mcheck_alloc_prehook(size_t sz)
 static void *mcheck_allocated_helper(void *altoghether_ptr, size_t customer_sz,
 size_t alignment, int clean_content)
 {
-   struct mcheck_hdr *hdr = (struct mcheck_hdr *)altoghether_ptr;
+   const size_t slop = alignment ?
+   mcheck_evaluate_memalign_prefix_size(alignment) - sizeof(struct 
mcheck_hdr) : 0;
+   struct mcheck_hdr *hdr = (struct mcheck_hdr *)((char *)altoghether_ptr 
+ slop);
int i;
 
hdr->size = customer_sz;
+   hdr->aln_skip = slop;
for (i = 0; i < CANARY_DEPTH; ++i)
hdr->canary.elems[i] = MAGICWORD;
 
@@ -204,6 +210,16 @@ static void *mcheck_alloc_noclean_posthook(void 
*altoghether_ptr, size_t custome
return mcheck_allocated_helper(altoghether_ptr, customer_sz, 
ANY_ALIGNMENT, KEEP_CONTENT);
 }
 
+static size_t mcheck_memalign_prehook(size_t alig, size_t sz)
+{
+   return mcheck_evaluate_memalign_prefix_size(alig) + sz + 
sizeof(mcheck_canary);
+}
+
+static void *mcheck_memalign_posthook(size_t alignment, void *altoghether_ptr, 
size_t customer_sz)
+{
+   return mcheck_allocated_helper(altoghether_ptr, customer_sz, alignment, 
CLEAN_CONTENT);
+}
+
 static enum mcheck_status mcheck_mprobe(void *ptr)
 {
struct mcheck_hdr *hdr = &((struct mcheck_hdr *)ptr)[-1];
-- 
2.25.1

[PATCH 3/9] mcheck: introduce essentials of mcheck

[Eugene Uriev]

The core part of mcheck, but without memalign.
memalign - to be added in ensuing commits.

Signed-off-by: Eugene Uriev 
---

 common/mcheck_core.inc.h | 220 +++
 include/mcheck.h |  42 
 2 files changed, 262 insertions(+)
 create mode 100644 common/mcheck_core.inc.h
 create mode 100644 include/mcheck.h

diff --git a/common/mcheck_core.inc.h b/common/mcheck_core.inc.h
new file mode 100644
index 00..6f26ef00d9
--- /dev/null
+++ b/common/mcheck_core.inc.h
@@ -0,0 +1,220 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2024 Free Software Foundation, Inc.
+ * Written by Eugene Uriev, based on glibc 2.0 prototype of Mike Haertel.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Library General Public License for more details.
+ * 
+ */
+
+/*
+ * TL;DR: this is a porting of glibc mcheck into U-Boot
+ *
+ * This file contains no entities for external linkage.
+ * So mcheck protection may be used in parallel, e.g. for "malloc_simple(..)" 
and "malloc(..)".
+ * To do so, the file should be shared/include twice, - without linkage 
conflicts.
+ * I.e. "core"-part is shared as a source, but not as a binary.
+ * Maybe some optimization here make sense, to engage more binary sharing too.
+ * But, currently I strive to keep it as simple, as possible.
+ * And this, programmers'-only, mode don't pretend to be main.
+ *
+ * This library is aware of U-Boot specific. It's also aware of ARM alignment 
concerns.
+ * Unlike glibc-clients, U-Boot has limited malloc-usage, and only one thread.
+ * So it's better to make the protection heavier.
+ * Thus overflow canary here is greater, than glibc's one. Underflow canary is 
bigger too.
+ * Heavy canary allows to catch not only memset(..)-errors,
+ * but overflow/underflow of struct-array access:
+ * {
+ * struct mystruct* p = malloc(sizeof(struct mystruct) * N);
+ * p[-1].field1 = 0;
+ * p[N].field2 = 13;
+ * }
+ * TODO: In order to guarantee full coverage of that kind of errors, a user 
can add variable-size
+ *   canaries here. So pre- and post-canary with size >= reqested_size, 
could be provided
+ *   (with the price of 3x heap-usage). Therefore, it would catch 100% of 
changes beyond
+ *   an array, for index(+1/-1) errors.
+ *
+ * U-Boot is a BL, not an OS with a lib. Activity of the library is set not in 
runtime,
+ * rather in compile-time, by MCHECK_HEAP_PROTECTION macro. That guarantees 
that
+ * we haven't missed first malloc.
+ */
+#ifndef _MCHECKCORE_INC_H
+#define _MCHECKCORE_INC_H  1
+#include "mcheck.h"
+
+#if defined(MCHECK_HEAP_PROTECTION)
+#define mcheck_flood memset
+
+// these are from /dev/random:
+#define MAGICWORD  0x99ccf430fa562a05ULL
+#define MAGICFREE  0x4875e63c0c6fc08eULL
+#define MAGICTAIL  0x918dbcd7df78dcd6ULL
+#define MALLOCFLOOD((char)0xb6)
+#define FREEFLOOD  ((char)0xf5)
+#define PADDINGFLOOD   ((char)0x58)
+
+#define CANARY_DEPTH   2
+
+typedef unsigned long long mcheck_elem;
+typedef struct {
+   mcheck_elem elems[CANARY_DEPTH];
+} mcheck_canary;
+struct mcheck_hdr {
+   size_t size; /* Exact size requested by user.  */
+   mcheck_canary canary; /* Magic number to check header integrity.  */
+};
+
+static void mcheck_default_abort(enum mcheck_status status)
+{
+   const char *msg;
+
+   switch (status) {
+   case MCHECK_OK:
+   msg = "memory is consistent, library is buggy\n";
+   break;
+   case MCHECK_HEAD:
+   msg = "memory clobbered before allocated block\n";
+   break;
+   case MCHECK_TAIL:
+   msg = "memory clobbered past end of allocated block\n";
+   break;
+   case MCHECK_FREE:
+   msg = "block freed twice\n";
+   break;
+   default:
+   msg = "bogus mcheck_status, library is buggy\n";
+   break;
+   }
+   printf("\n\nmcheck: %s!!!\n\n", msg);
+}
+
+static mcheck_abortfunc_t mcheck_abortfunc = _default_abort;
+
+static inline size_t allign_size_up(size_t sz, size_t grain)
+{
+   return (sz + grain - 1) & ~(grain - 1);
+}
+
+#define mcheck_allign_customer_size(SZ) allign_size_up(SZ, sizeof(mcheck_elem))
+
+static enum mcheck_status mcheck_OnNok(enum mcheck_status status)
+{
+   (*mcheck_abortfunc)(status);
+   return status;
+}
+
+static enum mcheck_status mcheck_checkhdr(const struct mcheck_hdr *hdr)
+{
+   int i;
+
+   for (i = 0; i < 

[PATCH 4/9] mcheck: integrate mcheck into dlmalloc.c

[Eugene Uriev]

This changes are probable worth to be generalized in a
separate .h-file so, making it able to cover
libc-mallocs and others, without too much copy-paste.

But the malloc<=>mALLOc substitutions interfere
with an elegant way to do this.

Signed-off-by: Eugene Uriev 
---

 common/dlmalloc.c | 67 +++
 1 file changed, 67 insertions(+)

diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 0813e7e8b1..8de15d7193 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -2225,6 +2225,73 @@ void cfree(mem) Void_t *mem;
 #endif
 
 
+#ifdef MCHECK_HEAP_PROTECTION
+ #include "mcheck_core.inc.h"
+ #if !__STD_C
+  #error "must have __STD_C"
+ #endif
+
+Void_t *mALLOc(size_t bytes)
+{
+   size_t fullsz = mcheck_alloc_prehook(bytes);
+   void *p = mALLOc_impl(fullsz);
+
+   if (!p)
+   return p;
+   return mcheck_alloc_posthook(p, bytes);
+}
+
+void fREe(Void_t *mem) { fREe_impl(mcheck_free_prehook(mem)); }
+
+Void_t *rEALLOc(Void_t *oldmem, size_t bytes)
+{
+   if (bytes == 0) {
+   if (oldmem)
+   fREe(oldmem);
+   return NULL;
+   }
+
+   if (oldmem == NULL)
+   return mALLOc(bytes);
+
+   void *p = mcheck_reallocfree_prehook(oldmem);
+   size_t newsz = mcheck_alloc_prehook(bytes);
+
+   p = rEALLOc_impl(p, newsz);
+   if (!p)
+   return p;
+   return mcheck_alloc_noclean_posthook(p, bytes);
+}
+
+Void_t *mEMALIGn(size_t alignment, size_t bytes)
+{
+   return NULL;
+}
+
+// pvALLOc, vALLOc - redirect to mEMALIGn, defined here, so they need no 
wrapping.
+
+Void_t *cALLOc(size_t n, size_t elem_size)
+{
+   // NB: here is no overflow check.
+   size_t fullsz = mcheck_alloc_prehook(n * elem_size);
+   void *p = cALLOc_impl(1, fullsz);
+
+   if (!p)
+   return p;
+   return mcheck_alloc_noclean_posthook(p, n * elem_size);
+}
+
+// mcheck API {
+int mcheck(mcheck_abortfunc_t f)
+{
+   mcheck_initialize(f, 0);
+   return 0;
+}
+
+enum mcheck_status mprobe(void *__ptr) { return mcheck_mprobe(__ptr); }
+// mcheck API }
+#endif
+
 
 /*
 
-- 
2.25.1

[PATCH 1/9] mcheck: prepare +1 tier for mcheck-wrappers, in dl-*alloc commands

[Eugene Uriev]

Signed-off-by: Eugene Uriev 

---
The file contradicts U-Boot code style a lot; so I preserve
original style, according to recommendations.

 common/dlmalloc.c | 66 +--
 1 file changed, 41 insertions(+), 25 deletions(-)

diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index de3f04225f..40acd3dfa5 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -32,6 +32,17 @@ void malloc_stats();
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef MCHECK_HEAP_PROTECTION
+ #define STATIC_IF_MCHECK static
+#else
+ #define STATIC_IF_MCHECK
+ #define mALLOc_impl mALLOc
+ #define fREe_impl fREe
+ #define rEALLOc_impl rEALLOc
+ #define mEMALIGn_impl mEMALIGn
+ #define cALLOc_impl cALLOc
+#endif
+
 /*
   Emulation of sbrk for WIN32
   All code within the ifdef WIN32 is untested by me.
@@ -1270,10 +1281,11 @@ static void malloc_extend_top(nb) INTERNAL_SIZE_T nb;
 
 */
 
+STATIC_IF_MCHECK
 #if __STD_C
-Void_t* mALLOc(size_t bytes)
+Void_t* mALLOc_impl(size_t bytes)
 #else
-Void_t* mALLOc(bytes) size_t bytes;
+Void_t* mALLOc_impl(bytes) size_t bytes;
 #endif
 {
   mchunkptr victim;  /* inspected/selected chunk */
@@ -1555,10 +1567,11 @@ Void_t* mALLOc(bytes) size_t bytes;
 */
 
 
+STATIC_IF_MCHECK
 #if __STD_C
-void fREe(Void_t* mem)
+void fREe_impl(Void_t* mem)
 #else
-void fREe(mem) Void_t* mem;
+void fREe_impl(mem) Void_t* mem;
 #endif
 {
   mchunkptr p; /* chunk corresponding to mem */
@@ -1696,10 +1709,11 @@ void fREe(mem) Void_t* mem;
 */
 
 
+STATIC_IF_MCHECK
 #if __STD_C
-Void_t* rEALLOc(Void_t* oldmem, size_t bytes)
+Void_t* rEALLOc_impl(Void_t* oldmem, size_t bytes)
 #else
-Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes;
+Void_t* rEALLOc_impl(oldmem, bytes) Void_t* oldmem; size_t bytes;
 #endif
 {
   INTERNAL_SIZE_Tnb;  /* padded request size */
@@ -1725,7 +1739,7 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t 
bytes;
 
 #ifdef REALLOC_ZERO_BYTES_FREES
   if (!bytes) {
-   fREe(oldmem);
+   fREe_impl(oldmem);
return NULL;
   }
 #endif
@@ -1733,7 +1747,7 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t 
bytes;
   if ((long)bytes < 0) return NULL;
 
   /* realloc of null is supposed to be same as malloc */
-  if (oldmem == NULL) return mALLOc(bytes);
+  if (oldmem == NULL) return mALLOc_impl(bytes);
 
 #if CONFIG_IS_ENABLED(SYS_MALLOC_F)
if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) {
@@ -1758,7 +1772,7 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t 
bytes;
 /* Note the extra SIZE_SZ overhead. */
 if(oldsize - SIZE_SZ >= nb) return oldmem; /* do nothing */
 /* Must alloc, copy, free. */
-newmem = mALLOc(bytes);
+newmem = mALLOc_impl(bytes);
 if (!newmem)
return NULL; /* propagate failure */
 MALLOC_COPY(newmem, oldmem, oldsize - 2*SIZE_SZ);
@@ -1869,7 +1883,7 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t 
bytes;
 
 /* Must allocate */
 
-newmem = mALLOc (bytes);
+newmem = mALLOc_impl (bytes);
 
 if (newmem == NULL)  /* propagate failure */
   return NULL;
@@ -1886,7 +1900,7 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t 
bytes;
 
 /* Otherwise copy, free, and exit */
 MALLOC_COPY(newmem, oldmem, oldsize - SIZE_SZ);
-fREe(oldmem);
+fREe_impl(oldmem);
 return newmem;
   } else {
 VALGRIND_RESIZEINPLACE_BLOCK(oldmem, 0, bytes, SIZE_SZ);
@@ -1905,7 +1919,7 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t 
bytes;
 set_inuse_bit_at_offset(remainder, remainder_size);
 VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(remainder), remainder_size, SIZE_SZ,
  false);
-fREe(chunk2mem(remainder)); /* let free() deal with it */
+fREe_impl(chunk2mem(remainder)); /* let free() deal with it */
   }
   else
   {
@@ -1939,10 +1953,11 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t 
bytes;
 */
 
 
+STATIC_IF_MCHECK
 #if __STD_C
-Void_t* mEMALIGn(size_t alignment, size_t bytes)
+Void_t* mEMALIGn_impl(size_t alignment, size_t bytes)
 #else
-Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes;
+Void_t* mEMALIGn_impl(alignment, bytes) size_t alignment; size_t bytes;
 #endif
 {
   INTERNAL_SIZE_Tnb;  /* padded  request size */
@@ -1965,7 +1980,7 @@ Void_t* mEMALIGn(alignment, bytes) size_t alignment; 
size_t bytes;
 
   /* If need less alignment than we give anyway, just relay to malloc */
 
-  if (alignment <= MALLOC_ALIGNMENT) return mALLOc(bytes);
+  if (alignment <= MALLOC_ALIGNMENT) return mALLOc_impl(bytes);
 
   /* Otherwise, ensure that it is at least a minimum chunk size */
 
@@ -1974,7 +1989,7 @@ Void_t* mEMALIGn(alignment, bytes) size_t alignment; 
size_t bytes;
   /* Call malloc with worst case padding to hit alignment. */
 
   nb = request2size(bytes);
-  m  = (char*)(mALLOc(nb + alignment + MINSIZE));
+  m  = (char*)(mALLOc_impl(nb + alignment + MINSIZE));
 
   /*
   * The attempt to over-allocate (with a size large enough to 

[PATCH 2/9] mcheck: Use memset/memcpy instead of MALLOC_ZERO/MALLOC_COPY for mcheck.

[Eugene Uriev]

These fast helpers sometimes breach mem-chunk boundaries.
Thus they trigger mcheck alarm. Standard ones are accurate though.

Signed-off-by: Eugene Uriev 
---

 common/dlmalloc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 40acd3dfa5..0813e7e8b1 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -34,6 +34,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef MCHECK_HEAP_PROTECTION
  #define STATIC_IF_MCHECK static
+ #undef MALLOC_COPY
+ #undef MALLOC_ZERO
+static inline void MALLOC_ZERO(void *p, size_t sz) { memset(p, 0, sz); }
+static inline void MALLOC_COPY(void *dest, const void *src, size_t sz) { 
memcpy(dest, src, sz); }
 #else
  #define STATIC_IF_MCHECK
  #define mALLOc_impl mALLOc
-- 
2.25.1

[PATCH 0/9] mcheck implementation for U-Boot

[Eugene Uriev]

There was no "mcheck" for U-Boot before.

Since U-Boot has only 1 thread, and normally makes 4000+ - 6000+
mallocs, it's better to use havier canaries to protect heap-chunks.
My variant uses 2x8 = 16byte-long protector. And
the multiplier could be changed to tune speed/protection tradeoff.
This protects not only against memset()-s, but against "near" wild
pointers too, and makes more probable to catch "distant" ones.

The core file of the set is included into the C-file, not complied
separately in order to enable (potential) coexisting of
mcheck-protectors, e.g. malloc_simple(.) and dlmalloc simultaneously.

My tests were for ARM SoC, 64bit, so the patch is
aware of alignment.

Primary this patch is for using by developers: to verify,
if a change doesn't break the heap integrity.
By default the mcheck is disabled and wouldn't affect the boot.

I used pedantic mode, canary=16byte, registry-size=6608.
For my system the overhead was 230ms.

I assume, the merge window coming. So I send it now.


Eugene Uriev (9):
  mcheck: prepare +1 tier for mcheck-wrappers, in dl-*alloc commands
  mcheck: Use memset/memcpy instead of MALLOC_ZERO/MALLOC_COPY for
mcheck.
  mcheck: introduce essentials of mcheck
  mcheck: integrate mcheck into dlmalloc.c
  mcheck: support memalign
  mcheck: add pedantic mode support
  mcheck: introduce mcheck_on_ramrelocation(.)
  mcheck: add stats, add a comment with test results
  mcheck: let mcheck_abortfunc_t print the pointer

 common/board_f.c |   4 +
 common/dlmalloc.c| 154 
 common/mcheck_core.inc.h | 304 +++
 include/mcheck.h |  51 +++
 4 files changed, 488 insertions(+), 25 deletions(-)
 create mode 100644 common/mcheck_core.inc.h
 create mode 100644 include/mcheck.h

-- 
2.25.1

[PATCH 30/31] rockchip: rk3399-pinebook-pro: Sync device tree from linux v6.8

[Jonas Karlman]

Sync rk3399-pinebook-pro device tree from linux v6.8.

Add SF_DEFAULT_SPEED=1000 and SPI_FLASH_SFDP_SUPPORT=y to improve
support for booting from SPI flash.

Add CMD_POWEROFF=y to support poweroff using cmdline and power on using
the pwr button on the board.

Remove SPL_TINY_MEMSET=y to use full memset in SPL.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3399-pinebook-pro.dts  | 24 +++-
 configs/pinebook-pro-rk3399_defconfig |  6 --
 2 files changed, 11 insertions(+), 19 deletions(-)

diff --git a/arch/arm/dts/rk3399-pinebook-pro.dts 
b/arch/arm/dts/rk3399-pinebook-pro.dts
index d6b68d77d63a..054c6a4d1a45 100644
--- a/arch/arm/dts/rk3399-pinebook-pro.dts
+++ b/arch/arm/dts/rk3399-pinebook-pro.dts
@@ -50,19 +50,9 @@
pinctrl-0 = <_en_pin>;
power-supply = <_panel>;
 
-   ports {
-   #address-cells = <1>;
-   #size-cells = <0>;
-
-   port@0 {
-   reg = <0>;
-   #address-cells = <1>;
-   #size-cells = <0>;
-
-   panel_in_edp: endpoint@0 {
-   reg = <0>;
-   remote-endpoint = <_out_panel>;
-   };
+   port {
+   panel_in_edp: endpoint {
+   remote-endpoint = <_out_panel>;
};
};
};
@@ -76,7 +66,7 @@
pinctrl-names = "default";
pinctrl-0 = <_pin>;
 
-   lid {
+   switch-lid {
debounce-interval = <20>;
gpios = < RK_PA1 GPIO_ACTIVE_LOW>;
label = "Lid";
@@ -92,7 +82,7 @@
pinctrl-names = "default";
pinctrl-0 = <_pin>;
 
-   power {
+   key-power {
debounce-interval = <20>;
gpios = < RK_PA5 GPIO_ACTIVE_LOW>;
label = "Power";
@@ -675,7 +665,7 @@
i2c-scl-rising-time-ns = <168>;
status = "okay";
 
-   es8316: es8316@11 {
+   es8316: audio-codec@11 {
compatible = "everest,es8316";
reg = <0x11>;
clocks = < SCLK_I2S_8CH_OUT>;
@@ -943,7 +933,7 @@
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <_clk _cmd _bus4>;
-   sd-uhs-sdr104;
+   sd-uhs-sdr50;
vmmc-supply = <_sd>;
vqmmc-supply = <_sdio>;
status = "okay";
diff --git a/configs/pinebook-pro-rk3399_defconfig 
b/configs/pinebook-pro-rk3399_defconfig
index dd8bc2b72cc3..8ac6ddd49dea 100644
--- a/configs/pinebook-pro-rk3399_defconfig
+++ b/configs/pinebook-pro-rk3399_defconfig
@@ -4,7 +4,7 @@ CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SPL_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_SF_DEFAULT_SPEED=2000
+CONFIG_SF_DEFAULT_SPEED=1000
 CONFIG_ENV_SIZE=0x8000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro"
@@ -36,6 +36,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
@@ -64,7 +65,9 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_NVME_PCI=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -98,5 +101,4 @@ CONFIG_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_DISPLAY_ROCKCHIP_EDP=y
-CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
-- 
2.43.2

[PATCH 31/31] rockchip: rk3399-pinephone-pro: Sync device tree from linux v6.8

[Jonas Karlman]

Sync rk3399-pinephone-pro device tree from linux v6.8.

Add SPI flash related node and options to support booting from SPI flash.

Remove REGULATOR_PWM=y, board does not use pwm-regulator compatible.

Add SYS_NS16550_MEM32=y to use readl/writel for serial console.

Remove SPL_TINY_MEMSET=y to use full memset in SPL.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi |  12 ++
 arch/arm/dts/rk3399-pinephone-pro.dts | 147 ++
 configs/pinephone-pro-rk3399_defconfig|   8 +-
 3 files changed, 163 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi 
b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
index dcfcec4f3072..6a248691e29d 100644
--- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
@@ -13,3 +13,15 @@
  {
max-frequency = <2000>;
 };
+
+ {
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   bootph-some-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <1000>;
+   };
+};
diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts 
b/arch/arm/dts/rk3399-pinephone-pro.dts
index 04403a76238b..61f3fec5a8b1 100644
--- a/arch/arm/dts/rk3399-pinephone-pro.dts
+++ b/arch/arm/dts/rk3399-pinephone-pro.dts
@@ -10,6 +10,7 @@
  */
 
 /dts-v1/;
+#include 
 #include 
 #include "rk3399.dtsi"
 #include "rk3399-opp.dtsi"
@@ -29,6 +30,31 @@
stdout-path = "serial2:115200n8";
};
 
+   adc-keys {
+   compatible = "adc-keys";
+   io-channels = < 1>;
+   io-channel-names = "buttons";
+   keyup-threshold-microvolt = <160>;
+   poll-interval = <100>;
+
+   button-up {
+   label = "Volume Up";
+   linux,code = ;
+   press-threshold-microvolt = <10>;
+   };
+
+   button-down {
+   label = "Volume Down";
+   linux,code = ;
+   press-threshold-microvolt = <60>;
+   };
+   };
+
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   pwms = < 0 5 0>;
+   };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -102,6 +128,37 @@
/* WL_REG_ON on module */
reset-gpios = < RK_PB2 GPIO_ACTIVE_LOW>;
};
+
+   /* MIPI DSI panel 1.8v supply */
+   vcc1v8_lcd: vcc1v8-lcd {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   regulator-name = "vcc1v8_lcd";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   vin-supply = <_sys>;
+   gpio = < RK_PA5 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   };
+
+   /* MIPI DSI panel 2.8v supply */
+   vcc2v8_lcd: vcc2v8-lcd {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   regulator-name = "vcc2v8_lcd";
+   regulator-min-microvolt = <280>;
+   regulator-max-microvolt = <280>;
+   vin-supply = <_sys>;
+   gpio = < RK_PA1 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   };
+};
+
+_alert0 {
+   temperature = <65000>;
+};
+_alert1 {
+   temperature = <68000>;
 };
 
 _l0 {
@@ -132,6 +189,11 @@
status = "okay";
 };
 
+ {
+   mali-supply = <_gpu>;
+   status = "okay";
+};
+
  {
clock-frequency = <40>;
i2c-scl-rising-time-ns = <168>;
@@ -326,6 +388,25 @@
};
 };
 
+ {
+   i2c-scl-rising-time-ns = <450>;
+   i2c-scl-falling-time-ns = <15>;
+   status = "okay";
+
+   touchscreen@14 {
+   compatible = "goodix,gt1158";
+   reg = <0x14>;
+   interrupt-parent = <>;
+   interrupts = ;
+   irq-gpios = < RK_PB5 GPIO_ACTIVE_HIGH>;
+   reset-gpios = < RK_PB4 GPIO_ACTIVE_HIGH>;
+   AVDD28-supply = <_touch>;
+   VDDIO-supply = <_touch>;
+   touchscreen-size-x = <720>;
+   touchscreen-size-y = <1440>;
+   };
+};
+
 _opp {
opp04 {
status = "disabled";
@@ -355,6 +436,39 @@
status = "okay";
 };
 
+_dsi {
+   status = "okay";
+   clock-master;
+
+   ports {
+   mipi_out: port@1 {
+   #address-cells = <0>;
+   #size-cells = <0>;
+   reg = <1>;
+
+   mipi_out_panel: endpoint {
+   remote-endpoint = <_in_panel>;
+   };
+   };
+   };
+
+   panel@0 {
+   compatible = 

[PATCH 29/31] rockchip: rk3399-rockpro64: Sync device tree from linux v6.8

[Jonas Karlman]

Sync rk3399-rockpro64 device tree from linux v6.8.

Add SF_DEFAULT_SPEED=1000 and SPI_FLASH_SFDP_SUPPORT=y to improve
support for booting from SPI flash.

Remove USE_PREBOOT=y to speed up booting, standard boot will init USB
after faster boot media has been evaluated.

Add CMD_POWEROFF=y to support poweroff using cmdline and power on using
the pwr button on the board.

Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.

Remove SPL_TINY_MEMSET=y to use full memset in SPL.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3399-rockpro64.dtsi | 98 --
 configs/rockpro64-rk3399_defconfig |  7 ++-
 2 files changed, 97 insertions(+), 8 deletions(-)

diff --git a/arch/arm/dts/rk3399-rockpro64.dtsi 
b/arch/arm/dts/rk3399-rockpro64.dtsi
index 6bff8db7d33e..f30b82a10ca3 100644
--- a/arch/arm/dts/rk3399-rockpro64.dtsi
+++ b/arch/arm/dts/rk3399-rockpro64.dtsi
@@ -11,6 +11,7 @@
 
 / {
aliases {
+   ethernet0 = 
mmc0 = 
mmc1 = 
mmc2 = 
@@ -20,6 +21,15 @@
stdout-path = "serial2:150n8";
};
 
+   /* enable for panel backlight support */
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   brightness-levels = <0 4 8 16 32 64 128 255>;
+   default-brightness-level = <5>;
+   pwms = < 0 100 0>;
+   status = "disabled";
+   };
+
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <12500>;
@@ -33,7 +43,7 @@
pinctrl-names = "default";
pinctrl-0 = <>;
 
-   power {
+   key-power {
debounce-interval = <100>;
gpios = < RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
@@ -69,6 +79,7 @@
 
fan: pwm-fan {
compatible = "pwm-fan";
+   cooling-levels = <0 100 150 200 255>;
#cooling-cells = <2>;
fan-supply = <_dcin>;
pwms = < 0 5 0>;
@@ -106,6 +117,14 @@
};
};
 
+   avdd: avdd-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "avdd";
+   regulator-min-microvolt = <1100>;
+   regulator-max-microvolt = <1100>;
+   vin-supply = <_s0>;
+   };
+
vcc12v_dcin: vcc12v-dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
@@ -212,12 +231,12 @@
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = < 0 25000 1>;
+   pwm-supply = <_sys>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <80>;
regulator-max-microvolt = <170>;
-   vin-supply = <_sys>;
};
 };
 
@@ -245,6 +264,34 @@
cpu-supply = <_cpu_b>;
 };
 
+_thermal {
+   trips {
+   cpu_warm: cpu_warm {
+   temperature = <55000>;
+   hysteresis = <2000>;
+   type = "active";
+   };
+
+   cpu_hot: cpu_hot {
+   temperature = <65000>;
+   hysteresis = <2000>;
+   type = "active";
+   };
+   };
+
+   cooling-maps {
+   map2 {
+   trip = <_warm>;
+   cooling-device = < THERMAL_NO_LIMIT 1>;
+   };
+
+   map3 {
+   trip = <_hot>;
+   cooling-device = < 2 THERMAL_NO_LIMIT>;
+   };
+   };
+};
+
 _phy {
status = "okay";
 };
@@ -371,8 +418,6 @@
 
vcc3v0_touch: LDO_REG2 {
regulator-name = "vcc3v0_touch";
-   regulator-always-on;
-   regulator-boot-on;
regulator-min-microvolt = <300>;
regulator-max-microvolt = <300>;
regulator-state-mem {
@@ -461,8 +506,6 @@
 
vcc3v3_s0: SWITCH_REG2 {
regulator-name = "vcc3v3_s0";
-   regulator-always-on;
-   regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
@@ -536,6 +579,19 @@
vbus-supply = <_typec>;
status = "okay";
};
+
+   /* enable for pine64 touch screen support */
+   touch: touchscreen@5d {
+   compatible = "goodix,gt911";
+   reg = <0x5d>;
+

[PATCH 28/31] rockchip: rk3399-rock-pi-4: Sync device tree from linux v6.8

[Jonas Karlman]

Sync rk3399-rock-pi-4 related device tree from linux v6.8.

Add SPI flash related options to support booting from SPI flash.

Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.

Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.

Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.

Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.

Remove SPL_TINY_MEMSET=y to use full memset in SPL.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 12 ++
 arch/arm/dts/rk3399-rock-4c-plus.dts |  1 +
 arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 ++
 arch/arm/dts/rk3399-rock-pi-4.dtsi   |  4 +++-
 arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi   |  7 ++
 arch/arm/dts/rk3399-rock-pi-4c.dts   | 10 
 configs/rock-4c-plus-rk3399_defconfig| 24 +++-
 configs/rock-4se-rk3399_defconfig| 23 +--
 configs/rock-pi-4-rk3399_defconfig   |  8 +++
 configs/rock-pi-4c-rk3399_defconfig  | 24 ++--
 10 files changed, 114 insertions(+), 11 deletions(-)

diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi 
b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
index 9785b97b9eea..b5ee644a83dd 100644
--- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
@@ -11,3 +11,15 @@
 _pull_up_8ma {
bootph-pre-ram;
 };
+
+ {
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   bootph-some-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <1000>;
+   };
+};
diff --git a/arch/arm/dts/rk3399-rock-4c-plus.dts 
b/arch/arm/dts/rk3399-rock-4c-plus.dts
index 8bfd5f88d1ef..7baf9d1b22fd 100644
--- a/arch/arm/dts/rk3399-rock-4c-plus.dts
+++ b/arch/arm/dts/rk3399-rock-4c-plus.dts
@@ -15,6 +15,7 @@
compatible = "radxa,rock-4c-plus", "rockchip,rk3399";
 
aliases {
+   ethernet0 = 
mmc0 = 
mmc1 = 
};
diff --git a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi 
b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
index 85ee5770add0..2213d0093052 100644
--- a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
@@ -4,3 +4,15 @@
  */
 
 #include "rk3399-rock-pi-4-u-boot.dtsi"
+
+ {
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   bootph-some-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <1000>;
+   };
+};
diff --git a/arch/arm/dts/rk3399-rock-pi-4.dtsi 
b/arch/arm/dts/rk3399-rock-pi-4.dtsi
index b1b7f4ffb1d4..281a12180703 100644
--- a/arch/arm/dts/rk3399-rock-pi-4.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4.dtsi
@@ -12,6 +12,7 @@
 
 / {
aliases {
+   ethernet0 = 
mmc0 = 
mmc1 = 
};
@@ -44,7 +45,7 @@
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = < 1>;
-   clock-names = "ext_clock";
+   clock-names = "lpo";
pinctrl-names = "default";
pinctrl-0 = <_enable_h>;
reset-gpios = < RK_PB2 GPIO_ACTIVE_LOW>;
@@ -492,6 +493,7 @@
 
  {
pinctrl-0 = <_2ch_bus>;
+   pinctrl-1 = <_2ch_bus_bclk_off>;
rockchip,capture-channels = <2>;
rockchip,playback-channels = <2>;
status = "okay";
diff --git a/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi 
b/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi
index 85ee5770add0..38385621deb1 100644
--- a/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi
@@ -4,3 +4,10 @@
  */
 
 #include "rk3399-rock-pi-4-u-boot.dtsi"
+
+ {
+   flash@0 {
+   bootph-pre-ram;
+   bootph-some-ram;
+   };
+};
diff --git a/arch/arm/dts/rk3399-rock-pi-4c.dts 
b/arch/arm/dts/rk3399-rock-pi-4c.dts
index d32efab74e94..de2ebe4cb4f3 100644
--- a/arch/arm/dts/rk3399-rock-pi-4c.dts
+++ b/arch/arm/dts/rk3399-rock-pi-4c.dts
@@ -43,6 +43,16 @@
hp-det-gpio = < RK_PA0 GPIO_ACTIVE_HIGH>;
 };
 
+ {
+   status = "okay";
+
+   flash@0 {
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <1000>;
+   };
+};
+
  {
status = "okay";
 
diff --git a/configs/rock-4c-plus-rk3399_defconfig 
b/configs/rock-4c-plus-rk3399_defconfig
index 2024defb2bf0..e97fde17acc2 100644
--- a/configs/rock-4c-plus-rk3399_defconfig
+++ b/configs/rock-4c-plus-rk3399_defconfig
@@ -3,22 +3,27 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=1000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4c-plus"
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y

[PATCH 27/31] rockchip: rk3399-khadas: Sync device tree from linux v6.8

[Jonas Karlman]

Sync rk3399-khadas related device tree from linux v6.8.

Add SPI flash related options to support booting from SPI flash.

Add DM_RESET=y to support reset signals.

Add PCI=y, CMD_PCI=y and NVME_PCI=y to support PCIe and NVMe boot.

Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.

Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.

Add CMD_ROCKUSB=y, CMD_USB_MASS_STORAGE=y and USB_GADGET=y to support
RockUSB and UMS gadget.

Remove CONFIG_NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on
cpuid read from eFUSE.

Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.

Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.

Add DM_ETH_PHY=y to support ethernet PHY.

Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.

Remove SPL_TINY_MEMSET=y to use full memset in SPL.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3399-khadas-edge-captain.dts  |  4 +++
 arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi  |  5 +++
 arch/arm/dts/rk3399-khadas-edge-v.dts|  4 +++
 arch/arm/dts/rk3399-khadas-edge.dtsi | 10 +++---
 configs/khadas-edge-captain-rk3399_defconfig | 33 ++--
 configs/khadas-edge-rk3399_defconfig | 27 +---
 configs/khadas-edge-v-rk3399_defconfig   | 33 ++--
 7 files changed, 100 insertions(+), 16 deletions(-)

diff --git a/arch/arm/dts/rk3399-khadas-edge-captain.dts 
b/arch/arm/dts/rk3399-khadas-edge-captain.dts
index 8302e51def52..99ac4ed0f13f 100644
--- a/arch/arm/dts/rk3399-khadas-edge-captain.dts
+++ b/arch/arm/dts/rk3399-khadas-edge-captain.dts
@@ -10,6 +10,10 @@
 / {
model = "Khadas Edge-Captain";
compatible = "khadas,edge-captain", "rockchip,rk3399";
+
+   aliases {
+   ethernet0 = 
+   };
 };
 
  {
diff --git a/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi 
b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
index 4a3b23e48313..dd7a84d2b4a8 100644
--- a/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
@@ -6,6 +6,11 @@
 #include "rk3399-u-boot.dtsi"
 #include "rk3399-sdram-lpddr4-100.dtsi"
 
+ {
+   bootph-pre-ram;
+   bootph-some-ram;
+};
+
 _log {
regulator-init-microvolt = <95>;
 };
diff --git a/arch/arm/dts/rk3399-khadas-edge-v.dts 
b/arch/arm/dts/rk3399-khadas-edge-v.dts
index f5dcb99dc349..e12e7b4d64ca 100644
--- a/arch/arm/dts/rk3399-khadas-edge-v.dts
+++ b/arch/arm/dts/rk3399-khadas-edge-v.dts
@@ -10,6 +10,10 @@
 / {
model = "Khadas Edge-V";
compatible = "khadas,edge-v", "rockchip,rk3399";
+
+   aliases {
+   ethernet0 = 
+   };
 };
 
  {
diff --git a/arch/arm/dts/rk3399-khadas-edge.dtsi 
b/arch/arm/dts/rk3399-khadas-edge.dtsi
index d5c7648c841d..9d9297bc5f04 100644
--- a/arch/arm/dts/rk3399-khadas-edge.dtsi
+++ b/arch/arm/dts/rk3399-khadas-edge.dtsi
@@ -6,6 +6,7 @@
 
 /dts-v1/;
 #include 
+#include 
 #include 
 #include "rk3399.dtsi"
 #include "rk3399-opp.dtsi"
@@ -80,12 +81,12 @@
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = < 0 25000 1>;
+   pwm-supply = <_3v3>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <80>;
regulator-max-microvolt = <140>;
-   vin-supply = <_3v3>;
};
 
vsys: vsys {
@@ -122,7 +123,7 @@
keyup-threshold-microvolt = <180>;
poll-interval = <100>;
 
-   recovery {
+   button-recovery {
label = "Recovery";
linux,code = ;
press-threshold-microvolt = <18000>;
@@ -135,7 +136,7 @@
pinctrl-names = "default";
pinctrl-0 = <>;
 
-   power {
+   key-power {
debounce-interval = <100>;
gpios = < RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
@@ -682,7 +683,7 @@
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <>;
-   interrupts = ;
+   interrupts = ;
interrupt-names = "host-wake";
brcm,drive-strength = <5>;
pinctrl-names = "default";
@@ -705,7 +706,6 @@
  {
bus-width = <8>;
mmc-hs400-1_8v;
-   mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
 };
diff --git a/configs/khadas-edge-captain-rk3399_defconfig 
b/configs/khadas-edge-captain-rk3399_defconfig
index 230b9d796442..cf6516656e9a 100644
--- a/configs/khadas-edge-captain-rk3399_defconfig
+++ b/configs/khadas-edge-captain-rk3399_defconfig
@@ -3,51 +3,76 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=1000
 

[PATCH 26/31] rockchip: rk3399-rock960: Sync device tree from linux v6.8

[Jonas Karlman]

Sync rk3399-rock960 related device tree from linux v6.8.

Add DM_RESET=y to support reset signals.

Add PCI=y, CMD_PCI=y and NVME_PCI=y to support PCIe and NVMe boot.

Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.

Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.

Remove CONFIG_NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on
cpuid read from eFUSE.

Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.

Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.

Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.

Remove REGULATOR_PWM=y and DM_REGULATOR_GPIO=y, boards does not use
pwm-regulator or regulator-gpio compatible.

Add USB_XHCI_HCD=y, USB_DWC3=y and USB_DWC3_GENERIC=y to support USB3.

Remove USE_PREBOOT=y to speed up booting, standard boot will init USB
after faster boot media has been evaluated.

Add CMD_ROCKUSB=y, CMD_USB_MASS_STORAGE=y and USB_GADGET=y to support
RockUSB and UMS gadget.

Remove SPL_TINY_MEMSET=y to use full memset in SPL.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3399-ficus.dts|  4 
 arch/arm/dts/rk3399-rock960.dtsi |  5 -
 configs/ficus-rk3399_defconfig   | 22 +-
 configs/rock960-rk3399_defconfig | 14 +++---
 4 files changed, 36 insertions(+), 9 deletions(-)

diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts
index 1ce85a5816e4..30e4879f322c 100644
--- a/arch/arm/dts/rk3399-ficus.dts
+++ b/arch/arm/dts/rk3399-ficus.dts
@@ -13,6 +13,10 @@
model = "96boards RK3399 Ficus";
compatible = "vamrs,ficus", "rockchip,rk3399";
 
+   aliases {
+   ethernet0 = 
+   };
+
chosen {
stdout-path = "serial2:150n8";
};
diff --git a/arch/arm/dts/rk3399-rock960.dtsi b/arch/arm/dts/rk3399-rock960.dtsi
index 25dc61c26a94..c920ddf44baf 100644
--- a/arch/arm/dts/rk3399-rock960.dtsi
+++ b/arch/arm/dts/rk3399-rock960.dtsi
@@ -7,6 +7,7 @@
 
 #include "rk3399.dtsi"
 #include "rk3399-opp.dtsi"
+#include 
 
 / {
aliases {
@@ -127,6 +128,8 @@
 };
 
  {
+   avdd-0v9-supply = <_hdmi>;
+   avdd-1v8-supply = <_hdmi>;
ddc-i2c-bus = <>;
pinctrl-names = "default";
pinctrl-0 = <_cec>;
@@ -528,7 +531,7 @@
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <>;
-   interrupts = ;
+   interrupts = ;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <_host_wake_l>;
diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig
index f4e3ebba8f46..0d97b7ecb3c7 100644
--- a/configs/ficus-rk3399_defconfig
+++ b/configs/ficus-rk3399_defconfig
@@ -5,15 +5,18 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SF_DEFAULT_SPEED=2000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus"
+CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_TARGET_ROCK960_RK3399=y
 CONFIG_DEBUG_UART_BASE=0xFF1A
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-ficus.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -21,6 +24,7 @@ CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
@@ -29,27 +33,35 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent 
assigned-clocks assigne
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_RGMII=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
-CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
+CONFIG_SCSI=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
index 3b5ab7dc5781..e19b28753156 100644
--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig
@@ -12,11 +12,11 @@ CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
-CONFIG_USE_PREBOOT=y
+CONFIG_AHCI=y
 

[PATCH 25/31] rockchip: rk3399-nanopi-4: Sync device tree from linux v6.8

[Jonas Karlman]

Sync rk3399-nanopi-4 related device tree from linux v6.8.

Add DM_RESET=y to support reset signals.

Add PCI=y, CMD_PCI=y and NVME_PCI=y to support PCIe and NVMe boot.

Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.

Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.

Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.

Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.

Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.

Remove REGULATOR_PWM=y, boards does not use pwm-regulator compatible.

Remove SPL_TINY_MEMSET=y to use full memset in SPL.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3399-nanopc-t4.dts   |  2 +-
 arch/arm/dts/rk3399-nanopi-m4-2gb.dts   | 55 +
 arch/arm/dts/rk3399-nanopi-m4b.dts  |  2 +-
 arch/arm/dts/rk3399-nanopi-r4s.dts  |  4 +-
 arch/arm/dts/rk3399-nanopi4-u-boot.dtsi |  4 ++
 arch/arm/dts/rk3399-nanopi4.dtsi|  7 ++--
 configs/nanopc-t4-rk3399_defconfig  | 14 +--
 configs/nanopi-m4-2gb-rk3399_defconfig  | 18 ++--
 configs/nanopi-m4-rk3399_defconfig  | 18 ++--
 configs/nanopi-m4b-rk3399_defconfig | 18 ++--
 configs/nanopi-neo4-rk3399_defconfig| 18 ++--
 configs/nanopi-r4s-rk3399_defconfig | 12 +++---
 12 files changed, 91 insertions(+), 81 deletions(-)

diff --git a/arch/arm/dts/rk3399-nanopc-t4.dts 
b/arch/arm/dts/rk3399-nanopc-t4.dts
index 452728b82e42..3bf8f959e42c 100644
--- a/arch/arm/dts/rk3399-nanopc-t4.dts
+++ b/arch/arm/dts/rk3399-nanopc-t4.dts
@@ -39,7 +39,7 @@
keyup-threshold-microvolt = <180>;
poll-interval = <100>;
 
-   recovery {
+   button-recovery {
label = "Recovery";
linux,code = ;
press-threshold-microvolt = <18000>;
diff --git a/arch/arm/dts/rk3399-nanopi-m4-2gb.dts 
b/arch/arm/dts/rk3399-nanopi-m4-2gb.dts
index 60358ab8c7df..e9cf71f224a3 100644
--- a/arch/arm/dts/rk3399-nanopi-m4-2gb.dts
+++ b/arch/arm/dts/rk3399-nanopi-m4-2gb.dts
@@ -10,57 +10,4 @@
  */
 
 /dts-v1/;
-#include "rk3399-nanopi4.dtsi"
-
-/ {
-   model = "FriendlyElec NanoPi M4";
-   compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399";
-
-   vdd_5v: vdd-5v {
-   compatible = "regulator-fixed";
-   regulator-name = "vdd_5v";
-   regulator-always-on;
-   regulator-boot-on;
-   };
-
-   vcc5v0_core: vcc5v0-core {
-   compatible = "regulator-fixed";
-   regulator-name = "vcc5v0_core";
-   regulator-always-on;
-   regulator-boot-on;
-   vin-supply = <_5v>;
-   };
-
-   vcc5v0_usb1: vcc5v0-usb1 {
-   compatible = "regulator-fixed";
-   regulator-name = "vcc5v0_usb1";
-   regulator-always-on;
-   regulator-boot-on;
-   vin-supply = <_sys>;
-   };
-
-   vcc5v0_usb2: vcc5v0-usb2 {
-   compatible = "regulator-fixed";
-   regulator-name = "vcc5v0_usb2";
-   regulator-always-on;
-   regulator-boot-on;
-   vin-supply = <_sys>;
-   };
-};
-
-_sys {
-   vin-supply = <_core>;
-};
-
-_host {
-   phy-supply = <_usb1>;
-};
-
-_host {
-   phy-supply = <_usb2>;
-};
-
-_typec {
-   regulator-always-on;
-   vin-supply = <_5v>;
-};
+#include "rk3399-nanopi-m4.dts"
diff --git a/arch/arm/dts/rk3399-nanopi-m4b.dts 
b/arch/arm/dts/rk3399-nanopi-m4b.dts
index 72182c58cc46..65cb21837b0c 100644
--- a/arch/arm/dts/rk3399-nanopi-m4b.dts
+++ b/arch/arm/dts/rk3399-nanopi-m4b.dts
@@ -19,7 +19,7 @@
keyup-threshold-microvolt = <150>;
poll-interval = <100>;
 
-   recovery {
+   button-recovery {
label = "Recovery";
linux,code = ;
press-threshold-microvolt = <18000>;
diff --git a/arch/arm/dts/rk3399-nanopi-r4s.dts 
b/arch/arm/dts/rk3399-nanopi-r4s.dts
index cef4d18b599d..fe5b52610010 100644
--- a/arch/arm/dts/rk3399-nanopi-r4s.dts
+++ b/arch/arm/dts/rk3399-nanopi-r4s.dts
@@ -46,9 +46,9 @@
gpio-keys {
pinctrl-0 = <_button_pin>;
 
-   /delete-node/ power;
+   /delete-node/ key-power;
 
-   reset {
+   key-reset {
debounce-interval = <50>;
gpios = < RK_PC6 GPIO_ACTIVE_LOW>;
label = "reset";
diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi 
b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
index e0d7a518dfc2..757361249968 100644
--- a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
@@ -20,3 +20,7 @@
 _sd {
bootph-pre-ram;
 };
+
+_sdio {
+   regulator-init-microvolt = <300>;
+};
diff --git a/arch/arm/dts/rk3399-nanopi4.dtsi b/arch/arm/dts/rk3399-nanopi4.dtsi

[PATCH 24/31] rockchip: rk3399-roc-pc: Sync device tree from linux v6.8

[Jonas Karlman]

Sync rk3399-roc-pc related device tree from linux v6.8.

Add SF_DEFAULT_SPEED=3000 and SPI_FLASH_SFDP_SUPPORT=y to improve
support for booting from SPI flash.

Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA.

Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.

Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.

Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.

Remove SPL_TINY_MEMSET=y to use full memset in SPL.

Remove USE_PREBOOT=y to speed up booting, standard boot will init USB
after faster boot media has been evaluated.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3399-roc-pc.dtsi   | 15 ---
 configs/roc-pc-mezzanine-rk3399_defconfig | 11 ++-
 configs/roc-pc-rk3399_defconfig   |  7 +--
 3 files changed, 23 insertions(+), 10 deletions(-)

diff --git a/arch/arm/dts/rk3399-roc-pc.dtsi b/arch/arm/dts/rk3399-roc-pc.dtsi
index d1aaf8e83391..ca7a446b6568 100644
--- a/arch/arm/dts/rk3399-roc-pc.dtsi
+++ b/arch/arm/dts/rk3399-roc-pc.dtsi
@@ -14,6 +14,7 @@
compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
 
aliases {
+   ethernet0 = 
mmc0 = 
mmc1 = 
};
@@ -41,7 +42,7 @@
keyup-threshold-microvolt = <150>;
poll-interval = <100>;
 
-   recovery {
+   button-recovery {
label = "Recovery";
linux,code = ;
press-threshold-microvolt = <18000>;
@@ -54,7 +55,7 @@
pinctrl-names = "default";
pinctrl-0 = <_key_l>;
 
-   power {
+   key-power {
debounce-interval = <100>;
gpios = < RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
@@ -271,6 +272,8 @@
 };
 
  {
+   avdd-0v9-supply = <_hdmi>;
+   avdd-1v8-supply = <_hdmi>;
ddc-i2c-bus = <>;
pinctrl-names = "default";
pinctrl-0 = <_cec>;
@@ -310,8 +313,6 @@
vcc10-supply = <_sys>;
vcc11-supply = <_sys>;
vcc12-supply = <_sys>;
-   vcc13-supply = <_sys>;
-   vcc14-supply = <_sys>;
vddio-supply = <_3v0>;
 
regulators {
@@ -371,8 +372,8 @@
};
};
 
-   vcc1v8_hdmi: LDO_REG2 {
-   regulator-name = "vcc1v8_hdmi";
+   vcca1v8_hdmi: LDO_REG2 {
+   regulator-name = "vcca1v8_hdmi";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <180>;
@@ -735,7 +736,7 @@
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
-   spi-max-frequency = <1000>;
+   spi-max-frequency = <3000>;
};
 };
 
diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig 
b/configs/roc-pc-mezzanine-rk3399_defconfig
index e13356faabbc..85a20957fa37 100644
--- a/configs/roc-pc-mezzanine-rk3399_defconfig
+++ b/configs/roc-pc-mezzanine-rk3399_defconfig
@@ -4,6 +4,7 @@ CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SPL_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=3000
 CONFIG_ENV_SIZE=0x8000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_ENV_SECT_SIZE=0x1000
@@ -19,6 +20,7 @@ CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -41,14 +43,21 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_NVME_PCI=y
@@ -61,6 +70,7 @@ CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 # CONFIG_RAM_ROCKCHIP_DEBUG is not set
 CONFIG_RAM_ROCKCHIP_LPDDR4=y
+CONFIG_SCSI=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
@@ -84,5 +94,4 @@ CONFIG_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index dee342898d1f..b8adf430e9ea 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig

[PATCH 23/31] rockchip: rk3399-orangepi: Sync device tree from linux v6.8

[Jonas Karlman]

Sync rk3399-orangepi device tree from linux v6.8.

Add DM_RESET=y to support reset signals.

Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.

Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.

Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.

Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.

Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.

Remove SPL_TINY_MEMSET=y to use full memset in SPL.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3399-orangepi.dts  | 12 +++-
 configs/orangepi-rk3399_defconfig | 10 --
 2 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/arch/arm/dts/rk3399-orangepi.dts b/arch/arm/dts/rk3399-orangepi.dts
index 04b54abea3cc..e7551449e718 100644
--- a/arch/arm/dts/rk3399-orangepi.dts
+++ b/arch/arm/dts/rk3399-orangepi.dts
@@ -7,6 +7,7 @@
 
 #include "dt-bindings/pwm/pwm.h"
 #include "dt-bindings/input/input.h"
+#include 
 #include "dt-bindings/usb/pd.h"
 #include "rk3399.dtsi"
 #include "rk3399-opp.dtsi"
@@ -16,6 +17,7 @@
compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399";
 
aliases {
+   ethernet0 = 
mmc0 = 
mmc1 = 
mmc2 = 
@@ -51,13 +53,13 @@
press-threshold-microvolt = <30>;
};
 
-   back {
+   button-back {
label = "Back";
linux,code = ;
press-threshold-microvolt = <985000>;
};
 
-   menu {
+   button-menu {
label = "Menu";
linux,code = ;
press-threshold-microvolt = <1314000>;
@@ -77,7 +79,7 @@
compatible = "gpio-keys";
autorepeat;
 
-   power {
+   key-power {
debounce-interval = <100>;
gpios = < RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
@@ -166,12 +168,12 @@
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = < 0 25000 1>;
+   pwm-supply = <_sys>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <80>;
regulator-max-microvolt = <140>;
-   vin-supply = <_sys>;
};
 };
 
@@ -735,7 +737,7 @@
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <>;
-   interrupts = ;
+   interrupts = ;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <_host_wake_l>;
diff --git a/configs/orangepi-rk3399_defconfig 
b/configs/orangepi-rk3399_defconfig
index 703732ad15f0..2d0c9b77e584 100644
--- a/configs/orangepi-rk3399_defconfig
+++ b/configs/orangepi-rk3399_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi"
+CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_TARGET_EVB_RK3399=y
 CONFIG_DEBUG_UART_BASE=0xFF1A
@@ -14,7 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -31,12 +32,18 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_SPL_DM_REGULATOR_FIXED=y
@@ -58,5 +65,4 @@ CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_RTL8152=y
 CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
-- 
2.43.2

[PATCH 22/31] rockchip: rk3399-firefly: Sync device tree from linux v6.8

[Jonas Karlman]

Sync rk3399-firefly device tree from linux v6.8.

Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA.

Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.

Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.

Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.

Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.

Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.

Remove SPL_TINY_MEMSET=y to use full memset in SPL.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3399-firefly.dts  | 17 -
 configs/firefly-rk3399_defconfig | 13 +++--
 2 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts
index c4dd2a6b4836..260415d99aeb 100644
--- a/arch/arm/dts/rk3399-firefly.dts
+++ b/arch/arm/dts/rk3399-firefly.dts
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 #include 
+#include 
 #include 
 #include 
 #include "rk3399.dtsi"
@@ -15,6 +16,7 @@
compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
 
aliases {
+   ethernet0 = 
mmc0 = 
mmc1 = 
mmc2 = 
@@ -86,7 +88,7 @@
pinctrl-names = "default";
pinctrl-0 = <>;
 
-   power {
+   key-power {
debounce-interval = <100>;
gpios = < RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
@@ -245,12 +247,12 @@
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = < 0 25000 1>;
+   pwm-supply = <_sys>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <43>;
regulator-max-microvolt = <140>;
-   vin-supply = <_sys>;
};
 };
 
@@ -298,6 +300,11 @@
status = "okay";
 };
 
+ {
+   mali-supply = <_gpu>;
+   status = "okay";
+};
+
  {
ddc-i2c-bus = <>;
pinctrl-names = "default";
@@ -770,8 +777,8 @@
sd-uhs-sdr104;
 
/* Power supply */
-   vqmmc-supply = _s3;  /* IO line */
-   vmmc-supply = _sdio;/* card's power */
+   vqmmc-supply = <_s3>;/* IO line */
+   vmmc-supply = <_sdio>;  /* card's power */
 
#address-cells = <1>;
#size-cells = <0>;
@@ -781,7 +788,7 @@
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <>;
-   interrupts = ;
+   interrupts = ;
interrupt-names = "host-wake";
brcm,drive-strength = <5>;
pinctrl-names = "default";
diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig
index db98926b627a..2f81a2ed0da6 100644
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig
@@ -14,9 +14,10 @@ CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -32,19 +33,28 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
+CONFIG_SCSI=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
@@ -61,5 +71,4 @@ CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_RTL8152=y
 CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
-- 
2.43.2

[PATCH 21/31] rockchip: rk3399-evb: Sync device tree from linux v6.8

[Jonas Karlman]

Sync rk3399-evb device tree from linux v6.8.

Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.

Remove CONFIG_NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on
cpuid read from eFUSE.

Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.

Remove SPL_TINY_MEMSET=y to use full memset in SPL.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3399-evb-u-boot.dtsi | 11 +--
 arch/arm/dts/rk3399-evb.dts |  3 ++-
 configs/evb-rk3399_defconfig|  6 +++---
 3 files changed, 6 insertions(+), 14 deletions(-)

diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi 
b/arch/arm/dts/rk3399-evb-u-boot.dtsi
index 9df4a02c3e74..68d86194cc4c 100644
--- a/arch/arm/dts/rk3399-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi
@@ -12,14 +12,6 @@
};
 };
 
- {
-   bootph-all;
-};
-
- {
-   bootph-all;
-};
-
  {
status = "okay";
 };
@@ -41,10 +33,9 @@
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
-   cd-gpios = < 7 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <15000>;
pinctrl-names = "default";
-   pinctrl-0 = <_clk _cmd _bus4>;
+   pinctrl-0 = <_clk _cmd _cd _bus4>;
status = "okay";
 };
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index 7b717ebec8ff..55eca7a50a1f 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -12,6 +12,7 @@
compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
 
aliases {
+   ethernet0 = 
mmc0 = 
};
 
@@ -55,7 +56,7 @@
};
 
edp_panel: edp-panel {
-   compatible ="lg,lp079qx1-sp0v";
+   compatible = "lg,lp079qx1-sp0v";
backlight = <>;
enable-gpios = < RK_PB5 GPIO_ACTIVE_HIGH>;
power-supply = <_s0>;
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index afb79987464f..334259f73eb2 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -15,7 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -30,7 +30,6 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MMC_HS400_SUPPORT=y
@@ -39,6 +38,8 @@ CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -69,5 +70,4 @@ CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200
 CONFIG_DISPLAY_ROCKCHIP_MIPI=y
-CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
-- 
2.43.2

[PATCH 20/31] rockchip: rk3399-leez: Sync device tree from linux v6.8

[Jonas Karlman]

Sync rk3399-leez-p710 device tree from linux v6.8.

Add DM_RESET=y to support reset signals.

Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.

Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.

Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.

Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.

Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.

Remove SPL_TINY_MEMSET=y to use full memset in SPL.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3399-leez-p710.dts |  8 +---
 configs/leez-rk3399_defconfig | 10 --
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/rk3399-leez-p710.dts 
b/arch/arm/dts/rk3399-leez-p710.dts
index 7c93f840bc64..cb69e2145fa9 100644
--- a/arch/arm/dts/rk3399-leez-p710.dts
+++ b/arch/arm/dts/rk3399-leez-p710.dts
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 #include 
+#include 
 #include 
 #include "rk3399.dtsi"
 #include "rk3399-opp.dtsi"
@@ -14,6 +15,7 @@
compatible = "leez,p710", "rockchip,rk3399";
 
aliases {
+   ethernet0 = 
mmc0 = 
mmc1 = 
mmc2 = 
@@ -55,7 +57,7 @@
regulator-boot-on;
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
-   vim-supply = <_sys>;
+   vin-supply = <_sys>;
};
 
vcc3v3_sys: vcc3v3-sys {
@@ -102,12 +104,12 @@
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = < 0 25000 1>;
+   pwm-supply = <_sys>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <80>;
regulator-max-microvolt = <140>;
-   vin-supply = <_sys>;
};
 };
 
@@ -509,7 +511,7 @@
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <>;
-   interrupts = ;
+   interrupts = ;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <_host_wake_l>;
diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig
index 13453e523444..903125aa5c1d 100644
--- a/configs/leez-rk3399_defconfig
+++ b/configs/leez-rk3399_defconfig
@@ -5,6 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-leez-p710"
+CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_TARGET_EVB_RK3399=y
 CONFIG_DEBUG_UART_BASE=0xFF1A
@@ -13,7 +14,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -30,12 +31,18 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
@@ -57,5 +64,4 @@ CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_RTL8152=y
 CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
-- 
2.43.2

[PATCH 19/31] rockchip: rk3399-eaidk-610: Sync device tree from linux v6.8

[Jonas Karlman]

Sync rk3399-eaidk-610 device tree from linux v6.8.

Add DM_RESET=y to support reset signals.

Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.

Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.

Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.

Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.

Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.

Remove REGULATOR_PWM=y, board does not use pwm-regulator compatible.

Remove SPL_TINY_MEMSET=y to use full memset in SPL.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3399-eaidk-610.dts  |  3 ++-
 configs/eaidk-610-rk3399_defconfig | 11 ---
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/rk3399-eaidk-610.dts 
b/arch/arm/dts/rk3399-eaidk-610.dts
index d1f343345f67..173da81fc231 100644
--- a/arch/arm/dts/rk3399-eaidk-610.dts
+++ b/arch/arm/dts/rk3399-eaidk-610.dts
@@ -15,6 +15,7 @@
compatible = "openailab,eaidk-610", "rockchip,rk3399";
 
aliases {
+   ethernet0 = 
mmc0 = 
mmc1 = 
mmc2 = 
@@ -773,7 +774,7 @@
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <>;
-   interrupts = ;
+   interrupts = ;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <_host_wake_l>;
diff --git a/configs/eaidk-610-rk3399_defconfig 
b/configs/eaidk-610-rk3399_defconfig
index eba6f90c605b..d9cde9ecced5 100644
--- a/configs/eaidk-610-rk3399_defconfig
+++ b/configs/eaidk-610-rk3399_defconfig
@@ -5,6 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-eaidk-610"
+CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_TARGET_EVB_RK3399=y
 CONFIG_DEBUG_UART_BASE=0xFF1A
@@ -13,7 +14,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-eaidk-610.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -30,14 +31,19 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_BAUDRATE=150
@@ -50,5 +56,4 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
-CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
-- 
2.43.2

[PATCH 18/31] rockchip: rk3399-rock-pi-n10: Sync device tree from linux v6.8

[Jonas Karlman]

Sync rk3399-rock-pi-n10 related device tree from linux v6.8.

Remove SPL_GPIO=y, board does not use gpio in SPL.

Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.

Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.

Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.

Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.

Remove REGULATOR_PWM=y, board does not use pwm-regulator compatible.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3288-vmarc-som.dtsi| 48 +++
 arch/arm/dts/rk3399pro-vmarc-som.dtsi | 20 ++--
 .../dts/rockchip-radxa-dalang-carrier.dtsi| 21 
 configs/rock-pi-n10-rk3399pro_defconfig   |  8 ++--
 4 files changed, 89 insertions(+), 8 deletions(-)

diff --git a/arch/arm/dts/rk3288-vmarc-som.dtsi 
b/arch/arm/dts/rk3288-vmarc-som.dtsi
index 717cb3dc816e..793951655b73 100644
--- a/arch/arm/dts/rk3288-vmarc-som.dtsi
+++ b/arch/arm/dts/rk3288-vmarc-som.dtsi
@@ -231,11 +231,43 @@
};
 };
 
+ {
+   clock-frequency = <40>;
+   status = "okay";
+
+   hym8563: rtc@51 {
+   compatible = "haoyu,hym8563";
+   reg = <0x51>;
+   interrupt-parent = <>;
+   interrupts = ;
+   #clock-cells = <0>;
+   clock-output-names = "hym8563";
+   pinctrl-names = "default";
+   pinctrl-0 = <_int>;
+   };
+};
+
  {
status = "okay";
 };
 
+_domains {
+   bb-supply = <_io>;
+   flash0-supply = <_flash>;
+   gpio1830-supply = <_18>;
+   gpio30-supply = <_io>;
+   sdcard-supply = <_sd>;
+   wifi-supply = <_wl>;
+   status = "okay";
+};
+
  {
+   hym8563 {
+   hym8563_int: hym8563-int {
+   rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO _pull_up>;
+   };
+   };
+
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
drive-strength = <8>;
};
@@ -251,6 +283,12 @@
};
};
 
+   sdio-pwrseq {
+   wifi_enable_h: wifi-enable-h {
+   rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO _pull_none>;
+   };
+   };
+
sdmmc {
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins =
@@ -282,6 +320,16 @@
};
 };
 
+_pwrseq {
+   /*
+* On the module itself this is one of these (depending
+* on the actual card populated):
+* - SDIO_RESET_L_WL_REG_ON
+* - PDN (power down when low)
+*/
+   reset-gpios = < RK_PD4 GPIO_ACTIVE_LOW>;  /* WIFI_REG_ON */
+};
+
  {
status = "okay";
 };
diff --git a/arch/arm/dts/rk3399pro-vmarc-som.dtsi 
b/arch/arm/dts/rk3399pro-vmarc-som.dtsi
index e1cb426f2aa5..8823c924dc1d 100644
--- a/arch/arm/dts/rk3399pro-vmarc-som.dtsi
+++ b/arch/arm/dts/rk3399pro-vmarc-som.dtsi
@@ -13,8 +13,9 @@
compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro";
 
aliases {
-   mmc0 = 
-   mmc1 = 
+   ethernet0 = 
+   mmc0 = 
+   mmc1 = 
};
 
vcc3v3_pcie: vcc-pcie-regulator {
@@ -297,11 +298,10 @@
clock-frequency = <40>;
status = "okay";
 
-   hym8563: hym8563@51 {
+   hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
-   clock-frequency = <32768>;
clock-output-names = "hym8563";
pinctrl-names = "default";
pinctrl-0 = <_int>;
@@ -347,7 +347,7 @@
 
pcie {
pcie_pwr: pcie-pwr {
-   rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO _pull_up>;
+   rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO _pull_up>;
};
};
 
@@ -381,6 +381,16 @@
pmu1830-supply = <_1v8>;
 };
 
+_pwrseq {
+   /*
+* On the module itself this is one of these (depending
+* on the actual card populated):
+* - SDIO_RESET_L_WL_REG_ON
+* - PDN (power down when low)
+*/
+   reset-gpios = < RK_PD3 GPIO_ACTIVE_LOW>;
+};
+
  {
bus-width = <8>;
mmc-hs400-1_8v;
diff --git a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi 
b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi
index 26b53eac4706..da1d548b7330 100644
--- a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi
+++ b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi
@@ -15,6 +15,14 @@
#clock-cells = <0>;
};
 
+   sdio_pwrseq: sdio-pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   clocks = <>;
+   clock-names = "ext_clock";
+   pinctrl-names = "default";
+   pinctrl-0 = <_enable_h>;
+   };
+
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
@@ -78,6 +86,19 @@
status = "okay";
 };
 
+ {
+   

[PATCH 17/31] rockchip: rk3399-puma: Sync DT from linux v6.8

[Jonas Karlman]

Sync rk3399-puma related device tree from linux v6.8.

SPL_MAX_SIZE is not adjusted to the now common 0x4 (256 KiB) due to
TPL+SPL combined (idbloader.img) is limited to max 224 KiB because of:

  SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200

Because FIT payload is located at sector 0x200 instead of the more
Rockchip common 0x4000, TPL+SPL cannot take up more than 224 KiB:

  (0x200 - 64) x 512 = 0x38000 (224 KiB)

Also adjust SPL_PAD_TO to match the 0x200 sector offset.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 20 ++
 arch/arm/dts/rk3399-puma-haikou.dts | 42 ++---
 arch/arm/dts/rk3399-puma.dtsi   | 17 -
 configs/puma-rk3399_defconfig   |  2 +-
 4 files changed, 57 insertions(+), 24 deletions(-)

diff --git a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi 
b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
index f48d395f972a..65340f98d595 100644
--- a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
@@ -30,18 +30,6 @@
aliases {
spi5 = 
};
-
-   vdd_log: vdd-log {
-   compatible = "pwm-regulator";
-   pwms = < 0 25000 1>;
-   regulator-name = "vdd_log";
-   regulator-always-on;
-   regulator-boot-on;
-   regulator-min-microvolt = <80>;
-   regulator-max-microvolt = <140>;
-   regulator-init-microvolt = <95>;
-   vin-supply = <_sys>;
-   };
 };
 
  {
@@ -87,10 +75,6 @@
bootph-all;
 };
 
-_pin_hog {
-   bootph-all;
-};
-
  {
bootph-pre-ram;
bootph-some-ram;
@@ -111,3 +95,7 @@
 _xfer {
bootph-all;
 };
+
+_log {
+   regulator-init-microvolt = <95>;
+};
diff --git a/arch/arm/dts/rk3399-puma-haikou.dts 
b/arch/arm/dts/rk3399-puma-haikou.dts
index 115c14c0a3c6..18a98c4648ea 100644
--- a/arch/arm/dts/rk3399-puma-haikou.dts
+++ b/arch/arm/dts/rk3399-puma-haikou.dts
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 #include "rk3399-puma.dtsi"
+#include 
 
 / {
model = "Theobroma Systems RK3399-Q7 SoM";
@@ -18,6 +19,38 @@
stdout-path = "serial0:115200n8";
};
 
+   gpio-keys {
+   compatible = "gpio-keys";
+   pinctrl-0 = <_keys_pin>;
+   pinctrl-names = "default";
+
+   button-batlow-n {
+   gpios = < RK_PB2 GPIO_ACTIVE_LOW>;
+   label = "BATLOW#";
+   linux,code = ;
+   };
+
+   button-slp-btn-n {
+   gpios = < RK_PB3 GPIO_ACTIVE_LOW>;
+   label = "SLP_BTN#";
+   linux,code = ;
+   };
+
+   button-wake-n {
+   gpios = < RK_PB1 GPIO_ACTIVE_LOW>;
+   label = "WAKE#";
+   linux,code = ;
+   wakeup-source;
+   };
+
+   switch-lid-btn-n {
+   gpios = < RK_PA4 GPIO_ACTIVE_LOW>;
+   label = "LID_BTN#";
+   linux,code = ;
+   linux,input-type = ;
+   };
+   };
+
leds {
pinctrl-0 = <_led_pin>, <_card_led_pin>;
 
@@ -165,11 +198,8 @@
 };
 
  {
-   pinctrl-names = "default";
-   pinctrl-0 = <_pin_hog>;
-
-   hog {
-   haikou_pin_hog: haikou-pin-hog {
+   buttons {
+   haikou_keys_pin: haikou-keys-pin {
rockchip,pins =
  /* LID_BTN */
  <0 RK_PA4 RK_FUNC_GPIO _pull_up>,
@@ -177,7 +207,7 @@
  <0 RK_PB2 RK_FUNC_GPIO _pull_up>,
  /* SLP_BTN# */
  <0 RK_PB3 RK_FUNC_GPIO _pull_up>,
- /* BIOS_DISABLE# */
+ /* WAKE# */
  <0 RK_PB1 RK_FUNC_GPIO _pull_up>;
};
};
diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi
index aa3e21bd6c8f..c08e69391c01 100644
--- a/arch/arm/dts/rk3399-puma.dtsi
+++ b/arch/arm/dts/rk3399-puma.dtsi
@@ -9,6 +9,7 @@
 
 / {
aliases {
+   ethernet0 = 
mmc0 = 
};
 
@@ -27,7 +28,7 @@
 
extcon_usb3: extcon-usb3 {
compatible = "linux,extcon-usb-gpio";
-   id-gpio = < RK_PC2 GPIO_ACTIVE_HIGH>;
+   id-gpios = < RK_PC2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <_id>;
};
@@ -119,6 +120,20 @@
drive-impedance-ohm = <33>;
 };
 
+ {
+   /*
+* The BIOS_DISABLE hog is a feedback pin for the actual status of the
+* signal. This usually represents the state of a switch on the 
baseboard.
+* The pin has a 10k pull-up resistor connected, so no pull-up setting 
is needed.
+ 

[PATCH 16/31] rockchip: rk3399-gru: Sync device tree from linux v6.8

[Jonas Karlman]

Sync rk3399-gru related device tree from linux v6.8.

The spi_flash symbol is no longer part of upstream DT, it is re-defined
to allow exising use in related u-boot.dtsi-files.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3399-gru-bob.dts |   8 +-
 arch/arm/dts/rk3399-gru-chromebook.dtsi | 200 +++-
 arch/arm/dts/rk3399-gru-kevin.dts   |   3 +-
 arch/arm/dts/rk3399-gru-u-boot.dtsi |  10 +-
 arch/arm/dts/rk3399-gru.dtsi|  52 +-
 5 files changed, 254 insertions(+), 19 deletions(-)

diff --git a/arch/arm/dts/rk3399-gru-bob.dts b/arch/arm/dts/rk3399-gru-bob.dts
index e6c1c94c8d69..1cba1d857c96 100644
--- a/arch/arm/dts/rk3399-gru-bob.dts
+++ b/arch/arm/dts/rk3399-gru-bob.dts
@@ -16,6 +16,7 @@
 "google,bob-rev7", "google,bob-rev6",
 "google,bob-rev5", "google,bob-rev4",
 "google,bob", "google,gru", "rockchip,rk3399";
+   chassis-type = "convertible";
 
edp_panel: edp-panel {
compatible = "boe,nv101wxmn51";
@@ -69,7 +70,7 @@
  {
status = "okay";
 
-   cr50@0 {
+   tpm@0 {
compatible = "google,cr50";
reg = <0>;
interrupt-parent = <>;
@@ -87,3 +88,8 @@
};
};
 };
+
+_host_wake_l {
+   /* Kevin has an external pull up, but Bob does not. */
+   rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO _pull_up>;
+};
diff --git a/arch/arm/dts/rk3399-gru-chromebook.dtsi 
b/arch/arm/dts/rk3399-gru-chromebook.dtsi
index 1384dabbdf40..cacbad35cfc8 100644
--- a/arch/arm/dts/rk3399-gru-chromebook.dtsi
+++ b/arch/arm/dts/rk3399-gru-chromebook.dtsi
@@ -198,7 +198,6 @@
power-supply = <_disp>;
pinctrl-names = "default";
pinctrl-0 = <_en>;
-   pwm-delay-us = <1>;
};
 
gpio_keys: gpio-keys {
@@ -206,7 +205,7 @@
pinctrl-names = "default";
pinctrl-0 = <_host_wake_l>;
 
-   wake_on_bt: wake-on-bt {
+   wake_on_bt: key-wake-on-bt {
label = "Wake-on-Bluetooth";
gpios = < 3 GPIO_ACTIVE_LOW>;
linux,code = ;
@@ -234,9 +233,24 @@
extcon = <_extcon0>, <_extcon1>;
 };
 
+ {
+   center-supply = <_centerlogic>;
+   rockchip,pd-idle-dis-freq-hz = <8>;
+   rockchip,sr-idle-dis-freq-hz = <8>;
+   rockchip,sr-mc-gate-idle-dis-freq-hz = <8>;
+};
+
  {
status = "okay";
 
+   /*
+* eDP PHY/clk don't sync reliably at anything other than 24 MHz. Only
+* set this here, because rk3399-gru.dtsi ensures we can generate this
+* off GPLL=600MHz, whereas some other RK3399 boards may not.
+*/
+   assigned-clocks = < PCLK_EDP>;
+   assigned-clock-rates = <2400>;
+
ports {
edp_out: port@1 {
reg = <1>;
@@ -251,6 +265,182 @@
};
 };
 
+ {
+   gpio-line-names = /* GPIO0 A 0-7 */
+ "AP_RTC_CLK_IN",
+ "EC_AP_INT_L",
+ "PP1800_AUDIO_EN",
+ "BT_HOST_WAKE_L",
+ "WLAN_MODULE_PD_L",
+ "H1_INT_OD_L",
+ "CENTERLOGIC_DVS_PWM",
+ "",
+
+ /* GPIO0 B 0-4 */
+ "WIFI_HOST_WAKE_L",
+ "PMUIO2_33_18_L",
+ "PP1500_EN",
+ "AP_EC_WARM_RESET_REQ",
+ "PP3000_EN";
+};
+
+ {
+   gpio-line-names = /* GPIO1 A 0-7 */
+ "",
+ "",
+ "SPK_PA_EN",
+ "",
+ "TRACKPAD_INT_L",
+ "AP_EC_S3_S0_L",
+ "AP_EC_OVERTEMP",
+ "AP_SPI_FLASH_MISO",
+
+ /* GPIO1 B 0-7 */
+ "AP_SPI_FLASH_MOSI_R",
+ "AP_SPI_FLASH_CLK_R",
+ "AP_SPI_FLASH_CS_L_R",
+ "WLAN_MODULE_RESET_L",
+ "WIFI_DISABLE_L",
+ "MIC_INT",
+ "",
+ "AP_I2C_DVS_SDA",
+
+ /* GPIO1 C 0-7 */
+ "AP_I2C_DVS_SCL",
+ "AP_BL_EN",
+ /*
+  * AP_FLASH_WP is crossystem ABI. Schematics call it
+  * AP_FW_WP or CPU1_FW_WP, depending on the variant.
+  */
+ "AP_FLASH_WP",
+ "LITCPU_DVS_PWM",
+ "AP_I2C_AUDIO_SDA",
+ "AP_I2C_AUDIO_SCL",
+ "",
+ 

[PATCH 10/31] rockchip: rk3399: Fix loading FIT from SD-card when booting from eMMC

[Jonas Karlman]

When RK3399 boards run SPL from eMMC and fail to load FIT from eMMC due
to it being missing or checksum validation fails there can be a fallback
to read FIT from SD-card. However, without proper pinctrl configuration
reading FIT from SD-card may fail:

  U-Boot SPL 2024.04-rc4 (Mar 17 2024 - 22:54:45 +)
  Trying to boot from MMC2
  mmc_load_image_raw_sector: mmc block read error
  Trying to boot from MMC2
  mmc_load_image_raw_sector: mmc block read error
  Trying to boot from MMC1
  Card did not respond to voltage select! : -110
  mmc_init: -95, time 12
  spl: mmc init failed with error: -95
  SPL: failed to boot from all boot devices (err=-6)
  ### ERROR ### Please RESET the board ###

Fix this by tagging related sdhci and sdmmc pinctrl nodes with bootph
props. Also sort and move common nodes shared by all boards to the SoC
u-boot.dtsi. Finally imply the SPL_DM_SEQ_ALIAS Kconfig option to enable
it on all RK3399 boards.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3399-evb-u-boot.dtsi   |  1 -
 arch/arm/dts/rk3399-ficus-u-boot.dtsi |  8 ++
 arch/arm/dts/rk3399-gru-u-boot.dtsi   | 24 ++
 arch/arm/dts/rk3399-nanopi4-u-boot.dtsi   | 12 +++
 arch/arm/dts/rk3399-orangepi-u-boot.dtsi  | 12 +++
 arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi  | 17 -
 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi |  2 -
 arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi   | 19 ++---
 arch/arm/dts/rk3399-roc-pc-u-boot.dtsi| 41 ++
 arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi  |  8 ++
 arch/arm/dts/rk3399-rock960-u-boot.dtsi   |  8 ++
 arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 17 -
 arch/arm/dts/rk3399-u-boot.dtsi   | 75 +++
 arch/arm/mach-rockchip/Kconfig|  1 +
 configs/chromebook_bob_defconfig  |  1 -
 configs/chromebook_kevin_defconfig|  1 -
 configs/eaidk-610-rk3399_defconfig|  2 +-
 configs/evb-rk3399_defconfig  |  2 +-
 configs/ficus-rk3399_defconfig|  2 +-
 configs/firefly-rk3399_defconfig  |  2 +-
 configs/khadas-edge-captain-rk3399_defconfig  |  2 +-
 configs/khadas-edge-rk3399_defconfig  |  2 +-
 configs/khadas-edge-v-rk3399_defconfig|  2 +-
 configs/leez-rk3399_defconfig |  2 +-
 configs/nanopc-t4-rk3399_defconfig|  4 +-
 configs/nanopi-m4-2gb-rk3399_defconfig|  4 +-
 configs/nanopi-m4-rk3399_defconfig|  4 +-
 configs/nanopi-m4b-rk3399_defconfig   |  4 +-
 configs/nanopi-neo4-rk3399_defconfig  |  4 +-
 configs/nanopi-r4s-rk3399_defconfig   |  4 +-
 configs/orangepi-rk3399_defconfig |  4 +-
 configs/pinebook-pro-rk3399_defconfig |  5 +-
 configs/pinephone-pro-rk3399_defconfig|  3 +-
 configs/puma-rk3399_defconfig |  1 -
 configs/roc-pc-mezzanine-rk3399_defconfig |  4 +-
 configs/roc-pc-rk3399_defconfig   |  4 +-
 configs/rock-4c-plus-rk3399_defconfig |  2 +-
 configs/rock-4se-rk3399_defconfig |  2 +-
 configs/rock-pi-4-rk3399_defconfig|  3 +-
 configs/rock-pi-4c-rk3399_defconfig   |  2 +-
 configs/rock-pi-n10-rk3399pro_defconfig   |  2 +-
 configs/rock960-rk3399_defconfig  |  2 +-
 configs/rockpro64-rk3399_defconfig|  5 +-
 43 files changed, 243 insertions(+), 83 deletions(-)

diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi 
b/arch/arm/dts/rk3399-evb-u-boot.dtsi
index 796ac9642399..9df4a02c3e74 100644
--- a/arch/arm/dts/rk3399-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi
@@ -38,7 +38,6 @@
 };
 
  {
-   bootph-all;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
diff --git a/arch/arm/dts/rk3399-ficus-u-boot.dtsi 
b/arch/arm/dts/rk3399-ficus-u-boot.dtsi
index 67b63a835238..d821cabfaa67 100644
--- a/arch/arm/dts/rk3399-ficus-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-ficus-u-boot.dtsi
@@ -5,3 +5,11 @@
 
 #include "rk3399-u-boot.dtsi"
 #include "rk3399-sdram-ddr3-1600.dtsi"
+
+_pull_none_18ma {
+   bootph-pre-ram;
+};
+
+_pull_up_8ma {
+   bootph-pre-ram;
+};
diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi 
b/arch/arm/dts/rk3399-gru-u-boot.dtsi
index b1604a6872c0..0cc40eb6d6f6 100644
--- a/arch/arm/dts/rk3399-gru-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi
@@ -54,6 +54,30 @@
enable-gpios = < 2 GPIO_ACTIVE_HIGH>;
 };
 
+ {
+   /delete-property/ bootph-pre-ram;
+};
+
+ {
+   /delete-property/ bootph-pre-ram;
+};
+
+_bus4 {
+   /delete-property/ bootph-pre-ram;
+};
+
+_cd {
+   /delete-property/ bootph-pre-ram;
+};
+
+_clk {
+   /delete-property/ bootph-pre-ram;
+};
+
+_cmd {
+   /delete-property/ bootph-pre-ram;
+};
+
  {
spi-activate-delay = <100>;
spi-max-frequency = <300>;
diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi 
b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
index a126bbaf086f..e0d7a518dfc2 100644

[PATCH 15/31] rockchip: rk3399: Sync soc device tree from linux v6.8

[Jonas Karlman]

Sync RK3399 SoC common .dtsi-files from linux v6.8.

The ethernet0 alias is removed from rk3399.dtsi in this patch, it will
be restored in board specific .dts-files. There is no other intended
change with this patch.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3399-op1-opp.dtsi  |  31 +-
 arch/arm/dts/rk3399-opp.dtsi  |   6 +-
 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi |   4 -
 arch/arm/dts/rk3399-u-boot.dtsi   |  52 ++--
 arch/arm/dts/rk3399.dtsi  | 289 --
 5 files changed, 308 insertions(+), 74 deletions(-)

diff --git a/arch/arm/dts/rk3399-op1-opp.dtsi b/arch/arm/dts/rk3399-op1-opp.dtsi
index 69cc9b05baa5..783120e9cebe 100644
--- a/arch/arm/dts/rk3399-op1-opp.dtsi
+++ b/arch/arm/dts/rk3399-op1-opp.dtsi
@@ -4,7 +4,7 @@
  */
 
 / {
-   cluster0_opp: opp-table0 {
+   cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
 
@@ -39,7 +39,7 @@
};
};
 
-   cluster1_opp: opp-table1 {
+   cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
 
@@ -82,7 +82,7 @@
};
};
 
-   gpu_opp_table: opp-table2 {
+   gpu_opp_table: opp-table-2 {
compatible = "operating-points-v2";
 
opp00 {
@@ -110,6 +110,27 @@
opp-microvolt = <1075000>;
};
};
+
+   dmc_opp_table: opp-table-3 {
+   compatible = "operating-points-v2";
+
+   opp00 {
+   opp-hz = /bits/ 64 <4>;
+   opp-microvolt = <90>;
+   };
+   opp01 {
+   opp-hz = /bits/ 64 <66600>;
+   opp-microvolt = <90>;
+   };
+   opp02 {
+   opp-hz = /bits/ 64 <8>;
+   opp-microvolt = <90>;
+   };
+   opp03 {
+   opp-hz = /bits/ 64 <92800>;
+   opp-microvolt = <925000>;
+   };
+   };
 };
 
 _l0 {
@@ -136,6 +157,10 @@
operating-points-v2 = <_opp>;
 };
 
+ {
+   operating-points-v2 = <_opp_table>;
+};
+
  {
operating-points-v2 = <_opp_table>;
 };
diff --git a/arch/arm/dts/rk3399-opp.dtsi b/arch/arm/dts/rk3399-opp.dtsi
index da41cd81ebb7..fee5e7111279 100644
--- a/arch/arm/dts/rk3399-opp.dtsi
+++ b/arch/arm/dts/rk3399-opp.dtsi
@@ -4,7 +4,7 @@
  */
 
 / {
-   cluster0_opp: opp-table0 {
+   cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
 
@@ -35,7 +35,7 @@
};
};
 
-   cluster1_opp: opp-table1 {
+   cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
 
@@ -74,7 +74,7 @@
};
};
 
-   gpu_opp_table: opp-table2 {
+   gpu_opp_table: opp-table-2 {
compatible = "operating-points-v2";
 
opp00 {
diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi 
b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
index b8f95b86d86b..dcfcec4f3072 100644
--- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
@@ -6,10 +6,6 @@
 #include "rk3399-u-boot.dtsi"
 #include "rk3399-sdram-lpddr4-100.dtsi"
 
- {
-   status = "okay";
-};
-
  {
max-frequency = <2500>;
 };
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index adb64d17e040..d2648abd0a44 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -2,8 +2,6 @@
 /*
  * Copyright (C) 2019 Jagan Teki 
  */
-#define USB_CLASS_HUB  9
-
 #include "rockchip-u-boot.dtsi"
 
 / {
@@ -24,44 +22,11 @@
reg = <0x0 0xff62 0x0 0x100>;
};
 
-   dfi: dfi@ff63 {
-   bootph-all;
-   reg = <0x00 0xff63 0x00 0x4000>;
-   compatible = "rockchip,rk3399-dfi";
-   rockchip,pmu = <>;
-   clocks = < PCLK_DDR_MON>;
-   clock-names = "pclk_ddr_mon";
-   };
-
-   rng: rng@ff8b8000 {
-   compatible = "rockchip,rk3399-crypto";
-   reg = <0x0 0xff8b8000 0x0 0x1000>;
-   status = "okay";
-   };
-
-   dmc: dmc {
-   bootph-all;
-   compatible = "rockchip,rk3399-dmc";
-   devfreq-events = <>;
-   interrupts = ;
-   clocks = < SCLK_DDRC>;
-   clock-names = "dmc_clk";
-   reg = <0x0 0xffa8 0x0 0x0800
-  0x0 0xffa80800 0x0 0x1800
-  0x0 0xffa82000 0x0 0x2000
-  0x0 0xffa84000 0x0 0x1000
-  0x0 0xffa88000 0x0 0x0800
-  0x0 0xffa88800 0x0 

[PATCH 14/31] clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support

[Jonas Karlman]

The SCLK_USB3OTGx_REF clocks is used as reference clock for USB3 block.

Add simple support to get rate of SCLK_USB3OTGx_REF clocks to fix
reference clock period configuration.

Also replace use of 2400 with the OSC_HZ constant.

Signed-off-by: Jonas Karlman 
---
 drivers/clk/rockchip/clk_rk3399.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3399.c 
b/drivers/clk/rockchip/clk_rk3399.c
index 29b01abeca06..6408c5d0aa6a 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -956,7 +956,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
case SCLK_UART1:
case SCLK_UART2:
case SCLK_UART3:
-   return 2400;
+   case SCLK_USB3OTG0_REF:
+   case SCLK_USB3OTG1_REF:
+   return OSC_HZ;
case PCLK_HDMI_CTRL:
break;
case DCLK_VOP0:
-- 
2.43.2

[PATCH 13/31] clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock

[Jonas Karlman]

rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the
SCLK_PCIEPHY_REF clock.

The existing enable/disable ops for SCLK_PCIEPHY_REF already handles
setting correct parent once the clock gets enabled. And 100 MHz is the
default rate used for this clock.

Add dummy support for setting parent, getting and setting clock rate of
the SCLK_PCIEPHY_REF clock to allow use of PCIe on affected boards.

Signed-off-by: Jonas Karlman 
---
 drivers/clk/rockchip/clk_rk3399.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3399.c 
b/drivers/clk/rockchip/clk_rk3399.c
index 5934771b4096..29b01abeca06 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -972,6 +972,7 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
case ACLK_GIC_PRE:
case PCLK_DDR:
case ACLK_VDU:
+   case SCLK_PCIEPHY_REF:
break;
case PCLK_ALIVE:
case PCLK_WDT:
@@ -1063,6 +1064,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong 
rate)
case ACLK_GIC_PRE:
case PCLK_DDR:
case ACLK_VDU:
+   case SCLK_PCIEPHY_REF:
return 0;
default:
log_debug("Unknown clock %lu\n", clk->id);
@@ -1114,6 +1116,8 @@ static int __maybe_unused rk3399_clk_set_parent(struct 
clk *clk,
switch (clk->id) {
case SCLK_RMII_SRC:
return rk3399_gmac_set_parent(clk, parent);
+   case SCLK_PCIEPHY_REF:
+   return 0;
}
 
debug("%s: unsupported clk %ld\n", __func__, clk->id);
-- 
2.43.2

[PATCH 12/31] clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock

[Jonas Karlman]

rk3399.dtsi from linux v5.19 and newer try to set VDU clock rate to
400 MHz using an assigned-clock-rates prop of the CRU node.

U-Boot does not use or need this clock so add dummy support for getting
and setting ACLK_VDU clock rate to allow CRU driver to be loaded with an
updated rk3399.dtsi.

Signed-off-by: Jonas Karlman 
---
 drivers/clk/rockchip/clk_rk3399.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3399.c 
b/drivers/clk/rockchip/clk_rk3399.c
index f0ce54067f8c..5934771b4096 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -971,6 +971,7 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
case ACLK_HDCP:
case ACLK_GIC_PRE:
case PCLK_DDR:
+   case ACLK_VDU:
break;
case PCLK_ALIVE:
case PCLK_WDT:
@@ -1061,6 +1062,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong 
rate)
case ACLK_HDCP:
case ACLK_GIC_PRE:
case PCLK_DDR:
+   case ACLK_VDU:
return 0;
default:
log_debug("Unknown clock %lu\n", clk->id);
-- 
2.43.2

[PATCH 11/31] clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC

[Jonas Karlman]

Sync rk3399-cru.h with one from linux v6.2+ and fix use of the
SCLK_DDRCLK name that was only used by U-Boot.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3399-u-boot.dtsi|  2 +-
 drivers/clk/rockchip/clk_rk3399.c  |  2 +-
 include/dt-bindings/clock/rk3399-cru.h | 30 ++
 3 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index 69e6b808a69b..adb64d17e040 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -44,7 +44,7 @@
compatible = "rockchip,rk3399-dmc";
devfreq-events = <>;
interrupts = ;
-   clocks = < SCLK_DDRCLK>;
+   clocks = < SCLK_DDRC>;
clock-names = "dmc_clk";
reg = <0x0 0xffa8 0x0 0x0800
   0x0 0xffa80800 0x0 0x1800
diff --git a/drivers/clk/rockchip/clk_rk3399.c 
b/drivers/clk/rockchip/clk_rk3399.c
index 80f65a237e8e..f0ce54067f8c 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1049,7 +1049,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong 
rate)
 * return 0 to satisfy clk_set_defaults during device probe.
 */
return 0;
-   case SCLK_DDRCLK:
+   case SCLK_DDRC:
ret = rk3399_ddr_set_clk(priv->cru, rate);
break;
case PCLK_EFUSE1024NS:
diff --git a/include/dt-bindings/clock/rk3399-cru.h 
b/include/dt-bindings/clock/rk3399-cru.h
index 211faf8fa891..39169d94a44e 100644
--- a/include/dt-bindings/clock/rk3399-cru.h
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -1,6 +1,7 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
 /*
  * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng 
  */
 
 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
@@ -121,16 +122,17 @@
 #define SCLK_DPHY_RX0_CFG  165
 #define SCLK_RMII_SRC  166
 #define SCLK_PCIEPHY_REF100M   167
-#define SCLK_USBPHY0_480M_SRC  168
-#define SCLK_USBPHY1_480M_SRC  169
-#define SCLK_DDRCLK170
-#define SCLK_TESTOUT2  171
+#define SCLK_DDRC  168
+#define SCLK_TESTCLKOUT1   169
+#define SCLK_TESTCLKOUT2   170
 
 #define DCLK_VOP0  180
 #define DCLK_VOP1  181
 #define DCLK_VOP0_DIV  182
 #define DCLK_VOP1_DIV  183
 #define DCLK_M0_PERILP 184
+#define DCLK_VOP0_FRAC 185
+#define DCLK_VOP1_FRAC 186
 
 #define FCLK_CM0S  190
 
@@ -545,8 +547,8 @@
 #define SRST_H_PERILP0 171
 #define SRST_H_PERILP0_NOC 172
 #define SRST_ROM   173
-#define SRST_CRYPTO_S  174
-#define SRST_CRYPTO_M  175
+#define SRST_CRYPTO0_S 174
+#define SRST_CRYPTO0_M 175
 
 /* cru_softrst_con11 */
 #define SRST_P_DCF 176
@@ -554,7 +556,7 @@
 #define SRST_CM0S  178
 #define SRST_CM0S_DBG  179
 #define SRST_CM0S_PO   180
-#define SRST_CRYPTO181
+#define SRST_CRYPTO0   181
 #define SRST_P_PERILP1_SGRF182
 #define SRST_P_PERILP1_GRF 183
 #define SRST_CRYPTO1_S 184
@@ -592,13 +594,13 @@
 #define SRST_P_SPI0214
 #define SRST_P_SPI1215
 #define SRST_P_SPI2216
-#define SRST_P_SPI4217
-#define SRST_P_SPI5218
+#define SRST_P_SPI3217
+#define SRST_P_SPI4218
 #define SRST_SPI0  219
 #define SRST_SPI1  220
 #define SRST_SPI2  221
-#define SRST_SPI4  222
-#define SRST_SPI5  223
+#define SRST_SPI3  222
+#define SRST_SPI4  223
 
 /* cru_softrst_con14 */
 #define SRST_I2S0_8CH  224
@@ -720,8 +722,8 @@
 #define SRST_H_CM0S_NOC3
 #define SRST_DBG_CM0S  4
 #define SRST_PO_CM0S   5
-#define SRST_P_SPI36
-#define SRST_SPI3  7
+#define SRST_P_SPI66
+#define SRST_SPI6  7
 #define SRST_P_TIMER_0_1   8
 #define SRST_P_TIMER_0 9
 #define SRST_P_TIMER_1 10
-- 
2.43.2

[PATCH 09/31] rockchip: rk3399: Add a default spl-boot-order prop

[Jonas Karlman]

A lot of RK3399 boards use a u-boot,spl-boot-order of "same-as-spl",
 and 

Move this to rk3399-u-boot.dtsi and make this default for boards
currently missing a u-boot,spl-boot-order prop.

The _flash reference has been dropped from spl-boot-order now that
boot source id is cached and "same-as-spl" can be resolved into the SPI
flash node.

Signed-off-by: Jonas Karlman 
---
 arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi  | 1 -
 arch/arm/dts/rk3399-evb-u-boot.dtsi| 1 -
 arch/arm/dts/rk3399-ficus-u-boot.dtsi  | 6 --
 arch/arm/dts/rk3399-firefly-u-boot.dtsi| 6 --
 arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi| 6 --
 arch/arm/dts/rk3399-leez-p710-u-boot.dtsi  | 6 --
 arch/arm/dts/rk3399-nanopi4-u-boot.dtsi| 6 --
 arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi   | 6 --
 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi  | 6 --
 arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 4 
 arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi  | 6 --
 arch/arm/dts/rk3399-rock960-u-boot.dtsi| 5 -
 arch/arm/dts/rk3399-rockpro64-u-boot.dtsi  | 5 +
 arch/arm/dts/rk3399-u-boot.dtsi| 4 
 arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi | 6 --
 15 files changed, 5 insertions(+), 69 deletions(-)

diff --git a/arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi 
b/arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi
index a3f27566e438..6c07de98fa01 100644
--- a/arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi
@@ -9,7 +9,6 @@
 / {
chosen {
stdout-path = "serial2:150n8";
-   u-boot,spl-boot-order = "same-as-spl", , 
};
 };
 
diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi 
b/arch/arm/dts/rk3399-evb-u-boot.dtsi
index dfce63e4d428..796ac9642399 100644
--- a/arch/arm/dts/rk3399-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi
@@ -9,7 +9,6 @@
 / {
chosen {
stdout-path = "serial2:150n8";
-   u-boot,spl-boot-order = "same-as-spl", , 
};
 };
 
diff --git a/arch/arm/dts/rk3399-ficus-u-boot.dtsi 
b/arch/arm/dts/rk3399-ficus-u-boot.dtsi
index 38e0897db91d..67b63a835238 100644
--- a/arch/arm/dts/rk3399-ficus-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-ficus-u-boot.dtsi
@@ -5,9 +5,3 @@
 
 #include "rk3399-u-boot.dtsi"
 #include "rk3399-sdram-ddr3-1600.dtsi"
-
-/ {
-   chosen {
-   u-boot,spl-boot-order = "same-as-spl", , 
-   };
-};
diff --git a/arch/arm/dts/rk3399-firefly-u-boot.dtsi 
b/arch/arm/dts/rk3399-firefly-u-boot.dtsi
index c58ad95d120a..1f5fda1d0f1d 100644
--- a/arch/arm/dts/rk3399-firefly-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-firefly-u-boot.dtsi
@@ -6,12 +6,6 @@
 #include "rk3399-u-boot.dtsi"
 #include "rk3399-sdram-ddr3-1600.dtsi"
 
-/ {
-   chosen {
-   u-boot,spl-boot-order = "same-as-spl", , 
-   };
-};
-
 _log {
regulator-init-microvolt = <95>;
 };
diff --git a/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi 
b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
index a7039d74a016..4a3b23e48313 100644
--- a/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
@@ -6,12 +6,6 @@
 #include "rk3399-u-boot.dtsi"
 #include "rk3399-sdram-lpddr4-100.dtsi"
 
-/ {
-   chosen {
-   u-boot,spl-boot-order = "same-as-spl", , 
-   };
-};
-
 _log {
regulator-init-microvolt = <95>;
 };
diff --git a/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi 
b/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi
index c638ce259731..03b596850635 100644
--- a/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi
@@ -6,12 +6,6 @@
 #include "rk3399-u-boot.dtsi"
 #include "rk3399-sdram-lpddr4-100.dtsi"
 
-/ {
-   chosen {
-   u-boot,spl-boot-order = "same-as-spl", , 
-   };
-};
-
 _log {
regulator-init-microvolt = <95>;
 };
diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi 
b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
index a9d10592d573..a126bbaf086f 100644
--- a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
@@ -5,12 +5,6 @@
 
 #include "rk3399-u-boot.dtsi"
 
-/{
-   chosen {
-   u-boot,spl-boot-order = "same-as-spl", , 
-   };
-};
-
  {
pinctrl-0 = <_bus4 _clk _cmd _cd>;
 };
diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi 
b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi
index 88a77cad8d43..83b0c44e9ec5 100644
--- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi
@@ -6,12 +6,6 @@
 #include "rk3399-u-boot.dtsi"
 #include "rk3399-sdram-lpddr4-100.dtsi"
 
-/ {
-   chosen {
-   u-boot,spl-boot-order = "same-as-spl", , , 

-   };
-};
-
  {
rockchip,panel = <_panel>;
 };
diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi 
b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
index cabf0a9dae89..e29757590611 100644
--- 

[PATCH 07/31] rockchip: rk3399: Enable DT overlay support on all boards

[Jonas Karlman]

Imply OF_LIBFDT_OVERLAY Kconfig options to add device tree overlay
support on all RK3399 boards.

Signed-off-by: Jonas Karlman 
---
 arch/arm/mach-rockchip/Kconfig| 1 +
 configs/rock-4c-plus-rk3399_defconfig | 1 -
 configs/rock-4se-rk3399_defconfig | 1 -
 configs/rock-pi-4-rk3399_defconfig| 1 -
 configs/rock-pi-4c-rk3399_defconfig   | 1 -
 5 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index a07ad38f2efc..8dca9d2853b4 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -268,6 +268,7 @@ config ROCKCHIP_RK3399
imply LEGACY_IMAGE_FORMAT
imply MISC
imply MISC_INIT_R
+   imply OF_LIBFDT_OVERLAY
imply OF_LIVE
imply PARTITION_TYPE_GUID
imply PHY_GIGE if GMAC_ROCKCHIP
diff --git a/configs/rock-4c-plus-rk3399_defconfig 
b/configs/rock-4c-plus-rk3399_defconfig
index bebea4fd0691..6c69e8bdcb92 100644
--- a/configs/rock-4c-plus-rk3399_defconfig
+++ b/configs/rock-4c-plus-rk3399_defconfig
@@ -5,7 +5,6 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4c-plus"
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_TARGET_ROCKPI4_RK3399=y
diff --git a/configs/rock-4se-rk3399_defconfig 
b/configs/rock-4se-rk3399_defconfig
index 04622df3c0a0..e5ed81022bd6 100644
--- a/configs/rock-4se-rk3399_defconfig
+++ b/configs/rock-4se-rk3399_defconfig
@@ -5,7 +5,6 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4se"
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_TARGET_ROCKPI4_RK3399=y
diff --git a/configs/rock-pi-4-rk3399_defconfig 
b/configs/rock-pi-4-rk3399_defconfig
index 9036c51de421..2801becedb4b 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -6,7 +6,6 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_SF_DEFAULT_SPEED=1000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4a"
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_ROCKCHIP_SPI_IMAGE=y
diff --git a/configs/rock-pi-4c-rk3399_defconfig 
b/configs/rock-pi-4c-rk3399_defconfig
index e1adec600174..72d37bff9e9a 100644
--- a/configs/rock-pi-4c-rk3399_defconfig
+++ b/configs/rock-pi-4c-rk3399_defconfig
@@ -5,7 +5,6 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4c"
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_TARGET_ROCKPI4_RK3399=y
-- 
2.43.2

[PATCH 08/31] rockchip: rk3399: Remove use of xPL_MISC_DRIVERS options

[Jonas Karlman]

The TPL and/or SPL control FDT on RK3399 boards does not contain any
node with a compatible that is supported by driver/misc/ drivers.

Remove use of xPL_MISC_DRIVERS options to stop including e.g an unused
efuse driver in TPL and/or SPL.

Signed-off-by: Jonas Karlman 
---
 arch/arm/mach-rockchip/Kconfig | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 8dca9d2853b4..bc03d69a7f5c 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -250,7 +250,6 @@ config ROCKCHIP_RK3399
select TPL_NEEDS_SEPARATE_STACK if TPL
select SPL_SEPARATE_BSS
select SPL_SERIAL
-   select SPL_DRIVERS_MISC
select CLK
select FIT
select PINCTRL
@@ -282,7 +281,6 @@ config ROCKCHIP_RK3399
imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
imply TPL_CLK
imply TPL_DM
-   imply TPL_DRIVERS_MISC
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
imply TPL_OF_CONTROL
-- 
2.43.2

[PATCH 05/31] rockchip: rk3399: Enable random generator on all boards

[Jonas Karlman]

The RK3399 SoC contain a crypto engine block that can generate random
numbers.

Imply DM_RNG and RNG_ROCKCHIP Kconfig options to take advantage of the
random generator on all RK3399 boards.

Signed-off-by: Jonas Karlman 
---
 arch/arm/mach-rockchip/Kconfig | 2 ++
 configs/chromebook_bob_defconfig   | 2 --
 configs/chromebook_kevin_defconfig | 2 --
 configs/evb-rk3399_defconfig   | 2 --
 configs/firefly-rk3399_defconfig   | 2 --
 configs/pinebook-pro-rk3399_defconfig  | 2 --
 configs/pinephone-pro-rk3399_defconfig | 2 --
 configs/roc-pc-rk3399_defconfig| 2 --
 configs/rock960-rk3399_defconfig   | 2 --
 configs/rockpro64-rk3399_defconfig | 2 --
 10 files changed, 2 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index eb74cd850409..e18d7f373f77 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -264,12 +264,14 @@ config ROCKCHIP_RK3399
imply ARMV8_SET_SMPEN
imply BOOTSTD_FULL
imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
+   imply DM_RNG
imply LEGACY_IMAGE_FORMAT
imply MISC
imply MISC_INIT_R
imply OF_LIVE
imply PARTITION_TYPE_GUID
imply PRE_CONSOLE_BUFFER
+   imply RNG_ROCKCHIP
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_EFUSE
imply ROCKCHIP_SDRAM_COMMON
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
index 5d8037d31422..6e203a6cf0e1 100644
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig
@@ -89,8 +89,6 @@ CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_CROS_EC=y
 CONFIG_PWM_ROCKCHIP=y
-CONFIG_DM_RNG=y
-CONFIG_RNG_ROCKCHIP=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SPI=y
diff --git a/configs/chromebook_kevin_defconfig 
b/configs/chromebook_kevin_defconfig
index 54ba2fdd136f..e3d16f44d62a 100644
--- a/configs/chromebook_kevin_defconfig
+++ b/configs/chromebook_kevin_defconfig
@@ -90,8 +90,6 @@ CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_CROS_EC=y
 CONFIG_PWM_ROCKCHIP=y
-CONFIG_DM_RNG=y
-CONFIG_RNG_ROCKCHIP=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SPI=y
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index d81c7f9604e1..c4936768ffb6 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -47,8 +47,6 @@ CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
-CONFIG_DM_RNG=y
-CONFIG_RNG_ROCKCHIP=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig
index 545c047c6df8..8f68ffbd3a49 100644
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig
@@ -45,8 +45,6 @@ CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
-CONFIG_DM_RNG=y
-CONFIG_RNG_ROCKCHIP=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
diff --git a/configs/pinebook-pro-rk3399_defconfig 
b/configs/pinebook-pro-rk3399_defconfig
index 23ac24a0bffe..e4aad1b710cb 100644
--- a/configs/pinebook-pro-rk3399_defconfig
+++ b/configs/pinebook-pro-rk3399_defconfig
@@ -75,8 +75,6 @@ CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM_ROCKCHIP_LPDDR4=y
-CONFIG_DM_RNG=y
-CONFIG_RNG_ROCKCHIP=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
diff --git a/configs/pinephone-pro-rk3399_defconfig 
b/configs/pinephone-pro-rk3399_defconfig
index 8c6323f6c516..285c47d76b6e 100644
--- a/configs/pinephone-pro-rk3399_defconfig
+++ b/configs/pinephone-pro-rk3399_defconfig
@@ -65,8 +65,6 @@ CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM_ROCKCHIP_LPDDR4=y
-CONFIG_DM_RNG=y
-CONFIG_RNG_ROCKCHIP=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_ROCKCHIP_SPI=y
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index a41f71d9e167..5d6e6b17091f 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -60,8 +60,6 @@ CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 # CONFIG_RAM_ROCKCHIP_DEBUG is not set
 CONFIG_RAM_ROCKCHIP_LPDDR4=y
-CONFIG_DM_RNG=y
-CONFIG_RNG_ROCKCHIP=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
index 13575c580054..7a4a3df85b1b 100644
--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig
@@ -52,8 +52,6 @@ CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
-CONFIG_DM_RNG=y
-CONFIG_RNG_ROCKCHIP=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
diff --git a/configs/rockpro64-rk3399_defconfig 

[PATCH 06/31] rockchip: rk3399: Imply support for GbE PHY

[Jonas Karlman]

Imply support for GbE PHY status parsing and configuration when support
for onboard ethernet is enabled.

Signed-off-by: Jonas Karlman 
---
 arch/arm/mach-rockchip/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index e18d7f373f77..a07ad38f2efc 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -270,6 +270,7 @@ config ROCKCHIP_RK3399
imply MISC_INIT_R
imply OF_LIVE
imply PARTITION_TYPE_GUID
+   imply PHY_GIGE if GMAC_ROCKCHIP
imply PRE_CONSOLE_BUFFER
imply RNG_ROCKCHIP
imply ROCKCHIP_COMMON_BOARD
-- 
2.43.2

[PATCH 04/31] rockchip: rk3399: Enable ARMv8 crypto and FIT checksum validation

[Jonas Karlman]

The RK3399 SoC support the ARMv8 Cryptography Extensions, use of ARMv8
crypto can speed up FIT checksum validation in SPL.

Imply ARMV8_SET_SMPEN and ARMV8_CRYPTO to take advantage of the crypto
extensions for SHA256 when validating checksum of FIT images.

Imply SPL_FIT_SIGNATURE and LEGACY_IMAGE_FORMAT to enable FIT checksum
validation to almost all RK3399 boards.

The following boards have been excluded:
- chromebook_bob: SPL max size limitation of 120 KiB
- chromebook_kevin: SPL max size limitation of 120 KiB
- puma-rk3399: SPL stack in SRAM and TPL+SPL combined max size
   limitation of 224 KiB

Also imply OF_LIVE to help speed up init of U-Boot proper and disable
CONFIG_SPL_RAW_IMAGE_SUPPORT on leez-rk3399 to ensure SPL does not try
to jump to code that failed checksum validation.

Signed-off-by: Jonas Karlman 
---
 arch/arm/mach-rockchip/Kconfig | 5 +
 configs/chromebook_bob_defconfig   | 1 +
 configs/chromebook_kevin_defconfig | 1 +
 configs/leez-rk3399_defconfig  | 1 +
 configs/puma-rk3399_defconfig  | 2 +-
 configs/rock-4se-rk3399_defconfig  | 2 --
 configs/rock-pi-4-rk3399_defconfig | 1 -
 configs/rockpro64-rk3399_defconfig | 2 --
 8 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index c0010fbb6887..eb74cd850409 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -260,15 +260,20 @@ config ROCKCHIP_RK3399
select DM_PMIC
select DM_REGULATOR_FIXED
select BOARD_LATE_INIT
+   imply ARMV8_CRYPTO
+   imply ARMV8_SET_SMPEN
imply BOOTSTD_FULL
imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
+   imply LEGACY_IMAGE_FORMAT
imply MISC
imply MISC_INIT_R
+   imply OF_LIVE
imply PARTITION_TYPE_GUID
imply PRE_CONSOLE_BUFFER
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_EFUSE
imply ROCKCHIP_SDRAM_COMMON
+   imply SPL_FIT_SIGNATURE
imply SPL_ROCKCHIP_COMMON_BOARD
imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
imply TPL_CLK
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
index 58e76f11472c..5d8037d31422 100644
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig
@@ -23,6 +23,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
+# CONFIG_SPL_FIT_SIGNATURE is not set
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/chromebook_kevin_defconfig 
b/configs/chromebook_kevin_defconfig
index 5adc276a746a..54ba2fdd136f 100644
--- a/configs/chromebook_kevin_defconfig
+++ b/configs/chromebook_kevin_defconfig
@@ -24,6 +24,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
+# CONFIG_SPL_FIT_SIGNATURE is not set
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig
index e5088341389a..2831cfb36689 100644
--- a/configs/leez-rk3399_defconfig
+++ b/configs/leez-rk3399_defconfig
@@ -15,6 +15,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x2e000
 CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index c2759e1a9520..fe7aac791271 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -23,6 +23,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
+# CONFIG_SPL_FIT_SIGNATURE is not set
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x2e000
@@ -52,7 +53,6 @@ CONFIG_CMD_TIME=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIVE=y
 CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
diff --git a/configs/rock-4se-rk3399_defconfig 
b/configs/rock-4se-rk3399_defconfig
index 712502517eb2..04622df3c0a0 100644
--- a/configs/rock-4se-rk3399_defconfig
+++ b/configs/rock-4se-rk3399_defconfig
@@ -15,8 +15,6 @@ CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
-CONFIG_SPL_FIT_SIGNATURE=y
-CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4se.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x2e000
diff --git a/configs/rock-pi-4-rk3399_defconfig 
b/configs/rock-pi-4-rk3399_defconfig
index 315b8b853fc3..9036c51de421 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ 

[PATCH 03/31] rockchip: rk3399: Sort imply statements alphabetically

[Jonas Karlman]

Sort imply statements under ROCKCHIP_RK3399 alphabetically.

Signed-off-by: Jonas Karlman 
---
 arch/arm/mach-rockchip/Kconfig | 28 ++--
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 22eccaaf5cb1..c0010fbb6887 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -260,30 +260,30 @@ config ROCKCHIP_RK3399
select DM_PMIC
select DM_REGULATOR_FIXED
select BOARD_LATE_INIT
+   imply BOOTSTD_FULL
+   imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
+   imply MISC
+   imply MISC_INIT_R
imply PARTITION_TYPE_GUID
imply PRE_CONSOLE_BUFFER
imply ROCKCHIP_COMMON_BOARD
+   imply ROCKCHIP_EFUSE
imply ROCKCHIP_SDRAM_COMMON
imply SPL_ROCKCHIP_COMMON_BOARD
-   imply TPL_SERIAL
+   imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
+   imply TPL_CLK
+   imply TPL_DM
+   imply TPL_DRIVERS_MISC
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
+   imply TPL_OF_CONTROL
+   imply TPL_RAM
+   imply TPL_REGMAP
+   imply TPL_ROCKCHIP_COMMON_BOARD
+   imply TPL_SERIAL
imply TPL_SYS_MALLOC_SIMPLE
-   imply TPL_DRIVERS_MISC
-   imply TPL_OF_CONTROL
-   imply TPL_DM
-   imply TPL_REGMAP
imply TPL_SYSCON
-   imply TPL_RAM
-   imply TPL_CLK
imply TPL_TINY_MEMSET
-   imply TPL_ROCKCHIP_COMMON_BOARD
-   imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
-   imply BOOTSTD_FULL
-   imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
-   imply MISC
-   imply ROCKCHIP_EFUSE
-   imply MISC_INIT_R
help
  The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
  and quad-core Cortex-A53.
-- 
2.43.2

[PATCH 02/31] rockchip: rk3399-ficus: Enable TPL and use common bss and stack addr

[Jonas Karlman]

The rk3399-ficus board is only using SPL and not TPL+SPL like all other
RK3399 boards, chromebook bob/kevin excluded. It does not seem to be any
technical reason why this board was left using only SPL.

Switch to use TPL+SPL and use common bss and stack addresses to allow
for more options to be enabled in a future patch. Also add the missing
DEFAULT_FDT_FILE option.

Signed-off-by: Jonas Karlman 
---
 configs/ficus-rk3399_defconfig | 14 ++
 1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig
index 4859042d6b56..3bcd0fd66b91 100644
--- a/configs/ficus-rk3399_defconfig
+++ b/configs/ficus-rk3399_defconfig
@@ -2,32 +2,22 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x0020
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x30
 CONFIG_SF_DEFAULT_SPEED=2000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus"
-CONFIG_SPL_TEXT_BASE=0xff8c2000
 CONFIG_ROCKCHIP_RK3399=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
 CONFIG_TARGET_ROCK960_RK3399=y
-CONFIG_SPL_STACK=0xff8e
 CONFIG_DEBUG_UART_BASE=0xFF1A
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-ficus.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x2e000
 CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0xff8e
-CONFIG_SPL_BSS_MAX_SIZE=0x1
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
-- 
2.43.2

[PATCH 01/31] rockchip: rk3399-gru: Fix max SPL size on bob and kevin

[Jonas Karlman]

Chromebook bob and kevin only use SPL and not TPL+SPL like other RK3399
boards, this mean that SPL is loaded to and run from SRAM instead of
DRAM. The SPL and U-Boot payload is loaded from SPI flash.

The U-Boot payload is located at 0x4 (256 KiB) offset in SPI flash
and because the BROM only read first 2 KiB for each 4 KiB page, the size
of SPL (idbloader.img) is limited to max 128 KiB.

The chosen bss start address further limits the size of SPL to 120 KiB.

  0xff8e (SPL_BSS_START_ADDR) - 0xff8c2000 (SPL_TEXT_BASE) = 0x1e000

Update SPL_MAX_SIZE to reflect the 120 KiB max size limitation.

Signed-off-by: Jonas Karlman 
---
 configs/chromebook_bob_defconfig   | 2 +-
 configs/chromebook_kevin_defconfig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
index d0321948697b..58e76f11472c 100644
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig
@@ -30,7 +30,7 @@ CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_BLOBLIST=y
 CONFIG_BLOBLIST_ADDR=0x10
 CONFIG_BLOBLIST_SIZE=0x1000
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x1e000
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xff8e
diff --git a/configs/chromebook_kevin_defconfig 
b/configs/chromebook_kevin_defconfig
index 120c11c04972..5adc276a746a 100644
--- a/configs/chromebook_kevin_defconfig
+++ b/configs/chromebook_kevin_defconfig
@@ -31,7 +31,7 @@ CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_BLOBLIST=y
 CONFIG_BLOBLIST_ADDR=0x10
 CONFIG_BLOBLIST_SIZE=0x1000
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x1e000
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xff8e
-- 
2.43.2

[PATCH 00/31] rockchip: rk3399: Sync DT with linux v6.8 and update defconfigs

[Jonas Karlman]

This series adds support for new clocks used in linux v6.8 device trees,
enables use of FIT signature check for checksum validation and fixes
loading FIT from SD-card when loading FIT from eMMC fails.

After this series it should be possible to move RK3399 boards to use
OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag.

I have runtime tested this series on following devices:
- 96boards Rock960
- Khadas Edge Captain
- Pine64 PineBook Pro
- Pine64 RockPro64
- Radxa ROCK 4C+
- Radxa ROCK 4SE
- Radxa ROCK Pi 4A
- Radxa ROCK Pi 4B+

This series depends on the following series:
- Enable booting from SPI flash on ROCK Pi 4 [1]
- rockchip: spl: Cache boot source id for later use [2]

A copy of this series and all its depends can be found at [3]

[1] https://patchwork.ozlabs.org/cover/1912469/
[2] https://patchwork.ozlabs.org/cover/1915071/
[3] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3399-dt-sync-v1

Jonas Karlman (31):
  rockchip: rk3399-gru: Fix max SPL size on bob and kevin
  rockchip: rk3399-ficus: Enable TPL and use common bss and stack addr
  rockchip: rk3399: Sort imply statements alphabetically
  rockchip: rk3399: Enable ARMv8 crypto and FIT checksum validation
  rockchip: rk3399: Enable random generator on all boards
  rockchip: rk3399: Imply support for GbE PHY
  rockchip: rk3399: Enable DT overlay support on all boards
  rockchip: rk3399: Remove use of xPL_MISC_DRIVERS options
  rockchip: rk3399: Add a default spl-boot-order prop
  rockchip: rk3399: Fix loading FIT from SD-card when booting from eMMC
  clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC
  clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock
  clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock
  clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support
  rockchip: rk3399: Sync soc device tree from linux v6.8
  rockchip: rk3399-gru: Sync device tree from linux v6.8
  rockchip: rk3399-puma: Sync DT from linux v6.8
  rockchip: rk3399-rock-pi-n10: Sync device tree from linux v6.8
  rockchip: rk3399-eaidk-610: Sync device tree from linux v6.8
  rockchip: rk3399-leez: Sync device tree from linux v6.8
  rockchip: rk3399-evb: Sync device tree from linux v6.8
  rockchip: rk3399-firefly: Sync device tree from linux v6.8
  rockchip: rk3399-orangepi: Sync device tree from linux v6.8
  rockchip: rk3399-roc-pc: Sync device tree from linux v6.8
  rockchip: rk3399-nanopi-4: Sync device tree from linux v6.8
  rockchip: rk3399-rock960: Sync device tree from linux v6.8
  rockchip: rk3399-khadas: Sync device tree from linux v6.8
  rockchip: rk3399-rock-pi-4: Sync device tree from linux v6.8
  rockchip: rk3399-rockpro64: Sync device tree from linux v6.8
  rockchip: rk3399-pinebook-pro: Sync device tree from linux v6.8
  rockchip: rk3399-pinephone-pro: Sync device tree from linux v6.8

 arch/arm/dts/rk3288-vmarc-som.dtsi|  48 +++
 arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi |   1 -
 arch/arm/dts/rk3399-eaidk-610.dts |   3 +-
 arch/arm/dts/rk3399-evb-u-boot.dtsi   |  13 +-
 arch/arm/dts/rk3399-evb.dts   |   3 +-
 arch/arm/dts/rk3399-ficus-u-boot.dtsi |  10 +-
 arch/arm/dts/rk3399-ficus.dts |   4 +
 arch/arm/dts/rk3399-firefly-u-boot.dtsi   |   6 -
 arch/arm/dts/rk3399-firefly.dts   |  17 +-
 arch/arm/dts/rk3399-gru-bob.dts   |   8 +-
 arch/arm/dts/rk3399-gru-chromebook.dtsi   | 200 +++-
 arch/arm/dts/rk3399-gru-kevin.dts |   3 +-
 arch/arm/dts/rk3399-gru-u-boot.dtsi   |  34 ++-
 arch/arm/dts/rk3399-gru.dtsi  |  52 +++-
 arch/arm/dts/rk3399-khadas-edge-captain.dts   |   4 +
 arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi   |   7 +-
 arch/arm/dts/rk3399-khadas-edge-v.dts |   4 +
 arch/arm/dts/rk3399-khadas-edge.dtsi  |  10 +-
 arch/arm/dts/rk3399-leez-p710-u-boot.dtsi |   6 -
 arch/arm/dts/rk3399-leez-p710.dts |   8 +-
 arch/arm/dts/rk3399-nanopc-t4.dts |   2 +-
 arch/arm/dts/rk3399-nanopi-m4-2gb.dts |  55 +---
 arch/arm/dts/rk3399-nanopi-m4b.dts|   2 +-
 arch/arm/dts/rk3399-nanopi-r4s.dts|   4 +-
 arch/arm/dts/rk3399-nanopi4-u-boot.dtsi   |  18 +-
 arch/arm/dts/rk3399-nanopi4.dtsi  |   7 +-
 arch/arm/dts/rk3399-op1-opp.dtsi  |  31 +-
 arch/arm/dts/rk3399-opp.dtsi  |   6 +-
 arch/arm/dts/rk3399-orangepi-u-boot.dtsi  |  12 +
 arch/arm/dts/rk3399-orangepi.dts  |  12 +-
 arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi  |  23 +-
 arch/arm/dts/rk3399-pinebook-pro.dts  |  24 +-
 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi |  24 +-
 arch/arm/dts/rk3399-pinephone-pro.dts | 147 +
 arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi   |  27 +-
 arch/arm/dts/rk3399-puma-haikou.dts   |  42 ++-
 arch/arm/dts/rk3399-puma.dtsi |  17 +-
 arch/arm/dts/rk3399-roc-pc-u-boot.dtsi|  45 +--
 

[PATCH] ARM: stm32: Jump to ep on successful resume in PSCI suspend code

[Marek Vasut]

In case the system has resumed successfully, the PSCI suspend resume
code has to jump to the 'ep' successful resume entry point code path,
otherwise the code has to jump to content of the LR register, which
points to failed resume code path.

To implement this distinction, rewrite LR register stored on stack
with 'ep' value in case of a successful resume, which is really in
every case unless some catastrophic failure occurred during suspend.

Without this change, Linux counts every resume as failed in
/sys/power/suspend_stats/fail

Signed-off-by: Marek Vasut 
---
Cc: Patrice Chotard 
Cc: Patrick Delaunay 
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
Cc: uboot-st...@st-md-mailman.stormreply.com
---
 arch/arm/mach-stm32mp/psci.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c
index 8cdeb0ab3f2..4f2379df45f 100644
--- a/arch/arm/mach-stm32mp/psci.c
+++ b/arch/arm/mach-stm32mp/psci.c
@@ -703,6 +703,8 @@ void __secure psci_system_suspend(u32 __always_unused 
function_id,
 {
u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr;
u32 gicd_addr = stm32mp_get_gicd_base_address();
+   u32 cpu = psci_get_cpu_id();
+   u32 sp = (u32)__secure_stack_end - (cpu << ARM_PSCI_STACK_SHIFT);
bool iwdg1_wake = false;
bool iwdg2_wake = false;
bool other_wake = false;
@@ -805,4 +807,16 @@ void __secure psci_system_suspend(u32 __always_unused 
function_id,
 
writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR);
clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
+
+   /*
+* The system has resumed successfully. Rewrite LR register stored
+* on stack with 'ep' value, so that on return from this PSCI call,
+* the code would jump to that 'ep' resume entry point code path
+* instead of the previous 'lr' register content which (e.g. with
+* Linux) points to resume failure code path.
+*
+* See arch/arm/cpu/armv7/psci.S _smc_psci: for the stack layout
+* used here, SP-4 is PC, SP-8 is LR, SP-12 is R7, and so on.
+*/
+   writel(ep, sp - 8);
 }
-- 
2.43.0

Re: [GIT PULL] Please pull u-boot-imx-next-20240330

[Tom Rini]

On Sat, Mar 30, 2024 at 04:40:31PM -0300, Fabio Estevam wrote:

> Hi Tom,
> 
> Please pull this material for next from u-boot-imx, thanks.
> 
> The following changes since commit 6e2228fb052b68c84688d5baff06e2ebc787a4a5:
> 
>   Merge patch series "Clean up arm linker scripts" (2024-03-29 10:39:38 -0400)
> 
> are available in the Git repository at:
> 
>   https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git 
> tags/u-boot-imx-next-20240330
> 
> for you to fetch changes up to f21b3e2cd954634d405fb522198d099879f3f1e7:
> 
>   config: xea: Add limits for SPL and u-boot proper sizes (2024-03-30 
> 15:12:22 -0300)
> 
> u-boot-imx-next-20240330

Applied to u-boot/next, thanks!

-- 
Tom


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