Re: [U-Boot] [PATCH v2 3/8] riscv: Add EFI application infrastructure
> The hello world binary and a few selftests require to build EFI target
> binaries, not just the EFI host environment.
>
> This patch adds all required files to generate an EFI binary for RISC-V.
>
> Signed-off-by: Alexander Graf
>
> ---
>
> new in v2
> ---
> arch/riscv/config.mk | 5 ++
> arch/riscv/lib/Makefile| 11 +
> arch/riscv/lib/elf_riscv32_efi.lds | 70 +++
> arch/riscv/lib/elf_riscv64_efi.lds | 70 +++
> arch/riscv/lib/reloc_riscv_efi.c | 97
> ++
> 5 files changed, 253 insertions(+)
> create mode 100644 arch/riscv/lib/elf_riscv32_efi.lds
> create mode 100644 arch/riscv/lib/elf_riscv64_efi.lds
> create mode 100644 arch/riscv/lib/reloc_riscv_efi.c
>
> diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk index
> 69f4cf6ce8..9175aa765d 100644
> --- a/arch/riscv/config.mk
> +++ b/arch/riscv/config.mk
> @@ -19,10 +19,12 @@ endif
>
> ifdef CONFIG_32BIT
> PLATFORM_LDFLAGS += -m $(32bit-emul)
> +EFI_LDS:= elf_riscv32_efi.lds
> endif
>
> ifdef CONFIG_64BIT
> PLATFORM_LDFLAGS += -m $(64bit-emul)
> +EFI_LDS:= elf_riscv64_efi.lds
> endif
>
> CONFIG_STANDALONE_LOAD_ADDR = 0x \ @@ -31,3 +33,6 @@
> CONFIG_STANDALONE_LOAD_ADDR = 0x \
> PLATFORM_CPPFLAGS += -ffixed-gp -fpic
> PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -gdwarf-2
> -ffunction-sections LDFLAGS_u-boot += --gc-sections -static -pie
> +
> +EFI_CRT0 := crt0_riscv_efi.o
> +EFI_RELOC := reloc_riscv_efi.o
Hi Alexander
make fail as below
make[1]: *** No rule to make target 'arch/riscv/lib/crt0_riscv_efi.o',
needed by '__build'. Stop.
Makefile:1340: recipe for target 'arch/riscv/lib' failed
Shall crt0_riscv_efi.c be uploaded there ?
B.R.
Rick
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index
> 6d97aa2719..33f80ebdca 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -13,3 +13,14 @@ obj-$(CONFIG_CMD_GO) += boot.o
> obj-y += cache.o
> obj-y += interrupts.o
> obj-y += setjmp.o
> +
> +# For building EFI apps
> +CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI)
> +CFLAGS_REMOVE_$(EFI_CRT0) := $(CFLAGS_NON_EFI)
> +
> +CFLAGS_$(EFI_RELOC) := $(CFLAGS_EFI)
> +CFLAGS_REMOVE_$(EFI_RELOC) := $(CFLAGS_NON_EFI)
> +
> +extra-$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE) += $(EFI_CRT0) $(EFI_RELOC)
> +extra-$(CONFIG_CMD_BOOTEFI_SELFTEST) += $(EFI_CRT0) $(EFI_RELOC)
> +extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC)
> diff --git a/arch/riscv/lib/elf_riscv32_efi.lds
> b/arch/riscv/lib/elf_riscv32_efi.lds
> new file mode 100644
> index 00..96d11985b0
> --- /dev/null
> +++ b/arch/riscv/lib/elf_riscv32_efi.lds
> @@ -0,0 +1,70 @@
> +/*
> + * U-Boot riscv32 EFI linker script
> + *
> + * SPDX-License-Identifier:BSD-2-Clause
> + *
> + * Modified from arch/arm/lib/elf_aarch64_efi.lds */
> +
> +OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv",
> +"elf32-littleriscv")
> +OUTPUT_ARCH(riscv)
> +ENTRY(_start)
> +SECTIONS
> +{
> + .text 0x0 : {
> + _text = .;
> + *(.text.head)
> + *(.text)
> + *(.text.*)
> + *(.gnu.linkonce.t.*)
> + *(.srodata)
> + *(.rodata*)
> + . = ALIGN(16);
> + }
> + _etext = .;
> + _text_size = . - _text;
> + .dynamic : { *(.dynamic) }
> + .data : {
> + _data = .;
> + *(.sdata)
> + *(.data)
> + *(.data1)
> + *(.data.*)
> + *(.got.plt)
> + *(.got)
> +
> + /*
> +* The EFI loader doesn't seem to like a .bss section, so we
> +* stick it all into .data:
> +*/
> + . = ALIGN(16);
> + _bss = .;
> + *(.sbss)
> + *(.scommon)
> + *(.dynbss)
> + *(.bss)
> + *(.bss.*)
> + *(COMMON)
> + . = ALIGN(16);
> + _bss_end = .;
> + _edata = .;
> + }
> + .rela.dyn : { *(.rela.dyn) }
> + .rela.plt : { *(.rela.plt) }
> + .rela.got : { *(.rela.got) }
> + .rela.data : { *(.rela.data) *(.rela.data*) }
> + _data_size = . - _etext;
> +
> + . = ALIGN(4096);
> + .dynsym : { *(.dynsym) }
> + . = ALIGN(4096);
> + .dynstr : { *(.dynstr) }
> + . = ALIGN(4096);
> + .note.gnu.build-id : { *(.note.gnu.build-id) }
> + /DISCARD/ : {
> + *(.rel.reloc)
> + *(.eh_frame)
> + *(.note.GNU-stack)
> + }
> + .comment 0 : { *(.comment) }
> +}
> diff --git a/arch/riscv/lib/elf_riscv64_efi.lds
> b/arch/riscv/lib/elf_riscv64_efi.lds
> new file mode 100644
> index 00..25c863de8a
> --- /dev/null
> +++ b/arch/ris
Re: [U-Boot] [PATCH] spi: atcspi200: Full dm conversion
2018-03-07 19:02 GMT+08:00 Jagan Teki : > > > On 07-Mar-2018 1:12 PM, "陳建志" wrote: > > 2018-03-07 15:20 GMT+08:00 Jagan Teki : >> On Wed, Mar 7, 2018 at 12:34 PM, Andes wrote: >>> From: Rick Chen >>> >>> atcspi200_spi now support dt along with platform data. >>> >>> Signed-off-by: Rick Chen >>> Signed-off-by: Rick Chen >>> Signed-off-by: Greentime Hu >>> --- >>> drivers/spi/atcspi200_spi.c | 134 >>> ++ >>> include/dm/platform_data/spi_atcspi200.h | 15 >> >> I have seen only two boards using this driver (adp-ae3xx_defconfig, >> nx25-ae250_defconfig) and both are enabled DM_SPI with OF_CONTROL why >> we need to have platdata for this? here [1] is non-dm code drop. >> >> [1] https://patchwork.ozlabs.org/patch/882404/ > > Hi Tagan Teki > > I just refer to [PATCH][Boards Need to Switch DM] spi: davinci: Full > dm conversion > And have this modification. > > So it is not necessary to add platdata for atcspi200_spi, just drop > non-dm code, right ? > > > There are two boards using this driver adp-ae3xx_defconfig and > nx25-ae250_defconfig, both of them use DM_SPL with dr. With this reason it > is not require to add pdata here? Thanks for your explanations. Rick ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] spi: atcspi200: Full dm conversion
2018-03-07 15:20 GMT+08:00 Jagan Teki : > On Wed, Mar 7, 2018 at 12:34 PM, Andes wrote: >> From: Rick Chen >> >> atcspi200_spi now support dt along with platform data. >> >> Signed-off-by: Rick Chen >> Signed-off-by: Rick Chen >> Signed-off-by: Greentime Hu >> --- >> drivers/spi/atcspi200_spi.c | 134 >> ++ >> include/dm/platform_data/spi_atcspi200.h | 15 > > I have seen only two boards using this driver (adp-ae3xx_defconfig, > nx25-ae250_defconfig) and both are enabled DM_SPI with OF_CONTROL why > we need to have platdata for this? here [1] is non-dm code drop. > > [1] https://patchwork.ozlabs.org/patch/882404/ Hi Tagan Teki I just refer to [PATCH][Boards Need to Switch DM] spi: davinci: Full dm conversion And have this modification. So it is not necessary to add platdata for atcspi200_spi, just drop non-dm code, right ? Thank you Rick ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2, 01/12] riscv: cpu: Add nx25 to support RISC-V
2018-02-02 16:20 GMT+08:00 陳建志 : >> Actually I have checked with checkpatch.pl and cleaned most before >> sending patchs. >> But it seem still left some, I will keep fixing them. >> >> Thanks for Tom and Wolfgang's help. >> >> Rick >> >> 2018-01-15 21:52 GMT+08:00 Tom Rini : >>> On Tue, Dec 26, 2017 at 01:55:48PM +0800, Andes wrote: >>> >>>> From: Rick Chen >>>> >>>> Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch >>>> >>>> Verifications: >>>> 1. startup and relocation ok. >>>> 2. boot from rom or ram both ok. >>>> 2. timer driver ok. >>>> 3. uart driver ok >>>> 4. mmc driver ok >>>> 5. spi driver ok. >>>> 6. 32/64 bit both ok. >>>> >>>> Detail verification message please see doc/README.ae250. >>>> >>>> Signed-off-by: Rick Chen >>>> Signed-off-by: Rick Chen >>>> Signed-off-by: Greentime Hu >>>> Cc: Padmarao Begari >>> >>> Applied to u-boot/master. >>> >>> But that said, the whole of arch/riscv/ and board/AndesTech/nx25-ae250/ >>> introduces some checkpatch.pl issues, please investigate and fix >>> appropriate ones, thanks! >>> >>> -- >>> Tom > > Hi Tom > > I am trying to fix this checkpatch.pl issue. > > Though I download mainline by > git clone http://git.denx.de/u-boot.git > It can be seen /arch/riscv folder there. > > But when I try to download riscv repository by > git clone http://git.denx.de/u-boot-riscv.git > and it fail. > > Below is the error messge: > Cloning into 'u-boot-riscv'... > fatal: http://git.denx.de/u-boot-riscv.git/info/refs not found: did > you run git update-server-info on the server? > > Download nds32 repo by > git clone http://git.denx.de/u-boot-nds32.git > is ok. > > May I ask have this riscv repo been created ? > or > did I do something wrong ? > > It seem that after I finish fixing the checkpatch.pl issue, I can not do > git push ssh://gu-ri...@git.denx.de/u-boot-riscv.git master > without riscv repo for contribution. > > Rick Hi Tom It can be downloaded now. Please ignore it. Rick ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2, 01/12] riscv: cpu: Add nx25 to support RISC-V
> Actually I have checked with checkpatch.pl and cleaned most before > sending patchs. > But it seem still left some, I will keep fixing them. > > Thanks for Tom and Wolfgang's help. > > Rick > > 2018-01-15 21:52 GMT+08:00 Tom Rini : >> On Tue, Dec 26, 2017 at 01:55:48PM +0800, Andes wrote: >> >>> From: Rick Chen >>> >>> Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch >>> >>> Verifications: >>> 1. startup and relocation ok. >>> 2. boot from rom or ram both ok. >>> 2. timer driver ok. >>> 3. uart driver ok >>> 4. mmc driver ok >>> 5. spi driver ok. >>> 6. 32/64 bit both ok. >>> >>> Detail verification message please see doc/README.ae250. >>> >>> Signed-off-by: Rick Chen >>> Signed-off-by: Rick Chen >>> Signed-off-by: Greentime Hu >>> Cc: Padmarao Begari >> >> Applied to u-boot/master. >> >> But that said, the whole of arch/riscv/ and board/AndesTech/nx25-ae250/ >> introduces some checkpatch.pl issues, please investigate and fix >> appropriate ones, thanks! >> >> -- >> Tom Hi Tom I am trying to fix this checkpatch.pl issue. Though I download mainline by git clone http://git.denx.de/u-boot.git It can be seen /arch/riscv folder there. But when I try to download riscv repository by git clone http://git.denx.de/u-boot-riscv.git and it fail. Below is the error messge: Cloning into 'u-boot-riscv'... fatal: http://git.denx.de/u-boot-riscv.git/info/refs not found: did you run git update-server-info on the server? Download nds32 repo by git clone http://git.denx.de/u-boot-nds32.git is ok. May I ask have this riscv repo been created ? or did I do something wrong ? It seem that after I finish fixing the checkpatch.pl issue, I can not do git push ssh://gu-ri...@git.denx.de/u-boot-riscv.git master without riscv repo for contribution. Rick ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2, 01/12] riscv: cpu: Add nx25 to support RISC-V
Actually I have checked with checkpatch.pl and cleaned most before sending patchs. But it seem still left some, I will keep fixing them. Thanks for Tom and Wolfgang's help. Rick 2018-01-15 21:52 GMT+08:00 Tom Rini : > On Tue, Dec 26, 2017 at 01:55:48PM +0800, Andes wrote: > >> From: Rick Chen >> >> Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch >> >> Verifications: >> 1. startup and relocation ok. >> 2. boot from rom or ram both ok. >> 2. timer driver ok. >> 3. uart driver ok >> 4. mmc driver ok >> 5. spi driver ok. >> 6. 32/64 bit both ok. >> >> Detail verification message please see doc/README.ae250. >> >> Signed-off-by: Rick Chen >> Signed-off-by: Rick Chen >> Signed-off-by: Greentime Hu >> Cc: Padmarao Begari > > Applied to u-boot/master. > > But that said, the whole of arch/riscv/ and board/AndesTech/nx25-ae250/ > introduces some checkpatch.pl issues, please investigate and fix > appropriate ones, thanks! > > -- > Tom ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 01/12] riscv: cpu: Add nx25 to support RISC-V
Hi Tom
How about the Andes NX25 cpu for RISC-V arch patchsets [PATCH v2 x/12]
reviewing status ?
Is everything ok ?
Rick
2017-12-26 13:55 GMT+08:00 Andes :
> From: Rick Chen
>
> Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch
>
> Verifications:
> 1. startup and relocation ok.
> 2. boot from rom or ram both ok.
> 2. timer driver ok.
> 3. uart driver ok
> 4. mmc driver ok
> 5. spi driver ok.
> 6. 32/64 bit both ok.
>
> Detail verification message please see doc/README.ae250.
>
> Signed-off-by: Rick Chen
> Signed-off-by: Rick Chen
> Signed-off-by: Greentime Hu
> Cc: Padmarao Begari
> ---
> arch/riscv/cpu/nx25/Makefile | 10 ++
> arch/riscv/cpu/nx25/cpu.c | 33 +
> arch/riscv/cpu/nx25/start.S| 291
> +
> arch/riscv/cpu/nx25/u-boot.lds | 69 ++
> 4 files changed, 403 insertions(+)
> create mode 100644 arch/riscv/cpu/nx25/Makefile
> create mode 100644 arch/riscv/cpu/nx25/cpu.c
> create mode 100644 arch/riscv/cpu/nx25/start.S
> create mode 100644 arch/riscv/cpu/nx25/u-boot.lds
>
> diff --git a/arch/riscv/cpu/nx25/Makefile b/arch/riscv/cpu/nx25/Makefile
> new file mode 100644
> index 000..5fcf100
> --- /dev/null
> +++ b/arch/riscv/cpu/nx25/Makefile
> @@ -0,0 +1,10 @@
> +#
> +# Copyright (C) 2017 Andes Technology Corporation
> +# Rick Chen, Andes Technology Corporation
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +extra-y= start.o
> +
> +obj-y := cpu.o
> diff --git a/arch/riscv/cpu/nx25/cpu.c b/arch/riscv/cpu/nx25/cpu.c
> new file mode 100644
> index 000..5478f4f
> --- /dev/null
> +++ b/arch/riscv/cpu/nx25/cpu.c
> @@ -0,0 +1,33 @@
> +/*
> + * Copyright (C) 2017 Andes Technology Corporation
> + * Rick Chen, Andes Technology Corporation
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +/* CPU specific code */
> +#include
> +#include
> +#include
> +#include
> +
> +/*
> + * cleanup_before_linux() is called just before we call linux
> + * it prepares the processor for linux
> + *
> + * we disable interrupt and caches.
> + */
> +int cleanup_before_linux(void)
> +{
> + disable_interrupts();
> +
> + /* turn off I/D-cache */
> +
> + return 0;
> +}
> +
> +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +{
> + disable_interrupts();
> + panic("nx25-ae250 wdt not support yet.\n");
> +}
> diff --git a/arch/riscv/cpu/nx25/start.S b/arch/riscv/cpu/nx25/start.S
> new file mode 100644
> index 000..6a07663
> --- /dev/null
> +++ b/arch/riscv/cpu/nx25/start.S
> @@ -0,0 +1,291 @@
> +/*
> + * Startup Code for RISC-V Core
> + *
> + * Copyright (c) 2017 Microsemi Corporation.
> + * Copyright (c) 2017 Padmarao Begari
> + *
> + * Copyright (C) 2017 Andes Technology Corporation
> + * Rick Chen, Andes Technology Corporation
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#ifdef CONFIG_32BIT
> +#define LREG lw
> +#define SREG sw
> +#define REGBYTES 4
> +#define RELOC_TYPE R_RISCV_32
> +#define SYM_INDEX 0x8
> +#define SYM_SIZE 0x10
> +#else
> +#define LREG ld
> +#define SREG sd
> +#define REGBYTES 8
> +#define RELOC_TYPE R_RISCV_64
> +#define SYM_INDEX 0x20
> +#define SYM_SIZE 0x18
> +#endif
> +
> +.section .text
> +.globl _start
> +_start:
> + j handle_reset
> +
> +nmi_vector:
> + j nmi_vector
> +
> +trap_vector:
> + j trap_entry
> +
> +.global trap_entry
> +handle_reset:
> + la t0, trap_entry
> + csrw mtvec, t0
> + csrwi mstatus, 0
> + csrwi mie, 0
> +
> +/*
> + * Do CPU critical regs init only at reboot,
> + * not when booting from ram
> + */
> +#ifdef CONFIG_INIT_CRITICAL
> + jal cpu_init_crit /* Do CPU critical regs init */
> +#endif
> +
> +/*
> + * Set stackpointer in internal/ex RAM to call board_init_f
> + */
> +call_board_init_f:
> + li t0, -16
> + li t1, CONFIG_SYS_INIT_SP_ADDR
> + and sp, t1, t0 /* force 16 byte alignment */
> +
> +#ifdef CONFIG_DEBUG_UART
> + jal debug_uart_init
> +#endif
> +
> +call_board_init_f_0:
> + mv a0, sp
> + jal board_init_f_alloc_reserve
> + mv sp, a0
> + jal board_init_f_init_reserve
> +
> + mv a0, zero/* a0 <-- boot_flags = 0 */
> + la t5, board_init_f
> + jr t5 /* jump to board_init_f() */
> +
> +/*
> + * void relocate_code (addr_sp, gd, addr_moni)
> + *
> + * This "function" does not return, instead it continues in RAM
> + * after relocating the monitor code.
> + *
> + */
> +.globl relocate_code
> +relocate_code:
> + mv s2, a0 /* save addr_sp */
> + mv s3, a1 /* save addr of gd */
> + mv s4, a2 /* save addr of destination */
> +
> +/*
> + *Se
Re: [U-Boot] [PATCH 09/12] risck: tools: Prelink u-boot
2017-12-22 23:31 GMT+08:00 Tom Rini : > On Fri, Dec 22, 2017 at 03:44:26PM +0800, Andes wrote: > >> From: Rick Chen >> >> Add prelink-riscv to arrange .rela.dyn and .rela.got >> in compile time. >> >> Signed-off-by: Rick Chen >> Signed-off-by: Rick Chen >> Signed-off-by: Greentime Hu >> --- >> Makefile|4 ++ >> tools/Makefile |1 + >> tools/prelink-riscv.c | 91 ++ >> tools/prelink-riscv.inc | 101 >> +++ >> 4 files changed, 197 insertions(+), 0 deletions(-) >> create mode 100644 tools/prelink-riscv.c >> create mode 100644 tools/prelink-riscv.inc >> >> diff --git a/Makefile b/Makefile >> index c573ddb..bb6416f 100644 >> --- a/Makefile >> +++ b/Makefile >> @@ -1264,6 +1264,10 @@ ifeq ($(CONFIG_KALLSYMS),y) >> $(call cmd,u-boot__) common/system_map.o >> endif >> >> +ifeq ($(CONFIG_RISCV),y) >> + @tools/prelink-riscv $@ 0 >> +endif >> + >> quiet_cmd_sym ?= SYM $@ >>cmd_sym ?= $(OBJDUMP) -t $< > $@ >> u-boot.sym: u-boot FORCE >> diff --git a/tools/Makefile b/tools/Makefile >> index 4d32fe5..571f571 100644 >> --- a/tools/Makefile >> +++ b/tools/Makefile >> @@ -185,6 +185,7 @@ hostprogs-$(CONFIG_KIRKWOOD) += kwboot >> hostprogs-$(CONFIG_ARCH_MVEBU) += kwboot >> hostprogs-y += proftool >> hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela >> +hostprogs-$(CONFIG_RISCV) += prelink-riscv >> >> hostprogs-y += fdtgrep >> fdtgrep-objs += $(LIBFDT_OBJS) fdtgrep.o >> diff --git a/tools/prelink-riscv.c b/tools/prelink-riscv.c >> new file mode 100644 >> index 000..dd099a9 >> --- /dev/null >> +++ b/tools/prelink-riscv.c >> @@ -0,0 +1,91 @@ >> +#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__ >> +#error "Only little-endian host is supported" >> +#endif > [snip] >> diff --git a/tools/prelink-riscv.inc b/tools/prelink-riscv.inc >> new file mode 100644 >> index 000..f7f9596 >> --- /dev/null >> +++ b/tools/prelink-riscv.inc > > Needs license information, thanks! > I will add license information in the next version. Thanks for reviewing. Rick > -- > Tom ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 05/12] riscv: Add Kconfig to support RISC-V
2017-12-22 23:30 GMT+08:00 Tom Rini : > On Fri, Dec 22, 2017 at 03:44:22PM +0800, Andes wrote: > >> From: Rick Chen >> >> Add Kconfig and makefile for RISC-V >> >> Signed-off-by: Rick Chen >> Signed-off-by: Rick Chen >> Signed-off-by: Greentime Hu >> Cc: Padmarao Begari >> --- >> arch/riscv/Kconfig | 42 ++ >> arch/riscv/Makefile | 11 +++ >> arch/riscv/config.mk | 33 + >> 3 files changed, 86 insertions(+), 0 deletions(-) >> create mode 100644 arch/riscv/Kconfig >> create mode 100644 arch/riscv/Makefile >> create mode 100644 arch/riscv/config.mk > > This should also touch the top-level MAINTAINERS, thanks! > I will touch the top-level MAINTAINERS in the next version. Thanks for reviewing. Rick > -- > Tom ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
