[U-Boot] [PATCH V3 6/8] dts: peach_pit: Add SLP and RST GPIO properties in parade DT node
Now that parade driver supports reading SLP and RST GPIO
from DT, specify the same in parade DT node.
Signed-off-by: Ajay Kumar
Reviewed-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/dts/exynos5420-peach-pit.dts |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts
b/arch/arm/dts/exynos5420-peach-pit.dts
index b801de9..3ad4728 100644
--- a/arch/arm/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -67,6 +67,8 @@
edp-lvds-bridge@48 {
compatible = "parade,ps8625";
reg = <0x48>;
+ sleep-gpio = <&gpx3 5 GPIO_ACTIVE_HIGH>;
+ reset-gpio = <&gpy7 7 GPIO_ACTIVE_HIGH>;
};
};
--
1.7.9.5
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[U-Boot] [PATCH V3 8/8] smdk5420: Remove GPIO enums
Remove GPIOs from smdk5420 board file and because the same
is already specified via DT.
Signed-off-by: Ajay Kumar
Reviewed-by: Simon Glass
Tested-by: Simon Glass
---
board/samsung/smdk5420/smdk5420.c | 15 ---
1 file changed, 15 deletions(-)
diff --git a/board/samsung/smdk5420/smdk5420.c
b/board/samsung/smdk5420/smdk5420.c
index 1aca9fa..82f607b 100644
--- a/board/samsung/smdk5420/smdk5420.c
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -58,16 +58,6 @@ void exynos_lcd_power_on(void)
mdelay(5);
- /* TODO(ajaykumar...@samsung.com): Use device tree */
- gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");
- gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */
- mdelay(10);
- gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");
- gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */
- gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");
- gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
- gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
-
if (has_edp_bridge())
if (parade_init(gd->fdt_blob))
printf("%s: ps8625_init() failed\n", __func__);
@@ -75,11 +65,6 @@ void exynos_lcd_power_on(void)
void exynos_backlight_on(unsigned int onoff)
{
- /* For PWM */
- gpio_request(EXYNOS5420_GPIO_B20, "backlight_on");
- gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(0x1));
- gpio_set_value(EXYNOS5420_GPIO_B20, 1);
-
#ifdef CONFIG_POWER_TPS65090
tps65090_fet_enable(1);
#endif
--
1.7.9.5
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[U-Boot] [PATCH V3 7/8] dts: peach_pi: Add DT properties needed for display
Add backlight enable GPIO, and delay needed for panel powerup via FIMD DT node. Signed-off-by: Ajay Kumar Reviewed-by: Simon Glass Tested-by: Simon Glass --- arch/arm/dts/exynos5800-peach-pi.dts |3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts index e4bc100..494f764 100644 --- a/arch/arm/dts/exynos5800-peach-pi.dts +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -144,10 +144,13 @@ samsung,vl-vfpd = <10>; samsung,vl-cmd-allow-len = <0xf>; + samsung,power-on-delay = <3>; samsung,winid = <3>; samsung,interface-mode = <1>; samsung,dp-enabled = <1>; samsung,dual-lcd-enabled = <0>; + + samsung,bl-en-gpio = <&gpx2 2 GPIO_ACTIVE_HIGH>; }; }; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 0/8] peach_pi: Add support for FIMD and DP
Add support for the eDP panel supported on peach_pi. Changes since V1: -- Address comments for clock changes -- Remove the use of GPIO enums, and use DT to specify GPIOs. Changes since V2: -- Address comments for clock patch and modify GPIO usage as specified by Simon. Ajay Kumar (8): [PATCH V3 1/8] arm: exynos: add display clocks for Exynos5800 [PATCH V3 2/8] Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels [PATCH V3 3/8] video: exynos_fb: configure backlight GPIOs if specified in DT [PATCH V3 4/8] video: parade: configure SLP and RST GPIOs if specified in DT [PATCH V3 5/8] dts: exynos54xx: Add samsung,pwm-out-gpio property to FIMD node [PATCH V3 6/8] dts: peach_pit: Add SLP and RST GPIO properties in parade DT node [PATCH V3 7/8] dts: peach_pi: Add DT properties needed for display [PATCH V3 8/8] smdk5420: Remove GPIO enums arch/arm/cpu/armv7/exynos/clock.c | 65 ++-- arch/arm/cpu/armv7/exynos/clock_init_exynos5.c |4 +- arch/arm/dts/exynos5420-peach-pit.dts |2 + arch/arm/dts/exynos54xx.dtsi |1 + arch/arm/dts/exynos5800-peach-pi.dts |3 ++ arch/arm/include/asm/arch-exynos/clk.h |3 ++ board/samsung/smdk5420/smdk5420.c | 15 -- doc/device-tree-bindings/video/exynos-fb.txt |2 + drivers/video/exynos_fb.c | 21 drivers/video/parade.c | 11 10 files changed, 107 insertions(+), 20 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 2/8] Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels
The existing setting for rpll_sdiv generates 70.5Mhz RPLL
video clock to drive 1366x768 panel on peach_pit.
This clock rate is not sufficient to drive 1920x1080 panel on peach-pi.
So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock
which can drive peach-pi LCD.
This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD
divider at IP level will get set to 1(the required divider setting
will be calculated and set by exynos_fimd_set_clock()) and hence
peach-pit LCD still works fine.
Signed-off-by: Ajay Kumar
Reviewed-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/cpu/armv7/exynos/clock_init_exynos5.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
index 0aff3d0..0200fd1 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
+++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
@@ -179,10 +179,10 @@ struct mem_timings mem_timings[] = {
.spll_mdiv = 0xc8,
.spll_pdiv = 0x3,
.spll_sdiv = 0x2,
- /* RPLL @70.5Mhz */
+ /* RPLL @141Mhz */
.rpll_mdiv = 0x5E,
.rpll_pdiv = 0x2,
- .rpll_sdiv = 0x4,
+ .rpll_sdiv = 0x3,
.direct_cmd_msr = {
0x00020018, 0x0003, 0x00010046, 0x0d70,
--
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[U-Boot] [PATCH V3 1/8] arm: exynos: add display clocks for Exynos5800
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by
exynos video driver.
Signed-off-by: Ajay Kumar
Reviewed-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/cpu/armv7/exynos/clock.c | 65 ++--
arch/arm/include/asm/arch-exynos/clk.h |3 ++
2 files changed, 65 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index c6455c2..8bee324 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -14,7 +14,6 @@
#define PLL_DIV_1024 1024
#define PLL_DIV_65535 65535
#define PLL_DIV_65536 65536
-
/* *
* This structure is to store the src bit, div bit and prediv bit
* positions of the peripheral clocks of the src and div registers
@@ -1028,6 +1027,40 @@ static unsigned long exynos5420_get_lcd_clk(void)
return pclk;
}
+static unsigned long exynos5800_get_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+* CLK_SRC_DISP10
+* CLKMUX_FIMD1 [6:4]
+*/
+ sel = (readl(&clk->src_disp10) >> 4) & 0x7;
+
+ if (sel) {
+ /*
+* Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into
+* PLLs. The first element is a placeholder to bypass the
+* default settig.
+*/
+ const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL,
+ RPLL};
+ sclk = get_pll_clk(reg_map[sel]);
+ } else
+ sclk = CONFIG_SYS_CLK_FREQ;
+ /*
+* CLK_DIV_DISP10
+* FIMD1_RATIO [3:0]
+*/
+ ratio = readl(&clk->div_disp10) & 0xf;
+
+ return sclk / (ratio + 1);
+}
+
void exynos4_set_lcd_clk(void)
{
struct exynos4_clock *clk =
@@ -1159,6 +1192,28 @@ void exynos5420_set_lcd_clk(void)
writel(cfg, &clk->div_disp10);
}
+void exynos5800_set_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned int cfg;
+
+ /*
+* Use RPLL for pixel clock
+* CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]
+* ==
+* 111: SCLK_RPLL
+*/
+ cfg = readl(&clk->src_disp10) | (0x7 << 4);
+ writel(cfg, &clk->src_disp10);
+
+ /*
+* CLK_DIV_DISP10
+* FIMD1_RATIO [3:0]
+*/
+ clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0);
+}
+
void exynos4_set_mipi_clk(void)
{
struct exynos4_clock *clk =
@@ -1646,8 +1701,10 @@ unsigned long get_lcd_clk(void)
if (cpu_is_exynos4())
return exynos4_get_lcd_clk();
else {
- if (proid_is_exynos5420() || proid_is_exynos5800())
+ if (proid_is_exynos5420())
return exynos5420_get_lcd_clk();
+ else if (proid_is_exynos5800())
+ return exynos5800_get_lcd_clk();
else
return exynos5_get_lcd_clk();
}
@@ -1660,8 +1717,10 @@ void set_lcd_clk(void)
else {
if (proid_is_exynos5250())
exynos5_set_lcd_clk();
- else if (proid_is_exynos5420() || proid_is_exynos5800())
+ else if (proid_is_exynos5420())
exynos5420_set_lcd_clk();
+ else
+ exynos5800_set_lcd_clk();
}
}
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index 2a17dfc..d20b7d2 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -16,6 +16,9 @@
#define BPLL 5
#define RPLL 6
#define SPLL 7
+#define CPLL 8
+#define DPLL 9
+#define IPLL 10
#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8))
#define MASK_RATIO(x) (0xf << (x << 4))
--
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[U-Boot] [PATCH V3 5/8] dts: exynos54xx: Add samsung, pwm-out-gpio property to FIMD node
Now that the exynos_fb driver supports handling backlight GPIO
via DT, specify pwm output property via FIMD DT node.
Signed-off-by: Ajay Kumar
Reviewed-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/dts/exynos54xx.dtsi |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi
index 916cf3a..31fabb1 100644
--- a/arch/arm/dts/exynos54xx.dtsi
+++ b/arch/arm/dts/exynos54xx.dtsi
@@ -168,6 +168,7 @@
fimd@1440 {
/* sysmmu is not used in U-Boot */
samsung,disable-sysmmu;
+ samsung,pwm-out-gpio = <&gpb2 0 GPIO_ACTIVE_HIGH>;
};
dp@145b {
--
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[U-Boot] [PATCH V3 4/8] video: parade: configure SLP and RST GPIOs if specified in DT
Add support to configure EDP_RST GPIO and EDP_SLP GPIO,
if provided in parade DT node.
Signed-off-by: Ajay Kumar
Reviewed-by: Simon Glass
Tested-by: Simon Glass
---
drivers/video/parade.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/video/parade.c b/drivers/video/parade.c
index 0f543f6..ae50971 100644
--- a/drivers/video/parade.c
+++ b/drivers/video/parade.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
/*
* Initialization of the chip is a process of writing certaing values into
@@ -180,6 +181,8 @@ static int parade_write_regs(int base_addr, const struct
reg_data *table)
int parade_init(const void *blob)
{
+ struct gpio_desc rst_gpio;
+ struct gpio_desc slp_gpio;
int bus, old_bus;
int parent;
int node;
@@ -201,6 +204,14 @@ int parade_init(const void *blob)
return -1;
}
+ gpio_request_by_name_nodev(blob, node, "sleep-gpio", 0, &slp_gpio,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+ mdelay(10);
+
+ gpio_request_by_name_nodev(blob, node, "reset-gpio", 0, &rst_gpio,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
bus = i2c_get_bus_num_fdt(parent);
old_bus = i2c_get_bus_num();
--
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[U-Boot] [PATCH V3 3/8] video: exynos_fb: configure backlight GPIOs if specified in DT
Add support to configure PWM_OUT(PWM output) GPIO and
BL_EN(backlight enable) GPIO, if provided in FIMD DT node.
Signed-off-by: Ajay Kumar
Reviewed-by: Simon Glass
Tested-by: Simon Glass
---
doc/device-tree-bindings/video/exynos-fb.txt |2 ++
drivers/video/exynos_fb.c| 21 +
2 files changed, 23 insertions(+)
diff --git a/doc/device-tree-bindings/video/exynos-fb.txt
b/doc/device-tree-bindings/video/exynos-fb.txt
index dc4e44f..b022f61 100644
--- a/doc/device-tree-bindings/video/exynos-fb.txt
+++ b/doc/device-tree-bindings/video/exynos-fb.txt
@@ -61,6 +61,8 @@ Board(panel specific):
disabled with compatible string
"samsung,sysmmu-v3.3", with a "reg" property
holding the register address of FIMD sysmmu.
+ samsung,pwm-out-gpio: PWM output GPIO.
+ samsung,bl-en-gpio: backlight enable GPIO.
Example:
SOC specific part:
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
index c5d7330..8f3b826 100644
--- a/drivers/video/exynos_fb.c
+++ b/drivers/video/exynos_fb.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
#include "exynos_fb.h"
@@ -102,6 +103,10 @@ __weak int exynos_lcd_misc_init(vidinfo_t *vid)
static void lcd_panel_on(vidinfo_t *vid)
{
+ struct gpio_desc pwm_out_gpio;
+ struct gpio_desc bl_en_gpio;
+ unsigned int node;
+
udelay(vid->init_delay);
exynos_backlight_reset();
@@ -121,6 +126,22 @@ static void lcd_panel_on(vidinfo_t *vid)
exynos_backlight_on(1);
+#ifdef CONFIG_OF_CONTROL
+ node = fdtdec_next_compatible(gd->fdt_blob, 0,
+ COMPAT_SAMSUNG_EXYNOS_FIMD);
+ if (node <= 0) {
+ debug("FIMD: Can't get device node for FIMD\n");
+ return;
+ }
+ gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,pwm-out-gpio",
+ 0, &pwm_out_gpio,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+ gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,bl-en-gpio", 0,
+ &bl_en_gpio,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+#endif
exynos_cfg_ldo();
exynos_enable_ldo(1);
--
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Re: [U-Boot] [PATCH V2 0/8] peach_pi: Add support for FIMD and DP
On Tue, Mar 3, 2015 at 7:33 PM, Ajay Kumar wrote: > Add support for the eDP panel supported on peach_pi. > > Changes since V1: > -- Address comments for clock changes > -- Remove the use of GPIO enums, and use DT to specify GPIOs. > > Ajay Kumar (8): > [PATCH V2 1/8] arm: exynos: add display clocks for Exynos5800 > [PATCH V2 2/8] Exynos5: Fix rpll_sdiv to support both peach-pit and > peach-pi panels > [PATCH V2 3/8] video: exynos_fb: configure backlight GPIOs if specified in > DT > [PATCH V2 4/8] video: parade: configure SLP and RST GPIOs if specified in DT > [PATCH V2 5/8] dts: exynos54xx: Add samsung,pwm-out-gpio property to FIMD > node > [PATCH V2 6/8] dts: peach_pit: Add SLP and RST GPIO properties in parade DT > node > [PATCH V2 7/8] dts: peach_pi: Add DT properties needed for display > [PATCH V2 8/8] smdk5420: Remove GPIO enums > > arch/arm/cpu/armv7/exynos/clock.c | 66 > ++-- > arch/arm/cpu/armv7/exynos/clock_init_exynos5.c |4 +- > arch/arm/dts/exynos5420-peach-pit.dts |2 + > arch/arm/dts/exynos54xx.dtsi |1 + > arch/arm/dts/exynos5800-peach-pi.dts |3 ++ > arch/arm/include/asm/arch-exynos/clk.h |3 ++ > board/samsung/smdk5420/smdk5420.c | 15 -- > doc/device-tree-bindings/video/exynos-fb.txt |2 + > drivers/video/exynos_fb.c | 23 + > drivers/video/parade.c | 15 ++ > 10 files changed, 114 insertions(+), 20 deletions(-) > > -- > 1.7.9.5 > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/8] Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels
The existing setting for rpll_sdiv generates 70.5Mhz RPLL
video clock to drive 1366x768 panel on peach_pit.
This clock rate is not sufficient to drive 1920x1080 panel on peach-pi.
So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock
which can drive peach-pi LCD.
This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD
divider at IP level will get set to 1(the required divider setting
will be calculated and set by exynos_fimd_set_clock()) and hence
peach-pit LCD still works fine.
Signed-off-by: Ajay Kumar
---
arch/arm/cpu/armv7/exynos/clock_init_exynos5.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
index 0aff3d0..0200fd1 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
+++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
@@ -179,10 +179,10 @@ struct mem_timings mem_timings[] = {
.spll_mdiv = 0xc8,
.spll_pdiv = 0x3,
.spll_sdiv = 0x2,
- /* RPLL @70.5Mhz */
+ /* RPLL @141Mhz */
.rpll_mdiv = 0x5E,
.rpll_pdiv = 0x2,
- .rpll_sdiv = 0x4,
+ .rpll_sdiv = 0x3,
.direct_cmd_msr = {
0x00020018, 0x0003, 0x00010046, 0x0d70,
--
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[U-Boot] [PATCH V2 1/8] arm: exynos: add display clocks for Exynos5800
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by
exynos video driver.
Signed-off-by: Ajay Kumar
---
arch/arm/cpu/armv7/exynos/clock.c | 66 ++--
arch/arm/include/asm/arch-exynos/clk.h |3 ++
2 files changed, 66 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index c6455c2..23f8ff7 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -14,7 +14,7 @@
#define PLL_DIV_1024 1024
#define PLL_DIV_65535 65535
#define PLL_DIV_65536 65536
-
+#define FIN_HZ 2400
/* *
* This structure is to store the src bit, div bit and prediv bit
* positions of the peripheral clocks of the src and div registers
@@ -1028,6 +1028,40 @@ static unsigned long exynos5420_get_lcd_clk(void)
return pclk;
}
+static unsigned long exynos5800_get_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+* CLK_SRC_DISP10
+* CLKMUX_FIMD1 [6:4]
+*/
+ sel = (readl(&clk->src_disp10) >> 4) & 0x7;
+
+ if (sel) {
+ /*
+* Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into
+* PLLs. The first element is a placeholder to bypass the
+* default settig.
+*/
+ const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL,
+ RPLL};
+ sclk = get_pll_clk(reg_map[sel]);
+ } else
+ sclk = FIN_HZ;
+ /*
+* CLK_DIV_DISP10
+* FIMD1_RATIO [3:0]
+*/
+ ratio = readl(&clk->div_disp10) & 0xf;
+
+ return sclk / (ratio + 1);
+}
+
void exynos4_set_lcd_clk(void)
{
struct exynos4_clock *clk =
@@ -1159,6 +1193,28 @@ void exynos5420_set_lcd_clk(void)
writel(cfg, &clk->div_disp10);
}
+void exynos5800_set_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned int cfg;
+
+ /*
+* Use RPLL for pixel clock
+* CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]
+* ==
+* 111: SCLK_RPLL
+*/
+ cfg = readl(&clk->src_disp10) | (0x7 << 4);
+ writel(cfg, &clk->src_disp10);
+
+ /*
+* CLK_DIV_DISP10
+* FIMD1_RATIO [3:0]
+*/
+ clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0);
+}
+
void exynos4_set_mipi_clk(void)
{
struct exynos4_clock *clk =
@@ -1646,8 +1702,10 @@ unsigned long get_lcd_clk(void)
if (cpu_is_exynos4())
return exynos4_get_lcd_clk();
else {
- if (proid_is_exynos5420() || proid_is_exynos5800())
+ if (proid_is_exynos5420())
return exynos5420_get_lcd_clk();
+ else if (proid_is_exynos5800())
+ return exynos5800_get_lcd_clk();
else
return exynos5_get_lcd_clk();
}
@@ -1660,8 +1718,10 @@ void set_lcd_clk(void)
else {
if (proid_is_exynos5250())
exynos5_set_lcd_clk();
- else if (proid_is_exynos5420() || proid_is_exynos5800())
+ else if (proid_is_exynos5420())
exynos5420_set_lcd_clk();
+ else
+ exynos5800_set_lcd_clk();
}
}
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index 2a17dfc..d20b7d2 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -16,6 +16,9 @@
#define BPLL 5
#define RPLL 6
#define SPLL 7
+#define CPLL 8
+#define DPLL 9
+#define IPLL 10
#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8))
#define MASK_RATIO(x) (0xf << (x << 4))
--
1.7.9.5
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[U-Boot] [PATCH V2 6/8] dts: peach_pit: Add SLP and RST GPIO properties in parade DT node
Now that parade driver supports reading SLP and RST GPIO
from DT, specify the same in parade DT node.
Signed-off-by: Ajay Kumar
---
arch/arm/dts/exynos5420-peach-pit.dts |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts
b/arch/arm/dts/exynos5420-peach-pit.dts
index b801de9..3ad4728 100644
--- a/arch/arm/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -67,6 +67,8 @@
edp-lvds-bridge@48 {
compatible = "parade,ps8625";
reg = <0x48>;
+ sleep-gpio = <&gpx3 5 GPIO_ACTIVE_HIGH>;
+ reset-gpio = <&gpy7 7 GPIO_ACTIVE_HIGH>;
};
};
--
1.7.9.5
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[U-Boot] [PATCH V2 8/8] smdk5420: Remove GPIO enums
Remove GPIOs from smdk5420 board file and because the same
is already specified via DT.
Signed-off-by: Ajay Kumar
---
board/samsung/smdk5420/smdk5420.c | 15 ---
1 file changed, 15 deletions(-)
diff --git a/board/samsung/smdk5420/smdk5420.c
b/board/samsung/smdk5420/smdk5420.c
index 1aca9fa..82f607b 100644
--- a/board/samsung/smdk5420/smdk5420.c
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -58,16 +58,6 @@ void exynos_lcd_power_on(void)
mdelay(5);
- /* TODO(ajaykumar...@samsung.com): Use device tree */
- gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");
- gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */
- mdelay(10);
- gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");
- gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */
- gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");
- gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
- gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
-
if (has_edp_bridge())
if (parade_init(gd->fdt_blob))
printf("%s: ps8625_init() failed\n", __func__);
@@ -75,11 +65,6 @@ void exynos_lcd_power_on(void)
void exynos_backlight_on(unsigned int onoff)
{
- /* For PWM */
- gpio_request(EXYNOS5420_GPIO_B20, "backlight_on");
- gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(0x1));
- gpio_set_value(EXYNOS5420_GPIO_B20, 1);
-
#ifdef CONFIG_POWER_TPS65090
tps65090_fet_enable(1);
#endif
--
1.7.9.5
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[U-Boot] [PATCH V2 7/8] dts: peach_pi: Add DT properties needed for display
Add backlight enable GPIO, and delay needed for panel powerup via FIMD DT node. Signed-off-by: Ajay Kumar --- arch/arm/dts/exynos5800-peach-pi.dts |3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts index e4bc100..494f764 100644 --- a/arch/arm/dts/exynos5800-peach-pi.dts +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -144,10 +144,13 @@ samsung,vl-vfpd = <10>; samsung,vl-cmd-allow-len = <0xf>; + samsung,power-on-delay = <3>; samsung,winid = <3>; samsung,interface-mode = <1>; samsung,dp-enabled = <1>; samsung,dual-lcd-enabled = <0>; + + samsung,bl-en-gpio = <&gpx2 2 GPIO_ACTIVE_HIGH>; }; }; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 4/8] video: parade: configure SLP and RST GPIOs if specified in DT
Add support to configure EDP_RST GPIO and EDP_SLP GPIO,
if provided in parade DT node.
Signed-off-by: Ajay Kumar
---
drivers/video/parade.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/video/parade.c b/drivers/video/parade.c
index 0f543f6..525ef07 100644
--- a/drivers/video/parade.c
+++ b/drivers/video/parade.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
/*
* Initialization of the chip is a process of writing certaing values into
@@ -180,6 +181,8 @@ static int parade_write_regs(int base_addr, const struct
reg_data *table)
int parade_init(const void *blob)
{
+ struct gpio_desc rst_gpio;
+ struct gpio_desc slp_gpio;
int bus, old_bus;
int parent;
int node;
@@ -201,6 +204,18 @@ int parade_init(const void *blob)
return -1;
}
+ gpio_request_by_name_nodev(blob, node, "sleep-gpio", 0, &slp_gpio,
+ GPIOD_IS_OUT);
+ if (dm_gpio_is_valid(&slp_gpio))
+ dm_gpio_set_value(&slp_gpio, 1);
+
+ mdelay(10);
+
+ gpio_request_by_name_nodev(blob, node, "reset-gpio", 0, &rst_gpio,
+ GPIOD_IS_OUT);
+ if (dm_gpio_is_valid(&rst_gpio))
+ dm_gpio_set_value(&rst_gpio, 1);
+
bus = i2c_get_bus_num_fdt(parent);
old_bus = i2c_get_bus_num();
--
1.7.9.5
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[U-Boot] [PATCH V2 5/8] dts: exynos54xx: Add samsung, pwm-out-gpio property to FIMD node
Now that the exynos_fb driver supports handling backlight GPIO
via DT, specify pwm output property via FIMD DT node.
Signed-off-by: Ajay Kumar
---
arch/arm/dts/exynos54xx.dtsi |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi
index 916cf3a..31fabb1 100644
--- a/arch/arm/dts/exynos54xx.dtsi
+++ b/arch/arm/dts/exynos54xx.dtsi
@@ -168,6 +168,7 @@
fimd@1440 {
/* sysmmu is not used in U-Boot */
samsung,disable-sysmmu;
+ samsung,pwm-out-gpio = <&gpb2 0 GPIO_ACTIVE_HIGH>;
};
dp@145b {
--
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[U-Boot] [PATCH V2 0/8] peach_pi: Add support for FIMD and DP
Add support for the eDP panel supported on peach_pi. Changes since V1: -- Address comments for clock changes -- Remove the use of GPIO enums, and use DT to specify GPIOs. Ajay Kumar (8): [PATCH V2 1/8] arm: exynos: add display clocks for Exynos5800 [PATCH V2 2/8] Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels [PATCH V2 3/8] video: exynos_fb: configure backlight GPIOs if specified in DT [PATCH V2 4/8] video: parade: configure SLP and RST GPIOs if specified in DT [PATCH V2 5/8] dts: exynos54xx: Add samsung,pwm-out-gpio property to FIMD node [PATCH V2 6/8] dts: peach_pit: Add SLP and RST GPIO properties in parade DT node [PATCH V2 7/8] dts: peach_pi: Add DT properties needed for display [PATCH V2 8/8] smdk5420: Remove GPIO enums arch/arm/cpu/armv7/exynos/clock.c | 66 ++-- arch/arm/cpu/armv7/exynos/clock_init_exynos5.c |4 +- arch/arm/dts/exynos5420-peach-pit.dts |2 + arch/arm/dts/exynos54xx.dtsi |1 + arch/arm/dts/exynos5800-peach-pi.dts |3 ++ arch/arm/include/asm/arch-exynos/clk.h |3 ++ board/samsung/smdk5420/smdk5420.c | 15 -- doc/device-tree-bindings/video/exynos-fb.txt |2 + drivers/video/exynos_fb.c | 23 + drivers/video/parade.c | 15 ++ 10 files changed, 114 insertions(+), 20 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 3/8] video: exynos_fb: configure backlight GPIOs if specified in DT
Add support to configure PWM_OUT(PWM output) GPIO and
BL_EN(backlight enable) GPIO, if provided in FIMD DT node.
Signed-off-by: Ajay Kumar
---
doc/device-tree-bindings/video/exynos-fb.txt |2 ++
drivers/video/exynos_fb.c| 23 +++
2 files changed, 25 insertions(+)
diff --git a/doc/device-tree-bindings/video/exynos-fb.txt
b/doc/device-tree-bindings/video/exynos-fb.txt
index dc4e44f..b022f61 100644
--- a/doc/device-tree-bindings/video/exynos-fb.txt
+++ b/doc/device-tree-bindings/video/exynos-fb.txt
@@ -61,6 +61,8 @@ Board(panel specific):
disabled with compatible string
"samsung,sysmmu-v3.3", with a "reg" property
holding the register address of FIMD sysmmu.
+ samsung,pwm-out-gpio: PWM output GPIO.
+ samsung,bl-en-gpio: backlight enable GPIO.
Example:
SOC specific part:
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
index c5d7330..be85ed8 100644
--- a/drivers/video/exynos_fb.c
+++ b/drivers/video/exynos_fb.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
#include "exynos_fb.h"
@@ -102,6 +103,10 @@ __weak int exynos_lcd_misc_init(vidinfo_t *vid)
static void lcd_panel_on(vidinfo_t *vid)
{
+ struct gpio_desc pwm_out_gpio;
+ struct gpio_desc bl_en_gpio;
+ unsigned int node;
+
udelay(vid->init_delay);
exynos_backlight_reset();
@@ -121,6 +126,24 @@ static void lcd_panel_on(vidinfo_t *vid)
exynos_backlight_on(1);
+#ifdef CONFIG_OF_CONTROL
+ node = fdtdec_next_compatible(gd->fdt_blob, 0,
+ COMPAT_SAMSUNG_EXYNOS_FIMD);
+ if (node <= 0) {
+ debug("FIMD: Can't get device node for FIMD\n");
+ return;
+ }
+ gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,pwm-out-gpio",
+ 0, &pwm_out_gpio, GPIOD_IS_OUT);
+ if (dm_gpio_is_valid(&pwm_out_gpio))
+ dm_gpio_set_value(&pwm_out_gpio, 1);
+
+ gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,bl-en-gpio", 0,
+ &bl_en_gpio, GPIOD_IS_OUT);
+ if (dm_gpio_is_valid(&bl_en_gpio))
+ dm_gpio_set_value(&bl_en_gpio, 1);
+
+#endif
exynos_cfg_ldo();
exynos_enable_ldo(1);
--
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Re: [U-Boot] [PATCH 2/5] arm: exynos: add display clocks for Exynos5800
Hi Simon,
On Mon, Mar 2, 2015 at 7:53 AM, Simon Glass wrote:
> Hi Ajay,
>
> On 8 December 2014 at 15:40, Simon Glass wrote:
>> Hi Ajay,
>>
>>
>> On 7 December 2014 at 22:43, Ajay kumar wrote:
>>>
>>> Hi Minkyu,
>>>
>>>
>>> On Mon, Dec 8, 2014 at 11:07 AM, Ajay kumar wrote:
>>> > On Fri, Dec 5, 2014 at 9:02 PM, Minkyu Kang wrote:
>>> >> Dear Ajay Kumar,
>>> >>
>>> >> On 5 December 2014 at 23:13, Ajay Kumar
>>> >> wrote:
>>> >>
>>> >>> Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by
>>> >>> exynos video driver.
>>> >>>
>>> >>> Signed-off-by: Ajay Kumar
>>> >>> ---
>>> >>> arch/arm/cpu/armv7/exynos/clock.c | 63
>>> >>> +++-
>>> >>> arch/arm/include/asm/arch-exynos/clk.h |3 ++
>>> >>> 2 files changed, 64 insertions(+), 2 deletions(-)
>>> >>>
>>> >>> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
>>> >>> b/arch/arm/cpu/armv7/exynos/clock.c
>>> >>> index 8fab135..1a34ad6 100644
>>> >>> --- a/arch/arm/cpu/armv7/exynos/clock.c
>>> >>> +++ b/arch/arm/cpu/armv7/exynos/clock.c
>>> >>> @@ -1066,6 +1066,36 @@ static unsigned long
>>> >>> exynos5420_get_lcd_clk(void)
>>> >>> return pclk;
>>> >>> }
>>> >>>
>>> >>> +static unsigned long exynos5800_get_lcd_clk(void)
>>> >>> +{
>>> >>> + struct exynos5420_clock *clk =
>>> >>> + (struct exynos5420_clock *)samsung_get_base_clock();
>>> >>> + unsigned long sclk;
>>> >>> + unsigned sel;
>>> >>>
>>> >>
>>> >> just unsigned? why don't you specify in detail?
>>> I will fix this.
>>>
>>> >>
>>> >>> + unsigned ratio;
>>> >>> +
>>> >>> + sel = (readl(&clk->src_disp10) >> 4) & 7;
>>> >>>
>>> >>
>>> >> please add comment how you get "sel" from disp10.
>>> >> and if 7 means mask then please use 0x7. it looks more clearly.
>>> Ok.
>>>
>>> >> +
>>> >>> + /*
>>> >>> +* Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into
>>> >>> +* PLLs. The first element is a placeholder to bypass the
>>> >>> +* default settig.
>>> >>> +*/
>>> >>> + const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL,
>>> >>> + IPLL, EPLL, RPLL};
>>> >>>
>>> >>
>>> >> please don't define local variable at middle of function.
>>> >> you can move it to top of the function or
>>> >> it seems to use sel is true then you can move it into the if statement.
>>> I will move this to the top of the function.
>>>
>>> >>
>>> >>> + if (sel)
>>> >>> + sclk = get_pll_clk(reg_map[sel]);
>>> >>> + else
>>> >>> + sclk = 2400;
>>> >>>
>>> >>
>>> >> please define this value.
>>> Ok.
>>>
>>> >>
>>> >>> + /*
>>> >>> +* CLK_DIV_DISP10
>>> >>> +* FIMD1_RATIO [3:0]
>>> >>> +*/
>>> >>> + ratio = readl(&clk->div_disp10) & 0xf;
>>> >>> +
>>> >>> + return sclk / (ratio + 1);
>>> >>> +}
>>> >>> +
>>> >>> void exynos4_set_lcd_clk(void)
>>> >>> {
>>> >>> struct exynos4_clock *clk =
>>> >>> @@ -1197,6 +1227,31 @@ void exynos5420_set_lcd_clk(void)
>>> >>> writel(cfg, &clk->div_disp10);
>>> >>> }
>>> >>>
>>> >>> +void exynos5800_set_lcd_clk(void)
>>> >>> +{
>>> >>> + struct exynos5420_clock *clk =
>>> >>> + (struct exynos5420_clock *)samsung_get_base_clock();
>>> >>> + unsigned
Re: [U-Boot] [PATCH 4/5] exynos5420: Add LCD and LED powerup settings for peach-pi
Hi,
On Fri, Dec 5, 2014 at 10:12 PM, Simon Glass wrote:
> Hi,
>
> On 5 December 2014 at 08:42, Sjoerd Simons
> wrote:
>> On Fri, 2014-12-05 at 19:43 +0530, Ajay Kumar wrote:
>>> Add code to support powerup sequence for peach-pi LCD.
>>>
>>> Signed-off-by: Ajay Kumar
>>> ---
>>> board/samsung/smdk5420/smdk5420.c | 32 +---
>>> 1 file changed, 21 insertions(+), 11 deletions(-)
>>>
>>> diff --git a/board/samsung/smdk5420/smdk5420.c
>>> b/board/samsung/smdk5420/smdk5420.c
>>> index a691222..915125e 100644
>>> --- a/board/samsung/smdk5420/smdk5420.c
>>> +++ b/board/samsung/smdk5420/smdk5420.c
>>> @@ -73,19 +73,24 @@ void exynos_lcd_power_on(void)
>>>
>>> mdelay(5);
>>>
>>> - /* TODO(ajaykumar...@samsung.com): Use device tree */
>>> - gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");
>>> - gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */
>>> - mdelay(10);
>>> - gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");
>>> - gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */
>>> - gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");
>>> - gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
>>> - gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
>>> -
>>> - if (has_edp_bridge())
>>> + if (has_edp_bridge()) {
>>> + /* TODO(ajaykumar...@samsung.com): Use device tree */
>>> + gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");
>>> + gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */
>>> + mdelay(10);
>>> + gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");
>>> + gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */
>>> + gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");
>>> + gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
>>> + gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
>>> +
>>> if (parade_init(gd->fdt_blob))
>>> printf("%s: ps8625_init() failed\n", __func__);
>>> + } else {
>>> + gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");
>>> + gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
>>> + gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
>>> + }
>>
>> Any chance you could switch to using device-tree while changing this
>> area. On SMDK5420 and XU3 EXYNOS5420_GPIO_X26 is used for USB so there
>> is a bit of a potentially nastly clash there.
>
> Yes we should really do that.
I am trying to consolidate what all needs to be done for Exynos5250
and Exynos5420,
in order to remove LCD routines from the board files.
Here are my observations:
1) A separate driver for ptn3460 should be created.
2) Need a place holder for tps65090 FET settings.
3) I am planning to move all the LCD_EN/BACKLIGHT_EN GPIOs
to the "weak function definitions" in exynos_fb.c.
In that case, we have a limitation. All boards under a specific
SOC should conform
to use only device tree or use only define board level LCD routines.
ex: smdk5250 and snow - both need to use device tree to specify LCD details,
or both need to define LCD powerup routines. It cannot be
like snow uses device tree,
and smdk5250 defines LCD routines in smdk5250 board file.
Ajay
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Re: [U-Boot] [PATCH 2/5] arm: exynos: add display clocks for Exynos5800
Hi Minkyu,
On Mon, Dec 8, 2014 at 11:07 AM, Ajay kumar wrote:
> On Fri, Dec 5, 2014 at 9:02 PM, Minkyu Kang wrote:
>> Dear Ajay Kumar,
>>
>> On 5 December 2014 at 23:13, Ajay Kumar wrote:
>>
>>> Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by
>>> exynos video driver.
>>>
>>> Signed-off-by: Ajay Kumar
>>> ---
>>> arch/arm/cpu/armv7/exynos/clock.c | 63
>>> +++-
>>> arch/arm/include/asm/arch-exynos/clk.h |3 ++
>>> 2 files changed, 64 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
>>> b/arch/arm/cpu/armv7/exynos/clock.c
>>> index 8fab135..1a34ad6 100644
>>> --- a/arch/arm/cpu/armv7/exynos/clock.c
>>> +++ b/arch/arm/cpu/armv7/exynos/clock.c
>>> @@ -1066,6 +1066,36 @@ static unsigned long exynos5420_get_lcd_clk(void)
>>> return pclk;
>>> }
>>>
>>> +static unsigned long exynos5800_get_lcd_clk(void)
>>> +{
>>> + struct exynos5420_clock *clk =
>>> + (struct exynos5420_clock *)samsung_get_base_clock();
>>> + unsigned long sclk;
>>> + unsigned sel;
>>>
>>
>> just unsigned? why don't you specify in detail?
I will fix this.
>>
>>> + unsigned ratio;
>>> +
>>> + sel = (readl(&clk->src_disp10) >> 4) & 7;
>>>
>>
>> please add comment how you get "sel" from disp10.
>> and if 7 means mask then please use 0x7. it looks more clearly.
Ok.
>> +
>>> + /*
>>> +* Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into
>>> +* PLLs. The first element is a placeholder to bypass the
>>> +* default settig.
>>> +*/
>>> + const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL,
>>> + IPLL, EPLL, RPLL};
>>>
>>
>> please don't define local variable at middle of function.
>> you can move it to top of the function or
>> it seems to use sel is true then you can move it into the if statement.
I will move this to the top of the function.
>>
>>> + if (sel)
>>> + sclk = get_pll_clk(reg_map[sel]);
>>> + else
>>> + sclk = 2400;
>>>
>>
>> please define this value.
Ok.
>>
>>> + /*
>>> +* CLK_DIV_DISP10
>>> +* FIMD1_RATIO [3:0]
>>> +*/
>>> + ratio = readl(&clk->div_disp10) & 0xf;
>>> +
>>> + return sclk / (ratio + 1);
>>> +}
>>> +
>>> void exynos4_set_lcd_clk(void)
>>> {
>>> struct exynos4_clock *clk =
>>> @@ -1197,6 +1227,31 @@ void exynos5420_set_lcd_clk(void)
>>> writel(cfg, &clk->div_disp10);
>>> }
>>>
>>> +void exynos5800_set_lcd_clk(void)
>>> +{
>>> + struct exynos5420_clock *clk =
>>> + (struct exynos5420_clock *)samsung_get_base_clock();
>>> + unsigned int cfg;
>>> +
>>> + /*
>>> +* Use RPLL for pixel clock
>>> +* CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]
>>> +* ==
>>> +* 111: SCLK_RPLL
>>> +*/
>>> + cfg = readl(&clk->src_disp10) | (7 << 4);
>>> + writel(cfg, &clk->src_disp10);
>>> +
>>> + /*
>>> +* CLK_DIV_DISP10
>>> +* FIMD1_RATIO [3:0]
>>> +*/
>>> + cfg = readl(&clk->div_disp10);
>>> + cfg &= ~(0xf << 0);
>>> + cfg |= (0 << 0);
>>>
>>
>> it looks meaningless.
Why not?
I agree that the calculation can be skipped, and directly FIMD
clock divider can be set to 0. But, I prefer to keep the readability.
In fact, similar "meaningless" code is already part of the tree:
http://git.denx.de/?p=u-boot/u-boot-samsung.git;a=blob;f=arch/arm/cpu/armv7/exynos/clock.c;h=8fab135bebf4ef6900677847b60a8e1a1520254c;hb=HEAD#l1194
Ajay
>>
>>> + writel(cfg, &clk->div_disp10);
>>> +}
>>> +
>>> void exynos4_set_mipi_clk(void)
>>> {
>>> struct exynos4_clock *clk =
>>> @@ -1669,8 +1724,10 @@ unsigned long get_lcd_clk(void)
>>> if (cpu_is_exynos4())
>>> return exynos4_get_lcd_clk();
>>>
Re: [U-Boot] [PATCH 2/5] arm: exynos: add display clocks for Exynos5800
On Fri, Dec 5, 2014 at 9:02 PM, Minkyu Kang wrote:
> Dear Ajay Kumar,
>
> On 5 December 2014 at 23:13, Ajay Kumar wrote:
>
>> Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by
>> exynos video driver.
>>
>> Signed-off-by: Ajay Kumar
>> ---
>> arch/arm/cpu/armv7/exynos/clock.c | 63
>> +++-
>> arch/arm/include/asm/arch-exynos/clk.h |3 ++
>> 2 files changed, 64 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
>> b/arch/arm/cpu/armv7/exynos/clock.c
>> index 8fab135..1a34ad6 100644
>> --- a/arch/arm/cpu/armv7/exynos/clock.c
>> +++ b/arch/arm/cpu/armv7/exynos/clock.c
>> @@ -1066,6 +1066,36 @@ static unsigned long exynos5420_get_lcd_clk(void)
>> return pclk;
>> }
>>
>> +static unsigned long exynos5800_get_lcd_clk(void)
>> +{
>> + struct exynos5420_clock *clk =
>> + (struct exynos5420_clock *)samsung_get_base_clock();
>> + unsigned long sclk;
>> + unsigned sel;
>>
>
> just unsigned? why don't you specify in detail?
>
>
>> + unsigned ratio;
>> +
>> + sel = (readl(&clk->src_disp10) >> 4) & 7;
>>
>
> please add comment how you get "sel" from disp10.
> and if 7 means mask then please use 0x7. it looks more clearly.
>
> +
>> + /*
>> +* Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into
>> +* PLLs. The first element is a placeholder to bypass the
>> +* default settig.
>> +*/
>> + const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL,
>> + IPLL, EPLL, RPLL};
>>
>
> please don't define local variable at middle of function.
> you can move it to top of the function or
> it seems to use sel is true then you can move it into the if statement.
>
>
>> + if (sel)
>> + sclk = get_pll_clk(reg_map[sel]);
>> + else
>> + sclk = 2400;
>>
>
> please define this value.
>
>
>> + /*
>> +* CLK_DIV_DISP10
>> +* FIMD1_RATIO [3:0]
>> +*/
>> + ratio = readl(&clk->div_disp10) & 0xf;
>> +
>> + return sclk / (ratio + 1);
>> +}
>> +
>> void exynos4_set_lcd_clk(void)
>> {
>> struct exynos4_clock *clk =
>> @@ -1197,6 +1227,31 @@ void exynos5420_set_lcd_clk(void)
>> writel(cfg, &clk->div_disp10);
>> }
>>
>> +void exynos5800_set_lcd_clk(void)
>> +{
>> + struct exynos5420_clock *clk =
>> + (struct exynos5420_clock *)samsung_get_base_clock();
>> + unsigned int cfg;
>> +
>> + /*
>> +* Use RPLL for pixel clock
>> +* CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]
>> +* ==
>> +* 111: SCLK_RPLL
>> +*/
>> + cfg = readl(&clk->src_disp10) | (7 << 4);
>> + writel(cfg, &clk->src_disp10);
>> +
>> + /*
>> +* CLK_DIV_DISP10
>> +* FIMD1_RATIO [3:0]
>> +*/
>> + cfg = readl(&clk->div_disp10);
>> + cfg &= ~(0xf << 0);
>> + cfg |= (0 << 0);
>>
>
> it looks meaningless.
>
>
>> + writel(cfg, &clk->div_disp10);
>> +}
>> +
>> void exynos4_set_mipi_clk(void)
>> {
>> struct exynos4_clock *clk =
>> @@ -1669,8 +1724,10 @@ unsigned long get_lcd_clk(void)
>> if (cpu_is_exynos4())
>> return exynos4_get_lcd_clk();
>> else {
>> - if (proid_is_exynos5420() || proid_is_exynos5800())
>> + if (proid_is_exynos5420())
>> return exynos5420_get_lcd_clk();
>> + else if (proid_is_exynos5800())
>> + return exynos5800_get_lcd_clk();
>> else
>> return exynos5_get_lcd_clk();
>> }
>> @@ -1683,8 +1740,10 @@ void set_lcd_clk(void)
>> else {
>> if (proid_is_exynos5250())
>> exynos5_set_lcd_clk();
>> - else if (proid_is_exynos5420() || proid_is_exynos5800())
>> + else if (proid_is_exynos5420())
>> exynos5420_set_lcd_clk();
>> + else
>> + exynos5800_set_lcd_clk();
>> }
>> }
>
Re: [U-Boot] [PATCH 1/2 v2] Exynos5800: The Peach-Pi board does not have a Parade video bridge
Hi All, On Tue, Dec 2, 2014 at 2:00 AM, Simon Glass wrote: > Hi Sjoerd, > > On 1 December 2014 at 13:25, Sjoerd Simons > wrote: >> On Mon, 2014-12-01 at 13:09 -0700, Simon Glass wrote: >>> +Akshay >>> >>> Hi Sjoerd, >>> >>> On 1 December 2014 at 03:03, Sjoerd Simons >>> wrote: >>> > Hey Simon, >>> > >>> > On Sun, 2014-11-30 at 11:56 -0700, Simon Glass wrote: >>> >> On 27 November 2014 at 08:08, Sjoerd Simons >>> >> wrote: >>> >> > Unlike the Peach-Pit board, there is no parade edp to lvds bridge on >>> >> > the >>> >> > Pi. So drop it from device-tree >>> >> > >>> >> > Signed-off-by: Sjoerd Simons >>> >> > --- >>> >> > Changes since v1: Only modify the DTB >>> >> > >>> >> > arch/arm/dts/exynos5800-peach-pi.dts | 5 - >>> >> > 1 file changed, 5 deletions(-) >>> >> >>> >> Acked-by: Simon Glass >>> >> >>> >> Tested on snow, pit, pi (display does not yet work on Pi). >>> > >>> > Just to be clear, in your testing does the display not work on Pi? It >>> > seems to be ok here (with u-boot starting chainloaded from one of the >>> > KERN partitions) >>> >>> That's right, not in U-Boot. I think this is because some GPIOs need >>> to be enabled to turn on the backlight etc. Maybe you have an EC which >>> turns these on automatically? >>> >>> If current mainline is supposed to make the display work on Pi then I >>> need to do some debugging. Please let me know. >> >> It does work on my machine, so i was wondering if it's a setup >> difference. I'm using the chained u-boot method (iotw the standard >> chromeos u-boot in flash starts main-line u-boot from mmc/SD), which >> might well mean that the GPIOs you're referring to are still turned on >> by the first u-boot (which it has to do to show me the unverified boot >> warning screen)? > > Yes that's right. Maybe Akshay / Ajay have ideas, or otherwise I can > add this. I think it is two GPIOs, but it might be TPSCHROME also. Now, I have added support for peach_pi display in u-boot. Kindly check the patches. Ajay ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/5] Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels
The existing setting for rpll_sdiv generates 70.5Mhz RPLL
video clock to drive 1366x768 panel on peach_pit.
This clock rate is not sufficient to drive 1920x1080 panel on peach-pi.
So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock
which can drive peach-pi LCD.
This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD
divider at IP level will get set to 1(the required divider setting
will be calculated and set by exynos_fimd_set_clock()) and hence
peach-pit LCD still works fine.
Signed-off-by: Ajay Kumar
---
arch/arm/cpu/armv7/exynos/clock_init_exynos5.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
index 0aff3d0..0200fd1 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
+++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
@@ -179,10 +179,10 @@ struct mem_timings mem_timings[] = {
.spll_mdiv = 0xc8,
.spll_pdiv = 0x3,
.spll_sdiv = 0x2,
- /* RPLL @70.5Mhz */
+ /* RPLL @141Mhz */
.rpll_mdiv = 0x5E,
.rpll_pdiv = 0x2,
- .rpll_sdiv = 0x4,
+ .rpll_sdiv = 0x3,
.direct_cmd_msr = {
0x00020018, 0x0003, 0x00010046, 0x0d70,
--
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[U-Boot] [PATCH 5/5] peach_pi: dts: Add lcd poweron delay
Add some delay after powering up the peach_pi eDP panel, to make sure the panel is ready for link training. Signed-off-by: Ajay Kumar --- arch/arm/dts/exynos5800-peach-pi.dts |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts index 2f9d2db..109dab5 100644 --- a/arch/arm/dts/exynos5800-peach-pi.dts +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -144,6 +144,7 @@ samsung,vl-vfpd = <10>; samsung,vl-cmd-allow-len = <0xf>; + samsung,power-on-delay = <3>; samsung,winid = <3>; samsung,interface-mode = <1>; samsung,dp-enabled = <1>; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/5] exynos5420: Add LCD and LED powerup settings for peach-pi
Add code to support powerup sequence for peach-pi LCD.
Signed-off-by: Ajay Kumar
---
board/samsung/smdk5420/smdk5420.c | 32 +---
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/board/samsung/smdk5420/smdk5420.c
b/board/samsung/smdk5420/smdk5420.c
index a691222..915125e 100644
--- a/board/samsung/smdk5420/smdk5420.c
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -73,19 +73,24 @@ void exynos_lcd_power_on(void)
mdelay(5);
- /* TODO(ajaykumar...@samsung.com): Use device tree */
- gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");
- gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */
- mdelay(10);
- gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");
- gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */
- gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");
- gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
- gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
-
- if (has_edp_bridge())
+ if (has_edp_bridge()) {
+ /* TODO(ajaykumar...@samsung.com): Use device tree */
+ gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");
+ gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */
+ mdelay(10);
+ gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");
+ gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */
+ gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");
+ gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
+ gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
+
if (parade_init(gd->fdt_blob))
printf("%s: ps8625_init() failed\n", __func__);
+ } else {
+ gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");
+ gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
+ gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
+ }
}
void exynos_backlight_on(unsigned int onoff)
@@ -98,6 +103,11 @@ void exynos_backlight_on(unsigned int onoff)
#ifdef CONFIG_POWER_TPS65090
tps65090_fet_enable(1);
#endif
+
+ if (!has_edp_bridge()) {
+ gpio_request(EXYNOS5420_GPIO_X22, "bl_en");
+ gpio_direction_output(EXYNOS5420_GPIO_X22, 1);
+ }
}
#endif
--
1.7.9.5
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[U-Boot] [PATCH 2/5] arm: exynos: add display clocks for Exynos5800
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by
exynos video driver.
Signed-off-by: Ajay Kumar
---
arch/arm/cpu/armv7/exynos/clock.c | 63 +++-
arch/arm/include/asm/arch-exynos/clk.h |3 ++
2 files changed, 64 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 8fab135..1a34ad6 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -1066,6 +1066,36 @@ static unsigned long exynos5420_get_lcd_clk(void)
return pclk;
}
+static unsigned long exynos5800_get_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long sclk;
+ unsigned sel;
+ unsigned ratio;
+
+ sel = (readl(&clk->src_disp10) >> 4) & 7;
+
+ /*
+* Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into
+* PLLs. The first element is a placeholder to bypass the
+* default settig.
+*/
+ const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL,
+ IPLL, EPLL, RPLL};
+ if (sel)
+ sclk = get_pll_clk(reg_map[sel]);
+ else
+ sclk = 2400;
+ /*
+* CLK_DIV_DISP10
+* FIMD1_RATIO [3:0]
+*/
+ ratio = readl(&clk->div_disp10) & 0xf;
+
+ return sclk / (ratio + 1);
+}
+
void exynos4_set_lcd_clk(void)
{
struct exynos4_clock *clk =
@@ -1197,6 +1227,31 @@ void exynos5420_set_lcd_clk(void)
writel(cfg, &clk->div_disp10);
}
+void exynos5800_set_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned int cfg;
+
+ /*
+* Use RPLL for pixel clock
+* CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]
+* ==
+* 111: SCLK_RPLL
+*/
+ cfg = readl(&clk->src_disp10) | (7 << 4);
+ writel(cfg, &clk->src_disp10);
+
+ /*
+* CLK_DIV_DISP10
+* FIMD1_RATIO [3:0]
+*/
+ cfg = readl(&clk->div_disp10);
+ cfg &= ~(0xf << 0);
+ cfg |= (0 << 0);
+ writel(cfg, &clk->div_disp10);
+}
+
void exynos4_set_mipi_clk(void)
{
struct exynos4_clock *clk =
@@ -1669,8 +1724,10 @@ unsigned long get_lcd_clk(void)
if (cpu_is_exynos4())
return exynos4_get_lcd_clk();
else {
- if (proid_is_exynos5420() || proid_is_exynos5800())
+ if (proid_is_exynos5420())
return exynos5420_get_lcd_clk();
+ else if (proid_is_exynos5800())
+ return exynos5800_get_lcd_clk();
else
return exynos5_get_lcd_clk();
}
@@ -1683,8 +1740,10 @@ void set_lcd_clk(void)
else {
if (proid_is_exynos5250())
exynos5_set_lcd_clk();
- else if (proid_is_exynos5420() || proid_is_exynos5800())
+ else if (proid_is_exynos5420())
exynos5420_set_lcd_clk();
+ else
+ exynos5800_set_lcd_clk();
}
}
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index db24dc0..bf3d348 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -16,6 +16,9 @@
#define BPLL 5
#define RPLL 6
#define SPLL 7
+#define CPLL 8
+#define DPLL 9
+#define IPLL 10
#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8))
#define MASK_RATIO(x) (0xf << (x << 4))
--
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[U-Boot] [PATCH 1/5] Exynos5800: The Peach-Pi board does not have a Parade video bridge
From: Sjoerd Simons
Unlike the Peach-Pit board, there is no parade edp to lvds bridge on the
Pi. So drop it from device-tree.
Signed-off-by: Sjoerd Simons
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/dts/exynos5800-peach-pi.dts |5 -
1 file changed, 5 deletions(-)
diff --git a/arch/arm/dts/exynos5800-peach-pi.dts
b/arch/arm/dts/exynos5800-peach-pi.dts
index 8aedf8e..2f9d2db 100644
--- a/arch/arm/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/dts/exynos5800-peach-pi.dts
@@ -63,11 +63,6 @@
reg = <0x20>;
compatible = "maxim,max98090-codec";
};
-
- edp-lvds-bridge@48 {
- compatible = "parade,ps8625";
- reg = <0x48>;
- };
};
sound@383 {
--
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[U-Boot] [PATCH 0/5] peach_pi: Add support for FIMD and DP
Add support for the eDP panel supported on peach_pi. Sjoerd Simons(1): [PATCH 1/5] Exynos5800: The Peach-Pi board does not have a Parade video bridge Ajay Kumar (4): [PATCH 2/5] arm: exynos: add display clocks for Exynos5800 [PATCH 3/5] Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels [PATCH 4/5] exynos5420: Add LCD and LED powerup settings for peach-pi [PATCH 5/5] peach_pi: dts: Add lcd poweron delay arch/arm/cpu/armv7/exynos/clock.c | 63 +++- arch/arm/cpu/armv7/exynos/clock_init_exynos5.c |4 +- arch/arm/dts/exynos5800-peach-pi.dts |6 +-- arch/arm/include/asm/arch-exynos/clk.h |3 ++ board/samsung/smdk5420/smdk5420.c | 32 +++- 5 files changed, 88 insertions(+), 20 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] exynos5420: fix compilation without parade video
On Mon, Nov 24, 2014 at 8:45 PM, Sjoerd Simons
wrote:
> Not all exynos 5420 based devices with an LCD also have a parade LVDS
> bridge. So make sure compilation doesn't break if CONFIG_LCD is enabled
> and CONFIG_VIDEO_PARADE is not.
>
> Signed-off-by: Sjoerd Simons
> ---
> board/samsung/smdk5420/smdk5420.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/board/samsung/smdk5420/smdk5420.c
> b/board/samsung/smdk5420/smdk5420.c
> index a691222..f8be401 100644
> --- a/board/samsung/smdk5420/smdk5420.c
> +++ b/board/samsung/smdk5420/smdk5420.c
> @@ -43,6 +43,7 @@ int exynos_init(void)
> }
>
> #ifdef CONFIG_LCD
> +#ifdef CONFIG_VIDEO_PARADE
I think this is unnecessary.
> static int has_edp_bridge(void)
> {
> int node;
> @@ -56,6 +57,7 @@ static int has_edp_bridge(void)
> /* Default is with bridge ic */
> return 1;
> }
> +#endif
>
> void exynos_lcd_power_on(void)
> {
> @@ -83,9 +85,11 @@ void exynos_lcd_power_on(void)
> gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
> gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
>
> +#ifdef CONFIG_VIDEO_PARADE
How about moving this to some header and modify it like below:
#ifdef CONFIG_VIDEO_PARADE
int parade_init(const void *blob);
#else
static inline int parade_init(const void *blob)
{
return 0;
}
#endif
> if (has_edp_bridge())
> if (parade_init(gd->fdt_blob))
> printf("%s: ps8625_init() failed\n", __func__);
> +#endif
> }
>
> void exynos_backlight_on(unsigned int onoff)
> --
> 2.1.3
>
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Re: [U-Boot] [PATCH V4 0/9] peach_pit: Add support for FIMD, DP and parade chip
Hi Minkyu, On Fri, Sep 5, 2014 at 3:33 PM, Minkyu Kang wrote: > On 04/08/14 20:39, Ajay kumar wrote: >> +Minkyu >> >> On Mon, Aug 4, 2014 at 4:49 PM, Simon Glass wrote: >>> Hi, >>> >>> On 30 July 2014 03:11, Ajay Kumar wrote: >>>> Patchset V1: >>>> https://www.mail-archive.com/u-boot@lists.denx.de/msg140596.html >>>> >>>> Patchset V2: >>>> https://www.mail-archive.com/u-boot@lists.denx.de/msg141203.html >>>> >>>> Patchset V3: >>>> http://lists.denx.de/pipermail/u-boot/2014-July/183096.html >>>> >>>> Changes from V1: >>>> [PATCH V2 3/10] : Don't mix cpu_is and proid_is as per Minkyu's suggestion. >>>> Also, incorporate Simon's suggestion of not using else. >>>> [PATCH V2 4/10] : For FIMD SYSMMU DT, use same compatible string as kernel. >>>> [TEST_ONLY V2 6/10]: Make this patch TEST_ONLY >>>> >>>> Changes from V2: >>>> [PATCH V3 5/9] : Use SPDX tags to define the license for the file: parade.c >>>> Removed TEST_ONLY patches. >>>> >>>> Changes from V3: >>>> [PATCH V4 1/9] : Fix comment style. >>>> [PATCH V4 3/9] : Use 'else if' clause instead of 'if'. >>> >>> Is this series ready to be merged? I have several series dependent on it. >> I have addressed all the comments from Minkyu. >> Hopefully, it should get in this time! >> >> Ajay >> > > Could you please rebase & resend this patch? I have sent "[PATCH V5 0/9] peach_pit: Add support for FIMD, DP and parade chip" after rebasing and testing. Thanks, Ajay ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V5 8/9] ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chip
This patch adds DT properties for fimd and the parade bridge chip
present on peach_pit. The panel supports 1366x768 resolution.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/dts/exynos5420-peach-pit.dts | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts
b/arch/arm/dts/exynos5420-peach-pit.dts
index 8d148af..3ed70a8 100644
--- a/arch/arm/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -63,6 +63,11 @@
reg = <0x20>;
compatible = "maxim,max98090-codec";
};
+
+ edp-lvds-bridge@48 {
+ compatible = "parade,ps8625";
+ reg = <0x48>;
+ };
};
sound@383 {
@@ -124,4 +129,29 @@
xhci@1240 {
samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
};
+
+ fimd@1440 {
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <1366>;
+ samsung,vl-row = <768>;
+ samsung,vl-width = <1366>;
+ samsung,vl-height = <768>;
+
+ samsung,vl-clkp;
+ samsung,vl-dp;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <32>;
+ samsung,vl-hbpd = <40>;
+ samsung,vl-hfpd = <40>;
+ samsung,vl-vspw = <6>;
+ samsung,vl-vbpd = <10>;
+ samsung,vl-vfpd = <12>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,winid = <3>;
+ samsung,interface-mode = <1>;
+ samsung,dp-enabled = <1>;
+ samsung,dual-lcd-enabled = <0>;
+ };
};
--
1.7.9.5
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[U-Boot] [PATCH V5 9/9] CONFIGS: peach-pit: Enable display for peach_pit board
Enable drivers for FIMD, DP and parade bridge chip. Signed-off-by: Ajay Kumar --- include/configs/peach-pit.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 76b8d7a..88c093f 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -22,4 +22,14 @@ #define CONFIG_SYS_PROMPT "Peach # " #define CONFIG_IDENT_STRING" for Peach" +#define CONFIG_VIDEO_PARADE + +/* Display */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_EXYNOS_FB +#define CONFIG_EXYNOS_DP +#define LCD_BPPLCD_COLOR16 +#endif + #endif /* __CONFIG_PEACH_PIT_H */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V5 6/9] ARM: exynos: Add missing declaration for gpio_direction_input
This patch adds missing declaration for gpio_direction_input
function, thereby helps in resolving compilation warnings.
Signed-off-by: Ajay Kumar
---
arch/arm/include/asm/arch-exynos/gpio.h |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h
index be5113f..8fb5c23 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1504,6 +1504,7 @@ static const struct gpio_name_num_table
exynos5420_gpio_table[] = {
void gpio_cfg_pin(int gpio, int cfg);
void gpio_set_pull(int gpio, int mode);
void gpio_set_drv(int gpio, int mode);
+int gpio_direction_input(unsigned gpio);
int gpio_direction_output(unsigned gpio, int value);
int gpio_set_value(unsigned gpio, int value);
int gpio_get_value(unsigned gpio);
--
1.7.9.5
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[U-Boot] [PATCH V5 7/9] exynos5420: add callbacks needed for exynos_fb driver
Add initialization code for peach_pit panel, parade bridge chip,
and backlight.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/include/asm/arch-exynos/system.h |3 +
board/samsung/smdk5420/smdk5420.c | 129 +++--
2 files changed, 50 insertions(+), 82 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/system.h
b/arch/arm/include/asm/arch-exynos/system.h
index 4968d3d..320763f 100644
--- a/arch/arm/include/asm/arch-exynos/system.h
+++ b/arch/arm/include/asm/arch-exynos/system.h
@@ -41,4 +41,7 @@ void set_usbhost_mode(unsigned int mode);
void set_system_display_ctrl(void);
int exynos_lcd_early_init(const void *blob);
+/* Initialize the Parade dP<->LVDS bridge if present */
+int parade_init(const void *blob);
+
#endif /* _EXYNOS4_SYSTEM_H */
diff --git a/board/samsung/smdk5420/smdk5420.c
b/board/samsung/smdk5420/smdk5420.c
index 183c522..270ee83 100644
--- a/board/samsung/smdk5420/smdk5420.c
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -10,11 +10,14 @@
#include
#include
#include
+#include
#include
#include
#include
#include
+#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -40,95 +43,57 @@ int exynos_init(void)
}
#ifdef CONFIG_LCD
-void cfg_lcd_gpio(void)
+static int has_edp_bridge(void)
{
- /* For Backlight */
- gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_OUTPUT);
- gpio_set_value(EXYNOS5420_GPIO_B20, 1);
+ int node;
+
+ node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_PARADE_PS8625);
- /* LCD power on */
- gpio_cfg_pin(EXYNOS5420_GPIO_X15, S5P_GPIO_OUTPUT);
- gpio_set_value(EXYNOS5420_GPIO_X15, 1);
+ /* No node for bridge in device tree. */
+ if (node <= 0)
+ return 0;
- /* Set Hotplug detect for DP */
- gpio_cfg_pin(EXYNOS5420_GPIO_X07, S5P_GPIO_FUNC(0x3));
+ /* Default is with bridge ic */
+ return 1;
}
-vidinfo_t panel_info = {
- .vl_freq= 60,
- .vl_col = 2560,
- .vl_row = 1600,
- .vl_width = 2560,
- .vl_height = 1600,
- .vl_clkp= CONFIG_SYS_LOW,
- .vl_hsp = CONFIG_SYS_LOW,
- .vl_vsp = CONFIG_SYS_LOW,
- .vl_dp = CONFIG_SYS_LOW,
- .vl_bpix= 4,/* LCD_BPP = 2^4, for output conosle on LCD */
-
- /* wDP panel timing infomation */
- .vl_hspw= 32,
- .vl_hbpd= 80,
- .vl_hfpd= 48,
-
- .vl_vspw= 6,
- .vl_vbpd= 37,
- .vl_vfpd= 3,
- .vl_cmd_allow_len = 0xf,
-
- .win_id = 3,
- .cfg_gpio = cfg_lcd_gpio,
- .backlight_on = NULL,
- .lcd_power_on = NULL,
- .reset_lcd = NULL,
- .dual_lcd_enabled = 0,
-
- .init_delay = 0,
- .power_on_delay = 0,
- .reset_delay= 0,
- .interface_mode = FIMD_RGB_INTERFACE,
- .dp_enabled = 1,
-};
-
-static struct edp_device_info edp_info = {
- .disp_info = {
- .h_res = 2560,
- .h_sync_width = 32,
- .h_back_porch = 80,
- .h_front_porch = 48,
- .v_res = 1600,
- .v_sync_width = 6,
- .v_back_porch = 37,
- .v_front_porch = 3,
- .v_sync_rate = 60,
- },
- .lt_info = {
- .lt_status = DP_LT_NONE,
- },
- .video_info = {
- .master_mode = 0,
- .bist_mode = DP_DISABLE,
- .bist_pattern = NO_PATTERN,
- .h_sync_polarity = 0,
- .v_sync_polarity = 0,
- .interlaced = 0,
- .color_space = COLOR_RGB,
- .dynamic_range = VESA,
- .ycbcr_coeff = COLOR_YCBCR601,
- .color_depth = COLOR_8,
- },
-};
-
-static struct exynos_dp_platform_data dp_platform_data = {
- .phy_enable = set_dp_phy_ctrl,
- .edp_dev_info = &edp_info,
-};
-
-void init_panel_info(vidinfo_t *vid)
+void exynos_lcd_power_on(void)
{
- vid->rgb_mode = MODE_RGB_P;
+ int ret;
+
+#ifdef CONFIG_POWER_TPS65090
+ ret = tps65090_init();
+ if (ret < 0) {
+ printf("%s: tps65090_init() failed\n", __func__);
+ return;
+ }
+
+ tps65090_fet_enable(6);
+#endif
+
+ mdelay(5);
+
+ /* TODO(ajaykumar...@samsung.com): Use device tree */
+ gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */
+ mdelay(10);
+ gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */
+ gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
+ gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
- exynos_set_dp_platform_data(&dp_platform_data);
+ if (has_edp_bridge())
+ if (parade_init(gd->fdt_blob))
+
[U-Boot] [PATCH V5 3/9] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/cpu/armv7/exynos/clock.c | 83 +++--
arch/arm/cpu/armv7/exynos/exynos5_setup.h |2 +-
arch/arm/include/asm/arch-exynos/clk.h|1 +
3 files changed, 80 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 400d134..7558eff 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r,
unsigned int k)
* VPLL_CON: MIDV [24:16]
* BPLL_CON: MIDV [25:16]: Exynos5
*/
- if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
+ if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
+ pllreg == SPLL)
mask = 0x3ff;
else
mask = 0x1ff;
@@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg)
r = readl(&clk->rpll_con0);
k = readl(&clk->rpll_con1);
break;
+ case SPLL:
+ r = readl(&clk->spll_con0);
+ break;
default:
printf("Unsupported PLL (%d)\n", pllreg);
return 0;
@@ -1027,6 +1031,40 @@ static unsigned long exynos5_get_lcd_clk(void)
return pclk;
}
+static unsigned long exynos5420_get_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long pclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+* CLK_SRC_DISP10
+* FIMD1_SEL [4]
+* 0: SCLK_RPLL
+* 1: SCLK_SPLL
+*/
+ sel = readl(&clk->src_disp10);
+ sel &= (1 << 4);
+
+ if (sel)
+ sclk = get_pll_clk(SPLL);
+ else
+ sclk = get_pll_clk(RPLL);
+
+ /*
+* CLK_DIV_DISP10
+* FIMD1_RATIO [3:0]
+*/
+ ratio = readl(&clk->div_disp10);
+ ratio = ratio & 0xf;
+
+ pclk = sclk / (ratio + 1);
+
+ return pclk;
+}
+
void exynos4_set_lcd_clk(void)
{
struct exynos4_clock *clk =
@@ -1131,6 +1169,33 @@ void exynos5_set_lcd_clk(void)
clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
}
+void exynos5420_set_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned int cfg;
+
+ /*
+* CLK_SRC_DISP10
+* FIMD1_SEL [4]
+* 0: SCLK_RPLL
+* 1: SCLK_SPLL
+*/
+ cfg = readl(&clk->src_disp10);
+ cfg &= ~(0x1 << 4);
+ cfg |= (0 << 4);
+ writel(cfg, &clk->src_disp10);
+
+ /*
+* CLK_DIV_DISP10
+* FIMD1_RATIO [3:0]
+*/
+ cfg = readl(&clk->div_disp10);
+ cfg &= ~(0xf << 0);
+ cfg |= (0 << 0);
+ writel(cfg, &clk->div_disp10);
+}
+
void exynos4_set_mipi_clk(void)
{
struct exynos4_clock *clk =
@@ -1602,16 +1667,24 @@ unsigned long get_lcd_clk(void)
{
if (cpu_is_exynos4())
return exynos4_get_lcd_clk();
- else
- return exynos5_get_lcd_clk();
+ else {
+ if (proid_is_exynos5420())
+ return exynos5420_get_lcd_clk();
+ else
+ return exynos5_get_lcd_clk();
+ }
}
void set_lcd_clk(void)
{
if (cpu_is_exynos4())
exynos4_set_lcd_clk();
- else
- exynos5_set_lcd_clk();
+ else {
+ if (proid_is_exynos5250())
+ exynos5_set_lcd_clk();
+ else if (proid_is_exynos5420())
+ exynos5420_set_lcd_clk();
+ }
}
void set_mipi_clk(void)
diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
index 3242093..2eea48a 100644
--- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
+++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
@@ -783,7 +783,7 @@
#define CLK_SRC_TOP2_VAL 0x11101000
#define CLK_SRC_TOP3_VAL 0x
#define CLK_SRC_TOP4_VAL 0x0111
-#define CLK_SRC_TOP5_VAL 0x1100
+#define CLK_SRC_TOP5_VAL 0x1101
#define CLK_SRC_TOP6_VAL 0x0111
#define CLK_SRC_TOP7_VAL 0x00022200
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index ffbc07e..db24dc0 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -15,6 +15,7 @@
#define VPLL 4
#define BPLL 5
#define RPLL 6
+#define SPL
[U-Boot] [PATCH V5 5/9] video: Add driver for Parade PS8625 dP to LVDS bridge
From: Vadim Bendebury
The initialization table comes from the "Illustration of I2C command
for initialing PS8625" document supplied by Parade.
Signed-off-by: Vadim Bendebury
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
drivers/video/Makefile |1 +
drivers/video/parade.c | 220
include/fdtdec.h |1 +
lib/fdtdec.c |1 +
4 files changed, 223 insertions(+)
create mode 100644 drivers/video/parade.c
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 93a91c3..248aa35 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -42,3 +42,4 @@ obj-$(CONFIG_VIDEO_TEGRA) += tegra.o
obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
obj-$(CONFIG_FORMIKE) += formike.o
obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
+obj-$(CONFIG_VIDEO_PARADE) += parade.o
diff --git a/drivers/video/parade.c b/drivers/video/parade.c
new file mode 100644
index 000..0f543f6
--- /dev/null
+++ b/drivers/video/parade.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * This file is a driver for Parade dP<->LVDS bridges. The original submission
+ * is for the ps8625 chip.
+ */
+#include
+#include
+#include
+#include
+
+/*
+ * Initialization of the chip is a process of writing certaing values into
+ * certain registers over i2c bus. The chip in fact responds to a range of
+ * addresses on the i2c bus, so for each written value three parameters are
+ * required: i2c address, register address and the actual value.
+ *
+ * The base address is derived from the device tree, only address offset is
+ * stored in the table below.
+ */
+/**
+ * struct reg_data() - data for a parade register write
+ *
+ * @addr_offoffset from the i2c base address for parade
+ * @reg_addrregister address to write
+ * @value value to be written
+ */
+struct reg_data {
+ uint8_t addr_off;
+ uint8_t reg;
+ uint8_t value;
+} _packed;
+
+#define END_OF_TABLE 0xff /* Ficticious offset */
+
+static const struct reg_data parade_values[] = {
+ {0x02, 0xa1, 0x01}, /* HPD low */
+/*
+ * SW setting
+ * [1:0] SW output 1.2V voltage is lower to 96%
+ */
+ {0x04, 0x14, 0x01},
+/*
+ * RCO SS setting
+ * [5:4] = b01 0.5%, b10 1%, b11 1.5%
+ */
+ {0x04, 0xe3, 0x20},
+ {0x04, 0xe2, 0x80}, /* [7] RCO SS enable */
+/*
+ * RPHY Setting
+ * [3:2] CDR tune wait cycle before
+ * measure for fine tune b00: 1us,
+ * 01: 0.5us, 10:2us, 11:4us.
+ */
+ {0x04, 0x8a, 0x0c},
+ {0x04, 0x89, 0x08}, /* [3] RFD always on */
+/*
+ * CTN lock in/out:
+ * 2ppm/8ppm. Lock out 2
+ * times.
+ */
+ {0x04, 0x71, 0x2d},
+/*
+ * 2.7G CDR settings
+ * NOF=40LSB for HBR CDR setting
+ */
+ {0x04, 0x7d, 0x07},
+ {0x04, 0x7b, 0x00}, /* [1:0] Fmin=+4bands */
+ {0x04, 0x7a, 0xfd}, /* [7:5] DCO_FTRNG=+-40% */
+/*
+ * 1.62G CDR settings
+ * [5:2]NOF=64LSB [1:0]DCO scale is 2/5
+ */
+ {0x04, 0xc0, 0x12},
+ {0x04, 0xc1, 0x92}, /* Gitune=-37% */
+ {0x04, 0xc2, 0x1c}, /* Fbstep=100% */
+ {0x04, 0x32, 0x80}, /* [7] LOS signal disable */
+/*
+ * RPIO Setting
+ * [7:4] LVDS driver bias current :
+ * 75% (250mV swing)
+ */
+ {0x04, 0x00, 0xb0},
+/*
+ * [7:6] Right-bar GPIO output strength is 8mA
+ */
+ {0x04, 0x15, 0x40},
+/* EQ Training State Machine Setting */
+ {0x04, 0x54, 0x10}, /* RCO calibration start */
+/* [4:0] MAX_LANE_COUNT set to one lane */
+ {0x01, 0x02, 0x81},
+/* [4:0] LANE_COUNT_SET set to one lane */
+ {0x01, 0x21, 0x81},
+ {0x00, 0x52, 0x20},
+ {0x00, 0xf1, 0x03}, /* HPD CP toggle enable */
+ {0x00, 0x62, 0x41},
+/* Counter number, add 1ms counter delay */
+ {0x00, 0xf6, 0x01},
+/*
+ * [6]PWM function control by
+ * DPCD0040f[7], default is PWM
+ * block always works.
+ */
+ {0x00, 0x77, 0x06},
+/*
+ * 04h Adjust VTotal tolerance to
+ * fix the 30Hz no display issue
+ */
+ {0x00, 0x4c, 0x04},
+/* DPCD00400='h00, Parade OUI = 'h001cf8 */
+ {0x01, 0xc0, 0x00},
+ {0x01, 0xc1, 0x1c}, /* DPCD00401='h1c */
+ {0x01, 0xc2, 0xf8}, /* DPCD00402='hf8 */
+/*
+ * DPCD403~408 = ASCII code
+ * D2SLV5='h4432534c5635
+ */
+ {0x01, 0xc3, 0x44},
+ {0x01, 0xc4, 0x32}, /* DPCD404 */
+ {0x01, 0xc5, 0x53}, /* DPCD405 */
+ {0x01, 0xc6, 0x4c}, /* DPCD406 */
+ {0x01, 0xc7, 0x56}, /* DPCD407 *
[U-Boot] [PATCH V5 4/9] video: exynos_fimd: Add framework to disable FIMD sysmmu
On Exynos5420 and newer versions, the FIMD sysmmus are in
"on state" by default.
We have to disable them in order to make FIMD DMA work.
This patch adds the required framework to exynos_fimd driver,
and disables FIMD sysmmu on Exynos5420.
Signed-off-by: Ajay Kumar
---
arch/arm/dts/exynos54xx.dtsi | 10 ++
doc/device-tree-bindings/video/exynos-fb.txt |6
drivers/video/exynos_fimd.c | 43 ++
include/fdtdec.h |1 +
lib/fdtdec.c |1 +
5 files changed, 61 insertions(+)
diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi
index b9f8e0b..c21d798 100644
--- a/arch/arm/dts/exynos54xx.dtsi
+++ b/arch/arm/dts/exynos54xx.dtsi
@@ -113,6 +113,16 @@
status = "disabled";
};
+ fimdm0_sysmmu@0x1464 {
+ compatible = "samsung,sysmmu-v3.3";
+ reg = <0x1464 0x100>;
+ };
+
+ fimdm1_sysmmu@0x1468 {
+ compatible = "samsung,sysmmu-v3.3";
+ reg = <0x1468 0x100>;
+ };
+
fimd@1440 {
/* sysmmu is not used in U-Boot */
samsung,disable-sysmmu;
diff --git a/doc/device-tree-bindings/video/exynos-fb.txt
b/doc/device-tree-bindings/video/exynos-fb.txt
index bb7441c..dc4e44f 100644
--- a/doc/device-tree-bindings/video/exynos-fb.txt
+++ b/doc/device-tree-bindings/video/exynos-fb.txt
@@ -55,6 +55,12 @@ Board(panel specific):
samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)
samsung,sclk-div: parent_clock/source_clock ratio
samsung,dual-lcd-enabled: 1 if you support two LCD, else 0
+ samsung,disable-sysmmu: Define this if you want to disable FIMD sysmmu.
+ (needed for Exynos5420 and newer versions)
+ Add the required FIMD sysmmu nodes to be
+ disabled with compatible string
+ "samsung,sysmmu-v3.3", with a "reg" property
+ holding the register address of FIMD sysmmu.
Example:
SOC specific part:
diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
index cebbba7..f67fa81 100644
--- a/drivers/video/exynos_fimd.c
+++ b/drivers/video/exynos_fimd.c
@@ -251,6 +251,45 @@ void exynos_fimd_window_off(unsigned int win_id)
writel(cfg, &fimd_ctrl->winshmap);
}
+#ifdef CONFIG_OF_CONTROL
+/*
+* The reset value for FIMD SYSMMU register MMU_CTRL is 3
+* on Exynos5420 and newer versions.
+* This means FIMD SYSMMU is on by default on Exynos5420
+* and newer versions.
+* Since in u-boot we don't use SYSMMU, we should disable
+* those FIMD SYSMMU.
+* Note that there are 2 SYSMMU for FIMD: m0 and m1.
+* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3.
+* We disable both of them here.
+*/
+void exynos_fimd_disable_sysmmu(void)
+{
+ u32 *sysmmufimd;
+ unsigned int node;
+ int node_list[2];
+ int count;
+ int i;
+
+ count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd",
+ COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2);
+ for (i = 0; i < count; i++) {
+ node = node_list[i];
+ if (node <= 0) {
+ debug("Can't get device node for fimd sysmmu\n");
+ return;
+ }
+
+ sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
+ if (!sysmmufimd) {
+ debug("Can't get base address for sysmmu fimdm0");
+ return;
+ }
+
+ writel(0x0, sysmmufimd);
+ }
+}
+#endif
void exynos_fimd_lcd_init(vidinfo_t *vid)
{
@@ -268,6 +307,10 @@ void exynos_fimd_lcd_init(vidinfo_t *vid)
node, "reg");
if (fimd_ctrl == NULL)
debug("Can't get the FIMD base address\n");
+
+ if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
+ exynos_fimd_disable_sysmmu();
+
#else
fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd();
#endif
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 856e6cf..d883bd2 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -94,6 +94,7 @@ enum fdt_compat_id {
COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */
COMPAT_TI_TPS65090, /* Texas Instrument TPS65090 */
COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */
+ COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */
COMPAT_COUNT,
};
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index eb5aa20..d95135d 10
[U-Boot] [PATCH V5 0/9] peach_pit: Add support for FIMD, DP and parade chip
Patchset V1: https://www.mail-archive.com/u-boot@lists.denx.de/msg140596.html Patchset V2: https://www.mail-archive.com/u-boot@lists.denx.de/msg141203.html Patchset V3: http://lists.denx.de/pipermail/u-boot/2014-July/183096.html Patchset V4: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/191730 Changes from V1: [PATCH V2 3/10] : Don't mix cpu_is and proid_is as per Minkyu's suggestion. Also, incorporate Simon's suggestion of not using else. [PATCH V2 4/10] : For FIMD SYSMMU DT, use same compatible string as kernel. [TEST_ONLY V2 6/10]: Make this patch TEST_ONLY Changes from V2: [PATCH V3 5/9] : Use SPDX tags to define the license for the file: parade.c Removed TEST_ONLY patches. Changes from V3: [PATCH V4 1/9] : Fix comment style. [PATCH V4 3/9] : Use 'else if' clause instead of 'if'. Changes from V4: Rebase all patches on top of the tree. To test this, we need 6 patches for cros_ec from Simon: [PATCH 1/6] cros_ec: Fix two bugs in the SPI implementation [PATCH 2/6] exynos: spi: Fix calculation of SPI transaction start time [PATCH 3/6] spi: Support half-duplex mode in FDT decode [PATCH 4/6] exynos5: Enable data cashe [PATCH 5/6] cros_ec: power: Add a tunnelled version of the tps65090 driver [PATCH 6/6] cros_ec: exynos: Use the correct tps65090 driver in each case Ajay Kumar (8): [PATCH V5 1/9] exynos_fb: Remove usage of static defines [PATCH V5 2/9] arm: exynos: Add RPLL for Exynos5420 [PATCH V5 3/9] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 [PATCH V5 4/9] video: exynos_fimd: Add framework to disable FIMD sysmmu [PATCH V5 6/9] ARM: exynos: Add missing declaration for gpio_direction_input [PATCH V5 7/9] exynos5420: add callbacks needed for exynos_fb driver [PATCH V5 8/9] ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chip [PATCH V5 9/9] CONFIGS: peach-pit: Enable display for peach_pit board Vadim Bendebury (1): [PATCH V5 5/9] video: Add driver for Parade PS8625 dP to LVDS bridge arch/arm/cpu/armv7/exynos/clock.c | 83 - arch/arm/cpu/armv7/exynos/clock_init.h |3 + arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 ++ arch/arm/cpu/armv7/exynos/exynos5_setup.h |2 +- arch/arm/dts/exynos5420-peach-pit.dts | 30 arch/arm/dts/exynos54xx.dtsi | 10 ++ arch/arm/include/asm/arch-exynos/clk.h |1 + arch/arm/include/asm/arch-exynos/gpio.h|1 + arch/arm/include/asm/arch-exynos/system.h |4 + board/samsung/common/board.c | 16 ++ board/samsung/smdk5420/smdk5420.c | 129 +- doc/device-tree-bindings/video/exynos-fb.txt |6 + drivers/video/Makefile |1 + drivers/video/exynos_fb.c | 18 +- drivers/video/exynos_fimd.c| 43 + drivers/video/parade.c | 220 include/configs/exynos5250-dt.h|2 - include/configs/peach-pit.h| 10 ++ include/configs/s5pc210_universal.h|3 - include/configs/trats.h|3 - include/configs/trats2.h |3 - include/fdtdec.h |2 + lib/fdtdec.c |2 + 23 files changed, 494 insertions(+), 111 deletions(-) create mode 100644 drivers/video/parade.c -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V5 2/9] arm: exynos: Add RPLL for Exynos5420
RPLL is needed to drive the LCD panel on Exynos5420 based boards.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/cpu/armv7/exynos/clock_init.h |3 +++
arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 +
2 files changed, 16 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h
b/arch/arm/cpu/armv7/exynos/clock_init.h
index a875d0b..fce502f 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init.h
+++ b/arch/arm/cpu/armv7/exynos/clock_init.h
@@ -75,6 +75,9 @@ struct mem_timings {
unsigned spll_mdiv;
unsigned spll_pdiv;
unsigned spll_sdiv;
+ unsigned rpll_mdiv;
+ unsigned rpll_pdiv;
+ unsigned rpll_sdiv;
unsigned pclk_cdrex_ratio;
unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
index 1d6977f..b6a9bc1 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
+++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
@@ -179,6 +179,10 @@ struct mem_timings mem_timings[] = {
.spll_mdiv = 0xc8,
.spll_pdiv = 0x3,
.spll_sdiv = 0x2,
+ /* RPLL @70.5Mhz */
+ .rpll_mdiv = 0x5E,
+ .rpll_pdiv = 0x2,
+ .rpll_sdiv = 0x4,
.direct_cmd_msr = {
0x00020018, 0x0003, 0x00010046, 0x0d70,
@@ -800,6 +804,7 @@ static void exynos5420_system_clock_init(void)
writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
+ writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);
setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
@@ -898,6 +903,14 @@ static void exynos5420_system_clock_init(void)
while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
;
+ /* Set RPLL */
+ writel(RPLL_CON2_VAL, &clk->rpll_con2);
+ writel(RPLL_CON1_VAL, &clk->rpll_con1);
+ val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv);
+ writel(val, &clk->rpll_con0);
+ while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0)
+ ;
+
writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
--
1.7.9.5
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[U-Boot] [PATCH V5 1/9] exynos_fb: Remove usage of static defines
Previously, we used to statically assign values for vl_col, vl_row and
vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.
Introducing the function exynos_lcd_early_init() would take care of this
assignment on the fly by parsing FIMD DT properties, thereby allowing us
to remove LCD_XRES and LCD_YRES from the main config file.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/include/asm/arch-exynos/system.h |1 +
board/samsung/common/board.c | 15 ++
drivers/video/exynos_fb.c | 18 +--
include/configs/exynos5250-dt.h |2 -
include/configs/s5pc210_universal.h |3 -
include/configs/trats.h |3 -
include/configs/trats2.h |3 -
9 files changed, 243 insertions(+), 23 deletions(-)
create mode 100644 include/config.mk
create mode 100644 include/spl-autoconf.mk
diff --git a/arch/arm/include/asm/arch-exynos/system.h
b/arch/arm/include/asm/arch-exynos/system.h
index 7e2057c..4968d3d 100644
--- a/arch/arm/include/asm/arch-exynos/system.h
+++ b/arch/arm/include/asm/arch-exynos/system.h
@@ -39,5 +39,6 @@ struct exynos5_sysreg {
void set_usbhost_mode(unsigned int mode);
void set_system_display_ctrl(void);
+int exynos_lcd_early_init(const void *blob);
#endif /* _EXYNOS4_SYSTEM_H */
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 3d1cf43..4fe78c7 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -149,6 +150,21 @@ int board_early_init_f(void)
#ifdef CONFIG_SYS_I2C_INIT_BOARD
board_i2c_init(gd->fdt_blob);
#endif
+
+#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_EXYNOS_FB)
+/*
+ * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
+ * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix, to reserve
+ * FB memory at a very early stage. So, we need to fill panel_info.vl_col,
+ * panel_info.vl_row and panel_info.vl_bpix before lcd_setmem() is called.
+ */
+ err = exynos_lcd_early_init(gd->fdt_blob);
+ if (err) {
+ debug("LCD early init failed\n");
+ return err;
+ }
+#endif
+
return exynos_early_init_f();
}
#endif
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
index e1e0d80..180a3b4 100644
--- a/drivers/video/exynos_fb.c
+++ b/drivers/video/exynos_fb.c
@@ -27,17 +27,13 @@ DECLARE_GLOBAL_DATA_PTR;
static unsigned int panel_width, panel_height;
-/*
- * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
- * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix to reserve
- * FB memory at a very early stage, i.e even before exynos_fimd_parse_dt()
- * is called. So, we are forced to statically assign it.
- */
#ifdef CONFIG_OF_CONTROL
vidinfo_t panel_info = {
- .vl_col = LCD_XRES,
- .vl_row = LCD_YRES,
- .vl_bpix = LCD_COLOR16,
+ /*
+* Insert a value here so that we don't end up in the BSS
+* Reference: drivers/video/tegra.c
+*/
+ .vl_col = -1,
};
#endif
@@ -141,7 +137,7 @@ static void lcd_panel_on(vidinfo_t *vid)
}
#ifdef CONFIG_OF_CONTROL
-int exynos_fimd_parse_dt(const void *blob)
+int exynos_lcd_early_init(const void *blob)
{
unsigned int node;
node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD);
@@ -286,8 +282,6 @@ void lcd_ctrl_init(void *lcdbase)
set_lcd_clk();
#ifdef CONFIG_OF_CONTROL
- if (exynos_fimd_parse_dt(gd->fdt_blob))
- debug("Can't get proper panel info\n");
#ifdef CONFIG_EXYNOS_MIPI_DSIM
exynos_init_dsim_platform_data(&panel_info);
#endif
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 74e72a5..c24984b 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -61,8 +61,6 @@
#ifdef CONFIG_LCD
#define CONFIG_EXYNOS_FB
#define CONFIG_EXYNOS_DP
-#define LCD_XRES 2560
-#define LCD_YRES 1600
#define LCD_BPPLCD_COLOR16
#endif
diff --git a/include/configs/s5pc210_universal.h
b/include/configs/s5pc210_universal.h
index eb046cd..20985da 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -247,7 +247,4 @@ int universal_spi_read(void);
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-#define LCD_XRES 480
-#define LCD_YRES 800
-
#endif /* __CONFIG_H */
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 7db1db6..6fa646b 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -261,7 +261,4 @@
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-#define LCD_XRES 720
-#define
Re: [U-Boot] [PATCH V4 0/9] peach_pit: Add support for FIMD, DP and parade chip
+Minkyu On Mon, Aug 4, 2014 at 4:49 PM, Simon Glass wrote: > Hi, > > On 30 July 2014 03:11, Ajay Kumar wrote: >> Patchset V1: >> https://www.mail-archive.com/u-boot@lists.denx.de/msg140596.html >> >> Patchset V2: >> https://www.mail-archive.com/u-boot@lists.denx.de/msg141203.html >> >> Patchset V3: >> http://lists.denx.de/pipermail/u-boot/2014-July/183096.html >> >> Changes from V1: >> [PATCH V2 3/10] : Don't mix cpu_is and proid_is as per Minkyu's suggestion. >> Also, incorporate Simon's suggestion of not using else. >> [PATCH V2 4/10] : For FIMD SYSMMU DT, use same compatible string as kernel. >> [TEST_ONLY V2 6/10]: Make this patch TEST_ONLY >> >> Changes from V2: >> [PATCH V3 5/9] : Use SPDX tags to define the license for the file: parade.c >> Removed TEST_ONLY patches. >> >> Changes from V3: >> [PATCH V4 1/9] : Fix comment style. >> [PATCH V4 3/9] : Use 'else if' clause instead of 'if'. > > Is this series ready to be merged? I have several series dependent on it. I have addressed all the comments from Minkyu. Hopefully, it should get in this time! Ajay ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V4 8/9] ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chip
This patch adds DT properties for fimd and the parade bridge chip
present on peach_pit. The panel supports 1366x768 resolution.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/dts/exynos5420-peach-pit.dts | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts
b/arch/arm/dts/exynos5420-peach-pit.dts
index 8d148af..3ed70a8 100644
--- a/arch/arm/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -63,6 +63,11 @@
reg = <0x20>;
compatible = "maxim,max98090-codec";
};
+
+ edp-lvds-bridge@48 {
+ compatible = "parade,ps8625";
+ reg = <0x48>;
+ };
};
sound@383 {
@@ -124,4 +129,29 @@
xhci@1240 {
samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
};
+
+ fimd@1440 {
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <1366>;
+ samsung,vl-row = <768>;
+ samsung,vl-width = <1366>;
+ samsung,vl-height = <768>;
+
+ samsung,vl-clkp;
+ samsung,vl-dp;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <32>;
+ samsung,vl-hbpd = <40>;
+ samsung,vl-hfpd = <40>;
+ samsung,vl-vspw = <6>;
+ samsung,vl-vbpd = <10>;
+ samsung,vl-vfpd = <12>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,winid = <3>;
+ samsung,interface-mode = <1>;
+ samsung,dp-enabled = <1>;
+ samsung,dual-lcd-enabled = <0>;
+ };
};
--
1.7.9.5
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[U-Boot] [PATCH V4 9/9] CONFIGS: peach-pit: Enable display for peach_pit board
Enable drivers for FIMD, DP and parade bridge chip. Signed-off-by: Ajay Kumar Acked-by: Simon Glass Tested-by: Simon Glass --- include/configs/peach-pit.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 76b8d7a..88c093f 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -22,4 +22,14 @@ #define CONFIG_SYS_PROMPT "Peach # " #define CONFIG_IDENT_STRING" for Peach" +#define CONFIG_VIDEO_PARADE + +/* Display */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_EXYNOS_FB +#define CONFIG_EXYNOS_DP +#define LCD_BPPLCD_COLOR16 +#endif + #endif /* __CONFIG_PEACH_PIT_H */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V4 3/9] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/cpu/armv7/exynos/clock.c | 83 +++--
arch/arm/cpu/armv7/exynos/exynos5_setup.h |2 +-
arch/arm/include/asm/arch-exynos/clk.h|1 +
3 files changed, 80 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 400d134..c8be39b 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r,
unsigned int k)
* VPLL_CON: MIDV [24:16]
* BPLL_CON: MIDV [25:16]: Exynos5
*/
- if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
+ if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
+ pllreg == SPLL)
mask = 0x3ff;
else
mask = 0x1ff;
@@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg)
r = readl(&clk->rpll_con0);
k = readl(&clk->rpll_con1);
break;
+ case SPLL:
+ r = readl(&clk->spll_con0);
+ break;
default:
printf("Unsupported PLL (%d)\n", pllreg);
return 0;
@@ -1027,6 +1031,40 @@ static unsigned long exynos5_get_lcd_clk(void)
return pclk;
}
+static unsigned long exynos5420_get_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long pclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+* CLK_SRC_DISP10
+* FIMD1_SEL [4]
+* 0: SCLK_RPLL
+* 1: SCLK_SPLL
+*/
+ sel = readl(&clk->src_disp10);
+ sel &= (1 << 4);
+
+ if (sel)
+ sclk = get_pll_clk(SPLL);
+ else
+ sclk = get_pll_clk(RPLL);
+
+ /*
+* CLK_DIV_DISP10
+* FIMD1_RATIO [3:0]
+*/
+ ratio = readl(&clk->div_disp10);
+ ratio = ratio & 0xf;
+
+ pclk = sclk / (ratio + 1);
+
+ return pclk;
+}
+
void exynos4_set_lcd_clk(void)
{
struct exynos4_clock *clk =
@@ -1131,6 +1169,33 @@ void exynos5_set_lcd_clk(void)
clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
}
+void exynos5420_set_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned int cfg;
+
+ /*
+* CLK_SRC_DISP10
+* FIMD1_SEL [4]
+* 0: SCLK_RPLL
+* 1: SCLK_SPLL
+*/
+ cfg = readl(&clk->src_disp10);
+ cfg &= ~(0x1 << 4);
+ cfg |= (0 << 4);
+ writel(cfg, &clk->src_disp10);
+
+ /*
+* CLK_DIV_DISP10
+* FIMD1_RATIO [3:0]
+*/
+ cfg = readl(&clk->div_disp10);
+ cfg &= ~(0xf << 0);
+ cfg |= (0 << 0);
+ writel(cfg, &clk->div_disp10);
+}
+
void exynos4_set_mipi_clk(void)
{
struct exynos4_clock *clk =
@@ -1602,16 +1667,24 @@ unsigned long get_lcd_clk(void)
{
if (cpu_is_exynos4())
return exynos4_get_lcd_clk();
- else
- return exynos5_get_lcd_clk();
+ else {
+ if (proid_is_exynos5420())
+ return exynos5420_get_lcd_clk();
+ else
+ return exynos5_get_lcd_clk();
+ }
}
void set_lcd_clk(void)
{
if (cpu_is_exynos4())
exynos4_set_lcd_clk();
- else
- exynos5_set_lcd_clk();
+ else {
+ if (proid_is_exynos5250())
+ exynos5_set_lcd_clk();
+ else if (proid_is_exynos5420())
+ exynos5420_set_lcd_clk();
+ }
}
void set_mipi_clk(void)
diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
index 3242093..2eea48a 100644
--- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
+++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
@@ -783,7 +783,7 @@
#define CLK_SRC_TOP2_VAL 0x11101000
#define CLK_SRC_TOP3_VAL 0x
#define CLK_SRC_TOP4_VAL 0x0111
-#define CLK_SRC_TOP5_VAL 0x1100
+#define CLK_SRC_TOP5_VAL 0x1101
#define CLK_SRC_TOP6_VAL 0x0111
#define CLK_SRC_TOP7_VAL 0x00022200
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index ffbc07e..db24dc0 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -15,6 +15,7 @@
#define VPLL 4
#define BPLL 5
#define RPLL 6
+#define SPL
[U-Boot] [PATCH V4 4/9] video: exynos_fimd: Add framework to disable FIMD sysmmu
On Exynos5420 and newer versions, the FIMD sysmmus are in
"on state" by default.
We have to disable them in order to make FIMD DMA work.
This patch adds the required framework to exynos_fimd driver,
and disables FIMD sysmmu on Exynos5420.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
---
arch/arm/dts/exynos54xx.dtsi | 10 ++
doc/device-tree-bindings/video/exynos-fb.txt |6
drivers/video/exynos_fimd.c | 43 ++
include/fdtdec.h |1 +
lib/fdtdec.c |1 +
5 files changed, 61 insertions(+)
diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi
index b9f8e0b..c21d798 100644
--- a/arch/arm/dts/exynos54xx.dtsi
+++ b/arch/arm/dts/exynos54xx.dtsi
@@ -113,6 +113,16 @@
status = "disabled";
};
+ fimdm0_sysmmu@0x1464 {
+ compatible = "samsung,sysmmu-v3.3";
+ reg = <0x1464 0x100>;
+ };
+
+ fimdm1_sysmmu@0x1468 {
+ compatible = "samsung,sysmmu-v3.3";
+ reg = <0x1468 0x100>;
+ };
+
fimd@1440 {
/* sysmmu is not used in U-Boot */
samsung,disable-sysmmu;
diff --git a/doc/device-tree-bindings/video/exynos-fb.txt
b/doc/device-tree-bindings/video/exynos-fb.txt
index bb7441c..dc4e44f 100644
--- a/doc/device-tree-bindings/video/exynos-fb.txt
+++ b/doc/device-tree-bindings/video/exynos-fb.txt
@@ -55,6 +55,12 @@ Board(panel specific):
samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)
samsung,sclk-div: parent_clock/source_clock ratio
samsung,dual-lcd-enabled: 1 if you support two LCD, else 0
+ samsung,disable-sysmmu: Define this if you want to disable FIMD sysmmu.
+ (needed for Exynos5420 and newer versions)
+ Add the required FIMD sysmmu nodes to be
+ disabled with compatible string
+ "samsung,sysmmu-v3.3", with a "reg" property
+ holding the register address of FIMD sysmmu.
Example:
SOC specific part:
diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
index cebbba7..f67fa81 100644
--- a/drivers/video/exynos_fimd.c
+++ b/drivers/video/exynos_fimd.c
@@ -251,6 +251,45 @@ void exynos_fimd_window_off(unsigned int win_id)
writel(cfg, &fimd_ctrl->winshmap);
}
+#ifdef CONFIG_OF_CONTROL
+/*
+* The reset value for FIMD SYSMMU register MMU_CTRL is 3
+* on Exynos5420 and newer versions.
+* This means FIMD SYSMMU is on by default on Exynos5420
+* and newer versions.
+* Since in u-boot we don't use SYSMMU, we should disable
+* those FIMD SYSMMU.
+* Note that there are 2 SYSMMU for FIMD: m0 and m1.
+* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3.
+* We disable both of them here.
+*/
+void exynos_fimd_disable_sysmmu(void)
+{
+ u32 *sysmmufimd;
+ unsigned int node;
+ int node_list[2];
+ int count;
+ int i;
+
+ count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd",
+ COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2);
+ for (i = 0; i < count; i++) {
+ node = node_list[i];
+ if (node <= 0) {
+ debug("Can't get device node for fimd sysmmu\n");
+ return;
+ }
+
+ sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
+ if (!sysmmufimd) {
+ debug("Can't get base address for sysmmu fimdm0");
+ return;
+ }
+
+ writel(0x0, sysmmufimd);
+ }
+}
+#endif
void exynos_fimd_lcd_init(vidinfo_t *vid)
{
@@ -268,6 +307,10 @@ void exynos_fimd_lcd_init(vidinfo_t *vid)
node, "reg");
if (fimd_ctrl == NULL)
debug("Can't get the FIMD base address\n");
+
+ if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
+ exynos_fimd_disable_sysmmu();
+
#else
fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd();
#endif
diff --git a/include/fdtdec.h b/include/fdtdec.h
index a7e6ee7..a583d68 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -94,6 +94,7 @@ enum fdt_compat_id {
COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */
COMPAT_TI_TPS65090, /* Texas Instrument TPS65090 */
COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */
+ COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */
COMPAT_COUNT,
};
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index a
[U-Boot] [PATCH V4 7/9] exynos5420: add callbacks needed for exynos_fb driver
Add initialization code for peach_pit panel, parade bridge chip,
and backlight.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/include/asm/arch-exynos/system.h |3 +
board/samsung/smdk5420/smdk5420.c | 129 +++--
2 files changed, 50 insertions(+), 82 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/system.h
b/arch/arm/include/asm/arch-exynos/system.h
index 4968d3d..320763f 100644
--- a/arch/arm/include/asm/arch-exynos/system.h
+++ b/arch/arm/include/asm/arch-exynos/system.h
@@ -41,4 +41,7 @@ void set_usbhost_mode(unsigned int mode);
void set_system_display_ctrl(void);
int exynos_lcd_early_init(const void *blob);
+/* Initialize the Parade dP<->LVDS bridge if present */
+int parade_init(const void *blob);
+
#endif /* _EXYNOS4_SYSTEM_H */
diff --git a/board/samsung/smdk5420/smdk5420.c
b/board/samsung/smdk5420/smdk5420.c
index 183c522..270ee83 100644
--- a/board/samsung/smdk5420/smdk5420.c
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -10,11 +10,14 @@
#include
#include
#include
+#include
#include
#include
#include
#include
+#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -40,95 +43,57 @@ int exynos_init(void)
}
#ifdef CONFIG_LCD
-void cfg_lcd_gpio(void)
+static int has_edp_bridge(void)
{
- /* For Backlight */
- gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_OUTPUT);
- gpio_set_value(EXYNOS5420_GPIO_B20, 1);
+ int node;
+
+ node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_PARADE_PS8625);
- /* LCD power on */
- gpio_cfg_pin(EXYNOS5420_GPIO_X15, S5P_GPIO_OUTPUT);
- gpio_set_value(EXYNOS5420_GPIO_X15, 1);
+ /* No node for bridge in device tree. */
+ if (node <= 0)
+ return 0;
- /* Set Hotplug detect for DP */
- gpio_cfg_pin(EXYNOS5420_GPIO_X07, S5P_GPIO_FUNC(0x3));
+ /* Default is with bridge ic */
+ return 1;
}
-vidinfo_t panel_info = {
- .vl_freq= 60,
- .vl_col = 2560,
- .vl_row = 1600,
- .vl_width = 2560,
- .vl_height = 1600,
- .vl_clkp= CONFIG_SYS_LOW,
- .vl_hsp = CONFIG_SYS_LOW,
- .vl_vsp = CONFIG_SYS_LOW,
- .vl_dp = CONFIG_SYS_LOW,
- .vl_bpix= 4,/* LCD_BPP = 2^4, for output conosle on LCD */
-
- /* wDP panel timing infomation */
- .vl_hspw= 32,
- .vl_hbpd= 80,
- .vl_hfpd= 48,
-
- .vl_vspw= 6,
- .vl_vbpd= 37,
- .vl_vfpd= 3,
- .vl_cmd_allow_len = 0xf,
-
- .win_id = 3,
- .cfg_gpio = cfg_lcd_gpio,
- .backlight_on = NULL,
- .lcd_power_on = NULL,
- .reset_lcd = NULL,
- .dual_lcd_enabled = 0,
-
- .init_delay = 0,
- .power_on_delay = 0,
- .reset_delay= 0,
- .interface_mode = FIMD_RGB_INTERFACE,
- .dp_enabled = 1,
-};
-
-static struct edp_device_info edp_info = {
- .disp_info = {
- .h_res = 2560,
- .h_sync_width = 32,
- .h_back_porch = 80,
- .h_front_porch = 48,
- .v_res = 1600,
- .v_sync_width = 6,
- .v_back_porch = 37,
- .v_front_porch = 3,
- .v_sync_rate = 60,
- },
- .lt_info = {
- .lt_status = DP_LT_NONE,
- },
- .video_info = {
- .master_mode = 0,
- .bist_mode = DP_DISABLE,
- .bist_pattern = NO_PATTERN,
- .h_sync_polarity = 0,
- .v_sync_polarity = 0,
- .interlaced = 0,
- .color_space = COLOR_RGB,
- .dynamic_range = VESA,
- .ycbcr_coeff = COLOR_YCBCR601,
- .color_depth = COLOR_8,
- },
-};
-
-static struct exynos_dp_platform_data dp_platform_data = {
- .phy_enable = set_dp_phy_ctrl,
- .edp_dev_info = &edp_info,
-};
-
-void init_panel_info(vidinfo_t *vid)
+void exynos_lcd_power_on(void)
{
- vid->rgb_mode = MODE_RGB_P;
+ int ret;
+
+#ifdef CONFIG_POWER_TPS65090
+ ret = tps65090_init();
+ if (ret < 0) {
+ printf("%s: tps65090_init() failed\n", __func__);
+ return;
+ }
+
+ tps65090_fet_enable(6);
+#endif
+
+ mdelay(5);
+
+ /* TODO(ajaykumar...@samsung.com): Use device tree */
+ gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */
+ mdelay(10);
+ gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */
+ gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
+ gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
- exynos_set_dp_platform_data(&dp_platform_data);
+ if (has_edp_bridge())
+ if (parade_init(gd->fdt_blob))
+
[U-Boot] [PATCH V4 1/9] exynos_fb: Remove usage of static defines
Previously, we used to statically assign values for vl_col, vl_row and
vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.
Introducing the function exynos_lcd_early_init() would take care of this
assignment on the fly by parsing FIMD DT properties, thereby allowing us
to remove LCD_XRES and LCD_YRES from the main config file.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/include/asm/arch-exynos/system.h |1 +
board/samsung/common/board.c | 15 +++
drivers/video/exynos_fb.c | 17 +
include/configs/exynos5250-dt.h |2 --
include/configs/s5pc210_universal.h |3 ---
include/configs/trats.h |3 ---
include/configs/trats2.h |3 ---
7 files changed, 21 insertions(+), 23 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/system.h
b/arch/arm/include/asm/arch-exynos/system.h
index 7e2057c..4968d3d 100644
--- a/arch/arm/include/asm/arch-exynos/system.h
+++ b/arch/arm/include/asm/arch-exynos/system.h
@@ -39,5 +39,6 @@ struct exynos5_sysreg {
void set_usbhost_mode(unsigned int mode);
void set_system_display_ctrl(void);
+int exynos_lcd_early_init(const void *blob);
#endif /* _EXYNOS4_SYSTEM_H */
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 9dc7c83..1f6f0a0 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -148,6 +149,20 @@ int board_early_init_f(void)
board_i2c_init(gd->fdt_blob);
#endif
+#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_EXYNOS_FB)
+/*
+ * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
+ * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix, to reserve
+ * FB memory at a very early stage. So, we need to fill panel_info.vl_col,
+ * panel_info.vl_row and panel_info.vl_bpix before lcd_setmem() is called.
+ */
+ err = exynos_lcd_early_init(gd->fdt_blob);
+ if (err) {
+ debug("LCD early init failed\n");
+ return err;
+ }
+#endif
+
return exynos_early_init_f();
}
#endif
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
index e1e0d80..bc478a9 100644
--- a/drivers/video/exynos_fb.c
+++ b/drivers/video/exynos_fb.c
@@ -27,17 +27,13 @@ DECLARE_GLOBAL_DATA_PTR;
static unsigned int panel_width, panel_height;
-/*
- * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
- * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix to reserve
- * FB memory at a very early stage, i.e even before exynos_fimd_parse_dt()
- * is called. So, we are forced to statically assign it.
- */
#ifdef CONFIG_OF_CONTROL
vidinfo_t panel_info = {
- .vl_col = LCD_XRES,
- .vl_row = LCD_YRES,
- .vl_bpix = LCD_COLOR16,
+ /*
+* Insert a value here so that we don't end up in the BSS
+* Reference: drivers/video/tegra.c
+*/
+ .vl_col = -1,
};
#endif
@@ -141,7 +136,7 @@ static void lcd_panel_on(vidinfo_t *vid)
}
#ifdef CONFIG_OF_CONTROL
-int exynos_fimd_parse_dt(const void *blob)
+int exynos_lcd_early_init(const void *blob)
{
unsigned int node;
node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD);
@@ -286,8 +281,6 @@ void lcd_ctrl_init(void *lcdbase)
set_lcd_clk();
#ifdef CONFIG_OF_CONTROL
- if (exynos_fimd_parse_dt(gd->fdt_blob))
- debug("Can't get proper panel info\n");
#ifdef CONFIG_EXYNOS_MIPI_DSIM
exynos_init_dsim_platform_data(&panel_info);
#endif
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 74e72a5..c24984b 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -61,8 +61,6 @@
#ifdef CONFIG_LCD
#define CONFIG_EXYNOS_FB
#define CONFIG_EXYNOS_DP
-#define LCD_XRES 2560
-#define LCD_YRES 1600
#define LCD_BPPLCD_COLOR16
#endif
diff --git a/include/configs/s5pc210_universal.h
b/include/configs/s5pc210_universal.h
index eb046cd..20985da 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -247,7 +247,4 @@ int universal_spi_read(void);
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-#define LCD_XRES 480
-#define LCD_YRES 800
-
#endif /* __CONFIG_H */
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 90f1962..35c1feb 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -261,7 +261,4 @@
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-#define LCD_XRES 720
-#define LCD_YRES 1280
-
#endif /* __CONFIG_H */
diff --git a/include/configs/trats2.
[U-Boot] [PATCH V4 6/9] ARM: exynos: Add missing declaration for gpio_direction_input
This patch adds missing declaration for gpio_direction_input
function, thereby helps in resolving compilation warnings.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/include/asm/arch-exynos/gpio.h |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h
index be5113f..8fb5c23 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1504,6 +1504,7 @@ static const struct gpio_name_num_table
exynos5420_gpio_table[] = {
void gpio_cfg_pin(int gpio, int cfg);
void gpio_set_pull(int gpio, int mode);
void gpio_set_drv(int gpio, int mode);
+int gpio_direction_input(unsigned gpio);
int gpio_direction_output(unsigned gpio, int value);
int gpio_set_value(unsigned gpio, int value);
int gpio_get_value(unsigned gpio);
--
1.7.9.5
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[U-Boot] [PATCH V4 0/9] peach_pit: Add support for FIMD, DP and parade chip
Patchset V1: https://www.mail-archive.com/u-boot@lists.denx.de/msg140596.html Patchset V2: https://www.mail-archive.com/u-boot@lists.denx.de/msg141203.html Patchset V3: http://lists.denx.de/pipermail/u-boot/2014-July/183096.html Changes from V1: [PATCH V2 3/10] : Don't mix cpu_is and proid_is as per Minkyu's suggestion. Also, incorporate Simon's suggestion of not using else. [PATCH V2 4/10] : For FIMD SYSMMU DT, use same compatible string as kernel. [TEST_ONLY V2 6/10]: Make this patch TEST_ONLY Changes from V2: [PATCH V3 5/9] : Use SPDX tags to define the license for the file: parade.c Removed TEST_ONLY patches. Changes from V3: [PATCH V4 1/9] : Fix comment style. [PATCH V4 3/9] : Use 'else if' clause instead of 'if'. Ajay Kumar (8): [PATCH V4 1/9] exynos_fb: Remove usage of static defines [PATCH V4 2/9] arm: exynos: Add RPLL for Exynos5420 [PATCH V4 3/9] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 [PATCH V4 4/9] video: exynos_fimd: Add framework to disable FIMD sysmmu [PATCH V4 6/9] ARM: exynos: Add missing declaration for gpio_direction_input [PATCH V4 7/9] exynos5420: add callbacks needed for exynos_fb driver [PATCH V4 8/9] ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chip [PATCH V4 9/9] CONFIGS: peach-pit: Enable display for peach_pit board Vadim Bendebury (1): [PATCH V4 5/9] video: Add driver for Parade PS8625 dP to LVDS bridge arch/arm/cpu/armv7/exynos/clock.c | 83 - arch/arm/cpu/armv7/exynos/clock_init.h |3 + arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 ++ arch/arm/cpu/armv7/exynos/exynos5_setup.h |2 +- arch/arm/dts/exynos5420-peach-pit.dts | 30 arch/arm/dts/exynos54xx.dtsi | 10 ++ arch/arm/include/asm/arch-exynos/clk.h |1 + arch/arm/include/asm/arch-exynos/gpio.h|1 + arch/arm/include/asm/arch-exynos/system.h |4 + board/samsung/common/board.c | 15 ++ board/samsung/smdk5420/smdk5420.c | 129 +- doc/device-tree-bindings/video/exynos-fb.txt |6 + drivers/video/Makefile |1 + drivers/video/exynos_fb.c | 17 +- drivers/video/exynos_fimd.c| 43 + drivers/video/parade.c | 220 include/configs/exynos5250-dt.h|2 - include/configs/peach-pit.h| 10 ++ include/configs/s5pc210_universal.h|3 - include/configs/trats.h|3 - include/configs/trats2.h |3 - include/fdtdec.h |2 + lib/fdtdec.c |2 + 23 files changed, 492 insertions(+), 111 deletions(-) create mode 100644 drivers/video/parade.c -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V4 2/9] arm: exynos: Add RPLL for Exynos5420
RPLL is needed to drive the LCD panel on Exynos5420 based boards.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/cpu/armv7/exynos/clock_init.h |3 +++
arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 +
2 files changed, 16 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h
b/arch/arm/cpu/armv7/exynos/clock_init.h
index a875d0b..fce502f 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init.h
+++ b/arch/arm/cpu/armv7/exynos/clock_init.h
@@ -75,6 +75,9 @@ struct mem_timings {
unsigned spll_mdiv;
unsigned spll_pdiv;
unsigned spll_sdiv;
+ unsigned rpll_mdiv;
+ unsigned rpll_pdiv;
+ unsigned rpll_sdiv;
unsigned pclk_cdrex_ratio;
unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
index 1d6977f..b6a9bc1 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
+++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
@@ -179,6 +179,10 @@ struct mem_timings mem_timings[] = {
.spll_mdiv = 0xc8,
.spll_pdiv = 0x3,
.spll_sdiv = 0x2,
+ /* RPLL @70.5Mhz */
+ .rpll_mdiv = 0x5E,
+ .rpll_pdiv = 0x2,
+ .rpll_sdiv = 0x4,
.direct_cmd_msr = {
0x00020018, 0x0003, 0x00010046, 0x0d70,
@@ -800,6 +804,7 @@ static void exynos5420_system_clock_init(void)
writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
+ writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);
setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
@@ -898,6 +903,14 @@ static void exynos5420_system_clock_init(void)
while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
;
+ /* Set RPLL */
+ writel(RPLL_CON2_VAL, &clk->rpll_con2);
+ writel(RPLL_CON1_VAL, &clk->rpll_con1);
+ val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv);
+ writel(val, &clk->rpll_con0);
+ while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0)
+ ;
+
writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
--
1.7.9.5
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[U-Boot] [PATCH V4 5/9] video: Add driver for Parade PS8625 dP to LVDS bridge
From: Vadim Bendebury
The initialization table comes from the "Illustration of I2C command
for initialing PS8625" document supplied by Parade.
Signed-off-by: Vadim Bendebury
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
drivers/video/Makefile |1 +
drivers/video/parade.c | 220
include/fdtdec.h |1 +
lib/fdtdec.c |1 +
4 files changed, 223 insertions(+)
create mode 100644 drivers/video/parade.c
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 945f35d..8618590 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -41,3 +41,4 @@ obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
obj-$(CONFIG_VIDEO_TEGRA) += tegra.o
obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
obj-$(CONFIG_FORMIKE) += formike.o
+obj-$(CONFIG_VIDEO_PARADE) += parade.o
diff --git a/drivers/video/parade.c b/drivers/video/parade.c
new file mode 100644
index 000..0f543f6
--- /dev/null
+++ b/drivers/video/parade.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * This file is a driver for Parade dP<->LVDS bridges. The original submission
+ * is for the ps8625 chip.
+ */
+#include
+#include
+#include
+#include
+
+/*
+ * Initialization of the chip is a process of writing certaing values into
+ * certain registers over i2c bus. The chip in fact responds to a range of
+ * addresses on the i2c bus, so for each written value three parameters are
+ * required: i2c address, register address and the actual value.
+ *
+ * The base address is derived from the device tree, only address offset is
+ * stored in the table below.
+ */
+/**
+ * struct reg_data() - data for a parade register write
+ *
+ * @addr_offoffset from the i2c base address for parade
+ * @reg_addrregister address to write
+ * @value value to be written
+ */
+struct reg_data {
+ uint8_t addr_off;
+ uint8_t reg;
+ uint8_t value;
+} _packed;
+
+#define END_OF_TABLE 0xff /* Ficticious offset */
+
+static const struct reg_data parade_values[] = {
+ {0x02, 0xa1, 0x01}, /* HPD low */
+/*
+ * SW setting
+ * [1:0] SW output 1.2V voltage is lower to 96%
+ */
+ {0x04, 0x14, 0x01},
+/*
+ * RCO SS setting
+ * [5:4] = b01 0.5%, b10 1%, b11 1.5%
+ */
+ {0x04, 0xe3, 0x20},
+ {0x04, 0xe2, 0x80}, /* [7] RCO SS enable */
+/*
+ * RPHY Setting
+ * [3:2] CDR tune wait cycle before
+ * measure for fine tune b00: 1us,
+ * 01: 0.5us, 10:2us, 11:4us.
+ */
+ {0x04, 0x8a, 0x0c},
+ {0x04, 0x89, 0x08}, /* [3] RFD always on */
+/*
+ * CTN lock in/out:
+ * 2ppm/8ppm. Lock out 2
+ * times.
+ */
+ {0x04, 0x71, 0x2d},
+/*
+ * 2.7G CDR settings
+ * NOF=40LSB for HBR CDR setting
+ */
+ {0x04, 0x7d, 0x07},
+ {0x04, 0x7b, 0x00}, /* [1:0] Fmin=+4bands */
+ {0x04, 0x7a, 0xfd}, /* [7:5] DCO_FTRNG=+-40% */
+/*
+ * 1.62G CDR settings
+ * [5:2]NOF=64LSB [1:0]DCO scale is 2/5
+ */
+ {0x04, 0xc0, 0x12},
+ {0x04, 0xc1, 0x92}, /* Gitune=-37% */
+ {0x04, 0xc2, 0x1c}, /* Fbstep=100% */
+ {0x04, 0x32, 0x80}, /* [7] LOS signal disable */
+/*
+ * RPIO Setting
+ * [7:4] LVDS driver bias current :
+ * 75% (250mV swing)
+ */
+ {0x04, 0x00, 0xb0},
+/*
+ * [7:6] Right-bar GPIO output strength is 8mA
+ */
+ {0x04, 0x15, 0x40},
+/* EQ Training State Machine Setting */
+ {0x04, 0x54, 0x10}, /* RCO calibration start */
+/* [4:0] MAX_LANE_COUNT set to one lane */
+ {0x01, 0x02, 0x81},
+/* [4:0] LANE_COUNT_SET set to one lane */
+ {0x01, 0x21, 0x81},
+ {0x00, 0x52, 0x20},
+ {0x00, 0xf1, 0x03}, /* HPD CP toggle enable */
+ {0x00, 0x62, 0x41},
+/* Counter number, add 1ms counter delay */
+ {0x00, 0xf6, 0x01},
+/*
+ * [6]PWM function control by
+ * DPCD0040f[7], default is PWM
+ * block always works.
+ */
+ {0x00, 0x77, 0x06},
+/*
+ * 04h Adjust VTotal tolerance to
+ * fix the 30Hz no display issue
+ */
+ {0x00, 0x4c, 0x04},
+/* DPCD00400='h00, Parade OUI = 'h001cf8 */
+ {0x01, 0xc0, 0x00},
+ {0x01, 0xc1, 0x1c}, /* DPCD00401='h1c */
+ {0x01, 0xc2, 0xf8}, /* DPCD00402='hf8 */
+/*
+ * DPCD403~408 = ASCII code
+ * D2SLV5='h4432534c5635
+ */
+ {0x01, 0xc3, 0x44},
+ {0x01, 0xc4, 0x32}, /* DPCD404 */
+ {0x01, 0xc5, 0x53}, /* DPCD405 */
+ {0x01, 0xc6, 0x4c}, /* DPCD406 */
+ {0x01, 0xc7,
Re: [U-Boot] [PATCH V3 0/9] peach_pit: Add support for FIMD, DP and parade chip
Hi Minkyu, I think you can pick this series. This has been tested and Acked. Regards, Ajay Kumar On Fri, Jul 4, 2014 at 6:49 PM, Ajay Kumar wrote: > Patchset V1: > https://www.mail-archive.com/u-boot@lists.denx.de/msg140596.html > > Patchset V2: > https://www.mail-archive.com/u-boot@lists.denx.de/msg141203.html > > Changes from V1: > [PATCH V2 3/10] : Don't mix cpu_is and proid_isas per Minkyu's suggestion. > Also, incorporate Simon's suggestion of not using else. > [PATCH V2 4/10] : For FIMD SYSMMU DT, use same compatible string as kernel. > [TEST_ONLY V2 6/10]: Make this patch TEST_ONLY > > Changes from V2: > [PATCH V3 5/9] : Use SPDX tags to define the license for the file: parade.c > Removed TEST_ONLY patches. > > Ajay Kumar (8): > [PATCH V3 1/9] exynos_fb: Remove usage of static defines > [PATCH V3 2/9] arm: exynos: Add RPLL for Exynos5420 > [PATCH V3 3/9] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for > Exynos5420 > [PATCH V3 4/9] video: exynos_fimd: Add framework to disable FIMD sysmmu > [PATCH V3 6/9] ARM: exynos: Add missing declaration for gpio_direction_input > [PATCH V3 7/9] exynos5420: add callbacks needed for exynos_fb driver > [PATCH V3 8/9] ARM: exynos: peach_pit: Add DT nodes for fimd and parade > bridge chip > [PATCH V3 9/9] CONFIGS: peach-pit: Enable display for peach_pit board > > Vadim Bendebury (1): > [PATCH V3 5/9] video: Add driver for Parade PS8625 dP to LVDS bridge > > arch/arm/cpu/armv7/exynos/clock.c | 83 - > arch/arm/cpu/armv7/exynos/clock_init.h |3 + > arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 ++ > arch/arm/cpu/armv7/exynos/exynos5_setup.h |2 +- > arch/arm/dts/exynos5420-peach-pit.dts | 30 > arch/arm/dts/exynos54xx.dtsi | 10 ++ > arch/arm/include/asm/arch-exynos/clk.h |1 + > arch/arm/include/asm/arch-exynos/gpio.h|1 + > arch/arm/include/asm/arch-exynos/system.h |4 + > board/samsung/common/board.c | 15 ++ > board/samsung/smdk5420/smdk5420.c | 129 +- > doc/device-tree-bindings/video/exynos-fb.txt |6 + > drivers/video/Makefile |1 + > drivers/video/exynos_fb.c | 17 +- > drivers/video/exynos_fimd.c| 43 + > drivers/video/parade.c | 220 > > include/configs/exynos5250-dt.h|2 - > include/configs/peach-pit.h| 10 ++ > include/configs/s5pc210_universal.h|3 - > include/configs/trats.h|3 - > include/configs/trats2.h |3 - > include/fdtdec.h |2 + > lib/fdtdec.c |2 + > 23 files changed, 492 insertions(+), 111 deletions(-) > create mode 100644 drivers/video/parade.c > > -- > 1.7.9.5 > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V3 4/9] video: exynos_fimd: Add framework to disable FIMD sysmmu
Hi Simon, On Fri, Jul 11, 2014 at 9:17 AM, Simon Glass wrote: > On 4 July 2014 07:19, Ajay Kumar wrote: >> >> On Exynos5420 and newer versions, the FIMD sysmmus are in >> "on state" by default. >> We have to disable them in order to make FIMD DMA work. >> This patch adds the required framework to exynos_fimd driver, >> and disables FIMD sysmmu on Exynos5420. >> >> Signed-off-by: Ajay Kumar > > > Acked-by: Simon Glass > > (was there supposed to be a change log or is this a new patch?) This is old patch with a new compatible string as in kernel. I have added the change log in coverletter: [PATCH V3 0/9] peach_pit: Add support for FIMD, DP and parade chip Regards, Ajay Kumar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/6] cros_ec: exynos: Use the correct tps65090 driver in each case
On Mon, Jul 7, 2014 at 9:46 PM, Simon Glass wrote:
> Exynos 5250 boards (snow, spring) use the I2C driver but Exynos 5420 boards
> cannot due to a hardware design decision. Select out the correct driver to
> use in each case.
>
> Signed-off-by: Simon Glass
> ---
>
> board/samsung/common/board.c| 6 ++
> drivers/power/pmic/Makefile | 2 +-
> include/configs/exynos5250-dt.h | 1 +
> include/configs/peach-pit.h | 2 ++
> include/configs/smdk5420.h | 2 ++
> 5 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
> index 9dc7c83..108c82b 100644
> --- a/board/samsung/common/board.c
> +++ b/board/samsung/common/board.c
> @@ -21,6 +21,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -157,6 +158,11 @@ int power_init_board(void)
> {
> set_ps_hold_ctrl();
>
> +#ifdef CONFIG_POWER_TPS65090
> + tps65090_fet_enable(1); /* Enable FET1, backlight */
> + tps65090_fet_enable(6); /* Enable FET6, lcd panel */
> +#endif
> +
> return exynos_power_init();
> }
> #endif
> diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
> index 0b76611..e7b07eb 100644
> --- a/drivers/power/pmic/Makefile
> +++ b/drivers/power/pmic/Makefile
> @@ -11,7 +11,7 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
> obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
> obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
> obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
> -obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o
> +obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o
> obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o
> obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
> obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
> diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
> index 74e72a5..2c0df29 100644
> --- a/include/configs/exynos5250-dt.h
> +++ b/include/configs/exynos5250-dt.h
> @@ -42,6 +42,7 @@
>
> /* PMIC */
> #define CONFIG_POWER_MAX77686
> +#define CONFIG_POWER_TPS65090_I2C
>
> /* Sound */
> #define CONFIG_CMD_SOUND
> diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
> index 76b8d7a..41ccd10 100644
> --- a/include/configs/peach-pit.h
> +++ b/include/configs/peach-pit.h
> @@ -22,4 +22,6 @@
> #define CONFIG_SYS_PROMPT "Peach # "
> #define CONFIG_IDENT_STRING" for Peach"
>
> +#define CONFIG_POWER_TPS65090_EC
> +
> #endif /* __CONFIG_PEACH_PIT_H */
> diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
> index 606739b..39d235c 100644
> --- a/include/configs/smdk5420.h
> +++ b/include/configs/smdk5420.h
> @@ -24,4 +24,6 @@
> #define CONFIG_SYS_PROMPT "SMDK5420 # "
> #define CONFIG_IDENT_STRING" for SMDK5420"
>
> +#define CONFIG_POWER_TPS65090_EC
> +
> #endif /* __CONFIG_SMDK5420_H */
> --
> 2.0.0.526.g5318336
>
> ___
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Able to test display on peach_pit(which needs tps65090) with these patches.
Also, crosec commands from u-boot prompt works as expected on peach_pit.
Tested-by: Ajay Kumar
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Re: [U-Boot] [PATCH 5/6] cros_ec: power: Add a tunnelled version of the tps65090 driver
all is ok, returns 0.
> + */
> +static int tps65090_fet_set(int fet_id, int set)
> +{
> + int retry;
> + u8 reg = 0, value;
> +
> + value = FET_CTRL_ADENFET | FET_CTRL_WAIT;
> + if (set)
> + value |= FET_CTRL_ENFET;
> +
> + if (tps65090_write(REG_FET1_CTRL + fet_id - 1, value))
> + return FET_ERR_COMMS;
> + /* Try reading until we get a result */
> + for (retry = 0; retry < MAX_CTRL_READ_TRIES; retry++) {
> + if (tps65090_read(REG_FET1_CTRL + fet_id - 1, ®))
> + return FET_ERR_COMMS;
> +
> + /* Check that the fet went into the expected state */
> + if (!!(reg & FET_CTRL_PGFET) == set)
> + return 0;
> +
> + /* If we got a timeout, there is no point in waiting longer */
> + if (reg & FET_CTRL_TOFET)
> + break;
> +
> + mdelay(1);
> + }
> +
> + debug("FET %d: Power good should have set to %d but reg=%#02x\n",
> + fet_id, set, reg);
> + return FET_ERR_NOT_READY;
> +}
> +
> +int tps65090_fet_enable(unsigned int fet_id)
> +{
> + int loops;
> + ulong start;
> + int ret = 0;
> +
> + if (tps65090_check_fet(fet_id))
> + return -1;
> +
> + start = get_timer(0);
> + for (loops = 0; ; loops++) {
> + ret = tps65090_fet_set(fet_id, 1);
> + if (!ret)
> + break;
> +
> + if (get_timer(start) > 100)
> + break;
> +
> + /* Turn it off and try again until we time out */
> + tps65090_fet_set(fet_id, 0);
> + }
> +
> + if (ret) {
> + debug("%s: FET%d failed to power on: time=%lums, loops=%d\n",
> + __func__, fet_id, get_timer(start), loops);
> + } else if (loops) {
> + debug("%s: FET%d powered on after %lums, loops=%d\n",
> + __func__, fet_id, get_timer(start), loops);
> + }
> + /*
> +* Unfortunately, there are some conditions where the power
> +* good bit will be 0, but the fet still comes up. One such
> +* case occurs with the lcd backlight. We'll just return 0 here
> +* and assume that the fet will eventually come up.
> +*/
> + if (ret == FET_ERR_NOT_READY)
> + ret = 0;
> +
> + return ret;
> +}
> +
> +int tps65090_fet_disable(unsigned int fet_id)
> +{
> + int ret;
> +
> + if (tps65090_check_fet(fet_id))
> + return -1;
> +
> + ret = tps65090_fet_set(fet_id, 0);
> +
> + return ret;
> +}
> +
> +int tps65090_fet_is_enabled(unsigned int fet_id)
> +{
> + u8 reg = 0;
> + int ret;
> +
> + if (tps65090_check_fet(fet_id))
> + return -1;
> + ret = tps65090_read(REG_FET1_CTRL + fet_id - 1, ®);
> + if (ret) {
> + debug("fail to read FET%u_CTRL register over I2C", fet_id);
> + return -2;
> + }
> +
> + return reg & FET_CTRL_ENFET;
> +}
> +
> +int tps65090_init(void)
> +{
> + puts("TPS65090 PMIC EC init\n");
> +
> + config.dev = board_get_cros_ec_dev();
> + if (!config.dev) {
> + debug("%s: no cros_ec device: cannot init tps65090\n",
> + __func__);
> + return -1;
> + }
> +
> + return 0;
> +}
> diff --git a/include/power/tps65090_pmic.h b/include/power/tps65090_pmic.h
> index dcf99c9..531751d 100644
> --- a/include/power/tps65090_pmic.h
> +++ b/include/power/tps65090_pmic.h
> @@ -18,6 +18,12 @@ enum {
> TPS65090_ST1_STATE_MASK = 0xf << TPS65090_ST1_STATE_SHIFT,
> };
>
> +/* FET errors */
> +enum {
> + FET_ERR_COMMS = -1, /* FET comms error */
> + FET_ERR_NOT_READY = -2, /* FET is not yet ready - retry */
> +};
> +
> /**
> * Enable FET
> *
> --
> 2.0.0.526.g5318336
>
> ___
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> U-Boot@lists.denx.de
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Able to test display on peach_pit(which needs tps65090) with these patches.
Also, crosec commands from u-boot prompt works as expected on peach_pit.
Tested-by: Ajay Kumar
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Re: [U-Boot] [PATCH 4/6] exynos5: Enable data cashe
cashe/cache in patch name On Mon, Jul 7, 2014 at 9:46 PM, Simon Glass wrote: > Things run faster when the data cache is enabled, so turn it on along with > the 'dcache' command. > > Signed-off-by: Simon Glass > --- > > include/configs/exynos5-dt.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h > index e36a031..4e316b9 100644 > --- a/include/configs/exynos5-dt.h > +++ b/include/configs/exynos5-dt.h > @@ -37,8 +37,8 @@ > #define CONFIG_TRACE_EARLY_ADDR0x5000 > > /* Keep L2 Cache Disabled */ > -#define CONFIG_SYS_DCACHE_OFF > #define CONFIG_SYS_CACHELINE_SIZE 64 > +#define CONFIG_CMD_CACHE > > /* Enable ACE acceleration for SHA1 and SHA256 */ > #define CONFIG_EXYNOS_ACE_SHA > -- > 2.0.0.526.g5318336 > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot Able to test display on peach_pit(which needs tps65090) with these patches. Also, crosec commands from u-boot prompt works as expected on peach_pit. Tested-by: Ajay Kumar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/6] spi: Support half-duplex mode in FDT decode
On Mon, Jul 7, 2014 at 9:46 PM, Simon Glass wrote: > This parameter should also be supported. > > Signed-off-by: Simon Glass > --- > > doc/device-tree-bindings/spi/spi-bus.txt | 2 ++ > drivers/spi/spi.c| 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/doc/device-tree-bindings/spi/spi-bus.txt > b/doc/device-tree-bindings/spi/spi-bus.txt > index 800dafe..5c8720a 100644 > --- a/doc/device-tree-bindings/spi/spi-bus.txt > +++ b/doc/device-tree-bindings/spi/spi-bus.txt > @@ -59,6 +59,8 @@ contain the following properties. >used for MOSI. Defaults to 1 if not present. > - spi-rx-bus-width - (optional) The bus width(number of data wires) that >used for MISO. Defaults to 1 if not present. > +- spi-half-duplex - (optional) Indicates that the SPI bus should wait for > + a header byte before reading data from the slave. > > Some SPI controllers and devices support Dual and Quad SPI transfer mode. > It allows data in SPI system transfered in 2 wires(DUAL) or 4 wires(QUAD). > diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c > index 7ddea9b..7d81fbd 100644 > --- a/drivers/spi/spi.c > +++ b/drivers/spi/spi.c > @@ -53,6 +53,8 @@ struct spi_slave *spi_base_setup_slave_fdt(const void > *blob, int busnum, > mode |= SPI_CPHA; > if (fdtdec_get_bool(blob, node, "spi-cs-high")) > mode |= SPI_CS_HIGH; > + if (fdtdec_get_bool(blob, node, "spi-half-duplex")) > + mode |= SPI_PREAMBLE; > return spi_setup_slave(busnum, cs, max_hz, mode); > } > #endif > -- > 2.0.0.526.g5318336 > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot Able to test display on peach_pit(which needs tps65090) with these patches. Also, crosec commands from u-boot prompt works as expected on peach_pit. Tested-by: Ajay Kumar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/6] exynos: spi: Fix calculation of SPI transaction start time
On Mon, Jul 7, 2014 at 9:46 PM, Simon Glass wrote:
> The SPI transaction delay is supposed to be measured from the end of one
> transaction to the start of the next. The code does not work that way, so
> fix it.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/spi/exynos_spi.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
> index c92276f..2969184 100644
> --- a/drivers/spi/exynos_spi.c
> +++ b/drivers/spi/exynos_spi.c
> @@ -428,10 +428,6 @@ void spi_cs_activate(struct spi_slave *slave)
> clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
> debug("Activate CS, bus %d\n", spi_slave->slave.bus);
> spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE;
> -
> - /* Remember time of this transaction so we can honour the bus delay */
> - if (spi_slave->bus->deactivate_delay_us)
> - spi_slave->last_transaction_us = timer_get_us();
> }
>
> /**
> @@ -445,6 +441,11 @@ void spi_cs_deactivate(struct spi_slave *slave)
> struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
>
> setbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
> +
> + /* Remember time of this transaction so we can honour the bus delay */
> + if (spi_slave->bus->deactivate_delay_us)
> + spi_slave->last_transaction_us = timer_get_us();
> +
> debug("Deactivate CS, bus %d\n", spi_slave->slave.bus);
> }
>
> --
> 2.0.0.526.g5318336
>
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
Able to test display on peach_pit(which needs tps65090) with these patches.
Also, crosec commands from u-boot prompt works as expected on peach_pit.
Tested-by: Ajay Kumar
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Re: [U-Boot] [PATCH 1/6] cros_ec: Fix two bugs in the SPI implementation
On Mon, Jul 7, 2014 at 9:46 PM, Simon Glass wrote:
> An incorrect message version is passed to the EC in some cases and the
> parameters of one function are switched.
>
> Fix these problems.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/misc/cros_ec_spi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c
> index 7df709c..015333f 100644
> --- a/drivers/misc/cros_ec_spi.c
> +++ b/drivers/misc/cros_ec_spi.c
> @@ -98,7 +98,7 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t
> cmd, int cmd_version,
> }
>
> out = dev->dout;
> - out[0] = cmd_version;
> + out[0] = EC_CMD_VERSION0 + cmd_version;
> out[1] = cmd;
> out[2] = (uint8_t)dout_len;
> memcpy(out + 3, dout, dout_len);
> @@ -165,7 +165,7 @@ int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const
> void *blob)
> */
> int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob)
> {
> - dev->spi = spi_setup_slave_fdt(blob, dev->parent_node, dev->node);
> + dev->spi = spi_setup_slave_fdt(blob, dev->node, dev->parent_node);
> if (!dev->spi) {
> debug("%s: Could not setup SPI slave\n", __func__);
> return -1;
> --
> 2.0.0.526.g5318336
>
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
Able to test display on peach_pit(which needs tps65090) with these patches.
Also, crosec commands from u-boot prompt works as expected on peach_pit.
Tested-by: Ajay Kumar
___
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[U-Boot] [PATCH V3 8/9] ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chip
This patch adds DT properties for fimd and the parade bridge chip
present on peach_pit. The panel supports 1366x768 resolution.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/dts/exynos5420-peach-pit.dts | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts
b/arch/arm/dts/exynos5420-peach-pit.dts
index 8d148af..3ed70a8 100644
--- a/arch/arm/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -63,6 +63,11 @@
reg = <0x20>;
compatible = "maxim,max98090-codec";
};
+
+ edp-lvds-bridge@48 {
+ compatible = "parade,ps8625";
+ reg = <0x48>;
+ };
};
sound@383 {
@@ -124,4 +129,29 @@
xhci@1240 {
samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
};
+
+ fimd@1440 {
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <1366>;
+ samsung,vl-row = <768>;
+ samsung,vl-width = <1366>;
+ samsung,vl-height = <768>;
+
+ samsung,vl-clkp;
+ samsung,vl-dp;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <32>;
+ samsung,vl-hbpd = <40>;
+ samsung,vl-hfpd = <40>;
+ samsung,vl-vspw = <6>;
+ samsung,vl-vbpd = <10>;
+ samsung,vl-vfpd = <12>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,winid = <3>;
+ samsung,interface-mode = <1>;
+ samsung,dp-enabled = <1>;
+ samsung,dual-lcd-enabled = <0>;
+ };
};
--
1.7.9.5
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[U-Boot] [PATCH V3 9/9] CONFIGS: peach-pit: Enable display for peach_pit board
Enable drivers for FIMD, DP and parade bridge chip. Signed-off-by: Ajay Kumar --- include/configs/peach-pit.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 76b8d7a..88c093f 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -22,4 +22,14 @@ #define CONFIG_SYS_PROMPT "Peach # " #define CONFIG_IDENT_STRING" for Peach" +#define CONFIG_VIDEO_PARADE + +/* Display */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_EXYNOS_FB +#define CONFIG_EXYNOS_DP +#define LCD_BPPLCD_COLOR16 +#endif + #endif /* __CONFIG_PEACH_PIT_H */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 6/9] ARM: exynos: Add missing declaration for gpio_direction_input
This patch adds missing declaration for gpio_direction_input
function, thereby helps in resolving compilation warnings.
Signed-off-by: Ajay Kumar
---
arch/arm/include/asm/arch-exynos/gpio.h |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h
index be5113f..8fb5c23 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1504,6 +1504,7 @@ static const struct gpio_name_num_table
exynos5420_gpio_table[] = {
void gpio_cfg_pin(int gpio, int cfg);
void gpio_set_pull(int gpio, int mode);
void gpio_set_drv(int gpio, int mode);
+int gpio_direction_input(unsigned gpio);
int gpio_direction_output(unsigned gpio, int value);
int gpio_set_value(unsigned gpio, int value);
int gpio_get_value(unsigned gpio);
--
1.7.9.5
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[U-Boot] [PATCH V3 7/9] exynos5420: add callbacks needed for exynos_fb driver
Add initialization code for peach_pit panel, parade bridge chip,
and backlight.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/include/asm/arch-exynos/system.h |3 +
board/samsung/smdk5420/smdk5420.c | 129 +++--
2 files changed, 50 insertions(+), 82 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/system.h
b/arch/arm/include/asm/arch-exynos/system.h
index 4968d3d..320763f 100644
--- a/arch/arm/include/asm/arch-exynos/system.h
+++ b/arch/arm/include/asm/arch-exynos/system.h
@@ -41,4 +41,7 @@ void set_usbhost_mode(unsigned int mode);
void set_system_display_ctrl(void);
int exynos_lcd_early_init(const void *blob);
+/* Initialize the Parade dP<->LVDS bridge if present */
+int parade_init(const void *blob);
+
#endif /* _EXYNOS4_SYSTEM_H */
diff --git a/board/samsung/smdk5420/smdk5420.c
b/board/samsung/smdk5420/smdk5420.c
index 183c522..270ee83 100644
--- a/board/samsung/smdk5420/smdk5420.c
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -10,11 +10,14 @@
#include
#include
#include
+#include
#include
#include
#include
#include
+#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -40,95 +43,57 @@ int exynos_init(void)
}
#ifdef CONFIG_LCD
-void cfg_lcd_gpio(void)
+static int has_edp_bridge(void)
{
- /* For Backlight */
- gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_OUTPUT);
- gpio_set_value(EXYNOS5420_GPIO_B20, 1);
+ int node;
+
+ node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_PARADE_PS8625);
- /* LCD power on */
- gpio_cfg_pin(EXYNOS5420_GPIO_X15, S5P_GPIO_OUTPUT);
- gpio_set_value(EXYNOS5420_GPIO_X15, 1);
+ /* No node for bridge in device tree. */
+ if (node <= 0)
+ return 0;
- /* Set Hotplug detect for DP */
- gpio_cfg_pin(EXYNOS5420_GPIO_X07, S5P_GPIO_FUNC(0x3));
+ /* Default is with bridge ic */
+ return 1;
}
-vidinfo_t panel_info = {
- .vl_freq= 60,
- .vl_col = 2560,
- .vl_row = 1600,
- .vl_width = 2560,
- .vl_height = 1600,
- .vl_clkp= CONFIG_SYS_LOW,
- .vl_hsp = CONFIG_SYS_LOW,
- .vl_vsp = CONFIG_SYS_LOW,
- .vl_dp = CONFIG_SYS_LOW,
- .vl_bpix= 4,/* LCD_BPP = 2^4, for output conosle on LCD */
-
- /* wDP panel timing infomation */
- .vl_hspw= 32,
- .vl_hbpd= 80,
- .vl_hfpd= 48,
-
- .vl_vspw= 6,
- .vl_vbpd= 37,
- .vl_vfpd= 3,
- .vl_cmd_allow_len = 0xf,
-
- .win_id = 3,
- .cfg_gpio = cfg_lcd_gpio,
- .backlight_on = NULL,
- .lcd_power_on = NULL,
- .reset_lcd = NULL,
- .dual_lcd_enabled = 0,
-
- .init_delay = 0,
- .power_on_delay = 0,
- .reset_delay= 0,
- .interface_mode = FIMD_RGB_INTERFACE,
- .dp_enabled = 1,
-};
-
-static struct edp_device_info edp_info = {
- .disp_info = {
- .h_res = 2560,
- .h_sync_width = 32,
- .h_back_porch = 80,
- .h_front_porch = 48,
- .v_res = 1600,
- .v_sync_width = 6,
- .v_back_porch = 37,
- .v_front_porch = 3,
- .v_sync_rate = 60,
- },
- .lt_info = {
- .lt_status = DP_LT_NONE,
- },
- .video_info = {
- .master_mode = 0,
- .bist_mode = DP_DISABLE,
- .bist_pattern = NO_PATTERN,
- .h_sync_polarity = 0,
- .v_sync_polarity = 0,
- .interlaced = 0,
- .color_space = COLOR_RGB,
- .dynamic_range = VESA,
- .ycbcr_coeff = COLOR_YCBCR601,
- .color_depth = COLOR_8,
- },
-};
-
-static struct exynos_dp_platform_data dp_platform_data = {
- .phy_enable = set_dp_phy_ctrl,
- .edp_dev_info = &edp_info,
-};
-
-void init_panel_info(vidinfo_t *vid)
+void exynos_lcd_power_on(void)
{
- vid->rgb_mode = MODE_RGB_P;
+ int ret;
+
+#ifdef CONFIG_POWER_TPS65090
+ ret = tps65090_init();
+ if (ret < 0) {
+ printf("%s: tps65090_init() failed\n", __func__);
+ return;
+ }
+
+ tps65090_fet_enable(6);
+#endif
+
+ mdelay(5);
+
+ /* TODO(ajaykumar...@samsung.com): Use device tree */
+ gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */
+ mdelay(10);
+ gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */
+ gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
+ gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
- exynos_set_dp_platform_data(&dp_platform_data);
+ if (has_edp_bridge())
+ if (parade_init(gd->fdt_blob))
+
[U-Boot] [PATCH V3 5/9] video: Add driver for Parade PS8625 dP to LVDS bridge
From: Vadim Bendebury
The initialization table comes from the "Illustration of I2C command
for initialing PS8625" document supplied by Parade.
Signed-off-by: Vadim Bendebury
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
drivers/video/Makefile |1 +
drivers/video/parade.c | 220
include/fdtdec.h |1 +
lib/fdtdec.c |1 +
4 files changed, 223 insertions(+)
create mode 100644 drivers/video/parade.c
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 945f35d..8618590 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -41,3 +41,4 @@ obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
obj-$(CONFIG_VIDEO_TEGRA) += tegra.o
obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
obj-$(CONFIG_FORMIKE) += formike.o
+obj-$(CONFIG_VIDEO_PARADE) += parade.o
diff --git a/drivers/video/parade.c b/drivers/video/parade.c
new file mode 100644
index 000..0f543f6
--- /dev/null
+++ b/drivers/video/parade.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * This file is a driver for Parade dP<->LVDS bridges. The original submission
+ * is for the ps8625 chip.
+ */
+#include
+#include
+#include
+#include
+
+/*
+ * Initialization of the chip is a process of writing certaing values into
+ * certain registers over i2c bus. The chip in fact responds to a range of
+ * addresses on the i2c bus, so for each written value three parameters are
+ * required: i2c address, register address and the actual value.
+ *
+ * The base address is derived from the device tree, only address offset is
+ * stored in the table below.
+ */
+/**
+ * struct reg_data() - data for a parade register write
+ *
+ * @addr_offoffset from the i2c base address for parade
+ * @reg_addrregister address to write
+ * @value value to be written
+ */
+struct reg_data {
+ uint8_t addr_off;
+ uint8_t reg;
+ uint8_t value;
+} _packed;
+
+#define END_OF_TABLE 0xff /* Ficticious offset */
+
+static const struct reg_data parade_values[] = {
+ {0x02, 0xa1, 0x01}, /* HPD low */
+/*
+ * SW setting
+ * [1:0] SW output 1.2V voltage is lower to 96%
+ */
+ {0x04, 0x14, 0x01},
+/*
+ * RCO SS setting
+ * [5:4] = b01 0.5%, b10 1%, b11 1.5%
+ */
+ {0x04, 0xe3, 0x20},
+ {0x04, 0xe2, 0x80}, /* [7] RCO SS enable */
+/*
+ * RPHY Setting
+ * [3:2] CDR tune wait cycle before
+ * measure for fine tune b00: 1us,
+ * 01: 0.5us, 10:2us, 11:4us.
+ */
+ {0x04, 0x8a, 0x0c},
+ {0x04, 0x89, 0x08}, /* [3] RFD always on */
+/*
+ * CTN lock in/out:
+ * 2ppm/8ppm. Lock out 2
+ * times.
+ */
+ {0x04, 0x71, 0x2d},
+/*
+ * 2.7G CDR settings
+ * NOF=40LSB for HBR CDR setting
+ */
+ {0x04, 0x7d, 0x07},
+ {0x04, 0x7b, 0x00}, /* [1:0] Fmin=+4bands */
+ {0x04, 0x7a, 0xfd}, /* [7:5] DCO_FTRNG=+-40% */
+/*
+ * 1.62G CDR settings
+ * [5:2]NOF=64LSB [1:0]DCO scale is 2/5
+ */
+ {0x04, 0xc0, 0x12},
+ {0x04, 0xc1, 0x92}, /* Gitune=-37% */
+ {0x04, 0xc2, 0x1c}, /* Fbstep=100% */
+ {0x04, 0x32, 0x80}, /* [7] LOS signal disable */
+/*
+ * RPIO Setting
+ * [7:4] LVDS driver bias current :
+ * 75% (250mV swing)
+ */
+ {0x04, 0x00, 0xb0},
+/*
+ * [7:6] Right-bar GPIO output strength is 8mA
+ */
+ {0x04, 0x15, 0x40},
+/* EQ Training State Machine Setting */
+ {0x04, 0x54, 0x10}, /* RCO calibration start */
+/* [4:0] MAX_LANE_COUNT set to one lane */
+ {0x01, 0x02, 0x81},
+/* [4:0] LANE_COUNT_SET set to one lane */
+ {0x01, 0x21, 0x81},
+ {0x00, 0x52, 0x20},
+ {0x00, 0xf1, 0x03}, /* HPD CP toggle enable */
+ {0x00, 0x62, 0x41},
+/* Counter number, add 1ms counter delay */
+ {0x00, 0xf6, 0x01},
+/*
+ * [6]PWM function control by
+ * DPCD0040f[7], default is PWM
+ * block always works.
+ */
+ {0x00, 0x77, 0x06},
+/*
+ * 04h Adjust VTotal tolerance to
+ * fix the 30Hz no display issue
+ */
+ {0x00, 0x4c, 0x04},
+/* DPCD00400='h00, Parade OUI = 'h001cf8 */
+ {0x01, 0xc0, 0x00},
+ {0x01, 0xc1, 0x1c}, /* DPCD00401='h1c */
+ {0x01, 0xc2, 0xf8}, /* DPCD00402='hf8 */
+/*
+ * DPCD403~408 = ASCII code
+ * D2SLV5='h4432534c5635
+ */
+ {0x01, 0xc3, 0x44},
+ {0x01, 0xc4, 0x32}, /* DPCD404 */
+ {0x01, 0xc5, 0x53}, /* DPCD405 */
+ {0x01, 0xc6, 0x4c}, /* DPCD406 */
+ {0x01, 0xc7,
[U-Boot] [PATCH V3 4/9] video: exynos_fimd: Add framework to disable FIMD sysmmu
On Exynos5420 and newer versions, the FIMD sysmmus are in
"on state" by default.
We have to disable them in order to make FIMD DMA work.
This patch adds the required framework to exynos_fimd driver,
and disables FIMD sysmmu on Exynos5420.
Signed-off-by: Ajay Kumar
---
arch/arm/dts/exynos54xx.dtsi | 10 ++
doc/device-tree-bindings/video/exynos-fb.txt |6
drivers/video/exynos_fimd.c | 43 ++
include/fdtdec.h |1 +
lib/fdtdec.c |1 +
5 files changed, 61 insertions(+)
diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi
index b9f8e0b..c21d798 100644
--- a/arch/arm/dts/exynos54xx.dtsi
+++ b/arch/arm/dts/exynos54xx.dtsi
@@ -113,6 +113,16 @@
status = "disabled";
};
+ fimdm0_sysmmu@0x1464 {
+ compatible = "samsung,sysmmu-v3.3";
+ reg = <0x1464 0x100>;
+ };
+
+ fimdm1_sysmmu@0x1468 {
+ compatible = "samsung,sysmmu-v3.3";
+ reg = <0x1468 0x100>;
+ };
+
fimd@1440 {
/* sysmmu is not used in U-Boot */
samsung,disable-sysmmu;
diff --git a/doc/device-tree-bindings/video/exynos-fb.txt
b/doc/device-tree-bindings/video/exynos-fb.txt
index bb7441c..dc4e44f 100644
--- a/doc/device-tree-bindings/video/exynos-fb.txt
+++ b/doc/device-tree-bindings/video/exynos-fb.txt
@@ -55,6 +55,12 @@ Board(panel specific):
samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)
samsung,sclk-div: parent_clock/source_clock ratio
samsung,dual-lcd-enabled: 1 if you support two LCD, else 0
+ samsung,disable-sysmmu: Define this if you want to disable FIMD sysmmu.
+ (needed for Exynos5420 and newer versions)
+ Add the required FIMD sysmmu nodes to be
+ disabled with compatible string
+ "samsung,sysmmu-v3.3", with a "reg" property
+ holding the register address of FIMD sysmmu.
Example:
SOC specific part:
diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
index cebbba7..f67fa81 100644
--- a/drivers/video/exynos_fimd.c
+++ b/drivers/video/exynos_fimd.c
@@ -251,6 +251,45 @@ void exynos_fimd_window_off(unsigned int win_id)
writel(cfg, &fimd_ctrl->winshmap);
}
+#ifdef CONFIG_OF_CONTROL
+/*
+* The reset value for FIMD SYSMMU register MMU_CTRL is 3
+* on Exynos5420 and newer versions.
+* This means FIMD SYSMMU is on by default on Exynos5420
+* and newer versions.
+* Since in u-boot we don't use SYSMMU, we should disable
+* those FIMD SYSMMU.
+* Note that there are 2 SYSMMU for FIMD: m0 and m1.
+* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3.
+* We disable both of them here.
+*/
+void exynos_fimd_disable_sysmmu(void)
+{
+ u32 *sysmmufimd;
+ unsigned int node;
+ int node_list[2];
+ int count;
+ int i;
+
+ count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd",
+ COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2);
+ for (i = 0; i < count; i++) {
+ node = node_list[i];
+ if (node <= 0) {
+ debug("Can't get device node for fimd sysmmu\n");
+ return;
+ }
+
+ sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
+ if (!sysmmufimd) {
+ debug("Can't get base address for sysmmu fimdm0");
+ return;
+ }
+
+ writel(0x0, sysmmufimd);
+ }
+}
+#endif
void exynos_fimd_lcd_init(vidinfo_t *vid)
{
@@ -268,6 +307,10 @@ void exynos_fimd_lcd_init(vidinfo_t *vid)
node, "reg");
if (fimd_ctrl == NULL)
debug("Can't get the FIMD base address\n");
+
+ if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
+ exynos_fimd_disable_sysmmu();
+
#else
fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd();
#endif
diff --git a/include/fdtdec.h b/include/fdtdec.h
index a7e6ee7..a583d68 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -94,6 +94,7 @@ enum fdt_compat_id {
COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */
COMPAT_TI_TPS65090, /* Texas Instrument TPS65090 */
COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */
+ COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */
COMPAT_COUNT,
};
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index aaa6620..64d2398 10
[U-Boot] [PATCH V3 3/9] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/cpu/armv7/exynos/clock.c | 83 +++--
arch/arm/cpu/armv7/exynos/exynos5_setup.h |2 +-
arch/arm/include/asm/arch-exynos/clk.h|1 +
3 files changed, 80 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 400d134..c8be39b 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r,
unsigned int k)
* VPLL_CON: MIDV [24:16]
* BPLL_CON: MIDV [25:16]: Exynos5
*/
- if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
+ if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
+ pllreg == SPLL)
mask = 0x3ff;
else
mask = 0x1ff;
@@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg)
r = readl(&clk->rpll_con0);
k = readl(&clk->rpll_con1);
break;
+ case SPLL:
+ r = readl(&clk->spll_con0);
+ break;
default:
printf("Unsupported PLL (%d)\n", pllreg);
return 0;
@@ -1027,6 +1031,40 @@ static unsigned long exynos5_get_lcd_clk(void)
return pclk;
}
+static unsigned long exynos5420_get_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long pclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+* CLK_SRC_DISP10
+* FIMD1_SEL [4]
+* 0: SCLK_RPLL
+* 1: SCLK_SPLL
+*/
+ sel = readl(&clk->src_disp10);
+ sel &= (1 << 4);
+
+ if (sel)
+ sclk = get_pll_clk(SPLL);
+ else
+ sclk = get_pll_clk(RPLL);
+
+ /*
+* CLK_DIV_DISP10
+* FIMD1_RATIO [3:0]
+*/
+ ratio = readl(&clk->div_disp10);
+ ratio = ratio & 0xf;
+
+ pclk = sclk / (ratio + 1);
+
+ return pclk;
+}
+
void exynos4_set_lcd_clk(void)
{
struct exynos4_clock *clk =
@@ -1131,6 +1169,33 @@ void exynos5_set_lcd_clk(void)
clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
}
+void exynos5420_set_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned int cfg;
+
+ /*
+* CLK_SRC_DISP10
+* FIMD1_SEL [4]
+* 0: SCLK_RPLL
+* 1: SCLK_SPLL
+*/
+ cfg = readl(&clk->src_disp10);
+ cfg &= ~(0x1 << 4);
+ cfg |= (0 << 4);
+ writel(cfg, &clk->src_disp10);
+
+ /*
+* CLK_DIV_DISP10
+* FIMD1_RATIO [3:0]
+*/
+ cfg = readl(&clk->div_disp10);
+ cfg &= ~(0xf << 0);
+ cfg |= (0 << 0);
+ writel(cfg, &clk->div_disp10);
+}
+
void exynos4_set_mipi_clk(void)
{
struct exynos4_clock *clk =
@@ -1602,16 +1667,24 @@ unsigned long get_lcd_clk(void)
{
if (cpu_is_exynos4())
return exynos4_get_lcd_clk();
- else
- return exynos5_get_lcd_clk();
+ else {
+ if (proid_is_exynos5420())
+ return exynos5420_get_lcd_clk();
+ else
+ return exynos5_get_lcd_clk();
+ }
}
void set_lcd_clk(void)
{
if (cpu_is_exynos4())
exynos4_set_lcd_clk();
- else
- exynos5_set_lcd_clk();
+ else {
+ if (proid_is_exynos5250())
+ exynos5_set_lcd_clk();
+ if (proid_is_exynos5420())
+ exynos5420_set_lcd_clk();
+ }
}
void set_mipi_clk(void)
diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
index 3242093..2eea48a 100644
--- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
+++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
@@ -783,7 +783,7 @@
#define CLK_SRC_TOP2_VAL 0x11101000
#define CLK_SRC_TOP3_VAL 0x
#define CLK_SRC_TOP4_VAL 0x0111
-#define CLK_SRC_TOP5_VAL 0x1100
+#define CLK_SRC_TOP5_VAL 0x1101
#define CLK_SRC_TOP6_VAL 0x0111
#define CLK_SRC_TOP7_VAL 0x00022200
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index ffbc07e..db24dc0 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -15,6 +15,7 @@
#define VPLL 4
#define BPLL 5
#define RPLL 6
+#define SPL
[U-Boot] [PATCH V3 2/9] arm: exynos: Add RPLL for Exynos5420
RPLL is needed to drive the LCD panel on Exynos5420 based boards.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/cpu/armv7/exynos/clock_init.h |3 +++
arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 +
2 files changed, 16 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h
b/arch/arm/cpu/armv7/exynos/clock_init.h
index a875d0b..fce502f 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init.h
+++ b/arch/arm/cpu/armv7/exynos/clock_init.h
@@ -75,6 +75,9 @@ struct mem_timings {
unsigned spll_mdiv;
unsigned spll_pdiv;
unsigned spll_sdiv;
+ unsigned rpll_mdiv;
+ unsigned rpll_pdiv;
+ unsigned rpll_sdiv;
unsigned pclk_cdrex_ratio;
unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
index 1d6977f..b6a9bc1 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
+++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
@@ -179,6 +179,10 @@ struct mem_timings mem_timings[] = {
.spll_mdiv = 0xc8,
.spll_pdiv = 0x3,
.spll_sdiv = 0x2,
+ /* RPLL @70.5Mhz */
+ .rpll_mdiv = 0x5E,
+ .rpll_pdiv = 0x2,
+ .rpll_sdiv = 0x4,
.direct_cmd_msr = {
0x00020018, 0x0003, 0x00010046, 0x0d70,
@@ -800,6 +804,7 @@ static void exynos5420_system_clock_init(void)
writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
+ writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);
setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
@@ -898,6 +903,14 @@ static void exynos5420_system_clock_init(void)
while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
;
+ /* Set RPLL */
+ writel(RPLL_CON2_VAL, &clk->rpll_con2);
+ writel(RPLL_CON1_VAL, &clk->rpll_con1);
+ val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv);
+ writel(val, &clk->rpll_con0);
+ while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0)
+ ;
+
writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
--
1.7.9.5
___
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[U-Boot] [PATCH V3 1/9] exynos_fb: Remove usage of static defines
Previously, we used to statically assign values for vl_col, vl_row and
vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.
Introducing the function exynos_lcd_early_init() would take care of this
assignment on the fly by parsing FIMD DT properties, thereby allowing us
to remove LCD_XRES and LCD_YRES from the main config file.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/include/asm/arch-exynos/system.h |1 +
board/samsung/common/board.c | 15 +++
drivers/video/exynos_fb.c | 17 +
include/configs/exynos5250-dt.h |2 --
include/configs/s5pc210_universal.h |3 ---
include/configs/trats.h |3 ---
include/configs/trats2.h |3 ---
7 files changed, 21 insertions(+), 23 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/system.h
b/arch/arm/include/asm/arch-exynos/system.h
index 7e2057c..4968d3d 100644
--- a/arch/arm/include/asm/arch-exynos/system.h
+++ b/arch/arm/include/asm/arch-exynos/system.h
@@ -39,5 +39,6 @@ struct exynos5_sysreg {
void set_usbhost_mode(unsigned int mode);
void set_system_display_ctrl(void);
+int exynos_lcd_early_init(const void *blob);
#endif /* _EXYNOS4_SYSTEM_H */
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 9dc7c83..1f6f0a0 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -148,6 +149,20 @@ int board_early_init_f(void)
board_i2c_init(gd->fdt_blob);
#endif
+#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_EXYNOS_FB)
+/*
+ * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
+ * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix, to reserve
+ * FB memory at a very early stage. So, we need to fill panel_info.vl_col,
+ * panel_info.vl_row and panel_info.vl_bpix before lcd_setmem() is called.
+ */
+ err = exynos_lcd_early_init(gd->fdt_blob);
+ if (err) {
+ debug("LCD early init failed\n");
+ return err;
+ }
+#endif
+
return exynos_early_init_f();
}
#endif
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
index e1e0d80..bc478a9 100644
--- a/drivers/video/exynos_fb.c
+++ b/drivers/video/exynos_fb.c
@@ -27,17 +27,12 @@ DECLARE_GLOBAL_DATA_PTR;
static unsigned int panel_width, panel_height;
-/*
- * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
- * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix to reserve
- * FB memory at a very early stage, i.e even before exynos_fimd_parse_dt()
- * is called. So, we are forced to statically assign it.
- */
#ifdef CONFIG_OF_CONTROL
vidinfo_t panel_info = {
- .vl_col = LCD_XRES,
- .vl_row = LCD_YRES,
- .vl_bpix = LCD_COLOR16,
+ /* Insert a value here so that we don't end up in the BSS
+* Reference: drivers/video/tegra.c
+*/
+ .vl_col = -1,
};
#endif
@@ -141,7 +136,7 @@ static void lcd_panel_on(vidinfo_t *vid)
}
#ifdef CONFIG_OF_CONTROL
-int exynos_fimd_parse_dt(const void *blob)
+int exynos_lcd_early_init(const void *blob)
{
unsigned int node;
node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD);
@@ -286,8 +281,6 @@ void lcd_ctrl_init(void *lcdbase)
set_lcd_clk();
#ifdef CONFIG_OF_CONTROL
- if (exynos_fimd_parse_dt(gd->fdt_blob))
- debug("Can't get proper panel info\n");
#ifdef CONFIG_EXYNOS_MIPI_DSIM
exynos_init_dsim_platform_data(&panel_info);
#endif
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 74e72a5..c24984b 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -61,8 +61,6 @@
#ifdef CONFIG_LCD
#define CONFIG_EXYNOS_FB
#define CONFIG_EXYNOS_DP
-#define LCD_XRES 2560
-#define LCD_YRES 1600
#define LCD_BPPLCD_COLOR16
#endif
diff --git a/include/configs/s5pc210_universal.h
b/include/configs/s5pc210_universal.h
index eb046cd..20985da 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -247,7 +247,4 @@ int universal_spi_read(void);
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-#define LCD_XRES 480
-#define LCD_YRES 800
-
#endif /* __CONFIG_H */
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 90f1962..35c1feb 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -261,7 +261,4 @@
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-#define LCD_XRES 720
-#define LCD_YRES 1280
-
#endif /* __CONFIG_H */
diff --git a/include/configs/trats2.h b/inc
[U-Boot] [PATCH V3 0/9] peach_pit: Add support for FIMD, DP and parade chip
Patchset V1: https://www.mail-archive.com/u-boot@lists.denx.de/msg140596.html Patchset V2: https://www.mail-archive.com/u-boot@lists.denx.de/msg141203.html Changes from V1: [PATCH V2 3/10] : Don't mix cpu_is and proid_isas per Minkyu's suggestion. Also, incorporate Simon's suggestion of not using else. [PATCH V2 4/10] : For FIMD SYSMMU DT, use same compatible string as kernel. [TEST_ONLY V2 6/10]: Make this patch TEST_ONLY Changes from V2: [PATCH V3 5/9] : Use SPDX tags to define the license for the file: parade.c Removed TEST_ONLY patches. Ajay Kumar (8): [PATCH V3 1/9] exynos_fb: Remove usage of static defines [PATCH V3 2/9] arm: exynos: Add RPLL for Exynos5420 [PATCH V3 3/9] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 [PATCH V3 4/9] video: exynos_fimd: Add framework to disable FIMD sysmmu [PATCH V3 6/9] ARM: exynos: Add missing declaration for gpio_direction_input [PATCH V3 7/9] exynos5420: add callbacks needed for exynos_fb driver [PATCH V3 8/9] ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chip [PATCH V3 9/9] CONFIGS: peach-pit: Enable display for peach_pit board Vadim Bendebury (1): [PATCH V3 5/9] video: Add driver for Parade PS8625 dP to LVDS bridge arch/arm/cpu/armv7/exynos/clock.c | 83 - arch/arm/cpu/armv7/exynos/clock_init.h |3 + arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 ++ arch/arm/cpu/armv7/exynos/exynos5_setup.h |2 +- arch/arm/dts/exynos5420-peach-pit.dts | 30 arch/arm/dts/exynos54xx.dtsi | 10 ++ arch/arm/include/asm/arch-exynos/clk.h |1 + arch/arm/include/asm/arch-exynos/gpio.h|1 + arch/arm/include/asm/arch-exynos/system.h |4 + board/samsung/common/board.c | 15 ++ board/samsung/smdk5420/smdk5420.c | 129 +- doc/device-tree-bindings/video/exynos-fb.txt |6 + drivers/video/Makefile |1 + drivers/video/exynos_fb.c | 17 +- drivers/video/exynos_fimd.c| 43 + drivers/video/parade.c | 220 include/configs/exynos5250-dt.h|2 - include/configs/peach-pit.h| 10 ++ include/configs/s5pc210_universal.h|3 - include/configs/trats.h|3 - include/configs/trats2.h |3 - include/fdtdec.h |2 + lib/fdtdec.c |2 + 23 files changed, 492 insertions(+), 111 deletions(-) create mode 100644 drivers/video/parade.c -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [TEST_ONLY V2 10/10] Pit WIP
On Thu, Jun 26, 2014 at 4:19 PM, Wolfgang Denk wrote: > Dear Ajay kumar, > > In message > you > wrote: >> >> > In message <1403769668-2026-11-git-send-email-ajaykumar...@samsung.com> >> > you wrote: >> >> WIP patch to enable cros-ec on peach_pit. >> This Entire patch is a TEST_ONLY since it is still WIP(Work In Progress). >> That would mean somebody else is already working on it, but he/she hasn't >> sent >> that patchset yet, and till that comes up in the mailing list, this WIP patch >> can be used for testing the dependent patches. >> So, this would not be merged into the tree, but I thought its better to send >> it with a TEST_ONLY tag, so that maintainers can test this patchset. > > I don't think this is an excuse for cryptic or missing description of > what this is about. > > If you post something on the mailing list, then please make sure > everybody can understand it. If the message is not intended to public > audience, then don't post it here and use some other, more private > form of communication. I did mention about this in the cover letter. Still, I will make sure I elaborate more from the next time. Thanks and regards, Ajay Kumar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [TEST_ONLY V2 10/10] Pit WIP
Hi Denk,
On Thu, Jun 26, 2014 at 2:16 PM, Wolfgang Denk wrote:
> Dear Ajay Kumar,
>
> In message <1403769668-2026-11-git-send-email-ajaykumar...@samsung.com> you
> wrote:
>> WIP patch to enable cros-ec on peach_pit.
This Entire patch is a TEST_ONLY since it is still WIP(Work In Progress).
That would mean somebody else is already working on it, but he/she hasn't sent
that patchset yet, and till that comes up in the mailing list, this WIP patch
can be used for testing the dependent patches.
So, this would not be merged into the tree, but I thought its better to send
it with a TEST_ONLY tag, so that maintainers can test this patchset.
Regards,
Ajay Kumar
> Do you think anybody would be able to figure out what this is supposed
> to mean? I can't...
>
>> @@ -0,0 +1,212 @@
>> +/*
>> + * Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
>> + * Use of this source code is governed by a BSD-style license that can be
>> + * found in the LICENSE file.
>> + *
>> + * Alternatively, this software may be distributed under the terms of the
>> + * GNU General Public License ("GPL") version 2 as published by the Free
>> + * Software Foundation.
>> + */
>
> Please use SPDX license tags, and make sure to use GPL-2.0+ rather
> than GPL-2.0
>
>> diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
>> index c92276f..2969184 100644
>> --- a/drivers/spi/exynos_spi.c
>> +++ b/drivers/spi/exynos_spi.c
>> @@ -428,10 +428,6 @@ void spi_cs_activate(struct spi_slave *slave)
>> clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
>> debug("Activate CS, bus %d\n", spi_slave->slave.bus);
>> spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE;
>> -
>> - /* Remember time of this transaction so we can honour the bus delay */
>> - if (spi_slave->bus->deactivate_delay_us)
>> - spi_slave->last_transaction_us = timer_get_us();
>> }
>>
>> /**
>> @@ -445,6 +441,11 @@ void spi_cs_deactivate(struct spi_slave *slave)
>> struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
>>
>> setbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
>> +
>> + /* Remember time of this transaction so we can honour the bus delay */
>> + if (spi_slave->bus->deactivate_delay_us)
>> + spi_slave->last_transaction_us = timer_get_us();
>> +
>> debug("Deactivate CS, bus %d\n", spi_slave->slave.bus);
>> }
>
> Is this really a related change, or shoudl that go into a separate
> commit?
>
>> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
>> index 7ddea9b..7d81fbd 100644
>> --- a/drivers/spi/spi.c
>> +++ b/drivers/spi/spi.c
>> @@ -53,6 +53,8 @@ struct spi_slave *spi_base_setup_slave_fdt(const void
>> *blob, int busnum,
>> mode |= SPI_CPHA;
>> if (fdtdec_get_bool(blob, node, "spi-cs-high"))
>> mode |= SPI_CS_HIGH;
>> + if (fdtdec_get_bool(blob, node, "spi-half-duplex"))
>> + mode |= SPI_PREAMBLE;
>> return spi_setup_slave(busnum, cs, max_hz, mode);
>
> Ditto?
>
>> diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h
>> index e36a031..4e316b9 100644
>> --- a/include/configs/exynos5-dt.h
>> +++ b/include/configs/exynos5-dt.h
>> @@ -37,8 +37,8 @@
>> #define CONFIG_TRACE_EARLY_ADDR 0x5000
>>
>> /* Keep L2 Cache Disabled */
>> -#define CONFIG_SYS_DCACHE_OFF
>> #define CONFIG_SYS_CACHELINE_SIZE64
>> +#define CONFIG_CMD_CACHE
>
> Ditto?
>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
> Politics: A strife of interests masquerading as a contest of
> principles. The conduct of public affairs for private advantage.
> - Ambrose Bierce
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
___
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[U-Boot] [TEST_ONLY V2 10/10] Pit WIP
WIP patch to enable cros-ec on peach_pit.
Signed-off-by: Simon Glass
---
drivers/misc/cros_ec_spi.c| 4 +-
drivers/power/pmic/Makefile | 3 +-
drivers/power/pmic/pmic_tps65090_ec.c | 212 ++
drivers/spi/exynos_spi.c | 9 +-
drivers/spi/spi.c | 2 +
include/configs/exynos5-dt.h | 2 +-
include/configs/peach-pit.h | 2 +
include/power/tps65090_pmic.h | 6 +
8 files changed, 232 insertions(+), 8 deletions(-)
create mode 100644 drivers/power/pmic/pmic_tps65090_ec.c
diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c
index 7df709c..015333f 100644
--- a/drivers/misc/cros_ec_spi.c
+++ b/drivers/misc/cros_ec_spi.c
@@ -98,7 +98,7 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd,
int cmd_version,
}
out = dev->dout;
- out[0] = cmd_version;
+ out[0] = EC_CMD_VERSION0 + cmd_version;
out[1] = cmd;
out[2] = (uint8_t)dout_len;
memcpy(out + 3, dout, dout_len);
@@ -165,7 +165,7 @@ int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const
void *blob)
*/
int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob)
{
- dev->spi = spi_setup_slave_fdt(blob, dev->parent_node, dev->node);
+ dev->spi = spi_setup_slave_fdt(blob, dev->node, dev->parent_node);
if (!dev->spi) {
debug("%s: Could not setup SPI slave\n", __func__);
return -1;
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index a472f61..e7b07eb 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -11,7 +11,8 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
-obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o
+obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o
+obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o
obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
diff --git a/drivers/power/pmic/pmic_tps65090_ec.c
b/drivers/power/pmic/pmic_tps65090_ec.c
new file mode 100644
index 000..93b7923
--- /dev/null
+++ b/drivers/power/pmic/pmic_tps65090_ec.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TPS65090_ADDR 0x48
+
+static struct tps65090 {
+ struct cros_ec_dev *dev;/* The CROS_EC device */
+} config;
+
+/* TPS65090 register addresses */
+enum {
+ REG_FET1_CTRL = 0x0f,
+ REG_FET2_CTRL,
+ REG_FET3_CTRL,
+ REG_FET4_CTRL,
+ REG_FET5_CTRL,
+ REG_FET6_CTRL,
+ REG_FET7_CTRL,
+ TPS65090_NUM_REGS,
+};
+
+enum {
+ MAX_FET_NUM = 7,
+ MAX_CTRL_READ_TRIES = 5,
+
+ /* TPS65090 FET_CTRL register values */
+ FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */
+ FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */
+ FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */
+ FET_CTRL_ADENFET= 1 << 1, /* Enable output auto discharge */
+ FET_CTRL_ENFET = 1 << 0, /* Enable FET */
+};
+
+/**
+ * tps65090_read - read a byte from tps6090
+ *
+ * @param reg The register address to read from.
+ * @param val We'll return value value read here.
+ * @return 0 if ok; error if EC returns failure.
+ */
+static int tps65090_read(u32 reg, u8 *val)
+{
+ return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1,
+ val, 1, true);
+}
+
+/**
+ * tps65090_write - write a byte to tps6090
+ *
+ * @param reg The register address to write to.
+ * @param val The value to write.
+ * @return 0 if ok; error if EC returns failure.
+ */
+static int tps65090_write(u32 reg, u8 val)
+{
+ return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1,
+ &val, 1, false);
+}
+
+/**
+ * Checks for a valid FET number
+ *
+ * @param fet_id FET number to check
+ * @return 0 if ok, -1 if FET value is out of range
+ */
+static int tps65090_check_fet(unsigned int fet_id)
+{
+ if (fet_id == 0 || fet_id > MAX_FET_NUM) {
+ debug("parameter fet_id is out of range, %u not in 1 ~ %u\n",
+ fet_id, MAX_FET_NUM);
+ return -1;
+ }
+
+ return 0;
+}
+
+/**
+ * Set the power state for a FET
+ *
+ * @param fet_id
[U-Boot] [PATCH V2 07/10] exynos5420: add callbacks needed for exynos_fb driver
Add initialization code for peach_pit panel, parade bridge chip,
and backlight.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/include/asm/arch-exynos/system.h | 3 +
board/samsung/smdk5420/smdk5420.c | 129 +++---
2 files changed, 50 insertions(+), 82 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/system.h
b/arch/arm/include/asm/arch-exynos/system.h
index 4968d3d..320763f 100644
--- a/arch/arm/include/asm/arch-exynos/system.h
+++ b/arch/arm/include/asm/arch-exynos/system.h
@@ -41,4 +41,7 @@ void set_usbhost_mode(unsigned int mode);
void set_system_display_ctrl(void);
int exynos_lcd_early_init(const void *blob);
+/* Initialize the Parade dP<->LVDS bridge if present */
+int parade_init(const void *blob);
+
#endif /* _EXYNOS4_SYSTEM_H */
diff --git a/board/samsung/smdk5420/smdk5420.c
b/board/samsung/smdk5420/smdk5420.c
index 183c522..270ee83 100644
--- a/board/samsung/smdk5420/smdk5420.c
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -10,11 +10,14 @@
#include
#include
#include
+#include
#include
#include
#include
#include
+#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -40,95 +43,57 @@ int exynos_init(void)
}
#ifdef CONFIG_LCD
-void cfg_lcd_gpio(void)
+static int has_edp_bridge(void)
{
- /* For Backlight */
- gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_OUTPUT);
- gpio_set_value(EXYNOS5420_GPIO_B20, 1);
+ int node;
+
+ node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_PARADE_PS8625);
- /* LCD power on */
- gpio_cfg_pin(EXYNOS5420_GPIO_X15, S5P_GPIO_OUTPUT);
- gpio_set_value(EXYNOS5420_GPIO_X15, 1);
+ /* No node for bridge in device tree. */
+ if (node <= 0)
+ return 0;
- /* Set Hotplug detect for DP */
- gpio_cfg_pin(EXYNOS5420_GPIO_X07, S5P_GPIO_FUNC(0x3));
+ /* Default is with bridge ic */
+ return 1;
}
-vidinfo_t panel_info = {
- .vl_freq= 60,
- .vl_col = 2560,
- .vl_row = 1600,
- .vl_width = 2560,
- .vl_height = 1600,
- .vl_clkp= CONFIG_SYS_LOW,
- .vl_hsp = CONFIG_SYS_LOW,
- .vl_vsp = CONFIG_SYS_LOW,
- .vl_dp = CONFIG_SYS_LOW,
- .vl_bpix= 4,/* LCD_BPP = 2^4, for output conosle on LCD */
-
- /* wDP panel timing infomation */
- .vl_hspw= 32,
- .vl_hbpd= 80,
- .vl_hfpd= 48,
-
- .vl_vspw= 6,
- .vl_vbpd= 37,
- .vl_vfpd= 3,
- .vl_cmd_allow_len = 0xf,
-
- .win_id = 3,
- .cfg_gpio = cfg_lcd_gpio,
- .backlight_on = NULL,
- .lcd_power_on = NULL,
- .reset_lcd = NULL,
- .dual_lcd_enabled = 0,
-
- .init_delay = 0,
- .power_on_delay = 0,
- .reset_delay= 0,
- .interface_mode = FIMD_RGB_INTERFACE,
- .dp_enabled = 1,
-};
-
-static struct edp_device_info edp_info = {
- .disp_info = {
- .h_res = 2560,
- .h_sync_width = 32,
- .h_back_porch = 80,
- .h_front_porch = 48,
- .v_res = 1600,
- .v_sync_width = 6,
- .v_back_porch = 37,
- .v_front_porch = 3,
- .v_sync_rate = 60,
- },
- .lt_info = {
- .lt_status = DP_LT_NONE,
- },
- .video_info = {
- .master_mode = 0,
- .bist_mode = DP_DISABLE,
- .bist_pattern = NO_PATTERN,
- .h_sync_polarity = 0,
- .v_sync_polarity = 0,
- .interlaced = 0,
- .color_space = COLOR_RGB,
- .dynamic_range = VESA,
- .ycbcr_coeff = COLOR_YCBCR601,
- .color_depth = COLOR_8,
- },
-};
-
-static struct exynos_dp_platform_data dp_platform_data = {
- .phy_enable = set_dp_phy_ctrl,
- .edp_dev_info = &edp_info,
-};
-
-void init_panel_info(vidinfo_t *vid)
+void exynos_lcd_power_on(void)
{
- vid->rgb_mode = MODE_RGB_P;
+ int ret;
+
+#ifdef CONFIG_POWER_TPS65090
+ ret = tps65090_init();
+ if (ret < 0) {
+ printf("%s: tps65090_init() failed\n", __func__);
+ return;
+ }
+
+ tps65090_fet_enable(6);
+#endif
+
+ mdelay(5);
+
+ /* TODO(ajaykumar...@samsung.com): Use device tree */
+ gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */
+ mdelay(10);
+ gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */
+ gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
+ gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
- exynos_set_dp_platform_data(&dp_platform_data);
+ if (has_edp_bridge())
+ if (parade_init(gd->fdt_blob))
+
[U-Boot] [PATCH V2 04/10] video: exynos_fimd: Add framework to disable FIMD sysmmu
On Exynos5420 and newer versions, the FIMD sysmmus are in
"on state" by default.
We have to disable them in order to make FIMD DMA work.
This patch adds the required framework to exynos_fimd driver,
and disables FIMD sysmmu on Exynos5420.
Signed-off-by: Ajay Kumar
---
arch/arm/dts/exynos54xx.dtsi | 10 +++
doc/device-tree-bindings/video/exynos-fb.txt | 6
drivers/video/exynos_fimd.c | 43
include/fdtdec.h | 1 +
lib/fdtdec.c | 1 +
5 files changed, 61 insertions(+)
diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi
index b9f8e0b..c21d798 100644
--- a/arch/arm/dts/exynos54xx.dtsi
+++ b/arch/arm/dts/exynos54xx.dtsi
@@ -113,6 +113,16 @@
status = "disabled";
};
+ fimdm0_sysmmu@0x1464 {
+ compatible = "samsung,sysmmu-v3.3";
+ reg = <0x1464 0x100>;
+ };
+
+ fimdm1_sysmmu@0x1468 {
+ compatible = "samsung,sysmmu-v3.3";
+ reg = <0x1468 0x100>;
+ };
+
fimd@1440 {
/* sysmmu is not used in U-Boot */
samsung,disable-sysmmu;
diff --git a/doc/device-tree-bindings/video/exynos-fb.txt
b/doc/device-tree-bindings/video/exynos-fb.txt
index bb7441c..dc4e44f 100644
--- a/doc/device-tree-bindings/video/exynos-fb.txt
+++ b/doc/device-tree-bindings/video/exynos-fb.txt
@@ -55,6 +55,12 @@ Board(panel specific):
samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)
samsung,sclk-div: parent_clock/source_clock ratio
samsung,dual-lcd-enabled: 1 if you support two LCD, else 0
+ samsung,disable-sysmmu: Define this if you want to disable FIMD sysmmu.
+ (needed for Exynos5420 and newer versions)
+ Add the required FIMD sysmmu nodes to be
+ disabled with compatible string
+ "samsung,sysmmu-v3.3", with a "reg" property
+ holding the register address of FIMD sysmmu.
Example:
SOC specific part:
diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
index cebbba7..f67fa81 100644
--- a/drivers/video/exynos_fimd.c
+++ b/drivers/video/exynos_fimd.c
@@ -251,6 +251,45 @@ void exynos_fimd_window_off(unsigned int win_id)
writel(cfg, &fimd_ctrl->winshmap);
}
+#ifdef CONFIG_OF_CONTROL
+/*
+* The reset value for FIMD SYSMMU register MMU_CTRL is 3
+* on Exynos5420 and newer versions.
+* This means FIMD SYSMMU is on by default on Exynos5420
+* and newer versions.
+* Since in u-boot we don't use SYSMMU, we should disable
+* those FIMD SYSMMU.
+* Note that there are 2 SYSMMU for FIMD: m0 and m1.
+* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3.
+* We disable both of them here.
+*/
+void exynos_fimd_disable_sysmmu(void)
+{
+ u32 *sysmmufimd;
+ unsigned int node;
+ int node_list[2];
+ int count;
+ int i;
+
+ count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd",
+ COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2);
+ for (i = 0; i < count; i++) {
+ node = node_list[i];
+ if (node <= 0) {
+ debug("Can't get device node for fimd sysmmu\n");
+ return;
+ }
+
+ sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
+ if (!sysmmufimd) {
+ debug("Can't get base address for sysmmu fimdm0");
+ return;
+ }
+
+ writel(0x0, sysmmufimd);
+ }
+}
+#endif
void exynos_fimd_lcd_init(vidinfo_t *vid)
{
@@ -268,6 +307,10 @@ void exynos_fimd_lcd_init(vidinfo_t *vid)
node, "reg");
if (fimd_ctrl == NULL)
debug("Can't get the FIMD base address\n");
+
+ if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
+ exynos_fimd_disable_sysmmu();
+
#else
fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd();
#endif
diff --git a/include/fdtdec.h b/include/fdtdec.h
index a7e6ee7..a583d68 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -94,6 +94,7 @@ enum fdt_compat_id {
COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */
COMPAT_TI_TPS65090, /* Texas Instrument TPS65090 */
COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */
+ COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */
COMPAT_COUNT,
};
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 13d3d2f..1ccfb39 100644
--- a/l
[U-Boot] [PATCH V2 03/10] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/cpu/armv7/exynos/clock.c | 83 +--
arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +-
arch/arm/include/asm/arch-exynos/clk.h| 1 +
3 files changed, 80 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 400d134..7558eff 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r,
unsigned int k)
* VPLL_CON: MIDV [24:16]
* BPLL_CON: MIDV [25:16]: Exynos5
*/
- if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
+ if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
+ pllreg == SPLL)
mask = 0x3ff;
else
mask = 0x1ff;
@@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg)
r = readl(&clk->rpll_con0);
k = readl(&clk->rpll_con1);
break;
+ case SPLL:
+ r = readl(&clk->spll_con0);
+ break;
default:
printf("Unsupported PLL (%d)\n", pllreg);
return 0;
@@ -1027,6 +1031,40 @@ static unsigned long exynos5_get_lcd_clk(void)
return pclk;
}
+static unsigned long exynos5420_get_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long pclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+* CLK_SRC_DISP10
+* FIMD1_SEL [4]
+* 0: SCLK_RPLL
+* 1: SCLK_SPLL
+*/
+ sel = readl(&clk->src_disp10);
+ sel &= (1 << 4);
+
+ if (sel)
+ sclk = get_pll_clk(SPLL);
+ else
+ sclk = get_pll_clk(RPLL);
+
+ /*
+* CLK_DIV_DISP10
+* FIMD1_RATIO [3:0]
+*/
+ ratio = readl(&clk->div_disp10);
+ ratio = ratio & 0xf;
+
+ pclk = sclk / (ratio + 1);
+
+ return pclk;
+}
+
void exynos4_set_lcd_clk(void)
{
struct exynos4_clock *clk =
@@ -1131,6 +1169,33 @@ void exynos5_set_lcd_clk(void)
clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
}
+void exynos5420_set_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned int cfg;
+
+ /*
+* CLK_SRC_DISP10
+* FIMD1_SEL [4]
+* 0: SCLK_RPLL
+* 1: SCLK_SPLL
+*/
+ cfg = readl(&clk->src_disp10);
+ cfg &= ~(0x1 << 4);
+ cfg |= (0 << 4);
+ writel(cfg, &clk->src_disp10);
+
+ /*
+* CLK_DIV_DISP10
+* FIMD1_RATIO [3:0]
+*/
+ cfg = readl(&clk->div_disp10);
+ cfg &= ~(0xf << 0);
+ cfg |= (0 << 0);
+ writel(cfg, &clk->div_disp10);
+}
+
void exynos4_set_mipi_clk(void)
{
struct exynos4_clock *clk =
@@ -1602,16 +1667,24 @@ unsigned long get_lcd_clk(void)
{
if (cpu_is_exynos4())
return exynos4_get_lcd_clk();
- else
- return exynos5_get_lcd_clk();
+ else {
+ if (proid_is_exynos5420())
+ return exynos5420_get_lcd_clk();
+ else
+ return exynos5_get_lcd_clk();
+ }
}
void set_lcd_clk(void)
{
if (cpu_is_exynos4())
exynos4_set_lcd_clk();
- else
- exynos5_set_lcd_clk();
+ else {
+ if (proid_is_exynos5250())
+ exynos5_set_lcd_clk();
+ if (proid_is_exynos5420())
+ exynos5420_set_lcd_clk();
+ }
}
void set_mipi_clk(void)
diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
index 3242093..2eea48a 100644
--- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
+++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
@@ -783,7 +783,7 @@
#define CLK_SRC_TOP2_VAL 0x11101000
#define CLK_SRC_TOP3_VAL 0x
#define CLK_SRC_TOP4_VAL 0x0111
-#define CLK_SRC_TOP5_VAL 0x1100
+#define CLK_SRC_TOP5_VAL 0x1101
#define CLK_SRC_TOP6_VAL 0x0111
#define CLK_SRC_TOP7_VAL 0x00022200
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index ffbc07e..db24dc0 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -15,6 +15,7 @@
#define VPLL 4
#define BPLL 5
#define RPLL 6
+#define SPL
[U-Boot] [PATCH V2 09/10] CONFIGS: peach-pit: Enable display for peach_pit board
Enable drivers for FIMD, DP and parade bridge chip. Signed-off-by: Ajay Kumar --- include/configs/peach-pit.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 76b8d7a..88c093f 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -22,4 +22,14 @@ #define CONFIG_SYS_PROMPT "Peach # " #define CONFIG_IDENT_STRING" for Peach" +#define CONFIG_VIDEO_PARADE + +/* Display */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_EXYNOS_FB +#define CONFIG_EXYNOS_DP +#define LCD_BPPLCD_COLOR16 +#endif + #endif /* __CONFIG_PEACH_PIT_H */ -- 1.8.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 02/10] arm: exynos: Add RPLL for Exynos5420
RPLL is needed to drive the LCD panel on Exynos5420 based boards.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/cpu/armv7/exynos/clock_init.h | 3 +++
arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 +
2 files changed, 16 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h
b/arch/arm/cpu/armv7/exynos/clock_init.h
index a875d0b..fce502f 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init.h
+++ b/arch/arm/cpu/armv7/exynos/clock_init.h
@@ -75,6 +75,9 @@ struct mem_timings {
unsigned spll_mdiv;
unsigned spll_pdiv;
unsigned spll_sdiv;
+ unsigned rpll_mdiv;
+ unsigned rpll_pdiv;
+ unsigned rpll_sdiv;
unsigned pclk_cdrex_ratio;
unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
index 1d6977f..b6a9bc1 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
+++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
@@ -179,6 +179,10 @@ struct mem_timings mem_timings[] = {
.spll_mdiv = 0xc8,
.spll_pdiv = 0x3,
.spll_sdiv = 0x2,
+ /* RPLL @70.5Mhz */
+ .rpll_mdiv = 0x5E,
+ .rpll_pdiv = 0x2,
+ .rpll_sdiv = 0x4,
.direct_cmd_msr = {
0x00020018, 0x0003, 0x00010046, 0x0d70,
@@ -800,6 +804,7 @@ static void exynos5420_system_clock_init(void)
writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
+ writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);
setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
@@ -898,6 +903,14 @@ static void exynos5420_system_clock_init(void)
while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
;
+ /* Set RPLL */
+ writel(RPLL_CON2_VAL, &clk->rpll_con2);
+ writel(RPLL_CON1_VAL, &clk->rpll_con1);
+ val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv);
+ writel(val, &clk->rpll_con0);
+ while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0)
+ ;
+
writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
--
1.8.1.2
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[U-Boot] [PATCH V2 05/10] video: Add driver for Parade PS8625 dP to LVDS bridge
From: Vadim Bendebury
The initialization table comes from the "Illustration of I2C command
for initialing PS8625" document supplied by Parade.
Signed-off-by: Vadim Bendebury
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
drivers/video/Makefile | 1 +
drivers/video/parade.c | 220 +
include/fdtdec.h | 1 +
lib/fdtdec.c | 1 +
4 files changed, 223 insertions(+)
create mode 100644 drivers/video/parade.c
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 945f35d..8618590 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -41,3 +41,4 @@ obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
obj-$(CONFIG_VIDEO_TEGRA) += tegra.o
obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
obj-$(CONFIG_FORMIKE) += formike.o
+obj-$(CONFIG_VIDEO_PARADE) += parade.o
diff --git a/drivers/video/parade.c b/drivers/video/parade.c
new file mode 100644
index 000..36e5d80
--- /dev/null
+++ b/drivers/video/parade.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * This file is a driver for Parade dP<->LVDS bridges. The original submission
+ * is for the ps8625 chip.
+ */
+#include
+#include
+#include
+#include
+
+/*
+ * Initialization of the chip is a process of writing certaing values into
+ * certain registers over i2c bus. The chip in fact responds to a range of
+ * addresses on the i2c bus, so for each written value three parameters are
+ * required: i2c address, register address and the actual value.
+ *
+ * The base address is derived from the device tree, only address offset is
+ * stored in the table below.
+ */
+/**
+ * struct reg_data() - data for a parade register write
+ *
+ * @addr_offoffset from the i2c base address for parade
+ * @reg_addrregister address to write
+ * @value value to be written
+ */
+struct reg_data {
+ uint8_t addr_off;
+ uint8_t reg;
+ uint8_t value;
+} _packed;
+
+#define END_OF_TABLE 0xff /* Ficticious offset */
+
+static const struct reg_data parade_values[] = {
+ {0x02, 0xa1, 0x01}, /* HPD low */
+/*
+ * SW setting
+ * [1:0] SW output 1.2V voltage is lower to 96%
+ */
+ {0x04, 0x14, 0x01},
+/*
+ * RCO SS setting
+ * [5:4] = b01 0.5%, b10 1%, b11 1.5%
+ */
+ {0x04, 0xe3, 0x20},
+ {0x04, 0xe2, 0x80}, /* [7] RCO SS enable */
+/*
+ * RPHY Setting
+ * [3:2] CDR tune wait cycle before
+ * measure for fine tune b00: 1us,
+ * 01: 0.5us, 10:2us, 11:4us.
+ */
+ {0x04, 0x8a, 0x0c},
+ {0x04, 0x89, 0x08}, /* [3] RFD always on */
+/*
+ * CTN lock in/out:
+ * 2ppm/8ppm. Lock out 2
+ * times.
+ */
+ {0x04, 0x71, 0x2d},
+/*
+ * 2.7G CDR settings
+ * NOF=40LSB for HBR CDR setting
+ */
+ {0x04, 0x7d, 0x07},
+ {0x04, 0x7b, 0x00}, /* [1:0] Fmin=+4bands */
+ {0x04, 0x7a, 0xfd}, /* [7:5] DCO_FTRNG=+-40% */
+/*
+ * 1.62G CDR settings
+ * [5:2]NOF=64LSB [1:0]DCO scale is 2/5
+ */
+ {0x04, 0xc0, 0x12},
+ {0x04, 0xc1, 0x92}, /* Gitune=-37% */
+ {0x04, 0xc2, 0x1c}, /* Fbstep=100% */
+ {0x04, 0x32, 0x80}, /* [7] LOS signal disable */
+/*
+ * RPIO Setting
+ * [7:4] LVDS driver bias current :
+ * 75% (250mV swing)
+ */
+ {0x04, 0x00, 0xb0},
+/*
+ * [7:6] Right-bar GPIO output strength is 8mA
+ */
+ {0x04, 0x15, 0x40},
+/* EQ Training State Machine Setting */
+ {0x04, 0x54, 0x10}, /* RCO calibration start */
+/* [4:0] MAX_LANE_COUNT set to one lane */
+ {0x01, 0x02, 0x81},
+/* [4:0] LANE_COUNT_SET set to one lane */
+ {0x01, 0x21, 0x81},
+ {0x00, 0x52, 0x20},
+ {0x00, 0xf1, 0x03}, /* HPD CP toggle enable */
+ {0x00, 0x62, 0x41},
+/* Counter number, add 1ms counter delay */
+ {0x00, 0xf6, 0x01},
+/*
+ * [6]PWM function control by
+ * DPCD0040f[7], default is PWM
+ * block always works.
+ */
+ {0x00, 0x77, 0x06},
+/*
+ * 04h Adjust VTotal tolerance to
+ * fix the 30Hz no display issue
+ */
+ {0x00, 0x4c, 0x04},
+/* DPCD00400='h00, Parade OUI = 'h001cf8 */
+ {0x01, 0xc0, 0x00},
+ {0x01, 0xc1, 0x1c}, /* DPCD00401='h1c */
+ {0x01, 0xc2, 0xf8}, /* DPCD00402='hf8 */
+/*
+ * DPCD403~408 = ASCII code
+ * D2SLV5='h4432534c5635
+ */
+ {0x01, 0xc3, 0x44},
+ {0x01, 0xc4, 0x32}, /* DPCD404 */
+ {0x01, 0xc5, 0x53}, /* DPCD405 *
[U-Boot] [PATCH V2 08/10] ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chip
This patch adds DT properties for fimd and the parade bridge chip
present on peach_pit. The panel supports 1366x768 resolution.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/dts/exynos5420-peach-pit.dts | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts
b/arch/arm/dts/exynos5420-peach-pit.dts
index 8d148af..3ed70a8 100644
--- a/arch/arm/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -63,6 +63,11 @@
reg = <0x20>;
compatible = "maxim,max98090-codec";
};
+
+ edp-lvds-bridge@48 {
+ compatible = "parade,ps8625";
+ reg = <0x48>;
+ };
};
sound@383 {
@@ -124,4 +129,29 @@
xhci@1240 {
samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
};
+
+ fimd@1440 {
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <1366>;
+ samsung,vl-row = <768>;
+ samsung,vl-width = <1366>;
+ samsung,vl-height = <768>;
+
+ samsung,vl-clkp;
+ samsung,vl-dp;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <32>;
+ samsung,vl-hbpd = <40>;
+ samsung,vl-hfpd = <40>;
+ samsung,vl-vspw = <6>;
+ samsung,vl-vbpd = <10>;
+ samsung,vl-vfpd = <12>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,winid = <3>;
+ samsung,interface-mode = <1>;
+ samsung,dp-enabled = <1>;
+ samsung,dual-lcd-enabled = <0>;
+ };
};
--
1.8.1.2
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[U-Boot] [PATCH V2 01/10] exynos_fb: Remove usage of static defines
Previously, we used to statically assign values for vl_col, vl_row and
vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.
Introducing the function exynos_lcd_early_init() would take care of this
assignment on the fly by parsing FIMD DT properties, thereby allowing us
to remove LCD_XRES and LCD_YRES from the main config file.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/include/asm/arch-exynos/system.h | 1 +
board/samsung/common/board.c | 15 +++
drivers/video/exynos_fb.c | 17 +
include/configs/exynos5250-dt.h | 2 --
include/configs/s5pc210_universal.h | 3 ---
include/configs/trats.h | 3 ---
include/configs/trats2.h | 3 ---
7 files changed, 21 insertions(+), 23 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/system.h
b/arch/arm/include/asm/arch-exynos/system.h
index 7e2057c..4968d3d 100644
--- a/arch/arm/include/asm/arch-exynos/system.h
+++ b/arch/arm/include/asm/arch-exynos/system.h
@@ -39,5 +39,6 @@ struct exynos5_sysreg {
void set_usbhost_mode(unsigned int mode);
void set_system_display_ctrl(void);
+int exynos_lcd_early_init(const void *blob);
#endif /* _EXYNOS4_SYSTEM_H */
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 9dc7c83..1f6f0a0 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -148,6 +149,20 @@ int board_early_init_f(void)
board_i2c_init(gd->fdt_blob);
#endif
+#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_EXYNOS_FB)
+/*
+ * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
+ * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix, to reserve
+ * FB memory at a very early stage. So, we need to fill panel_info.vl_col,
+ * panel_info.vl_row and panel_info.vl_bpix before lcd_setmem() is called.
+ */
+ err = exynos_lcd_early_init(gd->fdt_blob);
+ if (err) {
+ debug("LCD early init failed\n");
+ return err;
+ }
+#endif
+
return exynos_early_init_f();
}
#endif
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
index e1e0d80..bc478a9 100644
--- a/drivers/video/exynos_fb.c
+++ b/drivers/video/exynos_fb.c
@@ -27,17 +27,12 @@ DECLARE_GLOBAL_DATA_PTR;
static unsigned int panel_width, panel_height;
-/*
- * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
- * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix to reserve
- * FB memory at a very early stage, i.e even before exynos_fimd_parse_dt()
- * is called. So, we are forced to statically assign it.
- */
#ifdef CONFIG_OF_CONTROL
vidinfo_t panel_info = {
- .vl_col = LCD_XRES,
- .vl_row = LCD_YRES,
- .vl_bpix = LCD_COLOR16,
+ /* Insert a value here so that we don't end up in the BSS
+* Reference: drivers/video/tegra.c
+*/
+ .vl_col = -1,
};
#endif
@@ -141,7 +136,7 @@ static void lcd_panel_on(vidinfo_t *vid)
}
#ifdef CONFIG_OF_CONTROL
-int exynos_fimd_parse_dt(const void *blob)
+int exynos_lcd_early_init(const void *blob)
{
unsigned int node;
node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD);
@@ -286,8 +281,6 @@ void lcd_ctrl_init(void *lcdbase)
set_lcd_clk();
#ifdef CONFIG_OF_CONTROL
- if (exynos_fimd_parse_dt(gd->fdt_blob))
- debug("Can't get proper panel info\n");
#ifdef CONFIG_EXYNOS_MIPI_DSIM
exynos_init_dsim_platform_data(&panel_info);
#endif
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 74e72a5..c24984b 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -61,8 +61,6 @@
#ifdef CONFIG_LCD
#define CONFIG_EXYNOS_FB
#define CONFIG_EXYNOS_DP
-#define LCD_XRES 2560
-#define LCD_YRES 1600
#define LCD_BPPLCD_COLOR16
#endif
diff --git a/include/configs/s5pc210_universal.h
b/include/configs/s5pc210_universal.h
index eb046cd..20985da 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -247,7 +247,4 @@ int universal_spi_read(void);
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-#define LCD_XRES 480
-#define LCD_YRES 800
-
#endif /* __CONFIG_H */
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 90f1962..35c1feb 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -261,7 +261,4 @@
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-#define LCD_XRES 720
-#define LCD_YRES 1280
-
#endif /* __CONFIG_H */
diff --git a/include/configs/trats2.h b/include/configs/t
[U-Boot] [TEST_ONLY V2 06/10] ARM: exynos: Add missing declaration for gpio_direction_input
This patch adds missing declaration for gpio_direction_input
function, thereby helps in resolving compilation warnings.
Signed-off-by: Ajay Kumar
---
arch/arm/include/asm/arch-exynos/gpio.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h
index be5113f..8fb5c23 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1504,6 +1504,7 @@ static const struct gpio_name_num_table
exynos5420_gpio_table[] = {
void gpio_cfg_pin(int gpio, int cfg);
void gpio_set_pull(int gpio, int mode);
void gpio_set_drv(int gpio, int mode);
+int gpio_direction_input(unsigned gpio);
int gpio_direction_output(unsigned gpio, int value);
int gpio_set_value(unsigned gpio, int value);
int gpio_get_value(unsigned gpio);
--
1.8.1.2
___
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U-Boot@lists.denx.de
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[U-Boot] [PATCH V2 00/10] peach_pit: Add support for FIMD, DP and parade chip
Patchset V1: https://www.mail-archive.com/u-boot@lists.denx.de/msg140596.html Patch 6 is TEST_ONLY since Simon will be sending it as a part of device model changes. Patch 10 is TEST_ONLY and it adds support for cros-ec on peach_pit. Simon will be sending a proper patchset for the same. Changes from V1: [PATCH V2 3/10] : Don't mix cpu_is and proid_isas per Minkyu's suggestion. Also, incorporate Simon's suggestion of not using else. [PATCH V2 4/10] : For FIMD SYSMMU DT, use same compatible string as kernel. [TEST_ONLY V2 6/10]: Make this patch TEST_ONLY Ajay Kumar (9): [PATCH V2 1/10] exynos_fb: Remove usage of static defines [PATCH V2 2/10] arm: exynos: Add RPLL for Exynos5420 [PATCH V2 3/10] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 [PATCH V2 4/10] video: exynos_fimd: Add framework to disable FIMD sysmmu [TEST_ONLY V2 6/10] ARM: exynos: Add missing declaration for gpio_direction_input [PATCH V2 7/10] exynos5420: add callbacks needed for exynos_fb driver [PATCH V2 8/10] ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chip [PATCH V2 9/10] CONFIGS: peach_pit: Enable display for peach_pit board [TEST_ONLY V2 10/10] Pit WIP Vadim Bendebury (1): [PATCH V2 5/10] video: Add driver for Parade PS8625 dP to LVDS bridge arch/arm/cpu/armv7/exynos/clock.c | 83 +- arch/arm/cpu/armv7/exynos/clock_init.h | 3 + arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 ++ arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +- arch/arm/dts/exynos5420-peach-pit.dts | 30 arch/arm/dts/exynos54xx.dtsi | 10 ++ arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/gpio.h| 1 + arch/arm/include/asm/arch-exynos/system.h | 4 + board/samsung/common/board.c | 15 ++ board/samsung/smdk5420/smdk5420.c | 129 ++- doc/device-tree-bindings/video/exynos-fb.txt | 6 + drivers/misc/cros_ec_spi.c | 4 +- drivers/power/pmic/Makefile| 3 +- drivers/power/pmic/pmic_tps65090_ec.c | 212 drivers/spi/exynos_spi.c | 9 +- drivers/spi/spi.c | 2 + drivers/video/Makefile | 1 + drivers/video/exynos_fb.c | 17 +- drivers/video/exynos_fimd.c| 43 + drivers/video/parade.c | 220 + include/configs/exynos5-dt.h | 2 +- include/configs/exynos5250-dt.h| 2 - include/configs/peach-pit.h| 12 ++ include/configs/s5pc210_universal.h| 3 - include/configs/trats.h| 3 - include/configs/trats2.h | 3 - include/fdtdec.h | 2 + include/power/tps65090_pmic.h | 6 + lib/fdtdec.c | 2 + 30 files changed, 724 insertions(+), 119 deletions(-) create mode 100644 drivers/power/pmic/pmic_tps65090_ec.c create mode 100644 drivers/video/parade.c -- 1.8.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 03/10] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
On Tue, Jun 24, 2014 at 7:36 AM, Minkyu Kang wrote:
> On 24/06/14 20:28, Ajay kumar wrote:
>> Hi Minkyu,
>>
>> On Tue, Jun 24, 2014 at 3:36 AM, Minkyu Kang wrote:
>>> On 17/06/14 18:06, Ajay Kumar wrote:
>>>> Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
>>>> exynos video driver.
>>>> Also, configure ACLK_400_DISP1 as the parent for
>>>> MUX_ACLK_400_DISP1_SUB_SEL.
>>>>
>>>> Signed-off-by: Ajay Kumar
>>>> ---
>>>> arch/arm/cpu/armv7/exynos/clock.c | 74
>>>> +--
>>>> arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +-
>>>> arch/arm/include/asm/arch-exynos/clk.h| 1 +
>>>> 3 files changed, 73 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
>>>> b/arch/arm/cpu/armv7/exynos/clock.c
>>>> index 400d134..c29b12d 100644
>>>> --- a/arch/arm/cpu/armv7/exynos/clock.c
>>>> +++ b/arch/arm/cpu/armv7/exynos/clock.c
>>>> @@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int
>>>> r, unsigned int k)
>>>>* VPLL_CON: MIDV [24:16]
>>>>* BPLL_CON: MIDV [25:16]: Exynos5
>>>>*/
>>>> - if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
>>>> + if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
>>>> + pllreg == SPLL)
>>>> mask = 0x3ff;
>>>> else
>>>> mask = 0x1ff;
>>>> @@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg)
>>>> r = readl(&clk->rpll_con0);
>>>> k = readl(&clk->rpll_con1);
>>>> break;
>>>> + case SPLL:
>>>> + r = readl(&clk->spll_con0);
>>>> + break;
>>>> default:
>>>> printf("Unsupported PLL (%d)\n", pllreg);
>>>> return 0;
>>>> @@ -1027,6 +1031,40 @@ static unsigned long exynos5_get_lcd_clk(void)
>>>> return pclk;
>>>> }
>>>>
>>>> +static unsigned long exynos5420_get_lcd_clk(void)
>>>> +{
>>>> + struct exynos5420_clock *clk =
>>>> + (struct exynos5420_clock *)samsung_get_base_clock();
>>>> + unsigned long pclk, sclk;
>>>> + unsigned int sel;
>>>> + unsigned int ratio;
>>>> +
>>>> + /*
>>>> + * CLK_SRC_DISP10
>>>> + * FIMD1_SEL [4]
>>>> + * 0: SCLK_RPLL
>>>> + * 1: SCLK_SPLL
>>>> + */
>>>> + sel = readl(&clk->src_disp10);
>>>> + sel &= (1 << 4);
>>>> +
>>>> + if (sel)
>>>> + sclk = get_pll_clk(SPLL);
>>>> + else
>>>> + sclk = get_pll_clk(RPLL);
>>>> +
>>>> + /*
>>>> + * CLK_DIV_DISP10
>>>> + * FIMD1_RATIO [3:0]
>>>> + */
>>>> + ratio = readl(&clk->div_disp10);
>>>> + ratio = ratio & 0xf;
>>>> +
>>>> + pclk = sclk / (ratio + 1);
>>>> +
>>>> + return pclk;
>>>> +}
>>>> +
>>>> void exynos4_set_lcd_clk(void)
>>>> {
>>>> struct exynos4_clock *clk =
>>>> @@ -1131,6 +1169,33 @@ void exynos5_set_lcd_clk(void)
>>>> clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
>>>> }
>>>>
>>>> +void exynos5420_set_lcd_clk(void)
>>>> +{
>>>> + struct exynos5420_clock *clk =
>>>> + (struct exynos5420_clock *)samsung_get_base_clock();
>>>> + unsigned int cfg;
>>>> +
>>>> + /*
>>>> + * CLK_SRC_DISP10
>>>> + * FIMD1_SEL [4]
>>>> + * 0: SCLK_RPLL
>>>> + * 1: SCLK_SPLL
>>>> + */
>>>> + cfg = readl(&clk->src_disp10);
>>>> + cfg &= ~(0x1 << 4);
>>>> + cfg |= (0 << 4);
>>>> + writel(cfg, &clk->src_disp10);
>>>> +
>>>> + /*
>>>> + * CLK_DIV_DISP10
>>>> + * FIMD1_RATIO [3:0]
>>>> + */
>>>> + cfg = read
Re: [U-Boot] [PATCH 03/10] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
Hi Minkyu,
On Tue, Jun 24, 2014 at 3:36 AM, Minkyu Kang wrote:
> On 17/06/14 18:06, Ajay Kumar wrote:
>> Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
>> exynos video driver.
>> Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.
>>
>> Signed-off-by: Ajay Kumar
>> ---
>> arch/arm/cpu/armv7/exynos/clock.c | 74
>> +--
>> arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +-
>> arch/arm/include/asm/arch-exynos/clk.h| 1 +
>> 3 files changed, 73 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
>> b/arch/arm/cpu/armv7/exynos/clock.c
>> index 400d134..c29b12d 100644
>> --- a/arch/arm/cpu/armv7/exynos/clock.c
>> +++ b/arch/arm/cpu/armv7/exynos/clock.c
>> @@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r,
>> unsigned int k)
>>* VPLL_CON: MIDV [24:16]
>>* BPLL_CON: MIDV [25:16]: Exynos5
>>*/
>> - if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
>> + if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
>> + pllreg == SPLL)
>> mask = 0x3ff;
>> else
>> mask = 0x1ff;
>> @@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg)
>> r = readl(&clk->rpll_con0);
>> k = readl(&clk->rpll_con1);
>> break;
>> + case SPLL:
>> + r = readl(&clk->spll_con0);
>> + break;
>> default:
>> printf("Unsupported PLL (%d)\n", pllreg);
>> return 0;
>> @@ -1027,6 +1031,40 @@ static unsigned long exynos5_get_lcd_clk(void)
>> return pclk;
>> }
>>
>> +static unsigned long exynos5420_get_lcd_clk(void)
>> +{
>> + struct exynos5420_clock *clk =
>> + (struct exynos5420_clock *)samsung_get_base_clock();
>> + unsigned long pclk, sclk;
>> + unsigned int sel;
>> + unsigned int ratio;
>> +
>> + /*
>> + * CLK_SRC_DISP10
>> + * FIMD1_SEL [4]
>> + * 0: SCLK_RPLL
>> + * 1: SCLK_SPLL
>> + */
>> + sel = readl(&clk->src_disp10);
>> + sel &= (1 << 4);
>> +
>> + if (sel)
>> + sclk = get_pll_clk(SPLL);
>> + else
>> + sclk = get_pll_clk(RPLL);
>> +
>> + /*
>> + * CLK_DIV_DISP10
>> + * FIMD1_RATIO [3:0]
>> + */
>> + ratio = readl(&clk->div_disp10);
>> + ratio = ratio & 0xf;
>> +
>> + pclk = sclk / (ratio + 1);
>> +
>> + return pclk;
>> +}
>> +
>> void exynos4_set_lcd_clk(void)
>> {
>> struct exynos4_clock *clk =
>> @@ -1131,6 +1169,33 @@ void exynos5_set_lcd_clk(void)
>> clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
>> }
>>
>> +void exynos5420_set_lcd_clk(void)
>> +{
>> + struct exynos5420_clock *clk =
>> + (struct exynos5420_clock *)samsung_get_base_clock();
>> + unsigned int cfg;
>> +
>> + /*
>> + * CLK_SRC_DISP10
>> + * FIMD1_SEL [4]
>> + * 0: SCLK_RPLL
>> + * 1: SCLK_SPLL
>> + */
>> + cfg = readl(&clk->src_disp10);
>> + cfg &= ~(0x1 << 4);
>> + cfg |= (0 << 4);
>> + writel(cfg, &clk->src_disp10);
>> +
>> + /*
>> + * CLK_DIV_DISP10
>> + * FIMD1_RATIO [3:0]
>> + */
>> + cfg = readl(&clk->div_disp10);
>> + cfg &= ~(0xf << 0);
>> + cfg |= (0 << 0);
>> + writel(cfg, &clk->div_disp10);
>> +}
>> +
>> void exynos4_set_mipi_clk(void)
>> {
>> struct exynos4_clock *clk =
>> @@ -1602,14 +1667,17 @@ unsigned long get_lcd_clk(void)
>> {
>> if (cpu_is_exynos4())
>> return exynos4_get_lcd_clk();
>> - else
>> - return exynos5_get_lcd_clk();
>> + else if (proid_is_exynos5420())
>> + return exynos5420_get_lcd_clk();
>> + return exynos5_get_lcd_clk();
>
> No. Please don't mix cpu_is... and proid_is
> You can refer to other functions.
Actually, only "cpu_is_exynos4" and "cpu_is_exynos5" are defined in cpu.h.
And, I need different clock setting for 5250 and 5420.
The only way to achieve this is by calling appropriate function
Re: [U-Boot] [PATCH 04/10] video: exynos_fimd: Add framework to disable FIMD sysmmu
Simon, On Mon, Jun 23, 2014 at 5:45 PM, Simon Glass wrote: > Hi Ajay, > > On 20 June 2014 00:42, Ajay kumar wrote: >> Hi Simon, >> >> >> On Fri, Jun 20, 2014 at 8:59 AM, Simon Glass wrote: >>> On 17 June 2014 03:06, Ajay Kumar wrote: >>>> On Exynos5420 and newer versions, the FIMD sysmmus are in >>>> "on state" by default. >>>> We have to disable them in order to make FIMD DMA work. >>>> This patch adds the required framework to exynos_fimd driver, >>>> and disables FIMD sysmmu on Exynos5420. >>>> >>>> Signed-off-by: Ajay Kumar >>> >>> Acked-by: Simon Glass >>> Tested-by: Simon Glass >>> >>> (I assume this is the same device tree binding as Linux?) >> Actually, No! >> Kernel has a generic binding named "samsung,sysmmu-v3.3", and it is common >> for all sysmmu nodes. There is a seperate IOMMU driver to handle the same. >> We can port the device probing part from kernel to u-boot, but we would need >> to add seperate driver(since the name is generic) to handle the same. >> That driver, even though being generic, will be used only by FIMD >> sysmmus(that too, just to turn them off). > > OK. I suppose you could add a very short new C file with a function > which finds the device tree node by its compatible string or whatever, > and then updates the hardware. Ok. I will add this. Ajay > Regards, > Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 04/10] video: exynos_fimd: Add framework to disable FIMD sysmmu
Hi Simon, On Fri, Jun 20, 2014 at 8:59 AM, Simon Glass wrote: > On 17 June 2014 03:06, Ajay Kumar wrote: >> On Exynos5420 and newer versions, the FIMD sysmmus are in >> "on state" by default. >> We have to disable them in order to make FIMD DMA work. >> This patch adds the required framework to exynos_fimd driver, >> and disables FIMD sysmmu on Exynos5420. >> >> Signed-off-by: Ajay Kumar > > Acked-by: Simon Glass > Tested-by: Simon Glass > > (I assume this is the same device tree binding as Linux?) Actually, No! Kernel has a generic binding named "samsung,sysmmu-v3.3", and it is common for all sysmmu nodes. There is a seperate IOMMU driver to handle the same. We can port the device probing part from kernel to u-boot, but we would need to add seperate driver(since the name is generic) to handle the same. That driver, even though being generic, will be used only by FIMD sysmmus(that too, just to turn them off). Ajay > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 09/10] CONFIGS: peach-pit: Enable display for peach_pit board
Simon, On Fri, Jun 20, 2014 at 9:08 AM, Simon Glass wrote: > Hi Ajay, > > On 17 June 2014 03:06, Ajay Kumar wrote: >> Enable drivers for FIMD, DP and parade bridge chip. >> >> Signed-off-by: Ajay Kumar >> --- >> include/configs/peach-pit.h | 10 ++ >> 1 file changed, 10 insertions(+) >> >> diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h >> index 76b8d7a..88c093f 100644 >> --- a/include/configs/peach-pit.h >> +++ b/include/configs/peach-pit.h >> @@ -22,4 +22,14 @@ >> #define CONFIG_SYS_PROMPT "Peach # " >> #define CONFIG_IDENT_STRING" for Peach" >> >> +#define CONFIG_VIDEO_PARADE >> + >> +/* Display */ >> +#define CONFIG_LCD >> +#ifdef CONFIG_LCD >> +#define CONFIG_EXYNOS_FB >> +#define CONFIG_EXYNOS_DP >> +#define LCD_BPPLCD_COLOR16 >> +#endif >> + >> #endif /* __CONFIG_PEACH_PIT_H */ > > Can this go in exynos5420.h? It seems to be common except for the PARADE bit. No. This patchset enables display only for peach_pit. So, we cannot move this to exynos5420.h. Ajay > Regards, > Simon > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 10/10] Pit WIP
From: Simon Glass
WIP patch to enable cros-ec on peach_pit.
Signed-off-by: Simon Glass
---
drivers/misc/cros_ec_spi.c| 4 +-
drivers/power/pmic/Makefile | 3 +-
drivers/power/pmic/pmic_tps65090_ec.c | 212 ++
drivers/spi/exynos_spi.c | 9 +-
drivers/spi/spi.c | 2 +
include/configs/exynos5-dt.h | 2 +-
include/configs/peach-pit.h | 2 +
include/power/tps65090_pmic.h | 6 +
8 files changed, 232 insertions(+), 8 deletions(-)
create mode 100644 drivers/power/pmic/pmic_tps65090_ec.c
diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c
index 7df709c..015333f 100644
--- a/drivers/misc/cros_ec_spi.c
+++ b/drivers/misc/cros_ec_spi.c
@@ -98,7 +98,7 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd,
int cmd_version,
}
out = dev->dout;
- out[0] = cmd_version;
+ out[0] = EC_CMD_VERSION0 + cmd_version;
out[1] = cmd;
out[2] = (uint8_t)dout_len;
memcpy(out + 3, dout, dout_len);
@@ -165,7 +165,7 @@ int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const
void *blob)
*/
int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob)
{
- dev->spi = spi_setup_slave_fdt(blob, dev->parent_node, dev->node);
+ dev->spi = spi_setup_slave_fdt(blob, dev->node, dev->parent_node);
if (!dev->spi) {
debug("%s: Could not setup SPI slave\n", __func__);
return -1;
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index a472f61..e7b07eb 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -11,7 +11,8 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
-obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o
+obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o
+obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o
obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
diff --git a/drivers/power/pmic/pmic_tps65090_ec.c
b/drivers/power/pmic/pmic_tps65090_ec.c
new file mode 100644
index 000..93b7923
--- /dev/null
+++ b/drivers/power/pmic/pmic_tps65090_ec.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TPS65090_ADDR 0x48
+
+static struct tps65090 {
+ struct cros_ec_dev *dev;/* The CROS_EC device */
+} config;
+
+/* TPS65090 register addresses */
+enum {
+ REG_FET1_CTRL = 0x0f,
+ REG_FET2_CTRL,
+ REG_FET3_CTRL,
+ REG_FET4_CTRL,
+ REG_FET5_CTRL,
+ REG_FET6_CTRL,
+ REG_FET7_CTRL,
+ TPS65090_NUM_REGS,
+};
+
+enum {
+ MAX_FET_NUM = 7,
+ MAX_CTRL_READ_TRIES = 5,
+
+ /* TPS65090 FET_CTRL register values */
+ FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */
+ FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */
+ FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */
+ FET_CTRL_ADENFET= 1 << 1, /* Enable output auto discharge */
+ FET_CTRL_ENFET = 1 << 0, /* Enable FET */
+};
+
+/**
+ * tps65090_read - read a byte from tps6090
+ *
+ * @param reg The register address to read from.
+ * @param val We'll return value value read here.
+ * @return 0 if ok; error if EC returns failure.
+ */
+static int tps65090_read(u32 reg, u8 *val)
+{
+ return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1,
+ val, 1, true);
+}
+
+/**
+ * tps65090_write - write a byte to tps6090
+ *
+ * @param reg The register address to write to.
+ * @param val The value to write.
+ * @return 0 if ok; error if EC returns failure.
+ */
+static int tps65090_write(u32 reg, u8 val)
+{
+ return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1,
+ &val, 1, false);
+}
+
+/**
+ * Checks for a valid FET number
+ *
+ * @param fet_id FET number to check
+ * @return 0 if ok, -1 if FET value is out of range
+ */
+static int tps65090_check_fet(unsigned int fet_id)
+{
+ if (fet_id == 0 || fet_id > MAX_FET_NUM) {
+ debug("parameter fet_id is out of range, %u not in 1 ~ %u\n",
+ fet_id, MAX_FET_NUM);
+ return -1;
+ }
+
+ return 0;
+}
+
+/**
+ * Set the power state for a FET
+
[U-Boot] [PATCH 08/10] ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chip
This patch adds DT properties for fimd and the parade bridge chip
present on peach_pit. The panel supports 1366x768 resolution.
Signed-off-by: Ajay Kumar
---
arch/arm/dts/exynos5420-peach-pit.dts | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts
b/arch/arm/dts/exynos5420-peach-pit.dts
index 8d148af..3ed70a8 100644
--- a/arch/arm/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -63,6 +63,11 @@
reg = <0x20>;
compatible = "maxim,max98090-codec";
};
+
+ edp-lvds-bridge@48 {
+ compatible = "parade,ps8625";
+ reg = <0x48>;
+ };
};
sound@383 {
@@ -124,4 +129,29 @@
xhci@1240 {
samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
};
+
+ fimd@1440 {
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <1366>;
+ samsung,vl-row = <768>;
+ samsung,vl-width = <1366>;
+ samsung,vl-height = <768>;
+
+ samsung,vl-clkp;
+ samsung,vl-dp;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <32>;
+ samsung,vl-hbpd = <40>;
+ samsung,vl-hfpd = <40>;
+ samsung,vl-vspw = <6>;
+ samsung,vl-vbpd = <10>;
+ samsung,vl-vfpd = <12>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,winid = <3>;
+ samsung,interface-mode = <1>;
+ samsung,dp-enabled = <1>;
+ samsung,dual-lcd-enabled = <0>;
+ };
};
--
1.8.1.2
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[U-Boot] [PATCH 07/10] exynos5420: add callbacks needed for exynos_fb driver
Add initialization code for peach_pit panel, parade bridge chip,
and backlight.
Signed-off-by: Ajay Kumar
---
arch/arm/include/asm/arch-exynos/system.h | 3 +
board/samsung/smdk5420/smdk5420.c | 129 +++---
2 files changed, 50 insertions(+), 82 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/system.h
b/arch/arm/include/asm/arch-exynos/system.h
index 4968d3d..320763f 100644
--- a/arch/arm/include/asm/arch-exynos/system.h
+++ b/arch/arm/include/asm/arch-exynos/system.h
@@ -41,4 +41,7 @@ void set_usbhost_mode(unsigned int mode);
void set_system_display_ctrl(void);
int exynos_lcd_early_init(const void *blob);
+/* Initialize the Parade dP<->LVDS bridge if present */
+int parade_init(const void *blob);
+
#endif /* _EXYNOS4_SYSTEM_H */
diff --git a/board/samsung/smdk5420/smdk5420.c
b/board/samsung/smdk5420/smdk5420.c
index 183c522..270ee83 100644
--- a/board/samsung/smdk5420/smdk5420.c
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -10,11 +10,14 @@
#include
#include
#include
+#include
#include
#include
#include
#include
+#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -40,95 +43,57 @@ int exynos_init(void)
}
#ifdef CONFIG_LCD
-void cfg_lcd_gpio(void)
+static int has_edp_bridge(void)
{
- /* For Backlight */
- gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_OUTPUT);
- gpio_set_value(EXYNOS5420_GPIO_B20, 1);
+ int node;
+
+ node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_PARADE_PS8625);
- /* LCD power on */
- gpio_cfg_pin(EXYNOS5420_GPIO_X15, S5P_GPIO_OUTPUT);
- gpio_set_value(EXYNOS5420_GPIO_X15, 1);
+ /* No node for bridge in device tree. */
+ if (node <= 0)
+ return 0;
- /* Set Hotplug detect for DP */
- gpio_cfg_pin(EXYNOS5420_GPIO_X07, S5P_GPIO_FUNC(0x3));
+ /* Default is with bridge ic */
+ return 1;
}
-vidinfo_t panel_info = {
- .vl_freq= 60,
- .vl_col = 2560,
- .vl_row = 1600,
- .vl_width = 2560,
- .vl_height = 1600,
- .vl_clkp= CONFIG_SYS_LOW,
- .vl_hsp = CONFIG_SYS_LOW,
- .vl_vsp = CONFIG_SYS_LOW,
- .vl_dp = CONFIG_SYS_LOW,
- .vl_bpix= 4,/* LCD_BPP = 2^4, for output conosle on LCD */
-
- /* wDP panel timing infomation */
- .vl_hspw= 32,
- .vl_hbpd= 80,
- .vl_hfpd= 48,
-
- .vl_vspw= 6,
- .vl_vbpd= 37,
- .vl_vfpd= 3,
- .vl_cmd_allow_len = 0xf,
-
- .win_id = 3,
- .cfg_gpio = cfg_lcd_gpio,
- .backlight_on = NULL,
- .lcd_power_on = NULL,
- .reset_lcd = NULL,
- .dual_lcd_enabled = 0,
-
- .init_delay = 0,
- .power_on_delay = 0,
- .reset_delay= 0,
- .interface_mode = FIMD_RGB_INTERFACE,
- .dp_enabled = 1,
-};
-
-static struct edp_device_info edp_info = {
- .disp_info = {
- .h_res = 2560,
- .h_sync_width = 32,
- .h_back_porch = 80,
- .h_front_porch = 48,
- .v_res = 1600,
- .v_sync_width = 6,
- .v_back_porch = 37,
- .v_front_porch = 3,
- .v_sync_rate = 60,
- },
- .lt_info = {
- .lt_status = DP_LT_NONE,
- },
- .video_info = {
- .master_mode = 0,
- .bist_mode = DP_DISABLE,
- .bist_pattern = NO_PATTERN,
- .h_sync_polarity = 0,
- .v_sync_polarity = 0,
- .interlaced = 0,
- .color_space = COLOR_RGB,
- .dynamic_range = VESA,
- .ycbcr_coeff = COLOR_YCBCR601,
- .color_depth = COLOR_8,
- },
-};
-
-static struct exynos_dp_platform_data dp_platform_data = {
- .phy_enable = set_dp_phy_ctrl,
- .edp_dev_info = &edp_info,
-};
-
-void init_panel_info(vidinfo_t *vid)
+void exynos_lcd_power_on(void)
{
- vid->rgb_mode = MODE_RGB_P;
+ int ret;
+
+#ifdef CONFIG_POWER_TPS65090
+ ret = tps65090_init();
+ if (ret < 0) {
+ printf("%s: tps65090_init() failed\n", __func__);
+ return;
+ }
+
+ tps65090_fet_enable(6);
+#endif
+
+ mdelay(5);
+
+ /* TODO(ajaykumar...@samsung.com): Use device tree */
+ gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */
+ mdelay(10);
+ gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */
+ gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
+ gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
- exynos_set_dp_platform_data(&dp_platform_data);
+ if (has_edp_bridge())
+ if (parade_init(gd->fdt_blob))
+ printf("%s: ps
[U-Boot] [PATCH 09/10] CONFIGS: peach-pit: Enable display for peach_pit board
Enable drivers for FIMD, DP and parade bridge chip. Signed-off-by: Ajay Kumar --- include/configs/peach-pit.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 76b8d7a..88c093f 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -22,4 +22,14 @@ #define CONFIG_SYS_PROMPT "Peach # " #define CONFIG_IDENT_STRING" for Peach" +#define CONFIG_VIDEO_PARADE + +/* Display */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_EXYNOS_FB +#define CONFIG_EXYNOS_DP +#define LCD_BPPLCD_COLOR16 +#endif + #endif /* __CONFIG_PEACH_PIT_H */ -- 1.8.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 02/10] arm: exynos: Add RPLL for Exynos5420
RPLL is needed to drive the LCD panel on Exynos5420 based boards.
Signed-off-by: Ajay Kumar
---
arch/arm/cpu/armv7/exynos/clock_init.h | 3 +++
arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 +
2 files changed, 16 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h
b/arch/arm/cpu/armv7/exynos/clock_init.h
index a875d0b..fce502f 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init.h
+++ b/arch/arm/cpu/armv7/exynos/clock_init.h
@@ -75,6 +75,9 @@ struct mem_timings {
unsigned spll_mdiv;
unsigned spll_pdiv;
unsigned spll_sdiv;
+ unsigned rpll_mdiv;
+ unsigned rpll_pdiv;
+ unsigned rpll_sdiv;
unsigned pclk_cdrex_ratio;
unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
index 1d6977f..b6a9bc1 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
+++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
@@ -179,6 +179,10 @@ struct mem_timings mem_timings[] = {
.spll_mdiv = 0xc8,
.spll_pdiv = 0x3,
.spll_sdiv = 0x2,
+ /* RPLL @70.5Mhz */
+ .rpll_mdiv = 0x5E,
+ .rpll_pdiv = 0x2,
+ .rpll_sdiv = 0x4,
.direct_cmd_msr = {
0x00020018, 0x0003, 0x00010046, 0x0d70,
@@ -800,6 +804,7 @@ static void exynos5420_system_clock_init(void)
writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
+ writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);
setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
@@ -898,6 +903,14 @@ static void exynos5420_system_clock_init(void)
while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
;
+ /* Set RPLL */
+ writel(RPLL_CON2_VAL, &clk->rpll_con2);
+ writel(RPLL_CON1_VAL, &clk->rpll_con1);
+ val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv);
+ writel(val, &clk->rpll_con0);
+ while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0)
+ ;
+
writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
--
1.8.1.2
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[U-Boot] [PATCH 06/10] ARM: exynos: Add missing declaration for gpio_direction_input
This patch adds missing declaration for gpio_direction_input
function, thereby helps in resolving compilation warnings.
Signed-off-by: Ajay Kumar
---
arch/arm/include/asm/arch-exynos/gpio.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h
index be5113f..8fb5c23 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1504,6 +1504,7 @@ static const struct gpio_name_num_table
exynos5420_gpio_table[] = {
void gpio_cfg_pin(int gpio, int cfg);
void gpio_set_pull(int gpio, int mode);
void gpio_set_drv(int gpio, int mode);
+int gpio_direction_input(unsigned gpio);
int gpio_direction_output(unsigned gpio, int value);
int gpio_set_value(unsigned gpio, int value);
int gpio_get_value(unsigned gpio);
--
1.8.1.2
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[U-Boot] [PATCH 03/10] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.
Signed-off-by: Ajay Kumar
---
arch/arm/cpu/armv7/exynos/clock.c | 74 +--
arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +-
arch/arm/include/asm/arch-exynos/clk.h| 1 +
3 files changed, 73 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 400d134..c29b12d 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r,
unsigned int k)
* VPLL_CON: MIDV [24:16]
* BPLL_CON: MIDV [25:16]: Exynos5
*/
- if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
+ if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
+ pllreg == SPLL)
mask = 0x3ff;
else
mask = 0x1ff;
@@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg)
r = readl(&clk->rpll_con0);
k = readl(&clk->rpll_con1);
break;
+ case SPLL:
+ r = readl(&clk->spll_con0);
+ break;
default:
printf("Unsupported PLL (%d)\n", pllreg);
return 0;
@@ -1027,6 +1031,40 @@ static unsigned long exynos5_get_lcd_clk(void)
return pclk;
}
+static unsigned long exynos5420_get_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long pclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+* CLK_SRC_DISP10
+* FIMD1_SEL [4]
+* 0: SCLK_RPLL
+* 1: SCLK_SPLL
+*/
+ sel = readl(&clk->src_disp10);
+ sel &= (1 << 4);
+
+ if (sel)
+ sclk = get_pll_clk(SPLL);
+ else
+ sclk = get_pll_clk(RPLL);
+
+ /*
+* CLK_DIV_DISP10
+* FIMD1_RATIO [3:0]
+*/
+ ratio = readl(&clk->div_disp10);
+ ratio = ratio & 0xf;
+
+ pclk = sclk / (ratio + 1);
+
+ return pclk;
+}
+
void exynos4_set_lcd_clk(void)
{
struct exynos4_clock *clk =
@@ -1131,6 +1169,33 @@ void exynos5_set_lcd_clk(void)
clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
}
+void exynos5420_set_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned int cfg;
+
+ /*
+* CLK_SRC_DISP10
+* FIMD1_SEL [4]
+* 0: SCLK_RPLL
+* 1: SCLK_SPLL
+*/
+ cfg = readl(&clk->src_disp10);
+ cfg &= ~(0x1 << 4);
+ cfg |= (0 << 4);
+ writel(cfg, &clk->src_disp10);
+
+ /*
+* CLK_DIV_DISP10
+* FIMD1_RATIO [3:0]
+*/
+ cfg = readl(&clk->div_disp10);
+ cfg &= ~(0xf << 0);
+ cfg |= (0 << 0);
+ writel(cfg, &clk->div_disp10);
+}
+
void exynos4_set_mipi_clk(void)
{
struct exynos4_clock *clk =
@@ -1602,14 +1667,17 @@ unsigned long get_lcd_clk(void)
{
if (cpu_is_exynos4())
return exynos4_get_lcd_clk();
- else
- return exynos5_get_lcd_clk();
+ else if (proid_is_exynos5420())
+ return exynos5420_get_lcd_clk();
+ return exynos5_get_lcd_clk();
}
void set_lcd_clk(void)
{
if (cpu_is_exynos4())
exynos4_set_lcd_clk();
+ else if (proid_is_exynos5420())
+ exynos5420_set_lcd_clk();
else
exynos5_set_lcd_clk();
}
diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
index db8ea86..5eac9cf 100644
--- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
+++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
@@ -779,7 +779,7 @@
#define CLK_SRC_TOP2_VAL 0x11101000
#define CLK_SRC_TOP3_VAL 0x
#define CLK_SRC_TOP4_VAL 0x0111
-#define CLK_SRC_TOP5_VAL 0x1100
+#define CLK_SRC_TOP5_VAL 0x1101
#define CLK_SRC_TOP6_VAL 0x0111
#define CLK_SRC_TOP7_VAL 0x00022200
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index ffbc07e..db24dc0 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -15,6 +15,7 @@
#define VPLL 4
#define BPLL 5
#define RPLL 6
+#define SPLL 7
#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8))
#define MASK_RATIO(x) (0xf << (x << 4))
--
1.8.1.2
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[U-Boot] [PATCH 04/10] video: exynos_fimd: Add framework to disable FIMD sysmmu
On Exynos5420 and newer versions, the FIMD sysmmus are in
"on state" by default.
We have to disable them in order to make FIMD DMA work.
This patch adds the required framework to exynos_fimd driver,
and disables FIMD sysmmu on Exynos5420.
Signed-off-by: Ajay Kumar
---
arch/arm/dts/exynos54xx.dtsi | 10 ++
doc/device-tree-bindings/video/exynos-fb.txt | 2 ++
drivers/video/exynos_fimd.c | 52
include/fdtdec.h | 4 +++
lib/fdtdec.c | 2 ++
5 files changed, 70 insertions(+)
diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi
index b9f8e0b..402d12b 100644
--- a/arch/arm/dts/exynos54xx.dtsi
+++ b/arch/arm/dts/exynos54xx.dtsi
@@ -113,6 +113,16 @@
status = "disabled";
};
+ fimdm0_sysmmu@0x1464 {
+ compatible = "samsung,sysmmu-fimdm0";
+ reg = <0x1464 0x100>;
+ };
+
+ fimdm1_sysmmu@0x1468 {
+ compatible = "samsung,sysmmu-fimdm1";
+ reg = <0x1468 0x100>;
+ };
+
fimd@1440 {
/* sysmmu is not used in U-Boot */
samsung,disable-sysmmu;
diff --git a/doc/device-tree-bindings/video/exynos-fb.txt
b/doc/device-tree-bindings/video/exynos-fb.txt
index bb7441c..7d9b995 100644
--- a/doc/device-tree-bindings/video/exynos-fb.txt
+++ b/doc/device-tree-bindings/video/exynos-fb.txt
@@ -55,6 +55,8 @@ Board(panel specific):
samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)
samsung,sclk-div: parent_clock/source_clock ratio
samsung,dual-lcd-enabled: 1 if you support two LCD, else 0
+ samsung,disable-sysmmu: present if you want to disable the sysmmu
+ (needed for Exynos5420 and newer versions)
Example:
SOC specific part:
diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
index cebbba7..5630d0b 100644
--- a/drivers/video/exynos_fimd.c
+++ b/drivers/video/exynos_fimd.c
@@ -251,6 +251,54 @@ void exynos_fimd_window_off(unsigned int win_id)
writel(cfg, &fimd_ctrl->winshmap);
}
+#ifdef CONFIG_OF_CONTROL
+void exynos_fimd_disable_sysmmu(void)
+{
+ u32 *sysmmufimd;
+ unsigned int node;
+
+ /*
+ * The reset value for FIMD SYSMMU register MMU_CTRL is 3
+ * on Exynos5420 and newer versions.
+ * This means FIMD SYSMMU is on by default on Exynos5420
+ * and newer versions.
+ * Since in u-boot we don't use SYSMMU, we should disable
+ * those FIMD SYSMMU.
+ * Note that there are 2 SYSMMU for FIMD: m0 and m1.
+ * m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3.
+ * We disable both of them here.
+ */
+ node = fdtdec_next_compatible(gd->fdt_blob, 0,
+ COMPAT_SAMSUNG_EXYNOS_FIMD_SYSMMU0);
+ if (node <= 0) {
+ debug("exynos_fb: Can't get device node for fimd dma m0\n");
+ return;
+ }
+
+ sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
+ if (!sysmmufimd) {
+ debug("Can't get base address for sysmmu fimdm0");
+ return;
+ }
+
+ writel(0x0, sysmmufimd);
+
+ node = fdtdec_next_compatible(gd->fdt_blob, 0,
+ COMPAT_SAMSUNG_EXYNOS_FIMD_SYSMMU1);
+ if (node <= 0) {
+ debug("exynos_fb: Can't get device node for fimd dma m1\n");
+ return;
+ }
+
+ sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
+ if (!sysmmufimd) {
+ debug("Can't get base address for sysmmu fimdm0");
+ return;
+ }
+
+ writel(0x0, sysmmufimd);
+}
+#endif
void exynos_fimd_lcd_init(vidinfo_t *vid)
{
@@ -268,6 +316,10 @@ void exynos_fimd_lcd_init(vidinfo_t *vid)
node, "reg");
if (fimd_ctrl == NULL)
debug("Can't get the FIMD base address\n");
+
+ if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
+ exynos_fimd_disable_sysmmu();
+
#else
fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd();
#endif
diff --git a/include/fdtdec.h b/include/fdtdec.h
index a7e6ee7..3329623 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -94,6 +94,10 @@ enum fdt_compat_id {
COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */
COMPAT_TI_TPS65090, /* Texas Instrument TPS65090 */
COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */
+ /* Exynos Display controller sysmmu0 */
+ COMPAT_SAMSUNG_EXYNOS_FIMD_SYSMMU0,
+ /* Exynos Display co
[U-Boot] [PATCH 00/10] peach_pit: Add support for FIMD, DP and parade chip
This patchset has dependency on Akshay's base patchset for peach_pit: https://www.mail-archive.com/u-boot@lists.denx.de/msg138595.html This patchset is actually a rebase of my older patchset: http://lists.denx.de/pipermail/u-boot/2013-November/166935.html, and this patchset enables display on exynos5420 based peach_pit board. The last patch is TEST_ONLY, and it adds support for cros-ec on peach_pit. Simon will be sending a proper patchset for the same. Ajay Kumar (9): [PATCH 1/10] exynos_fb: Remove usage of static defines [PATCH 2/10] arm: exynos: Add RPLL for Exynos5420 [PATCH 3/10] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 [PATCH 4/10] video: exynos_fimd: Add framework to disable FIMD sysmmu [PATCH 6/10] ARM: exynos: Add missing declaration for gpio_direction_input [PATCH 7/10] exynos5420: add callbacks needed for exynos_fb driver [PATCH 8/10] ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chip [PATCH 9/10] CONFIGS: peach_pit: Enable display for peach_pit board Vadim Bendebury (1): [PATCH 5/10] video: Add driver for Parade PS8625 dP to LVDS bridge Simon Glass (1): [TEST_ONLY 10/10] Pit WIP arch/arm/cpu/armv7/exynos/clock.c | 74 - arch/arm/cpu/armv7/exynos/clock_init.h | 3 + arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 ++ arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +- arch/arm/dts/exynos5420-peach-pit.dts | 30 arch/arm/dts/exynos54xx.dtsi | 10 ++ arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/gpio.h| 1 + arch/arm/include/asm/arch-exynos/system.h | 4 + board/samsung/common/board.c | 15 ++ board/samsung/smdk5420/smdk5420.c | 129 ++- doc/device-tree-bindings/video/exynos-fb.txt | 2 + drivers/misc/cros_ec_spi.c | 4 +- drivers/power/pmic/Makefile| 3 +- drivers/power/pmic/pmic_tps65090_ec.c | 212 drivers/spi/exynos_spi.c | 9 +- drivers/spi/spi.c | 2 + drivers/video/Makefile | 1 + drivers/video/exynos_fb.c | 17 +- drivers/video/exynos_fimd.c| 52 ++ drivers/video/parade.c | 220 + include/configs/exynos5-dt.h | 2 +- include/configs/exynos5250-dt.h| 2 - include/configs/peach-pit.h| 12 ++ include/configs/s5pc210_universal.h| 3 - include/configs/trats.h| 3 - include/configs/trats2.h | 3 - include/fdtdec.h | 5 + include/power/tps65090_pmic.h | 6 + lib/fdtdec.c | 3 + 30 files changed, 726 insertions(+), 117 deletions(-) create mode 100644 drivers/power/pmic/pmic_tps65090_ec.c create mode 100644 drivers/video/parade.c -- 1.8.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 01/10] exynos_fb: Remove usage of static defines
Previously, we used to statically assign values for vl_col, vl_row and
vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.
Introducing the function exynos_lcd_early_init() would take care of this
assignment on the fly by parsing FIMD DT properties, thereby allowing us
to remove LCD_XRES and LCD_YRES from the main config file.
Signed-off-by: Ajay Kumar
---
arch/arm/include/asm/arch-exynos/system.h | 1 +
board/samsung/common/board.c | 15 +++
drivers/video/exynos_fb.c | 17 +
include/configs/exynos5250-dt.h | 2 --
include/configs/s5pc210_universal.h | 3 ---
include/configs/trats.h | 3 ---
include/configs/trats2.h | 3 ---
7 files changed, 21 insertions(+), 23 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/system.h
b/arch/arm/include/asm/arch-exynos/system.h
index 7e2057c..4968d3d 100644
--- a/arch/arm/include/asm/arch-exynos/system.h
+++ b/arch/arm/include/asm/arch-exynos/system.h
@@ -39,5 +39,6 @@ struct exynos5_sysreg {
void set_usbhost_mode(unsigned int mode);
void set_system_display_ctrl(void);
+int exynos_lcd_early_init(const void *blob);
#endif /* _EXYNOS4_SYSTEM_H */
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 9dc7c83..1f6f0a0 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -148,6 +149,20 @@ int board_early_init_f(void)
board_i2c_init(gd->fdt_blob);
#endif
+#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_EXYNOS_FB)
+/*
+ * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
+ * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix, to reserve
+ * FB memory at a very early stage. So, we need to fill panel_info.vl_col,
+ * panel_info.vl_row and panel_info.vl_bpix before lcd_setmem() is called.
+ */
+ err = exynos_lcd_early_init(gd->fdt_blob);
+ if (err) {
+ debug("LCD early init failed\n");
+ return err;
+ }
+#endif
+
return exynos_early_init_f();
}
#endif
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
index e1e0d80..bc478a9 100644
--- a/drivers/video/exynos_fb.c
+++ b/drivers/video/exynos_fb.c
@@ -27,17 +27,12 @@ DECLARE_GLOBAL_DATA_PTR;
static unsigned int panel_width, panel_height;
-/*
- * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
- * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix to reserve
- * FB memory at a very early stage, i.e even before exynos_fimd_parse_dt()
- * is called. So, we are forced to statically assign it.
- */
#ifdef CONFIG_OF_CONTROL
vidinfo_t panel_info = {
- .vl_col = LCD_XRES,
- .vl_row = LCD_YRES,
- .vl_bpix = LCD_COLOR16,
+ /* Insert a value here so that we don't end up in the BSS
+* Reference: drivers/video/tegra.c
+*/
+ .vl_col = -1,
};
#endif
@@ -141,7 +136,7 @@ static void lcd_panel_on(vidinfo_t *vid)
}
#ifdef CONFIG_OF_CONTROL
-int exynos_fimd_parse_dt(const void *blob)
+int exynos_lcd_early_init(const void *blob)
{
unsigned int node;
node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD);
@@ -286,8 +281,6 @@ void lcd_ctrl_init(void *lcdbase)
set_lcd_clk();
#ifdef CONFIG_OF_CONTROL
- if (exynos_fimd_parse_dt(gd->fdt_blob))
- debug("Can't get proper panel info\n");
#ifdef CONFIG_EXYNOS_MIPI_DSIM
exynos_init_dsim_platform_data(&panel_info);
#endif
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 9d1d56a..86a2570 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -65,8 +65,6 @@
#ifdef CONFIG_LCD
#define CONFIG_EXYNOS_FB
#define CONFIG_EXYNOS_DP
-#define LCD_XRES 2560
-#define LCD_YRES 1600
#define LCD_BPPLCD_COLOR16
#endif
#endif /* __CONFIG_5250_H */
diff --git a/include/configs/s5pc210_universal.h
b/include/configs/s5pc210_universal.h
index eb046cd..20985da 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -247,7 +247,4 @@ int universal_spi_read(void);
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-#define LCD_XRES 480
-#define LCD_YRES 800
-
#endif /* __CONFIG_H */
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 90f1962..35c1feb 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -261,7 +261,4 @@
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-#define LCD_XRES 720
-#define LCD_YRES 1280
-
#endif /* __CONFIG_H */
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 206
[U-Boot] [PATCH 05/10] video: Add driver for Parade PS8625 dP to LVDS bridge
From: Vadim Bendebury
The initialization table comes from the "Illustration of I2C command
for initialing PS8625" document supplied by Parade.
Signed-off-by: Vadim Bendebury
Signed-off-by: Ajay Kumar
---
drivers/video/Makefile | 1 +
drivers/video/parade.c | 220 +
include/fdtdec.h | 1 +
lib/fdtdec.c | 1 +
4 files changed, 223 insertions(+)
create mode 100644 drivers/video/parade.c
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 945f35d..8618590 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -41,3 +41,4 @@ obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
obj-$(CONFIG_VIDEO_TEGRA) += tegra.o
obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
obj-$(CONFIG_FORMIKE) += formike.o
+obj-$(CONFIG_VIDEO_PARADE) += parade.o
diff --git a/drivers/video/parade.c b/drivers/video/parade.c
new file mode 100644
index 000..36e5d80
--- /dev/null
+++ b/drivers/video/parade.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * This file is a driver for Parade dP<->LVDS bridges. The original submission
+ * is for the ps8625 chip.
+ */
+#include
+#include
+#include
+#include
+
+/*
+ * Initialization of the chip is a process of writing certaing values into
+ * certain registers over i2c bus. The chip in fact responds to a range of
+ * addresses on the i2c bus, so for each written value three parameters are
+ * required: i2c address, register address and the actual value.
+ *
+ * The base address is derived from the device tree, only address offset is
+ * stored in the table below.
+ */
+/**
+ * struct reg_data() - data for a parade register write
+ *
+ * @addr_offoffset from the i2c base address for parade
+ * @reg_addrregister address to write
+ * @value value to be written
+ */
+struct reg_data {
+ uint8_t addr_off;
+ uint8_t reg;
+ uint8_t value;
+} _packed;
+
+#define END_OF_TABLE 0xff /* Ficticious offset */
+
+static const struct reg_data parade_values[] = {
+ {0x02, 0xa1, 0x01}, /* HPD low */
+/*
+ * SW setting
+ * [1:0] SW output 1.2V voltage is lower to 96%
+ */
+ {0x04, 0x14, 0x01},
+/*
+ * RCO SS setting
+ * [5:4] = b01 0.5%, b10 1%, b11 1.5%
+ */
+ {0x04, 0xe3, 0x20},
+ {0x04, 0xe2, 0x80}, /* [7] RCO SS enable */
+/*
+ * RPHY Setting
+ * [3:2] CDR tune wait cycle before
+ * measure for fine tune b00: 1us,
+ * 01: 0.5us, 10:2us, 11:4us.
+ */
+ {0x04, 0x8a, 0x0c},
+ {0x04, 0x89, 0x08}, /* [3] RFD always on */
+/*
+ * CTN lock in/out:
+ * 2ppm/8ppm. Lock out 2
+ * times.
+ */
+ {0x04, 0x71, 0x2d},
+/*
+ * 2.7G CDR settings
+ * NOF=40LSB for HBR CDR setting
+ */
+ {0x04, 0x7d, 0x07},
+ {0x04, 0x7b, 0x00}, /* [1:0] Fmin=+4bands */
+ {0x04, 0x7a, 0xfd}, /* [7:5] DCO_FTRNG=+-40% */
+/*
+ * 1.62G CDR settings
+ * [5:2]NOF=64LSB [1:0]DCO scale is 2/5
+ */
+ {0x04, 0xc0, 0x12},
+ {0x04, 0xc1, 0x92}, /* Gitune=-37% */
+ {0x04, 0xc2, 0x1c}, /* Fbstep=100% */
+ {0x04, 0x32, 0x80}, /* [7] LOS signal disable */
+/*
+ * RPIO Setting
+ * [7:4] LVDS driver bias current :
+ * 75% (250mV swing)
+ */
+ {0x04, 0x00, 0xb0},
+/*
+ * [7:6] Right-bar GPIO output strength is 8mA
+ */
+ {0x04, 0x15, 0x40},
+/* EQ Training State Machine Setting */
+ {0x04, 0x54, 0x10}, /* RCO calibration start */
+/* [4:0] MAX_LANE_COUNT set to one lane */
+ {0x01, 0x02, 0x81},
+/* [4:0] LANE_COUNT_SET set to one lane */
+ {0x01, 0x21, 0x81},
+ {0x00, 0x52, 0x20},
+ {0x00, 0xf1, 0x03}, /* HPD CP toggle enable */
+ {0x00, 0x62, 0x41},
+/* Counter number, add 1ms counter delay */
+ {0x00, 0xf6, 0x01},
+/*
+ * [6]PWM function control by
+ * DPCD0040f[7], default is PWM
+ * block always works.
+ */
+ {0x00, 0x77, 0x06},
+/*
+ * 04h Adjust VTotal tolerance to
+ * fix the 30Hz no display issue
+ */
+ {0x00, 0x4c, 0x04},
+/* DPCD00400='h00, Parade OUI = 'h001cf8 */
+ {0x01, 0xc0, 0x00},
+ {0x01, 0xc1, 0x1c}, /* DPCD00401='h1c */
+ {0x01, 0xc2, 0xf8}, /* DPCD00402='hf8 */
+/*
+ * DPCD403~408 = ASCII code
+ * D2SLV5='h4432534c5635
+ */
+ {0x01, 0xc3, 0x44},
+ {0x01, 0xc4, 0x32}, /* DPCD404 */
+ {0x01, 0xc5, 0x53}, /* DPCD405 */
+ {0x01, 0xc6, 0x4c}, /* DPCD406 */
+ {0x01,
