Re: [U-Boot] [PATCH] serial: ns16550: Fix serial output on Tegra186

2016-09-30 Thread Alexandre Courbot 
Hi Paul,

On 09/30/2016 06:47 PM, Paul Burton wrote:
> * PGP Signed by an unknown key
> 
> On Friday, 30 September 2016 17:53:38 BST Alexandre Courbot wrote:
>> On 09/30/2016 05:46 PM, Thierry Reding wrote:
>>> From: Thierry Reding <tred...@nvidia.com>
>>>
>>> For Tegra186 there are currently no UART clocks wired up in device tree.
>>> This exposes a regression introduced in commit 50fce1d5d874 ("serial:
>>> ns16550: Support clocks via phandle"), which causes the p2771--500
>>> board (and probably any Tegra186-based board as well) to fail to boot.
>>>
>>> The reason is that if no clocks property exists, then clk_get_by_index()
>>> returns -ENOENT (via fdtdec_parse_phandle_with_args()) rather than
>>> -ENODEV as the above-mentioned commit expects.
>>>
>>> Fix this by checking for the right error code.
>>
>> Tested-by: Alexandre Courbot <acour...@nvidia.com>
>>
>> I sent a similar patch ~10 minutes before this one, but Thierry's commit
>> message is clearer than mine (and his handling of -ENODEV probably more
>> correct as well), so let's go with this version!
> 
> 
> Hi Thierry & Alexandre,
> 
> Apologies for the breakage!
> 
> If a DT contains a clock & the UART node references it by phandle then I 
> believe clk_get_by_index() could return -ENODEV via 
> uclass_get_device_by_of_offset & uclass_find_device_by_of_offset. So we 
> probably need to handle both -ENOENT for the "no clocks property" case & -
> ENODEV for the "clocks property but no driver" case, as Alexandre's patch 
> does?

But if a DT contains a clock, shouldn't it simply take precedence over
the legacy method? (not very familiar with this code so my comment may
not make sense).

IOW, do we have a case where clk_get_by_index() returns -ENODEV and
fdtdec_get_int() returns a valid clock?
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Re: [U-Boot] [PATCH] serial: ns16550: Fix serial output on Tegra186

2016-09-30 Thread Alexandre Courbot 
On 09/30/2016 05:46 PM, Thierry Reding wrote:
> From: Thierry Reding <tred...@nvidia.com>
> 
> For Tegra186 there are currently no UART clocks wired up in device tree.
> This exposes a regression introduced in commit 50fce1d5d874 ("serial:
> ns16550: Support clocks via phandle"), which causes the p2771--500
> board (and probably any Tegra186-based board as well) to fail to boot.
> 
> The reason is that if no clocks property exists, then clk_get_by_index()
> returns -ENOENT (via fdtdec_parse_phandle_with_args()) rather than
> -ENODEV as the above-mentioned commit expects.
> 
> Fix this by checking for the right error code.

Tested-by: Alexandre Courbot <acour...@nvidia.com>

I sent a similar patch ~10 minutes before this one, but Thierry's commit
message is clearer than mine (and his handling of -ENODEV probably more
correct as well), so let's go with this version!
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Re: [U-Boot] [PATCH] serial: ns16550: Handle -ENOENT when requesting clock

2016-09-30 Thread Alexandre Courbot 
On 09/30/2016 05:37 PM, Alexandre Courbot wrote:
> When calling clk_get_by_index(), fall back to the legacy method of
> getting the clock if -ENOENT is returned.

Withdrawing this patch as Thierry sent a better version of it.

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[U-Boot] [PATCH] serial: ns16550: Handle -ENOENT when requesting clock

2016-09-30 Thread Alexandre Courbot 
When calling clk_get_by_index(), fall back to the legacy method of
getting the clock if -ENOENT is returned.

Signed-off-by: Alexandre Courbot <acour...@nvidia.com>
---
 drivers/serial/ns16550.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 765499dab646..29d547166b90 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -408,7 +408,7 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
err = clk_get_rate();
if (!IS_ERR_VALUE(err))
plat->clock = err;
-   } else if (err != -ENODEV && err != -ENOSYS) {
+   } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
debug("ns16550 failed to get clock\n");
return err;
}
-- 
2.10.0

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Re: [U-Boot] [PATCH] ARM: tegra: enable GPU node by compatible value

2016-04-12 Thread Alexandre Courbot 

On 04/13/2016 02:17 AM, Stephen Warren wrote:

From: Stephen Warren <swar...@nvidia.com>

In current Linux kernel Tegra DT files, 64-bit addresses are represented
in unit addresses as a pair of comma-separated 32-bit values. Apparently
this is no longer the correct representation for simple busses, and the
unit address should be represented as a single 64-bit value. If this is
changed in the DTs, arm/arm/mach-tegra/board2.c:ft_system_setup() will no
longer be able to find and enable the GPU node, since it looks up the node
by name.

Fix that function to enable nodes based on their compatible value rather
than their node name. This will work no matter what the node name is, i.e
for DTs both before and after any rename operation.


Generally speaking it is also much better to do it that way. Thanks!

Acked-by: Alexandre Courbot <acour...@nvidia.com>

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Re: [U-Boot] [PATCH 0/4] ARM: tegra: GPU WPR region support

2015-10-28 Thread Alexandre Courbot 
On Wed, Oct 28, 2015 at 12:57 AM, Tom Warren <twar...@nvidia.com> wrote:
> Sorry, Alex. Missed these.
>
>> -Original Message-
>> From: Alexandre Courbot [mailto:gnu...@gmail.com]
>> Sent: Sunday, October 25, 2015 10:50 PM
>> To: Alex Courbot <acour...@nvidia.com>
>> Cc: Tom Warren <twar...@nvidia.com>; Stephen Warren
>> <swar...@nvidia.com>; Thierry Reding <tred...@nvidia.com>; u-
>> b...@lists.denx.de; linux-te...@vger.kernel.org
>> Subject: Re: [PATCH 0/4] ARM: tegra: GPU WPR region support
>>
>> Ping Tom, how does this look to you?
> Looks pretty good, but what about saving the security_carveout reg settings 
> back to the BCT or scratch regs so those settings will be restored on LP0 
> resume?

Absolutely - I am not familiar at all with BCT or scratch registers
(and U-boot in general :) ) though, could you point me to some part of
the code which I could use as a reference for this?

Also, how can I decide which mechanism to use over the other?

Thanks,
Alex.
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Re: [U-Boot] [PATCH 4/4] ARM: tegra210: gpu: configure WPR region

2015-10-28 Thread Alexandre Courbot 

On 10/29/2015 02:59 AM, Stephen Warren wrote:

On 10/18/2015 10:57 PM, Alexandre Courbot wrote:

T210's GPU secure firmware loading requires a write-protected region
to be set up.

This patch reserves the upper 256KB of RAM as the WPR region and locks
it so the kernel can initiate secure firmware loading.


On T210, it's the responsibility of nvtboot (which runs before U-Boot)
to set up any and all carve-outs. This code should not be necessary, and
indeed I expect the registers it touches can't actually be programmed
from U-Boot, which runs in non-secure mode after WPR is already locked.


Ok, I was running from Thierry's miniloader which did not program or 
lock these registers.


The question then is: do we have an official nvtboot binary available 
for upstream support? AFAICT Thierry's miniloader solution is the only 
solution available to the public, and without this setup one cannot use 
the GPU on T210.

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Re: [U-Boot] [PATCH 0/4] ARM: tegra: GPU WPR region support

2015-10-26 Thread Alexandre Courbot 
Ping Tom, how does this look to you?

On Mon, Oct 19, 2015 at 1:57 PM, Alexandre Courbot <acour...@nvidia.com> wrote:
> This series makes U-boot program the write-protected (WPR) region of T210 
> chips,
> allowing the kernel to perform GPU secure firmware loading.
>
> Tegra 210's GPU requires its firmware to be loaded though a write-protected
> region. An area of physical memory is carved-out, programmed into the
> corresponding memory controller registers, and locked such as only the GPU can
> write into it. This area needs to be set up by the bootloader since it cannot
> be re-claimed for normal use after being locked.
>
> The first 3 patches of this series are cleanup patches. Patch 2 implements a
> suggestion made by Stephen, patch 3 renames GPU-related functions to sound 
> less
> generic.
>
> The last patch adds support for the GPU WPR region. The top 256KB of memory 
> are
> removed from the available memory, and the corresponding MC registers are
> programmed to point to it, which allows the kernel to initiate secure firmware
> loading.
>
> Alexandre Courbot (4):
>   ARM: tegra: remove vpr_configured() function
>   ARM: tegra: simplify GPU setup
>   ARM: tegra: rename GPU functions
>   ARM: tegra210: gpu: configure WPR region
>
>  arch/arm/include/asm/arch-tegra/gpu.h   | 14 +++--
>  arch/arm/include/asm/arch-tegra210/mc.h | 12 
>  arch/arm/mach-tegra/board.c |  4 +++
>  arch/arm/mach-tegra/board2.c| 22 +-
>  arch/arm/mach-tegra/gpu.c   | 52 
> +
>  board/nvidia/jetson-tk1/jetson-tk1.c|  8 -
>  board/nvidia/p2571/p2571.c  |  7 -
>  board/nvidia/venice2/venice2.c  |  8 -
>  include/configs/jetson-tk1.h|  2 --
>  include/configs/p2571.h |  2 --
>  include/configs/tegra-common.h  |  2 ++
>  include/configs/venice2.h   |  2 --
>  12 files changed, 89 insertions(+), 46 deletions(-)
>
> --
> 2.6.1
>
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[U-Boot] [PATCH 4/4] ARM: tegra210: gpu: configure WPR region

2015-10-18 Thread Alexandre Courbot 
T210's GPU secure firmware loading requires a write-protected region
to be set up.

This patch reserves the upper 256KB of RAM as the WPR region and locks
it so the kernel can initiate secure firmware loading.

Signed-off-by: Alexandre Courbot <acour...@nvidia.com>
---
 arch/arm/include/asm/arch-tegra210/mc.h | 12 +
 arch/arm/mach-tegra/board.c |  4 +++
 arch/arm/mach-tegra/gpu.c   | 47 -
 3 files changed, 62 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-tegra210/mc.h 
b/arch/arm/include/asm/arch-tegra210/mc.h
index 77e9aa51f60f..e6d1758d372f 100644
--- a/arch/arm/include/asm/arch-tegra210/mc.h
+++ b/arch/arm/include/asm/arch-tegra210/mc.h
@@ -62,6 +62,16 @@ struct mc_ctlr {
u32 mc_video_protect_bom;   /* offset 0x648 */
u32 mc_video_protect_size_mb;   /* offset 0x64c */
u32 mc_video_protect_reg_ctrl;  /* offset 0x650 */
+   u32 reserved11[385];/* offset 0x654 - 0xc54 */
+   u32 mc_security_carveout2_cfg0; /* offset 0xc58 */
+   u32 mc_security_carveout2_bom;  /* offset 0xc5c */
+   u32 mc_security_carveout2_bom_hi;   /* offset 0xc60 */
+   u32 mc_security_carveout2_size_128k;/* offset 0xc64 */
+   u32 reserved12[16]; /* offset 0xc68 - 0xca4 */
+   u32 mc_security_carveout3_cfg0; /* offset 0xca8 */
+   u32 mc_security_carveout3_bom;  /* offset 0xcac */
+   u32 mc_security_carveout3_bom_hi;   /* offset 0xcb0 */
+   u32 mc_security_carveout3_size_128k;/* offset 0xcb4 */
 };
 
 #define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0)
@@ -69,4 +79,6 @@ struct mc_ctlr {
 #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED(0 << 0)
 #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED   (1 << 0)
 
+#define TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED  (1 << 1)
+
 #endif /* _TEGRA210_MC_H_ */
diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index b00e4b5c1e25..0bff063b00f4 100644
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -111,6 +111,10 @@ static phys_size_t query_sdram_size(void)
if (size_bytes == SZ_2G)
size_bytes -= SZ_1M;
 #endif
+#if defined(CONFIG_TEGRA210)
+   /* Reserve GPU WPR area, 2 * 128KB */
+   size_bytes = round_down(size_bytes - (SZ_128K * 2), SZ_128K);
+#endif
 
return size_bytes;
 }
diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c
index c7d705d8efe9..61d734fd5767 100644
--- a/arch/arm/mach-tegra/gpu.c
+++ b/arch/arm/mach-tegra/gpu.c
@@ -23,9 +23,11 @@
 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static bool _configured;
 
-void tegra_gpu_config(void)
+static void config_vpr(void)
 {
struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
 
@@ -37,6 +39,49 @@ void tegra_gpu_config(void)
readl(>mc_video_protect_reg_ctrl);
 
debug("configured VPR\n");
+}
+
+#if defined(CONFIG_TEGRA210)
+static void config_wpr(void)
+{
+   struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
+   u64 wpr_start = NV_PA_SDRAM_BASE + gd->ram_size;
+   u32 reg;
+
+   /*
+* Carveout2 uses the upper 256KB of upper memory that we reserved as
+* WPR region for secure firmware loading
+*/
+   writel(lower_32_bits(wpr_start), >mc_security_carveout2_bom);
+   writel(upper_32_bits(wpr_start), >mc_security_carveout2_bom_hi);
+   writel(0x2, >mc_security_carveout2_size_128k);
+   reg = readl(>mc_security_carveout2_cfg0);
+   reg |= TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED;
+   writel(reg, >mc_security_carveout2_cfg0);
+
+   /* Carveout3 is left empty */
+   writel(0x0, >mc_security_carveout3_bom);
+   writel(0x0, >mc_security_carveout3_bom_hi);
+   writel(0x0, >mc_security_carveout3_size_128k);
+   reg = readl(>mc_security_carveout3_cfg0);
+   reg |= TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED;
+   writel(reg, >mc_security_carveout3_cfg0);
+
+   /* read back to ensure the write went through */
+   readl(>mc_security_carveout3_cfg0);
+
+   debug("configured WPR\n");
+}
+#else
+static inline void config_wpr(void)
+{
+}
+#endif
+
+void tegra_gpu_config(void)
+{
+   config_vpr();
+   config_wpr();
 
_configured = true;
 }
-- 
2.6.1

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[U-Boot] [PATCH 2/4] ARM: tegra: simplify GPU setup

2015-10-18 Thread Alexandre Courbot 
Enable the GPU node in the system-wide ft_system_setup() hook instead of
the board-specific ft_board_hook(). This allows us to enable GPU per SoC
generation instead of per-board as we did initially.

Reported-by: Stephen Warren <swar...@nvidia.com>
Signed-off-by: Alexandre Courbot <acour...@nvidia.com>
---
 arch/arm/mach-tegra/board2.c | 20 
 board/nvidia/jetson-tk1/jetson-tk1.c |  8 
 board/nvidia/p2571/p2571.c   |  7 ---
 board/nvidia/venice2/venice2.c   |  8 
 include/configs/jetson-tk1.h |  2 --
 include/configs/p2571.h  |  2 --
 include/configs/tegra-common.h   |  2 ++
 include/configs/venice2.h|  2 --
 8 files changed, 22 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 8ecc67459a10..ff9e77cfa3a3 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -403,3 +403,23 @@ ulong board_get_usable_ram_top(ulong total_size)
 {
return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
 }
+
+/*
+ * This function is called right before the kernel is booted. "blob" is the
+ * device tree that will be passed to the kernel.
+ */
+int ft_system_setup(void *blob, bd_t *bd)
+{
+   const char *gpu_path =
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
+   "/gpu@0,5700";
+#else
+   NULL;
+#endif
+
+   /* Enable GPU node if GPU setup has been performed */
+   if (gpu_path != NULL)
+   return gpu_enable_node(blob, gpu_path);
+
+   return 0;
+}
diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c 
b/board/nvidia/jetson-tk1/jetson-tk1.c
index 3c21767ce4da..52425a8f6dea 100644
--- a/board/nvidia/jetson-tk1/jetson-tk1.c
+++ b/board/nvidia/jetson-tk1/jetson-tk1.c
@@ -11,7 +11,6 @@
 
 #include 
 #include 
-#include 
 
 #include "pinmux-config-jetson-tk1.h"
 
@@ -80,10 +79,3 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);
 }
 #endif /* PCI */
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-   gpu_enable_node(blob, "/gpu@0,5700");
-
-   return 0;
-}
diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c
index d33e4d12b2fa..d80a7d0d3e31 100644
--- a/board/nvidia/p2571/p2571.c
+++ b/board/nvidia/p2571/p2571.c
@@ -11,7 +11,6 @@
 #include 
 #include 
 #include "max77620_init.h"
-#include 
 #include "pinmux-config-p2571.h"
 
 void pin_mux_mmc(void)
@@ -62,9 +61,3 @@ void start_cpu_fan(void)
gpio_request(GPIO_PE4, "FAN_VDD");
gpio_direction_output(GPIO_PE4, 1);
 }
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-   gpu_enable_node(blob, "/gpu@0,5700");
-   return 0;
-}
diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c
index 3e2b9a7745e9..c56ef129d6c7 100644
--- a/board/nvidia/venice2/venice2.c
+++ b/board/nvidia/venice2/venice2.c
@@ -8,7 +8,6 @@
 #include 
 #include 
 #include 
-#include 
 #include "pinmux-config-venice2.h"
 
 /*
@@ -28,10 +27,3 @@ void pinmux_init(void)
pinmux_config_drvgrp_table(venice2_drvgrps,
   ARRAY_SIZE(venice2_drvgrps));
 }
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-   gpu_enable_node(blob, "/gpu@0,5700");
-
-   return 0;
-}
diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h
index e87a01047d30..f63957ab92fd 100644
--- a/include/configs/jetson-tk1.h
+++ b/include/configs/jetson-tk1.h
@@ -78,6 +78,4 @@
 #define CONFIG_ARMV7_SECURE_BASE   0xfff0
 #define CONFIG_ARMV7_SECURE_RESERVE_SIZE   0x0010
 
-#define CONFIG_OF_BOARD_SETUP
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/p2571.h b/include/configs/p2571.h
index c65d3e5fcbc1..a5de411121b0 100644
--- a/include/configs/p2571.h
+++ b/include/configs/p2571.h
@@ -60,6 +60,4 @@
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
 
-#define CONFIG_OF_BOARD_SETUP
-
 #endif /* _P2571_H */
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 1c469d092e8c..9f0d4644431a 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -144,4 +144,6 @@
 #define CONFIG_FAT_WRITE
 #endif
 
+#define CONFIG_OF_SYSTEM_SETUP
+
 #endif /* _TEGRA_COMMON_H_ */
diff --git a/include/configs/venice2.h b/include/configs/venice2.h
index 0fc8cf7674d1..a374cd948849 100644
--- a/include/configs/venice2.h
+++ b/include/configs/venice2.h
@@ -60,6 +60,4 @@
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
 
-#define CONFIG_OF_BOARD_SETUP
-
 #endif /* __CONFIG_H */
-- 
2.6.1

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[U-Boot] [PATCH 3/4] ARM: tegra: rename GPU functions

2015-10-18 Thread Alexandre Courbot 
Rename GPU functions to less generic names to avoid potential name
collisions.

Signed-off-by: Alexandre Courbot <acour...@nvidia.com>
---
 arch/arm/include/asm/arch-tegra/gpu.h | 8 
 arch/arm/mach-tegra/board2.c  | 4 ++--
 arch/arm/mach-tegra/gpu.c | 4 ++--
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/arch-tegra/gpu.h 
b/arch/arm/include/asm/arch-tegra/gpu.h
index 2fdb2c5049e6..4423386f2805 100644
--- a/arch/arm/include/asm/arch-tegra/gpu.h
+++ b/arch/arm/include/asm/arch-tegra/gpu.h
@@ -10,11 +10,11 @@
 
 #if defined(CONFIG_TEGRA_GPU)
 
-void config_gpu(void);
+void tegra_gpu_config(void);
 
 #else /* CONFIG_TEGRA_GPU */
 
-static inline void config_gpu(void)
+static inline void tegra_gpu_config(void)
 {
 }
 
@@ -22,11 +22,11 @@ static inline void config_gpu(void)
 
 #if defined(CONFIG_OF_LIBFDT)
 
-int gpu_enable_node(void *blob, const char *gpupath);
+int tegra_gpu_enable_node(void *blob, const char *gpupath);
 
 #else /* CONFIG_OF_LIBFDT */
 
-static inline int gpu_enable_node(void *blob, const char *gpupath)
+static inline int tegra_gpu_enable_node(void *blob, const char *gpupath)
 {
return 0;
 }
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index ff9e77cfa3a3..8ba143d996ca 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -128,7 +128,7 @@ int board_init(void)
clock_init();
clock_verify();
 
-   config_gpu();
+   tegra_gpu_config();
 
 #ifdef CONFIG_TEGRA_SPI
pin_mux_spi();
@@ -419,7 +419,7 @@ int ft_system_setup(void *blob, bd_t *bd)
 
/* Enable GPU node if GPU setup has been performed */
if (gpu_path != NULL)
-   return gpu_enable_node(blob, gpu_path);
+   return tegra_gpu_enable_node(blob, gpu_path);
 
return 0;
 }
diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c
index dc29b79e0126..c7d705d8efe9 100644
--- a/arch/arm/mach-tegra/gpu.c
+++ b/arch/arm/mach-tegra/gpu.c
@@ -25,7 +25,7 @@
 
 static bool _configured;
 
-void config_gpu(void)
+void tegra_gpu_config(void)
 {
struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
 
@@ -43,7 +43,7 @@ void config_gpu(void)
 
 #if defined(CONFIG_OF_LIBFDT)
 
-int gpu_enable_node(void *blob, const char *gpupath)
+int tegra_gpu_enable_node(void *blob, const char *gpupath)
 {
int offset;
 
-- 
2.6.1

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[U-Boot] [PATCH 1/4] ARM: tegra: remove vpr_configured() function

2015-10-18 Thread Alexandre Courbot 
There is no justification for this function, especially in exported
form.

Signed-off-by: Alexandre Courbot <acour...@nvidia.com>
---
 arch/arm/include/asm/arch-tegra/gpu.h | 6 --
 arch/arm/mach-tegra/gpu.c | 7 +--
 2 files changed, 1 insertion(+), 12 deletions(-)

diff --git a/arch/arm/include/asm/arch-tegra/gpu.h 
b/arch/arm/include/asm/arch-tegra/gpu.h
index 52280f40ce31..2fdb2c5049e6 100644
--- a/arch/arm/include/asm/arch-tegra/gpu.h
+++ b/arch/arm/include/asm/arch-tegra/gpu.h
@@ -11,7 +11,6 @@
 #if defined(CONFIG_TEGRA_GPU)
 
 void config_gpu(void);
-bool gpu_configured(void);
 
 #else /* CONFIG_TEGRA_GPU */
 
@@ -19,11 +18,6 @@ static inline void config_gpu(void)
 {
 }
 
-static inline bool gpu_configured(void)
-{
-   return false;
-}
-
 #endif /* CONFIG_TEGRA_GPU */
 
 #if defined(CONFIG_OF_LIBFDT)
diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c
index 4ea046d3e5b6..dc29b79e0126 100644
--- a/arch/arm/mach-tegra/gpu.c
+++ b/arch/arm/mach-tegra/gpu.c
@@ -41,18 +41,13 @@ void config_gpu(void)
_configured = true;
 }
 
-bool vpr_configured(void)
-{
-   return _configured;
-}
-
 #if defined(CONFIG_OF_LIBFDT)
 
 int gpu_enable_node(void *blob, const char *gpupath)
 {
int offset;
 
-   if (vpr_configured()) {
+   if (_configured) {
offset = fdt_path_offset(blob, gpupath);
if (offset > 0) {
fdt_status_okay(blob, offset);
-- 
2.6.1

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[U-Boot] [PATCH 0/4] ARM: tegra: GPU WPR region support

2015-10-18 Thread Alexandre Courbot 
This series makes U-boot program the write-protected (WPR) region of T210 chips,
allowing the kernel to perform GPU secure firmware loading.

Tegra 210's GPU requires its firmware to be loaded though a write-protected
region. An area of physical memory is carved-out, programmed into the
corresponding memory controller registers, and locked such as only the GPU can
write into it. This area needs to be set up by the bootloader since it cannot
be re-claimed for normal use after being locked.

The first 3 patches of this series are cleanup patches. Patch 2 implements a
suggestion made by Stephen, patch 3 renames GPU-related functions to sound less
generic.

The last patch adds support for the GPU WPR region. The top 256KB of memory are
removed from the available memory, and the corresponding MC registers are
programmed to point to it, which allows the kernel to initiate secure firmware
loading.

Alexandre Courbot (4):
  ARM: tegra: remove vpr_configured() function
  ARM: tegra: simplify GPU setup
  ARM: tegra: rename GPU functions
  ARM: tegra210: gpu: configure WPR region

 arch/arm/include/asm/arch-tegra/gpu.h   | 14 +++--
 arch/arm/include/asm/arch-tegra210/mc.h | 12 
 arch/arm/mach-tegra/board.c |  4 +++
 arch/arm/mach-tegra/board2.c| 22 +-
 arch/arm/mach-tegra/gpu.c   | 52 +
 board/nvidia/jetson-tk1/jetson-tk1.c|  8 -
 board/nvidia/p2571/p2571.c  |  7 -
 board/nvidia/venice2/venice2.c  |  8 -
 include/configs/jetson-tk1.h|  2 --
 include/configs/p2571.h |  2 --
 include/configs/tegra-common.h  |  2 ++
 include/configs/venice2.h   |  2 --
 12 files changed, 89 insertions(+), 46 deletions(-)

-- 
2.6.1

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Re: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node

2015-08-06 Thread Alexandre Courbot 

On 08/05/2015 08:24 AM, Tom Warren wrote:

Alex/Andreas,


-Original Message-
From: Tom Warren
Sent: Tuesday, August 04, 2015 8:41 AM
To: 'Andreas Färber'; u-boot@lists.denx.de
Cc: Alex Courbot; linux-te...@vger.kernel.org; gnu...@gmail.com; Stephen
Warren; Guillaume Gardet
Subject: RE: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node

Andreas,


-Original Message-
From: Andreas Färber [mailto:afaer...@suse.de]
Sent: Tuesday, August 04, 2015 6:56 AM
To: u-boot@lists.denx.de
Cc: Alex Courbot; linux-te...@vger.kernel.org; gnu...@gmail.com;
Stephen Warren; Tom Warren; Guillaume Gardet
Subject: Re: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node

Am 23.07.2015 um 13:46 schrieb Andreas Färber:

Am 09.07.2015 um 09:32 schrieb Alexandre Courbot:

Tegra124 requires the bootloader to perform VPR initialization,
otherwise the GPU cannot be used by the system. Since using the GPU
without that initialization results in a hang, the GPU DT node is
left disabled, and it is the task of the bootloader to enable it
after ensuring it is safe to use the GPU.

VPR init is already performed since patch df3443dfa449, but the
device tree was left untouched. This patch series performs this
last step and prepares the GPU intialization code to receive more
code for

newer chips.


Tested-by: Andreas Färber afaer...@suse.de

I've tested this patchset on v2015.07 with 4.2.0-rc3-00115-gc5dfd65
- with these two patches I get a console login on HDMI again.


Ping! Independent of the Linux and X11 discussions this thread has
drifted off into, these two patches are still missing in v2015.10-rc1
and don't apply any more (as reported by Guillaume). Can you please rebase

and merge them?
Is that request for me? Sorry, lost track of these patches since it appeared 
that
there was an on-going discussion.
If you're sure they're OK within the context of Tegra U-Boot, I'll apply them 
and
send them with the next PR.

Tom

Applied to u-boot-tegra/next (along with some other pending Tegra patches for 
clocks/PLL/SPI/ums/etc.). I added T210/P2571 support to this patchset.

PTAL.  Also, there doesn't appear to be a 'gpu@0,5700' property in any 
t124/t210 DT file. Is that coming in another patch or one I missed?


Thanks Tom! I have tried your branch and can confirm it is booting 
Jetson TK1 as expected (i.e. the GPU is in a usable state).


The GPU node is not needed in U-boot's DT files (if that's what you 
meant). It is present in the kernel though, and that's the DT my patches 
will modify.


Alex.
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Re: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node

2015-08-04 Thread Alexandre Courbot 

On 07/24/2015 10:07 PM, Peter Robinson wrote:

Hi,


Tegra124 requires the bootloader to perform VPR initialization, otherwise the
GPU cannot be used by the system. Since using the GPU without that
initialization results in a hang, the GPU DT node is left disabled, and it is
the task of the bootloader to enable it after ensuring it is safe to use the
GPU.

VPR init is already performed since patch df3443dfa449, but the device tree was
left untouched. This patch series performs this last step and prepares the GPU
intialization code to receive more code for newer chips.


Tested-by: Andreas Färber afaer...@suse.de

I've tested this patchset on v2015.07 with 4.2.0-rc3-00115-gc5dfd65 -
with these two patches I get a console login on HDMI again.

However, I'm still having trouble with X11... Should that be working
with linux.git? (haven't tried linux-next.git yet)


My understanding is that it's not or you need  to use glamour to do
so, wayland in theory should work.


Among other errors, it seems that nouveau is looking for firmware
nouveau/nvea_fuc409c and nouveau/fuc409c - who should be providing that?
It's not in linux-firmware.git [1], and I see no /dev/mmcblk0p* to check
whether the original system has such a file (which I doubt, given the
nouveau naming). It then falls back to the tegra drm iiuc.


Details of the changes with firmware loading in this patch series
here, likely need the patches, or maybe newer ones for it to work:
http://www.spinics.net/lists/dri-devel/msg84828.html

Firmware landed upstream here:
https://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/commit/?id=899ebcb6812681b91cf2dfd390574b478c612442


With -rc2 I've seen the system freeze, with -rc3 just not behaving as
expected when starting X (with ssh/serial remaining usable).


Without the above patchset I've seen the lockups too.


Sorry for the delayed reply.

As Peter mentioned, the correct firmware files have landed in 
linux-firmware, and the loading code using the right paths is in 
Nouveau. It may not have landed in Linux mainline yet, so for the moment 
I recommend to use https://github.com/Gnurou/linux/tree/staging/nouveau 
(can probably be merged into any recent kernel tree) for the kernel and 
https://github.com/Gnurou/nouveau/tree/staging for Nouveau. This will 
require Nouveau to be loaded as a module.


As for X, there are two issues to be addressed:

1) The display and render functions are performed by two different DRI 
nodes, and two different drivers (tegradrm for display, nouveau for 
render). I suspect the fastest path towards X acceleration is to use the 
modesetting driver + GLamor. It may require some changes to handle the 
two different nodes. Modesetting without GLamor should just work, in any 
case. I really should have a look at this sometime but am hoping someone 
else will pick that low-hanging fruit. :)


2) Buffers generated by Nouveau use a tiling mode that tegradrm can 
understand, but it needs to be told about it through a dedicated IOCTL. 
Without this, buffers would need to be copied into linear buffers before 
sharing, which would be suboptimal. The kmscube repository linked by 
Mikko includes the code to do that.


Note that Nouveau's DDX can also somehow work with this patch:

http://comments.gmane.org/gmane.comp.freedesktop.xorg.nouveau/20101

However, I think modesetting + GLamor is the way to do, especially since 
the DDX solution cannot currently work with the Maxwell GPUs found in 
Tegra X1 (whereas GLamor should provide acceleration).


In any case, I would be very interested to hear about progress with 
getting X on Tegra K1. I don't think the effort required is too big.


Good luck!
Alex.
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[U-Boot] [PATCH 2/2] ARM: tegra: enable GPU DT node when appropriate

2015-07-09 Thread Alexandre Courbot 
T124 requires some specific configuration (VPR setup) to be performed by
the bootloader before the GPU can be used. For this reason, the GPU node
in the device tree is disabled by default. This patch enables the node
if U-boot has performed VPR configuration.

Boards enabled by this patch are T124's Jetson TK1 and Venice 2.

Signed-off-by: Alexandre Courbot acour...@nvidia.com
Cc: Stephen Warren swar...@nvidia.com
Cc: Tom Warren twar...@nvidia.com
---
 arch/arm/include/asm/arch-tegra/gpu.h | 16 
 arch/arm/mach-tegra/gpu.c | 19 +++
 board/nvidia/jetson-tk1/jetson-tk1.c  |  8 
 board/nvidia/venice2/venice2.c|  8 
 include/configs/jetson-tk1.h  |  2 ++
 include/configs/venice2.h |  2 ++
 6 files changed, 55 insertions(+)

diff --git a/arch/arm/include/asm/arch-tegra/gpu.h 
b/arch/arm/include/asm/arch-tegra/gpu.h
index b347a21835f5..eac73ed5fddf 100644
--- a/arch/arm/include/asm/arch-tegra/gpu.h
+++ b/arch/arm/include/asm/arch-tegra/gpu.h
@@ -25,3 +25,19 @@ static inline bool gpu_configured(void)
 }
 
 #endif /* CONFIG_TEGRA_GPU */
+
+
+#if defined(CONFIG_OF_LIBFDT)
+
+int gpu_enable_node(void *blob, const char *gpupath);
+
+#else /* CONFIG_OF_LIBFDT */
+
+static inline int gpu_enable_node(void *blob, const char *gpupath)
+{
+   return 0;
+}
+
+#endif /* CONFIG_OF_LIBFDT */
+
+#endif
diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c
index b2fa50b5400e..4ea046d3e5b6 100644
--- a/arch/arm/mach-tegra/gpu.c
+++ b/arch/arm/mach-tegra/gpu.c
@@ -45,3 +45,22 @@ bool vpr_configured(void)
 {
return _configured;
 }
+
+#if defined(CONFIG_OF_LIBFDT)
+
+int gpu_enable_node(void *blob, const char *gpupath)
+{
+   int offset;
+
+   if (vpr_configured()) {
+   offset = fdt_path_offset(blob, gpupath);
+   if (offset  0) {
+   fdt_status_okay(blob, offset);
+   debug(enabled GPU node %s\n, gpupath);
+   }
+   }
+
+   return 0;
+}
+
+#endif
diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c 
b/board/nvidia/jetson-tk1/jetson-tk1.c
index 52425a8f6dea..3c21767ce4da 100644
--- a/board/nvidia/jetson-tk1/jetson-tk1.c
+++ b/board/nvidia/jetson-tk1/jetson-tk1.c
@@ -11,6 +11,7 @@
 
 #include asm/arch/gpio.h
 #include asm/arch/pinmux.h
+#include asm/arch-tegra/gpu.h
 
 #include pinmux-config-jetson-tk1.h
 
@@ -79,3 +80,10 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);
 }
 #endif /* PCI */
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+   gpu_enable_node(blob, /gpu@0,5700);
+
+   return 0;
+}
diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c
index c56ef129d6c7..3e2b9a7745e9 100644
--- a/board/nvidia/venice2/venice2.c
+++ b/board/nvidia/venice2/venice2.c
@@ -8,6 +8,7 @@
 #include common.h
 #include asm/arch/gpio.h
 #include asm/arch/pinmux.h
+#include asm/arch-tegra/gpu.h
 #include pinmux-config-venice2.h
 
 /*
@@ -27,3 +28,10 @@ void pinmux_init(void)
pinmux_config_drvgrp_table(venice2_drvgrps,
   ARRAY_SIZE(venice2_drvgrps));
 }
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+   gpu_enable_node(blob, /gpu@0,5700);
+
+   return 0;
+}
diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h
index 3bbff282df27..b3e649664508 100644
--- a/include/configs/jetson-tk1.h
+++ b/include/configs/jetson-tk1.h
@@ -82,4 +82,6 @@
 #define CONFIG_ARMV7_SECURE_BASE   0xfff0
 #define CONFIG_ARMV7_SECURE_RESERVE_SIZE   0x0010
 
+#define CONFIG_OF_BOARD_SETUP
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/venice2.h b/include/configs/venice2.h
index 1d9d053b3566..bc5080aa27f0 100644
--- a/include/configs/venice2.h
+++ b/include/configs/venice2.h
@@ -64,4 +64,6 @@
 #include tegra-common-usb-gadget.h
 #include tegra-common-post.h
 
+#define CONFIG_OF_BOARD_SETUP
+
 #endif /* __CONFIG_H */
-- 
2.4.4

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[U-Boot] [PATCH 1/2] ARM: tegra: move VPR configuration to a later stage

2015-07-09 Thread Alexandre Courbot 
U-boot is responsible for enabling the GPU DT node after all necessary
configuration (VPR setup for T124) is performed. In order to be able to
check whether this configuration has been performed right before booting
the kernel, make it happen during board_init().

Also move VPR configuration into the more generic gpu.c file, which will
also host other GPU-related functions, and let boards specify
individually whether they need VPR setup or not.

Signed-off-by: Alexandre Courbot acour...@nvidia.com
Cc: Stephen Warren swar...@nvidia.com
Cc: Tom Warren twar...@nvidia.com
---
 arch/arm/include/asm/arch-tegra/ap.h  |  9 ---
 arch/arm/include/asm/arch-tegra/gpu.h | 27 
 arch/arm/mach-tegra/Makefile  |  2 +-
 arch/arm/mach-tegra/ap.c  |  3 ---
 arch/arm/mach-tegra/board2.c  |  3 +++
 arch/arm/mach-tegra/gpu.c | 47 +++
 arch/arm/mach-tegra/vpr.c | 35 --
 include/configs/tegra124-common.h |  3 +++
 8 files changed, 81 insertions(+), 48 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-tegra/gpu.h
 create mode 100644 arch/arm/mach-tegra/gpu.c
 delete mode 100644 arch/arm/mach-tegra/vpr.c

diff --git a/arch/arm/include/asm/arch-tegra/ap.h 
b/arch/arm/include/asm/arch-tegra/ap.h
index ca40e4e0bce6..2d58271e39f9 100644
--- a/arch/arm/include/asm/arch-tegra/ap.h
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -66,15 +66,6 @@ int tegra_get_sku_info(void);
 /* Do any chip-specific cache config */
 void config_cache(void);
 
-#if defined(CONFIG_TEGRA124)
-/* Do chip-specific vpr config */
-void config_vpr(void);
-#else
-static inline void config_vpr(void)
-{
-}
-#endif
-
 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
 bool tegra_cpu_is_non_secure(void);
 #endif
diff --git a/arch/arm/include/asm/arch-tegra/gpu.h 
b/arch/arm/include/asm/arch-tegra/gpu.h
new file mode 100644
index ..b347a21835f5
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/gpu.h
@@ -0,0 +1,27 @@
+/*
+ *  (C) Copyright 2015
+ *  NVIDIA Corporation www.nvidia.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_TEGRA_GPU_H
+#define __ASM_ARCH_TEGRA_GPU_H
+
+#if defined(CONFIG_TEGRA_GPU)
+
+void config_gpu(void);
+bool gpu_configured(void);
+
+#else /* CONFIG_TEGRA_GPU */
+
+static inline void config_gpu(void)
+{
+}
+
+static inline bool gpu_configured(void)
+{
+   return false;
+}
+
+#endif /* CONFIG_TEGRA_GPU */
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index fefc180b130e..f6f5583d6dd1 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -24,7 +24,7 @@ obj-y += pinmux-common.o
 obj-y += powergate.o
 obj-y += xusb-padctl.o
 obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
-obj-$(CONFIG_TEGRA124) += vpr.o
+obj-$(CONFIG_TEGRA_GPU) += gpu.o
 obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
 
 ifndef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c
index 0b94e8aaf9c3..70613f9c3649 100644
--- a/arch/arm/mach-tegra/ap.c
+++ b/arch/arm/mach-tegra/ap.c
@@ -218,7 +218,4 @@ void s_init(void)
 
/* enable SMMU */
smmu_enable();
-
-   /* init vpr */
-   config_vpr();
 }
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index ce9b6959efb1..1d7c5eff5587 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -29,6 +29,7 @@
 #include asm/arch-tegra/sys_proto.h
 #include asm/arch-tegra/uart.h
 #include asm/arch-tegra/warmboot.h
+#include asm/arch-tegra/gpu.h
 #ifdef CONFIG_TEGRA_CLOCK_SCALING
 #include asm/arch/emc.h
 #endif
@@ -125,6 +126,8 @@ int board_init(void)
clock_init();
clock_verify();
 
+   config_gpu();
+
 #ifdef CONFIG_TEGRA_SPI
pin_mux_spi();
 #endif
diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c
new file mode 100644
index ..b2fa50b5400e
--- /dev/null
+++ b/arch/arm/mach-tegra/gpu.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see http://www.gnu.org/licenses/.
+ */
+
+/* Tegra vpr routines */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/tegra.h
+#include asm/arch/mc.h
+
+#include fdt_support.h
+
+static bool _configured;
+
+void config_gpu(void)
+{
+   struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
+
+   /* Turn VPR off */
+   writel

[U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node

2015-07-09 Thread Alexandre Courbot 
Tegra124 requires the bootloader to perform VPR initialization, otherwise the
GPU cannot be used by the system. Since using the GPU without that
initialization results in a hang, the GPU DT node is left disabled, and it is
the task of the bootloader to enable it after ensuring it is safe to use the
GPU.

VPR init is already performed since patch df3443dfa449, but the device tree was
left untouched. This patch series performs this last step and prepares the GPU
intialization code to receive more code for newer chips.

Patch 1 of this series moves the GPU initialization code to a more generic
place, since newer chips like T210 require extra steps to initialize the GPU
(e.g. WPR setup). It also performs VPR initialization at a later time of the
bootloader life, so that we can check the status variable right before booting
the kernel and patch the DT accordingly.

Patch 2 performs the DT patching using the ft_board_setup() hook.

Alexandre Courbot (2):
  ARM: tegra: move VPR configuration to a later stage
  ARM: tegra: enable GPU DT node when appropriate

 arch/arm/include/asm/arch-tegra/ap.h  |  9 -
 arch/arm/include/asm/arch-tegra/gpu.h | 43 +++
 arch/arm/mach-tegra/Makefile  |  2 +-
 arch/arm/mach-tegra/ap.c  |  3 --
 arch/arm/mach-tegra/board2.c  |  3 ++
 arch/arm/mach-tegra/gpu.c | 66 +++
 arch/arm/mach-tegra/vpr.c | 35 ---
 board/nvidia/jetson-tk1/jetson-tk1.c  |  8 +
 board/nvidia/venice2/venice2.c|  8 +
 include/configs/jetson-tk1.h  |  2 ++
 include/configs/tegra124-common.h |  3 ++
 include/configs/venice2.h |  2 ++
 12 files changed, 136 insertions(+), 48 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-tegra/gpu.h
 create mode 100644 arch/arm/mach-tegra/gpu.c
 delete mode 100644 arch/arm/mach-tegra/vpr.c

-- 
2.4.4

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Re: [U-Boot] [PATCH] net: asix: Add support for AX88772B

2014-10-21 Thread Alexandre Courbot 

Hi Marek,

I am still not seeing this patch in mainline ; maybe you will want to 
take it as you suggested?


Thanks,
Alex.

On 10/10/2014 12:10 AM, Marek Vasut wrote:

On Thursday, October 09, 2014 at 05:43:30 AM, Alexandre Courbot wrote:

This USB device works as-is on this driver.

Signed-off-by: Alexandre Courbot acour...@nvidia.com


Acked-by: Marek Vasut ma...@denx.de

It's a network device, but it's also USB. Joe, do you want to pick
this up please? Alexandre, please keep an eye on the patch and if
it doesn't get picked up for a week or so, poke me and I'll pick
it through USB.

I would be even OK if such a trivial thing made it into 2014.10, but
I'm not in position to vouch on that right now.

Best regards,
Marek Vasut



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[U-Boot] [PATCH] net: asix: Add support for AX88772B

2014-10-08 Thread Alexandre Courbot 
This USB device works as-is on this driver.

Signed-off-by: Alexandre Courbot acour...@nvidia.com
---

 drivers/usb/eth/asix.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c
index 6557055e02b8..11811094ede8 100644
--- a/drivers/usb/eth/asix.c
+++ b/drivers/usb/eth/asix.c
@@ -580,6 +580,7 @@ static const struct asix_dongle asix_dongles[] = {
{ 0x2001, 0x3c05, FLAG_TYPE_AX88772 },
/* ASIX 88772B */
{ 0x0b95, 0x772b, FLAG_TYPE_AX88772B | FLAG_EEPROM_MAC },
+   { 0x0b95, 0x7e2b, FLAG_TYPE_AX88772B },
{ 0x, 0x, FLAG_NONE }   /* END - Do not remove */
 };
 
-- 
2.1.2

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Re: [U-Boot] [PATCH v3] ARM: tegra: Disable VPR

2014-07-01 Thread Alexandre Courbot 
Tom, is this patch ok for you? If yes, do you plan to merge it?

On Sat, Jun 28, 2014 at 1:21 AM, Thierry Reding
thierry.red...@gmail.com wrote:
 On Tue, Jun 24, 2014 at 11:45:29AM +0900, Alexandre Courbot wrote:
 From: Bryan Wu pe...@nvidia.com

 On Tegra114 and Tegra124 platforms, certain display-related registers cannot
 be accessed unless the VPR registers are programmed.  For bootloader, we
 probably don't care about VPR, so we disable it (which counts as programming
 it, and allows those display-related registers to be accessed.

 This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c
 in Chromium OS U-Boot project.

 Signed-off-by: Andrew Chew ac...@nvidia.com
 Signed-off-by: Jimmy Zhang jimmzh...@nvidia.com
 Signed-off-by: Bryan Wu pe...@nvidia.com
 [acourbot: ensure write went through, vpr.c style changes]
 Signed-off-by: Alexandre Courbot acour...@nvidia.com
 Reviewed-by: Stephen Warren swar...@nvidia.com
 Cc: Tom Warren twar...@nvidia.com
 Cc: Stephen Warren swar...@nvidia.com
 Cc: Terje Bergstrom tbergst...@nvidia.com
 ---
 Changes since v2:
 - Remove useless switch case

 Changes since v1:
 - Use proper defines for fields values
 - Move MC layout to T124 arch as it is exclusive to it
 - Only compile VPR support if T124 is enabled

  arch/arm/cpu/tegra-common/Makefile  |  1 +
  arch/arm/cpu/tegra-common/ap.c  |  3 ++
  arch/arm/cpu/tegra-common/vpr.c | 35 +++
  arch/arm/include/asm/arch-tegra/ap.h|  9 ++
  arch/arm/include/asm/arch-tegra124/mc.h | 49 
 +
  5 files changed, 97 insertions(+)
  create mode 100644 arch/arm/cpu/tegra-common/vpr.c
  create mode 100644 arch/arm/include/asm/arch-tegra124/mc.h

 Tested-by: Thierry Reding tred...@nvidia.com
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[U-Boot] [PATCH v2] ARM: tegra: Disable VPR

2014-06-23 Thread Alexandre Courbot 
From: Bryan Wu pe...@nvidia.com

On Tegra114 and Tegra124 platforms, certain display-related registers cannot
be accessed unless the VPR registers are programmed.  For bootloader, we
probably don't care about VPR, so we disable it (which counts as programming
it, and allows those display-related registers to be accessed.

This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c
in Chromium OS U-Boot project.

Signed-off-by: Andrew Chew ac...@nvidia.com
Signed-off-by: Jimmy Zhang jimmzh...@nvidia.com
Signed-off-by: Bryan Wu pe...@nvidia.com
[acourbot: ensure write went through, vpr.c style changes]
Signed-off-by: Alexandre Courbot acour...@nvidia.com
Cc: Tom Warren twar...@nvidia.com
Cc: Stephen Warren swar...@nvidia.com
Cc: Terje Bergstrom tbergst...@nvidia.com
---
Changes since v1:
- Use proper defines for fields values
- Move MC layout to T124 arch as it is exclusive to it
- Only compile VPR support if T124 is enabled

 arch/arm/cpu/tegra-common/Makefile  |  1 +
 arch/arm/cpu/tegra-common/ap.c  |  3 ++
 arch/arm/cpu/tegra-common/vpr.c | 45 ++
 arch/arm/include/asm/arch-tegra/ap.h|  9 ++
 arch/arm/include/asm/arch-tegra124/mc.h | 49 +
 5 files changed, 107 insertions(+)
 create mode 100644 arch/arm/cpu/tegra-common/vpr.c
 create mode 100644 arch/arm/include/asm/arch-tegra124/mc.h

diff --git a/arch/arm/cpu/tegra-common/Makefile 
b/arch/arm/cpu/tegra-common/Makefile
index 892556e64451..a18c318739fa 100644
--- a/arch/arm/cpu/tegra-common/Makefile
+++ b/arch/arm/cpu/tegra-common/Makefile
@@ -14,3 +14,4 @@ obj-y += clock.o
 obj-y += lowlevel_init.o
 obj-y += pinmux-common.o
 obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
+obj-$(CONFIG_TEGRA124) += vpr.o
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 91d70da65661..a17dfd1e225e 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -163,4 +163,7 @@ void s_init(void)
 
/* init the cache */
config_cache();
+
+   /* init vpr */
+   config_vpr();
 }
diff --git a/arch/arm/cpu/tegra-common/vpr.c b/arch/arm/cpu/tegra-common/vpr.c
new file mode 100644
index ..1a442d9a40ef
--- /dev/null
+++ b/arch/arm/cpu/tegra-common/vpr.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see http://www.gnu.org/licenses/.
+ */
+
+/* Tegra vpr routines */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/gp_padctrl.h
+#include asm/arch/tegra.h
+#include asm/arch/mc.h
+#include asm/arch-tegra/ap.h
+
+/* Configures VPR.  Right now, all we do is turn it off. */
+void config_vpr(void)
+{
+   struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
+
+   /* VPR is only in T114 and T124 */
+   switch (tegra_get_chip()) {
+   case CHIPID_TEGRA114:
+   case CHIPID_TEGRA124:
+   /* Turn off VPR */
+   writel(0, mc-mc_video_protect_size_mb);
+   writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
+  mc-mc_video_protect_reg_ctrl);
+   /* read back to ensure the write went through */
+   readl(mc-mc_video_protect_reg_ctrl);
+   break;
+   default:
+   break;
+   }
+}
diff --git a/arch/arm/include/asm/arch-tegra/ap.h 
b/arch/arm/include/asm/arch-tegra/ap.h
index bc5851c1d045..5c8be94d9772 100644
--- a/arch/arm/include/asm/arch-tegra/ap.h
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -65,3 +65,12 @@ int tegra_get_sku_info(void);
 
 /* Do any chip-specific cache config */
 void config_cache(void);
+
+#if defined(CONFIG_TEGRA124)
+/* Do chip-specific vpr config */
+void config_vpr(void);
+#else
+static inline void config_vpr(void)
+{
+}
+#endif
diff --git a/arch/arm/include/asm/arch-tegra124/mc.h 
b/arch/arm/include/asm/arch-tegra124/mc.h
new file mode 100644
index ..d526dfe15c30
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/mc.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied

Re: [U-Boot] [PATCH v2] ARM: tegra: Disable VPR

2014-06-23 Thread Alexandre Courbot 

On 06/24/2014 03:44 AM, Stephen Warren wrote:

On 06/23/2014 01:20 AM, Alexandre Courbot wrote:

From: Bryan Wu pe...@nvidia.com

On Tegra114 and Tegra124 platforms, certain display-related registers cannot
be accessed unless the VPR registers are programmed.  For bootloader, we
probably don't care about VPR, so we disable it (which counts as programming
it, and allows those display-related registers to be accessed.

This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c
in Chromium OS U-Boot project.



diff --git a/arch/arm/cpu/tegra-common/vpr.c b/arch/arm/cpu/tegra-common/vpr.c



+void config_vpr(void)
+{
+   struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
+
+   /* VPR is only in T114 and T124 */
+   switch (tegra_get_chip()) {
+   case CHIPID_TEGRA114:
+   case CHIPID_TEGRA124:


You can drop the switch() and call to tegra_get_chip() since this is all
done at compile-time now.


Of course. What was I thinking...



Other than that,
Reviewed-by: Stephen Warren swar...@nvidia.com


Thanks!

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[U-Boot] [PATCH v3] ARM: tegra: Disable VPR

2014-06-23 Thread Alexandre Courbot 
From: Bryan Wu pe...@nvidia.com

On Tegra114 and Tegra124 platforms, certain display-related registers cannot
be accessed unless the VPR registers are programmed.  For bootloader, we
probably don't care about VPR, so we disable it (which counts as programming
it, and allows those display-related registers to be accessed.

This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c
in Chromium OS U-Boot project.

Signed-off-by: Andrew Chew ac...@nvidia.com
Signed-off-by: Jimmy Zhang jimmzh...@nvidia.com
Signed-off-by: Bryan Wu pe...@nvidia.com
[acourbot: ensure write went through, vpr.c style changes]
Signed-off-by: Alexandre Courbot acour...@nvidia.com
Reviewed-by: Stephen Warren swar...@nvidia.com
Cc: Tom Warren twar...@nvidia.com
Cc: Stephen Warren swar...@nvidia.com
Cc: Terje Bergstrom tbergst...@nvidia.com
---
Changes since v2:
- Remove useless switch case

Changes since v1:
- Use proper defines for fields values
- Move MC layout to T124 arch as it is exclusive to it
- Only compile VPR support if T124 is enabled

 arch/arm/cpu/tegra-common/Makefile  |  1 +
 arch/arm/cpu/tegra-common/ap.c  |  3 ++
 arch/arm/cpu/tegra-common/vpr.c | 35 +++
 arch/arm/include/asm/arch-tegra/ap.h|  9 ++
 arch/arm/include/asm/arch-tegra124/mc.h | 49 +
 5 files changed, 97 insertions(+)
 create mode 100644 arch/arm/cpu/tegra-common/vpr.c
 create mode 100644 arch/arm/include/asm/arch-tegra124/mc.h

diff --git a/arch/arm/cpu/tegra-common/Makefile 
b/arch/arm/cpu/tegra-common/Makefile
index 892556e64451..a18c318739fa 100644
--- a/arch/arm/cpu/tegra-common/Makefile
+++ b/arch/arm/cpu/tegra-common/Makefile
@@ -14,3 +14,4 @@ obj-y += clock.o
 obj-y += lowlevel_init.o
 obj-y += pinmux-common.o
 obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
+obj-$(CONFIG_TEGRA124) += vpr.o
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 91d70da65661..a17dfd1e225e 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -163,4 +163,7 @@ void s_init(void)
 
/* init the cache */
config_cache();
+
+   /* init vpr */
+   config_vpr();
 }
diff --git a/arch/arm/cpu/tegra-common/vpr.c b/arch/arm/cpu/tegra-common/vpr.c
new file mode 100644
index ..f695811c9b6d
--- /dev/null
+++ b/arch/arm/cpu/tegra-common/vpr.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see http://www.gnu.org/licenses/.
+ */
+
+/* Tegra vpr routines */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/tegra.h
+#include asm/arch/mc.h
+
+/* Configures VPR.  Right now, all we do is turn it off. */
+void config_vpr(void)
+{
+   struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
+
+   /* Turn VPR off */
+   writel(0, mc-mc_video_protect_size_mb);
+   writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
+  mc-mc_video_protect_reg_ctrl);
+   /* read back to ensure the write went through */
+   readl(mc-mc_video_protect_reg_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-tegra/ap.h 
b/arch/arm/include/asm/arch-tegra/ap.h
index bc5851c1d045..5c8be94d9772 100644
--- a/arch/arm/include/asm/arch-tegra/ap.h
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -65,3 +65,12 @@ int tegra_get_sku_info(void);
 
 /* Do any chip-specific cache config */
 void config_cache(void);
+
+#if defined(CONFIG_TEGRA124)
+/* Do chip-specific vpr config */
+void config_vpr(void);
+#else
+static inline void config_vpr(void)
+{
+}
+#endif
diff --git a/arch/arm/include/asm/arch-tegra124/mc.h 
b/arch/arm/include/asm/arch-tegra124/mc.h
new file mode 100644
index ..d526dfe15c30
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/mc.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program

[U-Boot] [PATCH] ARM: tegra: Disable VPR

2014-06-19 Thread Alexandre Courbot 
From: Bryan Wu pe...@nvidia.com

On Tegra114 and Tegra124 platforms, certain display-related registers cannot
be accessed unless the VPR registers are programmed.  For bootloader, we
probably don't care about VPR, so we disable it (which counts as programming
it, and allows those display-related registers to be accessed.

This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c
in Chromium OS U-Boot project.

Signed-off-by: Andrew Chew ac...@nvidia.com
Signed-off-by: Jimmy Zhang jimmzh...@nvidia.com
Signed-off-by: Bryan Wu pe...@nvidia.com
[acourbot: ensure write went through, vpr.c style changes]
Signed-off-by: Alexandre Courbot acour...@nvidia.com
Cc: Tom Warren twar...@nvidia.com
Cc: Stephen Warren swar...@nvidia.com
Cc: Terje Bergstrom tbergst...@nvidia.com
---
 arch/arm/cpu/tegra-common/Makefile   |  1 +
 arch/arm/cpu/tegra-common/ap.c   |  3 +++
 arch/arm/cpu/tegra-common/vpr.c  | 43 ++
 arch/arm/include/asm/arch-tegra/ap.h |  3 +++
 arch/arm/include/asm/arch-tegra/mc.h | 45 
 5 files changed, 95 insertions(+)
 create mode 100644 arch/arm/cpu/tegra-common/vpr.c
 create mode 100644 arch/arm/include/asm/arch-tegra/mc.h

diff --git a/arch/arm/cpu/tegra-common/Makefile 
b/arch/arm/cpu/tegra-common/Makefile
index 892556e64451..5c541bef557e 100644
--- a/arch/arm/cpu/tegra-common/Makefile
+++ b/arch/arm/cpu/tegra-common/Makefile
@@ -14,3 +14,4 @@ obj-y += clock.o
 obj-y += lowlevel_init.o
 obj-y += pinmux-common.o
 obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
+obj-y += vpr.o
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 91d70da65661..a17dfd1e225e 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -163,4 +163,7 @@ void s_init(void)
 
/* init the cache */
config_cache();
+
+   /* init vpr */
+   config_vpr();
 }
diff --git a/arch/arm/cpu/tegra-common/vpr.c b/arch/arm/cpu/tegra-common/vpr.c
new file mode 100644
index ..595744254375
--- /dev/null
+++ b/arch/arm/cpu/tegra-common/vpr.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see http://www.gnu.org/licenses/.
+ */
+
+/* Tegra vpr routines */
+
+#include common.h
+#include asm/io.h
+#include asm/arch-tegra/ap.h
+#include asm/arch-tegra/mc.h
+#include asm/arch/gp_padctrl.h
+
+/* Configures VPR.  Right now, all we do is turn it off. */
+void config_vpr(void)
+{
+   struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
+
+   /* VPR is only in T114 and T124 */
+   switch (tegra_get_chip()) {
+   case CHIPID_TEGRA114:
+   case CHIPID_TEGRA124:
+   /* Turn off VPR */
+   writel(0x, mc-mc_video_protect_size_mb);
+   writel(0x0001, mc-mc_video_protect_reg_ctrl);
+   /* read back to ensure the write went through */
+   readl(mc-mc_video_protect_reg_ctrl);
+   break;
+   default:
+   break;
+   }
+}
diff --git a/arch/arm/include/asm/arch-tegra/ap.h 
b/arch/arm/include/asm/arch-tegra/ap.h
index bc5851c1d045..908407aeded0 100644
--- a/arch/arm/include/asm/arch-tegra/ap.h
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -65,3 +65,6 @@ int tegra_get_sku_info(void);
 
 /* Do any chip-specific cache config */
 void config_cache(void);
+
+/* Do chip-specific vpr config */
+void config_vpr(void);
diff --git a/arch/arm/include/asm/arch-tegra/mc.h 
b/arch/arm/include/asm/arch-tegra/mc.h
new file mode 100644
index ..2fdcf90d7508
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/mc.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see http://www.gnu.org/licenses/.
+ */
+
+#ifndef _TEGRA_MC_H_
+#define _TEGRA_MC_H_
+
+/**
+ * Defines the memory