Re: [U-Boot] [PATCH] powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cache
> >>> While enabling L2 cache, the value of L2PE (L2 cache parity/ECC > >>> error checking enable) must not be changed while the L2 cache is enabled. > >>> So, L2PE must be set before enabling L2 cache. > >> > >> Aneesh, > >> > >> The original code set L2PE and L2E together. The L2PE bit doesn't change > >> after > that. > >> Doesn't this satisfy the requirement? Did you observe any failure before > >> your > patch? > >> > >> York > > > > e6500 block guide states that "The value of L2PE must not be changed while > > the L2 > cache is enabled" > > So, when both the bits are set together, it might lead to L2 cache > > getting enabled first and L2PE getting set after that. So L2PE is getting > > changed from > 0 to 1 while L2 is still enabled which should not be done. > > > > In normal non-secure boot, U-Boot is the first to use L2 after reset > > but in case of secure boot, L2 is used by Bot ROM before U-Boot. If > > L2PE and L2E are done together, ECC errors are observed on L2 (L2CAPTECC - > > L2 > cache error capture ECC syndrome) and U-Boot crashes. > > > > I believe this is because of ECC/Parity checking not getting enabled > > properly and resulting into erroneous detection of errors > > > > When this is changed to setting L2PE before L2E, or not setting L2PE > > at all i.e. disabling ECC error checks, no ECC errors are observed and > > U-Boot works > fine. > > > > Aneesh, > > You said for secure boot L2 cache was used by bootrom before U-Boot. Could the > L2 cache be left enabled when U-Boot runs? If true, that indeed sets L2PE bit > while > L2E is enabled. Please confirm. > > If L2E was left set by secure boot, your change actually fixes it, but the > commit > message needs to be rewritten. L2 is not left enabled by Boot ROM in case of Secure Boot. The IBR code enables L2 but disables it before transferring control to U-Boot. What I was trying to suggest is that the way we are enabling L2 in U-Boot seems to be incorrect as we are setting L2PE and L2E simultaneously. This does not cause any issues in case of non-secure boot as U-Boot is the first entity to enable and use L2 cache. But in case of secure boot, L2 is enabled, used and disabled by Boot ROM first. Now in U-Boot, if ECC/Parity checking is not enabled correctly then it starts reporting ECC errors randomly and U-Boot crashes. After making this change, no ECC errors are observed and U-Boot starts working correct in case of non-secure boot. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cache
> -Original Message- > From: York Sun [mailto:york@nxp.com] > Sent: Tuesday, April 19, 2016 10:03 PM > To: Aneesh Bansal <aneesh.ban...@nxp.com>; u-boot@lists.denx.de > Cc: Ruchika Gupta <ruchika.gu...@nxp.com>; Prabhakar Kushwaha > <prabhakar.kushw...@nxp.com> > Subject: Re: [PATCH] powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 > cache > > On 04/18/2016 05:16 AM, Aneesh Bansal wrote: > > While enabling L2 cache, the value of L2PE (L2 cache parity/ECC error > > checking enable) must not be changed while the L2 cache is enabled. > > So, L2PE must be set before enabling L2 cache. > > Aneesh, > > The original code set L2PE and L2E together. The L2PE bit doesn't change > after that. > Doesn't this satisfy the requirement? Did you observe any failure before your > patch? > > York e6500 block guide states that "The value of L2PE must not be changed while the L2 cache is enabled" So, when both the bits are set together, it might lead to L2 cache getting enabled first and L2PE getting set after that. So L2PE is getting changed from 0 to 1 while L2 is still enabled which should not be done. In normal non-secure boot, U-Boot is the first to use L2 after reset but in case of secure boot, L2 is used by Bot ROM before U-Boot. If L2PE and L2E are done together, ECC errors are observed on L2 (L2CAPTECC - L2 cache error capture ECC syndrome) and U-Boot crashes. I believe this is because of ECC/Parity checking not getting enabled properly and resulting into erroneous detection of errors When this is changed to setting L2PE before L2E, or not setting L2PE at all i.e. disabling ECC error checks, no ECC errors are observed and U-Boot works fine. Aneesh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cache
While enabling L2 cache, the value of L2PE (L2 cache parity/ECC error checking enable) must not be changed while the L2 cache is enabled. So, L2PE must be set before enabling L2 cache. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> --- arch/powerpc/cpu/mpc85xx/start.S | 23 +++ 1 file changed, 23 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 82a151a..4c51225 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -720,16 +720,39 @@ enable_l2_cluster_l2: ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l sync stw r4, 0(r3) /* invalidate L2 */ + /* Poll till the bits are cleared */ 1: sync lwz r0, 0(r3) twi 0, r0, 0 isync and.r1, r0, r4 bne 1b + + /* L2PE must be set before L2 cache is enabled */ + lis r4, (L2CSR0_L2PE)@h + ori r4, r4, (L2CSR0_L2PE)@l + sync + stw r4, 0(r3) /* enable L2 parity/ECC error checking */ + /* Poll till the bit is set */ +1: sync + lwz r0, 0(r3) + twi 0, r0, 0 + isync + and.r1, r0, r4 + beq 1b + lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h ori r4, r4, (L2CSR0_L2REP_MODE)@l sync stw r4, 0(r3) /* enable L2 */ + /* Poll till the bit is set */ +1: sync + lwz r0, 0(r3) + twi 0, r0, 0 + isync + and.r1, r0, r4 + beq 1b + delete_ccsr_l2_tlb: delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC2, MAS2_I|MAS2_G, r3 #endif -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] armv8: ls2080: enable sec_init in U-Boot
Define CONFIG_FSL_CAAM for LS2080 which would enable call to sec_init() during U-Boot. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> --- include/configs/ls2080a_common.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 13ce349..4150e17 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -28,6 +28,8 @@ /* We need architecture specific misc initializations */ #define CONFIG_ARCH_MISC_INIT +#define CONFIG_FSL_CAAM/* Enable SEC/CAAM */ + /* Link Definitions */ #ifdef CONFIG_SPL #define CONFIG_SYS_TEXT_BASE 0x8040 @@ -307,5 +309,10 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif #endif /* __LS2_COMMON_H */ -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] board: ls1043ardb: move sec_init to board_init
sec_init() which was earlier called in misc_init_r()
is now done in board_init() before PPA init as SEC
block will be used during PPA image validation.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
The patchset is dependent on
http://patchwork.ozlabs.org/patch/571339/
board/freescale/ls1043ardb/ls1043ardb.c | 32 +---
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c
b/board/freescale/ls1043ardb/ls1043ardb.c
index eff09aa..aa2c962 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -117,6 +117,23 @@ int board_init(void)
enable_layerscape_ns_access();
#endif
+#ifdef CONFIG_SECURE_BOOT
+ /* In case of Secure Boot, the IBR configures the SMMU
+* to allow only Secure transactions.
+* SMMU must be reset in bypass mode.
+* Set the ClientPD bit and Clear the USFCFG Bit
+*/
+ u32 val;
+ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_SCR0, val);
+ val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_NSCR0, val);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+ sec_init();
+#endif
+
#ifdef CONFIG_FSL_LS_PPA
ppa_init_pre(_entry);
@@ -136,21 +153,6 @@ int config_board_mux(void)
int misc_init_r(void)
{
config_board_mux();
-#ifdef CONFIG_SECURE_BOOT
- /* In case of Secure Boot, the IBR configures the SMMU
-* to allow only Secure transactions.
-* SMMU must be reset in bypass mode.
-* Set the ClientPD bit and Clear the USFCFG Bit
-*/
- u32 val;
- val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
- out_le32(SMMU_SCR0, val);
- val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
- out_le32(SMMU_NSCR0, val);
-#endif
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
-#endif
return 0;
}
#endif
--
1.8.1.4
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[U-Boot] [PATCH 2/2] ls1043ardb: PPA: add PPA validation in case of secure boot
As part of Secure Boot Chain of trust, PPA image must be validated
before the image is started.
The code for the same has been added.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
The patchset is dependent on
http://patchwork.ozlabs.org/patch/571339/
arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 22 ++
arch/arm/include/asm/fsl_secure_boot.h | 16
2 files changed, 38 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
index db767f9..804c4d7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
@@ -18,6 +18,9 @@
#include
#endif
#include
+#ifdef CONFIG_CHAIN_OF_TRUST
+#include
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -69,12 +72,31 @@ static int parse_ppa_firmware_fit_image(const void
**raw_image_addr,
int conf_node_off, fw_node_off;
char *conf_node_name = NULL;
+#ifdef CONFIG_CHAIN_OF_TRUST
+ int ret;
+ uintptr_t ppa_esbc_hdr = CONFIG_SYS_LS_PPA_ESBC_ADDR;
+ uintptr_t ppa_img_addr = 0;
+#endif
+
#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
fit_hdr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
#else
#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
#endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+ ppa_img_addr = (uintptr_t)fit_hdr;
+ if (fsl_check_boot_mode_secure() != 0) {
+ ret = fsl_secboot_validate(ppa_esbc_hdr,
+ CONFIG_PPA_KEY_HASH,
+ _img_addr);
+ if (ret != 0)
+ printf("PPA validation failed\n");
+ else
+ printf("PPA validation Successful\n");
+ }
+#endif
+
conf_node_name = LS_PPA_FIT_CNF_NAME;
if (fdt_check_header(fit_hdr)) {
diff --git a/arch/arm/include/asm/fsl_secure_boot.h
b/arch/arm/include/asm/fsl_secure_boot.h
index 0da0599..d275dd1 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -56,6 +56,22 @@
/* The address needs to be modified according to NOR memory map */
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
+#ifdef CONFIG_LS1043A
+#define CONFIG_SYS_LS_PPA_ESBC_ADDR0x600c
+#endif
+#else
+#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
+#endif
+
+/* Define the key hash here if SRK used for signing PPA image is
+ * different from SRK hash put in SFP used for U-Boot.
+ * Example
+ * #define CONFIG_PPA_KEY_HASH \
+ * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
+ */
+#define CONFIG_PPA_KEY_HASHNULL
+
#include
#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
#endif
--
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[U-Boot] [PATCH 2/2] drivers/crypto/fsl: define structures for PDB
Structures have been defined for PDB (Protocol Data Blcks)
for various operations.
These structure will be used to add PDB data while creating
the PDB descriptors.
CC: Ulises Cardenas <raul.ca...@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
drivers/crypto/fsl/desc.h | 55 +++
1 file changed, 55 insertions(+)
diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h
index 1c13fbc..1ac3a09 100644
--- a/drivers/crypto/fsl/desc.h
+++ b/drivers/crypto/fsl/desc.h
@@ -688,4 +688,59 @@
#define OP_ALG_RNG4_MAS(0x1f3 << OP_ALG_RNG4_SHIFT)
#define OP_ALG_RNG4_SK (0x100 << OP_ALG_RNG4_SHIFT)
+
+/* Structures for Protocol Data Blocks */
+struct __packed pdb_ecdsa_verify {
+ uint32_t pdb_hdr;
+ dma_addr_t dma_q; /* Pointer to q (elliptic curve) */
+ dma_addr_t dma_r; /* Pointer to r (elliptic curve) */
+ dma_addr_t dma_g_xy;/* Pointer to Gx,y (elliptic curve) */
+ dma_addr_t dma_pkey;/* Pointer to Wx,y (public key) */
+ dma_addr_t dma_hash;/* Pointer to hash input */
+ dma_addr_t dma_c; /* Pointer to C_signature */
+ dma_addr_t dma_d; /* Pointer to D_signature */
+ dma_addr_t dma_buf; /* Pointer to 64-byte temp buffer */
+ dma_addr_t dma_ab; /* Pointer to a,b (elliptic curve ) */
+ uint32_t img_size; /* Length of Message */
+};
+
+struct __packed pdb_ecdsa_sign {
+ uint32_t pdb_hdr;
+ dma_addr_t dma_q; /* Pointer to q (elliptic curve) */
+ dma_addr_t dma_r; /* Pointer to r (elliptic curve) */
+ dma_addr_t dma_g_xy;/* Pointer to Gx,y (elliptic curve) */
+ dma_addr_t dma_pri_key; /* Pointer to S (Private key) */
+ dma_addr_t dma_hash;/* Pointer to hash input */
+ dma_addr_t dma_c; /* Pointer to C_signature */
+ dma_addr_t dma_d; /* Pointer to D_signature */
+ dma_addr_t dma_ab; /* Pointer to a,b (elliptic curve ) */
+ dma_addr_t dma_u; /* Pointer to Per Message Random */
+ uint32_t img_size; /* Length of Message */
+};
+
+#define PDB_ECDSA_SGF_SHIFT23
+#define PDB_ECDSA_L_SHIFT 7
+#define PDB_ECDSA_N_SHIFT 0
+
+struct __packed pdb_mp_pub_k {
+ uint32_t pdb_hdr;
+ #define PDB_MP_PUB_K_SGF_SHIFT 31
+ dma_addr_t dma_pkey;/* Pointer to Wx,y (public key) */
+};
+
+struct __packed pdb_mp_sign {
+ uint32_t pdb_hdr;
+ #define PDB_MP_SIGN_SGF_SHIFT 28
+ dma_addr_t dma_addr_msg;/* Pointer to Message */
+ dma_addr_t dma_addr_hash; /* Pointer to hash output */
+ dma_addr_t dma_addr_c_sig; /* Pointer to C_signature */
+ dma_addr_t dma_addr_d_sig; /* Pointer to D_signature */
+ uint32_t img_size; /* Length of Message */
+};
+
+#define PDB_MP_CSEL_SHIFT 17
+#define PDB_MP_CSEL_P256 0x3 << PDB_MP_CSEL_SHIFT/* P-256 */
+#define PDB_MP_CSEL_P384 0x4 << PDB_MP_CSEL_SHIFT/* P-384 */
+#define PDB_MP_CSEL_P521 0x5 << PDB_MP_CSEL_SHIFT/* P-521 */
+
#endif /* DESC_H */
--
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[U-Boot] [PATCH 1/2] drivers/crypto/fsl: add constructs for protocol descriptors
Construct API's have been added to create Protocol Descriptors
for CAAM block.
CC: Ulises Cardenas <raul.ca...@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
drivers/crypto/fsl/desc.h| 25 +
drivers/crypto/fsl/desc_constr.h | 27 +++
2 files changed, 52 insertions(+)
diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h
index 18e2ec8..1c13fbc 100644
--- a/drivers/crypto/fsl/desc.h
+++ b/drivers/crypto/fsl/desc.h
@@ -436,6 +436,31 @@
#define OP_PCLID_BLOB (0x0d << OP_PCLID_SHIFT)
#define OP_PCLID_SECRETKEY (0x11 << OP_PCLID_SHIFT)
#define OP_PCLID_PUBLICKEYPAIR (0x14 << OP_PCLID_SHIFT)
+#define OP_PCLID_DSA_SIGN (0x15 << OP_PCLID_SHIFT)
+#define OP_PCLID_DSA_VERIFY(0x16 << OP_PCLID_SHIFT)
+
+/* Assuming OP_TYPE = OP_TYPE_DECAP_PROTOCOL */
+#define OP_PCLID_MP_PUB_KEY(0x14 << OP_PCLID_SHIFT)
+#define OP_PCLID_MP_SIGN (0x15 << OP_PCLID_SHIFT)
+
+/* Assuming OP_TYPE = OP_TYPE_ENCAP_PROTOCOL */
+#define OP_PCLID_MP_PRIV_KEY (0x14 << OP_PCLID_SHIFT)
+
+/* PROTINFO fields for discrete log public key protocols */
+#define OP_PROTINFO_F2M_FP 0x0001
+#define OP_PROTINFO_ECC_DL 0x0002
+#define OP_PROTINFO_ENC_PRI0x0004
+#define OP_PROTINFO_TEST 0x0008
+#define OP_PROTINFO_EXT_PRI0x0010
+#define OP_PROTINFO_ENC_Z 0x0020
+#define OP_PROTINFO_EKT_Z 0x0040
+#define OP_PROTINFO_MES_REP0x0400
+#define OP_PROTINFO_HASH_MD5 0x
+#define OP_PROTINFO_HASH_SHA1 0x0080
+#define OP_PROTINFO_HASH_SHA2240x0100
+#define OP_PROTINFO_HASH_SHA2560x0180
+#define OP_PROTINFO_HASH_SHA3840x0200
+#define OP_PROTINFO_HASH_SHA5120x0280
/* For non-protocol/alg-only op commands */
#define OP_ALG_TYPE_SHIFT 24
diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h
index 2559ccd..4ea93b0 100644
--- a/drivers/crypto/fsl/desc_constr.h
+++ b/drivers/crypto/fsl/desc_constr.h
@@ -53,6 +53,19 @@ union ptr_addr_t {
};
#endif
+static inline void pdb_add_ptr(dma_addr_t *offset, dma_addr_t ptr)
+{
+#ifdef CONFIG_PHYS_64BIT
+ /* The Position of low and high part of 64 bit address
+* will depend on the endianness of CAAM Block */
+ union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset;
+ ptr_addr->m_halfs.high = (u32)(ptr >> 32);
+ ptr_addr->m_halfs.low = (u32)ptr;
+#else
+ *offset = ptr;
+#endif
+}
+
static inline int desc_len(u32 *desc)
{
return *desc & HDR_DESCLEN_MASK;
@@ -68,6 +81,11 @@ static inline u32 *desc_end(u32 *desc)
return desc + desc_len(desc);
}
+static inline void *desc_pdb(u32 *desc)
+{
+ return desc + 1;
+}
+
static inline void init_desc(u32 *desc, u32 options)
{
*desc = (options | HDR_ONE) + 1;
@@ -78,6 +96,15 @@ static inline void init_job_desc(u32 *desc, u32 options)
init_desc(desc, CMD_DESC_HDR | options);
}
+static inline void init_job_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes)
+{
+ u32 pdb_len = (pdb_bytes + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ;
+
+ init_job_desc(desc,
+ (((pdb_len + 1) << HDR_START_IDX_SHIFT) + pdb_len) |
+ options);
+}
+
static inline void append_ptr(u32 *desc, dma_addr_t ptr)
{
dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
--
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[U-Boot] [PATCH] drivers/crypto/fsl: correct error checking in run_descriptor
When CAAM runs a descriptor and an error occurs, a non-zero
value is set in Output Status Register.
The if condition should check the status for a non-zero value.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
drivers/crypto/fsl/jr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index b553e3c..f4069b5 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -353,7 +353,7 @@ int run_descriptor_jr(uint32_t *desc)
}
}
- if (!op.status) {
+ if (op.status) {
debug("Error %x\n", op.status);
ret = op.status;
}
--
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Re: [U-Boot] [PATCH 2/3][v3] Data types defined for 64 bit physical address
> -Original Message- > From: york sun > Sent: Wednesday, February 10, 2016 10:51 AM > To: Scott Wood <o...@buserror.net>; Aneesh Bansal <aneesh.ban...@nxp.com> > Cc: u-boot@lists.denx.de; Ruchika Gupta <ruchika.gu...@freescale.com>; > Prabhakar > Kushwaha <prabha...@freescale.com> > Subject: Re: [PATCH 2/3][v3] Data types defined for 64 bit physical address > > On 02/09/2016 09:10 PM, Scott Wood wrote: > > On Wed, 2016-02-10 at 02:30 +, york sun wrote: > > > > >> > >> Aneesh and Scott, > >> > >> I need to revisit this patch. Would it be better to change it as below? > >> > >> +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_ARM64) typedef > >> +unsigned long long dma_addr_t; typedef unsigned long long > >> +phys_addr_t; typedef unsigned long long phys_size_t; #else > >> +/* DMA addresses are 32-bits wide */ > >> typedef u32 dma_addr_t; > >> - > >> typedef unsigned long phys_addr_t; > >> typedef unsigned long phys_size_t; > >> +#endif > >> > >> I am debugging another patch and found changing phys_addr_t makes > >> some trouble for ARM64, especially to mix with ulong. > > > > What sort of trouble is it causing? And why would you mix it with ulong? > > > > I am debugging this patch http://patchwork.ozlabs.org/patch/514590/. > ulong is used a lot for image related calls. I tried to change to > phys_addr_t, but only > buried myself even deeper. Basically I am battling on three sides > > 1. All 32-bit SoCs should continue to work without using 64-bit variables for > addresses. If CONFIG_PHYS_64BIT is not defined, phys_addr_t is defined to ulong. So it will be 32 bit for 32 bit cores (Armv7) and 64 bit for 64 bit cores (Armv8). So as long as CONFIG_PHYS_64BIT is not defined, using phys_addr_t will use 32 bit variable. > 2. 64-bit SoCs such as ARMv8 will support FIT with addresses beyond 32 bits. > 3. Host tool such as mkimage should work on both 32- and 64-bit host OS. > > Any suggestion is welcomed. > > York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4] armv7: ls102xa: Enable snooping on transactions from CAAM
CAAM IP lies behind SMMU in the system. Configure SMMU to do the following:
a) Program SCR to bypass transactions with stream ID other than that of CAAM
b) Program S2CR to change memroy attributes of transactions with CAAM's stream
ID (0x10) to cacheable.
CC: Alison Wang <alison.w...@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Nitesh Narayan Lal <nitesh@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v4:
- Modified the Commit message
- Functionality moved to SoC Specific file
The patch is dependent on
http://patchwork.ozlabs.org/patch/579377/
arch/arm/cpu/armv7/ls102xa/soc.c | 5 +++
arch/arm/include/asm/arch-ls102xa/config.h | 2 ++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 35
.../include/asm/arch-ls102xa/ls102xa_stream_id.h | 1 +
board/freescale/common/ls102xa_stream_id.c | 37 +-
5 files changed, 79 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index b1b0c71..42cd31a 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -134,5 +134,10 @@ int ls102xa_smmu_stream_id_init(void)
ls102xa_config_smmu_stream_id(dev_stream_id,
ARRAY_SIZE(dev_stream_id));
+ /* Configure SMMU to make transactions with CAAM stream ID
+* as cacheable
+*/
+ ls1021x_config_smmu_caam_cacheable(0x10);
+
return 0;
}
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
b/arch/arm/include/asm/arch-ls102xa/config.h
index 424fe87..f189ea8 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -62,6 +62,8 @@
#define LPUART_BASE(CONFIG_SYS_IMMR + 0x0195)
+#define SMMU_BASE (CONFIG_SYS_IMMR + 0x30)
+
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x250)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 0a80772..61da884 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -435,4 +435,39 @@ struct ccsr_ahci {
uint get_svr(void);
+/* MMU 400 */
+#define SMMU_NSCR (SMMU_BASE + 0x400)
+#define SMMU_SMR (SMMU_BASE + 0x800)
+#define SMMU_S2CR (SMMU_BASE + 0xc00)
+
+#define SMMU_NSCR_CLIENTPD_SHIFT 0
+#define SMMU_NSCR_MTCFG_SHIFT 20
+
+#define SMR_SMR_VALID_SHIFT31
+#define SMR_ID_MASK0x7fff
+#define SMR_MASK_SHIFT 16
+
+#define S2CR_WACFG_SHIFT 22
+#define S2CR_WACFG_MASK0x3
+#define S2CR_WACFG_WRITE_ALLOCATE 0x2
+
+#define S2CR_RACFG_SHIFT 20
+#define S2CR_RACFG_MASK0x3
+#define S2CR_RACFG_READ_ALLOCATE 0x2
+
+#define S2CR_TYPE_SHIFT16
+#define S2CR_TYPE_MASK 0x3
+#define S2CR_TYPE_BYPASS 0x01
+
+#define S2CR_MEM_ATTR_SHIFT12
+#define S2CR_MEM_ATTR_MASK 0xf
+#define S2CR_MEM_ATTR_CACHEABLE0xa
+
+#define S2CR_MTCFG 0x0800
+
+#define S2CR_SHCFG_SHIFT 8
+#define S2CR_SHCFG_MASK0x3
+#define S2CR_SHCFG_OUTER_CACHEABLE 0x1
+#define S2CR_SHCFG_INNER_CACHEABLE 0x2
+
#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
index fa571b3..c1d22bf 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
@@ -71,4 +71,5 @@ struct smmu_stream_id {
void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size);
void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
+void ls1021x_config_smmu_caam_cacheable(uint32_t liodn);
#endif
diff --git a/board/freescale/common/ls102xa_stream_id.c
b/board/freescale/common/ls102xa_stream_id.c
index f434269..8e28d64 100644
--- a/board/freescale/common/ls102xa_stream_id.c
+++ b/board/freescale/common/ls102xa_stream_id.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
{
@@ -20,7 +21,7 @@ void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id,
uint32_t num)
void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
{
int i;
- u32 liodn;
+ uint32_t liodn;
for (i = 0; i < size; i++) {
if (tbl[i].num_ids == 2)
@@ -31,3 +32,37 @@ void ls1021x_c
Re: [U-Boot] [PATCH v3] Enable snooping on transactions from CAAM block
> -Original Message- > From: Huan Wang > Sent: Tuesday, February 02, 2016 12:31 PM > To: york sun <york@nxp.com>; Aneesh Bansal <aneesh.ban...@nxp.com>; u- > b...@lists.denx.de; Huan Wang-B18965 <alison.w...@freescale.com> > Cc: Ruchika Gupta <ruchika.gu...@nxp.com>; Prabhakar Kushwaha > <prabhakar.kushw...@nxp.com>; Nitesh Lal <nitesh@nxp.com> > Subject: RE: [PATCH v3] Enable snooping on transactions from CAAM block > > Hi, York, > > > -Original Message- > > From: york sun [mailto:york@nxp.com] > > Sent: Tuesday, February 02, 2016 1:06 AM > > To: Aneesh Bansal; u-boot@lists.denx.de; Huan Wang-B18965 > > Cc: Ruchika Gupta; Prabhakar Kushwaha; Nitesh Lal > > Subject: Re: [PATCH v3] Enable snooping on transactions from CAAM > > block > > > > +Alison to comment on my question at the end of this email > > > > Aneesh, > > > > A few comments to this patch. > > > > First, please prefix the subject with a meaningful tag. In this case, > > it should be armv7: ls1020a. > > > > On 01/17/2016 10:16 PM, Aneesh Bansal wrote: > > > To enable snooping on CAAM transactions following programming is > > > done > > > > > > 1. Enable core snooping (CCI interface, Core is Slave5 on CCI) This > > > setting is also required for making the system coherent > > > > > > 2. CAAM IP lies behind SMMU3 in the system. Configure SMMU3 to do > > > the > > following: > > > a) Program SCR to bypass transactions with stream ID other than that > > > of CAAM > > > b) Program S2CR to change memroy attributes of transactions with > > > CAAM's stream ID (0x10) to cacheable. > > > > Second, the commit message should not exceed 72 characters. > > Third, the commit message should explain why and what this patch is > > doing. I don't see any change related to enabling snooping on CCI in > > this patch. > > > > > > > > Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com> > > > Signed-off-by: Nitesh Narayan Lal <nitesh@nxp.com> > > > Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> > > > --- > > > Changes in v3: > > > Modified the commit message. > > > > > > Changes in v2: > > > Avoid mixing the use of u32 and uint32_t. > > > Using uint32_t at all places. > > > > > > arch/arm/include/asm/arch-ls102xa/config.h | 1 + > > > .../include/asm/arch-ls102xa/ls102xa_stream_id.h | 34 > > > > > board/freescale/common/ls102xa_stream_id.c | 36 > > +- > > > board/freescale/ls1021aqds/ls1021aqds.c| 4 +++ > > > board/freescale/ls1021atwr/ls1021atwr.c| 4 +++ > > > 5 files changed, 78 insertions(+), 1 deletion(-) > > > > > > diff --git a/arch/arm/include/asm/arch-ls102xa/config.h > > > b/arch/arm/include/asm/arch-ls102xa/config.h > > > index f066480..f14ea2f 100644 > > > --- a/arch/arm/include/asm/arch-ls102xa/config.h > > > +++ b/arch/arm/include/asm/arch-ls102xa/config.h > > > @@ -38,6 +38,7 @@ > > > #define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR > (CONFIG_SYS_IMMR + > > 0x0210) > > > #define CONFIG_SYS_LS102XA_USB1_ADDR \ > > > (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET) > > > +#define CONFIG_SYS_SMMU3_ADDR > (CONFIG_SYS_IMMR + > > 0x30) > > > > > > #define CONFIG_SYS_FSL_SEC_OFFSET0x0070 > > > #define CONFIG_SYS_LS102XA_USB1_OFFSET 0x0760 > > > diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h > > > b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h > > > index fa571b3..68e4e02 100644 > > > --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h > > > +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h > > > @@ -6,6 +6,39 @@ > > > > > > #ifndef __FSL_LS102XA_STREAM_ID_H_ > > > #define __FSL_LS102XA_STREAM_ID_H_ > > > +#define CONFIG_SMMU_NSCR_OFFSET 0x400 > > > +#define CONFIG_SMMU_SMR_OFFSET 0x800 > > > +#define CONFIG_SMMU_S2CR_OFFSET 0xc00 > > > + > > > +#define SMMU_NSCR_CLIENTPD_SHIFT 0 > > > +#define SMMU_NSCR_MTCFG_SHIFT20 > > > + > > > +#define SMR_SMR_VALID_SHIFT 31 > > > +#define SMR_ID_MASK 0x7fff > > > +#define SMR_MA
Re: [U-Boot] [PATCH v3 15/15] SECURE_BOOT: Enable IE (Key extention) Feature in Ls2085a & LS2088a
> -Original Message-
> From: Saksham Jain [mailto:saksham.j...@nxp.com]
> Sent: Monday, February 01, 2016 5:14 PM
> To: u-boot@lists.denx.de
> Cc: york sun <york@nxp.com>; Ruchika Gupta <ruchika.gu...@nxp.com>;
> Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>; Saksham Jain
> <saksham.j...@nxp.com>; Aneesh Bansal <aneesh.ban...@nxp.com>
> Subject: [PATCH v3 15/15] SECURE_BOOT: Enable IE (Key extention) Feature in
> Ls2085a & LS2088a
>
> For validating images from uboot (Such as Kernel Image), either keys from SoC
> fuses
> can be used or keys from a veriied table of public keys can be used. The
> latter feature
> is called IE Key Extension Feature.
>
> For earlier SoCs, BootROM used to verify IE Key Table and then write the
> address of
> this table in a secure register (SCRATCHREG). But in LS2088 and LS2085, no
> such
> secure registers are available. Hence IE Table is left to be verified by
> Uboot.
>
> The new procedure is to first verify IE table using Keys stored in fuses, and
> then use
> the keys in this table to verify further images. So the steps
> are:
>
> 1) Verify IE Table (If "IE Table Flag" set in any image i.e. Verify IE Table
> only when
> any image needs IE Table's Key to be verified)
> 2) Install IE table. (To be used across verification of multiple images.
> Stored in a static global structure.)
> 3) If IE flag enabled in header of any image, Use keys from IE table,
> otherwise use
> keys tied up with SoC's fuses (SRK).
>
> The address of IE Table HDR is fixed for NOR. In case of boot from other
> devices, IE
> Table and it's Header needs to be copied to an XIP Memory.
>
> Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
> Signed-off-by: Saksham Jain <saksham.j...@nxp.com>
> ---
> Changes for v2:
> - No changes
> Changes for v3:
> -changes to remove compliation warning for various platforms
>
> arch/arm/include/asm/fsl_secure_boot.h | 6 +--
> board/freescale/common/fsl_validate.c | 97 --
> include/fsl_validate.h | 23 +++-
> 3 files changed, 105 insertions(+), 21 deletions(-)
>
> diff --git a/arch/arm/include/asm/fsl_secure_boot.h
> b/arch/arm/include/asm/fsl_secure_boot.h
> index eafdc0b..061c9f5 100644
> --- a/arch/arm/include/asm/fsl_secure_boot.h
> +++ b/arch/arm/include/asm/fsl_secure_boot.h
> @@ -41,11 +41,11 @@
> * in boot ROM of the SoC.
> * The feature is only applicable in case of NOR boot and is
> * not applicable in case of RAMBOOT (NAND, SD, SPI).
> + * For LS, this feature is available for all device if IE Table
> + * is copied to XIP memory
> + * Also, for LS, ISBC doesn't verify this table.
> */
> -#ifndef CONFIG_ESBC_HDR_LS
> -/* Current Key EXT feature not available in LS ESBC Header */ #define
> CONFIG_FSL_ISBC_KEY_EXT -#endif
>
> #endif
>
> diff --git a/board/freescale/common/fsl_validate.c
> b/board/freescale/common/fsl_validate.c
> index 64e4e30..248a759 100644
> --- a/board/freescale/common/fsl_validate.c
> +++ b/board/freescale/common/fsl_validate.c
> @@ -27,6 +27,10 @@
> #define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES /
> 4) || \
>((key_len) == 2 * KEY_SIZE_BYTES / 2) || \
>((key_len) == 2 * KEY_SIZE_BYTES))
> +#if defined(CONFIG_FSL_ISBC_KEY_EXT)
> +/* Global data structure */
> +static struct fsl_secboot_glb glb;
> +#endif
>
> /* This array contains DER value for SHA-256 */ static const u8
> hash_identifier[] = {
> 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, @@ -60,7 +64,7 @@ self:
> #if defined(CONFIG_FSL_ISBC_KEY_EXT)
> static u32 check_ie(struct fsl_secboot_img_priv *img) {
> - if (img->hdr.ie_flag)
> + if (img->hdr.ie_flag & IE_FLAG_MASK)
> return 1;
>
> return 0;
> @@ -119,7 +123,8 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
> } #endif
>
> -static int get_ie_info_addr(u32 *ie_addr)
> +#if !defined(CONFIG_ESBC_HDR_LS)
> +static int get_ie_info_addr(uintptr_t *ie_addr)
> {
> struct fsl_secboot_img_hdr *hdr;
> struct fsl_secboot_sg_table *sg_tbl;
> @@ -147,16 +152,17 @@ static int get_ie_info_addr(u32 *ie_addr)
>
> /* IE Key Table is the first entry in the SG Table */ #if
> defined(CONFIG_MPC85xx)
> - *ie_addr = (sg_tbl->src_addr & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
> -flash_base_addr;
> + *ie_addr = (uintptr_t)((sg_tbl->src_addr &
> + ~(CONFIG_SYS_PBI_FLASH_BASE)) +
> + flash_base_addr);
> #else
&g
Re: [U-Boot] [PATCH v3 0/7] Determine Boot mode at run time
> -Original Message- > From: Tom Rini [mailto:tr...@konsulko.com] > Sent: Monday, January 25, 2016 9:06 PM > To: Aneesh Bansal <aneesh.ban...@nxp.com> > Cc: u-boot@lists.denx.de; Ruchika Gupta <ruchika.gu...@nxp.com> > Subject: Re: [U-Boot] [PATCH v3 0/7] Determine Boot mode at run time > > On Fri, Jan 22, 2016 at 04:37:21PM +0530, Aneesh Bansal wrote: > > > There are two phases in Secure Boot > > 1. ISBC: In BootROM, validate the BootLoader (U-Boot). > > 2. ESBC: In U-Boot, continuing the Chain of Trust by > > validating and booting LINUX. > > > > For ESBC phase, there is no difference in SoC's based on ARM or > > PowerPC cores. > > > > But the exit conditions after ISBC phase i.e. entry conditions for > > U-Boot are different for ARM and PowerPC. > > PowerPC: > > > > If Secure Boot is executed, a separate U-Boot target is required which > > must be compiled with a diffrent Text Base as compared to Non-Secure Boot. > > There are some LAW and TLB settings which are required specifically > > for Secure Boot scenario. > > > > ARM: > > > > ARM based SoC's have a fixed memory map and exit conditions from > > BootROM are same irrespective of boot mode (Secure or Non-Secure). > > > > This patchset is aimed at removing the requirement for a separate > > Secure Boot target for ARM based SoC's. > > > > Another Security Requirement for running CHAIN_OF_TRUST is that U-Boot > > environemnt must not be picked from flash/external memory. This cannot > > be done based on bootmode at run time in current U-Boot architecture. > > Once this dependency is resolved, no separate SECURE_BOOT target will be > required for ARM based SoC's. > > > > Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is > > defining CONFIG_ENV_IS_NOWHERE > > > > The patches have been tested on LS1043, LS1021, P3041 and T1024. > > > > The patch set is dependent on following: > > http://patchwork.ozlabs.org/patch/553826/ > > > > Aneesh Bansal (7): > > include/configs: make secure boot header file include uniform > > include/configs: move definition of CONFIG_CMD_BLOB > > SECURE_BOOT: split the secure boot functionality in two parts > > create function to determine boot mode > > enable chain of trust for ARM platforms > > enable chain of trust for PowerPC platforms > > SECURE_BOOT: change error handler for esbc_validate > > > > arch/arm/cpu/armv8/fsl-layerscape/soc.c| 6 ++ > > .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 + > > arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 + > > arch/arm/include/asm/fsl_secure_boot.h | 20 +++- > > arch/powerpc/cpu/mpc85xx/cpu_init.c| 14 +++ > > arch/powerpc/include/asm/fsl_secure_boot.h | 47 ++--- > > arch/powerpc/include/asm/immap_85xx.h | 3 + > > board/freescale/common/Makefile| 1 + > > board/freescale/common/cmd_esbc_validate.c | 7 +- > > board/freescale/common/fsl_chain_of_trust.c| 70 + > > board/freescale/common/fsl_validate.c | 7 ++ > > board/freescale/ls1021aqds/ls1021aqds.c| 4 + > > board/freescale/ls1021atwr/ls1021atwr.c| 4 + > > include/config_fsl_chain_trust.h | 101 ++ > > include/config_fsl_secboot.h | 116 > > - > > include/configs/B4860QDS.h | 4 - > > include/configs/BSC9132QDS.h | 4 - > > include/configs/P1010RDB.h | 4 - > > include/configs/P2041RDB.h | 4 - > > include/configs/T102xQDS.h | 10 +- > > include/configs/T102xRDB.h | 10 +- > > include/configs/T1040QDS.h | 3 - > > include/configs/T104xRDB.h | 3 - > > include/configs/T208xQDS.h | 4 - > > include/configs/T208xRDB.h | 4 - > > include/configs/T4240QDS.h | 4 - > > include/configs/T4240RDB.h | 9 -- > > include/configs/corenet_ds.h | 4 - > > include/configs/ls1021aqds.h | 5 +- > > include/configs/ls1021atwr.h | 5 +- > > include/configs/ls1043a_common.h | 8 ++ > > include/configs/ls1043aq
Re: [U-Boot] [PATCH v2 5/7] enable chain of trust for ARM platforms
> -Original Message- > From: york sun > Sent: Friday, January 22, 2016 1:52 AM > To: Aneesh Bansal <aneesh.ban...@nxp.com>; u-boot@lists.denx.de > Cc: Ruchika Gupta <ruchika.gu...@nxp.com>; Prabhakar Kushwaha > <prabhakar.kushw...@nxp.com> > Subject: Re: [PATCH v2 5/7] enable chain of trust for ARM platforms > > On 01/17/2016 01:42 AM, Aneesh Bansal wrote: > > Chain of Trust is enabled for ARM platforms (LS1021 and LS1043). > > In board_late_init(), fsl_setenv_chain_of_trust() is called which will > > perform the following: > > - If boot mode is non-secure, return (No Change) > > - If boot mode is secure, set the following environmet variables: > >bootdelay = 0 (To disable Boot Prompt) > >bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) > > > > Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> > > --- > > Changes in v2: > > Defconfigs for Secure Boot Target are not removed > > > > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 > > board/freescale/common/Makefile | 1 + > > board/freescale/common/fsl_chain_of_trust.c | 17 + > > board/freescale/ls1021aqds/ls1021aqds.c | 4 > > board/freescale/ls1021atwr/ls1021atwr.c | 4 > > include/fsl_validate.h | 2 ++ > > 6 files changed, 32 insertions(+) > > > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c > > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c > > index 23d6b73..2f92b55 100644 > > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c > > @@ -12,6 +12,7 @@ > > #include > > #include > > #include > > +#include > > Does this patch depend on other patches? It causes compiling error for > fsl_sec.h on ls2 > boards. > > error: #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE > is defined > > York I have patches for LS2 to be sent on top of this patchset. I will submit a new rev of the patch in which inclusion of is protected by CONFIG_CHAIN_OF_TRUST. When we add chain of trust support for LS2, CONFIG_SYS_FSL_SEC_LE will also be defined. Aneesh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 0/7] Determine Boot mode at run time
There are two phases in Secure Boot 1. ISBC: In BootROM, validate the BootLoader (U-Boot). 2. ESBC: In U-Boot, continuing the Chain of Trust by validating and booting LINUX. For ESBC phase, there is no difference in SoC's based on ARM or PowerPC cores. But the exit conditions after ISBC phase i.e. entry conditions for U-Boot are different for ARM and PowerPC. PowerPC: If Secure Boot is executed, a separate U-Boot target is required which must be compiled with a diffrent Text Base as compared to Non-Secure Boot. There are some LAW and TLB settings which are required specifically for Secure Boot scenario. ARM: ARM based SoC's have a fixed memory map and exit conditions from BootROM are same irrespective of boot mode (Secure or Non-Secure). This patchset is aimed at removing the requirement for a separate Secure Boot target for ARM based SoC's. Another Security Requirement for running CHAIN_OF_TRUST is that U-Boot environemnt must not be picked from flash/external memory. This cannot be done based on bootmode at run time in current U-Boot architecture. Once this dependency is resolved, no separate SECURE_BOOT target will be required for ARM based SoC's. Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining CONFIG_ENV_IS_NOWHERE The patches have been tested on LS1043, LS1021, P3041 and T1024. The patch set is dependent on following: http://patchwork.ozlabs.org/patch/553826/ Aneesh Bansal (7): include/configs: make secure boot header file include uniform include/configs: move definition of CONFIG_CMD_BLOB SECURE_BOOT: split the secure boot functionality in two parts create function to determine boot mode enable chain of trust for ARM platforms enable chain of trust for PowerPC platforms SECURE_BOOT: change error handler for esbc_validate arch/arm/cpu/armv8/fsl-layerscape/soc.c| 6 ++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 + arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 + arch/arm/include/asm/fsl_secure_boot.h | 20 +++- arch/powerpc/cpu/mpc85xx/cpu_init.c| 14 +++ arch/powerpc/include/asm/fsl_secure_boot.h | 47 ++--- arch/powerpc/include/asm/immap_85xx.h | 3 + board/freescale/common/Makefile| 1 + board/freescale/common/cmd_esbc_validate.c | 7 +- board/freescale/common/fsl_chain_of_trust.c| 70 + board/freescale/common/fsl_validate.c | 7 ++ board/freescale/ls1021aqds/ls1021aqds.c| 4 + board/freescale/ls1021atwr/ls1021atwr.c| 4 + include/config_fsl_chain_trust.h | 101 ++ include/config_fsl_secboot.h | 116 - include/configs/B4860QDS.h | 4 - include/configs/BSC9132QDS.h | 4 - include/configs/P1010RDB.h | 4 - include/configs/P2041RDB.h | 4 - include/configs/T102xQDS.h | 10 +- include/configs/T102xRDB.h | 10 +- include/configs/T1040QDS.h | 3 - include/configs/T104xRDB.h | 3 - include/configs/T208xQDS.h | 4 - include/configs/T208xRDB.h | 4 - include/configs/T4240QDS.h | 4 - include/configs/T4240RDB.h | 9 -- include/configs/corenet_ds.h | 4 - include/configs/ls1021aqds.h | 5 +- include/configs/ls1021atwr.h | 5 +- include/configs/ls1043a_common.h | 8 ++ include/configs/ls1043aqds.h | 2 + include/configs/ls1043ardb.h | 8 -- include/fsl_validate.h | 2 + 34 files changed, 299 insertions(+), 203 deletions(-) create mode 100644 board/freescale/common/fsl_chain_of_trust.c create mode 100644 include/config_fsl_chain_trust.h delete mode 100644 include/config_fsl_secboot.h -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 1/7] include/configs: make secure boot header file include uniform
The file fsl_secure_boot.h must be included in config file for Secure Boot. This is not required to be protected by any macro. CONFIG_FSL_CAAM must be defined and CONFIG_CMD_HASH should be turned on. The above was missing in some config files and all files have been made uniform in this respect. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> --- Changes in v3: None Changes in v2: None (Changed the Sign-Off with New E-Mail ID) arch/arm/include/asm/fsl_secure_boot.h | 5 + include/configs/C29XPCIE.h | 4 include/configs/T102xQDS.h | 12 +++- include/configs/T102xRDB.h | 12 +++- include/configs/T1040QDS.h | 3 ++- include/configs/T104xRDB.h | 3 ++- include/configs/T208xQDS.h | 3 ++- include/configs/T208xRDB.h | 3 ++- include/configs/ls1021aqds.h | 5 - include/configs/ls1021atwr.h | 5 - include/configs/ls1043a_common.h | 8 include/configs/ls1043aqds.h | 2 ++ include/configs/ls1043ardb.h | 8 13 files changed, 57 insertions(+), 16 deletions(-) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 806302b..b29e71c 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -34,6 +34,11 @@ #define CONFIG_FSL_ISBC_KEY_EXT #endif +#ifdef CONFIG_LS1043A +/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */ +#define CONFIG_ESBC_ADDR_64BIT +#endif + #ifndef CONFIG_FIT_SIGNATURE #define CONFIG_EXTRA_ENV \ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 16920c6..890dcbb 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -567,4 +567,8 @@ #include +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 951cbc4..fb41a7d 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -39,6 +39,8 @@ #define CONFIG_BOARD_EARLY_INIT_F #endif +#define CONFIG_FSL_CAAM/* Enable SEC/CAAM */ + #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg @@ -936,8 +938,16 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + #include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB #endif #endif /* __T1024QDS_H */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 4a0f5b2..113df37 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -33,6 +33,8 @@ #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_FSL_CAAM/* Enable SEC/CAAM */ + /* support deep sleep */ #ifdef CONFIG_PPC_T1024 #define CONFIG_DEEP_SLEEP @@ -948,8 +950,16 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + #include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB #endif #endif /* __T1024RDB_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 9e151da..5fd93a1 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -835,8 +835,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB #endif diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index da65f56..eec2971 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -938,8 +938,9 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB #endif diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index a0cecc6..019878a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -933,8 +933,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB #undef CONFIG_CMD_USB #endif diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 312b0eb..3665b7d 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -889,8 +889,9 @@ unsigne
[U-Boot] [PATCH v3 4/7] create function to determine boot mode
A function is created to detrmine if the boot mode is secure
or non-secure for differnt SoC's.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v3:
None
Changes in v2:
Corrected the macro for SB_EN bit in RCW.
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 ++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +
arch/powerpc/include/asm/immap_85xx.h | 3 ++
board/freescale/common/fsl_chain_of_trust.c| 53 ++
4 files changed, 61 insertions(+)
create mode 100644 board/freescale/common/fsl_chain_of_trust.c
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 21b803f..297ff35 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -218,6 +218,9 @@ struct ccsr_gur {
#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0x
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16
+#define RCW_SB_EN_REG_INDEX7
+#define RCW_SB_EN_MASK 0x0020
+
u8 res_140[0x200-0x140];
u32 scratchrw[4]; /* Scratch Read/Write */
u8 res_210[0x300-0x210];
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 89339fe..0a80772 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -120,6 +120,8 @@ struct ccsr_gur {
u32 brrl; /* Boot release */
u8 res_0e8[0x100-0xe8];
u32 rcwsr[16]; /* Reset control word status */
+#define RCW_SB_EN_REG_INDEX7
+#define RCW_SB_EN_MASK 0x0020
u8 res_140[0x200-0x140];
u32 scratchrw[4]; /* Scratch Read/Write */
u8 res_210[0x300-0x210];
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index bc7e5f8..53ca6d9 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1749,6 +1749,8 @@ typedef struct ccsr_gur {
u32 brrl; /* Boot release */
u8 res17[24];
u32 rcwsr[16]; /* Reset control word status */
+#define RCW_SB_EN_REG_INDEX7
+#define RCW_SB_EN_MASK 0x0020
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
@@ -2193,6 +2195,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR2_DDR_SPD_00x0008
#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
#endif
+#define MPC85xx_PORDEVSR2_SBC_MASK 0x1000
/* The 8544 RM says this is bit 26, but it's really bit 24 */
#define MPC85xx_PORDEVSR2_SEC_CFG 0x0080
u8 res1[8];
diff --git a/board/freescale/common/fsl_chain_of_trust.c
b/board/freescale/common/fsl_chain_of_trust.c
new file mode 100644
index 000..ff67bd7
--- /dev/null
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+
+#ifdef CONFIG_LS102XA
+#include
+#endif
+
+#if defined(CONFIG_MPC85xx)
+#define CONFIG_DCFG_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+#else
+#define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR
+#endif
+
+#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
+#define gur_in32(a) in_le32(a)
+#else
+#define gur_in32(a) in_be32(a)
+#endif
+
+/* Check the Boot Mode. If Secure, return 1 else return 0 */
+int fsl_check_boot_mode_secure(void)
+{
+ uint32_t val;
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR);
+
+ val = sfp_in32(_regs->ospr) & ITS_MASK;
+ if (val == ITS_MASK)
+ return 1;
+
+#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx)
+ /* For PBL based platforms check the SB_EN bit in RCWSR */
+ val = gur_in32(>rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK;
+ if (val == RCW_SB_EN_MASK)
+ return 1;
+#endif
+
+#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET)
+ /* For Non-PBL Platforms, check the Device Status register 2*/
+ val = gur_in32(>pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK;
+ if (val != MPC85xx_PORDEVSR2_SBC_MASK)
+ return 1;
+
+#endif
+ return 0;
+}
--
1.8.1.4
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[U-Boot] [PATCH v3 2/7] include/configs: move definition of CONFIG_CMD_BLOB
CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was earlier defined in all config files. The definition has been moved to a common file which is included by all configs. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> --- Changes in v3: None Changes in v2: None (Changed the Sign-Off with New E-Mail ID) arch/arm/include/asm/fsl_secure_boot.h | 1 + arch/powerpc/include/asm/fsl_secure_boot.h | 1 + include/configs/B4860QDS.h | 4 include/configs/BSC9132QDS.h | 4 include/configs/C29XPCIE.h | 4 include/configs/P1010RDB.h | 4 include/configs/P2041RDB.h | 4 include/configs/T102xQDS.h | 4 include/configs/T102xRDB.h | 4 include/configs/T1040QDS.h | 4 include/configs/T104xRDB.h | 4 include/configs/T208xQDS.h | 5 - include/configs/T208xRDB.h | 5 - include/configs/T4240QDS.h | 4 include/configs/T4240RDB.h | 9 - include/configs/corenet_ds.h | 4 include/configs/ls1021aqds.h | 4 include/configs/ls1021atwr.h | 4 18 files changed, 2 insertions(+), 71 deletions(-) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index b29e71c..8491a72 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -9,6 +9,7 @@ #ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_CMD_BLOB #define CONFIG_FSL_SEC_MON #define CONFIG_SHA_PROG_HW_ACCEL #define CONFIG_RSA diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 87415b1..7d217a6 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -10,6 +10,7 @@ #ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_CMD_BLOB #define CONFIG_FSL_SEC_MON #define CONFIG_SHA_PROG_HW_ACCEL #define CONFIG_DM diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 9fb5cee..bcbae50 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -924,8 +924,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index d0e5a25..89907dc 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -722,8 +722,4 @@ combinations. this should be removed later #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 890dcbb..16920c6 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -567,8 +567,4 @@ #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index f9776c0..3c0faca 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -952,8 +952,4 @@ extern unsigned long get_sdram_size(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index b2e51b5..f250e7f 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -756,8 +756,4 @@ unsigned long get_board_sys_clk(unsigned long dummy); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index fb41a7d..e5df784 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -946,8 +946,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __T1024QDS_H */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 113df37..3cda3b1 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -958,8 +958,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __T1024RDB_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 5fd93a1..2e7892f 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -837,8 +837,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index eec2971..5fc3497 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -940,8 +940,4 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_r
[U-Boot] [PATCH v3 7/7] SECURE_BOOT: change error handler for esbc_validate
In case of error while executing esbc_validate command, SNVS
transition and issue of reset is required only for secure-boot.
If boot mode is non-secure, this is not required.
Similarly, esbc_halt command which puts the core in Spin Loop
is applicable only for Secure Boot.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v3:
None
Changes in v2:
None (Changed the Sign-Off with New E-Mail ID)
board/freescale/common/cmd_esbc_validate.c | 7 ++-
board/freescale/common/fsl_validate.c | 7 +++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/board/freescale/common/cmd_esbc_validate.c
b/board/freescale/common/cmd_esbc_validate.c
index ca7c737..dfa3e21 100644
--- a/board/freescale/common/cmd_esbc_validate.c
+++ b/board/freescale/common/cmd_esbc_validate.c
@@ -11,6 +11,11 @@
static int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
+ if (fsl_check_boot_mode_secure() == 0) {
+ printf("Boot Mode is Non-Secure. Not entering spin loop.\n");
+ return 0;
+ }
+
printf("Core is entering spin loop.\n");
loop:
goto loop;
@@ -64,6 +69,6 @@ U_BOOT_CMD(
U_BOOT_CMD(
esbc_halt, 1, 0, do_esbc_halt,
- "Put the core in spin loop ",
+ "Put the core in spin loop (Secure Boot Only)",
""
);
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index de40081..8fd6dd6 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -370,6 +370,13 @@ void fsl_secboot_handle_error(int error)
printf("ERROR :: %x :: %s\n", error, e->name);
}
+ /* If Boot Mode is secure, transition the SNVS state and issue
+* reset based on type of failure and ITS setting.
+* If Boot mode is non-secure, return from this function.
+*/
+ if (fsl_check_boot_mode_secure() == 0)
+ return;
+
switch (error) {
case ERROR_ESBC_CLIENT_HEADER_BARKER:
case ERROR_ESBC_CLIENT_HEADER_IMG_SIZE:
--
1.8.1.4
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[U-Boot] [PATCH v3 6/7] enable chain of trust for PowerPC platforms
Chain of Trust is enabled for PowerPC platforms for Secure Boot.
CONFIG_BOARD_LATE_INIT is defined.
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
bootdelay = 0 (To disable Boot Prompt)
bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v3:
Protect the inclusion of file fsl_validate.h with macro CONFIG_CHAIN_OF_TRUST
Changes in v2:
None (Changed the Sign-Off with New E-Mail ID)
arch/powerpc/cpu/mpc85xx/cpu_init.c| 14 ++
arch/powerpc/include/asm/fsl_secure_boot.h | 7 +++
2 files changed, 21 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 50bb86a..a4dc140 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -27,6 +27,9 @@
#include
#include
#include "mp.h"
+#ifdef CONFIG_CHAIN_OF_TRUST
+#include
+#endif
#ifdef CONFIG_FSL_CAAM
#include
#endif
@@ -1011,3 +1014,14 @@ void cpu_secondary_init_r(void)
qe_reset();
#endif
}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
+
+ return 0;
+}
+#endif
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h
b/arch/powerpc/include/asm/fsl_secure_boot.h
index 41058d1..c45cace 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -87,6 +87,13 @@
#define CONFIG_FSL_CAAM
#endif
+/* fsl_setenv_chain_of_trust() must be called from
+ * board_late_init()
+ */
+#ifndef CONFIG_BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
+#endif
+
/* If Boot Script is not on NOR and is required to be copied on RAM */
#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
#define CONFIG_BS_HDR_ADDR_RAM 0x0001
--
1.8.1.4
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[U-Boot] [PATCH v3 3/7] SECURE_BOOT: split the secure boot functionality in two parts
There are two phases in Secure Boot 1. ISBC: In BootROM, validate the BootLoader (U-Boot). 2. ESBC: In U-Boot, continuing the Chain of Trust by validating and booting LINUX. For ESBC phase, there is no difference in SoC's based on ARM or PowerPC cores. But the exit conditions after ISBC phase i.e. entry conditions for U-Boot are different for ARM and PowerPC. PowerPC: If Secure Boot is executed, a separate U-Boot target is required which must be compiled with a diffrent Text Base as compared to Non-Secure Boot. There are some LAW and TLB settings which are required specifically for Secure Boot scenario. ARM: ARM based SoC's have a fixed memory map and exit conditions from BootROM are same irrespective of boot mode (Secure or Non-Secure). Thus the current Secure Boot functionlity has been split into two parts: CONFIG_CHAIN_OF_TRUST This will have the following functionality as part of U-Boot: 1. Enable commands like esbc_validate, esbc_halt 2. Change the environment settings based on bootmode (determined at run time): - If bootmode is non-secure, no change - If bootmode is secure, set the following: - bootdelay = 0 (Don't give boot prompt) - bootcmd = Validate and execute the bootscript. CONFIG_SECURE_BOOT = This is defined only for creating a different compile time target for secure boot. Traditionally, both these functionalities were defined under CONFIG_SECURE_BOOT This patch is aimed at removing the requirement for a separate Secure Boot target for ARM based SoC's. CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be determine at run time. Another Security Requirement for running CHAIN_OF_TRUST is that U-Boot environemnt must not be picked from flash/external memory. This cannot be done based on bootmode at run time in current U-Boot architecture. Once this dependency is resolved, no separate SECURE_BOOT target will be required for ARM based SoC's. Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining CONFIG_ENV_IS_NOWHERE Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> --- Changes in v3: None Changes in v2: CONFIG_ENV_IS_NOWHERE is defined for Secure Boot arch/arm/include/asm/fsl_secure_boot.h | 16 ++-- arch/powerpc/include/asm/fsl_secure_boot.h | 41 +- include/config_fsl_chain_trust.h | 101 + include/config_fsl_secboot.h | 116 - 4 files changed, 135 insertions(+), 139 deletions(-) create mode 100644 include/config_fsl_chain_trust.h delete mode 100644 include/config_fsl_secboot.h diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 8491a72..0da0599 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -8,6 +8,14 @@ #define __FSL_SECURE_BOOT_H #ifdef CONFIG_SECURE_BOOT + +#ifndef CONFIG_FIT_SIGNATURE +#define CONFIG_CHAIN_OF_TRUST +#endif + +#endif + +#ifdef CONFIG_CHAIN_OF_TRUST #define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_CMD_BLOB #define CONFIG_FSL_SEC_MON @@ -40,8 +48,6 @@ #define CONFIG_ESBC_ADDR_64BIT #endif -#ifndef CONFIG_FIT_SIGNATURE - #define CONFIG_EXTRA_ENV \ "setenv fdt_high 0xcfff;" \ "setenv initrd_high 0xcfff;"\ @@ -50,8 +56,6 @@ /* The address needs to be modified according to NOR memory map */ #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a -#include -#endif -#endif - +#include +#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 7d217a6..41058d1 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -9,19 +9,11 @@ #include #ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_ESBC_VALIDATE -#define CONFIG_CMD_BLOB -#define CONFIG_FSL_SEC_MON -#define CONFIG_SHA_PROG_HW_ACCEL -#define CONFIG_DM -#define CONFIG_RSA -#define CONFIG_RSA_FREESCALE_EXP -#ifndef CONFIG_FSL_CAAM -#define CONFIG_FSL_CAAM -#endif + +#ifndef CONFIG_FIT_SIGNATURE +#define CONFIG_CHAIN_OF_TRUST #endif -#ifdef CONFIG_SECURE_BOOT #if defined(CONFIG_FSL_CORENET) #define CONFIG_SYS_PBI_FLASH_BASE 0xc000 #elif defined(CONFIG_BSC9132QDS) @@ -76,8 +68,25 @@ */ #define CONFIG_FSL_ISBC_KEY_EXT #endif +#endif /* #ifdef CONFIG_SECURE_BOOT */ + +#ifdef CONFIG_CHAIN_OF_TRUST + +#define CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_CMD_BLOB +#define CONFIG_FSL_SEC_MON +#define CONFIG_SHA_PROG_HW_ACCEL +#define CONFIG_RSA +#define CONFIG_RSA_FREESCALE_EXP + +#ifndef CONFIG_DM +#define CONFIG_DM +#endif + +#ifndef CONFIG_FSL_CAAM +#define CONFIG_FSL_CAAM +#endif -#ifndef CONFIG_FIT_SIGNATURE /* If Boot Script is not on NOR and is required to be copied on RAM */ #ifdef CONFIG_BOOTSCRIPT_COPY_RAM #define CONFIG_BS_HDR_ADDR_RAM 0x
[U-Boot] [PATCH v3 5/7] enable chain of trust for ARM platforms
Chain of Trust is enabled for ARM platforms (LS1021 and LS1043).
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
bootdelay = 0 (To disable Boot Prompt)
bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v3:
Protect the inclusion of file fsl_validate.h with macro CONFIG_CHAIN_OF_TRUST
Changes in v2:
Defconfigs for Secure Boot Target are not removed.
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 ++
board/freescale/common/Makefile | 1 +
board/freescale/common/fsl_chain_of_trust.c | 17 +
board/freescale/ls1021aqds/ls1021aqds.c | 4
board/freescale/ls1021atwr/ls1021atwr.c | 4
include/fsl_validate.h | 2 ++
6 files changed, 34 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 23d6b73..d97a445 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -12,6 +12,9 @@
#include
#include
#include
+#ifdef CONFIG_CHAIN_OF_TRUST
+#include
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -241,6 +244,9 @@ int board_late_init(void)
#ifdef CONFIG_SCSI_AHCI_PLAT
sata_init();
#endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
return 0;
}
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 51d2814..be114ce 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -76,5 +76,6 @@ obj-$(CONFIG_LAYERSCAPE_NS_ACCESS)+= ns_access.o
ifdef CONFIG_SECURE_BOOT
obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o
endif
+obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o
endif
diff --git a/board/freescale/common/fsl_chain_of_trust.c
b/board/freescale/common/fsl_chain_of_trust.c
index ff67bd7..ecfcc82 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -51,3 +51,20 @@ int fsl_check_boot_mode_secure(void)
#endif
return 0;
}
+
+int fsl_setenv_chain_of_trust(void)
+{
+ /* Check Boot Mode
+* If Boot Mode is Non-Secure, no changes are required
+*/
+ if (fsl_check_boot_mode_secure() == 0)
+ return 0;
+
+ /* If Boot mode is Secure, set the environment variables
+* bootdelay = 0 (To disable Boot Prompt)
+* bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
+*/
+ setenv("bootdelay", "0");
+ setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD);
+ return 0;
+}
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
b/board/freescale/ls1021aqds/ls1021aqds.c
index ca1ea61..6e82232 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#include "../common/sleep.h"
#include "../common/qixis.h"
@@ -369,6 +370,9 @@ int board_late_init(void)
#ifdef CONFIG_SCSI_AHCI_PLAT
ls1021a_sata_init();
#endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
return 0;
}
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
b/board/freescale/ls1021atwr/ls1021atwr.c
index ae62bca..054cc3d 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -30,6 +30,7 @@
#ifdef CONFIG_U_QE
#include "../../../drivers/qe/qe.h"
#endif
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -553,6 +554,9 @@ int board_late_init(void)
#ifdef CONFIG_SCSI_AHCI_PLAT
ls1021a_sata_init();
#endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
return 0;
}
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index ad14867..83efcf4 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -205,4 +205,6 @@ int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int
argc,
int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[]);
+int fsl_check_boot_mode_secure(void);
+int fsl_setenv_chain_of_trust(void);
#endif
--
1.8.1.4
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[U-Boot] [PATCH v4] powerpc/SECURE_BOOT: Add PAMU driver
PAMU driver basic support for usage in Secure Boot.
In secure boot PAMU is not in bypass mode. Hence to use
any peripheral (SEC Job ring in our case), PAMU has to be
configured.
The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3.
The Header file pamu.h and few functions in driver have been derived
from Freescale Libos.
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v4:
Resolved the format specifier warning by printf()
Changes in v3:
Replace the Debug printf() call with debug()
Merged the two commits into a single commit
Changes in v2:
Replace the Debug printf() call with debug()
arch/powerpc/cpu/mpc85xx/cpu_init.c | 18 +-
arch/powerpc/cpu/mpc8xxx/Makefile | 1 +
arch/powerpc/cpu/mpc8xxx/fsl_pamu.c | 433 ++
arch/powerpc/cpu/mpc8xxx/pamu_table.c | 55 +
arch/powerpc/include/asm/fsl_pamu.h | 169 +
arch/powerpc/include/asm/immap_85xx.h | 19 +-
drivers/crypto/fsl/jr.c | 23 ++
7 files changed, 709 insertions(+), 9 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
create mode 100644 arch/powerpc/cpu/mpc8xxx/pamu_table.c
create mode 100644 arch/powerpc/include/asm/fsl_pamu.h
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 13a7d0f..50bb86a 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -30,6 +30,10 @@
#ifdef CONFIG_FSL_CAAM
#include
#endif
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+#include
+#include
+#endif
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include
#include
@@ -425,8 +429,7 @@ void fsl_erratum_a007212_workaround(void)
ulong cpu_init_f(void)
{
extern void m8560_cpm_reset (void);
-#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
- (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_SECURE_BOOT)
@@ -458,12 +461,6 @@ ulong cpu_init_f(void)
#if defined(CONFIG_SYS_CPC_REINIT_F)
disable_cpc_sram();
#endif
-
-#if defined(CONFIG_FSL_CORENET)
- /* Put PAMU in bypass mode */
- out_be32(>pamubypenr, FSL_CORENET_PAMU_BYPASS);
-#endif
-
#endif
#ifdef CONFIG_CPM2
@@ -940,6 +937,11 @@ int cpu_init_r(void)
fman_enet_init();
#endif
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+ if (pamu_init() < 0)
+ fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
+#endif
+
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile
b/arch/powerpc/cpu/mpc8xxx/Makefile
index ac45e0e..c5592cd 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -24,5 +24,6 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
obj-$(CONFIG_SYS_SRIO) += srio.o
obj-$(CONFIG_FSL_LAW) += law.o
+obj-$(CONFIG_FSL_CORENET) += fsl_pamu.o pamu_table.o
endif
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
new file mode 100644
index 000..9421f1e
--- /dev/null
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
@@ -0,0 +1,433 @@
+/*
+ * FSL PAMU driver
+ *
+ * Copyright 2012-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+struct paace *ppaact;
+struct paace *sec;
+unsigned long fspi;
+
+static inline int __ilog2_roundup_64(uint64_t val)
+{
+ if ((val & (val - 1)) == 0)
+ return __ilog2_u64(val);
+ else
+ return __ilog2_u64(val) + 1;
+}
+
+
+static inline int count_lsb_zeroes(unsigned long val)
+{
+ return ffs(val) - 1;
+}
+
+static unsigned int map_addrspace_size_to_wse(uint64_t addrspace_size)
+{
+ /* window size is 2^(WSE+1) bytes */
+ return count_lsb_zeroes(addrspace_size >> PAMU_PAGE_SHIFT) +
+ PAMU_PAGE_SHIFT - 1;
+}
+
+static unsigned int map_subwindow_cnt_to_wce(uint32_t subwindow_cnt)
+{
+ /* window count is 2^(WCE+1) bytes */
+ return count_lsb_zeroes(subwindow_cnt) - 1;
+}
+
+static void pamu_setup_default_xfer_to_host_ppaace(struct paace *ppaace)
+{
+ set_bf(ppaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_PRIMARY);
+ set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+ PAACE_M_COHERENCE_REQ);
+}
+
+static void pamu_setup_default_xfer_to_host_spaace(struct paace *spaace)
+{
+ set_bf(spaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_SECONDARY);
+ set_bf(spaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+ PAACE_M_COHERENCE_REQ);
+}
+
+/** Sets up PPAACE entry for specified liodn
+ *
+ * @param[in] liodn Logical IO device number
+ * @param[in] win_addr starting address of DS
[U-Boot] [PATCH v3] Enable snooping on transactions from CAAM block
To enable snooping on CAAM transactions following programming is done
1. Enable core snooping (CCI interface, Core is Slave5 on CCI)
This setting is also required for making the system coherent
2. CAAM IP lies behind SMMU3 in the system. Configure SMMU3 to do the following:
a) Program SCR to bypass transactions with stream ID other than that of CAAM
b) Program S2CR to change memroy attributes of transactions with CAAM's stream
ID (0x10) to cacheable.
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Nitesh Narayan Lal <nitesh@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v3:
Modified the commit message.
Changes in v2:
Avoid mixing the use of u32 and uint32_t.
Using uint32_t at all places.
arch/arm/include/asm/arch-ls102xa/config.h | 1 +
.../include/asm/arch-ls102xa/ls102xa_stream_id.h | 34
board/freescale/common/ls102xa_stream_id.c | 36 +-
board/freescale/ls1021aqds/ls1021aqds.c| 4 +++
board/freescale/ls1021atwr/ls1021atwr.c| 4 +++
5 files changed, 78 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
b/arch/arm/include/asm/arch-ls102xa/config.h
index f066480..f14ea2f 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -38,6 +38,7 @@
#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x0210)
#define CONFIG_SYS_LS102XA_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
+#define CONFIG_SYS_SMMU3_ADDR (CONFIG_SYS_IMMR + 0x30)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x0070
#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x0760
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
index fa571b3..68e4e02 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
@@ -6,6 +6,39 @@
#ifndef __FSL_LS102XA_STREAM_ID_H_
#define __FSL_LS102XA_STREAM_ID_H_
+#define CONFIG_SMMU_NSCR_OFFSET0x400
+#define CONFIG_SMMU_SMR_OFFSET 0x800
+#define CONFIG_SMMU_S2CR_OFFSET0xc00
+
+#define SMMU_NSCR_CLIENTPD_SHIFT 0
+#define SMMU_NSCR_MTCFG_SHIFT 20
+
+#define SMR_SMR_VALID_SHIFT31
+#define SMR_ID_MASK0x7fff
+#define SMR_MASK_SHIFT 16
+
+#define S2CR_WACFG_SHIFT 22
+#define S2CR_WACFG_MASK0x3
+#define S2CR_WACFG_WRITE_ALLOCATE 0x2
+
+#define S2CR_RACFG_SHIFT 20
+#define S2CR_RACFG_MASK0x3
+#define S2CR_RACFG_READ_ALLOCATE 0x2
+
+#define S2CR_TYPE_SHIFT16
+#define S2CR_TYPE_MASK 0x3
+#define S2CR_TYPE_BYPASS 0x01
+
+#define S2CR_MEM_ATTR_SHIFT12
+#define S2CR_MEM_ATTR_MASK 0xf
+#define S2CR_MEM_ATTR_CACHEABLE0xa
+
+#define S2CR_MTCFG 0x0800
+
+#define S2CR_SHCFG_SHIFT 8
+#define S2CR_SHCFG_MASK0x3
+#define S2CR_SHCFG_OUTER_CACHEABLE 0x1
+#define S2CR_SHCFG_INNER_CACHEABLE 0x2
#include
@@ -71,4 +104,5 @@ struct smmu_stream_id {
void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size);
void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
+void ls1021x_config_smmu3(uint32_t liodn);
#endif
diff --git a/board/freescale/common/ls102xa_stream_id.c
b/board/freescale/common/ls102xa_stream_id.c
index f434269..9ae29b8 100644
--- a/board/freescale/common/ls102xa_stream_id.c
+++ b/board/freescale/common/ls102xa_stream_id.c
@@ -20,7 +20,7 @@ void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id,
uint32_t num)
void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
{
int i;
- u32 liodn;
+ uint32_t liodn;
for (i = 0; i < size; i++) {
if (tbl[i].num_ids == 2)
@@ -31,3 +31,37 @@ void ls1021x_config_caam_stream_id(struct liodn_id_table
*tbl, int size)
out_le32((uint32_t *)(tbl[i].reg_offset), liodn);
}
}
+
+void ls1021x_config_smmu3(uint32_t liodn)
+{
+ uint32_t *addr;
+ uint32_t smr, s2cr, nscr;
+
+ addr = (uint32_t *)(CONFIG_SYS_SMMU3_ADDR + CONFIG_SMMU_NSCR_OFFSET);
+ /* SMMU NSCR configuration */
+ nscr = in_le32(addr);
+
+ nscr = nscr & ~(1 << SMMU_NSCR_CLIENTPD_SHIFT |
+1 << SMMU_NSCR_MTCFG_SHIFT);
+ out_le32(addr, nscr);
+
+ /* SMMU SMR configuration */
+ addr = (uint32_t *)(CONFIG_SYS_SMMU3_ADDR + CONFIG_SMMU_SMR_OFFSET);
+
+ smr = 0;
+ smr = smr & (~(SMR_ID_MASK << SMR_MASK_SHIFT));
+ smr = smr | (1 << SMR_SMR_VALID_SHIFT) | liodn;
[U-Boot] [PATCH v2] Enable snooping on transactions from CAAM block
To enable snooping on CAAM transactions following programmign is done
1. Enable core snooping (CCI interface, Core is Slave5 on CCI)
This setting is also required for making the system coherent
2. CAAM IP lies behind SMMU3 in teh system. Configure SMMU3 to do teh following:
a) Program SCR to bypass transactions with stream ID other than taht of CAAM
b_ Program S2CR to change memroy attributes of transactions with CAAM's stream
ID (0x10) to cacheable.
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Nitesh Narayan Lal <nitesh@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v2:
Avoid mixing the use of u32 and uint32_t.
Using uint32_t at all places.
arch/arm/include/asm/arch-ls102xa/config.h | 1 +
.../include/asm/arch-ls102xa/ls102xa_stream_id.h | 34
board/freescale/common/ls102xa_stream_id.c | 36 +-
board/freescale/ls1021aqds/ls1021aqds.c| 4 +++
board/freescale/ls1021atwr/ls1021atwr.c| 4 +++
5 files changed, 78 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
b/arch/arm/include/asm/arch-ls102xa/config.h
index f066480..f14ea2f 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -38,6 +38,7 @@
#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x0210)
#define CONFIG_SYS_LS102XA_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
+#define CONFIG_SYS_SMMU3_ADDR (CONFIG_SYS_IMMR + 0x30)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x0070
#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x0760
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
index fa571b3..68e4e02 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
@@ -6,6 +6,39 @@
#ifndef __FSL_LS102XA_STREAM_ID_H_
#define __FSL_LS102XA_STREAM_ID_H_
+#define CONFIG_SMMU_NSCR_OFFSET0x400
+#define CONFIG_SMMU_SMR_OFFSET 0x800
+#define CONFIG_SMMU_S2CR_OFFSET0xc00
+
+#define SMMU_NSCR_CLIENTPD_SHIFT 0
+#define SMMU_NSCR_MTCFG_SHIFT 20
+
+#define SMR_SMR_VALID_SHIFT31
+#define SMR_ID_MASK0x7fff
+#define SMR_MASK_SHIFT 16
+
+#define S2CR_WACFG_SHIFT 22
+#define S2CR_WACFG_MASK0x3
+#define S2CR_WACFG_WRITE_ALLOCATE 0x2
+
+#define S2CR_RACFG_SHIFT 20
+#define S2CR_RACFG_MASK0x3
+#define S2CR_RACFG_READ_ALLOCATE 0x2
+
+#define S2CR_TYPE_SHIFT16
+#define S2CR_TYPE_MASK 0x3
+#define S2CR_TYPE_BYPASS 0x01
+
+#define S2CR_MEM_ATTR_SHIFT12
+#define S2CR_MEM_ATTR_MASK 0xf
+#define S2CR_MEM_ATTR_CACHEABLE0xa
+
+#define S2CR_MTCFG 0x0800
+
+#define S2CR_SHCFG_SHIFT 8
+#define S2CR_SHCFG_MASK0x3
+#define S2CR_SHCFG_OUTER_CACHEABLE 0x1
+#define S2CR_SHCFG_INNER_CACHEABLE 0x2
#include
@@ -71,4 +104,5 @@ struct smmu_stream_id {
void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size);
void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
+void ls1021x_config_smmu3(uint32_t liodn);
#endif
diff --git a/board/freescale/common/ls102xa_stream_id.c
b/board/freescale/common/ls102xa_stream_id.c
index f434269..9ae29b8 100644
--- a/board/freescale/common/ls102xa_stream_id.c
+++ b/board/freescale/common/ls102xa_stream_id.c
@@ -20,7 +20,7 @@ void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id,
uint32_t num)
void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
{
int i;
- u32 liodn;
+ uint32_t liodn;
for (i = 0; i < size; i++) {
if (tbl[i].num_ids == 2)
@@ -31,3 +31,37 @@ void ls1021x_config_caam_stream_id(struct liodn_id_table
*tbl, int size)
out_le32((uint32_t *)(tbl[i].reg_offset), liodn);
}
}
+
+void ls1021x_config_smmu3(uint32_t liodn)
+{
+ uint32_t *addr;
+ uint32_t smr, s2cr, nscr;
+
+ addr = (uint32_t *)(CONFIG_SYS_SMMU3_ADDR + CONFIG_SMMU_NSCR_OFFSET);
+ /* SMMU NSCR configuration */
+ nscr = in_le32(addr);
+
+ nscr = nscr & ~(1 << SMMU_NSCR_CLIENTPD_SHIFT |
+1 << SMMU_NSCR_MTCFG_SHIFT);
+ out_le32(addr, nscr);
+
+ /* SMMU SMR configuration */
+ addr = (uint32_t *)(CONFIG_SYS_SMMU3_ADDR + CONFIG_SMMU_SMR_OFFSET);
+
+ smr = 0;
+ smr = smr & (~(SMR_ID_MASK << SMR_MASK_SHIFT));
+ smr = smr | (1 << SMR_SMR_VALID_SHIFT) | liodn;
+
+ out_le32(addr, smr);
+
+ /
[U-Boot] [PATCH v2 0/7] Determine Boot mode at run time
There are two phases in Secure Boot 1. ISBC: In BootROM, validate the BootLoader (U-Boot). 2. ESBC: In U-Boot, continuing the Chain of Trust by validating and booting LINUX. For ESBC phase, there is no difference in SoC's based on ARM or PowerPC cores. But the exit conditions after ISBC phase i.e. entry conditions for U-Boot are different for ARM and PowerPC. PowerPC: If Secure Boot is executed, a separate U-Boot target is required which must be compiled with a diffrent Text Base as compared to Non-Secure Boot. There are some LAW and TLB settings which are required specifically for Secure Boot scenario. ARM: ARM based SoC's have a fixed memory map and exit conditions from BootROM are same irrespective of boot mode (Secure or Non-Secure). This patchset is aimed at removing the requirement for a separate Secure Boot target for ARM based SoC's. Another Security Requirement for running CHAIN_OF_TRUST is that U-Boot environemnt must not be picked from flash/external memory. This cannot be done based on bootmode at run time in current U-Boot architecture. Once this dependency is resolved, no separate SECURE_BOOT target will be required for ARM based SoC's. Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining CONFIG_ENV_IS_NOWHERE The patches have been tested on LS1043, LS1021, P3041 and T1024. The patch set is dependent on following: http://patchwork.ozlabs.org/patch/553826/ Aneesh Bansal (7): include/configs: make secure boot header file include uniform include/configs: move definition of CONFIG_CMD_BLOB SECURE_BOOT: split the secure boot functionality in two parts create function to determine boot mode enable chain of trust for ARM platforms enable chain of trust for PowerPC platforms SECURE_BOOT: change error handler for esbc_validate arch/arm/cpu/armv8/fsl-layerscape/soc.c| 4 + .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 + arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 + arch/arm/include/asm/fsl_secure_boot.h | 20 +++- arch/powerpc/cpu/mpc85xx/cpu_init.c| 12 +++ arch/powerpc/include/asm/fsl_secure_boot.h | 47 ++--- arch/powerpc/include/asm/immap_85xx.h | 3 + board/freescale/common/Makefile| 1 + board/freescale/common/cmd_esbc_validate.c | 7 +- board/freescale/common/fsl_chain_of_trust.c| 70 + board/freescale/common/fsl_validate.c | 7 ++ board/freescale/ls1021aqds/ls1021aqds.c| 4 + board/freescale/ls1021atwr/ls1021atwr.c| 4 + include/config_fsl_chain_trust.h | 101 ++ include/config_fsl_secboot.h | 116 - include/configs/B4860QDS.h | 4 - include/configs/BSC9132QDS.h | 4 - include/configs/P1010RDB.h | 4 - include/configs/P2041RDB.h | 4 - include/configs/T102xQDS.h | 10 +- include/configs/T102xRDB.h | 10 +- include/configs/T1040QDS.h | 3 - include/configs/T104xRDB.h | 3 - include/configs/T208xQDS.h | 4 - include/configs/T208xRDB.h | 4 - include/configs/T4240QDS.h | 4 - include/configs/T4240RDB.h | 9 -- include/configs/corenet_ds.h | 4 - include/configs/ls1021aqds.h | 5 +- include/configs/ls1021atwr.h | 5 +- include/configs/ls1043a_common.h | 8 ++ include/configs/ls1043aqds.h | 2 + include/configs/ls1043ardb.h | 8 -- include/fsl_validate.h | 2 + 34 files changed, 295 insertions(+), 203 deletions(-) create mode 100644 board/freescale/common/fsl_chain_of_trust.c create mode 100644 include/config_fsl_chain_trust.h delete mode 100644 include/config_fsl_secboot.h -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/7] include/configs: make secure boot header file include uniform
The file fsl_secure_boot.h must be included in config file for Secure Boot. This is not required to be protected by any macro. CONFIG_FSL_CAAM must be defined and CONFIG_CMD_HASH should be turned on. The above was missing in some config files and all files have been made uniform in this respect. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> --- Changes in v2: None (Changed the Sign-Off with New E-Mail ID) arch/arm/include/asm/fsl_secure_boot.h | 5 + include/configs/C29XPCIE.h | 4 include/configs/T102xQDS.h | 12 +++- include/configs/T102xRDB.h | 12 +++- include/configs/T1040QDS.h | 3 ++- include/configs/T104xRDB.h | 3 ++- include/configs/T208xQDS.h | 3 ++- include/configs/T208xRDB.h | 3 ++- include/configs/ls1021aqds.h | 5 - include/configs/ls1021atwr.h | 5 - include/configs/ls1043a_common.h | 8 include/configs/ls1043aqds.h | 2 ++ include/configs/ls1043ardb.h | 8 13 files changed, 57 insertions(+), 16 deletions(-) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 806302b..b29e71c 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -34,6 +34,11 @@ #define CONFIG_FSL_ISBC_KEY_EXT #endif +#ifdef CONFIG_LS1043A +/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */ +#define CONFIG_ESBC_ADDR_64BIT +#endif + #ifndef CONFIG_FIT_SIGNATURE #define CONFIG_EXTRA_ENV \ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 16920c6..890dcbb 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -567,4 +567,8 @@ #include +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 951cbc4..fb41a7d 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -39,6 +39,8 @@ #define CONFIG_BOARD_EARLY_INIT_F #endif +#define CONFIG_FSL_CAAM/* Enable SEC/CAAM */ + #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg @@ -936,8 +938,16 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + #include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB #endif #endif /* __T1024QDS_H */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 4a0f5b2..113df37 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -33,6 +33,8 @@ #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_FSL_CAAM/* Enable SEC/CAAM */ + /* support deep sleep */ #ifdef CONFIG_PPC_T1024 #define CONFIG_DEEP_SLEEP @@ -948,8 +950,16 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + #include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB #endif #endif /* __T1024RDB_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 9e151da..5fd93a1 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -835,8 +835,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB #endif diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index da65f56..eec2971 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -938,8 +938,9 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB #endif diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index a0cecc6..019878a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -933,8 +933,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB #undef CONFIG_CMD_USB #endif diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 312b0eb..3665b7d 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -889,8 +889,9 @@ unsigned long get_board_ddr_cl
[U-Boot] [PATCH v2 4/7] create function to determine boot mode
A function is created to detrmine if the boot mode is secure
or non-secure for differnt SoC's.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v2:
Corrected the macro for SB_EN bit in RCW.
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 ++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +
arch/powerpc/include/asm/immap_85xx.h | 3 ++
board/freescale/common/fsl_chain_of_trust.c| 53 ++
4 files changed, 61 insertions(+)
create mode 100644 board/freescale/common/fsl_chain_of_trust.c
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 21b803f..297ff35 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -218,6 +218,9 @@ struct ccsr_gur {
#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0x
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16
+#define RCW_SB_EN_REG_INDEX7
+#define RCW_SB_EN_MASK 0x0020
+
u8 res_140[0x200-0x140];
u32 scratchrw[4]; /* Scratch Read/Write */
u8 res_210[0x300-0x210];
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 89339fe..0a80772 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -120,6 +120,8 @@ struct ccsr_gur {
u32 brrl; /* Boot release */
u8 res_0e8[0x100-0xe8];
u32 rcwsr[16]; /* Reset control word status */
+#define RCW_SB_EN_REG_INDEX7
+#define RCW_SB_EN_MASK 0x0020
u8 res_140[0x200-0x140];
u32 scratchrw[4]; /* Scratch Read/Write */
u8 res_210[0x300-0x210];
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index bc7e5f8..53ca6d9 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1749,6 +1749,8 @@ typedef struct ccsr_gur {
u32 brrl; /* Boot release */
u8 res17[24];
u32 rcwsr[16]; /* Reset control word status */
+#define RCW_SB_EN_REG_INDEX7
+#define RCW_SB_EN_MASK 0x0020
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
@@ -2193,6 +2195,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR2_DDR_SPD_00x0008
#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
#endif
+#define MPC85xx_PORDEVSR2_SBC_MASK 0x1000
/* The 8544 RM says this is bit 26, but it's really bit 24 */
#define MPC85xx_PORDEVSR2_SEC_CFG 0x0080
u8 res1[8];
diff --git a/board/freescale/common/fsl_chain_of_trust.c
b/board/freescale/common/fsl_chain_of_trust.c
new file mode 100644
index 000..ff67bd7
--- /dev/null
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+
+#ifdef CONFIG_LS102XA
+#include
+#endif
+
+#if defined(CONFIG_MPC85xx)
+#define CONFIG_DCFG_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+#else
+#define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR
+#endif
+
+#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
+#define gur_in32(a) in_le32(a)
+#else
+#define gur_in32(a) in_be32(a)
+#endif
+
+/* Check the Boot Mode. If Secure, return 1 else return 0 */
+int fsl_check_boot_mode_secure(void)
+{
+ uint32_t val;
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR);
+
+ val = sfp_in32(_regs->ospr) & ITS_MASK;
+ if (val == ITS_MASK)
+ return 1;
+
+#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx)
+ /* For PBL based platforms check the SB_EN bit in RCWSR */
+ val = gur_in32(>rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK;
+ if (val == RCW_SB_EN_MASK)
+ return 1;
+#endif
+
+#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET)
+ /* For Non-PBL Platforms, check the Device Status register 2*/
+ val = gur_in32(>pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK;
+ if (val != MPC85xx_PORDEVSR2_SBC_MASK)
+ return 1;
+
+#endif
+ return 0;
+}
--
1.8.1.4
___
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[U-Boot] [PATCH v2 3/7] SECURE_BOOT: split the secure boot functionality in two parts
There are two phases in Secure Boot 1. ISBC: In BootROM, validate the BootLoader (U-Boot). 2. ESBC: In U-Boot, continuing the Chain of Trust by validating and booting LINUX. For ESBC phase, there is no difference in SoC's based on ARM or PowerPC cores. But the exit conditions after ISBC phase i.e. entry conditions for U-Boot are different for ARM and PowerPC. PowerPC: If Secure Boot is executed, a separate U-Boot target is required which must be compiled with a diffrent Text Base as compared to Non-Secure Boot. There are some LAW and TLB settings which are required specifically for Secure Boot scenario. ARM: ARM based SoC's have a fixed memory map and exit conditions from BootROM are same irrespective of boot mode (Secure or Non-Secure). Thus the current Secure Boot functionlity has been split into two parts: CONFIG_CHAIN_OF_TRUST This will have the following functionality as part of U-Boot: 1. Enable commands like esbc_validate, esbc_halt 2. Change the environment settings based on bootmode (determined at run time): - If bootmode is non-secure, no change - If bootmode is secure, set the following: - bootdelay = 0 (Don't give boot prompt) - bootcmd = Validate and execute the bootscript. CONFIG_SECURE_BOOT = This is defined only for creating a different compile time target for secure boot. Traditionally, both these functionalities were defined under CONFIG_SECURE_BOOT This patch is aimed at removing the requirement for a separate Secure Boot target for ARM based SoC's. CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be determine at run time. Another Security Requirement for running CHAIN_OF_TRUST is that U-Boot environemnt must not be picked from flash/external memory. This cannot be done based on bootmode at run time in current U-Boot architecture. Once this dependency is resolved, no separate SECURE_BOOT target will be required for ARM based SoC's. Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining CONFIG_ENV_IS_NOWHERE Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> --- Changes in v2: CONFIG_ENV_IS_NOWHERE is defined for Secure Boot arch/arm/include/asm/fsl_secure_boot.h | 16 ++-- arch/powerpc/include/asm/fsl_secure_boot.h | 41 +- include/config_fsl_chain_trust.h | 101 + include/config_fsl_secboot.h | 116 - 4 files changed, 135 insertions(+), 139 deletions(-) create mode 100644 include/config_fsl_chain_trust.h delete mode 100644 include/config_fsl_secboot.h diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 8491a72..0da0599 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -8,6 +8,14 @@ #define __FSL_SECURE_BOOT_H #ifdef CONFIG_SECURE_BOOT + +#ifndef CONFIG_FIT_SIGNATURE +#define CONFIG_CHAIN_OF_TRUST +#endif + +#endif + +#ifdef CONFIG_CHAIN_OF_TRUST #define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_CMD_BLOB #define CONFIG_FSL_SEC_MON @@ -40,8 +48,6 @@ #define CONFIG_ESBC_ADDR_64BIT #endif -#ifndef CONFIG_FIT_SIGNATURE - #define CONFIG_EXTRA_ENV \ "setenv fdt_high 0xcfff;" \ "setenv initrd_high 0xcfff;"\ @@ -50,8 +56,6 @@ /* The address needs to be modified according to NOR memory map */ #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a -#include -#endif -#endif - +#include +#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 7d217a6..41058d1 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -9,19 +9,11 @@ #include #ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_ESBC_VALIDATE -#define CONFIG_CMD_BLOB -#define CONFIG_FSL_SEC_MON -#define CONFIG_SHA_PROG_HW_ACCEL -#define CONFIG_DM -#define CONFIG_RSA -#define CONFIG_RSA_FREESCALE_EXP -#ifndef CONFIG_FSL_CAAM -#define CONFIG_FSL_CAAM -#endif + +#ifndef CONFIG_FIT_SIGNATURE +#define CONFIG_CHAIN_OF_TRUST #endif -#ifdef CONFIG_SECURE_BOOT #if defined(CONFIG_FSL_CORENET) #define CONFIG_SYS_PBI_FLASH_BASE 0xc000 #elif defined(CONFIG_BSC9132QDS) @@ -76,8 +68,25 @@ */ #define CONFIG_FSL_ISBC_KEY_EXT #endif +#endif /* #ifdef CONFIG_SECURE_BOOT */ + +#ifdef CONFIG_CHAIN_OF_TRUST + +#define CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_CMD_BLOB +#define CONFIG_FSL_SEC_MON +#define CONFIG_SHA_PROG_HW_ACCEL +#define CONFIG_RSA +#define CONFIG_RSA_FREESCALE_EXP + +#ifndef CONFIG_DM +#define CONFIG_DM +#endif + +#ifndef CONFIG_FSL_CAAM +#define CONFIG_FSL_CAAM +#endif -#ifndef CONFIG_FIT_SIGNATURE /* If Boot Script is not on NOR and is required to be copied on RAM */ #ifdef CONFIG_BOOTSCRIPT_COPY_RAM #define CONFIG_BS_HDR_ADDR_RAM 0x0001 @@
[U-Boot] [PATCH v2 7/7] SECURE_BOOT: change error handler for esbc_validate
In case of error while executing esbc_validate command, SNVS
transition and issue of reset is required only for secure-boot.
If boot mode is non-secure, this is not required.
Similarly, esbc_halt command which puts the core in Spin Loop
is applicable only for Secure Boot.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v2:
None (Changed the Sign-Off with New E-Mail ID)
board/freescale/common/cmd_esbc_validate.c | 7 ++-
board/freescale/common/fsl_validate.c | 7 +++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/board/freescale/common/cmd_esbc_validate.c
b/board/freescale/common/cmd_esbc_validate.c
index ca7c737..dfa3e21 100644
--- a/board/freescale/common/cmd_esbc_validate.c
+++ b/board/freescale/common/cmd_esbc_validate.c
@@ -11,6 +11,11 @@
static int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
+ if (fsl_check_boot_mode_secure() == 0) {
+ printf("Boot Mode is Non-Secure. Not entering spin loop.\n");
+ return 0;
+ }
+
printf("Core is entering spin loop.\n");
loop:
goto loop;
@@ -64,6 +69,6 @@ U_BOOT_CMD(
U_BOOT_CMD(
esbc_halt, 1, 0, do_esbc_halt,
- "Put the core in spin loop ",
+ "Put the core in spin loop (Secure Boot Only)",
""
);
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index de40081..8fd6dd6 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -370,6 +370,13 @@ void fsl_secboot_handle_error(int error)
printf("ERROR :: %x :: %s\n", error, e->name);
}
+ /* If Boot Mode is secure, transition the SNVS state and issue
+* reset based on type of failure and ITS setting.
+* If Boot mode is non-secure, return from this function.
+*/
+ if (fsl_check_boot_mode_secure() == 0)
+ return;
+
switch (error) {
case ERROR_ESBC_CLIENT_HEADER_BARKER:
case ERROR_ESBC_CLIENT_HEADER_IMG_SIZE:
--
1.8.1.4
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[U-Boot] [PATCH v2 5/7] enable chain of trust for ARM platforms
Chain of Trust is enabled for ARM platforms (LS1021 and LS1043).
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
bootdelay = 0 (To disable Boot Prompt)
bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v2:
Defconfigs for Secure Boot Target are not removed
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4
board/freescale/common/Makefile | 1 +
board/freescale/common/fsl_chain_of_trust.c | 17 +
board/freescale/ls1021aqds/ls1021aqds.c | 4
board/freescale/ls1021atwr/ls1021atwr.c | 4
include/fsl_validate.h | 2 ++
6 files changed, 32 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 23d6b73..2f92b55 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -241,6 +242,9 @@ int board_late_init(void)
#ifdef CONFIG_SCSI_AHCI_PLAT
sata_init();
#endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
return 0;
}
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 51d2814..be114ce 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -76,5 +76,6 @@ obj-$(CONFIG_LAYERSCAPE_NS_ACCESS)+= ns_access.o
ifdef CONFIG_SECURE_BOOT
obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o
endif
+obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o
endif
diff --git a/board/freescale/common/fsl_chain_of_trust.c
b/board/freescale/common/fsl_chain_of_trust.c
index ff67bd7..ecfcc82 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -51,3 +51,20 @@ int fsl_check_boot_mode_secure(void)
#endif
return 0;
}
+
+int fsl_setenv_chain_of_trust(void)
+{
+ /* Check Boot Mode
+* If Boot Mode is Non-Secure, no changes are required
+*/
+ if (fsl_check_boot_mode_secure() == 0)
+ return 0;
+
+ /* If Boot mode is Secure, set the environment variables
+* bootdelay = 0 (To disable Boot Prompt)
+* bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
+*/
+ setenv("bootdelay", "0");
+ setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD);
+ return 0;
+}
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
b/board/freescale/ls1021aqds/ls1021aqds.c
index ca1ea61..6e82232 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#include "../common/sleep.h"
#include "../common/qixis.h"
@@ -369,6 +370,9 @@ int board_late_init(void)
#ifdef CONFIG_SCSI_AHCI_PLAT
ls1021a_sata_init();
#endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
return 0;
}
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
b/board/freescale/ls1021atwr/ls1021atwr.c
index ae62bca..054cc3d 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -30,6 +30,7 @@
#ifdef CONFIG_U_QE
#include "../../../drivers/qe/qe.h"
#endif
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -553,6 +554,9 @@ int board_late_init(void)
#ifdef CONFIG_SCSI_AHCI_PLAT
ls1021a_sata_init();
#endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
return 0;
}
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index ad14867..83efcf4 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -205,4 +205,6 @@ int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int
argc,
int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[]);
+int fsl_check_boot_mode_secure(void);
+int fsl_setenv_chain_of_trust(void);
#endif
--
1.8.1.4
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[U-Boot] [PATCH v2 6/7] enable chain of trust for PowerPC platforms
Chain of Trust is enabled for PowerPC platforms for Secure Boot.
CONFIG_BOARD_LATE_INIT is defined.
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
bootdelay = 0 (To disable Boot Prompt)
bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v2:
None (Changed the Sign-Off with New E-Mail ID)
arch/powerpc/cpu/mpc85xx/cpu_init.c| 12
arch/powerpc/include/asm/fsl_secure_boot.h | 7 +++
2 files changed, 19 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 50bb86a..a797980 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -26,6 +26,7 @@
#include
#include
#include
+#include
#include "mp.h"
#ifdef CONFIG_FSL_CAAM
#include
@@ -1011,3 +1012,14 @@ void cpu_secondary_init_r(void)
qe_reset();
#endif
}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
+
+ return 0;
+}
+#endif
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h
b/arch/powerpc/include/asm/fsl_secure_boot.h
index 41058d1..c45cace 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -87,6 +87,13 @@
#define CONFIG_FSL_CAAM
#endif
+/* fsl_setenv_chain_of_trust() must be called from
+ * board_late_init()
+ */
+#ifndef CONFIG_BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
+#endif
+
/* If Boot Script is not on NOR and is required to be copied on RAM */
#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
#define CONFIG_BS_HDR_ADDR_RAM 0x0001
--
1.8.1.4
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[U-Boot] [PATCH v2 2/7] include/configs: move definition of CONFIG_CMD_BLOB
CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was earlier defined in all config files. The definition has been moved to a common file which is included by all configs. Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com> --- Changes in v2: None (Changed the Sign-Off with New E-Mail ID) arch/arm/include/asm/fsl_secure_boot.h | 1 + arch/powerpc/include/asm/fsl_secure_boot.h | 1 + include/configs/B4860QDS.h | 4 include/configs/BSC9132QDS.h | 4 include/configs/C29XPCIE.h | 4 include/configs/P1010RDB.h | 4 include/configs/P2041RDB.h | 4 include/configs/T102xQDS.h | 4 include/configs/T102xRDB.h | 4 include/configs/T1040QDS.h | 4 include/configs/T104xRDB.h | 4 include/configs/T208xQDS.h | 5 - include/configs/T208xRDB.h | 5 - include/configs/T4240QDS.h | 4 include/configs/T4240RDB.h | 9 - include/configs/corenet_ds.h | 4 include/configs/ls1021aqds.h | 4 include/configs/ls1021atwr.h | 4 18 files changed, 2 insertions(+), 71 deletions(-) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index b29e71c..8491a72 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -9,6 +9,7 @@ #ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_CMD_BLOB #define CONFIG_FSL_SEC_MON #define CONFIG_SHA_PROG_HW_ACCEL #define CONFIG_RSA diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 87415b1..7d217a6 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -10,6 +10,7 @@ #ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_CMD_BLOB #define CONFIG_FSL_SEC_MON #define CONFIG_SHA_PROG_HW_ACCEL #define CONFIG_DM diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 9fb5cee..bcbae50 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -924,8 +924,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index d0e5a25..89907dc 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -722,8 +722,4 @@ combinations. this should be removed later #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 890dcbb..16920c6 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -567,8 +567,4 @@ #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index f9776c0..3c0faca 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -952,8 +952,4 @@ extern unsigned long get_sdram_size(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index b2e51b5..f250e7f 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -756,8 +756,4 @@ unsigned long get_board_sys_clk(unsigned long dummy); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index fb41a7d..e5df784 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -946,8 +946,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __T1024QDS_H */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 113df37..3cda3b1 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -958,8 +958,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __T1024RDB_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 5fd93a1..2e7892f 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -837,8 +837,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index eec2971..5fc3497 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -940,8 +940,4 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #include -
[U-Boot] [PATCH v3] powerpc/SECURE_BOOT: Add PAMU driver
PAMU driver basic support for usage in Secure Boot.
In secure boot PAMU is not in bypass mode. Hence to use
any peripheral (SEC Job ring in our case), PAMU has to be
configured.
The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3.
The Header file pamu.h and few functions in driver have been derived
from Freescale Libos.
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v3:
Replace the Debug printf() call with debug()
Merged the two commits into a single commit
Changes in v2:
Replace the Debug printf() call with debug()
arch/powerpc/cpu/mpc85xx/cpu_init.c | 18 +-
arch/powerpc/cpu/mpc8xxx/Makefile | 1 +
arch/powerpc/cpu/mpc8xxx/fsl_pamu.c | 433 ++
arch/powerpc/cpu/mpc8xxx/pamu_table.c | 55 +
arch/powerpc/include/asm/fsl_pamu.h | 169 +
arch/powerpc/include/asm/immap_85xx.h | 19 +-
drivers/crypto/fsl/jr.c | 23 ++
7 files changed, 709 insertions(+), 9 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
create mode 100644 arch/powerpc/cpu/mpc8xxx/pamu_table.c
create mode 100644 arch/powerpc/include/asm/fsl_pamu.h
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 13a7d0f..50bb86a 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -30,6 +30,10 @@
#ifdef CONFIG_FSL_CAAM
#include
#endif
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+#include
+#include
+#endif
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include
#include
@@ -425,8 +429,7 @@ void fsl_erratum_a007212_workaround(void)
ulong cpu_init_f(void)
{
extern void m8560_cpm_reset (void);
-#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
- (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_SECURE_BOOT)
@@ -458,12 +461,6 @@ ulong cpu_init_f(void)
#if defined(CONFIG_SYS_CPC_REINIT_F)
disable_cpc_sram();
#endif
-
-#if defined(CONFIG_FSL_CORENET)
- /* Put PAMU in bypass mode */
- out_be32(>pamubypenr, FSL_CORENET_PAMU_BYPASS);
-#endif
-
#endif
#ifdef CONFIG_CPM2
@@ -940,6 +937,11 @@ int cpu_init_r(void)
fman_enet_init();
#endif
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+ if (pamu_init() < 0)
+ fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
+#endif
+
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile
b/arch/powerpc/cpu/mpc8xxx/Makefile
index ac45e0e..c5592cd 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -24,5 +24,6 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
obj-$(CONFIG_SYS_SRIO) += srio.o
obj-$(CONFIG_FSL_LAW) += law.o
+obj-$(CONFIG_FSL_CORENET) += fsl_pamu.o pamu_table.o
endif
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
new file mode 100644
index 000..8ad3b7c
--- /dev/null
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
@@ -0,0 +1,433 @@
+/*
+ * FSL PAMU driver
+ *
+ * Copyright 2012-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+struct paace *ppaact;
+struct paace *sec;
+unsigned long fspi;
+
+static inline int __ilog2_roundup_64(uint64_t val)
+{
+ if ((val & (val - 1)) == 0)
+ return __ilog2_u64(val);
+ else
+ return __ilog2_u64(val) + 1;
+}
+
+
+static inline int count_lsb_zeroes(unsigned long val)
+{
+ return ffs(val) - 1;
+}
+
+static unsigned int map_addrspace_size_to_wse(uint64_t addrspace_size)
+{
+ /* window size is 2^(WSE+1) bytes */
+ return count_lsb_zeroes(addrspace_size >> PAMU_PAGE_SHIFT) +
+ PAMU_PAGE_SHIFT - 1;
+}
+
+static unsigned int map_subwindow_cnt_to_wce(uint32_t subwindow_cnt)
+{
+ /* window count is 2^(WCE+1) bytes */
+ return count_lsb_zeroes(subwindow_cnt) - 1;
+}
+
+static void pamu_setup_default_xfer_to_host_ppaace(struct paace *ppaace)
+{
+ set_bf(ppaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_PRIMARY);
+ set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+ PAACE_M_COHERENCE_REQ);
+}
+
+static void pamu_setup_default_xfer_to_host_spaace(struct paace *spaace)
+{
+ set_bf(spaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_SECONDARY);
+ set_bf(spaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+ PAACE_M_COHERENCE_REQ);
+}
+
+/** Sets up PPAACE entry for specified liodn
+ *
+ * @param[in] liodn Logical IO device number
+ * @param[in] win_addr starting address of DSA window
+ * @param[in] win-size size of DSA window
+ * @param
[U-Boot] [PATCH v2 2/2] powerpc/SECURE_BOOT: Add PAMU driver
PAMU driver basic support for usage in Secure Boot.
In secure boot PAMU is not in bypass mode. Hence to use
any peripheral (SEC Job ring in our case), PAMU has to be
configured.
The Header file pamu.h and few functions in driver have been derived
from Freescale Libos.
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v2:
Replace the Debug printf() call with debug()
arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 +
arch/powerpc/cpu/mpc8xxx/Makefile | 1 +
arch/powerpc/cpu/mpc8xxx/fsl_pamu.c | 449 ++
arch/powerpc/cpu/mpc8xxx/pamu_table.c | 55 +
arch/powerpc/include/asm/fsl_pamu.h | 169 +
arch/powerpc/include/asm/immap_85xx.h | 18 ++
drivers/crypto/fsl/jr.c | 23 ++
7 files changed, 724 insertions(+)
create mode 100644 arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
create mode 100644 arch/powerpc/cpu/mpc8xxx/pamu_table.c
create mode 100644 arch/powerpc/include/asm/fsl_pamu.h
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index c738c96..50bb86a 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -30,6 +30,10 @@
#ifdef CONFIG_FSL_CAAM
#include
#endif
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+#include
+#include
+#endif
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include
#include
@@ -933,6 +937,11 @@ int cpu_init_r(void)
fman_enet_init();
#endif
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+ if (pamu_init() < 0)
+ fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
+#endif
+
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile
b/arch/powerpc/cpu/mpc8xxx/Makefile
index ac45e0e..c5592cd 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -24,5 +24,6 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
obj-$(CONFIG_SYS_SRIO) += srio.o
obj-$(CONFIG_FSL_LAW) += law.o
+obj-$(CONFIG_FSL_CORENET) += fsl_pamu.o pamu_table.o
endif
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
new file mode 100644
index 000..8dee2e7
--- /dev/null
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
@@ -0,0 +1,449 @@
+/*
+ * FSL PAMU driver
+ *
+ * Copyright 2012-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+struct paace *ppaact;
+struct paace *sec;
+unsigned long fspi;
+
+static inline int __ilog2_roundup_64(uint64_t val)
+{
+ if ((val & (val - 1)) == 0)
+ return __ilog2_u64(val);
+ else
+ return __ilog2_u64(val) + 1;
+}
+
+
+static inline int count_lsb_zeroes(unsigned long val)
+{
+ return ffs(val) - 1;
+}
+
+static unsigned int map_addrspace_size_to_wse(uint64_t addrspace_size)
+{
+ /* window size is 2^(WSE+1) bytes */
+ return count_lsb_zeroes(addrspace_size >> PAMU_PAGE_SHIFT) +
+ PAMU_PAGE_SHIFT - 1;
+}
+
+static unsigned int map_subwindow_cnt_to_wce(uint32_t subwindow_cnt)
+{
+ /* window count is 2^(WCE+1) bytes */
+ return count_lsb_zeroes(subwindow_cnt) - 1;
+}
+
+static void pamu_setup_default_xfer_to_host_ppaace(struct paace *ppaace)
+{
+ set_bf(ppaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_PRIMARY);
+ set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+ PAACE_M_COHERENCE_REQ);
+}
+
+static void pamu_setup_default_xfer_to_host_spaace(struct paace *spaace)
+{
+ set_bf(spaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_SECONDARY);
+ set_bf(spaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+ PAACE_M_COHERENCE_REQ);
+}
+
+/** Sets up PPAACE entry for specified liodn
+ *
+ * @param[in] liodn Logical IO device number
+ * @param[in] win_addr starting address of DSA window
+ * @param[in] win-size size of DSA window
+ * @param[in] omiOperation mapping index -- if ~omi == 0 then omi
+ not defined
+ * @param[in] stashidcache stash id for associated cpu -- if ~stashid == 0
+ then stashid not defined
+ * @param[in] snoopidsnoop id for hardware coherency -- if ~snoopid == 0
+ then snoopid not defined
+ * @param[in] subwin_cnt number of sub-windows
+ *
+ * @return Returns 0 upon success else error code < 0 returned
+ */
+static int pamu_config_ppaace(uint32_t liodn, uint64_t win_addr,
+ uint64_t win_size, uint32_t omi,
+ uint32_t snoopid, uint32_t stashid,
+ uint32_t subwin_cnt)
+{
+ struct paace *ppaace;
+
+ if ((win_size & (win_size - 1)) || win_size < PAMU_PAGE_SIZE)
+ return -1;
+
+ if (win_addr & (win_size - 1))
[U-Boot] [PATCH v2 1/2] Revert "powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure boot"
This reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3.
PAMU should not be by-passed in case of Secure Boot.
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
Changes in v2:
Modified the commit message
arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 +
arch/powerpc/include/asm/immap_85xx.h | 1 -
2 files changed, 1 insertion(+), 9 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 13a7d0f..c738c96 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -425,8 +425,7 @@ void fsl_erratum_a007212_workaround(void)
ulong cpu_init_f(void)
{
extern void m8560_cpm_reset (void);
-#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
- (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_SECURE_BOOT)
@@ -458,12 +457,6 @@ ulong cpu_init_f(void)
#if defined(CONFIG_SYS_CPC_REINIT_F)
disable_cpc_sram();
#endif
-
-#if defined(CONFIG_FSL_CORENET)
- /* Put PAMU in bypass mode */
- out_be32(>pamubypenr, FSL_CORENET_PAMU_BYPASS);
-#endif
-
#endif
#ifdef CONFIG_CPM2
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 101b8db..667a97e 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1933,7 +1933,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
u8 res24[64];
u32 pblsr; /* Preboot loader status */
u32 pamubypenr; /* PAMU bypass enable */
-#define FSL_CORENET_PAMU_BYPASS0x
u32 dmacr1; /* DMA control */
u8 res25[4];
u32 gensr1; /* General status */
--
1.8.1.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Enable snooping on transactions from CAAM block
To enable snooping on CAAM transactions following programmign is done
1. Enable core snooping (CCI interface, Core is Slave5 on CCI)
This setting is also required for making the system coherent
2. CAAM IP lies behind SMMU3 in teh system. Configure SMMU3 to do teh following:
a) Program SCR to bypass transactions with stream ID other than taht of CAAM
b_ Program S2CR to change memroy attributes of transactions with CAAM's stream
ID (0x10) to cacheable.
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Nitesh Narayan Lal <nitesh@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
arch/arm/include/asm/arch-ls102xa/config.h | 1 +
.../include/asm/arch-ls102xa/ls102xa_stream_id.h | 34 ++
board/freescale/common/ls102xa_stream_id.c | 34 ++
board/freescale/ls1021aqds/ls1021aqds.c| 4 +++
board/freescale/ls1021atwr/ls1021atwr.c| 4 +++
5 files changed, 77 insertions(+)
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
b/arch/arm/include/asm/arch-ls102xa/config.h
index f066480..f14ea2f 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -38,6 +38,7 @@
#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x0210)
#define CONFIG_SYS_LS102XA_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
+#define CONFIG_SYS_SMMU3_ADDR (CONFIG_SYS_IMMR + 0x30)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x0070
#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x0760
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
index fa571b3..68e4e02 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
@@ -6,6 +6,39 @@
#ifndef __FSL_LS102XA_STREAM_ID_H_
#define __FSL_LS102XA_STREAM_ID_H_
+#define CONFIG_SMMU_NSCR_OFFSET0x400
+#define CONFIG_SMMU_SMR_OFFSET 0x800
+#define CONFIG_SMMU_S2CR_OFFSET0xc00
+
+#define SMMU_NSCR_CLIENTPD_SHIFT 0
+#define SMMU_NSCR_MTCFG_SHIFT 20
+
+#define SMR_SMR_VALID_SHIFT31
+#define SMR_ID_MASK0x7fff
+#define SMR_MASK_SHIFT 16
+
+#define S2CR_WACFG_SHIFT 22
+#define S2CR_WACFG_MASK0x3
+#define S2CR_WACFG_WRITE_ALLOCATE 0x2
+
+#define S2CR_RACFG_SHIFT 20
+#define S2CR_RACFG_MASK0x3
+#define S2CR_RACFG_READ_ALLOCATE 0x2
+
+#define S2CR_TYPE_SHIFT16
+#define S2CR_TYPE_MASK 0x3
+#define S2CR_TYPE_BYPASS 0x01
+
+#define S2CR_MEM_ATTR_SHIFT12
+#define S2CR_MEM_ATTR_MASK 0xf
+#define S2CR_MEM_ATTR_CACHEABLE0xa
+
+#define S2CR_MTCFG 0x0800
+
+#define S2CR_SHCFG_SHIFT 8
+#define S2CR_SHCFG_MASK0x3
+#define S2CR_SHCFG_OUTER_CACHEABLE 0x1
+#define S2CR_SHCFG_INNER_CACHEABLE 0x2
#include
@@ -71,4 +104,5 @@ struct smmu_stream_id {
void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size);
void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
+void ls1021x_config_smmu3(uint32_t liodn);
#endif
diff --git a/board/freescale/common/ls102xa_stream_id.c
b/board/freescale/common/ls102xa_stream_id.c
index f434269..2b12a8c 100644
--- a/board/freescale/common/ls102xa_stream_id.c
+++ b/board/freescale/common/ls102xa_stream_id.c
@@ -31,3 +31,37 @@ void ls1021x_config_caam_stream_id(struct liodn_id_table
*tbl, int size)
out_le32((uint32_t *)(tbl[i].reg_offset), liodn);
}
}
+
+void ls1021x_config_smmu3(uint32_t liodn)
+{
+ uint32_t *addr;
+ u32 smr, s2cr, nscr;
+
+ addr = (uint32_t *)(CONFIG_SYS_SMMU3_ADDR + CONFIG_SMMU_NSCR_OFFSET);
+ /* SMMU NSCR configuration */
+ nscr = in_le32(addr);
+
+ nscr = nscr & ~(1 << SMMU_NSCR_CLIENTPD_SHIFT |
+1 << SMMU_NSCR_MTCFG_SHIFT);
+ out_le32(addr, nscr);
+
+ /* SMMU SMR configuration */
+ addr = (uint32_t *)(CONFIG_SYS_SMMU3_ADDR + CONFIG_SMMU_SMR_OFFSET);
+
+ smr = 0;
+ smr = smr & (~(SMR_ID_MASK << SMR_MASK_SHIFT));
+ smr = smr | (1 << SMR_SMR_VALID_SHIFT) | liodn;
+
+ out_le32(addr, smr);
+
+ /* SMMU S2CR configuration */
+ addr = (uint32_t *)(CONFIG_SYS_SMMU3_ADDR + CONFIG_SMMU_S2CR_OFFSET);
+ s2cr = (S2CR_WACFG_WRITE_ALLOCATE << S2CR_WACFG_SHIFT) |
+ (S2CR_RACFG_READ_ALLOCATE << S2CR_RACFG_SHIFT) |
+ (S2CR_TYPE_BYPASS << S2CR_TYPE_SHIFT) |
+ (S2CR_MEM_ATTR_CACHEABLE << S2CR_MEM_ATTR_SHIFT) |
+ S2CR_MTCFG |
+ (S2CR
[U-Boot] [PATCH 2/2] powerpc/SECURE_BOOT: Add PAMU driver
PAMU driver basic support for usage in Secure Boot.
In secure boot PAMU is not in bypass mode. Hence to use
any peripheral (SEC Job ring in our case), PAMU has to be
configured.
The Header file pamu.h and few functions in driver have been derived
from Freescale Libos.
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 +
arch/powerpc/cpu/mpc8xxx/Makefile | 1 +
arch/powerpc/cpu/mpc8xxx/fsl_pamu.c | 449 ++
arch/powerpc/cpu/mpc8xxx/pamu_table.c | 57 +
arch/powerpc/include/asm/fsl_pamu.h | 169 +
arch/powerpc/include/asm/immap_85xx.h | 18 ++
drivers/crypto/fsl/jr.c | 23 ++
7 files changed, 726 insertions(+)
create mode 100644 arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
create mode 100644 arch/powerpc/cpu/mpc8xxx/pamu_table.c
create mode 100644 arch/powerpc/include/asm/fsl_pamu.h
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index c738c96..50bb86a 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -30,6 +30,10 @@
#ifdef CONFIG_FSL_CAAM
#include
#endif
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+#include
+#include
+#endif
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include
#include
@@ -933,6 +937,11 @@ int cpu_init_r(void)
fman_enet_init();
#endif
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+ if (pamu_init() < 0)
+ fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
+#endif
+
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile
b/arch/powerpc/cpu/mpc8xxx/Makefile
index ac45e0e..c5592cd 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -24,5 +24,6 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
obj-$(CONFIG_SYS_SRIO) += srio.o
obj-$(CONFIG_FSL_LAW) += law.o
+obj-$(CONFIG_FSL_CORENET) += fsl_pamu.o pamu_table.o
endif
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
new file mode 100644
index 000..8dee2e7
--- /dev/null
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
@@ -0,0 +1,449 @@
+/*
+ * FSL PAMU driver
+ *
+ * Copyright 2012-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+struct paace *ppaact;
+struct paace *sec;
+unsigned long fspi;
+
+static inline int __ilog2_roundup_64(uint64_t val)
+{
+ if ((val & (val - 1)) == 0)
+ return __ilog2_u64(val);
+ else
+ return __ilog2_u64(val) + 1;
+}
+
+
+static inline int count_lsb_zeroes(unsigned long val)
+{
+ return ffs(val) - 1;
+}
+
+static unsigned int map_addrspace_size_to_wse(uint64_t addrspace_size)
+{
+ /* window size is 2^(WSE+1) bytes */
+ return count_lsb_zeroes(addrspace_size >> PAMU_PAGE_SHIFT) +
+ PAMU_PAGE_SHIFT - 1;
+}
+
+static unsigned int map_subwindow_cnt_to_wce(uint32_t subwindow_cnt)
+{
+ /* window count is 2^(WCE+1) bytes */
+ return count_lsb_zeroes(subwindow_cnt) - 1;
+}
+
+static void pamu_setup_default_xfer_to_host_ppaace(struct paace *ppaace)
+{
+ set_bf(ppaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_PRIMARY);
+ set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+ PAACE_M_COHERENCE_REQ);
+}
+
+static void pamu_setup_default_xfer_to_host_spaace(struct paace *spaace)
+{
+ set_bf(spaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_SECONDARY);
+ set_bf(spaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+ PAACE_M_COHERENCE_REQ);
+}
+
+/** Sets up PPAACE entry for specified liodn
+ *
+ * @param[in] liodn Logical IO device number
+ * @param[in] win_addr starting address of DSA window
+ * @param[in] win-size size of DSA window
+ * @param[in] omiOperation mapping index -- if ~omi == 0 then omi
+ not defined
+ * @param[in] stashidcache stash id for associated cpu -- if ~stashid == 0
+ then stashid not defined
+ * @param[in] snoopidsnoop id for hardware coherency -- if ~snoopid == 0
+ then snoopid not defined
+ * @param[in] subwin_cnt number of sub-windows
+ *
+ * @return Returns 0 upon success else error code < 0 returned
+ */
+static int pamu_config_ppaace(uint32_t liodn, uint64_t win_addr,
+ uint64_t win_size, uint32_t omi,
+ uint32_t snoopid, uint32_t stashid,
+ uint32_t subwin_cnt)
+{
+ struct paace *ppaace;
+
+ if ((win_size & (win_size - 1)) || win_size < PAMU_PAGE_SIZE)
+ return -1;
+
+ if (win_addr & (win_size - 1))
+ return -2;
+
+ if (liodn > NUM_PPAAC
[U-Boot] [PATCH 1/2] Revert "powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure boot"
This reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3.
Signed-off-by: Aneesh Bansal <aneesh.ban...@nxp.com>
CC: Ruchika Gupta <ruchika.gu...@nxp.com>
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 +
arch/powerpc/include/asm/immap_85xx.h | 1 -
2 files changed, 1 insertion(+), 9 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 13a7d0f..c738c96 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -425,8 +425,7 @@ void fsl_erratum_a007212_workaround(void)
ulong cpu_init_f(void)
{
extern void m8560_cpm_reset (void);
-#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
- (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_SECURE_BOOT)
@@ -458,12 +457,6 @@ ulong cpu_init_f(void)
#if defined(CONFIG_SYS_CPC_REINIT_F)
disable_cpc_sram();
#endif
-
-#if defined(CONFIG_FSL_CORENET)
- /* Put PAMU in bypass mode */
- out_be32(>pamubypenr, FSL_CORENET_PAMU_BYPASS);
-#endif
-
#endif
#ifdef CONFIG_CPM2
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 101b8db..667a97e 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1933,7 +1933,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
u8 res24[64];
u32 pblsr; /* Preboot loader status */
u32 pamubypenr; /* PAMU bypass enable */
-#define FSL_CORENET_PAMU_BYPASS0x
u32 dmacr1; /* DMA control */
u8 res25[4];
u32 gensr1; /* General status */
--
1.8.1.4
___
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[U-Boot] [PATCH 5/7] enable chain of trust for ARM platforms
Chain of Trust is enabled for ARM platforms (LS1021 and LS1043).
Compile time Secure Boot targets are removed.
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
bootdelay = 0 (To disable Boot Prompt)
bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4
board/freescale/common/Makefile | 1 +
board/freescale/common/fsl_chain_of_trust.c | 17 +
board/freescale/ls1021aqds/ls1021aqds.c | 4
board/freescale/ls1021atwr/ls1021atwr.c | 4
configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 7 ---
configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 7 ---
configs/ls1043ardb_SECURE_BOOT_defconfig | 9 -
include/fsl_validate.h | 2 ++
9 files changed, 32 insertions(+), 23 deletions(-)
delete mode 100644 configs/ls1021aqds_nor_SECURE_BOOT_defconfig
delete mode 100644 configs/ls1021atwr_nor_SECURE_BOOT_defconfig
delete mode 100644 configs/ls1043ardb_SECURE_BOOT_defconfig
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 23d6b73..2f92b55 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -241,6 +242,9 @@ int board_late_init(void)
#ifdef CONFIG_SCSI_AHCI_PLAT
sata_init();
#endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
return 0;
}
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 9af8782..eef518e 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -74,5 +74,6 @@ obj-$(CONFIG_P5040DS) += p_corenet/
obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o
obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o
+obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o
endif
diff --git a/board/freescale/common/fsl_chain_of_trust.c
b/board/freescale/common/fsl_chain_of_trust.c
index ff67bd7..ecfcc82 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -51,3 +51,20 @@ int fsl_check_boot_mode_secure(void)
#endif
return 0;
}
+
+int fsl_setenv_chain_of_trust(void)
+{
+ /* Check Boot Mode
+* If Boot Mode is Non-Secure, no changes are required
+*/
+ if (fsl_check_boot_mode_secure() == 0)
+ return 0;
+
+ /* If Boot mode is Secure, set the environment variables
+* bootdelay = 0 (To disable Boot Prompt)
+* bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
+*/
+ setenv("bootdelay", "0");
+ setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD);
+ return 0;
+}
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
b/board/freescale/ls1021aqds/ls1021aqds.c
index be3358a..5f4ec9d 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#include "../common/sleep.h"
#include "../common/qixis.h"
@@ -369,6 +370,9 @@ int board_late_init(void)
#ifdef CONFIG_SCSI_AHCI_PLAT
ls1021a_sata_init();
#endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
return 0;
}
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
b/board/freescale/ls1021atwr/ls1021atwr.c
index 8eaff5f..b85774c 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -30,6 +30,7 @@
#ifdef CONFIG_U_QE
#include "../../../drivers/qe/qe.h"
#endif
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -549,6 +550,9 @@ int board_late_init(void)
#ifdef CONFIG_SCSI_AHCI_PLAT
ls1021a_sata_init();
#endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
return 0;
}
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
deleted file mode 100644
index 025a8f2..000
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1021AQDS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_SYS_NS16550=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
deleted file mode 100644
index bf19c33..000
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1021ATWR=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
-# CONFIG_CMD_SETEXPR is n
[U-Boot] [PATCH 1/7] include/configs: make secure boot header file include uniform
The file fsl_secure_boot.h must be included in config file for Secure Boot. This is not required to be protected by any macro. CONFIG_FSL_CAAM must be defined and CONFIG_CMD_HASH should be turned on. The above was missing in some config files and all files have been made uniform in this respect. Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com> --- include/configs/C29XPCIE.h | 4 include/configs/T102xQDS.h | 12 +++- include/configs/T102xRDB.h | 12 +++- include/configs/T1040QDS.h | 3 ++- include/configs/T104xRDB.h | 3 ++- include/configs/T208xQDS.h | 3 ++- include/configs/T208xRDB.h | 3 ++- include/configs/ls1021aqds.h | 5 - include/configs/ls1021atwr.h | 5 - include/configs/ls1043a_common.h | 8 include/configs/ls1043ardb.h | 6 ++ 11 files changed, 52 insertions(+), 12 deletions(-) diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 16920c6..890dcbb 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -567,4 +567,8 @@ #include +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 951cbc4..fb41a7d 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -39,6 +39,8 @@ #define CONFIG_BOARD_EARLY_INIT_F #endif +#define CONFIG_FSL_CAAM/* Enable SEC/CAAM */ + #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg @@ -936,8 +938,16 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + #include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB #endif #endif /* __T1024QDS_H */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 4a0f5b2..113df37 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -33,6 +33,8 @@ #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_FSL_CAAM/* Enable SEC/CAAM */ + /* support deep sleep */ #ifdef CONFIG_PPC_T1024 #define CONFIG_DEEP_SLEEP @@ -948,8 +950,16 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + #include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB #endif #endif /* __T1024RDB_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 9e151da..5fd93a1 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -835,8 +835,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB #endif diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index da65f56..eec2971 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -938,8 +938,9 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB #endif diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index a0cecc6..019878a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -933,8 +933,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB #undef CONFIG_CMD_USB #endif diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 312b0eb..3665b7d 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -889,8 +889,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB #undef CONFIG_CMD_USB #endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 2e8dbc7..0f1ad21 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -660,12 +660,15 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MISC_INIT_R /* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM #define CONFIG_CMD_HASH #define CONFIG_SHA_HW_ACCEL +#endif + +#include #ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB -#include #endif #endif diff
[U-Boot] [PATCH 0/7] Determine Boot mode at run time for ARM
For ARM based SoC's there is no need to add a separate target/defconfig for Secure Boot. Boot Mode can be determined at run time to continue the chain of trust. The patch set is dependent on following: http://patchwork.ozlabs.org/patch/560391/ http://patchwork.ozlabs.org/patch/553826/ Aneesh Bansal (7): include/configs: make secure boot header file include uniform include/configs: move definition of CONFIG_CMD_BLOB SECURE_BOOT: split the secure boot functionality in two parts create function to determine boot mode enable chain of trust for ARM platforms enable chain of trust for PowerPC platforms SECURE_BOOT: change error handler for esbc_validate arch/arm/cpu/armv8/fsl-layerscape/soc.c| 4 + .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 + arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 + arch/arm/include/asm/fsl_secure_boot.h | 7 +- arch/powerpc/cpu/mpc85xx/cpu_init.c| 12 +++ arch/powerpc/include/asm/fsl_secure_boot.h | 39 --- arch/powerpc/include/asm/immap_85xx.h | 3 + board/freescale/common/Makefile| 3 +- board/freescale/common/cmd_esbc_validate.c | 7 +- board/freescale/common/fsl_chain_of_trust.c| 70 + board/freescale/common/fsl_validate.c | 7 ++ board/freescale/ls1021aqds/ls1021aqds.c| 4 + board/freescale/ls1021atwr/ls1021atwr.c| 4 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 7 -- configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 7 -- configs/ls1043ardb_SECURE_BOOT_defconfig | 9 -- include/config_fsl_chain_trust.h | 89 include/config_fsl_secboot.h | 116 - include/configs/B4860QDS.h | 4 - include/configs/BSC9132QDS.h | 4 - include/configs/P1010RDB.h | 4 - include/configs/P2041RDB.h | 4 - include/configs/T102xQDS.h | 10 +- include/configs/T102xRDB.h | 10 +- include/configs/T1040QDS.h | 3 - include/configs/T104xRDB.h | 3 - include/configs/T208xQDS.h | 4 - include/configs/T208xRDB.h | 4 - include/configs/T4240QDS.h | 4 - include/configs/T4240RDB.h | 9 -- include/configs/corenet_ds.h | 4 - include/configs/ls1021aqds.h | 8 +- include/configs/ls1021atwr.h | 8 +- include/configs/ls1043a_common.h | 8 ++ include/configs/ls1043aqds.h | 10 ++ include/configs/ls1043ardb.h | 12 +-- include/fsl_validate.h | 2 + 37 files changed, 287 insertions(+), 221 deletions(-) create mode 100644 board/freescale/common/fsl_chain_of_trust.c delete mode 100644 configs/ls1021aqds_nor_SECURE_BOOT_defconfig delete mode 100644 configs/ls1021atwr_nor_SECURE_BOOT_defconfig delete mode 100644 configs/ls1043ardb_SECURE_BOOT_defconfig create mode 100644 include/config_fsl_chain_trust.h delete mode 100644 include/config_fsl_secboot.h -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/7] include/configs: move definition of CONFIG_CMD_BLOB
CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was earlier defined in all config files. The definition has been moved to a common file which is included by all configs. Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com> --- arch/arm/include/asm/fsl_secure_boot.h | 1 + arch/powerpc/include/asm/fsl_secure_boot.h | 1 + include/configs/B4860QDS.h | 4 include/configs/BSC9132QDS.h | 4 include/configs/C29XPCIE.h | 4 include/configs/P1010RDB.h | 4 include/configs/P2041RDB.h | 4 include/configs/T102xQDS.h | 4 include/configs/T102xRDB.h | 4 include/configs/T1040QDS.h | 4 include/configs/T104xRDB.h | 4 include/configs/T208xQDS.h | 5 - include/configs/T208xRDB.h | 5 - include/configs/T4240QDS.h | 4 include/configs/T4240RDB.h | 9 - include/configs/corenet_ds.h | 4 include/configs/ls1021aqds.h | 4 include/configs/ls1021atwr.h | 4 include/configs/ls1043ardb.h | 3 +-- 19 files changed, 3 insertions(+), 73 deletions(-) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 806302b..05d3c07 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -9,6 +9,7 @@ #ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_CMD_BLOB #define CONFIG_FSL_SEC_MON #define CONFIG_SHA_PROG_HW_ACCEL #define CONFIG_RSA diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 87415b1..7d217a6 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -10,6 +10,7 @@ #ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_CMD_BLOB #define CONFIG_FSL_SEC_MON #define CONFIG_SHA_PROG_HW_ACCEL #define CONFIG_DM diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 9fb5cee..bcbae50 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -924,8 +924,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index d0e5a25..89907dc 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -722,8 +722,4 @@ combinations. this should be removed later #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 890dcbb..16920c6 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -567,8 +567,4 @@ #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index f9776c0..3c0faca 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -952,8 +952,4 @@ extern unsigned long get_sdram_size(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index b2e51b5..f250e7f 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -756,8 +756,4 @@ unsigned long get_board_sys_clk(unsigned long dummy); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index fb41a7d..e5df784 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -946,8 +946,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __T1024QDS_H */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 113df37..3cda3b1 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -958,8 +958,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __T1024RDB_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 5fd93a1..2e7892f 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -837,8 +837,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index eec2971..5fc3497 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -940,8 +940,4 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #include -
[U-Boot] [PATCH 7/7] SECURE_BOOT: change error handler for esbc_validate
In case of error while executing esbc_validate command, SNVS
transition and issue of reset is required only for secure-boot.
If boot mode is non-secure, this is not required.
Similarly, esbc_halt command which puts the core in Spin Loop
is applicable only for Secure Boot.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
board/freescale/common/cmd_esbc_validate.c | 7 ++-
board/freescale/common/fsl_validate.c | 7 +++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/board/freescale/common/cmd_esbc_validate.c
b/board/freescale/common/cmd_esbc_validate.c
index ca7c737..dfa3e21 100644
--- a/board/freescale/common/cmd_esbc_validate.c
+++ b/board/freescale/common/cmd_esbc_validate.c
@@ -11,6 +11,11 @@
static int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
+ if (fsl_check_boot_mode_secure() == 0) {
+ printf("Boot Mode is Non-Secure. Not entering spin loop.\n");
+ return 0;
+ }
+
printf("Core is entering spin loop.\n");
loop:
goto loop;
@@ -64,6 +69,6 @@ U_BOOT_CMD(
U_BOOT_CMD(
esbc_halt, 1, 0, do_esbc_halt,
- "Put the core in spin loop ",
+ "Put the core in spin loop (Secure Boot Only)",
""
);
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index de40081..8fd6dd6 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -370,6 +370,13 @@ void fsl_secboot_handle_error(int error)
printf("ERROR :: %x :: %s\n", error, e->name);
}
+ /* If Boot Mode is secure, transition the SNVS state and issue
+* reset based on type of failure and ITS setting.
+* If Boot mode is non-secure, return from this function.
+*/
+ if (fsl_check_boot_mode_secure() == 0)
+ return;
+
switch (error) {
case ERROR_ESBC_CLIENT_HEADER_BARKER:
case ERROR_ESBC_CLIENT_HEADER_IMG_SIZE:
--
1.8.1.4
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[U-Boot] [PATCH 6/7] enable chain of trust for PowerPC platforms
Chain of Trust is enabled for PowerPC platforms
for Secure Boot. CONFIG_BOARD_LATE_INIT is defined.
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
bootdelay = 0 (To disable Boot Prompt)
bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
arch/powerpc/cpu/mpc85xx/cpu_init.c| 12
arch/powerpc/include/asm/fsl_secure_boot.h | 7 +++
2 files changed, 19 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 13a7d0f..a02f6f5 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -26,6 +26,7 @@
#include
#include
#include
+#include
#include "mp.h"
#ifdef CONFIG_FSL_CAAM
#include
@@ -1009,3 +1010,14 @@ void cpu_secondary_init_r(void)
qe_reset();
#endif
}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
+
+ return 0;
+}
+#endif
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h
b/arch/powerpc/include/asm/fsl_secure_boot.h
index b29246a..a4ea15c 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -13,6 +13,13 @@
#define CONFIG_CHAIN_OF_TRUST
#endif
+/* fsl_setenv_chain_of_trust() must be called from
+ * board_late_init()
+ */
+#ifndef CONFIG_BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
+#endif
+
#if defined(CONFIG_FSL_CORENET)
#define CONFIG_SYS_PBI_FLASH_BASE 0xc000
#elif defined(CONFIG_BSC9132QDS)
--
1.8.1.4
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[U-Boot] [PATCH 3/7] SECURE_BOOT: split the secure boot functionality in two parts
There are two phases in Secure Boot 1. ISBC: In BootROM, validate the BootLoader (U-Boot). 2. ESBC: In U-Boot, continuing the Chain of Trust by validating and booting LINUX. For ESBC phase, there is no difference in SoC's based on ARM or PowerPC cores. But the exit conditions after ISBC phase i.e. entry conditions for U-Boot are different for ARM and PowerPC. PowerPC: If Secure Boot is executed, a separate U-Boot target is required which must be compiled with a diffrent Text Base as compared to Non-Secure Boot. There are some LAW and TLB settings which are required specifically for Secure Boot scenario. ARM: ARM based SoC's have a fixed memory map and exit conditions from BootROM are same irrespective of boot mode (Secure or Non-Secure). Thus there is no seperate requirement for a separate Compile time target. Thus the current Secure Boot functionlity has been split into two parts: CONFIG_SECURE_BOOT = This is defined only for PowerPC SoC's for creating a different compile time target for secure boot. CONFIG_CHAIN_OF_TRUST This is defined for both ARM and PowerPC SoC's. It will have the following functionality as part of U-Boot: 1. Enable commands like esbc_validate, esbc_halt 2. Change the environment settings based on bootmode (determined at run time): - If bootmode is non-secure, no change - If bootmode is secure, set the following: - bootdelay = 0 (Don't give boot prompt) - bootcmd = Validate and execute the bootscript. Traditionally, both these functionalities were defined under CONFIG_SECURE_BOOT and thus a new target had to be added for Secure boot. After this change, for all ARM based SoC's, no separate target will be required for Secure Boot. CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be determine at run time. Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com> --- arch/arm/include/asm/fsl_secure_boot.h | 6 +- arch/powerpc/include/asm/fsl_secure_boot.h | 35 + board/freescale/common/Makefile| 2 - include/config_fsl_chain_trust.h | 89 ++ include/config_fsl_secboot.h | 116 - include/configs/ls1021aqds.h | 3 + include/configs/ls1021atwr.h | 3 + include/configs/ls1043aqds.h | 10 +++ include/configs/ls1043ardb.h | 3 + 9 files changed, 131 insertions(+), 136 deletions(-) create mode 100644 include/config_fsl_chain_trust.h delete mode 100644 include/config_fsl_secboot.h diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 05d3c07..bda1aca 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -7,7 +7,7 @@ #ifndef __FSL_SECURE_BOOT_H #define __FSL_SECURE_BOOT_H -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_CHAIN_OF_TRUST #define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_CMD_BLOB #define CONFIG_FSL_SEC_MON @@ -45,8 +45,8 @@ /* The address needs to be modified according to NOR memory map */ #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a -#include -#endif +#include #endif +#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 7d217a6..b29246a 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -9,19 +9,10 @@ #include #ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_ESBC_VALIDATE -#define CONFIG_CMD_BLOB -#define CONFIG_FSL_SEC_MON -#define CONFIG_SHA_PROG_HW_ACCEL -#define CONFIG_DM -#define CONFIG_RSA -#define CONFIG_RSA_FREESCALE_EXP -#ifndef CONFIG_FSL_CAAM -#define CONFIG_FSL_CAAM -#endif +#ifndef CONFIG_CHAIN_OF_TRUST +#define CONFIG_CHAIN_OF_TRUST #endif -#ifdef CONFIG_SECURE_BOOT #if defined(CONFIG_FSL_CORENET) #define CONFIG_SYS_PBI_FLASH_BASE 0xc000 #elif defined(CONFIG_BSC9132QDS) @@ -76,6 +67,20 @@ */ #define CONFIG_FSL_ISBC_KEY_EXT #endif +#endif /* #ifdef CONFIG_SECURE_BOOT */ + +#ifdef CONFIG_CHAIN_OF_TRUST + +#define CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_CMD_BLOB +#define CONFIG_FSL_SEC_MON +#define CONFIG_SHA_PROG_HW_ACCEL +#define CONFIG_DM +#define CONFIG_RSA +#define CONFIG_RSA_FREESCALE_EXP +#ifndef CONFIG_FSL_CAAM +#define CONFIG_FSL_CAAM +#endif #ifndef CONFIG_FIT_SIGNATURE /* If Boot Script is not on NOR and is required to be copied on RAM */ @@ -105,10 +110,10 @@ #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee02 #endif -#endif +#endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */ -#include -#endif +#include +#endif /* #ifndef CONFIG_FIT_SIGNATURE */ -#endif +#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 51d2814..9af8782 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/
[U-Boot] [PATCH 4/7] create function to determine boot mode
A function is created to detrmine if the boot mode is secure
or non-secure for differnt SoC's.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 ++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +
arch/powerpc/include/asm/immap_85xx.h | 3 ++
board/freescale/common/fsl_chain_of_trust.c| 53 ++
4 files changed, 61 insertions(+)
create mode 100644 board/freescale/common/fsl_chain_of_trust.c
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 21b803f..feb4498 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -218,6 +218,9 @@ struct ccsr_gur {
#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0x
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16
+#define RCW_SB_EN_REG_INDEX7
+#define RCW_SB_EN_MASK 0x0040
+
u8 res_140[0x200-0x140];
u32 scratchrw[4]; /* Scratch Read/Write */
u8 res_210[0x300-0x210];
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 89339fe..7665e3a 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -120,6 +120,8 @@ struct ccsr_gur {
u32 brrl; /* Boot release */
u8 res_0e8[0x100-0xe8];
u32 rcwsr[16]; /* Reset control word status */
+#define RCW_SB_EN_REG_INDEX7
+#define RCW_SB_EN_MASK 0x0040
u8 res_140[0x200-0x140];
u32 scratchrw[4]; /* Scratch Read/Write */
u8 res_210[0x300-0x210];
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 101b8db..f21dd97 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1749,6 +1749,8 @@ typedef struct ccsr_gur {
u32 brrl; /* Boot release */
u8 res17[24];
u32 rcwsr[16]; /* Reset control word status */
+#define RCW_SB_EN_REG_INDEX7
+#define RCW_SB_EN_MASK 0x0040
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
@@ -2194,6 +2196,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR2_DDR_SPD_00x0008
#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
#endif
+#define MPC85xx_PORDEVSR2_SBC_MASK 0x1000
/* The 8544 RM says this is bit 26, but it's really bit 24 */
#define MPC85xx_PORDEVSR2_SEC_CFG 0x0080
u8 res1[8];
diff --git a/board/freescale/common/fsl_chain_of_trust.c
b/board/freescale/common/fsl_chain_of_trust.c
new file mode 100644
index 000..ff67bd7
--- /dev/null
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+
+#ifdef CONFIG_LS102XA
+#include
+#endif
+
+#if defined(CONFIG_MPC85xx)
+#define CONFIG_DCFG_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+#else
+#define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR
+#endif
+
+#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
+#define gur_in32(a) in_le32(a)
+#else
+#define gur_in32(a) in_be32(a)
+#endif
+
+/* Check the Boot Mode. If Secure, return 1 else return 0 */
+int fsl_check_boot_mode_secure(void)
+{
+ uint32_t val;
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR);
+
+ val = sfp_in32(_regs->ospr) & ITS_MASK;
+ if (val == ITS_MASK)
+ return 1;
+
+#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx)
+ /* For PBL based platforms check the SB_EN bit in RCWSR */
+ val = gur_in32(>rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK;
+ if (val == RCW_SB_EN_MASK)
+ return 1;
+#endif
+
+#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET)
+ /* For Non-PBL Platforms, check the Device Status register 2*/
+ val = gur_in32(>pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK;
+ if (val != MPC85xx_PORDEVSR2_SBC_MASK)
+ return 1;
+
+#endif
+ return 0;
+}
--
1.8.1.4
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[U-Boot] [PATCH] arm, Makefile: correct compilation flag for u-boot-dtb
The compilation of u-boot-dtb.img should be controlled by CONFIG_OF_CONTROL and not CONFIG_DM. CONFIG_DM may be defined even without Device Tree requirement. This was added in commit 947cee1127c5fa97529c8cda4f0b48d141f92560. Signed-off-by: Ruchika Gupta <ruchika.gu...@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com> CC: Alison Wang <alison.w...@freescale.com> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index b58f283..a6af95d 100644 --- a/Makefile +++ b/Makefile @@ -1136,7 +1136,7 @@ spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) ifeq ($(ARCH),arm) -ifdef CONFIG_DM +ifdef CONFIG_OF_CONTROL UBOOT_BINLOAD := u-boot-dtb.img else UBOOT_BINLOAD := u-boot.img -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/4] SECURE BOOT: support for validation of dynamic image
Some images to be validated are relocated to a dynamic
address at run time. So, these addresses cannot be known
befor hand while signing the images and creating the header
offline.
So, support is required to pass the image address to the
validate function as an argument.
If an address is provided to the function, the address
field in Header is not read and is treated as a reserved
field.
Signed-off-by: Saksham Jain <saks...@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
board/freescale/common/cmd_esbc_validate.c | 10 ++---
board/freescale/common/fsl_validate.c | 33 ++
include/fsl_validate.h | 7 +--
3 files changed, 32 insertions(+), 18 deletions(-)
diff --git a/board/freescale/common/cmd_esbc_validate.c
b/board/freescale/common/cmd_esbc_validate.c
index ae6a9af..ca7c737 100644
--- a/board/freescale/common/cmd_esbc_validate.c
+++ b/board/freescale/common/cmd_esbc_validate.c
@@ -22,7 +22,7 @@ static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int
argc,
char * const argv[])
{
char *hash_str = NULL;
- ulong haddr;
+ uintptr_t haddr;
int ret;
if (argc < 2)
@@ -32,9 +32,13 @@ static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int
argc,
hash_str = argv[2];
/* First argument - header address -32/64bit */
- haddr = simple_strtoul(argv[1], NULL, 16);
+ haddr = (uintptr_t)simple_strtoul(argv[1], NULL, 16);
- ret = fsl_secboot_validate(haddr, hash_str);
+ /* With esbc_validate command, Image address must be
+* part of header. So, the function is called
+* by passing this argument as 0.
+*/
+ ret = fsl_secboot_validate(haddr, hash_str, 0);
if (ret)
return 1;
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 08a2f79..de40081 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -536,13 +536,8 @@ static int calc_esbchdr_esbc_hash(struct
fsl_secboot_img_priv *img)
return ret;
/* Update hash for actual Image */
-#ifdef CONFIG_ESBC_ADDR_64BIT
ret = algo->hash_update(algo, ctx,
- (u8 *)(uintptr_t)img->hdr.pimg64, img->hdr.img_size, 1);
-#else
- ret = algo->hash_update(algo, ctx,
- (u8 *)(uintptr_t)img->hdr.pimg, img->hdr.img_size, 1);
-#endif
+ (u8 *)img->img_addr, img->img_size, 1);
if (ret)
return ret;
@@ -632,16 +627,25 @@ static int read_validate_esbc_client_header(struct
fsl_secboot_img_priv *img)
if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN))
return ERROR_ESBC_CLIENT_HEADER_BARKER;
-#ifdef CONFIG_ESBC_ADDR_64BIT
- sprintf(buf, "%llx", hdr->pimg64);
-#else
- sprintf(buf, "%x", hdr->pimg);
-#endif
+ /* If Image Address is not passed as argument to function,
+* then Address and Size must be read from the Header.
+*/
+ if (img->img_addr == 0) {
+ #ifdef CONFIG_ESBC_ADDR_64BIT
+ img->img_addr = hdr->pimg64;
+ #else
+ img->img_addr = hdr->pimg;
+ #endif
+ }
+
+ sprintf(buf, "%lx", img->img_addr);
setenv("img_addr", buf);
if (!hdr->img_size)
return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE;
+ img->img_size = hdr->img_size;
+
/* Key checking*/
#ifdef CONFIG_KEY_REVOCATION
if (check_srk(img)) {
@@ -774,7 +778,8 @@ static int calculate_cmp_img_sig(struct
fsl_secboot_img_priv *img)
return 0;
}
-int fsl_secboot_validate(ulong haddr, char *arg_hash_str)
+int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
+ uintptr_t img_addr)
{
struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
ulong hash[SHA256_BYTES/sizeof(ulong)];
@@ -824,9 +829,11 @@ int fsl_secboot_validate(ulong haddr, char *arg_hash_str)
memset(img, 0, sizeof(struct fsl_secboot_img_priv));
+ /* Update the information in Private Struct */
hdr = >hdr;
img->ehdrloc = haddr;
- esbc = (u8 *)(uintptr_t)img->ehdrloc;
+ img->img_addr = img_addr;
+ esbc = (u8 *)img->ehdrloc;
memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr));
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index bda802f..ad14867 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -193,10 +193,13 @@ struct fsl_secboot_img_priv {
*/
struct fsl_secboot_sg_table sgtbl[MAX_SG_ENTRIES]; /* SG table */
- ulong ehdrloc; /* ESBC client location */
+ uintptr_t ehdrloc; /* ES
[U-Boot] [PATCH 2/5][v5] armv8: Make SEC read/write as snoopable for LS1043
For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
New Patch set created with an additional patch
Commit Subject modified
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 8896b70..85d8df8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -124,11 +124,16 @@ void fsl_lsch3_early_init_f(void)
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_FSL_IFC
init_early_memctl_regs(); /* tighten IFC timing */
#endif
+ /* Make SEC reads and writes snoopable */
+ setbits_be32(>snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
+SCFG_SNPCNFGCR_SECWRSNP);
+
/*
* Enable snoop requests and DVM message requests for
* Slave insterface S4 (A53 core cluster)
--
1.8.1.4
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[U-Boot] [PATCH 4/5][v5] armv8/ls1043ardb: add SECURE BOOT target for NOR
LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com> --- Changes in v5: - Commit Subject modified - Call to sec_init() placed under CONFIG_FSL_CAAM Changes in v4: - Fixed compilation break for LS1021AQDS Changes in v3: - Enabled CONFIG_SYS_NS16550=y, CONFIF_DM=y and other options similar to ls1043ardb_defconfig. - fsl_secure_boot.h is included outside of ifdef in file include/configs/ls1043ardb.h Changes in v2: - New Patch set created with an additional patch - Pointers typecasted to uintptr_t to remove compiler warnings arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 +-- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 +- arch/arm/include/asm/fsl_secure_boot.h | 6 +++- board/freescale/common/fsl_validate.c | 34 ++ board/freescale/ls1043ardb/MAINTAINERS | 5 board/freescale/ls1043ardb/ls1043ardb.c| 18 +++- common/cmd_blob.c | 6 ++-- configs/ls1043ardb_SECURE_BOOT_defconfig | 9 ++ include/configs/ls1043ardb.h | 10 +++ include/fsl_validate.h | 9 +- 10 files changed, 82 insertions(+), 21 deletions(-) create mode 100644 configs/ls1043ardb_SECURE_BOOT_defconfig diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index b5a2d28..6f4773a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -147,8 +147,8 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SNVS_LE -#define CONFIG_SYS_FSL_SEC_LE +#define CONFIG_SYS_FSL_SEC_MON_BE +#define CONFIG_SYS_FSL_SEC_BE #define CONFIG_SYS_FSL_SFP_BE #define CONFIG_SYS_FSL_SRK_LE #define CONFIG_KEY_REVOCATION diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 83caa91..e7def3a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -38,7 +38,7 @@ #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x260) #define CONFIG_SYS_FSL_SEC_ADDR(CONFIG_SYS_IMMR + 0x70) #define CONFIG_SYS_FSL_JR0_ADDR(CONFIG_SYS_IMMR + 0x71) -#define CONFIG_SYS_SNVS_ADDR (CONFIG_SYS_IMMR + 0xe9) +#define CONFIG_SYS_SEC_MON_ADDR(CONFIG_SYS_IMMR + 0xe9) #define CONFIG_SYS_SFP_ADDR(CONFIG_SYS_IMMR + 0xe80200) #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b0 diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index f2d4c3c..806302b 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -11,13 +11,17 @@ #define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_FSL_SEC_MON #define CONFIG_SHA_PROG_HW_ACCEL -#define CONFIG_DM #define CONFIG_RSA #define CONFIG_RSA_FREESCALE_EXP + #ifndef CONFIG_FSL_CAAM #define CONFIG_FSL_CAAM #endif +#ifndef CONFIG_DM +#define CONFIG_DM +#endif + #define CONFIG_KEY_REVOCATION #ifndef CONFIG_SYS_RAMBOOT /* The key used for verification of next level images diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 73b6718..b510c71 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -15,7 +15,7 @@ #include #include #include -#ifndef CONFIG_MPC85xx +#ifdef CONFIG_LS102XA #include #endif @@ -99,7 +99,8 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 csf_hdr_addr = in_be32(>scratchrw[0]); - if (memcmp((u8 *)csf_hdr_addr, barker_code, ESBC_BARKER_LEN)) + if (memcmp((u8 *)(uintptr_t)csf_hdr_addr, + barker_code, ESBC_BARKER_LEN)) return -1; *csf_addr = csf_hdr_addr; @@ -117,7 +118,7 @@ static int get_ie_info_addr(u32 *ie_addr) if (get_csf_base_addr(_addr, _base_addr)) return -1; - hdr = (struct fsl_secboot_img_hdr *)csf_addr; + hdr = (struct fsl_secboot_img_hdr *)(uintptr_t)csf_addr; /* For SoC's with Trust Architecture v1 with corenet bus * the sg table field in CSF header has absolute address @@ -130,7 +131,7 @@ static int get_ie_info_addr(u32 *ie_addr) (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + flash_base_addr); #else - sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr
[U-Boot] [PATCH 5/5][v5] drivers/crypto/fsl: fix endianness issue in RNG
For Setting and clearing the bits in SEC Block registers sec_clrbits32() and sec_setbits32() are used which work as per endianness of CAAM block. So these must be used with SEC register address as argument. If the value is read in a local variable, then the functions will not behave correctly where endianness of CAAM and core is different. Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com> CC: Alex Porosanu <alexandru.poros...@freescale.com> --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None (New Patch set created with an additional patch) drivers/crypto/fsl/jr.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index f63eacb..b553e3c 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -470,17 +470,13 @@ static void kick_trng(int ent_delay) sec_out32(>rtfreqmin, ent_delay >> 2); /* disable maximum frequency count */ sec_out32(>rtfreqmax, RTFRQMAX_DISABLE); - /* read the control register */ - val = sec_in32(>rtmctl); /* * select raw sampling in both entropy shifter * and statistical checker */ - sec_setbits32(, RTMCTL_SAMP_MODE_RAW_ES_SC); + sec_setbits32(>rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC); /* put RNG4 into run mode */ - sec_clrbits32(, RTMCTL_PRGM); - /* write back the control register */ - sec_out32(>rtmctl, val); + sec_clrbits32(>rtmctl, RTMCTL_PRGM); } static int rng_init(void) -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/5][v5] include/linux: move typdef for uintptr_t
uintptr_t which is a typdef for unsigned long is needed for creating pointers (32 or 64 bit depending on Core) from 32 bit variables storing the address. If a 32 bit variable (u32) is typecasted to a pointer (void *), compiler gives a warning in case size of pointer on the core is 64 bit. The typdef has been moved from include/compiler.h to include/linux/types.h Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com> --- Changes in v5: New patch instead of http://patchwork.ozlabs.org/patch/546319/ Changes in v4: None Changes in v3: None Changes in v2: None include/compiler.h| 3 --- include/linux/types.h | 1 + 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/include/compiler.h b/include/compiler.h index 47c296e..f853ed4 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -115,9 +115,6 @@ typedef unsigned int uint; #ifdef CONFIG_USE_STDINT /* Provided by gcc. */ #include -#else -/* Type for `void *' pointers. */ -typedef unsigned long int uintptr_t; #endif #include diff --git a/include/linux/types.h b/include/linux/types.h index 6f75be4..c7e8fdb 100644 --- a/include/linux/types.h +++ b/include/linux/types.h @@ -124,6 +124,7 @@ typedef __UINT64_TYPE__ u_int64_t; typedef__INT64_TYPE__ int64_t; #endif +typedef unsigned long uintptr_t; /* * Below are truly Linux-specific types that should never collide with * any application/library that wants linux/types.h. -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/5][v5] armv8: define usec2ticks function
usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v5:
- Commit Subject modified
Changes in v4: None
Changes in v3: None
Changes in v2: None (New Patch set created with an additional patch)
arch/arm/cpu/armv8/generic_timer.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/cpu/armv8/generic_timer.c
b/arch/arm/cpu/armv8/generic_timer.c
index 8e60bae..8f47a82 100644
--- a/arch/arm/cpu/armv8/generic_timer.c
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -40,3 +40,14 @@ unsigned long timer_read_counter(void)
#endif
return cntpct;
}
+
+unsigned long usec2ticks(unsigned long usec)
+{
+ ulong ticks;
+ if (usec < 1000)
+ ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
+ else
+ ticks = ((usec / 10) * (get_tbclk() / 10));
+
+ return ticks;
+}
--
1.8.1.4
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[U-Boot] [PATCH 2/4] SECURE BOOT: separate functions for reading keys
Separate functions are created for reading and checking the
sanity of Public keys:
- read_validate_single_key
- read_validate_ie_tbl
- read_validate_srk_table
Signed-off-by: Saksham Jain <saks...@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
board/freescale/common/fsl_validate.c | 169 +++---
1 file changed, 96 insertions(+), 73 deletions(-)
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 282ce53..ef7a5ae 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -24,6 +24,10 @@
#define SHA256_NIBBLES (256/4)
#define NUM_HEX_CHARS (sizeof(ulong) * 2)
+#define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \
+((key_len) == 2 * KEY_SIZE_BYTES / 2) || \
+((key_len) == 2 * KEY_SIZE_BYTES))
+
/* This array contains DER value for SHA-256 */
static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60,
0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00,
@@ -179,20 +183,97 @@ static u32 is_key_revoked(u32 keynum, u32 rev_flag)
return 0;
}
-/* It validates srk_table key lengths.*/
-static u32 validate_srk_tbl(struct srk_table *tbl, u32 num_entries)
+/* It read validates srk_table key lengths.*/
+static u32 read_validate_srk_tbl(struct fsl_secboot_img_priv *img)
{
int i = 0;
- for (i = 0; i < num_entries; i++) {
- if (!((tbl[i].key_len == 2 * KEY_SIZE_BYTES/4) ||
- (tbl[i].key_len == 2 * KEY_SIZE_BYTES/2) ||
- (tbl[i].key_len == 2 * KEY_SIZE_BYTES)))
+ u32 ret, key_num, key_revoc_flag, size;
+ struct fsl_secboot_img_hdr *hdr = >hdr;
+ void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
+
+ if ((hdr->len_kr.num_srk == 0) ||
+ (hdr->len_kr.num_srk > MAX_KEY_ENTRIES))
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY;
+
+ key_num = hdr->len_kr.srk_sel;
+ if (key_num == 0 || key_num > hdr->len_kr.num_srk)
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM;
+
+ /* Get revoc key from sfp */
+ key_revoc_flag = get_key_revoc();
+ ret = is_key_revoked(key_num, key_revoc_flag);
+ if (ret)
+ return ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED;
+
+ size = hdr->len_kr.num_srk * sizeof(struct srk_table);
+
+ memcpy(>srk_tbl, esbc + hdr->srk_tbl_off, size);
+
+ for (i = 0; i < hdr->len_kr.num_srk; i++) {
+ if (!CHECK_KEY_LEN(img->srk_tbl[i].key_len))
return ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN;
}
+
+ img->key_len = img->srk_tbl[key_num - 1].key_len;
+
+ memcpy(>img_key, &(img->srk_tbl[key_num - 1].pkey),
+ img->key_len);
+
return 0;
}
#endif
+static u32 read_validate_single_key(struct fsl_secboot_img_priv *img)
+{
+ struct fsl_secboot_img_hdr *hdr = >hdr;
+ void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
+
+ /* check key length */
+ if (!CHECK_KEY_LEN(hdr->key_len))
+ return ERROR_ESBC_CLIENT_HEADER_KEY_LEN;
+
+ memcpy(>img_key, esbc + hdr->pkey, hdr->key_len);
+
+ img->key_len = hdr->key_len;
+
+ return 0;
+}
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img)
+{
+ struct fsl_secboot_img_hdr *hdr = >hdr;
+ u32 ie_key_len, ie_revoc_flag, ie_num;
+ struct ie_key_info *ie_info;
+
+ if (get_ie_info_addr(>ie_addr))
+ return ERROR_IE_TABLE_NOT_FOUND;
+ ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr;
+ if (ie_info->num_keys == 0 || ie_info->num_keys > 32)
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY;
+
+ ie_num = hdr->ie_key_sel;
+ if (ie_num == 0 || ie_num > ie_info->num_keys)
+ return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM;
+
+ ie_revoc_flag = ie_info->key_revok;
+ if ((u32)(1 << (ie_num - 1)) & ie_revoc_flag)
+ return ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED;
+
+ ie_key_len = ie_info->ie_key_tbl[ie_num - 1].key_len;
+
+ if (!CHECK_KEY_LEN(ie_key_len))
+ return ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN;
+
+ memcpy(>img_key, &(ie_info->ie_key_tbl[ie_num - 1].pkey),
+ ie_key_len);
+
+ img->key_len = ie_key_len;
+ return 0;
+}
+#endif
+
+
/* This function return length of public key.*/
static inline u32 get_key_len(struct fsl_secboot_img_priv *img)
{
@@ -541,13 +622,9 @@ static int read_validate_esbc_client_header(struct
fsl_secboot_img_priv *img)
struct fsl_secboot_img_hdr *hdr = >hdr;
void *esb
[U-Boot] [PATCH 0/4] SECURE BOOT: support image validation before U-Boot completion
During U-Boot bringup, various other images like (MC, AIP etc.) are loaded from within U-Boot. In case of secure boot, these images must also be validated. Thus the existing Secure Boot validation code is made modular and the prototype for the function is changed. This patchset is dependent on [PATCH 5/5, v5] drivers/crypto/fsl: fix endianness issue in RNG http://patchwork.ozlabs.org/patch/553822/ Aneesh Bansal (4): SECURE BOOT: change prototype of fsl_secboot_validate function SECURE BOOT: separate functions for reading keys SECURE BOOT: separate function created for signature SECURE BOOT: Support for validation of dynamic image board/freescale/common/cmd_esbc_validate.c | 21 +- board/freescale/common/fsl_validate.c | 316 - include/fsl_validate.h | 8 +- 3 files changed, 201 insertions(+), 144 deletions(-) -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/4] SECURE BOOT: change prototype of fsl_secboot_validate function
The prototype and defination of function fsl_secboot_validate
has been changed to support calling this function from another
function within u-boot.
Only two aruments needed:
1) header address - Mandatory
2) SHA256 string - optional
Signed-off-by: Saksham Jain <saks...@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
board/freescale/common/cmd_esbc_validate.c | 17 -
board/freescale/common/fsl_validate.c | 18 +++---
include/fsl_validate.h | 5 ++---
3 files changed, 25 insertions(+), 15 deletions(-)
diff --git a/board/freescale/common/cmd_esbc_validate.c
b/board/freescale/common/cmd_esbc_validate.c
index 8bbe85b..ae6a9af 100644
--- a/board/freescale/common/cmd_esbc_validate.c
+++ b/board/freescale/common/cmd_esbc_validate.c
@@ -21,10 +21,25 @@ loop:
static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
+ char *hash_str = NULL;
+ ulong haddr;
+ int ret;
+
if (argc < 2)
return cmd_usage(cmdtp);
+ else if (argc > 2)
+ /* Second arg - Optional - Hash Str*/
+ hash_str = argv[2];
+
+ /* First argument - header address -32/64bit */
+ haddr = simple_strtoul(argv[1], NULL, 16);
- return fsl_secboot_validate(cmdtp, flag, argc, argv);
+ ret = fsl_secboot_validate(haddr, hash_str);
+ if (ret)
+ return 1;
+
+ printf("esbc_validate command successful\n");
+ return 0;
}
/***/
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index b510c71..282ce53 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -699,13 +699,11 @@ static inline int str2longbe(const char *p, ulong *num)
return *p != '\0' && *endptr == '\0';
}
-int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
+int fsl_secboot_validate(ulong haddr, char *arg_hash_str)
{
struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
ulong hash[SHA256_BYTES/sizeof(ulong)];
char hash_str[NUM_HEX_CHARS + 1];
- ulong addr = simple_strtoul(argv[1], NULL, 16);
struct fsl_secboot_img_priv *img;
struct fsl_secboot_img_hdr *hdr;
void *esbc;
@@ -717,8 +715,8 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int
argc,
struct udevice *mod_exp_dev;
#endif
- if (argc == 3) {
- char *cp = argv[2];
+ if (arg_hash_str != NULL) {
+ const char *cp = arg_hash_str;
int i = 0;
if (*cp == '0' && *(cp + 1) == 'x')
@@ -731,7 +729,7 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int
argc,
*/
if (strlen(cp) != SHA256_NIBBLES) {
printf("%s is not a 256 bits hex string as expected\n",
- argv[2]);
+ arg_hash_str);
return -1;
}
@@ -741,7 +739,7 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int
argc,
hash_str[NUM_HEX_CHARS] = '\0';
if (!str2longbe(hash_str, [i])) {
printf("%s is not a 256 bits hex string ",
- argv[2]);
+ arg_hash_str);
return -1;
}
}
@@ -757,7 +755,7 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int
argc,
memset(img, 0, sizeof(struct fsl_secboot_img_priv));
hdr = >hdr;
- img->ehdrloc = addr;
+ img->ehdrloc = haddr;
esbc = (u8 *)(uintptr_t)img->ehdrloc;
memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr));
@@ -843,8 +841,6 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int
argc,
goto exit;
}
- printf("esbc_validate command successful\n");
-
exit:
- return 0;
+ return ret;
}
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index a62dc74..bda802f 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -193,11 +193,10 @@ struct fsl_secboot_img_priv {
*/
struct fsl_secboot_sg_table sgtbl[MAX_SG_ENTRIES]; /* SG table */
- u32 ehdrloc;/* ESBC client location */
+ ulong ehdrloc; /* ESBC client location */
};
-int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[]);
+int fsl_secboot_validate(ulong haddr, char *arg_hash_str);
int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc,
[U-Boot] [PATCH 3/4] SECURE BOOT: separate function created for signature
The code for image hash calculation, hash calculation from
RSA signature and comparison of hashes has been mobed to a
separate function.
Signed-off-by: Saksham Jain <saks...@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
board/freescale/common/fsl_validate.c | 98 +++
1 file changed, 54 insertions(+), 44 deletions(-)
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index ef7a5ae..08a2f79 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -721,6 +721,58 @@ static inline int str2longbe(const char *p, ulong *num)
return *p != '\0' && *endptr == '\0';
}
+/* Function to calculate the ESBC Image Hash
+ * and hash from Digital signature.
+ * The Two hash's are compared to yield the
+ * result of signature validation.
+ */
+static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img)
+{
+ int ret;
+ uint32_t key_len;
+ struct key_prop prop;
+#if !defined(USE_HOSTCC)
+ struct udevice *mod_exp_dev;
+#endif
+ ret = calc_esbchdr_esbc_hash(img);
+ if (ret)
+ return ret;
+
+ /* Construct encoded hash EM' wrt PKCSv1.5 */
+ construct_img_encoded_hash_second(img);
+
+ /* Fill prop structure for public key */
+ memset(, 0, sizeof(struct key_prop));
+ key_len = get_key_len(img) / 2;
+ prop.modulus = img->img_key;
+ prop.public_exponent = img->img_key + key_len;
+ prop.num_bits = key_len * 8;
+ prop.exp_len = key_len;
+
+ ret = uclass_get_device(UCLASS_MOD_EXP, 0, _exp_dev);
+ if (ret) {
+ printf("RSA: Can't find Modular Exp implementation\n");
+ return -EINVAL;
+ }
+
+ ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len,
+ , img->img_encoded_hash);
+ if (ret)
+ return ret;
+
+ /*
+* compare the encoded messages EM' and EM wrt RSA PKCSv1.5
+* memcmp returns zero on success
+* memcmp returns non-zero on failure
+*/
+ ret = memcmp(>img_encoded_hash_second, >img_encoded_hash,
+ img->hdr.sign_len);
+
+ if (ret)
+ return ERROR_ESBC_CLIENT_HASH_COMPARE_EM;
+
+ return 0;
+}
int fsl_secboot_validate(ulong haddr, char *arg_hash_str)
{
@@ -732,11 +784,6 @@ int fsl_secboot_validate(ulong haddr, char *arg_hash_str)
void *esbc;
int ret, i, hash_cmd = 0;
u32 srk_hash[8];
- uint32_t key_len;
- struct key_prop prop;
-#if !defined(USE_HOSTCC)
- struct udevice *mod_exp_dev;
-#endif
if (arg_hash_str != NULL) {
const char *cp = arg_hash_str;
@@ -821,46 +868,9 @@ int fsl_secboot_validate(ulong haddr, char *arg_hash_str)
goto exit;
}
- ret = calc_esbchdr_esbc_hash(img);
- if (ret) {
- fsl_secblk_handle_error(ret);
- goto exit;
- }
-
- /* Construct encoded hash EM' wrt PKCSv1.5 */
- construct_img_encoded_hash_second(img);
-
- /* Fill prop structure for public key */
- memset(, 0, sizeof(struct key_prop));
- key_len = get_key_len(img) / 2;
- prop.modulus = img->img_key;
- prop.public_exponent = img->img_key + key_len;
- prop.num_bits = key_len * 8;
- prop.exp_len = key_len;
-
- ret = uclass_get_device(UCLASS_MOD_EXP, 0, _exp_dev);
- if (ret) {
- printf("RSA: Can't find Modular Exp implementation\n");
- return -EINVAL;
- }
-
- ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len,
- , img->img_encoded_hash);
- if (ret) {
- fsl_secblk_handle_error(ret);
- goto exit;
- }
-
- /*
-* compare the encoded messages EM' and EM wrt RSA PKCSv1.5
-* memcmp returns zero on success
-* memcmp returns non-zero on failure
-*/
- ret = memcmp(>img_encoded_hash_second, >img_encoded_hash,
- img->hdr.sign_len);
-
+ ret = calculate_cmp_img_sig(img);
if (ret) {
- fsl_secboot_handle_error(ERROR_ESBC_CLIENT_HASH_COMPARE_EM);
+ fsl_secboot_handle_error(ret);
goto exit;
}
--
1.8.1.4
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[U-Boot] [PATCH 4/5][v4] armv8/ls1043ardb: SECURE BOOT target added for NOR
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v4:
- Fixed compilation break for LS1021AQDS
arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 +--
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 +-
arch/arm/include/asm/fsl_secure_boot.h | 6 +++-
board/freescale/common/fsl_validate.c | 34 ++
board/freescale/ls1043ardb/MAINTAINERS | 5
board/freescale/ls1043ardb/ls1043ardb.c| 18 +++-
common/cmd_blob.c | 6 ++--
configs/ls1043ardb_SECURE_BOOT_defconfig | 9 ++
include/configs/ls1043ardb.h | 10 +++
include/fsl_validate.h | 9 +-
10 files changed, 82 insertions(+), 21 deletions(-)
create mode 100644 configs/ls1043ardb_SECURE_BOOT_defconfig
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index b5a2d28..6f4773a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -147,8 +147,8 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_SFP_VER_3_2
-#define CONFIG_SYS_FSL_SNVS_LE
-#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SEC_MON_BE
+#define CONFIG_SYS_FSL_SEC_BE
#define CONFIG_SYS_FSL_SFP_BE
#define CONFIG_SYS_FSL_SRK_LE
#define CONFIG_KEY_REVOCATION
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 83caa91..e7def3a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -38,7 +38,7 @@
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x260)
#define CONFIG_SYS_FSL_SEC_ADDR(CONFIG_SYS_IMMR +
0x70)
#define CONFIG_SYS_FSL_JR0_ADDR(CONFIG_SYS_IMMR +
0x71)
-#define CONFIG_SYS_SNVS_ADDR (CONFIG_SYS_IMMR + 0xe9)
+#define CONFIG_SYS_SEC_MON_ADDR(CONFIG_SYS_IMMR +
0xe9)
#define CONFIG_SYS_SFP_ADDR(CONFIG_SYS_IMMR + 0xe80200)
#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b0
diff --git a/arch/arm/include/asm/fsl_secure_boot.h
b/arch/arm/include/asm/fsl_secure_boot.h
index f2d4c3c..806302b 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -11,13 +11,17 @@
#define CONFIG_CMD_ESBC_VALIDATE
#define CONFIG_FSL_SEC_MON
#define CONFIG_SHA_PROG_HW_ACCEL
-#define CONFIG_DM
#define CONFIG_RSA
#define CONFIG_RSA_FREESCALE_EXP
+
#ifndef CONFIG_FSL_CAAM
#define CONFIG_FSL_CAAM
#endif
+#ifndef CONFIG_DM
+#define CONFIG_DM
+#endif
+
#define CONFIG_KEY_REVOCATION
#ifndef CONFIG_SYS_RAMBOOT
/* The key used for verification of next level images
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 73b6718..b510c71 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -15,7 +15,7 @@
#include
#include
#include
-#ifndef CONFIG_MPC85xx
+#ifdef CONFIG_LS102XA
#include
#endif
@@ -99,7 +99,8 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(>scratchrw[0]);
- if (memcmp((u8 *)csf_hdr_addr, barker_code, ESBC_BARKER_LEN))
+ if (memcmp((u8 *)(uintptr_t)csf_hdr_addr,
+ barker_code, ESBC_BARKER_LEN))
return -1;
*csf_addr = csf_hdr_addr;
@@ -117,7 +118,7 @@ static int get_ie_info_addr(u32 *ie_addr)
if (get_csf_base_addr(_addr, _base_addr))
return -1;
- hdr = (struct fsl_secboot_img_hdr *)csf_addr;
+ hdr = (struct fsl_secboot_img_hdr *)(uintptr_t)csf_addr;
/* For SoC's with Trust Architecture v1 with corenet bus
* the sg table field in CSF header has absolute address
@@ -130,7 +131,7 @@ static int get_ie_info_addr(u32 *ie_addr)
(((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
flash_base_addr);
#else
- sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr +
+ sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr +
(u32)hdr->psgtable);
#endif
@@ -379,8 +380,8 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv
*img)
#ifdef CONFIG_KEY_REVOCATION
if (check_srk(img)) {
ret = algo->hash_update(algo, ctx,
- (u8 *)(img->ehdrloc + img->hdr.srk
[U-Boot] [PATCH 4/5][v3] armv8/ls1043ardb: SECURE BOOT target added for NOR
LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com> --- Changes in v3: - Enabled CONFIG_SYS_NS16550=y, CONFIF_DM=y and other options similar to ls1043ardb_defconfig. - fsl_secure_boot.h is included outside of ifdef in file include/configs/ls1043ardb.h arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 +-- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 +- arch/arm/include/asm/fsl_secure_boot.h | 6 +++- board/freescale/common/fsl_validate.c | 35 +- board/freescale/ls1043ardb/MAINTAINERS | 5 board/freescale/ls1043ardb/ls1043ardb.c| 18 ++- common/cmd_blob.c | 6 ++-- configs/ls1043ardb_SECURE_BOOT_defconfig | 9 ++ include/configs/ls1043ardb.h | 10 +++ include/fsl_validate.h | 9 +- 10 files changed, 81 insertions(+), 23 deletions(-) create mode 100644 configs/ls1043ardb_SECURE_BOOT_defconfig diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index b5a2d28..6f4773a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -147,8 +147,8 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SNVS_LE -#define CONFIG_SYS_FSL_SEC_LE +#define CONFIG_SYS_FSL_SEC_MON_BE +#define CONFIG_SYS_FSL_SEC_BE #define CONFIG_SYS_FSL_SFP_BE #define CONFIG_SYS_FSL_SRK_LE #define CONFIG_KEY_REVOCATION diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 83caa91..e7def3a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -38,7 +38,7 @@ #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x260) #define CONFIG_SYS_FSL_SEC_ADDR(CONFIG_SYS_IMMR + 0x70) #define CONFIG_SYS_FSL_JR0_ADDR(CONFIG_SYS_IMMR + 0x71) -#define CONFIG_SYS_SNVS_ADDR (CONFIG_SYS_IMMR + 0xe9) +#define CONFIG_SYS_SEC_MON_ADDR(CONFIG_SYS_IMMR + 0xe9) #define CONFIG_SYS_SFP_ADDR(CONFIG_SYS_IMMR + 0xe80200) #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b0 diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index f2d4c3c..806302b 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -11,13 +11,17 @@ #define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_FSL_SEC_MON #define CONFIG_SHA_PROG_HW_ACCEL -#define CONFIG_DM #define CONFIG_RSA #define CONFIG_RSA_FREESCALE_EXP + #ifndef CONFIG_FSL_CAAM #define CONFIG_FSL_CAAM #endif +#ifndef CONFIG_DM +#define CONFIG_DM +#endif + #define CONFIG_KEY_REVOCATION #ifndef CONFIG_SYS_RAMBOOT /* The key used for verification of next level images diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 73b6718..733aa48 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -15,9 +15,6 @@ #include #include #include -#ifndef CONFIG_MPC85xx -#include -#endif #define SHA256_BITS256 #define SHA256_BYTES (256/8) @@ -99,7 +96,8 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 csf_hdr_addr = in_be32(>scratchrw[0]); - if (memcmp((u8 *)csf_hdr_addr, barker_code, ESBC_BARKER_LEN)) + if (memcmp((u8 *)(uintptr_t)csf_hdr_addr, + barker_code, ESBC_BARKER_LEN)) return -1; *csf_addr = csf_hdr_addr; @@ -117,7 +115,7 @@ static int get_ie_info_addr(u32 *ie_addr) if (get_csf_base_addr(_addr, _base_addr)) return -1; - hdr = (struct fsl_secboot_img_hdr *)csf_addr; + hdr = (struct fsl_secboot_img_hdr *)(uintptr_t)csf_addr; /* For SoC's with Trust Architecture v1 with corenet bus * the sg table field in CSF header has absolute address @@ -130,7 +128,7 @@ static int get_ie_info_addr(u32 *ie_addr) (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + flash_base_addr); #else - sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr + + sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr + (u32)hdr->psgtable); #endif @@ -379,8 +377,8 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv *img)
[U-Boot] [PATCH 1/4] armv8: usec2ticks function defined
usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
arch/arm/cpu/armv8/generic_timer.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/cpu/armv8/generic_timer.c
b/arch/arm/cpu/armv8/generic_timer.c
index 8e60bae..8f47a82 100644
--- a/arch/arm/cpu/armv8/generic_timer.c
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -40,3 +40,14 @@ unsigned long timer_read_counter(void)
#endif
return cntpct;
}
+
+unsigned long usec2ticks(unsigned long usec)
+{
+ ulong ticks;
+ if (usec < 1000)
+ ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
+ else
+ ticks = ((usec / 10) * (get_tbclk() / 10));
+
+ return ticks;
+}
--
1.8.1.4
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[U-Boot] [PATCH 4/4] drivers/crypto/fsl: fix endianness issue in RNG
For Setting and clearing the bits in SEC Block registers sec_clrbits32() and sec_setbits32() are used which work as per endianness of CAAM block. So these must be used with SEC register address as argument. If the value is read in a local variable, then the functions will not behave correctly where endianness of CAAM and core is different. Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com> CC: Alex Porosanu <alexandru.poros...@freescale.com> --- drivers/crypto/fsl/jr.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index f63eacb..b553e3c 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -470,17 +470,13 @@ static void kick_trng(int ent_delay) sec_out32(>rtfreqmin, ent_delay >> 2); /* disable maximum frequency count */ sec_out32(>rtfreqmax, RTFRQMAX_DISABLE); - /* read the control register */ - val = sec_in32(>rtmctl); /* * select raw sampling in both entropy shifter * and statistical checker */ - sec_setbits32(, RTMCTL_SAMP_MODE_RAW_ES_SC); + sec_setbits32(>rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC); /* put RNG4 into run mode */ - sec_clrbits32(, RTMCTL_PRGM); - /* write back the control register */ - sec_out32(>rtmctl, val); + sec_clrbits32(>rtmctl, RTMCTL_PRGM); } static int rng_init(void) -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4] armv8/ls1043ardb: SECURE BOOT target added for NOR
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 16 --
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 +-
board/freescale/common/fsl_validate.c | 35 +-
board/freescale/ls1043ardb/MAINTAINERS | 5
board/freescale/ls1043ardb/ls1043ardb.c| 18 ++-
common/cmd_blob.c | 6 ++--
configs/ls1043ardb_SECURE_BOOT_defconfig | 4 +++
include/configs/ls1043ardb.h | 12
include/fsl_validate.h | 9 +-
9 files changed, 85 insertions(+), 22 deletions(-)
create mode 100644 configs/ls1043ardb_SECURE_BOOT_defconfig
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 87bb937..d6729a0 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -122,9 +122,21 @@
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_ESBC_VALIDATE
+#define CONFIG_FSL_SEC_MON
+#define CONFIG_SHA_PROG_HW_ACCEL
+#define CONFIG_DM
+#define CONFIG_RSA
+#define CONFIG_RSA_FREESCALE_EXP
+#ifndef CONFIG_FSL_CAAM
+#define CONFIG_FSL_CAAM
+#endif
+#endif
+
#define CONFIG_SYS_FSL_SFP_VER_3_2
-#define CONFIG_SYS_FSL_SNVS_LE
-#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SEC_MON_BE
+#define CONFIG_SYS_FSL_SEC_BE
#define CONFIG_SYS_FSL_SFP_BE
#define CONFIG_SYS_FSL_SRK_LE
#define CONFIG_KEY_REVOCATION
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d941437..2a3a7da 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -38,7 +38,7 @@
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x260)
#define CONFIG_SYS_FSL_SEC_ADDR(CONFIG_SYS_IMMR +
0x70)
#define CONFIG_SYS_FSL_JR0_ADDR(CONFIG_SYS_IMMR +
0x71)
-#define CONFIG_SYS_SNVS_ADDR (CONFIG_SYS_IMMR + 0xe9)
+#define CONFIG_SYS_SEC_MON_ADDR(CONFIG_SYS_IMMR +
0xe9)
#define CONFIG_SYS_SFP_ADDR(CONFIG_SYS_IMMR + 0xe80200)
#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b0
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 73b6718..1fb5eaa 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -15,9 +15,6 @@
#include
#include
#include
-#ifndef CONFIG_MPC85xx
-#include
-#endif
#define SHA256_BITS256
#define SHA256_BYTES (256/8)
@@ -99,7 +96,8 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(>scratchrw[0]);
- if (memcmp((u8 *)csf_hdr_addr, barker_code, ESBC_BARKER_LEN))
+ if (memcmp((u8 *)(dma_addr_t)csf_hdr_addr,
+ barker_code, ESBC_BARKER_LEN))
return -1;
*csf_addr = csf_hdr_addr;
@@ -117,7 +115,7 @@ static int get_ie_info_addr(u32 *ie_addr)
if (get_csf_base_addr(_addr, _base_addr))
return -1;
- hdr = (struct fsl_secboot_img_hdr *)csf_addr;
+ hdr = (struct fsl_secboot_img_hdr *)(dma_addr_t)csf_addr;
/* For SoC's with Trust Architecture v1 with corenet bus
* the sg table field in CSF header has absolute address
@@ -130,7 +128,7 @@ static int get_ie_info_addr(u32 *ie_addr)
(((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
flash_base_addr);
#else
- sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr +
+ sg_tbl = (struct fsl_secboot_sg_table *)(dma_addr_t)(csf_addr +
(u32)hdr->psgtable);
#endif
@@ -379,8 +377,8 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv
*img)
#ifdef CONFIG_KEY_REVOCATION
if (check_srk(img)) {
ret = algo->hash_update(algo, ctx,
- (u8 *)(img->ehdrloc + img->hdr.srk_tbl_off),
- img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1);
+ (u8 *)(dma_addr_t)(img->ehdrloc + img->hdr.srk_tbl_off),
+ img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1);
srk = 1;
}
#endif
@@ -438,8 +436,8 @@ static int calc_esbchdr_esbc_hash(struct
fsl_secboot_img_priv *img)
#ifd
[U-Boot] [PATCH 2/4] armv8: Make SEC read/write as Snoopable for LS1043
For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 637853d..e7b188d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -81,11 +81,16 @@ void fsl_lsch3_early_init_f(void)
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_FSL_IFC
init_early_memctl_regs(); /* tighten IFC timing */
#endif
+ /* Make SEC reads and writes snoopable */
+ setbits_be32(>snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
+SCFG_SNPCNFGCR_SECWRSNP);
+
/*
* Enable snoop requests and DVM message requests for
* Slave insterface S4 (A53 core cluster)
--
1.8.1.4
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[U-Boot] [PATCH 2/5][v2] armv8: Make SEC read/write as snoopable for LS1043
For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v2:
New Patch Set created with an additional patch
Commit Subject modified
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 637853d..e7b188d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -81,11 +81,16 @@ void fsl_lsch3_early_init_f(void)
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_FSL_IFC
init_early_memctl_regs(); /* tighten IFC timing */
#endif
+ /* Make SEC reads and writes snoopable */
+ setbits_be32(>snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
+SCFG_SNPCNFGCR_SECWRSNP);
+
/*
* Enable snoop requests and DVM message requests for
* Slave insterface S4 (A53 core cluster)
--
1.8.1.4
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[U-Boot] [PATCH 4/5][v2] armv8/ls1043ardb: SECURE BOOT target added for NOR
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v2:
New Patch Set created with an additional patch.
Pointers typecasted to uintptr_t to remove compiler warnings
arch/arm/include/asm/arch-fsl-layerscape/config.h | 16 --
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 +-
board/freescale/common/fsl_validate.c | 35 +-
board/freescale/ls1043ardb/MAINTAINERS | 5
board/freescale/ls1043ardb/ls1043ardb.c| 18 ++-
common/cmd_blob.c | 6 ++--
configs/ls1043ardb_SECURE_BOOT_defconfig | 4 +++
include/configs/ls1043ardb.h | 12
include/fsl_validate.h | 9 +-
9 files changed, 85 insertions(+), 22 deletions(-)
create mode 100644 configs/ls1043ardb_SECURE_BOOT_defconfig
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 87bb937..d6729a0 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -122,9 +122,21 @@
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_ESBC_VALIDATE
+#define CONFIG_FSL_SEC_MON
+#define CONFIG_SHA_PROG_HW_ACCEL
+#define CONFIG_DM
+#define CONFIG_RSA
+#define CONFIG_RSA_FREESCALE_EXP
+#ifndef CONFIG_FSL_CAAM
+#define CONFIG_FSL_CAAM
+#endif
+#endif
+
#define CONFIG_SYS_FSL_SFP_VER_3_2
-#define CONFIG_SYS_FSL_SNVS_LE
-#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SEC_MON_BE
+#define CONFIG_SYS_FSL_SEC_BE
#define CONFIG_SYS_FSL_SFP_BE
#define CONFIG_SYS_FSL_SRK_LE
#define CONFIG_KEY_REVOCATION
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d941437..2a3a7da 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -38,7 +38,7 @@
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x260)
#define CONFIG_SYS_FSL_SEC_ADDR(CONFIG_SYS_IMMR +
0x70)
#define CONFIG_SYS_FSL_JR0_ADDR(CONFIG_SYS_IMMR +
0x71)
-#define CONFIG_SYS_SNVS_ADDR (CONFIG_SYS_IMMR + 0xe9)
+#define CONFIG_SYS_SEC_MON_ADDR(CONFIG_SYS_IMMR +
0xe9)
#define CONFIG_SYS_SFP_ADDR(CONFIG_SYS_IMMR + 0xe80200)
#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b0
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 73b6718..733aa48 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -15,9 +15,6 @@
#include
#include
#include
-#ifndef CONFIG_MPC85xx
-#include
-#endif
#define SHA256_BITS256
#define SHA256_BYTES (256/8)
@@ -99,7 +96,8 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(>scratchrw[0]);
- if (memcmp((u8 *)csf_hdr_addr, barker_code, ESBC_BARKER_LEN))
+ if (memcmp((u8 *)(uintptr_t)csf_hdr_addr,
+ barker_code, ESBC_BARKER_LEN))
return -1;
*csf_addr = csf_hdr_addr;
@@ -117,7 +115,7 @@ static int get_ie_info_addr(u32 *ie_addr)
if (get_csf_base_addr(_addr, _base_addr))
return -1;
- hdr = (struct fsl_secboot_img_hdr *)csf_addr;
+ hdr = (struct fsl_secboot_img_hdr *)(uintptr_t)csf_addr;
/* For SoC's with Trust Architecture v1 with corenet bus
* the sg table field in CSF header has absolute address
@@ -130,7 +128,7 @@ static int get_ie_info_addr(u32 *ie_addr)
(((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
flash_base_addr);
#else
- sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr +
+ sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr +
(u32)hdr->psgtable);
#endif
@@ -379,8 +377,8 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv
*img)
#ifdef CONFIG_KEY_REVOCATION
if (check_srk(img)) {
ret = algo->hash_update(algo, ctx,
- (u8 *)(img->ehdrloc + img->hdr.srk_tbl_off),
- img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1);
+ (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off),
+ img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1);
srk = 1
[U-Boot] [PATCH 1/5][v2] armv8: usec2ticks function defined
usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v2:
New Patch Set created with an additional patch.
arch/arm/cpu/armv8/generic_timer.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/cpu/armv8/generic_timer.c
b/arch/arm/cpu/armv8/generic_timer.c
index 8e60bae..8f47a82 100644
--- a/arch/arm/cpu/armv8/generic_timer.c
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -40,3 +40,14 @@ unsigned long timer_read_counter(void)
#endif
return cntpct;
}
+
+unsigned long usec2ticks(unsigned long usec)
+{
+ ulong ticks;
+ if (usec < 1000)
+ ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
+ else
+ ticks = ((usec / 10) * (get_tbclk() / 10));
+
+ return ticks;
+}
--
1.8.1.4
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[U-Boot] [PATCH 3/5] Data type defined for pointer addresses
A new data type uintptr_t has been defined for creating pointers (32 or 64 bit depending on Core) from 32 bit variables storing the address. If a 32 bit variable (u32) is typecasted to a pointer (void *), compiler gives a warning in case size of pointer on the core is 64 bit. Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com> --- arch/arm/include/asm/types.h | 2 ++ arch/powerpc/include/asm/types.h | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h index 388058e..765 100644 --- a/arch/arm/include/asm/types.h +++ b/arch/arm/include/asm/types.h @@ -56,6 +56,8 @@ typedef unsigned long phys_addr_t; typedef unsigned long phys_size_t; #endif +typedef unsigned long uintptr_t; + #endif /* __KERNEL__ */ typedef unsigned long resource_size_t; diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h index b29ce79..6b908ec 100644 --- a/arch/powerpc/include/asm/types.h +++ b/arch/powerpc/include/asm/types.h @@ -56,6 +56,7 @@ typedef unsigned long phys_addr_t; typedef unsigned long phys_size_t; #endif +typedef unsigned long uintptr_t; #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/5][v2] drivers/crypto/fsl: fix endianness issue in RNG
For Setting and clearing the bits in SEC Block registers sec_clrbits32() and sec_setbits32() are used which work as per endianness of CAAM block. So these must be used with SEC register address as argument. If the value is read in a local variable, then the functions will not behave correctly where endianness of CAAM and core is different. Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com> CC: Alex Porosanu <alexandru.poros...@freescale.com> --- Changes in v2: New Patch Set created with an additional patch. drivers/crypto/fsl/jr.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index f63eacb..b553e3c 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -470,17 +470,13 @@ static void kick_trng(int ent_delay) sec_out32(>rtfreqmin, ent_delay >> 2); /* disable maximum frequency count */ sec_out32(>rtfreqmax, RTFRQMAX_DISABLE); - /* read the control register */ - val = sec_in32(>rtmctl); /* * select raw sampling in both entropy shifter * and statistical checker */ - sec_setbits32(, RTMCTL_SAMP_MODE_RAW_ES_SC); + sec_setbits32(>rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC); /* put RNG4 into run mode */ - sec_clrbits32(, RTMCTL_PRGM); - /* write back the control register */ - sec_out32(>rtmctl, val); + sec_clrbits32(>rtmctl, RTMCTL_PRGM); } static int rng_init(void) -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3][v5] crypto/fsl: SEC driver cleanup for 64 bit and endianness
The SEC driver code has been cleaned up to work for 64 bit
physical addresses and systems where endianess of SEC block
is different from the Core.
Changes:
1. Descriptor created on Core is modified as per SEC block
endianness before the job is submitted.
2. The read/write of physical addresses to Job Rings will
be depend on endianness of SEC block as 32 bit low and
high part of the 64 bit address will vary.
3. The 32 bit low and high part of the 64 bit address in
descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v5:
Removed compile time warnings
drivers/crypto/fsl/desc_constr.h | 26
drivers/crypto/fsl/fsl_hash.c| 8 ++--
drivers/crypto/fsl/jr.c | 86 ++--
drivers/crypto/fsl/jr.h | 7 ++--
include/fsl_sec.h| 6 +--
5 files changed, 109 insertions(+), 24 deletions(-)
diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h
index f9cae91..2559ccd 100644
--- a/drivers/crypto/fsl/desc_constr.h
+++ b/drivers/crypto/fsl/desc_constr.h
@@ -36,6 +36,23 @@
LDST_SRCDST_WORD_DECOCTRL | \
(LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
+#ifdef CONFIG_PHYS_64BIT
+union ptr_addr_t {
+ u64 m_whole;
+ struct {
+#ifdef CONFIG_SYS_FSL_SEC_LE
+ u32 low;
+ u32 high;
+#elif defined(CONFIG_SYS_FSL_SEC_BE)
+ u32 high;
+ u32 low;
+#else
+#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
+#endif
+ } m_halfs;
+};
+#endif
+
static inline int desc_len(u32 *desc)
{
return *desc & HDR_DESCLEN_MASK;
@@ -65,7 +82,16 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr)
{
dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
+#ifdef CONFIG_PHYS_64BIT
+ /* The Position of low and high part of 64 bit address
+* will depend on the endianness of CAAM Block */
+ union ptr_addr_t ptr_addr;
+ ptr_addr.m_halfs.high = (u32)(ptr >> 32);
+ ptr_addr.m_halfs.low = (u32)ptr;
+ *offset = ptr_addr.m_whole;
+#else
*offset = ptr;
+#endif
(*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ;
}
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
index c298404..887e88c 100644
--- a/drivers/crypto/fsl/fsl_hash.c
+++ b/drivers/crypto/fsl/fsl_hash.c
@@ -84,7 +84,7 @@ static int caam_hash_update(void *hash_ctx, const void *buf,
enum caam_hash_algos caam_algo)
{
uint32_t final = 0;
- dma_addr_t addr = virt_to_phys((void *)buf);
+ phys_addr_t addr = virt_to_phys((void *)buf);
struct sha_ctx *ctx = hash_ctx;
if (ctx->sg_num >= MAX_SG_32) {
@@ -93,11 +93,11 @@ static int caam_hash_update(void *hash_ctx, const void *buf,
}
#ifdef CONFIG_PHYS_64BIT
- ctx->sg_tbl[ctx->sg_num].addr_hi = addr >> 32;
+ sec_out32(>sg_tbl[ctx->sg_num].addr_hi, (uint32_t)(addr >> 32));
#else
- ctx->sg_tbl[ctx->sg_num].addr_hi = 0x0;
+ sec_out32(>sg_tbl[ctx->sg_num].addr_hi, 0x0);
#endif
- ctx->sg_tbl[ctx->sg_num].addr_lo = addr;
+ sec_out32(>sg_tbl[ctx->sg_num].addr_lo, (uint32_t)addr);
sec_out32(>sg_tbl[ctx->sg_num].len_flag,
(size & SG_ENTRY_LENGTH_MASK));
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 17392c9..f63eacb 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -11,6 +11,7 @@
#include "fsl_sec.h"
#include "jr.h"
#include "jobdesc.h"
+#include "desc_constr.h"
#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
@@ -154,19 +155,35 @@ static int jr_hw_reset(void)
/* -1 --- error, can't enqueue -- no space available */
static int jr_enqueue(uint32_t *desc_addr,
- void (*callback)(uint32_t desc, uint32_t status, void *arg),
+ void (*callback)(uint32_t status, void *arg),
void *arg)
{
struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
int head = jr.head;
- dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
+ uint32_t desc_word;
+ int length = desc_len(desc_addr);
+ int i;
+#ifdef CONFIG_PHYS_64BIT
+ uint32_t *addr_hi, *addr_lo;
+#endif
+
+ /* The descriptor must be submitted to SEC block as per endianness
+* of the SEC Block.
+* So, if the endianness of Core and SEC block is different, each word
+* of the descriptor will be byte-swapped.
+*/
+ for (i = 0; i < length; i++) {
+ desc_word = desc_addr[i];
+ sec_out32((uint32_t *)_addr[i], desc_word);
+
[U-Boot] [PATCH 3/3][v4] crypto/fsl: SEC driver cleanup for 64 bit and endianness
The SEC driver code has been cleaned up to work for 64 bit
physical addresses and systems where endianess of SEC block
is different from the Core.
Changes:
1. Descriptor created on Core is modified as per SEC block
endianness before the job is submitted.
2. The read/write of physical addresses to Job Rings will
be depend on endianness of SEC block as 32 bit low and
high part of the 64 bit address will vary.
3. The 32 bit low and high part of the 64 bit address in
descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v4:
Removed compile time warnings when compiling for ls1021a
drivers/crypto/fsl/desc_constr.h | 26
drivers/crypto/fsl/fsl_hash.c| 8 ++--
drivers/crypto/fsl/jr.c | 85 ++--
drivers/crypto/fsl/jr.h | 7 ++--
include/fsl_sec.h| 6 +--
5 files changed, 108 insertions(+), 24 deletions(-)
diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h
index f9cae91..2559ccd 100644
--- a/drivers/crypto/fsl/desc_constr.h
+++ b/drivers/crypto/fsl/desc_constr.h
@@ -36,6 +36,23 @@
LDST_SRCDST_WORD_DECOCTRL | \
(LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
+#ifdef CONFIG_PHYS_64BIT
+union ptr_addr_t {
+ u64 m_whole;
+ struct {
+#ifdef CONFIG_SYS_FSL_SEC_LE
+ u32 low;
+ u32 high;
+#elif defined(CONFIG_SYS_FSL_SEC_BE)
+ u32 high;
+ u32 low;
+#else
+#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
+#endif
+ } m_halfs;
+};
+#endif
+
static inline int desc_len(u32 *desc)
{
return *desc & HDR_DESCLEN_MASK;
@@ -65,7 +82,16 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr)
{
dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
+#ifdef CONFIG_PHYS_64BIT
+ /* The Position of low and high part of 64 bit address
+* will depend on the endianness of CAAM Block */
+ union ptr_addr_t ptr_addr;
+ ptr_addr.m_halfs.high = (u32)(ptr >> 32);
+ ptr_addr.m_halfs.low = (u32)ptr;
+ *offset = ptr_addr.m_whole;
+#else
*offset = ptr;
+#endif
(*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ;
}
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
index c298404..887e88c 100644
--- a/drivers/crypto/fsl/fsl_hash.c
+++ b/drivers/crypto/fsl/fsl_hash.c
@@ -84,7 +84,7 @@ static int caam_hash_update(void *hash_ctx, const void *buf,
enum caam_hash_algos caam_algo)
{
uint32_t final = 0;
- dma_addr_t addr = virt_to_phys((void *)buf);
+ phys_addr_t addr = virt_to_phys((void *)buf);
struct sha_ctx *ctx = hash_ctx;
if (ctx->sg_num >= MAX_SG_32) {
@@ -93,11 +93,11 @@ static int caam_hash_update(void *hash_ctx, const void *buf,
}
#ifdef CONFIG_PHYS_64BIT
- ctx->sg_tbl[ctx->sg_num].addr_hi = addr >> 32;
+ sec_out32(>sg_tbl[ctx->sg_num].addr_hi, (uint32_t)(addr >> 32));
#else
- ctx->sg_tbl[ctx->sg_num].addr_hi = 0x0;
+ sec_out32(>sg_tbl[ctx->sg_num].addr_hi, 0x0);
#endif
- ctx->sg_tbl[ctx->sg_num].addr_lo = addr;
+ sec_out32(>sg_tbl[ctx->sg_num].addr_lo, (uint32_t)addr);
sec_out32(>sg_tbl[ctx->sg_num].len_flag,
(size & SG_ENTRY_LENGTH_MASK));
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 17392c9..f344908 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -11,6 +11,7 @@
#include "fsl_sec.h"
#include "jr.h"
#include "jobdesc.h"
+#include "desc_constr.h"
#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
@@ -154,19 +155,35 @@ static int jr_hw_reset(void)
/* -1 --- error, can't enqueue -- no space available */
static int jr_enqueue(uint32_t *desc_addr,
- void (*callback)(uint32_t desc, uint32_t status, void *arg),
+ void (*callback)(uint32_t status, void *arg),
void *arg)
{
struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
int head = jr.head;
- dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
+ uint32_t desc_word;
+ int length = desc_len(desc_addr);
+ int i;
+#ifdef CONFIG_PHYS_64BIT
+ uint32_t *addr_hi, *addr_lo;
+#endif
+
+ /* The descriptor must be submitted to SEC block as per endianness
+* of the SEC Block.
+* So, if the endianness of Core and SEC block is different, each word
+* of the descriptor will be byte-swapped.
+*/
+ for (i = 0; i < length; i++) {
+ desc_word = desc_addr[i];
+ sec_out32((uint32_t
[U-Boot] [PATCH] SECURE_BOOT: Correct reading of ITS bit
The ITS bit was being read incorrectly beacause of operator precedence. The same ahs been corrected. Signed-off-by: Lawish Deshmukh <lawish.deshm...@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com> --- board/freescale/common/fsl_validate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 5283648..b528fb7 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -246,7 +246,7 @@ static void fsl_secboot_image_verification_failure(void) struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); u32 sts = sec_mon_in32(_mon_regs->hp_stat); - u32 its = sfp_in32(_regs->ospr) & ITS_MASK >> ITS_BIT; + u32 its = (sfp_in32(_regs->ospr) & ITS_MASK) >> ITS_BIT; /* * Read the SEC_MON status register -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3][v3] Data types defined for 64 bit physical address
Data types and I/O functions have been defined for
64 bit physical addresses in arm.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v3:
Corrected the definition of virt_to_phys() and definition of phys_addr_t.
arch/arm/include/asm/io.h| 4 ++--
arch/arm/include/asm/types.h | 10 +++---
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index bfbe0a0..75773bd 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -46,7 +46,7 @@ static inline void sync(void)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
- return (void *)paddr;
+ return (void *)((unsigned long)paddr);
}
/*
@@ -59,7 +59,7 @@ static inline void unmap_physmem(void *vaddr, unsigned long
flags)
static inline phys_addr_t virt_to_phys(void * vaddr)
{
- return (phys_addr_t)(vaddr);
+ return (phys_addr_t)((unsigned long)vaddr);
}
/*
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
index ee77c41..388058e 100644
--- a/arch/arm/include/asm/types.h
+++ b/arch/arm/include/asm/types.h
@@ -45,12 +45,16 @@ typedef unsigned long long u64;
#define BITS_PER_LONG 32
#endif /* CONFIG_ARM64 */
-/* Dma addresses are 32-bits wide. */
-
+#ifdef CONFIG_PHYS_64BIT
+typedef unsigned long long dma_addr_t;
+typedef unsigned long long phys_addr_t;
+typedef unsigned long long phys_size_t;
+#else
+/* DMA addresses are 32-bits wide */
typedef u32 dma_addr_t;
-
typedef unsigned long phys_addr_t;
typedef unsigned long phys_size_t;
+#endif
#endif /* __KERNEL__ */
--
1.8.1.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3][v3] Pointers in ESBC header made 32 bit
For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v3:
Patch Rebased and removed compile time warnings
board/freescale/common/fsl_validate.c | 20 ++--
include/fsl_validate.h| 14 +++---
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 5283648..465676f 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -63,12 +63,12 @@ static u32 check_ie(struct fsl_secboot_img_priv *img)
* address
*/
#if defined(CONFIG_MPC85xx)
-int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
+int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(>scratchrw[0]);
u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE);
- ulong flash_addr, addr;
+ u32 flash_addr, addr;
int found = 0;
int i = 0;
@@ -76,7 +76,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
flash_addr = flash_info[i].start[0];
addr = flash_info[i].start[0] + csf_flash_offset;
if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) {
- debug("Barker found on addr %lx\n", addr);
+ debug("Barker found on addr %x\n", addr);
found = 1;
break;
}
@@ -94,7 +94,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
/* For platforms like LS1020, correct flash address is present in
* the header. So the function reqturns flash base address as 0
*/
-int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
+int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(>scratchrw[0]);
@@ -108,11 +108,11 @@ int get_csf_base_addr(ulong *csf_addr, ulong
*flash_base_addr)
}
#endif
-static int get_ie_info_addr(ulong *ie_addr)
+static int get_ie_info_addr(u32 *ie_addr)
{
struct fsl_secboot_img_hdr *hdr;
struct fsl_secboot_sg_table *sg_tbl;
- ulong flash_base_addr, csf_addr;
+ u32 flash_base_addr, csf_addr;
if (get_csf_base_addr(_addr, _base_addr))
return -1;
@@ -127,11 +127,11 @@ static int get_ie_info_addr(ulong *ie_addr)
*/
#if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET)
sg_tbl = (struct fsl_secboot_sg_table *)
-(((ulong)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+(((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
flash_base_addr);
#else
sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr +
-(ulong)hdr->psgtable);
+(u32)hdr->psgtable);
#endif
/* IE Key Table is the first entry in the SG Table */
@@ -142,7 +142,7 @@ static int get_ie_info_addr(ulong *ie_addr)
*ie_addr = sg_tbl->src_addr;
#endif
- debug("IE Table address is %lx\n", *ie_addr);
+ debug("IE Table address is %x\n", *ie_addr);
return 0;
}
@@ -549,7 +549,7 @@ static int read_validate_esbc_client_header(struct
fsl_secboot_img_priv *img)
if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN))
return ERROR_ESBC_CLIENT_HEADER_BARKER;
- sprintf(buf, "%p", hdr->pimg);
+ sprintf(buf, "%x", hdr->pimg);
setenv("img_addr", buf);
if (!hdr->img_size)
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index c460534..92dd98b 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -82,14 +82,14 @@ struct fsl_secboot_img_hdr {
u32 psign; /* signature offset */
u32 sign_len; /* length of the signature in bytes */
union {
- struct fsl_secboot_sg_table *psgtable; /* ptr to SG table */
- u8 *pimg; /* ptr to ESBC client image */
+ u32 psgtable; /* ptr to SG table */
+ u32 pimg; /* ptr to ESBC client image */
};
union {
u32 sg_entries; /* no of entries in SG table */
u32 img_size; /* ESBC client image size in bytes */
};
- ulong img_start;/* ESBC client entry point */
+ u32 img_start; /* ESBC client entry point */
u3
[U-Boot] [PATCH 3/3][v3] crypto/fsl: SEC driver cleanup for 64 bit and endianness
The SEC driver code has been cleaned up to work for 64 bit
physical addresses and systems where endianess of SEC block
is different from the Core.
Changes:
1. Descriptor created on Core is modified as per SEC block
endianness before the job is submitted.
2. The read/write of physical addresses to Job Rings will
be depend on endianness of SEC block as 32 bit low and
high part of the 64 bit address will vary.
3. The 32 bit low and high part of the 64 bit address in
descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
Changes in v3:sec_out_phys and sec_in_phys
The rwad/write for 64 bit address is done using 32 bit
aadr_lo and addr_hi. There is no need to define wrapper
functions sec_out_phys and sec_in_phys.
drivers/crypto/fsl/desc_constr.h | 26 +
drivers/crypto/fsl/fsl_hash.c| 8 ++--
drivers/crypto/fsl/jr.c | 83 ++--
drivers/crypto/fsl/jr.h | 7 ++--
include/fsl_sec.h| 6 +--
5 files changed, 106 insertions(+), 24 deletions(-)
diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h
index f9cae91..2559ccd 100644
--- a/drivers/crypto/fsl/desc_constr.h
+++ b/drivers/crypto/fsl/desc_constr.h
@@ -36,6 +36,23 @@
LDST_SRCDST_WORD_DECOCTRL | \
(LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
+#ifdef CONFIG_PHYS_64BIT
+union ptr_addr_t {
+ u64 m_whole;
+ struct {
+#ifdef CONFIG_SYS_FSL_SEC_LE
+ u32 low;
+ u32 high;
+#elif defined(CONFIG_SYS_FSL_SEC_BE)
+ u32 high;
+ u32 low;
+#else
+#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
+#endif
+ } m_halfs;
+};
+#endif
+
static inline int desc_len(u32 *desc)
{
return *desc & HDR_DESCLEN_MASK;
@@ -65,7 +82,16 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr)
{
dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
+#ifdef CONFIG_PHYS_64BIT
+ /* The Position of low and high part of 64 bit address
+* will depend on the endianness of CAAM Block */
+ union ptr_addr_t ptr_addr;
+ ptr_addr.m_halfs.high = (u32)(ptr >> 32);
+ ptr_addr.m_halfs.low = (u32)ptr;
+ *offset = ptr_addr.m_whole;
+#else
*offset = ptr;
+#endif
(*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ;
}
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
index c298404..887e88c 100644
--- a/drivers/crypto/fsl/fsl_hash.c
+++ b/drivers/crypto/fsl/fsl_hash.c
@@ -84,7 +84,7 @@ static int caam_hash_update(void *hash_ctx, const void *buf,
enum caam_hash_algos caam_algo)
{
uint32_t final = 0;
- dma_addr_t addr = virt_to_phys((void *)buf);
+ phys_addr_t addr = virt_to_phys((void *)buf);
struct sha_ctx *ctx = hash_ctx;
if (ctx->sg_num >= MAX_SG_32) {
@@ -93,11 +93,11 @@ static int caam_hash_update(void *hash_ctx, const void *buf,
}
#ifdef CONFIG_PHYS_64BIT
- ctx->sg_tbl[ctx->sg_num].addr_hi = addr >> 32;
+ sec_out32(>sg_tbl[ctx->sg_num].addr_hi, (uint32_t)(addr >> 32));
#else
- ctx->sg_tbl[ctx->sg_num].addr_hi = 0x0;
+ sec_out32(>sg_tbl[ctx->sg_num].addr_hi, 0x0);
#endif
- ctx->sg_tbl[ctx->sg_num].addr_lo = addr;
+ sec_out32(>sg_tbl[ctx->sg_num].addr_lo, (uint32_t)addr);
sec_out32(>sg_tbl[ctx->sg_num].len_flag,
(size & SG_ENTRY_LENGTH_MASK));
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 17392c9..c88c727 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -11,6 +11,7 @@
#include "fsl_sec.h"
#include "jr.h"
#include "jobdesc.h"
+#include "desc_constr.h"
#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
@@ -154,19 +155,35 @@ static int jr_hw_reset(void)
/* -1 --- error, can't enqueue -- no space available */
static int jr_enqueue(uint32_t *desc_addr,
- void (*callback)(uint32_t desc, uint32_t status, void *arg),
+ void (*callback)(uint32_t status, void *arg),
void *arg)
{
struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
int head = jr.head;
- dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
+ uint32_t desc_word;
+ int length = desc_len(desc_addr);
+ int i;
+#ifdef CONFIG_PHYS_64BIT
+ uint32_t *addr_hi, *addr_lo;
+#endif
+
+ /* The descriptor must be submitted to SEC block as per endianness
+* of the SEC Block.
+* So, if the endianness of Core and SEC block is different, each word
+* of the descriptor will be byte-swapped.
+
[U-Boot] [PATCH 1/3][v2] Pointers in ESBC header made 32 bit
For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v2:
Compile time warning removed when printing Header Address.
board/freescale/common/fsl_validate.c | 20 ++--
include/fsl_validate.h| 14 +++---
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 5283648..465676f 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -63,12 +63,12 @@ static u32 check_ie(struct fsl_secboot_img_priv *img)
* address
*/
#if defined(CONFIG_MPC85xx)
-int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
+int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(gur-scratchrw[0]);
u32 csf_flash_offset = csf_hdr_addr ~(CONFIG_SYS_PBI_FLASH_BASE);
- ulong flash_addr, addr;
+ u32 flash_addr, addr;
int found = 0;
int i = 0;
@@ -76,7 +76,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
flash_addr = flash_info[i].start[0];
addr = flash_info[i].start[0] + csf_flash_offset;
if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) {
- debug(Barker found on addr %lx\n, addr);
+ debug(Barker found on addr %x\n, addr);
found = 1;
break;
}
@@ -94,7 +94,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
/* For platforms like LS1020, correct flash address is present in
* the header. So the function reqturns flash base address as 0
*/
-int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
+int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(gur-scratchrw[0]);
@@ -108,11 +108,11 @@ int get_csf_base_addr(ulong *csf_addr, ulong
*flash_base_addr)
}
#endif
-static int get_ie_info_addr(ulong *ie_addr)
+static int get_ie_info_addr(u32 *ie_addr)
{
struct fsl_secboot_img_hdr *hdr;
struct fsl_secboot_sg_table *sg_tbl;
- ulong flash_base_addr, csf_addr;
+ u32 flash_base_addr, csf_addr;
if (get_csf_base_addr(csf_addr, flash_base_addr))
return -1;
@@ -127,11 +127,11 @@ static int get_ie_info_addr(ulong *ie_addr)
*/
#if defined(CONFIG_FSL_TRUST_ARCH_v1) defined(CONFIG_FSL_CORENET)
sg_tbl = (struct fsl_secboot_sg_table *)
-(((ulong)hdr-psgtable ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+(((u32)hdr-psgtable ~(CONFIG_SYS_PBI_FLASH_BASE)) +
flash_base_addr);
#else
sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr +
-(ulong)hdr-psgtable);
+(u32)hdr-psgtable);
#endif
/* IE Key Table is the first entry in the SG Table */
@@ -142,7 +142,7 @@ static int get_ie_info_addr(ulong *ie_addr)
*ie_addr = sg_tbl-src_addr;
#endif
- debug(IE Table address is %lx\n, *ie_addr);
+ debug(IE Table address is %x\n, *ie_addr);
return 0;
}
@@ -549,7 +549,7 @@ static int read_validate_esbc_client_header(struct
fsl_secboot_img_priv *img)
if (memcmp(hdr-barker, barker_code, ESBC_BARKER_LEN))
return ERROR_ESBC_CLIENT_HEADER_BARKER;
- sprintf(buf, %p, hdr-pimg);
+ sprintf(buf, %x, hdr-pimg);
setenv(img_addr, buf);
if (!hdr-img_size)
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index c460534..92dd98b 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -82,14 +82,14 @@ struct fsl_secboot_img_hdr {
u32 psign; /* signature offset */
u32 sign_len; /* length of the signature in bytes */
union {
- struct fsl_secboot_sg_table *psgtable; /* ptr to SG table */
- u8 *pimg; /* ptr to ESBC client image */
+ u32 psgtable; /* ptr to SG table */
+ u32 pimg; /* ptr to ESBC client image */
};
union {
u32 sg_entries; /* no of entries in SG table */
u32 img_size; /* ESBC client image size in bytes */
};
- ulong img_start;/* ESBC client entry point */
+ u32 img_start; /* ESBC client entry point */
u32 sg_flag;/* Scatter gather flag */
u32 uid_flag;
u32 fsl_uid_0;
@@ -133,7 +133,7 @@ struct srk_table {
*/
struct
[U-Boot] [PATCH 2/3][v2] Data types defined for 64 bit physical address
Data types and I/O functions have been defined for 64 bit physical addresses in arm. Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com --- Changes in v2: There is no need for defining 64 bit I/O operations. If an IP needs to do 64 bit access, it will do it by defining 32 bit addr_hi and addr_lo. arch/arm/include/asm/types.h | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h index ee77c41..d87f955 100644 --- a/arch/arm/include/asm/types.h +++ b/arch/arm/include/asm/types.h @@ -45,12 +45,15 @@ typedef unsigned long long u64; #define BITS_PER_LONG 32 #endif /* CONFIG_ARM64 */ -/* Dma addresses are 32-bits wide. */ - +#ifdef CONFIG_PHYS_64BIT +typedef u64 dma_addr_t; +typedef u64 phys_addr_t; +typedef u64 phys_size_t; +#else typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; +typedef u32 phys_addr_t; +typedef u32 phys_size_t; +#endif #endif /* __KERNEL__ */ -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3][v2] crypto/fsl: SEC driver cleanup for 64 bit and endianness
The SEC driver code has been cleaned up to work for 64 bit
physical addresses and systems where endianess of SEC block
is different from the Core.
Changes:
1. Descriptor created on Core is modified as per SEC block
endianness before the job is submitted.
2. The read/write of physical addresses to Job Rings are done
using I/O functions defined for SEC which will take care of
the endianness.
3. The 32 bit low and high part of the 64 bit address in
descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v2:
sec_out_phys and sec_in_phys has been defined in fsl_sec.h
to do two 32 bit write or read opeartions.
The low and high part of the 32 bit address will depend on
endianness of CAAM Block.
drivers/crypto/fsl/desc_constr.h | 24
drivers/crypto/fsl/jr.c | 32 ++--
drivers/crypto/fsl/jr.h | 3 +--
include/fsl_sec.h| 28
4 files changed, 75 insertions(+), 12 deletions(-)
diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h
index f9cae91..ac4a933 100644
--- a/drivers/crypto/fsl/desc_constr.h
+++ b/drivers/crypto/fsl/desc_constr.h
@@ -36,6 +36,21 @@
LDST_SRCDST_WORD_DECOCTRL | \
(LDOFF_ENABLE_AUTO_NFIFO LDST_OFFSET_SHIFT))
+#ifdef CONFIG_PHYS_64BIT
+union ptr_addr_t {
+ u64 m_whole;
+ struct {
+#ifdef CONFIG_SYS_FSL_SEC_LE
+ u32 low;
+ u32 high;
+#else
+ u32 high;
+ u32 low;
+#endif
+ } m_halfs;
+};
+#endif
+
static inline int desc_len(u32 *desc)
{
return *desc HDR_DESCLEN_MASK;
@@ -65,7 +80,16 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr)
{
dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
+#ifdef CONFIG_PHYS_64BIT
+ /* The Position of low and high part of 64 bit address
+* will depend on the endianness of CAAM Block */
+ union ptr_addr_t ptr_addr;
+ ptr_addr.m_halfs.high = (u32)(ptr 32);
+ ptr_addr.m_halfs.low = (u32)ptr;
+ *offset = ptr_addr.m_whole;
+#else
*offset = ptr;
+#endif
(*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ;
}
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 17392c9..07b97e8 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -11,6 +11,7 @@
#include fsl_sec.h
#include jr.h
#include jobdesc.h
+#include desc_constr.h
#define CIRC_CNT(head, tail, size) (((head) - (tail)) (size - 1))
#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
@@ -154,11 +155,25 @@ static int jr_hw_reset(void)
/* -1 --- error, can't enqueue -- no space available */
static int jr_enqueue(uint32_t *desc_addr,
- void (*callback)(uint32_t desc, uint32_t status, void *arg),
+ void (*callback)(uint32_t status, void *arg),
void *arg)
{
struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
int head = jr.head;
+ uint32_t desc_word;
+ int length = desc_len(desc_addr);
+ int i;
+
+ /* The descriptor must be submitted to SEC block as per endianness
+* of the SEC Block.
+* So, if the endianness of Core and SEC block is different, each word
+* of the descriptor will be byte-swapped.
+*/
+ for (i = 0; i length; i++) {
+ desc_word = desc_addr[i];
+ sec_out32((uint32_t *)desc_addr[i], desc_word);
+ }
+
dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
if (sec_in32(regs-irsa) == 0 ||
@@ -166,7 +181,6 @@ static int jr_enqueue(uint32_t *desc_addr,
return -1;
jr.info[head].desc_phys_addr = desc_phys_addr;
- jr.info[head].desc_addr = (uint32_t)desc_addr;
jr.info[head].callback = (void *)callback;
jr.info[head].arg = arg;
jr.info[head].op_done = 0;
@@ -177,7 +191,7 @@ static int jr_enqueue(uint32_t *desc_addr,
ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
- jr.input_ring[head] = desc_phys_addr;
+ sec_out_phys(jr.input_ring[head], desc_phys_addr);
start = (unsigned long)jr.input_ring[head] ~(ARCH_DMA_MINALIGN - 1);
end = ALIGN(start + sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
@@ -195,7 +209,7 @@ static int jr_dequeue(void)
int head = jr.head;
int tail = jr.tail;
int idx, i, found;
- void (*callback)(uint32_t desc, uint32_t status, void *arg);
+ void (*callback)(uint32_t status, void *arg);
void *arg = NULL;
while (sec_in32(regs-orsf) CIRC_CNT(jr.head, jr.tail, jr.size)) {
@@ -208,14 +222,12 @@ static int jr_dequeue(void)
found = 0;
- dma_addr_t op_desc = jr.output_ring
[U-Boot] [PATCH 1/3][v2] Pointers in ESBC header made 32 bit
For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v2:
Compile time warning removed when printing Header Address.
board/freescale/common/fsl_validate.c | 20 ++--
include/fsl_validate.h| 14 +++---
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 5283648..465676f 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -63,12 +63,12 @@ static u32 check_ie(struct fsl_secboot_img_priv *img)
* address
*/
#if defined(CONFIG_MPC85xx)
-int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
+int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(gur-scratchrw[0]);
u32 csf_flash_offset = csf_hdr_addr ~(CONFIG_SYS_PBI_FLASH_BASE);
- ulong flash_addr, addr;
+ u32 flash_addr, addr;
int found = 0;
int i = 0;
@@ -76,7 +76,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
flash_addr = flash_info[i].start[0];
addr = flash_info[i].start[0] + csf_flash_offset;
if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) {
- debug(Barker found on addr %lx\n, addr);
+ debug(Barker found on addr %x\n, addr);
found = 1;
break;
}
@@ -94,7 +94,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
/* For platforms like LS1020, correct flash address is present in
* the header. So the function reqturns flash base address as 0
*/
-int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
+int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(gur-scratchrw[0]);
@@ -108,11 +108,11 @@ int get_csf_base_addr(ulong *csf_addr, ulong
*flash_base_addr)
}
#endif
-static int get_ie_info_addr(ulong *ie_addr)
+static int get_ie_info_addr(u32 *ie_addr)
{
struct fsl_secboot_img_hdr *hdr;
struct fsl_secboot_sg_table *sg_tbl;
- ulong flash_base_addr, csf_addr;
+ u32 flash_base_addr, csf_addr;
if (get_csf_base_addr(csf_addr, flash_base_addr))
return -1;
@@ -127,11 +127,11 @@ static int get_ie_info_addr(ulong *ie_addr)
*/
#if defined(CONFIG_FSL_TRUST_ARCH_v1) defined(CONFIG_FSL_CORENET)
sg_tbl = (struct fsl_secboot_sg_table *)
-(((ulong)hdr-psgtable ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+(((u32)hdr-psgtable ~(CONFIG_SYS_PBI_FLASH_BASE)) +
flash_base_addr);
#else
sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr +
-(ulong)hdr-psgtable);
+(u32)hdr-psgtable);
#endif
/* IE Key Table is the first entry in the SG Table */
@@ -142,7 +142,7 @@ static int get_ie_info_addr(ulong *ie_addr)
*ie_addr = sg_tbl-src_addr;
#endif
- debug(IE Table address is %lx\n, *ie_addr);
+ debug(IE Table address is %x\n, *ie_addr);
return 0;
}
@@ -549,7 +549,7 @@ static int read_validate_esbc_client_header(struct
fsl_secboot_img_priv *img)
if (memcmp(hdr-barker, barker_code, ESBC_BARKER_LEN))
return ERROR_ESBC_CLIENT_HEADER_BARKER;
- sprintf(buf, %p, hdr-pimg);
+ sprintf(buf, %x, hdr-pimg);
setenv(img_addr, buf);
if (!hdr-img_size)
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index c460534..92dd98b 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -82,14 +82,14 @@ struct fsl_secboot_img_hdr {
u32 psign; /* signature offset */
u32 sign_len; /* length of the signature in bytes */
union {
- struct fsl_secboot_sg_table *psgtable; /* ptr to SG table */
- u8 *pimg; /* ptr to ESBC client image */
+ u32 psgtable; /* ptr to SG table */
+ u32 pimg; /* ptr to ESBC client image */
};
union {
u32 sg_entries; /* no of entries in SG table */
u32 img_size; /* ESBC client image size in bytes */
};
- ulong img_start;/* ESBC client entry point */
+ u32 img_start; /* ESBC client entry point */
u32 sg_flag;/* Scatter gather flag */
u32 uid_flag;
u32 fsl_uid_0;
@@ -133,7 +133,7 @@ struct srk_table {
*/
struct
[U-Boot] [PATCH 3/4][v8] powerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAM
For running Chain of Trust when doing Secure Boot from NAND, the Bootscript header and bootscript must be copied from NAND to RAM(DDR). The addresses and commands for the same have been defined. Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com --- Changes in v8: New Patchset Created arch/powerpc/include/asm/fsl_secure_boot.h | 14 ++ include/config_fsl_secboot.h | 29 - include/configs/corenet_ds.h | 1 + 3 files changed, 43 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index cc33466..6e55716 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -73,6 +73,18 @@ #endif #ifndef CONFIG_FIT_SIGNATURE +/* If Boot Script is not on NOR and is required to be copied on RAM */ +#ifdef CONFIG_BOOTSCRIPT_COPY_RAM +#define CONFIG_BS_HDR_ADDR_RAM 0x0001 +#define CONFIG_BS_HDR_ADDR_FLASH 0x0080 +#define CONFIG_BS_HDR_SIZE 0x2000 +#define CONFIG_BS_ADDR_RAM 0x00012000 +#define CONFIG_BS_ADDR_FLASH 0x00802000 +#define CONFIG_BS_SIZE 0x1000 + +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM +#else + /* The bootscript header address is different for B4860 because the NOR * mapping is different on B4 due to reduced NOR size. */ @@ -88,6 +100,8 @@ #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee02 #endif +#endif + #include config_fsl_secboot.h #endif diff --git a/include/config_fsl_secboot.h b/include/config_fsl_secboot.h index 050b157..fc6788a 100644 --- a/include/config_fsl_secboot.h +++ b/include/config_fsl_secboot.h @@ -55,6 +55,22 @@ /* For secure boot flow, default environment used will be used */ #if defined(CONFIG_SYS_RAMBOOT) +#ifdef CONFIG_BOOTSCRIPT_COPY_RAM +#define CONFIG_BS_COPY_ENV \ + setenv bs_hdr_ram __stringify(CONFIG_BS_HDR_ADDR_RAM); \ + setenv bs_hdr_flash __stringify(CONFIG_BS_HDR_ADDR_FLASH); \ + setenv bs_hdr_size __stringify(CONFIG_BS_HDR_SIZE); \ + setenv bs_ram __stringify(CONFIG_BS_ADDR_RAM); \ + setenv bs_flash __stringify(CONFIG_BS_ADDR_FLASH); \ + setenv bs_size __stringify(CONFIG_BS_SIZE); + +#if defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_BS_COPY_CMD \ + nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ; \ + nand read $bs_ram $bs_flash $bs_size ; +#endif /* CONFIG_RAMBOOT_NAND */ +#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ + #if defined(CONFIG_RAMBOOT_SPIFLASH) #undef CONFIG_ENV_IS_IN_SPI_FLASH #elif defined(CONFIG_RAMBOOT_NAND) @@ -68,6 +84,17 @@ #define CONFIG_ENV_IS_NOWHERE +#ifndef CONFIG_BS_COPY_ENV +#define CONFIG_BS_COPY_ENV +#endif + +#ifndef CONFIG_BS_COPY_CMD +#define CONFIG_BS_COPY_CMD +#endif + +#define CONFIG_SECBOOT_CMD CONFIG_BS_COPY_ENV \ + CONFIG_BS_COPY_CMD \ + CONFIG_SECBOOT /* * We don't want boot delay for secure boot flow * before autoboot starts @@ -75,7 +102,7 @@ #undef CONFIG_BOOTDELAY #define CONFIG_BOOTDELAY 0 #undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND CONFIG_SECBOOT +#define CONFIG_BOOTCOMMAND CONFIG_SECBOOT_CMD /* * CONFIG_ZERO_BOOTDELAY_CHECK should not be defined for diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 7c8b73d..9aaa0f5 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -22,6 +22,7 @@ #ifdef CONFIG_NAND #define CONFIG_RAMBOOT_NAND #endif +#define CONFIG_BOOTSCRIPT_COPY_RAM #else #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS0xfffc -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/4][v8] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
Secure Boot Target is added for NAND for P3041.
Changes:
In PowerPC, the core begins execution from address 0xFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFF.
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on SRAM configured
at address 0xBFF0.
In the U-Boot code, TLB entries are created to map the virtual address
0xFFF0 to physical address 0xBFF0 of CPC configured as SRAM.
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v8:
New Patchset Created
Makefile | 4
arch/powerpc/cpu/mpc85xx/start.S | 11 +++
arch/powerpc/include/asm/fsl_secure_boot.h | 5 +
board/freescale/common/p_corenet/tlb.c | 15 +++
board/freescale/corenet_ds/MAINTAINERS | 5 +
configs/P3041DS_NAND_SECURE_BOOT_defconfig | 4
include/configs/corenet_ds.h | 8
7 files changed, 52 insertions(+)
create mode 100644 configs/P3041DS_NAND_SECURE_BOOT_defconfig
diff --git a/Makefile b/Makefile
index 394ed09..605003e 100644
--- a/Makefile
+++ b/Makefile
@@ -736,8 +736,12 @@ ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
ifeq ($(CONFIG_SPL_FSL_PBL),y)
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
else
+ifneq ($(CONFIG_SECURE_BOOT), y)
+# For Secure Boot The Image needs to be signed and Header must also
+# be included. So The image has to be built explicitly
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
endif
+endif
ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index e61d8e0..a70fb71 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1052,6 +1052,17 @@ create_init_ram_area:
CONFIG_SYS_MONITOR_BASE 0xfff0, MAS2_I|MAS2_G, \
CONFIG_SYS_PBI_FLASH_WINDOW 0xfff0,
MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
+
+#elif defined(CONFIG_RAMBOOT_PBL) defined(CONFIG_SECURE_BOOT)
+ /* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE
+* to L3 Address configured by PBL for ISBC code
+ */
+ create_tlb1_entry 15, \
+ 1, BOOKE_PAGESZ_1M, \
+ CONFIG_SYS_MONITOR_BASE 0xfff0, MAS2_I|MAS2_G, \
+ CONFIG_SYS_INIT_L3_ADDR 0xfff0, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
+
#else
/*
* create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE
space, the main
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h
b/arch/powerpc/include/asm/fsl_secure_boot.h
index 8f794ef..cc33466 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -46,6 +46,11 @@
#define CONFIG_SYS_INIT_L3_ADDR0xbff0
#endif
+#if defined(CONFIG_RAMBOOT_PBL)
+#undef CONFIG_SYS_INIT_L3_ADDR
+#define CONFIG_SYS_INIT_L3_ADDR0xbff0
+#endif
+
#if defined(CONFIG_C29XPCIE)
#define CONFIG_KEY_REVOCATION
#endif
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index 8148e46..56e4f63 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -43,6 +43,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 */
/* *I*** - Covers boot page */
#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR)
+
+#if !defined(CONFIG_SECURE_BOOT)
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
* SRAM is at 0xfff0, it covered the 0xf000.
@@ -50,6 +52,19 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ /*
+* *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot
+* the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR,
+* and virtual address is CONFIG_SYS_MONITOR_BASE
+*/
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE 0xfff0,
+ CONFIG_SYS_INIT_L3_ADDR 0xfff0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#endif
+
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
diff --git a/board/freescale/corenet_ds/MAINTAINERS
b/board/freescale/corenet_ds/MAINTAINERS
index 745847c..6855446 100644
--- a/board/freescale/corenet_ds/MAINTAINERS
+++ b/board/freescale/corenet_ds/MAINTAINERS
@@ -28,3 +28,8 @@ F:configs
[U-Boot] [PATCH 2/4][v8] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040
Secure Boot Target is added for NAND for P5020 and P5040. The Secure boot target has already been added for P3041 by enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM. The targets for P5020 and P5040 are added in the same manner. Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com --- Changes in v8: New Patchset Created board/freescale/corenet_ds/MAINTAINERS | 2 ++ configs/P5020DS_NAND_SECURE_BOOT_defconfig | 4 configs/P5040DS_NAND_SECURE_BOOT_defconfig | 4 3 files changed, 10 insertions(+) create mode 100644 configs/P5020DS_NAND_SECURE_BOOT_defconfig create mode 100644 configs/P5040DS_NAND_SECURE_BOOT_defconfig diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS index 6855446..73b0553 100644 --- a/board/freescale/corenet_ds/MAINTAINERS +++ b/board/freescale/corenet_ds/MAINTAINERS @@ -33,3 +33,5 @@ CORENET_DS_SECURE_BOOT BOARD M: Aneesh Bansal aneesh.ban...@freescale.com S: Maintained F: configs/P3041DS_NAND_SECURE_BOOT_defconfig +F: configs/P5020DS_NAND_SECURE_BOOT_defconfig +F: configs/P5040DS_NAND_SECURE_BOOT_defconfig diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 000..5edfe45 --- /dev/null +++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS=RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF4 +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5020DS=y diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 000..f33d236 --- /dev/null +++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS=RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF4 +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5040DS=y -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] Data types defined for 64 bit physical address
Data types and I/O functions have been defined for
64 bit physical addresses in arm and powerpc
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
arch/arm/include/asm/io.h | 4 +++-
arch/arm/include/asm/types.h | 13 -
arch/powerpc/include/asm/io.h | 13 +
3 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index bfbe0a0..09d192d 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -59,7 +59,7 @@ static inline void unmap_physmem(void *vaddr, unsigned long
flags)
static inline phys_addr_t virt_to_phys(void * vaddr)
{
- return (phys_addr_t)(vaddr);
+ return (phys_addr_t)((unsigned long)vaddr);
}
/*
@@ -183,9 +183,11 @@ static inline void __raw_readsl(unsigned long addr, void
*data, int longlen)
#define in_le32(a) in_arch(l,le32,a)
#define in_le16(a) in_arch(w,le16,a)
+#define out_be64(a, v) out_arch(q, be64, a, v)
#define out_be32(a,v) out_arch(l,be32,a,v)
#define out_be16(a,v) out_arch(w,be16,a,v)
+#define in_be64(a) in_arch(q, be64, a)
#define in_be32(a) in_arch(l,be32,a)
#define in_be16(a) in_arch(w,be16,a)
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
index ee77c41..d87f955 100644
--- a/arch/arm/include/asm/types.h
+++ b/arch/arm/include/asm/types.h
@@ -45,12 +45,15 @@ typedef unsigned long long u64;
#define BITS_PER_LONG 32
#endif /* CONFIG_ARM64 */
-/* Dma addresses are 32-bits wide. */
-
+#ifdef CONFIG_PHYS_64BIT
+typedef u64 dma_addr_t;
+typedef u64 phys_addr_t;
+typedef u64 phys_size_t;
+#else
typedef u32 dma_addr_t;
-
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
+typedef u32 phys_addr_t;
+typedef u32 phys_size_t;
+#endif
#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index a5257e9..8c6f47e 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -246,6 +246,19 @@ extern inline void out_be32(volatile unsigned __iomem
*addr, u32 val)
__asm__ __volatile__(sync; stw%U0%X0 %1,%0 : =m (*addr) : r
(val));
}
+extern inline u64 in_be64(const u64 *addr)
+{
+ return ((u64)in_be32((u32 *)addr) 32) |
+ (in_be32((u32 *)addr + 1));
+}
+
+extern inline void out_be64(u64 *addr, u64 val)
+{
+ out_be32((u32 *)addr, (u32)(val 32));
+ out_be32((u32 *)addr + 1, (u32)val);
+}
+
+
/* Clear and set bits in one shot. These macros can be used to clear and
* set multiple bits in a register using a single call. These macros can
* also be used to set a multiple-bit bit pattern using a mask, by
--
1.8.1.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] Pointers in ESBC header made 32 bit
For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
board/freescale/common/fsl_validate.c | 18 +-
include/fsl_validate.h| 14 +++---
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 5283648..be35828 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -63,12 +63,12 @@ static u32 check_ie(struct fsl_secboot_img_priv *img)
* address
*/
#if defined(CONFIG_MPC85xx)
-int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
+int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(gur-scratchrw[0]);
u32 csf_flash_offset = csf_hdr_addr ~(CONFIG_SYS_PBI_FLASH_BASE);
- ulong flash_addr, addr;
+ u32 flash_addr, addr;
int found = 0;
int i = 0;
@@ -94,7 +94,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
/* For platforms like LS1020, correct flash address is present in
* the header. So the function reqturns flash base address as 0
*/
-int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
+int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(gur-scratchrw[0]);
@@ -108,11 +108,11 @@ int get_csf_base_addr(ulong *csf_addr, ulong
*flash_base_addr)
}
#endif
-static int get_ie_info_addr(ulong *ie_addr)
+static int get_ie_info_addr(u32 *ie_addr)
{
struct fsl_secboot_img_hdr *hdr;
struct fsl_secboot_sg_table *sg_tbl;
- ulong flash_base_addr, csf_addr;
+ u32 flash_base_addr, csf_addr;
if (get_csf_base_addr(csf_addr, flash_base_addr))
return -1;
@@ -127,11 +127,11 @@ static int get_ie_info_addr(ulong *ie_addr)
*/
#if defined(CONFIG_FSL_TRUST_ARCH_v1) defined(CONFIG_FSL_CORENET)
sg_tbl = (struct fsl_secboot_sg_table *)
-(((ulong)hdr-psgtable ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+(((u32)hdr-psgtable ~(CONFIG_SYS_PBI_FLASH_BASE)) +
flash_base_addr);
#else
sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr +
-(ulong)hdr-psgtable);
+(u32)hdr-psgtable);
#endif
/* IE Key Table is the first entry in the SG Table */
@@ -142,7 +142,7 @@ static int get_ie_info_addr(ulong *ie_addr)
*ie_addr = sg_tbl-src_addr;
#endif
- debug(IE Table address is %lx\n, *ie_addr);
+ debug(IE Table address is %x\n, *ie_addr);
return 0;
}
@@ -549,7 +549,7 @@ static int read_validate_esbc_client_header(struct
fsl_secboot_img_priv *img)
if (memcmp(hdr-barker, barker_code, ESBC_BARKER_LEN))
return ERROR_ESBC_CLIENT_HEADER_BARKER;
- sprintf(buf, %p, hdr-pimg);
+ sprintf(buf, %x, hdr-pimg);
setenv(img_addr, buf);
if (!hdr-img_size)
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index c460534..92dd98b 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -82,14 +82,14 @@ struct fsl_secboot_img_hdr {
u32 psign; /* signature offset */
u32 sign_len; /* length of the signature in bytes */
union {
- struct fsl_secboot_sg_table *psgtable; /* ptr to SG table */
- u8 *pimg; /* ptr to ESBC client image */
+ u32 psgtable; /* ptr to SG table */
+ u32 pimg; /* ptr to ESBC client image */
};
union {
u32 sg_entries; /* no of entries in SG table */
u32 img_size; /* ESBC client image size in bytes */
};
- ulong img_start;/* ESBC client entry point */
+ u32 img_start; /* ESBC client entry point */
u32 sg_flag;/* Scatter gather flag */
u32 uid_flag;
u32 fsl_uid_0;
@@ -133,7 +133,7 @@ struct srk_table {
*/
struct fsl_secboot_sg_table {
u32 len;/* length of the segment in bytes */
- ulong src_addr; /* ptr to the data segment */
+ u32 src_addr; /* ptr to the data segment */
};
#else
/*
@@ -146,8 +146,8 @@ struct fsl_secboot_sg_table {
struct fsl_secboot_sg_table {
u32 len;
u32 trgt_id;
- ulong src_addr;
- ulong dst_addr;
+ u32 src_addr;
+ u32 dst_addr;
};
#endif
@@ -162,7 +162,7 @@ struct fsl_secboot_sg_table {
*/
struct fsl_secboot_img_priv {
uint32_t
[U-Boot] [PATCH 1/3] Pointers in ESBC header made 32 bit
For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
board/freescale/common/fsl_validate.c | 18 +-
include/fsl_validate.h| 14 +++---
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 5283648..be35828 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -63,12 +63,12 @@ static u32 check_ie(struct fsl_secboot_img_priv *img)
* address
*/
#if defined(CONFIG_MPC85xx)
-int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
+int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(gur-scratchrw[0]);
u32 csf_flash_offset = csf_hdr_addr ~(CONFIG_SYS_PBI_FLASH_BASE);
- ulong flash_addr, addr;
+ u32 flash_addr, addr;
int found = 0;
int i = 0;
@@ -94,7 +94,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
/* For platforms like LS1020, correct flash address is present in
* the header. So the function reqturns flash base address as 0
*/
-int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
+int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(gur-scratchrw[0]);
@@ -108,11 +108,11 @@ int get_csf_base_addr(ulong *csf_addr, ulong
*flash_base_addr)
}
#endif
-static int get_ie_info_addr(ulong *ie_addr)
+static int get_ie_info_addr(u32 *ie_addr)
{
struct fsl_secboot_img_hdr *hdr;
struct fsl_secboot_sg_table *sg_tbl;
- ulong flash_base_addr, csf_addr;
+ u32 flash_base_addr, csf_addr;
if (get_csf_base_addr(csf_addr, flash_base_addr))
return -1;
@@ -127,11 +127,11 @@ static int get_ie_info_addr(ulong *ie_addr)
*/
#if defined(CONFIG_FSL_TRUST_ARCH_v1) defined(CONFIG_FSL_CORENET)
sg_tbl = (struct fsl_secboot_sg_table *)
-(((ulong)hdr-psgtable ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+(((u32)hdr-psgtable ~(CONFIG_SYS_PBI_FLASH_BASE)) +
flash_base_addr);
#else
sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr +
-(ulong)hdr-psgtable);
+(u32)hdr-psgtable);
#endif
/* IE Key Table is the first entry in the SG Table */
@@ -142,7 +142,7 @@ static int get_ie_info_addr(ulong *ie_addr)
*ie_addr = sg_tbl-src_addr;
#endif
- debug(IE Table address is %lx\n, *ie_addr);
+ debug(IE Table address is %x\n, *ie_addr);
return 0;
}
@@ -549,7 +549,7 @@ static int read_validate_esbc_client_header(struct
fsl_secboot_img_priv *img)
if (memcmp(hdr-barker, barker_code, ESBC_BARKER_LEN))
return ERROR_ESBC_CLIENT_HEADER_BARKER;
- sprintf(buf, %p, hdr-pimg);
+ sprintf(buf, %x, hdr-pimg);
setenv(img_addr, buf);
if (!hdr-img_size)
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index c460534..92dd98b 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -82,14 +82,14 @@ struct fsl_secboot_img_hdr {
u32 psign; /* signature offset */
u32 sign_len; /* length of the signature in bytes */
union {
- struct fsl_secboot_sg_table *psgtable; /* ptr to SG table */
- u8 *pimg; /* ptr to ESBC client image */
+ u32 psgtable; /* ptr to SG table */
+ u32 pimg; /* ptr to ESBC client image */
};
union {
u32 sg_entries; /* no of entries in SG table */
u32 img_size; /* ESBC client image size in bytes */
};
- ulong img_start;/* ESBC client entry point */
+ u32 img_start; /* ESBC client entry point */
u32 sg_flag;/* Scatter gather flag */
u32 uid_flag;
u32 fsl_uid_0;
@@ -133,7 +133,7 @@ struct srk_table {
*/
struct fsl_secboot_sg_table {
u32 len;/* length of the segment in bytes */
- ulong src_addr; /* ptr to the data segment */
+ u32 src_addr; /* ptr to the data segment */
};
#else
/*
@@ -146,8 +146,8 @@ struct fsl_secboot_sg_table {
struct fsl_secboot_sg_table {
u32 len;
u32 trgt_id;
- ulong src_addr;
- ulong dst_addr;
+ u32 src_addr;
+ u32 dst_addr;
};
#endif
@@ -162,7 +162,7 @@ struct fsl_secboot_sg_table {
*/
struct fsl_secboot_img_priv {
uint32_t
[U-Boot] [PATCH 4/4][v8] SECURE_BOOT: Disable IE Key feature for RAMBOOT
ISBC Key Extension feature is not applicable for RAMBOOT as there is no way to retrieve the CSF Header and validated IE Key table from SRAM once CPC has been disabled. The feature is only applicable in case of NOR SECURE BOOT. Code Cleanup: The SECURE_BOOT specific defines have been moved from arch-ls102xa/config.h to arm/include/asm/fsl_secure_boot.h Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com --- Changes in v8: New Patch added in patchset arch/arm/include/asm/arch-ls102xa/config.h | 14 -- arch/arm/include/asm/fsl_secure_boot.h | 22 ++ arch/powerpc/include/asm/fsl_secure_boot.h | 6 -- 3 files changed, 26 insertions(+), 16 deletions(-) diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index c55cdef..bcaf7bf 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -103,20 +103,6 @@ #define CONFIG_SYS_FSL_SFP_VER_3_2 #define CONFIG_SYS_FSL_SFP_BE #define CONFIG_SYS_FSL_SRK_LE -#define CONFIG_KEY_REVOCATION -#define CONFIG_FSL_ISBC_KEY_EXT - -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_ESBC_VALIDATE -#define CONFIG_FSL_SEC_MON -#define CONFIG_SHA_PROG_HW_ACCEL -#define CONFIG_DM -#define CONFIG_RSA -#define CONFIG_RSA_FREESCALE_EXP -#ifndef CONFIG_FSL_CAAM -#define CONFIG_FSL_CAAM -#endif -#endif #define DCU_LAYER_MAX_NUM 16 diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index f097c81..f2d4c3c 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -8,6 +8,28 @@ #define __FSL_SECURE_BOOT_H #ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_FSL_SEC_MON +#define CONFIG_SHA_PROG_HW_ACCEL +#define CONFIG_DM +#define CONFIG_RSA +#define CONFIG_RSA_FREESCALE_EXP +#ifndef CONFIG_FSL_CAAM +#define CONFIG_FSL_CAAM +#endif + +#define CONFIG_KEY_REVOCATION +#ifndef CONFIG_SYS_RAMBOOT +/* The key used for verification of next level images + * is picked up from an Extension Table which has + * been verified by the ISBC (Internal Secure boot Code) + * in boot ROM of the SoC. + * The feature is only applicable in case of NOR boot and is + * not applicable in case of RAMBOOT (NAND, SD, SPI). + */ +#define CONFIG_FSL_ISBC_KEY_EXT +#endif + #ifndef CONFIG_FIT_SIGNATURE #define CONFIG_EXTRA_ENV \ diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 6e55716..0985865 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -63,11 +63,13 @@ #define CONFIG_FSL_TRUST_ARCH_v1 #endif -#if defined(CONFIG_FSL_CORENET) +#if defined(CONFIG_FSL_CORENET) !defined(CONFIG_SYS_RAMBOOT) /* The key used for verification of next level images * is picked up from an Extension Table which has * been verified by the ISBC (Internal Secure boot Code) - * in boot ROM of the SoC + * in boot ROM of the SoC. + * The feature is only applicable in case of NOR boot and is + * not applicable in case of RAMBOOT (NAND, SD, SPI). */ #define CONFIG_FSL_ISBC_KEY_EXT #endif -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] crypto/fsl: SEC driver cleanup for 64 bit and endianness
The SEC driver code has been cleaned up to work for 64 bit
physical addresses and systems where endianess of SEC block
is different from the Core.
Changes:
1. Descriptor created on Core is modified as per SEC block
endianness before the job is submitted.
2. The read/write to Job Rings are done using I/O functions
defined for SEC which will take care of the endianness.
3. The 32 bit low and high part of the 64 bit address in
descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
drivers/crypto/fsl/desc_constr.h | 24
drivers/crypto/fsl/fsl_hash.c| 7 +--
drivers/crypto/fsl/jr.c | 40 ++--
drivers/crypto/fsl/jr.h | 19 +--
include/fsl_sec.h| 24 ++--
5 files changed, 74 insertions(+), 40 deletions(-)
diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h
index f9cae91..ac4a933 100644
--- a/drivers/crypto/fsl/desc_constr.h
+++ b/drivers/crypto/fsl/desc_constr.h
@@ -36,6 +36,21 @@
LDST_SRCDST_WORD_DECOCTRL | \
(LDOFF_ENABLE_AUTO_NFIFO LDST_OFFSET_SHIFT))
+#ifdef CONFIG_PHYS_64BIT
+union ptr_addr_t {
+ u64 m_whole;
+ struct {
+#ifdef CONFIG_SYS_FSL_SEC_LE
+ u32 low;
+ u32 high;
+#else
+ u32 high;
+ u32 low;
+#endif
+ } m_halfs;
+};
+#endif
+
static inline int desc_len(u32 *desc)
{
return *desc HDR_DESCLEN_MASK;
@@ -65,7 +80,16 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr)
{
dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
+#ifdef CONFIG_PHYS_64BIT
+ /* The Position of low and high part of 64 bit address
+* will depend on the endianness of CAAM Block */
+ union ptr_addr_t ptr_addr;
+ ptr_addr.m_halfs.high = (u32)(ptr 32);
+ ptr_addr.m_halfs.low = (u32)ptr;
+ *offset = ptr_addr.m_whole;
+#else
*offset = ptr;
+#endif
(*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ;
}
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
index c298404..9b243f6 100644
--- a/drivers/crypto/fsl/fsl_hash.c
+++ b/drivers/crypto/fsl/fsl_hash.c
@@ -92,12 +92,7 @@ static int caam_hash_update(void *hash_ctx, const void *buf,
return -EINVAL;
}
-#ifdef CONFIG_PHYS_64BIT
- ctx-sg_tbl[ctx-sg_num].addr_hi = addr 32;
-#else
- ctx-sg_tbl[ctx-sg_num].addr_hi = 0x0;
-#endif
- ctx-sg_tbl[ctx-sg_num].addr_lo = addr;
+ sec_out64(ctx-sg_tbl[ctx-sg_num].addr, addr);
sec_out32(ctx-sg_tbl[ctx-sg_num].len_flag,
(size SG_ENTRY_LENGTH_MASK));
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index f99d594..fcc8a5a 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -11,6 +11,7 @@
#include fsl_sec.h
#include jr.h
#include jobdesc.h
+#include desc_constr.h
#define CIRC_CNT(head, tail, size) (((head) - (tail)) (size - 1))
#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
@@ -154,11 +155,25 @@ static int jr_hw_reset(void)
/* -1 --- error, can't enqueue -- no space available */
static int jr_enqueue(uint32_t *desc_addr,
- void (*callback)(uint32_t desc, uint32_t status, void *arg),
+ void (*callback)(uint32_t status, void *arg),
void *arg)
{
struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
- int head = jr.head;
+ uint32_t head = jr.head;
+ uint32_t desc_word;
+ int length = desc_len(desc_addr);
+ int i;
+
+ /* The descriptor must be submitted to SEC block as per endianness
+* of the SEC Block.
+* So, if the endianness of Core and SEC block is different, each word
+* of the descriptor will be byte-swapped.
+*/
+ for (i = 0; i length; i++) {
+ desc_word = desc_addr[i];
+ sec_out32((uint32_t *)desc_addr[i], desc_word);
+ }
+
dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
if (sec_in32(regs-irsa) == 0 ||
@@ -166,7 +181,6 @@ static int jr_enqueue(uint32_t *desc_addr,
return -1;
jr.info[head].desc_phys_addr = desc_phys_addr;
- jr.info[head].desc_addr = (uint32_t)desc_addr;
jr.info[head].callback = (void *)callback;
jr.info[head].arg = arg;
jr.info[head].op_done = 0;
@@ -177,7 +191,7 @@ static int jr_enqueue(uint32_t *desc_addr,
ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
- jr.input_ring[head] = desc_phys_addr;
+ sec_out_phys(jr.input_ring[head], desc_phys_addr);
start = (unsigned long)jr.input_ring[head] ~(ARCH_DMA_MINALIGN - 1);
end = ALIGN(start + sizeof(dma_addr_t), ARCH_DMA_MINALIGN
[U-Boot] [PATCH 3/3][v7] powerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAM
For running Chain of Trust when doing Secure Boot from NAND, the Bootscript header and bootscript must be copied from NAND to RAM(DDR). The addresses and commands for the same have been defined. Signed-off-by: Saksham Jain saks...@freescale.com Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com --- Changes in v7: Patchset created. arch/powerpc/include/asm/fsl_secure_boot.h | 14 ++ include/config_fsl_secboot.h | 29 - include/configs/corenet_ds.h | 1 + 3 files changed, 43 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index cc33466..6e55716 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -73,6 +73,18 @@ #endif #ifndef CONFIG_FIT_SIGNATURE +/* If Boot Script is not on NOR and is required to be copied on RAM */ +#ifdef CONFIG_BOOTSCRIPT_COPY_RAM +#define CONFIG_BS_HDR_ADDR_RAM 0x0001 +#define CONFIG_BS_HDR_ADDR_FLASH 0x0080 +#define CONFIG_BS_HDR_SIZE 0x2000 +#define CONFIG_BS_ADDR_RAM 0x00012000 +#define CONFIG_BS_ADDR_FLASH 0x00802000 +#define CONFIG_BS_SIZE 0x1000 + +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM +#else + /* The bootscript header address is different for B4860 because the NOR * mapping is different on B4 due to reduced NOR size. */ @@ -88,6 +100,8 @@ #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee02 #endif +#endif + #include config_fsl_secboot.h #endif diff --git a/include/config_fsl_secboot.h b/include/config_fsl_secboot.h index 050b157..fc6788a 100644 --- a/include/config_fsl_secboot.h +++ b/include/config_fsl_secboot.h @@ -55,6 +55,22 @@ /* For secure boot flow, default environment used will be used */ #if defined(CONFIG_SYS_RAMBOOT) +#ifdef CONFIG_BOOTSCRIPT_COPY_RAM +#define CONFIG_BS_COPY_ENV \ + setenv bs_hdr_ram __stringify(CONFIG_BS_HDR_ADDR_RAM); \ + setenv bs_hdr_flash __stringify(CONFIG_BS_HDR_ADDR_FLASH); \ + setenv bs_hdr_size __stringify(CONFIG_BS_HDR_SIZE); \ + setenv bs_ram __stringify(CONFIG_BS_ADDR_RAM); \ + setenv bs_flash __stringify(CONFIG_BS_ADDR_FLASH); \ + setenv bs_size __stringify(CONFIG_BS_SIZE); + +#if defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_BS_COPY_CMD \ + nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ; \ + nand read $bs_ram $bs_flash $bs_size ; +#endif /* CONFIG_RAMBOOT_NAND */ +#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ + #if defined(CONFIG_RAMBOOT_SPIFLASH) #undef CONFIG_ENV_IS_IN_SPI_FLASH #elif defined(CONFIG_RAMBOOT_NAND) @@ -68,6 +84,17 @@ #define CONFIG_ENV_IS_NOWHERE +#ifndef CONFIG_BS_COPY_ENV +#define CONFIG_BS_COPY_ENV +#endif + +#ifndef CONFIG_BS_COPY_CMD +#define CONFIG_BS_COPY_CMD +#endif + +#define CONFIG_SECBOOT_CMD CONFIG_BS_COPY_ENV \ + CONFIG_BS_COPY_CMD \ + CONFIG_SECBOOT /* * We don't want boot delay for secure boot flow * before autoboot starts @@ -75,7 +102,7 @@ #undef CONFIG_BOOTDELAY #define CONFIG_BOOTDELAY 0 #undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND CONFIG_SECBOOT +#define CONFIG_BOOTCOMMAND CONFIG_SECBOOT_CMD /* * CONFIG_ZERO_BOOTDELAY_CHECK should not be defined for diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 2ec7fd4f..497b58b 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -22,6 +22,7 @@ #ifdef CONFIG_NAND #define CONFIG_RAMBOOT_NAND #endif +#define CONFIG_BOOTSCRIPT_COPY_RAM #else #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS0xfffc -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3][[v7] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040
Secure Boot Target is added for NAND for P5020 and P5040. The Secure boot target has already been added for P3041 by enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM. The targets for P5020 and P5040 are added in the same manner. Signed-off-by: Saksham Jain saks...@freescale.com Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com --- Changes in v7: Patchset created. TEXT BASE is defined as 0xFFF4 as per new design. board/freescale/corenet_ds/MAINTAINERS | 2 ++ configs/P5020DS_NAND_SECURE_BOOT_defconfig | 4 configs/P5040DS_NAND_SECURE_BOOT_defconfig | 4 3 files changed, 10 insertions(+) create mode 100644 configs/P5020DS_NAND_SECURE_BOOT_defconfig create mode 100644 configs/P5040DS_NAND_SECURE_BOOT_defconfig diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS index 6855446..73b0553 100644 --- a/board/freescale/corenet_ds/MAINTAINERS +++ b/board/freescale/corenet_ds/MAINTAINERS @@ -33,3 +33,5 @@ CORENET_DS_SECURE_BOOT BOARD M: Aneesh Bansal aneesh.ban...@freescale.com S: Maintained F: configs/P3041DS_NAND_SECURE_BOOT_defconfig +F: configs/P5020DS_NAND_SECURE_BOOT_defconfig +F: configs/P5040DS_NAND_SECURE_BOOT_defconfig diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 000..5edfe45 --- /dev/null +++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS=RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF4 +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5020DS=y diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 000..f33d236 --- /dev/null +++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS=RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF4 +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5040DS=y -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3][v7] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
Secure Boot Target is added for NAND for P3041.
Changes:
In PowerPC, the core begins execution from address 0xFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFF.
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on SRAM configured
at address 0xBFF0.
In the U-Boot code, TLB entries are created to map the virtual address
0xFFF0 to physical address 0xBFF0 of CPC configured as SRAM.
Signed-off-by: Saksham Jain saks...@freescale.com
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v7:
Created TLB entry to map virtual address 0xFFF0 to physical address
0xBFF0 as per discussion.
Makefile | 4
arch/powerpc/cpu/mpc85xx/start.S | 11 +++
arch/powerpc/include/asm/fsl_secure_boot.h | 5 +
board/freescale/common/p_corenet/tlb.c | 15 +++
board/freescale/corenet_ds/MAINTAINERS | 5 +
configs/P3041DS_NAND_SECURE_BOOT_defconfig | 4
include/configs/corenet_ds.h | 8
7 files changed, 52 insertions(+)
create mode 100644 configs/P3041DS_NAND_SECURE_BOOT_defconfig
diff --git a/Makefile b/Makefile
index 0a674bf..1753709 100644
--- a/Makefile
+++ b/Makefile
@@ -737,8 +737,12 @@ ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
ifeq ($(CONFIG_SPL_FSL_PBL),y)
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
else
+ifneq ($(CONFIG_SECURE_BOOT), y)
+# For Secure Boot The Image needs to be signed and Header must also
+# be included. So The image has to be built explicitly
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
endif
+endif
ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index e61d8e0..a70fb71 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1052,6 +1052,17 @@ create_init_ram_area:
CONFIG_SYS_MONITOR_BASE 0xfff0, MAS2_I|MAS2_G, \
CONFIG_SYS_PBI_FLASH_WINDOW 0xfff0,
MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
+
+#elif defined(CONFIG_RAMBOOT_PBL) defined(CONFIG_SECURE_BOOT)
+ /* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE
+* to L3 Address configured by PBL for ISBC code
+ */
+ create_tlb1_entry 15, \
+ 1, BOOKE_PAGESZ_1M, \
+ CONFIG_SYS_MONITOR_BASE 0xfff0, MAS2_I|MAS2_G, \
+ CONFIG_SYS_INIT_L3_ADDR 0xfff0, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
+
#else
/*
* create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE
space, the main
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h
b/arch/powerpc/include/asm/fsl_secure_boot.h
index 8f794ef..cc33466 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -46,6 +46,11 @@
#define CONFIG_SYS_INIT_L3_ADDR0xbff0
#endif
+#if defined(CONFIG_RAMBOOT_PBL)
+#undef CONFIG_SYS_INIT_L3_ADDR
+#define CONFIG_SYS_INIT_L3_ADDR0xbff0
+#endif
+
#if defined(CONFIG_C29XPCIE)
#define CONFIG_KEY_REVOCATION
#endif
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index 8148e46..56e4f63 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -43,6 +43,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 */
/* *I*** - Covers boot page */
#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR)
+
+#if !defined(CONFIG_SECURE_BOOT)
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
* SRAM is at 0xfff0, it covered the 0xf000.
@@ -50,6 +52,19 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ /*
+* *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot
+* the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR,
+* and virtual address is CONFIG_SYS_MONITOR_BASE
+*/
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE 0xfff0,
+ CONFIG_SYS_INIT_L3_ADDR 0xfff0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#endif
+
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
diff --git a/board/freescale/corenet_ds/MAINTAINERS
b
[U-Boot] [PATCH 1/2][v6] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
Secure Boot Target is added for NAND for P3041.
Changes:
In PowerPC, the core begins execution from address 0xFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFF.
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on this SRAM at
location 0xBFF4 with entry point as 0xBFFC.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v6:
Changed the version in Patchset.
Makefile | 4
arch/powerpc/cpu/mpc85xx/cpu_init.c| 17 +
board/freescale/common/p_corenet/tlb.c | 19 +--
board/freescale/corenet_ds/MAINTAINERS | 5 +
configs/P3041DS_NAND_SECURE_BOOT_defconfig | 4
include/configs/corenet_ds.h | 21 +
6 files changed, 68 insertions(+), 2 deletions(-)
create mode 100644 configs/P3041DS_NAND_SECURE_BOOT_defconfig
diff --git a/Makefile b/Makefile
index bd4abab..acfaa23 100644
--- a/Makefile
+++ b/Makefile
@@ -719,8 +719,12 @@ ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
ifeq ($(CONFIG_SPL_FSL_PBL),y)
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
else
+ifneq ($(CONFIG_SECURE_BOOT), y)
+# For Secure Boot The Image needs to be signed and Header must also
+# be included. So The image has to be built explicitly
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
endif
+endif
ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 4cf8853..1f520fe 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -843,6 +843,23 @@ int cpu_init_r(void)
setup_mp();
#endif
+#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR) \
+ defined(CONFIG_SECURE_BOOT)
+ /* Disable the TLB Created for L3 and create the TLB required for
+* PCIE which was not created earlier.
+*/
+ int tlb_index;
+ tlb_index = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
+ if (tlb_index != -1) {
+ disable_tlb(tlb_index);
+
+ set_tlb(1, CONFIG_SECBOOT_TLB_VIRT_ADDR,
+ CONFIG_SECBOOT_TLB_PHYS_ADDR,
+ CONFIG_SECBOOT_TLB_PERM, CONFIG_SECBOOT_TLB_ATTR,
+ 0, tlb_index, CONFIG_SECBOOT_TLB_PAGESZ, 1);
+ }
+#endif
+
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
{
if (SVR_MAJ(svr) 3) {
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index 8148e46..dcadba1 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -42,7 +42,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 */
/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR)
+ /* In Case of Secure RAM Boot L3 address is defined at 0xbff0 */
+#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR) \
+ !defined(CONFIG_SECURE_BOOT)
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
* SRAM is at 0xfff0, it covered the 0xf000.
@@ -76,11 +78,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
+#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR) \
+ defined(CONFIG_SECURE_BOOT)
+ /* In case of Secure Boot, L3 is used as 1M SRAM
+* and the address of the SRAM is at 0xbff0.
+* The PCIE TLB entry conflicts with the above entry.
+* So, the entry for PCIE is not created at this point of time.
+* It will be created later on in cpu_init_r()
+* when U-Boot has relocated to DDR
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1M, 1),
+#else
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
-
+#endif
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x4000,
CONFIG_SYS_PCIE1_MEM_PHYS + 0x4000,
diff --git a/board/freescale/corenet_ds/MAINTAINERS
b/board/freescale/corenet_ds/MAINTAINERS
index 745847c..6855446 100644
--- a/board/freescale/corenet_ds/MAINTAINERS
+++ b/board/freescale/corenet_ds/MAINTAINERS
@@ -28,3 +28,8 @@ F:configs/P5040DS_NAND_defconfig
F: configs
[U-Boot] [PATCH 2/2][v6] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040
Secure Boot Target is added for NAND for P5020 and P5040. The Secure boot target has already been added for P3041 by enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM. The targets for P5020 and P5040 are added in the same manner. Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com --- Changes in v6: Changed the version in Patchset. board/freescale/corenet_ds/MAINTAINERS | 2 ++ configs/P5020DS_NAND_SECURE_BOOT_defconfig | 4 configs/P5040DS_NAND_SECURE_BOOT_defconfig | 4 3 files changed, 10 insertions(+) create mode 100644 configs/P5020DS_NAND_SECURE_BOOT_defconfig create mode 100644 configs/P5040DS_NAND_SECURE_BOOT_defconfig diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS index 6855446..73b0553 100644 --- a/board/freescale/corenet_ds/MAINTAINERS +++ b/board/freescale/corenet_ds/MAINTAINERS @@ -33,3 +33,5 @@ CORENET_DS_SECURE_BOOT BOARD M: Aneesh Bansal aneesh.ban...@freescale.com S: Maintained F: configs/P3041DS_NAND_SECURE_BOOT_defconfig +F: configs/P5020DS_NAND_SECURE_BOOT_defconfig +F: configs/P5040DS_NAND_SECURE_BOOT_defconfig diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 000..8e99633 --- /dev/null +++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS=RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xBFF4 +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5020DS=y diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 000..97b266a --- /dev/null +++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS=RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xBFF4 +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5040DS=y -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2][v2] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040
Secure Boot Target is added for NAND for P5020 and P5040. The Secure boot target has already been added for P3041 by enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM. The targets for P5020 and P5040 are added in the same manner. Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com --- Changes in v2: New patch set created. board/freescale/corenet_ds/MAINTAINERS | 2 ++ configs/P5020DS_NAND_SECURE_BOOT_defconfig | 4 configs/P5040DS_NAND_SECURE_BOOT_defconfig | 4 3 files changed, 10 insertions(+) create mode 100644 configs/P5020DS_NAND_SECURE_BOOT_defconfig create mode 100644 configs/P5040DS_NAND_SECURE_BOOT_defconfig diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS index 6855446..73b0553 100644 --- a/board/freescale/corenet_ds/MAINTAINERS +++ b/board/freescale/corenet_ds/MAINTAINERS @@ -33,3 +33,5 @@ CORENET_DS_SECURE_BOOT BOARD M: Aneesh Bansal aneesh.ban...@freescale.com S: Maintained F: configs/P3041DS_NAND_SECURE_BOOT_defconfig +F: configs/P5020DS_NAND_SECURE_BOOT_defconfig +F: configs/P5040DS_NAND_SECURE_BOOT_defconfig diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 000..8e99633 --- /dev/null +++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS=RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xBFF4 +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5020DS=y diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 000..97b266a --- /dev/null +++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS=RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xBFF4 +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5040DS=y -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2][v5] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
Secure Boot Target is added for NAND for P3041.
Changes:
In PowerPC, the core begins execution from address 0xFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFF.
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on this SRAM at
location 0xBFF4 with entry point as 0xBFFC.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v5:
Created MACRO's for address and other attributes required for
creation of PCIE TLB entry.
Makefile | 4
arch/powerpc/cpu/mpc85xx/cpu_init.c| 17 +
board/freescale/common/p_corenet/tlb.c | 19 +--
board/freescale/corenet_ds/MAINTAINERS | 5 +
configs/P3041DS_NAND_SECURE_BOOT_defconfig | 4
include/configs/corenet_ds.h | 21 +
6 files changed, 68 insertions(+), 2 deletions(-)
create mode 100644 configs/P3041DS_NAND_SECURE_BOOT_defconfig
diff --git a/Makefile b/Makefile
index bd4abab..acfaa23 100644
--- a/Makefile
+++ b/Makefile
@@ -719,8 +719,12 @@ ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
ifeq ($(CONFIG_SPL_FSL_PBL),y)
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
else
+ifneq ($(CONFIG_SECURE_BOOT), y)
+# For Secure Boot The Image needs to be signed and Header must also
+# be included. So The image has to be built explicitly
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
endif
+endif
ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 4cf8853..1f520fe 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -843,6 +843,23 @@ int cpu_init_r(void)
setup_mp();
#endif
+#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR) \
+ defined(CONFIG_SECURE_BOOT)
+ /* Disable the TLB Created for L3 and create the TLB required for
+* PCIE which was not created earlier.
+*/
+ int tlb_index;
+ tlb_index = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
+ if (tlb_index != -1) {
+ disable_tlb(tlb_index);
+
+ set_tlb(1, CONFIG_SECBOOT_TLB_VIRT_ADDR,
+ CONFIG_SECBOOT_TLB_PHYS_ADDR,
+ CONFIG_SECBOOT_TLB_PERM, CONFIG_SECBOOT_TLB_ATTR,
+ 0, tlb_index, CONFIG_SECBOOT_TLB_PAGESZ, 1);
+ }
+#endif
+
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
{
if (SVR_MAJ(svr) 3) {
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index 8148e46..dcadba1 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -42,7 +42,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 */
/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR)
+ /* In Case of Secure RAM Boot L3 address is defined at 0xbff0 */
+#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR) \
+ !defined(CONFIG_SECURE_BOOT)
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
* SRAM is at 0xfff0, it covered the 0xf000.
@@ -76,11 +78,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
+#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR) \
+ defined(CONFIG_SECURE_BOOT)
+ /* In case of Secure Boot, L3 is used as 1M SRAM
+* and the address of the SRAM is at 0xbff0.
+* The PCIE TLB entry conflicts with the above entry.
+* So, the entry for PCIE is not created at this point of time.
+* It will be created later on in cpu_init_r()
+* when U-Boot has relocated to DDR
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1M, 1),
+#else
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
-
+#endif
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x4000,
CONFIG_SYS_PCIE1_MEM_PHYS + 0x4000,
diff --git a/board/freescale/corenet_ds/MAINTAINERS
b/board/freescale/corenet_ds/MAINTAINERS
index 745847c..6855446 100644
--- a/board/freescale/corenet_ds/MAINTAINERS
+++ b/board/freescale/corenet_ds/MAINTAINERS
@@ -28,3 +28,8 @@ F
[U-Boot] [PATCH 1/2][v4] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
Secure Boot Target is added for NAND for P3041.
Changes:
In PowerPC, the core begins execution from address 0xFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFF.
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on this SRAM at
location 0xBFF4 with entry point as 0xBFFC.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v4:
- Created a patch set.
Makefile | 4
arch/powerpc/cpu/mpc85xx/cpu_init.c| 17 +
board/freescale/common/p_corenet/tlb.c | 18 +-
board/freescale/corenet_ds/MAINTAINERS | 5 +
configs/P3041DS_NAND_SECURE_BOOT_defconfig | 4
include/configs/corenet_ds.h | 9 +
6 files changed, 56 insertions(+), 1 deletion(-)
create mode 100644 configs/P3041DS_NAND_SECURE_BOOT_defconfig
diff --git a/Makefile b/Makefile
index bd4abab..acfaa23 100644
--- a/Makefile
+++ b/Makefile
@@ -719,8 +719,12 @@ ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
ifeq ($(CONFIG_SPL_FSL_PBL),y)
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
else
+ifneq ($(CONFIG_SECURE_BOOT), y)
+# For Secure Boot The Image needs to be signed and Header must also
+# be included. So The image has to be built explicitly
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
endif
+endif
ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 4cf8853..ef56cc0 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -843,6 +843,23 @@ int cpu_init_r(void)
setup_mp();
#endif
+#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR) \
+ defined(CONFIG_SECURE_BOOT)
+ /* Disable the TLB Created for L3 and create the TLB required for
+* PCIE (CONFIG_SYS_PCIE1_MEM_VIRT) which was not created earlier.
+*/
+ int tlb_index;
+ tlb_index = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
+ if (tlb_index != -1) {
+ disable_tlb(tlb_index);
+
+ set_tlb(1, CONFIG_SYS_PCIE1_MEM_VIRT,
+ CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, tlb_index, BOOKE_PAGESZ_1G, 1);
+ }
+#endif
+
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
{
if (SVR_MAJ(svr) 3) {
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index 8148e46..1b60cfb 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -42,7 +42,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 */
/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR)
+ /* In Case of Secure RAM Boot L3 address is defined at 0xbff0 */
+#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR) \
+ !defined(CONFIG_SECURE_BOOT)
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
* SRAM is at 0xfff0, it covered the 0xf000.
@@ -76,11 +78,25 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
+#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR) \
+ defined(CONFIG_SECURE_BOOT)
+ /* In case of Secure Boot, L3 is used as 1M SRAM
+* and the address of the SRAM is at 0xbff0.
+* The PCIE TLB entry conflicts with the above entry.
+* So, the entry for PCIE is not created at this point of time.
+* It will be created later on in cpu_init_r()
+* when U-Boot has relocated to DDR
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1M, 1),
+#else
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
+#endif
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x4000,
CONFIG_SYS_PCIE1_MEM_PHYS + 0x4000,
diff --git a/board/freescale/corenet_ds/MAINTAINERS
b/board/freescale/corenet_ds/MAINTAINERS
index 745847c..6855446 100644
--- a/board/freescale/corenet_ds/MAINTAINERS
+++ b/board/freescale/corenet_ds/MAINTAINERS
@@ -28,3 +28,8 @@ F:configs/P5040DS_NAND_defconfig
F: configs/P5040DS_SDCARD_defconfig
F: configs
[U-Boot] [PATCH 2/2] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040
Secure Boot Target is added for NAND for P5020 and P5040. The Secure boot target has already been added for P3041 by enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM. The targets for P5020 and P5040 are added in the same manner. Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com --- board/freescale/corenet_ds/MAINTAINERS | 2 ++ configs/P5020DS_NAND_SECURE_BOOT_defconfig | 4 configs/P5040DS_NAND_SECURE_BOOT_defconfig | 4 3 files changed, 10 insertions(+) create mode 100644 configs/P5020DS_NAND_SECURE_BOOT_defconfig create mode 100644 configs/P5040DS_NAND_SECURE_BOOT_defconfig diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS index 6855446..73b0553 100644 --- a/board/freescale/corenet_ds/MAINTAINERS +++ b/board/freescale/corenet_ds/MAINTAINERS @@ -33,3 +33,5 @@ CORENET_DS_SECURE_BOOT BOARD M: Aneesh Bansal aneesh.ban...@freescale.com S: Maintained F: configs/P3041DS_NAND_SECURE_BOOT_defconfig +F: configs/P5020DS_NAND_SECURE_BOOT_defconfig +F: configs/P5040DS_NAND_SECURE_BOOT_defconfig diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 000..8e99633 --- /dev/null +++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS=RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xBFF4 +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5020DS=y diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 000..97b266a --- /dev/null +++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS=RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xBFF4 +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5040DS=y -- 1.8.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH][v3] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
Secure Boot Target is added for NAND for P3041.
Changes:
In PowerPC, the core begins execution from address 0xFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFF.
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on this SRAM at
location 0xBFF4 with entry point as 0xBFFC.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v3:
- Updated MAINTAINERS file
- In cpu_init_r, TLB for L3 is to be disabled only in case of SECURE_BOOT
and CONFIG_SYS_RAMBOOT
Makefile | 4
arch/powerpc/cpu/mpc85xx/cpu_init.c| 17 +
board/freescale/common/p_corenet/tlb.c | 18 +-
board/freescale/corenet_ds/MAINTAINERS | 5 +
configs/P3041DS_NAND_SECURE_BOOT_defconfig | 4
include/configs/corenet_ds.h | 9 +
6 files changed, 56 insertions(+), 1 deletion(-)
create mode 100644 configs/P3041DS_NAND_SECURE_BOOT_defconfig
diff --git a/Makefile b/Makefile
index 92faed6..4bc83d6 100644
--- a/Makefile
+++ b/Makefile
@@ -714,8 +714,12 @@ ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
ifeq ($(CONFIG_SPL_FSL_PBL),y)
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
else
+ifneq ($(CONFIG_SECURE_BOOT), y)
+# For Secure Boot The Image needs to be signed and Header must also
+# be included. So The image has to be built explicitly
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
endif
+endif
ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 4cf8853..ef56cc0 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -843,6 +843,23 @@ int cpu_init_r(void)
setup_mp();
#endif
+#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR) \
+ defined(CONFIG_SECURE_BOOT)
+ /* Disable the TLB Created for L3 and create the TLB required for
+* PCIE (CONFIG_SYS_PCIE1_MEM_VIRT) which was not created earlier.
+*/
+ int tlb_index;
+ tlb_index = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
+ if (tlb_index != -1) {
+ disable_tlb(tlb_index);
+
+ set_tlb(1, CONFIG_SYS_PCIE1_MEM_VIRT,
+ CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, tlb_index, BOOKE_PAGESZ_1G, 1);
+ }
+#endif
+
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
{
if (SVR_MAJ(svr) 3) {
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index 8148e46..1b60cfb 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -42,7 +42,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 */
/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR)
+ /* In Case of Secure RAM Boot L3 address is defined at 0xbff0 */
+#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR) \
+ !defined(CONFIG_SECURE_BOOT)
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
* SRAM is at 0xfff0, it covered the 0xf000.
@@ -76,11 +78,25 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
+#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR) \
+ defined(CONFIG_SECURE_BOOT)
+ /* In case of Secure Boot, L3 is used as 1M SRAM
+* and the address of the SRAM is at 0xbff0.
+* The PCIE TLB entry conflicts with the above entry.
+* So, the entry for PCIE is not created at this point of time.
+* It will be created later on in cpu_init_r()
+* when U-Boot has relocated to DDR
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1M, 1),
+#else
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
+#endif
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x4000,
CONFIG_SYS_PCIE1_MEM_PHYS + 0x4000,
diff --git a/board/freescale/corenet_ds/MAINTAINERS
b/board/freescale/corenet_ds/MAINTAINERS
index 745847c..6855446 100644
--- a/board/freescale/corenet_ds/MAINTAINERS
+++ b/board/freescale/corenet_ds/MAINTAINERS
@@ -28,3 +28,8
[U-Boot] [PATCH][v2] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
Secure Boot Target is added for NAND for P3041
Changes:
In PowerPC, the core begins execution from address 0xFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e 0x0 - 0xDFFF
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on this SRAM at
location 0xBFF4 with entry point as 0xBFFC.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Changes in v2:
set_tlb call moved inside the if condition for checking
if tlb_index is valid.
Makefile | 4
arch/powerpc/cpu/mpc85xx/cpu_init.c| 16
board/freescale/common/p_corenet/tlb.c | 18 +-
configs/P3041DS_NAND_SECURE_BOOT_defconfig | 4
include/configs/corenet_ds.h | 6 ++
5 files changed, 47 insertions(+), 1 deletion(-)
create mode 100644 configs/P3041DS_NAND_SECURE_BOOT_defconfig
diff --git a/Makefile b/Makefile
index 36a9a28..ca98b3e 100644
--- a/Makefile
+++ b/Makefile
@@ -714,8 +714,12 @@ ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
ifeq ($(CONFIG_SPL_FSL_PBL),y)
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
else
+ifneq ($(CONFIG_SECURE_BOOT), y)
+# For Secure Boot The Image needs to be signed and Header must also
+# be included. So The image has to be built explicitly
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
endif
+endif
ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 85d32fc..026ed53 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -851,6 +851,22 @@ int cpu_init_r(void)
setup_mp();
#endif
+#ifdef CONFIG_SECURE_BOOT
+ /* Disable the TLB Created for L3 and create the TLB required for
+* PCIE (CONFIG_SYS_PCIE1_MEM_VIRT) which was not created earlier.
+*/
+ int tlb_index;
+ tlb_index = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
+ if (tlb_index != -1) {
+ disable_tlb(tlb_index);
+
+ set_tlb(1, CONFIG_SYS_PCIE1_MEM_VIRT,
+ CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, tlb_index, BOOKE_PAGESZ_1G, 1);
+ }
+#endif
+
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
{
if (SVR_MAJ(svr) 3) {
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index 8148e46..1b60cfb 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -42,7 +42,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 */
/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR)
+ /* In Case of Secure RAM Boot L3 address is defined at 0xbff0 */
+#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR) \
+ !defined(CONFIG_SECURE_BOOT)
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
* SRAM is at 0xfff0, it covered the 0xf000.
@@ -76,11 +78,25 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
+#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR) \
+ defined(CONFIG_SECURE_BOOT)
+ /* In case of Secure Boot, L3 is used as 1M SRAM
+* and the address of the SRAM is at 0xbff0.
+* The PCIE TLB entry conflicts with the above entry.
+* So, the entry for PCIE is not created at this point of time.
+* It will be created later on in cpu_init_r()
+* when U-Boot has relocated to DDR
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1M, 1),
+#else
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
+#endif
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x4000,
CONFIG_SYS_PCIE1_MEM_PHYS + 0x4000,
diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig
b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
new file mode 100644
index 000..e810b1c
--- /dev/null
+++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS=RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xBFF4
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P3041DS=y
diff --git a/include/configs/corenet_ds.h b/include
[U-Boot] [PATCH] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
Secure Boot Target is added for NAND for P3041
Changes:
In PowerPC, the core begins execution from address 0xFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e 0x0 - 0xDFFF
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on this SRAM at
location 0xBFF4 with entry point as 0xBFFC.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Makefile | 4
arch/powerpc/cpu/mpc85xx/cpu_init.c| 15 +++
board/freescale/common/p_corenet/tlb.c | 18 +-
configs/P3041DS_NAND_SECURE_BOOT_defconfig | 4
include/configs/corenet_ds.h | 6 ++
5 files changed, 46 insertions(+), 1 deletion(-)
create mode 100644 configs/P3041DS_NAND_SECURE_BOOT_defconfig
diff --git a/Makefile b/Makefile
index 36a9a28..ca98b3e 100644
--- a/Makefile
+++ b/Makefile
@@ -714,8 +714,12 @@ ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
ifeq ($(CONFIG_SPL_FSL_PBL),y)
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
else
+ifneq ($(CONFIG_SECURE_BOOT), y)
+# For Secure Boot The Image needs to be signed and Header must also
+# be included. So The image has to be built explicitly
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
endif
+endif
ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 85d32fc..2da99a1 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -851,6 +851,21 @@ int cpu_init_r(void)
setup_mp();
#endif
+#ifdef CONFIG_SECURE_BOOT
+ /* Disable the TLB Created for L3 and create the TLB required for
+* PCIE (CONFIG_SYS_PCIE1_MEM_VIRT) which was not created earlier.
+*/
+ int tlb_index;
+ tlb_index = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
+ if (tlb_index != -1)
+ disable_tlb(tlb_index);
+
+ set_tlb(1, CONFIG_SYS_PCIE1_MEM_VIRT,
+ CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, tlb_index, BOOKE_PAGESZ_1G, 1);
+#endif
+
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
{
if (SVR_MAJ(svr) 3) {
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index 8148e46..1b60cfb 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -42,7 +42,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 */
/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR)
+ /* In Case of Secure RAM Boot L3 address is defined at 0xbff0 */
+#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR) \
+ !defined(CONFIG_SECURE_BOOT)
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
* SRAM is at 0xfff0, it covered the 0xf000.
@@ -76,11 +78,25 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
+#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L3_ADDR) \
+ defined(CONFIG_SECURE_BOOT)
+ /* In case of Secure Boot, L3 is used as 1M SRAM
+* and the address of the SRAM is at 0xbff0.
+* The PCIE TLB entry conflicts with the above entry.
+* So, the entry for PCIE is not created at this point of time.
+* It will be created later on in cpu_init_r()
+* when U-Boot has relocated to DDR
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1M, 1),
+#else
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
+#endif
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x4000,
CONFIG_SYS_PCIE1_MEM_PHYS + 0x4000,
diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig
b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
new file mode 100644
index 000..e810b1c
--- /dev/null
+++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS=RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xBFF4
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P3041DS=y
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 225ffdd..8fba5ec 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -16,6 +16,11
