[PATCH v2] nitrogen6x: Remove extra quotes in fdtfile
After commit 395110284b56 ("nitrogen6x: Populate FDTFILE at build-time
for all platforms") iMX.6Q Sabrelite fails to boot due to a bad fdtfile
string:
Retrieving file: /dtbs/5.18.0-0.deb11.4-armmp/"imx6q-sabrelite".dtb
** File not found /dtbs/5.18.0-0.deb11.4-armmp/"imx6q-sabrelite".dtb **
CONFIG_DEFAULT_DEVICE_TREE option is string typed, so __stringify() is
adding extra quotes. Remove this.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Fabio Estevam
---
include/configs/nitrogen6x.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 2007b48868..26e6de2d2c 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -76,7 +76,7 @@
"fdt_high=0x\0" \
"initrd_high=0x\0" \
"fdt_addr_r=0x1800\0" \
- "fdtfile=" __stringify(CONFIG_DEFAULT_DEVICE_TREE) ".dtb\0" \
+ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
--
2.37.2
Re: [PATCH] imx6: Remove extra quotes in fdtfile environment variable
Hi Fabio,
On 9/27/22 11:20, Fabio Estevam wrote:
> Hi Ariel,
>
> On Tue, Sep 27, 2022 at 11:14 AM Ariel D'Alessandro
> wrote:
>>
>> After commit 395110284b56 ("nitrogen6x: Populate FDTFILE at build-time
>> for all platforms") iMX.6Q Sabrelite fails to boot due to a bad fdtfile
>> string:
>>
>> Retrieving file: /dtbs/5.18.0-0.deb11.4-armmp/"imx6q-sabrelite".dtb
>> ** File not found /dtbs/5.18.0-0.deb11.4-armmp/"imx6q-sabrelite".dtb **
>>
>> CONFIG_DEFAULT_DEVICE_TREE option is string typed, so __stringify() is
>> adding extra quotes. Remove this.
>>
>> Signed-off-by: Ariel D'Alessandro
>
> Just a nit: in the Subject, it would be better to change it like this:
>
> nitrogen6x: Remove extra quotes in fdtfile
Makes sense. Will amend it right away.
>
> Reviewed-by: Fabio Estevam
>
> Stefano/Tom,
>
> This is 2022.10 material IMHO.
Thanks!
[PATCH] imx6: Remove extra quotes in fdtfile environment variable
After commit 395110284b56 ("nitrogen6x: Populate FDTFILE at build-time
for all platforms") iMX.6Q Sabrelite fails to boot due to a bad fdtfile
string:
Retrieving file: /dtbs/5.18.0-0.deb11.4-armmp/"imx6q-sabrelite".dtb
** File not found /dtbs/5.18.0-0.deb11.4-armmp/"imx6q-sabrelite".dtb **
CONFIG_DEFAULT_DEVICE_TREE option is string typed, so __stringify() is
adding extra quotes. Remove this.
Signed-off-by: Ariel D'Alessandro
---
include/configs/nitrogen6x.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 2007b48868..26e6de2d2c 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -76,7 +76,7 @@
"fdt_high=0x\0" \
"initrd_high=0x\0" \
"fdt_addr_r=0x1800\0" \
- "fdtfile=" __stringify(CONFIG_DEFAULT_DEVICE_TREE) ".dtb\0" \
+ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
--
2.37.2
Re: [PATCH] rpi: Set FDT for RPi CM4 to the IO Board one
Hi Matthias,
On 9/19/22 08:37, Matthias Brugger wrote:
> Hi Ariel,
>
> On 16/09/2022 17:13, Ariel D'Alessandro wrote:
>> For the RPi CM4 (Compute Module 4), we currently try to load the dtb
>> file bcm2711-rpi-cm4.dtb, which is not built by the upstream kernel.
>>
>> Instead, the only CM4 dtb file provided by linux upstream is the
>> bcm2711-rpi-cm4-io.dtb, so let's use that.
>>
>> Signed-off-by: Ariel D'Alessandro
>> ---
>> board/raspberrypi/rpi/rpi.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
>> index 17b8108cc8..b88f80ce05 100644
>> --- a/board/raspberrypi/rpi/rpi.c
>> +++ b/board/raspberrypi/rpi/rpi.c
>> @@ -168,8 +168,8 @@ static const struct rpi_model
>> rpi_models_new_scheme[] = {
>> true,
>> },
>> [0x14] = {
>> - "Compute Module 4",
>> - DTB_DIR "bcm2711-rpi-cm4.dtb",
>> + "Compute Module 4 IO Board",
>> + DTB_DIR "bcm2711-rpi-cm4-io.dtb",
>
> We had that discussion in the past. It is supposed that most CM4s will
> be used with a custom board. I don't think it's a good idea to tie the
> ID of the module to a specific IO board.
Ah, sorry I didn't notice that previous thread. Your point makes sense.
I guess another question would be: to avoid this inconsistency, does it
make sense to have a generic bcm2711-rpi-cm4.dtb built in the kernel?
Thanks!
Ariel
[PATCH] rpi: Set FDT for RPi CM4 to the IO Board one
For the RPi CM4 (Compute Module 4), we currently try to load the dtb
file bcm2711-rpi-cm4.dtb, which is not built by the upstream kernel.
Instead, the only CM4 dtb file provided by linux upstream is the
bcm2711-rpi-cm4-io.dtb, so let's use that.
Signed-off-by: Ariel D'Alessandro
---
board/raspberrypi/rpi/rpi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 17b8108cc8..b88f80ce05 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -168,8 +168,8 @@ static const struct rpi_model rpi_models_new_scheme[] = {
true,
},
[0x14] = {
- "Compute Module 4",
- DTB_DIR "bcm2711-rpi-cm4.dtb",
+ "Compute Module 4 IO Board",
+ DTB_DIR "bcm2711-rpi-cm4-io.dtb",
true,
},
};
--
2.37.2
Re: [PATCH 2/4] configs: imx8m: use common imx8m.h for i.MX8MN
Peng, On 5/4/22 16:30, Ariel D'Alessandro wrote: > Hi Peng, > > On 5/3/22 12:43, Tim Harvey wrote: >> On Tue, May 3, 2022 at 4:39 AM Peng Fan (OSS) wrote: >>> >>> From: Peng Fan >>> >>> Some SPL definitions could be gerneralized, so use imx8m.h for iMX8MN. >>> >> >> Peng, >> >> s/gerneralized/generalized >> >> (looks like that typo is all the patches in your series) >> >> Great cleanup - thanks! This is a great start to getting rid of the >> remaining items in the config headers. >> >> If you do end up doing a 2nd version you can probably remove the >> comments on the sizes, for example 'SZ_8K /* 8 KB */'' as I think the >> comment is not needed. >> >> Works great for imx8mn-venice-*. >> >> Tested-by: Tim Harvey #imx8mm-venice-* > > Thanks a lot for the cleanup! I agree with Tim's comments, would be > worth removing those redundant sizes comments. > > Tested on i.MX8MN BSH SMM S2 PRO board. > Tested-by: Ariel D'Alessandro Tested on i.MX8MN Variscite Symphony board Tested-by: Ariel D'Alessandro > >> >>> Signed-off-by: Peng Fan >>> --- >>> include/configs/imx8m.h| 10 ++ >>> include/configs/imx8mn_bsh_smm_s2_common.h | 17 + >>> include/configs/imx8mn_evk.h | 20 +--- >>> include/configs/imx8mn_var_som.h | 15 +-- >>> include/configs/imx8mn_venice.h| 18 +- >>> 5 files changed, 14 insertions(+), 66 deletions(-) > > [snip]
Re: [PATCH 2/4] configs: imx8m: use common imx8m.h for i.MX8MN
Hi Peng, On 5/3/22 12:43, Tim Harvey wrote: > On Tue, May 3, 2022 at 4:39 AM Peng Fan (OSS) wrote: >> >> From: Peng Fan >> >> Some SPL definitions could be gerneralized, so use imx8m.h for iMX8MN. >> > > Peng, > > s/gerneralized/generalized > > (looks like that typo is all the patches in your series) > > Great cleanup - thanks! This is a great start to getting rid of the > remaining items in the config headers. > > If you do end up doing a 2nd version you can probably remove the > comments on the sizes, for example 'SZ_8K /* 8 KB */'' as I think the > comment is not needed. > > Works great for imx8mn-venice-*. > > Tested-by: Tim Harvey #imx8mm-venice-* Thanks a lot for the cleanup! I agree with Tim's comments, would be worth removing those redundant sizes comments. Tested on i.MX8MN BSH SMM S2 PRO board. Tested-by: Ariel D'Alessandro > >> Signed-off-by: Peng Fan >> --- >> include/configs/imx8m.h| 10 ++ >> include/configs/imx8mn_bsh_smm_s2_common.h | 17 + >> include/configs/imx8mn_evk.h | 20 +--- >> include/configs/imx8mn_var_som.h | 15 +-- >> include/configs/imx8mn_venice.h| 18 +- >> 5 files changed, 14 insertions(+), 66 deletions(-) [snip]
Re: [PATCH 11/17] imx: imx8mn_smm_s2: clean up board watchdog code
Hi Peng, On 5/3/22 09:24, Peng Fan (OSS) wrote: > From: Peng Fan > > pinctrl_wdog already marked u-boot,dm-spl, so clean up board code. > set_wdog_reset function could be handled by imx_watchdog.c driver. > > Signed-off-by: Peng Fan > --- > board/bsh/imx8mn_smm_s2/spl.c | 11 --- > 1 file changed, 11 deletions(-) Tested on i.MX8MN BSH SMM S2 PRO board. Tested-by: Ariel D'Alessandro Thanks!
Re: [PATCH 12/17] imx: imx8mn_var_som: clean up board watchdog code
Hi Peng, On 5/3/22 09:24, Peng Fan (OSS) wrote: > From: Peng Fan > > pinctrl_wdog already marked u-boot,dm-spl, so clean up board code. > set_wdog_reset function could be handled by imx_watchdog.c driver. > > Signed-off-by: Peng Fan > --- > board/variscite/imx8mn_var_som/spl.c | 11 --- > 1 file changed, 11 deletions(-) Tested on i.MX8MN Variscite Symphony board Tested-by: Ariel D'Alessandro Thanks!
Re: [PATCH 08/15] imx: imx8mn_var_som: enable DM_SERIAL
Hi Peng, On 4/30/22 09:43, Peng Fan (OSS) wrote: > From: Peng Fan > > Enable CONFIG_DM_SERIAL. uart and its pinmux was already > marked with u-boot,dm-spl. > Move preloader_console_init after spl_init to make sure driver > model work. > > Signed-off-by: Peng Fan > --- > board/variscite/imx8mn_var_som/spl.c | 11 ++- > configs/imx8mn_var_som_defconfig | 1 + > include/configs/imx8mn_var_som.h | 2 -- > 3 files changed, 3 insertions(+), 11 deletions(-) Reviewed-by: Ariel D'Alessandro Thanks!
Re: [PATCH V3] board: bsh: imx8mn_bsh_smm_s2/s2pro: enable DM_SERIAL
Hi Michael, On 4/18/22 03:53, Michael Trimarchi wrote: > Enable DM_SERIAL for both U_Boot and the SPL. The uart4 and its pinmux > are already marked with u-boot,dm-spl but we need to move the call to > preloader_console_init() after spl_init() to avoid a board hang > as dm can't be used until after spl_init(). > > Remove the manual config of the UART pinmux now that it is no longer > needed. > > Signed-off-by: Michael Trimarchi > Cc: Tim Harvey > Reviewed-by: Fabio Estevam Tested-by: Ariel D'Alessandro
[RFC PATCH] imx: hab: Support FIT images with external data
The IVT table is located right after the FIT image. If the FIT image is
generated using external data, the total size needs to be computed
including the FIT struct and external data lengths.
Signed-off-by: Ariel D'Alessandro
---
arch/arm/mach-imx/hab.c | 3 ++-
boot/image-fit.c| 44 +
include/image.h | 9 +
3 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index 55317abba23..d0bee716772 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -593,7 +593,8 @@ static ulong get_image_ivt_offset(ulong img_addr)
#endif
#if CONFIG_IS_ENABLED(FIT)
case IMAGE_FORMAT_FIT:
- return (fit_get_size(buf) + 0x1000 - 1) & ~(0x1000 - 1);
+ return (fit_get_size_external(buf)
+ + 0x1000 - 1) & ~(0x1000 - 1);
#endif
default:
return 0;
diff --git a/boot/image-fit.c b/boot/image-fit.c
index 6610035d0ad..7a9b6b6c71d 100644
--- a/boot/image-fit.c
+++ b/boot/image-fit.c
@@ -1168,6 +1168,50 @@ ulong fit_get_end(const void *fit)
return map_to_sysmem((void *)(fit + fdt_totalsize(fit)));
}
+ulong fit_get_size_external(const void *fit)
+{
+ int images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
+ unsigned int ret = fit_get_size(fit);
+ int noffset, ndepth, offset;
+ const void *data;
+ size_t size;
+
+ /* Find images parent node offset */
+ if (images_noffset < 0) {
+ printf("Can't find images parent node '%s' (%s)\n",
+ FIT_IMAGES_PATH, fdt_strerror(images_noffset));
+ return 0;
+ }
+
+ /* Process its subnodes, print out component images details */
+ for (ndepth = 0, noffset = fdt_next_node(fit, images_noffset, );
+(noffset >= 0) && (ndepth > 0);
+noffset = fdt_next_node(fit, noffset, )) {
+ /*
+* Omit indirect child nodes of the images parent node, as it's
+* not a component image node.
+*/
+ if (ndepth != 1)
+ continue;
+
+ /* Omit images that are not external, as its size is already
+* included in the FIT image.
+*/
+ if (fit_image_get_data_position(fit, noffset, ) &&
+ fit_image_get_data_offset(fit, noffset, ))
+ continue;
+
+ if (fit_image_get_data_and_size(fit, noffset, , )) {
+ printf("Couldn't get image data/size (noffset=%d)\n",
+ noffset);
+ return 0;
+ }
+ ret += size;
+ }
+
+ return ret;
+}
+
/**
* fit_set_timestamp - set node timestamp property
* @fit: pointer to the FIT format image header
diff --git a/include/image.h b/include/image.h
index e4c6a50b885..012ea28ba1b 100644
--- a/include/image.h
+++ b/include/image.h
@@ -979,6 +979,15 @@ static inline ulong fit_get_size(const void *fit)
*/
ulong fit_get_end(const void *fit);
+/**
+ * fit_get_size_external - get FIT image size including external data
+ * @fit: pointer to the FIT format image header
+ *
+ * returns:
+ * size of the FIT image (including external data) in memory
+ */
+ulong fit_get_size_external(const void *fit);
+
/**
* fit_get_name - get FIT node name
* @fit: pointer to the FIT format image header
--
2.34.1
[PATCH v5 7/7] bsh: imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
Introduce BSH SystemMaster (SMM) S2 board family, which consists of:
iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards.
Add support for iMX8MN BSH SMM S2 board:
- 256 MiB DDR3 RAM
- 512MiB Nand
- USBOTG1 peripheral - fastboot.
- 100Mbit Ethernet
Add support for iMX8MN BSH SMM S2 PRO board:
- 512 MiB DDR3 RAM
- 8 GiB eMMC
- USBOTG1 peripheral - fastboot.
- 100Mbit Ethernet
Signed-off-by: Ariel D'Alessandro
Signed-off-by: Michael Trimarchi
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi| 423
.../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 225 +
arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi| 15 +
arch/arm/dts/imx8mn-bsh-smm-s2.dts| 48 +
arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi | 15 +
arch/arm/dts/imx8mn-bsh-smm-s2pro.dts | 80 ++
arch/arm/mach-imx/imx8m/Kconfig | 15 +
board/bsh/imx8mn_smm_s2/Kconfig | 49 +
board/bsh/imx8mn_smm_s2/MAINTAINERS | 8 +
board/bsh/imx8mn_smm_s2/Makefile | 13 +
board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c | 941 ++
board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c | 941 ++
board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c | 23 +
board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg | 8 +
board/bsh/imx8mn_smm_s2/spl.c | 97 ++
configs/imx8mn_bsh_smm_s2_defconfig | 96 ++
configs/imx8mn_bsh_smm_s2pro_defconfig| 93 ++
doc/board/bsh/imx8mn_bsh_smm_s2.rst | 62 ++
doc/board/bsh/index.rst | 9 +
doc/board/index.rst | 1 +
include/configs/imx8mn_bsh_smm_s2.h | 51 +
include/configs/imx8mn_bsh_smm_s2_common.h| 59 ++
include/configs/imx8mn_bsh_smm_s2pro.h| 35 +
24 files changed, 3309 insertions(+)
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2.dts
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro.dts
create mode 100644 board/bsh/imx8mn_smm_s2/Kconfig
create mode 100644 board/bsh/imx8mn_smm_s2/MAINTAINERS
create mode 100644 board/bsh/imx8mn_smm_s2/Makefile
create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c
create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c
create mode 100644 board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c
create mode 100644 board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg
create mode 100644 board/bsh/imx8mn_smm_s2/spl.c
create mode 100644 configs/imx8mn_bsh_smm_s2_defconfig
create mode 100644 configs/imx8mn_bsh_smm_s2pro_defconfig
create mode 100644 doc/board/bsh/imx8mn_bsh_smm_s2.rst
create mode 100644 doc/board/bsh/index.rst
create mode 100644 include/configs/imx8mn_bsh_smm_s2.h
create mode 100644 include/configs/imx8mn_bsh_smm_s2_common.h
create mode 100644 include/configs/imx8mn_bsh_smm_s2pro.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cd9a820f956..811e5581488 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -913,6 +913,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-venice-gw7902.dtb \
imx8mm-verdin.dtb \
phycore-imx8mm.dtb \
+ imx8mn-bsh-smm-s2.dtb \
+ imx8mn-bsh-smm-s2pro.dtb \
imx8mn-ddr4-evk.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \
diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
b/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
new file mode 100644
index 000..184c715bd38
--- /dev/null
+++ b/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
@@ -0,0 +1,423 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ * Copyright 2021 BSH Hausgeraete GmbH
+ */
+
+#include "imx8mn.dtsi"
+
+/ {
+ chosen {
+ stdout-path =
+ };
+
+ fec_supply: fec_supply_en {
+ compatible = "regulator-fixed";
+ regulator-name = "tja1101_en";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = < 20 GPIO_ACTIVE_HIGH>;
+ vin-supply = <_reg>;
+ enable-active-high;
+ };
+
+ usdhc2_pwrseq: usdhc2_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <_usdhc2_pwrseq>;
+ reset-gpios = < 27 GPIO_ACTIVE_LOW>;
+ };
+};
+
+_0 {
+ cpu-supply = <_reg>;
+};
+
+_1 {
+ cpu-supply = <_reg>;
+};
+
+_2 {
+ cpu-supply = <_reg>;
+};
+
+_3 {
+ cpu-supply = <_reg>;
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_espi2>;
+ status = "okay";
+
[PATCH v5 6/7] net: phy: nxp-tja11xx: Add NXP TJA11xx PHY driver
From: Michael Trimarchi
Add driver for the NXP TJA1100 and TJA1101 PHYs. These PHYs are special
BroadRReach 100BaseT1 PHYs used in automotive.
Signed-off-by: Michael Trimarchi
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Ramon Fried
---
drivers/net/phy/Kconfig | 5 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/nxp-tja11xx.c | 277 ++
drivers/net/phy/phy.c | 3 +
include/phy.h | 1 +
5 files changed, 287 insertions(+)
create mode 100644 drivers/net/phy/nxp-tja11xx.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 014a4de223e..d40ce92cadc 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -215,6 +215,11 @@ config PHY_NXP_C45_TJA11XX
Enable support for NXP C45 TJA11XX PHYs.
Currently supports only the TJA1103 PHY.
+config PHY_NXP_TJA11XX
+ bool "NXP TJA11XX Ethernet PHYs support"
+ help
+ Currently supports the NXP TJA1100 and TJA1101 PHY.
+
config PHY_REALTEK
bool "Realtek Ethernet PHYs support"
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index b28440bc4e5..67ca4d3a69f 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o
obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o
+obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o
obj-$(CONFIG_PHY_REALTEK) += realtek.o
obj-$(CONFIG_PHY_SMSC) += smsc.o
obj-$(CONFIG_PHY_TERANETICS) += teranetics.o
diff --git a/drivers/net/phy/nxp-tja11xx.c b/drivers/net/phy/nxp-tja11xx.c
new file mode 100644
index 000..30dec5e605b
--- /dev/null
+++ b/drivers/net/phy/nxp-tja11xx.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0
+/* NXP TJA1100 BroadRReach PHY driver
+ *
+ * Copyright (C) 2022 Michael Trimarchi
+ * Copyright (C) 2022 Ariel D'Alessandro
+ * Copyright (C) 2018 Marek Vasut
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define PHY_ID_MASK0xfff0
+#define PHY_ID_TJA1100 0x0180dc40
+#define PHY_ID_TJA1101 0x0180dd00
+
+#define MII_ECTRL 17
+#define MII_ECTRL_LINK_CONTROL BIT(15)
+#define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11)
+#define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11)
+#define MII_ECTRL_POWER_MODE_NORMAL(0x3 << 11)
+#define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11)
+#define MII_ECTRL_CABLE_TEST BIT(5)
+#define MII_ECTRL_CONFIG_ENBIT(2)
+#define MII_ECTRL_WAKE_REQUEST BIT(0)
+
+#define MII_CFG1 18
+#define MII_CFG1_MASTER_SLAVE BIT(15)
+#define MII_CFG1_AUTO_OP BIT(14)
+#define MII_CFG1_SLEEP_CONFIRM BIT(6)
+#define MII_CFG1_LED_MODE_MASK GENMASK(5, 4)
+#define MII_CFG1_LED_MODE_LINKUP 0
+#define MII_CFG1_LED_ENABLEBIT(3)
+
+#define MII_CFG2 19
+#define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0)
+#define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3
+
+#define MII_INTSRC 21
+#define MII_INTSRC_LINK_FAIL BIT(10)
+#define MII_INTSRC_LINK_UP BIT(9)
+#define MII_INTSRC_MASK(MII_INTSRC_LINK_FAIL | \
+MII_INTSRC_LINK_UP)
+#define MII_INTSRC_UV_ERR BIT(3)
+#define MII_INTSRC_TEMP_ERRBIT(1)
+
+#define MII_INTEN 22
+#define MII_INTEN_LINK_FAILBIT(10)
+#define MII_INTEN_LINK_UP BIT(9)
+#define MII_INTEN_UV_ERR BIT(3)
+#define MII_INTEN_TEMP_ERR BIT(1)
+
+#define MII_COMMSTAT 23
+#define MII_COMMSTAT_LINK_UP BIT(15)
+#define MII_COMMSTAT_SQI_STATE GENMASK(7, 5)
+#define MII_COMMSTAT_SQI_MAX 7
+
+#define MII_GENSTAT24
+#define MII_GENSTAT_PLL_LOCKED BIT(14)
+
+#define MII_EXTSTAT25
+#define MII_EXTSTAT_SHORT_DETECT BIT(8)
+#define MII_EXTSTAT_OPEN_DETECTBIT(7)
+#define MII_EXTSTAT_POLARITY_DETECTBIT(6)
+
+#define MII_COMMCFG27
+#define MII_COMMCFG_AUTO_OPBIT(15)
+
+static inline int tja11xx_set_bits(struct phy_device *phydev, u32 regnum,
+ u16 val)
+{
+ return phy_set_bits_mmd(phydev, MDIO_DEVAD_NONE, regnum, val);
+}
+
+static inline int tja11xx_clear_bits(struct phy_device *phydev, u32 regnum,
+u16 val)
+{
+ return phy_clear_bits_mmd(phydev, MDIO_DEVAD_NONE, regnum, val);
+}
+
+static inline int tja11xx_read(struct phy_device *phydev, int regnum)
+{
+ return phy_read(phydev, MDIO_DEVAD_NONE, regnum);
+}
+
+static inline int tja11xx_modify(struct phy_device *phydev, int regnum,
+
[PATCH v5 5/7] net: phy: Add phy_modify() accessor
Add read-modify-write unlocked accessor for accessing a PHY register.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Ramon Fried
---
drivers/net/phy/phy.c | 20
include/phy.h | 2 ++
2 files changed, 22 insertions(+)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index e61c9b8a178..50448cf62c4 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -1110,3 +1110,23 @@ int phy_get_interface_by_name(const char *str)
return -1;
}
+
+/**
+ * phy_modify - Convenience function for modifying a given PHY register
+ * @phydev: the phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: register number to write
+ * @mask: bit mask of bits to clear
+ * @set: new value of bits set in mask to write to @regnum
+ */
+int phy_modify(struct phy_device *phydev, int devad, int regnum, u16 mask,
+ u16 set)
+{
+ int ret;
+
+ ret = phy_read(phydev, devad, regnum);
+ if (ret < 0)
+ return ret;
+
+ return phy_write(phydev, devad, regnum, (ret & ~mask) | set);
+}
diff --git a/include/phy.h b/include/phy.h
index 807c2932fda..1a30aee5421 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -526,6 +526,8 @@ int phy_config(struct phy_device *phydev);
int phy_shutdown(struct phy_device *phydev);
int phy_register(struct phy_driver *drv);
int phy_set_supported(struct phy_device *phydev, u32 max_speed);
+int phy_modify(struct phy_device *phydev, int devad, int regnum, u16 mask,
+ u16 set);
int genphy_config_aneg(struct phy_device *phydev);
int genphy_restart_aneg(struct phy_device *phydev);
int genphy_update_link(struct phy_device *phydev);
--
2.34.1
[PATCH v5 4/7] iopoll: Extend read_poll_timeout macro to support variable parameters
This macro currently supports only one parameter. Based on Linux iopoll,
let's extend read_poll_timeout common API to allow multiple variable
parameters.
Signed-off-by: Ariel D'Alessandro
---
arch/arm/mach-socfpga/reset_manager_s10.c | 20 +++-
drivers/mmc/rockchip_sdhci.c | 9 +
include/linux/iopoll.h| 12 ++--
3 files changed, 22 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
b/arch/arm/mach-socfpga/reset_manager_s10.c
index d2337bd4d62..f47fec10a0c 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -80,9 +80,9 @@ void socfpga_bridges_reset(int enable)
~0);
/* Poll until all idleack to 0 */
- read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLEACK, reg, !reg, 1000,
- 30);
+ read_poll_timeout(readl, reg, !reg, 1000, 30,
+ socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLEACK);
} else {
/* set idle request to all bridges */
writel(~0,
@@ -93,18 +93,20 @@ void socfpga_bridges_reset(int enable)
writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
/* Poll until all idleack to 1 */
- read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLEACK, reg,
+ read_poll_timeout(readl, reg,
reg == (SYSMGR_NOC_H2F_MSK |
SYSMGR_NOC_LWH2F_MSK),
- 1000, 30);
+ 1000, 30,
+ socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLEACK);
/* Poll until all idlestatus to 1 */
- read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLESTATUS, reg,
+ read_poll_timeout(readl, reg,
reg == (SYSMGR_NOC_H2F_MSK |
SYSMGR_NOC_LWH2F_MSK),
- 1000, 30);
+ 1000, 30,
+ socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLESTATUS);
/* Reset all bridges (except NOR DDR scheduler & F2S) */
setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index f3f9d83ba36..1fdc8415178 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -202,8 +202,8 @@ static void rk3399_emmc_phy_power_on(struct
rockchip_emmc_phy *phy, u32 clock)
/* REN Enable on STRB Line for HS400 */
writel(RK_CLRSETBITS(0, 1 << 9), >emmcphy_con[2]);
- read_poll_timeout(readl, >emmcphy_status, dllrdy,
- PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1, 5000);
+ read_poll_timeout(readl, dllrdy, PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1,
+ 5000, >emmcphy_status);
}
static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy)
@@ -328,8 +328,9 @@ static int rk3568_sdhci_emmc_set_clock(struct sdhci_host
*host, unsigned int clo
DWCMSHC_EMMC_DLL_START;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
- ret = read_poll_timeout(readl, host->ioaddr +
DWCMSHC_EMMC_DLL_STATUS0,
- val, DLL_LOCK_WO_TMOUT(val), 1, 500);
+ ret = read_poll_timeout(readl, val, DLL_LOCK_WO_TMOUT(val), 1,
+ 500,
+ host->ioaddr +
DWCMSHC_EMMC_DLL_STATUS0);
if (ret)
return ret;
diff --git a/include/linux/iopoll.h b/include/linux/iopoll.h
index 30cdea0cdc1..0ee2bddaa83 100644
--- a/include/linux/iopoll.h
+++ b/include/linux/iopoll.h
@@ -14,11 +14,11 @@
/**
* read_poll_timeout - Periodically poll an address until a condition is met
or a timeout occurs
* @op: accessor function (takes @addr as its only argument)
- * @addr: Address to poll
* @val: Variable to read the value into
* @cond: Break condition (usually involving @val)
* @sleep_us: Maximum time to sleep in us
* @timeout_us: Timeout in us, 0 means never timeout
+ * @args: arguments for @op poll
*
* Returns 0 on success and -ETIMEDOUT upon a timeout. In either
* case, the last read value at @addr is stored in @val.
@@ -26,15 +26,15 @@
* When available, you'll probably want to use one of the specialized
* macros defined bel
[PATCH v5 3/7] phy: nxp-c45-tja11xx: Rename functions to be c45 tja11xx specific
This driver supports NXP C45 TJA11XX PHYs, but there're also other NXP
TJA11XX PHYs. Let's rename functions in this driver to be c45 variant
specific, so further drivers can be introduced adding support for NXP
TJA11XX PHYs.
Signed-off-by: Ariel D'Alessandro
---
drivers/net/phy/nxp-c45-tja11xx.c | 6 +++---
drivers/net/phy/phy.c | 2 +-
include/phy.h | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/phy/nxp-c45-tja11xx.c
b/drivers/net/phy/nxp-c45-tja11xx.c
index f86e31f0d9e..a0f41fab698 100644
--- a/drivers/net/phy/nxp-c45-tja11xx.c
+++ b/drivers/net/phy/nxp-c45-tja11xx.c
@@ -330,7 +330,7 @@ static int nxp_c45_probe(struct phy_device *phydev)
return 0;
}
-static struct phy_driver nxp_tja11xx = {
+static struct phy_driver nxp_c45_tja11xx = {
.name = "NXP C45 TJA1103",
.uid = PHY_ID_TJA_1103,
.mask = 0xf0,
@@ -341,8 +341,8 @@ static struct phy_driver nxp_tja11xx = {
.shutdown = _shutdown,
};
-int phy_nxp_tja11xx_init(void)
+int phy_nxp_c45_tja11xx_init(void)
{
- phy_register(_tja11xx);
+ phy_register(_c45_tja11xx);
return 0;
}
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index d4731860f73..e61c9b8a178 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -530,7 +530,7 @@ int phy_init(void)
phy_natsemi_init();
#endif
#ifdef CONFIG_NXP_C45_TJA11XX_PHY
- phy_nxp_tja11xx_init();
+ phy_nxp_c45_tja11xx_init();
#endif
#ifdef CONFIG_PHY_REALTEK
phy_realtek_init();
diff --git a/include/phy.h b/include/phy.h
index 5e3da4b01b6..807c2932fda 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -553,7 +553,7 @@ int phy_micrel_ksz8xxx_init(void);
int phy_micrel_ksz90x1_init(void);
int phy_meson_gxl_init(void);
int phy_natsemi_init(void);
-int phy_nxp_tja11xx_init(void);
+int phy_nxp_c45_tja11xx_init(void);
int phy_realtek_init(void);
int phy_smsc_init(void);
int phy_teranetics_init(void);
--
2.34.1
[PATCH v5 2/7] imx8m: add init_nand_clk
From: Michael Trimarchi Add init_nand_clk to enable gpmi nand clock. Since i.MX8M not use CCF, so we still use legacy mode to configure the clock. Signed-off-by: Michael Trimarchi --- arch/arm/include/asm/arch-imx8m/clock.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h index c705dfdf460..e4433763bc4 100644 --- a/arch/arm/include/asm/arch-imx8m/clock.h +++ b/arch/arm/include/asm/arch-imx8m/clock.h @@ -256,6 +256,7 @@ u32 imx_get_fecclk(void); u32 imx_get_uartclk(void); int clock_init(void); void init_clk_usdhc(u32 index); +void init_nand_clk(void); void init_uart_clk(u32 index); void init_usb_clk(void); void init_wdog_clk(void); -- 2.34.1
[PATCH v5 1/7] imx8m: add regs used by GPMI
From: Michael Trimarchi Add regs used by GPMI Signed-off-by: Michael Trimarchi Signed-off-by: Ariel D'Alessandro Reviewed-by: Fabio Estevam --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 45d95a7c197..fb665412465 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -58,6 +58,13 @@ #define SRC_DDRC_RCR_ADDR 0x30391000 #define SRC_DDRC2_RCR_ADDR 0x30391004 +#define APBH_DMA_ARB_BASE_ADDR 0x3300 +#define APBH_DMA_ARB_END_ADDR 0x33007FFF +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR + +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) + #define DDRC_DDR_SS_GPR0 0x3d00 #define DDRC_IPS_BASE_ADDR(X) (0x3d40 + ((X) * 0x200)) #define DDR_CSD1_BASE_ADDR 0x4000 -- 2.34.1
[PATCH v5 0/7] imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
Introduce BSH SystemMaster (SMM) S2 board family, which consists of: iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards. This patchset also adds support for NXP TJA11xx Ethernet PHYs. Changes in v5: * Export init_nand_clk() function. * Drop __ASSEMBLY__ in ddr config. * Init nand clk in spl, required when usb boot is forced. * Migrate symbols to defconfig. Changes in v4: * Add new Reviewed-by tags to patches. * Set atf-bl31 blob type in device tree binman configuration. Changes in v3: * Added nxp-c45-tja11xx driver. * Added ethernet support to iMX8MN BSH SMM S2 boards. Changes in v2: * Properly added MAINTAINERS entry. * Fixed binman configuration. * Picked device tree from kernel. * Removed CONFIG_SPL_BUILD anti-pattern in board config. * Removed downstream stuff in bootargs. * Added board documentation. Ariel D'Alessandro (4): phy: nxp-c45-tja11xx: Rename functions to be c45 tja11xx specific iopoll: Extend read_poll_timeout macro to support variable parameters net: phy: Add phy_modify() accessor bsh: imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards Michael Trimarchi (3): imx8m: add regs used by GPMI imx8m: add init_nand_clk net: phy: nxp-tja11xx: Add NXP TJA11xx PHY driver arch/arm/dts/Makefile | 2 + arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi| 423 .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 225 + arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi| 15 + arch/arm/dts/imx8mn-bsh-smm-s2.dts| 48 + arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi | 15 + arch/arm/dts/imx8mn-bsh-smm-s2pro.dts | 80 ++ arch/arm/include/asm/arch-imx8m/clock.h | 1 + arch/arm/include/asm/arch-imx8m/imx-regs.h| 7 + arch/arm/mach-imx/imx8m/Kconfig | 15 + arch/arm/mach-socfpga/reset_manager_s10.c | 20 +- board/bsh/imx8mn_smm_s2/Kconfig | 49 + board/bsh/imx8mn_smm_s2/MAINTAINERS | 8 + board/bsh/imx8mn_smm_s2/Makefile | 13 + board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c | 941 ++ board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c | 941 ++ board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c | 23 + board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg | 8 + board/bsh/imx8mn_smm_s2/spl.c | 97 ++ configs/imx8mn_bsh_smm_s2_defconfig | 96 ++ configs/imx8mn_bsh_smm_s2pro_defconfig| 93 ++ doc/board/bsh/imx8mn_bsh_smm_s2.rst | 62 ++ doc/board/bsh/index.rst | 9 + doc/board/index.rst | 1 + drivers/mmc/rockchip_sdhci.c | 9 +- drivers/net/phy/Kconfig | 5 + drivers/net/phy/Makefile | 1 + drivers/net/phy/nxp-c45-tja11xx.c | 6 +- drivers/net/phy/nxp-tja11xx.c | 277 ++ drivers/net/phy/phy.c | 23 + include/configs/imx8mn_bsh_smm_s2.h | 51 + include/configs/imx8mn_bsh_smm_s2_common.h| 59 ++ include/configs/imx8mn_bsh_smm_s2pro.h| 35 + include/linux/iopoll.h| 12 +- include/phy.h | 3 + 35 files changed, 3651 insertions(+), 22 deletions(-) create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2.dts create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro.dts create mode 100644 board/bsh/imx8mn_smm_s2/Kconfig create mode 100644 board/bsh/imx8mn_smm_s2/MAINTAINERS create mode 100644 board/bsh/imx8mn_smm_s2/Makefile create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c create mode 100644 board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c create mode 100644 board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg create mode 100644 board/bsh/imx8mn_smm_s2/spl.c create mode 100644 configs/imx8mn_bsh_smm_s2_defconfig create mode 100644 configs/imx8mn_bsh_smm_s2pro_defconfig create mode 100644 doc/board/bsh/imx8mn_bsh_smm_s2.rst create mode 100644 doc/board/bsh/index.rst create mode 100644 drivers/net/phy/nxp-tja11xx.c create mode 100644 include/configs/imx8mn_bsh_smm_s2.h create mode 100644 include/configs/imx8mn_bsh_smm_s2_common.h create mode 100644 include/configs/imx8mn_bsh_smm_s2pro.h -- 2.34.1
Re: [PATCH v4 0/6] imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
Hi Stefano, On 4/11/22 12:56, Stefano Babic wrote: > Hi Ariel, > > On 11.04.22 13:56, Ariel D'Alessandro wrote: >> Hi, >> >> Gentle re-ping. What's blocking this? >> This has been reviewed and queued for some time already. Please, be >> clear on the status or what's the plan for this patchset. >> > > After first run, build is blocked by CI due to CONFIG_ that should be se > in configs/imx8mn_bsh_smm_s2_defconfig instead of > include/configs/imx8mn_bsh_smm_s2_common.h. I can recognize at least > CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (and family), but it looks like > there are some more. > > See error here: > > https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/420878 Thanks! Fixed, will send patchset v5 right away. Regards, Ariel
Re: [PATCH v4 0/6] imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
Hi, Gentle re-ping. What's blocking this? This has been reviewed and queued for some time already. Please, be clear on the status or what's the plan for this patchset. Regards, Ariel On 4/5/22 19:46, Tom Rini wrote: > Yes, there's a lot of iMX things I would like to see a PR come in for > soon. > > On Tue, Apr 05, 2022 at 05:44:47PM -0300, Ariel D'Alessandro wrote: >> Hi Tom, Stefano, >> >> Gentle ping :-) Can we get this merged now? >> >> On 3/4/22 09:22, Ariel D'Alessandro wrote: >>> Introduce BSH SystemMaster (SMM) S2 board family, which consists of: >>> iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards. >>> >>> This patchset also adds support for NXP TJA11xx Ethernet PHYs. >>> >>> Changes in v4: >>> * Add new Reviewed-by tags to patches. >>> * Set atf-bl31 blob type in device tree binman configuration. >>> >>> Changes in v3: >>> * Added nxp-c45-tja11xx driver. >>> * Added ethernet support to iMX8MN BSH SMM S2 boards. >>> >>> Changes in v2: >>> * Properly added MAINTAINERS entry. >>> * Fixed binman configuration. >>> * Picked device tree from kernel. >>> * Removed CONFIG_SPL_BUILD anti-pattern in board config. >>> * Removed downstream stuff in bootargs. >>> * Added board documentation. >>> >>> Ariel D'Alessandro (4): >>> phy: nxp-c45-tja11xx: Rename functions to be c45 tja11xx specific >>> iopoll: Extend read_poll_timeout macro to support variable parameters >>> net: phy: Add phy_modify() accessor >>> bsh: imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards >>> >>> Michael Trimarchi (2): >>> imx8m: add regs used by GPMI >>> net: phy: nxp-tja11xx: Add NXP TJA11xx PHY driver >>> >>> arch/arm/dts/Makefile | 2 + >>> arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi| 423 >>> .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 225 + >>> arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi| 15 + >>> arch/arm/dts/imx8mn-bsh-smm-s2.dts| 48 + >>> arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi | 15 + >>> arch/arm/dts/imx8mn-bsh-smm-s2pro.dts | 80 ++ >>> arch/arm/include/asm/arch-imx8m/imx-regs.h| 7 + >>> arch/arm/mach-imx/imx8m/Kconfig | 15 + >>> arch/arm/mach-socfpga/reset_manager_s10.c | 20 +- >>> board/bsh/imx8mn_smm_s2/Kconfig | 49 + >>> board/bsh/imx8mn_smm_s2/MAINTAINERS | 8 + >>> board/bsh/imx8mn_smm_s2/Makefile | 13 + >>> board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c | 941 ++ >>> board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c | 941 ++ >>> board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c | 23 + >>> board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg | 10 + >>> board/bsh/imx8mn_smm_s2/spl.c | 93 ++ >>> configs/imx8mn_bsh_smm_s2_defconfig | 97 ++ >>> configs/imx8mn_bsh_smm_s2pro_defconfig| 94 ++ >>> doc/board/bsh/imx8mn_bsh_smm_s2.rst | 62 ++ >>> doc/board/bsh/index.rst | 9 + >>> doc/board/index.rst | 1 + >>> drivers/mmc/rockchip_sdhci.c | 9 +- >>> drivers/net/phy/Kconfig | 5 + >>> drivers/net/phy/Makefile | 1 + >>> drivers/net/phy/nxp-c45-tja11xx.c | 6 +- >>> drivers/net/phy/nxp-tja11xx.c | 277 ++ >>> drivers/net/phy/phy.c | 23 + >>> include/configs/imx8mn_bsh_smm_s2.h | 52 + >>> include/configs/imx8mn_bsh_smm_s2_common.h| 62 ++ >>> include/configs/imx8mn_bsh_smm_s2pro.h| 35 + >>> include/linux/iopoll.h| 12 +- >>> include/phy.h | 3 + >>> 34 files changed, 3654 insertions(+), 22 deletions(-) >>> create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi >>> create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi >>> create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi >>> create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2.dts >>> create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi >>> create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro.dts >>> create mode 100644 board/bsh/imx8mn_smm_s2/Kconfig >>> create mode 100644 board/bsh/imx8mn_smm_s2/MAINTAINERS >>> create mode 100644 b
Re: [PATCH v4 0/6] imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
Hi Tom, Stefano, Gentle ping :-) Can we get this merged now? On 3/4/22 09:22, Ariel D'Alessandro wrote: > Introduce BSH SystemMaster (SMM) S2 board family, which consists of: > iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards. > > This patchset also adds support for NXP TJA11xx Ethernet PHYs. > > Changes in v4: > * Add new Reviewed-by tags to patches. > * Set atf-bl31 blob type in device tree binman configuration. > > Changes in v3: > * Added nxp-c45-tja11xx driver. > * Added ethernet support to iMX8MN BSH SMM S2 boards. > > Changes in v2: > * Properly added MAINTAINERS entry. > * Fixed binman configuration. > * Picked device tree from kernel. > * Removed CONFIG_SPL_BUILD anti-pattern in board config. > * Removed downstream stuff in bootargs. > * Added board documentation. > > Ariel D'Alessandro (4): > phy: nxp-c45-tja11xx: Rename functions to be c45 tja11xx specific > iopoll: Extend read_poll_timeout macro to support variable parameters > net: phy: Add phy_modify() accessor > bsh: imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards > > Michael Trimarchi (2): > imx8m: add regs used by GPMI > net: phy: nxp-tja11xx: Add NXP TJA11xx PHY driver > > arch/arm/dts/Makefile | 2 + > arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi| 423 > .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 225 + > arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi| 15 + > arch/arm/dts/imx8mn-bsh-smm-s2.dts| 48 + > arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi | 15 + > arch/arm/dts/imx8mn-bsh-smm-s2pro.dts | 80 ++ > arch/arm/include/asm/arch-imx8m/imx-regs.h| 7 + > arch/arm/mach-imx/imx8m/Kconfig | 15 + > arch/arm/mach-socfpga/reset_manager_s10.c | 20 +- > board/bsh/imx8mn_smm_s2/Kconfig | 49 + > board/bsh/imx8mn_smm_s2/MAINTAINERS | 8 + > board/bsh/imx8mn_smm_s2/Makefile | 13 + > board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c | 941 ++ > board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c | 941 ++ > board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c | 23 + > board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg | 10 + > board/bsh/imx8mn_smm_s2/spl.c | 93 ++ > configs/imx8mn_bsh_smm_s2_defconfig | 97 ++ > configs/imx8mn_bsh_smm_s2pro_defconfig| 94 ++ > doc/board/bsh/imx8mn_bsh_smm_s2.rst | 62 ++ > doc/board/bsh/index.rst | 9 + > doc/board/index.rst | 1 + > drivers/mmc/rockchip_sdhci.c | 9 +- > drivers/net/phy/Kconfig | 5 + > drivers/net/phy/Makefile | 1 + > drivers/net/phy/nxp-c45-tja11xx.c | 6 +- > drivers/net/phy/nxp-tja11xx.c | 277 ++ > drivers/net/phy/phy.c | 23 + > include/configs/imx8mn_bsh_smm_s2.h | 52 + > include/configs/imx8mn_bsh_smm_s2_common.h| 62 ++ > include/configs/imx8mn_bsh_smm_s2pro.h| 35 + > include/linux/iopoll.h| 12 +- > include/phy.h | 3 + > 34 files changed, 3654 insertions(+), 22 deletions(-) > create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi > create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi > create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi > create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2.dts > create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi > create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro.dts > create mode 100644 board/bsh/imx8mn_smm_s2/Kconfig > create mode 100644 board/bsh/imx8mn_smm_s2/MAINTAINERS > create mode 100644 board/bsh/imx8mn_smm_s2/Makefile > create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c > create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c > create mode 100644 board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c > create mode 100644 board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg > create mode 100644 board/bsh/imx8mn_smm_s2/spl.c > create mode 100644 configs/imx8mn_bsh_smm_s2_defconfig > create mode 100644 configs/imx8mn_bsh_smm_s2pro_defconfig > create mode 100644 doc/board/bsh/imx8mn_bsh_smm_s2.rst > create mode 100644 doc/board/bsh/index.rst > create mode 100644 drivers/net/phy/nxp-tja11xx.c > create mode 100644 include/configs/imx8mn_bsh_smm_s2.h > create mode 100644 include/configs/imx8mn_bsh_smm_s2_common.h > create mode 100644 include/configs/imx8mn_bsh_smm_s2pro.h >
[PATCH v4 6/6] bsh: imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
Introduce BSH SystemMaster (SMM) S2 board family, which consists of:
iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards.
Add support for iMX8MN BSH SMM S2 board:
- 256 MiB DDR3 RAM
- 512MiB Nand
- USBOTG1 peripheral - fastboot.
- 100Mbit Ethernet
Add support for iMX8MN BSH SMM S2 PRO board:
- 512 MiB DDR3 RAM
- 8 GiB eMMC
- USBOTG1 peripheral - fastboot.
- 100Mbit Ethernet
Signed-off-by: Ariel D'Alessandro
Signed-off-by: Michael Trimarchi
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi| 423
.../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 225 +
arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi| 15 +
arch/arm/dts/imx8mn-bsh-smm-s2.dts| 48 +
arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi | 15 +
arch/arm/dts/imx8mn-bsh-smm-s2pro.dts | 80 ++
arch/arm/mach-imx/imx8m/Kconfig | 15 +
board/bsh/imx8mn_smm_s2/Kconfig | 49 +
board/bsh/imx8mn_smm_s2/MAINTAINERS | 8 +
board/bsh/imx8mn_smm_s2/Makefile | 13 +
board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c | 941 ++
board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c | 941 ++
board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c | 23 +
board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg | 10 +
board/bsh/imx8mn_smm_s2/spl.c | 93 ++
configs/imx8mn_bsh_smm_s2_defconfig | 97 ++
configs/imx8mn_bsh_smm_s2pro_defconfig| 94 ++
doc/board/bsh/imx8mn_bsh_smm_s2.rst | 62 ++
doc/board/bsh/index.rst | 9 +
doc/board/index.rst | 1 +
include/configs/imx8mn_bsh_smm_s2.h | 52 +
include/configs/imx8mn_bsh_smm_s2_common.h| 62 ++
include/configs/imx8mn_bsh_smm_s2pro.h| 35 +
24 files changed, 3313 insertions(+)
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2.dts
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro.dts
create mode 100644 board/bsh/imx8mn_smm_s2/Kconfig
create mode 100644 board/bsh/imx8mn_smm_s2/MAINTAINERS
create mode 100644 board/bsh/imx8mn_smm_s2/Makefile
create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c
create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c
create mode 100644 board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c
create mode 100644 board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg
create mode 100644 board/bsh/imx8mn_smm_s2/spl.c
create mode 100644 configs/imx8mn_bsh_smm_s2_defconfig
create mode 100644 configs/imx8mn_bsh_smm_s2pro_defconfig
create mode 100644 doc/board/bsh/imx8mn_bsh_smm_s2.rst
create mode 100644 doc/board/bsh/index.rst
create mode 100644 include/configs/imx8mn_bsh_smm_s2.h
create mode 100644 include/configs/imx8mn_bsh_smm_s2_common.h
create mode 100644 include/configs/imx8mn_bsh_smm_s2pro.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 960f1a9fd4d..08881244ec6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -911,6 +911,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-venice-gw7902.dtb \
imx8mm-verdin.dtb \
phycore-imx8mm.dtb \
+ imx8mn-bsh-smm-s2.dtb \
+ imx8mn-bsh-smm-s2pro.dtb \
imx8mn-ddr4-evk.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \
diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
b/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
new file mode 100644
index 000..184c715bd38
--- /dev/null
+++ b/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
@@ -0,0 +1,423 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ * Copyright 2021 BSH Hausgeraete GmbH
+ */
+
+#include "imx8mn.dtsi"
+
+/ {
+ chosen {
+ stdout-path =
+ };
+
+ fec_supply: fec_supply_en {
+ compatible = "regulator-fixed";
+ regulator-name = "tja1101_en";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = < 20 GPIO_ACTIVE_HIGH>;
+ vin-supply = <_reg>;
+ enable-active-high;
+ };
+
+ usdhc2_pwrseq: usdhc2_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <_usdhc2_pwrseq>;
+ reset-gpios = < 27 GPIO_ACTIVE_LOW>;
+ };
+};
+
+_0 {
+ cpu-supply = <_reg>;
+};
+
+_1 {
+ cpu-supply = <_reg>;
+};
+
+_2 {
+ cpu-supply = <_reg>;
+};
+
+_3 {
+ cpu-supply = <_reg>;
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_espi2>;
+ status = "okay";
+
[PATCH v4 5/6] net: phy: nxp-tja11xx: Add NXP TJA11xx PHY driver
From: Michael Trimarchi
Add driver for the NXP TJA1100 and TJA1101 PHYs. These PHYs are special
BroadRReach 100BaseT1 PHYs used in automotive.
Signed-off-by: Michael Trimarchi
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Ramon Fried
---
drivers/net/phy/Kconfig | 5 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/nxp-tja11xx.c | 277 ++
drivers/net/phy/phy.c | 3 +
include/phy.h | 1 +
5 files changed, 287 insertions(+)
create mode 100644 drivers/net/phy/nxp-tja11xx.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 4f8d33ce8fd..8de6130113c 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -211,6 +211,11 @@ config PHY_NXP_C45_TJA11XX
Enable support for NXP C45 TJA11XX PHYs.
Currently supports only the TJA1103 PHY.
+config PHY_NXP_TJA11XX
+ bool "NXP TJA11XX Ethernet PHYs support"
+ help
+ Currently supports the NXP TJA1100 and TJA1101 PHY.
+
config PHY_REALTEK
bool "Realtek Ethernet PHYs support"
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 77f7f606215..7cfbab0b5c8 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o
obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o
+obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o
obj-$(CONFIG_PHY_REALTEK) += realtek.o
obj-$(CONFIG_PHY_SMSC) += smsc.o
obj-$(CONFIG_PHY_TERANETICS) += teranetics.o
diff --git a/drivers/net/phy/nxp-tja11xx.c b/drivers/net/phy/nxp-tja11xx.c
new file mode 100644
index 000..30dec5e605b
--- /dev/null
+++ b/drivers/net/phy/nxp-tja11xx.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0
+/* NXP TJA1100 BroadRReach PHY driver
+ *
+ * Copyright (C) 2022 Michael Trimarchi
+ * Copyright (C) 2022 Ariel D'Alessandro
+ * Copyright (C) 2018 Marek Vasut
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define PHY_ID_MASK0xfff0
+#define PHY_ID_TJA1100 0x0180dc40
+#define PHY_ID_TJA1101 0x0180dd00
+
+#define MII_ECTRL 17
+#define MII_ECTRL_LINK_CONTROL BIT(15)
+#define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11)
+#define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11)
+#define MII_ECTRL_POWER_MODE_NORMAL(0x3 << 11)
+#define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11)
+#define MII_ECTRL_CABLE_TEST BIT(5)
+#define MII_ECTRL_CONFIG_ENBIT(2)
+#define MII_ECTRL_WAKE_REQUEST BIT(0)
+
+#define MII_CFG1 18
+#define MII_CFG1_MASTER_SLAVE BIT(15)
+#define MII_CFG1_AUTO_OP BIT(14)
+#define MII_CFG1_SLEEP_CONFIRM BIT(6)
+#define MII_CFG1_LED_MODE_MASK GENMASK(5, 4)
+#define MII_CFG1_LED_MODE_LINKUP 0
+#define MII_CFG1_LED_ENABLEBIT(3)
+
+#define MII_CFG2 19
+#define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0)
+#define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3
+
+#define MII_INTSRC 21
+#define MII_INTSRC_LINK_FAIL BIT(10)
+#define MII_INTSRC_LINK_UP BIT(9)
+#define MII_INTSRC_MASK(MII_INTSRC_LINK_FAIL | \
+MII_INTSRC_LINK_UP)
+#define MII_INTSRC_UV_ERR BIT(3)
+#define MII_INTSRC_TEMP_ERRBIT(1)
+
+#define MII_INTEN 22
+#define MII_INTEN_LINK_FAILBIT(10)
+#define MII_INTEN_LINK_UP BIT(9)
+#define MII_INTEN_UV_ERR BIT(3)
+#define MII_INTEN_TEMP_ERR BIT(1)
+
+#define MII_COMMSTAT 23
+#define MII_COMMSTAT_LINK_UP BIT(15)
+#define MII_COMMSTAT_SQI_STATE GENMASK(7, 5)
+#define MII_COMMSTAT_SQI_MAX 7
+
+#define MII_GENSTAT24
+#define MII_GENSTAT_PLL_LOCKED BIT(14)
+
+#define MII_EXTSTAT25
+#define MII_EXTSTAT_SHORT_DETECT BIT(8)
+#define MII_EXTSTAT_OPEN_DETECTBIT(7)
+#define MII_EXTSTAT_POLARITY_DETECTBIT(6)
+
+#define MII_COMMCFG27
+#define MII_COMMCFG_AUTO_OPBIT(15)
+
+static inline int tja11xx_set_bits(struct phy_device *phydev, u32 regnum,
+ u16 val)
+{
+ return phy_set_bits_mmd(phydev, MDIO_DEVAD_NONE, regnum, val);
+}
+
+static inline int tja11xx_clear_bits(struct phy_device *phydev, u32 regnum,
+u16 val)
+{
+ return phy_clear_bits_mmd(phydev, MDIO_DEVAD_NONE, regnum, val);
+}
+
+static inline int tja11xx_read(struct phy_device *phydev, int regnum)
+{
+ return phy_read(phydev, MDIO_DEVAD_NONE, regnum);
+}
+
+static inline int tja11xx_modify(struct phy_device *phydev, int regnum,
+
[PATCH v4 4/6] net: phy: Add phy_modify() accessor
Add read-modify-write unlocked accessor for accessing a PHY register.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Ramon Fried
---
drivers/net/phy/phy.c | 20
include/phy.h | 2 ++
2 files changed, 22 insertions(+)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 9935e40fcdc..b73361d87d9 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -1105,3 +1105,23 @@ int phy_get_interface_by_name(const char *str)
return -1;
}
+
+/**
+ * phy_modify - Convenience function for modifying a given PHY register
+ * @phydev: the phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: register number to write
+ * @mask: bit mask of bits to clear
+ * @set: new value of bits set in mask to write to @regnum
+ */
+int phy_modify(struct phy_device *phydev, int devad, int regnum, u16 mask,
+ u16 set)
+{
+ int ret;
+
+ ret = phy_read(phydev, devad, regnum);
+ if (ret < 0)
+ return ret;
+
+ return phy_write(phydev, devad, regnum, (ret & ~mask) | set);
+}
diff --git a/include/phy.h b/include/phy.h
index d4035fdef2b..2dd2e02ab5d 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -500,6 +500,8 @@ int phy_config(struct phy_device *phydev);
int phy_shutdown(struct phy_device *phydev);
int phy_register(struct phy_driver *drv);
int phy_set_supported(struct phy_device *phydev, u32 max_speed);
+int phy_modify(struct phy_device *phydev, int devad, int regnum, u16 mask,
+ u16 set);
int genphy_config_aneg(struct phy_device *phydev);
int genphy_restart_aneg(struct phy_device *phydev);
int genphy_update_link(struct phy_device *phydev);
--
2.34.1
[PATCH v4 3/6] iopoll: Extend read_poll_timeout macro to support variable parameters
This macro currently supports only one parameter. Based on Linux iopoll,
let's extend read_poll_timeout common API to allow multiple variable
parameters.
Signed-off-by: Ariel D'Alessandro
---
arch/arm/mach-socfpga/reset_manager_s10.c | 20 +++-
drivers/mmc/rockchip_sdhci.c | 9 +
include/linux/iopoll.h| 12 ++--
3 files changed, 22 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
b/arch/arm/mach-socfpga/reset_manager_s10.c
index d2337bd4d62..f47fec10a0c 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -80,9 +80,9 @@ void socfpga_bridges_reset(int enable)
~0);
/* Poll until all idleack to 0 */
- read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLEACK, reg, !reg, 1000,
- 30);
+ read_poll_timeout(readl, reg, !reg, 1000, 30,
+ socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLEACK);
} else {
/* set idle request to all bridges */
writel(~0,
@@ -93,18 +93,20 @@ void socfpga_bridges_reset(int enable)
writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
/* Poll until all idleack to 1 */
- read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLEACK, reg,
+ read_poll_timeout(readl, reg,
reg == (SYSMGR_NOC_H2F_MSK |
SYSMGR_NOC_LWH2F_MSK),
- 1000, 30);
+ 1000, 30,
+ socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLEACK);
/* Poll until all idlestatus to 1 */
- read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLESTATUS, reg,
+ read_poll_timeout(readl, reg,
reg == (SYSMGR_NOC_H2F_MSK |
SYSMGR_NOC_LWH2F_MSK),
- 1000, 30);
+ 1000, 30,
+ socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLESTATUS);
/* Reset all bridges (except NOR DDR scheduler & F2S) */
setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 278473899c7..87f14b0ee9c 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -146,8 +146,8 @@ static void rk3399_emmc_phy_power_on(struct
rockchip_emmc_phy *phy, u32 clock)
/* REN Enable on STRB Line for HS400 */
writel(RK_CLRSETBITS(0, 1 << 9), >emmcphy_con[2]);
- read_poll_timeout(readl, >emmcphy_status, dllrdy,
- PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1, 5000);
+ read_poll_timeout(readl, dllrdy, PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1,
+ 5000, >emmcphy_status);
}
static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy)
@@ -235,8 +235,9 @@ static int rk3568_sdhci_emmc_set_clock(struct sdhci_host
*host, unsigned int clo
DWCMSHC_EMMC_DLL_START;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
- ret = read_poll_timeout(readl, host->ioaddr +
DWCMSHC_EMMC_DLL_STATUS0,
- val, DLL_LOCK_WO_TMOUT(val), 1, 500);
+ ret = read_poll_timeout(readl, val, DLL_LOCK_WO_TMOUT(val), 1,
+ 500,
+ host->ioaddr +
DWCMSHC_EMMC_DLL_STATUS0);
if (ret)
return ret;
diff --git a/include/linux/iopoll.h b/include/linux/iopoll.h
index 30cdea0cdc1..0ee2bddaa83 100644
--- a/include/linux/iopoll.h
+++ b/include/linux/iopoll.h
@@ -14,11 +14,11 @@
/**
* read_poll_timeout - Periodically poll an address until a condition is met
or a timeout occurs
* @op: accessor function (takes @addr as its only argument)
- * @addr: Address to poll
* @val: Variable to read the value into
* @cond: Break condition (usually involving @val)
* @sleep_us: Maximum time to sleep in us
* @timeout_us: Timeout in us, 0 means never timeout
+ * @args: arguments for @op poll
*
* Returns 0 on success and -ETIMEDOUT upon a timeout. In either
* case, the last read value at @addr is stored in @val.
@@ -26,15 +26,15 @@
* When available, you'll probably want to use one of the specialized
* macros defined bel
[PATCH v4 2/6] phy: nxp-c45-tja11xx: Rename functions to be c45 tja11xx specific
This driver supports NXP C45 TJA11XX PHYs, but there're also other NXP
TJA11XX PHYs. Let's rename functions in this driver to be c45 variant
specific, so further drivers can be introduced adding support for NXP
TJA11XX PHYs.
Signed-off-by: Ariel D'Alessandro
---
drivers/net/phy/nxp-c45-tja11xx.c | 6 +++---
drivers/net/phy/phy.c | 2 +-
include/phy.h | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/phy/nxp-c45-tja11xx.c
b/drivers/net/phy/nxp-c45-tja11xx.c
index f86e31f0d9e..a0f41fab698 100644
--- a/drivers/net/phy/nxp-c45-tja11xx.c
+++ b/drivers/net/phy/nxp-c45-tja11xx.c
@@ -330,7 +330,7 @@ static int nxp_c45_probe(struct phy_device *phydev)
return 0;
}
-static struct phy_driver nxp_tja11xx = {
+static struct phy_driver nxp_c45_tja11xx = {
.name = "NXP C45 TJA1103",
.uid = PHY_ID_TJA_1103,
.mask = 0xf0,
@@ -341,8 +341,8 @@ static struct phy_driver nxp_tja11xx = {
.shutdown = _shutdown,
};
-int phy_nxp_tja11xx_init(void)
+int phy_nxp_c45_tja11xx_init(void)
{
- phy_register(_tja11xx);
+ phy_register(_c45_tja11xx);
return 0;
}
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index c9fc20855ba..9935e40fcdc 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -530,7 +530,7 @@ int phy_init(void)
phy_natsemi_init();
#endif
#ifdef CONFIG_NXP_C45_TJA11XX_PHY
- phy_nxp_tja11xx_init();
+ phy_nxp_c45_tja11xx_init();
#endif
#ifdef CONFIG_PHY_REALTEK
phy_realtek_init();
diff --git a/include/phy.h b/include/phy.h
index c66fd43ea88..d4035fdef2b 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -527,7 +527,7 @@ int phy_micrel_ksz8xxx_init(void);
int phy_micrel_ksz90x1_init(void);
int phy_meson_gxl_init(void);
int phy_natsemi_init(void);
-int phy_nxp_tja11xx_init(void);
+int phy_nxp_c45_tja11xx_init(void);
int phy_realtek_init(void);
int phy_smsc_init(void);
int phy_teranetics_init(void);
--
2.34.1
[PATCH v4 1/6] imx8m: add regs used by GPMI
From: Michael Trimarchi Add regs used by GPMI Signed-off-by: Michael Trimarchi Signed-off-by: Ariel D'Alessandro Reviewed-by: Fabio Estevam --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 45d95a7c197..fb665412465 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -58,6 +58,13 @@ #define SRC_DDRC_RCR_ADDR 0x30391000 #define SRC_DDRC2_RCR_ADDR 0x30391004 +#define APBH_DMA_ARB_BASE_ADDR 0x3300 +#define APBH_DMA_ARB_END_ADDR 0x33007FFF +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR + +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) + #define DDRC_DDR_SS_GPR0 0x3d00 #define DDRC_IPS_BASE_ADDR(X) (0x3d40 + ((X) * 0x200)) #define DDR_CSD1_BASE_ADDR 0x4000 -- 2.34.1
[PATCH v4 0/6] imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
Introduce BSH SystemMaster (SMM) S2 board family, which consists of: iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards. This patchset also adds support for NXP TJA11xx Ethernet PHYs. Changes in v4: * Add new Reviewed-by tags to patches. * Set atf-bl31 blob type in device tree binman configuration. Changes in v3: * Added nxp-c45-tja11xx driver. * Added ethernet support to iMX8MN BSH SMM S2 boards. Changes in v2: * Properly added MAINTAINERS entry. * Fixed binman configuration. * Picked device tree from kernel. * Removed CONFIG_SPL_BUILD anti-pattern in board config. * Removed downstream stuff in bootargs. * Added board documentation. Ariel D'Alessandro (4): phy: nxp-c45-tja11xx: Rename functions to be c45 tja11xx specific iopoll: Extend read_poll_timeout macro to support variable parameters net: phy: Add phy_modify() accessor bsh: imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards Michael Trimarchi (2): imx8m: add regs used by GPMI net: phy: nxp-tja11xx: Add NXP TJA11xx PHY driver arch/arm/dts/Makefile | 2 + arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi| 423 .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 225 + arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi| 15 + arch/arm/dts/imx8mn-bsh-smm-s2.dts| 48 + arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi | 15 + arch/arm/dts/imx8mn-bsh-smm-s2pro.dts | 80 ++ arch/arm/include/asm/arch-imx8m/imx-regs.h| 7 + arch/arm/mach-imx/imx8m/Kconfig | 15 + arch/arm/mach-socfpga/reset_manager_s10.c | 20 +- board/bsh/imx8mn_smm_s2/Kconfig | 49 + board/bsh/imx8mn_smm_s2/MAINTAINERS | 8 + board/bsh/imx8mn_smm_s2/Makefile | 13 + board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c | 941 ++ board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c | 941 ++ board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c | 23 + board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg | 10 + board/bsh/imx8mn_smm_s2/spl.c | 93 ++ configs/imx8mn_bsh_smm_s2_defconfig | 97 ++ configs/imx8mn_bsh_smm_s2pro_defconfig| 94 ++ doc/board/bsh/imx8mn_bsh_smm_s2.rst | 62 ++ doc/board/bsh/index.rst | 9 + doc/board/index.rst | 1 + drivers/mmc/rockchip_sdhci.c | 9 +- drivers/net/phy/Kconfig | 5 + drivers/net/phy/Makefile | 1 + drivers/net/phy/nxp-c45-tja11xx.c | 6 +- drivers/net/phy/nxp-tja11xx.c | 277 ++ drivers/net/phy/phy.c | 23 + include/configs/imx8mn_bsh_smm_s2.h | 52 + include/configs/imx8mn_bsh_smm_s2_common.h| 62 ++ include/configs/imx8mn_bsh_smm_s2pro.h| 35 + include/linux/iopoll.h| 12 +- include/phy.h | 3 + 34 files changed, 3654 insertions(+), 22 deletions(-) create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2.dts create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro.dts create mode 100644 board/bsh/imx8mn_smm_s2/Kconfig create mode 100644 board/bsh/imx8mn_smm_s2/MAINTAINERS create mode 100644 board/bsh/imx8mn_smm_s2/Makefile create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c create mode 100644 board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c create mode 100644 board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg create mode 100644 board/bsh/imx8mn_smm_s2/spl.c create mode 100644 configs/imx8mn_bsh_smm_s2_defconfig create mode 100644 configs/imx8mn_bsh_smm_s2pro_defconfig create mode 100644 doc/board/bsh/imx8mn_bsh_smm_s2.rst create mode 100644 doc/board/bsh/index.rst create mode 100644 drivers/net/phy/nxp-tja11xx.c create mode 100644 include/configs/imx8mn_bsh_smm_s2.h create mode 100644 include/configs/imx8mn_bsh_smm_s2_common.h create mode 100644 include/configs/imx8mn_bsh_smm_s2pro.h -- 2.34.1
[PATCH v1] arm: dts: imx8mn_var_som: Set atf-bl31 blob entry type
Configure binman ATF blob entry type to use the path from the BL31
environment variable, if defined.
Signed-off-by: Ariel D'Alessandro
---
arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index ce475885df6..6e37622cca7 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -200,7 +200,7 @@
atf_blob {
filename = "bl31.bin";
- type = "blob-ext";
+ type = "atf-bl31";
};
};
--
2.34.1
[PATCH v3 6/6] bsh: imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
Introduce BSH SystemMaster (SMM) S2 board family, which consists of:
iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards.
Add support for iMX8MN BSH SMM S2 board:
- 256 MiB DDR3 RAM
- 512MiB Nand
- USBOTG1 peripheral - fastboot.
- 100Mbit Ethernet
Add support for iMX8MN BSH SMM S2 PRO board:
- 512 MiB DDR3 RAM
- 8 GiB eMMC
- USBOTG1 peripheral - fastboot.
- 100Mbit Ethernet
Signed-off-by: Ariel D'Alessandro
Signed-off-by: Michael Trimarchi
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi| 423
.../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 225 +
arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi| 15 +
arch/arm/dts/imx8mn-bsh-smm-s2.dts| 48 +
arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi | 15 +
arch/arm/dts/imx8mn-bsh-smm-s2pro.dts | 80 ++
arch/arm/mach-imx/imx8m/Kconfig | 15 +
board/bsh/imx8mn_smm_s2/Kconfig | 49 +
board/bsh/imx8mn_smm_s2/MAINTAINERS | 8 +
board/bsh/imx8mn_smm_s2/Makefile | 13 +
board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c | 941 ++
board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c | 941 ++
board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c | 23 +
board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg | 10 +
board/bsh/imx8mn_smm_s2/spl.c | 93 ++
configs/imx8mn_bsh_smm_s2_defconfig | 97 ++
configs/imx8mn_bsh_smm_s2pro_defconfig| 94 ++
doc/board/bsh/imx8mn_bsh_smm_s2.rst | 62 ++
doc/board/bsh/index.rst | 9 +
doc/board/index.rst | 1 +
include/configs/imx8mn_bsh_smm_s2.h | 52 +
include/configs/imx8mn_bsh_smm_s2_common.h| 62 ++
include/configs/imx8mn_bsh_smm_s2pro.h| 35 +
24 files changed, 3313 insertions(+)
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2.dts
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro.dts
create mode 100644 board/bsh/imx8mn_smm_s2/Kconfig
create mode 100644 board/bsh/imx8mn_smm_s2/MAINTAINERS
create mode 100644 board/bsh/imx8mn_smm_s2/Makefile
create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c
create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c
create mode 100644 board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c
create mode 100644 board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg
create mode 100644 board/bsh/imx8mn_smm_s2/spl.c
create mode 100644 configs/imx8mn_bsh_smm_s2_defconfig
create mode 100644 configs/imx8mn_bsh_smm_s2pro_defconfig
create mode 100644 doc/board/bsh/imx8mn_bsh_smm_s2.rst
create mode 100644 doc/board/bsh/index.rst
create mode 100644 include/configs/imx8mn_bsh_smm_s2.h
create mode 100644 include/configs/imx8mn_bsh_smm_s2_common.h
create mode 100644 include/configs/imx8mn_bsh_smm_s2pro.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 086533b61bb..fc7509e511c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -911,6 +911,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-venice-gw7902.dtb \
imx8mm-verdin.dtb \
phycore-imx8mm.dtb \
+ imx8mn-bsh-smm-s2.dtb \
+ imx8mn-bsh-smm-s2pro.dtb \
imx8mn-ddr4-evk.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \
diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
b/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
new file mode 100644
index 000..184c715bd38
--- /dev/null
+++ b/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
@@ -0,0 +1,423 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ * Copyright 2021 BSH Hausgeraete GmbH
+ */
+
+#include "imx8mn.dtsi"
+
+/ {
+ chosen {
+ stdout-path =
+ };
+
+ fec_supply: fec_supply_en {
+ compatible = "regulator-fixed";
+ regulator-name = "tja1101_en";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = < 20 GPIO_ACTIVE_HIGH>;
+ vin-supply = <_reg>;
+ enable-active-high;
+ };
+
+ usdhc2_pwrseq: usdhc2_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <_usdhc2_pwrseq>;
+ reset-gpios = < 27 GPIO_ACTIVE_LOW>;
+ };
+};
+
+_0 {
+ cpu-supply = <_reg>;
+};
+
+_1 {
+ cpu-supply = <_reg>;
+};
+
+_2 {
+ cpu-supply = <_reg>;
+};
+
+_3 {
+ cpu-supply = <_reg>;
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_espi2>;
+ status = "okay";
+
[PATCH v3 5/6] net: phy: nxp-tja11xx: Add NXP TJA11xx PHY driver
From: Michael Trimarchi
Add driver for the NXP TJA1100 and TJA1101 PHYs. These PHYs are special
BroadRReach 100BaseT1 PHYs used in automotive.
Signed-off-by: Michael Trimarchi
Signed-off-by: Ariel D'Alessandro
---
drivers/net/phy/Kconfig | 5 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/nxp-tja11xx.c | 277 ++
drivers/net/phy/phy.c | 3 +
include/phy.h | 1 +
5 files changed, 287 insertions(+)
create mode 100644 drivers/net/phy/nxp-tja11xx.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 4f8d33ce8fd..8de6130113c 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -211,6 +211,11 @@ config PHY_NXP_C45_TJA11XX
Enable support for NXP C45 TJA11XX PHYs.
Currently supports only the TJA1103 PHY.
+config PHY_NXP_TJA11XX
+ bool "NXP TJA11XX Ethernet PHYs support"
+ help
+ Currently supports the NXP TJA1100 and TJA1101 PHY.
+
config PHY_REALTEK
bool "Realtek Ethernet PHYs support"
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 77f7f606215..7cfbab0b5c8 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o
obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o
+obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o
obj-$(CONFIG_PHY_REALTEK) += realtek.o
obj-$(CONFIG_PHY_SMSC) += smsc.o
obj-$(CONFIG_PHY_TERANETICS) += teranetics.o
diff --git a/drivers/net/phy/nxp-tja11xx.c b/drivers/net/phy/nxp-tja11xx.c
new file mode 100644
index 000..30dec5e605b
--- /dev/null
+++ b/drivers/net/phy/nxp-tja11xx.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0
+/* NXP TJA1100 BroadRReach PHY driver
+ *
+ * Copyright (C) 2022 Michael Trimarchi
+ * Copyright (C) 2022 Ariel D'Alessandro
+ * Copyright (C) 2018 Marek Vasut
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define PHY_ID_MASK0xfff0
+#define PHY_ID_TJA1100 0x0180dc40
+#define PHY_ID_TJA1101 0x0180dd00
+
+#define MII_ECTRL 17
+#define MII_ECTRL_LINK_CONTROL BIT(15)
+#define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11)
+#define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11)
+#define MII_ECTRL_POWER_MODE_NORMAL(0x3 << 11)
+#define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11)
+#define MII_ECTRL_CABLE_TEST BIT(5)
+#define MII_ECTRL_CONFIG_ENBIT(2)
+#define MII_ECTRL_WAKE_REQUEST BIT(0)
+
+#define MII_CFG1 18
+#define MII_CFG1_MASTER_SLAVE BIT(15)
+#define MII_CFG1_AUTO_OP BIT(14)
+#define MII_CFG1_SLEEP_CONFIRM BIT(6)
+#define MII_CFG1_LED_MODE_MASK GENMASK(5, 4)
+#define MII_CFG1_LED_MODE_LINKUP 0
+#define MII_CFG1_LED_ENABLEBIT(3)
+
+#define MII_CFG2 19
+#define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0)
+#define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3
+
+#define MII_INTSRC 21
+#define MII_INTSRC_LINK_FAIL BIT(10)
+#define MII_INTSRC_LINK_UP BIT(9)
+#define MII_INTSRC_MASK(MII_INTSRC_LINK_FAIL | \
+MII_INTSRC_LINK_UP)
+#define MII_INTSRC_UV_ERR BIT(3)
+#define MII_INTSRC_TEMP_ERRBIT(1)
+
+#define MII_INTEN 22
+#define MII_INTEN_LINK_FAILBIT(10)
+#define MII_INTEN_LINK_UP BIT(9)
+#define MII_INTEN_UV_ERR BIT(3)
+#define MII_INTEN_TEMP_ERR BIT(1)
+
+#define MII_COMMSTAT 23
+#define MII_COMMSTAT_LINK_UP BIT(15)
+#define MII_COMMSTAT_SQI_STATE GENMASK(7, 5)
+#define MII_COMMSTAT_SQI_MAX 7
+
+#define MII_GENSTAT24
+#define MII_GENSTAT_PLL_LOCKED BIT(14)
+
+#define MII_EXTSTAT25
+#define MII_EXTSTAT_SHORT_DETECT BIT(8)
+#define MII_EXTSTAT_OPEN_DETECTBIT(7)
+#define MII_EXTSTAT_POLARITY_DETECTBIT(6)
+
+#define MII_COMMCFG27
+#define MII_COMMCFG_AUTO_OPBIT(15)
+
+static inline int tja11xx_set_bits(struct phy_device *phydev, u32 regnum,
+ u16 val)
+{
+ return phy_set_bits_mmd(phydev, MDIO_DEVAD_NONE, regnum, val);
+}
+
+static inline int tja11xx_clear_bits(struct phy_device *phydev, u32 regnum,
+u16 val)
+{
+ return phy_clear_bits_mmd(phydev, MDIO_DEVAD_NONE, regnum, val);
+}
+
+static inline int tja11xx_read(struct phy_device *phydev, int regnum)
+{
+ return phy_read(phydev, MDIO_DEVAD_NONE, regnum);
+}
+
+static inline int tja11xx_modify(struct phy_device *phydev, int regnum,
+
[PATCH v3 4/6] net: phy: Add phy_modify() accessor
Add read-modify-write unlocked accessor for accessing a PHY register.
Signed-off-by: Ariel D'Alessandro
---
drivers/net/phy/phy.c | 20
include/phy.h | 2 ++
2 files changed, 22 insertions(+)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 9935e40fcdc..b73361d87d9 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -1105,3 +1105,23 @@ int phy_get_interface_by_name(const char *str)
return -1;
}
+
+/**
+ * phy_modify - Convenience function for modifying a given PHY register
+ * @phydev: the phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: register number to write
+ * @mask: bit mask of bits to clear
+ * @set: new value of bits set in mask to write to @regnum
+ */
+int phy_modify(struct phy_device *phydev, int devad, int regnum, u16 mask,
+ u16 set)
+{
+ int ret;
+
+ ret = phy_read(phydev, devad, regnum);
+ if (ret < 0)
+ return ret;
+
+ return phy_write(phydev, devad, regnum, (ret & ~mask) | set);
+}
diff --git a/include/phy.h b/include/phy.h
index d4035fdef2b..2dd2e02ab5d 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -500,6 +500,8 @@ int phy_config(struct phy_device *phydev);
int phy_shutdown(struct phy_device *phydev);
int phy_register(struct phy_driver *drv);
int phy_set_supported(struct phy_device *phydev, u32 max_speed);
+int phy_modify(struct phy_device *phydev, int devad, int regnum, u16 mask,
+ u16 set);
int genphy_config_aneg(struct phy_device *phydev);
int genphy_restart_aneg(struct phy_device *phydev);
int genphy_update_link(struct phy_device *phydev);
--
2.34.1
[PATCH v3 2/6] phy: nxp-c45-tja11xx: Rename functions to be c45 tja11xx specific
This driver supports NXP C45 TJA11XX PHYs, but there're also other NXP
TJA11XX PHYs. Let's rename functions in this driver to be c45 variant
specific, so further drivers can be introduced adding support for NXP
TJA11XX PHYs.
Signed-off-by: Ariel D'Alessandro
---
drivers/net/phy/nxp-c45-tja11xx.c | 6 +++---
drivers/net/phy/phy.c | 2 +-
include/phy.h | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/phy/nxp-c45-tja11xx.c
b/drivers/net/phy/nxp-c45-tja11xx.c
index f86e31f0d9e..a0f41fab698 100644
--- a/drivers/net/phy/nxp-c45-tja11xx.c
+++ b/drivers/net/phy/nxp-c45-tja11xx.c
@@ -330,7 +330,7 @@ static int nxp_c45_probe(struct phy_device *phydev)
return 0;
}
-static struct phy_driver nxp_tja11xx = {
+static struct phy_driver nxp_c45_tja11xx = {
.name = "NXP C45 TJA1103",
.uid = PHY_ID_TJA_1103,
.mask = 0xf0,
@@ -341,8 +341,8 @@ static struct phy_driver nxp_tja11xx = {
.shutdown = _shutdown,
};
-int phy_nxp_tja11xx_init(void)
+int phy_nxp_c45_tja11xx_init(void)
{
- phy_register(_tja11xx);
+ phy_register(_c45_tja11xx);
return 0;
}
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index c9fc20855ba..9935e40fcdc 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -530,7 +530,7 @@ int phy_init(void)
phy_natsemi_init();
#endif
#ifdef CONFIG_NXP_C45_TJA11XX_PHY
- phy_nxp_tja11xx_init();
+ phy_nxp_c45_tja11xx_init();
#endif
#ifdef CONFIG_PHY_REALTEK
phy_realtek_init();
diff --git a/include/phy.h b/include/phy.h
index c66fd43ea88..d4035fdef2b 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -527,7 +527,7 @@ int phy_micrel_ksz8xxx_init(void);
int phy_micrel_ksz90x1_init(void);
int phy_meson_gxl_init(void);
int phy_natsemi_init(void);
-int phy_nxp_tja11xx_init(void);
+int phy_nxp_c45_tja11xx_init(void);
int phy_realtek_init(void);
int phy_smsc_init(void);
int phy_teranetics_init(void);
--
2.34.1
[PATCH v3 3/6] iopoll: Extend read_poll_timeout macro to support variable parameters
This macro currently supports only one parameter. Based on Linux iopoll,
let's extend read_poll_timeout common API to allow multiple variable
parameters.
Signed-off-by: Ariel D'Alessandro
---
arch/arm/mach-socfpga/reset_manager_s10.c | 20 +++-
drivers/mmc/rockchip_sdhci.c | 9 +
include/linux/iopoll.h| 12 ++--
3 files changed, 22 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
b/arch/arm/mach-socfpga/reset_manager_s10.c
index d2337bd4d62..f47fec10a0c 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -80,9 +80,9 @@ void socfpga_bridges_reset(int enable)
~0);
/* Poll until all idleack to 0 */
- read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLEACK, reg, !reg, 1000,
- 30);
+ read_poll_timeout(readl, reg, !reg, 1000, 30,
+ socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLEACK);
} else {
/* set idle request to all bridges */
writel(~0,
@@ -93,18 +93,20 @@ void socfpga_bridges_reset(int enable)
writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
/* Poll until all idleack to 1 */
- read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLEACK, reg,
+ read_poll_timeout(readl, reg,
reg == (SYSMGR_NOC_H2F_MSK |
SYSMGR_NOC_LWH2F_MSK),
- 1000, 30);
+ 1000, 30,
+ socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLEACK);
/* Poll until all idlestatus to 1 */
- read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLESTATUS, reg,
+ read_poll_timeout(readl, reg,
reg == (SYSMGR_NOC_H2F_MSK |
SYSMGR_NOC_LWH2F_MSK),
- 1000, 30);
+ 1000, 30,
+ socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLESTATUS);
/* Reset all bridges (except NOR DDR scheduler & F2S) */
setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 278473899c7..87f14b0ee9c 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -146,8 +146,8 @@ static void rk3399_emmc_phy_power_on(struct
rockchip_emmc_phy *phy, u32 clock)
/* REN Enable on STRB Line for HS400 */
writel(RK_CLRSETBITS(0, 1 << 9), >emmcphy_con[2]);
- read_poll_timeout(readl, >emmcphy_status, dllrdy,
- PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1, 5000);
+ read_poll_timeout(readl, dllrdy, PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1,
+ 5000, >emmcphy_status);
}
static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy)
@@ -235,8 +235,9 @@ static int rk3568_sdhci_emmc_set_clock(struct sdhci_host
*host, unsigned int clo
DWCMSHC_EMMC_DLL_START;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
- ret = read_poll_timeout(readl, host->ioaddr +
DWCMSHC_EMMC_DLL_STATUS0,
- val, DLL_LOCK_WO_TMOUT(val), 1, 500);
+ ret = read_poll_timeout(readl, val, DLL_LOCK_WO_TMOUT(val), 1,
+ 500,
+ host->ioaddr +
DWCMSHC_EMMC_DLL_STATUS0);
if (ret)
return ret;
diff --git a/include/linux/iopoll.h b/include/linux/iopoll.h
index 30cdea0cdc1..0ee2bddaa83 100644
--- a/include/linux/iopoll.h
+++ b/include/linux/iopoll.h
@@ -14,11 +14,11 @@
/**
* read_poll_timeout - Periodically poll an address until a condition is met
or a timeout occurs
* @op: accessor function (takes @addr as its only argument)
- * @addr: Address to poll
* @val: Variable to read the value into
* @cond: Break condition (usually involving @val)
* @sleep_us: Maximum time to sleep in us
* @timeout_us: Timeout in us, 0 means never timeout
+ * @args: arguments for @op poll
*
* Returns 0 on success and -ETIMEDOUT upon a timeout. In either
* case, the last read value at @addr is stored in @val.
@@ -26,15 +26,15 @@
* When available, you'll probably want to use one of the specialized
* macros defined bel
[PATCH v3 1/6] imx8m: add regs used by GPMI
From: Michael Trimarchi Add regs used by GPMI Signed-off-by: Michael Trimarchi Signed-off-by: Ariel D'Alessandro Reviewed-by: Fabio Estevam --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 45d95a7c197..fb665412465 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -58,6 +58,13 @@ #define SRC_DDRC_RCR_ADDR 0x30391000 #define SRC_DDRC2_RCR_ADDR 0x30391004 +#define APBH_DMA_ARB_BASE_ADDR 0x3300 +#define APBH_DMA_ARB_END_ADDR 0x33007FFF +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR + +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) + #define DDRC_DDR_SS_GPR0 0x3d00 #define DDRC_IPS_BASE_ADDR(X) (0x3d40 + ((X) * 0x200)) #define DDR_CSD1_BASE_ADDR 0x4000 -- 2.34.1
[PATCH v3 0/6] imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
Introduce BSH SystemMaster (SMM) S2 board family, which consists of: iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards. This patchset also adds support for NXP TJA11xx Ethernet PHYs. Changes in v3: * Added nxp-c45-tja11xx driver. * Added ethernet support to iMX8MN BSH SMM S2 boards. Changes in v2: * Properly added MAINTAINERS entry. * Fixed binman configuration. * Picked device tree from kernel. * Removed CONFIG_SPL_BUILD anti-pattern in board config. * Removed downstream stuff in bootargs. * Added board documentation. Ariel D'Alessandro (4): phy: nxp-c45-tja11xx: Rename functions to be c45 tja11xx specific iopoll: Extend read_poll_timeout macro to support variable parameters net: phy: Add phy_modify() accessor bsh: imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards Michael Trimarchi (2): imx8m: add regs used by GPMI net: phy: nxp-tja11xx: Add NXP TJA11xx PHY driver arch/arm/dts/Makefile | 2 + arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi| 423 .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 225 + arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi| 15 + arch/arm/dts/imx8mn-bsh-smm-s2.dts| 48 + arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi | 15 + arch/arm/dts/imx8mn-bsh-smm-s2pro.dts | 80 ++ arch/arm/include/asm/arch-imx8m/imx-regs.h| 7 + arch/arm/mach-imx/imx8m/Kconfig | 15 + arch/arm/mach-socfpga/reset_manager_s10.c | 20 +- board/bsh/imx8mn_smm_s2/Kconfig | 49 + board/bsh/imx8mn_smm_s2/MAINTAINERS | 8 + board/bsh/imx8mn_smm_s2/Makefile | 13 + board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c | 941 ++ board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c | 941 ++ board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c | 23 + board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg | 10 + board/bsh/imx8mn_smm_s2/spl.c | 93 ++ configs/imx8mn_bsh_smm_s2_defconfig | 97 ++ configs/imx8mn_bsh_smm_s2pro_defconfig| 94 ++ doc/board/bsh/imx8mn_bsh_smm_s2.rst | 62 ++ doc/board/bsh/index.rst | 9 + doc/board/index.rst | 1 + drivers/mmc/rockchip_sdhci.c | 9 +- drivers/net/phy/Kconfig | 5 + drivers/net/phy/Makefile | 1 + drivers/net/phy/nxp-c45-tja11xx.c | 6 +- drivers/net/phy/nxp-tja11xx.c | 277 ++ drivers/net/phy/phy.c | 23 + include/configs/imx8mn_bsh_smm_s2.h | 52 + include/configs/imx8mn_bsh_smm_s2_common.h| 62 ++ include/configs/imx8mn_bsh_smm_s2pro.h| 35 + include/linux/iopoll.h| 12 +- include/phy.h | 3 + 34 files changed, 3654 insertions(+), 22 deletions(-) create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2.dts create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro.dts create mode 100644 board/bsh/imx8mn_smm_s2/Kconfig create mode 100644 board/bsh/imx8mn_smm_s2/MAINTAINERS create mode 100644 board/bsh/imx8mn_smm_s2/Makefile create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c create mode 100644 board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c create mode 100644 board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg create mode 100644 board/bsh/imx8mn_smm_s2/spl.c create mode 100644 configs/imx8mn_bsh_smm_s2_defconfig create mode 100644 configs/imx8mn_bsh_smm_s2pro_defconfig create mode 100644 doc/board/bsh/imx8mn_bsh_smm_s2.rst create mode 100644 doc/board/bsh/index.rst create mode 100644 drivers/net/phy/nxp-tja11xx.c create mode 100644 include/configs/imx8mn_bsh_smm_s2.h create mode 100644 include/configs/imx8mn_bsh_smm_s2_common.h create mode 100644 include/configs/imx8mn_bsh_smm_s2pro.h -- 2.34.1
Re: [PATCH v2 0/2] imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
Ping :-) Can we get this merged? On 1/31/22 10:39, Ariel D'Alessandro wrote: > Hi Tom, > > Any reason why this is still pending? > Please let me know. > > Thanks in advance, > Ariel > > On 1/26/22 08:08, Michael Nazzareno Trimarchi wrote: >> Hi Fabio >> >> On Sat, Jan 15, 2022 at 3:11 PM Fabio Estevam wrote: >>> >>> On Mon, Jan 3, 2022 at 6:11 PM Ariel D'Alessandro >>> wrote: >>>> >>>> Gentle ping. Can we get this merged? >>> >>> Looks good to me: >>> >>> Reviewed-by: Fabio Estevam >> >> Where will it be pick up? I will need even some followup to the patch >> that write the nand_bcb to avoid to use the kernel tool >> >> Michael
Re: [PATCH v6 0/1] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Hi Stefano, On 1/31/22 10:46, Stefano Babic wrote: Hi Ariel, On 31.01.22 14:36, Ariel D'Alessandro wrote: Hi Tom, Any reason why this is still pending? Main reason is that I was (as IMX maintainer) on holiday, and I am just since today back - and of course, I have a lot of things from my job to do before. So checking / applying U-Boot's patches is of course on my list, but it still requires some time until I can take care of it. Ah, I see :-) Cool, thanks for the quick answer. Regards, Ariel Best regards, Stefano Thanks, Ariel On 1/4/22 11:10, Ariel D'Alessandro wrote: Hi Tom, On 1/4/22 10:56, Tom Rini wrote: On Mon, Jan 03, 2022 at 05:55:21PM -0300, Ariel D'Alessandro wrote: Gentle ping. Can we get this merged? Does this need to be in for the v2022.01 release or can it wait for v2022.04? Thanks. No, there's no real rush for this to be in v2022.01. Just wanted to know if there was any pending changes and get it approved. Thanks. On 11/23/21 13:33, Ariel D'Alessandro wrote: Changes in v6: * Fixed typo in documentation. * Removed downstream config option IMX8M_BOARD_INIT_DRAM. Changes in v5: * Fixed documentation. Changes in v4: * Added board documentation. * Cleaned up board config. Changes in v3: * Picked device tree from kernel. * Properly added MAINTAINERS entry. * Removed CONFIG_SPL_BUILD anti-pattern in board config. Changes in v2: * Reordered dt properties alphabetically. * Removed downstream stuff in bootargs. * Fixed binman configuration. * Several code styling fixes. Ariel D'Alessandro (1): imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board arch/arm/dts/Makefile | 1 + .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 256 arch/arm/dts/imx8mn-var-som-symphony.dts | 240 arch/arm/dts/imx8mn-var-som.dtsi | 547 ++ arch/arm/mach-imx/imx8m/Kconfig | 8 + board/variscite/imx8mn_var_som/Kconfig | 17 + board/variscite/imx8mn_var_som/MAINTAINERS | 7 + board/variscite/imx8mn_var_som/Makefile | 12 + board/variscite/imx8mn_var_som/ddr4_timing.c | 528 + .../variscite/imx8mn_var_som/imx8mn_var_som.c | 30 + .../imx8mn_var_som/imximage-8mn-ddr4.cfg | 10 + board/variscite/imx8mn_var_som/spl.c | 93 +++ configs/imx8mn_var_som_defconfig | 98 doc/board/index.rst | 1 + doc/board/variscite/imx8mn_var_som.rst | 56 ++ doc/board/variscite/index.rst | 9 + include/configs/imx8mn_var_som.h | 90 +++ 17 files changed, 2003 insertions(+) create mode 100644 arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-var-som-symphony.dts create mode 100644 arch/arm/dts/imx8mn-var-som.dtsi create mode 100644 board/variscite/imx8mn_var_som/Kconfig create mode 100644 board/variscite/imx8mn_var_som/MAINTAINERS create mode 100644 board/variscite/imx8mn_var_som/Makefile create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg create mode 100644 board/variscite/imx8mn_var_som/spl.c create mode 100644 configs/imx8mn_var_som_defconfig create mode 100644 doc/board/variscite/imx8mn_var_som.rst create mode 100644 doc/board/variscite/index.rst create mode 100644 include/configs/imx8mn_var_som.h
Re: [PATCH v2 0/2] imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
Hi Tom, Any reason why this is still pending? Please let me know. Thanks in advance, Ariel On 1/26/22 08:08, Michael Nazzareno Trimarchi wrote: Hi Fabio On Sat, Jan 15, 2022 at 3:11 PM Fabio Estevam wrote: On Mon, Jan 3, 2022 at 6:11 PM Ariel D'Alessandro wrote: Gentle ping. Can we get this merged? Looks good to me: Reviewed-by: Fabio Estevam Where will it be pick up? I will need even some followup to the patch that write the nand_bcb to avoid to use the kernel tool Michael
Re: [PATCH v6 0/1] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Hi Tom, Any reason why this is still pending? Thanks, Ariel On 1/4/22 11:10, Ariel D'Alessandro wrote: Hi Tom, On 1/4/22 10:56, Tom Rini wrote: On Mon, Jan 03, 2022 at 05:55:21PM -0300, Ariel D'Alessandro wrote: Gentle ping. Can we get this merged? Does this need to be in for the v2022.01 release or can it wait for v2022.04? Thanks. No, there's no real rush for this to be in v2022.01. Just wanted to know if there was any pending changes and get it approved. Thanks. On 11/23/21 13:33, Ariel D'Alessandro wrote: Changes in v6: * Fixed typo in documentation. * Removed downstream config option IMX8M_BOARD_INIT_DRAM. Changes in v5: * Fixed documentation. Changes in v4: * Added board documentation. * Cleaned up board config. Changes in v3: * Picked device tree from kernel. * Properly added MAINTAINERS entry. * Removed CONFIG_SPL_BUILD anti-pattern in board config. Changes in v2: * Reordered dt properties alphabetically. * Removed downstream stuff in bootargs. * Fixed binman configuration. * Several code styling fixes. Ariel D'Alessandro (1): imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board arch/arm/dts/Makefile | 1 + .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 256 arch/arm/dts/imx8mn-var-som-symphony.dts | 240 arch/arm/dts/imx8mn-var-som.dtsi | 547 ++ arch/arm/mach-imx/imx8m/Kconfig | 8 + board/variscite/imx8mn_var_som/Kconfig | 17 + board/variscite/imx8mn_var_som/MAINTAINERS | 7 + board/variscite/imx8mn_var_som/Makefile | 12 + board/variscite/imx8mn_var_som/ddr4_timing.c | 528 + .../variscite/imx8mn_var_som/imx8mn_var_som.c | 30 + .../imx8mn_var_som/imximage-8mn-ddr4.cfg | 10 + board/variscite/imx8mn_var_som/spl.c | 93 +++ configs/imx8mn_var_som_defconfig | 98 doc/board/index.rst | 1 + doc/board/variscite/imx8mn_var_som.rst | 56 ++ doc/board/variscite/index.rst | 9 + include/configs/imx8mn_var_som.h | 90 +++ 17 files changed, 2003 insertions(+) create mode 100644 arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-var-som-symphony.dts create mode 100644 arch/arm/dts/imx8mn-var-som.dtsi create mode 100644 board/variscite/imx8mn_var_som/Kconfig create mode 100644 board/variscite/imx8mn_var_som/MAINTAINERS create mode 100644 board/variscite/imx8mn_var_som/Makefile create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg create mode 100644 board/variscite/imx8mn_var_som/spl.c create mode 100644 configs/imx8mn_var_som_defconfig create mode 100644 doc/board/variscite/imx8mn_var_som.rst create mode 100644 doc/board/variscite/index.rst create mode 100644 include/configs/imx8mn_var_som.h
Re: [PATCH v6 0/1] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Hi Tom, On 1/4/22 10:56, Tom Rini wrote: On Mon, Jan 03, 2022 at 05:55:21PM -0300, Ariel D'Alessandro wrote: Gentle ping. Can we get this merged? Does this need to be in for the v2022.01 release or can it wait for v2022.04? Thanks. No, there's no real rush for this to be in v2022.01. Just wanted to know if there was any pending changes and get it approved. Thanks. On 11/23/21 13:33, Ariel D'Alessandro wrote: Changes in v6: * Fixed typo in documentation. * Removed downstream config option IMX8M_BOARD_INIT_DRAM. Changes in v5: * Fixed documentation. Changes in v4: * Added board documentation. * Cleaned up board config. Changes in v3: * Picked device tree from kernel. * Properly added MAINTAINERS entry. * Removed CONFIG_SPL_BUILD anti-pattern in board config. Changes in v2: * Reordered dt properties alphabetically. * Removed downstream stuff in bootargs. * Fixed binman configuration. * Several code styling fixes. Ariel D'Alessandro (1): imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board arch/arm/dts/Makefile | 1 + .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 256 arch/arm/dts/imx8mn-var-som-symphony.dts | 240 arch/arm/dts/imx8mn-var-som.dtsi | 547 ++ arch/arm/mach-imx/imx8m/Kconfig | 8 + board/variscite/imx8mn_var_som/Kconfig| 17 + board/variscite/imx8mn_var_som/MAINTAINERS| 7 + board/variscite/imx8mn_var_som/Makefile | 12 + board/variscite/imx8mn_var_som/ddr4_timing.c | 528 + .../variscite/imx8mn_var_som/imx8mn_var_som.c | 30 + .../imx8mn_var_som/imximage-8mn-ddr4.cfg | 10 + board/variscite/imx8mn_var_som/spl.c | 93 +++ configs/imx8mn_var_som_defconfig | 98 doc/board/index.rst | 1 + doc/board/variscite/imx8mn_var_som.rst| 56 ++ doc/board/variscite/index.rst | 9 + include/configs/imx8mn_var_som.h | 90 +++ 17 files changed, 2003 insertions(+) create mode 100644 arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-var-som-symphony.dts create mode 100644 arch/arm/dts/imx8mn-var-som.dtsi create mode 100644 board/variscite/imx8mn_var_som/Kconfig create mode 100644 board/variscite/imx8mn_var_som/MAINTAINERS create mode 100644 board/variscite/imx8mn_var_som/Makefile create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg create mode 100644 board/variscite/imx8mn_var_som/spl.c create mode 100644 configs/imx8mn_var_som_defconfig create mode 100644 doc/board/variscite/imx8mn_var_som.rst create mode 100644 doc/board/variscite/index.rst create mode 100644 include/configs/imx8mn_var_som.h
Re: [PATCH v2 0/2] imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
Gentle ping. Can we get this merged? On 11/23/21 14:42, Ariel D'Alessandro wrote: Changes in v2: * Properly added MAINTAINERS entry. * Fixed binman configuration. * Picked device tree from kernel. * Removed CONFIG_SPL_BUILD anti-pattern in board config. * Removed downstream stuff in bootargs. * Added board documentation. Ariel D'Alessandro (1): bsh: imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards Michael Trimarchi (1): imx8m: add regs used by GPMI arch/arm/dts/Makefile | 2 + arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi| 423 .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 225 + arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi| 15 + arch/arm/dts/imx8mn-bsh-smm-s2.dts| 48 + arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi | 15 + arch/arm/dts/imx8mn-bsh-smm-s2pro.dts | 80 ++ arch/arm/include/asm/arch-imx8m/imx-regs.h| 7 + arch/arm/mach-imx/imx8m/Kconfig | 15 + board/bsh/imx8mn_smm_s2/Kconfig | 38 + board/bsh/imx8mn_smm_s2/MAINTAINERS | 8 + board/bsh/imx8mn_smm_s2/Makefile | 13 + board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c | 941 ++ board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c | 941 ++ board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c | 23 + board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg | 10 + board/bsh/imx8mn_smm_s2/spl.c | 93 ++ configs/imx8mn_bsh_smm_s2_defconfig | 92 ++ configs/imx8mn_bsh_smm_s2pro_defconfig| 89 ++ doc/board/bsh/imx8mn_bsh_smm_s2.rst | 62 ++ doc/board/bsh/index.rst | 9 + doc/board/index.rst | 1 + include/configs/imx8mn_bsh_smm_s2.h | 52 + include/configs/imx8mn_bsh_smm_s2_common.h| 62 ++ include/configs/imx8mn_bsh_smm_s2pro.h| 35 + 25 files changed, 3299 insertions(+) create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2.dts create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro.dts create mode 100644 board/bsh/imx8mn_smm_s2/Kconfig create mode 100644 board/bsh/imx8mn_smm_s2/MAINTAINERS create mode 100644 board/bsh/imx8mn_smm_s2/Makefile create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c create mode 100644 board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c create mode 100644 board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg create mode 100644 board/bsh/imx8mn_smm_s2/spl.c create mode 100644 configs/imx8mn_bsh_smm_s2_defconfig create mode 100644 configs/imx8mn_bsh_smm_s2pro_defconfig create mode 100644 doc/board/bsh/imx8mn_bsh_smm_s2.rst create mode 100644 doc/board/bsh/index.rst create mode 100644 include/configs/imx8mn_bsh_smm_s2.h create mode 100644 include/configs/imx8mn_bsh_smm_s2_common.h create mode 100644 include/configs/imx8mn_bsh_smm_s2pro.h
Re: [PATCH v6 0/1] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Gentle ping. Can we get this merged? On 11/23/21 13:33, Ariel D'Alessandro wrote: Changes in v6: * Fixed typo in documentation. * Removed downstream config option IMX8M_BOARD_INIT_DRAM. Changes in v5: * Fixed documentation. Changes in v4: * Added board documentation. * Cleaned up board config. Changes in v3: * Picked device tree from kernel. * Properly added MAINTAINERS entry. * Removed CONFIG_SPL_BUILD anti-pattern in board config. Changes in v2: * Reordered dt properties alphabetically. * Removed downstream stuff in bootargs. * Fixed binman configuration. * Several code styling fixes. Ariel D'Alessandro (1): imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board arch/arm/dts/Makefile | 1 + .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 256 arch/arm/dts/imx8mn-var-som-symphony.dts | 240 arch/arm/dts/imx8mn-var-som.dtsi | 547 ++ arch/arm/mach-imx/imx8m/Kconfig | 8 + board/variscite/imx8mn_var_som/Kconfig| 17 + board/variscite/imx8mn_var_som/MAINTAINERS| 7 + board/variscite/imx8mn_var_som/Makefile | 12 + board/variscite/imx8mn_var_som/ddr4_timing.c | 528 + .../variscite/imx8mn_var_som/imx8mn_var_som.c | 30 + .../imx8mn_var_som/imximage-8mn-ddr4.cfg | 10 + board/variscite/imx8mn_var_som/spl.c | 93 +++ configs/imx8mn_var_som_defconfig | 98 doc/board/index.rst | 1 + doc/board/variscite/imx8mn_var_som.rst| 56 ++ doc/board/variscite/index.rst | 9 + include/configs/imx8mn_var_som.h | 90 +++ 17 files changed, 2003 insertions(+) create mode 100644 arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-var-som-symphony.dts create mode 100644 arch/arm/dts/imx8mn-var-som.dtsi create mode 100644 board/variscite/imx8mn_var_som/Kconfig create mode 100644 board/variscite/imx8mn_var_som/MAINTAINERS create mode 100644 board/variscite/imx8mn_var_som/Makefile create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg create mode 100644 board/variscite/imx8mn_var_som/spl.c create mode 100644 configs/imx8mn_var_som_defconfig create mode 100644 doc/board/variscite/imx8mn_var_som.rst create mode 100644 doc/board/variscite/index.rst create mode 100644 include/configs/imx8mn_var_som.h
[PATCH v2 2/2] bsh: imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
Introduce BSH SystemMaster (SMM) S2 board family, which consists of:
iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards.
Add support for iMX8MN BSH SMM S2 board:
- 256 MiB DDR3 RAM
- 512MiB Nand
- USBOTG1 peripheral - fastboot.
Add support for iMX8MN BSH SMM S2 PRO board:
- 512 MiB DDR3 RAM
- 8 GiB eMMC
- USBOTG1 peripheral - fastboot.
Signed-off-by: Ariel D'Alessandro
Signed-off-by: Michael Trimarchi
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi| 423
.../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 225 +
arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi| 15 +
arch/arm/dts/imx8mn-bsh-smm-s2.dts| 48 +
arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi | 15 +
arch/arm/dts/imx8mn-bsh-smm-s2pro.dts | 80 ++
arch/arm/mach-imx/imx8m/Kconfig | 15 +
board/bsh/imx8mn_smm_s2/Kconfig | 38 +
board/bsh/imx8mn_smm_s2/MAINTAINERS | 8 +
board/bsh/imx8mn_smm_s2/Makefile | 13 +
board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c | 941 ++
board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c | 941 ++
board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c | 23 +
board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg | 10 +
board/bsh/imx8mn_smm_s2/spl.c | 93 ++
configs/imx8mn_bsh_smm_s2_defconfig | 92 ++
configs/imx8mn_bsh_smm_s2pro_defconfig| 89 ++
doc/board/bsh/imx8mn_bsh_smm_s2.rst | 62 ++
doc/board/bsh/index.rst | 9 +
doc/board/index.rst | 1 +
include/configs/imx8mn_bsh_smm_s2.h | 52 +
include/configs/imx8mn_bsh_smm_s2_common.h| 62 ++
include/configs/imx8mn_bsh_smm_s2pro.h| 35 +
24 files changed, 3292 insertions(+)
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2.dts
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro.dts
create mode 100644 board/bsh/imx8mn_smm_s2/Kconfig
create mode 100644 board/bsh/imx8mn_smm_s2/MAINTAINERS
create mode 100644 board/bsh/imx8mn_smm_s2/Makefile
create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c
create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c
create mode 100644 board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c
create mode 100644 board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg
create mode 100644 board/bsh/imx8mn_smm_s2/spl.c
create mode 100644 configs/imx8mn_bsh_smm_s2_defconfig
create mode 100644 configs/imx8mn_bsh_smm_s2pro_defconfig
create mode 100644 doc/board/bsh/imx8mn_bsh_smm_s2.rst
create mode 100644 doc/board/bsh/index.rst
create mode 100644 include/configs/imx8mn_bsh_smm_s2.h
create mode 100644 include/configs/imx8mn_bsh_smm_s2_common.h
create mode 100644 include/configs/imx8mn_bsh_smm_s2pro.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7f622fedbd..25a3a6f713 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -899,6 +899,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-venice-gw7902.dtb \
imx8mm-verdin.dtb \
phycore-imx8mm.dtb \
+ imx8mn-bsh-smm-s2.dtb \
+ imx8mn-bsh-smm-s2pro.dtb \
imx8mn-ddr4-evk.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \
diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
b/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
new file mode 100644
index 00..184c715bd3
--- /dev/null
+++ b/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
@@ -0,0 +1,423 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ * Copyright 2021 BSH Hausgeraete GmbH
+ */
+
+#include "imx8mn.dtsi"
+
+/ {
+ chosen {
+ stdout-path =
+ };
+
+ fec_supply: fec_supply_en {
+ compatible = "regulator-fixed";
+ regulator-name = "tja1101_en";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = < 20 GPIO_ACTIVE_HIGH>;
+ vin-supply = <_reg>;
+ enable-active-high;
+ };
+
+ usdhc2_pwrseq: usdhc2_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <_usdhc2_pwrseq>;
+ reset-gpios = < 27 GPIO_ACTIVE_LOW>;
+ };
+};
+
+_0 {
+ cpu-supply = <_reg>;
+};
+
+_1 {
+ cpu-supply = <_reg>;
+};
+
+_2 {
+ cpu-supply = <_reg>;
+};
+
+_3 {
+ cpu-supply = <_reg>;
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_espi2>;
+ status = "okay";
+};
+
+ {
+ pinctrl-names = "defau
[PATCH v2 1/2] imx8m: add regs used by GPMI
From: Michael Trimarchi Add regs used by GPMI Signed-off-by: Michael Trimarchi Signed-off-by: Ariel D'Alessandro --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index b800da13a1..14955d1090 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -58,6 +58,13 @@ #define SRC_DDRC_RCR_ADDR 0x30391000 #define SRC_DDRC2_RCR_ADDR 0x30391004 +#define APBH_DMA_ARB_BASE_ADDR 0x3300 +#define APBH_DMA_ARB_END_ADDR 0x33007FFF +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR + +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) + #define DDRC_DDR_SS_GPR0 0x3d00 #define DDRC_IPS_BASE_ADDR(X) (0x3d40 + ((X) * 0x200)) #define DDR_CSD1_BASE_ADDR 0x4000 -- 2.30.2
[PATCH v2 0/2] imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
Changes in v2: * Properly added MAINTAINERS entry. * Fixed binman configuration. * Picked device tree from kernel. * Removed CONFIG_SPL_BUILD anti-pattern in board config. * Removed downstream stuff in bootargs. * Added board documentation. Ariel D'Alessandro (1): bsh: imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards Michael Trimarchi (1): imx8m: add regs used by GPMI arch/arm/dts/Makefile | 2 + arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi| 423 .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 225 + arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi| 15 + arch/arm/dts/imx8mn-bsh-smm-s2.dts| 48 + arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi | 15 + arch/arm/dts/imx8mn-bsh-smm-s2pro.dts | 80 ++ arch/arm/include/asm/arch-imx8m/imx-regs.h| 7 + arch/arm/mach-imx/imx8m/Kconfig | 15 + board/bsh/imx8mn_smm_s2/Kconfig | 38 + board/bsh/imx8mn_smm_s2/MAINTAINERS | 8 + board/bsh/imx8mn_smm_s2/Makefile | 13 + board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c | 941 ++ board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c | 941 ++ board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c | 23 + board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg | 10 + board/bsh/imx8mn_smm_s2/spl.c | 93 ++ configs/imx8mn_bsh_smm_s2_defconfig | 92 ++ configs/imx8mn_bsh_smm_s2pro_defconfig| 89 ++ doc/board/bsh/imx8mn_bsh_smm_s2.rst | 62 ++ doc/board/bsh/index.rst | 9 + doc/board/index.rst | 1 + include/configs/imx8mn_bsh_smm_s2.h | 52 + include/configs/imx8mn_bsh_smm_s2_common.h| 62 ++ include/configs/imx8mn_bsh_smm_s2pro.h| 35 + 25 files changed, 3299 insertions(+) create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2.dts create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro.dts create mode 100644 board/bsh/imx8mn_smm_s2/Kconfig create mode 100644 board/bsh/imx8mn_smm_s2/MAINTAINERS create mode 100644 board/bsh/imx8mn_smm_s2/Makefile create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c create mode 100644 board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c create mode 100644 board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg create mode 100644 board/bsh/imx8mn_smm_s2/spl.c create mode 100644 configs/imx8mn_bsh_smm_s2_defconfig create mode 100644 configs/imx8mn_bsh_smm_s2pro_defconfig create mode 100644 doc/board/bsh/imx8mn_bsh_smm_s2.rst create mode 100644 doc/board/bsh/index.rst create mode 100644 include/configs/imx8mn_bsh_smm_s2.h create mode 100644 include/configs/imx8mn_bsh_smm_s2_common.h create mode 100644 include/configs/imx8mn_bsh_smm_s2pro.h -- 2.30.2
[PATCH v6 1/1] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for:
- 1GiB DDR4 RAM
- 16 GiB eMMC
- SD card
- Gigabit ethernet
- USBOTG1 peripheral - fastboot
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Tom Rini
Reviewed-by: Fabio Estevam
---
arch/arm/dts/Makefile | 1 +
.../dts/imx8mn-var-som-symphony-u-boot.dtsi | 256
arch/arm/dts/imx8mn-var-som-symphony.dts | 240
arch/arm/dts/imx8mn-var-som.dtsi | 547 ++
arch/arm/mach-imx/imx8m/Kconfig | 8 +
board/variscite/imx8mn_var_som/Kconfig| 17 +
board/variscite/imx8mn_var_som/MAINTAINERS| 7 +
board/variscite/imx8mn_var_som/Makefile | 12 +
board/variscite/imx8mn_var_som/ddr4_timing.c | 528 +
.../variscite/imx8mn_var_som/imx8mn_var_som.c | 30 +
.../imx8mn_var_som/imximage-8mn-ddr4.cfg | 10 +
board/variscite/imx8mn_var_som/spl.c | 93 +++
configs/imx8mn_var_som_defconfig | 98
doc/board/index.rst | 1 +
doc/board/variscite/imx8mn_var_som.rst| 56 ++
doc/board/variscite/index.rst | 9 +
include/configs/imx8mn_var_som.h | 90 +++
17 files changed, 2003 insertions(+)
create mode 100644 arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-var-som-symphony.dts
create mode 100644 arch/arm/dts/imx8mn-var-som.dtsi
create mode 100644 board/variscite/imx8mn_var_som/Kconfig
create mode 100644 board/variscite/imx8mn_var_som/MAINTAINERS
create mode 100644 board/variscite/imx8mn_var_som/Makefile
create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c
create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c
create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg
create mode 100644 board/variscite/imx8mn_var_som/spl.c
create mode 100644 configs/imx8mn_var_som_defconfig
create mode 100644 doc/board/variscite/imx8mn_var_som.rst
create mode 100644 doc/board/variscite/index.rst
create mode 100644 include/configs/imx8mn_var_som.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7f622fedbd..3794b424c6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -902,6 +902,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mn-ddr4-evk.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \
+ imx8mn-var-som-symphony.dtb \
imx8mq-evk.dtb \
imx8mm-beacon-kit.dtb \
imx8mn-beacon-kit.dtb \
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
new file mode 100644
index 00..ce475885df
--- /dev/null
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <>;
+ u-boot,dm-spl;
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_24m {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+_i2c1 {
+ u-boot,dm-spl;
+};
+
+_pmic {
+ u-boot,dm-spl;
+};
+
+_reg_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+_uart4 {
+ u-boot,dm-spl;
+};
+
+_usdhc2 {
+ u-boot,dm-spl;
+};
+
+_usdhc3 {
+ u-boot,dm-spl;
+};
+
+_wdog {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot-spl-ddr {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
+
+ 1d-imem {
+ filename = "ddr4_imem_1d.bin";
+ size = <0x8000>;
+ type = "blob-ext";
+ };
+
+ 1d_dmem {
+ filename = &qu
[PATCH v6 0/1] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Changes in v6: * Fixed typo in documentation. * Removed downstream config option IMX8M_BOARD_INIT_DRAM. Changes in v5: * Fixed documentation. Changes in v4: * Added board documentation. * Cleaned up board config. Changes in v3: * Picked device tree from kernel. * Properly added MAINTAINERS entry. * Removed CONFIG_SPL_BUILD anti-pattern in board config. Changes in v2: * Reordered dt properties alphabetically. * Removed downstream stuff in bootargs. * Fixed binman configuration. * Several code styling fixes. Ariel D'Alessandro (1): imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board arch/arm/dts/Makefile | 1 + .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 256 arch/arm/dts/imx8mn-var-som-symphony.dts | 240 arch/arm/dts/imx8mn-var-som.dtsi | 547 ++ arch/arm/mach-imx/imx8m/Kconfig | 8 + board/variscite/imx8mn_var_som/Kconfig| 17 + board/variscite/imx8mn_var_som/MAINTAINERS| 7 + board/variscite/imx8mn_var_som/Makefile | 12 + board/variscite/imx8mn_var_som/ddr4_timing.c | 528 + .../variscite/imx8mn_var_som/imx8mn_var_som.c | 30 + .../imx8mn_var_som/imximage-8mn-ddr4.cfg | 10 + board/variscite/imx8mn_var_som/spl.c | 93 +++ configs/imx8mn_var_som_defconfig | 98 doc/board/index.rst | 1 + doc/board/variscite/imx8mn_var_som.rst| 56 ++ doc/board/variscite/index.rst | 9 + include/configs/imx8mn_var_som.h | 90 +++ 17 files changed, 2003 insertions(+) create mode 100644 arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-var-som-symphony.dts create mode 100644 arch/arm/dts/imx8mn-var-som.dtsi create mode 100644 board/variscite/imx8mn_var_som/Kconfig create mode 100644 board/variscite/imx8mn_var_som/MAINTAINERS create mode 100644 board/variscite/imx8mn_var_som/Makefile create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg create mode 100644 board/variscite/imx8mn_var_som/spl.c create mode 100644 configs/imx8mn_var_som_defconfig create mode 100644 doc/board/variscite/imx8mn_var_som.rst create mode 100644 doc/board/variscite/index.rst create mode 100644 include/configs/imx8mn_var_som.h -- 2.30.2
[PATCH v5 1/1] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for:
- 1GiB DDR4 RAM
- 16 GiB eMMC
- SD card
- Gigabit ethernet
- USBOTG1 peripheral - fastboot
Signed-off-by: Ariel D'Alessandro
---
arch/arm/dts/Makefile | 1 +
.../dts/imx8mn-var-som-symphony-u-boot.dtsi | 256
arch/arm/dts/imx8mn-var-som-symphony.dts | 240
arch/arm/dts/imx8mn-var-som.dtsi | 547 ++
arch/arm/mach-imx/imx8m/Kconfig | 9 +
board/variscite/imx8mn_var_som/Kconfig| 17 +
board/variscite/imx8mn_var_som/MAINTAINERS| 7 +
board/variscite/imx8mn_var_som/Makefile | 12 +
board/variscite/imx8mn_var_som/ddr4_timing.c | 528 +
.../variscite/imx8mn_var_som/imx8mn_var_som.c | 30 +
.../imx8mn_var_som/imximage-8mn-ddr4.cfg | 10 +
board/variscite/imx8mn_var_som/spl.c | 93 +++
configs/imx8mn_var_som_defconfig | 98
doc/board/index.rst | 1 +
doc/board/variscite/imx8mn_var_som.rst| 56 ++
doc/board/variscite/index.rst | 9 +
include/configs/imx8mn_var_som.h | 90 +++
17 files changed, 2004 insertions(+)
create mode 100644 arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-var-som-symphony.dts
create mode 100644 arch/arm/dts/imx8mn-var-som.dtsi
create mode 100644 board/variscite/imx8mn_var_som/Kconfig
create mode 100644 board/variscite/imx8mn_var_som/MAINTAINERS
create mode 100644 board/variscite/imx8mn_var_som/Makefile
create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c
create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c
create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg
create mode 100644 board/variscite/imx8mn_var_som/spl.c
create mode 100644 configs/imx8mn_var_som_defconfig
create mode 100644 doc/board/variscite/imx8mn_var_som.rst
create mode 100644 doc/board/variscite/index.rst
create mode 100644 include/configs/imx8mn_var_som.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cc34da7bd83..8d27876fa0e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -901,6 +901,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mn-ddr4-evk.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \
+ imx8mn-var-som-symphony.dtb \
imx8mq-evk.dtb \
imx8mm-beacon-kit.dtb \
imx8mn-beacon-kit.dtb \
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
new file mode 100644
index 000..ce475885df6
--- /dev/null
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <>;
+ u-boot,dm-spl;
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_24m {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+_i2c1 {
+ u-boot,dm-spl;
+};
+
+_pmic {
+ u-boot,dm-spl;
+};
+
+_reg_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+_uart4 {
+ u-boot,dm-spl;
+};
+
+_usdhc2 {
+ u-boot,dm-spl;
+};
+
+_usdhc3 {
+ u-boot,dm-spl;
+};
+
+_wdog {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot-spl-ddr {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
+
+ 1d-imem {
+ filename = "ddr4_imem_1d.bin";
+ size = <0x8000>;
+ type = "blob-ext";
+ };
+
+ 1d_dmem {
+ filename = "ddr4_dmem_1d.bin";
+ size = <0x4000>;
+
[PATCH v5 0/1] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Changes in v5: * Fixed documentation. Changes in v4: * Added board documentation. * Cleaned up board config. Changes in v3: * Picked device tree from kernel. * Properly added MAINTAINERS entry. * Removed CONFIG_SPL_BUILD anti-pattern in board config. Changes in v2: * Reordered dt properties alphabetically. * Removed downstream stuff in bootargs. * Fixed binman configuration. * Several code styling fixes. Ariel D'Alessandro (1): imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board arch/arm/dts/Makefile | 1 + .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 256 arch/arm/dts/imx8mn-var-som-symphony.dts | 240 arch/arm/dts/imx8mn-var-som.dtsi | 547 ++ arch/arm/mach-imx/imx8m/Kconfig | 9 + board/variscite/imx8mn_var_som/Kconfig| 17 + board/variscite/imx8mn_var_som/MAINTAINERS| 7 + board/variscite/imx8mn_var_som/Makefile | 12 + board/variscite/imx8mn_var_som/ddr4_timing.c | 528 + .../variscite/imx8mn_var_som/imx8mn_var_som.c | 30 + .../imx8mn_var_som/imximage-8mn-ddr4.cfg | 10 + board/variscite/imx8mn_var_som/spl.c | 93 +++ configs/imx8mn_var_som_defconfig | 98 doc/board/index.rst | 1 + doc/board/variscite/imx8mn_var_som.rst| 56 ++ doc/board/variscite/index.rst | 9 + include/configs/imx8mn_var_som.h | 90 +++ 17 files changed, 2004 insertions(+) create mode 100644 arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-var-som-symphony.dts create mode 100644 arch/arm/dts/imx8mn-var-som.dtsi create mode 100644 board/variscite/imx8mn_var_som/Kconfig create mode 100644 board/variscite/imx8mn_var_som/MAINTAINERS create mode 100644 board/variscite/imx8mn_var_som/Makefile create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg create mode 100644 board/variscite/imx8mn_var_som/spl.c create mode 100644 configs/imx8mn_var_som_defconfig create mode 100644 doc/board/variscite/imx8mn_var_som.rst create mode 100644 doc/board/variscite/index.rst create mode 100644 include/configs/imx8mn_var_som.h -- 2.30.2
Re: [PATCH v4 1/1] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Hi Tom, On 11/16/21 2:52 PM, Tom Rini wrote: > On Tue, Nov 16, 2021 at 11:26:01AM -0300, Ariel D'Alessandro wrote: > >> Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for: >> >> - 1GiB DDR4 RAM >> - 16 GiB eMMC >> - SD card >> - Gigabit ethernet >> - USBOTG1 peripheral - fastboot >> >> Signed-off-by: Ariel D'Alessandro >> --- >> arch/arm/dts/Makefile | 1 + >> .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 256 >> arch/arm/dts/imx8mn-var-som-symphony.dts | 240 >> arch/arm/dts/imx8mn-var-som.dtsi | 547 ++ >> arch/arm/mach-imx/imx8m/Kconfig | 9 + >> board/variscite/imx8mn_var_som/Kconfig| 17 + >> board/variscite/imx8mn_var_som/MAINTAINERS| 7 + >> board/variscite/imx8mn_var_som/Makefile | 12 + >> board/variscite/imx8mn_var_som/ddr4_timing.c | 528 + >> .../variscite/imx8mn_var_som/imx8mn_var_som.c | 30 + >> .../imx8mn_var_som/imximage-8mn-ddr4.cfg | 10 + >> board/variscite/imx8mn_var_som/spl.c | 93 +++ >> configs/imx8mn_var_som_defconfig | 98 >> doc/board/variscite/imx8mn_var_som.rst| 56 ++ >> doc/board/variscite/index.rst | 9 + > > You need to update doc/board/index.rst as well, otherwise you get: > Warning, treated as error: > /home/trini/work/u-boot/u-boot/doc/board/variscite/index.rst:document isn't > included in any toctree > make[1]: *** [doc/Makefile:68: htmldocs] Error 2 > make: *** [Makefile:2250: htmldocs] Error 2 > > The easiest way to test doc building is: > $ virtualenv -p /usr/bin/python3 /tmp/venv > $ ( . /tmp/venv/bin/activate ; pip install -r doc/sphinx/requirements.txt ; > make htmldocs) Fixed, thanks a lot for the patience :-)
Re: [PATCH v4 1/1] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
On 11/16/21 2:54 PM, Fabio Estevam wrote: > On Tue, Nov 16, 2021 at 11:26 AM Ariel D'Alessandro > wrote: > >> --- /dev/null >> +++ b/doc/board/variscite/imx8mn_var_som.rst >> @@ -0,0 +1,56 @@ >> +.. SPDX-License-Identifier: GPL-2.0+ >> + >> +imx8mn_evk >> +== > > Copy and paste error :-) Ugh, :hard-facepalm: Thanks!
[PATCH v4 1/1] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for:
- 1GiB DDR4 RAM
- 16 GiB eMMC
- SD card
- Gigabit ethernet
- USBOTG1 peripheral - fastboot
Signed-off-by: Ariel D'Alessandro
---
arch/arm/dts/Makefile | 1 +
.../dts/imx8mn-var-som-symphony-u-boot.dtsi | 256
arch/arm/dts/imx8mn-var-som-symphony.dts | 240
arch/arm/dts/imx8mn-var-som.dtsi | 547 ++
arch/arm/mach-imx/imx8m/Kconfig | 9 +
board/variscite/imx8mn_var_som/Kconfig| 17 +
board/variscite/imx8mn_var_som/MAINTAINERS| 7 +
board/variscite/imx8mn_var_som/Makefile | 12 +
board/variscite/imx8mn_var_som/ddr4_timing.c | 528 +
.../variscite/imx8mn_var_som/imx8mn_var_som.c | 30 +
.../imx8mn_var_som/imximage-8mn-ddr4.cfg | 10 +
board/variscite/imx8mn_var_som/spl.c | 93 +++
configs/imx8mn_var_som_defconfig | 98
doc/board/variscite/imx8mn_var_som.rst| 56 ++
doc/board/variscite/index.rst | 9 +
include/configs/imx8mn_var_som.h | 90 +++
16 files changed, 2003 insertions(+)
create mode 100644 arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-var-som-symphony.dts
create mode 100644 arch/arm/dts/imx8mn-var-som.dtsi
create mode 100644 board/variscite/imx8mn_var_som/Kconfig
create mode 100644 board/variscite/imx8mn_var_som/MAINTAINERS
create mode 100644 board/variscite/imx8mn_var_som/Makefile
create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c
create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c
create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg
create mode 100644 board/variscite/imx8mn_var_som/spl.c
create mode 100644 configs/imx8mn_var_som_defconfig
create mode 100644 doc/board/variscite/imx8mn_var_som.rst
create mode 100644 doc/board/variscite/index.rst
create mode 100644 include/configs/imx8mn_var_som.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cc34da7bd83..8d27876fa0e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -901,6 +901,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mn-ddr4-evk.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \
+ imx8mn-var-som-symphony.dtb \
imx8mq-evk.dtb \
imx8mm-beacon-kit.dtb \
imx8mn-beacon-kit.dtb \
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
new file mode 100644
index 000..ce475885df6
--- /dev/null
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <>;
+ u-boot,dm-spl;
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_24m {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+_i2c1 {
+ u-boot,dm-spl;
+};
+
+_pmic {
+ u-boot,dm-spl;
+};
+
+_reg_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+_uart4 {
+ u-boot,dm-spl;
+};
+
+_usdhc2 {
+ u-boot,dm-spl;
+};
+
+_usdhc3 {
+ u-boot,dm-spl;
+};
+
+_wdog {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot-spl-ddr {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
+
+ 1d-imem {
+ filename = "ddr4_imem_1d.bin";
+ size = <0x8000>;
+ type = "blob-ext";
+ };
+
+ 1d_dmem {
+ filename = "ddr4_dmem_1d.bin";
+ size = <0x4000>;
+ type = "blob-ext";
+
[PATCH v4 0/1] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Changes in v4: * Added board documentation. * Cleaned up board config. Changes in v3: * Picked device tree from kernel. * Properly added MAINTAINERS entry. * Removed CONFIG_SPL_BUILD anti-pattern in board config. Changes in v2: * Reordered dt properties alphabetically. * Removed downstream stuff in bootargs. * Fixed binman configuration. * Several code styling fixes. Ariel D'Alessandro (1): imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board arch/arm/dts/Makefile | 1 + .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 256 arch/arm/dts/imx8mn-var-som-symphony.dts | 240 arch/arm/dts/imx8mn-var-som.dtsi | 547 ++ arch/arm/mach-imx/imx8m/Kconfig | 9 + board/variscite/imx8mn_var_som/Kconfig| 17 + board/variscite/imx8mn_var_som/MAINTAINERS| 7 + board/variscite/imx8mn_var_som/Makefile | 12 + board/variscite/imx8mn_var_som/ddr4_timing.c | 528 + .../variscite/imx8mn_var_som/imx8mn_var_som.c | 30 + .../imx8mn_var_som/imximage-8mn-ddr4.cfg | 10 + board/variscite/imx8mn_var_som/spl.c | 93 +++ configs/imx8mn_var_som_defconfig | 98 doc/board/variscite/imx8mn_var_som.rst| 56 ++ doc/board/variscite/index.rst | 9 + include/configs/imx8mn_var_som.h | 90 +++ 16 files changed, 2003 insertions(+) create mode 100644 arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-var-som-symphony.dts create mode 100644 arch/arm/dts/imx8mn-var-som.dtsi create mode 100644 board/variscite/imx8mn_var_som/Kconfig create mode 100644 board/variscite/imx8mn_var_som/MAINTAINERS create mode 100644 board/variscite/imx8mn_var_som/Makefile create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg create mode 100644 board/variscite/imx8mn_var_som/spl.c create mode 100644 configs/imx8mn_var_som_defconfig create mode 100644 doc/board/variscite/imx8mn_var_som.rst create mode 100644 doc/board/variscite/index.rst create mode 100644 include/configs/imx8mn_var_som.h -- 2.30.2
Re: [PATCH v3 1/1] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Hi Fabio, On 11/16/21 8:37 AM, Fabio Estevam wrote: > Hi Ariel, > > The patch looks good. Only some minor comments: > > On Tue, Nov 16, 2021 at 12:51 AM Ariel D'Alessandro > wrote: >> >> Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for: >> >> - 1GiB DDR4 RAM >> - 16 GiB eMMC >> - SD card >> - Gigabit ethernet >> - USBOTG1 peripheral - fastboot >> >> Signed-off-by: Ariel D'Alessandro > > It would be nice to have a README file so that the users can know how > to build and flash mainline > U-Boot in this board. Added that to doc/board/variscite/imx8mn_var_som.rst Will submit in v4. > >> +#define PHYS_SDRAM 0x4000 >> +#define PHYS_SDRAM_SIZESZ_1G /* 1GB DDR */ >> + >> +#define CONFIG_BAUDRATE115200 > > This is the default. No need to be specified here. Ack. > >> +#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR >> + >> +/* Monitor Command Prompt */ >> +#define CONFIG_SYS_CBSIZE SZ_2K >> +#define CONFIG_SYS_MAXARGS 64 >> +#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE >> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ >> +sizeof(CONFIG_SYS_PROMPT) + 16) >> + >> +/* USDHC */ >> +#define CONFIG_FSL_USDHC > > This should be placed in defconfig. Done. > >> +#define CONFIG_SYS_FSL_USDHC_NUM 2 > > This is not used. Please remove it. Done. Thanks a lot, Ariel
Re: [PATCH v3 1/1] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Hi Tom, On 11/16/21 10:13 AM, Tom Rini wrote: > On Tue, Nov 16, 2021 at 08:37:06AM -0300, Fabio Estevam wrote: >> Hi Ariel, >> >> The patch looks good. Only some minor comments: >> >> On Tue, Nov 16, 2021 at 12:51 AM Ariel D'Alessandro >> wrote: >>> >>> Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for: >>> >>> - 1GiB DDR4 RAM >>> - 16 GiB eMMC >>> - SD card >>> - Gigabit ethernet >>> - USBOTG1 peripheral - fastboot >>> >>> Signed-off-by: Ariel D'Alessandro >> >> It would be nice to have a README file so that the users can know how >> to build and flash mainline >> U-Boot in this board. > > And that means an entry under doc/board/variscite/ to be clear. Yes :-) thanks, will add it in v4.
[PATCH v3 1/1] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for:
- 1GiB DDR4 RAM
- 16 GiB eMMC
- SD card
- Gigabit ethernet
- USBOTG1 peripheral - fastboot
Signed-off-by: Ariel D'Alessandro
---
arch/arm/dts/Makefile | 1 +
.../dts/imx8mn-var-som-symphony-u-boot.dtsi | 256
arch/arm/dts/imx8mn-var-som-symphony.dts | 240
arch/arm/dts/imx8mn-var-som.dtsi | 547 ++
arch/arm/mach-imx/imx8m/Kconfig | 9 +
board/variscite/imx8mn_var_som/Kconfig| 17 +
board/variscite/imx8mn_var_som/MAINTAINERS| 7 +
board/variscite/imx8mn_var_som/Makefile | 12 +
board/variscite/imx8mn_var_som/ddr4_timing.c | 528 +
.../variscite/imx8mn_var_som/imx8mn_var_som.c | 30 +
.../imx8mn_var_som/imximage-8mn-ddr4.cfg | 10 +
board/variscite/imx8mn_var_som/spl.c | 93 +++
configs/imx8mn_var_som_defconfig | 98
include/configs/imx8mn_var_som.h | 95 +++
14 files changed, 1943 insertions(+)
create mode 100644 arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-var-som-symphony.dts
create mode 100644 arch/arm/dts/imx8mn-var-som.dtsi
create mode 100644 board/variscite/imx8mn_var_som/Kconfig
create mode 100644 board/variscite/imx8mn_var_som/MAINTAINERS
create mode 100644 board/variscite/imx8mn_var_som/Makefile
create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c
create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c
create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg
create mode 100644 board/variscite/imx8mn_var_som/spl.c
create mode 100644 configs/imx8mn_var_som_defconfig
create mode 100644 include/configs/imx8mn_var_som.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cc34da7bd83..8d27876fa0e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -901,6 +901,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mn-ddr4-evk.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \
+ imx8mn-var-som-symphony.dtb \
imx8mq-evk.dtb \
imx8mm-beacon-kit.dtb \
imx8mn-beacon-kit.dtb \
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
new file mode 100644
index 000..ce475885df6
--- /dev/null
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <>;
+ u-boot,dm-spl;
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_24m {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+_i2c1 {
+ u-boot,dm-spl;
+};
+
+_pmic {
+ u-boot,dm-spl;
+};
+
+_reg_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+_uart4 {
+ u-boot,dm-spl;
+};
+
+_usdhc2 {
+ u-boot,dm-spl;
+};
+
+_usdhc3 {
+ u-boot,dm-spl;
+};
+
+_wdog {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot-spl-ddr {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
+
+ 1d-imem {
+ filename = "ddr4_imem_1d.bin";
+ size = <0x8000>;
+ type = "blob-ext";
+ };
+
+ 1d_dmem {
+ filename = "ddr4_dmem_1d.bin";
+ size = <0x4000>;
+ type = "blob-ext";
+ };
+
+ 2d_imem {
+ filename = "ddr4_imem_2d.bin";
+ size = <0x8000>;
+ type = "blob-ext";
+ };
+
[PATCH v3 0/1] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Changes in v3: * Picked device tree from kernel. * Properly added MAINTAINERS entry. * Removed CONFIG_SPL_BUILD anti-pattern in board config. Changes in v2: * Reordered dt properties alphabetically. * Removed downstream stuff in bootargs. * Fixed binman configuration. * Several code styling fixes. Ariel D'Alessandro (1): imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board arch/arm/dts/Makefile | 1 + .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 256 arch/arm/dts/imx8mn-var-som-symphony.dts | 240 arch/arm/dts/imx8mn-var-som.dtsi | 547 ++ arch/arm/mach-imx/imx8m/Kconfig | 9 + board/variscite/imx8mn_var_som/Kconfig| 17 + board/variscite/imx8mn_var_som/MAINTAINERS| 7 + board/variscite/imx8mn_var_som/Makefile | 12 + board/variscite/imx8mn_var_som/ddr4_timing.c | 528 + .../variscite/imx8mn_var_som/imx8mn_var_som.c | 30 + .../imx8mn_var_som/imximage-8mn-ddr4.cfg | 10 + board/variscite/imx8mn_var_som/spl.c | 93 +++ configs/imx8mn_var_som_defconfig | 98 include/configs/imx8mn_var_som.h | 95 +++ 14 files changed, 1943 insertions(+) create mode 100644 arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-var-som-symphony.dts create mode 100644 arch/arm/dts/imx8mn-var-som.dtsi create mode 100644 board/variscite/imx8mn_var_som/Kconfig create mode 100644 board/variscite/imx8mn_var_som/MAINTAINERS create mode 100644 board/variscite/imx8mn_var_som/Makefile create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg create mode 100644 board/variscite/imx8mn_var_som/spl.c create mode 100644 configs/imx8mn_var_som_defconfig create mode 100644 include/configs/imx8mn_var_som.h -- 2.30.2
Re: [PATCH] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
On 11/15/21 6:39 PM, Fabio Estevam wrote: > On Tue, Nov 2, 2021 at 8:19 PM Ariel D'Alessandro > wrote: > >> --- /dev/null >> +++ b/arch/arm/dts/imx8mn-var-som.dts > > In the Linux kernel, this is called imx8mn-var-som.dtsi. > >> @@ -0,0 +1,425 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * Copyright 2021 Collabora Ltd. > > In the Linux kernel it has: > > // SPDX-License-Identifier: (GPL-2.0+ OR MIT) > /* > * Copyright 2019 NXP > * Copyright 2019-2020 Variscite Ltd. > * Copyright (C) 2020 Krzysztof Kozlowski > */ > > I suggest you pick the dts directly from the kernel. Makes sense. Will address in v3.
Re: [PATCH v2] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
On 11/15/21 6:28 PM, Tom Rini wrote: > On Mon, Nov 15, 2021 at 06:27:08PM -0300, Ariel D'Alessandro wrote: >> Hi Tom, >> >> Thanks for the feedback. >> >> On 11/15/21 6:11 PM, Tom Rini wrote: >>> On Mon, Nov 15, 2021 at 05:24:22PM -0300, Ariel D'Alessandro wrote: >>> >>>> Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for: >>>> >>>> - 1GiB DDR4 RAM >>>> - 16 GiB eMMC >>>> - SD card >>>> - Gigabit ethernet >>>> - USBOTG1 peripheral - fastboot >>>> >>>> Signed-off-by: Ariel D'Alessandro >>>> --- [snip] >>>> +#ifdef CONFIG_SPL_BUILD >>>> + >>>> +#define CONFIG_SPL_STACK 0x98 >>>> +#define CONFIG_SPL_BSS_START_ADDR 0x95 >>>> +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K >>>> +#define CONFIG_SYS_SPL_MALLOC_START 0x4220 >>>> +#define CONFIG_SYS_SPL_MALLOC_SIZESZ_512K >>>> + >>>> +/* For RAW image gives a error info not panic */ >>>> +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE >>>> + >>>> +#endif /* CONFIG_SPL_BUILD */ >>> >>> We can't guard CONFIG options with CONFIG_SPL_BUILD or >>> !CONFIG_SPL_BUILD. >> >> Sorry I don't understand, could you expand on the proper way to handle >> the above configuration? AFAICS, several imx8m boards follow this same >> pattern: >> >> $ git grep -l CONFIG_SPL_BUILD -- include/configs/imx8m* >> include/configs/imx8mm-cl-iot-gate.h >> include/configs/imx8mm_beacon.h >> include/configs/imx8mm_evk.h >> include/configs/imx8mm_icore_mx8mm.h >> include/configs/imx8mm_venice.h >> include/configs/imx8mn_beacon.h >> include/configs/imx8mn_evk.h >> include/configs/imx8mp_evk.h >> include/configs/imx8mq_cm.h >> include/configs/imx8mq_evk.h >> include/configs/imx8mq_phanbell.h > > Yes, it's sadly a common anti-pattern. Just always define things. I see. Will be fixed in v3. Thanks a lot! Ariel
Re: [PATCH v2] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Hi Tom, Thanks for the feedback. On 11/15/21 6:11 PM, Tom Rini wrote: > On Mon, Nov 15, 2021 at 05:24:22PM -0300, Ariel D'Alessandro wrote: > >> Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for: >> >> - 1GiB DDR4 RAM >> - 16 GiB eMMC >> - SD card >> - Gigabit ethernet >> - USBOTG1 peripheral - fastboot >> >> Signed-off-by: Ariel D'Alessandro >> --- >> MAINTAINERS | 8 + > > Typically this goes in to board/.../MAINTAINERS Will fix in v3. > >> arch/arm/dts/imx8mn-var-som.dts | 423 ++ > > What linux kernel version (or, is it just in linux-next?) is this from? It's already supported in current linux/master: $ git describe origin/master v5.16-rc1-3-g8ab774587903 > > [snip] >> +#ifdef CONFIG_SPL_BUILD >> + >> +#define CONFIG_SPL_STACK0x98 >> +#define CONFIG_SPL_BSS_START_ADDR 0x95 >> +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K >> +#define CONFIG_SYS_SPL_MALLOC_START 0x4220 >> +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K >> + >> +/* For RAW image gives a error info not panic */ >> +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE >> + >> +#endif /* CONFIG_SPL_BUILD */ > > We can't guard CONFIG options with CONFIG_SPL_BUILD or > !CONFIG_SPL_BUILD. Sorry I don't understand, could you expand on the proper way to handle the above configuration? AFAICS, several imx8m boards follow this same pattern: $ git grep -l CONFIG_SPL_BUILD -- include/configs/imx8m* include/configs/imx8mm-cl-iot-gate.h include/configs/imx8mm_beacon.h include/configs/imx8mm_evk.h include/configs/imx8mm_icore_mx8mm.h include/configs/imx8mm_venice.h include/configs/imx8mn_beacon.h include/configs/imx8mn_evk.h include/configs/imx8mp_evk.h include/configs/imx8mq_cm.h include/configs/imx8mq_evk.h include/configs/imx8mq_phanbell.h Regards, Ariel
[PATCH v2] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for:
- 1GiB DDR4 RAM
- 16 GiB eMMC
- SD card
- Gigabit ethernet
- USBOTG1 peripheral - fastboot
Signed-off-by: Ariel D'Alessandro
---
MAINTAINERS | 8 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/imx8mn-var-som-u-boot.dtsi | 256 +
arch/arm/dts/imx8mn-var-som.dts | 423 ++
arch/arm/mach-imx/imx8m/Kconfig | 9 +
board/variscite/imx8mn_var_som/Kconfig| 17 +
board/variscite/imx8mn_var_som/Makefile | 12 +
board/variscite/imx8mn_var_som/ddr4_timing.c | 528 ++
.../variscite/imx8mn_var_som/imx8mn_var_som.c | 30 +
.../imx8mn_var_som/imximage-8mn-ddr4.cfg | 10 +
board/variscite/imx8mn_var_som/spl.c | 93 +++
configs/imx8mn_var_som_defconfig | 98
include/configs/imx8mn_var_som.h | 106
13 files changed, 1591 insertions(+)
create mode 100644 arch/arm/dts/imx8mn-var-som-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-var-som.dts
create mode 100644 board/variscite/imx8mn_var_som/Kconfig
create mode 100644 board/variscite/imx8mn_var_som/Makefile
create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c
create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c
create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg
create mode 100644 board/variscite/imx8mn_var_som/spl.c
create mode 100644 configs/imx8mn_var_som_defconfig
create mode 100644 include/configs/imx8mn_var_som.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 6db5354322f..b13098c2138 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -550,6 +550,14 @@ F: arch/arm/mach-uniphier/
F: configs/uniphier_*_defconfig
N: uniphier
+ARM VARISCITE VAR-SOM-MX8MN MODULE
+M: Ariel D'Alessandro
+S: Maintained
+F: arch/arm/dts/arch/arm/dts/imx8mn-var-som*
+F: board/variscite/imx8mn_var_som/
+F: configs/imx8mn_var_som_defconfig
+F: include/configs/imx8mn_var_som.h
+
ARM VERSAL
M: Michal Simek
S: Maintained
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cc34da7bd83..dfa034be80f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -901,6 +901,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mn-ddr4-evk.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \
+ imx8mn-var-som.dtb \
imx8mq-evk.dtb \
imx8mm-beacon-kit.dtb \
imx8mn-beacon-kit.dtb \
diff --git a/arch/arm/dts/imx8mn-var-som-u-boot.dtsi
b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi
new file mode 100644
index 000..ce475885df6
--- /dev/null
+++ b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <>;
+ u-boot,dm-spl;
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_24m {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+_i2c1 {
+ u-boot,dm-spl;
+};
+
+_pmic {
+ u-boot,dm-spl;
+};
+
+_reg_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+_uart4 {
+ u-boot,dm-spl;
+};
+
+_usdhc2 {
+ u-boot,dm-spl;
+};
+
+_usdhc3 {
+ u-boot,dm-spl;
+};
+
+_wdog {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot-spl-ddr {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
+
+ 1d-imem {
+ filename = "ddr4_imem_1d.bin";
+ size = <0x8000>;
+ type = "blob-ext";
+ };
+
+ 1d_dmem {
+ filename = "ddr4_dmem_1d.bin";
+
Re: [PATCH] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Hi Marcel,
On 11/3/21 6:22 PM, Marcel Ziswiler wrote:
> Hi Ariel
>
> On Tue, 2021-11-02 at 20:18 -0300, Ariel D'Alessandro wrote:
>> Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for:
>>
>> - 1GiB DDR4 RAM
>> - 16 GiB eMMC
>> - SD card
>> - Gigabit ethernet
>> - USBOTG1 peripheral - fastboot
>>
>> Signed-off-by: Ariel D'Alessandro
>> ---
>> arch/arm/dts/Makefile | 1 +
>> arch/arm/dts/imx8mn-var-som-u-boot.dtsi | 220
>> arch/arm/dts/imx8mn-var-som.dts | 425 ++
>> arch/arm/mach-imx/imx8m/Kconfig | 9 +
>> board/variscite/imx8mn_var_som/Kconfig | 17 +
>> board/variscite/imx8mn_var_som/Makefile | 12 +
>> board/variscite/imx8mn_var_som/ddr4_timing.c | 529 ++
>> .../variscite/imx8mn_var_som/imx8mn_var_som.c | 35 ++
>> .../imx8mn_var_som/imximage-8mn-ddr4.cfg | 12 +
>> board/variscite/imx8mn_var_som/spl.c | 104
>> configs/imx8mn_var_som_defconfig | 98
>> include/configs/imx8mn_var_som.h | 106
>> 12 files changed, 1568 insertions(+)
>> create mode 100644 arch/arm/dts/imx8mn-var-som-u-boot.dtsi
>> create mode 100644 arch/arm/dts/imx8mn-var-som.dts
>> create mode 100644 board/variscite/imx8mn_var_som/Kconfig
>> create mode 100644 board/variscite/imx8mn_var_som/Makefile
>> create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c
>> create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c
>> create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg
>> create mode 100644 board/variscite/imx8mn_var_som/spl.c
>> create mode 100644 configs/imx8mn_var_som_defconfig
>> create mode 100644 include/configs/imx8mn_var_som.h
>>
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index cc34da7bd83..dfa034be80f 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -901,6 +901,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
>> imx8mn-ddr4-evk.dtb \
>> imx8mq-cm.dtb \
>> imx8mn-evk.dtb \
>> + imx8mn-var-som.dtb \
>> imx8mq-evk.dtb \
>> imx8mm-beacon-kit.dtb \
>> imx8mn-beacon-kit.dtb \
>> diff --git a/arch/arm/dts/imx8mn-var-som-u-boot.dtsi
>> b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi
>> new file mode 100644
>> index 000..73df408bc82
>> --- /dev/null
>> +++ b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi
>> @@ -0,0 +1,220 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright 2021 Collabora Ltd.
>> + */
>> +
>> +/ {
>> + binman: binman {
>> + multiple-images;
>> + };
>> +
>> + wdt-reboot {
>> + compatible = "wdt-reboot";
>> + wdt = <>;
>> + u-boot,dm-spl;
>> + };
>> +};
>> +
>> +&{/soc@0} {
>> + u-boot,dm-pre-reloc;
>> + u-boot,dm-spl;
>> +};
>> +
>> +&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
>> + u-boot,dm-spl;
>> +};
>> +
>> +&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
>> + u-boot,dm-spl;
>> +};
>> +
>> + {
>> + u-boot,dm-spl;
>> + u-boot,dm-pre-reloc;
>
> You might want to consistently order properties alphabetically (e.g. see 3
> nodes further up).
Will do.
>
>> +};
>> +
>> + {
>> + u-boot,dm-spl;
>> +};
>> +
>> + {
>> + u-boot,dm-spl;
>> +};
>> +
>> + {
>> + u-boot,dm-spl;
>> + u-boot,dm-pre-reloc;
>
> Ditto.
Will do.
>
>> + /delete-property/ assigned-clocks;
>> + /delete-property/ assigned-clock-parents;
>> + /delete-property/ assigned-clock-rates;
>> +};
>> +
>> + {
>> + u-boot,dm-spl;
>> +};
>> +
>> + {
>> + u-boot,dm-spl;
>> +};
>> +
>> + {
>> + u-boot,dm-spl;
>> +};
>> +
>> + {
>> + u-boot,dm-spl;
>> +};
>> +
>> + {
>> + u-boot,dm-spl;
>> +};
>> +
>> +_24m {
>> + u-boot,dm-spl;
>> + u-boot,dm-pre-reloc;
>
> Ditto.
Will do.
>
>> +};
>> +
>> +_i2c1 {
>> + u-boot,dm-spl;
>> +};
>> +
>> +_pmic {
>> + u-boot,dm-spl;
>> +};
>> +
>> +_reg_usdhc2_vmmc {
>> + u-boot,d
Re: [PATCH v1 2/2] bsh: imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
Hi all, On 11/3/21 4:56 PM, Ariel D'Alessandro wrote: > Introduce BSH SystemMaster (SMM) S2 board family, which consists of: > iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards. > > Add support for iMX8MN BSH SMM S2 board: > > - 256 MiB DDR3 RAM > - 512MiB Nand > - USBOTG1 peripheral - fastboot. > > Add support for iMX8MN BSH SMM S2 PRO board: > > - 512 MiB DDR3 RAM > - 8 GiB eMMC > - USBOTG1 peripheral - fastboot. > > Signed-off-by: Ariel D'Alessandro > Signed-off-by: Michael Trimarchi > --- > MAINTAINERS | 9 + > arch/arm/dts/Makefile | 2 + > arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi| 203 > .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 179 > arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi| 15 + > arch/arm/dts/imx8mn-bsh-smm-s2.dts| 48 + > arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi | 15 + > arch/arm/dts/imx8mn-bsh-smm-s2pro.dts | 75 ++ > arch/arm/mach-imx/imx8m/Kconfig | 15 + > board/bsh/imx8mn_smm_s2/Kconfig | 38 + > board/bsh/imx8mn_smm_s2/Makefile | 13 + > board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c | 943 ++ > board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c | 943 ++ > board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c | 24 + > board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg | 12 + > board/bsh/imx8mn_smm_s2/spl.c | 104 ++ > configs/imx8mn_bsh_smm_s2_defconfig | 93 ++ > configs/imx8mn_bsh_smm_s2pro_defconfig| 90 ++ > include/configs/imx8mn_bsh_smm_s2.h | 56 ++ > include/configs/imx8mn_bsh_smm_s2_common.h| 69 ++ > include/configs/imx8mn_bsh_smm_s2pro.h| 42 + > 21 files changed, 2988 insertions(+) > create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi > create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi > create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi > create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2.dts > create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi > create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro.dts > create mode 100644 board/bsh/imx8mn_smm_s2/Kconfig > create mode 100644 board/bsh/imx8mn_smm_s2/Makefile > create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c > create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c > create mode 100644 board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c > create mode 100644 board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg > create mode 100644 board/bsh/imx8mn_smm_s2/spl.c > create mode 100644 configs/imx8mn_bsh_smm_s2_defconfig > create mode 100644 configs/imx8mn_bsh_smm_s2pro_defconfig > create mode 100644 include/configs/imx8mn_bsh_smm_s2.h > create mode 100644 include/configs/imx8mn_bsh_smm_s2_common.h > create mode 100644 include/configs/imx8mn_bsh_smm_s2pro.h [snip] > diff --git a/board/bsh/imx8mn_smm_s2/Kconfig b/board/bsh/imx8mn_smm_s2/Kconfig > new file mode 100644 > index 000..37fe723e290 > --- /dev/null > +++ b/board/bsh/imx8mn_smm_s2/Kconfig > @@ -0,0 +1,38 @@ > +config BSH_SMM_S2_DDR3L_256 > + bool "BSH SMM S2 DDR3L 256 MiB RAM support" > + > +config BSH_SMM_S2_DDR3L_512 > + bool "BSH SMM S2 DDR3L 512 MiB RAM support" > + > +config SYS_BOARD > + default "imx8mn_smm_s2" > + > +config SYS_VENDOR > + default "bsh" > + > +config IMX_CONFIG > + default "board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg" > + > +if TARGET_IMX8MN_BSH_SMM_S2 > + > +config SYS_CONFIG_NAME > + default "imx8mn_bsh_smm_s2" > + > +config BOARD_SPECIFIC_OPTIONS # dummy > + def_bool y > + select BSH_SMM_S2_DDR3L_256 > + > +endif > + > +if TARGET_IMX8MN_BSH_SMM_S2PRO > + > +config SYS_CONFIG_NAME > + default "imx8mn_bsh_smm_s2pro" > + > +config BOARD_SPECIFIC_OPTIONS # dummy > + def_bool y > + select BSH_SMM_S2_DDR3L_512 > + > +endif > + > +source "board/freescale/common/Kconfig" Please omit the above, as it's totally wrong. Will fix in v2 as follows: config BSH_SMM_S2_DDR3L_256 bool "BSH SMM S2 DDR3L 256 MiB RAM support" config BSH_SMM_S2_DDR3L_512 bool "BSH SMM S2 DDR3L 512 MiB RAM support" if TARGET_IMX8MN_BSH_SMM_S2 config SYS_BOARD default "imx8mn_smm_s2" config SYS_VENDOR default "bsh" config IMX_CONFIG default "board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg" config SYS_CONFIG_NAME default "imx8mn_bsh_smm_s2" config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BSH_SMM_S2_DDR3L_
[PATCH v1 2/2] bsh: imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
Introduce BSH SystemMaster (SMM) S2 board family, which consists of:
iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards.
Add support for iMX8MN BSH SMM S2 board:
- 256 MiB DDR3 RAM
- 512MiB Nand
- USBOTG1 peripheral - fastboot.
Add support for iMX8MN BSH SMM S2 PRO board:
- 512 MiB DDR3 RAM
- 8 GiB eMMC
- USBOTG1 peripheral - fastboot.
Signed-off-by: Ariel D'Alessandro
Signed-off-by: Michael Trimarchi
---
MAINTAINERS | 9 +
arch/arm/dts/Makefile | 2 +
arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi| 203
.../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 179
arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi| 15 +
arch/arm/dts/imx8mn-bsh-smm-s2.dts| 48 +
arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi | 15 +
arch/arm/dts/imx8mn-bsh-smm-s2pro.dts | 75 ++
arch/arm/mach-imx/imx8m/Kconfig | 15 +
board/bsh/imx8mn_smm_s2/Kconfig | 38 +
board/bsh/imx8mn_smm_s2/Makefile | 13 +
board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c | 943 ++
board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c | 943 ++
board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c | 24 +
board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg | 12 +
board/bsh/imx8mn_smm_s2/spl.c | 104 ++
configs/imx8mn_bsh_smm_s2_defconfig | 93 ++
configs/imx8mn_bsh_smm_s2pro_defconfig| 90 ++
include/configs/imx8mn_bsh_smm_s2.h | 56 ++
include/configs/imx8mn_bsh_smm_s2_common.h| 69 ++
include/configs/imx8mn_bsh_smm_s2pro.h| 42 +
21 files changed, 2988 insertions(+)
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2.dts
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro.dts
create mode 100644 board/bsh/imx8mn_smm_s2/Kconfig
create mode 100644 board/bsh/imx8mn_smm_s2/Makefile
create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c
create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c
create mode 100644 board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c
create mode 100644 board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg
create mode 100644 board/bsh/imx8mn_smm_s2/spl.c
create mode 100644 configs/imx8mn_bsh_smm_s2_defconfig
create mode 100644 configs/imx8mn_bsh_smm_s2pro_defconfig
create mode 100644 include/configs/imx8mn_bsh_smm_s2.h
create mode 100644 include/configs/imx8mn_bsh_smm_s2_common.h
create mode 100644 include/configs/imx8mn_bsh_smm_s2pro.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 9d8cba90280..82b9c1ff20b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -197,6 +197,15 @@ F: doc/README.bcm7xxx
F: drivers/mmc/bcmstb_sdhci.c
F: drivers/spi/bcmstb_spi.c
+ARM BSH SMM S2 boards
+M: Ariel D'Alessandro
+M: Michael Trimarchi
+S: Maintained
+F: arch/arm/dts/imx8mn-bsh-smm-s2*
+F: board/bsh/imx8mn_smm_s2/
+F: configs/imx8mn_bsh_smm_s2*
+F: include/configs/imx8mn_bsh_smm_s2*
+
ARM CORTINA ACCESS CA
M: Alex Nemirovsky
S: Supported
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cc34da7bd83..7d21c32f62f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -898,6 +898,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-venice-gw7902.dtb \
imx8mm-verdin.dtb \
phycore-imx8mm.dtb \
+ imx8mn-bsh-smm-s2.dtb \
+ imx8mn-bsh-smm-s2pro.dtb \
imx8mn-ddr4-evk.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \
diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
b/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
new file mode 100644
index 000..d08f6cb76f4
--- /dev/null
+++ b/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ * Copyright 2021 BSH Hausgeraete GmbH
+ */
+
+/dts-v1/;
+
+#include "imx8mn.dtsi"
+
+/ {
+ chosen {
+ bootargs = "console=ttymxc3,115200
earlycon=ec_imx6q,0x30a6,115200";
+ stdout-path =
+ };
+};
+
+_0 {
+ cpu-supply = <_reg>;
+};
+
+_1 {
+ cpu-supply = <_reg>;
+};
+
+_2 {
+ cpu-supply = <_reg>;
+};
+
+_3 {
+ cpu-supply = <_reg>;
+};
+
+ {
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL
0x40c2
+ MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA
0x40c2
+ >;
+ };
+
+ pinctrl_pmic: pmicirq {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x040
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
[PATCH v1 1/2] imx8m: add regs used by GPMI
From: Michael Trimarchi Add regs used by GPMI Signed-off-by: Michael Trimarchi Signed-off-by: Ariel D'Alessandro --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index b800da13a1e..14955d10900 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -58,6 +58,13 @@ #define SRC_DDRC_RCR_ADDR 0x30391000 #define SRC_DDRC2_RCR_ADDR 0x30391004 +#define APBH_DMA_ARB_BASE_ADDR 0x3300 +#define APBH_DMA_ARB_END_ADDR 0x33007FFF +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR + +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) + #define DDRC_DDR_SS_GPR0 0x3d00 #define DDRC_IPS_BASE_ADDR(X) (0x3d40 + ((X) * 0x200)) #define DDR_CSD1_BASE_ADDR 0x4000 -- 2.30.2
Re: [PATCH] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
+Cc Sjoerd
On 11/2/21 8:18 PM, Ariel D'Alessandro wrote:
> Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for:
>
> - 1GiB DDR4 RAM
> - 16 GiB eMMC
> - SD card
> - Gigabit ethernet
> - USBOTG1 peripheral - fastboot
>
> Signed-off-by: Ariel D'Alessandro
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/imx8mn-var-som-u-boot.dtsi | 220
> arch/arm/dts/imx8mn-var-som.dts | 425 ++
> arch/arm/mach-imx/imx8m/Kconfig | 9 +
> board/variscite/imx8mn_var_som/Kconfig| 17 +
> board/variscite/imx8mn_var_som/Makefile | 12 +
> board/variscite/imx8mn_var_som/ddr4_timing.c | 529 ++
> .../variscite/imx8mn_var_som/imx8mn_var_som.c | 35 ++
> .../imx8mn_var_som/imximage-8mn-ddr4.cfg | 12 +
> board/variscite/imx8mn_var_som/spl.c | 104
> configs/imx8mn_var_som_defconfig | 98
> include/configs/imx8mn_var_som.h | 106
> 12 files changed, 1568 insertions(+)
> create mode 100644 arch/arm/dts/imx8mn-var-som-u-boot.dtsi
> create mode 100644 arch/arm/dts/imx8mn-var-som.dts
> create mode 100644 board/variscite/imx8mn_var_som/Kconfig
> create mode 100644 board/variscite/imx8mn_var_som/Makefile
> create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c
> create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c
> create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg
> create mode 100644 board/variscite/imx8mn_var_som/spl.c
> create mode 100644 configs/imx8mn_var_som_defconfig
> create mode 100644 include/configs/imx8mn_var_som.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index cc34da7bd83..dfa034be80f 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -901,6 +901,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
> imx8mn-ddr4-evk.dtb \
> imx8mq-cm.dtb \
> imx8mn-evk.dtb \
> + imx8mn-var-som.dtb \
> imx8mq-evk.dtb \
> imx8mm-beacon-kit.dtb \
> imx8mn-beacon-kit.dtb \
> diff --git a/arch/arm/dts/imx8mn-var-som-u-boot.dtsi
> b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi
> new file mode 100644
> index 000..73df408bc82
> --- /dev/null
> +++ b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi
> @@ -0,0 +1,220 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2021 Collabora Ltd.
> + */
> +
> +/ {
> + binman: binman {
> + multiple-images;
> + };
> +
> + wdt-reboot {
> + compatible = "wdt-reboot";
> + wdt = <>;
> + u-boot,dm-spl;
> + };
> +};
> +
> +&{/soc@0} {
> + u-boot,dm-pre-reloc;
> + u-boot,dm-spl;
> +};
> +
> +&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
> + u-boot,dm-spl;
> +};
> +
> +&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> + u-boot,dm-pre-reloc;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> + u-boot,dm-pre-reloc;
> + /delete-property/ assigned-clocks;
> + /delete-property/ assigned-clock-parents;
> + /delete-property/ assigned-clock-rates;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> +_24m {
> + u-boot,dm-spl;
> + u-boot,dm-pre-reloc;
> +};
> +
> +_i2c1 {
> + u-boot,dm-spl;
> +};
> +
> +_pmic {
> + u-boot,dm-spl;
> +};
> +
> +_reg_usdhc2_vmmc {
> + u-boot,dm-spl;
> +};
> +
> +_uart4 {
> + u-boot,dm-spl;
> +};
> +
> +_usdhc2 {
> + u-boot,dm-spl;
> +};
> +
> +_usdhc3 {
> + u-boot,dm-spl;
> +};
> +
> +_wdog {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot-spl-ddr {
> + filename = "u-boot-spl-ddr.bin";
> + pad-byte = <0xff>;
> + align-size = <4>;
> + align = <4>;
> +
> + u-boot-spl {
> + align-end = <4>;
> + };
> +
> + blob_1: blob-ext@1 {
> + filename = "ddr4_imem_1d.bi
[PATCH] imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for:
- 1GiB DDR4 RAM
- 16 GiB eMMC
- SD card
- Gigabit ethernet
- USBOTG1 peripheral - fastboot
Signed-off-by: Ariel D'Alessandro
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/imx8mn-var-som-u-boot.dtsi | 220
arch/arm/dts/imx8mn-var-som.dts | 425 ++
arch/arm/mach-imx/imx8m/Kconfig | 9 +
board/variscite/imx8mn_var_som/Kconfig| 17 +
board/variscite/imx8mn_var_som/Makefile | 12 +
board/variscite/imx8mn_var_som/ddr4_timing.c | 529 ++
.../variscite/imx8mn_var_som/imx8mn_var_som.c | 35 ++
.../imx8mn_var_som/imximage-8mn-ddr4.cfg | 12 +
board/variscite/imx8mn_var_som/spl.c | 104
configs/imx8mn_var_som_defconfig | 98
include/configs/imx8mn_var_som.h | 106
12 files changed, 1568 insertions(+)
create mode 100644 arch/arm/dts/imx8mn-var-som-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-var-som.dts
create mode 100644 board/variscite/imx8mn_var_som/Kconfig
create mode 100644 board/variscite/imx8mn_var_som/Makefile
create mode 100644 board/variscite/imx8mn_var_som/ddr4_timing.c
create mode 100644 board/variscite/imx8mn_var_som/imx8mn_var_som.c
create mode 100644 board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg
create mode 100644 board/variscite/imx8mn_var_som/spl.c
create mode 100644 configs/imx8mn_var_som_defconfig
create mode 100644 include/configs/imx8mn_var_som.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cc34da7bd83..dfa034be80f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -901,6 +901,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mn-ddr4-evk.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \
+ imx8mn-var-som.dtb \
imx8mq-evk.dtb \
imx8mm-beacon-kit.dtb \
imx8mn-beacon-kit.dtb \
diff --git a/arch/arm/dts/imx8mn-var-som-u-boot.dtsi
b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi
new file mode 100644
index 000..73df408bc82
--- /dev/null
+++ b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Collabora Ltd.
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <>;
+ u-boot,dm-spl;
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+_i2c1 {
+ u-boot,dm-spl;
+};
+
+_pmic {
+ u-boot,dm-spl;
+};
+
+_reg_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+_uart4 {
+ u-boot,dm-spl;
+};
+
+_usdhc2 {
+ u-boot,dm-spl;
+};
+
+_usdhc3 {
+ u-boot,dm-spl;
+};
+
+_wdog {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ blob_1: blob-ext@1 {
+ filename = "ddr4_imem_1d.bin";
+ size = <0x8000>;
+ };
+
+ blob_2: blob-ext@2 {
+ filename = "ddr4_dmem_1d.bin";
+ size = <0x4000>;
+ };
+
+ blob_3: blob-ext@3 {
+ filename = "ddr4_imem_2d.bin";
+ size = <0x8000>;
+ };
+
+ blob_4: blob-ext@4 {
+ filename = "ddr4_dmem_2d.bin";
+ size = <0x4000>;
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ #address-cells = <1>;
+ fit,external-off
Re: [PATCH] tools: imx8m_image: Support ddr3 firmware
+Cc Sebastien, Frieder, Baruch, Adding you as you were involved in this file commit log. Any comments on this simple patch? On 9/30/21 10:31 AM, Ariel D'Alessandro wrote: > Some boards use ddr3, not ddr4, so we need to check ddr3 firmware. Some boards are still using this script, instead of binman, to properly pad the firmware files and generate the final image. Could we add this simple fix to also support ddr3? > > Signed-off-by: Ariel D'Alessandro > --- > tools/imx8m_image.sh | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/tools/imx8m_image.sh b/tools/imx8m_image.sh > index ba601044435..4ab3116ee00 100755 > --- a/tools/imx8m_image.sh > +++ b/tools/imx8m_image.sh > @@ -41,6 +41,13 @@ if [ $post_process = 1 ]; then > cat spl/u-boot-spl-pad.bin ddr4_1d_fw.bin ddr4_2d_fw.bin > > spl/u-boot-spl-ddr.bin > rm -f ddr4_1d_fw.bin ddr4_2d_fw.bin ddr4_imem_1d_pad.bin > ddr4_dmem_1d_pad.bin ddr4_imem_2d_pad.bin spl/u-boot-spl-pad.bin > fi > + if [ -f ddr3_imem_1d.bin ]; then > + objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 > ddr3_imem_1d.bin ddr3_imem_1d_pad.bin > + cat ddr3_imem_1d_pad.bin ddr3_dmem_1d.bin > ddr3_1d_fw.bin > + dd if=spl/u-boot-spl.bin of=spl/u-boot-spl-pad.bin bs=4 > conv=sync > + cat spl/u-boot-spl-pad.bin ddr3_1d_fw.bin > > spl/u-boot-spl-ddr.bin > + rm -f ddr3_1d_fw.bin ddr3_imem_1d_pad.bin spl/u-boot-spl-pad.bin > + fi > fi > > exit 0 > Regards, Ariel
Re: [PATCH] fastboot: mmc: Fix dest size in strlcat()
Hi Sean, On 9/30/21 12:15 PM, Sean Anderson wrote: > > > > On 9/30/21 9:47 AM, Ariel D'Alessandro wrote: >> strlcat() is truncating the destination string to the size of the source >> string. Fix size argument in strlcat() to match the size of destination >> buffer. >> >> Bug was introduced in the following commit: >> >> commit 69a752983171c2983fc1f29c7cfa1844f41e5d8b >> Author: Sean Anderson >> >> fastboot: Fix possible buffer overrun >> >> Signed-off-by: Ariel D'Alessandro >> --- >> drivers/fastboot/fb_mmc.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c >> index cbb3f7b1dea..4c54f0c3893 100644 >> --- a/drivers/fastboot/fb_mmc.c >> +++ b/drivers/fastboot/fb_mmc.c >> @@ -40,7 +40,7 @@ static int raw_part_get_info_by_name(struct blk_desc >> *dev_desc, >> >> /* check for raw partition descriptor */ >> strcpy(env_desc_name, "fastboot_raw_partition_"); >> - strlcat(env_desc_name, name, PART_NAME_LEN); >> + strlcat(env_desc_name, name, ARRAY_SIZE(env_desc_name)); >> raw_part_desc = strdup(env_get(env_desc_name)); >> if (raw_part_desc == NULL) >> return -ENODEV; >> @@ -114,7 +114,7 @@ static int part_get_info_by_name_or_alias(struct >> blk_desc **dev_desc, >> >> /* check for alias */ >> strcpy(env_alias_name, "fastboot_partition_alias_"); >> - strlcat(env_alias_name, name, PART_NAME_LEN); >> + strlcat(env_alias_name, name, ARRAY_SIZE(env_alias_name)); >> aliased_part_name = env_get(env_alias_name); >> if (aliased_part_name != NULL) >> ret = do_get_part_info(dev_desc, aliased_part_name, >> > > This looks like a duplicate of [1]. I think the only difference is > ARRAY_SIZE vs sizeof, but they are equivalent since sizeof(char) == 1. Ah, you're right. Sorry I missed that patch. > > --Sean > > [1] > http://patchwork.ozlabs.org/project/uboot/patch/20210730122354.6281-1-matthias.schif...@ew.tq-group.com/ >
[PATCH] fastboot: mmc: Fix dest size in strlcat()
strlcat() is truncating the destination string to the size of the source string. Fix size argument in strlcat() to match the size of destination buffer. Bug was introduced in the following commit: commit 69a752983171c2983fc1f29c7cfa1844f41e5d8b Author: Sean Anderson fastboot: Fix possible buffer overrun Signed-off-by: Ariel D'Alessandro --- drivers/fastboot/fb_mmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c index cbb3f7b1dea..4c54f0c3893 100644 --- a/drivers/fastboot/fb_mmc.c +++ b/drivers/fastboot/fb_mmc.c @@ -40,7 +40,7 @@ static int raw_part_get_info_by_name(struct blk_desc *dev_desc, /* check for raw partition descriptor */ strcpy(env_desc_name, "fastboot_raw_partition_"); - strlcat(env_desc_name, name, PART_NAME_LEN); + strlcat(env_desc_name, name, ARRAY_SIZE(env_desc_name)); raw_part_desc = strdup(env_get(env_desc_name)); if (raw_part_desc == NULL) return -ENODEV; @@ -114,7 +114,7 @@ static int part_get_info_by_name_or_alias(struct blk_desc **dev_desc, /* check for alias */ strcpy(env_alias_name, "fastboot_partition_alias_"); - strlcat(env_alias_name, name, PART_NAME_LEN); + strlcat(env_alias_name, name, ARRAY_SIZE(env_alias_name)); aliased_part_name = env_get(env_alias_name); if (aliased_part_name != NULL) ret = do_get_part_info(dev_desc, aliased_part_name, -- 2.30.2
[PATCH] tools: imx8m_image: Support ddr3 firmware
Some boards use ddr3, not ddr4, so we need to check ddr3 firmware. Signed-off-by: Ariel D'Alessandro --- tools/imx8m_image.sh | 7 +++ 1 file changed, 7 insertions(+) diff --git a/tools/imx8m_image.sh b/tools/imx8m_image.sh index ba601044435..4ab3116ee00 100755 --- a/tools/imx8m_image.sh +++ b/tools/imx8m_image.sh @@ -41,6 +41,13 @@ if [ $post_process = 1 ]; then cat spl/u-boot-spl-pad.bin ddr4_1d_fw.bin ddr4_2d_fw.bin > spl/u-boot-spl-ddr.bin rm -f ddr4_1d_fw.bin ddr4_2d_fw.bin ddr4_imem_1d_pad.bin ddr4_dmem_1d_pad.bin ddr4_imem_2d_pad.bin spl/u-boot-spl-pad.bin fi + if [ -f ddr3_imem_1d.bin ]; then + objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 ddr3_imem_1d.bin ddr3_imem_1d_pad.bin + cat ddr3_imem_1d_pad.bin ddr3_dmem_1d.bin > ddr3_1d_fw.bin + dd if=spl/u-boot-spl.bin of=spl/u-boot-spl-pad.bin bs=4 conv=sync + cat spl/u-boot-spl-pad.bin ddr3_1d_fw.bin > spl/u-boot-spl-ddr.bin + rm -f ddr3_1d_fw.bin ddr3_imem_1d_pad.bin spl/u-boot-spl-pad.bin + fi fi exit 0 -- 2.30.2
Re: [U-Boot] [PATCH 07/12] ns16550: unify serial_rockchip
Hi Thomas, El 16/11/15 a las 21:35, Thomas Chou escribió: > Hi Ariel, > > On 2015年11月16日 22:36, Thomas Chou wrote: >> Unify serial_rockchip, and use the generic binding. >> >> Signed-off-by: Thomas Chou <tho...@wytron.com.tw> >> --- >> arch/arm/mach-rockchip/Kconfig | 8 +++- >> drivers/serial/Kconfig | 9 - >> drivers/serial/Makefile | 1 - >> drivers/serial/serial_rockchip.c | 43 >> >> 4 files changed, 7 insertions(+), 54 deletions(-) >> delete mode 100644 drivers/serial/serial_rockchip.c >> > > Please check this series. Though I run buildman, I don't have a rockchip > board to test. Thanks. Successfully tested on a Firefly RK3288 board. Tested-by: Ariel D'Alessandro <ar...@vanguardiasur.com.ar> -- Ariel D'Alessandro, VanguardiaSur www.vanguardiasur.com.ar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] rockchip: Turn on CONFIG_DEBUG_UART_NS16550 in defconfigs
No UART driver was specified in defconfig, thus DEBUG_UART_ALTERA_JTAGUART was incorrectly selected by default since commit 220e8021af96741bd7149ca9895e1f0c8a38d0bb added a new Altera UART driver. Signed-off-by: Ariel D'Alessandro <ar...@vanguardiasur.com.ar> --- configs/chromebook_jerry_defconfig | 1 + configs/firefly-rk3288_defconfig | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 3ded392..5d39a9a 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -33,6 +33,7 @@ CONFIG_REGULATOR_ACT8846=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_NS16550=y CONFIG_DEBUG_UART_BASE=0xff69 CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index edb2db2..6f42377 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -3,9 +3,9 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_FIREFLY_RK3288=y +CONFIG_SPL_STACK_R_ADDR=0x8 CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly" CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_ADDR=0x8 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PMIC=y @@ -34,6 +34,7 @@ CONFIG_REGULATOR_ACT8846=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_NS16550=y CONFIG_DEBUG_UART_BASE=0xff69 CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART_SHIFT=2 -- 2.6.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] rockchip: move SYS_MALLOC_SIMPLE to mach-rockchip Kconfig
Commit 1eb0c03c2198a7ec9de456b83dacdc4831b96cbf added SPL_SYS_MALLOC_SIMPLE Kconfig option and changed the way it is evaluated. Thus, the definitions of CONFIG_SYS_MALLOC_SIMPLE in rk3***_common.h board configs are now incorrect because CONFIG_SPL_BUILD is enabled so CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) will look for SPL_SYS_MALLOC_SIMPLE instead of SYS_MALLOC_SIMPLE. This commit fix this enabling SPL_SYS_MALLOC_SIMPLE with the new Kconfig option by default in rockchip-mach. Signed-off-by: Ariel D'Alessandro <ar...@vanguardiasur.com.ar> --- arch/arm/mach-rockchip/Kconfig | 3 +++ include/configs/rk3036_common.h | 4 include/configs/rk3288_common.h | 4 3 files changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6dddbab..607cb71 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -31,6 +31,9 @@ config ROCKCHIP_MAX_INIT_SIZE config SYS_MALLOC_F default y +config SPL_SYS_MALLOC_SIMPLE + default y + config SPL_DM default y diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index b7f78d5..4d3610f 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -27,10 +27,6 @@ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_MEM32 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - #define CONFIG_SYS_TEXT_BASE 0x6000 #define CONFIG_SYS_INIT_SP_ADDR0x6010 #define CONFIG_SYS_LOAD_ADDR 0x60800800 diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 5ba084d..74c7ee1 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -34,10 +34,6 @@ #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SPL_BOARD_INIT -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - #define CONFIG_SYS_TEXT_BASE 0x0010 #define CONFIG_SYS_INIT_SP_ADDR0x0010 #define CONFIG_SYS_LOAD_ADDR 0x00800800 -- 2.6.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/2] rockchip: fixes in config files
Hi, This patchset fixes some issues found in Rockchip's configuration due to previuos patches that add/modified some u-boot config options. It is built on top of Lin Huang's patchset: [PATCH v5 00/21] Bring up rk3036 uboot Best regards, Ariel D'Alessandro (2): rockchip: Turn on CONFIG_DEBUG_UART_NS16550 in defconfigs rockchip: move SYS_MALLOC_SIMPLE to mach-rockchip Kconfig arch/arm/mach-rockchip/Kconfig | 3 +++ configs/chromebook_jerry_defconfig | 1 + configs/firefly-rk3288_defconfig | 3 ++- include/configs/rk3036_common.h| 4 include/configs/rk3288_common.h| 4 5 files changed, 6 insertions(+), 9 deletions(-) -- 2.6.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 12/21] rockchip: rk3036: Add pinctrl driver
Hi Lin, El 10/11/15 a las 07:24, Lin Huang escribió: > Add a driver which support pin multiplexing setup for rk3036 > > Signed-off-by: Lin Huang <h...@rock-chips.com> > Acked-by: Simon Glass <s...@chromium.org> > --- > Changes in v1: > - clean copyright announcement > Changes in v2: None > Changes in v3: > - fix some coding style error > Changes in v4: None > Changes in v5: None > > drivers/pinctrl/Kconfig | 18 ++ > drivers/pinctrl/rockchip/Makefile | 1 + > drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 > ++ > 3 files changed, 295 insertions(+) > create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c > > diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig > index 3b6e3b7..6495313 100644 > --- a/drivers/pinctrl/Kconfig > +++ b/drivers/pinctrl/Kconfig > @@ -114,6 +114,24 @@ config ROCKCHIP_PINCTRL > definitions and pin control functions for each available multiplex > function. > > +config ROCKCHIP_3036_PINCTRL > + bool "Rockchip rk3036 pin control driver" > + depends on DM > + help > + Support pin multiplexing control on Rockchip rk3036 SoCs. The driver > is > + controlled by a device tree node which contains both the GPIO > + definitions and pin control functions for each available multiplex > + function. > + > +config ROCKCHIP_PINCTRL You're duplicating ROCKCHIP_PINCTRL entry here. > + bool "Rockchip pin control driver" > + depends on DM > + help > + Support pin multiplexing control on Rockchip SoCs. The driver is > + controlled by a device tree node which contains both the GPIO > + definitions and pin control functions for each available multiplex > + function. > + > config PINCTRL_SANDBOX > bool "Sandbox pinctrl driver" > depends on SANDBOX [...] -- Ariel D'Alessandro, VanguardiaSur www.vanguardiasur.com.ar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] rockchip: Turn on CONFIG_DEBUG_LL for firefly
Eze, El 12/11/15 a las 19:11, Ezequiel Garcia escribió: > On 12 November 2015 at 18:42, Ariel D'Alessandro > <ar...@vanguardiasur.com.ar> wrote: >> CONFIG_DEBUG_UART is enabled in defconfig, but there's no Low-level >> debugging functions implemented, so build fails because of undefined >> references to `printch' in common/console.c. >> In order to fix this, enable CONFIG_DEBUG_LL. >> > > I think you are fixing this the wrong way. This patch > solves the problem as well, and I think it's the right way: > > [patch format is probably wasted] > @@ -34,6 +34,7 @@ CONFIG_REGULATOR_ACT8846=y > CONFIG_RAM=y > CONFIG_SPL_RAM=y > CONFIG_DEBUG_UART=y > +CONFIG_DEBUG_UART_NS16550=y > CONFIG_DEBUG_UART_BASE=0xff69 > CONFIG_DEBUG_UART_CLOCK=2400 > CONFIG_DEBUG_UART_SHIFT=2 > > Without this fix, Altera JTAG UART is selected instead of NS16550. You're right. No UART driver is specified in defconfig, thus DEBUG_UART_ALTERA_JTAGUART is incorrectly selected by default. In fact, firefly-rk3288_defconfig got broken after the following commit was applied: commit 220e8021af96741bd7149ca9895e1f0c8a38d0bb Author: Thomas Chou <tho...@wytron.com.tw> nios2: convert altera_jtag_uart to driver model > I expect other defconfigs (e.g. chromebook_jerry_defconfig) to suffer > from this as well. Yes, chromebook_jerry_defconfig has exactly the same problem. > > That said, I still haven't looked at the differences between > DEBUG_LL and DEBUG_UART. > -- Ariel D'Alessandro, VanguardiaSur www.vanguardiasur.com.ar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] rockchip: Turn on CONFIG_DEBUG_LL for firefly
CONFIG_DEBUG_UART is enabled in defconfig, but there's no Low-level debugging functions implemented, so build fails because of undefined references to `printch' in common/console.c. In order to fix this, enable CONFIG_DEBUG_LL. Signed-off-by: Ariel D'Alessandro <ar...@vanguardiasur.com.ar> --- configs/firefly-rk3288_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index edb2db2..446ade9 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -3,9 +3,11 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_FIREFLY_RK3288=y +CONFIG_SPL_STACK_R_ADDR=0x8 +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_UART_PHYS=0xff69 CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly" CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_ADDR=0x8 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PMIC=y -- 2.6.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
