Re: [U-Boot] [PATCH 1/2] spi: add support for ARM PL022 SPI controller
Quentin,
Thx for resurrecting it!
I took a quick look and it seems good to me.
Armando
On 08/07/2018 11:17 AM, Quentin Schulz wrote:
This adds support for the ARM PL022 SPI controller for the standard
variant (0x00041022) which has a 16bit wide and 8 locations deep TX/RX
FIFO.
A few parts were borrowed from the Linux kernel driver.
Cc: Armando Visconti
Cc: Vipin Kumar
Signed-off-by: Quentin Schulz
---
Based on "[PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller"
from Armando Visconti sent about 5 years ago.
Modifications:
- use readw/writew instead of readl/writel functions since the registers
are 16bit wide and not 32,
- flush the RX FIFO before claiming and releasing the bus (taken from the
Linux kernel driver),
- migrate to DM,
- rework the register access (defines instead of a structure),
- fix the set_speed function (taken from Linux kernel driver),
drivers/spi/Kconfig | 8 +-
drivers/spi/Makefile| 1 +-
drivers/spi/pl022_spi.c | 337 +-
include/pl022_spi.h | 28 +++-
4 files changed, 374 insertions(+)
create mode 100644 drivers/spi/pl022_spi.c
create mode 100644 include/pl022_spi.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index dcd719f..7d4d47d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -125,6 +125,14 @@ config PIC32_SPI
to access the SPI NOR flash, MMC-over-SPI on platforms based on
Microchip PIC32 family devices.
+config PL022_SPI
+ bool "ARM AMBA PL022 SSP controller driver"
+ depends on ARM
+ help
+ This selects the ARM(R) AMBA(R) PrimeCell PL022 SSP
+ controller. If you have an embedded system with an AMBA(R)
+ bus and a PL022 controller, say Y or M here.
+
config RENESAS_RPC_SPI
bool "Renesas RPC SPI driver"
depends on RCAR_GEN3
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 728e30c..6679987 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_MXS_SPI) += mxs_spi.o
obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o
obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
+obj-$(CONFIG_PL022_SPI) += pl022_spi.o
obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
new file mode 100644
index 000..dc494a5
--- /dev/null
+++ b/drivers/spi/pl022_spi.c
@@ -0,0 +1,337 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visco...@st.com.
+ *
+ * (C) Copyright 2018
+ * Quentin Schulz, Bootlin, quentin.sch...@bootlin.com
+ *
+ * Driver for ARM PL022 SPI Controller.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SSP_CR0(r) (r + 0x000)
+#define SSP_CR1(r) (r + 0x004)
+#define SSP_DR(r) (r + 0x008)
+#define SSP_SR(r) (r + 0x00C)
+#define SSP_CPSR(r)(r + 0x010)
+#define SSP_IMSC(r)(r + 0x014)
+#define SSP_RIS(r) (r + 0x018)
+#define SSP_MIS(r) (r + 0x01C)
+#define SSP_ICR(r) (r + 0x020)
+#define SSP_DMACR(r) (r + 0x024)
+#define SSP_CSR(r) (r + 0x030) /* vendor extension */
+#define SSP_ITCR(r)(r + 0x080)
+#define SSP_ITIP(r)(r + 0x084)
+#define SSP_ITOP(r)(r + 0x088)
+#define SSP_TDR(r) (r + 0x08C)
+
+#define SSP_PID0(r)(r + 0xFE0)
+#define SSP_PID1(r)(r + 0xFE4)
+#define SSP_PID2(r)(r + 0xFE8)
+#define SSP_PID3(r)(r + 0xFEC)
+
+#define SSP_CID0(r)(r + 0xFF0)
+#define SSP_CID1(r)(r + 0xFF4)
+#define SSP_CID2(r)(r + 0xFF8)
+#define SSP_CID3(r)(r + 0xFFC)
+
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO(0x1 << 6)
+#define SSP_CR0_SPH(0x1 << 7)
+#define SSP_CR0_BIT_MODE(x)((x) - 1)
+#define SSP_SCR_MIN(0x00)
+#define SSP_SCR_MAX(0xFF)
+#define SSP_SCR_SHFT 8
+#define DFLT_CLKRATE 2
+
+/* SSP Control Register 1 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 << 1)
+
+#define SSP_CPSR_MIN (0x02)
+#define SSP_CPSR_MAX (0xFE)
+#define DFLT_PRESCALE (0x40)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE(0x1 << 0) /* Transmit FIFO empty */
+#define SSP_SR_MASK_TNF(0x1 << 1) /* Transmit FIFO not full */
+#define SSP_SR_MASK_RNE(0x1 << 2) /* Receive FIFO not empty */
+#define SSP_SR_MASK_RFF(0x1 << 3) /* Receive FIFO full */
+#define SSP_SR_MASK_BSY(0x1 << 4) /* Busy Flag */
+
+struct pl022_spi_slave {
+ void *base;
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct clk clk;
+#else
+ unsigned int freq;
+#endif
+};
+
+/*
+
Re: [U-Boot] [PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller
/pl022_spi.c
+++ b/drivers/spi/pl022_spi.c
@@ -0,0 +1,321 @@
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visconti at st.com.
+ *
+ * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c
+ * by Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* Comment by Jagan: Use latest SPDX-License-Identifier: >> check for any
existing one. */
+
+#include
+#include
+#include
+#include
+//#include
+
+/* SSP registers mapping */
+/* Comment by Jagan: Something like pl022_spi_regs*/
+struct pl022 {
+ u32 ssp_cr0;/* 0x000 */
+ u32 ssp_cr1;/* 0x004 */
+ u32 ssp_dr; /* 0x008 */
+ u32 ssp_sr; /* 0x00c */
+ u32 ssp_cpsr; /* 0x010 */
+ u32 ssp_imsc; /* 0x014 */
+ u32 ssp_ris;/* 0x018 */
+ u32 ssp_mis;/* 0x01c */
+ u32 ssp_icr;/* 0x020 */
+ u32 ssp_dmacr; /* 0x024 */
+ u8 reserved_1[0x080 - 0x028];
+ u32 ssp_itcr; /* 0x080 */
+ u32 ssp_itip; /* 0x084 */
+ u32 ssp_itop; /* 0x088 */
+ u32 ssp_tdr;/* 0x08c */
+ u8 reserved_2[0xFE0 - 0x090];
+ u32 ssp_pid0; /* 0xfe0 */
+ u32 ssp_pid1; /* 0xfe4 */
+ u32 ssp_pid2; /* 0xfe8 */
+ u32 ssp_pid3; /* 0xfec */
+ u32 ssp_cid0; /* 0xff0 */
+ u32 ssp_cid1; /* 0xff4 */
+ u32 ssp_cid2; /* 0xff8 */
+ u32 ssp_cid3; /* 0xffc */
+};
+
+/* Comment by Jagan: -- TAG+*/
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO(0x1 << 6)
+#define SSP_CR0_SPH(0x1 << 7)
+#define SSP_CR0_8BIT_MODE (0x07)
+#define SSP_SCR_MAX(0xFF)
+#define SSP_SCR_SHFT 8
+
+/* SSP Control Register 0 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 << 1)
+
+#define SSP_CPSR_MAX (0xFE)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE(0x1 << 0) /* Transmit FIFO empty */
+#define SSP_SR_MASK_TNF(0x1 << 1) /* Transmit FIFO not full */
+#define SSP_SR_MASK_RNE(0x1 << 2) /* Receive FIFO not empty */
+#define SSP_SR_MASK_RFF(0x1 << 3) /* Receive FIFO full */
+#define SSP_SR_MASK_BSY(0x1 << 4) /* Busy Flag */
+
+/* Comment by Jagan: --- TAG -*/
+/* Comment by Jagan:
+ * Bit mask macros - please place after headers.
+ * We follow a simple format to write spi driver - please check
+ * http://patchwork.ozlabs.org/patch/265683/
+ *
+ * And try to verify your code w.r.t above format - let me know any comments.
+ */
+struct pl022_spi_slave {
+ struct spi_slave slave;
+ void *regs;
+/* Comment by Jagan: Please use the structure pointer instead of void. */
+
+ unsigned int freq;
+};
+
+static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct pl022_spi_slave, slave);
+}
+
+/*
+ * Following three functions should be provided by the
+ * board support package.
+ */
+int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void __weak spi_cs_activate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void __weak spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void spi_init(void)
+{
+ /* do nothing */
+}
+
+/*
+ * ARM PL022 exists in different 'flavors'.
+ * This drivers currently support the standard variant (0x00041022), that has a
+ * 16bit wide and 8 locations deep TX/RX FIFO.
+ */
+static int pl022_is_supported(struct pl022_spi_slave *ps)
+{
+ struct pl022 *pl022 = (struct pl022 *)ps->regs;
+
+ /* PL022 version is 0x00041022 */
+ if ((readl(>ssp_pid0) == 0x22) &&
+ (readl(>ssp_pid1) == 0x10) &&
+ ((readl(>ssp_pid2) & 0xf) == 0x04) &&
+ (readl(>ssp_pid3) == 0x00))
+ return 1;
+
+ return 0;
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned
Re: [U-Boot] [PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller
Ciao Michael,
On 09/08/2016 04:21 PM, Michael Brandl wrote:
Dear U-Boot (SPI) Developers,
this patch seems to be my only chance to get spi working without/before Linux.
I wrote and used this code for u-boot for a asic
specified by one of our customers. The patch was generic
enough to be pushed in u-boot, but I didn't have
much time to test it on a different, more generic
platform. So the maintainer decided to drop it...
Would be nice if you could work on it and resurrect it...
:)
Let me know if you have progressed on this or abandoned it.
I'm a student from Augsburg (Germany) experimenting with the Hikey Board from
96boards.
The hi6220 processor from HiSilicon isn't fully documented, there is just one
document called Function Description:
http://mirror.lemaker.org/Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
Yes, I'm currently using HiKey platform for doing my day by day
job here in office. Nevertheless, I don't think I have enough
time to take a look into testing this commit.
U-Boot already supports the Hikey Board to be loaded from ARM Trusted Firmware
(ATF) but only UART and SDMMC is supported by now.
I cloned the u-boot-spi.git and tried to integrate this patch but I'm not
experienced enough to adjust the specific config for the Hikey Board.
Maybe I can try to recover the work that was done to integrate
this commit into the customer platform I was talking about.
I'll take a look into it right now...
Taking a look at armv7 devices with spi support I started like this:
+++ b/arch/arm/include/asm/arch-hi6220/hi6220.h
+/*Hi6220V100_Multi-Mode_Application_Processor_Function_Description on p.5-45*/
+#define HI6220_SPI_BASE0xF7106000
+++ b/include/configs/hikey.h
+/* Synchronous Serial Port PL022 for SPI */
+#define CONFIG_PL022_SPI
+++ b/board/hisilicon/hikey/hikey.c
int board_init(void)
{
+#ifdef CONFIG_PL022_SPI
+ hikey_spi0_hw_init();
+#endif
return 0;
}
+static void hikey_spi0_hw_init(void)
+{
+ hi6220_pinmux_config(PERIPH_ID_SPI0)
+// at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
+ gpio_request(0, "PWR_HOLD_GPIO0_0");
+ gpio_direction_output(0, 1);
+
+ /* Enable clock */
+// at91_periph_clk_enable(ATMEL_ID_SPI0);
+/* from Kernel { HI6220_SPI_CLK, "spi_clk", "clk_150m",
CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 9, 0, }, */
+ hi6220_clk_enable(PERI_CLK0_SPI0, _sc->clk3_en);
+
+}
+#endif /* CONFIG_PL022_SPI */
+
+++ b/arch/arm/cpu/armv8/hisilicon/pinmux.c
+static void hi6220_spi_config(int peripheral)
+{
+ switch (peripheral) {
+ case PERIPH_ID_SPI0:
+// at91_set_a_periph(AT91_PIO_PORTC, 0, 0);/* SPI0_MISO */
+// at91_set_a_periph(AT91_PIO_PORTC, 1, 0);/* SPI0_MOSI */
+// at91_set_a_periph(AT91_PIO_PORTC, 2, 0);/* SPI0_SPCK */
+ break;
+
+ case PERIPH_ID_SPI1:
+ break;
+
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return;
+ }
+}
Maybe you can help me to get spi working on Hikey. My overall aim is to port
the pl022 driver then to ARM TF ... maybe also that could be interessing for
you.
With kind Regards,
Michael Brandl
Rgds,
Armando
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Re: [U-Boot] [PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller
Hello Jagan,
Sorry for late reply.
On 12/20/2013 8:03 PM, Jagan Teki wrote:
On Fri, Oct 4, 2013 at 12:20 PM, Jagan Teki jagannadh.t...@gmail.com wrote:
Hi Vipin,
I have few quick comments, please fix it.
Please use the u-boot-spi.git with master-probe branch for testing this driver.
Let me know for any issues/concerns.
On Wed, Jun 12, 2013 at 7:55 PM, Jagan Teki jagannadh.t...@gmail.com wrote:
Thanks for v6 sent.
Have you tested this?
on which board, include/configs/*.h file?
--
Thanks,
Jagan.
On Wed, Jun 12, 2013 at 6:17 PM, Armando Visconti
armando.visco...@st.com wrote:
This patch adds the support for the ARM PL022 SPI controller for the standard
variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO.
Signed-off-by: Armando Visconti armando.visco...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Acked-by: Stefan Roese s...@denx.de
---
v5-v6
1. Make use of spi_alloc_slave() macro.
2. Changed the identation on 'if statement' as requested
by Jagan.
drivers/spi/Makefile| 1 +
drivers/spi/pl022_spi.c | 308
2 files changed, 309 insertions(+)
create mode 100644 drivers/spi/pl022_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d08609e..b6443b1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
new file mode 100644
index 000..5b47413
--- /dev/null
+++ b/drivers/spi/pl022_spi.c
@@ -0,0 +1,308 @@
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visco...@st.com.
+ *
+ * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c
+ * by Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
Use latest SPDX-License-Identifier:
check for any existing one.
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+/* SSP registers mapping */
+struct pl022 {
Something like pl022_spi_regs
+ u32 ssp_cr0;/* 0x000 */
+ u32 ssp_cr1;/* 0x004 */
+ u32 ssp_dr; /* 0x008 */
+ u32 ssp_sr; /* 0x00c */
+ u32 ssp_cpsr; /* 0x010 */
+ u32 ssp_imsc; /* 0x014 */
+ u32 ssp_ris;/* 0x018 */
+ u32 ssp_mis;/* 0x01c */
+ u32 ssp_icr;/* 0x020 */
+ u32 ssp_dmacr; /* 0x024 */
+ u8 reserved_1[0x080 - 0x028];
+ u32 ssp_itcr; /* 0x080 */
+ u32 ssp_itip; /* 0x084 */
+ u32 ssp_itop; /* 0x088 */
+ u32 ssp_tdr;/* 0x08c */
+ u8 reserved_2[0xFE0 - 0x090];
+ u32 ssp_pid0; /* 0xfe0 */
+ u32 ssp_pid1; /* 0xfe4 */
+ u32 ssp_pid2; /* 0xfe8 */
+ u32 ssp_pid3; /* 0xfec */
+ u32 ssp_cid0; /* 0xff0 */
+ u32 ssp_cid1; /* 0xff4 */
+ u32 ssp_cid2; /* 0xff8 */
+ u32 ssp_cid3; /* 0xffc */
+};
+
-- TAG+
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO(0x1 6)
+#define SSP_CR0_SPH(0x1 7)
+#define SSP_CR0_8BIT_MODE (0x07)
+#define SSP_SCR_MAX(0xFF)
+#define SSP_SCR_SHFT 8
+
+/* SSP Control Register 0 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 1)
+
+#define SSP_CPSR_MAX (0xFE)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE(0x1 0) /* Transmit FIFO empty */
+#define SSP_SR_MASK_TNF(0x1 1) /* Transmit FIFO not full */
+#define SSP_SR_MASK_RNE(0x1 2) /* Receive FIFO not empty */
+#define SSP_SR_MASK_RFF(0x1 3) /* Receive FIFO full */
+#define SSP_SR_MASK_BSY(0x1 4) /* Busy Flag */
+
--- TAG -
Bit mask macros - please place after headers.
We follow a simple format to write spi driver - please
[U-Boot] [u-boot V5] spi: arm-pl022: Add support for ARM PL022 spi controller
This patch adds the support for the ARM PL022 SPI controller for the standard
variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO.
Signed-off-by: Armando Visconti armando.visco...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Acked-by: Stefan Roese s...@denx.de
---
V4-V5:
Changed the commit message to a more standard format.
Armando
drivers/spi/Makefile| 1 +
drivers/spi/pl022_spi.c | 310
2 files changed, 311 insertions(+)
create mode 100644 drivers/spi/pl022_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d08609e..b6443b1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
new file mode 100644
index 000..8a8b9ab
--- /dev/null
+++ b/drivers/spi/pl022_spi.c
@@ -0,0 +1,310 @@
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visco...@st.com.
+ *
+ * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c
+ * by Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+/* SSP registers mapping */
+struct pl022 {
+ u32 ssp_cr0;/* 0x000 */
+ u32 ssp_cr1;/* 0x004 */
+ u32 ssp_dr; /* 0x008 */
+ u32 ssp_sr; /* 0x00c */
+ u32 ssp_cpsr; /* 0x010 */
+ u32 ssp_imsc; /* 0x014 */
+ u32 ssp_ris;/* 0x018 */
+ u32 ssp_mis;/* 0x01c */
+ u32 ssp_icr;/* 0x020 */
+ u32 ssp_dmacr; /* 0x024 */
+ u8 reserved_1[0x080 - 0x028];
+ u32 ssp_itcr; /* 0x080 */
+ u32 ssp_itip; /* 0x084 */
+ u32 ssp_itop; /* 0x088 */
+ u32 ssp_tdr;/* 0x08c */
+ u8 reserved_2[0xFE0 - 0x090];
+ u32 ssp_pid0; /* 0xfe0 */
+ u32 ssp_pid1; /* 0xfe4 */
+ u32 ssp_pid2; /* 0xfe8 */
+ u32 ssp_pid3; /* 0xfec */
+ u32 ssp_cid0; /* 0xff0 */
+ u32 ssp_cid1; /* 0xff4 */
+ u32 ssp_cid2; /* 0xff8 */
+ u32 ssp_cid3; /* 0xffc */
+};
+
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO(0x1 6)
+#define SSP_CR0_SPH(0x1 7)
+#define SSP_CR0_8BIT_MODE (0x07)
+#define SSP_SCR_MAX(0xFF)
+#define SSP_SCR_SHFT 8
+
+/* SSP Control Register 0 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 1)
+
+#define SSP_CPSR_MAX (0xFE)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE(0x1 0) /* Transmit FIFO empty */
+#define SSP_SR_MASK_TNF(0x1 1) /* Transmit FIFO not full */
+#define SSP_SR_MASK_RNE(0x1 2) /* Receive FIFO not empty */
+#define SSP_SR_MASK_RFF(0x1 3) /* Receive FIFO full */
+#define SSP_SR_MASK_BSY(0x1 4) /* Busy Flag */
+
+struct pl022_spi_slave {
+ struct spi_slave slave;
+ void *regs;
+ unsigned int freq;
+};
+
+static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct pl022_spi_slave, slave);
+}
+
+/*
+ * Following three functions should be provided by the
+ * board support package.
+ */
+int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void __weak spi_cs_activate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void __weak spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void spi_init(void)
+{
+ /* do nothing */
+}
+
+/*
+ * ARM PL022 exists in different 'flavors'.
+ * This drivers currently support the standard variant (0x00041022), that has a
+ * 16bit wide and 8 locations deep TX/RX FIFO.
+ */
+static int
Re: [U-Boot] [u-boot V5] spi: arm-pl022: Add support for ARM PL022 spi controller
On 06/12/2013 10:56 AM, Jagan Teki wrote: Hi, Your patch looks good to me, but the same time I have sent some comments on v4 patch http://patchwork.ozlabs.org/patch/249603/ I think you might respond to above thread before sending v5, may be your missing my earlier comments? Yes, I missed them. Sorry... I'm doing too many things at the same time... :( I will analyse them right now. fyi: One one more thing the patch subject prefix should be PATCH like --subject-prefix=PATCH v5 ok, I will. Next will be v6 at thi point.. Please respond to above thread for sending next level patch. sure Arm ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [u-boot V4] spi/arm-pl022: Add support for ARM PL022 spi controller
On 06/10/2013 06:01 PM, Jagan Teki wrote:
Hi,
Please use the commit header as below: just to sync with remaining
drivers in tree.
spi: arm-pl022: Add support for ARM PL022 spi controller
OK,
I already did it for v5.
I'll keep it for v6 as well...
On Fri, Jun 7, 2013 at 1:14 PM, Armando Visconti
armando.visco...@st.com wrote:
This patch adds the support for the ARM PL022 SPI controller for the standard
variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO.
Signed-off-by: Armando Visconti armando.visco...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Acked-by: Stefan Roese s...@denx.de
---
v3-v4
Just removed all warnings when running checkpatch.
Didn't find Jagan's feedback... So, pls, let me know if we
need to change anything else...
Armando
drivers/spi/Makefile| 1 +
drivers/spi/pl022_spi.c | 310
2 files changed, 311 insertions(+)
create mode 100644 drivers/spi/pl022_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d08609e..b6443b1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
new file mode 100644
index 000..8a8b9ab
--- /dev/null
+++ b/drivers/spi/pl022_spi.c
@@ -0,0 +1,310 @@
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visco...@st.com.
+ *
+ * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c
+ * by Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+/* SSP registers mapping */
+struct pl022 {
+ u32 ssp_cr0;/* 0x000 */
+ u32 ssp_cr1;/* 0x004 */
+ u32 ssp_dr; /* 0x008 */
+ u32 ssp_sr; /* 0x00c */
+ u32 ssp_cpsr; /* 0x010 */
+ u32 ssp_imsc; /* 0x014 */
+ u32 ssp_ris;/* 0x018 */
+ u32 ssp_mis;/* 0x01c */
+ u32 ssp_icr;/* 0x020 */
+ u32 ssp_dmacr; /* 0x024 */
+ u8 reserved_1[0x080 - 0x028];
+ u32 ssp_itcr; /* 0x080 */
+ u32 ssp_itip; /* 0x084 */
+ u32 ssp_itop; /* 0x088 */
+ u32 ssp_tdr;/* 0x08c */
+ u8 reserved_2[0xFE0 - 0x090];
+ u32 ssp_pid0; /* 0xfe0 */
+ u32 ssp_pid1; /* 0xfe4 */
+ u32 ssp_pid2; /* 0xfe8 */
+ u32 ssp_pid3; /* 0xfec */
+ u32 ssp_cid0; /* 0xff0 */
+ u32 ssp_cid1; /* 0xff4 */
+ u32 ssp_cid2; /* 0xff8 */
+ u32 ssp_cid3; /* 0xffc */
+};
+
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO(0x1 6)
+#define SSP_CR0_SPH(0x1 7)
+#define SSP_CR0_8BIT_MODE (0x07)
+#define SSP_SCR_MAX(0xFF)
+#define SSP_SCR_SHFT 8
+
+/* SSP Control Register 0 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 1)
+
+#define SSP_CPSR_MAX (0xFE)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE(0x1 0) /* Transmit FIFO empty */
+#define SSP_SR_MASK_TNF(0x1 1) /* Transmit FIFO not full */
+#define SSP_SR_MASK_RNE(0x1 2) /* Receive FIFO not empty */
+#define SSP_SR_MASK_RFF(0x1 3) /* Receive FIFO full */
+#define SSP_SR_MASK_BSY(0x1 4) /* Busy Flag */
+
+struct pl022_spi_slave {
+ struct spi_slave slave;
+ void *regs;
+ unsigned int freq;
+};
+
+static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct pl022_spi_slave, slave);
+}
+
-- TAG+
+/*
+ * Following three functions should be provided by the
+ * board support package.
+ */
+int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs
Re: [U-Boot] [u-boot V4] spi/arm-pl022: Add support for ARM PL022 spi controller
Hello Jagan,
+
+/*
+ * ARM PL022 exists in different 'flavors'.
+ * This drivers currently support the standard variant (0x00041022),
that has a
+ * 16bit wide and 8 locations deep TX/RX FIFO.
+ */
+static int pl022_is_supported(struct pl022_spi_slave *ps)
+{
+ struct pl022 *pl022 = (struct pl022 *)ps-regs;
+
+ /* PL022 version is 0x00041022 */
+ if ((readl(pl022-ssp_pid0) == 0x22)
+ (readl(pl022-ssp_pid1) == 0x10)
+ ((readl(pl022-ssp_pid2) 0xf) == 0x04)
+ (readl(pl022-ssp_pid3) == 0x00))
Tab space is required, for this if statement i guess, please check.
If I do then checkpatch reports a warning, saying that I need to keep
all lines of a 'if' statement aligned properly...
So, I guess that this way is more proper.
Agree, but it should be easy to interpret where should the if block
end and where should the code block starts.
I always use tab space like
+static int pl022_is_supported(struct pl022_spi_slave *ps)
+{
+ struct pl022 *pl022 = (struct pl022 *)ps-regs;
+
+ /* PL022 version is 0x00041022 */
+ if ((readl(pl022-ssp_pid0) == 0x22)
+ (readl(pl022-ssp_pid1) == 0x10)
+ ((readl(pl022-ssp_pid2) 0xf) == 0x04)
+ (readl(pl022-ssp_pid3) == 0x00))
+ return 1;
+
+ return 0;
+}
If you see return 1 is code block, so prior to this if ends.
OK, I'll do it in this way even if it may generate warnings.
Give me few mins and I'll send a v6 patch!
Thx,
Arm
--
-- Every step appears to be the unavoidable consequence of the
-- preceding one. (A. Einstein)
--
Armando Visconti Mobile: (+39) 346 8879146
Senior SW EngineerFax:(+39) 02 93519290
CPG Work: (+39) 02 93519683
Computer System Division e-mail: armando.visco...@st.com
ST Microelectronics TINA: 051 4683
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [u-boot V4] spi/arm-pl022: Add support for ARM PL022 spi controller
Please use the commit header as spi: pl022_spi: as you haven't use the same on v5 i guess, please check. OK, Jagan, I'll do it! Armando ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller
This patch adds the support for the ARM PL022 SPI controller for the standard
variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO.
Signed-off-by: Armando Visconti armando.visco...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Acked-by: Stefan Roese s...@denx.de
---
v5-v6
1. Make use of spi_alloc_slave() macro.
2. Changed the identation on 'if statement' as requested
by Jagan.
drivers/spi/Makefile| 1 +
drivers/spi/pl022_spi.c | 308
2 files changed, 309 insertions(+)
create mode 100644 drivers/spi/pl022_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d08609e..b6443b1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
new file mode 100644
index 000..5b47413
--- /dev/null
+++ b/drivers/spi/pl022_spi.c
@@ -0,0 +1,308 @@
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visco...@st.com.
+ *
+ * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c
+ * by Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+/* SSP registers mapping */
+struct pl022 {
+ u32 ssp_cr0;/* 0x000 */
+ u32 ssp_cr1;/* 0x004 */
+ u32 ssp_dr; /* 0x008 */
+ u32 ssp_sr; /* 0x00c */
+ u32 ssp_cpsr; /* 0x010 */
+ u32 ssp_imsc; /* 0x014 */
+ u32 ssp_ris;/* 0x018 */
+ u32 ssp_mis;/* 0x01c */
+ u32 ssp_icr;/* 0x020 */
+ u32 ssp_dmacr; /* 0x024 */
+ u8 reserved_1[0x080 - 0x028];
+ u32 ssp_itcr; /* 0x080 */
+ u32 ssp_itip; /* 0x084 */
+ u32 ssp_itop; /* 0x088 */
+ u32 ssp_tdr;/* 0x08c */
+ u8 reserved_2[0xFE0 - 0x090];
+ u32 ssp_pid0; /* 0xfe0 */
+ u32 ssp_pid1; /* 0xfe4 */
+ u32 ssp_pid2; /* 0xfe8 */
+ u32 ssp_pid3; /* 0xfec */
+ u32 ssp_cid0; /* 0xff0 */
+ u32 ssp_cid1; /* 0xff4 */
+ u32 ssp_cid2; /* 0xff8 */
+ u32 ssp_cid3; /* 0xffc */
+};
+
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO(0x1 6)
+#define SSP_CR0_SPH(0x1 7)
+#define SSP_CR0_8BIT_MODE (0x07)
+#define SSP_SCR_MAX(0xFF)
+#define SSP_SCR_SHFT 8
+
+/* SSP Control Register 0 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 1)
+
+#define SSP_CPSR_MAX (0xFE)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE(0x1 0) /* Transmit FIFO empty */
+#define SSP_SR_MASK_TNF(0x1 1) /* Transmit FIFO not full */
+#define SSP_SR_MASK_RNE(0x1 2) /* Receive FIFO not empty */
+#define SSP_SR_MASK_RFF(0x1 3) /* Receive FIFO full */
+#define SSP_SR_MASK_BSY(0x1 4) /* Busy Flag */
+
+struct pl022_spi_slave {
+ struct spi_slave slave;
+ void *regs;
+ unsigned int freq;
+};
+
+static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct pl022_spi_slave, slave);
+}
+
+/*
+ * Following three functions should be provided by the
+ * board support package.
+ */
+int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void __weak spi_cs_activate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void __weak spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void spi_init(void)
+{
+ /* do nothing */
+}
+
+/*
+ * ARM PL022 exists in different 'flavors'.
+ * This drivers currently support the standard variant (0x00041022), that has a
+ * 16bit wide and 8
Re: [U-Boot] [PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller
On 06/12/2013 04:25 PM, Jagan Teki wrote: Thanks for v6 sent. Have you tested this? on which board, include/configs/*.h file? No Jagan. I have not tested v6, as I currently don't have a spare board. Nevertheless, Vipin tested it up to v3. And he tested it on spear1340 evaluation board. After v3, no big changes have been performed. Just style changes and make use of spi_alloc_slave()... But if you prefer to be on safer side I think we need to re-do some checks on a spare 1340 board... Pls let me know, Arm -- -- Every step appears to be the unavoidable consequence of the -- preceding one. (A. Einstein) -- Armando Visconti Mobile: (+39) 346 8879146 Senior SW EngineerFax:(+39) 02 93519290 CPG Work: (+39) 02 93519683 Computer System Division e-mail: armando.visco...@st.com ST Microelectronics TINA: 051 4683 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller
But if you prefer to be on safer side I think we need to re-do some checks on a spare 1340 board... OK, maybe it is better to re-check again. I need to find some time and a spare board... I'll let you know, Arm ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller
On 06/12/2013 05:29 PM, Jagan Teki wrote: On Wed, Jun 12, 2013 at 8:49 PM, Armando Visconti armando.visco...@st.com wrote: But if you prefer to be on safer side I think we need to re-do some checks on a spare 1340 board... OK, maybe it is better to re-check again. I need to find some time and a spare board... I'll let you know, Arm Do we have an config file available in master, i need to build at-least. Mmmh... currently in mainline there is only spear3xx config file, but there is no PL022 support there. In fact, to compile locally here I had to change it in this way, even if they cannot be used for testing (only compiling): diff --git a/include/configs/spear3xx_evb.h b/include/configs/spear3xx_evb.h index 3cd56dc..03a046e 100644 --- a/include/configs/spear3xx_evb.h +++ b/include/configs/spear3xx_evb.h @@ -54,6 +54,11 @@ /* Ethernet driver configuration */ #define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_PL022_SPI1 +#define CONFIG_SYS_SPI_BASE 0xE010 +#define CONFIG_SYS_SPI_CLK 8300 +#define CONFIG_CMD_SPI 1 + #if defined(CONFIG_SPEAR310) #define CONFIG_MACB #define CONFIG_MACB0_PHY 0x01 I know that Vipin was going to add support of spear1340 in mainline. His patches are currently already submitted and partially acked but I'm not sure what is the status now... Vipin, can you update us? Rgds, Arm ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [u-boot V4] spi/arm-pl022: Add support for ARM PL022 spi controller
This patch adds the support for the ARM PL022 SPI controller for the standard
variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO.
Signed-off-by: Armando Visconti armando.visco...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Acked-by: Stefan Roese s...@denx.de
---
v3-v4
Just removed all warnings when running checkpatch.
Didn't find Jagan's feedback... So, pls, let me know if we
need to change anything else...
Armando
drivers/spi/Makefile| 1 +
drivers/spi/pl022_spi.c | 310
2 files changed, 311 insertions(+)
create mode 100644 drivers/spi/pl022_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d08609e..b6443b1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
new file mode 100644
index 000..8a8b9ab
--- /dev/null
+++ b/drivers/spi/pl022_spi.c
@@ -0,0 +1,310 @@
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visco...@st.com.
+ *
+ * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c
+ * by Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+/* SSP registers mapping */
+struct pl022 {
+ u32 ssp_cr0;/* 0x000 */
+ u32 ssp_cr1;/* 0x004 */
+ u32 ssp_dr; /* 0x008 */
+ u32 ssp_sr; /* 0x00c */
+ u32 ssp_cpsr; /* 0x010 */
+ u32 ssp_imsc; /* 0x014 */
+ u32 ssp_ris;/* 0x018 */
+ u32 ssp_mis;/* 0x01c */
+ u32 ssp_icr;/* 0x020 */
+ u32 ssp_dmacr; /* 0x024 */
+ u8 reserved_1[0x080 - 0x028];
+ u32 ssp_itcr; /* 0x080 */
+ u32 ssp_itip; /* 0x084 */
+ u32 ssp_itop; /* 0x088 */
+ u32 ssp_tdr;/* 0x08c */
+ u8 reserved_2[0xFE0 - 0x090];
+ u32 ssp_pid0; /* 0xfe0 */
+ u32 ssp_pid1; /* 0xfe4 */
+ u32 ssp_pid2; /* 0xfe8 */
+ u32 ssp_pid3; /* 0xfec */
+ u32 ssp_cid0; /* 0xff0 */
+ u32 ssp_cid1; /* 0xff4 */
+ u32 ssp_cid2; /* 0xff8 */
+ u32 ssp_cid3; /* 0xffc */
+};
+
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO(0x1 6)
+#define SSP_CR0_SPH(0x1 7)
+#define SSP_CR0_8BIT_MODE (0x07)
+#define SSP_SCR_MAX(0xFF)
+#define SSP_SCR_SHFT 8
+
+/* SSP Control Register 0 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 1)
+
+#define SSP_CPSR_MAX (0xFE)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE(0x1 0) /* Transmit FIFO empty */
+#define SSP_SR_MASK_TNF(0x1 1) /* Transmit FIFO not full */
+#define SSP_SR_MASK_RNE(0x1 2) /* Receive FIFO not empty */
+#define SSP_SR_MASK_RFF(0x1 3) /* Receive FIFO full */
+#define SSP_SR_MASK_BSY(0x1 4) /* Busy Flag */
+
+struct pl022_spi_slave {
+ struct spi_slave slave;
+ void *regs;
+ unsigned int freq;
+};
+
+static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct pl022_spi_slave, slave);
+}
+
+/*
+ * Following three functions should be provided by the
+ * board support package.
+ */
+int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void __weak spi_cs_activate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void __weak spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void spi_init(void)
+{
+ /* do nothing */
+}
+
+/*
+ * ARM PL022 exists in different 'flavors'.
+ * This drivers currently support the standard variant (0x00041022
Re: [U-Boot] [u-boot] spi/arm-pl022: Add support for ARM PL022 spi controller
On 06/03/2013 12:10 PM, Jagan Teki wrote: I completely lost the original thread... I will re-start from V3... Pls discard this noisy thread, Please check the below thread for earlier v3 http://patchwork.ozlabs.org/patch/205814/ Thx Jagan, I have a v4 ready, where I just corrected the checkpatch errors. Nevertheless, I failed to find your comments over the v3. Can you possibly send to me the link to the discussion thread? Thx, Arm ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [u-boot] spi/arm-pl022: Add support for ARM PL022 spi controller
This patch adds the support for the ARM PL022 SPI controller for the standard
variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO.
Signed-off-by: Armando Visconti armando.visco...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
---
This driver has been tested on the ST SPEAr1340 evaluation board.
Patch has just been rebased on http://git.denx.de/u-boot-spi.git
master branch and can be cleanly applied there.
Armando
drivers/spi/Makefile| 1 +
drivers/spi/pl022_spi.c | 308
2 files changed, 309 insertions(+)
create mode 100644 drivers/spi/pl022_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d08609e..b6443b1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
new file mode 100644
index 000..3ea769a
--- /dev/null
+++ b/drivers/spi/pl022_spi.c
@@ -0,0 +1,308 @@
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visco...@st.com.
+ *
+ * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c
+ * by Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+/* SSP registers mapping */
+#define SSP_CR00x000
+#define SSP_CR10x004
+#define SSP_DR 0x008
+#define SSP_SR 0x00C
+#define SSP_CPSR 0x010
+#define SSP_IMSC 0x014
+#define SSP_RIS0x018
+#define SSP_MIS0x01C
+#define SSP_ICR0x020
+#define SSP_DMACR 0x024
+#define SSP_ITCR 0x080
+#define SSP_ITIP 0x084
+#define SSP_ITOP 0x088
+#define SSP_TDR0x08C
+
+#define SSP_PID0 0xFE0
+#define SSP_PID1 0xFE4
+#define SSP_PID2 0xFE8
+#define SSP_PID3 0xFEC
+
+#define SSP_CID0 0xFF0
+#define SSP_CID1 0xFF4
+#define SSP_CID2 0xFF8
+#define SSP_CID3 0xFFC
+
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO(0x1 6)
+#define SSP_CR0_SPH(0x1 7)
+#define SSP_CR0_8BIT_MODE (0x07)
+#define SSP_SCR_MAX(0xFF)
+#define SSP_SCR_SHFT 8
+
+/* SSP Control Register 0 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 1)
+
+#define SSP_CPSR_MAX (0xFE)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE(0x1 0) /* Transmit FIFO empty */
+#define SSP_SR_MASK_TNF(0x1 1) /* Transmit FIFO not full */
+#define SSP_SR_MASK_RNE(0x1 2) /* Receive FIFO not empty */
+#define SSP_SR_MASK_RFF(0x1 3) /* Receive FIFO full */
+#define SSP_SR_MASK_BSY(0x1 4) /* Busy Flag */
+
+struct pl022_spi_slave {
+ struct spi_slave slave;
+ void *regs;
+ unsigned int freq;
+};
+
+static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct pl022_spi_slave, slave);
+}
+
+/*
+ * Following three functions should be provided by the
+ * board support package.
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+ __attribute__((weak, alias(__spi_cs_is_valid)));
+void spi_cs_activate(struct spi_slave *slave)
+ __attribute__((weak, alias(__spi_cs_activate)));
+void spi_cs_deactivate(struct spi_slave *slave)
+ __attribute__((weak, alias(__spi_cs_deactivate)));
+
+int __spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void __spi_cs_activate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void __spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void spi_init()
+{
+ /* do nothing */
+}
+
+/*
+ * ARM PL022 exists in different 'flavors'.
+ * This drivers currently support the standard variant (0x00041022), that has a
+ * 16bit wide and 8 locations deep TX/RX
Re: [U-Boot] [u-boot] spi/arm-pl022: Add support for ARM PL022 spi controller
On 06/03/2013 11:48 AM, Jagan Teki wrote: Hi, Is this the v4? I sent some comment for v3 on same driver. Sorry, I completely lost the original thread... I will re-start from V3... Pls discard this noisy thread, Armando ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH resend] armv7/ltimer: Add support for local timer on armv7 cpus
Ciao Vipin,
Yes, I agree about the need to have the generic
local_timer support in u-boot.
Internally I was not able to give comment about this
part. So, see my comments now.
On 12/06/2012 10:22 AM, Vipin KUMAR wrote:
Certain ARMV7 cpus eg. CortexA9 contains a local and a global timer within the
CPU core itself. This patch adds generic support for local timer.
Signed-off-by: Vipin Kumarvipin.ku...@st.com
---
arch/arm/cpu/armv7/Makefile | 11 ++-
arch/arm/cpu/armv7/ca9_ltimer.c | 152 ++
arch/arm/include/asm/ca9_ltimer.h | 40 ++
3 files changed, 199 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/cpu/armv7/ca9_ltimer.c
create mode 100644 arch/arm/include/asm/ca9_ltimer.h
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 4fdbee4..3ef01f6 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -27,15 +27,18 @@ LIB = $(obj)lib$(CPU).o
START := start.o
-COBJS += cache_v7.o
+COBJS-y+= cache_v7.o
-COBJS += cpu.o
-COBJS += syslib.o
+COBJS-y+= cpu.o
+COBJS-y+= syslib.o
+COBJS-$(CONFIG_ARMV7_CA9LTIMER) += ca9_ltimer.o
Is it really necessary to have the 'ca9' prefix here?
I think it would be better to stay more generic here,
like: 'CONFIG_ARMV7_LTIMER' and 'ltimer.o'.
In linux as well is kept generic, even across architectures...
If accepted, apply globally...
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
-SOBJS += lowlevel_init.o
+SOBJS-y+= lowlevel_init.o
endif
+COBJS := $(sort $(COBJS-y))
+SOBJS := $(sort $(SOBJS-y))
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
START := $(addprefix $(obj),$(START))
diff --git a/arch/arm/cpu/armv7/ca9_ltimer.c b/arch/arm/cpu/armv7/ca9_ltimer.c
new file mode 100644
index 000..cbf1552
--- /dev/null
+++ b/arch/arm/cpu/armv7/ca9_ltimer.c
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.ku...@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#includecommon.h
+#includeasm/io.h
+#includeasm/ca9_ltimer.h
+#includeasm/arch/hardware.h
+
+#define READ_TIMER() readl(ca9_timer_p-count)
+
+static struct ca9_timer_regs *const ca9_timer_p =
+ (struct ca9_timer_regs *)CONFIG_ARMV7_LTIMER_BASE;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd-tbl
+#define lastdecgd-lastinc
+#define tickshzgd-timer_rate_hz
+#define ticksper10usec gd-tbu
+
+int timer_init(void)
+{
+ u32 prescaler, timertickshz;
+ /*
+* Genrally, CortexA9 MPUs are operating from 500MHz to 1500MHz which
+* means that CA9 local timer clock would be in the range of 250 MHz to
+* 750MHz.
+* Try to find a prescaler which can perfectly divide the local timer
+* clock. Take prescaler as 200 if nothing is found
+*/
+ for (prescaler = 255; prescaler 1; prescaler--) {
+ if (CONFIG_ARMV7_LTMR_CLK ==
+ (CONFIG_ARMV7_LTMR_CLK / prescaler) * prescaler)
+ break;
+ }
+
+ if (prescaler == 1)
+ prescaler = 200;
Where the default '200' prescaler selection come from?
Shouldn't it be a configurable option (i.e. CONFIG_)?
Or passed as an argument to this function?
+ timertickshz = CONFIG_ARMV7_LTMR_CLK / prescaler;
+ ticksper10usec = timertickshz / (100 * 1000);
+ tickshz = timertickshz / CONFIG_SYS_HZ;
+
+ /* disable timers */
+ writel(((prescaler - 1) 8) | AUTO_RELOAD,ca9_timer_p-control);
+
Why can't single-shot be selectable?
Shouldn't it be passed as an argument to timer_init()?
+ /* load value for free running */
+ writel(FREE_RUNNING,ca9_timer_p-load);
+
+ /* auto reload, start timer */
+ setbits_le32(ca9_timer_p-control, TIMER_ENABLE);
+
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return (get_timer_masked() / tickshz) - base;
+}
+
+void set_timer(ulong t)
+{
+
Re: [U-Boot] [PATCH v3] spi/arm-pl022: Add support for ARM PL022 spi controller
On 12/13/2012 12:41 PM, Vipin KUMAR wrote: From: Armando Viscontiarmando.visco...@st.com This patch adds the support for the ARM PL022 SPI controller for the standard variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO. Signed-off-by: Armando Viscontiarmando.visco...@st.com Signed-off-by: Vipin Kumarvipin.ku...@st.com --- Changes in v3 Added void to spi_init arguments Used readl/writel in place of u16 accessors Fix: Provided address of register in place of value to readl/writel IO accessors Tested with spear1340-evb I recall now that SPI variant is same also on the new SoC (I2C cell is different). So no need to test over it. SPEAr1340 is enough. Ciao, Arm ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH resend] spi/arm-pl022: Add support for ARM PL022 spi controller
+ +/* SSP registers mapping */ +#define SSP_CR00x000 +#define SSP_CR10x004 +#define SSP_DR 0x008 +#define SSP_SR 0x00C +#define SSP_CPSR 0x010 +#define SSP_IMSC 0x014 +#define SSP_RIS0x018 +#define SSP_MIS0x01C +#define SSP_ICR0x020 +#define SSP_DMACR 0x024 +#define SSP_ITCR 0x080 +#define SSP_ITIP 0x084 +#define SSP_ITOP 0x088 +#define SSP_TDR0x08C Please use C-structs instead to access the registers. May be this patch is a ripped version from linux. That's why Thanks. I will do this in v2 Yes, I took this part from the linux pl022 driver. Never understood which way (C-struct or defines) is preferable and why... Rgds, Arm ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] spi/arm-pl022: Add support for ARM PL022 spi controller
Ciao Vipin,
On 12/12/2012 01:04 PM, Vipin KUMAR wrote:
From: Armando Viscontiarmando.visco...@st.com
This patch adds the support for the ARM PL022 SPI controller for the standard
variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO.
Have you tested this patch on the new variant as well?
You should have a couple of boards there with the
new asic.
Signed-off-by: Armando Viscontiarmando.visco...@st.com
Signed-off-by: Vipin Kumarvipin.ku...@st.com
---
drivers/spi/Makefile| 1 +
drivers/spi/pl022_spi.c | 310
2 files changed, 311 insertions(+)
create mode 100644 drivers/spi/pl022_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 824d357..3a4e4b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -42,6 +42,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
new file mode 100644
index 000..ba018b8
--- /dev/null
+++ b/drivers/spi/pl022_spi.c
@@ -0,0 +1,310 @@
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visco...@st.com.
+ *
+ * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c
+ * by Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#includecommon.h
+#includemalloc.h
+#includespi.h
+#includeasm/io.h
+#includeasm/arch/hardware.h
+
+/* SSP registers mapping */
+struct pl022 {
+ u32 ssp_cr0;/* 0x000 */
+ u32 ssp_cr1;/* 0x004 */
+ u32 ssp_dr; /* 0x008 */
+ u32 ssp_sr; /* 0x00c */
+ u32 ssp_cpsr; /* 0x010 */
+ u32 ssp_imsc; /* 0x014 */
+ u32 ssp_ris;/* 0x018 */
+ u32 ssp_mis;/* 0x01c */
+ u32 ssp_icr;/* 0x020 */
+ u32 ssp_dmacr; /* 0x024 */
+ u8 reserved_1[0x080 - 0x028];
+ u32 ssp_itcr; /* 0x080 */
+ u32 ssp_itip; /* 0x084 */
+ u32 ssp_itop; /* 0x088 */
+ u32 ssp_tdr;/* 0x08c */
+ u8 reserved_2[0xFE0 - 0x090];
+ u32 ssp_pid0; /* 0xfe0 */
+ u32 ssp_pid1; /* 0xfe4 */
+ u32 ssp_pid2; /* 0xfe8 */
+ u32 ssp_pid3; /* 0xfec */
+ u32 ssp_cid0; /* 0xff0 */
+ u32 ssp_cid1; /* 0xff4 */
+ u32 ssp_cid2; /* 0xff8 */
+ u32 ssp_cid3; /* 0xffc */
+};
It's correct!
:)
+
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO(0x1 6)
+#define SSP_CR0_SPH(0x1 7)
+#define SSP_CR0_8BIT_MODE (0x07)
+#define SSP_SCR_MAX(0xFF)
+#define SSP_SCR_SHFT 8
+
+/* SSP Control Register 0 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 1)
+
+#define SSP_CPSR_MAX (0xFE)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE(0x1 0) /* Transmit FIFO empty */
+#define SSP_SR_MASK_TNF(0x1 1) /* Transmit FIFO not full */
+#define SSP_SR_MASK_RNE(0x1 2) /* Receive FIFO not empty */
+#define SSP_SR_MASK_RFF(0x1 3) /* Receive FIFO full */
+#define SSP_SR_MASK_BSY(0x1 4) /* Busy Flag */
+
+struct pl022_spi_slave {
+ struct spi_slave slave;
+ void *regs;
+ unsigned int freq;
+};
+
+static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct pl022_spi_slave, slave);
+}
+
+/*
+ * Following three functions should be provided by the
+ * board support package.
+ */
+int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void __weak spi_cs_activate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void __weak spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void spi_init()
Maybe you can put 'void' also in the arguments.
I think we forgot it in the original patch
[U-Boot] [PATCH V2 4/5] designware_i2c.h: Fixed the correct values for SCL low/high time
Signed-off-by: Armando Visconti armando.visco...@st.com
---
drivers/i2c/designware_i2c.h |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h
index e004152..0dc8884 100644
--- a/drivers/i2c/designware_i2c.h
+++ b/drivers/i2c/designware_i2c.h
@@ -65,9 +65,9 @@ struct i2c_regs {
/* High and low times in different speed modes (in ns) */
#define MIN_SS_SCL_HIGHTIME4000
-#define MIN_SS_SCL_LOWTIME 5000
-#define MIN_FS_SCL_HIGHTIME800
-#define MIN_FS_SCL_LOWTIME 1700
+#define MIN_SS_SCL_LOWTIME 4700
+#define MIN_FS_SCL_HIGHTIME600
+#define MIN_FS_SCL_LOWTIME 1300
#define MIN_HS_SCL_HIGHTIME60
#define MIN_HS_SCL_LOWTIME 160
--
1.7.4.4
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[U-Boot] [PATCH V2 5/5] designware_i2c.h: Define IC_CLK only if not already defined in config file
Signed-off-by: Armando Visconti armando.visco...@st.com
---
drivers/i2c/designware_i2c.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h
index 0dc8884..2faf4a8 100644
--- a/drivers/i2c/designware_i2c.h
+++ b/drivers/i2c/designware_i2c.h
@@ -60,7 +60,9 @@ struct i2c_regs {
u32 ic_tx_abrt_source;
};
+#if !defined(IC_CLK)
#define IC_CLK 166
+#endif
#define NANO_TO_MICRO 1000
/* High and low times in different speed modes (in ns) */
--
1.7.4.4
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[U-Boot] [PATCH V2 1/5] designware_i2c.c: Added the support for MULTI_BUS
This patch adds the capability to switch between 10
different I2C busses (from 0 to 9).
Signed-off-by: Armando Visconti armando.visco...@st.com
---
drivers/i2c/designware_i2c.c | 82 +-
1 files changed, 81 insertions(+), 1 deletions(-)
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index bf64a2a..4e4bfd4 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -26,7 +26,12 @@
#include asm/arch/hardware.h
#include designware_i2c.h
-static struct i2c_regs *const i2c_regs_p =
+#ifdef CONFIG_I2C_MULTI_BUS
+static unsigned int bus_initialized[CONFIG_SYS_I2C_BUS_MAX];
+static unsigned int current_bus = 0;
+#endif
+
+static struct i2c_regs *i2c_regs_p =
(struct i2c_regs *)CONFIG_SYS_I2C_BASE;
/*
@@ -150,6 +155,10 @@ void i2c_init(int speed, int slaveadd)
enbl = readl(i2c_regs_p-ic_enable);
enbl |= IC_ENABLE_0B;
writel(enbl, i2c_regs_p-ic_enable);
+
+#ifdef CONFIG_I2C_MULTI_BUS
+ bus_initialized[current_bus] = 1;
+#endif
}
/*
@@ -344,3 +353,74 @@ int i2c_probe(uchar chip)
return ret;
}
+
+#ifdef CONFIG_I2C_MULTI_BUS
+int i2c_set_bus_num(unsigned int bus)
+{
+ switch (bus) {
+ case 0:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE;
+ break;
+#ifdef CONFIG_SYS_I2C_BASE1
+ case 1:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE1;
+ break;
+#endif
+#ifdef CONFIG_SYS_I2C_BASE2
+ case 2:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE2;
+ break;
+#endif
+#ifdef CONFIG_SYS_I2C_BASE3
+ case 3:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE3;
+ break;
+#endif
+#ifdef CONFIG_SYS_I2C_BASE4
+ case 4:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE4;
+ break;
+#endif
+#ifdef CONFIG_SYS_I2C_BASE5
+ case 5:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE5;
+ break;
+#endif
+#ifdef CONFIG_SYS_I2C_BASE6
+ case 6:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE6;
+ break;
+#endif
+#ifdef CONFIG_SYS_I2C_BASE7
+ case 7:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE7;
+ break;
+#endif
+#ifdef CONFIG_SYS_I2C_BASE8
+ case 8:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE8;
+ break;
+#endif
+#ifdef CONFIG_SYS_I2C_BASE9
+ case 9:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE9;
+ break;
+#endif
+ default:
+ printf(Bad bus: %d\n, bus);
+ return -1;
+ }
+
+ current_bus = bus;
+
+ if (!bus_initialized[current_bus])
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ return 0;
+}
+
+int i2c_get_bus_num(void)
+{
+ return current_bus;
+}
+#endif
--
1.7.4.4
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[U-Boot] [PATCH V2 0/5] I2C designware patches
Changes from V1: Added two patches that I missed to send... Armando Visconti (5): designware_i2c.c: Added the support for MULTI_BUS designware_i2c: Added s/w generation of stop bit designware_i2c: Fixed the setting of the i2c bus speed designware_i2c.h: Fixed the correct values for SCL low/high time designware_i2c.h: Define IC_CLK only if not already defined in config file drivers/i2c/designware_i2c.c | 121 +++--- drivers/i2c/designware_i2c.h |9 ++- 2 files changed, 108 insertions(+), 22 deletions(-) -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 3/5] designware_i2c: Fixed the setting of the i2c bus speed
There are three couple (hcnt/lcnt) of registers for each
speed (SS/FS/HS). The driver needs to set the proper couple
of regs according to what speed we are setting.
Signed-off-by: Armando Visconti armando.visco...@st.com
---
drivers/i2c/designware_i2c.c | 28 +---
1 files changed, 13 insertions(+), 15 deletions(-)
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index eab3131..6653870 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -44,7 +44,6 @@ static void set_speed(int i2c_spd)
{
unsigned int cntl;
unsigned int hcnt, lcnt;
- unsigned int high, low;
unsigned int enbl;
/* to set speed cltr must be disabled */
@@ -52,39 +51,38 @@ static void set_speed(int i2c_spd)
enbl = ~IC_ENABLE_0B;
writel(enbl, i2c_regs_p-ic_enable);
-
cntl = (readl(i2c_regs_p-ic_con) (~IC_CON_SPD_MSK));
switch (i2c_spd) {
case IC_SPEED_MODE_MAX:
cntl |= IC_CON_SPD_HS;
- high = MIN_HS_SCL_HIGHTIME;
- low = MIN_HS_SCL_LOWTIME;
+ hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
+ writel(hcnt, i2c_regs_p-ic_hs_scl_hcnt);
+ lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
+ writel(lcnt, i2c_regs_p-ic_hs_scl_lcnt);
break;
case IC_SPEED_MODE_STANDARD:
cntl |= IC_CON_SPD_SS;
- high = MIN_SS_SCL_HIGHTIME;
- low = MIN_SS_SCL_LOWTIME;
+ hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
+ writel(hcnt, i2c_regs_p-ic_ss_scl_hcnt);
+ lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
+ writel(lcnt, i2c_regs_p-ic_ss_scl_lcnt);
break;
case IC_SPEED_MODE_FAST:
default:
cntl |= IC_CON_SPD_FS;
- high = MIN_FS_SCL_HIGHTIME;
- low = MIN_FS_SCL_LOWTIME;
+ hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
+ writel(hcnt, i2c_regs_p-ic_fs_scl_hcnt);
+ lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
+ writel(lcnt, i2c_regs_p-ic_fs_scl_lcnt);
break;
}
writel(cntl, i2c_regs_p-ic_con);
- hcnt = (IC_CLK * high) / NANO_TO_MICRO;
- writel(hcnt, i2c_regs_p-ic_fs_scl_hcnt);
-
- lcnt = (IC_CLK * low) / NANO_TO_MICRO;
- writel(lcnt, i2c_regs_p-ic_fs_scl_lcnt);
-
- /* re-enable i2c ctrl back now that speed is set */
+ /* Enable back i2c now speed set */
enbl |= IC_ENABLE_0B;
writel(enbl, i2c_regs_p-ic_enable);
}
--
1.7.4.4
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[U-Boot] [PATCH V2 2/5] designware_i2c: Added s/w generation of stop bit
In the newer versions of designware i2c IP there is the possibility
of configuring it with IC_EMPTYFIFO_HOLD_MASTER_EN=1, which basically
requires the s/w to generate the stop bit condition directly, as
the h/w will not automatically generate it when TX_FIFO is empty.
To avoid generation of an extra 0x0 byte sent as data, the
IC_STOP command must be sent along with the last IC_CMD.
This patch always writes bit[9] of ic_data_cmd even in the
older versions, assuming that it is a noop there.
Signed-off-by: Armando Visconti armando.visco...@st.com
---
drivers/i2c/designware_i2c.c | 11 ---
drivers/i2c/designware_i2c.h |1 +
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 4e4bfd4..eab3131 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -283,7 +283,10 @@ int i2c_read(uchar chip, uint addr, int alen, uchar
*buffer, int len)
start_time_rx = get_timer(0);
while (len) {
- writel(IC_CMD, i2c_regs_p-ic_cmd_data);
+ if (len == 1)
+ writel(IC_CMD | IC_STOP, i2c_regs_p-ic_cmd_data);
+ else
+ writel(IC_CMD, i2c_regs_p-ic_cmd_data);
if (readl(i2c_regs_p-ic_status) IC_STATUS_RFNE) {
*buffer++ = (uchar)readl(i2c_regs_p-ic_cmd_data);
@@ -322,9 +325,11 @@ int i2c_write(uchar chip, uint addr, int alen, uchar
*buffer, int len)
start_time_tx = get_timer(0);
while (len) {
if (readl(i2c_regs_p-ic_status) IC_STATUS_TFNF) {
- writel(*buffer, i2c_regs_p-ic_cmd_data);
+ if (--len == 0)
+ writel(*buffer | IC_STOP,
i2c_regs_p-ic_cmd_data);
+ else
+ writel(*buffer, i2c_regs_p-ic_cmd_data);
buffer++;
- len--;
start_time_tx = get_timer(0);
} else if (get_timer(start_time_tx) (nb * I2C_BYTE_TO)) {
diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h
index 03b520e..e004152 100644
--- a/drivers/i2c/designware_i2c.h
+++ b/drivers/i2c/designware_i2c.h
@@ -95,6 +95,7 @@ struct i2c_regs {
/* i2c data buffer and command register definitions */
#define IC_CMD 0x0100
+#define IC_STOP0x0200
/* i2c interrupt status register definitions */
#define IC_GEN_CALL0x0800
--
1.7.4.4
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[U-Boot] [PATCH 2/3] designware_i2c: Added s/w generation of stop bit
In the newer versions of designware i2c IP there is the possibility
of configuring it with IC_EMPTYFIFO_HOLD_MASTER_EN=1, which basically
requires the s/w to generate the stop bit condition directly, as
the h/w will not automatically generate it when TX_FIFO is empty.
To avoid generation of an extra 0x0 byte sent as data, the
IC_STOP command must be sent along with the last IC_CMD.
This patch always writes bit[9] of ic_data_cmd even in the
older versions, assuming that it is a noop there.
Signed-off-by: Armando Visconti armando.visco...@st.com
---
drivers/i2c/designware_i2c.c | 11 ---
drivers/i2c/designware_i2c.h |1 +
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 4e4bfd4..eab3131 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -283,7 +283,10 @@ int i2c_read(uchar chip, uint addr, int alen, uchar
*buffer, int len)
start_time_rx = get_timer(0);
while (len) {
- writel(IC_CMD, i2c_regs_p-ic_cmd_data);
+ if (len == 1)
+ writel(IC_CMD | IC_STOP, i2c_regs_p-ic_cmd_data);
+ else
+ writel(IC_CMD, i2c_regs_p-ic_cmd_data);
if (readl(i2c_regs_p-ic_status) IC_STATUS_RFNE) {
*buffer++ = (uchar)readl(i2c_regs_p-ic_cmd_data);
@@ -322,9 +325,11 @@ int i2c_write(uchar chip, uint addr, int alen, uchar
*buffer, int len)
start_time_tx = get_timer(0);
while (len) {
if (readl(i2c_regs_p-ic_status) IC_STATUS_TFNF) {
- writel(*buffer, i2c_regs_p-ic_cmd_data);
+ if (--len == 0)
+ writel(*buffer | IC_STOP,
i2c_regs_p-ic_cmd_data);
+ else
+ writel(*buffer, i2c_regs_p-ic_cmd_data);
buffer++;
- len--;
start_time_tx = get_timer(0);
} else if (get_timer(start_time_tx) (nb * I2C_BYTE_TO)) {
diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h
index 03b520e..e004152 100644
--- a/drivers/i2c/designware_i2c.h
+++ b/drivers/i2c/designware_i2c.h
@@ -95,6 +95,7 @@ struct i2c_regs {
/* i2c data buffer and command register definitions */
#define IC_CMD 0x0100
+#define IC_STOP0x0200
/* i2c interrupt status register definitions */
#define IC_GEN_CALL0x0800
--
1.7.4.4
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[U-Boot] [PATCH 3/3] designware_i2c: Fixed the setting of the i2c bus speed
There are three couple (hcnt/lcnt) of registers for each
speed (SS/FS/HS). The driver needs to set the proper couple
of regs according to what speed we are setting.
Signed-off-by: Armando Visconti armando.visco...@st.com
---
drivers/i2c/designware_i2c.c | 28 +---
1 files changed, 13 insertions(+), 15 deletions(-)
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index eab3131..6653870 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -44,7 +44,6 @@ static void set_speed(int i2c_spd)
{
unsigned int cntl;
unsigned int hcnt, lcnt;
- unsigned int high, low;
unsigned int enbl;
/* to set speed cltr must be disabled */
@@ -52,39 +51,38 @@ static void set_speed(int i2c_spd)
enbl = ~IC_ENABLE_0B;
writel(enbl, i2c_regs_p-ic_enable);
-
cntl = (readl(i2c_regs_p-ic_con) (~IC_CON_SPD_MSK));
switch (i2c_spd) {
case IC_SPEED_MODE_MAX:
cntl |= IC_CON_SPD_HS;
- high = MIN_HS_SCL_HIGHTIME;
- low = MIN_HS_SCL_LOWTIME;
+ hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
+ writel(hcnt, i2c_regs_p-ic_hs_scl_hcnt);
+ lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
+ writel(lcnt, i2c_regs_p-ic_hs_scl_lcnt);
break;
case IC_SPEED_MODE_STANDARD:
cntl |= IC_CON_SPD_SS;
- high = MIN_SS_SCL_HIGHTIME;
- low = MIN_SS_SCL_LOWTIME;
+ hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
+ writel(hcnt, i2c_regs_p-ic_ss_scl_hcnt);
+ lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
+ writel(lcnt, i2c_regs_p-ic_ss_scl_lcnt);
break;
case IC_SPEED_MODE_FAST:
default:
cntl |= IC_CON_SPD_FS;
- high = MIN_FS_SCL_HIGHTIME;
- low = MIN_FS_SCL_LOWTIME;
+ hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
+ writel(hcnt, i2c_regs_p-ic_fs_scl_hcnt);
+ lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
+ writel(lcnt, i2c_regs_p-ic_fs_scl_lcnt);
break;
}
writel(cntl, i2c_regs_p-ic_con);
- hcnt = (IC_CLK * high) / NANO_TO_MICRO;
- writel(hcnt, i2c_regs_p-ic_fs_scl_hcnt);
-
- lcnt = (IC_CLK * low) / NANO_TO_MICRO;
- writel(lcnt, i2c_regs_p-ic_fs_scl_lcnt);
-
- /* re-enable i2c ctrl back now that speed is set */
+ /* Enable back i2c now speed set */
enbl |= IC_ENABLE_0B;
writel(enbl, i2c_regs_p-ic_enable);
}
--
1.7.4.4
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[U-Boot] [PATCH 1/3] designware_i2c.c: Added the support for MULTI_BUS
This patch adds the capability to switch between 10
different I2C busses (from 0 to 9).
Signed-off-by: Armando Visconti armando.visco...@st.com
---
drivers/i2c/designware_i2c.c | 82 +-
1 files changed, 81 insertions(+), 1 deletions(-)
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index bf64a2a..4e4bfd4 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -26,7 +26,12 @@
#include asm/arch/hardware.h
#include designware_i2c.h
-static struct i2c_regs *const i2c_regs_p =
+#ifdef CONFIG_I2C_MULTI_BUS
+static unsigned int bus_initialized[CONFIG_SYS_I2C_BUS_MAX];
+static unsigned int current_bus = 0;
+#endif
+
+static struct i2c_regs *i2c_regs_p =
(struct i2c_regs *)CONFIG_SYS_I2C_BASE;
/*
@@ -150,6 +155,10 @@ void i2c_init(int speed, int slaveadd)
enbl = readl(i2c_regs_p-ic_enable);
enbl |= IC_ENABLE_0B;
writel(enbl, i2c_regs_p-ic_enable);
+
+#ifdef CONFIG_I2C_MULTI_BUS
+ bus_initialized[current_bus] = 1;
+#endif
}
/*
@@ -344,3 +353,74 @@ int i2c_probe(uchar chip)
return ret;
}
+
+#ifdef CONFIG_I2C_MULTI_BUS
+int i2c_set_bus_num(unsigned int bus)
+{
+ switch (bus) {
+ case 0:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE;
+ break;
+#ifdef CONFIG_SYS_I2C_BASE1
+ case 1:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE1;
+ break;
+#endif
+#ifdef CONFIG_SYS_I2C_BASE2
+ case 2:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE2;
+ break;
+#endif
+#ifdef CONFIG_SYS_I2C_BASE3
+ case 3:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE3;
+ break;
+#endif
+#ifdef CONFIG_SYS_I2C_BASE4
+ case 4:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE4;
+ break;
+#endif
+#ifdef CONFIG_SYS_I2C_BASE5
+ case 5:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE5;
+ break;
+#endif
+#ifdef CONFIG_SYS_I2C_BASE6
+ case 6:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE6;
+ break;
+#endif
+#ifdef CONFIG_SYS_I2C_BASE7
+ case 7:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE7;
+ break;
+#endif
+#ifdef CONFIG_SYS_I2C_BASE8
+ case 8:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE8;
+ break;
+#endif
+#ifdef CONFIG_SYS_I2C_BASE9
+ case 9:
+ i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE9;
+ break;
+#endif
+ default:
+ printf(Bad bus: %d\n, bus);
+ return -1;
+ }
+
+ current_bus = bus;
+
+ if (!bus_initialized[current_bus])
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ return 0;
+}
+
+int i2c_get_bus_num(void)
+{
+ return current_bus;
+}
+#endif
--
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[U-Boot] [PATCH 0/3] I2C designware patches
Hello Vipin, I have prepared this patch after the work I have done for the new asic which embeds the I2C designware IP configured with the stop bit controlled by s/w. I quickly tested it on both this asic AND the SPEAr1340, but if you can quickly check yourself would be good. I think that this patch may be included in the work you are preparing on your own repo, but I rebased this work on the Heiko's u-boot-i2c.git repo. Thx, Arm Armando Visconti (3): designware_i2c.c: Added the support for MULTI_BUS designware_i2c: Added s/w generation of stop bit designware_i2c: Fixed the setting of the i2c bus speed drivers/i2c/designware_i2c.c | 121 +++--- drivers/i2c/designware_i2c.h |1 + 2 files changed, 103 insertions(+), 19 deletions(-) -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 00/46] Enhance spear support
On 11/21/2012 10:24 AM, Wolfgang Denk wrote: Dear Vipin, In message50a0d0eb.4080...@st.com you wrote: The ssh key is as below THnaks a lot. The repository should be ready for your use now. Sorry it took so long. Please feel free to contact me directly if there should be any problems. Wolfgang, Vipin, Not sure what are next steps for this patchset. Is someone going to review it, or part of it? Or is Vipin expected to do something on the repository assigned to him (maybe he already did)? Thx for clarifying it... Rgds, Arm ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 00/46] Enhance spear support
On 11/30/2012 01:34 PM, Wolfgang Denk wrote: Dear Armando Visconti, In message50b89534.6040...@st.com you wrote: Not sure what are next steps for this patchset. Is someone going to review it, or part of it? Or is Vipin expected to do something on the repository assigned to him (maybe he already did)? Vipin volunteered as custodian, so the next step should be that he performs a final review, applies the patches to his repo, and sends a pullr equest to Albert. Clear. Ciao, Arm ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 00/46] Enhance spear support
On 11/11/2012 06:49 PM, Albert ARIBAUD wrote: Hi Wolfgang, On Sun, 11 Nov 2012 08:50:46 +0100, Wolfgang Denkw...@denx.de wrote: Dear Stefan, In message509f4194.9070...@denx.de you wrote: Vipin, please send your public ssh key to Wolfgang so that we can create the new spear U-Boot git repository for you. Will this be only SPEAr, or should we expect other chips fromSTM to go though it, too (so a more generic name like u-boot-stm would be better) ? Even if it's only SPEAr for now, I 'vote' for u-boot-stm. It is only SPEAr for the moment, but I think that Vipin can be the custodian also for other stm devices... Vipin, do you agree with that? Rgds, Arm -- -- Every step appears to be the unavoidable consequence of the -- preceding one. (A. Einstein) -- Armando Visconti Mobile: (+39) 346 8879146 Senior SW EngineerFax:(+39) 02 93519290 CPG Work: (+39) 02 93519683 Computer System Division e-mail: armando.visco...@st.com ST Microelectronics TINA: 051 4683 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 00/18] Network support for spear platforms and SPEAr1300
Tom, Wolfgang,
THis time everything should be ok.
Thks for your attention,
Arm
Vipin KUMAR wrote:
Dear Wolfgang, Tom,
The following set of patches is the fifth iteration of patches for the
following
changes
- Network device driver for synopsys designware peripheral
- SPEAr1300 SoC support
- A few other misc changes and bugfixes
These also include the feedbacks given by Tom and Ben
These set of patches are rebased on e5ed138a23923ebe61843244748d98d3dbc04777
Please include these changes in the mainline u-boot
Regards
Vipin
Vipin KUMAR (18):
change_bit routine defined
SPEAr : SMI erase and write timeouts increased
SPEAr : Placing ethaddr write and read within CONFIG_CMD_NET
SPEAr : Reducing the max RAM size to 128MB
SPEAr : Basic arch related support added for SPEAr SoCs
SPEAr : Network driver support added
SPEAr : Network support configured for spear SoCs
SPEAr : macb driver support added for spear310 and spear320
SPEAr : FSMC driver support added
SPEAr : Configuring FSMC driver for NAND interface
SPEAr : i2c driver moved completely into drivers/i2c
SPEAr : smi driver moved completely into drivers/mtd
SPEAr : USB Device Controller driver support added
SPEAr : Supporting various configurations for spear3xx and spear6xx
boards
SPEAr : Basic spear1300 architecture support added
SPEAr : spear1300 SoC support added
SPEAr : Removing extraneous code
SPEAr : USB device controller bugfixes
MAINTAINERS|1 +
MAKEALL|1 +
Makefile | 28 +-
arch/arm/cpu/arm926ejs/spear/Makefile |3 +-
arch/arm/cpu/arm926ejs/spear/cpu.c | 78 +++
arch/arm/cpu/arm_cortexa8/spear13xx/Makefile | 52 ++
arch/arm/cpu/arm_cortexa8/spear13xx/cache.S| 114 +
arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c | 96
.../arm_cortexa8/spear13xx/reset.c}| 52 +--
arch/arm/cpu/arm_cortexa8/spear13xx/timer.c| 138 +
.../arm/include/asm/arch-spear/clk.h | 26 +-
arch/arm/include/asm/arch-spear/hardware.h | 16 +-
arch/arm/include/asm/arch-spear/spr_misc.h |5 +
.../arm/include/asm/arch-spear13xx/hardware.h | 33 +-
arch/arm/include/asm/arch-spear13xx/spr_gpt.h | 85
arch/arm/include/asm/arch-spear13xx/spr_misc.h | 317
.../arm/include/asm/arch-spear13xx/sys_proto.h | 29 +-
arch/arm/include/asm/bitops.h | 11 +-
board/spear/common/Makefile| 10 +-
board/spear/common/spr_misc.c | 32 +-
board/spear/spear1300/Makefile | 51 ++
board/spear/spear1300/config.mk| 28 +
board/spear/spear1300/spear1300.c | 88
.../spear/spear1300/spr_lowlevel_init.S| 35 +-
board/spear/spear300/config.mk | 11 -
board/spear/spear300/spear300.c| 18 +-
board/spear/spear310/config.mk | 11 -
board/spear/spear310/spear310.c| 35 ++-
board/spear/spear320/config.mk | 11 -
board/spear/spear320/spear320.c| 23 +-
board/spear/spear600/config.mk | 11 -
board/spear/spear600/spear600.c| 18 +-
doc/README.designware_eth | 25 +
doc/README.spear | 46 ++-
drivers/i2c/Makefile |2 +-
drivers/i2c/{spr_i2c.c = designware_i2c.c}|4 +-
.../spr_i2c.h = drivers/i2c/designware_i2c.h |6 +-
drivers/mtd/Makefile |2 +-
drivers/mtd/nand/Makefile |2 +-
drivers/mtd/nand/fsmc_nand.c | 366 ++
drivers/mtd/nand/spr_nand.c| 124 -
drivers/mtd/{spr_smi.c = st_smi.c}| 59 ++-
.../arch-spear/spr_smi.h = drivers/mtd/st_smi.h |8 +-
drivers/net/Makefile |1 +
drivers/net/designware.c | 531
drivers/net/designware.h | 264 ++
drivers/serial/usbtty.h|4 +-
drivers/usb/gadget/Makefile|2 +-
drivers/usb/gadget/{spr_udc.c = designware_udc.c} | 116 +++--
include/configs/spear-common.h | 33 +-
include/configs/spear13xx_evb.h| 202
include/configs/{spear3xx.h = spear3xx_evb.h} | 30 ++
include/configs/{spear6xx.h = spear6xx_evb.h} | 13 +
include/linux/mtd/fsmc_nand.h | 104
include/netdev.h
Re: [U-Boot] SPEAr (ARM) patchset inclusion for u-boot
Vipin, I have already sent a patch v4 specifically for Network subpatches and got an ack from Ben for both the patches Please have a look at http://www.mail-archive.com/u-boot@lists.denx.de/msg33153.html http://www.mail-archive.com/u-boot@lists.denx.de/msg33152.html OK, good. So, you've already taken care of Ben's recommendation in your patchset. The whole patch series should be rebased; please use the next branch as reference, and I will care that it goes in more quickly next time. Thanks for your inputs. So, Should I rebase and send a next version ? I think so. Pls rebase it to latest next and resend it accordingly. I think this time we will be able to got it included in the mainline. Thanks, Arm ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] SPEAr (ARM) patchset inclusion for u-boot
On 6/22/2010 10:30 PM, Wolfgang Denk wrote: Dear Armando VISCONTI, Ciao Wolfgang, In message4c20d70c.2050...@st.com you wrote: As the patchset has already been acked by the proper people in the community and since it has been floating around for long time can you possibly include it in your tree? As far as I can tell there was a review comment from Ben about [PATCH v3 08/19] which has not been taken care of yet, see http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/78434/focus=78606 Yes I see the comment. I let Vipin reply on it as I'm in business trip in US and have limited access to the source code. For sure if this is the only point missing we certainly do it very quickly and resubmit the patchset. Actually we really believe in open source contribution, but I'm worried that Vipin is getting a little bit frustrated as he doesn't see the conclusion of his hard work. Ben's comment is right, I agree that this should be fixed. Other parts of the patch series (like [PATCH v3 01/19]) have been added (independently) to mainline long ago. So, I guess we should avoid resubmitting the already-added patches, right? The whole patch series should be rebased; please use the next branch as reference, and I will care that it goes in more quickly next time. ok, sounds good. Thx, Armando ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 07/17] SPEAr : Network driver support added
Hi Ben, I agree that MDIO bus probing doesn't make much sense. I don't know anything about your SOC, but the ones that I work with typically have multiple MACs (data link) but only one MDIO bus (control link). The end result is multiple PHYs on a multi-drop bus, and there's no way of knowing which one has its data link connected to which MAC. I'd prefer to see it hard-coded, either through a CONFIG option or an environment variable. In our SoC current architecture there are multiple sdio buses, basically one for each MAC. Neverthelees this architecture might change in the future. Moreover, I agree that driver should be generic, so I guess that we might add a phy_addr field in the device structure and pass it thru the initialize routine, as the macb driver is doing. In the meantime I saw that Vipin already provided a V2 of the driver, which is still in the old way. Vipin, can you possibly provide your comments? Thanks, Arm -- -- Every step appears to be the unavoidable consequence of the -- preceding one. (A. Einstein) -- Armando Visconti Mobile: (+39) 346 8879146 Senior SW EngineerFax:(+39) 02 93519290 CPG Work: (+39) 02 93519683 Computer System Division e-mail: armando.visco...@st.com ST Microelectronics TINA: 051 4683 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 07/17] SPEAr : Network driver support added
Ben,
I have a specific question on the way we handle phy address
in SPEAr.
+
+static u8 find_phy(struct eth_device *dev)
+{
+u8 phy_addr = 0;
+u16 ctrl, oldctrl;
+
+do {
+eth_mdio_read(dev, phy_addr, PHY_BMCR,ctrl);
+oldctrl = ctrl PHY_BMCR_AUTON;
+
+ctrl ^= PHY_BMCR_AUTON;
+eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl);
+eth_mdio_read(dev, phy_addr, PHY_BMCR,ctrl);
+ctrl= PHY_BMCR_AUTON;
+
+if (ctrl == oldctrl) {
+phy_addr++;
+} else {
+ctrl ^= PHY_BMCR_AUTON;
+eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl);
+break;
+}
+} while (phy_addr 32);
+
+return phy_addr;
+}
+
As you can see we use an auto-probing mechanism implemented as find_phy()
routine. This auto-probing is also used in other cases, like the
drivers/net/mcfmii.c (mii_discover_phy()).
Actually I'm not sure this auto-probing mechanism is correct, as it
works only
in case (very used) in which the MAC-PHY are in 1:1 relationship.
Instead, the MDIO bus nature implies that there might be N MACs and M
PHYs connected
to the bus, so the auto-probing would not work.
See here some comments on the same:
http://lists.ozlabs.org/pipermail/devicetree-discuss/2010-February/001670.html
In our PCB we have the 1:1 relationship, but since the dw_eth.c driver
is generic, it
might be used on differently designed pcb.
What is your general opinion in that?
Should we implement it differently?
Regards,
Arm
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Re: [U-Boot] [PATCH RFC 0/2] dcache on ARM
Alessandro, I don't see the flush_cache() call inside cmd_bootm.c. Don't you think it is necessary before jumping to Linux? Or am I missing something? Rgds, Arm Alessandro Rubini wrote: These patches enable the dcache for ARM9. It's mainly an RFC, as some details are still to be sorted out, but they work fine (and the speed increase is noticeable for kernel boots and cp.b -- didn't make more tests. I tested the code on at91sam9263ek and nhk8815. No makeall at this point, as I'm mainly interested in comments here. This is based on the cache-cp15.c infrastructure set up by Jean-Christophe for icache enabling. I'm sure Drasko Draskovic has better code, but since he has sent no a patch yet (asked in Mar 2009, and then again and again), here is my approach. Alessandro Rubini (2): flush cache for arm926 arm cp15: setup mmu and enable dcache lib_arm/cache-cp15.c | 37 + lib_arm/cache.c |6 ++ 2 files changed, 43 insertions(+), 0 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot -- -- Every step appears to be the unavoidable consequence of the -- preceding one. (A. Einstein) -- Armando Visconti Mobile: (+39) 346 8879146 Senior SW EngineerFax:(+39) 02 93519290 CPG Work: (+39) 02 93519683 Computer System Division e-mail: armando.visco...@st.com ST Microelectronics TINA: 051 4683 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [STATUS] Merge Window closed, waiting for pull requests
Ciao Wolfgang, I think it would be better if could pull directly from Tom's tree. Neverthelss, I already applied Vipin's patches on 'upstream' branch of our public git tree, which I had rebased on the latest 'origin/master' of your git tree. Our tree: http://git.stlinux.com/spear/u-boot Pls note that it will be re-syncronyzed this night, so you might be able to access it tomorrow. Rgds, Arm Vipin Kumar wrote: On Wed, Jan 20, 2010 at 4:00 AM, Wolfgang Denk w...@denx.de wrote: Hi as you probably have noticed, the merge window closed about 24 hours ago. Checking my list, I still see s _long_ list of ARM related patches that have not been processed yet. For many of them I haven't seen any review comments, nor have architecture maintainer picked these up and sent pull requests to Tom. Dear Wolfgang, Can you please take the following patches into your list http://www.mail-archive.com/u-boot@lists.denx.de/msg27418.html http://www.mail-archive.com/u-boot@lists.denx.de/msg27416.html http://www.mail-archive.com/u-boot@lists.denx.de/msg27415.html http://www.mail-archive.com/u-boot@lists.denx.de/msg27423.html http://www.mail-archive.com/u-boot@lists.denx.de/msg27422.html http://www.mail-archive.com/u-boot@lists.denx.de/msg27417.html http://www.mail-archive.com/u-boot@lists.denx.de/msg27420.html http://www.mail-archive.com/u-boot@lists.denx.de/msg27419.html http://www.mail-archive.com/u-boot@lists.denx.de/msg27414.html http://www.mail-archive.com/u-boot@lists.denx.de/msg27412.html http://www.mail-archive.com/u-boot@lists.denx.de/msg27421.html http://www.mail-archive.com/u-boot@lists.denx.de/msg27413.html http://www.mail-archive.com/u-boot@lists.denx.de/msg27411.html These patches are already acked by Tom, Scott and Remy http://www.mail-archive.com/u-boot@lists.denx.de/msg27547.html http://www.mail-archive.com/u-boot@lists.denx.de/msg27668.html http://www.mail-archive.com/u-boot@lists.denx.de/msg27670.html -Vipin Can you please try and work on this now, so that we can have the outstanding patches integrated into mainline in the next few days? Thanks in advance. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de The faster I go, the behinder I get. -- Lewis Carroll ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot -- -- Every step appears to be the unavoidable consequence of the -- preceding one. (A. Einstein) -- Armando Visconti Mobile: (+39) 346 8879146 Senior SW EngineerFax:(+39) 02 93519290 CPG Work: (+39) 02 93519683 Computer System Division e-mail: armando.visco...@st.com ST Microelectronics TINA: 051 4683 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 00/12] Support for SPEAr SoCs
Tom, After Remy's and Scott's Acks, are we still in time for merging the patch set into the mainline? I really count on that Thx, Armando Remy Bohmer wrote: Hi, USB subsystem http://www.mail-archive.com/u-boot@lists.denx.de/msg27163.html I saw these comments. I did not see any explicit ack's I thought it was explicit enough... so again: Acked-by: Remy Bohmer li...@bohmer.net Remy -- -- Every step appears to be the unavoidable consequence of the -- preceding one. (A. Einstein) -- Armando Visconti Mobile: (+39) 346 8879146 Senior SW EngineerFax:(+39) 02 93519290 CPG Work: (+39) 02 93519683 Computer System Division e-mail: armando.visco...@st.com ST Microelectronics TINA: 051 4683 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/9] Added support for SPEAr SoCs
Thanks Tom, Tomorrow Vipin will change it according to your inputs. He will also do the rebase to latest uboot. Rgds, Arm Tom wrote: Vipin KUMAR wrote: This patch set is a reworked patch which incorporates all review feedbacks from earlier earlier mails This patch set contains the support for 4 SoCs SPEAr600 SPEAr300 SPEAr310 SPEAr320 SPEAr is an ARM based SoC which supports rich set of peripherals like Ethernet, USB Host, USB Device etc to support various general applications For further info on SPEAr SoC, please see README.spear also contained in the patch set. Vipin (9): Added README.spear SPEAr600 SoC support added SPEAr300 SoC support added SPEAr310 SoC support added SPEAr320 SoC support added i2c driver support for SPEAr SoCs smi driver support for SPEAr SoCs nand(fsmc) driver support for SPEAr SoCs usbd driver support for SPEAr SoCs This review is mechanical. Whitespace/formatting checking with checkpatch.pl is in general ok. Some warnings about braces, fix if you think approprate On patch 9, ERROR: foo * bar should be foo *bar #283: FILE: drivers/usb/gadget/spr_udc.c:229: +static void usbputpcktofifo(int epNum, u8 * bufp, u32 len) These should fixed The readme has trailing whitespace issues that were caught in the 'git am ' Please fix. On patch 9, usb. There are some merge warnings. Applying: usbd driver support for SPEAr SoCs error: patch failed: drivers/serial/usbtty.h:31 error: drivers/serial/usbtty.h: patch does not apply Using index info to reconstruct a base tree... Falling back to patching base and 3-way merge... Auto-merged drivers/serial/usbtty.h There are some recent updates for usb. Please rebase you source. On MAKEALL arm Spear boards fail to build Errors similar to this Assembler messages: Fatal error: can't create build/board/spear/spear300/../common/spr_misc.o: No such file or directory Assembler messages: Fatal error: can't create build/board/spear/spear300/../common/spr_lowlevel_init.o: No such file or directory The way i test MAKEALL is to define the BUILD_DIR to be something that is not the source directory. Please rerun MAKEALL this way and resolve these errors. I will do a more detailed review soon. Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot -- -- Every step appears to be the unavoidable consequence of the -- preceding one. (A. Einstein) -- Armando Visconti Mobile: (+39) 346 8879146 Senior SW EngineerFax:(+39) 02 93519290 CPG Work: (+39) 02 93519683 Computer System Division e-mail: armando.visco...@st.com ST Microelectronics TINA: 051 4683 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/9] Support for SPEAr SoCs
All, Just fyi SPEAr is an ARM based family of SoC designed by us here in STMicro. THx for your help in reviewing. Regards, Arm Vipin KUMAR wrote: This patchset contains the support for 4 SoCs from SPEAr family SPEAr300 SPEAr310 SPEAr320 SPEAr600 It also contains the drivers needed for spear devices Regards Vipin Kumar Vipin (9): i2c driver support for SPEAr SoCs smi driver support for SPEAr SoCs nand driver support for SPEAr SoCs usbd driver and usb boot firmware support for SPEAr SoCs SPEAr600 SoC support added SPEAr300 SoC support added SPEAr310 SoC support added SPEAr320 SoC support added SPEAr600 build support added MAKEALL|4 + Makefile | 12 + board/spear/common/spr_lowlevel_init.S | 202 + board/spear/common/spr_misc.c | 270 +++ board/spear/spear300/Makefile | 52 ++ board/spear/spear300/config.mk | 39 + board/spear/spear300/spr300_board.c| 57 ++ board/spear/spear310/Makefile | 52 ++ board/spear/spear310/config.mk | 42 + board/spear/spear310/spr310_board.c| 58 ++ board/spear/spear320/Makefile | 52 ++ board/spear/spear320/config.mk | 42 + board/spear/spear320/spr320_board.c| 58 ++ board/spear/spear600/Makefile | 52 ++ board/spear/spear600/config.mk | 39 + board/spear/spear600/spr600_board.c| 53 ++ common/cmd_bdinfo.c| 20 + common/main.c |2 + cpu/arm926ejs/spear/Makefile | 52 ++ cpu/arm926ejs/spear/reset.c| 49 ++ cpu/arm926ejs/spear/timer.c| 148 drivers/i2c/Makefile |1 + drivers/i2c/spr_i2c.c | 321 drivers/mtd/Makefile |1 + drivers/mtd/nand/Makefile |1 + drivers/mtd/nand/spr_nand.c| 126 +++ drivers/mtd/spr_smi.c | 548 + drivers/serial/usbtty.h|2 + drivers/usb/gadget/Makefile|1 + drivers/usb/gadget/spr_udc.c | 996 include/asm-arm/arch-spear/spr_defs.h | 31 + include/asm-arm/arch-spear/spr_emi.h | 55 ++ include/asm-arm/arch-spear/spr_gpt.h | 83 ++ include/asm-arm/arch-spear/spr_i2c.h | 143 include/asm-arm/arch-spear/spr_misc.h | 126 +++ include/asm-arm/arch-spear/spr_nand.h | 58 ++ include/asm-arm/arch-spear/spr_smi.h | 112 +++ include/asm-arm/arch-spear/spr_syscntl.h | 38 + include/asm-arm/arch-spear/spr_xloader_table.h | 67 ++ include/asm-arm/u-boot.h |5 + include/configs/spear300.h | 260 ++ include/configs/spear310.h | 353 + include/configs/spear320.h | 336 include/configs/spear600.h | 260 ++ include/usb/spr_udc.h | 227 ++ 45 files changed, 5506 insertions(+), 0 deletions(-) create mode 100755 board/spear/common/spr_lowlevel_init.S create mode 100755 board/spear/common/spr_misc.c create mode 100755 board/spear/spear300/Makefile create mode 100755 board/spear/spear300/config.mk create mode 100755 board/spear/spear300/spr300_board.c create mode 100755 board/spear/spear310/Makefile create mode 100755 board/spear/spear310/config.mk create mode 100755 board/spear/spear310/spr310_board.c create mode 100755 board/spear/spear320/Makefile create mode 100755 board/spear/spear320/config.mk create mode 100755 board/spear/spear320/spr320_board.c create mode 100755 board/spear/spear600/Makefile create mode 100755 board/spear/spear600/config.mk create mode 100755 board/spear/spear600/spr600_board.c create mode 100755 cpu/arm926ejs/spear/Makefile create mode 100755 cpu/arm926ejs/spear/reset.c create mode 100755 cpu/arm926ejs/spear/timer.c mode change 100644 = 100755 drivers/i2c/Makefile create mode 100755 drivers/i2c/spr_i2c.c mode change 100644 = 100755 drivers/mtd/Makefile create mode 100755 drivers/mtd/nand/spr_nand.c create mode 100755 drivers/mtd/spr_smi.c mode change 100644 = 100755 drivers/serial/usbtty.h mode change 100644 = 100755 drivers/usb/gadget/Makefile create mode 100755 drivers/usb/gadget/spr_udc.c create mode 100644 include/asm-arm/arch-spear/spr_defs.h create mode 100755 include/asm-arm/arch-spear/spr_emi.h create mode 100755 include/asm-arm/arch-spear/spr_gpt.h create mode 100755 include/asm-arm/arch-spear/spr_i2c.h create mode 100644
Re: [U-Boot] [PATCH 5/9] SPEAr600 SoC support added
Ciao Peter, The changes to board/* should be moved out of this patch and into patch 9 SPEAr600 build support added. Same comment for include/configs/spear600.h. Tomorrow we will resend patch_5 and patch_9. It'd also be nice to give a description of each board and SOC you add. Eg what's the difference between the 300, 310, 320, 600? What peripherals do they support? What does SPEAr stand for? More commit messages in general wouldn't hurt:) SPEAr (Structured Processor Enhanced Architecture). You can find some description throughout Internet, for example here: http://embedded-system.net/spear-basic-customizable-arm-based-soc-stmicroelectronics.html (SPEARBasic means SPEAr300.) As you can see this SoC family embeds a customizable logic that could be programmed one-time by a customer at silicon mask level (i.e. not at runtime!). We are now adding the support in u-boot for two SoC: SPEAr600 and SPEAr3xx. Pls note that SPEAr300/310/320 differs only for the default customization. All 4 SoCs share common peripherals. 1. ARM926ejs core based (sp600 has two AMP cores, the 2nd handled only in Linux) 2. FastEthernet (sp600 has Gbit version, but same controller - GMAC) 3. USB Host 4. USB Device 5. NAND controller (FSMC) 6. Serial NOR ctrl 7. I2C 8. SPI 9. CLCD 10. others .. sp600 is not customized by default. sp3xx are differently customized... sp300 is more oriented to TELECOM/video (it has tdm, i2s, ITU i/f support) sp310 for networking (a part GMAC in fixed part, it has 5 MACB ctrls in custom) sp320 for industrial (SPP ctrl, CAN ctrl, 2 MACBs, ...) Everything is supported in Linux. u-boot is not currently supporting all peripeharls (just a few). Regards, Arm Peter Tyser wrote: On Wed, 2009-12-16 at 14:48 +0530, Vipin KUMAR wrote: Signed-off-by: Vipin vipin.ku...@st.com --- board/spear/common/spr_lowlevel_init.S | 202 ++ board/spear/common/spr_misc.c | 270 board/spear/spear600/Makefile | 52 + board/spear/spear600/config.mk | 39 board/spear/spear600/spr600_board.c| 53 + The changes to board/* should be moved out of this patch and into patch 9 SPEAr600 build support added. Same comment for include/configs/spear600.h. common/cmd_bdinfo.c| 20 ++ cpu/arm926ejs/spear/Makefile | 52 + cpu/arm926ejs/spear/reset.c| 49 + cpu/arm926ejs/spear/timer.c| 148 + include/asm-arm/arch-spear/spr_defs.h | 31 +++ include/asm-arm/arch-spear/spr_emi.h | 55 + include/asm-arm/arch-spear/spr_gpt.h | 83 include/asm-arm/arch-spear/spr_syscntl.h | 38 include/asm-arm/arch-spear/spr_xloader_table.h | 67 ++ include/asm-arm/u-boot.h |5 + include/configs/spear600.h | 260 +++ It'd also be nice to give a description of each board and SOC you add. Eg what's the difference between the 300, 310, 320, 600? What peripherals do they support? What does SPEAr stand for? More commit messages in general wouldn't hurt:) Best, Peter ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot -- -- Every step appears to be the unavoidable consequence of the -- preceding one. (A. Einstein) -- Armando Visconti Mobile: (+39) 346 8879146 Senior SW EngineerFax:(+39) 02 93519290 CPG Work: (+39) 02 93519683 Computer System Division e-mail: armando.visco...@st.com ST Microelectronics TINA: 051 4683 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] cpu/cortex_a9
Dears, I'm not able to find the code for Cortex A9, but in some discussion I saw it is (maybe) planned to be in cpu/cortex_a9. Is this correct? Anyway, can you possibly update me about the current status? Thx, Armando ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] working with the Custodian's GIT
Hello everybody, We are a team of developers that would like to post a series of patches for the support in u-boot of a new ARM platform (SPEAr). I have one questions regarding the GIT. Do we really require to have a public GIT repository to publish our work so that others can watch at it? Or it is enough just to clone the proper GIT repository and submit GIT patches to the mailing list for the review? We are beyond a company firewall, and I would prefer, if possible, to simplify the transaction. No problems to clone the GIT thru http. Thx, Armando ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
