[U-Boot] [PATCH] arm: PSCI: remove CONFIG_MP to support LS1012A
To support PSCI on LS1012A, remove the macro CONFIG_MP.
And, do code cleanup.
Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
---
arch/arm/cpu/armv8/cpu-dt.c | 14
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 33 +--
arch/arm/cpu/armv8/sec_firmware.c | 2 +-
arch/arm/include/asm/arch-fsl-layerscape/mp.h | 4
arch/arm/include/asm/armv8/sec_firmware.h | 7 ++
5 files changed, 33 insertions(+), 27 deletions(-)
diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c
index 9ffb49c..247d8da 100644
--- a/arch/arm/cpu/armv8/cpu-dt.c
+++ b/arch/arm/cpu/armv8/cpu-dt.c
@@ -6,26 +6,22 @@
#include
#include
-#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
#include
-#endif
+#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
int psci_update_dt(void *fdt)
{
-#ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_PSCI)
-#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
/*
* If the PSCI in SEC Firmware didn't work, avoid to update the
* device node of PSCI. But still return 0 instead of an error
* number to support detecting PSCI dynamically and then switching
* the SMP boot method between PSCI and spin-table.
*/
- if (sec_firmware_support_psci_version() == 0x)
+ if (sec_firmware_support_psci_version() == PSCI_INVALID_VER)
return 0;
-#endif
+
fdt_psci(fdt);
-#endif
-#endif
+
return 0;
}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 0b516e3..a2b6c02 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -14,18 +14,14 @@
#include
#include
#include
-#ifdef CONFIG_MP
#include
-#endif
#include
#include
#include
#ifdef CONFIG_FSL_ESDHC
#include
#endif
-#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
#include
-#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -391,28 +387,31 @@ int cpu_eth_init(bd_t *bis)
return error;
}
+static inline int check_psci(void)
+{
+ unsigned int psci_ver;
+
+ psci_ver = sec_firmware_support_psci_version();
+ if (psci_ver == PSCI_INVALID_VER)
+ return 1;
+
+ return 0;
+}
+
int arch_early_init_r(void)
{
-#ifdef CONFIG_MP
- int rv = 1;
- u32 psci_ver = 0x;
-#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
erratum_a009635();
#endif
-#ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
- /* Check the psci version to determine if the psci is supported */
- psci_ver = sec_firmware_support_psci_version();
-#endif
- if (psci_ver == 0x) {
- rv = fsl_layerscape_wake_seconday_cores();
- if (rv)
+ if (check_psci()) {
+ printf("PSCI: PSCI does not exist.\n");
+
+ /* if PSCI does not exist, boot secondary cores here */
+ if (fsl_layerscape_wake_seconday_cores())
printf("Did not wake secondary cores\n");
}
-#endif
#ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
diff --git a/arch/arm/cpu/armv8/sec_firmware.c
b/arch/arm/cpu/armv8/sec_firmware.c
index 2ddd67e..ecab451 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -227,7 +227,7 @@ unsigned int sec_firmware_support_psci_version(void)
if (sec_firmware_addr & SEC_FIRMWARE_RUNNING)
return _sec_firmware_support_psci_version();
- return 0x;
+ return PSCI_INVALID_VER;
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h
b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
index f7306ff..7f01423 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
@@ -29,7 +29,11 @@ extern u64 __spin_table[];
extern u64 __real_cntfrq;
extern u64 *secondary_boot_code;
extern size_t __secondary_boot_code_size;
+#ifdef CONFIG_MP
int fsl_layerscape_wake_seconday_cores(void);
+#else
+static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; }
+#endif
void *get_spin_tbl_addr(void);
phys_addr_t determine_mp_bootpg(void);
void secondary_boot_func(void);
diff --git a/arch/arm/include/asm/armv8/sec_firmware.h
b/arch/arm/include/asm/armv8/sec_firmware.h
index eb68185..f3e6a80 100644
--- a/arch/arm/include/asm/armv8/sec_firmware.h
+++ b/arch/arm/include/asm/armv8/sec_firmware.h
@@ -11,12 +11,19 @@
#include
#endif
+#define PSCI_INVALID_VER 0x
+
int sec_firmware_init(const void *, u32 *, u32 *);
int _sec_firmware_entry(const void *, u32 *, u32 *);
bool sec_firmware_is_valid(const void *);
#ifdef CONFIG_ARMV8_PSCI
unsigned int sec_firmware_support_psci_version(void);
unsigned int _sec_firmware_support_psci_version(void);
+#else
+static inline unsigned int sec_firmware_support_psci_version(vo
Re: [U-Boot] [PATCH] arm: psci: save and restore registers from r4 to r12
On Thu, Oct 13, 2016 at 5:52 PM, Chen-Yu Tsai <w...@csie.org> wrote:
> On Sat, Oct 8, 2016 at 7:08 PM, Chenhui Zhao <chenhui.z...@nxp.com> wrote:
>> Save and restore core registers from r4 to r12 so that PSCI code won't
>> break their value.
>>
>> Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
>> Signed-off-by: Alison Wang <alison.w...@nxp.com>
>> Signed-off-by: Abhimanyu Saini <abhimanyu.sa...@nxp.com>
>> ---
>> arch/arm/cpu/armv7/psci.S | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
>> index 6a36208..746297c 100644
>> --- a/arch/arm/cpu/armv7/psci.S
>> +++ b/arch/arm/cpu/armv7/psci.S
>> @@ -152,7 +152,7 @@ _psci_table:
>> .word 0
>>
>> _smc_psci:
>> - push{r4-r7,lr}
>> + push{r4-r12,lr}
>
> This change is not needed. This function only uses r4-r7.
> Any subroutines called should save variable registers (r4-r12)
> themselves, per the ARM calling conventions.
>
> ChenYu
>
I do not think it is a normal calling, instead it is an exception
handler. In the exception context,
it is necessary to save/restore all registers.
Sorry, my mail server has something wrong.
Chenhui
>>
>> @ Switch to secure
>> mrc p15, 0, r7, c1, c1, 0
>> @@ -175,7 +175,7 @@ _smc_psci:
>> @ Switch back to non-secure
>> 2: mcr p15, 0, r7, c1, c1, 0
>>
>> - pop {r4-r7, lr}
>> + pop {r4-r12, lr}
>> movspc, lr @ Return to the kernel
>>
>> @ Requires dense and single-cluster CPU ID space
>> --
>> 1.9.1
>>
>> ___
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[U-Boot] [PATCH] arm: psci: save and restore registers from r4 to r12
Save and restore core registers from r4 to r12 so that PSCI code won't
break their value.
Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
Signed-off-by: Alison Wang <alison.w...@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.sa...@nxp.com>
---
arch/arm/cpu/armv7/psci.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 6a36208..746297c 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -152,7 +152,7 @@ _psci_table:
.word 0
_smc_psci:
- push{r4-r7,lr}
+ push{r4-r12,lr}
@ Switch to secure
mrc p15, 0, r7, c1, c1, 0
@@ -175,7 +175,7 @@ _smc_psci:
@ Switch back to non-secure
2: mcr p15, 0, r7, c1, c1, 0
- pop {r4-r7, lr}
+ pop {r4-r12, lr}
movspc, lr @ Return to the kernel
@ Requires dense and single-cluster CPU ID space
--
1.9.1
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[U-Boot] [PATCH] arm: psci: save and restore registers from r4 to r12
Save and restore core registers from r4 to r12 so that PSCI code won't
break their value.
Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
Signed-off-by: Alison Wang <alison.w...@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.sa...@nxp.com>
---
arch/arm/cpu/armv7/psci.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 6a36208..746297c 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -152,7 +152,7 @@ _psci_table:
.word 0
_smc_psci:
- push{r4-r7,lr}
+ push{r4-r12,lr}
@ Switch to secure
mrc p15, 0, r7, c1, c1, 0
@@ -175,7 +175,7 @@ _smc_psci:
@ Switch back to non-secure
2: mcr p15, 0, r7, c1, c1, 0
- pop {r4-r7, lr}
+ pop {r4-r12, lr}
movspc, lr @ Return to the kernel
@ Requires dense and single-cluster CPU ID space
--
1.9.1
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Re: [U-Boot] [PATCH 3/9] ARM: ARMv7: PSCI: move target PC in each CPU stack no longer is shared
Add Hongbo.
Thanks,
Chenhui
From: Dongsheng Wang <dongsheng.w...@nxp.com>
Sent: Monday, January 18, 2016 12:27 PM
To: albert.u.b...@aribaud.net
Cc: tr...@konsulko.com; sba...@denx.de; i...@hellion.org.uk;
hdego...@redhat.com; twar...@nvidia.com; Huan Wang; york sun;
jan.kis...@siemens.com; Frank Li; Peng Fan; Zhengxiong Jin; Chenhui Zhao;
o...@buserror.net; u-boot@lists.denx.de; Dongsheng Wang
Subject: [PATCH 3/9] ARM: ARMv7: PSCI: move target PC in each CPU stack no
longer is shared
From: Wang Dongsheng <dongsheng.w...@nxp.com>
All of cpu share the same targetPC space that is unsafe. So move
target PC save space into CPU stack.
Signed-off-by: Wang Dongsheng <dongsheng.w...@nxp.com>
---
arch/arm/cpu/armv7/ls102xa/psci.S | 4 +--
arch/arm/cpu/armv7/mx7/psci.S | 4 +--
arch/arm/cpu/armv7/psci.S | 51 ---
arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 4 +--
arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 4 +--
arch/arm/cpu/armv7/virt-dt.c | 3 ++-
arch/arm/include/asm/psci.h | 4 +++
arch/arm/mach-tegra/psci.S| 4 +--
8 files changed, 53 insertions(+), 25 deletions(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S
b/arch/arm/cpu/armv7/ls102xa/psci.S
index 0b067d9..3a34064 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -36,9 +36,7 @@ psci_cpu_on:
and r1, r1, #0xff
mov r0, r1
- bl psci_get_cpu_stack_top
- str r2, [r0]
- dsb
+ bl psci_save_target_pc
@ Get DCFG base address
movwr4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0x)
diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S
index 34c6ab3..cb39f27 100644
--- a/arch/arm/cpu/armv7/mx7/psci.S
+++ b/arch/arm/cpu/armv7/mx7/psci.S
@@ -30,9 +30,7 @@ psci_cpu_on:
push{lr}
mov r0, r1
- bl psci_get_cpu_stack_top
- str r2, [r0]
- dsb
+ bl psci_save_target_pc
ldr r2, =psci_cpu_entry
bl imx_cpu_on
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 2425f6a..0e0f98e 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -20,6 +20,8 @@
#include
#include
+#define SAVE_SPACE_TARGET_PC_OFFSET0x0
+
.pushsection ._secure.text, "ax"
.arch_extension sec
@@ -196,27 +198,58 @@ ENDPROC(psci_cpu_off_common)
@ expects CPU ID in r0 and returns stack top in r0
ENTRY(psci_get_cpu_stack_top)
- mov r5, #0x400 @ 1kB of stack per CPU
- mul r0, r0, r5
-
+ @ Align psci_text_end minumum page size. Even if page is greater than
+ @ 4K, we still can ensure that data is always safe access by the CPU.
ldr r5, =psci_text_end @ end of monitor text
- add r5, r5, #0x2000 @ Skip two pages
- lsr r5, r5, #12 @ Align to start of page
+ @ Detect page border
+ lsl r4, r5, #20
+ cmp r4, #0
+ beq out_psci_stack_align
+ add r5, r5, #PSCI_STACK_ALIGN_SIZE
+ lsr r5, r5, #12
lsl r5, r5, #12
- sub r5, r5, #4 @ reserve 1 word for target PC
- sub r0, r5, r0 @ here's our stack!
+
+out_psci_stack_align:
+ mov r4, #PSCI_PERCPU_STACK_SIZE
+ add r0, r0, #1
+ mul r0, r0, r4
+ add r0, r0, r5
bx lr
ENDPROC(psci_get_cpu_stack_top)
+@ Save space in percpu stack tail.
+@ expects CPU ID in r0 and returns save space address in r0.
+ENTRY(psci_get_cpu_save_space)
+ mov r10, lr
+
+ bl psci_get_cpu_stack_top
+ sub r0, r0, #PSCI_PERCPU_STACK_SIZE
+
+ bx r10
+ENDPROC(psci_get_cpu_save_space)
+
+@ Expects cpu ID in r0 and PC in r2, please ignore the return value.
+ENTRY(psci_save_target_pc)
+ push{lr}
+
+ @ Save target PC into stack
+ bl psci_get_cpu_save_space
+ str r2, [r0, #SAVE_SPACE_TARGET_PC_OFFSET]
+ dsb
+
+ pop {lr}
+ bx lr
+ENDPROC(psci_save_target_pc)
+
ENTRY(psci_cpu_entry)
bl psci_enable_smp
bl _nonsec_init
bl psci_get_cpu_id @ CPU ID => r0
- bl psci_get_cpu_stack_top @ stack top => r0
- ldr r0, [r0]@ target PC at stack top
+ bl psci_get_cpu_save_space
+ ldr r0, [r0, #SAVE_SPACE_TARGET_PC_OFFSET]
b _do_nonsec_entry
ENDPROC(psci_cpu_entry)
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index b96c5ef..e8981af 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -135,9 +135,7 @@ psci_cpu_on:
push{
[U-Boot] [PATCH] arm: ls1021atwr: program the regulator for deep sleep
Program the external regulator to switch off voltage in deep sleep.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
board/freescale/ls1021atwr/ls1021atwr.c | 34 +
1 file changed, 34 insertions(+)
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
b/board/freescale/ls1021atwr/ls1021atwr.c
index 2c8d6d1..37ec0ba 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -578,6 +578,37 @@ struct smmu_stream_id dev_stream_id[] = {
{ 0x18c, 0x0e, DEBUG },
};
+#ifdef CONFIG_DEEP_SLEEP
+/* program the regulator (MC34VR500) to support deep sleep */
+void ls1twr_program_regulator(void)
+{
+ unsigned int i2c_bus;
+ u8 i2c_device_id;
+
+#define LS1TWR_I2C_BUS_MC34VR500 1
+#define MC34VR500_ADDR 0x8
+#define MC34VR500_DEVICEID 0x4
+#define MC34VR500_DEVICEID_MASK0x0f
+
+ i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
+ i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0)
+ MC34VR500_DEVICEID_MASK;
+ if (i2c_device_id != MC34VR500_DEVICEID) {
+ printf(The regulator (MC34VR500) does not exist. The device
does not support deep sleep.\n);
+ return;
+ }
+
+ i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
+ i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
+ i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
+ i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
+ i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
+
+ i2c_set_bus_num(i2c_bus);
+}
+#endif
+
int board_init(void)
{
#ifndef CONFIG_SYS_FSL_NO_SERDES
@@ -600,6 +631,9 @@ int board_init(void)
u_qe_init();
#endif
+#ifdef CONFIG_DEEP_SLEEP
+ ls1twr_program_regulator();
+#endif
return 0;
}
--
1.9.1
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[U-Boot] [PATCH] arm: ls102xa: workaround for cache coherency problem
The RCPM FSM may not be reset after power-on, for example,
in the cases of cold boot and wakeup from deep sleep.
It causes cache coherency problem and may block deep sleep.
Therefore, reset them if they are not be reset.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
arch/arm/cpu/armv7/ls102xa/cpu.c | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index ce2d92f..a61f6d1 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -14,6 +14,13 @@
#include fsl_epu.h
+#define DCSR_RCPM2_BLOCK_OFFSET0x223000
+#define DCSR_RCPM2_CPMFSMCR0 0x400
+#define DCSR_RCPM2_CPMFSMSR0 0x404
+#define DCSR_RCPM2_CPMFSMCR1 0x414
+#define DCSR_RCPM2_CPMFSMSR1 0x418
+#define CPMFSMSR_FSM_STATE_MASK0x7f
+
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_DISPLAY_CPUINFO)
@@ -107,6 +114,27 @@ int cpu_eth_init(bd_t *bis)
int arch_cpu_init(void)
{
void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+ void *rcpm2_base =
+ (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+ u32 state;
+
+ /*
+* The RCPM FSM state may not be reset after power-on.
+* So, reset them.
+*/
+ state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0)
+ CPMFSMSR_FSM_STATE_MASK;
+ if (state != 0) {
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80);
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0);
+ }
+
+ state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1)
+ CPMFSMSR_FSM_STATE_MASK;
+ if (state != 0) {
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80);
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0);
+ }
/*
* After wakeup from deep sleep, Clear EPU registers
--
1.9.1
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[U-Boot] [PATCH] arm: ls102xa: clear EPU registers for deep sleep
After wakeup from deep sleep, Clear EPU registers as early as possible
to prevent from possible issue. It's also safe to clear at normal boot.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
arch/arm/cpu/armv7/ls102xa/Makefile|1 +
arch/arm/cpu/armv7/ls102xa/cpu.c | 16 +++
arch/arm/cpu/armv7/ls102xa/fsl_epu.c | 57 +++
arch/arm/cpu/armv7/ls102xa/fsl_epu.h | 68
arch/arm/include/asm/arch-ls102xa/config.h |1 +
5 files changed, 143 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_epu.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_epu.h
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile
b/arch/arm/cpu/armv7/ls102xa/Makefile
index d82ce8d..ae4f25d 100644
--- a/arch/arm/cpu/armv7/ls102xa/Makefile
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -7,6 +7,7 @@
obj-y += cpu.o
obj-y += clock.o
obj-y += timer.o
+obj-y += fsl_epu.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index b7dde45..fae6c68 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -12,6 +12,8 @@
#include netdev.h
#include fsl_esdhc.h
+#include fsl_epu.h
+
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_DISPLAY_CPUINFO)
@@ -101,3 +103,17 @@ int cpu_eth_init(bd_t *bis)
return 0;
}
+
+int arch_cpu_init(void)
+{
+ void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+
+ /*
+* After wakeup from deep sleep, Clear EPU registers
+* as early as possible to prevent from possible issue.
+* It's also safe to clear at normal boot.
+*/
+ fsl_epu_clean(epu_base);
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
new file mode 100644
index 000..6212640
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+
+#include fsl_epu.h
+
+/**
+ * fsl_epu_clean - Clear EPU registers
+ */
+void fsl_epu_clean(void *epu_base)
+{
+ u32 offset;
+
+ /* follow the exact sequence to clear the registers */
+ /* Clear EPACRn */
+ for (offset = EPACR0; offset = EPACR15; offset += EPACR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPEVTCRn */
+ for (offset = EPEVTCR0; offset = EPEVTCR9; offset += EPEVTCR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPGCR */
+ out_be32(epu_base + EPGCR, 0);
+
+ /* Clear EPSMCRn */
+ for (offset = EPSMCR0; offset = EPSMCR15; offset += EPSMCR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPCCRn */
+ for (offset = EPCCR0; offset = EPCCR31; offset += EPCCR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPCMPRn */
+ for (offset = EPCMPR0; offset = EPCMPR31; offset += EPCMPR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPCTRn */
+ for (offset = EPCTR0; offset = EPCTR31; offset += EPCTR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPIMCRn */
+ for (offset = EPIMCR0; offset = EPIMCR31; offset += EPIMCR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPXTRIGCRn */
+ out_be32(epu_base + EPXTRIGCR, 0);
+
+ /* Clear EPECRn */
+ for (offset = EPECR0; offset = EPECR15; offset += EPECR_STRIDE)
+ out_be32(epu_base + offset, 0);
+}
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.h
b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h
new file mode 100644
index 000..d658aad
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __FSL_EPU_H
+#define __FSL_EPU_H
+
+#include asm/types.h
+
+#define FSL_STRIDE_4B 4
+#define FSL_STRIDE_8B 8
+
+/* Block offsets */
+#define EPU_BLOCK_OFFSET 0x
+
+/* EPGCR (Event Processor Global Control Register) */
+#define EPGCR 0x000
+
+/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
+#define EPEVTCR0 0x050
+#define EPEVTCR9 0x074
+#define EPEVTCR_STRIDE FSL_STRIDE_4B
+
+/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
+#define EPXTRIGCR 0x090
+
+/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
+#define EPIMCR00x100
+#define EPIMCR31 0x17C
+#define EPIMCR_STRIDE FSL_STRIDE_4B
+
+/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
+#define EPSMCR00x200
+#define EPSMCR15 0x278
+#define EPSMCR_STRIDE FSL_STRIDE_8B
+
+/* EPECR0-15 (Event Processor Event Control
[U-Boot] [PATCH v2] fsl_esdhc: Fix esdhc disabled problem on some platforms
Some new platform's esdhc pins don't share with other function.
The eSDHC shouldn't be disabled, even if esdhc isn't defined
in hwconfig env variable.
Use CONFIG_FSL_ESDHC_PIN_MUX to fix this problem.
Signed-off-by: Chenhui Zhao b26...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
Changes for v2:
Incoperated Anton Vorontsov's review comments
drivers/mmc/fsl_esdhc.c | 14 --
include/configs/MPC837XEMDS.h |1 +
include/configs/MPC837XERDB.h |1 +
include/configs/MPC8569MDS.h |1 +
4 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 40b136c..cef2859 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -508,17 +508,19 @@ int fsl_esdhc_mmc_init(bd_t *bis)
void fdt_fixup_esdhc(void *blob, bd_t *bd)
{
const char *compat = fsl,esdhc;
- const char *status = okay;
+#ifdef CONFIG_FSL_ESDHC_PIN_MUX
if (!hwconfig(esdhc)) {
- status = disabled;
- goto out;
+ do_fixup_by_compat(blob, compat, status, disabled,
+ 8 + 1, 1);
+ return;
}
+#endif
do_fixup_by_compat_u32(blob, compat, clock-frequency,
gd-sdhc_clk, 1);
-out:
- do_fixup_by_compat(blob, compat, status, status,
- strlen(status) + 1, 1);
+
+ do_fixup_by_compat(blob, compat, status, okay,
+ 4 + 1, 1);
}
#endif
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index c237991..abccfd6 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -509,6 +509,7 @@ extern int board_pci_host_broken(void);
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_ESDHC_PIN_MUX
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 385c7c3..ea3056b 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -517,6 +517,7 @@
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_ESDHC_PIN_MUX
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 9620fd0..f4a3c2f 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -561,6 +561,7 @@ extern unsigned long get_clock_freq(void);
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_ESDHC_PIN_MUX
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
--
1.6.4.1
___
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[U-Boot] [PATCH] fsl_esdhc: Fix esdhc disabled problem on some platforms
Some platform's esdhc pins don't share with other function.
The eSDHC shouldn't be disabled, even if esdhc isn't defined
in hwconfig env variable.
Use CONFIG_FSL_ESDHC_PIN_MUX to fix this problem.
The problem was introduced by this commit:
commit b33433a63fe08c9e723ea15a7c7c7143bf527c6d
Author: Anton Vorontsov avoront...@ru.mvista.com
Date: Wed Jun 10 00:25:29 2009 +0400
fsl_esdhc: Add device tree fixups
Signed-off-by: Chenhui Zhao b26...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
drivers/mmc/fsl_esdhc.c |2 ++
include/configs/MPC837XEMDS.h |1 +
include/configs/MPC837XERDB.h |1 +
include/configs/MPC8569MDS.h |1 +
4 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index cd78714..4c8caa9 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -527,10 +527,12 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd)
const char *compat = fsl,esdhc;
const char *status = okay;
+#ifdef CONFIG_FSL_ESDHC_PIN_MUX
if (!hwconfig(esdhc)) {
status = disabled;
goto out;
}
+#endif
do_fixup_by_compat_u32(blob, compat, clock-frequency,
gd-sdhc_clk, 1);
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index c237991..abccfd6 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -509,6 +509,7 @@ extern int board_pci_host_broken(void);
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_ESDHC_PIN_MUX
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 385c7c3..ea3056b 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -517,6 +517,7 @@
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_ESDHC_PIN_MUX
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 9620fd0..f4a3c2f 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -561,6 +561,7 @@ extern unsigned long get_clock_freq(void);
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_ESDHC_PIN_MUX
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
--
1.6.4.1
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