[PATCH] net: phy: add phyid search in vendor specific space
There are devices accesible through mdio clause-45, such as
retimers, that do not have PMA or PCS blocks.
This patch adds MDIO_MMD_VEND1 on the list of device addresses
where phyid is searched. Previous order of devices was kept.
Signed-off-by: Florin Chiculita
---
drivers/net/phy/phy.c | 22 --
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 505d3ab..d2edf9e 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -783,17 +783,27 @@ static struct phy_device *get_phy_device_by_mask(struct
mii_dev *bus,
uint phy_mask,
phy_interface_t interface)
{
- int i;
struct phy_device *phydev;
-
+ int devad[] = {
+ /* Clause-22 */
+ MDIO_DEVAD_NONE,
+ /* Clause-45 */
+ MDIO_MMD_PMAPMD,
+ MDIO_MMD_WIS,
+ MDIO_MMD_PCS,
+ MDIO_MMD_PHYXS,
+ MDIO_MMD_VEND1,
+ };
+ int i, devad_cnt;
+
+ devad_cnt = sizeof(devad)/sizeof(int);
phydev = search_for_existing_phy(bus, phy_mask, interface);
if (phydev)
return phydev;
- /* Try Standard (ie Clause 22) access */
- /* Otherwise we have to try Clause 45 */
- for (i = 0; i < 5; i++) {
+ /* try different access clauses */
+ for (i = 0; i < devad_cnt; i++) {
phydev = create_phy_by_mask(bus, phy_mask,
- i ? i : MDIO_DEVAD_NONE, interface);
+ devad[i], interface);
if (IS_ERR(phydev))
return NULL;
if (phydev)
--
1.9.3
[U-Boot] [PATCH] net: phy: aquantia: wait for phy init sequence to finish
Aquantia quad-phys may take longer to initialize. This commit adds
a polling mechanism for a global alarm bit that tells if phy init
sequence is completed.
Signed-off-by: Florin Chiculita
---
drivers/net/phy/aquantia.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index 465ec2d..ae3112c 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -37,6 +37,9 @@
#define GLOBAL_FAULT 0xc850
#define GLOBAL_RSTATUS_1 0xc885
+#define GLOBAL_ALARM_1 0xcc00
+#define SYSTEM_READY_BIT 0x40
+
#define GLOBAL_STANDARD_CONTROL 0x0
#define SOFT_RESET BIT(15)
#define LOW_POWER BIT(11)
@@ -258,6 +261,17 @@ int aquantia_config(struct phy_device *phydev)
{
u32 val, id, rstatus, fault;
u32 reg_val1 = 0;
+ int num_retries = 5;
+
+ /* check if the system is out of reset and init sequence completed.
+* chip-wide reset for gen1 quad phys takes longer
+*/
+ while (--num_retries) {
+ rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_ALARM_1);
+ if (rstatus & SYSTEM_READY_BIT)
+ break;
+ mdelay(10);
+ }
id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID);
rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1);
--
1.9.3
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[U-Boot] [PATCH] board: fsl: lx2160aqds: add support for SerDes protocol 14
Add SerDes1 protocol 14 in the list of supported protocols.
This configuration enables one high-speed 100G port and PCIe x4.
Signed-off-by: Florin Chiculita
---
board/freescale/lx2160a/eth_lx2160aqds.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c
b/board/freescale/lx2160a/eth_lx2160aqds.c
index e8e4dd8..033d2f9 100644
--- a/board/freescale/lx2160a/eth_lx2160aqds.c
+++ b/board/freescale/lx2160a/eth_lx2160aqds.c
@@ -104,6 +104,8 @@ static const struct serdes_phy_config serdes1_phy_config[]
= {
EMI1, IO_SLOT_1},
{WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
EMI1, IO_SLOT_2} } },
+ {14, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1} } },
{15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
EMI1, IO_SLOT_1},
{WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
--
1.9.3
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[U-Boot] [PATCH] board: fsl: lx2160aqds: fix 'compatible' property
The code that generates the compatible property concatenates the
ethernet phy id and clause-compatible information without
separating them with a comma, therefore no ethernet phy driver will
be loaded by Linux kernel.
Signed-off-by: Florin Chiculita
---
board/freescale/lx2160a/eth_lx2160aqds.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c
b/board/freescale/lx2160a/eth_lx2160aqds.c
index f6e22d7..e8e4dd8 100644
--- a/board/freescale/lx2160a/eth_lx2160aqds.c
+++ b/board/freescale/lx2160a/eth_lx2160aqds.c
@@ -685,7 +685,7 @@ int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr,
int *subnodeoffset,
struct phy_device *phy_dev, int phandle)
{
char phy_node_name[] = "ethernet-phy@00";
- char phy_id_compatible_str[] = "ethernet-phy-id.";
+ char phy_id_compatible_str[] = "ethernet-phy-id.,";
int ret;
sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
@@ -699,7 +699,7 @@ int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr,
int *subnodeoffset,
return *subnodeoffset;
}
- sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x",
+ sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
phy_dev->phy_id >> 16, phy_dev->phy_id & 0x);
debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
--
1.9.3
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[U-Boot] [PATCH] armv8: lx2160ardb: invert AQR107 pins polarity
AQR107 PHYs interrupt pins are active-low, while the GIC expects a
level-high signal.
Signed-off-by: Florin Chiculita
---
board/freescale/lx2160a/lx2160a.c | 8
include/configs/lx2160ardb.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index b763f6d..fa4520b 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -461,12 +461,20 @@ unsigned long get_board_ddr_clk(void)
int board_init(void)
{
+#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
+ u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
+#endif
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)_environment[0];
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
+ /* invert AQR107 IRQ pins polarity */
+ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
+#endif
+
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h
index 7acd93c..31dd43d 100644
--- a/include/configs/lx2160ardb.h
+++ b/include/configs/lx2160ardb.h
@@ -60,6 +60,7 @@
#define AQR107_PHY_ADDR1 0x04
#define AQR107_PHY_ADDR2 0x05
+#define AQR107_IRQ_MASK0x0C
#define CORTINA_NO_FW_UPLOAD
#define CORTINA_PHY_ADDR1 0x0
--
1.9.3
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