[U-Boot] [PATCH v3 1/1] udoo: Add SATA support on uDoo Board.
Add SATA support on uDoo Board. Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com CC: Stefano Babic sba...@denx.de CC: Fabio Estevam fabio.este...@freescale.com --- Changes in v3: - No changes. Changes in v2: - Split previous patch between nitrogen6x udoo code changes. --- board/udoo/udoo.c |4 include/configs/udoo.h | 12 2 files changed, 16 insertions(+) diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c index 0c38d9b..5b055f7 100644 --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -14,6 +14,7 @@ #include asm/errno.h #include asm/gpio.h #include asm/imx-common/iomux-v3.h +#include asm/imx-common/sata.h #include mmc.h #include fsl_esdhc.h #include asm/arch/crm_regs.h @@ -239,6 +240,9 @@ int board_init(void) /* address of boot parameters */ gd-bd-bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif return 0; } diff --git a/include/configs/udoo.h b/include/configs/udoo.h index b9a493c..a1a1750 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -34,6 +34,18 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE +/* SATA Configs */ + +#define CONFIG_CMD_SATA +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDRSATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + /* Network support */ #define CONFIG_CMD_PING -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 0/1] nitrogen6x: Move setup_sata to common part
Move setup_sata function definition from platform file nitrogen6x.c
to arch/arm/imx-common/sata.c to avoid code duplication.
Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com
CC: Stefano Babic sba...@denx.de
CC: Fabio Estevam fabio.este...@freescale.com
CC: Eric Nelson eric.nel...@boundarydevices.com
---
Changes in v3:
- Correct Makefile for filter sata.c to be compiled only for mx6
soc because in function setup_sata there are i.MX6 specific
registers definition and this breaks mx5 boards. mx5 boards
does not need setup_sata initialization.
Changes in v2:
- Split previous patch between nitrogen6x udoo code changes.
---
arch/arm/imx-common/Makefile |3 +++
arch/arm/imx-common/sata.c | 33
arch/arm/include/asm/imx-common/sata.h | 17
board/boundary/nitrogen6x/nitrogen6x.c | 27 +-
4 files changed, 54 insertions(+), 26 deletions(-)
create mode 100644 arch/arm/imx-common/sata.c
create mode 100644 arch/arm/include/asm/imx-common/sata.h
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 727a052..2656f2d 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -21,6 +21,9 @@ endif
ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
COBJS-y+= misc.o
endif
+ifeq ($(SOC),$(filter $(SOC),mx6))
+COBJS-$(CONFIG_CMD_SATA) += sata.o
+endif
COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
COBJS-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
COBJS := $(sort $(COBJS-y))
diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
new file mode 100644
index 000..1b4c502
--- /dev/null
+++ b/arch/arm/imx-common/sata.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm/imx-common/iomux-v3.h
+#include asm/arch/iomux.h
+#include asm/io.h
+
+int setup_sata(void)
+{
+ struct iomuxc_base_regs *const iomuxc_regs
+ = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+
+ int ret = enable_sata_clock();
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(iomuxc_regs-gpr[13],
+ IOMUXC_GPR13_SATA_MASK,
+ IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+ |IOMUXC_GPR13_SATA_PHY_7_SATA2M
+ |IOMUXC_GPR13_SATA_SPEED_3G
+ |(3IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+ |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+ |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+ |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+ |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+ |IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+ return 0;
+}
diff --git a/arch/arm/include/asm/imx-common/sata.h
b/arch/arm/include/asm/imx-common/sata.h
new file mode 100644
index 000..8bb4493
--- /dev/null
+++ b/arch/arm/include/asm/imx-common/sata.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __IMX_SATA_H_
+#define __IMX_SATA_H_
+
+/*
+ * SATA setup for i.mx6 quad based platform
+ */
+
+int setup_sata(void);
+
+#endif
+
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c
b/board/boundary/nitrogen6x/nitrogen6x.c
index 1712908..0c26bcb 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -17,6 +17,7 @@
#include asm/gpio.h
#include asm/imx-common/iomux-v3.h
#include asm/imx-common/mxc_i2c.h
+#include asm/imx-common/sata.h
#include asm/imx-common/boot_mode.h
#include mmc.h
#include fsl_esdhc.h
@@ -378,32 +379,6 @@ static void setup_buttons(void)
ARRAY_SIZE(button_pads));
}
-#ifdef CONFIG_CMD_SATA
-
-int setup_sata(void)
-{
- struct iomuxc_base_regs *const iomuxc_regs
- = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
- int ret = enable_sata_clock();
- if (ret)
- return ret;
-
- clrsetbits_le32(iomuxc_regs-gpr[13],
- IOMUXC_GPR13_SATA_MASK,
- IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
- |IOMUXC_GPR13_SATA_PHY_7_SATA2M
- |IOMUXC_GPR13_SATA_SPEED_3G
- |(3IOMUXC_GPR13_SATA_PHY_6_SHIFT)
- |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
- |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
- |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
- |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
- |IOMUXC_GPR13_SATA_PHY_1_SLOW);
-
- return 0;
-}
-#endif
-
#if defined(CONFIG_VIDEO_IPUV3)
static iomux_v3_cfg_t const backlight_pads[] = {
--
1.7.10.4
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Re: [U-Boot] [PATCH v2 1/4] udoo: Add ethernet support (FEC + Micrel KSZ9031).
Hi Stefano, On Thu, 2013-11-28 at 09:26 +0100, Stefano Babic wrote: Hi Giuseppe, On 15/11/2013 17:42, Giuseppe Pagano wrote: Add Ethernet and networking support on uDoo board (FEC +phy Micrel KSZ9031). Ethernet speed is currently limited to 10/100Mbps. --- I slightly change the patch to fix names of pins according to last patches to consolidate names between i.MX6 flavour. It's ok. Applied to u-boot-imx, thanks. Thanks. Best regards, Stefano Babic best regards Giuseppe ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 0/1] nitrogen6x: Move setup_sata to common part
Hi Stefano, On Thu, 2013-11-28 at 10:50 +0100, Stefano Babic wrote: Hi Giuseppe, .. endif +ifeq ($(SOC),$(filter $(SOC),mx6)) +COBJS-$(CONFIG_CMD_SATA) += sata.o +endif COBJS- was replaced by obj- Sorry, I was working on -next branch. Do you want me to send v4 patch with changes ? Best regards, Stefano Best regards Giuseppe Pagano ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 0/1] nitrogen6x: Move setup_sata to common part
Move setup_sata function definition from platform file nitrogen6x.c
to arch/arm/imx-common/sata.c to avoid code duplication.
Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com
CC: Stefano Babic sba...@denx.de
CC: Fabio Estevam fabio.este...@freescale.com
CC: Eric Nelson eric.nel...@boundarydevices.com
---
Changes in v4:
- Correct Makefile patch to use: obj- instead of COBJS-.
Changes in v3:
- Correct Makefile for filter sata.c to be compiled only for mx6
soc because in function setup_sata there are i.MX6 specific
registers definition and this breaks mx5 boards. mx5 boards
does not need setup_sata initialization.
Changes in v2:
- Split previous patch between nitrogen6x udoo code changes.
---
arch/arm/imx-common/Makefile |3 +++
arch/arm/imx-common/sata.c | 33
arch/arm/include/asm/imx-common/sata.h | 17
board/boundary/nitrogen6x/nitrogen6x.c | 27 +-
4 files changed, 54 insertions(+), 26 deletions(-)
create mode 100644 arch/arm/imx-common/sata.c
create mode 100644 arch/arm/include/asm/imx-common/sata.h
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 2c80441..68f0f52 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -17,6 +17,9 @@ endif
ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
obj-y += misc.o
endif
+ifeq ($(SOC),$(filter $(SOC),mx6))
+objs-$(CONFIG_CMD_SATA) += sata.o
+endif
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
new file mode 100644
index 000..1b4c502
--- /dev/null
+++ b/arch/arm/imx-common/sata.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm/imx-common/iomux-v3.h
+#include asm/arch/iomux.h
+#include asm/io.h
+
+int setup_sata(void)
+{
+ struct iomuxc_base_regs *const iomuxc_regs
+ = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+
+ int ret = enable_sata_clock();
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(iomuxc_regs-gpr[13],
+ IOMUXC_GPR13_SATA_MASK,
+ IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+ |IOMUXC_GPR13_SATA_PHY_7_SATA2M
+ |IOMUXC_GPR13_SATA_SPEED_3G
+ |(3IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+ |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+ |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+ |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+ |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+ |IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+ return 0;
+}
diff --git a/arch/arm/include/asm/imx-common/sata.h
b/arch/arm/include/asm/imx-common/sata.h
new file mode 100644
index 000..8bb4493
--- /dev/null
+++ b/arch/arm/include/asm/imx-common/sata.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __IMX_SATA_H_
+#define __IMX_SATA_H_
+
+/*
+ * SATA setup for i.mx6 quad based platform
+ */
+
+int setup_sata(void);
+
+#endif
+
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c
b/board/boundary/nitrogen6x/nitrogen6x.c
index 616ad55..3f4cfa1 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -17,6 +17,7 @@
#include asm/gpio.h
#include asm/imx-common/iomux-v3.h
#include asm/imx-common/mxc_i2c.h
+#include asm/imx-common/sata.h
#include asm/imx-common/boot_mode.h
#include mmc.h
#include fsl_esdhc.h
@@ -401,32 +402,6 @@ static void setup_buttons(void)
ARRAY_SIZE(button_pads));
}
-#ifdef CONFIG_CMD_SATA
-
-int setup_sata(void)
-{
- struct iomuxc_base_regs *const iomuxc_regs
- = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
- int ret = enable_sata_clock();
- if (ret)
- return ret;
-
- clrsetbits_le32(iomuxc_regs-gpr[13],
- IOMUXC_GPR13_SATA_MASK,
- IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
- |IOMUXC_GPR13_SATA_PHY_7_SATA2M
- |IOMUXC_GPR13_SATA_SPEED_3G
- |(3IOMUXC_GPR13_SATA_PHY_6_SHIFT)
- |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
- |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
- |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
- |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
- |IOMUXC_GPR13_SATA_PHY_1_SLOW);
-
- return 0;
-}
-#endif
-
#if defined(CONFIG_VIDEO_IPUV3)
static iomux_v3_cfg_t const backlight_pads[] = {
--
1.7.10.4
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[U-Boot] [PATCH v4 1/1] udoo: Add SATA support on uDoo Board.
Add SATA support on uDoo Board. Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com CC: Stefano Babic sba...@denx.de CC: Fabio Estevam fabio.este...@freescale.com --- Changes in v4: - No changes. Changes in v3: - No changes. Changes in v2: - Split previous patch between nitrogen6x udoo code changes. --- board/udoo/udoo.c |4 include/configs/udoo.h | 12 2 files changed, 16 insertions(+) diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c index 081d517..e9236d4 100644 --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -14,6 +14,7 @@ #include asm/errno.h #include asm/gpio.h #include asm/imx-common/iomux-v3.h +#include asm/imx-common/sata.h #include mmc.h #include fsl_esdhc.h #include asm/arch/crm_regs.h @@ -240,6 +241,9 @@ int board_init(void) /* address of boot parameters */ gd-bd-bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif return 0; } diff --git a/include/configs/udoo.h b/include/configs/udoo.h index b9a493c..a1a1750 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -34,6 +34,18 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE +/* SATA Configs */ + +#define CONFIG_CMD_SATA +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDRSATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + /* Network support */ #define CONFIG_CMD_PING -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/4] udoo: Add ethernet support (FEC + Micrel KSZ9031).
On Mon, 2013-11-18 at 18:05 +0100, Giuseppe Pagano wrote: + ksz9031_phy_extended_write(phydev, 0x02, +MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, +MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); I have september 2012 revision of KSZ9031's manual, and I think it is complete enough about skew parameter (preliminary version was not). Default value for GTX_CLK and RX_CLK swek register is 0x001ef (0 ns delay for both). I use maximum positive delay (value 0x03ff) as safe value, but it doesn't work on every board. To be more clear (for people who do not have KSZ9031 manual). GTX and RX skew delay have 5 bit resolution, so MII_KSZ9031_EXT_RGMII_CLOCK_SKEW register have this default value bit: reserved GTX skew RX skew _0001_111-0_ (0x01EF - 0ns delay) _0000_000-0_ (0x - -0.96ns delay both) _0011_111-1_ (0x03FF - +0.96ns delay both) _0011_111-0_ (0x03EF - +0.96ns delay only for GTX) etc. Best regards Giuseppe Pagano ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/4] udoo: Add ethernet support (FEC + Micrel KSZ9031).
Hi Stefano, On Mon, 2013-11-18 at 16:51 +0100, Stefano Babic wrote: Hi Giuseppe, On 15/11/2013 17:42, Giuseppe Pagano wrote: Add Ethernet and networking support on uDoo board (FEC +phy Micrel KSZ9031). Ethernet speed is currently limited to 10/100Mbps. Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com Tested-by: Fabio Estevam fabio.este...@freescale.com CC: Stefano Babic sba...@denx.de CC: Fabio Estevam fabio.este...@freescale.com --- IMHO the patch is ok. If there are not any further comments, I mark your patchset for merging. good! + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); I had also some issues with KSZ9031 and i.MX6. Gigabit starts working only after setting the clock skew. I see you set the register again with the default value (0x3FF). Because it is the reset value, it is not required to set it again, but more important : have you make a trying enabling Gb and adjusting only this extended register ? Rather the KSZ9031's manual is not clear and does not say a lot about it, I have september 2012 revision of KSZ9031's manual, and I think it is complete enough about skew parameter (preliminary version was not). Default value for GTX_CLK and RX_CLK swek register is 0x001ef (0 ns delay for both). I use maximum positive delay (value 0x03ff) as safe value, but it doesn't work on every board. I also tested halfway value and negative delay, but again this value doesn't works on every board I tested. Linux kernel, with the same skew configuration for data and clock, works well with Gigabit ! I've marked as to do to understand why Gigabit works under Linux, and not with u-boot. Best regards, Stefano Babic Best regards Giuseppe Pagano ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 2/4] udoo: Add ethernet support (FEC + Micrel KSZ9031).
Hi Stefano,
On Wed, 2013-11-13 at 10:04 +0100, Stefano Babic wrote:
Hi Giuseppe,
On 11/11/2013 18:11, Giuseppe Pagano wrote:
Add Ethernet and networking support on uDoo board (FEC + phy Micrel
KSZ9031).
Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com
CC: Stefano Babic sba...@denx.de
CC: Fabio Estevam fabio.este...@freescale.com
---
ok - remember to increment the version number of the patchset for next
time (this is really V2 instead of V1).
Ok, I'm going to prepare next patch. Sorry for the error, for this time
I think it would be better to use V2 in next submit to reduce confusion.
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ /*
+* Bug: Apparently uDoo does not works with Gigabit switches...
+* Limiting speed to 10/100Mbps, and setting master mode, seems to
+* be the only way to have a successfull PHY auto negotiation.
+* How to fix: Understand why Linux kernel do not have this issue.
+*/
Fine. This is ok, but could you also add to the commit message that
Ethernet is currently limited to 10/100Mbps ?
Ok, I will do.
Best regards,
Stefano Babic
Best Regards
Giuseppe Pagano
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[U-Boot] [PATCH v2 0/4] udoo: Move and optimize platform register setting.
Previous uDoo configuration adopts register settings for DDR3, clock, muxing, etc. taken from Nitrogen6x. uDoo schematics is rather different from that board, and it needs customized setting for most of the registers. All this changes can be considered atomical since it is part of initial support of the board. Patch changes uDoo configuration files path to a specific one, and adopt optimized value for every configured register. Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com Tested-by: Fabio Estevam fabio.este...@freescale.com CC: Stefano Babic sba...@denx.de CC: Fabio Estevam fabio.este...@freescale.com --- Changes in v2: - Cosmetic changes. board/udoo/1066mhz_4x256mx16.cfg | 55 board/udoo/clocks.cfg| 32 ++ board/udoo/ddr-setup.cfg | 87 ++ board/udoo/udoo.cfg | 29 + boards.cfg |2 +- 5 files changed, 205 insertions(+), 1 deletion(-) create mode 100644 board/udoo/1066mhz_4x256mx16.cfg create mode 100644 board/udoo/clocks.cfg create mode 100644 board/udoo/ddr-setup.cfg create mode 100644 board/udoo/udoo.cfg diff --git a/board/udoo/1066mhz_4x256mx16.cfg b/board/udoo/1066mhz_4x256mx16.cfg new file mode 100644 index 000..539e3f6 --- /dev/null +++ b/board/udoo/1066mhz_4x256mx16.cfg @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 + +DATA 4, MX6_MMDC_P0_MDCFG0, 0x54597955 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB + +DATA 4, MX6_MMDC_P0_MDMISC, 0x1740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x8000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x26D2 + +DATA 4, MX6_MMDC_P0_MDOR, 0x00591023 +DATA 4, MX6_MMDC_P0_MDASP, 0x0027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A + +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x8033 + +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P0_MDREF, 0x5800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x0007 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x0007 + +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43510360 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0342033F +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x033F033F +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03290266 + +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B3E4141 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x47413B4A +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x42404843 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4C3F4C45 + +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00350035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00010001 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00010001 + +DATA 4, MX6_MMDC_P0_MPMUR0, 0x0800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x0800 + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x + diff --git a/board/udoo/clocks.cfg b/board/udoo/clocks.cfg new file mode 100644 index 000..9cd1af1 --- /dev/null +++ b/board/udoo/clocks.cfg @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier:GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type AddressValue + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF0 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0FC3 +DATA 4, CCM_CCGR6, 0x03FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF0FF + +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + diff --git a/board/udoo/ddr-setup.cfg b/board/udoo/ddr-setup.cfg new file mode 100644 index 000..78cbe17 --- /dev/null +++ b/board/udoo/ddr-setup.cfg @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier:GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type AddressValue + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * DDR3 settings + * MX6Qddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), + *memory bus width: 64 bitsx16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + *memory bus width: 64 bitsx16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz
[U-Boot] [PATCH v2 2/4] nitrogen6x: Move setup_sata to common part
Move setup_sata function definition from platform file nitrogen6x.c
to arch/arm/imx-common/sata.c to avoid code duplication.
Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com
CC: Stefano Babic sba...@denx.de
CC: Fabio Estevam fabio.este...@freescale.com
CC: Eric Nelson eric.nel...@boundarydevices.com
---
Changes in v2:
- Split previous patch between nitrogen6x udoo code changes.
arch/arm/imx-common/Makefile |1 +
arch/arm/imx-common/sata.c | 33
arch/arm/include/asm/imx-common/sata.h | 17
board/boundary/nitrogen6x/nitrogen6x.c | 27 +-
4 files changed, 52 insertions(+), 26 deletions(-)
create mode 100644 arch/arm/imx-common/sata.c
create mode 100644 arch/arm/include/asm/imx-common/sata.h
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 727a052..6f85c42 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -17,6 +17,7 @@ endif
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
COBJS-y+= timer.o cpu.o speed.o
COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
+COBJS-$(CONFIG_CMD_SATA) += sata.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
COBJS-y+= misc.o
diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
new file mode 100644
index 000..08e4b2d
--- /dev/null
+++ b/arch/arm/imx-common/sata.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm/imx-common/iomux-v3.h
+#include asm/arch/iomux.h
+#include asm/io.h
+
+int setup_sata(void)
+{
+ struct iomuxc_base_regs *const iomuxc_regs
+ = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+
+ int ret = enable_sata_clock();
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(iomuxc_regs-gpr[13],
+ IOMUXC_GPR13_SATA_MASK,
+ IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+ |IOMUXC_GPR13_SATA_PHY_7_SATA2M
+ |IOMUXC_GPR13_SATA_SPEED_3G
+ |(3IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+ |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+ |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+ |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+ |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+ |IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+ return 0;
+}
diff --git a/arch/arm/include/asm/imx-common/sata.h
b/arch/arm/include/asm/imx-common/sata.h
new file mode 100644
index 000..40fbf77
--- /dev/null
+++ b/arch/arm/include/asm/imx-common/sata.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __IMX_SATA_H_
+#define __IMX_SATA_H_
+
+/*
+ * SATA setup for i.mx6 quad based platform
+ */
+
+int setup_sata(void);
+
+#endif
+
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c
b/board/boundary/nitrogen6x/nitrogen6x.c
index 1712908..0c26bcb 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -17,6 +17,7 @@
#include asm/gpio.h
#include asm/imx-common/iomux-v3.h
#include asm/imx-common/mxc_i2c.h
+#include asm/imx-common/sata.h
#include asm/imx-common/boot_mode.h
#include mmc.h
#include fsl_esdhc.h
@@ -378,32 +379,6 @@ static void setup_buttons(void)
ARRAY_SIZE(button_pads));
}
-#ifdef CONFIG_CMD_SATA
-
-int setup_sata(void)
-{
- struct iomuxc_base_regs *const iomuxc_regs
- = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
- int ret = enable_sata_clock();
- if (ret)
- return ret;
-
- clrsetbits_le32(iomuxc_regs-gpr[13],
- IOMUXC_GPR13_SATA_MASK,
- IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
- |IOMUXC_GPR13_SATA_PHY_7_SATA2M
- |IOMUXC_GPR13_SATA_SPEED_3G
- |(3IOMUXC_GPR13_SATA_PHY_6_SHIFT)
- |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
- |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
- |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
- |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
- |IOMUXC_GPR13_SATA_PHY_1_SLOW);
-
- return 0;
-}
-#endif
-
#if defined(CONFIG_VIDEO_IPUV3)
static iomux_v3_cfg_t const backlight_pads[] = {
--
1.7.10.4
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[U-Boot] [PATCH v2 1/4] udoo: Add ethernet support (FEC + Micrel KSZ9031).
Add Ethernet and networking support on uDoo board (FEC +phy Micrel KSZ9031).
Ethernet speed is currently limited to 10/100Mbps.
Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com
Tested-by: Fabio Estevam fabio.este...@freescale.com
CC: Stefano Babic sba...@denx.de
CC: Fabio Estevam fabio.este...@freescale.com
---
Changes in v2:
- Improve description and comment.
- uDoo does not works well with Gigabit switches, as workaround speed
will be limited to 10/100Mbps.
- use defines instead of hard coded values for KSZ9031 register address.
board/udoo/udoo.c | 140
include/configs/udoo.h | 16 ++
include/micrel.h |5 ++
3 files changed, 161 insertions(+)
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
index e9d6375..0c38d9b 100644
--- a/board/udoo/udoo.c
+++ b/board/udoo/udoo.c
@@ -9,6 +9,7 @@
#include asm/arch/clock.h
#include asm/arch/imx-regs.h
#include asm/arch/iomux.h
+#include malloc.h
#include asm/arch/mx6-pins.h
#include asm/errno.h
#include asm/gpio.h
@@ -18,6 +19,9 @@
#include asm/arch/crm_regs.h
#include asm/io.h
#include asm/arch/sys_proto.h
+#include micrel.h
+#include miiphy.h
+#include netdev.h
DECLARE_GLOBAL_DATA_PTR;
@@ -25,6 +29,9 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
@@ -58,6 +65,99 @@ static iomux_v3_cfg_t const wdog_pads[] = {
MX6_PAD_EIM_D19__GPIO_3_19,
};
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ /*
+* Bug: Apparently uDoo does not works with Gigabit switches...
+* Limiting speed to 10/100Mbps, and setting master mode, seems to
+* be the only way to have a successfull PHY auto negotiation.
+* How to fix: Understand why Linux kernel do not have this issue.
+*/
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
+
+ /* control data pad skew - devaddr = 0x02, register = 0x04 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x);
+ /* rx data pad skew - devaddr = 0x02, register = 0x05 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x);
+ /* tx data pad skew - devaddr = 0x02, register = 0x05 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x);
+ /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
+ return 0;
+}
+
+static iomux_v3_cfg_t const enet_pads1[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO| MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* RGMII reset */
+ MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* Ethernet power supply */
+ MX6_PAD_EIM_EB3__GPIO_2_31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 32 - 1 - (MODE0) all */
+ MX6_PAD_RGMII_RD0__GPIO_6_25| MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 31 - 1 - (MODE1) all */
+ MX6_PAD_RGMII_RD1__GPIO_6_27| MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 28 - 1 - (MODE2) all */
+ MX6_PAD_RGMII_RD2__GPIO_6_28| MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 27 - 1 - (MODE3) all */
+ MX6_PAD_RGMII_RD3__GPIO_6_29| MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+ MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL
[U-Boot] [PATCH v2 3/4] udoo: Add SATA support on uDoo Board.
Add SATA support on uDoo Board. Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com CC: Stefano Babic sba...@denx.de CC: Fabio Estevam fabio.este...@freescale.com --- Changes in v2: - Split previous patch between nitrogen6x udoo code changes. board/udoo/udoo.c |4 include/configs/udoo.h | 12 2 files changed, 16 insertions(+) diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c index 0c38d9b..64cb8d4 100644 --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -14,6 +14,7 @@ #include asm/errno.h #include asm/gpio.h #include asm/imx-common/iomux-v3.h +#include asm/imx-common/sata.h #include mmc.h #include fsl_esdhc.h #include asm/arch/crm_regs.h @@ -239,6 +240,9 @@ int board_init(void) /* address of boot parameters */ gd-bd-bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif return 0; } diff --git a/include/configs/udoo.h b/include/configs/udoo.h index b9a493c..a1a1750 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -34,6 +34,18 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE +/* SATA Configs */ + +#define CONFIG_CMD_SATA +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDRSATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + /* Network support */ #define CONFIG_CMD_PING -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 4/4] udoo: Fix watchdog during kernel boot.
uDoo uses APX823-31W5 watchdog chip. Timeout is about 1.2 seconds.
To disabled watchdog during kernel boot, WDI pin of that chip needs to be
in high impedance state. I.mx6 gpio configuration does not contemplate
tristate, so pin is set as input in high impedance.
Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com
Reviewed-by: Fabio Estevam fabio.este...@freescale.com
CC: Stefano Babic sba...@denx.de
CC: Fabio Estevam fabio.este...@freescale.com
---
Changes in v2:
- None
board/udoo/udoo.c |1 +
1 file changed, 1 insertion(+)
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
index 64cb8d4..8ac9072 100644
--- a/board/udoo/udoo.c
+++ b/board/udoo/udoo.c
@@ -169,6 +169,7 @@ static void setup_iomux_wdog(void)
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
gpio_direction_output(WDT_TRG, 0);
gpio_direction_output(WDT_EN, 1);
+ gpio_direction_input(WDT_TRG);
}
static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
--
1.7.10.4
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Re: [U-Boot] [PATCH v1 3/4] udoo: Add SATA support on uDoo Board.
Hi Ottavio, On Mon, 2013-11-11 at 16:00 -0200, Otavio Salvador wrote: Hello Giuseppe, On Mon, Nov 11, 2013 at 3:11 PM, Giuseppe Pagano giuseppe.pag...@seco.com wrote: Adds SATA support on uDoo Board. Moves sata_setup function definition from nitrogen6x.c and udoo.c to arch/arm/imx-common/sata.c to avoid code duplication. Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com Your patches should have the long description split in 80 cols; please do the nitrogen code move in a separated patch so it is clear what you did to include support for uDoo board. Ok I will split. Thanks Giuseppe ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 2/4] udoo: Add ethernet support (FEC + Micrel KSZ9031).
Hi Fabio, On Tue, 2013-11-12 at 13:00 -0200, Fabio Estevam wrote: + /* alimentazione ethernet*/ Actually this is pin is Ethernet PHY reset, so the comment in Italian is not correct :-) Sorry, I looked at the wrong line. Anyway, please change the comment to Ethernet power supply. Sure, I'll do in the next v2 version. Thanks, Fabio Estevam Bye Giuseppe ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 1/4] udoo: Move and optimize platform register setting.
Previous uDoo configuration adopts register settings for DDR3, clock, muxing, etc. taken from Nitrogen6x. uDoo schematics is rather different from that board, and it needs customized setting for most of the registers. All this changes can be considered atomical since it is part of initial support of the board. Patch changes uDoo configuration files path to a specific one, and adopt optimized value for every configured register. Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com CC: Stefano Babic sba...@denx.de CC: Fabio Estevam fabio.este...@freescale.com --- board/udoo/1066mhz_4x256mx16.cfg | 56 board/udoo/clocks.cfg| 32 ++ board/udoo/ddr-setup.cfg | 87 ++ board/udoo/udoo.cfg | 29 + boards.cfg |2 +- 5 files changed, 205 insertions(+), 1 deletion(-) create mode 100644 board/udoo/1066mhz_4x256mx16.cfg create mode 100644 board/udoo/clocks.cfg create mode 100644 board/udoo/ddr-setup.cfg create mode 100644 board/udoo/udoo.cfg diff --git a/board/udoo/1066mhz_4x256mx16.cfg b/board/udoo/1066mhz_4x256mx16.cfg new file mode 100644 index 000..539e3f6 --- /dev/null +++ b/board/udoo/1066mhz_4x256mx16.cfg @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier:GPL-2.0+ + */ + + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 + +DATA 4, MX6_MMDC_P0_MDCFG0, 0x54597955 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB + +DATA 4, MX6_MMDC_P0_MDMISC, 0x1740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x8000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x26D2 + +DATA 4, MX6_MMDC_P0_MDOR, 0x00591023 +DATA 4, MX6_MMDC_P0_MDASP, 0x0027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A + +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x8033 + +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P0_MDREF, 0x5800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x0007 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x0007 + +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43510360 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0342033F +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x033F033F +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03290266 + +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B3E4141 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x47413B4A +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x42404843 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4C3F4C45 + +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00350035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00010001 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00010001 + +DATA 4, MX6_MMDC_P0_MPMUR0, 0x0800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x0800 + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x + diff --git a/board/udoo/clocks.cfg b/board/udoo/clocks.cfg new file mode 100644 index 000..9cd1af1 --- /dev/null +++ b/board/udoo/clocks.cfg @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier:GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type AddressValue + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF0 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0FC3 +DATA 4, CCM_CCGR6, 0x03FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF0FF + +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + diff --git a/board/udoo/ddr-setup.cfg b/board/udoo/ddr-setup.cfg new file mode 100644 index 000..78cbe17 --- /dev/null +++ b/board/udoo/ddr-setup.cfg @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier:GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type AddressValue + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * DDR3 settings + * MX6Qddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), + *memory bus width: 64 bitsx16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + *memory bus width: 64 bitsx16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) + *memory bus width: 32 bitsx16/x32 + */ +DATA 4
[U-Boot] [PATCH v1 2/4] udoo: Add ethernet support (FEC + Micrel KSZ9031).
Add Ethernet and networking support on uDoo board (FEC + phy Micrel KSZ9031).
Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com
CC: Stefano Babic sba...@denx.de
CC: Fabio Estevam fabio.este...@freescale.com
---
board/udoo/udoo.c | 140
include/configs/udoo.h | 16 ++
include/micrel.h |5 ++
3 files changed, 161 insertions(+)
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
index e9d6375..ca49ebb 100644
--- a/board/udoo/udoo.c
+++ b/board/udoo/udoo.c
@@ -9,6 +9,7 @@
#include asm/arch/clock.h
#include asm/arch/imx-regs.h
#include asm/arch/iomux.h
+#include malloc.h
#include asm/arch/mx6-pins.h
#include asm/errno.h
#include asm/gpio.h
@@ -18,6 +19,9 @@
#include asm/arch/crm_regs.h
#include asm/io.h
#include asm/arch/sys_proto.h
+#include micrel.h
+#include miiphy.h
+#include netdev.h
DECLARE_GLOBAL_DATA_PTR;
@@ -25,6 +29,9 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
@@ -58,6 +65,99 @@ static iomux_v3_cfg_t const wdog_pads[] = {
MX6_PAD_EIM_D19__GPIO_3_19,
};
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ /*
+* Bug: Apparently uDoo does not works with Gigabit switches...
+* Limiting speed to 10/100Mbps, and setting master mode, seems to
+* be the only way to have a successfull PHY auto negotiation.
+* How to fix: Understand why Linux kernel do not have this issue.
+*/
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
+
+ /* control data pad skew - devaddr = 0x02, register = 0x04 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x);
+ /* rx data pad skew - devaddr = 0x02, register = 0x05 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x);
+ /* tx data pad skew - devaddr = 0x02, register = 0x05 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x);
+ /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
+ return 0;
+}
+
+static iomux_v3_cfg_t const enet_pads1[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO| MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* RGMII reset */
+ MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* alimentazione ethernet*/
+ MX6_PAD_EIM_EB3__GPIO_2_31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 32 - 1 - (MODE0) all */
+ MX6_PAD_RGMII_RD0__GPIO_6_25| MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 31 - 1 - (MODE1) all */
+ MX6_PAD_RGMII_RD1__GPIO_6_27| MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 28 - 1 - (MODE2) all */
+ MX6_PAD_RGMII_RD2__GPIO_6_28| MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 27 - 1 - (MODE3) all */
+ MX6_PAD_RGMII_RD3__GPIO_6_29| MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+ MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const enet_pads2[] = {
+ MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__ENET_RGMII_RD3
[U-Boot] [PATCH,v1,4/4] udoo: Fix watchdog during kernel boot.
uDoo uses APX823-31W5 watchdog chip. Timeout is about 1.2 seconds.
To disabled watchdog during kernel boot, WDI pin of that chip needs to be in
high impedance state.
I.mx6 gpio configuration does not contemplate tristate, so pin is set as input
in high impedance.
Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com
CC: Stefano Babic sba...@denx.de
CC: Fabio Estevam fabio.este...@freescale.com
---
board/udoo/udoo.c |1 +
1 file changed, 1 insertion(+)
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
index b53f70c..af8004e 100644
--- a/board/udoo/udoo.c
+++ b/board/udoo/udoo.c
@@ -169,6 +169,7 @@ static void setup_iomux_wdog(void)
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
gpio_direction_output(WDT_TRG, 0);
gpio_direction_output(WDT_EN, 1);
+ gpio_direction_input(WDT_TRG);
}
static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
--
1.7.10.4
___
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[U-Boot] [PATCH v1 3/4] udoo: Add SATA support on uDoo Board.
Adds SATA support on uDoo Board.
Moves sata_setup function definition from nitrogen6x.c and udoo.c to
arch/arm/imx-common/sata.c to avoid code duplication.
Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com
CC: Stefano Babic sba...@denx.de
CC: Fabio Estevam fabio.este...@freescale.com
CC: Eric Nelson eric.nel...@boundarydevices.com
---
arch/arm/imx-common/Makefile |1 +
arch/arm/imx-common/sata.c | 33
arch/arm/include/asm/imx-common/sata.h | 17
board/boundary/nitrogen6x/nitrogen6x.c | 27 +-
board/udoo/udoo.c |4
include/configs/udoo.h | 12
6 files changed, 68 insertions(+), 26 deletions(-)
create mode 100644 arch/arm/imx-common/sata.c
create mode 100644 arch/arm/include/asm/imx-common/sata.h
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 727a052..6f85c42 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -17,6 +17,7 @@ endif
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
COBJS-y+= timer.o cpu.o speed.o
COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
+COBJS-$(CONFIG_CMD_SATA) += sata.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
COBJS-y+= misc.o
diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
new file mode 100644
index 000..00b3d92
--- /dev/null
+++ b/arch/arm/imx-common/sata.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm/imx-common/iomux-v3.h
+#include asm/arch/iomux.h
+#include asm/io.h
+
+int sata_setup(void)
+{
+ struct iomuxc_base_regs *const iomuxc_regs
+ = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+
+ int ret = enable_sata_clock();
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(iomuxc_regs-gpr[13],
+ IOMUXC_GPR13_SATA_MASK,
+ IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+ |IOMUXC_GPR13_SATA_PHY_7_SATA2M
+ |IOMUXC_GPR13_SATA_SPEED_3G
+ |(3IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+ |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+ |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+ |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+ |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+ |IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+ return 0;
+}
diff --git a/arch/arm/include/asm/imx-common/sata.h
b/arch/arm/include/asm/imx-common/sata.h
new file mode 100644
index 000..40fbf77
--- /dev/null
+++ b/arch/arm/include/asm/imx-common/sata.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __IMX_SATA_H_
+#define __IMX_SATA_H_
+
+/*
+ * SATA setup for i.mx6 quad based platform
+ */
+
+int sata_setup(void);
+
+#endif
+
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c
b/board/boundary/nitrogen6x/nitrogen6x.c
index 1712908..0c26bcb 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -17,6 +17,7 @@
#include asm/gpio.h
#include asm/imx-common/iomux-v3.h
#include asm/imx-common/mxc_i2c.h
+#include asm/imx-common/sata.h
#include asm/imx-common/boot_mode.h
#include mmc.h
#include fsl_esdhc.h
@@ -378,32 +379,6 @@ static void setup_buttons(void)
ARRAY_SIZE(button_pads));
}
-#ifdef CONFIG_CMD_SATA
-
-int setup_sata(void)
-{
- struct iomuxc_base_regs *const iomuxc_regs
- = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
- int ret = enable_sata_clock();
- if (ret)
- return ret;
-
- clrsetbits_le32(iomuxc_regs-gpr[13],
- IOMUXC_GPR13_SATA_MASK,
- IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
- |IOMUXC_GPR13_SATA_PHY_7_SATA2M
- |IOMUXC_GPR13_SATA_SPEED_3G
- |(3IOMUXC_GPR13_SATA_PHY_6_SHIFT)
- |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
- |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
- |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
- |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
- |IOMUXC_GPR13_SATA_PHY_1_SLOW);
-
- return 0;
-}
-#endif
-
#if defined(CONFIG_VIDEO_IPUV3)
static iomux_v3_cfg_t const backlight_pads[] = {
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
index ca49ebb..b53f70c 100644
--- a/board/udoo/udoo.c
+++ b/board/udoo/udoo.c
@@ -14,6 +14,7 @@
#include asm/errno.h
#include asm/gpio.h
#include asm/imx-common/iomux-v3.h
+#include asm/imx-common/sata.h
#include mmc.h
#include fsl_esdhc.h
#include asm/arch/crm_regs.h
@@ -239,6 +240,9 @@ int board_init(void)
/* address of boot parameters */
gd-bd
Re: [U-Boot] [PATCH 0/4] udoo: Improve stability of DDR3 setting
Hi Stefano, On Thu, 2013-11-07 at 09:12 +0100, Stefano Babic wrote: Hi Giuseppe, On 06/11/2013 21:30, Giuseppe Pagano wrote: Move udoo configuration files to board/udoo/ folder. Align clock configuration and DDR3 calibration to Seco suggested value to increase system stability. There are some basic issues with your patchset. First, patches are corrupted by your editor and/or by your mailer and cannot be applied. . Instead of generating the patches with diff, use git format-patch, and then submit the patches to the mailing list with git send-email. Sorry, I used vim and imported patch as a file in evolution, I understood too late that I also need to change Format from normal to preformatted. In the future I will use git send-email. Please take a look at the rules to submit patches : http://www.denx.de/wiki/U-Boot/Patches Sure, I read it, nevertheless I made lots of errors. This was my first submit..sorry Do not fix multiple issues in the same patch if not strictly needed. The commit message is misleading: you say you are moving the configuration files, but they are not moved (they can't because they belong to nitrogen) and new files are generated. Maybe I was wrong in writing move configuration files.. I think [PATCH 0/4] can be consider an atomical change: Fabio first uDoo support adopt nitrogenx register setting for DDR3, clock, muxing, etc uDoo schematics is rather different from nitrogen6x, and it needs customized setting for most of the register (as every platform). It takes too long describe every single new setting. Previous configuration was very unstable and adopting those settings uDoo board has frequently crash. Seco had validated new setting I'm going to propose using climatic room and various tests, which stressed system and cpu for about 7 days long cycles. I do not understand what you mean with Align clock configuration and DDR3 calibration to Seco suggested value. Please explain: which values are wrong, what you have fix with your patch. See above. If you make change to a board, you should send your patches in CC to the board maintainer, too (for udoo, Fabio: I put him in CC). Fabio was abreast of this changes, but not in cc. I'll use CC in next post. Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com Cc: sba...@denx.de ... Best regards, Stefano Babic Best Regards, Giuseppe Pagano ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] udoo: fix watchdog setting
Hi Stefano, On Thu, 2013-11-07 at 09:19 +0100, Stefano Babic wrote: Hi Giuseppe, On 06/11/2013 21:44, Giuseppe Pagano wrote: To have watchdog quiet during kernel boot it is necessary to change gpio wdt trigger direction. Sorry, this is not a good explanation. You force a GPIO to drop a feture, instead of disabling the feature itself. And maybe some other people want to have this feature enabled. Which is the timeout for the watchdog ? Why is it hitting too soon ? Fix should be not done simply removing the effect, but checking the cause. I know, my explanation was poor. uDoo use APX823-31W5 as watchdog chip. Timeout is about 1.2 seconds. To disabled watchdog during kernel boot, WDI pin of that chip needs to be in high impedance state. As far as I known mx6 gpio configuration does not contemplate tristate, so the option I choose is to set pin as input and in high impedance. If wdt gpio is leaved as output che chip resets. Best regards, Stefano Babic Best regards, Giuseppe Pagano ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] udoo: Adjust default boot envirnment
Hi Stefano, On Thu, 2013-11-07 at 09:33 +0100, Stefano Babic wrote: Hi Giuseppe, On 06/11/2013 21:44, Giuseppe Pagano wrote: Change u-boot default environment for uDoo board to: - mount /dev/mmcblk0p1 partition - activate hdmi monitor by default (instead of nothing) Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com Cc: sba...@denx.de I have already explained my doubts regarding the abuse of EXTRA_ENV_SETTINGS. The setup that should be minimal and general for most of uses is then customized for a specific scope, that conflict with other goals. Ok I will leave unchanged default environment. @@ -189,7 +190,7 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP #define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT = +#define CONFIG_SYS_PROMPT uDoo board #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 We had already some discussion on the mailing list about the meaning and the usefulness of the U-Boot prompt. I will apply a patch for all Freescale boards that remove a custom prompt, letting the default. Which is the improvement to have a custom prompt ? And also I will leave unchanged u-boot prompt. I think I will support Simon idea, I think it is useful to recognize uboot console prompt if you have more than one serial console connected to your host. Maybe you are the second one asking for the feature: http://u-boot.10912.n7.nabble.com/Changing-CONFIG-SYS-PROMPT-on-the-fly-td166105.html As suggested by Simon (take a look at the whole thread), it is then better to set the prompt from an environment variable. Feel free to submit a patch for it. Best regards, Stefano Babic Best regards, Giuseppe Pagano ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] udoo: Add Ethernet support.
Hi Stefano,
On Thu, 2013-11-07 at 09:38 +0100, Stefano Babic wrote:
Hi Giuseppe,
On 06/11/2013 21:33, Giuseppe Pagano wrote:
Add Ethernet and networking support on uDoo board (FEC + phy Micrel)
Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com
Cc: sba...@denx.de
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ /* To advertise only 10 Mbs */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x4, 0x61);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x9, 0x0c00);
+
Why only 10 Mb/s ? I think the Micrel 9031 allows 1Gb/s.
I will check again, I remember this solves an issue present also in
sabrelite board; but not sure. Maybe we can remove.
Generally, use defines instead of hard coded values.
Ok
+ /* min rx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
Is is 9021 or 9031 ?
uDoo adopt a Micrel KSZ9031 phy.
Most of the register address are common to ksz9021 and ksz9031, and have
the same value. Maybe we should rename some variable to MII_KSZ90XX_...
+
+ gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY rst */
SABRE as comment is maybe wrong
+#define CONFIG_PHY_MICREL_KSZ9021
Ok, it is 9021 - please be consistent with the comments avoiding mixing
9031 and 9021.
No, it is 9031. I will create a new define.
Best regards,
Stefano Babic
Best regards,
Giuseppe Pagano
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Re: [U-Boot] [PATCH 2/4] udoo: Add SATA disk support.
On Thu, 2013-11-07 at 09:40 +0100, Stefano Babic wrote:
Hi Giuseppe,
On 06/11/2013 21:37, Giuseppe Pagano wrote:
Add Sata support on uDoo Board.
Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com
Cc: sba...@denx.de
---
+#ifdef CONFIG_CMD_SATA
+int setup_sata(void)
+{
+ struct iomuxc_base_regs *const iomuxc_regs
+ = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+
+ int ret = enable_sata_clock();
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(iomuxc_regs-gpr[13],
+ IOMUXC_GPR13_SATA_MASK,
+ IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+ |IOMUXC_GPR13_SATA_PHY_7_SATA2M
+ |IOMUXC_GPR13_SATA_SPEED_3G
+ |(3IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+ |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+ |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+ |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+ |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+ |IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+ return 0;
+}
+#endif
Do not copy code ! If you want to reuse functions from nitrogen, please
factorize the function and put it into imx-common, thanks.
Ok, I'll do.
I'm going to produce a new udoo patch with git send-patch and I'll
submit as v2 of this one.
Best regards,
Stefano Babic
Best regards,
Giuseppe Pagano
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[U-Boot] [PATCH 0/4] udoo: Improve stability of DDR3 setting
Move udoo configuration files to board/udoo/ folder. Align clock configuration and DDR3 calibration to Seco suggested value to increase system stability. Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com Cc: sba...@denx.de ... diff -uNr a/board/udoo/1066mhz_4x256mx16.cfg b/board/udoo/1066mhz_4x256mx16.cfg --- a/board/udoo/1066mhz_4x256mx16.cfg +++ b/board/udoo/1066mhz_4x256mx16.cfg @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier:GPL-2.0+ + */ + + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 + +DATA 4, MX6_MMDC_P0_MDCFG0, 0x54597955 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB + +DATA 4, MX6_MMDC_P0_MDMISC, 0x1740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x8000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x26D2 + +DATA 4, MX6_MMDC_P0_MDOR, 0x00591023 +DATA 4, MX6_MMDC_P0_MDASP, 0x0027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A + +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x8033 + +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P0_MDREF, 0x5800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x0007 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x0007 + +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43510360 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0342033F +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x033F033F +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03290266 + +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B3E4141 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x47413B4A +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x42404843 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4C3F4C45 + +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00350035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00010001 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00010001 + +DATA 4, MX6_MMDC_P0_MPMUR0, 0x0800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x0800 + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x + diff -uNr a/board/udoo/clocks.cfg b/board/udoo/clocks.cfg --- a/board/udoo/clocks.cfg +++ b/board/udoo/clocks.cfg @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier:GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type AddressValue + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF0 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0FC3 +DATA 4, CCM_CCGR6, 0x03FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF0FF + +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + diff -uNr a/board/udoo/ddr-setup.cfg b/board/udoo/ddr-setup.cfg --- a/board/udoo/ddr-setup.cfg +++ b/board/udoo/ddr-setup.cfg @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier:GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type AddressValue + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * DDR3 settings + * MX6Qddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), + *memory bus width: 64 bitsx16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + *memory bus width: 64 bitsx16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) + *memory bus width: 32 bitsx16/x32 + */ +DATA 4, MX6_IOM_DRAM_SDQS0, 0x0030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x0030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x0030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x0030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x0030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x0030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x0030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x0030 + +DATA 4, MX6_IOM_GRP_B0DS, 0x0030 +DATA 4, MX6_IOM_GRP_B1DS, 0x0030 +DATA 4, MX6_IOM_GRP_B2DS, 0x0030 +DATA 4, MX6_IOM_GRP_B3DS, 0x0030 +DATA 4, MX6_IOM_GRP_B4DS, 0x0030 +DATA 4, MX6_IOM_GRP_B5DS, 0x0030 +DATA 4, MX6_IOM_GRP_B6DS, 0x0030 +DATA 4, MX6_IOM_GRP_B7DS, 0x0030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x0030 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_CTLDS, 0x0030 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 +DATA 4
[U-Boot] [PATCH 1/4] udoo: Add Ethernet support.
Add Ethernet and networking support on uDoo board (FEC + phy Micrel)
Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com
Cc: sba...@denx.de
---
diff -uNr a/board/udoo/udoo.c b/board/udoo/udoo.c
--- a/board/udoo/udoo.c
+++ b/board/udoo/udoo.c
@@ -9,6 +9,7 @@
#include asm/arch/clock.h
#include asm/arch/imx-regs.h
#include asm/arch/iomux.h
+#include malloc.h
#include asm/arch/mx6-pins.h
#include asm/errno.h
#include asm/gpio.h
@@ -18,6 +19,9 @@
#include asm/arch/crm_regs.h
#include asm/io.h
#include asm/arch/sys_proto.h
+#include micrel.h
+#include miiphy.h
+#include netdev.h
DECLARE_GLOBAL_DATA_PTR;
@@ -25,6 +29,9 @@
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
@@ -58,6 +65,99 @@
MX6_PAD_EIM_D19__GPIO_3_19,
};
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ /* To advertise only 10 Mbs */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x4, 0x61);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x9, 0x0c00);
+
+ /* enable master mode, force phy to 100Mbps */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x9, 0x1c00);
+
+ /* min rx data delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x0b, 0x8105);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x0c, 0x);
+
+ /* max rx/tx clock delay, min rx/tx control delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x0b, 0x8104);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x0c, 0xf0f0);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x0b, 0x104);
+
+ /* min rx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
+ /* min tx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
+ /* max rx/tx clock delay, min rx/tx control */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0x03FF);
+ return 0;
+}
+
+static iomux_v3_cfg_t const enet_pads1[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO| MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* RGMII reset */
+ MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* alimentazione ethernet*/
+ MX6_PAD_EIM_EB3__GPIO_2_31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 32 - 1 - (MODE0) all */
+ MX6_PAD_RGMII_RD0__GPIO_6_25| MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 31 - 1 - (MODE1) all */
+ MX6_PAD_RGMII_RD1__GPIO_6_27| MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 28 - 1 - (MODE2) all */
+ MX6_PAD_RGMII_RD2__GPIO_6_28| MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 27 - 1 - (MODE3) all */
+ MX6_PAD_RGMII_RD3__GPIO_6_29| MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+ MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const enet_pads2[] = {
+ MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+ udelay(20);
+ gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power on of enet */
+
+ gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
+
+ gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 29
[U-Boot] [PATCH 4/4] udoo: fix watchdog setting
To have watchdog quiet during kernel boot it is necessary to
change gpio wdt trigger direction.
Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com
Cc: sba...@denx.de
---
diff -uNr a/board/udoo/udoo.c b/board/udoo/udoo.c
--- a/board/udoo/udoo.c 2013-11-06 18:47:26.0 +0100
+++ b/board/udoo/udoo.c 2013-11-06 18:54:46.0 +0100
@@ -168,6 +168,7 @@
imx_iomux_v3_setup_multiple_pads(wdog_pads,
ARRAY_SIZE(wdog_pads));
gpio_direction_output(WDT_TRG, 0);
gpio_direction_output(WDT_EN, 1);
+ gpio_direction_input(WDT_TRG);
}
static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
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[U-Boot] [PATCH 2/4] udoo: Add SATA disk support.
Add Sata support on uDoo Board.
Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com
Cc: sba...@denx.de
---
diff -uNr a/board/udoo/udoo.c b/board/udoo/udoo.c
--- a/board/udoo/udoo.c 2013-11-06 18:45:22.0 +0100
+++ b/board/udoo/udoo.c 2013-11-06 18:46:00.0 +0100
@@ -208,6 +208,32 @@
return 0;
}
+#ifdef CONFIG_CMD_SATA
+int setup_sata(void)
+{
+ struct iomuxc_base_regs *const iomuxc_regs
+ = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+
+ int ret = enable_sata_clock();
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(iomuxc_regs-gpr[13],
+ IOMUXC_GPR13_SATA_MASK,
+ IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+ |IOMUXC_GPR13_SATA_PHY_7_SATA2M
+ |IOMUXC_GPR13_SATA_SPEED_3G
+ |(3IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+ |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+ |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+ |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+ |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+ |IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+ return 0;
+}
+#endif
+
int board_mmc_init(bd_t *bis)
{
imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
ARRAY_SIZE(usdhc3_pads));
@@ -239,6 +265,9 @@
/* address of boot parameters */
gd-bd-bi_boot_params = PHYS_SDRAM + 0x100;
+#ifdef CONFIG_CMD_SATA
+ setup_sata();
+#endif
return 0;
}
diff -uNr a/include/configs/udoo.h b/include/configs/udoo.h
--- a/include/configs/udoo.h2013-11-06 18:45:22.0 +0100
+++ b/include/configs/udoo.h2013-11-06 18:46:27.0 +0100
@@ -34,6 +34,19 @@
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART2_BASE
+#define CONFIG_CMD_SATA
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_DWC_AHSATA_PORT_ID 0
+#define CONFIG_DWC_AHSATA_BASE_ADDRSATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
/* Network support */
#define CONFIG_CMD_PING
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[U-Boot] [PATCH 3/4] udoo: Adjust default boot envirnment
Change u-boot default environment for uDoo board to:
- mount /dev/mmcblk0p1 partition
- activate hdmi monitor by default (instead of nothing)
Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com
Cc: sba...@denx.de
---
diff -uNr a/include/configs/udoo.h b/include/configs/udoo.h
--- a/include/configs/udoo.h2013-11-06 18:51:57.0 +0100
+++ b/include/configs/udoo.h2013-11-06 18:52:16.0 +0100
@@ -100,7 +100,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
script=boot.scr\0 \
- uimage=uImage\0 \
+ uimage=/boot/uImage\0 \
console=ttymxc1\0 \
splashpos=m,m\0 \
fdt_high=0x\0 \
@@ -111,7 +111,7 @@
ip_dyn=yes\0 \
mmcdev=0\0 \
mmcpart=1\0 \
- mmcroot=/dev/mmcblk0p2 rootwait rw\0 \
+ mmcroot=/dev/mmcblk0p1 rootwait rw\0 \
update_sd_firmware_filename=u-boot.imx\0 \
update_sd_firmware= \
if test ${ip_dyn} = yes; then \
@@ -127,13 +127,14 @@
fi; \
fi\0 \
mmcargs=setenv bootargs console=${console},${baudrate} \
- root=${mmcroot}\0 \
+ root=${mmcroot} rootwait rw \
+ fbmem=24M video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24\0 \
loadbootscript= \
- fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0 \
+ ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0 \
bootscript=echo Running bootscript from mmc ...; \
source\0 \
- loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0
\
- loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0 \
+ loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0
\
+ loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0
\
mmcboot=echo Booting from mmc ...; \
run mmcargs; \
if test ${boot_fdt} = yes || test ${boot_fdt} = try; then \
@@ -189,7 +190,7 @@
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT =
+#define CONFIG_SYS_PROMPT uDoo board
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256
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