[U-Boot] [PATCH] generic_board: Call checkboard even though the root node has a model property

[Haikun Wang]

In case of enable CONFIG_OF_CONTROL and has a model property in the root node,
the board special checkboard will not be called.
Usually we show some useful version information in the function.
This patch enable call checkboard in any case.
It is not conflicting with showing model at the same time.

For example on LS2085AQDS:
Showing model only:
Model: Freescale Layerscape 2085a QDS Board

Showing checkboard only:
Board: LS2085E-QDS, Board Arch: V1, Board version: B, boot from vBank: 4

Showing both:
Model: Freescale Layerscape 2085a QDS Board
Board: LS2085E-QDS, Board Arch: V1, Board version: B, boot from vBank: 4

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 common/board_info.c | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/common/board_info.c b/common/board_info.c
index 42d0641..4e5a1f7 100644
--- a/common/board_info.c
+++ b/common/board_info.c
@@ -14,8 +14,7 @@ int __weak checkboard(void)
 
 /*
  * If the root node of the DTB has a model property, show it.
- * If CONFIG_OF_CONTROL is disabled or the model property is missing,
- * fall back to checkboard().
+ * Then call checkboard().
  */
 int show_board_info(void)
 {
@@ -25,10 +24,8 @@ int show_board_info(void)
 
model = fdt_getprop(gd-fdt_blob, 0, model, NULL);
 
-   if (model) {
+   if (model)
printf(Model: %s\n, model);
-   return 0;
-   }
 #endif
 
return checkboard();
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] defconfig: ls2085a: Enable FSL_DSPI, OF_CONTROL and DM support

[Haikun Wang]

Freescale DSPI driver has been converted to Driver Model.
The new driver is depended on OF_CONTROL, DM, DM_SPI.
This patch enable FSL_DSPI and its dependence configure options.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 configs/ls2085aqds_defconfig | 7 +++
 configs/ls2085ardb_defconfig | 7 +++
 2 files changed, 14 insertions(+)

diff --git a/configs/ls2085aqds_defconfig b/configs/ls2085aqds_defconfig
index fd208b18..00b062b 100644
--- a/configs/ls2085aqds_defconfig
+++ b/configs/ls2085aqds_defconfig
@@ -1,4 +1,11 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS2085AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE=fsl-ls2085a-qds
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_SYS_EXTRA_OPTIONS=SYS_FSL_DDR4
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
diff --git a/configs/ls2085ardb_defconfig b/configs/ls2085ardb_defconfig
index 308e935..c7dae4b 100644
--- a/configs/ls2085ardb_defconfig
+++ b/configs/ls2085ardb_defconfig
@@ -1,4 +1,11 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS2085ARDB=y
+CONFIG_DEFAULT_DEVICE_TREE=fsl-ls2085a-rdb
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_SYS_EXTRA_OPTIONS=SYS_FSL_DDR4
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/3] configs: ls2085aqds: Enable DSPI flash support for LS2085AQDS

[Haikun Wang]

From: Haikun Wang haikun.w...@freescale.com

Enable DSPI flash related configurations.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 include/configs/ls2085aqds.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
index e488ac8..bf5ea51 100644
--- a/include/configs/ls2085aqds.h
+++ b/include/configs/ls2085aqds.h
@@ -273,6 +273,15 @@ unsigned long get_board_ddr_clk(void);
 /* I2C bus multiplexer */
 #define I2C_MUX_CH_DEFAULT  0x8
 
+/* SPI */
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
 /*
  * MMC
  */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/3] configs: ls2085ardb: Enable DSPI flash support for LS2085ARDB

[Haikun Wang]

From: Haikun Wang haikun.w...@freescale.com

Enable DSPI flash related configurations for LS2085ARDB.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 include/configs/ls2085ardb.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index 600261e..8cd3bf7 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -245,6 +245,14 @@ unsigned long get_board_sys_clk(void);
 /* I2C bus multiplexer */
 #define I2C_MUX_CH_DEFAULT  0x8
 
+/* SPI */
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+#endif
+
 /*
  * RTC configuration
  */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/5] sf: sf_dataflash: Remove inline property of function dataflash_status

[Haikun Wang]

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 drivers/mtd/spi/sf_dataflash.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
index 3111f4f..f83f994 100644
--- a/drivers/mtd/spi/sf_dataflash.c
+++ b/drivers/mtd/spi/sf_dataflash.c
@@ -67,7 +67,6 @@
 #define OP_WRITE_SECURITY_REVC 0x9A
 #define OP_WRITE_SECURITY  0x9B/* revision D */
 
-
 struct dataflash {
uint8_t command[16];
unsigned short  page_offset;/* offset in flash address */
@@ -76,7 +75,7 @@ struct dataflash {
 /*
  * Return the status of the DataFlash device.
  */
-static inline int dataflash_status(struct spi_slave *spi)
+static int dataflash_status(struct spi_slave *spi)
 {
int ret;
u8 status;
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 5/5] sf: sf_dataflash: Update probing method of old chips which not support Device ID

[Haikun Wang]

Some old dataflash chips don't have device ID,
we should identif them using bits in the flash status byte.
Add a variable status_byte in struct flash_info,
and assign correct value for above old chips.
Add those chips to the supported flash chip table
and identify them through the new variable status_byte.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 drivers/mtd/spi/sf_dataflash.c | 226 +++--
 1 file changed, 107 insertions(+), 119 deletions(-)

diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
index 648f3ca..cd8d908 100644
--- a/drivers/mtd/spi/sf_dataflash.c
+++ b/drivers/mtd/spi/sf_dataflash.c
@@ -67,11 +67,87 @@
 #define OP_WRITE_SECURITY_REVC 0x9A
 #define OP_WRITE_SECURITY  0x9B/* revision D */
 
+#define ATMEL_VENDOR_ID0x1f
+
 struct dataflash {
uint8_t command[16];
unsigned short  page_offset;/* offset in flash address */
 };
 
+struct flash_info {
+   char*name;
+
+   /*
+* JEDEC id has a high byte of zero plus three data bytes:
+* the manufacturer id, then a two byte device id.
+*/
+   uint32_tjedec_id;
+
+   /* The size listed here is what works with OP_ERASE_PAGE. */
+   unsignednr_pages;
+   uint16_tpagesize;
+   uint16_tpageoffset;
+   uint8_t status_byte;
+
+   uint16_tflags;
+#define SUP_POW2PS 0x0002  /* supports 2^N byte pages */
+#define IS_POW2PS  0x0001  /* uses 2^N byte pages */
+};
+
+static struct flash_info dataflash_data[] = {
+   /*
+* NOTE:  chips with SUP_POW2PS (rev D and up) need two entries,
+* one with IS_POW2PS and the other without.  The entry with the
+* non-2^N byte page size can't name exact chip revisions without
+* losing backwards compatibility for cmdlinepart.
+*
+* Those two entries have different name spelling format in order to
+* show their difference obviously.
+* The upper case refer to the chip isn't in normal 2^N bytes page-size
+* mode.
+* The lower case refer to the chip is in normal 2^N bytes page-size
+* mode.
+*
+* These newer chips also support 128-byte security registers (with
+* 64 bytes one-time-programmable) and software write-protection.
+*/
+   { AT45DB011B,  0x1f2200, 512, 264, 9, 0, SUP_POW2PS},
+   { at45db011d,  0x1f2200, 512, 256, 8, 0, SUP_POW2PS | IS_POW2PS},
+
+   { AT45DB021B,  0x1f2300, 1024, 264, 9, 0, SUP_POW2PS},
+   { at45db021d,  0x1f2300, 1024, 256, 8, 0, SUP_POW2PS | IS_POW2PS},
+
+   { AT45DB041x,  0x1f2400, 2048, 264, 9, 0, SUP_POW2PS},
+   { at45db041d,  0x1f2400, 2048, 256, 8, 0, SUP_POW2PS | IS_POW2PS},
+
+   { AT45DB081B,  0x1f2500, 4096, 264, 9, 0, SUP_POW2PS},
+   { at45db081d,  0x1f2500, 4096, 256, 8, 0, SUP_POW2PS | IS_POW2PS},
+
+   { AT45DB161x,  0x1f2600, 4096, 528, 10, 0, SUP_POW2PS},
+   { at45db161d,  0x1f2600, 4096, 512, 9, 0, SUP_POW2PS | IS_POW2PS},
+
+   /* rev C */
+   { AT45DB321x,  0x1f2700, 8192, 528, 10, 0, 0},
+
+   { AT45DB321x,  0x1f2701, 8192, 528, 10, 0, SUP_POW2PS},
+   { at45db321d,  0x1f2701, 8192, 512, 9, 0, SUP_POW2PS | IS_POW2PS},
+
+   { AT45DB642x,  0x1f2800, 8192, 1056, 11, 0, SUP_POW2PS},
+   { at45db642d,  0x1f2800, 8192, 1024, 10, 0, SUP_POW2PS | IS_POW2PS},
+   /*
+   * Older chips support only legacy commands, identifing
+   * capacity using bits in the status byte.
+   */
+   { AT45DB011B-NOID, 0, 512, 264, 9, 0x0c, 0},
+   { AT45DB021B-NOID, 0, 1024, 264, 9, 0x14, 0},
+   { AT45DB041x-NOID, 0, 2048, 264, 9, 0x1c, 0},
+   { AT45DB081B-NOID, 0, 4096, 264, 9, 0x24, 0},
+   { AT45DB161x-NOID, 0, 4096, 528, 10, 0x2c, 0},
+   { AT45DB321x-NOID, 0, 8192, 528, 10, 0x34, 0},
+   { AT45DB642x-NOID, 0, 8192, 1056, 11, 0x38, 0},
+   { AT45DB642x-NOID, 0, 8192, 1056, 11, 0x3c, 0},
+};
+
 /*
  * Return the status of the DataFlash device.
  */
@@ -452,67 +528,7 @@ static int add_dataflash(struct udevice *dev, char *name, 
int nr_pages,
return 0;
 }
 
-struct flash_info {
-   char*name;
-
-   /*
-* JEDEC id has a high byte of zero plus three data bytes:
-* the manufacturer id, then a two byte device id.
-*/
-   uint32_tjedec_id;
-
-   /* The size listed here is what works with OP_ERASE_PAGE. */
-   unsignednr_pages;
-   uint16_tpagesize;
-   uint16_tpageoffset;
-
-   uint16_tflags;
-#define SUP_POW2PS 0x0002  /* supports 2^N byte pages */
-#define IS_POW2PS  0x0001  /* uses 2^N byte pages */
-};
-
-static struct flash_info dataflash_data[] = {
-   /*
-* NOTE:  chips with SUP_POW2PS (rev D and up) need two entries,
-* one

[U-Boot] [PATCH 4/5] sf: sf_dataflash: Change the return value of jedec_probe to int

[Haikun Wang]

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 drivers/mtd/spi/sf_dataflash.c | 28 +---
 1 file changed, 17 insertions(+), 11 deletions(-)

diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
index 6bf628b..648f3ca 100644
--- a/drivers/mtd/spi/sf_dataflash.c
+++ b/drivers/mtd/spi/sf_dataflash.c
@@ -512,7 +512,8 @@ static struct flash_info dataflash_data[] = {
{ at45db642d,  0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
 };
 
-static struct flash_info *jedec_probe(struct spi_slave *spi, u8 *id)
+static int jedec_probe(struct spi_slave *spi, u8 *id,
+   struct flash_info **pp_info)
 {
int tmp;
uint32_tjedec;
@@ -529,7 +530,7 @@ static struct flash_info *jedec_probe(struct spi_slave 
*spi, u8 *id)
 * only Atmel sells these chips.
 */
if (id[0] != 0x1f)
-   return NULL;
+   return -EINVAL;
 
jedec = id[0];
jedec = jedec  8;
@@ -546,17 +547,22 @@ static struct flash_info *jedec_probe(struct spi_slave 
*spi, u8 *id)
if (status  0) {
debug(SPI DataFlash: status error 
%d\n,
  status);
-   return NULL;
+   return -EIO;
}
if (status  0x1) {
-   if (info-flags  IS_POW2PS)
-   return info;
+   if (info-flags  IS_POW2PS) {
+   *pp_info = info;
+   return 0;
+   }
} else {
-   if (!(info-flags  IS_POW2PS))
-   return info;
+   if (!(info-flags  IS_POW2PS)) {
+   *pp_info = info;
+   return 0;
+   }
}
} else {
-   return info;
+   *pp_info = info;
+   return 0;
}
}
}
@@ -569,7 +575,7 @@ static struct flash_info *jedec_probe(struct spi_slave 
*spi, u8 *id)
printf(SPI DataFlash: Unsupported flash IDs: );
printf(manuf %02x, jedec %04x, ext_jedec %04x\n,
   id[0], jedec, id[3]  8 | id[4]);
-   return NULL;
+   return -EPROTONOSUPPORT;
 }
 
 /*
@@ -614,8 +620,8 @@ static int spi_dataflash_probe(struct udevice *dev)
 * Both support the security register, though with different
 * write procedures.
 */
-   info = jedec_probe(spi, idcode);
-   if (info != NULL)
+   ret = jedec_probe(spi, idcode, info);
+   if (!ret)
add_dataflash(dev, info-name, info-nr_pages,
  info-pagesize, info-pageoffset,
  (info-flags  SUP_POW2PS) ? 'd' : 'c');
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 3/5] sf: sf_dataflash: Remove CONFIG_SPI_DATAFLASH_WRITE_VERIFY option

[Haikun Wang]

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 drivers/mtd/spi/sf_dataflash.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
index 8f91527..6bf628b 100644
--- a/drivers/mtd/spi/sf_dataflash.c
+++ b/drivers/mtd/spi/sf_dataflash.c
@@ -371,7 +371,6 @@ int spi_dataflash_write(struct udevice *dev, u32 offset, 
size_t len,
goto release_bus;
}
 
-#ifdef CONFIG_SPI_DATAFLASH_WRITE_VERIFY
/* (3) Compare to Buffer1 */
addr = pageaddr  dataflash-page_offset;
command[0] = OP_COMPARE_BUF1;
@@ -404,7 +403,6 @@ int spi_dataflash_write(struct udevice *dev, u32 offset, 
size_t len,
status = 0;
}
 
-#endif /* CONFIG_SPI_DATAFLASH_WRITE_VERIFY */
remaining = remaining - writelen;
pageaddr++;
to = 0;
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/5] sf: sf_dataflash: Add error handler when flash operate fail

[Haikun Wang]

Add error handler when write/erase flash fail.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 drivers/mtd/spi/sf_dataflash.c | 30 ++
 1 file changed, 22 insertions(+), 8 deletions(-)

diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
index f83f994..8f91527 100644
--- a/drivers/mtd/spi/sf_dataflash.c
+++ b/drivers/mtd/spi/sf_dataflash.c
@@ -174,13 +174,14 @@ static int spi_dataflash_erase(struct udevice *dev, u32 
offset, size_t len)
status = spi_flash_cmd_write(spi, command, 4, NULL, 0);
if (status  0) {
debug(%s: erase send command error!\n, dev-name);
-   return -EIO;
+   status = -EIO;
+   goto release_bus;
}
 
status = dataflash_waitready(spi);
if (status  0) {
debug(%s: erase waitready error!\n, dev-name);
-   return status;
+   goto release_bus;
}
 
if (do_block) {
@@ -195,6 +196,11 @@ static int spi_dataflash_erase(struct udevice *dev, u32 
offset, size_t len)
spi_release_bus(spi);
 
return 0;
+
+release_bus:
+   spi_release_bus(spi);
+
+   return status;
 }
 
 /*
@@ -329,14 +335,15 @@ int spi_dataflash_write(struct udevice *dev, u32 offset, 
size_t len,
if (status  0) {
debug(%s: write(pagesize) command error!\n,
  dev-name);
-   return -EIO;
+   status = -EIO;
+   goto release_bus;
}
 
status = dataflash_waitready(spi);
if (status  0) {
debug(%s: write(pagesize) waitready error!\n,
  dev-name);
-   return status;
+   goto release_bus;
}
}
 
@@ -354,13 +361,14 @@ int spi_dataflash_write(struct udevice *dev, u32 offset, 
size_t len,
 4, writebuf, writelen);
if (status  0) {
debug(%s: write send command error!\n, dev-name);
-   return -EIO;
+   status = -EIO;
+   goto release_bus;
}
 
status = dataflash_waitready(spi);
if (status  0) {
debug(%s: write waitready error!\n, dev-name);
-   return status;
+   goto release_bus;
}
 
 #ifdef CONFIG_SPI_DATAFLASH_WRITE_VERIFY
@@ -379,7 +387,8 @@ int spi_dataflash_write(struct udevice *dev, u32 offset, 
size_t len,
if (status  0) {
debug(%s: write(compare) send command error!\n,
  dev-name);
-   return -EIO;
+   status = -EIO;
+   goto release_bus;
}
 
status = dataflash_waitready(spi);
@@ -390,7 +399,7 @@ int spi_dataflash_write(struct udevice *dev, u32 offset, 
size_t len,
   pageaddr, status);
remaining = 0;
status = -EIO;
-   break;
+   goto release_bus;
} else {
status = 0;
}
@@ -410,6 +419,11 @@ int spi_dataflash_write(struct udevice *dev, u32 offset, 
size_t len,
spi_release_bus(spi);
 
return 0;
+
+release_bus:
+   spi_release_bus(spi);
+
+   return status;
 }
 
 static int add_dataflash(struct udevice *dev, char *name, int nr_pages,
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2] sf: update sst25wf040b flash params

[Haikun Wang]

From: Haikun Wang haikun.w...@freescale.com

sst25wf040b doesn't support Auto Address Increment Programming command.
Remove SST_WR flag.

Signed-off-by: Haikun Wang b53...@freescale.com
---
Changes in V2:
- Remove extra line

 drivers/mtd/spi/sf_params.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index c12e8c6..4a4a3af 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -100,7 +100,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
{SST25WF010, 0xbf2502, 0x0,   64 * 1024, 2, RD_NORM,  
SECT_4K | SST_WR},
{SST25WF020, 0xbf2503, 0x0,   64 * 1024, 4, RD_NORM,  
SECT_4K | SST_WR},
{SST25WF040, 0xbf2504, 0x0,   64 * 1024, 8, RD_NORM,  
SECT_4K | SST_WR},
-   {SST25WF040B,0x621613, 0x0,   64 * 1024, 8, RD_NORM,  
SECT_4K | SST_WR},
+   {SST25WF040B,0x621613, 0x0,   64 * 1024, 8, RD_NORM,  
 SECT_4K},
{SST25WF080, 0xbf2505, 0x0,   64 * 1024,16, RD_NORM,  
SECT_4K | SST_WR},
 #endif
 #ifdef CONFIG_SPI_FLASH_WINBOND/* WINBOND */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 1/5] dm: sf: Add Atmel DataFlash spi flash driver

[Haikun Wang]

Atmel DataFlash chips have commands different from common spi
flash commands.
Atmel DataFlash also have special page-size.
This driver add support for accessing Atmel DataFlash.
It is based on the Driver Model.
Example:
= sf probe 1:0
SPI DataFlash: Detected AT45DB021B with page size 264 Bytes, erase size 264 
Bytes, total 264 KiB, revision d
= sf erase 0 42000
SF: 270336 bytes @ 0x0 Erased: OK
= mw.l 8200 45444342 2
= sf write 8200 0 42000
SF: 270336 bytes @ 0x0 Written: OK
= sf read 8300 0 42000
SF: 270336 bytes @ 0x0 Read: OK
= cmp.b 8200 8300 42000
Total of 270336 byte(s) were the same

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
Verified with AT45DB021B on LS1021AQDS.
Changes in v6:
- Add defconfig patch in this series

Changes in v5:
- Change CONFIG_DM_SF_DATAFLASH to CONFIG_SF_DATAFLASH

Changes in v4:
- Use dev_get_priv and dev_get_uclass_priv
- Add test log to commit message

Changes in v3:
- 1. Rename file spi_dataflash.c to sf_dataflash.c
- 2. Add comment for array dataflash_data

Changes in v2:
- 1. Correct comment style
- 2. Use get_timer in dataflash_waitready to check whether timeout
- 3. Remove struct spi_flash * in struct dataflash, and get it from 
udevice-uclass_priv
- 4. Replace spi_flash_write_common with spi_flash_cmd_write 
- 5. Replace spi_flash_read with spi_flash_cmd_read 
- 6. Change type of varible status form char to u8 in dataflash_status
- 7. Change add_dataflash's argument type due to change 3
- 8. Add claim_bus and release_bus in erase/write/read due to change 4  5

Changes in v1: None
 drivers/mtd/spi/Makefile   |   1 +
 drivers/mtd/spi/sf_dataflash.c | 711 +
 2 files changed, 712 insertions(+)
 create mode 100644 drivers/mtd/spi/sf_dataflash.c

diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index c61b784..87f20bc 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -15,6 +15,7 @@ endif
 #ifndef CONFIG_DM_SPI
 obj-$(CONFIG_SPI_FLASH) += sf_probe.o
 #endif
+obj-$(CONFIG_SF_DATAFLASH) += sf_dataflash.o
 obj-$(CONFIG_CMD_SF) += sf.o
 obj-$(CONFIG_SPI_FLASH) += sf_ops.o sf_params.o
 obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
new file mode 100644
index 000..d287db8
--- /dev/null
+++ b/drivers/mtd/spi/sf_dataflash.c
@@ -0,0 +1,711 @@
+/*
+ *
+ * Atmel DataFlash probing
+ *
+ * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
+ * Haikun Wang (haikun.w...@freescale.com)
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+*/
+#include common.h
+#include dm.h
+#include errno.h
+#include fdtdec.h
+#include spi.h
+#include spi_flash.h
+#include div64.h
+#include linux/err.h
+#include linux/math64.h
+
+#include sf_internal.h
+
+/*
+ * DataFlash is a kind of SPI flash.  Most AT45 chips have two buffers in
+ * each chip, which may be used for double buffered I/O; but this driver
+ * doesn't (yet) use these for any kind of i/o overlap or prefetching.
+ *
+ * Sometimes DataFlash is packaged in MMC-format cards, although the
+ * MMC stack can't (yet?) distinguish between MMC and DataFlash
+ * protocols during enumeration.
+ */
+
+/* reads can bypass the buffers */
+#define OP_READ_CONTINUOUS 0xE8
+#define OP_READ_PAGE   0xD2
+
+/* group B requests can run even while status reports busy */
+#define OP_READ_STATUS 0xD7/* group B */
+
+/* move data between host and buffer */
+#define OP_READ_BUFFER10xD4/* group B */
+#define OP_READ_BUFFER20xD6/* group B */
+#define OP_WRITE_BUFFER1   0x84/* group B */
+#define OP_WRITE_BUFFER2   0x87/* group B */
+
+/* erasing flash */
+#define OP_ERASE_PAGE  0x81
+#define OP_ERASE_BLOCK 0x50
+
+/* move data between buffer and flash */
+#define OP_TRANSFER_BUF1   0x53
+#define OP_TRANSFER_BUF2   0x55
+#define OP_MREAD_BUFFER1   0xD4
+#define OP_MREAD_BUFFER2   0xD6
+#define OP_MWERASE_BUFFER1 0x83
+#define OP_MWERASE_BUFFER2 0x86
+#define OP_MWRITE_BUFFER1  0x88/* sector must be pre-erased */
+#define OP_MWRITE_BUFFER2  0x89/* sector must be pre-erased */
+
+/* write to buffer, then write-erase to flash */
+#define OP_PROGRAM_VIA_BUF10x82
+#define OP_PROGRAM_VIA_BUF20x85
+
+/* compare buffer to flash */
+#define OP_COMPARE_BUF10x60
+#define OP_COMPARE_BUF20x61
+
+/* read flash to buffer, then write-erase to flash */
+#define OP_REWRITE_VIA_BUF10x58
+#define OP_REWRITE_VIA_BUF20x59
+
+/*
+ * newer chips report JEDEC manufacturer and device IDs; chip
+ * serial number and OTP bits; and per-sector writeprotect.
+ */
+#define OP_READ_ID 0x9F
+#define OP_READ_SECURITY   0x77
+#define OP_WRITE_SECURITY_REVC 0x9A
+#define OP_WRITE_SECURITY  0x9B/* revision D */
+
+
+struct dataflash {
+   uint8_t command[16];
+   unsigned short

[U-Boot] [PATCH v4 4/5] arm: ls102xa: Enable Driver Model SPI for ls1021atwr

[Haikun Wang]

From: Haikun Wang haikun.w...@freescale.com

Enable Driver Model SPI for ls1021atwr board.
DSPI and QSPI only be enabled when boot from QSPI.
DSPI and QSPI are compatible under Driver Model SPI.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
Change-Id: I6342807da7725ae8b678952117c8758c75a61d3d
Reviewed-on: http://git.am.freescale.net:8181/33447
Tested-by: Review Code-CDREVIEW cdrev...@freescale.com
Reviewed-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes in v4:
- Add defconfig patch in this series

Changes in v3:
- IS_ENABLED(CONFIG_XXX) is only work with configure option in Kconfig,
  and DM core code use IS_ENABLED(), so configure option in head file
  can't work, so remove CONFIG_OF_CONTROL CONFIG_OF_SEPARATE CONFIG_DM 
CONFIG_DM_SPI

Changes in v2:
- Move all changes inside of CONFIG_QSPI_BOOT 

Changes in v1: None
 include/configs/ls1021atwr.h | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 729205f..13e3aa4 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -229,16 +229,22 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
-/* QSPI */
+/* SPI */
 #ifdef CONFIG_QSPI_BOOT
+/* QSPI */
 #define CONFIG_FSL_QSPI
 #define QSPI0_AMBA_BASE0x4000
 #define FSL_QSPI_FLASH_SIZE(1  24)
 #define FSL_QSPI_FLASH_NUM 2
 
+#define CONFIG_SPI_FLASH_STMICRO
+
+/* DM SPI */
+#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 #define CONFIG_CMD_SF
+#define CONFIG_DM_SPI_FLASH
 #define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
+#endif
 #endif
 
 /*
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] armv7: ls1021a: Enable OF_CONTROL and DM support for DSPI and QSPI in defconfig

[Haikun Wang]

DSPI and QSPI only work when boot from QSPI on ls1021a.
This patch only enable options in qspi boot defconfig.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 configs/ls1021aqds_qspi_defconfig | 4 
 configs/ls1021atwr_qspi_defconfig | 4 
 2 files changed, 8 insertions(+)

diff --git a/configs/ls1021aqds_qspi_defconfig 
b/configs/ls1021aqds_qspi_defconfig
index c5372b7..61d4552 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -2,3 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_SYS_EXTRA_OPTIONS=QSPI_BOOT
 CONFIG_CMD_NET=y
+CONFIG_DEFAULT_DEVICE_TREE=ls1021a-qds
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SPI=y
diff --git a/configs/ls1021atwr_qspi_defconfig 
b/configs/ls1021atwr_qspi_defconfig
index 1ae0f9c..eb05f0a 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -2,3 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
 CONFIG_SYS_EXTRA_OPTIONS=QSPI_BOOT
 CONFIG_CMD_NET=y
+CONFIG_DEFAULT_DEVICE_TREE=ls1021a-twr
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SPI=y
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 2/5] dm: ls1021aqds: dts: Use spi_dataflash driver instead of spi_flash_std for DSPI flash

[Haikun Wang]

The type of DSPI flash on ls1021aqds is AT45DB021, it has specail
commands and page-size.
Use the special spi flash driver instead of spi_flash_std driver.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
Changes in v2:
- Add defconfig patch in this series

 arch/arm/dts/ls1021a-qds.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dts
index 8367811..e634292 100644
--- a/arch/arm/dts/ls1021a-qds.dts
+++ b/arch/arm/dts/ls1021a-qds.dts
@@ -30,7 +30,7 @@
dspiflash: at45db021d@0 {
#address-cells = 1;
#size-cells = 1;
-   compatible = spi-flash;
+   compatible = atmel,dataflash;
spi-max-frequency = 1600;
spi-cpol;
spi-cpha;
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] sf: update sst25wf040b flash params

[Haikun Wang]

From: Haikun Wang haikun.w...@freescale.com

sst25wf040b doesn't support Auto Address Increment Programming command.
Remove SST_WR flag.

Signed-off-by: Haikun Wang b53...@freescale.com
---
 drivers/mtd/spi/sf_params.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index c12e8c6..283087a 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -100,7 +100,8 @@ const struct spi_flash_params spi_flash_params_table[] = {
{SST25WF010, 0xbf2502, 0x0,   64 * 1024, 2, RD_NORM,  
SECT_4K | SST_WR},
{SST25WF020, 0xbf2503, 0x0,   64 * 1024, 4, RD_NORM,  
SECT_4K | SST_WR},
{SST25WF040, 0xbf2504, 0x0,   64 * 1024, 8, RD_NORM,  
SECT_4K | SST_WR},
-   {SST25WF040B,0x621613, 0x0,   64 * 1024, 8, RD_NORM,  
SECT_4K | SST_WR},
+   {SST25WF040B,0x621613, 0x0,   64 * 1024,
+8, RD_NORM,SECT_4K},
{SST25WF080, 0xbf2505, 0x0,   64 * 1024,16, RD_NORM,  
SECT_4K | SST_WR},
 #endif
 #ifdef CONFIG_SPI_FLASH_WINBOND/* WINBOND */
-- 
1.9.1

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[U-Boot] [PATCH v2 5/5] armv7: ls1021a: Enable OF_CONTROL and DM support for DSPI and QSPI in defconfig

[Haikun Wang]

DSPI and QSPI only work when boot from QSPI on ls1021a.
This patch only enable options in qspi boot defconfig.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
Changes in v2:
- Add this defconfig patch to previous dataflash driver patches series

Test log on LS1021AQDS:
= sf probe 1:0
SPI DataFlash: Detected at45db021d with page size 256 Bytes, erase size 256 
Bytes, total 256 KiB, revision d
= sf erase 0 4
SF: 262144 bytes @ 0x0 Erased: OK
= mw.b 8200 33 4
= sf write 8200 0 4
SF: 262144 bytes @ 0x0 Written: OK
= sf read 8300 0 4
SF: 262144 bytes @ 0x0 Read: OK
= cmp.b 8200 8300 4
Total of 262144 byte(s) were the same
= sf probe 0:0
SF: Detected S25FL128S_64K with page size 256 Bytes, erase size 64 KiB, total 
16 MiB

Test log on LS1021ATWR:
= sf probe 0:0
SF: Detected N25Q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB

 configs/ls1021aqds_qspi_defconfig | 4 
 configs/ls1021atwr_qspi_defconfig | 4 
 2 files changed, 8 insertions(+)

diff --git a/configs/ls1021aqds_qspi_defconfig 
b/configs/ls1021aqds_qspi_defconfig
index c5372b7..61d4552 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -2,3 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_SYS_EXTRA_OPTIONS=QSPI_BOOT
 CONFIG_CMD_NET=y
+CONFIG_DEFAULT_DEVICE_TREE=ls1021a-qds
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SPI=y
diff --git a/configs/ls1021atwr_qspi_defconfig 
b/configs/ls1021atwr_qspi_defconfig
index 1ae0f9c..eb05f0a 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -2,3 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
 CONFIG_SYS_EXTRA_OPTIONS=QSPI_BOOT
 CONFIG_CMD_NET=y
+CONFIG_DEFAULT_DEVICE_TREE=ls1021a-twr
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SPI=y
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/2] armv8: ls2085aqds: DSPI pin muxing configure through QIXIS

[Haikun Wang]

From: Haikun Wang haikun.w...@freescale.com

DSPI has pin muxing with SDHC and other IPs, this patch check the value of
RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check the hwconfig
configuration, if those pins are configured to DSPI and hwconfig enable
DSPI, set the BRDCFG5 of QIXIS FPGA to configure the SPI routing to on-board
SPI memory. Otherwise will configure to SDHC.
Enable DSPI in u-boot hwconfig using below command:
setenv hwconfig $hwconfig;dspi

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 arch/arm/include/asm/arch-fsl-lsch3/config.h |  2 ++
 board/freescale/ls2085aqds/ls2085aqds.c  | 48 
 2 files changed, 50 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h 
b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index ca8d38c..8675e91 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -137,6 +137,8 @@
 #define DCFG_PORSR10x000
 #define DCFG_PORSR1_RCW_SRC0xff80
 #define DCFG_PORSR1_RCW_SRC_NOR0x12f0
+#define DCFG_RCWSR13   0x130
+#define DCFG_RCWSR13_DSPI  (0  8)
 
 #define DCFG_DCSR_BASE 0X70010ULL
 #define DCFG_DCSR_PORCR1   0x000
diff --git a/board/freescale/ls2085aqds/ls2085aqds.c 
b/board/freescale/ls2085aqds/ls2085aqds.c
index c492c7e..08906a6 100644
--- a/board/freescale/ls2085aqds/ls2085aqds.c
+++ b/board/freescale/ls2085aqds/ls2085aqds.c
@@ -17,12 +17,23 @@
 #include environment.h
 #include i2c.h
 #include asm/arch-fsl-lsch3/soc.h
+#include hwconfig.h
 
 #include ../common/qixis.h
 #include ls2085aqds_qixis.h
 
+#define PIN_MUX_SEL_SDHC   0x00
+#define PIN_MUX_SEL_DSPI   0x0a
+
+#define SET_SDHC_MUX_SEL(reg, value)   ((reg  0xf0) | value)
+
 DECLARE_GLOBAL_DATA_PTR;
 
+enum {
+   MUX_TYPE_SDHC,
+   MUX_TYPE_DSPI,
+};
+
 unsigned long long get_qixis_addr(void)
 {
unsigned long long addr;
@@ -153,10 +164,47 @@ int select_i2c_ch_pca9547(u8 ch)
return 0;
 }
 
+int config_board_mux(int ctrl_type)
+{
+   u8 reg5;
+
+   reg5 = QIXIS_READ(brdcfg[5]);
+
+   switch (ctrl_type) {
+   case MUX_TYPE_SDHC:
+   reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
+   break;
+   case MUX_TYPE_DSPI:
+   reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
+   break;
+   default:
+   printf(Wrong mux interface type\n);
+   return -1;
+   }
+
+   QIXIS_WRITE(brdcfg[5], reg5);
+
+   return 0;
+}
+
 int board_init(void)
 {
+   char *env_hwconfig;
+   u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+   u32 val;
+
init_final_memctl_regs();
 
+   val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
+
+   env_hwconfig = getenv(hwconfig);
+
+   if (hwconfig_f(dspi, env_hwconfig) 
+   DCFG_RCWSR13_DSPI == (val  (u32)(0xf  8)))
+   config_board_mux(MUX_TYPE_DSPI);
+   else
+   config_board_mux(MUX_TYPE_SDHC);
+
 #ifdef CONFIG_ENV_IS_NOWHERE
gd-env_addr = (ulong)default_environment[0];
 #endif
-- 
1.9.1

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[U-Boot] [PATCH 2/2] armv8: ls2085ardb: DSPI pin muxing configure through QIXIS CPLD

[Haikun Wang]

DSPI has pin muxing with SDHC and other IPs, this patch check the value of
RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check the hwconfig
configuration, if those pins are configured to DSPI and hwconfig enable
DSPI, set the BRDCFG5 of QIXIS CPLD to configure the SPI routing to on-board
SPI memory. Otherwise will configure to SDHC.
Enable DSPI in u-boot hwconfig using below command:
setenv hwconfig $hwconfig;dspi

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 board/freescale/ls2085ardb/ls2085ardb.c | 47 +
 1 file changed, 47 insertions(+)

diff --git a/board/freescale/ls2085ardb/ls2085ardb.c 
b/board/freescale/ls2085ardb/ls2085ardb.c
index d05f2bc..674015a 100644
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2085ardb/ls2085ardb.c
@@ -10,6 +10,7 @@
 #include fsl_ifc.h
 #include fsl_ddr.h
 #include asm/io.h
+#include hwconfig.h
 #include fdt_support.h
 #include libfdt.h
 #include fsl_debug_server.h
@@ -21,8 +22,17 @@
 #include ../common/qixis.h
 #include ls2085ardb_qixis.h
 
+#define PIN_MUX_SEL_SDHC   0x00
+#define PIN_MUX_SEL_DSPI   0x0a
+
+#define SET_SDHC_MUX_SEL(reg, value)   ((reg  0xf0) | value)
 DECLARE_GLOBAL_DATA_PTR;
 
+enum {
+   MUX_TYPE_SDHC,
+   MUX_TYPE_DSPI,
+};
+
 unsigned long long get_qixis_addr(void)
 {
unsigned long long addr;
@@ -109,10 +119,47 @@ int select_i2c_ch_pca9547(u8 ch)
return 0;
 }
 
+int config_board_mux(int ctrl_type)
+{
+   u8 reg5;
+
+   reg5 = QIXIS_READ(brdcfg[5]);
+
+   switch (ctrl_type) {
+   case MUX_TYPE_SDHC:
+   reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
+   break;
+   case MUX_TYPE_DSPI:
+   reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
+   break;
+   default:
+   printf(Wrong mux interface type\n);
+   return -1;
+   }
+
+   QIXIS_WRITE(brdcfg[5], reg5);
+
+   return 0;
+}
+
 int board_init(void)
 {
+   char *env_hwconfig;
+   u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+   u32 val;
+
init_final_memctl_regs();
 
+   val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
+
+   env_hwconfig = getenv(hwconfig);
+
+   if (hwconfig_f(dspi, env_hwconfig) 
+   DCFG_RCWSR13_DSPI == (val  (u32)(0xf  8)))
+   config_board_mux(MUX_TYPE_DSPI);
+   else
+   config_board_mux(MUX_TYPE_SDHC);
+
 #ifdef CONFIG_ENV_IS_NOWHERE
gd-env_addr = (ulong)default_environment[0];
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] fdt: armv8: Fix build warnings on armv8

[Haikun Wang]

From: Haikun Wang haikun.w...@freescale.com

Fix below build warnings on armv8,
drivers/spi/fsl_dspi.c: In function ‘fsl_dspi_ofdata_to_platdata’:
drivers/spi/fsl_dspi.c:667:2:
warning: format ‘%x’ expects argument of type ‘unsigned int’,
but argument 2 has type ‘fdt_addr_t’ [-Wformat=]
debug(DSPI: regs=0x%x, max-frequency=%d, endianess=%s, num-cs=%d\n,
^
lib/fdtdec.c: In function ‘fdtdec_get_addr_size’:
lib/fdtdec.c:105:4:
warning: format ‘%lx’ expects argument of type ‘long unsigned int’,
but argument 3 has type ‘fdt_size_t’ [-Wformat=]
debug(addr=%08lx, size=%08lx\n,
^

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 drivers/spi/fsl_dspi.c | 4 ++--
 lib/fdtdec.c   | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c
index 6476f91..7928531 100644
--- a/drivers/spi/fsl_dspi.c
+++ b/drivers/spi/fsl_dspi.c
@@ -664,8 +664,8 @@ static int fsl_dspi_ofdata_to_platdata(struct udevice *bus)
plat-speed_hz = fdtdec_get_int(blob,
node, spi-max-frequency, FSL_DSPI_DEFAULT_SCK_FREQ);
 
-   debug(DSPI: regs=0x%x, max-frequency=%d, endianess=%s, num-cs=%d\n,
- plat-regs_addr, plat-speed_hz,
+   debug(DSPI: regs=0x%llx, max-frequency=%d, endianess=%s, num-cs=%d\n,
+ (u64)plat-regs_addr, plat-speed_hz,
  plat-flags  DSPI_FLAG_REGMAP_ENDIAN_BIG ? be : le,
  plat-num_chipselect);
 
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 80b897a..aeb9237 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -102,8 +102,8 @@ fdt_addr_t fdtdec_get_addr_size(const void *blob, int node,
size = (fdt_size_t *)((char *)cell +
sizeof(fdt_addr_t));
*sizep = fdt_size_to_cpu(*size);
-   debug(addr=%08lx, size=%08x\n,
- (ulong)addr, *sizep);
+   debug(addr=%08lx, size=%llx\n,
+ (ulong)addr, (u64)*sizep);
} else {
debug(%08lx\n, (ulong)addr);
}
-- 
1.9.1

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[U-Boot] [PATCH v4 3/5] arm: ls102xa: Enable Driver Model SPI for ls1021aqds

[Haikun Wang]

Enable Driver Model SPI for ls1021aqds board.
DSPI and QSPI is enabled only when boot from QSPI.
DSPI and QSPI are compatible under Driver Model SPI.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
Changes in v4:
- Add defconfig patch in this series

Changes in v3:
- Remove CONFIG_SPI_FLASH_ATMEL
- IS_ENABLED(CONFIG_XXX) is only work with configure option in Kconfig,
  and DM core code use IS_ENABLED(), so configure option in head file
  can't work, so remove CONFIG_OF_CONTROL CONFIG_OF_SEPARATE CONFIG_DM 
CONFIG_DM_SPI

Changes in v2:
- Move all changes inside of CONFIG_QSPI_BOOT 

Changes in v1: None
 include/configs/ls1021aqds.h | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 9a8fd50..55f52e8 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -409,16 +409,25 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
-/* QSPI */
+/* SPI */
 #ifdef CONFIG_QSPI_BOOT
+/* QSPI */
 #define CONFIG_FSL_QSPI
 #define QSPI0_AMBA_BASE0x4000
 #define FSL_QSPI_FLASH_SIZE(1  24)
 #define FSL_QSPI_FLASH_NUM 2
+#define CONFIG_SPI_FLASH_SPANSION
 
+/* DSPI */
+#define CONFIG_FSL_DSPI
+
+/* DM SPI */
+#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 #define CONFIG_CMD_SF
+#define CONFIG_DM_SPI_FLASH
 #define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SF_DATAFLASH
+#endif
 #endif
 
 /*
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 06/12] fdt: armv8: Fix build warnings on armv8

[Haikun Wang]

From: Haikun Wang haikun.w...@freescale.com

Fix below build warnings on armv8,
drivers/spi/fsl_dspi.c: In function ‘fsl_dspi_ofdata_to_platdata’:
drivers/spi/fsl_dspi.c:667:2:
warning: format ‘%x’ expects argument of type ‘unsigned int’,
but argument 2 has type ‘fdt_addr_t’ [-Wformat=]
debug(DSPI: regs=0x%x, max-frequency=%d, endianess=%s, num-cs=%d\n,
^
lib/fdtdec.c: In function ‘fdtdec_get_addr_size’:
lib/fdtdec.c:105:4:
warning: format ‘%lx’ expects argument of type ‘long unsigned int’,
but argument 3 has type ‘fdt_size_t’ [-Wformat=]
debug(addr=%08lx, size=%08lx\n,
^

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 drivers/spi/fsl_dspi.c | 4 ++--
 lib/fdtdec.c   | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c
index 6476f91..7928531 100644
--- a/drivers/spi/fsl_dspi.c
+++ b/drivers/spi/fsl_dspi.c
@@ -664,8 +664,8 @@ static int fsl_dspi_ofdata_to_platdata(struct udevice *bus)
plat-speed_hz = fdtdec_get_int(blob,
node, spi-max-frequency, FSL_DSPI_DEFAULT_SCK_FREQ);
 
-   debug(DSPI: regs=0x%x, max-frequency=%d, endianess=%s, num-cs=%d\n,
- plat-regs_addr, plat-speed_hz,
+   debug(DSPI: regs=0x%llx, max-frequency=%d, endianess=%s, num-cs=%d\n,
+ (u64)plat-regs_addr, plat-speed_hz,
  plat-flags  DSPI_FLAG_REGMAP_ENDIAN_BIG ? be : le,
  plat-num_chipselect);
 
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 80b897a..aeb9237 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -102,8 +102,8 @@ fdt_addr_t fdtdec_get_addr_size(const void *blob, int node,
size = (fdt_size_t *)((char *)cell +
sizeof(fdt_addr_t));
*sizep = fdt_size_to_cpu(*size);
-   debug(addr=%08lx, size=%08x\n,
- (ulong)addr, *sizep);
+   debug(addr=%08lx, size=%llx\n,
+ (ulong)addr, (u64)*sizep);
} else {
debug(%08lx\n, (ulong)addr);
}
-- 
1.9.1

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[U-Boot] [PATCH 05/12] armv8: ls2085a: Enable DSPI get input clk form 'mxc_get_clock'

[Haikun Wang]

From: Haikun Wang haikun.w...@freescale.com

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 arch/arm/cpu/armv8/fsl-lsch3/speed.c| 2 ++
 arch/arm/include/asm/arch-fsl-lsch3/clock.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c 
b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
index cac4f92..d9f137c 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
@@ -180,6 +180,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
switch (clk) {
case MXC_I2C_CLK:
return get_bus_freq(0) / 2;
+   case MXC_DSPI_CLK:
+   return get_bus_freq(0) / 2;
default:
printf(Unsupported clock\n);
}
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/clock.h 
b/arch/arm/include/asm/arch-fsl-lsch3/clock.h
index 831af0b..62bc53c 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/clock.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/clock.h
@@ -16,6 +16,7 @@ enum mxc_clock {
MXC_UART_CLK,
MXC_ESDHC_CLK,
MXC_I2C_CLK,
+   MXC_DSPI_CLK,
 };
 
 unsigned int mxc_get_clock(enum mxc_clock clk);
-- 
1.9.1

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[U-Boot] [PATCH 1/3] dm: dts: ls2085a: Bring in ls2085a dts files from linux kernel

[Haikun Wang]

From: Haikun Wang haikun.w...@freescale.com

Bring in required device tree files for ls2085a from Linux.
These are initially unchanged and have a number of pieces not needed by U-Boot.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 arch/arm/dts/fsl-ls2085a.dtsi | 120 ++
 1 file changed, 120 insertions(+)
 create mode 100644 arch/arm/dts/fsl-ls2085a.dtsi

diff --git a/arch/arm/dts/fsl-ls2085a.dtsi b/arch/arm/dts/fsl-ls2085a.dtsi
new file mode 100644
index 000..f0679a8
--- /dev/null
+++ b/arch/arm/dts/fsl-ls2085a.dtsi
@@ -0,0 +1,120 @@
+/*
+ * Freescale ls2085a SOC common device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/ {
+   compatible = fsl,ls2085a;
+   interrupt-parent = gic;
+   #address-cells = 2;
+   #size-cells = 2;
+
+   cpus {
+   #address-cells = 2;
+   #size-cells = 0;
+
+   /*
+* We expect the enable-method for cpu's to be psci, but this
+* is dependent on the SoC FW, which will fill this in.
+*
+* Currently supported enable-method is psci v0.2
+*/
+
+   /* We have 4 clusters having 2 Cortex-A57 cores each */
+   cpu@0 {
+   device_type = cpu;
+   compatible = arm,cortex-a57;
+   reg = 0x0 0x0;
+   };
+
+   cpu@1 {
+   device_type = cpu;
+   compatible = arm,cortex-a57;
+   reg = 0x0 0x1;
+   };
+
+   cpu@100 {
+   device_type = cpu;
+   compatible = arm,cortex-a57;
+   reg = 0x0 0x100;
+   };
+
+   cpu@101 {
+   device_type = cpu;
+   compatible = arm,cortex-a57;
+   reg = 0x0 0x101;
+   };
+
+   cpu@200 {
+   device_type = cpu;
+   compatible = arm,cortex-a57;
+   reg = 0x0 0x200;
+   };
+
+   cpu@201 {
+   device_type = cpu;
+   compatible = arm,cortex-a57;
+   reg = 0x0 0x201;
+   };
+
+   cpu@300 {
+   device_type = cpu;
+   compatible = arm,cortex-a57;
+   reg = 0x0 0x300;
+   };
+
+   cpu@301 {
+   device_type = cpu;
+   compatible = arm,cortex-a57;
+   reg = 0x0 0x301;
+   };
+   };
+
+   memory@8000 {
+   device_type = memory;
+   reg = 0x 0x8000 0 0x8000;
+ /* DRAM space - 1, size : 2 GB DRAM */
+   };
+
+   gic: interrupt-controller@600 {
+   compatible = arm,gic-v3;
+   reg = 0x0 0x0600 0 0x1, /* GIC Dist */
+ 0x0 0x0610 0 0x10; /* GICR (RD_base + SGI_base) 
*/
+   #interrupt-cells = 3;
+   interrupt-controller;
+   interrupts = 1 9 0x4;
+   };
+
+   timer {
+   compatible = arm,armv8-timer;
+   interrupts = 1 13 0x8, /* Physical Secure PPI, active-low */
+1 14 0x8, /* Physical Non-Secure PPI, active-low 
*/
+1 11 0x8, /* Virtual PPI, active-low */
+1 10 0x8; /* Hypervisor PPI, active-low */
+   };
+
+   serial0: serial@21c0500 {
+   device_type = serial;
+   compatible = fsl,ns16550, ns16550a;
+   reg = 0x0 0x21c0500 0x0 0x100;
+   clock-frequency = 0;  /* Updated by bootloader */
+   interrupts = 0 32 0x1; /* edge triggered */
+   };
+
+   serial1: serial@21c0600 {
+   device_type = serial;
+   compatible = fsl,ns16550, ns16550a;
+   reg = 0x0 0x21c0600 0x0 0x100;
+   clock-frequency = 0;  /* Updated by bootloader */
+   interrupts = 0 32 0x1; /* edge triggered */
+   };
+
+   fsl_mc: fsl-mc@80c00 {
+   compatible = fsl,qoriq-mc;
+   reg = 0x0008 0x0c00 0 0x40,/* MC portal base */
+ 0x 0x0834 0 0x4; /* MC control reg */
+   };
+};
-- 
1.9.1

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[U-Boot] [PATCH 2/3] dm: dts: ls2085a: Add DSPI dts node

[Haikun Wang]

From: Haikun Wang haikun.w...@freescale.com

Add DSPI controller dts node in fsl-ls2085a.dtsi

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 arch/arm/dts/fsl-ls2085a.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/dts/fsl-ls2085a.dtsi b/arch/arm/dts/fsl-ls2085a.dtsi
index f0679a8..96404c5 100644
--- a/arch/arm/dts/fsl-ls2085a.dtsi
+++ b/arch/arm/dts/fsl-ls2085a.dtsi
@@ -117,4 +117,13 @@
reg = 0x0008 0x0c00 0 0x40,/* MC portal base */
  0x 0x0834 0 0x4; /* MC control reg */
};
+
+   dspi: dspi@210 {
+   compatible = fsl,vf610-dspi;
+   #address-cells = 1;
+   #size-cells = 0;
+   reg = 0x0 0x210 0x0 0x1;
+   interrupts = 0 26 0x4; /* Level high type */
+   num-cs = 6;
+   };
 };
-- 
1.9.1

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[U-Boot] [PATCH 3/3] dm: dts: ls2085a: Add dts files for LS2085AQDS and LS2085ARDB

[Haikun Wang]

From: Haikun Wang haikun.w...@freescale.com

Add dts source files for LS2085AQDS and LS2085ARDB boards.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 arch/arm/dts/Makefile|  2 ++
 arch/arm/dts/fsl-ls2085a-qds.dts | 53 
 arch/arm/dts/fsl-ls2085a-rdb.dts | 35 ++
 3 files changed, 90 insertions(+)
 create mode 100644 arch/arm/dts/fsl-ls2085a-qds.dts
 create mode 100644 arch/arm/dts/fsl-ls2085a-rdb.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 15d60b9..2b64851 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -56,6 +56,8 @@ dtb-$(CONFIG_SOCFPGA) +=  \
 
 dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
ls1021a-twr.dtb
+dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \
+   fsl-ls2085a-rdb.dtb
 
 dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
diff --git a/arch/arm/dts/fsl-ls2085a-qds.dts b/arch/arm/dts/fsl-ls2085a-qds.dts
new file mode 100644
index 000..4477e54
--- /dev/null
+++ b/arch/arm/dts/fsl-ls2085a-qds.dts
@@ -0,0 +1,53 @@
+/*
+ * Freescale ls2085a QDS board device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include fsl-ls2085a.dtsi
+
+/ {
+   model = Freescale Layerscape 2085a QDS Board;
+   compatible = fsl,ls2085a-qds, fsl,ls2085a;
+
+   aliases {
+   spi1 = dspi;
+   };
+};
+
+dspi {
+   bus-num = 0;
+   status = okay;
+
+   dflash0: n25q128a {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = spi-flash;
+   spi-max-frequency = 300;
+   spi-cpol;
+   spi-cpha;
+   reg = 0;
+   };
+   dflash1: sst25wf040b {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = spi-flash;
+   spi-max-frequency = 300;
+   spi-cpol;
+   spi-cpha;
+   reg = 1;
+   };
+   dflash2: en25s64 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = spi-flash;
+   spi-max-frequency = 300;
+   spi-cpol;
+   spi-cpha;
+   reg = 2;
+   };
+};
diff --git a/arch/arm/dts/fsl-ls2085a-rdb.dts b/arch/arm/dts/fsl-ls2085a-rdb.dts
new file mode 100644
index 000..25278df
--- /dev/null
+++ b/arch/arm/dts/fsl-ls2085a-rdb.dts
@@ -0,0 +1,35 @@
+/*
+ * Freescale ls2085a RDB board device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include fsl-ls2085a.dtsi
+
+/ {
+   model = Freescale Layerscape 2085a RDB Board;
+   compatible = fsl,ls2085a-rdb, fsl,ls2085a;
+
+   aliases {
+   spi1 = dspi;
+   };
+};
+
+dspi {
+   bus-num = 0;
+   status = okay;
+
+   dflash0: n25q512a {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = spi-flash;
+   spi-max-frequency = 300;
+   spi-cpol;
+   spi-cpha;
+   reg = 0;
+   };
+};
-- 
1.9.1

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[U-Boot] [PATCH] armv8: ls2085a: Enable DSPI get input clk form 'mxc_get_clock'

[Haikun Wang]

From: Haikun Wang haikun.w...@freescale.com

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 arch/arm/cpu/armv8/fsl-lsch3/speed.c| 2 ++
 arch/arm/include/asm/arch-fsl-lsch3/clock.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c 
b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
index cac4f92..d9f137c 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
@@ -180,6 +180,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
switch (clk) {
case MXC_I2C_CLK:
return get_bus_freq(0) / 2;
+   case MXC_DSPI_CLK:
+   return get_bus_freq(0) / 2;
default:
printf(Unsupported clock\n);
}
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/clock.h 
b/arch/arm/include/asm/arch-fsl-lsch3/clock.h
index 831af0b..62bc53c 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/clock.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/clock.h
@@ -16,6 +16,7 @@ enum mxc_clock {
MXC_UART_CLK,
MXC_ESDHC_CLK,
MXC_I2C_CLK,
+   MXC_DSPI_CLK,
 };
 
 unsigned int mxc_get_clock(enum mxc_clock clk);
-- 
1.9.1

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[U-Boot] [PATCH v2] arm: ls102xa: Enable CONFIG_DEFAULT_DEVICE_TREE to defconfig for ls1021a

[Haikun Wang]

Enable CONFIG_OF_CONTROL and define CONFIG_DEFAULT_DEVICE_TREE in
ls1021axxx_qspi_defconfig.
DSPI and QSPI have converted to Driver Model.
Those options are needed by Driver Model driver.
DSPI and QSPI are only enabled when boot from QSPI.
So this patch only enable those optipns when boot from QSPI.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---

Changes in v2:
- Enable CONFIG_OF_CONTROL
- Using the savedefconfig feature
- Only Changeing the defconfig when boot from QSPI

Changes in v1: None

 configs/ls1021aqds_qspi_defconfig | 2 ++
 configs/ls1021atwr_qspi_defconfig | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/configs/ls1021aqds_qspi_defconfig 
b/configs/ls1021aqds_qspi_defconfig
index ee3f5ca..338b0cd 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -1,3 +1,5 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE=ls1021a-qds
 CONFIG_SYS_EXTRA_OPTIONS=QSPI_BOOT
+CONFIG_OF_CONTROL=y
diff --git a/configs/ls1021atwr_qspi_defconfig 
b/configs/ls1021atwr_qspi_defconfig
index 57e180d..34e47a9 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -1,3 +1,5 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
+CONFIG_DEFAULT_DEVICE_TREE=ls1021a-twr
 CONFIG_SYS_EXTRA_OPTIONS=QSPI_BOOT
+CONFIG_OF_CONTROL=y
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v5 1/4] dm: sf: Add Atmel DataFlash spi flash driver

[Haikun Wang]

Atmel DataFlash chips have commands different from common spi
flash commands.
Atmel DataFlash also have special page-size.
This driver add support for accessing Atmel DataFlash.
It is based on the Driver Model.
Example:
= sf probe 1:0
SPI DataFlash: Detected AT45DB021B with page size 264 Bytes, erase size 264 
Bytes, total 264 KiB, revision d
= sf erase 0 42000
SF: 270336 bytes @ 0x0 Erased: OK
= mw.l 8200 45444342 2
= sf write 8200 0 42000
SF: 270336 bytes @ 0x0 Written: OK
= sf read 8300 0 42000
SF: 270336 bytes @ 0x0 Read: OK
= cmp.b 8200 8300 42000
Total of 270336 byte(s) were the same

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
Verified with AT45DB021B on LS1021AQDS.
Changes in v5:
- Change CONFIG_DM_SF_DATAFLASH to CONFIG_SF_DATAFLASH

Changes in v4:
- Use dev_get_priv and dev_get_uclass_priv
- Add test log to commit message

Changes in v3:
- 1. Rename file spi_dataflash.c to sf_dataflash.c
- 2. Add comment for array dataflash_data

Changes in v2:
- 1. Correct comment style
- 2. Use get_timer in dataflash_waitready to check whether timeout
- 3. Remove struct spi_flash * in struct dataflash, and get it from 
udevice-uclass_priv
- 4. Replace spi_flash_write_common with spi_flash_cmd_write 
- 5. Replace spi_flash_read with spi_flash_cmd_read 
- 6. Change type of varible status form char to u8 in dataflash_status
- 7. Change add_dataflash's argument type due to change 3
- 8. Add claim_bus and release_bus in erase/write/read due to change 4  5

Changes in v1: None
 drivers/mtd/spi/Makefile   |   1 +
 drivers/mtd/spi/sf_dataflash.c | 711 +
 2 files changed, 712 insertions(+)
 create mode 100644 drivers/mtd/spi/sf_dataflash.c

diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index c61b784..87f20bc 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -15,6 +15,7 @@ endif
 #ifndef CONFIG_DM_SPI
 obj-$(CONFIG_SPI_FLASH) += sf_probe.o
 #endif
+obj-$(CONFIG_SF_DATAFLASH) += sf_dataflash.o
 obj-$(CONFIG_CMD_SF) += sf.o
 obj-$(CONFIG_SPI_FLASH) += sf_ops.o sf_params.o
 obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
new file mode 100644
index 000..d287db8
--- /dev/null
+++ b/drivers/mtd/spi/sf_dataflash.c
@@ -0,0 +1,711 @@
+/*
+ *
+ * Atmel DataFlash probing
+ *
+ * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
+ * Haikun Wang (haikun.w...@freescale.com)
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+*/
+#include common.h
+#include dm.h
+#include errno.h
+#include fdtdec.h
+#include spi.h
+#include spi_flash.h
+#include div64.h
+#include linux/err.h
+#include linux/math64.h
+
+#include sf_internal.h
+
+/*
+ * DataFlash is a kind of SPI flash.  Most AT45 chips have two buffers in
+ * each chip, which may be used for double buffered I/O; but this driver
+ * doesn't (yet) use these for any kind of i/o overlap or prefetching.
+ *
+ * Sometimes DataFlash is packaged in MMC-format cards, although the
+ * MMC stack can't (yet?) distinguish between MMC and DataFlash
+ * protocols during enumeration.
+ */
+
+/* reads can bypass the buffers */
+#define OP_READ_CONTINUOUS 0xE8
+#define OP_READ_PAGE   0xD2
+
+/* group B requests can run even while status reports busy */
+#define OP_READ_STATUS 0xD7/* group B */
+
+/* move data between host and buffer */
+#define OP_READ_BUFFER10xD4/* group B */
+#define OP_READ_BUFFER20xD6/* group B */
+#define OP_WRITE_BUFFER1   0x84/* group B */
+#define OP_WRITE_BUFFER2   0x87/* group B */
+
+/* erasing flash */
+#define OP_ERASE_PAGE  0x81
+#define OP_ERASE_BLOCK 0x50
+
+/* move data between buffer and flash */
+#define OP_TRANSFER_BUF1   0x53
+#define OP_TRANSFER_BUF2   0x55
+#define OP_MREAD_BUFFER1   0xD4
+#define OP_MREAD_BUFFER2   0xD6
+#define OP_MWERASE_BUFFER1 0x83
+#define OP_MWERASE_BUFFER2 0x86
+#define OP_MWRITE_BUFFER1  0x88/* sector must be pre-erased */
+#define OP_MWRITE_BUFFER2  0x89/* sector must be pre-erased */
+
+/* write to buffer, then write-erase to flash */
+#define OP_PROGRAM_VIA_BUF10x82
+#define OP_PROGRAM_VIA_BUF20x85
+
+/* compare buffer to flash */
+#define OP_COMPARE_BUF10x60
+#define OP_COMPARE_BUF20x61
+
+/* read flash to buffer, then write-erase to flash */
+#define OP_REWRITE_VIA_BUF10x58
+#define OP_REWRITE_VIA_BUF20x59
+
+/*
+ * newer chips report JEDEC manufacturer and device IDs; chip
+ * serial number and OTP bits; and per-sector writeprotect.
+ */
+#define OP_READ_ID 0x9F
+#define OP_READ_SECURITY   0x77
+#define OP_WRITE_SECURITY_REVC 0x9A
+#define OP_WRITE_SECURITY  0x9B/* revision D */
+
+
+struct dataflash {
+   uint8_t command[16];
+   unsigned short  page_offset;/* offset in flash address

[U-Boot] [PATCH v1 2/4] dm: ls1021aqds: dts: Use spi_dataflash driver instead of spi_flash_std for DSPI flash

[Haikun Wang]

The type of DSPI flash on ls1021aqds is AT45DB021, it has specail
commands and page-size.
Use the special spi flash driver instead of spi_flash_std driver.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 arch/arm/dts/ls1021a-qds.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dts
index 8367811..e634292 100644
--- a/arch/arm/dts/ls1021a-qds.dts
+++ b/arch/arm/dts/ls1021a-qds.dts
@@ -30,7 +30,7 @@
dspiflash: at45db021d@0 {
#address-cells = 1;
#size-cells = 1;
-   compatible = spi-flash;
+   compatible = atmel,dataflash;
spi-max-frequency = 1600;
spi-cpol;
spi-cpha;
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v3 3/4] arm: ls102xa: Enable Driver Model SPI for ls1021aqds

[Haikun Wang]

Enable Driver Model SPI for ls1021aqds board.
DSPI and QSPI is enabled only when boot from QSPI.
DSPI and QSPI are compatible under Driver Model SPI.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
Changes in v3:
- Remove CONFIG_SPI_FLASH_ATMEL
- IS_ENABLED(CONFIG_XXX) is only work with configure option in Kconfig,
  and DM core code use IS_ENABLED(), so configure option in head file
  can't work, so remove CONFIG_OF_CONTROL CONFIG_OF_SEPARATE CONFIG_DM 
CONFIG_DM_SPI

Changes in v2:
- Move all changes inside of CONFIG_QSPI_BOOT 

Changes in v1: None
 include/configs/ls1021aqds.h | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 9a8fd50..55f52e8 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -409,16 +409,25 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
-/* QSPI */
+/* SPI */
 #ifdef CONFIG_QSPI_BOOT
+/* QSPI */
 #define CONFIG_FSL_QSPI
 #define QSPI0_AMBA_BASE0x4000
 #define FSL_QSPI_FLASH_SIZE(1  24)
 #define FSL_QSPI_FLASH_NUM 2
+#define CONFIG_SPI_FLASH_SPANSION
 
+/* DSPI */
+#define CONFIG_FSL_DSPI
+
+/* DM SPI */
+#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 #define CONFIG_CMD_SF
+#define CONFIG_DM_SPI_FLASH
 #define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SF_DATAFLASH
+#endif
 #endif
 
 /*
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v3 4/4] arm: ls102xa: Enable Driver Model SPI for ls1021atwr

[Haikun Wang]

From: Haikun Wang haikun.w...@freescale.com

Enable Driver Model SPI for ls1021atwr board.
DSPI and QSPI only be enabled when boot from QSPI.
DSPI and QSPI are compatible under Driver Model SPI.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
Change-Id: I6342807da7725ae8b678952117c8758c75a61d3d
Reviewed-on: http://git.am.freescale.net:8181/33447
Tested-by: Review Code-CDREVIEW cdrev...@freescale.com
Reviewed-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes in v3:
- IS_ENABLED(CONFIG_XXX) is only work with configure option in Kconfig,
  and DM core code use IS_ENABLED(), so configure option in head file
  can't work, so remove CONFIG_OF_CONTROL CONFIG_OF_SEPARATE CONFIG_DM 
CONFIG_DM_SPI

Changes in v2:
- Move all changes inside of CONFIG_QSPI_BOOT 

Changes in v1: None
 include/configs/ls1021atwr.h | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 729205f..13e3aa4 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -229,16 +229,22 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
-/* QSPI */
+/* SPI */
 #ifdef CONFIG_QSPI_BOOT
+/* QSPI */
 #define CONFIG_FSL_QSPI
 #define QSPI0_AMBA_BASE0x4000
 #define FSL_QSPI_FLASH_SIZE(1  24)
 #define FSL_QSPI_FLASH_NUM 2
 
+#define CONFIG_SPI_FLASH_STMICRO
+
+/* DM SPI */
+#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 #define CONFIG_CMD_SF
+#define CONFIG_DM_SPI_FLASH
 #define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
+#endif
 #endif
 
 /*
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v4] dm: sf: Add Atmel DataFlash spi flash driver

[Haikun Wang]

Atmel DataFlash chips have commands different from common spi
flash commands.
Atmel DataFlash also have special page-size.
This driver add support for accessing Atmel DataFlash.
It is based on the Driver Model.
Example:
= sf probe 1:0
SPI DataFlash: Detected AT45DB021B with page size 264 Bytes, erase size 264 
Bytes, total 264 KiB, revision d
= sf erase 0 42000
SF: 270336 bytes @ 0x0 Erased: OK
= mw.l 8200 45444342 2
= sf write 8200 0 42000
SF: 270336 bytes @ 0x0 Written: OK
= sf read 8300 0 42000
SF: 270336 bytes @ 0x0 Read: OK
= cmp.b 8200 8300 42000
Total of 270336 byte(s) were the same

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
Verified with AT45DB021B on LS1021AQDS.

Changes in v4:
- Use dev_get_priv and dev_get_uclass_priv
- Add test log to commit message

Changes in v3:
- 1. Rename file spi_dataflash.c to sf_dataflash.c
- 2. Add comment for array dataflash_data

Changes in v2:
- 1. Correct comment style
- 2. Use get_timer in dataflash_waitready to check whether timeout
- 3. Remove struct spi_flash * in struct dataflash, and get it from 
udevice-uclass_priv
- 4. Replace spi_flash_write_common with spi_flash_cmd_write 
- 5. Replace spi_flash_read with spi_flash_cmd_read 
- 6. Change type of varible status form char to u8 in dataflash_status
- 7. Change add_dataflash's argument type due to change 3
- 8. Add claim_bus and release_bus in erase/write/read due to change 4  5

Changes in v1: None
 drivers/mtd/spi/Makefile   |   1 +
 drivers/mtd/spi/sf_dataflash.c | 711 +
 2 files changed, 712 insertions(+)
 create mode 100644 drivers/mtd/spi/sf_dataflash.c

diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index c61b784..8adec3d 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -15,6 +15,7 @@ endif
 #ifndef CONFIG_DM_SPI
 obj-$(CONFIG_SPI_FLASH) += sf_probe.o
 #endif
+obj-$(CONFIG_DM_SF_DATAFLASH) += sf_dataflash.o
 obj-$(CONFIG_CMD_SF) += sf.o
 obj-$(CONFIG_SPI_FLASH) += sf_ops.o sf_params.o
 obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
new file mode 100644
index 000..d287db8
--- /dev/null
+++ b/drivers/mtd/spi/sf_dataflash.c
@@ -0,0 +1,711 @@
+/*
+ *
+ * Atmel DataFlash probing
+ *
+ * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
+ * Haikun Wang (haikun.w...@freescale.com)
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+*/
+#include common.h
+#include dm.h
+#include errno.h
+#include fdtdec.h
+#include spi.h
+#include spi_flash.h
+#include div64.h
+#include linux/err.h
+#include linux/math64.h
+
+#include sf_internal.h
+
+/*
+ * DataFlash is a kind of SPI flash.  Most AT45 chips have two buffers in
+ * each chip, which may be used for double buffered I/O; but this driver
+ * doesn't (yet) use these for any kind of i/o overlap or prefetching.
+ *
+ * Sometimes DataFlash is packaged in MMC-format cards, although the
+ * MMC stack can't (yet?) distinguish between MMC and DataFlash
+ * protocols during enumeration.
+ */
+
+/* reads can bypass the buffers */
+#define OP_READ_CONTINUOUS 0xE8
+#define OP_READ_PAGE   0xD2
+
+/* group B requests can run even while status reports busy */
+#define OP_READ_STATUS 0xD7/* group B */
+
+/* move data between host and buffer */
+#define OP_READ_BUFFER10xD4/* group B */
+#define OP_READ_BUFFER20xD6/* group B */
+#define OP_WRITE_BUFFER1   0x84/* group B */
+#define OP_WRITE_BUFFER2   0x87/* group B */
+
+/* erasing flash */
+#define OP_ERASE_PAGE  0x81
+#define OP_ERASE_BLOCK 0x50
+
+/* move data between buffer and flash */
+#define OP_TRANSFER_BUF1   0x53
+#define OP_TRANSFER_BUF2   0x55
+#define OP_MREAD_BUFFER1   0xD4
+#define OP_MREAD_BUFFER2   0xD6
+#define OP_MWERASE_BUFFER1 0x83
+#define OP_MWERASE_BUFFER2 0x86
+#define OP_MWRITE_BUFFER1  0x88/* sector must be pre-erased */
+#define OP_MWRITE_BUFFER2  0x89/* sector must be pre-erased */
+
+/* write to buffer, then write-erase to flash */
+#define OP_PROGRAM_VIA_BUF10x82
+#define OP_PROGRAM_VIA_BUF20x85
+
+/* compare buffer to flash */
+#define OP_COMPARE_BUF10x60
+#define OP_COMPARE_BUF20x61
+
+/* read flash to buffer, then write-erase to flash */
+#define OP_REWRITE_VIA_BUF10x58
+#define OP_REWRITE_VIA_BUF20x59
+
+/*
+ * newer chips report JEDEC manufacturer and device IDs; chip
+ * serial number and OTP bits; and per-sector writeprotect.
+ */
+#define OP_READ_ID 0x9F
+#define OP_READ_SECURITY   0x77
+#define OP_WRITE_SECURITY_REVC 0x9A
+#define OP_WRITE_SECURITY  0x9B/* revision D */
+
+
+struct dataflash {
+   uint8_t command[16];
+   unsigned short  page_offset;/* offset in flash address */
+};
+
+/*
+ * Return the status of the DataFlash device.
+ */
+static

[U-Boot] [PATCH v2] dm: sf: Update default name of spi flash in structure udevice

[Haikun Wang]

Default name of spi flash like this 0:0, update it to spi_flash@0:0.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---

Changes in v2:
- Increase the size of array name to 30 

Changes in v1: None
 drivers/mtd/spi/sf-uclass.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c
index 4b25902..350e21a 100644
--- a/drivers/mtd/spi/sf-uclass.c
+++ b/drivers/mtd/spi/sf-uclass.c
@@ -53,10 +53,10 @@ int spi_flash_probe_bus_cs(unsigned int busnum, unsigned 
int cs,
 {
struct spi_slave *slave;
struct udevice *bus;
-   char name[20], *str;
+   char name[30], *str;
int ret;
 
-   snprintf(name, sizeof(name), %d:%d, busnum, cs);
+   snprintf(name, sizeof(name), spi_flash@%d:%d, busnum, cs);
str = strdup(name);
ret = spi_get_bus_and_cs(busnum, cs, max_hz, spi_mode,
  spi_flash_std, str, bus, slave);
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v3] dm: sf: Add Atmel DataFlash spi flash driver

[Haikun Wang]

Atmel DataFlash chips have commands different from common spi
flash commands.
Atmel DataFlash also have special page-size.
This driver add support for accessing Atmel DataFlash.
It is based on the Driver Model.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
Verified with AT45DB021B.

Changes in v3:
- 1. Rename file spi_dataflash.c to sf_dataflash.c
- 2. Add comment for array dataflash_data

Changes in v2:
- 1. Correct comment style
- 2. Use get_timer in dataflash_waitready to check whether timeout
- 3. Remove struct spi_flash * in struct dataflash, and get it from 
udevice-uclass_priv
- 4. Replace spi_flash_write_common with spi_flash_cmd_write 
- 5. Replace spi_flash_read with spi_flash_cmd_read 
- 6. Change type of varible status form char to u8 in dataflash_status
- 7. Change add_dataflash's argument type due to change 3
- 8. Add claim_bus and release_bus in erase/write/read due to change 4  5

Changes in v1: None
 drivers/mtd/spi/Makefile   |   1 +
 drivers/mtd/spi/sf_dataflash.c | 711 +
 2 files changed, 712 insertions(+)
 create mode 100644 drivers/mtd/spi/sf_dataflash.c

diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index c61b784..8adec3d 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -15,6 +15,7 @@ endif
 #ifndef CONFIG_DM_SPI
 obj-$(CONFIG_SPI_FLASH) += sf_probe.o
 #endif
+obj-$(CONFIG_DM_SF_DATAFLASH) += sf_dataflash.o
 obj-$(CONFIG_CMD_SF) += sf.o
 obj-$(CONFIG_SPI_FLASH) += sf_ops.o sf_params.o
 obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
new file mode 100644
index 000..817a9be
--- /dev/null
+++ b/drivers/mtd/spi/sf_dataflash.c
@@ -0,0 +1,711 @@
+/*
+ *
+ * Atmel DataFlash probing
+ *
+ * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
+ * Haikun Wang (haikun.w...@freescale.com)
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+*/
+#include common.h
+#include dm.h
+#include errno.h
+#include fdtdec.h
+#include spi.h
+#include spi_flash.h
+#include div64.h
+#include linux/err.h
+#include linux/math64.h
+
+#include sf_internal.h
+
+/*
+ * DataFlash is a kind of SPI flash.  Most AT45 chips have two buffers in
+ * each chip, which may be used for double buffered I/O; but this driver
+ * doesn't (yet) use these for any kind of i/o overlap or prefetching.
+ *
+ * Sometimes DataFlash is packaged in MMC-format cards, although the
+ * MMC stack can't (yet?) distinguish between MMC and DataFlash
+ * protocols during enumeration.
+ */
+
+/* reads can bypass the buffers */
+#define OP_READ_CONTINUOUS 0xE8
+#define OP_READ_PAGE   0xD2
+
+/* group B requests can run even while status reports busy */
+#define OP_READ_STATUS 0xD7/* group B */
+
+/* move data between host and buffer */
+#define OP_READ_BUFFER10xD4/* group B */
+#define OP_READ_BUFFER20xD6/* group B */
+#define OP_WRITE_BUFFER1   0x84/* group B */
+#define OP_WRITE_BUFFER2   0x87/* group B */
+
+/* erasing flash */
+#define OP_ERASE_PAGE  0x81
+#define OP_ERASE_BLOCK 0x50
+
+/* move data between buffer and flash */
+#define OP_TRANSFER_BUF1   0x53
+#define OP_TRANSFER_BUF2   0x55
+#define OP_MREAD_BUFFER1   0xD4
+#define OP_MREAD_BUFFER2   0xD6
+#define OP_MWERASE_BUFFER1 0x83
+#define OP_MWERASE_BUFFER2 0x86
+#define OP_MWRITE_BUFFER1  0x88/* sector must be pre-erased */
+#define OP_MWRITE_BUFFER2  0x89/* sector must be pre-erased */
+
+/* write to buffer, then write-erase to flash */
+#define OP_PROGRAM_VIA_BUF10x82
+#define OP_PROGRAM_VIA_BUF20x85
+
+/* compare buffer to flash */
+#define OP_COMPARE_BUF10x60
+#define OP_COMPARE_BUF20x61
+
+/* read flash to buffer, then write-erase to flash */
+#define OP_REWRITE_VIA_BUF10x58
+#define OP_REWRITE_VIA_BUF20x59
+
+/*
+ * newer chips report JEDEC manufacturer and device IDs; chip
+ * serial number and OTP bits; and per-sector writeprotect.
+ */
+#define OP_READ_ID 0x9F
+#define OP_READ_SECURITY   0x77
+#define OP_WRITE_SECURITY_REVC 0x9A
+#define OP_WRITE_SECURITY  0x9B/* revision D */
+
+
+struct dataflash {
+   uint8_t command[16];
+   unsigned short  page_offset;/* offset in flash address */
+};
+
+/*
+ * Return the status of the DataFlash device.
+ */
+static inline int dataflash_status(struct spi_slave *spi)
+{
+   int ret;
+   u8 status;
+   /*
+* NOTE:  at45db321c over 25 MHz wants to write
+* a dummy byte after the opcode...
+*/
+   ret = spi_flash_cmd(spi, OP_READ_STATUS, status, 1);
+   return ret ? -EIO : status;
+}
+
+/*
+ * Poll the DataFlash device until it is READY.
+ * This usually takes 5-20 msec or so; more for sector erase.
+ * ready: return  0
+ */
+static int dataflash_waitready(struct spi_slave *spi

[U-Boot] [PATCH v1 1/2] cmd_sf: Add command sf info to show current device info

[Haikun Wang]

Add command sf info to show the information of the current SPI flash device.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
In current sf driver, we show the debug information during the flash probe
period.

In case of without DM SPI, we need to run command sf probe to get the debug
information of the current SPI flash device. sf probe will re-identify the
device every time and it reduce the efficiency. We can get the debug information
without any re-identify process using sf info.

In case of using DM SPI, if we disable CONFIG_DM_DEVICE_REMOVE sf probe will
only call the flash driver's probe function the first time you run it and no
information will show after the first. It is recommended that only call the
flash driver's probe function once during u-boot period. You can get the debug
information using sf info in this case.

Changes in v1: None.

 common/cmd_sf.c | 43 ++-
 1 file changed, 42 insertions(+), 1 deletion(-)

diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 6aabf39..38841fa 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -503,6 +503,44 @@ static int do_spi_flash_test(int argc, char * const argv[])
 }
 #endif /* CONFIG_CMD_SF_TEST */
 
+static int do_spi_flash_info(struct spi_flash *flash, bool dm_column_style)
+{
+   if (dm_column_style) {
+   struct udevice *bus;
+   struct udevice *dev;
+   struct dm_spi_slave_platdata *plat;
+
+   dev = flash-dev;
+   bus = dev-parent;
+   plat = dev_get_parent_platdata(dev);
+
+   printf(Device: %s\n, dev-name);
+   printf(Chipselect: %d\n, plat-cs);
+   printf(Bind Driver: %s\n, dev-driver-name);
+   printf(SPI bus: %s\n, bus-name);
+   printf(SPI bus number: %d\n, bus-seq);
+   printf(Flash type: %s\n, flash-name);
+   printf(Page size: );
+   print_size(flash-page_size, \n);
+   printf(Erase size: );
+   print_size(flash-erase_size, \n);
+   printf(Total size: );
+   print_size(flash-size, \n);
+   if (flash-memory_map)
+   printf(Mapped at %p\n, flash-memory_map);
+   } else {
+   printf(SF: Detected %s with page size , flash-name);
+   print_size(flash-page_size, , erase size );
+   print_size(flash-erase_size, , total );
+   print_size(flash-size, );
+   if (flash-memory_map)
+   printf(, mapped at %p, flash-memory_map);
+   puts(\n);
+   }
+
+   return 0;
+}
+
 static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
 {
@@ -537,6 +575,8 @@ static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int 
argc,
else if (!strcmp(cmd, test))
ret = do_spi_flash_test(argc, argv);
 #endif
+   else if (!strcmp(cmd, info))
+   ret = do_spi_flash_info(flash, IS_ENABLED(CONFIG_DM_SPI_FLASH));
else
ret = -1;
 
@@ -567,6 +607,7 @@ U_BOOT_CMD(
sf erase offset [+]len - erase `len' bytes from `offset'\n
 `+len' round up `len' to block size\n
sf update addr offset len  - erase and write `len' bytes from 
memory\n
-at `addr' to flash at `offset'
+at `addr' to flash at `offset'\n
+   sf info - display info of the current SPI Flash device\n
SF_TEST_HELP
 );
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v1 2/2] dm: sf: Update default name of spi flash in structure udevice

[Haikun Wang]

Default name of spi flash like this 0:0, update it to spi_flash@0:0.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 drivers/mtd/spi/sf-uclass.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c
index 4b25902..e5612f7 100644
--- a/drivers/mtd/spi/sf-uclass.c
+++ b/drivers/mtd/spi/sf-uclass.c
@@ -56,7 +56,7 @@ int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int 
cs,
char name[20], *str;
int ret;
 
-   snprintf(name, sizeof(name), %d:%d, busnum, cs);
+   snprintf(name, sizeof(name), spi_flash@%d:%d, busnum, cs);
str = strdup(name);
ret = spi_get_bus_and_cs(busnum, cs, max_hz, spi_mode,
  spi_flash_std, str, bus, slave);
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2] dm: sf: Add Atmel DataFlash spi flash driver

[Haikun Wang]

Atmel DataFlash chips have commands different from common spi
flash commands.
Atmel DataFlash also have special page-size.
This driver add support for accessing Atmel DataFlash.
It is based on the Driver Model.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
Verified with AT45DB021B.

Changes in v2:
- 1. Correct comment style
- 2. Use get_timer in dataflash_waitready to check whether timeout
- 3. Remove struct spi_flash * in struct dataflash, and get it from 
udevice-uclass_priv
- 4. Replace spi_flash_write_common with spi_flash_cmd_write 
- 5. Replace spi_flash_read with spi_flash_cmd_read 
- 6. Change type of varible status form char to u8 in dataflash_status
- 7. Change add_dataflash's argument type due to change 3
- 8. Add claim_bus and release_bus in erase/write/read due to change 5  6

Changes in v1: None
 drivers/mtd/spi/Makefile|   1 +
 drivers/mtd/spi/spi_dataflash.c | 704 
 2 files changed, 705 insertions(+)
 create mode 100644 drivers/mtd/spi/spi_dataflash.c

diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index c61b784..42acd24 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -15,6 +15,7 @@ endif
 #ifndef CONFIG_DM_SPI
 obj-$(CONFIG_SPI_FLASH) += sf_probe.o
 #endif
+obj-$(CONFIG_DM_SPI_DATAFLASH) += spi_dataflash.o
 obj-$(CONFIG_CMD_SF) += sf.o
 obj-$(CONFIG_SPI_FLASH) += sf_ops.o sf_params.o
 obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
diff --git a/drivers/mtd/spi/spi_dataflash.c b/drivers/mtd/spi/spi_dataflash.c
new file mode 100644
index 000..c68cf2e
--- /dev/null
+++ b/drivers/mtd/spi/spi_dataflash.c
@@ -0,0 +1,704 @@
+/*
+ *
+ * Atmel DataFlash probing
+ *
+ * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
+ * Haikun Wang (haikun.w...@freescale.com)
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+*/
+#include common.h
+#include dm.h
+#include errno.h
+#include fdtdec.h
+#include spi.h
+#include spi_flash.h
+#include div64.h
+#include linux/err.h
+#include linux/math64.h
+
+#include sf_internal.h
+
+/*
+ * DataFlash is a kind of SPI flash.  Most AT45 chips have two buffers in
+ * each chip, which may be used for double buffered I/O; but this driver
+ * doesn't (yet) use these for any kind of i/o overlap or prefetching.
+ *
+ * Sometimes DataFlash is packaged in MMC-format cards, although the
+ * MMC stack can't (yet?) distinguish between MMC and DataFlash
+ * protocols during enumeration.
+ */
+
+/* reads can bypass the buffers */
+#define OP_READ_CONTINUOUS 0xE8
+#define OP_READ_PAGE   0xD2
+
+/* group B requests can run even while status reports busy */
+#define OP_READ_STATUS 0xD7/* group B */
+
+/* move data between host and buffer */
+#define OP_READ_BUFFER10xD4/* group B */
+#define OP_READ_BUFFER20xD6/* group B */
+#define OP_WRITE_BUFFER1   0x84/* group B */
+#define OP_WRITE_BUFFER2   0x87/* group B */
+
+/* erasing flash */
+#define OP_ERASE_PAGE  0x81
+#define OP_ERASE_BLOCK 0x50
+
+/* move data between buffer and flash */
+#define OP_TRANSFER_BUF1   0x53
+#define OP_TRANSFER_BUF2   0x55
+#define OP_MREAD_BUFFER1   0xD4
+#define OP_MREAD_BUFFER2   0xD6
+#define OP_MWERASE_BUFFER1 0x83
+#define OP_MWERASE_BUFFER2 0x86
+#define OP_MWRITE_BUFFER1  0x88/* sector must be pre-erased */
+#define OP_MWRITE_BUFFER2  0x89/* sector must be pre-erased */
+
+/* write to buffer, then write-erase to flash */
+#define OP_PROGRAM_VIA_BUF10x82
+#define OP_PROGRAM_VIA_BUF20x85
+
+/* compare buffer to flash */
+#define OP_COMPARE_BUF10x60
+#define OP_COMPARE_BUF20x61
+
+/* read flash to buffer, then write-erase to flash */
+#define OP_REWRITE_VIA_BUF10x58
+#define OP_REWRITE_VIA_BUF20x59
+
+/*
+ * newer chips report JEDEC manufacturer and device IDs; chip
+ * serial number and OTP bits; and per-sector writeprotect.
+ */
+#define OP_READ_ID 0x9F
+#define OP_READ_SECURITY   0x77
+#define OP_WRITE_SECURITY_REVC 0x9A
+#define OP_WRITE_SECURITY  0x9B/* revision D */
+
+
+struct dataflash {
+   uint8_t command[16];
+   unsigned short  page_offset;/* offset in flash address */
+};
+
+/*
+ * Return the status of the DataFlash device.
+ */
+static inline int dataflash_status(struct spi_slave *spi)
+{
+   int ret;
+   u8 status;
+   /*
+* NOTE:  at45db321c over 25 MHz wants to write
+* a dummy byte after the opcode...
+*/
+   ret = spi_flash_cmd(spi, OP_READ_STATUS, status, 1);
+   return ret ? -EIO : status;
+}
+
+/*
+ * Poll the DataFlash device until it is READY.
+ * This usually takes 5-20 msec or so; more for sector erase.
+ * ready: return  0
+ */
+static int dataflash_waitready(struct spi_slave *spi)
+{
+   int status;
+   int timeout = 2 * CONFIG_SYS_HZ;
+   int timebase;
+
+   timebase

[U-Boot] [PATCH 2/3 v2] arm: ls102xa: Enable Driver Model SPI for ls1021aqds

[Haikun Wang]

Enable Driver Model SPI for ls1021aqds board.
DSPI and QSPI is enabled only when boot from QSPI.
DSPI and QSPI are compatible under Driver Model SPI.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---

Changes in v2:
- Move all changes inside of CONFIG_QSPI_BOOT 

Changes in v1: None

 include/configs/ls1021aqds.h | 17 +++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 5de416d..c0e4bda 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -408,16 +408,29 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
-/* QSPI */
+/* SPI */
 #ifdef CONFIG_QSPI_BOOT
+/* QSPI */
 #define CONFIG_FSL_QSPI
 #define QSPI0_AMBA_BASE0x4000
 #define FSL_QSPI_FLASH_SIZE(1  24)
 #define FSL_QSPI_FLASH_NUM 2
+#define CONFIG_SPI_FLASH_SPANSION
 
+/* DSPI */
+#define CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_ATMEL
+
+/* DM SPI */
+#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+#define CONFIG_DM
+#define CONFIG_DM_SPI
 #define CONFIG_CMD_SF
+#define CONFIG_DM_SPI_FLASH
 #define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_SPANSION
+#endif
 #endif
 
 /*
-- 
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[U-Boot] [PATCH 3/3 v2] arm: ls102xa: Enable Driver Model SPI for ls1021atwr

[Haikun Wang]

Enable Driver Model SPI for ls1021atwr board.
DSPI and QSPI only be enabled when boot from QSPI.
DSPI and QSPI are compatible under Driver Model SPI.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---

Changes in v2:
- Move all changes inside of CONFIG_QSPI_BOOT 

Changes in v1: None

 include/configs/ls1021atwr.h | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index a13876b..1dd6336 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -228,16 +228,26 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
-/* QSPI */
+/* SPI */
 #ifdef CONFIG_QSPI_BOOT
+/* QSPI */
 #define CONFIG_FSL_QSPI
 #define QSPI0_AMBA_BASE0x4000
 #define FSL_QSPI_FLASH_SIZE(1  24)
 #define FSL_QSPI_FLASH_NUM 2
 
+#define CONFIG_SPI_FLASH_STMICRO
+
+/* DM SPI */
+#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+#define CONFIG_DM
+#define CONFIG_DM_SPI
 #define CONFIG_CMD_SF
+#define CONFIG_DM_SPI_FLASH
 #define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
+#endif
 #endif
 
 /*
-- 
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[U-Boot] [PATCH v1] dm: sf: Add Atmel DataFlash spi flash driver

[Haikun Wang]

Atmel DataFlash chips have commands different from common spi
flash commands.
Atmel DataFlash also have special page-size.
This driver add support for accessing Atmel DataFlash.
It is based on the Driver Model.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 drivers/mtd/spi/Makefile|   1 +
 drivers/mtd/spi/spi_dataflash.c | 674 
 2 files changed, 675 insertions(+)
 create mode 100644 drivers/mtd/spi/spi_dataflash.c

diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index c61b784..51de583 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_SPL_SPI_LOAD)+= spi_spl_load.o
 obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
 endif
 
+obj-$(CONFIG_DM_SPI_DATAFLASH) += spi_dataflash.o
 #ifndef CONFIG_DM_SPI
 obj-$(CONFIG_SPI_FLASH) += sf_probe.o
 #endif
diff --git a/drivers/mtd/spi/spi_dataflash.c b/drivers/mtd/spi/spi_dataflash.c
new file mode 100644
index 000..0b92964
--- /dev/null
+++ b/drivers/mtd/spi/spi_dataflash.c
@@ -0,0 +1,674 @@
+/*
+ *
+ * Atmel DataFlash probing
+ *
+ * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
+ * Haikun Wang (haikun.w...@freescale.com)
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+*/
+#include common.h
+#include dm.h
+#include errno.h
+#include fdtdec.h
+#include malloc.h
+#include spi.h
+#include spi_flash.h
+#include asm/io.h
+#include div64.h
+#include linux/err.h
+#include linux/math64.h
+
+#include sf_internal.h
+
+/*
+ * DataFlash is a kind of SPI flash.  Most AT45 chips have two buffers in
+ * each chip, which may be used for double buffered I/O; but this driver
+ * doesn't (yet) use these for any kind of i/o overlap or prefetching.
+ *
+ * Sometimes DataFlash is packaged in MMC-format cards, although the
+ * MMC stack can't (yet?) distinguish between MMC and DataFlash
+ * protocols during enumeration.
+ */
+
+/* reads can bypass the buffers */
+#define OP_READ_CONTINUOUS 0xE8
+#define OP_READ_PAGE   0xD2
+
+/* group B requests can run even while status reports busy */
+#define OP_READ_STATUS 0xD7/* group B */
+
+/* move data between host and buffer */
+#define OP_READ_BUFFER10xD4/* group B */
+#define OP_READ_BUFFER20xD6/* group B */
+#define OP_WRITE_BUFFER1   0x84/* group B */
+#define OP_WRITE_BUFFER2   0x87/* group B */
+
+/* erasing flash */
+#define OP_ERASE_PAGE  0x81
+#define OP_ERASE_BLOCK 0x50
+
+/* move data between buffer and flash */
+#define OP_TRANSFER_BUF1   0x53
+#define OP_TRANSFER_BUF2   0x55
+#define OP_MREAD_BUFFER1   0xD4
+#define OP_MREAD_BUFFER2   0xD6
+#define OP_MWERASE_BUFFER1 0x83
+#define OP_MWERASE_BUFFER2 0x86
+#define OP_MWRITE_BUFFER1  0x88/* sector must be pre-erased */
+#define OP_MWRITE_BUFFER2  0x89/* sector must be pre-erased */
+
+/* write to buffer, then write-erase to flash */
+#define OP_PROGRAM_VIA_BUF10x82
+#define OP_PROGRAM_VIA_BUF20x85
+
+/* compare buffer to flash */
+#define OP_COMPARE_BUF10x60
+#define OP_COMPARE_BUF20x61
+
+/* read flash to buffer, then write-erase to flash */
+#define OP_REWRITE_VIA_BUF10x58
+#define OP_REWRITE_VIA_BUF20x59
+
+/* newer chips report JEDEC manufacturer and device IDs; chip
+ * serial number and OTP bits; and per-sector writeprotect.
+ */
+#define OP_READ_ID 0x9F
+#define OP_READ_SECURITY   0x77
+#define OP_WRITE_SECURITY_REVC 0x9A
+#define OP_WRITE_SECURITY  0x9B/* revision D */
+
+
+struct dataflash {
+   uint8_t command[16];
+   unsigned short  page_offset;/* offset in flash address */
+   struct spi_flash*flash;
+};
+
+/* . */
+
+/*
+ * Return the status of the DataFlash device.
+ */
+static inline int dataflash_status(struct spi_slave *spi)
+{
+   int ret;
+   char status;
+   /* NOTE:  at45db321c over 25 MHz wants to write
+* a dummy byte after the opcode...
+*/
+   ret = spi_flash_cmd(spi, OP_READ_STATUS, status, 1);
+   return ret ? -EIO : status;
+}
+
+/*
+ * Poll the DataFlash device until it is READY.
+ * This usually takes 5-20 msec or so; more for sector erase.
+ * ready: return  0
+ */
+static int dataflash_waitready(struct spi_slave *spi)
+{
+   int status;
+   int timeout = 1000;
+
+   for (; timeout-- ;) {
+   status = dataflash_status(spi);
+   if (status  0)
+   status = 0;
+
+   if (status  (1  7))  /* RDY/nBSY */
+   return status;
+
+   mdelay(3);
+   }
+
+   return -ETIME;
+}
+
+/* . */
+
+/*
+ * Erase pages of flash.
+ */
+static int spi_dataflash_erase(struct udevice *dev, u32 offset

[U-Boot] [PATCH v2] dm: spi: Convert Freescale QSPI driver to driver model

[Haikun Wang]

Move the Freescale QSPI driver over to driver model.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
Signed-off-by: Peng Fan peng@freescale.com
---

Changes in v2:
- Fix build fail on mx6sxsabresd_spl issue
- Add configure regmap endian in NO-DM model

Changes in v1: None.

 drivers/spi/fsl_qspi.c | 985 -
 1 file changed, 656 insertions(+), 329 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 5e0b069..868df5f 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
  *
  * Freescale Quad Serial Peripheral Interface (QSPI) driver
  *
@@ -11,8 +11,12 @@
 #include spi.h
 #include asm/io.h
 #include linux/sizes.h
+#include dm.h
+#include errno.h
 #include fsl_qspi.h
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define RX_BUFFER_SIZE 0x80
 #ifdef CONFIG_MX6SX
 #define TX_BUFFER_SIZE 0x200
@@ -63,35 +67,85 @@
 #define QSPI_CMD_PP_4B 0x12/* Page program (up to 256 bytes) */
 #define QSPI_CMD_SE_4B 0xdc/* Sector erase (usually 64KiB) */
 
-#ifdef CONFIG_SYS_FSL_QSPI_LE
-#define qspi_read32in_le32
-#define qspi_write32   out_le32
-#elif defined(CONFIG_SYS_FSL_QSPI_BE)
-#define qspi_read32in_be32
-#define qspi_write32   out_be32
-#endif
+/* fsl_qspi_platdata flags */
+#define QSPI_FLAG_REGMAP_ENDIAN_BIG(1  0)
 
-static unsigned long spi_bases[] = {
-   QSPI0_BASE_ADDR,
-#ifdef CONFIG_MX6SX
-   QSPI1_BASE_ADDR,
-#endif
-};
+/* default SCK frequency, unit: HZ */
+#define FSL_QSPI_DEFAULT_SCK_FREQ  5000
 
-static unsigned long amba_bases[] = {
-   QSPI0_AMBA_BASE,
-#ifdef CONFIG_MX6SX
-   QSPI1_AMBA_BASE,
+/* QSPI max chipselect signals number */
+#define FSL_QSPI_MAX_CHIPSELECT_NUM 4
+
+#ifdef CONFIG_DM_SPI
+/**
+ * struct fsl_qspi_platdata - platform data for Freescale QSPI
+ *
+ * @flags: Flags for QSPI QSPI_FLAG_...
+ * @speed_hz: Default SCK frequency
+ * @reg_base: Base address of QSPI registers
+ * @amba_base: Base address of QSPI memory mapping
+ * @amba_total_size: size of QSPI memory mapping
+ * @flash_num: Number of active slave devices
+ * @num_chipselect: Number of QSPI chipselect signals
+ */
+struct fsl_qspi_platdata {
+   u32 flags;
+   u32 speed_hz;
+   u32 reg_base;
+   u32 amba_base;
+   u32 amba_total_size;
+   u32 flash_num;
+   u32 num_chipselect;
+};
 #endif
+
+/**
+ * struct fsl_qspi_priv - private data for Freescale QSPI
+ *
+ * @flags: Flags for QSPI QSPI_FLAG_...
+ * @bus_clk: QSPI input clk frequency
+ * @speed_hz: Default SCK frequency
+ * @cur_seqid: current LUT table sequence id
+ * @sf_addr: flash access offset
+ * @amba_base: Base address of QSPI memory mapping of every CS
+ * @amba_total_size: size of QSPI memory mapping
+ * @cur_amba_base: Base address of QSPI memory mapping of current CS
+ * @flash_num: Number of active slave devices
+ * @num_chipselect: Number of QSPI chipselect signals
+ * @regs: Point to QSPI register structure for I/O access
+ */
+struct fsl_qspi_priv {
+   u32 flags;
+   u32 bus_clk;
+   u32 speed_hz;
+   u32 cur_seqid;
+   u32 sf_addr;
+   u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
+   u32 amba_total_size;
+   u32 cur_amba_base;
+   u32 flash_num;
+   u32 num_chipselect;
+   struct fsl_qspi_regs *regs;
 };
 
+#ifndef CONFIG_DM_SPI
 struct fsl_qspi {
struct spi_slave slave;
-   unsigned long reg_base;
-   unsigned long amba_base;
-   u32 sf_addr;
-   u8 cur_seqid;
+   struct fsl_qspi_priv priv;
 };
+#endif
+
+static u32 qspi_read32(u32 flags, u32 *addr)
+{
+   return flags  QSPI_FLAG_REGMAP_ENDIAN_BIG ?
+   in_be32(addr) : in_le32(addr);
+}
+
+static void qspi_write32(u32 flags, u32 *addr, u32 val)
+{
+   flags  QSPI_FLAG_REGMAP_ENDIAN_BIG ?
+   out_be32(addr, val) : out_le32(addr, val);
+}
 
 /* QSPI support swapping the flash read/write data
  * in hardware for LS102xA, but not for VF610 */
@@ -104,131 +158,135 @@ static inline u32 qspi_endian_xchg(u32 data)
 #endif
 }
 
-static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave)
-{
-   return container_of(slave, struct fsl_qspi, slave);
-}
-
-static void qspi_set_lut(struct fsl_qspi *qspi)
+static void qspi_set_lut(struct fsl_qspi_priv *priv)
 {
-   struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi-reg_base;
+   struct fsl_qspi_regs *regs = priv-regs;
u32 lut_base;
 
/* Unlock the LUT */
-   qspi_write32(regs-lutkey, LUT_KEY_VALUE);
-   qspi_write32(regs-lckcr, QSPI_LCKCR_UNLOCK);
+   qspi_write32(priv-flags, regs-lutkey, LUT_KEY_VALUE);
+   qspi_write32(priv-flags, regs-lckcr, QSPI_LCKCR_UNLOCK);
 
/* Write Enable */
lut_base = SEQID_WREN * 4;
-   qspi_write32(regs-lut[lut_base

[U-Boot] [PATCH 1/3 v1] arm: ls102xa: Enable CONFIG_DEFAULT_DEVICE_TREE to defconfig for ls1021a

[Haikun Wang]

Define CONFIG_DEFAULT_DEVICE_TREE for ls1021a series boards.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 configs/ls1021aqds_ddr4_nor_defconfig| 1 +
 configs/ls1021aqds_nand_defconfig| 1 +
 configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 +
 configs/ls1021aqds_nor_defconfig | 1 +
 configs/ls1021aqds_nor_lpuart_defconfig  | 1 +
 configs/ls1021aqds_qspi_defconfig| 1 +
 configs/ls1021aqds_sdcard_defconfig  | 1 +
 configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 +
 configs/ls1021atwr_nor_defconfig | 1 +
 configs/ls1021atwr_nor_lpuart_defconfig  | 1 +
 configs/ls1021atwr_qspi_defconfig| 1 +
 configs/ls1021atwr_sdcard_defconfig  | 1 +
 12 files changed, 12 insertions(+)

diff --git a/configs/ls1021aqds_ddr4_nor_defconfig 
b/configs/ls1021aqds_ddr4_nor_defconfig
index 3c57481..d896027 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -1,3 +1,4 @@
 CONFIG_SYS_EXTRA_OPTIONS=SYS_FSL_DDR4
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE=ls1021a-qds
diff --git a/configs/ls1021aqds_nand_defconfig 
b/configs/ls1021aqds_nand_defconfig
index 3cd33fa..743e3c0 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -2,3 +2,4 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS=RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE=ls1021a-qds
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig 
b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index 2b47995..c5eb90a 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -1,3 +1,4 @@
 CONFIG_SYS_EXTRA_OPTIONS=SECURE_BOOT
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE=ls1021a-qds
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index 9e42d61..bd65322 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -1,2 +1,3 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE=ls1021a-qds
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig 
b/configs/ls1021aqds_nor_lpuart_defconfig
index a59f59e..0d90ab9 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -1,3 +1,4 @@
 CONFIG_SYS_EXTRA_OPTIONS=LPUART
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE=ls1021a-qds
diff --git a/configs/ls1021aqds_qspi_defconfig 
b/configs/ls1021aqds_qspi_defconfig
index 91c1125..5c79198 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -1,3 +1,4 @@
 CONFIG_SYS_EXTRA_OPTIONS=QSPI_BOOT
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE=ls1021a-qds
diff --git a/configs/ls1021aqds_sdcard_defconfig 
b/configs/ls1021aqds_sdcard_defconfig
index 910aa67..1c4a646 100644
--- a/configs/ls1021aqds_sdcard_defconfig
+++ b/configs/ls1021aqds_sdcard_defconfig
@@ -2,3 +2,4 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS=RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE=ls1021a-qds
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig 
b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index eeeb0d5..dedd832 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -1,3 +1,4 @@
 CONFIG_SYS_EXTRA_OPTIONS=SECURE_BOOT
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
+CONFIG_DEFAULT_DEVICE_TREE=ls1021a-twr
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 5f465d3..8903ab6 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -1,2 +1,3 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
+CONFIG_DEFAULT_DEVICE_TREE=ls1021a-twr
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig 
b/configs/ls1021atwr_nor_lpuart_defconfig
index 7c80041..9721183 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -1,3 +1,4 @@
 CONFIG_SYS_EXTRA_OPTIONS=LPUART
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
+CONFIG_DEFAULT_DEVICE_TREE=ls1021a-twr
diff --git a/configs/ls1021atwr_qspi_defconfig 
b/configs/ls1021atwr_qspi_defconfig
index c9715a4..ced7371 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -1,3 +1,4 @@
 CONFIG_SYS_EXTRA_OPTIONS=QSPI_BOOT
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
+CONFIG_DEFAULT_DEVICE_TREE=ls1021a-twr
diff --git a/configs/ls1021atwr_sdcard_defconfig 
b/configs/ls1021atwr_sdcard_defconfig
index 3390eac..c3e0db9 100644
--- a/configs/ls1021atwr_sdcard_defconfig
+++ b/configs/ls1021atwr_sdcard_defconfig
@@ -2,3 +2,4 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS=RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
+CONFIG_DEFAULT_DEVICE_TREE=ls1021a-twr
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/3 v1] arm: ls102xa: Enable Driver Model SPI for ls1021aqds

[Haikun Wang]

From: Haikun Wang haikun.w...@freescale.com

Enable Driver Model SPI for ls1021aqds board.
DSPI and QSPI are compatible under Driver Model SPI.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 include/configs/ls1021aqds.h | 14 +-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 3c66f87..8adb709 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -415,10 +415,22 @@ unsigned long get_board_ddr_clk(void);
 #define QSPI0_AMBA_BASE0x4000
 #define FSL_QSPI_FLASH_SIZE(1  24)
 #define FSL_QSPI_FLASH_NUM 2
+#define CONFIG_SPI_FLASH_SPANSION
+#endif
 
+/* DSPI */
+#define CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_ATMEL
+
+/* DM SPI */
+#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+#define CONFIG_DM
+#define CONFIG_DM_SPI
 #define CONFIG_CMD_SF
+#define CONFIG_DM_SPI_FLASH
 #define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_SPANSION
 #endif
 
 /*
-- 
1.9.1

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[U-Boot] [PATCH 3/3 v1] arm: ls102xa: Enable Driver Model SPI for ls1021atwr

[Haikun Wang]

From: Haikun Wang haikun.w...@freescale.com

Enable Driver Model SPI for ls1021atwr board.
DSPI and QSPI are compatible under Driver Model SPI.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 include/configs/ls1021atwr.h | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 0a0bb5f..6aeecda 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -235,9 +235,18 @@
 #define FSL_QSPI_FLASH_SIZE(1  24)
 #define FSL_QSPI_FLASH_NUM 2
 
+#define CONFIG_SPI_FLASH_STMICRO
+#endif
+
+/* DM SPI */
+#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+#define CONFIG_DM
+#define CONFIG_DM_SPI
 #define CONFIG_CMD_SF
+#define CONFIG_DM_SPI_FLASH
 #define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
 #endif
 
 /*
-- 
1.9.1

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[U-Boot] [PATCH 2/5 v2] dm: ls1021a: Bring in ls1021a dts files from linux kernel

[Haikun Wang]

From: haikun haikun.w...@freescale.com

Bring in required device tree files for ls1021a from Linux.
These are initially unchanged and have a number of pieces not needed by U-Boot.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---

Changes in v2:
- Use CONFIG_LS102XA in arch/arm/dts/Makefile

Changes in v1: None

 arch/arm/dts/Makefile|   3 +
 arch/arm/dts/ls1021a-qds.dts | 201 +++
 arch/arm/dts/ls1021a-twr.dts |  88 ++
 arch/arm/dts/ls1021a.dtsi| 370 +++
 4 files changed, 662 insertions(+)
 create mode 100644 arch/arm/dts/ls1021a-qds.dts
 create mode 100644 arch/arm/dts/ls1021a-twr.dts
 create mode 100644 arch/arm/dts/ls1021a.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cbe5b86..c326707 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -54,6 +54,9 @@ dtb-$(CONFIG_SOCFPGA) +=  \
socfpga_cyclone5_socdk.dtb  \
socfpga_cyclone5_socrates.dtb
 
+dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
+   ls1021a-twr.dtb
+
 targets += $(dtb-y)
 
 DTC_FLAGS += -R 4 -p 0x1000
diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dts
new file mode 100644
index 000..c89f85e
--- /dev/null
+++ b/arch/arm/dts/ls1021a-qds.dts
@@ -0,0 +1,201 @@
+/*
+ * Freescale ls1021a QDS board device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include ls1021a.dtsi
+
+/ {
+   model = LS1021A QDS Board;
+
+   aliases {
+   enet0_rgmii_phy = rgmii_phy1;
+   enet1_rgmii_phy = rgmii_phy2;
+   enet2_rgmii_phy = rgmii_phy3;
+   enet0_sgmii_phy = sgmii_phy1c;
+   enet1_sgmii_phy = sgmii_phy1d;
+   };
+};
+
+dspi0 {
+   bus-num = 0;
+   status = okay;
+
+   dspiflash: at45db021d@0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = atmel,at45db021d, atmel,at45, 
atmel,dataflash;
+   spi-max-frequency = 1600;
+   spi-cpol;
+   spi-cpha;
+   reg = 0;
+   };
+};
+
+i2c0 {
+   status = okay;
+
+   pca9547: mux@77 {
+   reg = 0x77;
+   #address-cells = 1;
+   #size-cells = 0;
+
+   i2c@0 {
+   #address-cells = 1;
+   #size-cells = 0;
+   reg = 0x0;
+
+   ds3232: rtc@68 {
+   compatible = dallas,ds3232;
+   reg = 0x68;
+   interrupts = GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH;
+   };
+   };
+
+   i2c@2 {
+   #address-cells = 1;
+   #size-cells = 0;
+   reg = 0x2;
+
+   ina220@40 {
+   compatible = ti,ina220;
+   reg = 0x40;
+   shunt-resistor = 1000;
+   };
+
+   ina220@41 {
+   compatible = ti,ina220;
+   reg = 0x41;
+   shunt-resistor = 1000;
+   };
+   };
+
+   i2c@3 {
+   #address-cells = 1;
+   #size-cells = 0;
+   reg = 0x3;
+
+   eeprom@56 {
+   compatible = atmel,24c512;
+   reg = 0x56;
+   };
+
+   eeprom@57 {
+   compatible = atmel,24c512;
+   reg = 0x57;
+   };
+
+   adt7461a@4c {
+   compatible = adi,adt7461a;
+   reg = 0x4c;
+   };
+   };
+   };
+};
+
+ifc {
+   #address-cells = 2;
+   #size-cells = 1;
+   /* NOR, NAND Flashes and FPGA on board */
+   ranges = 0x0 0x0 0x0 0x6000 0x0800
+ 0x2 0x0 0x0 0x7e80 0x0001
+ 0x3 0x0 0x0 0x7fb0 0x0100;
+   status = okay;
+
+   nor@0,0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = cfi-flash;
+   reg = 0x0 0x0 0x800;
+   bank-width = 2;
+   device-width = 1;
+   };
+
+   fpga: board-control@3,0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = simple-bus;
+   reg = 0x3 0x0 0x100;
+   bank-width = 1;
+   device-width = 1;
+   ranges = 0 3 0 0x100;
+
+   mdio-mux-emi1 {
+   compatible

[U-Boot] [PATCH 2/2 v1] sf: Update AT45DB021D flash chip parameters

[Haikun Wang]

From: Haikun Wang haikun.w...@freescale.com

AT45DB021D flash size is 1024*page_size, page_size is 256bytes or 264bytes.
In current params_table its size is 64*1024*8, recorrect it.
Add AT45DB_CMD flag for AT45DB021D.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---

Changes in v1: None

 drivers/mtd/spi/sf_params.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index c12e8c6..c6b68f8 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -16,7 +16,8 @@
 const struct spi_flash_params spi_flash_params_table[] = {
 #ifdef CONFIG_SPI_FLASH_ATMEL  /* ATMEL */
{AT45DB011D, 0x1f2200, 0x0,   64 * 1024, 4, RD_NORM,  
SECT_4K},
-   {AT45DB021D, 0x1f2300, 0x0,   64 * 1024, 8, RD_NORM,  
SECT_4K},
+   {AT45DB021D, 0x1f2300, 0x0,   64 * 1024, 4,
+RD_NORM,   AT45DB_CMD},
{AT45DB041D, 0x1f2400, 0x0,   64 * 1024, 8, RD_NORM,  
SECT_4K},
{AT45DB081D, 0x1f2500, 0x0,   64 * 1024,16, RD_NORM,  
SECT_4K},
{AT45DB161D, 0x1f2600, 0x0,   64 * 1024,32, RD_NORM,  
SECT_4K},
-- 
1.9.1

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[U-Boot] [PATCH 1/2 v1] sf: probe: Add support Atmel AT45DB series devices special commands

[Haikun Wang]

From: Haikun Wang haikun.w...@freescale.com

Atmel AT45DB series devices commands is different from common spi flash
commands. This patch add support for AT45DB special commands.
Add a flag AT45DB_CMD to control whether use those commands.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---

Changes in v1: None

 drivers/mtd/spi/sf_internal.h |  7 +++
 drivers/mtd/spi/sf_ops.c  |  2 +-
 drivers/mtd/spi/sf_probe.c| 10 ++
 3 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 785f7a9..234af21 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -43,6 +43,7 @@ enum {
SST_BP  = 1  3,
SST_WP  = 1  4,
WR_QPP  = 1  5,
+   AT45DB_CMD  = 1  6,
 };
 
 #define SST_WR (SST_BP | SST_WP)
@@ -106,6 +107,12 @@ enum {
 #define SPI_FLASH_PAGE_ERASE_TIMEOUT   (5 * CONFIG_SYS_HZ)
 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
 
+/* Atmel AT45DB specific */
+#define CMD_ATMEL_PAGE_PROGRAM 0x82
+#define CMD_ATMEL_READ_STATUS  0xd7
+#define CMD_ATMEL_FLAG_STATUS  0xd7
+#define CMD_ATMEL_BLK_ERASE0x50
+
 /* SST specific */
 #ifdef CONFIG_SPI_FLASH_SST
 # define CMD_SST_BP0x02/* Byte Program */
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 34bc54e..27ce5f9 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -165,7 +165,7 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, 
unsigned long timeout)
u8 poll_bit = STATUS_WIP;
u8 cmd = flash-poll_cmd;
 
-   if (cmd == CMD_FLAG_STATUS) {
+   if (cmd == CMD_FLAG_STATUS || cmd == CMD_ATMEL_FLAG_STATUS) {
poll_bit = STATUS_PEC;
check_status = poll_bit;
}
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 4103723..2ccddf2 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -226,6 +226,16 @@ static int spi_flash_validate_params(struct spi_slave 
*spi, u8 *idcode,
flash-poll_cmd = CMD_FLAG_STATUS;
 #endif
 
+#ifdef CONFIG_SPI_FLASH_ATMEL
+   if (params-flags  AT45DB_CMD) {
+   flash-poll_cmd = CMD_ATMEL_READ_STATUS;
+   flash-write_cmd = CMD_ATMEL_PAGE_PROGRAM;
+   /* use block-erase command, eight pages */
+   flash-erase_cmd = CMD_ATMEL_BLK_ERASE;
+   flash-erase_size = flash-page_size * 8;
+   }
+#endif
+
/* Configure the BAR - discover bank cmds and read current bank */
 #ifdef CONFIG_SPI_FLASH_BAR
u8 curr_bank = 0;
-- 
1.9.1

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[U-Boot] [PATCH 2/5] dm: ls1021a: Bring in ls1021a dts files from linux kernel

[Haikun Wang]

From: haikun haikun.w...@freescale.com

Bring in required device tree files for ls1021a from Linux.
These are initially unchanged and have a number of pieces not needed by U-Boot.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 arch/arm/dts/Makefile|   3 +
 arch/arm/dts/ls1021a-qds.dts | 201 +++
 arch/arm/dts/ls1021a-twr.dts |  88 ++
 arch/arm/dts/ls1021a.dtsi| 370 +++
 4 files changed, 662 insertions(+)
 create mode 100644 arch/arm/dts/ls1021a-qds.dts
 create mode 100644 arch/arm/dts/ls1021a-twr.dts
 create mode 100644 arch/arm/dts/ls1021a.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cbe5b86..67b821a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -54,6 +54,9 @@ dtb-$(CONFIG_SOCFPGA) +=  \
socfpga_cyclone5_socdk.dtb  \
socfpga_cyclone5_socrates.dtb
 
+dtb-$(CONFIG_TARGET_LS1021AQDS) += ls1021a-qds.dtb
+dtb-$(CONFIG_TARGET_LS1021ATWR) += ls1021a-twr.dtb
+
 targets += $(dtb-y)
 
 DTC_FLAGS += -R 4 -p 0x1000
diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dts
new file mode 100644
index 000..c89f85e
--- /dev/null
+++ b/arch/arm/dts/ls1021a-qds.dts
@@ -0,0 +1,201 @@
+/*
+ * Freescale ls1021a QDS board device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include ls1021a.dtsi
+
+/ {
+   model = LS1021A QDS Board;
+
+   aliases {
+   enet0_rgmii_phy = rgmii_phy1;
+   enet1_rgmii_phy = rgmii_phy2;
+   enet2_rgmii_phy = rgmii_phy3;
+   enet0_sgmii_phy = sgmii_phy1c;
+   enet1_sgmii_phy = sgmii_phy1d;
+   };
+};
+
+dspi0 {
+   bus-num = 0;
+   status = okay;
+
+   dspiflash: at45db021d@0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = atmel,at45db021d, atmel,at45, 
atmel,dataflash;
+   spi-max-frequency = 1600;
+   spi-cpol;
+   spi-cpha;
+   reg = 0;
+   };
+};
+
+i2c0 {
+   status = okay;
+
+   pca9547: mux@77 {
+   reg = 0x77;
+   #address-cells = 1;
+   #size-cells = 0;
+
+   i2c@0 {
+   #address-cells = 1;
+   #size-cells = 0;
+   reg = 0x0;
+
+   ds3232: rtc@68 {
+   compatible = dallas,ds3232;
+   reg = 0x68;
+   interrupts = GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH;
+   };
+   };
+
+   i2c@2 {
+   #address-cells = 1;
+   #size-cells = 0;
+   reg = 0x2;
+
+   ina220@40 {
+   compatible = ti,ina220;
+   reg = 0x40;
+   shunt-resistor = 1000;
+   };
+
+   ina220@41 {
+   compatible = ti,ina220;
+   reg = 0x41;
+   shunt-resistor = 1000;
+   };
+   };
+
+   i2c@3 {
+   #address-cells = 1;
+   #size-cells = 0;
+   reg = 0x3;
+
+   eeprom@56 {
+   compatible = atmel,24c512;
+   reg = 0x56;
+   };
+
+   eeprom@57 {
+   compatible = atmel,24c512;
+   reg = 0x57;
+   };
+
+   adt7461a@4c {
+   compatible = adi,adt7461a;
+   reg = 0x4c;
+   };
+   };
+   };
+};
+
+ifc {
+   #address-cells = 2;
+   #size-cells = 1;
+   /* NOR, NAND Flashes and FPGA on board */
+   ranges = 0x0 0x0 0x0 0x6000 0x0800
+ 0x2 0x0 0x0 0x7e80 0x0001
+ 0x3 0x0 0x0 0x7fb0 0x0100;
+   status = okay;
+
+   nor@0,0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = cfi-flash;
+   reg = 0x0 0x0 0x800;
+   bank-width = 2;
+   device-width = 1;
+   };
+
+   fpga: board-control@3,0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = simple-bus;
+   reg = 0x3 0x0 0x100;
+   bank-width = 1;
+   device-width = 1;
+   ranges = 0 3 0 0x100;
+
+   mdio-mux-emi1 {
+   compatible = mdio-mux-mmioreg;
+   mdio

[U-Boot] [PATCH 3/5 v1] dm: ls1021a: dts: Change address_cells and size_cells from 2 to 1

[Haikun Wang]

From: haikun haikun.w...@freescale.com

Change address_cells and size_cells of root node and 'soc' node
from 2 to 1.

We backport ls1021a device tree source files from kernel to u-boot.
Kernel files set address_cells and size_cells to 2 in order to access
more than 4GB space.
But we don't have this requirement now and u-boot fdtdec_get_xxx interfaces
can't support property whose size is 'u64' completely.
So make this change.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 arch/arm/dts/ls1021a-qds.dts |  6 ++--
 arch/arm/dts/ls1021a-twr.dts |  2 +-
 arch/arm/dts/ls1021a.dtsi| 72 ++--
 3 files changed, 40 insertions(+), 40 deletions(-)

diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dts
index c89f85e..7454ac6 100644
--- a/arch/arm/dts/ls1021a-qds.dts
+++ b/arch/arm/dts/ls1021a-qds.dts
@@ -101,9 +101,9 @@
#address-cells = 2;
#size-cells = 1;
/* NOR, NAND Flashes and FPGA on board */
-   ranges = 0x0 0x0 0x0 0x6000 0x0800
- 0x2 0x0 0x0 0x7e80 0x0001
- 0x3 0x0 0x0 0x7fb0 0x0100;
+   ranges = 0x0 0x0 0x6000 0x0800
+ 0x2 0x0 0x7e80 0x0001
+ 0x3 0x0 0x7fb0 0x0100;
status = okay;
 
nor@0,0 {
diff --git a/arch/arm/dts/ls1021a-twr.dts b/arch/arm/dts/ls1021a-twr.dts
index 34ac82d..2f0481d 100644
--- a/arch/arm/dts/ls1021a-twr.dts
+++ b/arch/arm/dts/ls1021a-twr.dts
@@ -46,7 +46,7 @@
#address-cells = 2;
#size-cells = 1;
/* NOR Flash on board */
-   ranges = 0x0 0x0 0x0 0x6000 0x0800;
+   ranges = 0x0 0x0 0x6000 0x0800;
status = okay;
 
nor@0,0 {
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 434b938..064d10c 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -6,7 +6,7 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#include skeleton64.dtsi
+#include skeleton.dtsi
 #include dt-bindings/interrupt-controller/arm-gic.h
 
 / {
@@ -58,8 +58,8 @@
 
soc {
compatible = simple-bus;
-   #address-cells = 2;
-   #size-cells = 2;
+   #address-cells = 1;
+   #size-cells = 1;
device_type = soc;
interrupt-parent = gic;
ranges;
@@ -68,29 +68,29 @@
compatible = arm,cortex-a7-gic;
#interrupt-cells = 3;
interrupt-controller;
-   reg = 0x0 0x1401000 0x0 0x1000,
- 0x0 0x1402000 0x0 0x1000,
- 0x0 0x1404000 0x0 0x2000,
- 0x0 0x1406000 0x0 0x2000;
+   reg = 0x1401000 0x1000,
+ 0x1402000 0x1000,
+ 0x1404000 0x2000,
+ 0x1406000 0x2000;
interrupts = GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_HIGH);
 
};
 
ifc: ifc@153 {
compatible = fsl,ifc, simple-bus;
-   reg = 0x0 0x153 0x0 0x1;
+   reg = 0x153 0x1;
interrupts = GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH;
};
 
dcfg: dcfg@1ee {
compatible = fsl,ls1021a-dcfg, syscon;
-   reg = 0x0 0x1ee 0x0 0x1;
+   reg = 0x1ee 0x1;
big-endian;
};
 
esdhc: esdhc@156 {
compatible = fsl,esdhc;
-   reg = 0x0 0x156 0x0 0x1;
+   reg = 0x156 0x1;
interrupts = GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH;
clock-frequency = 0;
voltage-ranges = 1800 1800 3300 3300;
@@ -102,14 +102,14 @@
 
scfg: scfg@157 {
compatible = fsl,ls1021a-scfg, syscon;
-   reg = 0x0 0x157 0x0 0x1;
+   reg = 0x157 0x1;
big-endian;
};
 
clockgen: clocking@1ee1000 {
#address-cells = 1;
#size-cells = 1;
-   ranges = 0x0 0x0 0x1ee1000 0x1;
+   ranges = 0x0 0x1ee1000 0x1;
 
sysclk: sysclk {
compatible = fixed-clock;
@@ -148,7 +148,7 @@
compatible = fsl,vf610-dspi;
#address-cells = 1;
#size-cells = 0;
-   reg = 0x0 0x210 0x0 0x1;
+   reg = 0x210 0x1;
interrupts = GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH

[U-Boot] [PATCH 4/5 v1] dm: ls1021a: dts: Update DSPI node to support DM SPI

[Haikun Wang]

Update DSPI controller node in ls1021a.dtsi.
Update flash device node in ls1021a-qds.dts.
Ls1021a-twr board doesn't support DSPI, so remove DSPI node
in ls1021a-twr.dts.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 arch/arm/dts/ls1021a-qds.dts |  3 ++-
 arch/arm/dts/ls1021a-twr.dts | 15 ---
 arch/arm/dts/ls1021a.dtsi|  4 ++--
 3 files changed, 4 insertions(+), 18 deletions(-)

diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dts
index 7454ac6..8971c18 100644
--- a/arch/arm/dts/ls1021a-qds.dts
+++ b/arch/arm/dts/ls1021a-qds.dts
@@ -18,6 +18,7 @@
enet2_rgmii_phy = rgmii_phy3;
enet0_sgmii_phy = sgmii_phy1c;
enet1_sgmii_phy = sgmii_phy1d;
+   spi1 = dspi0;
};
 };
 
@@ -28,7 +29,7 @@
dspiflash: at45db021d@0 {
#address-cells = 1;
#size-cells = 1;
-   compatible = atmel,at45db021d, atmel,at45, 
atmel,dataflash;
+   compatible = spi-flash;
spi-max-frequency = 1600;
spi-cpol;
spi-cpha;
diff --git a/arch/arm/dts/ls1021a-twr.dts b/arch/arm/dts/ls1021a-twr.dts
index 2f0481d..3d9f23b 100644
--- a/arch/arm/dts/ls1021a-twr.dts
+++ b/arch/arm/dts/ls1021a-twr.dts
@@ -19,21 +19,6 @@
};
 };
 
-dspi1 {
-   bus-num = 0;
-   status = okay;
-
-   dspiflash: s25fl064k@0 {
-   #address-cells = 1;
-   #size-cells = 1;
-   compatible = spansion,s25fl064k;
-   spi-max-frequency = 1600;
-   spi-cpol;
-   spi-cpha;
-   reg = 0;
-   };
-};
-
 i2c0 {
status = okay;
 };
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 064d10c..8b3c557 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -152,7 +152,7 @@
interrupts = GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH;
clock-names = dspi;
clocks = platform_clk 1;
-   spi-num-chipselects = 5;
+   num-cs = 6;
big-endian;
status = disabled;
};
@@ -165,7 +165,7 @@
interrupts = GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH;
clock-names = dspi;
clocks = platform_clk 1;
-   spi-num-chipselects = 5;
+   num-cs = 6;
big-endian;
status = disabled;
};
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/5 v1] dm: arm: Bring in skeleton64 device tree file from Linux

[Haikun Wang]

Backport of kernel commits:
7c14f6c719de092d69c81877786e83ce7ae1a860
35faad2a1563b3d4dc983a82ac41033fe053870c

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 arch/arm/dts/skeleton64.dtsi | 13 +
 1 file changed, 13 insertions(+)
 create mode 100644 arch/arm/dts/skeleton64.dtsi

diff --git a/arch/arm/dts/skeleton64.dtsi b/arch/arm/dts/skeleton64.dtsi
new file mode 100644
index 000..b5d7f36
--- /dev/null
+++ b/arch/arm/dts/skeleton64.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Skeleton device tree in the 64 bits version; the bare minimum
+ * needed to boot; just include and add a compatible value.  The
+ * bootloader will typically populate the memory node.
+ */
+
+/ {
+   #address-cells = 2;
+   #size-cells = 2;
+   chosen { };
+   aliases { };
+   memory { device_type = memory; reg = 0 0 0 0; };
+};
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 5/5 v1] dm: ls1021a: dts: Add QSPI dts node

[Haikun Wang]

Add QSPI controller dts node in ls1021a.dtsi.
Add QSPI slave device dts node in ls1021a-twr.dts and ls1021a-qds.dts.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 arch/arm/dts/ls1021a-qds.dts | 14 ++
 arch/arm/dts/ls1021a-twr.dts | 14 ++
 arch/arm/dts/ls1021a.dtsi| 11 +++
 3 files changed, 39 insertions(+)

diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dts
index 8971c18..8367811 100644
--- a/arch/arm/dts/ls1021a-qds.dts
+++ b/arch/arm/dts/ls1021a-qds.dts
@@ -18,6 +18,7 @@
enet2_rgmii_phy = rgmii_phy3;
enet0_sgmii_phy = sgmii_phy1c;
enet1_sgmii_phy = sgmii_phy1d;
+   spi0 = qspi;
spi1 = dspi0;
};
 };
@@ -37,6 +38,19 @@
};
 };
 
+qspi {
+   bus-num = 0;
+   status = okay;
+
+   qflash0: s25fl128s@0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = spi-flash;
+   spi-max-frequency = 2000;
+   reg = 0;
+   };
+};
+
 i2c0 {
status = okay;
 
diff --git a/arch/arm/dts/ls1021a-twr.dts b/arch/arm/dts/ls1021a-twr.dts
index 3d9f23b..0e61c07 100644
--- a/arch/arm/dts/ls1021a-twr.dts
+++ b/arch/arm/dts/ls1021a-twr.dts
@@ -16,6 +16,20 @@
enet2_rgmii_phy = rgmii_phy1;
enet0_sgmii_phy = sgmii_phy2;
enet1_sgmii_phy = sgmii_phy0;
+   spi0 = qspi;
+   };
+};
+
+qspi {
+   bus-num = 0;
+   status = okay;
+
+   qflash0: n25q128a13@0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = spi-flash;
+   spi-max-frequency = 2000;
+   reg = 0;
};
 };
 
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 8b3c557..7fadd7c 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -170,6 +170,17 @@
status = disabled;
};
 
+   qspi: quadspi@155 {
+   compatible = fsl,vf610-qspi;
+   #address-cells = 1;
+   #size-cells = 0;
+   reg = 0x155 0x1,
+   0x4000 0x400;
+   num-cs = 2;
+   big-endian;
+   status = disabled;
+   };
+
i2c0: i2c@218 {
compatible = fsl,vf610-i2c;
#address-cells = 1;
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v3] dm: spi: Convert Freescale DSPI driver to driver model

[Haikun Wang]

Move the Freescale DSPI driver over to driver model.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---

Changes in v3:
- Coding style cleanup
- Remove cur_slave_plat in structure fsl_dspi_priv
- Change arguments of 'claim_bus' and 'release_bus'
- Remove 'fsl_dspi_child_post_remove'
- Add support NO-DM SPI
- Add 'cpu_dspi_xxx' platform speical configure interface

Changes in v2:
- Coding style cleanup
- Add some comments
- Use structures for I/O access
- Handle timeout case in 'dspi_tx' and 'dspi_rx'
- Move some register configurations from 'set_mode' to 'claim_bus'
- Rename structure fsl_dspi_platdata's member baudrate 
- Remove some redundancy code

Changes in v1: None

 drivers/spi/Makefile   |   1 +
 drivers/spi/fsl_dspi.c | 737 +
 include/fsl_dspi.h | 150 ++
 3 files changed, 888 insertions(+)
 create mode 100644 drivers/spi/fsl_dspi.c
 create mode 100644 include/fsl_dspi.h

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index edbd520..9c2b8de 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -49,3 +49,4 @@ obj-$(CONFIG_TI_QSPI) += ti_qspi.o
 obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
 obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
+obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c
new file mode 100644
index 000..6476f91
--- /dev/null
+++ b/drivers/spi/fsl_dspi.c
@@ -0,0 +1,737 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
+ * TsiChung Liew (tsi-chung.l...@freescale.com)
+ * Chao Fu (b44...@freescale.com)
+ * Haikun Wang (b53...@freescale.com)
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include dm.h
+#include errno.h
+#include common.h
+#include spi.h
+#include malloc.h
+#include asm/io.h
+#include fdtdec.h
+#ifndef CONFIG_M68K
+#include asm/arch/clock.h
+#endif
+#include fsl_dspi.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* fsl_dspi_platdata flags */
+#define DSPI_FLAG_REGMAP_ENDIAN_BIG(1  0)
+
+/* idle data value */
+#define DSPI_IDLE_VAL  0x0
+
+/* max chipselect signals number */
+#define FSL_DSPI_MAX_CHIPSELECT6
+
+/* default SCK frequency, unit: HZ */
+#define FSL_DSPI_DEFAULT_SCK_FREQ  1000
+
+/* tx/rx data wait timeout value, unit: us */
+#define DSPI_TXRX_WAIT_TIMEOUT 100
+
+/* CTAR register pre-configure value */
+#define DSPI_CTAR_DEFAULT_VALUE(DSPI_CTAR_TRSZ(7) | \
+   DSPI_CTAR_PCSSCK_1CLK | \
+   DSPI_CTAR_PASC(0) | \
+   DSPI_CTAR_PDT(0) | \
+   DSPI_CTAR_CSSCK(0) | \
+   DSPI_CTAR_ASC(0) | \
+   DSPI_CTAR_DT(0))
+
+/* CTAR register pre-configure mask */
+#define DSPI_CTAR_SET_MODE_MASK(DSPI_CTAR_TRSZ(15) | \
+   DSPI_CTAR_PCSSCK(3) | \
+   DSPI_CTAR_PASC(3) | \
+   DSPI_CTAR_PDT(3) | \
+   DSPI_CTAR_CSSCK(15) | \
+   DSPI_CTAR_ASC(15) | \
+   DSPI_CTAR_DT(15))
+
+/**
+ * struct fsl_dspi_platdata - platform data for Freescale DSPI
+ *
+ * @flags: Flags for DSPI DSPI_FLAG_...
+ * @speed_hz: Default SCK frequency
+ * @num_chipselect: Number of DSPI chipselect signals
+ * @regs_addr: Base address of DSPI registers
+ */
+struct fsl_dspi_platdata {
+   uint flags;
+   uint speed_hz;
+   uint num_chipselect;
+   fdt_addr_t regs_addr;
+};
+
+/**
+ * struct fsl_dspi_priv - private data for Freescale DSPI
+ *
+ * @flags: Flags for DSPI DSPI_FLAG_...
+ * @mode: SPI mode to use for slave device (see SPI mode flags)
+ * @mcr_val: MCR register configure value
+ * @bus_clk: DSPI input clk frequency
+ * @speed_hz: Default SCK frequency
+ * @charbit: How many bits in every transfer
+ * @num_chipselect: Number of DSPI chipselect signals
+ * @ctar_val: CTAR register configure value of per chipselect slave device
+ * @regs: Point to DSPI register structure for I/O access
+ */
+struct fsl_dspi_priv {
+   uint flags;
+   uint mode;
+   uint mcr_val;
+   uint bus_clk;
+   uint speed_hz;
+   uint charbit;
+   uint num_chipselect;
+   uint ctar_val[FSL_DSPI_MAX_CHIPSELECT];
+   struct dspi *regs;
+};
+
+#ifndef CONFIG_DM_SPI
+struct fsl_dspi {
+   struct spi_slave slave;
+   struct fsl_dspi_priv priv;
+};
+#endif
+
+__weak void cpu_dspi_port_conf(void)
+{
+}
+
+__weak int cpu_dspi_claim_bus(uint bus, uint cs)
+{
+   return 0;
+}
+
+__weak void cpu_dspi_release_bus(uint bus, uint cs)
+{
+}
+
+static uint dspi_read32(uint flags, uint *addr)
+{
+   return

[U-Boot] [PATCH] dm: ls1021a: Bring in ls1021a dts files from linux kernel

[Haikun Wang]

From: haikun haikun.w...@freescale.com

Bring in device tree files for ls1021a from linux V3.19.
In order to use it in u-boot, make some changes:
1. remove 'gic' node and interrupt related properties in every node.
2. remove 'clockgen' node and clock related properties in every node.
3. change address-cells and size-cells of root node and 'soc' node
   from 2 to 1.
4. Add quadspi node.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
 arch/arm/dts/Makefile|   3 +
 arch/arm/dts/ls1021a-qds.dts |  47 
 arch/arm/dts/ls1021a-twr.dts |  31 +
 arch/arm/dts/ls1021a.dtsi| 265 +++
 4 files changed, 346 insertions(+)
 create mode 100644 arch/arm/dts/ls1021a-qds.dts
 create mode 100644 arch/arm/dts/ls1021a-twr.dts
 create mode 100644 arch/arm/dts/ls1021a.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cbe5b86..67b821a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -54,6 +54,9 @@ dtb-$(CONFIG_SOCFPGA) +=  \
socfpga_cyclone5_socdk.dtb  \
socfpga_cyclone5_socrates.dtb
 
+dtb-$(CONFIG_TARGET_LS1021AQDS) += ls1021a-qds.dtb
+dtb-$(CONFIG_TARGET_LS1021ATWR) += ls1021a-twr.dtb
+
 targets += $(dtb-y)
 
 DTC_FLAGS += -R 4 -p 0x1000
diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dts
new file mode 100644
index 000..9a06695
--- /dev/null
+++ b/arch/arm/dts/ls1021a-qds.dts
@@ -0,0 +1,47 @@
+/*
+ * Freescale ls1021a QDS board device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include ls1021a.dtsi
+
+/ {
+   model = LS1021A QDS Board;
+
+   aliases {
+   spi0 = qspi;
+   spi1 = dspi0;
+   };
+};
+
+dspi0 {
+   bus-num = 0;
+   status = okay;
+
+   dspiflash: at45db021d@0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = spi-flash;
+   spi-max-frequency = 1600;
+   spi-cpol;
+   spi-cpha;
+   reg = 0;
+   };
+};
+
+qspi {
+   bus-num = 0;
+   status = okay;
+
+   qflash0: s25fl128s@0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = spi-flash;
+   spi-max-frequency = 2000;
+   reg = 0;
+   };
+};
diff --git a/arch/arm/dts/ls1021a-twr.dts b/arch/arm/dts/ls1021a-twr.dts
new file mode 100644
index 000..db528f9
--- /dev/null
+++ b/arch/arm/dts/ls1021a-twr.dts
@@ -0,0 +1,31 @@
+/*
+ * Freescale ls1021a TWR board device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include ls1021a.dtsi
+
+/ {
+   model = LS1021A TWR Board;
+
+   aliases {
+   spi0 = qspi;
+   };
+};
+
+qspi {
+   bus-num = 0;
+   status = okay;
+
+   qflash0: n25q128a13@0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = spi-flash;
+   spi-max-frequency = 2000;
+   reg = 0;
+   };
+};
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
new file mode 100644
index 000..e160a5d
--- /dev/null
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -0,0 +1,265 @@
+/*
+ * Freescale ls1021a SOC common device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include skeleton.dtsi
+
+/ {
+   compatible = fsl,ls1021a;
+
+   aliases {
+   serial0 = lpuart0;
+   serial1 = lpuart1;
+   serial2 = lpuart2;
+   serial3 = lpuart3;
+   serial4 = lpuart4;
+   serial5 = lpuart5;
+   };
+
+   cpus {
+   #address-cells = 1;
+   #size-cells = 0;
+
+   cpu@f00 {
+   compatible = arm,cortex-a7;
+   device_type = cpu;
+   reg = 0xf00;
+   };
+
+   cpu@f01 {
+   compatible = arm,cortex-a7;
+   device_type = cpu;
+   reg = 0xf01;
+   };
+   };
+
+   timer {
+   compatible = arm,armv7-timer;
+   };
+
+   pmu {
+   compatible = arm,cortex-a7-pmu;
+   };
+
+   soc {
+   compatible = simple-bus;
+   #address-cells = 1;
+   #size-cells = 1;
+   device_type = soc;
+   ranges;
+
+
+   ifc: ifc@153 {
+   compatible = fsl,ifc, simple-bus;
+   reg = 0x153 0x1;
+   };
+
+   dcfg: dcfg@1ee {
+   compatible = fsl,ls1021a-dcfg, syscon;
+   reg = 0x1ee 0x1;
+   big

[U-Boot] [PATCH v1] dm: spi: Convert Freescale QSPI driver to driver model

[Haikun Wang]

Move the Freescale QSPI driver over to driver model.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
Signed-off-by: Peng Fan peng@freescale.com
---

This patch adds DM support for FSL QSPI driver.
Now this driver can support both DM frame and old SPI frame. 
Driver structure like below:

QSPI driver common code

#ifndef CONFIG_DM_SPI
Old SPI frame interface
#else
DM SPI frame interface
#endif

changes in v1: None

 drivers/spi/fsl_qspi.c | 970 -
 1 file changed, 645 insertions(+), 325 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 5e0b069..1429295 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -11,8 +11,12 @@
 #include spi.h
 #include asm/io.h
 #include linux/sizes.h
+#include dm.h
+#include errno.h
 #include fsl_qspi.h
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define RX_BUFFER_SIZE 0x80
 #ifdef CONFIG_MX6SX
 #define TX_BUFFER_SIZE 0x200
@@ -63,35 +67,85 @@
 #define QSPI_CMD_PP_4B 0x12/* Page program (up to 256 bytes) */
 #define QSPI_CMD_SE_4B 0xdc/* Sector erase (usually 64KiB) */
 
-#ifdef CONFIG_SYS_FSL_QSPI_LE
-#define qspi_read32in_le32
-#define qspi_write32   out_le32
-#elif defined(CONFIG_SYS_FSL_QSPI_BE)
-#define qspi_read32in_be32
-#define qspi_write32   out_be32
-#endif
+/* fsl_qspi_platdata flags */
+#define QSPI_FLAG_REGMAP_ENDIAN_BIG(1  0)
 
-static unsigned long spi_bases[] = {
-   QSPI0_BASE_ADDR,
-#ifdef CONFIG_MX6SX
-   QSPI1_BASE_ADDR,
-#endif
-};
+/* default SCK frequency, unit: HZ */
+#define FSL_QSPI_DEFAULT_SCK_FREQ  5000
 
-static unsigned long amba_bases[] = {
-   QSPI0_AMBA_BASE,
-#ifdef CONFIG_MX6SX
-   QSPI1_AMBA_BASE,
+/* QSPI max chipselect signals number */
+#define FSL_QSPI_MAX_CHIPSELECT_NUM 4
+
+#ifdef CONFIG_DM_SPI
+/**
+ * struct fsl_qspi_platdata - platform data for Freescale QSPI
+ *
+ * @flags: Flags for QSPI QSPI_FLAG_...
+ * @speed_hz: Default SCK frequency
+ * @reg_base: Base address of QSPI registers
+ * @amba_base: Base address of QSPI memory mapping
+ * @amba_total_size: size of QSPI memory mapping
+ * @flash_num: Number of active slave devices
+ * @num_chipselect: Number of QSPI chipselect signals
+ */
+struct fsl_qspi_platdata {
+   u32 flags;
+   u32 speed_hz;
+   u32 reg_base;
+   u32 amba_base;
+   u32 amba_total_size;
+   u32 flash_num;
+   u32 num_chipselect;
+};
 #endif
+
+/**
+ * struct fsl_qspi_priv - private data for Freescale QSPI
+ *
+ * @flags: Flags for QSPI QSPI_FLAG_...
+ * @bus_clk: QSPI input clk frequency
+ * @speed_hz: Default SCK frequency
+ * @cur_seqid: current LUT table sequence id
+ * @sf_addr: flash access offset
+ * @amba_base: Base address of QSPI memory mapping of every CS
+ * @amba_total_size: size of QSPI memory mapping
+ * @cur_amba_base: Base address of QSPI memory mapping of current CS
+ * @flash_num: Number of active slave devices
+ * @num_chipselect: Number of QSPI chipselect signals
+ * @regs: Point to QSPI register structure for I/O access
+ */
+struct fsl_qspi_priv {
+   u32 flags;
+   u32 bus_clk;
+   u32 speed_hz;
+   u32 cur_seqid;
+   u32 sf_addr;
+   u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
+   u32 amba_total_size;
+   u32 cur_amba_base;
+   u32 flash_num;
+   u32 num_chipselect;
+   struct fsl_qspi_regs *regs;
 };
 
+#ifndef CONFIG_DM_SPI
 struct fsl_qspi {
struct spi_slave slave;
-   unsigned long reg_base;
-   unsigned long amba_base;
-   u32 sf_addr;
-   u8 cur_seqid;
+   struct fsl_qspi_priv priv;
 };
+#endif
+
+static u32 qspi_read32(u32 flags, u32 *addr)
+{
+   return flags  QSPI_FLAG_REGMAP_ENDIAN_BIG ?
+   in_be32(addr) : in_le32(addr);
+}
+
+static void qspi_write32(u32 flags, u32 *addr, u32 val)
+{
+   flags  QSPI_FLAG_REGMAP_ENDIAN_BIG ?
+   out_be32(addr, val) : out_le32(addr, val);
+}
 
 /* QSPI support swapping the flash read/write data
  * in hardware for LS102xA, but not for VF610 */
@@ -104,131 +158,135 @@ static inline u32 qspi_endian_xchg(u32 data)
 #endif
 }
 
-static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave)
-{
-   return container_of(slave, struct fsl_qspi, slave);
-}
-
-static void qspi_set_lut(struct fsl_qspi *qspi)
+static void qspi_set_lut(struct fsl_qspi_priv *priv)
 {
-   struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi-reg_base;
+   struct fsl_qspi_regs *regs = priv-regs;
u32 lut_base;
 
/* Unlock the LUT */
-   qspi_write32(regs-lutkey, LUT_KEY_VALUE);
-   qspi_write32(regs-lckcr, QSPI_LCKCR_UNLOCK);
+   qspi_write32(priv-flags, regs-lutkey, LUT_KEY_VALUE);
+   qspi_write32(priv-flags, regs-lckcr, QSPI_LCKCR_UNLOCK);
 
/* Write Enable */
lut_base = SEQID_WREN * 4;
-   qspi_write32(regs-lut[lut_base], OPRND0(QSPI_CMD_WREN) |
+   qspi_write32(priv

[U-Boot] [PATCH v2] dm: spi: Convert Freescale DSPI driver to driver model

[Haikun Wang]

Move the Freescale DSPI driver over to driver model.

Signed-off-by: Haikun Wang haikun.w...@freescale.com
---

Changes in v2:
- Coding style cleanup
- Add some comments
- Use structures for I/O access
- Handle timeout case in 'dspi_tx' and 'dspi_rx'
- Move some register configurations from 'set_mode' to 'claim_bus'
- Rename structure fsl_dspi_platdata's member baudrate 
- Remove some redundancy code

Changes in v1: None

 drivers/spi/Makefile   |   1 +
 drivers/spi/fsl_dspi.c | 530 +
 include/fsl_dspi.h | 150 ++
 3 files changed, 681 insertions(+)
 create mode 100644 drivers/spi/fsl_dspi.c
 create mode 100644 include/fsl_dspi.h

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index edbd520..9c2b8de 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -49,3 +49,4 @@ obj-$(CONFIG_TI_QSPI) += ti_qspi.o
 obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
 obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
+obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c
new file mode 100644
index 000..6108041
--- /dev/null
+++ b/drivers/spi/fsl_dspi.c
@@ -0,0 +1,530 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
+ * TsiChung Liew (tsi-chung.l...@freescale.com)
+ * Chao Fu (b44...@freescale.com)
+ * Haikun Wang (b53...@freescale.com)
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include dm.h
+#include errno.h
+#include common.h
+#include spi.h
+#include malloc.h
+#include asm/io.h
+#include fdtdec.h
+#include asm/arch/clock.h
+#include fsl_dspi.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* fsl_dspi_platdata flags */
+#define DSPI_FLAG_REGMAP_ENDIAN_BIG(1  0)
+
+/* idle data value */
+#define DSPI_IDLE_VAL  0x0
+
+/* max chipselect signals number */
+#define FSL_DSPI_MAX_CHIPSELECT6
+
+/* default SCK frequency, unit: HZ */
+#define FSL_DSPI_DEFAULT_SCK_FREQ  1000
+
+/* tx/rx data wait timeout value, unit: us */
+#define DSPI_TXRX_WAIT_TIMEOUT 100
+
+/* CTAR register pre-configure value */
+#define DSPI_CTAR_DEFAULT_VALUE(DSPI_CTAR_TRSZ(7) | \
+   DSPI_CTAR_PCSSCK_1CLK | \
+   DSPI_CTAR_PASC(0) | \
+   DSPI_CTAR_PDT(0) | \
+   DSPI_CTAR_CSSCK(0) | \
+   DSPI_CTAR_ASC(0) | \
+   DSPI_CTAR_DT(0))
+
+/* CTAR register pre-configure mask */
+#define DSPI_CTAR_SET_MODE_MASK(DSPI_CTAR_TRSZ(15) | \
+   DSPI_CTAR_PCSSCK(3) | \
+   DSPI_CTAR_PASC(3) | \
+   DSPI_CTAR_PDT(3) | \
+   DSPI_CTAR_CSSCK(15) | \
+   DSPI_CTAR_ASC(15) | \
+   DSPI_CTAR_DT(15))
+
+/**
+ * struct fsl_dspi_platdata - platform data for Freescale DSPI
+ *
+ * @flags: Flags for DSPI DSPI_FLAG_...
+ * @speed_hz: Default SCK frequency
+ * @num_chipselect: Number of DSPI chipselect signals
+ * @regs_addr: Base address of DSPI registers
+ */
+struct fsl_dspi_platdata {
+   uint flags;
+   uint speed_hz;
+   uint num_chipselect;
+   fdt_addr_t regs_addr;
+};
+
+struct fsl_dspi_priv {
+   uint flags;
+   uint mode;
+   uint mcr_val;
+   uint bus_clk;
+   uint speed_hz;
+   uint charbit;
+   uint num_chipselect;
+   uint ctar_val[FSL_DSPI_MAX_CHIPSELECT];
+   struct dspi *regs;
+   struct dm_spi_slave_platdata *cur_slave_plat;
+};
+
+static uint dspi_read32(uint flags, uint *addr)
+{
+   return flags  DSPI_FLAG_REGMAP_ENDIAN_BIG ?
+   in_be32(addr) : in_le32(addr);
+}
+
+static void dspi_write32(uint flags, uint *addr, uint val)
+{
+   flags  DSPI_FLAG_REGMAP_ENDIAN_BIG ?
+   out_be32(addr, val) : out_le32(addr, val);
+}
+
+static void dspi_halt(struct udevice *bus, u8 halt)
+{
+   uint mcr_val;
+   struct fsl_dspi_priv *priv = dev_get_priv(bus);
+
+   mcr_val = dspi_read32(priv-flags, priv-regs-mcr);
+
+   if (halt)
+   mcr_val |= DSPI_MCR_HALT;
+   else
+   mcr_val = ~DSPI_MCR_HALT;
+
+   dspi_write32(priv-flags, priv-regs-mcr, mcr_val);
+}
+
+static int fsl_dspi_child_pre_probe(struct udevice *dev)
+{
+   struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+   struct fsl_dspi_priv *priv = dev_get_priv(dev-parent);
+
+   if (slave_plat-cs = priv-num_chipselect) {
+   debug(DSPI invalid chipselect number %d(max %d)!\n,
+ slave_plat-cs, priv