[PATCH 1/2] arm: mach-k3: am62: Get a53 max cpu frequency by speed grade
From: Joao Paulo Goncalves
AM62 SoC has multiple speed grades. Add function to return max A53 CPU
frequency based on grade. Fastest grade's max frequency also depends on
PMIC voltage, to simplify implementation use the smaller value.
Suggested-by: Vignesh Raghavendra
Signed-off-by: Joao Paulo Goncalves
---
arch/arm/mach-k3/include/mach/am62_hardware.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h
b/arch/arm/mach-k3/include/mach/am62_hardware.h
index 264f8a488b4..90682d8ee31 100644
--- a/arch/arm/mach-k3/include/mach/am62_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am62_hardware.h
@@ -122,6 +122,21 @@ static inline int k3_get_max_temp(void)
}
}
+static inline int k3_get_a53_max_frequency(void)
+{
+ switch (k3_get_speed_grade()) {
+ case 'K':
+ return 8;
+ case 'S':
+ return 10;
+ case 'T':
+ return 125000;
+ case 'G':
+ default:
+ return 3;
+ }
+}
+
static inline int k3_has_pru(void)
{
u32 full_devid = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
--
2.34.1
[PATCH 2/2] arm: mach-k3: am625: Fixup a53 cpu frequency by speed grade
From: Joao Paulo Goncalves
The maximum frequency of the A53 CPU on the AM62 depends on the speed
grade of the SoC. However, this value is hardcoded in the DT for all
AM62 variants, potentially causing specifications to be exceeded. Moreover,
setting a common lower frequency for all variants increases boot time.
To prevent these issues, modify the DT at runtime from the R5 core to
adjust the A53 CPU frequency based on its speed grade.
Suggested-by: Vignesh Raghavendra
Signed-off-by: Joao Paulo Goncalves
---
arch/arm/mach-k3/am625_init.c | 62 +++
1 file changed, 62 insertions(+)
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c
index 6c96e881146..961f36e6549 100644
--- a/arch/arm/mach-k3/am625_init.c
+++ b/arch/arm/mach-k3/am625_init.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#define RTC_BASE_ADDRESS 0x2b1f
#define REG_K3RTC_S_CNT_LSW(RTC_BASE_ADDRESS + 0x18)
@@ -24,6 +25,9 @@
#define K3RTC_KICK0_UNLOCK_VALUE 0x83e70b13
#define K3RTC_KICK1_UNLOCK_VALUE 0x95a4f1e0
+/* TISCI DEV ID for A53 Clock */
+#define AM62X_DEV_A53SS0_CORE_0_DEV_ID 135
+
/*
* This uninitialized global variable would normal end up in the .bss section,
* but the .bss is cleared between writing and reading this variable, so move
@@ -112,6 +116,62 @@ static __maybe_unused void rtc_erratumi2327_init(void)
writel(K3RTC_KICK1_UNLOCK_VALUE, REG_K3RTC_KICK1);
}
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static int get_a53_cpu_clock_index(ofnode node)
+{
+ int count, i;
+ struct ofnode_phandle_args *args;
+ ofnode clknode;
+
+ clknode =
ofnode_path("/bus@f/system-controller@44043000/clock-controller");
+ if (!ofnode_valid(clknode))
+ return -1;
+
+ count = ofnode_count_phandle_with_args(node, "assigned-clocks",
"#clock-cells", 0);
+
+ for (i = 0; i < count; i++) {
+ if (!ofnode_parse_phandle_with_args(node, "assigned-clocks",
+ "#clock-cells", 0, i,
args)) {
+ if (ofnode_equal(clknode, args->node) &&
+ args->args[0] == AM62X_DEV_A53SS0_CORE_0_DEV_ID)
+ return i;
+ }
+ }
+
+ return -1;
+}
+
+static void fixup_a53_cpu_freq_by_speed_grade(void)
+{
+ int index, size;
+ u32 *rates;
+ ofnode node;
+
+ node = ofnode_path("/a53@0");
+ if (!ofnode_valid(node))
+ return;
+
+ rates = fdt_getprop_w(ofnode_to_fdt(node), ofnode_to_offset(node),
+ "assigned-clock-rates", );
+
+ index = get_a53_cpu_clock_index(node);
+
+ if (!rates || index < 0 || index >= (size / sizeof(u32))) {
+ printf("Wrong A53 assigned-clocks configuration\n");
+ return;
+ }
+
+ rates[index] = cpu_to_fdt32(k3_get_a53_max_frequency());
+
+ printf("Changed A53 CPU frequency to %dHz (%c grade) in DT\n",
+ k3_get_a53_max_frequency(), k3_get_speed_grade());
+}
+#else
+static void fixup_a53_cpu_freq_by_speed_grade(void)
+{
+}
+#endif
+
void board_init_f(ulong dummy)
{
struct udevice *dev;
@@ -210,6 +270,8 @@ void board_init_f(ulong dummy)
panic("DRAM init failed: %d\n", ret);
}
spl_enable_cache();
+
+ fixup_a53_cpu_freq_by_speed_grade();
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
--
2.34.1
[PATCH 0/2] arm: mach-k3: am62: change a53 clock frequency by speed grade
From: Joao Paulo Goncalves This series introduces a method to dynamically set the AM62 A53 CPU frequency based on its speed grade. It adds a new function to retrieve the A53 frequency value by reading the speed grade from the hardware. Subsequently, it adjusts the Cortex R5 device tree at runtime with the frequency value before initializing the remote processor. Regards, João Paulo Goncalves Joao Paulo Goncalves (2): arm: mach-k3: am62: Get a53 max cpu frequency by speed grade arm: mach-k3: am625: Fixup a53 cpu frequency by speed grade arch/arm/mach-k3/am625_init.c | 62 +++ arch/arm/mach-k3/include/mach/am62_hardware.h | 15 + 2 files changed, 77 insertions(+) -- 2.34.1
[PATCH] arm: dts: k3-am625-verdin-r5: Change CPU frequency to 800MHz
From: Joao Paulo Goncalves
The lowest speed grade of Toradex AM62 SoMs is K speed, resulting in a
max value of 800MHz for the CPU operating frequency. A solution with
runtime selection of the CPU frequency is already planned to avoid these
kinds of problems in the future.
Fixes: 8fb8a6d49977 ("arm: dts: k3-am625-verdin-r5:Change CPU
frequency to 1000MHz")
Signed-off-by: Joao Paulo Goncalves
---
arch/arm/dts/k3-am625-verdin-r5.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts
b/arch/arm/dts/k3-am625-verdin-r5.dts
index 6b03e7405af..2b333e70f5c 100644
--- a/arch/arm/dts/k3-am625-verdin-r5.dts
+++ b/arch/arm/dts/k3-am625-verdin-r5.dts
@@ -23,7 +23,7 @@
*/
assigned-clocks = <_clks 61 0>, <_clks 135 0>, <_clks
157 20>;
assigned-clock-parents = <_clks 61 2>, <0>, <_clks 157
22>;
- assigned-clock-rates = <2>, <10>, <2500>;
+ assigned-clock-rates = <2>, <8>, <2500>;
clocks = <_clks 61 0>;
power-domains = <_pds 61 TI_SCI_PD_EXCLUSIVE>,
<_pds 135 TI_SCI_PD_EXCLUSIVE>,
--
2.34.1
[PATCH] toradex: tdx-cfg-block: add 0087 i.mx8m mini product variant
From: Joao Paulo Goncalves
Add new product id 0087 Verdin iMX8M Mini Quad 2GB IT.
Signed-off-by: Joao Paulo Goncalves
---
board/toradex/common/tdx-cfg-block.c | 1 +
board/toradex/common/tdx-cfg-block.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/board/toradex/common/tdx-cfg-block.c
b/board/toradex/common/tdx-cfg-block.c
index 4a7de5483d2..dcf00d2b632 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -157,6 +157,7 @@ const struct toradex_som toradex_modules[] = {
[84] = { "Apalis iMX6D 1GB IT",
TARGET_IS_ENABLED(APALIS_IMX6) },
[85] = { "Apalis iMX6Q 2GB IT",
TARGET_IS_ENABLED(APALIS_IMX6) },
[86] = { "Verdin iMX8M Mini DualLite 2GB IT",
TARGET_IS_ENABLED(VERDIN_IMX8MM) },
+ [87] = { "Verdin iMX8M Mini Quad 2GB IT",
TARGET_IS_ENABLED(VERDIN_IMX8MM) },
};
struct pid4list {
diff --git a/board/toradex/common/tdx-cfg-block.h
b/board/toradex/common/tdx-cfg-block.h
index 021cc21b5e2..183ee0f2dc9 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -112,6 +112,7 @@ enum {
APALIS_IMX6D_IT_NOWINCE,
APALIS_IMX6Q_IT_NOWINCE, /* 85 */
VERDIN_IMX8MMDL_2G_IT,
+ VERDIN_IMX8MMQ_2G_IT_NO_CAN,
};
enum {
--
2.34.1
[PATCH] toradex: tdx-cfg-block: add 0086 i.mx8m mini sku
From: Joao Paulo Goncalves
Add new product id 0086 Verdin iMX8M Mini DualLite 2GB IT.
Signed-off-by: Joao Paulo Goncalves
---
Hello,
The change was based on u-boot-imx/master-next because of [1].
[1]
https://lore.kernel.org/u-boot/20240122200930.673447-1-jpaulo.silvagoncal...@gmail.com/
Best Regards,
Joao Paulo Goncalves
board/toradex/common/tdx-cfg-block.c | 1 +
board/toradex/common/tdx-cfg-block.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/board/toradex/common/tdx-cfg-block.c
b/board/toradex/common/tdx-cfg-block.c
index 3f2f6b94391..4a7de5483d2 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -156,6 +156,7 @@ const struct toradex_som toradex_modules[] = {
[83] = { "Apalis iMX6Q 1GB",
TARGET_IS_ENABLED(APALIS_IMX6) },
[84] = { "Apalis iMX6D 1GB IT",
TARGET_IS_ENABLED(APALIS_IMX6) },
[85] = { "Apalis iMX6Q 2GB IT",
TARGET_IS_ENABLED(APALIS_IMX6) },
+ [86] = { "Verdin iMX8M Mini DualLite 2GB IT",
TARGET_IS_ENABLED(VERDIN_IMX8MM) },
};
struct pid4list {
diff --git a/board/toradex/common/tdx-cfg-block.h
b/board/toradex/common/tdx-cfg-block.h
index b783537ce76..021cc21b5e2 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -111,6 +111,7 @@ enum {
APALIS_IMX6Q_NOWINCE,
APALIS_IMX6D_IT_NOWINCE,
APALIS_IMX6Q_IT_NOWINCE, /* 85 */
+ VERDIN_IMX8MMDL_2G_IT,
};
enum {
--
2.34.1
[PATCH] toradex: tdx-cfg-block: Add new apalis and colibri pid
From: Joao Paulo Goncalves
Add new apalis imx6 and colibri imx6/imx7 products IDs.
Signed-off-by: Joao Paulo Goncalves
---
board/toradex/common/tdx-cfg-block.c | 9 +
board/toradex/common/tdx-cfg-block.h | 9 +
2 files changed, 18 insertions(+)
diff --git a/board/toradex/common/tdx-cfg-block.c
b/board/toradex/common/tdx-cfg-block.c
index 7187e1ba377..7affc290395 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -147,6 +147,15 @@ const struct toradex_som toradex_modules[] = {
[74] = { "Verdin AM62 Dual 1GB IT",
TARGET_IS_ENABLED(VERDIN_AM62_A53) },
[75] = { "Verdin AM62 Dual 1GB WB IT",
TARGET_IS_ENABLED(VERDIN_AM62_A53) },
[76] = { "Verdin AM62 Quad 2GB WB IT",
TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+ [77] = { "Colibri iMX6S 256MB",
TARGET_IS_ENABLED(COLIBRI_IMX6)},
+ [78] = { "Colibri iMX6S 256MB IT",
TARGET_IS_ENABLED(COLIBRI_IMX6)},
+ [79] = { "Colibri iMX6DL 512MB",
TARGET_IS_ENABLED(COLIBRI_IMX6)},
+ [80] = { "Colibri iMX6DL 512MB IT",
TARGET_IS_ENABLED(COLIBRI_IMX6)},
+ [81] = { "Colibri iMX7D 512MB",
TARGET_IS_ENABLED(COLIBRI_IMX7)},
+ [82] = { "Apalis iMX6D 512MB",
TARGET_IS_ENABLED(APALIS_IMX6) },
+ [83] = { "Apalis iMX6Q 1GB",
TARGET_IS_ENABLED(APALIS_IMX6) },
+ [84] = { "Apalis iMX6D 1GB IT",
TARGET_IS_ENABLED(APALIS_IMX6) },
+ [85] = { "Apalis iMX6Q 2GB IT",
TARGET_IS_ENABLED(APALIS_IMX6) },
};
struct pid4list {
diff --git a/board/toradex/common/tdx-cfg-block.h
b/board/toradex/common/tdx-cfg-block.h
index ea58bd43b17..b783537ce76 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -102,6 +102,15 @@ enum {
VERDIN_AM62D_1G_IT,
VERDIN_AM62D_1G_WIFI_BT_IT, /* 75 */
VERDIN_AM62Q_2G_WIFI_BT_IT,
+ COLIBRI_IMX6S_NOWINCE,
+ COLIBRI_IMX6S_IT_NOWINCE,
+ COLIBRI_IMX6DL_NOWINCE,
+ COLIBRI_IMX6DL_IT_NOWINCE, /* 80 */
+ COLIBRI_IMX7D_NOWINCE,
+ APALIS_IMX6D_NOWINCE,
+ APALIS_IMX6Q_NOWINCE,
+ APALIS_IMX6D_IT_NOWINCE,
+ APALIS_IMX6Q_IT_NOWINCE, /* 85 */
};
enum {
--
2.34.1
[PATCH 1/1] arm: k3: Enable instruction cache for main domain SPL
From: Joao Paulo Goncalves
Change spl_enable_dcache so it also enable icache on SPL
initialization for the main domain part of the boot flow. This
improves bootloader booting time.
Link:
https://lore.kernel.org/all/20231109140958.1093235-1-joao.goncal...@toradex.com/
Signed-off-by: Joao Paulo Goncalves
---
arch/arm/mach-k3/am625_init.c | 2 +-
arch/arm/mach-k3/am654_init.c | 2 +-
arch/arm/mach-k3/common.c | 4 ++--
arch/arm/mach-k3/common.h | 2 +-
arch/arm/mach-k3/j721e_init.c | 2 +-
arch/arm/mach-k3/j721s2_init.c | 2 +-
6 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c
index 8fa36f7b91..1d4ef35e7b 100644
--- a/arch/arm/mach-k3/am625_init.c
+++ b/arch/arm/mach-k3/am625_init.c
@@ -209,7 +209,7 @@ void board_init_f(ulong dummy)
if (ret)
panic("DRAM init failed: %d\n", ret);
}
- spl_enable_dcache();
+ spl_enable_cache();
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
diff --git a/arch/arm/mach-k3/am654_init.c b/arch/arm/mach-k3/am654_init.c
index 0d3889cde2..f46b063d91 100644
--- a/arch/arm/mach-k3/am654_init.c
+++ b/arch/arm/mach-k3/am654_init.c
@@ -259,7 +259,7 @@ void board_init_f(ulong dummy)
if (ret)
panic("DRAM init failed: %d\n", ret);
#endif
- spl_enable_dcache();
+ spl_enable_cache();
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index c3006ba387..f609e3001f 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -522,7 +522,7 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t
fwl_data_size)
}
}
-void spl_enable_dcache(void)
+void spl_enable_cache(void)
{
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
phys_addr_t ram_top = CFG_SYS_SDRAM_BASE;
@@ -543,7 +543,7 @@ void spl_enable_dcache(void)
gd->arch.tlb_addr + gd->arch.tlb_size);
gd->relocaddr = gd->arch.tlb_addr;
- dcache_enable();
+ enable_caches();
#endif
}
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index eabb44f620..bb84e98b55 100644
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -37,7 +37,7 @@ void disable_linefill_optimization(void);
void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size);
int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr);
void k3_sysfw_print_ver(void);
-void spl_enable_dcache(void);
+void spl_enable_cache(void);
void mmr_unlock(uintptr_t base, u32 partition);
bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
enum k3_device_type get_device_type(void);
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index b1f7e25ed0..7d793801de 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -287,7 +287,7 @@ void board_init_f(ulong dummy)
if (ret)
panic("DRAM init failed: %d\n", ret);
#endif
- spl_enable_dcache();
+ spl_enable_cache();
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c
index a5be84b147..d46d91e652 100644
--- a/arch/arm/mach-k3/j721s2_init.c
+++ b/arch/arm/mach-k3/j721s2_init.c
@@ -232,7 +232,7 @@ void k3_mem_init(void)
if (ret)
panic("DRAM 1 init failed: %d\n", ret);
}
- spl_enable_dcache();
+ spl_enable_cache();
}
/* Support for the various EVM / SK families */
--
2.34.1
[RFC PATCH 1/1] arm: mach-k3: Enable icache on am625 to boot faster
Enable the am625 instruction cache on SPL and U-boot earlier for the A53
to execute code a bit faster. For normal boot flow, it was possible to
gain about 2 seconds on boot time.
Signed-off-by: Joao Paulo Goncalves
---
Hello all,
We are trying to optimize boot time on our AM62 devices and on TI community
forum [1] someone advised to enable ICACHE for am625. We enabled it, tested and
got
around 2 seconds faster boot on storage media and about 5 seconds with DFU
for downloading images from A53 SPL. However, we don't know if this is the
correct
solution and want more comments on this or why the ICACHE was not enabled by TI
in
the first place.
[1]
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1217839/am625-boot-time-between-a53-spl-and-a53-u-boot
Regards,
Joao Paulo Goncalves
arch/arm/mach-k3/am625_init.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c
index 8fa36f7b91..d665d07b0b 100644
--- a/arch/arm/mach-k3/am625_init.c
+++ b/arch/arm/mach-k3/am625_init.c
@@ -210,6 +210,9 @@ void board_init_f(ulong dummy)
panic("DRAM init failed: %d\n", ret);
}
spl_enable_dcache();
+
+ if (!IS_ENABLED(CONFIG_CPU_V7R) && !IS_ENABLED(CONFIG_SYS_ICACHE_OFF))
+ icache_enable();
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
--
2.34.1
Re: Port gen_compile_commands.py from Linux to U-Boot
>Hello U-Boot community, >I'm submitting a patch series that ports the gen_compile_commands.py >script from the Linux kernel's sources to U-Boot. This script, originally >located in scripts/clang-tools/gen_compile_commands.py, enables the >generation of compile_commands.json file for improved code navigation >and analysis. The series consists of the initial script import, the >necessary modifications for U-Boot compatibility, and finally some >documentation. Tested-by: Joao Paulo Goncalves
