[PATCH] doc: board: sophgo: milkv_duo: Update Milk-V Duo documentation
Add detailed steps for compiling U-Boot and OpenSBI, generating the firmware package with fiptool, and booting the board. Signed-off-by: Kongyang Liu --- doc/board/sophgo/milkv_duo.rst | 41 +- 1 file changed, 30 insertions(+), 11 deletions(-) diff --git a/doc/board/sophgo/milkv_duo.rst b/doc/board/sophgo/milkv_duo.rst index cb2ed1ad98..a88db5b903 100644 --- a/doc/board/sophgo/milkv_duo.rst +++ b/doc/board/sophgo/milkv_duo.rst @@ -20,31 +20,50 @@ Building .. code-block:: console export CROSS_COMPILE= + +3. Compile U-Boot + +.. code-block:: console + cd make milkv_duo_defconfig make -This will generate u-boot-dtb.bin +This will generate u-boot.bin and u-boot.dtb -Booting -~~~ -Currently, we rely on vendor FSBL(First Stage Boot Loader) to initialize the -clock and load the u-boot image, then bootup from it. +4. Compile OpenSBI + +.. code-block:: console -Alternatively, to run u-boot-dtb.bin on top of FSBL, follow these steps: + cd + make PLATFORM=generic FW_FDT_PATH=/u-boot.dtb -1. Use the vendor-provided tool to create a unified fip.bin file containing - FSBL, OpenSBI, and U-Boot. +This will generate fw_dynamic.bin -2. Place the generated fip.bin file into the FAT partition of the SD card. +4. Generate firmware image package -3. Insert the SD card into the board and power it on. +Fiptool(https://github.com/sophgo/fiptool) is used to generate fip file. + +.. code-block:: console + + git clone https://github.com/sophgo/fiptool + cd fiptool + ./fiptool \ + --fsbl data/fsbl/cv180x.bin \ + --opensbi /fw_dynamic.bin \ + --uboot /u-boot.bin \ + +This will generate fip.bin + +Booting +~~~ +1. Place the generated fip.bin file into the FAT partition of the SD card. +2. Insert the SD card into the board and power it on. The board will automatically execute the FSBL from the fip.bin file. Subsequently, it will transition to OpenSBI, and finally, OpenSBI will invoke U-Boot. - Sample boot log from Milk-V Duo board ~ .. code-block:: none -- 2.41.0
Re: [PATCH 2/4] clk: sophgo: cv1800b: Add clock controller driver for cv1800b SoC
Yixun Lan 于2024年5月23日周四 07:39写道：
>
> Hi Kongyang:
>
> I've got one compiling error
>
> On 23:07 Sun 19 May , Kongyang Liu wrote:
> > Add clock controller driver for sophgo cv1800b SoC
> >
> > Signed-off-by: Kongyang Liu
> > ---
> >
> > drivers/clk/Kconfig | 1 +
> > drivers/clk/Makefile | 1 +
> > drivers/clk/sophgo/Kconfig | 14 +
> > drivers/clk/sophgo/Makefile | 6 +
> > drivers/clk/sophgo/clk-common.h | 74 +++
> > drivers/clk/sophgo/clk-cv1800b.c | 794 +++
> > drivers/clk/sophgo/clk-cv1800b.h | 123 +
> > drivers/clk/sophgo/clk-ip.c | 594 +++
> > drivers/clk/sophgo/clk-ip.h | 288 +++
> > drivers/clk/sophgo/clk-pll.c | 284 +++
> > drivers/clk/sophgo/clk-pll.h | 74 +++
> > 11 files changed, 2253 insertions(+)
> > create mode 100644 drivers/clk/sophgo/Kconfig
> > create mode 100644 drivers/clk/sophgo/Makefile
> > create mode 100644 drivers/clk/sophgo/clk-common.h
> > create mode 100644 drivers/clk/sophgo/clk-cv1800b.c
> > create mode 100644 drivers/clk/sophgo/clk-cv1800b.h
> > create mode 100644 drivers/clk/sophgo/clk-ip.c
> > create mode 100644 drivers/clk/sophgo/clk-ip.h
> > create mode 100644 drivers/clk/sophgo/clk-pll.c
> > create mode 100644 drivers/clk/sophgo/clk-pll.h
> >
>
> ...
>
> > +static ulong cv1800b_ipll_set_rate(struct clk *clk, ulong rate)
> > +{
> > + struct cv1800b_clk_ipll *pll = to_clk_ipll(clk);
> > + ulong parent_rate = clk_get_parent_rate(clk);
> > + u32 pre_div, post_div, div;
> > + u32 pre_div_sel, post_div_sel, div_sel;
> > + ulong new_rate, best_rate = 0;
> > + u32 mode, ictrl;
> > + u32 test, val;
> > +
> > + FOR_RANGE(pre_div, PLL_PRE_DIV)
> > + {
> > + FOR_RANGE(post_div, PLL_POST_DIV)
> > + {
> > + FOR_RANGE(div, PLL_DIV)
> > + {
> > + new_rate = DIV_ROUND_DOWN_ULL(parent_rate *
> > div
>
> ~~
> miss a comma here
I will fix it.
> > + pre_div *
> > post_div);
> > + if (rate - new_rate < rate - best_rate) {
> > + best_rate = new_rate;
> > + pre_div_sel = pre_div;
> > + post_div_sel = post_div;
> > + div_sel = div;
> > + }
> > + }
> > + }
> > + }
> > +
> > + FOR_RANGE(mode, PLL_MODE)
>
> --
> Yixun Lan (dlan)
> Gentoo Linux Developer
> GPG Key ID AABEFD55
[PATCH 1/2] usb: dwc2: Extract USB DWC2 register definitions
Extract the register definitions and their bit definitions from the USB
DWC2 driver host and device into a common file.
Signed-off-by: Kongyang Liu
---
drivers/usb/common/Makefile| 2 +
drivers/usb/common/dwc2_core.c | 53 ++
drivers/usb/common/dwc2_core.h | 556
drivers/usb/gadget/dwc2_udc_otg.c | 124 ++--
drivers/usb/gadget/dwc2_udc_otg_regs.h | 247 +--
drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c | 306 -
drivers/usb/host/dwc2.c| 362 +-
drivers/usb/host/dwc2.h| 736 -
8 files changed, 988 insertions(+), 1398 deletions(-)
create mode 100644 drivers/usb/common/dwc2_core.c
create mode 100644 drivers/usb/common/dwc2_core.h
diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile
index 2e9353b76a..708f13c52c 100644
--- a/drivers/usb/common/Makefile
+++ b/drivers/usb/common/Makefile
@@ -4,6 +4,8 @@
#
obj-$(CONFIG_$(SPL_)DM_USB) += common.o
+obj-$(CONFIG_USB_DWC2) += dwc2_core.o
+obj-$(CONFIG_USB_GADGET_DWC2_OTG) += dwc2_core.o
obj-$(CONFIG_USB_ISP1760) += usb_urb.o
obj-$(CONFIG_USB_MUSB_HOST) += usb_urb.o
obj-$(CONFIG_USB_MUSB_GADGET) += usb_urb.o
diff --git a/drivers/usb/common/dwc2_core.c b/drivers/usb/common/dwc2_core.c
new file mode 100644
index 00..2fa11fd59d
--- /dev/null
+++ b/drivers/usb/common/dwc2_core.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ */
+
+#include
+#include
+#include
+#include
+
+#include "dwc2_core.h"
+
+void dwc2_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
+{
+ int ret;
+
+ log_debug("Flush Tx FIFO %d\n", num);
+
+ /* Wait for AHB master IDLE state */
+ ret = wait_for_bit_le32(>global_regs.grstctl, GRSTCTL_AHBIDLE,
true, 1000, false);
+ if (ret)
+ log_warning("%s: Waiting for GRSTCTL_AHBIDLE timeout\n",
__func__);
+
+ writel(GRSTCTL_TXFFLSH | FIELD_PREP(GRSTCTL_TXFNUM_MASK, num),
>global_regs.grstctl);
+
+ ret = wait_for_bit_le32(>global_regs.grstctl, GRSTCTL_TXFFLSH,
false, 1000, false);
+ if (ret)
+ log_warning("%s: Waiting for GRSTCTL_TXFFLSH timeout\n",
__func__);
+
+ /* Wait for 3 PHY Clocks */
+ udelay(1);
+}
+
+void dwc2_flush_rx_fifo(struct dwc2_core_regs *regs)
+{
+ int ret;
+
+ log_debug("Flush Rx FIFO\n");
+
+ /* Wait for AHB master IDLE state */
+ ret = wait_for_bit_le32(>global_regs.grstctl, GRSTCTL_AHBIDLE,
true, 1000, false);
+ if (ret)
+ log_warning("%s: Waiting for GRSTCTL_AHBIDLE timeout\n",
__func__);
+
+ writel(GRSTCTL_RXFFLSH, >global_regs.grstctl);
+
+ ret = wait_for_bit_le32(>global_regs.grstctl, GRSTCTL_RXFFLSH,
false, 1000, false);
+ if (ret)
+ log_warning("%s: Waiting for GRSTCTL_RXFFLSH timeout\n",
__func__);
+
+ /* Wait for 3 PHY Clocks */
+ udelay(1);
+}
diff --git a/drivers/usb/common/dwc2_core.h b/drivers/usb/common/dwc2_core.h
new file mode 100644
index 00..8303153446
--- /dev/null
+++ b/drivers/usb/common/dwc2_core.h
@@ -0,0 +1,556 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ *
+ */
+
+#ifndef __DWC2_CORE_H_
+#define __DWC2_CORE_H_
+
+#include
+
+struct dwc2_global_regs {
+ u32 gotgctl;
+ u32 gotgint;
+ u32 gahbcfg;
+ u32 gusbcfg;
+ u32 grstctl;
+ u32 gintsts;
+ u32 gintmsk;
+ u32 grxstsr;
+ u32 grxstsp;
+ u32 grxfsiz;
+ u32 gnptxfsiz;
+ u32 gnptxsts;
+ u32 gi2cctl;
+ u32 gpvndctl;
+ u32 ggpio;
+ u32 guid;
+ u32 gsnpsid;
+ u32 ghwcfg1;
+ u32 ghwcfg2;
+ u32 ghwcfg3;
+ u32 ghwcfg4;
+ u32 glpmcfg;
+ u32 gpwrdn;
+ u32 gdfifocfg;
+ u32 gadpctl;
+ u32 grefclk;
+ u32 gintmsk2;
+ u32 gintsts2;
+ u8 _pad_from_0x70_to_0x100[0x100 - 0x70];
+ u32 hptxfsiz;
+ u32 dptxfsizn[15];
+ u8 _pad_from_0x140_to_0x400[0x400 - 0x140];
+};
+
+struct dwc2_hc_regs {
+ u32 hcchar;
+ u32 hcsplt;
+ u32 hcint;
+ u32 hcintmsk;
+ u32 hctsiz;
+ u32 hcdma;
+ u32 reserved;
+ u32 hcdmab;
+};
+
+struct dwc2_host_regs {
+ u32 hcfg;
+ u32 hfir;
+ u32 hfnum;
+ u32 _pad_0x40c;
+ u32 hptxsts;
+ u32 haint;
+ u32 haintmsk;
+ u32 hflbaddr;
+ u8 _pad_from_0x420_to_0x440[0x440 - 0x420];
+ u32 hprt0;
+ u8 _pad_from_0x444_to_0x500[0x500 - 0x444];
+ struct dwc2_hc_regs hc[16];
+ u8 _pad_from_0x700_to_0x800[0x800 - 0x700];
+};
+
+struct dwc2_dev_in_endp {
+ u32 diepctl;
+ u32 reserved0;
+ u32 diepint;
+ u32 reserved1;
+ u32 dieptsiz;
+ u32 diepdma;
+ u32 reserved2;
[PATCH 2/2] usb: dwc2: Update reset method for host and device mode
Starting from version 4.20a, there has been a change in the reset method.
A new bit, GRSTCTL_CSFTRST_DONE, has been introduced in the GRSTCTL
register to indicate whether the reset has been completed.
This patch mainly refers to the patch in the kernel.
Link:
https://lore.kernel.org/all/9be2bb0c728da3dabf634c894f77e0e9709edeaa.1590040892.git.hmi...@synopsys.com/
Signed-off-by: Kongyang Liu
---
drivers/usb/common/dwc2_core.c| 50 +++
drivers/usb/common/dwc2_core.h| 1 +
drivers/usb/gadget/dwc2_udc_otg.c | 2 +-
drivers/usb/host/dwc2.c | 36 ++
4 files changed, 55 insertions(+), 34 deletions(-)
diff --git a/drivers/usb/common/dwc2_core.c b/drivers/usb/common/dwc2_core.c
index 2fa11fd59d..323326e05d 100644
--- a/drivers/usb/common/dwc2_core.c
+++ b/drivers/usb/common/dwc2_core.c
@@ -10,6 +10,56 @@
#include "dwc2_core.h"
+int dwc2_core_reset(struct dwc2_core_regs *regs)
+{
+ u32 snpsid;
+ int ret;
+ bool host_mode = false;
+
+ if (!(readl(>global_regs.gotgctl) & GOTGCTL_CONID_B) ||
+ (readl(>global_regs.gusbcfg) & GUSBCFG_FORCEDEVMODE))
+ host_mode = true;
+
+ /* Core Soft Reset */
+ snpsid = readl(>global_regs.gsnpsid);
+ writel(GRSTCTL_CSFTRST, >global_regs.grstctl);
+ if (FIELD_GET(GSNPSID_VER_MASK, snpsid) < 0x420a) {
+ ret = wait_for_bit_le32(>global_regs.grstctl,
GRSTCTL_CSFTRST,
+ false, 1000, false);
+ if (ret) {
+ log_warning("%s: Waiting for GRSTCTL_CSFTRST
timeout\n", __func__);
+ return -EBUSY;
+ }
+ } else {
+ ret = wait_for_bit_le32(>global_regs.grstctl,
GRSTCTL_CSFTRST_DONE,
+ true, 1000, false);
+ if (ret) {
+ log_warning("%s: Waiting for GRSTCTL_CSFTRST_DONE
timeout\n", __func__);
+ return -EBUSY;
+ }
+ clrsetbits_le32(>global_regs.grstctl, GRSTCTL_CSFTRST,
GRSTCTL_CSFTRST_DONE);
+ }
+
+ /* Wait for AHB master IDLE state. */
+ ret = wait_for_bit_le32(>global_regs.grstctl, GRSTCTL_AHBIDLE,
+ true, 1000, false);
+ if (ret) {
+ log_warning("%s: Waiting for GRSTCTL_AHBIDLE timeout\n",
__func__);
+ return -EBUSY;
+ }
+
+ if (host_mode) {
+ ret = wait_for_bit_le32(>global_regs.gintsts,
GINTSTS_CURMODE_HOST,
+ host_mode, 1000, false);
+ if (ret) {
+ log_warning("%s: Waiting for GINTSTS_CURMODE_HOST
timeout\n", __func__);
+ return -EBUSY;
+ }
+ }
+
+ return 0;
+}
+
void dwc2_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
{
int ret;
diff --git a/drivers/usb/common/dwc2_core.h b/drivers/usb/common/dwc2_core.h
index 8303153446..dd6937dd30 100644
--- a/drivers/usb/common/dwc2_core.h
+++ b/drivers/usb/common/dwc2_core.h
@@ -123,6 +123,7 @@ struct dwc2_core_regs {
u8 ep_fifo[16][0x1000];
};
+int dwc2_core_reset(struct dwc2_core_regs *regs);
void dwc2_flush_tx_fifo(struct dwc2_core_regs *regs, const int num);
void dwc2_flush_rx_fifo(struct dwc2_core_regs *regs);
diff --git a/drivers/usb/gadget/dwc2_udc_otg.c
b/drivers/usb/gadget/dwc2_udc_otg.c
index ac902b325a..727832e859 100644
--- a/drivers/usb/gadget/dwc2_udc_otg.c
+++ b/drivers/usb/gadget/dwc2_udc_otg.c
@@ -469,7 +469,7 @@ static void reconfig_usbd(struct dwc2_udc *dev)
u32 max_hw_ep;
int pdata_hw_ep;
- writel(GRSTCTL_CSFTRST, >global_regs.grstctl);
+ dwc2_core_reset(reg);
debug("Resetting OTG controller\n");
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 93ed9604c2..6e73a3d90d 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -109,36 +109,6 @@ static void init_fslspclksel(struct dwc2_core_regs *regs)
FIELD_PREP(HCFG_FSLSPCLKSEL_MASK, phyclk));
}
-/*
- * Do core a soft reset of the core. Be careful with this because it
- * resets all the internal state machines of the core.
- */
-static void dwc_otg_core_reset(struct udevice *dev,
- struct dwc2_core_regs *regs)
-{
- int ret;
-
- /* Wait for AHB master IDLE state. */
- ret = wait_for_bit_le32(>global_regs.grstctl, GRSTCTL_AHBIDLE,
- true, 1000, false);
- if (ret)
- dev_info(dev, "%s: Timeout!\n", __func__);
-
- /* Core Soft Reset */
- writel(GRSTCTL_CSFTRST, >global_regs.grstctl);
- ret = wait_for_bit_le32(>global_regs.grstctl, GRSTCTL_CSFTRST,
- false
[PATCH 0/2] usb: dwc2: Refactor and update USB DWC2 driver
This series improves the USB DWC2 driver by extracting register definitions into a common file for better readability and updating the reset method to reflect changes in version 4.20a, including the new GRSTCTL_CSFTRST_DONE bit for reset completion indication. Kongyang Liu (2): usb: dwc2: Extract USB DWC2 register definitions usb: dwc2: Update reset method for host and device mode drivers/usb/common/Makefile| 2 + drivers/usb/common/dwc2_core.c | 103 +++ drivers/usb/common/dwc2_core.h | 557 drivers/usb/gadget/dwc2_udc_otg.c | 124 ++-- drivers/usb/gadget/dwc2_udc_otg_regs.h | 247 +-- drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c | 306 - drivers/usb/host/dwc2.c| 392 +-- drivers/usb/host/dwc2.h| 736 - 8 files changed, 1039 insertions(+), 1428 deletions(-) create mode 100644 drivers/usb/common/dwc2_core.c create mode 100644 drivers/usb/common/dwc2_core.h -- 2.41.0
[PATCH 4/4] riscv: dts: sophgo: Replace device clocks with real clocks.
Replace device clocks with real clocks from the clock controller, and
remove dummy clocks.
Signed-off-by: Kongyang Liu
---
arch/riscv/dts/cv18xx.dtsi | 40 +++---
1 file changed, 16 insertions(+), 24 deletions(-)
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index 4b0143450e..8a7386b76e 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -5,6 +5,7 @@
*/
#include
+#include
/ {
#address-cells = <1>;
@@ -45,13 +46,6 @@
#clock-cells = <0>;
};
- sdhci_clk: sdhci-clock {
- compatible = "fixed-clock";
- clock-frequency = <37500>;
- clock-output-names = "sdhci_clk";
- #clock-cells = <0>;
- };
-
eth_csrclk: eth-csrclk {
compatible = "fixed-clock";
clock-frequency = <25000>;
@@ -66,13 +60,6 @@
#clock-cells = <0x0>;
};
- spif_clk: spi-flash-clock {
- compatible = "fixed-clock";
- clock-frequency = <3>;
- clock-output-names = "spif_clk";
- #clock-cells = <0>;
- };
-
soc {
compatible = "simple-bus";
interrupt-parent = <>;
@@ -163,8 +150,8 @@
compatible = "sophgo,cv1800b-dwmac";
reg = <0x0407 0x1>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <_csrclk>, <_ptpclk>;
- clock-names = "stmmaceth", "ptp_ref";
+ clocks = < CLK_ETH0_500M>, < CLK_AXI4_ETH0>;
+ clock-names = "stmmaceth", "pclk";
status = "disabled";
};
@@ -172,7 +159,8 @@
compatible = "snps,dw-apb-uart";
reg = <0x0414 0x100>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <>;
+ clocks = < CLK_UART0>, < CLK_APB_UART0>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -182,7 +170,8 @@
compatible = "snps,dw-apb-uart";
reg = <0x0415 0x100>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <>;
+ clocks = < CLK_UART4>, < CLK_APB_UART4>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -192,7 +181,8 @@
compatible = "snps,dw-apb-uart";
reg = <0x0416 0x100>;
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <>;
+ clocks = < CLK_UART2>, < CLK_APB_UART2>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -202,7 +192,8 @@
compatible = "snps,dw-apb-uart";
reg = <0x0417 0x100>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <>;
+ clocks = < CLK_UART3>, < CLK_APB_UART3>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -212,7 +203,8 @@
compatible = "snps,dw-apb-uart";
reg = <0x041c 0x100>;
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <>;
+ clocks = < CLK_UART4>, < CLK_APB_UART4>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -222,8 +214,8 @@
compatible = "sophgo,cv1800b-dwcmshc";
reg = <0x431
[PATCH 2/4] clk: sophgo: cv1800b: Add clock controller driver for cv1800b SoC
Add clock controller driver for sophgo cv1800b SoC
Signed-off-by: Kongyang Liu
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/sophgo/Kconfig | 14 +
drivers/clk/sophgo/Makefile | 6 +
drivers/clk/sophgo/clk-common.h | 74 +++
drivers/clk/sophgo/clk-cv1800b.c | 794 +++
drivers/clk/sophgo/clk-cv1800b.h | 123 +
drivers/clk/sophgo/clk-ip.c | 594 +++
drivers/clk/sophgo/clk-ip.h | 288 +++
drivers/clk/sophgo/clk-pll.c | 284 +++
drivers/clk/sophgo/clk-pll.h | 74 +++
11 files changed, 2253 insertions(+)
create mode 100644 drivers/clk/sophgo/Kconfig
create mode 100644 drivers/clk/sophgo/Makefile
create mode 100644 drivers/clk/sophgo/clk-common.h
create mode 100644 drivers/clk/sophgo/clk-cv1800b.c
create mode 100644 drivers/clk/sophgo/clk-cv1800b.h
create mode 100644 drivers/clk/sophgo/clk-ip.c
create mode 100644 drivers/clk/sophgo/clk-ip.h
create mode 100644 drivers/clk/sophgo/clk-pll.c
create mode 100644 drivers/clk/sophgo/clk-pll.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9acbc47fe8..d9d518d703 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -257,6 +257,7 @@ source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/owl/Kconfig"
source "drivers/clk/qcom/Kconfig"
source "drivers/clk/renesas/Kconfig"
+source "drivers/clk/sophgo/Kconfig"
source "drivers/clk/sunxi/Kconfig"
source "drivers/clk/sifive/Kconfig"
source "drivers/clk/starfive/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 847b9b2911..f9b90a38b0 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_CLK_QCOM) += qcom/
obj-$(CONFIG_CLK_RENESAS) += renesas/
obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o
obj-$(CONFIG_CLK_SIFIVE) += sifive/
+obj-$(CONFIG_CLK_SOPHGO) += sophgo/
obj-$(CONFIG_CLK_SUNXI) += sunxi/
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
diff --git a/drivers/clk/sophgo/Kconfig b/drivers/clk/sophgo/Kconfig
new file mode 100644
index 00..59b51608fe
--- /dev/null
+++ b/drivers/clk/sophgo/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu
+
+config CLK_SOPHGO
+ bool
+
+config CLK_SOPHGO_CV1800B
+ bool "Sophgo CV1800B clock support"
+ depends on CLK
+ select CLK_CCF
+ select CLK_SOPHGO
+ help
+ This enables support clock driver for Sophgo CV1800B SoC.
diff --git a/drivers/clk/sophgo/Makefile b/drivers/clk/sophgo/Makefile
new file mode 100644
index 00..caec76222b
--- /dev/null
+++ b/drivers/clk/sophgo/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu
+
+obj-y += clk-ip.o clk-pll.o
+obj-$(CONFIG_CLK_SOPHGO_CV1800B) += clk-cv1800b.o
diff --git a/drivers/clk/sophgo/clk-common.h b/drivers/clk/sophgo/clk-common.h
new file mode 100644
index 00..95b82e968d
--- /dev/null
+++ b/drivers/clk/sophgo/clk-common.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ *
+ */
+
+#ifndef __CLK_SOPHGO_COMMON_H__
+#define __CLK_SOPHGO_COMMON_H__
+
+#include
+#include
+
+#define CV1800B_CLK_OSC 1
+#define CV1800B_CLK_BYPASS 2
+#define CV1800B_CLK_ID_TRANSFORM(_id) ((_id) + 3)
+
+struct cv1800b_clk_regbit {
+ u32 offset;
+ u8 shift;
+};
+
+struct cv1800b_clk_regfield {
+ u32 offset;
+ u8 shift;
+ u8 width;
+};
+
+#define CV1800B_CLK_REGBIT(_offset, _shift)\
+ { \
+ .offset = _offset, \
+ .shift = _shift,\
+ }
+
+#define CV1800B_CLK_REGFIELD(_offset, _shift, _width) \
+ { \
+ .offset = _offset, \
+ .shift = _shift,\
+ .width = _width,\
+ }
+
+static inline u32 cv1800b_clk_getbit(void *base, struct cv1800b_clk_regbit
*bit)
+{
+ return readl(base + bit->offset) & (BIT(bit->shift));
+}
+
+static inline u32 cv1800b_clk_setbit(void *base, struct cv1800b_clk_regbit
*bit)
+{
+ return setbits_le32(base + bit->offset, BIT(bit->shift));
+}
+
+static inline u32 cv1800b_clk_clrbit(void *base, struct cv1800b_clk_regbit
*bit)
+{
+ return clrbits_le32(base + bit->offset, BIT(bit->shift));
+}
+
+static inline u32 cv1800b_clk_getfield(void *base,
+ struct cv1800b_clk_regfield *field)
+{
+ u32 mask = GENMASK(field->shift + field->width - 1, field->shift);
+
+ return (readl(base + field->offset) & mask) >> field->shift;
+}
+
+static inline void
[PATCH 3/4] configs: milkv_duo: Enable clock controller
Add configs to enable clock controller for Sophgo Milk-V Duo board Signed-off-by: Kongyang Liu --- configs/milkv_duo_defconfig | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig index 0cb2922de4..1186763a73 100644 --- a/configs/milkv_duo_defconfig +++ b/configs/milkv_duo_defconfig @@ -1,6 +1,6 @@ CONFIG_RISCV=y CONFIG_SYS_MALLOC_LEN=0x82 -CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8230 @@ -26,17 +26,18 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK_SOPHGO_CV1800B=y CONFIG_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_CV1800B=y +CONFIG_SPI_FLASH_MACRONIX=y CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550_MEM32=y -CONFIG_SYSRESET=y -CONFIG_SYSRESET_CV1800B=y -CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI=y CONFIG_CV1800B_SPIF=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_CV1800B=y -- 2.41.0
[PATCH 1/4] dt-bindings: clk: import header for clock controller of sophgo CV1800B
Import header file of sophgo cv1800b clock controller from kernel Signed-off-by: Kongyang Liu Link: https://lore.kernel.org/all/ia1pr20mb4953637e7a6c121d7a700f1cbb...@ia1pr20mb4953.namprd20.prod.outlook.com/ --- include/dt-bindings/clock/sophgo,cv1800.h | 176 ++ 1 file changed, 176 insertions(+) create mode 100644 include/dt-bindings/clock/sophgo,cv1800.h diff --git a/include/dt-bindings/clock/sophgo,cv1800.h b/include/dt-bindings/clock/sophgo,cv1800.h new file mode 100644 index 00..cfbeca25a6 --- /dev/null +++ b/include/dt-bindings/clock/sophgo,cv1800.h @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2023 Sophgo Ltd. + */ + +#ifndef __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ +#define __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ + +#define CLK_MPLL 0 +#define CLK_TPLL 1 +#define CLK_FPLL 2 +#define CLK_MIPIMPLL 3 +#define CLK_A0PLL 4 +#define CLK_DISPPLL5 +#define CLK_CAM0PLL6 +#define CLK_CAM1PLL7 + +#define CLK_MIPIMPLL_D38 +#define CLK_CAM0PLL_D2 9 +#define CLK_CAM0PLL_D3 10 + +#define CLK_TPU11 +#define CLK_TPU_FAB12 +#define CLK_AHB_ROM13 +#define CLK_DDR_AXI_REG14 +#define CLK_RTC_25M15 +#define CLK_SRC_RTC_SYS_0 16 +#define CLK_TEMPSEN17 +#define CLK_SARADC 18 +#define CLK_EFUSE 19 +#define CLK_APB_EFUSE 20 +#define CLK_DEBUG 21 +#define CLK_AP_DEBUG 22 +#define CLK_XTAL_MISC 23 +#define CLK_AXI4_EMMC 24 +#define CLK_EMMC 25 +#define CLK_EMMC_100K 26 +#define CLK_AXI4_SD0 27 +#define CLK_SD028 +#define CLK_SD0_100K 29 +#define CLK_AXI4_SD1 30 +#define CLK_SD131 +#define CLK_SD1_100K 32 +#define CLK_SPI_NAND 33 +#define CLK_ETH0_500M 34 +#define CLK_AXI4_ETH0 35 +#define CLK_ETH1_500M 36 +#define CLK_AXI4_ETH1 37 +#define CLK_APB_GPIO 38 +#define CLK_APB_GPIO_INTR 39 +#define CLK_GPIO_DB40 +#define CLK_AHB_SF 41 +#define CLK_AHB_SF142 +#define CLK_A24M 43 +#define CLK_AUDSRC 44 +#define CLK_APB_AUDSRC 45 +#define CLK_SDMA_AXI 46 +#define CLK_SDMA_AUD0 47 +#define CLK_SDMA_AUD1 48 +#define CLK_SDMA_AUD2 49 +#define CLK_SDMA_AUD3 50 +#define CLK_I2C51 +#define CLK_APB_I2C52 +#define CLK_APB_I2C0 53 +#define CLK_APB_I2C1 54 +#define CLK_APB_I2C2 55 +#define CLK_APB_I2C3 56 +#define CLK_APB_I2C4 57 +#define CLK_APB_WDT58 +#define CLK_PWM_SRC59 +#define CLK_PWM60 +#define CLK_SPI61 +#define CLK_APB_SPI0 62 +#define CLK_APB_SPI1 63 +#define CLK_APB_SPI2 64 +#define CLK_APB_SPI3 65 +#define CLK_1M 66 +#define CLK_CAM0_200 67 +#define CLK_PM 68 +#define CLK_TIMER0 69 +#define CLK_TIMER1 70 +#define CLK_TIMER2 71 +#define CLK_TIMER3 72 +#define CLK_TIMER4 73 +#define CLK_TIMER5 74 +#define CLK_TIMER6 75 +#define CLK_TIMER7 76 +#define CLK_UART0 77 +#define CLK_APB_UART0 78 +#define CLK_UART1 79 +#define CLK_APB_UART1 80 +#define CLK_UART2 81 +#define CLK_APB_UART2 82 +#define CLK_UART3 83 +#define CLK_APB_UART3 84 +#define CLK_UART4 85 +#define CLK_APB_UART4 86 +#define CLK_APB_I2S0 87 +#define CLK_APB_I2S1 88 +#define CLK_APB_I2S2 89 +#define CLK_APB_I2S3 90 +#define CLK_AXI4_USB 91 +#define CLK_APB_USB92 +#define CLK_USB_125M 93 +#define CLK_USB_33K94 +#define CLK_USB_12M
[PATCH 0/4] clk: sophgo: milkv_duo: Add and enable clock controller driver
This series of patches introduces the clock controller driver for the Sophgo CV1800B SoC, updates the device tree sources to use the new clock controller, and enables the clock controller in the configuration for the Milk-V Duo board. Kongyang Liu (4): dt-bindings: clk: import header for clock controller of sophgo CV1800B clk: sophgo: cv1800b: Add clock controller driver for cv1800b SoC configs: milkv_duo: Enable clock controller riscv: dts: sophgo: Replace device clocks with real clocks. arch/riscv/dts/cv18xx.dtsi| 40 +- configs/milkv_duo_defconfig | 9 +- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/sophgo/Kconfig| 14 + drivers/clk/sophgo/Makefile | 6 + drivers/clk/sophgo/clk-common.h | 74 ++ drivers/clk/sophgo/clk-cv1800b.c | 794 ++ drivers/clk/sophgo/clk-cv1800b.h | 123 drivers/clk/sophgo/clk-ip.c | 594 drivers/clk/sophgo/clk-ip.h | 288 drivers/clk/sophgo/clk-pll.c | 284 drivers/clk/sophgo/clk-pll.h | 74 ++ include/dt-bindings/clock/sophgo,cv1800.h | 176 + 14 files changed, 2450 insertions(+), 28 deletions(-) create mode 100644 drivers/clk/sophgo/Kconfig create mode 100644 drivers/clk/sophgo/Makefile create mode 100644 drivers/clk/sophgo/clk-common.h create mode 100644 drivers/clk/sophgo/clk-cv1800b.c create mode 100644 drivers/clk/sophgo/clk-cv1800b.h create mode 100644 drivers/clk/sophgo/clk-ip.c create mode 100644 drivers/clk/sophgo/clk-ip.h create mode 100644 drivers/clk/sophgo/clk-pll.c create mode 100644 drivers/clk/sophgo/clk-pll.h create mode 100644 include/dt-bindings/clock/sophgo,cv1800.h -- 2.41.0
Re: [PATCH] usb: dwc2: update reset method for host and device mode
Marek Vasut 于2024年4月22日周一 04:45写道：
>
> On 3/28/24 2:14 PM, Kongyang Liu wrote:
>
> [...]
>
> > @@ -464,12 +464,26 @@ static void reconfig_usbd(struct dwc2_udc *dev)
> > {
> > /* 2. Soft-reset OTG Core and then unreset again. */
> > int i;
> > - unsigned int uTemp = writel(CORE_SOFT_RESET, >grstctl);
> > + unsigned int uTemp;
> > uint32_t dflt_gusbcfg;
> > uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
> > u32 max_hw_ep;
> > int pdata_hw_ep;
> >
>
> Drop this newline
>
I will fix it
> > + u32 snpsid, greset;
> > +
> > + snpsid = readl(>gsnpsid);
> > + writel(CORE_SOFT_RESET, >grstctl);
> > + if ((snpsid & SNPSID_VER_MASK) < (SNPSID_VER_420a & SNPSID_VER_MASK))
> > {
>
> Can you use FIELD_GET()/FIELD_PREP() for this ?
>
I will fix it
> > + wait_for_bit_le32(>grstctl, CORE_SOFT_RESET, false,
> > 1000, false);
> > + } else {
> > + wait_for_bit_le32(>grstctl, CORE_SOFT_RESET_DONE, true,
> > 1000, false);
> > + greset = readl(>grstctl);
> > + greset &= ~CORE_SOFT_RESET;
> > + greset |= CORE_SOFT_RESET_DONE;
> > + writel(greset, >grstctl);
>
> clrsetbits_le32()
>
I will fix it
> [...]
>
> > diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
> > index 637eb2dd06..1baeff96ee 100644
> > --- a/drivers/usb/host/dwc2.c
> > +++ b/drivers/usb/host/dwc2.c
> > @@ -159,6 +159,7 @@ static void dwc_otg_core_reset(struct udevice *dev,
> > struct dwc2_core_regs *regs)
> > {
> > int ret;
> > + u32 snpsid, greset;
> >
> > /* Wait for AHB master IDLE state. */
> > ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_AHBIDLE,
> > @@ -167,9 +168,20 @@ static void dwc_otg_core_reset(struct udevice *dev,
> > dev_info(dev, "%s: Timeout!\n", __func__);
> >
> > /* Core Soft Reset */
> > + snpsid = readl(>gsnpsid);
> > writel(DWC2_GRSTCTL_CSFTRST, >grstctl);
> > - ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_CSFTRST,
> > - false, 1000, false);
> > + if ((snpsid & DWC2_SNPSID_VER_MASK) < (DWC2_SNPSID_DEVID_VER_420a &
> > DWC2_SNPSID_VER_MASK)) {
> > + ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_CSFTRST,
> > + false, 1000, false);
> > + } else {
> > + ret = wait_for_bit_le32(>grstctl,
> > DWC2_GRSTCTL_GSFTRST_DONE,
> > + true, 1000, false);
> > + greset = readl(>grstctl);
> > + greset &= ~DWC2_GRSTCTL_CSFTRST;
> > + greset |= DWC2_GRSTCTL_GSFTRST_DONE;
> > + writel(greset, >grstctl);
>
> Same comments as above.
>
> Maybe this should be pulled into dedicated function to avoid duplication?
>
For U-Boot, the dwc2 USB driver is split into two modules: host and gadget.
Each has its own register definitions and definitions for register bits,
which makes it difficult to extract a single function. Moreover, deciding
where to place this function is also an issue.
> > + }
> > +
> > if (ret)
> > dev_info(dev, "%s: Timeout!\n", __func__);
> >
> > @@ -1180,7 +1192,8 @@ static int dwc2_init_common(struct udevice *dev,
> > struct dwc2_priv *priv)
> >snpsid >> 12 & 0xf, snpsid & 0xfff);
> >
> > if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
> > - (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
> > + (snpsid & DWC2_SNPSID_DEVID_MASK) !=
> > DWC2_SNPSID_DEVID_VER_3xx &&
> > + (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_4xx) {
>
> Try FIELD_GET/FIELD_PREP
I will fix it
Best regards
Kongyang Liu
[PATCH 3/3] configs: milkv_duo: Add spi nor configs
Add configs related to spi nor flash for Sophgo Milk-V Duo board Signed-off-by: Kongyang Liu --- configs/milkv_duo_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig index e8413d7aa9..c69eab5fad 100644 --- a/configs/milkv_duo_defconfig +++ b/configs/milkv_duo_defconfig @@ -28,5 +28,8 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_CV1800B=y +CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550_MEM32=y +CONFIG_SPI=y +CONFIG_CV1800B_SPIF=y -- 2.41.0
[PATCH 2/3] riscv: dts: sophgo: Add spi nor flash controller node
Add spi nor flash controller node for cv18xx SoCs
Signed-off-by: Kongyang Liu
---
arch/riscv/dts/cv1800b-milkv-duo.dts | 13 +
arch/riscv/dts/cv18xx.dtsi | 17 +
2 files changed, 30 insertions(+)
diff --git a/arch/riscv/dts/cv1800b-milkv-duo.dts
b/arch/riscv/dts/cv1800b-milkv-duo.dts
index 94e64ddce8..dd2c9cd17c 100644
--- a/arch/riscv/dts/cv1800b-milkv-duo.dts
+++ b/arch/riscv/dts/cv1800b-milkv-duo.dts
@@ -41,6 +41,19 @@
no-sdio;
};
+ {
+ status = "okay";
+
+ spiflash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <7500>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ m25p,fast-read;
+ };
+}
+
{
status = "okay";
};
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index ec99c4deeb..1623e354df 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -52,6 +52,13 @@
#clock-cells = <0>;
};
+ spif_clk: spi-flash-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <3>;
+ clock-output-names = "spif_clk";
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <>;
@@ -197,6 +204,16 @@
status = "disabled";
};
+ spif: spi-nor@1000 {
+ compatible = "sophgo,cv1800b-spif";
+ reg = <0x1000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <_clk>;
+ interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
plic: interrupt-controller@7000 {
reg = <0x7000 0x400>;
interrupts-extended = <_intc 11>, <_intc 9>;
--
2.41.0
[PATCH 1/3] spi: cv1800b: Add spi nor flash controller driver for cv1800b SoC
Add spi nor flash controller driver for cv1800b SoC
Signed-off-by: Kongyang Liu
---
drivers/spi/Kconfig| 8 +
drivers/spi/Makefile | 1 +
drivers/spi/cv1800b_spif.c | 321 +
3 files changed, 330 insertions(+)
create mode 100644 drivers/spi/cv1800b_spif.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 612434633b..35030ab355 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -168,6 +168,14 @@ config CF_SPI
Enable the ColdFire SPI driver. This driver can be used on
some m68k SoCs.
+config CV1800B_SPIF
+ bool "Sophgo cv1800b SPI Flash Controller driver"
+ depends on SPI_MEM
+ help
+ Enable the Sophgo cv1800b SPI Flash Controller driver. This driver
+ can be used to access the SPI NOR flash on platforms embedding this
+ Sophgo cv1800b IP core.
+
config DAVINCI_SPI
bool "Davinci & Keystone SPI driver"
depends on ARCH_DAVINCI || ARCH_KEYSTONE
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 14bdb97f18..32d7bf7237 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o
obj-$(CONFIG_CF_SPI) += cf_spi.o
obj-$(CONFIG_CORTINA_SFLASH) += ca_sflash.o
+obj-$(CONFIG_CV1800B_SPIF) += cv1800b_spif.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
diff --git a/drivers/spi/cv1800b_spif.c b/drivers/spi/cv1800b_spif.c
new file mode 100644
index 00..9c077f3ff9
--- /dev/null
+++ b/drivers/spi/cv1800b_spif.c
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define CV1800B_SPI_CTRL_SCK_DIV_MASKGENMASK(10, 0)
+#define CV1800B_SPI_CTRL_CPHABIT(12)
+#define CV1800B_SPI_CTRL_CPOLBIT(13)
+
+#define CV1800B_SPI_CE_MANUALBIT(0)
+#define CV1800B_SPI_CE_MANUAL_EN BIT(1)
+#define CV1800B_SPI_CE_ENABLE(CV1800B_SPI_CE_MANUAL | \
+ CV1800B_SPI_CE_MANUAL_EN)
+#define CV1800B_SPI_CE_DISABLE CV1800B_SPI_CE_MANUAL_EN
+#define CV1800B_SPI_CE_HARDWARE 0
+
+#define CV1800B_SPI_DLY_CTRL_NEG_SAMPLE BIT(14)
+
+#define CV1800B_SPI_TRAN_MODE_RX BIT(0)
+#define CV1800B_SPI_TRAN_MODE_TX BIT(1)
+#define CV1800B_SPI_TRAN_FAST_MODE BIT(3)
+#define CV1800B_SPI_TRAN_BUS_WIDTH_1_BIT 0x0
+#define CV1800B_SPI_TRAN_BUS_WIDTH_2_BIT BIT(4)
+#define CV1800B_SPI_TRAN_BUS_WIDTH_4_BIT BIT(5)
+#define CV1800B_SPI_TRAN_ADDR_3_BYTES(3 << 8)
+#define CV1800B_SPI_TRAN_ADDR_4_BYTES(4 << 8)
+#define CV1800B_SPI_TRAN_WITH_CMDBIT(11)
+#define CV1800B_SPI_TRAN_GO_BUSY BIT(15)
+#define CV1800B_SPI_TRAN_DUMMY_CYC_MASK GENMASK(19, 16)
+#define CV1800B_SPI_TRAN_DUMMY_CYC_OFFSET16
+#define CV1800B_SPI_TRAN_BYTE4_ENBIT(20)
+#define CV1800B_SPI_TRAN_BYTE4_CMD BIT(21)
+
+#define CV1800B_SPI_FF_PT_AVAILABLE_MASK GENMASK(3, 0)
+
+#define CV1800B_SPI_INT_TRAN_DONEBIT(0)
+#define CV1800B_SPI_INT_RD_FIFO BIT(2)
+#define CV1800B_SPI_INT_WR_FIFO BIT(3)
+
+#define CV1800B_FIFO_CAPACITY 8
+#define CV1800B_DEFAULT_DIV 4
+
+struct cv1800b_spif_regs {
+ u32 spi_ctrl;
+ u32 ce_ctrl;
+ u32 dly_ctrl;
+ u32 dmmr_ctrl;
+ u32 tran_csr;
+ u32 tran_num;
+ u32 ff_port;
+ u32 reserved0;
+ u32 ff_pt;
+ u32 reserved1;
+ u32 int_sts;
+ u32 int_en;
+};
+
+struct cv1800b_spi_priv {
+ struct cv1800b_spif_regs *regs;
+ uint clk_freq;
+ uint mode;
+ int div;
+};
+
+static int cv1800b_spi_probe(struct udevice *bus)
+{
+ struct cv1800b_spi_priv *priv = dev_get_priv(bus);
+ struct clk clkdev;
+ int ret;
+
+ priv->regs = (struct cv1800b_spif_regs *)dev_read_addr_ptr(bus);
+ if (priv->regs == 0)
+ return -EINVAL;
+
+ ret = clk_get_by_index(bus, 0, );
+ if (ret)
+ return ret;
+ priv->clk_freq = clk_get_rate();
+
+ /* DMMR mode is enabled by default, disable it */
+ writel(0, >regs->dmmr_ctrl);
+
+ return 0;
+}
+
+static void cv1800b_spi_config_dmmr(struct cv1800b_spi_priv *priv, struct
spi_nor *flash)
+{
+ struct cv1800b_spif_regs *regs = priv->regs;
+ u32 read_cm
[PATCH 0/3] spi: sophgo: milkv_duo: Add spi nor flash support for Milk-V Duo board
This series add spi nor flash controller driver for cv1800b SoC and enable it for Sophgo Milk-V Duo board. Kongyang Liu (3): spi: cv1800b: Add spi nor flash controller driver for cv1800b SoC riscv: dts: sophgo: Add spi nor flash controller node configs: milkv_duo: Add spi nor configs arch/riscv/dts/cv1800b-milkv-duo.dts | 13 ++ arch/riscv/dts/cv18xx.dtsi | 17 ++ configs/milkv_duo_defconfig | 3 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/cv1800b_spif.c | 321 +++ 6 files changed, 363 insertions(+) create mode 100644 drivers/spi/cv1800b_spif.c -- 2.41.0
[PATCH v2 3/3] configs: milkv_duo: Add ethernet configs
Add configs related to ethernet and ethernet boot command for Sophgo Milk-V Duo board Signed-off-by: Kongyang Liu Reviewed-by: Leo Yu-Chi Liang --- (no changes since v1) configs/milkv_duo_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig index e8413d7aa9..f66c4c5358 100644 --- a/configs/milkv_duo_defconfig +++ b/configs/milkv_duo_defconfig @@ -19,14 +19,18 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="milkv_duo# " CONFIG_CMD_MMC=y CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PXE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_CV1800B=y +CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550_MEM32=y -- 2.41.0
[PATCH v2 2/3] riscv: dts: sophgo: Add ethernet node
Add ethernet node for cv1800b SoC
Signed-off-by: Kongyang Liu
---
Changes in v2:
- Change compatible
- Add clocks and interrupt properties.
arch/riscv/dts/cv1800b-milkv-duo.dts | 7 ++-
arch/riscv/dts/cv18xx.dtsi | 23 +++
2 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/dts/cv1800b-milkv-duo.dts
b/arch/riscv/dts/cv1800b-milkv-duo.dts
index 94e64ddce8..c1e6611e33 100644
--- a/arch/riscv/dts/cv1800b-milkv-duo.dts
+++ b/arch/riscv/dts/cv1800b-milkv-duo.dts
@@ -29,6 +29,11 @@
};
};
+ {
+ status = "okay";
+ phy-mode = "rmii";
+};
+
{
clock-frequency = <2500>;
};
@@ -39,7 +44,7 @@
no-1-8-v;
no-mmc;
no-sdio;
-};
+}
{
status = "okay";
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index ec99c4deeb..c95bac77be 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -50,6 +50,20 @@
clock-frequency = <37500>;
clock-output-names = "sdhci_clk";
#clock-cells = <0>;
+ }
+
+ eth_csrclk: eth-csrclk {
+ compatible = "fixed-clock";
+ clock-frequency = <25000>;
+ clock-output-names = "eth_csrclk";
+ #clock-cells = <0x0>;
+ };
+
+ eth_ptpclk: eth-ptpclk {
+ compatible = "fixed-clock";
+ clock-frequency = <5000>;
+ clock-output-names = "eth_ptpclk";
+ #clock-cells = <0x0>;
};
soc {
@@ -138,6 +152,15 @@
};
};
+ ethernet0: ethernet@407 {
+ compatible = "sophgo,cv1800b-dwmac";
+ reg = <0x0407 0x1>;
+ interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <_csrclk>, <_ptpclk>;
+ clock-names = "stmmaceth", "ptp_ref";
+ status = "disabled";
+ };
+
uart0: serial@414 {
compatible = "snps,dw-apb-uart";
reg = <0x0414 0x100>;
--
2.41.0
[PATCH v2 1/3] board: milkv_duo: Add init code for Milk-V Duo ethernet
Initialize register in cv1800b ethernet phy to make it compatible with
generic phy driver
Signed-off-by: Kongyang Liu
Reviewed-by: Leo Yu-Chi Liang
---
(no changes since v1)
board/sophgo/milkv_duo/Makefile | 3 +-
board/sophgo/milkv_duo/board.c| 4 ++
board/sophgo/milkv_duo/ethernet.c | 79 +++
board/sophgo/milkv_duo/ethernet.h | 11 +
drivers/net/designware.c | 1 +
5 files changed, 97 insertions(+), 1 deletion(-)
create mode 100644 board/sophgo/milkv_duo/ethernet.c
create mode 100644 board/sophgo/milkv_duo/ethernet.h
diff --git a/board/sophgo/milkv_duo/Makefile b/board/sophgo/milkv_duo/Makefile
index a087013f5c..d0525eba85 100644
--- a/board/sophgo/milkv_duo/Makefile
+++ b/board/sophgo/milkv_duo/Makefile
@@ -2,4 +2,5 @@
#
# Copyright (c) 2024, Kongyang Liu
-obj-y := board.o
+obj-y += board.o
+obj-$(CONFIG_NET) += ethernet.o
diff --git a/board/sophgo/milkv_duo/board.c b/board/sophgo/milkv_duo/board.c
index eaa47be173..311576fe1c 100644
--- a/board/sophgo/milkv_duo/board.c
+++ b/board/sophgo/milkv_duo/board.c
@@ -3,7 +3,11 @@
* Copyright (c) 2024, Kongyang Liu
*/
+#include "ethernet.h"
+
int board_init(void)
{
+ if (IS_ENABLED(CONFIG_NET))
+ cv1800b_ephy_init();
return 0;
}
diff --git a/board/sophgo/milkv_duo/ethernet.c
b/board/sophgo/milkv_duo/ethernet.c
new file mode 100644
index 00..e997ce1037
--- /dev/null
+++ b/board/sophgo/milkv_duo/ethernet.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ */
+
+#include
+#include
+#include
+
+#define REG_EPHY_TOP_WRAP (u32 *)0x03009800
+#define REG_EPHY_BASE (u32 *)0x03009000
+
+#define REG_EPHY_CTL REG_EPHY_TOP_WRAP
+#define REG_EPHY_APB_RW_SEL REG_EPHY_TOP_WRAP + 1
+
+/* Page 0 register */
+#define REG_PHY_ID1 REG_EPHY_BASE + MII_PHYSID1
+#define REG_PHY_ID2 REG_EPHY_BASE + MII_PHYSID2
+#define REG_PHY_PAGE_SEL REG_EPHY_BASE + 0x1f
+
+/* Page 5 register */
+#define REG_PD_EN_CTLREG_EPHY_BASE + 0x10
+
+/* REG_EPHY_CTL */
+#define REG_EPHY_SHUTDOWNBIT(0)
+#define REG_EPHY_ANA_RST_N BIT(1)
+#define REG_EPHY_DIG_RST_N BIT(2)
+#define REG_EPHY_MAIN_RST_N BIT(3)
+
+/* REG_PD_EN_CTL */
+#define REG_EN_ETH_TXRT BIT(0)
+#define REG_EN_ETH_CLK100M BIT(1)
+#define REG_EN_ETH_CLK125M BIT(2)
+#define REG_EN_ETH_PLL_LCKDETBIT(3)
+#define REG_EN_ETH_RXADC BIT(4)
+#define REG_EN_ETH_RXPGA BIT(5)
+#define REG_EN_ETH_RXRT BIT(6)
+#define REG_EN_ETH_TXCROSSOVER BIT(7)
+#define REG_PD_ETH_PLL BIT(8)
+#define REG_PD_ETH_TXDAC BIT(9)
+#define REG_PD_ETH_TXDACBST BIT(10)
+#define REG_PD_ETH_TXECHOBIT(11)
+#define REG_PD_ETH_TXDRV_NMOSBIT(12)
+#define REG_PD_ETH_TXLDO BIT(13)
+
+void cv1800b_ephy_init(void)
+{
+ u32 reg;
+ u32 phy_id = 1;
+
+ /* enable direct memory access for phy register */
+ writel(1, REG_EPHY_APB_RW_SEL);
+
+ reg = readl(REG_EPHY_CTL);
+ reg &= ~REG_EPHY_SHUTDOWN;
+ reg |= REG_EPHY_ANA_RST_N | REG_EPHY_DIG_RST_N | REG_EPHY_MAIN_RST_N;
+ writel(reg, REG_EPHY_CTL);
+
+ /* switch to page 5 */
+ writel(5 << 8, REG_PHY_PAGE_SEL);
+ reg = readl(REG_PD_EN_CTL);
+ reg &= ~(REG_PD_ETH_TXLDO | REG_PD_ETH_TXDRV_NMOS | REG_PD_ETH_TXDAC |
REG_PD_ETH_PLL);
+ reg |= REG_EN_ETH_TXRT | REG_EN_ETH_CLK100M | REG_EN_ETH_CLK125M
+ | REG_EN_ETH_PLL_LCKDET | REG_EN_ETH_RXADC | REG_EN_ETH_RXPGA |
REG_EN_ETH_RXRT;
+ writel(reg, REG_PD_EN_CTL);
+
+ /* switch to page 0 */
+ writel(0 << 8, REG_PHY_PAGE_SEL);
+ /*
+* As the phy_id in the cv1800b PHY register is initialized to 0, it
+* is necessary to manually initialize the phy_id to an arbitrary
+* value so that it could corresponds to the generic PHY driver.
+*/
+ writel(phy_id >> 16, REG_PHY_ID1);
+ writel(phy_id & 0x, REG_PHY_ID2);
+
+ /* switch to MDIO control */
+ writel(0, REG_EPHY_APB_RW_SEL);
+}
diff --git a/board/sophgo/milkv_duo/ethernet.h
b/board/sophgo/milkv_duo/ethernet.h
new file mode 100644
index 00..7b21f1b0f6
--- /dev/null
+++ b/board/sophgo/milkv_duo/ethernet.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ */
+
+#ifndef __CV1800B_ETHERNET_H
+#define __CV1800B_ETHERNET_H
+
+void cv1800b_ephy_init(void);
+
+#endif
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 4c1642b29a..682045cea2 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -871,6 +871,7 @@ static const struct udevice_id designware_eth_ids[] = {
{ .compatible = "amlogic,meson6-dwmac" },
{ .compatible = "st,stm32-dwmac" },
{ .compatible = "snps,arc-dwmac-3.70a" },
+ { .compatible = "sophgo,cv1800b-dwmac" },
{ }
};
--
2.41.0
[PATCH v2 0/3] board: sophgo: milkv_duo: Add ethernet support for Milk-V Duo board
This series add init code for cv1800b ethernet phy and enable ethernet support for Sophgo Milk-V Duo board. In cv1800b, as the PHY register phy_id being initialized to 0, it is necessary to initialize the PHY before the ethernet driver initialization. Therefore, the initialization code is placed in the board_init function. For the Linux kernel, due to the presence of a hibernation mechanism, whether the phy id will be reset to 0 after hibernation and how to reassign it thereafter remains an issue to consider. Once this issue is resolved, the Ethernet driver for the Milk-V Duo will be sent to the kernel. Changes in v2: - Change compatible - Add clocks and interrupt properties. Kongyang Liu (3): board: milkv_duo: Add init code for Milk-V Duo ethernet riscv: dts: sophgo: Add ethernet node configs: milkv_duo: Add ethernet configs arch/riscv/dts/cv1800b-milkv-duo.dts | 7 ++- arch/riscv/dts/cv18xx.dtsi | 23 board/sophgo/milkv_duo/Makefile | 3 +- board/sophgo/milkv_duo/board.c | 4 ++ board/sophgo/milkv_duo/ethernet.c| 79 board/sophgo/milkv_duo/ethernet.h| 11 configs/milkv_duo_defconfig | 4 ++ drivers/net/designware.c | 1 + 8 files changed, 130 insertions(+), 2 deletions(-) create mode 100644 board/sophgo/milkv_duo/ethernet.c create mode 100644 board/sophgo/milkv_duo/ethernet.h -- 2.41.0
[PATCH 3/3] configs: milkv_duo: Add sysreset configs
Add sysreset configs as well as poweroff and reset commands for Sophgo Milk-V Duo board. Signed-off-by: Kongyang Liu --- configs/milkv_duo_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig index e8413d7aa9..28bd4b53d3 100644 --- a/configs/milkv_duo_defconfig +++ b/configs/milkv_duo_defconfig @@ -19,6 +19,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="milkv_duo# " CONFIG_CMD_MMC=y CONFIG_CMD_PART=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y @@ -30,3 +31,5 @@ CONFIG_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_CV1800B=y CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_CV1800B=y -- 2.41.0
[PATCH 2/3] board: sophgo: milkv_duo: Bind sysreset driver
Bind cv1800b sysreset driver for Sophgo Milk-V Duo board in board_init
function.
Signed-off-by: Kongyang Liu
---
board/sophgo/milkv_duo/board.c | 4
1 file changed, 4 insertions(+)
diff --git a/board/sophgo/milkv_duo/board.c b/board/sophgo/milkv_duo/board.c
index eaa47be173..e7e28fe248 100644
--- a/board/sophgo/milkv_duo/board.c
+++ b/board/sophgo/milkv_duo/board.c
@@ -3,7 +3,11 @@
* Copyright (c) 2024, Kongyang Liu
*/
+ #include
+
int board_init(void)
{
+ if (IS_ENABLED(CONFIG_SYSRESET_CV1800B))
+ device_bind_driver(gd->dm_root, "cv1800b_sysreset", "sysreset",
NULL);
return 0;
}
--
2.41.0
[PATCH 1/3] sysreset: cv1800b: Add sysreset driver for cv1800b SoC
Add sysreset driver for cv1800b SoC
Signed-off-by: Kongyang Liu
---
drivers/sysreset/Kconfig| 5 +++
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_cv1800b.c | 64 +
3 files changed, 70 insertions(+)
create mode 100644 drivers/sysreset/sysreset_cv1800b.c
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 49c0787b26..b64bfadb20 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -59,6 +59,11 @@ config SYSRESET_CMD_POWEROFF
endif
+config SYSRESET_CV1800B
+ bool "Enable support for Sophgo cv1800b System Reset"
+ help
+ Enable system reset support for Sophgo cv1800b SoC.
+
config POWEROFF_GPIO
bool "Enable support for GPIO poweroff driver"
depends on DM_GPIO
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index e0e732205d..d59299aa31 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o
obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o
obj-$(CONFIG_ARCH_STI) += sysreset_sti.o
obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
+obj-$(CONFIG_SYSRESET_CV1800B) += sysreset_cv1800b.o
obj-$(CONFIG_POWEROFF_GPIO) += poweroff_gpio.o
obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_MAX77663) += sysreset_max77663.o
diff --git a/drivers/sysreset/sysreset_cv1800b.c
b/drivers/sysreset/sysreset_cv1800b.c
new file mode 100644
index 00..9cd62772ef
--- /dev/null
+++ b/drivers/sysreset/sysreset_cv1800b.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define REG_RTC_BASE (void *)0x05026000
+#define REG_RTC_CTRL_BASE(void *)0x05025000
+#define REG_RTC_EN_SHDN_REQ (REG_RTC_BASE + 0xc0)
+#define REG_RTC_EN_PWR_CYC_REQ (REG_RTC_BASE + 0xc8)
+#define REG_RTC_EN_WARM_RST_REQ (REG_RTC_BASE + 0xcc)
+#define REG_RTC_CTRL_UNLOCKKEY (REG_RTC_CTRL_BASE + 0x4)
+#define REG_RTC_CTRL (REG_RTC_CTRL_BASE + 0x8)
+
+#define CTRL_UNLOCKKEY_MAGIC 0xAB18
+
+/* REG_RTC_CTRL */
+#define BIT_REQ_SHDN BIT(0)
+#define BIT_REQ_PWR_CYCBIT(3)
+#define BIT_REQ_WARM_RST BIT(4)
+
+static struct {
+ void *pre_req_reg;
+ u32 req_bit;
+} reset_info[SYSRESET_COUNT] = {
+ [SYSRESET_WARM] = { REG_RTC_EN_WARM_RST_REQ, BIT_REQ_WARM_RST },
+ [SYSRESET_COLD] = { REG_RTC_EN_WARM_RST_REQ, BIT_REQ_WARM_RST },
+ [SYSRESET_POWER] = { REG_RTC_EN_PWR_CYC_REQ, BIT_REQ_PWR_CYC },
+ [SYSRESET_POWER_OFF] = { REG_RTC_EN_SHDN_REQ, BIT_REQ_SHDN },
+};
+
+static int cv1800b_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ u32 reg;
+
+ writel(1, reset_info[type].pre_req_reg);
+ writel(CTRL_UNLOCKKEY_MAGIC, REG_RTC_CTRL_UNLOCKKEY);
+ reg = readl(REG_RTC_CTRL);
+ writel(0x0800 | reset_info[type].req_bit, REG_RTC_CTRL);
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops cv1800b_sysreset = {
+ .request = cv1800b_sysreset_request,
+};
+
+static const struct udevice_id cv1800b_sysreset_ids[] = {
+ { .compatible = "sophgo,cv1800b-sysreset", },
+ {},
+};
+
+U_BOOT_DRIVER(sysreset_cv1800b) = {
+ .name = "cv1800b_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = _sysreset,
+ .of_match = cv1800b_sysreset_ids
+};
--
2.41.0
[PATCH 0/3] sysreset: sophgo: milkv_duo: Add sysreset support for Milk-V Duo board
This series add sysreset driver for cv1800b SoC and enable poweroff and reset commands for Sophgo Milk-V Duo board. Kongyang Liu (3): sysreset: cv1800b: Add sysreset driver for cv1800b SoC board: sophgo: milkv_duo: Bind sysreset driver configs: milkv_duo: Add sysreset configs board/sophgo/milkv_duo/board.c | 4 ++ configs/milkv_duo_defconfig | 3 ++ drivers/sysreset/Kconfig| 5 +++ drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_cv1800b.c | 64 + 5 files changed, 77 insertions(+) create mode 100644 drivers/sysreset/sysreset_cv1800b.c -- 2.41.0
[PATCH] mmc: cv1800b: Add transmit tap delay config to fix write error
Currently, only the receive delay is configured while the transmit delay
is not set, which may result in errors when writing to the file. This issue
can be resolved by setting PHY_TX_SRC_INVERT to SDHCI_PHY_TX_RX_DLY.
Signed-off-by: Kongyang Liu
---
drivers/mmc/cv1800b_sdhci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/cv1800b_sdhci.c b/drivers/mmc/cv1800b_sdhci.c
index 2275c53777..a50f4cff0d 100644
--- a/drivers/mmc/cv1800b_sdhci.c
+++ b/drivers/mmc/cv1800b_sdhci.c
@@ -12,6 +12,8 @@
#define MMC_MAX_CLOCK37500
#define TUNE_MAX_PHCODE 128
+#define PHY_TX_SRC_INVERT BIT(8)
+
struct cv1800b_sdhci_plat {
struct mmc_config cfg;
struct mmc mmc;
@@ -19,7 +21,7 @@ struct cv1800b_sdhci_plat {
static void cv1800b_set_tap_delay(struct sdhci_host *host, u16 tap)
{
- sdhci_writel(host, tap << 16, SDHCI_PHY_TX_RX_DLY);
+ sdhci_writel(host, PHY_TX_SRC_INVERT | tap << 16, SDHCI_PHY_TX_RX_DLY);
}
static void cv1800b_sdhci_reset(struct sdhci_host *host, u8 mask)
--
2.41.0
[PATCH] usb: dwc2: update reset method for host and device mode
Starting from version 4.20a, there has been a change in the reset method.
A new bit, GRSTCTL_CSFTRST_DONE, has been introduced in the GRSTCTL
register to indicate whether the reset has been completed.
Signed-off-by: Kongyang Liu
---
drivers/usb/gadget/dwc2_udc_otg.c | 18 --
drivers/usb/gadget/dwc2_udc_otg_regs.h | 19 +--
drivers/usb/host/dwc2.c| 19 ---
drivers/usb/host/dwc2.h| 6 ++
4 files changed, 51 insertions(+), 11 deletions(-)
diff --git a/drivers/usb/gadget/dwc2_udc_otg.c
b/drivers/usb/gadget/dwc2_udc_otg.c
index 27082f5152..d1dd469a0f 100644
--- a/drivers/usb/gadget/dwc2_udc_otg.c
+++ b/drivers/usb/gadget/dwc2_udc_otg.c
@@ -42,7 +42,7 @@
#include
#include
-#include
+#include
#include
@@ -464,12 +464,26 @@ static void reconfig_usbd(struct dwc2_udc *dev)
{
/* 2. Soft-reset OTG Core and then unreset again. */
int i;
- unsigned int uTemp = writel(CORE_SOFT_RESET, >grstctl);
+ unsigned int uTemp;
uint32_t dflt_gusbcfg;
uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
u32 max_hw_ep;
int pdata_hw_ep;
+ u32 snpsid, greset;
+
+ snpsid = readl(>gsnpsid);
+ writel(CORE_SOFT_RESET, >grstctl);
+ if ((snpsid & SNPSID_VER_MASK) < (SNPSID_VER_420a & SNPSID_VER_MASK)) {
+ wait_for_bit_le32(>grstctl, CORE_SOFT_RESET, false, 1000,
false);
+ } else {
+ wait_for_bit_le32(>grstctl, CORE_SOFT_RESET_DONE, true,
1000, false);
+ greset = readl(>grstctl);
+ greset &= ~CORE_SOFT_RESET;
+ greset |= CORE_SOFT_RESET_DONE;
+ writel(greset, >grstctl);
+ }
+
debug("Resetting OTG controller\n");
dflt_gusbcfg =
diff --git a/drivers/usb/gadget/dwc2_udc_otg_regs.h
b/drivers/usb/gadget/dwc2_udc_otg_regs.h
index 9ca6f42375..b3d9117033 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_regs.h
+++ b/drivers/usb/gadget/dwc2_udc_otg_regs.h
@@ -63,24 +63,26 @@ struct dwc2_usbotg_reg {
u32 gnptxfsiz; /* Non-Periodic Transmit FIFO Size */
u8 res0[12];
u32 ggpio; /* 0x038 */
- u8 res1[20];
+ u8 res1[4];
+ u32 gsnpsid;
+ u8 res2[12];
u32 ghwcfg4; /* User HW Config4 */
- u8 res2[176];
+ u8 res3[176];
u32 dieptxf[15]; /* Device Periodic Transmit FIFO size register */
- u8 res3[1728];
+ u8 res4[1728];
/* Device Configuration */
u32 dcfg; /* Device Configuration Register */
u32 dctl; /* Device Control */
u32 dsts; /* Device Status */
- u8 res4[4];
+ u8 res5[4];
u32 diepmsk; /* Device IN Endpoint Common Interrupt Mask */
u32 doepmsk; /* Device OUT Endpoint Common Interrupt Mask */
u32 daint; /* Device All Endpoints Interrupt */
u32 daintmsk; /* Device All Endpoints Interrupt Mask */
- u8 res5[224];
+ u8 res6[224];
struct dwc2_dev_in_endp in_endp[16];
struct dwc2_dev_out_endp out_endp[16];
- u8 res6[768];
+ u8 res7[768];
struct ep_fifo ep[16];
};
@@ -118,6 +120,7 @@ struct dwc2_usbotg_reg {
/* DWC2_UDC_OTG_GRSTCTL */
#define AHB_MASTER_IDLE(1u<<31)
#define CORE_SOFT_RESET(0x1<<0)
+#define CORE_SOFT_RESET_DONE (0x1<<29)
/* DWC2_UDC_OTG_GINTSTS/DWC2_UDC_OTG_GINTMSK core interrupt register */
#define INT_RESUME (1u<<31)
@@ -285,6 +288,10 @@ struct dwc2_usbotg_reg {
#define DAINT_IN_EP_INT(x)(x << 0)
#define DAINT_OUT_EP_INT(x) (x << 16)
+/* DWC2_UDC_OTG_GSNPSID */
+#define SNPSID_VER_420a0x4f54420a
+#define SNPSID_VER_MASK0x
+
/* User HW Config4 */
#define GHWCFG4_NUM_IN_EPS_MASK(0xf << 26)
#define GHWCFG4_NUM_IN_EPS_SHIFT 26
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 637eb2dd06..1baeff96ee 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -159,6 +159,7 @@ static void dwc_otg_core_reset(struct udevice *dev,
struct dwc2_core_regs *regs)
{
int ret;
+ u32 snpsid, greset;
/* Wait for AHB master IDLE state. */
ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_AHBIDLE,
@@ -167,9 +168,20 @@ static void dwc_otg_core_reset(struct udevice *dev,
dev_info(dev, "%s: Timeout!\n", __func__);
/* Core Soft Reset */
+ snpsid = readl(>gsnpsid);
writel(DWC2_GRSTCTL_CSFTRST, >grstctl);
- ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_CSFTRST,
- false, 1000, false);
+ if ((snpsid & DWC2_SNPSID_VER_MASK) < (DWC2_SNP
Re: [PATCH 2/3] riscv: dts: sophgo: Add ethernet node
Conor Dooley 于2024年3月12日周二 21:20写道： > > On Tue, Mar 12, 2024 at 05:59:44PM +0800, Leo Liang wrote: > > On Sun, Mar 10, 2024 at 01:56:45PM +0800, Kongyang Liu wrote: > > > Add ethernet node for cv1800b SoC > > > > > > Signed-off-by: Kongyang Liu > > > --- > > > > > > arch/riscv/dts/cv18xx.dtsi | 6 ++ > > > 1 file changed, 6 insertions(+) > > > > Hi KongYang, > > > > Will there be a patch adding this ethernet node for kernel as well ? > > It's highly like that the compatible of "cv1800b-ethernet" will be > requested to be changed to "cv1800b-dwmac" to match the designware IP > used in other SoCs. > I will change it in next version > The added node also looks suspiciously missing any clocks or interrupts. If we only consider u-boot, since u-boot does not utilize interrupts and clocks, this code can function properly. However, if compatibility with the kernel is a concern, I will discuss this issue with who is working on Milk-V Duo Ethernet support for the kernel. Best regards Kongyang Liu
Re: [PATCH 2/3] riscv: dts: sophgo: Add ethernet node
Leo Liang 于2024年3月12日周二 17:59写道： > > On Sun, Mar 10, 2024 at 01:56:45PM +0800, Kongyang Liu wrote: > > Add ethernet node for cv1800b SoC > > > > Signed-off-by: Kongyang Liu > > --- > > > > arch/riscv/dts/cv18xx.dtsi | 6 ++ > > 1 file changed, 6 insertions(+) > > Hi KongYang, > > Will there be a patch adding this ethernet node for kernel as well ? > Currently, I'm only focusing on the u-boot for the Milk-V Duo board, while the kernel part is being handled by others. Therefore, this patch will not be added to the kernel. Best regards Kongyang Liu > Best regards, > Leo
[PATCH 3/3] configs: milkv_duo: Add ethernet configs
Add configs related to ethernet and ethernet boot command for Sophgo Milk-V Duo board Signed-off-by: Kongyang Liu --- configs/milkv_duo_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig index e8413d7aa9..f66c4c5358 100644 --- a/configs/milkv_duo_defconfig +++ b/configs/milkv_duo_defconfig @@ -19,14 +19,18 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="milkv_duo# " CONFIG_CMD_MMC=y CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PXE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_CV1800B=y +CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550_MEM32=y -- 2.41.0
[PATCH 2/3] riscv: dts: sophgo: Add ethernet node
Add ethernet node for cv1800b SoC
Signed-off-by: Kongyang Liu
---
arch/riscv/dts/cv18xx.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index ec99c4deeb..013372a40c 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -197,6 +197,12 @@
status = "disabled";
};
+ ethernet0: ethernet@407 {
+ compatible = "sophgo,cv1800b-ethernet";
+ reg = <0x0407 0x1>;
+ phy-mode = "rmii";
+ };
+
plic: interrupt-controller@7000 {
reg = <0x7000 0x400>;
interrupts-extended = <_intc 11>, <_intc 9>;
--
2.41.0
[PATCH 1/3] board: milkv_duo: Add init code for Milk-V Duo ethernet
Initialize register in cv1800b ethernet phy to make it compatible with
generic phy driver
Signed-off-by: Kongyang Liu
---
board/sophgo/milkv_duo/Makefile | 3 +-
board/sophgo/milkv_duo/board.c| 4 ++
board/sophgo/milkv_duo/ethernet.c | 79 +++
board/sophgo/milkv_duo/ethernet.h | 11 +
drivers/net/designware.c | 1 +
5 files changed, 97 insertions(+), 1 deletion(-)
create mode 100644 board/sophgo/milkv_duo/ethernet.c
create mode 100644 board/sophgo/milkv_duo/ethernet.h
diff --git a/board/sophgo/milkv_duo/Makefile b/board/sophgo/milkv_duo/Makefile
index a087013f5c..d0525eba85 100644
--- a/board/sophgo/milkv_duo/Makefile
+++ b/board/sophgo/milkv_duo/Makefile
@@ -2,4 +2,5 @@
#
# Copyright (c) 2024, Kongyang Liu
-obj-y := board.o
+obj-y += board.o
+obj-$(CONFIG_NET) += ethernet.o
diff --git a/board/sophgo/milkv_duo/board.c b/board/sophgo/milkv_duo/board.c
index eaa47be173..311576fe1c 100644
--- a/board/sophgo/milkv_duo/board.c
+++ b/board/sophgo/milkv_duo/board.c
@@ -3,7 +3,11 @@
* Copyright (c) 2024, Kongyang Liu
*/
+#include "ethernet.h"
+
int board_init(void)
{
+ if (IS_ENABLED(CONFIG_NET))
+ cv1800b_ephy_init();
return 0;
}
diff --git a/board/sophgo/milkv_duo/ethernet.c
b/board/sophgo/milkv_duo/ethernet.c
new file mode 100644
index 00..e997ce1037
--- /dev/null
+++ b/board/sophgo/milkv_duo/ethernet.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ */
+
+#include
+#include
+#include
+
+#define REG_EPHY_TOP_WRAP (u32 *)0x03009800
+#define REG_EPHY_BASE (u32 *)0x03009000
+
+#define REG_EPHY_CTL REG_EPHY_TOP_WRAP
+#define REG_EPHY_APB_RW_SEL REG_EPHY_TOP_WRAP + 1
+
+/* Page 0 register */
+#define REG_PHY_ID1 REG_EPHY_BASE + MII_PHYSID1
+#define REG_PHY_ID2 REG_EPHY_BASE + MII_PHYSID2
+#define REG_PHY_PAGE_SEL REG_EPHY_BASE + 0x1f
+
+/* Page 5 register */
+#define REG_PD_EN_CTLREG_EPHY_BASE + 0x10
+
+/* REG_EPHY_CTL */
+#define REG_EPHY_SHUTDOWNBIT(0)
+#define REG_EPHY_ANA_RST_N BIT(1)
+#define REG_EPHY_DIG_RST_N BIT(2)
+#define REG_EPHY_MAIN_RST_N BIT(3)
+
+/* REG_PD_EN_CTL */
+#define REG_EN_ETH_TXRT BIT(0)
+#define REG_EN_ETH_CLK100M BIT(1)
+#define REG_EN_ETH_CLK125M BIT(2)
+#define REG_EN_ETH_PLL_LCKDETBIT(3)
+#define REG_EN_ETH_RXADC BIT(4)
+#define REG_EN_ETH_RXPGA BIT(5)
+#define REG_EN_ETH_RXRT BIT(6)
+#define REG_EN_ETH_TXCROSSOVER BIT(7)
+#define REG_PD_ETH_PLL BIT(8)
+#define REG_PD_ETH_TXDAC BIT(9)
+#define REG_PD_ETH_TXDACBST BIT(10)
+#define REG_PD_ETH_TXECHOBIT(11)
+#define REG_PD_ETH_TXDRV_NMOSBIT(12)
+#define REG_PD_ETH_TXLDO BIT(13)
+
+void cv1800b_ephy_init(void)
+{
+ u32 reg;
+ u32 phy_id = 1;
+
+ /* enable direct memory access for phy register */
+ writel(1, REG_EPHY_APB_RW_SEL);
+
+ reg = readl(REG_EPHY_CTL);
+ reg &= ~REG_EPHY_SHUTDOWN;
+ reg |= REG_EPHY_ANA_RST_N | REG_EPHY_DIG_RST_N | REG_EPHY_MAIN_RST_N;
+ writel(reg, REG_EPHY_CTL);
+
+ /* switch to page 5 */
+ writel(5 << 8, REG_PHY_PAGE_SEL);
+ reg = readl(REG_PD_EN_CTL);
+ reg &= ~(REG_PD_ETH_TXLDO | REG_PD_ETH_TXDRV_NMOS | REG_PD_ETH_TXDAC |
REG_PD_ETH_PLL);
+ reg |= REG_EN_ETH_TXRT | REG_EN_ETH_CLK100M | REG_EN_ETH_CLK125M
+ | REG_EN_ETH_PLL_LCKDET | REG_EN_ETH_RXADC | REG_EN_ETH_RXPGA |
REG_EN_ETH_RXRT;
+ writel(reg, REG_PD_EN_CTL);
+
+ /* switch to page 0 */
+ writel(0 << 8, REG_PHY_PAGE_SEL);
+ /*
+* As the phy_id in the cv1800b PHY register is initialized to 0, it
+* is necessary to manually initialize the phy_id to an arbitrary
+* value so that it could corresponds to the generic PHY driver.
+*/
+ writel(phy_id >> 16, REG_PHY_ID1);
+ writel(phy_id & 0x, REG_PHY_ID2);
+
+ /* switch to MDIO control */
+ writel(0, REG_EPHY_APB_RW_SEL);
+}
diff --git a/board/sophgo/milkv_duo/ethernet.h
b/board/sophgo/milkv_duo/ethernet.h
new file mode 100644
index 00..7b21f1b0f6
--- /dev/null
+++ b/board/sophgo/milkv_duo/ethernet.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ */
+
+#ifndef __CV1800B_ETHERNET_H
+#define __CV1800B_ETHERNET_H
+
+void cv1800b_ephy_init(void);
+
+#endif
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index c222197b11..e4e173f9fd 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -861,6 +861,7 @@ static const struct udevice_id designware_eth_ids[] = {
{ .compatible = "amlogic,meson6-dwmac" },
{ .compatible = "st,stm32-dwmac" },
{ .compatible = "snps,arc-dwmac-3.70a" },
+ { .compatible = "sophgo,cv1800b-ethernet" },
{ }
};
--
2.41.0
[PATCH 0/3] board: sophgo: milkv_duo: Add ethernet support for Milk-V Duo board
This series add init code for cv1800b ethernet phy and enable ethernet support for Sophgo Milk-V Duo board. In cv1800b, due to the PHY register phy_id being initialized to 0, it is necessary to initialize the PHY before the ethernet driver initialization. Therefore, the initialization code is placed in the board_init function. Duo to modification of dts and defconfig, This series depends on the series: https://lore.kernel.org/all/20240309175330.79267-1-seashell11234...@gmail.com/ Kongyang Liu (3): board: milkv_duo: Add init code for Milk-V Duo ethernet riscv: dts: sophgo: Add ethernet node configs: milkv_duo: Add ethernet configs arch/riscv/dts/cv18xx.dtsi| 6 +++ board/sophgo/milkv_duo/Makefile | 3 +- board/sophgo/milkv_duo/board.c| 4 ++ board/sophgo/milkv_duo/ethernet.c | 79 +++ board/sophgo/milkv_duo/ethernet.h | 11 + configs/milkv_duo_defconfig | 4 ++ drivers/net/designware.c | 1 + 7 files changed, 107 insertions(+), 1 deletion(-) create mode 100644 board/sophgo/milkv_duo/ethernet.c create mode 100644 board/sophgo/milkv_duo/ethernet.h -- 2.41.0
[PATCH v2 3/3] configs: milkv_duo: Add SD card configs
Add configs related to sdhci and mmc for Sophgo Milk-V Duo board Signed-off-by: Kongyang Liu --- (no changes since v1) configs/milkv_duo_defconfig | 10 ++ 1 file changed, 10 insertions(+) diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig index 548adf174c..e8413d7aa9 100644 --- a/configs/milkv_duo_defconfig +++ b/configs/milkv_duo_defconfig @@ -17,6 +17,16 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=544 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="milkv_duo# " +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y +CONFIG_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_CV1800B=y CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550_MEM32=y -- 2.41.0
[PATCH v2 2/3] riscv: dts: sophgo: Add clk node and sdhci node
Add clk node and sdhci node for cv18xx SoCs according to patches from Linux
kernel.
clk:
https://lore.kernel.org/all/ia1pr20mb4953f9ad6792013b54636f05bb...@ia1pr20mb4953.namprd20.prod.outlook.com/
sdhci: https://lore.kernel.org/all/20240217144826.3944-1-jszh...@kernel.org/
Signed-off-by: Kongyang Liu
---
Changes in v2:
- Sync device tree with ptaches from Linux kernel
arch/riscv/dts/cv1800b-milkv-duo.dts | 8
arch/riscv/dts/cv1800b.dtsi | 4
arch/riscv/dts/cv18xx.dtsi | 22 ++
3 files changed, 34 insertions(+)
diff --git a/arch/riscv/dts/cv1800b-milkv-duo.dts
b/arch/riscv/dts/cv1800b-milkv-duo.dts
index 3af9e34b3b..94e64ddce8 100644
--- a/arch/riscv/dts/cv1800b-milkv-duo.dts
+++ b/arch/riscv/dts/cv1800b-milkv-duo.dts
@@ -33,6 +33,14 @@
clock-frequency = <2500>;
};
+ {
+ status = "okay";
+ bus-width = <4>;
+ no-1-8-v;
+ no-mmc;
+ no-sdio;
+};
+
{
status = "okay";
};
diff --git a/arch/riscv/dts/cv1800b.dtsi b/arch/riscv/dts/cv1800b.dtsi
index 165e9e320a..baf641829e 100644
--- a/arch/riscv/dts/cv1800b.dtsi
+++ b/arch/riscv/dts/cv1800b.dtsi
@@ -16,3 +16,7 @@
{
compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
};
+
+ {
+ compatible = "sophgo,cv1800-clk";
+};
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index 2d6f4a4b1e..ec99c4deeb 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -45,6 +45,13 @@
#clock-cells = <0>;
};
+ sdhci_clk: sdhci-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <37500>;
+ clock-output-names = "sdhci_clk";
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <>;
@@ -53,6 +60,12 @@
dma-noncoherent;
ranges;
+ clk: clock-controller@3002000 {
+ reg = <0x03002000 0x1000>;
+ clocks = <>;
+ #clock-cells = <1>;
+ };
+
gpio0: gpio@302 {
compatible = "snps,dw-apb-gpio";
reg = <0x302 0x1000>;
@@ -175,6 +188,15 @@
status = "disabled";
};
+ sdhci0: mmc@431 {
+ compatible = "sophgo,cv1800b-dwcmshc";
+ reg = <0x431 0x1000>;
+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <_clk>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
plic: interrupt-controller@7000 {
reg = <0x7000 0x400>;
interrupts-extended = <_intc 11>, <_intc 9>;
--
2.41.0
[PATCH v2 1/3] mmc: cv1800b: Add sdhci driver support for cv1800b SoC
Add sdhci driver for cv1800b SoC.
Signed-off-by: Kongyang Liu
---
Changes in v2:
- Refactored and simplified some of the code.
drivers/mmc/Kconfig | 13
drivers/mmc/Makefile| 1 +
drivers/mmc/cv1800b_sdhci.c | 116
3 files changed, 130 insertions(+)
create mode 100644 drivers/mmc/cv1800b_sdhci.c
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index cef05790dd..f7fe6d1042 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -568,6 +568,19 @@ config MMC_SDHCI_CADENCE
If unsure, say N.
+config MMC_SDHCI_CV1800B
+ bool "SDHCI support for the CV1800B SD/SDIO/eMMC controller"
+ depends on BLK && DM_MMC
+ depends on MMC_SDHCI
+ depends on OF_CONTROL
+ help
+ This selects the CV1800B SD/SDIO/eMMC driver.
+
+ If you have a controller with this interface,
+ say Y here.
+
+ If unsure, say N.
+
config MMC_SDHCI_AM654
bool "SDHCI Controller on TI's Am654 devices"
depends on ARCH_K3
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index e9cf1fcc64..3374321e29 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_MMC_SDHCI_ATMEL) += atmel_sdhci.o
obj-$(CONFIG_MMC_SDHCI_BCM2835)+= bcm2835_sdhci.o
obj-$(CONFIG_MMC_SDHCI_BCMSTB) += bcmstb_sdhci.o
obj-$(CONFIG_MMC_SDHCI_CADENCE)+= sdhci-cadence.o
+obj-$(CONFIG_MMC_SDHCI_CV1800B)+= cv1800b_sdhci.o
obj-$(CONFIG_MMC_SDHCI_AM654) += am654_sdhci.o
obj-$(CONFIG_MMC_SDHCI_IPROC) += iproc_sdhci.o
obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o
diff --git a/drivers/mmc/cv1800b_sdhci.c b/drivers/mmc/cv1800b_sdhci.c
new file mode 100644
index 00..2275c53777
--- /dev/null
+++ b/drivers/mmc/cv1800b_sdhci.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ */
+
+#include
+#include
+#include
+#include
+
+#define SDHCI_PHY_TX_RX_DLY 0x240
+#define MMC_MAX_CLOCK37500
+#define TUNE_MAX_PHCODE 128
+
+struct cv1800b_sdhci_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+static void cv1800b_set_tap_delay(struct sdhci_host *host, u16 tap)
+{
+ sdhci_writel(host, tap << 16, SDHCI_PHY_TX_RX_DLY);
+}
+
+static void cv1800b_sdhci_reset(struct sdhci_host *host, u8 mask)
+{
+ sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
+ while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)
+ udelay(10);
+}
+
+static int cv1800b_execute_tuning(struct mmc *mmc, u8 opcode)
+{
+ struct sdhci_host *host = dev_get_priv(mmc->dev);
+
+ u16 tap;
+
+ int current_size = 0;
+ int max_size = 0;
+ int max_window = 0;
+
+ for (tap = 0; tap < TUNE_MAX_PHCODE; tap++) {
+ cv1800b_set_tap_delay(host, tap);
+
+ if (mmc_send_tuning(host->mmc, opcode, NULL)) {
+ current_size = 0;
+ } else {
+ current_size++;
+ if (current_size > max_size) {
+ max_size = current_size;
+ max_window = tap;
+ }
+ }
+ }
+
+ cv1800b_sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+
+ cv1800b_set_tap_delay(host, max_window - max_size / 2);
+
+ return 0;
+}
+
+const struct sdhci_ops cv1800b_sdhci_sd_ops = {
+ .platform_execute_tuning = cv1800b_execute_tuning,
+};
+
+static int cv1800b_sdhci_bind(struct udevice *dev)
+{
+ struct cv1800b_sdhci_plat *plat = dev_get_plat(dev);
+
+ return sdhci_bind(dev, >mmc, >cfg);
+}
+
+static int cv1800b_sdhci_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct cv1800b_sdhci_plat *plat = dev_get_plat(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ int ret;
+
+ host->name = dev->name;
+ host->ioaddr = devfdt_get_addr_ptr(dev);
+
+ upriv->mmc = >mmc;
+ host->mmc = >mmc;
+ host->mmc->priv = host;
+ host->mmc->dev = dev;
+ host->ops = _sdhci_sd_ops;
+ host->max_clk = MMC_MAX_CLOCK;
+
+ ret = mmc_of_parse(dev, >cfg);
+ if (ret)
+ return ret;
+
+ ret = sdhci_setup_cfg(>cfg, host, 0, 20);
+ if (ret)
+ return ret;
+
+ return sdhci_probe(dev);
+}
+
+static const struct udevice_id cv1800b_sdhci_match[] = {
+ { .compatible = "sophgo,cv1800b-dwcmshc" },
+ { }
+};
+
+U_BOOT_DRIVER(cv1800b_sdhci) = {
+ .name = "sdhci-cv1800b",
+ .id = UCLASS_MMC,
+ .of_match = cv1800b_sdhci_match,
+ .bind = cv1800b_sdhci_bind,
+ .probe = cv1800b_sdhci_probe,
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct cv1800b_sdhci_plat),
+ .ops = _ops,
+};
--
2.41.0
[PATCH v2 0/3] mmc: sophgo: milkv_duo: Add SD card support for Milk-V Duo board
This series add sdhci driver for cv1800b SoC and enable SD card support for Sophgo Milk-V Duo board. Changes in v2: - Refactored and simplified some of the code. - Sync device tree with ptaches from Linux kernel Kongyang Liu (3): mmc: cv1800b: Add sdhci driver support for cv1800b SoC riscv: dts: sophgo: Add clk node and sdhci node configs: milkv_duo: Add SD card configs arch/riscv/dts/cv1800b-milkv-duo.dts | 8 ++ arch/riscv/dts/cv1800b.dtsi | 4 + arch/riscv/dts/cv18xx.dtsi | 22 + configs/milkv_duo_defconfig | 10 +++ drivers/mmc/Kconfig | 13 +++ drivers/mmc/Makefile | 1 + drivers/mmc/cv1800b_sdhci.c | 116 +++ 7 files changed, 174 insertions(+) create mode 100644 drivers/mmc/cv1800b_sdhci.c -- 2.41.0
[PATCH v2 2/2] riscv: cache: Implement dcache for cv1800b
Add dcache operations invalidate_dcache_range and flush_dcache_range for
cv1800b.
Signed-off-by: Kongyang Liu
---
(no changes since v1)
arch/riscv/cpu/cv1800b/Makefile | 1 +
arch/riscv/cpu/cv1800b/cache.c | 45 +
2 files changed, 46 insertions(+)
create mode 100644 arch/riscv/cpu/cv1800b/cache.c
diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile
index da12e0f64e..95beb34b51 100644
--- a/arch/riscv/cpu/cv1800b/Makefile
+++ b/arch/riscv/cpu/cv1800b/Makefile
@@ -4,3 +4,4 @@
obj-y += dram.o
obj-y += cpu.o
+obj-y += cache.o
diff --git a/arch/riscv/cpu/cv1800b/cache.c b/arch/riscv/cpu/cv1800b/cache.c
new file mode 100644
index 00..b8051e29e0
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/cache.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ */
+
+#include
+
+/*
+ * dcache.ipa rs1 (invalidate)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 00101010 rs1 000 0 0001011
+ *
+ * dcache.cpa rs1 (clean)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 00101001 rs1 000 0 0001011
+ *
+ * dcache.cipa rs1 (clean then invalidate)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 00101011 rs1 000 0 0001011
+ *
+ * sync.s
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 00011001 0 000 0 0001011
+ */
+#define DCACHE_IPA_A0 ".long 0x02a5000b"
+#define DCACHE_CPA_A0 ".long 0x0295000b"
+#define DCACHE_CIPA_A0 ".long 0x02b5000b"
+
+#define SYNC_S ".long 0x019b"
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+ register unsigned long i asm("a0") = start &
~(CONFIG_SYS_CACHELINE_SIZE - 1);
+ for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
+ __asm__ __volatile__(DCACHE_IPA_A0);
+ __asm__ __volatile__(SYNC_S);
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+ register unsigned long i asm("a0") = start &
~(CONFIG_SYS_CACHELINE_SIZE - 1);
+ for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
+ __asm__ __volatile__(DCACHE_CPA_A0);
+ __asm__ __volatile__(SYNC_S);
+}
--
2.41.0
[PATCH v2 1/2] riscv: cpu: cv1800b: Add support for cv1800b SoC
Add Sophgo cv1800b SoC to support RISC-V arch.
Signed-off-by: Kongyang Liu
---
Changes in v2:
- Remove duplicate code in function cleanup_before_linux
arch/riscv/Kconfig | 1 +
arch/riscv/cpu/cv1800b/Kconfig | 12
arch/riscv/cpu/cv1800b/Makefile | 6 ++
arch/riscv/cpu/cv1800b/cpu.c| 9 +
arch/riscv/cpu/cv1800b/dram.c | 21 +
board/sophgo/milkv_duo/Kconfig | 4 ++--
6 files changed, 51 insertions(+), 2 deletions(-)
create mode 100644 arch/riscv/cpu/cv1800b/Kconfig
create mode 100644 arch/riscv/cpu/cv1800b/Makefile
create mode 100644 arch/riscv/cpu/cv1800b/cpu.c
create mode 100644 arch/riscv/cpu/cv1800b/dram.c
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ac52c5e6da..2c92b0d9f6 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -93,6 +93,7 @@ source "board/xilinx/mbv/Kconfig"
# platform-specific options below
source "arch/riscv/cpu/andesv5/Kconfig"
+source "arch/riscv/cpu/cv1800b/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
source "arch/riscv/cpu/fu740/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
diff --git a/arch/riscv/cpu/cv1800b/Kconfig b/arch/riscv/cpu/cv1800b/Kconfig
new file mode 100644
index 00..7225b1210c
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu
+
+config SOPHGO_CV1800B
+ bool
+ select ARCH_EARLY_INIT_R
+ select SYS_CACHE_SHIFT_6
+ imply CPU
+ imply CPU_RISCV
+ imply RISCV_TIMER
+ imply CMD_CPU
diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile
new file mode 100644
index 00..da12e0f64e
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu
+
+obj-y += dram.o
+obj-y += cpu.o
diff --git a/arch/riscv/cpu/cv1800b/cpu.c b/arch/riscv/cpu/cv1800b/cpu.c
new file mode 100644
index 00..233a6a3d64
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/cpu.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ */
+
+int cleanup_before_linux(void)
+{
+ return 0;
+}
diff --git a/arch/riscv/cpu/cv1800b/dram.c b/arch/riscv/cpu/cv1800b/dram.c
new file mode 100644
index 00..91007c0a3d
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/dram.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
diff --git a/board/sophgo/milkv_duo/Kconfig b/board/sophgo/milkv_duo/Kconfig
index 2a458f291c..040a7487f1 100644
--- a/board/sophgo/milkv_duo/Kconfig
+++ b/board/sophgo/milkv_duo/Kconfig
@@ -7,7 +7,7 @@ config SYS_VENDOR
default "sophgo"
config SYS_CPU
- default "generic"
+ default "cv1800b"
config SYS_CONFIG_NAME
default "milkv_duo"
@@ -23,6 +23,6 @@ config ENV_SECT_SIZE
config BOARD_SPECIFIC_OPTIONS
def_bool y
- select GENERIC_RISCV
+ select SOPHGO_CV1800B
endif
--
2.41.0
[PATCH v2 0/2] riscv: cpu: Add support for cv1800b SoC
This series add basic support for cv1800b SoC and enable dcache support. The cv1800b utilizes CSR instructions to manipulate the first and second bits in the MHCR register (0x7C1) to indicate the activation status of icache and dcache. As the icache and dcache are already enabled in the FSBL (first stage bootloader) provided by the vendor, and the U-Boot running in S-Mode is unable to manipulate CSR registers, support for operations related to enabling, disabling, or checking the status of the cache is not provided. Changes in v2: - Remove duplicate code in function cleanup_before_linux Kongyang Liu (2): riscv: cpu: cv1800b: Add support for cv1800b SoC riscv: cache: Implement dcache for cv1800b arch/riscv/Kconfig | 1 + arch/riscv/cpu/cv1800b/Kconfig | 12 + arch/riscv/cpu/cv1800b/Makefile | 7 + arch/riscv/cpu/cv1800b/cache.c | 45 + arch/riscv/cpu/cv1800b/cpu.c| 9 +++ arch/riscv/cpu/cv1800b/dram.c | 21 +++ board/sophgo/milkv_duo/Kconfig | 4 +-- 7 files changed, 97 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/cpu/cv1800b/Kconfig create mode 100644 arch/riscv/cpu/cv1800b/Makefile create mode 100644 arch/riscv/cpu/cv1800b/cache.c create mode 100644 arch/riscv/cpu/cv1800b/cpu.c create mode 100644 arch/riscv/cpu/cv1800b/dram.c -- 2.41.0
Re: [PATCH 1/2] riscv: cpu: cv1800b: Add support for cv1800b SoC
Heinrich Schuchardt 于2024年2月2日周五 19:11写道：
>
> On 02.02.24 10:37, Kongyang Liu wrote:
> > Add Sophgo cv1800b SoC to support RISC-V arch.
> >
> > Signed-off-by: Kongyang Liu
> >
> > ---
> >
> > arch/riscv/Kconfig | 1 +
> > arch/riscv/cpu/cv1800b/Kconfig | 12
> > arch/riscv/cpu/cv1800b/Makefile | 6 ++
> > arch/riscv/cpu/cv1800b/cpu.c| 22 ++
> > arch/riscv/cpu/cv1800b/dram.c | 21 +
> > board/sophgo/milkv_duo/Kconfig | 4 ++--
> > 6 files changed, 64 insertions(+), 2 deletions(-)
> > create mode 100644 arch/riscv/cpu/cv1800b/Kconfig
> > create mode 100644 arch/riscv/cpu/cv1800b/Makefile
> > create mode 100644 arch/riscv/cpu/cv1800b/cpu.c
> > create mode 100644 arch/riscv/cpu/cv1800b/dram.c
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index ac52c5e6da..2c92b0d9f6 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -93,6 +93,7 @@ source "board/xilinx/mbv/Kconfig"
> >
> > # platform-specific options below
> > source "arch/riscv/cpu/andesv5/Kconfig"
> > +source "arch/riscv/cpu/cv1800b/Kconfig"
> > source "arch/riscv/cpu/fu540/Kconfig"
> > source "arch/riscv/cpu/fu740/Kconfig"
> > source "arch/riscv/cpu/generic/Kconfig"
> > diff --git a/arch/riscv/cpu/cv1800b/Kconfig b/arch/riscv/cpu/cv1800b/Kconfig
> > new file mode 100644
> > index 00..7225b1210c
> > --- /dev/null
> > +++ b/arch/riscv/cpu/cv1800b/Kconfig
> > @@ -0,0 +1,12 @@
> > +# SPDX-License-Identifier: GPL-2.0+
> > +#
> > +# Copyright (c) 2024, Kongyang Liu
> > +
> > +config SOPHGO_CV1800B
> > + bool
> > + select ARCH_EARLY_INIT_R
> > + select SYS_CACHE_SHIFT_6
> > + imply CPU
> > + imply CPU_RISCV
> > + imply RISCV_TIMER
> > + imply CMD_CPU
> > diff --git a/arch/riscv/cpu/cv1800b/Makefile
> > b/arch/riscv/cpu/cv1800b/Makefile
> > new file mode 100644
> > index 00..da12e0f64e
> > --- /dev/null
> > +++ b/arch/riscv/cpu/cv1800b/Makefile
> > @@ -0,0 +1,6 @@
> > +# SPDX-License-Identifier: GPL-2.0+
> > +#
> > +# Copyright (c) 2024, Kongyang Liu
> > +
> > +obj-y += dram.o
> > +obj-y += cpu.o
> > diff --git a/arch/riscv/cpu/cv1800b/cpu.c b/arch/riscv/cpu/cv1800b/cpu.c
> > new file mode 100644
> > index 00..f13c18942f
> > --- /dev/null
> > +++ b/arch/riscv/cpu/cv1800b/cpu.c
> > @@ -0,0 +1,22 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2018, Bin Meng
> > + */
> > +
> > +#include
> > +#include
> > +
> > +/*
> > + * cleanup_before_linux() is called just before we call linux
> > + * it prepares the processor for linux
> > + *
> > + * we disable interrupt and caches.
> > + */
> > +int cleanup_before_linux(void)
> > +{
> > + disable_interrupts();
> > +
> > + cache_flush();
> > +
> > + return 0;
> > +}
>
> Thank you for enabling another board.
>
> The same cleanup_before_linux() code can be found in:
>
> arch/riscv/cpu/fu740/cpu.c
> arch/riscv/cpu/andesv5/cpu.c
> arch/riscv/cpu/fu540/cpu.c
> arch/riscv/cpu/generic/cpu.c
> arch/riscv/cpu/jh7110/cpu.c
>
> We should try to avoid this code duplication.
>
> disable_interrupts() is already called by bootm_disable_interrupts().
>
> flushing the instruction cache after loading a binary is not
> architecture specific either. This is why bootm_load_os() calls
> flush_cache().
>
> It should be sufficient to let weak function flush_dcache_range() in
> arch/riscv/lib/cache.c call flush_dcache_all(). And then remove all
> cleanup_before_linux() implementations.
>
Thanks for your explanation.
Currently, we have only implemented cache for SoC cv1800b, and for the sake
of compatibility, the remaining code has been simply copied from the generic
folder without a thorough examination.
If this function is unnecessary, it will be removed in the next version.
Best regards
Kongyang Liu
> Best regards
>
> Heinrich
>
>
> > diff --git a/arch/riscv/cpu/cv1800b/dram.c b/arch/riscv/cpu/cv1800b/dram.c
> > new file mode 100644
> > index 00..91007c0a3d
> > --- /dev/null
> > +++ b/arch/riscv/cpu/cv1800b/dram.c
> > @@ -0,0 +1,21 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2018, Bin Meng
> > + */
> > +
> > +#
[PATCH 4/4] configs: milkv_duo: Add SD card configs
Add configs related to sdhci and mmc for Sophgo Milk-V Duo board Signed-off-by: Kongyang Liu --- configs/milkv_duo_defconfig | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig index 9eca6abfbc..60eff78ae3 100644 --- a/configs/milkv_duo_defconfig +++ b/configs/milkv_duo_defconfig @@ -11,13 +11,23 @@ CONFIG_TARGET_MILKV_DUO=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_FIT=y +CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=544 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="milkv_duo# " CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_CBSIZE=512 -CONFIG_SYS_PBSIZE=544 -CONFIG_SYS_BOOTM_LEN=0x400 +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y +CONFIG_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_CV1800B=y CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550_MEM32=y -- 2.41.0
[PATCH 3/4] riscv: dts: sophgo: Add sdhci node
Add sdhci node for cv1800b SoC.
Signed-off-by: Kongyang Liu
---
arch/riscv/dts/cv1800b.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/riscv/dts/cv1800b.dtsi b/arch/riscv/dts/cv1800b.dtsi
index baf641829e..11b84b5e79 100644
--- a/arch/riscv/dts/cv1800b.dtsi
+++ b/arch/riscv/dts/cv1800b.dtsi
@@ -7,6 +7,29 @@
/ {
compatible = "sophgo,cv1800b";
+
+ sd: sdhci@431 {
+ compatible = "sophgo,cv1800b-sdhci";
+ reg = <0x431 0x1000>;
+ reg-names = "core_mem";
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ no-sdio;
+ no-mmc;
+ no-1-8-v;
+ src-frequency = <37500>;
+ min-frequency = <40>;
+ max-frequency = <2>;
+ reset_tx_rx_phy;
+ reset-names = "sdhci";
+ pll_index = <0x6>;
+ pll_reg = <0x3002070>;
+ };
};
{
--
2.41.0
[PATCH 2/4] riscv: dts: sophgo: Add clk node
Add clk node for cv18xx SoCs according to patch from Linux kernel.
Link:
https://lore.kernel.org/all/ia1pr20mb4953355805f79abdd7fe9129bb...@ia1pr20mb4953.namprd20.prod.outlook.com/
Signed-off-by: Kongyang Liu
---
arch/riscv/dts/cv1800b.dtsi | 4
arch/riscv/dts/cv18xx.dtsi | 6 ++
2 files changed, 10 insertions(+)
diff --git a/arch/riscv/dts/cv1800b.dtsi b/arch/riscv/dts/cv1800b.dtsi
index 165e9e320a..baf641829e 100644
--- a/arch/riscv/dts/cv1800b.dtsi
+++ b/arch/riscv/dts/cv1800b.dtsi
@@ -16,3 +16,7 @@
{
compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
};
+
+ {
+ compatible = "sophgo,cv1800-clk";
+};
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index 2d6f4a4b1e..6ea1b2784d 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -53,6 +53,12 @@
dma-noncoherent;
ranges;
+ clk: clock-controller@3002000 {
+ reg = <0x03002000 0x1000>;
+ clocks = <>;
+ #clock-cells = <1>;
+ };
+
gpio0: gpio@302 {
compatible = "snps,dw-apb-gpio";
reg = <0x302 0x1000>;
--
2.41.0
[PATCH 1/4] mmc: cv1800b: Add sdhci driver support for cv1800b SoC
Add sdhci driver for cv1800b SoC.
Signed-off-by: Kongyang Liu
---
drivers/mmc/Kconfig | 13 ++
drivers/mmc/Makefile| 1 +
drivers/mmc/cv1800b_sdhci.c | 243
3 files changed, 257 insertions(+)
create mode 100644 drivers/mmc/cv1800b_sdhci.c
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 17618c3bdc..6d5b997fa5 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -568,6 +568,19 @@ config MMC_SDHCI_CADENCE
If unsure, say N.
+config MMC_SDHCI_CV1800B
+ bool "SDHCI support for the CV1800B SD/SDIO/eMMC controller"
+ depends on BLK && DM_MMC
+ depends on MMC_SDHCI
+ depends on OF_CONTROL
+ help
+ This selects the CV1800B SD/SDIO/eMMC driver.
+
+ If you have a controller with this interface,
+ say Y here.
+
+ If unsure, say N.
+
config MMC_SDHCI_AM654
bool "SDHCI Controller on TI's Am654 devices"
depends on ARCH_K3
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index e9cf1fcc64..3374321e29 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_MMC_SDHCI_ATMEL) += atmel_sdhci.o
obj-$(CONFIG_MMC_SDHCI_BCM2835)+= bcm2835_sdhci.o
obj-$(CONFIG_MMC_SDHCI_BCMSTB) += bcmstb_sdhci.o
obj-$(CONFIG_MMC_SDHCI_CADENCE)+= sdhci-cadence.o
+obj-$(CONFIG_MMC_SDHCI_CV1800B)+= cv1800b_sdhci.o
obj-$(CONFIG_MMC_SDHCI_AM654) += am654_sdhci.o
obj-$(CONFIG_MMC_SDHCI_IPROC) += iproc_sdhci.o
obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o
diff --git a/drivers/mmc/cv1800b_sdhci.c b/drivers/mmc/cv1800b_sdhci.c
new file mode 100644
index 00..0de1a2d916
--- /dev/null
+++ b/drivers/mmc/cv1800b_sdhci.c
@@ -0,0 +1,243 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SDHCI_VENDOR_OFFSET 0x200
+#define SDHCI_PHY_TX_RX_DLY (SDHCI_VENDOR_OFFSET + 0x40)
+#define SDHCI_PHY_CONFIG (SDHCI_VENDOR_OFFSET + 0x4C)
+
+#define MMC_MAX_CLOCK37500
+#define MMC_MAX_CLOCK_DIV_VALUE 0x40009
+
+#define REG_CLOCK_BYPASS_SELECT (void *)0x03002030
+#define REG_TOP_SD_PWRSW_CTRL(void *)0x030001F4
+#define REG_PWRSW_AUTO BIT(3)
+#define REG_PWRSW_DISC BIT(2)
+/* REG_PWRSW_VSEL=1: 1.8V, REG_PWRSW_VSEL=0: 3.0V */
+#define REG_PWRSW_VSEL BIT(1)
+#define REG_EN_PWRSW BIT(0)
+
+/* SD Tap Delay Config */
+#define MAX_TUNING_CMD_RETRY_COUNT 50
+#define TUNE_MAX_PHCODE128
+#define TAP_WINDOW_THLD20
+
+struct cv1800b_sdhci_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+struct cv1800b_sdhci_host {
+ struct sdhci_host host;
+ u32 pll_index;
+ u64 pll_reg;
+ bool no_1_8_v;
+ bool reset_tx_rx_phy;
+ u32 mmc_fmax_freq;
+ u32 mmc_fmin_freq;
+};
+
+static inline void sdhci_setbits(struct sdhci_host *host, int reg, u32 mask)
+{
+ u32 val;
+
+ val = sdhci_readl(host, reg);
+ val |= mask;
+ sdhci_writel(host, val, reg);
+}
+
+static inline void sdhci_clrbits(struct sdhci_host *host, int reg, u32 mask)
+{
+ u32 val;
+
+ val = sdhci_readl(host, reg);
+ val &= ~mask;
+ sdhci_writel(host, val, reg);
+}
+
+static void cv1800b_set_tap_delay(struct sdhci_host *host, u16 tap)
+{
+ sdhci_clrbits(host, SDHCI_CLOCK_CONTROL, SDHCI_CLOCK_CARD_EN);
+
+ sdhci_writel(host, 0, SDHCI_VENDOR_OFFSET);
+ sdhci_writel(host, BIT(8) | tap << 16, SDHCI_PHY_TX_RX_DLY);
+ sdhci_writel(host, 0, SDHCI_PHY_CONFIG);
+
+ sdhci_setbits(host, SDHCI_CLOCK_CONTROL, SDHCI_CLOCK_CARD_EN);
+}
+
+int cv1800b_get_cd(struct sdhci_host *host)
+{
+ return sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT;
+}
+
+int cv1800b_general_execute_tuning(struct mmc *mmc, u8 opcode)
+{
+ struct cv1800b_sdhci_host *priv = dev_get_priv(mmc->dev);
+ struct sdhci_host *host = >host;
+
+ int ret;
+
+ u16 tap = 0;
+ u32 retry_cnt = 0;
+
+ int cur_window_idx = -1;
+ int max_window_size = 0;
+ int cur_window_size = 0;
+ int final_tap = -1;
+
+ sdhci_clrbits(host, SDHCI_HOST_CONTROL2, SDHCI_CTRL_TUNED_CLK |
SDHCI_CTRL_DRV_TYPE_MASK);
+
+ for (tap = 0; tap < TUNE_MAX_PHCODE; tap++) {
+ sdhci_writew(host, BIT(2), SDHCI_VENDOR_OFFSET);
+ cv1800b_set_tap_delay(host, tap);
+
+ for (retry_cnt = 0; retry_cnt < MAX_TUNING_CMD_RETRY_COUNT;
retry_cnt++) {
+ ret = mmc_send_tuning(host->mmc, opcode, NULL);
+ if (ret)
+ break;
+ }
+
+ /* Find a final tap as median of maximum window */
+ if (ret) {
+
[PATCH 0/4] mmc: sophgo: milkv_duo: Add SD card support for Milk-V Duo board
This series add sdhci driver for cv1800b SoC and enable SD card support for Sophgo Milk-V Duo board. Kongyang Liu (4): mmc: cv1800b: Add sdhci driver support for cv1800b SoC riscv: dts: sophgo: Add clk node riscv: dts: sophgo: Add sdhci node configs: milkv_duo: Add SD card configs arch/riscv/dts/cv1800b.dtsi | 27 arch/riscv/dts/cv18xx.dtsi | 6 + configs/milkv_duo_defconfig | 16 ++- drivers/mmc/Kconfig | 13 ++ drivers/mmc/Makefile| 1 + drivers/mmc/cv1800b_sdhci.c | 243 6 files changed, 303 insertions(+), 3 deletions(-) create mode 100644 drivers/mmc/cv1800b_sdhci.c -- 2.41.0
[PATCH 2/2] riscv: cache: Implement dcache for cv1800b
Add dcache operations invalidate_dcache_range and flush_dcache_range for
cv1800b.
Signed-off-by: Kongyang Liu
---
arch/riscv/cpu/cv1800b/Makefile | 1 +
arch/riscv/cpu/cv1800b/cache.c | 45 +
2 files changed, 46 insertions(+)
create mode 100644 arch/riscv/cpu/cv1800b/cache.c
diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile
index da12e0f64e..95beb34b51 100644
--- a/arch/riscv/cpu/cv1800b/Makefile
+++ b/arch/riscv/cpu/cv1800b/Makefile
@@ -4,3 +4,4 @@
obj-y += dram.o
obj-y += cpu.o
+obj-y += cache.o
diff --git a/arch/riscv/cpu/cv1800b/cache.c b/arch/riscv/cpu/cv1800b/cache.c
new file mode 100644
index 00..b8051e29e0
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/cache.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ */
+
+#include
+
+/*
+ * dcache.ipa rs1 (invalidate)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 00101010 rs1 000 0 0001011
+ *
+ * dcache.cpa rs1 (clean)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 00101001 rs1 000 0 0001011
+ *
+ * dcache.cipa rs1 (clean then invalidate)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 00101011 rs1 000 0 0001011
+ *
+ * sync.s
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 00011001 0 000 0 0001011
+ */
+#define DCACHE_IPA_A0 ".long 0x02a5000b"
+#define DCACHE_CPA_A0 ".long 0x0295000b"
+#define DCACHE_CIPA_A0 ".long 0x02b5000b"
+
+#define SYNC_S ".long 0x019b"
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+ register unsigned long i asm("a0") = start &
~(CONFIG_SYS_CACHELINE_SIZE - 1);
+ for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
+ __asm__ __volatile__(DCACHE_IPA_A0);
+ __asm__ __volatile__(SYNC_S);
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+ register unsigned long i asm("a0") = start &
~(CONFIG_SYS_CACHELINE_SIZE - 1);
+ for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
+ __asm__ __volatile__(DCACHE_CPA_A0);
+ __asm__ __volatile__(SYNC_S);
+}
--
2.41.0
[PATCH 1/2] riscv: cpu: cv1800b: Add support for cv1800b SoC
Add Sophgo cv1800b SoC to support RISC-V arch.
Signed-off-by: Kongyang Liu
---
arch/riscv/Kconfig | 1 +
arch/riscv/cpu/cv1800b/Kconfig | 12
arch/riscv/cpu/cv1800b/Makefile | 6 ++
arch/riscv/cpu/cv1800b/cpu.c| 22 ++
arch/riscv/cpu/cv1800b/dram.c | 21 +
board/sophgo/milkv_duo/Kconfig | 4 ++--
6 files changed, 64 insertions(+), 2 deletions(-)
create mode 100644 arch/riscv/cpu/cv1800b/Kconfig
create mode 100644 arch/riscv/cpu/cv1800b/Makefile
create mode 100644 arch/riscv/cpu/cv1800b/cpu.c
create mode 100644 arch/riscv/cpu/cv1800b/dram.c
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ac52c5e6da..2c92b0d9f6 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -93,6 +93,7 @@ source "board/xilinx/mbv/Kconfig"
# platform-specific options below
source "arch/riscv/cpu/andesv5/Kconfig"
+source "arch/riscv/cpu/cv1800b/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
source "arch/riscv/cpu/fu740/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
diff --git a/arch/riscv/cpu/cv1800b/Kconfig b/arch/riscv/cpu/cv1800b/Kconfig
new file mode 100644
index 00..7225b1210c
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu
+
+config SOPHGO_CV1800B
+ bool
+ select ARCH_EARLY_INIT_R
+ select SYS_CACHE_SHIFT_6
+ imply CPU
+ imply CPU_RISCV
+ imply RISCV_TIMER
+ imply CMD_CPU
diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile
new file mode 100644
index 00..da12e0f64e
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu
+
+obj-y += dram.o
+obj-y += cpu.o
diff --git a/arch/riscv/cpu/cv1800b/cpu.c b/arch/riscv/cpu/cv1800b/cpu.c
new file mode 100644
index 00..f13c18942f
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/cpu.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng
+ */
+
+#include
+#include
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+ cache_flush();
+
+ return 0;
+}
diff --git a/arch/riscv/cpu/cv1800b/dram.c b/arch/riscv/cpu/cv1800b/dram.c
new file mode 100644
index 00..91007c0a3d
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/dram.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
diff --git a/board/sophgo/milkv_duo/Kconfig b/board/sophgo/milkv_duo/Kconfig
index 2a458f291c..040a7487f1 100644
--- a/board/sophgo/milkv_duo/Kconfig
+++ b/board/sophgo/milkv_duo/Kconfig
@@ -7,7 +7,7 @@ config SYS_VENDOR
default "sophgo"
config SYS_CPU
- default "generic"
+ default "cv1800b"
config SYS_CONFIG_NAME
default "milkv_duo"
@@ -23,6 +23,6 @@ config ENV_SECT_SIZE
config BOARD_SPECIFIC_OPTIONS
def_bool y
- select GENERIC_RISCV
+ select SOPHGO_CV1800B
endif
--
2.41.0
[PATCH 0/2] riscv: cpu: Add support for cv1800b SoC
This series add basic support for cv1800b SoC and enable dcache support. The cv1800b utilizes CSR instructions to manipulate the first and second bits in the MHCR register (0x7C1) to indicate the activation status of icache and dcache. As the icache and dcache are already enabled in the FSBL (first stage bootloader) provided by the vendor, and the U-Boot running in S-Mode is unable to manipulate CSR registers, support for operations related to enabling, disabling, or checking the status of the cache is not provided. Kongyang Liu (2): riscv: cpu: cv1800b: Add support for cv1800b SoC riscv: cache: Implement dcache for cv1800b arch/riscv/Kconfig | 1 + arch/riscv/cpu/cv1800b/Kconfig | 12 + arch/riscv/cpu/cv1800b/Makefile | 7 + arch/riscv/cpu/cv1800b/cache.c | 45 + arch/riscv/cpu/cv1800b/cpu.c| 22 arch/riscv/cpu/cv1800b/dram.c | 21 +++ board/sophgo/milkv_duo/Kconfig | 4 +-- 7 files changed, 110 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/cpu/cv1800b/Kconfig create mode 100644 arch/riscv/cpu/cv1800b/Makefile create mode 100644 arch/riscv/cpu/cv1800b/cache.c create mode 100644 arch/riscv/cpu/cv1800b/cpu.c create mode 100644 arch/riscv/cpu/cv1800b/dram.c -- 2.41.0
Re: [PATCH v4 3/3] doc: sophgo: milkv_duo: document Milk-V Duo board
Heinrich Schuchardt 于2024年1月28日周日 17:16写道： > > On 1/28/24 08:05, Kongyang Liu wrote: > > Add document for Milk-V Duo board which based on Sophgo's CV1800B SoC. > > > > Signed-off-by: Kongyang Liu > > > > --- > > > > (no changes since v3) > > > > Changes in v3: > > - Add brief description of the procedure to run u-boot-dtb.bin > > > > doc/board/index.rst| 1 + > > doc/board/sophgo/index.rst | 8 + > > doc/board/sophgo/milkv_duo.rst | 64 ++ > > 3 files changed, 73 insertions(+) > > create mode 100644 doc/board/sophgo/index.rst > > create mode 100644 doc/board/sophgo/milkv_duo.rst > > > > diff --git a/doc/board/index.rst b/doc/board/index.rst > > index c96e5fda28..d0f9f355d2 100644 > > --- a/doc/board/index.rst > > +++ b/doc/board/index.rst > > @@ -46,6 +46,7 @@ Board-specific doc > > sifive/index > > sipeed/index > > socionext/index > > + sophgo/index > > st/index > > starfive/index > > ste/index > > diff --git a/doc/board/sophgo/index.rst b/doc/board/sophgo/index.rst > > new file mode 100644 > > index 00..e097afdac6 > > --- /dev/null > > +++ b/doc/board/sophgo/index.rst > > @@ -0,0 +1,8 @@ > > +.. SPDX-License-Identifier: GPL-2.0+ > > + > > +Sophgo > > +== > > +.. toctree:: > > + :maxdepth: 1 > > + > > + milkv_duo > > diff --git a/doc/board/sophgo/milkv_duo.rst b/doc/board/sophgo/milkv_duo.rst > > new file mode 100644 > > index 00..cb2ed1ad98 > > --- /dev/null > > +++ b/doc/board/sophgo/milkv_duo.rst > > @@ -0,0 +1,64 @@ > > +.. SPDX-License-Identifier: GPL-2.0+ > > + > > +Milk-V Duo > > +== > > + > > +CV1800B RISC-V SoC > > +-- > > +The CV1800B is a high-performance, low-power 1+1 64-bit RISC-V SoC from > > Sophgo. > > + > > +Mainline support > > + > > +The support for following drivers are already enabled: > > +1. ns16550 UART Driver. > > + > > +Building > > + > > +1. Add the RISC-V toolchain to your PATH. > > +2. Setup ARCH & cross compilation environment variable: > > + > > +.. code-block:: console > > + > > + export CROSS_COMPILE= > > + cd > > + make milkv_duo_defconfig > > + make > > + > > +This will generate u-boot-dtb.bin > > + > > +Booting > > +~~~ > > +Currently, we rely on vendor FSBL(First Stage Boot Loader) to initialize > > the > > +clock and load the u-boot image, then bootup from it. > > + > > +Alternatively, to run u-boot-dtb.bin on top of FSBL, follow these steps: > > + > > +1. Use the vendor-provided tool to create a unified fip.bin file containing > > + FSBL, OpenSBI, and U-Boot. > > Hello Kongyang, > > thank you for providing a documentation for the board. > > Concerning the usage of fip.bin it would be helpful to add more detail: > > * From where can the vendor code be downloaded? > * Which are the commands to execute? > We have leveraged the BuildSDK from the Milk-V Duo project (https://github.com/milkv-duo/duo-buildroot-sdk) and made slight modifications to ensure compatibility with the mainline OpenSBI and U-Boot. After the repository reaches a stable state, we will publish it on GitHub. Best regards Kongyang Liu > Best regards > > Heinrich > > > + > > +2. Place the generated fip.bin file into the FAT partition of the SD card. > > + > > +3. Insert the SD card into the board and power it on. > > + > > +The board will automatically execute the FSBL from the fip.bin file. > > +Subsequently, it will transition to OpenSBI, and finally, OpenSBI will > > invoke > > +U-Boot. > > + > > + > > +Sample boot log from Milk-V Duo board > > +~ > > +.. code-block:: none > > + > > + U-Boot 2024.01-rc5-00010-g51965baa36 (Dec 28 2023 - 13:15:53 > > +0800)milkv_duo > > + > > + DRAM: 63.3 MiB > > + Core: 10 devices, 8 uclasses, devicetree: separate > > + Loading Environment from nowhere... OK > > + In:serial@414 > > + Out: serial@414 > > + Err: serial@414 > > + Net: No ethernet found. > > + milkv_duo# cpu detail > > + 0: cpu@0 rv64imafdc > > + ID = 0, freq = 0 Hz: L1 cache, MMU > > + milkv_duo# >
[PATCH v4 3/3] doc: sophgo: milkv_duo: document Milk-V Duo board
Add document for Milk-V Duo board which based on Sophgo's CV1800B SoC. Signed-off-by: Kongyang Liu --- (no changes since v3) Changes in v3: - Add brief description of the procedure to run u-boot-dtb.bin doc/board/index.rst| 1 + doc/board/sophgo/index.rst | 8 + doc/board/sophgo/milkv_duo.rst | 64 ++ 3 files changed, 73 insertions(+) create mode 100644 doc/board/sophgo/index.rst create mode 100644 doc/board/sophgo/milkv_duo.rst diff --git a/doc/board/index.rst b/doc/board/index.rst index c96e5fda28..d0f9f355d2 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -46,6 +46,7 @@ Board-specific doc sifive/index sipeed/index socionext/index + sophgo/index st/index starfive/index ste/index diff --git a/doc/board/sophgo/index.rst b/doc/board/sophgo/index.rst new file mode 100644 index 00..e097afdac6 --- /dev/null +++ b/doc/board/sophgo/index.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Sophgo +== +.. toctree:: + :maxdepth: 1 + + milkv_duo diff --git a/doc/board/sophgo/milkv_duo.rst b/doc/board/sophgo/milkv_duo.rst new file mode 100644 index 00..cb2ed1ad98 --- /dev/null +++ b/doc/board/sophgo/milkv_duo.rst @@ -0,0 +1,64 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Milk-V Duo +== + +CV1800B RISC-V SoC +-- +The CV1800B is a high-performance, low-power 1+1 64-bit RISC-V SoC from Sophgo. + +Mainline support + +The support for following drivers are already enabled: +1. ns16550 UART Driver. + +Building + +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: console + + export CROSS_COMPILE= + cd + make milkv_duo_defconfig + make + +This will generate u-boot-dtb.bin + +Booting +~~~ +Currently, we rely on vendor FSBL(First Stage Boot Loader) to initialize the +clock and load the u-boot image, then bootup from it. + +Alternatively, to run u-boot-dtb.bin on top of FSBL, follow these steps: + +1. Use the vendor-provided tool to create a unified fip.bin file containing + FSBL, OpenSBI, and U-Boot. + +2. Place the generated fip.bin file into the FAT partition of the SD card. + +3. Insert the SD card into the board and power it on. + +The board will automatically execute the FSBL from the fip.bin file. +Subsequently, it will transition to OpenSBI, and finally, OpenSBI will invoke +U-Boot. + + +Sample boot log from Milk-V Duo board +~ +.. code-block:: none + + U-Boot 2024.01-rc5-00010-g51965baa36 (Dec 28 2023 - 13:15:53 +0800)milkv_duo + + DRAM: 63.3 MiB + Core: 10 devices, 8 uclasses, devicetree: separate + Loading Environment from nowhere... OK + In:serial@414 + Out: serial@414 + Err: serial@414 + Net: No ethernet found. + milkv_duo# cpu detail + 0: cpu@0 rv64imafdc + ID = 0, freq = 0 Hz: L1 cache, MMU + milkv_duo# -- 2.41.0
[PATCH v4 2/3] riscv: sophgo: milkv_duo: initial support added
Add support for Sophgo's Milk-V Duo board, only minimal device tree and
serial console are enabled, and it can boot via vendor first stage
bootloader.
Signed-off-by: Kongyang Liu
---
(no changes since v3)
Changes in v3:
- Enable EFI loader
Changes in v2:
- Fold the defconfig patch to first patch
- Remove unnecessary environment settings of consoledev and baudrate in
config
arch/riscv/Kconfig | 4
board/sophgo/milkv_duo/Kconfig | 28
board/sophgo/milkv_duo/MAINTAINERS | 6 ++
board/sophgo/milkv_duo/Makefile| 5 +
board/sophgo/milkv_duo/board.c | 9 +
configs/milkv_duo_defconfig| 23 +++
include/configs/milkv_duo.h| 12
7 files changed, 87 insertions(+)
create mode 100644 board/sophgo/milkv_duo/Kconfig
create mode 100644 board/sophgo/milkv_duo/MAINTAINERS
create mode 100644 board/sophgo/milkv_duo/Makefile
create mode 100644 board/sophgo/milkv_duo/board.c
create mode 100644 configs/milkv_duo_defconfig
create mode 100644 include/configs/milkv_duo.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 67126d96af..ac52c5e6da 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -14,6 +14,9 @@ config TARGET_ANDES_AE350
config TARGET_MICROCHIP_ICICLE
bool "Support Microchip PolarFire-SoC Icicle Board"
+config TARGET_MILKV_DUO
+ bool "Support Milk-v Duo Board"
+
config TARGET_OPENPITON_RISCV64
bool "Support RISC-V cores on OpenPiton SoC"
@@ -83,6 +86,7 @@ source "board/openpiton/riscv64/Kconfig"
source "board/sifive/unleashed/Kconfig"
source "board/sifive/unmatched/Kconfig"
source "board/sipeed/maix/Kconfig"
+source "board/sophgo/milkv_duo/Kconfig"
source "board/starfive/visionfive2/Kconfig"
source "board/thead/th1520_lpi4a/Kconfig"
source "board/xilinx/mbv/Kconfig"
diff --git a/board/sophgo/milkv_duo/Kconfig b/board/sophgo/milkv_duo/Kconfig
new file mode 100644
index 00..2a458f291c
--- /dev/null
+++ b/board/sophgo/milkv_duo/Kconfig
@@ -0,0 +1,28 @@
+if TARGET_MILKV_DUO
+
+config SYS_BOARD
+ default "milkv_duo"
+
+config SYS_VENDOR
+ default "sophgo"
+
+config SYS_CPU
+ default "generic"
+
+config SYS_CONFIG_NAME
+ default "milkv_duo"
+
+config TEXT_BASE
+ default 0x8020
+
+config ENV_SIZE
+ default 0x2
+
+config ENV_SECT_SIZE
+ default 0x4
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select GENERIC_RISCV
+
+endif
diff --git a/board/sophgo/milkv_duo/MAINTAINERS
b/board/sophgo/milkv_duo/MAINTAINERS
new file mode 100644
index 00..651a0592f7
--- /dev/null
+++ b/board/sophgo/milkv_duo/MAINTAINERS
@@ -0,0 +1,6 @@
+Milk-V Duo
+M: Kongyang Liu
+S: Maintained
+F: board/sophgo/milkv_duo/
+F: configs/milkv_duo_defconfig
+F: doc/board/sophgo/milkv_duo.rst
diff --git a/board/sophgo/milkv_duo/Makefile b/board/sophgo/milkv_duo/Makefile
new file mode 100644
index 00..a087013f5c
--- /dev/null
+++ b/board/sophgo/milkv_duo/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu
+
+obj-y := board.o
diff --git a/board/sophgo/milkv_duo/board.c b/board/sophgo/milkv_duo/board.c
new file mode 100644
index 00..eaa47be173
--- /dev/null
+++ b/board/sophgo/milkv_duo/board.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ */
+
+int board_init(void)
+{
+ return 0;
+}
diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig
new file mode 100644
index 00..9eca6abfbc
--- /dev/null
+++ b/configs/milkv_duo_defconfig
@@ -0,0 +1,23 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x82
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8230
+CONFIG_DEFAULT_DEVICE_TREE="cv1800b-milkv-duo"
+CONFIG_IDENT_STRING="milkv_duo"
+CONFIG_SYS_LOAD_ADDR=0x8008
+CONFIG_TARGET_MILKV_DUO=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_FIT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="milkv_duo# "
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=544
+CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
diff --git a/include/configs/milkv_duo.h b/include/configs/milkv_duo.h
new file mode 100644
index 00..0b4109dc1f
--- /dev/null
+++ b/include/configs/milkv_duo.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CFG_SYS_SDRAM_BASE 0x8000
+
+#endif /* __CONFIG_H */
--
2.41.0
[PATCH v4 1/3] riscv: dts: sophgo: add basic device tree for Milk-V Duo board
Import device tree from Linux kernel to add basic support for CPU, PLIC,
UART and Timer. The name cv1800b in the filename represent the chip used
on Milk-V Duo board.
Signed-off-by: Kongyang Liu
---
Changes in v4:
- Sync dts files with Linux kernel
Changes in v3:
- Swap patch 1 and 2 duo to dependency of defconfig and device tree
arch/riscv/dts/Makefile | 1 +
arch/riscv/dts/cv1800b-milkv-duo.dts | 38 ++
arch/riscv/dts/cv1800b.dtsi | 18 +++
arch/riscv/dts/cv18xx.dtsi | 192 +++
4 files changed, 249 insertions(+)
create mode 100644 arch/riscv/dts/cv1800b-milkv-duo.dts
create mode 100644 arch/riscv/dts/cv1800b.dtsi
create mode 100644 arch/riscv/dts/cv18xx.dtsi
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index b05bb5607f..17cda483e1 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,6 +2,7 @@
dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
diff --git a/arch/riscv/dts/cv1800b-milkv-duo.dts
b/arch/riscv/dts/cv1800b-milkv-duo.dts
new file mode 100644
index 00..3af9e34b3b
--- /dev/null
+++ b/arch/riscv/dts/cv1800b-milkv-duo.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang
+ */
+
+/dts-v1/;
+
+#include "cv1800b.dtsi"
+
+/ {
+ model = "Milk-V Duo";
+ compatible = "milkv,duo", "sophgo,cv1800b";
+
+ aliases {
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
+ serial4 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x8000 0x3f4>;
+ };
+};
+
+ {
+ clock-frequency = <2500>;
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/riscv/dts/cv1800b.dtsi b/arch/riscv/dts/cv1800b.dtsi
new file mode 100644
index 00..165e9e320a
--- /dev/null
+++ b/arch/riscv/dts/cv1800b.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang
+ */
+
+#include "cv18xx.dtsi"
+
+/ {
+ compatible = "sophgo,cv1800b";
+};
+
+ {
+ compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
+};
+
+ {
+ compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
+};
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
new file mode 100644
index 00..2d6f4a4b1e
--- /dev/null
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang
+ * Copyright (C) 2023 Inochi Amaoto
+ */
+
+#include
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <2500>;
+
+ cpu0: cpu@0 {
+ compatible = "thead,c906", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <65536>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ osc: oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "osc_25m";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-par
[PATCH v4 0/3] riscv: sophgo: milkv_duo: add support for Milk-V Duo board
The Milk-V Duo board is built upon Sophgo's CV1800B SoC, featuring two XuanTie C906 CPUs running at 1.0GHz and 700MHz, respectively. This series introduces fundamental support for the Milk-V Duo board, encompassing UART, CPU, and PLIC support. This ensures that U-Boot can operate in serial console mode. Changes in v4: - Sync dts files with Linux kernel Changes in v3: - Swap patch 1 and 2 duo to dependency of defconfig and device tree - Enable EFI loader - Add brief description of the procedure to run u-boot-dtb.bin Changes in v2: - Fold the defconfig patch to first patch - Remove unnecessary environment settings of consoledev and baudrate in config Kongyang Liu (3): riscv: dts: sophgo: add basic device tree for Milk-V Duo board riscv: sophgo: milkv_duo: initial support added doc: sophgo: milkv_duo: document Milk-V Duo board arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/cv1800b-milkv-duo.dts | 38 ++ arch/riscv/dts/cv1800b.dtsi | 18 +++ arch/riscv/dts/cv18xx.dtsi | 192 +++ board/sophgo/milkv_duo/Kconfig | 28 board/sophgo/milkv_duo/MAINTAINERS | 6 + board/sophgo/milkv_duo/Makefile | 5 + board/sophgo/milkv_duo/board.c | 9 ++ configs/milkv_duo_defconfig | 23 doc/board/index.rst | 1 + doc/board/sophgo/index.rst | 8 ++ doc/board/sophgo/milkv_duo.rst | 64 + include/configs/milkv_duo.h | 12 ++ 14 files changed, 409 insertions(+) create mode 100644 arch/riscv/dts/cv1800b-milkv-duo.dts create mode 100644 arch/riscv/dts/cv1800b.dtsi create mode 100644 arch/riscv/dts/cv18xx.dtsi create mode 100644 board/sophgo/milkv_duo/Kconfig create mode 100644 board/sophgo/milkv_duo/MAINTAINERS create mode 100644 board/sophgo/milkv_duo/Makefile create mode 100644 board/sophgo/milkv_duo/board.c create mode 100644 configs/milkv_duo_defconfig create mode 100644 doc/board/sophgo/index.rst create mode 100644 doc/board/sophgo/milkv_duo.rst create mode 100644 include/configs/milkv_duo.h -- 2.41.0
[PATCH v3 3/3] doc: sophgo: milkv_duo: document Milk-V Duo board
Add document for Milk-V Duo board which based on Sophgo's CV1800B SoC. Signed-off-by: Kongyang Liu --- Changes in v3: - Add brief description of the procedure to run u-boot-dtb.bin doc/board/index.rst| 1 + doc/board/sophgo/index.rst | 8 + doc/board/sophgo/milkv_duo.rst | 64 ++ 3 files changed, 73 insertions(+) create mode 100644 doc/board/sophgo/index.rst create mode 100644 doc/board/sophgo/milkv_duo.rst diff --git a/doc/board/index.rst b/doc/board/index.rst index c96e5fda28..d0f9f355d2 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -46,6 +46,7 @@ Board-specific doc sifive/index sipeed/index socionext/index + sophgo/index st/index starfive/index ste/index diff --git a/doc/board/sophgo/index.rst b/doc/board/sophgo/index.rst new file mode 100644 index 00..e097afdac6 --- /dev/null +++ b/doc/board/sophgo/index.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Sophgo +== +.. toctree:: + :maxdepth: 1 + + milkv_duo diff --git a/doc/board/sophgo/milkv_duo.rst b/doc/board/sophgo/milkv_duo.rst new file mode 100644 index 00..cb2ed1ad98 --- /dev/null +++ b/doc/board/sophgo/milkv_duo.rst @@ -0,0 +1,64 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Milk-V Duo +== + +CV1800B RISC-V SoC +-- +The CV1800B is a high-performance, low-power 1+1 64-bit RISC-V SoC from Sophgo. + +Mainline support + +The support for following drivers are already enabled: +1. ns16550 UART Driver. + +Building + +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: console + + export CROSS_COMPILE= + cd + make milkv_duo_defconfig + make + +This will generate u-boot-dtb.bin + +Booting +~~~ +Currently, we rely on vendor FSBL(First Stage Boot Loader) to initialize the +clock and load the u-boot image, then bootup from it. + +Alternatively, to run u-boot-dtb.bin on top of FSBL, follow these steps: + +1. Use the vendor-provided tool to create a unified fip.bin file containing + FSBL, OpenSBI, and U-Boot. + +2. Place the generated fip.bin file into the FAT partition of the SD card. + +3. Insert the SD card into the board and power it on. + +The board will automatically execute the FSBL from the fip.bin file. +Subsequently, it will transition to OpenSBI, and finally, OpenSBI will invoke +U-Boot. + + +Sample boot log from Milk-V Duo board +~ +.. code-block:: none + + U-Boot 2024.01-rc5-00010-g51965baa36 (Dec 28 2023 - 13:15:53 +0800)milkv_duo + + DRAM: 63.3 MiB + Core: 10 devices, 8 uclasses, devicetree: separate + Loading Environment from nowhere... OK + In:serial@414 + Out: serial@414 + Err: serial@414 + Net: No ethernet found. + milkv_duo# cpu detail + 0: cpu@0 rv64imafdc + ID = 0, freq = 0 Hz: L1 cache, MMU + milkv_duo# -- 2.41.0
[PATCH v3 2/3] riscv: sophgo: milkv_duo: initial support added
Add support for Sophgo's Milk-V Duo board, only minimal device tree and
serial console are enabled, and it can boot via vendor first stage
bootloader.
Signed-off-by: Kongyang Liu
---
Changes in v3:
- Enable EFI loader
Changes in v2:
- Fold the defconfig patch to first patch
- Remove unnecessary environment settings of consoledev and baudrate in
config
arch/riscv/Kconfig | 4
board/sophgo/milkv_duo/Kconfig | 28
board/sophgo/milkv_duo/MAINTAINERS | 6 ++
board/sophgo/milkv_duo/Makefile| 5 +
board/sophgo/milkv_duo/board.c | 9 +
configs/milkv_duo_defconfig| 23 +++
include/configs/milkv_duo.h| 12
7 files changed, 87 insertions(+)
create mode 100644 board/sophgo/milkv_duo/Kconfig
create mode 100644 board/sophgo/milkv_duo/MAINTAINERS
create mode 100644 board/sophgo/milkv_duo/Makefile
create mode 100644 board/sophgo/milkv_duo/board.c
create mode 100644 configs/milkv_duo_defconfig
create mode 100644 include/configs/milkv_duo.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 67126d96af..ac52c5e6da 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -14,6 +14,9 @@ config TARGET_ANDES_AE350
config TARGET_MICROCHIP_ICICLE
bool "Support Microchip PolarFire-SoC Icicle Board"
+config TARGET_MILKV_DUO
+ bool "Support Milk-v Duo Board"
+
config TARGET_OPENPITON_RISCV64
bool "Support RISC-V cores on OpenPiton SoC"
@@ -83,6 +86,7 @@ source "board/openpiton/riscv64/Kconfig"
source "board/sifive/unleashed/Kconfig"
source "board/sifive/unmatched/Kconfig"
source "board/sipeed/maix/Kconfig"
+source "board/sophgo/milkv_duo/Kconfig"
source "board/starfive/visionfive2/Kconfig"
source "board/thead/th1520_lpi4a/Kconfig"
source "board/xilinx/mbv/Kconfig"
diff --git a/board/sophgo/milkv_duo/Kconfig b/board/sophgo/milkv_duo/Kconfig
new file mode 100644
index 00..2a458f291c
--- /dev/null
+++ b/board/sophgo/milkv_duo/Kconfig
@@ -0,0 +1,28 @@
+if TARGET_MILKV_DUO
+
+config SYS_BOARD
+ default "milkv_duo"
+
+config SYS_VENDOR
+ default "sophgo"
+
+config SYS_CPU
+ default "generic"
+
+config SYS_CONFIG_NAME
+ default "milkv_duo"
+
+config TEXT_BASE
+ default 0x8020
+
+config ENV_SIZE
+ default 0x2
+
+config ENV_SECT_SIZE
+ default 0x4
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select GENERIC_RISCV
+
+endif
diff --git a/board/sophgo/milkv_duo/MAINTAINERS
b/board/sophgo/milkv_duo/MAINTAINERS
new file mode 100644
index 00..651a0592f7
--- /dev/null
+++ b/board/sophgo/milkv_duo/MAINTAINERS
@@ -0,0 +1,6 @@
+Milk-V Duo
+M: Kongyang Liu
+S: Maintained
+F: board/sophgo/milkv_duo/
+F: configs/milkv_duo_defconfig
+F: doc/board/sophgo/milkv_duo.rst
diff --git a/board/sophgo/milkv_duo/Makefile b/board/sophgo/milkv_duo/Makefile
new file mode 100644
index 00..a087013f5c
--- /dev/null
+++ b/board/sophgo/milkv_duo/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu
+
+obj-y := board.o
diff --git a/board/sophgo/milkv_duo/board.c b/board/sophgo/milkv_duo/board.c
new file mode 100644
index 00..eaa47be173
--- /dev/null
+++ b/board/sophgo/milkv_duo/board.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ */
+
+int board_init(void)
+{
+ return 0;
+}
diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig
new file mode 100644
index 00..9eca6abfbc
--- /dev/null
+++ b/configs/milkv_duo_defconfig
@@ -0,0 +1,23 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x82
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8230
+CONFIG_DEFAULT_DEVICE_TREE="cv1800b-milkv-duo"
+CONFIG_IDENT_STRING="milkv_duo"
+CONFIG_SYS_LOAD_ADDR=0x8008
+CONFIG_TARGET_MILKV_DUO=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_FIT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="milkv_duo# "
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=544
+CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
diff --git a/include/configs/milkv_duo.h b/include/configs/milkv_duo.h
new file mode 100644
index 00..0b4109dc1f
--- /dev/null
+++ b/include/configs/milkv_duo.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CFG_SYS_SDRAM_BASE 0x8000
+
+#endif /* __CONFIG_H */
--
2.41.0
[PATCH v3 1/3] riscv: dts: sophgo: add basic device tree for Milk-V Duo board
Import device tree from Linux kernel to add basic support for CPU, PLIC,
UART and Timer. The name cv1800b in the filename represent the chip used
on Milk-V Duo board.
Signed-off-by: Kongyang Liu
---
Changes in v3:
- Swap patch 1 and 2 duo to dependency of defconfig and device tree
arch/riscv/dts/Makefile | 1 +
arch/riscv/dts/cv1800b-milkv-duo.dts | 38 +
arch/riscv/dts/cv1800b.dtsi | 123 +++
3 files changed, 162 insertions(+)
create mode 100644 arch/riscv/dts/cv1800b-milkv-duo.dts
create mode 100644 arch/riscv/dts/cv1800b.dtsi
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index b05bb5607f..17cda483e1 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,6 +2,7 @@
dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
diff --git a/arch/riscv/dts/cv1800b-milkv-duo.dts
b/arch/riscv/dts/cv1800b-milkv-duo.dts
new file mode 100644
index 00..3af9e34b3b
--- /dev/null
+++ b/arch/riscv/dts/cv1800b-milkv-duo.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang
+ */
+
+/dts-v1/;
+
+#include "cv1800b.dtsi"
+
+/ {
+ model = "Milk-V Duo";
+ compatible = "milkv,duo", "sophgo,cv1800b";
+
+ aliases {
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
+ serial4 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x8000 0x3f4>;
+ };
+};
+
+ {
+ clock-frequency = <2500>;
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/riscv/dts/cv1800b.dtsi b/arch/riscv/dts/cv1800b.dtsi
new file mode 100644
index 00..df40e87ee0
--- /dev/null
+++ b/arch/riscv/dts/cv1800b.dtsi
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang
+ */
+
+#include
+
+/ {
+ compatible = "sophgo,cv1800b";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <2500>;
+
+ cpu0: cpu@0 {
+ compatible = "thead,c906", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <65536>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ osc: oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "osc_25m";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-noncoherent;
+ ranges;
+
+ uart0: serial@414 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0414 0x100>;
+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart1: serial@415
[PATCH v3 0/3] riscv: sophgo: milkv_duo: add support for Milk-V Duo board
The Milk-V Duo board is built upon Sophgo's CV1800B SoC, featuring two XuanTie C906 CPUs running at 1.0GHz and 700MHz, respectively. This series introduces fundamental support for the Milk-V Duo board, encompassing UART, CPU, and PLIC support. This ensures that U-Boot can operate in serial console mode. Changes in v3: - Swap patch 1 and 2 duo to dependency of defconfig and device tree - Enable EFI loader - Add brief description of the procedure to run u-boot-dtb.bin Changes in v2: - Fold the defconfig patch to first patch - Remove unnecessary environment settings of consoledev and baudrate in config Kongyang Liu (3): riscv: dts: sophgo: add basic device tree for Milk-V Duo board riscv: sophgo: milkv_duo: initial support added doc: sophgo: milkv_duo: document Milk-V Duo board arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/cv1800b-milkv-duo.dts | 38 + arch/riscv/dts/cv1800b.dtsi | 123 +++ board/sophgo/milkv_duo/Kconfig | 28 ++ board/sophgo/milkv_duo/MAINTAINERS | 6 ++ board/sophgo/milkv_duo/Makefile | 5 ++ board/sophgo/milkv_duo/board.c | 9 ++ configs/milkv_duo_defconfig | 23 + doc/board/index.rst | 1 + doc/board/sophgo/index.rst | 8 ++ doc/board/sophgo/milkv_duo.rst | 64 ++ include/configs/milkv_duo.h | 12 +++ 13 files changed, 322 insertions(+) create mode 100644 arch/riscv/dts/cv1800b-milkv-duo.dts create mode 100644 arch/riscv/dts/cv1800b.dtsi create mode 100644 board/sophgo/milkv_duo/Kconfig create mode 100644 board/sophgo/milkv_duo/MAINTAINERS create mode 100644 board/sophgo/milkv_duo/Makefile create mode 100644 board/sophgo/milkv_duo/board.c create mode 100644 configs/milkv_duo_defconfig create mode 100644 doc/board/sophgo/index.rst create mode 100644 doc/board/sophgo/milkv_duo.rst create mode 100644 include/configs/milkv_duo.h -- 2.41.0
Re: [PATCH v2 3/3] doc: sophgo: milkv_duo: document Milk-V Duo board
Heinrich Schuchardt 于2024年1月15日周一 05:27写道： > > On 1/14/24 19:07, Kongyang Liu wrote: > > Add document for Milk-V Duo board which based on Sophgo's CV1800B SoC. > > > > Signed-off-by: Kongyang Liu > > --- > > > > (no changes since v1) > > > > doc/board/index.rst| 1 + > > doc/board/sophgo/index.rst | 8 ++ > > doc/board/sophgo/milkv_duo.rst | 50 ++ > > 3 files changed, 59 insertions(+) > > create mode 100644 doc/board/sophgo/index.rst > > create mode 100644 doc/board/sophgo/milkv_duo.rst > > > > diff --git a/doc/board/index.rst b/doc/board/index.rst > > index 531e547e7e..a0bd534742 100644 > > --- a/doc/board/index.rst > > +++ b/doc/board/index.rst > > @@ -45,6 +45,7 @@ Board-specific doc > > sifive/index > > sipeed/index > > socionext/index > > + sophgo/index > > st/index > > starfive/index > > ste/index > > diff --git a/doc/board/sophgo/index.rst b/doc/board/sophgo/index.rst > > new file mode 100644 > > index 00..e097afdac6 > > --- /dev/null > > +++ b/doc/board/sophgo/index.rst > > @@ -0,0 +1,8 @@ > > +.. SPDX-License-Identifier: GPL-2.0+ > > + > > +Sophgo > > +== > > +.. toctree:: > > + :maxdepth: 1 > > + > > + milkv_duo > > diff --git a/doc/board/sophgo/milkv_duo.rst b/doc/board/sophgo/milkv_duo.rst > > new file mode 100644 > > index 00..b63304b510 > > --- /dev/null > > +++ b/doc/board/sophgo/milkv_duo.rst > > @@ -0,0 +1,50 @@ > > +.. SPDX-License-Identifier: GPL-2.0+ > > + > > +Milk-V Duo > > +== > > + > > +CV1800B RISC-V SoC > > +-- > > +The CV1800B is a high-performance, low-power 1+1 64-bit RISC-V SoC from > > Sophgo. > > + > > +Mainline support > > + > > +The support for following drivers are already enabled: > > +1. ns16550 UART Driver. > > + > > +Building > > + > > +1. Add the RISC-V toolchain to your PATH. > > +2. Setup ARCH & cross compilation environment variable: > > + > > +.. code-block:: console > > + > > + export CROSS_COMPILE= > > + cd > > + make milkv_duo_defconfig > > + make > > + > > +This will generate u-boot-dtb.bin > > + > > +Booting > > +~~~ > > +Currently, we rely on vendor FSBL(First Stage Boot Loader) to initialize > > the > > +clock and load the u-boot image, then bootup from it. > > Thank you for providing documentation for the board. > > Could you please, additionally describe the procedure to run > u-boot-dtb.bin on top of FSBL. > I'd like to clarify your request for describing the procedure to run u-boot-dtb.bin on top of FSBL. Are you looking for a detailed, step-by-step guide to replicate the process and successfully run u-boot-dtb.bin, or would you prefer a more concise overview? Best regards Kongyang Liu > Best regards > > Heinrich > > > + > > +Sample boot log from Milk-V Duo board > > +~ > > +.. code-block:: none > > + > > + U-Boot 2024.01-rc5-00010-g51965baa36 (Dec 28 2023 - 13:15:53 > > +0800)milkv_duo > > + > > + DRAM: 63.3 MiB > > + Core: 10 devices, 8 uclasses, devicetree: separate > > + Loading Environment from nowhere... OK > > + In:serial@414 > > + Out: serial@414 > > + Err: serial@414 > > + Net: No ethernet found. > > + milkv_duo# cpu detail > > + 0: cpu@0 rv64imafdc > > + ID = 0, freq = 0 Hz: L1 cache, MMU > > + milkv_duo# >
Re: [PATCH v2 1/3] riscv: sophgo: milkv_duo: initial support added
Heinrich Schuchardt 于2024年1月15日周一 05:57写道： > > On 1/14/24 19:07, Kongyang Liu wrote: > > Add support for Sophgo's Milk-V Duo board, only minimal device tree and > > serial console are enabled, and it can boot via vendor first stage > > bootloader. > > > > Signed-off-by: Kongyang Liu > > The sequence of patches seems to be wrong. > > We expect that after each single patch building succeeds. But the > device-tree is neither in this patch nor in a preceding patch. Please, > swap patch 1 and 2. > > make[2]: *** No rule to make target > 'arch/riscv/dts/cv1800b-milkv-duo.dtb', needed by 'dtbs'. > > I forgot defconfig relies on dts files, I will swap patch 1 and 2. > > > > --- > > > > Changes in v2: > > - Fold the defconfig patch to first patch > > - Remove unnecessary environment settings of consoledev and baudrate in > > config > > > > arch/riscv/Kconfig | 4 > > board/sophgo/milkv_duo/Kconfig | 28 > > board/sophgo/milkv_duo/MAINTAINERS | 6 ++ > > board/sophgo/milkv_duo/Makefile| 5 + > > board/sophgo/milkv_duo/board.c | 9 + > > configs/milkv_duo_defconfig| 24 > > include/configs/milkv_duo.h| 12 > > 7 files changed, 88 insertions(+) > > create mode 100644 board/sophgo/milkv_duo/Kconfig > > create mode 100644 board/sophgo/milkv_duo/MAINTAINERS > > create mode 100644 board/sophgo/milkv_duo/Makefile > > create mode 100644 board/sophgo/milkv_duo/board.c > > create mode 100644 configs/milkv_duo_defconfig > > create mode 100644 include/configs/milkv_duo.h > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index 6d0d812ddb..de99ce3a28 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -14,6 +14,9 @@ config TARGET_ANDES_AE350 > > config TARGET_MICROCHIP_ICICLE > > bool "Support Microchip PolarFire-SoC Icicle Board" > > > > +config TARGET_MILKV_DUO > > + bool "Support Milk-v Duo Board" > > + > > config TARGET_OPENPITON_RISCV64 > > bool "Support RISC-V cores on OpenPiton SoC" > > > > @@ -80,6 +83,7 @@ source "board/openpiton/riscv64/Kconfig" > > source "board/sifive/unleashed/Kconfig" > > source "board/sifive/unmatched/Kconfig" > > source "board/sipeed/maix/Kconfig" > > +source "board/sophgo/milkv_duo/Kconfig" > > source "board/starfive/visionfive2/Kconfig" > > source "board/thead/th1520_lpi4a/Kconfig" > > error: patch failed: arch/riscv/Kconfig:80 > > Please, rebase. > > I will rebase it. > > > > diff --git a/board/sophgo/milkv_duo/Kconfig b/board/sophgo/milkv_duo/Kconfig > > new file mode 100644 > > index 00..2a458f291c > > --- /dev/null > > +++ b/board/sophgo/milkv_duo/Kconfig > > @@ -0,0 +1,28 @@ > > +if TARGET_MILKV_DUO > > + > > +config SYS_BOARD > > + default "milkv_duo" > > + > > +config SYS_VENDOR > > + default "sophgo" > > + > > +config SYS_CPU > > + default "generic" > > + > > +config SYS_CONFIG_NAME > > + default "milkv_duo" > > + > > +config TEXT_BASE > > + default 0x8020 > > + > > +config ENV_SIZE > > + default 0x2 > > + > > +config ENV_SECT_SIZE > > + default 0x4 > > + > > +config BOARD_SPECIFIC_OPTIONS > > + def_bool y > > + select GENERIC_RISCV > > + > > +endif > > diff --git a/board/sophgo/milkv_duo/MAINTAINERS > > b/board/sophgo/milkv_duo/MAINTAINERS > > new file mode 100644 > > index 00..651a0592f7 > > --- /dev/null > > +++ b/board/sophgo/milkv_duo/MAINTAINERS > > @@ -0,0 +1,6 @@ > > +Milk-V Duo > > +M: Kongyang Liu > > +S: Maintained > > +F: board/sophgo/milkv_duo/ > > +F: configs/milkv_duo_defconfig > > +F: doc/board/sophgo/milkv_duo.rst > > diff --git a/board/sophgo/milkv_duo/Makefile > > b/board/sophgo/milkv_duo/Makefile > > new file mode 100644 > > index 00..a087013f5c > > --- /dev/null > > +++ b/board/sophgo/milkv_duo/Makefile > > @@ -0,0 +1,5 @@ > > +# SPDX-License-Identifier: GPL-2.0+ > > +# > > +# Copyright (c) 2024, Kongyang Liu > > + > > +obj-y := board.o > > diff --git a/board/sophgo/milkv_duo/board.c b/board/sophgo/milkv_duo
[PATCH v2 3/3] doc: sophgo: milkv_duo: document Milk-V Duo board
Add document for Milk-V Duo board which based on Sophgo's CV1800B SoC. Signed-off-by: Kongyang Liu --- (no changes since v1) doc/board/index.rst| 1 + doc/board/sophgo/index.rst | 8 ++ doc/board/sophgo/milkv_duo.rst | 50 ++ 3 files changed, 59 insertions(+) create mode 100644 doc/board/sophgo/index.rst create mode 100644 doc/board/sophgo/milkv_duo.rst diff --git a/doc/board/index.rst b/doc/board/index.rst index 531e547e7e..a0bd534742 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -45,6 +45,7 @@ Board-specific doc sifive/index sipeed/index socionext/index + sophgo/index st/index starfive/index ste/index diff --git a/doc/board/sophgo/index.rst b/doc/board/sophgo/index.rst new file mode 100644 index 00..e097afdac6 --- /dev/null +++ b/doc/board/sophgo/index.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Sophgo +== +.. toctree:: + :maxdepth: 1 + + milkv_duo diff --git a/doc/board/sophgo/milkv_duo.rst b/doc/board/sophgo/milkv_duo.rst new file mode 100644 index 00..b63304b510 --- /dev/null +++ b/doc/board/sophgo/milkv_duo.rst @@ -0,0 +1,50 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Milk-V Duo +== + +CV1800B RISC-V SoC +-- +The CV1800B is a high-performance, low-power 1+1 64-bit RISC-V SoC from Sophgo. + +Mainline support + +The support for following drivers are already enabled: +1. ns16550 UART Driver. + +Building + +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: console + + export CROSS_COMPILE= + cd + make milkv_duo_defconfig + make + +This will generate u-boot-dtb.bin + +Booting +~~~ +Currently, we rely on vendor FSBL(First Stage Boot Loader) to initialize the +clock and load the u-boot image, then bootup from it. + +Sample boot log from Milk-V Duo board +~ +.. code-block:: none + + U-Boot 2024.01-rc5-00010-g51965baa36 (Dec 28 2023 - 13:15:53 +0800)milkv_duo + + DRAM: 63.3 MiB + Core: 10 devices, 8 uclasses, devicetree: separate + Loading Environment from nowhere... OK + In:serial@414 + Out: serial@414 + Err: serial@414 + Net: No ethernet found. + milkv_duo# cpu detail + 0: cpu@0 rv64imafdc + ID = 0, freq = 0 Hz: L1 cache, MMU + milkv_duo# -- 2.41.0
[PATCH v2 2/3] riscv: dts: sophgo: Add basic device tree for Milk-V Duo board
Import device tree from Linux kernel to add basic support for CPU, PLIC,
UART and Timer. The name cv1800b in the filename represent the chip used
on Milk-V Duo board.
Signed-off-by: Kongyang Liu
---
(no changes since v1)
arch/riscv/dts/Makefile | 1 +
arch/riscv/dts/cv1800b-milkv-duo.dts | 38 +
arch/riscv/dts/cv1800b.dtsi | 123 +++
3 files changed, 162 insertions(+)
create mode 100644 arch/riscv/dts/cv1800b-milkv-duo.dts
create mode 100644 arch/riscv/dts/cv1800b.dtsi
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index be6c8a4227..b9e1678676 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,6 +2,7 @@
dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
diff --git a/arch/riscv/dts/cv1800b-milkv-duo.dts
b/arch/riscv/dts/cv1800b-milkv-duo.dts
new file mode 100644
index 00..3af9e34b3b
--- /dev/null
+++ b/arch/riscv/dts/cv1800b-milkv-duo.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang
+ */
+
+/dts-v1/;
+
+#include "cv1800b.dtsi"
+
+/ {
+ model = "Milk-V Duo";
+ compatible = "milkv,duo", "sophgo,cv1800b";
+
+ aliases {
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
+ serial4 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x8000 0x3f4>;
+ };
+};
+
+ {
+ clock-frequency = <2500>;
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/riscv/dts/cv1800b.dtsi b/arch/riscv/dts/cv1800b.dtsi
new file mode 100644
index 00..df40e87ee0
--- /dev/null
+++ b/arch/riscv/dts/cv1800b.dtsi
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang
+ */
+
+#include
+
+/ {
+ compatible = "sophgo,cv1800b";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <2500>;
+
+ cpu0: cpu@0 {
+ compatible = "thead,c906", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <65536>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ osc: oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "osc_25m";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-noncoherent;
+ ranges;
+
+ uart0: serial@414 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0414 0x100>;
+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart1: serial@415 {
+ compatible = "snps,dw-a
[PATCH v2 1/3] riscv: sophgo: milkv_duo: initial support added
Add support for Sophgo's Milk-V Duo board, only minimal device tree and
serial console are enabled, and it can boot via vendor first stage
bootloader.
Signed-off-by: Kongyang Liu
---
Changes in v2:
- Fold the defconfig patch to first patch
- Remove unnecessary environment settings of consoledev and baudrate in
config
arch/riscv/Kconfig | 4
board/sophgo/milkv_duo/Kconfig | 28
board/sophgo/milkv_duo/MAINTAINERS | 6 ++
board/sophgo/milkv_duo/Makefile| 5 +
board/sophgo/milkv_duo/board.c | 9 +
configs/milkv_duo_defconfig| 24
include/configs/milkv_duo.h| 12
7 files changed, 88 insertions(+)
create mode 100644 board/sophgo/milkv_duo/Kconfig
create mode 100644 board/sophgo/milkv_duo/MAINTAINERS
create mode 100644 board/sophgo/milkv_duo/Makefile
create mode 100644 board/sophgo/milkv_duo/board.c
create mode 100644 configs/milkv_duo_defconfig
create mode 100644 include/configs/milkv_duo.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6d0d812ddb..de99ce3a28 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -14,6 +14,9 @@ config TARGET_ANDES_AE350
config TARGET_MICROCHIP_ICICLE
bool "Support Microchip PolarFire-SoC Icicle Board"
+config TARGET_MILKV_DUO
+ bool "Support Milk-v Duo Board"
+
config TARGET_OPENPITON_RISCV64
bool "Support RISC-V cores on OpenPiton SoC"
@@ -80,6 +83,7 @@ source "board/openpiton/riscv64/Kconfig"
source "board/sifive/unleashed/Kconfig"
source "board/sifive/unmatched/Kconfig"
source "board/sipeed/maix/Kconfig"
+source "board/sophgo/milkv_duo/Kconfig"
source "board/starfive/visionfive2/Kconfig"
source "board/thead/th1520_lpi4a/Kconfig"
diff --git a/board/sophgo/milkv_duo/Kconfig b/board/sophgo/milkv_duo/Kconfig
new file mode 100644
index 00..2a458f291c
--- /dev/null
+++ b/board/sophgo/milkv_duo/Kconfig
@@ -0,0 +1,28 @@
+if TARGET_MILKV_DUO
+
+config SYS_BOARD
+ default "milkv_duo"
+
+config SYS_VENDOR
+ default "sophgo"
+
+config SYS_CPU
+ default "generic"
+
+config SYS_CONFIG_NAME
+ default "milkv_duo"
+
+config TEXT_BASE
+ default 0x8020
+
+config ENV_SIZE
+ default 0x2
+
+config ENV_SECT_SIZE
+ default 0x4
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select GENERIC_RISCV
+
+endif
diff --git a/board/sophgo/milkv_duo/MAINTAINERS
b/board/sophgo/milkv_duo/MAINTAINERS
new file mode 100644
index 00..651a0592f7
--- /dev/null
+++ b/board/sophgo/milkv_duo/MAINTAINERS
@@ -0,0 +1,6 @@
+Milk-V Duo
+M: Kongyang Liu
+S: Maintained
+F: board/sophgo/milkv_duo/
+F: configs/milkv_duo_defconfig
+F: doc/board/sophgo/milkv_duo.rst
diff --git a/board/sophgo/milkv_duo/Makefile b/board/sophgo/milkv_duo/Makefile
new file mode 100644
index 00..a087013f5c
--- /dev/null
+++ b/board/sophgo/milkv_duo/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu
+
+obj-y := board.o
diff --git a/board/sophgo/milkv_duo/board.c b/board/sophgo/milkv_duo/board.c
new file mode 100644
index 00..eaa47be173
--- /dev/null
+++ b/board/sophgo/milkv_duo/board.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ */
+
+int board_init(void)
+{
+ return 0;
+}
diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig
new file mode 100644
index 00..c4782639ef
--- /dev/null
+++ b/configs/milkv_duo_defconfig
@@ -0,0 +1,24 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x82
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8230
+CONFIG_DEFAULT_DEVICE_TREE="cv1800b-milkv-duo"
+CONFIG_IDENT_STRING="milkv_duo"
+CONFIG_SYS_LOAD_ADDR=0x8008
+CONFIG_TARGET_MILKV_DUO=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_FIT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="milkv_duo# "
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=544
+CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/milkv_duo.h b/include/configs/milkv_duo.h
new file mode 100644
index 00..0b4109dc1f
--- /dev/null
+++ b/include/configs/milkv_duo.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CFG_SYS_SDRAM_BASE 0x8000
+
+#endif /* __CONFIG_H */
--
2.41.0
[PATCH v2 0/3] riscv: sophgo: milkv_duo: add support for Milk-V Duo board
The Milk-V Duo board is built upon Sophgo's CV1800B SoC, featuring two XuanTie C906 CPUs running at 1.0GHz and 700MHz, respectively. This series introduces fundamental support for the Milk-V Duo board, encompassing UART, CPU, and PLIC support. This ensures that U-Boot can operate in serial console mode. Changes in v2: - Fold the defconfig patch to first patch - Remove unnecessary environment settings of consoledev and baudrate in config Kongyang Liu (3): riscv: sophgo: milkv_duo: initial support added riscv: dts: sophgo: Add basic device tree for Milk-V Duo board doc: sophgo: milkv_duo: document Milk-V Duo board arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/cv1800b-milkv-duo.dts | 38 + arch/riscv/dts/cv1800b.dtsi | 123 +++ board/sophgo/milkv_duo/Kconfig | 28 ++ board/sophgo/milkv_duo/MAINTAINERS | 6 ++ board/sophgo/milkv_duo/Makefile | 5 ++ board/sophgo/milkv_duo/board.c | 9 ++ configs/milkv_duo_defconfig | 24 ++ doc/board/index.rst | 1 + doc/board/sophgo/index.rst | 8 ++ doc/board/sophgo/milkv_duo.rst | 50 +++ include/configs/milkv_duo.h | 12 +++ 13 files changed, 309 insertions(+) create mode 100644 arch/riscv/dts/cv1800b-milkv-duo.dts create mode 100644 arch/riscv/dts/cv1800b.dtsi create mode 100644 board/sophgo/milkv_duo/Kconfig create mode 100644 board/sophgo/milkv_duo/MAINTAINERS create mode 100644 board/sophgo/milkv_duo/Makefile create mode 100644 board/sophgo/milkv_duo/board.c create mode 100644 configs/milkv_duo_defconfig create mode 100644 doc/board/sophgo/index.rst create mode 100644 doc/board/sophgo/milkv_duo.rst create mode 100644 include/configs/milkv_duo.h -- 2.41.0
[PATCH 4/4] doc: sophgo: milkv_duo: document Milk-V Duo board
Add document for Milk-V Duo board which based on Sophgo's CV1800B SoC. Signed-off-by: Kongyang Liu --- doc/board/index.rst| 1 + doc/board/sophgo/index.rst | 8 ++ doc/board/sophgo/milkv_duo.rst | 50 ++ 3 files changed, 59 insertions(+) create mode 100644 doc/board/sophgo/index.rst create mode 100644 doc/board/sophgo/milkv_duo.rst diff --git a/doc/board/index.rst b/doc/board/index.rst index 531e547e7e..a0bd534742 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -45,6 +45,7 @@ Board-specific doc sifive/index sipeed/index socionext/index + sophgo/index st/index starfive/index ste/index diff --git a/doc/board/sophgo/index.rst b/doc/board/sophgo/index.rst new file mode 100644 index 00..e097afdac6 --- /dev/null +++ b/doc/board/sophgo/index.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Sophgo +== +.. toctree:: + :maxdepth: 1 + + milkv_duo diff --git a/doc/board/sophgo/milkv_duo.rst b/doc/board/sophgo/milkv_duo.rst new file mode 100644 index 00..b63304b510 --- /dev/null +++ b/doc/board/sophgo/milkv_duo.rst @@ -0,0 +1,50 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Milk-V Duo +== + +CV1800B RISC-V SoC +-- +The CV1800B is a high-performance, low-power 1+1 64-bit RISC-V SoC from Sophgo. + +Mainline support + +The support for following drivers are already enabled: +1. ns16550 UART Driver. + +Building + +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: console + + export CROSS_COMPILE= + cd + make milkv_duo_defconfig + make + +This will generate u-boot-dtb.bin + +Booting +~~~ +Currently, we rely on vendor FSBL(First Stage Boot Loader) to initialize the +clock and load the u-boot image, then bootup from it. + +Sample boot log from Milk-V Duo board +~ +.. code-block:: none + + U-Boot 2024.01-rc5-00010-g51965baa36 (Dec 28 2023 - 13:15:53 +0800)milkv_duo + + DRAM: 63.3 MiB + Core: 10 devices, 8 uclasses, devicetree: separate + Loading Environment from nowhere... OK + In:serial@414 + Out: serial@414 + Err: serial@414 + Net: No ethernet found. + milkv_duo# cpu detail + 0: cpu@0 rv64imafdc + ID = 0, freq = 0 Hz: L1 cache, MMU + milkv_duo# -- 2.41.0
[PATCH 3/4] configs: milkv_duo_defconfig: Add initial config
Add basic config for Milk-V Duo board which make it capable of booting into serial console. Signed-off-by: Kongyang Liu --- configs/milkv_duo_defconfig | 24 1 file changed, 24 insertions(+) create mode 100644 configs/milkv_duo_defconfig diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig new file mode 100644 index 00..c4782639ef --- /dev/null +++ b/configs/milkv_duo_defconfig @@ -0,0 +1,24 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_LEN=0x82 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8230 +CONFIG_DEFAULT_DEVICE_TREE="cv1800b-milkv-duo" +CONFIG_IDENT_STRING="milkv_duo" +CONFIG_SYS_LOAD_ADDR=0x8008 +CONFIG_TARGET_MILKV_DUO=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_FIT=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="milkv_duo# " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=544 +CONFIG_SYS_BOOTM_LEN=0x400 +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y +# CONFIG_EFI_LOADER is not set -- 2.41.0
[PATCH 2/4] riscv: dts: sophgo: Add basic device tree for Milk-V Duo board
Import device tree from Linux kernel to add basic support for CPU, PLIC,
UART and Timer. The name cv1800b in the filename represent the chip used
on Milk-V Duo board.
Signed-off-by: Kongyang Liu
---
arch/riscv/dts/Makefile | 1 +
arch/riscv/dts/cv1800b-milkv-duo.dts | 38 +
arch/riscv/dts/cv1800b.dtsi | 123 +++
3 files changed, 162 insertions(+)
create mode 100644 arch/riscv/dts/cv1800b-milkv-duo.dts
create mode 100644 arch/riscv/dts/cv1800b.dtsi
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index be6c8a4227..b9e1678676 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,6 +2,7 @@
dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
diff --git a/arch/riscv/dts/cv1800b-milkv-duo.dts
b/arch/riscv/dts/cv1800b-milkv-duo.dts
new file mode 100644
index 00..3af9e34b3b
--- /dev/null
+++ b/arch/riscv/dts/cv1800b-milkv-duo.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang
+ */
+
+/dts-v1/;
+
+#include "cv1800b.dtsi"
+
+/ {
+ model = "Milk-V Duo";
+ compatible = "milkv,duo", "sophgo,cv1800b";
+
+ aliases {
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
+ serial4 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x8000 0x3f4>;
+ };
+};
+
+ {
+ clock-frequency = <2500>;
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/riscv/dts/cv1800b.dtsi b/arch/riscv/dts/cv1800b.dtsi
new file mode 100644
index 00..df40e87ee0
--- /dev/null
+++ b/arch/riscv/dts/cv1800b.dtsi
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang
+ */
+
+#include
+
+/ {
+ compatible = "sophgo,cv1800b";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <2500>;
+
+ cpu0: cpu@0 {
+ compatible = "thead,c906", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <65536>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ osc: oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "osc_25m";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-noncoherent;
+ ranges;
+
+ uart0: serial@414 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0414 0x100>;
+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart1: serial@415 {
+ compatible = "snps,dw-a
[PATCH 1/4] riscv: sophgo: milkv_duo: initial support added
Add support for Sophgo's Milk-V Duo board, only minimal device tree and
serial console are enabled, and it can boot via vendor first stage
bootloader.
Signed-off-by: Kongyang Liu
---
arch/riscv/Kconfig | 4
board/sophgo/milkv_duo/Kconfig | 28
board/sophgo/milkv_duo/MAINTAINERS | 6 ++
board/sophgo/milkv_duo/Makefile| 5 +
board/sophgo/milkv_duo/board.c | 9 +
include/configs/milkv_duo.h| 16
6 files changed, 68 insertions(+)
create mode 100644 board/sophgo/milkv_duo/Kconfig
create mode 100644 board/sophgo/milkv_duo/MAINTAINERS
create mode 100644 board/sophgo/milkv_duo/Makefile
create mode 100644 board/sophgo/milkv_duo/board.c
create mode 100644 include/configs/milkv_duo.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6d0d812ddb..de99ce3a28 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -14,6 +14,9 @@ config TARGET_ANDES_AE350
config TARGET_MICROCHIP_ICICLE
bool "Support Microchip PolarFire-SoC Icicle Board"
+config TARGET_MILKV_DUO
+ bool "Support Milk-v Duo Board"
+
config TARGET_OPENPITON_RISCV64
bool "Support RISC-V cores on OpenPiton SoC"
@@ -80,6 +83,7 @@ source "board/openpiton/riscv64/Kconfig"
source "board/sifive/unleashed/Kconfig"
source "board/sifive/unmatched/Kconfig"
source "board/sipeed/maix/Kconfig"
+source "board/sophgo/milkv_duo/Kconfig"
source "board/starfive/visionfive2/Kconfig"
source "board/thead/th1520_lpi4a/Kconfig"
diff --git a/board/sophgo/milkv_duo/Kconfig b/board/sophgo/milkv_duo/Kconfig
new file mode 100644
index 00..2a458f291c
--- /dev/null
+++ b/board/sophgo/milkv_duo/Kconfig
@@ -0,0 +1,28 @@
+if TARGET_MILKV_DUO
+
+config SYS_BOARD
+ default "milkv_duo"
+
+config SYS_VENDOR
+ default "sophgo"
+
+config SYS_CPU
+ default "generic"
+
+config SYS_CONFIG_NAME
+ default "milkv_duo"
+
+config TEXT_BASE
+ default 0x8020
+
+config ENV_SIZE
+ default 0x2
+
+config ENV_SECT_SIZE
+ default 0x4
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select GENERIC_RISCV
+
+endif
diff --git a/board/sophgo/milkv_duo/MAINTAINERS
b/board/sophgo/milkv_duo/MAINTAINERS
new file mode 100644
index 00..651a0592f7
--- /dev/null
+++ b/board/sophgo/milkv_duo/MAINTAINERS
@@ -0,0 +1,6 @@
+Milk-V Duo
+M: Kongyang Liu
+S: Maintained
+F: board/sophgo/milkv_duo/
+F: configs/milkv_duo_defconfig
+F: doc/board/sophgo/milkv_duo.rst
diff --git a/board/sophgo/milkv_duo/Makefile b/board/sophgo/milkv_duo/Makefile
new file mode 100644
index 00..a087013f5c
--- /dev/null
+++ b/board/sophgo/milkv_duo/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu
+
+obj-y := board.o
diff --git a/board/sophgo/milkv_duo/board.c b/board/sophgo/milkv_duo/board.c
new file mode 100644
index 00..eaa47be173
--- /dev/null
+++ b/board/sophgo/milkv_duo/board.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ */
+
+int board_init(void)
+{
+ return 0;
+}
diff --git a/include/configs/milkv_duo.h b/include/configs/milkv_duo.h
new file mode 100644
index 00..dd1d146c50
--- /dev/null
+++ b/include/configs/milkv_duo.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CFG_SYS_SDRAM_BASE 0x8000
+
+#define CFG_EXTRA_ENV_SETTINGS \
+ "consoledev=ttyS0" \
+ "baudrate=115200\0"\
+
+#endif /* __CONFIG_H */
--
2.41.0
[PATCH 0/4] riscv: sophgo: milkv_duo: add support for Milk-V Duo board
The Milk-V Duo board is built upon Sophgo's CV1800B SoC, featuring two XuanTie C906 CPUs running at 1.0GHz and 700MHz, respectively. This series introduces fundamental support for the Milk-V Duo board, encompassing UART, CPU, and PLIC support. This ensures that U-Boot can operate in serial console mode. Kongyang Liu (4): riscv: sophgo: milkv_duo: initial support added riscv: dts: sophgo: Add basic device tree for Milk-V Duo board configs: milkv_duo_defconfig: Add initial config doc: sophgo: milkv_duo: document Milk-V Duo board arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/cv1800b-milkv-duo.dts | 38 + arch/riscv/dts/cv1800b.dtsi | 123 +++ board/sophgo/milkv_duo/Kconfig | 28 ++ board/sophgo/milkv_duo/MAINTAINERS | 6 ++ board/sophgo/milkv_duo/Makefile | 5 ++ board/sophgo/milkv_duo/board.c | 9 ++ configs/milkv_duo_defconfig | 24 ++ doc/board/index.rst | 1 + doc/board/sophgo/index.rst | 8 ++ doc/board/sophgo/milkv_duo.rst | 50 +++ include/configs/milkv_duo.h | 16 13 files changed, 313 insertions(+) create mode 100644 arch/riscv/dts/cv1800b-milkv-duo.dts create mode 100644 arch/riscv/dts/cv1800b.dtsi create mode 100644 board/sophgo/milkv_duo/Kconfig create mode 100644 board/sophgo/milkv_duo/MAINTAINERS create mode 100644 board/sophgo/milkv_duo/Makefile create mode 100644 board/sophgo/milkv_duo/board.c create mode 100644 configs/milkv_duo_defconfig create mode 100644 doc/board/sophgo/index.rst create mode 100644 doc/board/sophgo/milkv_duo.rst create mode 100644 include/configs/milkv_duo.h -- 2.41.0
