[PATCH] mips: vcoreiii: Fix cache coherency issues
This patch fixes an stability issue seen on some vcoreiii targets,
which was root caused to a cache inconsistency situation.
The inconsistency was caused by having kuseg pointing to NOR area but
used as a stack/gd/heap area during initialization, while only
relatively late remapping the RAM area into kuseg position.
The fix is to initialize the DDR right after the TLB setup, and then
remapping it into position before gd/stack/heap usage.
Reported-by: Ramin Seyed-Moussavi
Reviewed-by: Alexandre Belloni
Reviewed-by: Horatiu Vultur
Signed-off-by: Lars Povlsen
---
arch/mips/mach-mscc/cpu.c | 9 +
arch/mips/mach-mscc/dram.c | 14 +-
arch/mips/mach-mscc/include/mach/ddr.h | 4
arch/mips/mach-mscc/lowlevel_init.S| 17 -
4 files changed, 26 insertions(+), 18 deletions(-)
diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c
index ac75d51da5..3ee589891b 100644
--- a/arch/mips/mach-mscc/cpu.c
+++ b/arch/mips/mach-mscc/cpu.c
@@ -7,6 +7,7 @@
#include
#include
+#include
#include
#include
@@ -53,7 +54,6 @@ void vcoreiii_tlb_init(void)
MMU_REGIO_RW);
#endif
-#if CONFIG_SYS_TEXT_BASE == MSCC_FLASH_TO
/*
* If U-Boot is located in NOR then we want to be able to use
* the data cache in order to boot in a decent duration
@@ -71,9 +71,10 @@ void vcoreiii_tlb_init(void)
create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW,
MSCC_ATTRIB2);
- /* Enable caches by clearing the bit ERL, which is set on reset */
- write_c0_status(read_c0_status() & ~BIT(2));
-#endif /* CONFIG_SYS_TEXT_BASE */
+ /* Enable mapping (using TLB) kuseg by clearing the bit ERL,
+* which is set on reset.
+*/
+ write_c0_status(read_c0_status() & ~ST0_ERL);
}
int mach_cpu_init(void)
diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c
index c43f7a585b..72c70c9e84 100644
--- a/arch/mips/mach-mscc/dram.c
+++ b/arch/mips/mach-mscc/dram.c
@@ -31,7 +31,7 @@ static inline int vcoreiii_train_bytelane(void)
int vcoreiii_ddr_init(void)
{
- int res;
+ register int res;
if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT)
& ICPU_MEMCTRL_STAT_INIT_DONE)) {
@@ -40,20 +40,19 @@ int vcoreiii_ddr_init(void)
if (hal_vcoreiii_init_dqs() || vcoreiii_train_bytelane())
hal_vcoreiii_ddr_failed();
}
-#if (CONFIG_SYS_TEXT_BASE != 0x2000)
+
res = dram_check();
if (res == 0)
hal_vcoreiii_ddr_verified();
else
hal_vcoreiii_ddr_failed();
- /* Clear boot-mode and read-back to activate/verify */
+ /* Remap DDR to kuseg: Clear boot-mode */
clrbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
ICPU_GENERAL_CTRL_BOOT_MODE_ENA);
+ /* - and read-back to activate/verify */
readl(BASE_CFG + ICPU_GENERAL_CTRL);
-#else
- res = 0;
-#endif
+
return res;
}
@@ -66,9 +65,6 @@ int print_cpuinfo(void)
int dram_init(void)
{
- while (vcoreiii_ddr_init())
- ;
-
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h
b/arch/mips/mach-mscc/include/mach/ddr.h
index d1f4287f65..bf75e52ec3 100644
--- a/arch/mips/mach-mscc/include/mach/ddr.h
+++ b/arch/mips/mach-mscc/include/mach/ddr.h
@@ -435,16 +435,12 @@ static inline void hal_vcoreiii_ddr_failed(void)
reset = KSEG0ADDR(_machine_restart);
icache_lock((void *)reset, 128);
asm volatile ("jr %0"::"r" (reset));
-
- panic("DDR init failed\n");
}
#else /* JR2 || ServalT */
static inline void hal_vcoreiii_ddr_failed(void)
{
writel(0, BASE_CFG + ICPU_RESET);
writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST);
-
- panic("DDR init failed\n");
}
#endif
diff --git a/arch/mips/mach-mscc/lowlevel_init.S
b/arch/mips/mach-mscc/lowlevel_init.S
index dfbe06766c..91f29ae252 100644
--- a/arch/mips/mach-mscc/lowlevel_init.S
+++ b/arch/mips/mach-mscc/lowlevel_init.S
@@ -8,6 +8,7 @@
.set noreorder
.extern vcoreiii_tlb_init
+.extern vcoreiii_ddr_init
#ifdef CONFIG_SOC_LUTON
.extern pll_init
#endif
@@ -17,14 +18,28 @@ LEAF(lowlevel_init)
* As we have no stack yet, we can assume the restricted
* luxury of the sX-registers without saving them
*/
- moves0,ra
+
+ /* Modify ra/s0 such we return to physical NOR location */
+ li t0, 0x0fff
+ li t1, CONFIG_SYS_TEXT_BASE
+ and s0, ra, t0
+ add s0, s0, t1
jal vcoreiii_tlb_init
nop
+
#ifdef CONFIG_SOC_LUTON
jal pll_init
nop
#endif
+
+ /* Initialize DDR controller to enable stack/gd/hea
[PATCH] mips: vcoreiii: Ajust CONFIG_SYS_MEMTEST_END
This patch ajust CONFIG_SYS_MEMTEST_END for vcoreiii-based systems to avoid overwriting the relocated u-boot. The former setting was too agressive with networking etc. enabled on some platforms. Reviewed-by: Alexandre Belloni Reviewed-by: Horatiu Vultur Signed-off-by: Lars Povlsen --- include/configs/vcoreiii.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index e69456ef7c..6a2f80c2fb 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -39,7 +39,8 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - SZ_1M) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + \ +CONFIG_SYS_SDRAM_SIZE - SZ_4M) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -- 2.23.0
[U-Boot] [RESEND PATCH] ARMv8: PSCI: Fix PSCI_TABLE relocation issue
This fixes relaction isses with the PSCI_TABLE entries in the psci_32_table and psci_64_table. When using 32-bit adress pointers relocation was not being applied to the tables, causing PSCI handlers to point to the un-relocated code area. By using 64-bit data relocation is properly applied. The handlers are thus in the "secure data" area, which is protected by /memreserve/ in the FDT. Signed-off-by: Lars Povlsen --- arch/arm/cpu/armv8/psci.S | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S index 358df8fee9..b4568cf053 100644 --- a/arch/arm/cpu/armv8/psci.S +++ b/arch/arm/cpu/armv8/psci.S @@ -19,8 +19,8 @@ /* PSCI function and ID table definition*/ #define PSCI_TABLE(__id, __fn) \ - .word __id; \ - .word __fn + .quad __id; \ + .quad __fn .pushsection ._secure.text, "ax" @@ -132,16 +132,15 @@ PSCI_TABLE(0, 0) /* Caller must put PSCI function-ID table base in x9 */ handle_psci: psci_enter -1: ldr x10, [x9] /* Load PSCI function table */ - ubfx x11, x10, #32, #32 - ubfx x10, x10, #0, #32 +1: ldr x10, [x9] /* Load PSCI function table */ cbz x10, 3f /* If reach the end, bail out */ cmp x10, x0 b.eq2f /* PSCI function found */ - add x9, x9, #8 /* If not match, try next entry */ + add x9, x9, #16 /* If not match, try next entry */ b 1b -2: blr x11 /* Call PSCI function */ +2: ldr x11, [x9, #8] /* Load PSCI function */ + blr x11 /* Call PSCI function */ psci_return 3: mov x0, #ARM_PSCI_RET_NI -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] ARMv8: PSCI: Fix PSCI_TABLE relocation issue
This fixes relaction isses with the PSCI_TABLE entries in the psci_32_table and psci_64_table. When using 32-bit adress pointers relocation was not being applied to the tables, causing PSCI handlers to point to the un-relocated code area. By using 64-bit data relocation is properly applied. The handlers are thus in the "secure data" area, which is protected by /memreserve/ in the FDT. Signed-off-by: Lars Povlsen --- arch/arm/cpu/armv8/psci.S | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S index 358df8fee9..b4568cf053 100644 --- a/arch/arm/cpu/armv8/psci.S +++ b/arch/arm/cpu/armv8/psci.S @@ -19,8 +19,8 @@ /* PSCI function and ID table definition*/ #define PSCI_TABLE(__id, __fn) \ - .word __id; \ - .word __fn + .quad __id; \ + .quad __fn .pushsection ._secure.text, "ax" @@ -132,16 +132,15 @@ PSCI_TABLE(0, 0) /* Caller must put PSCI function-ID table base in x9 */ handle_psci: psci_enter -1: ldr x10, [x9] /* Load PSCI function table */ - ubfx x11, x10, #32, #32 - ubfx x10, x10, #0, #32 +1: ldr x10, [x9] /* Load PSCI function table */ cbz x10, 3f /* If reach the end, bail out */ cmp x10, x0 b.eq2f /* PSCI function found */ - add x9, x9, #8 /* If not match, try next entry */ + add x9, x9, #16 /* If not match, try next entry */ b 1b -2: blr x11 /* Call PSCI function */ +2: ldr x11, [x9, #8] /* Load PSCI function */ + blr x11 /* Call PSCI function */ psci_return 3: mov x0, #ARM_PSCI_RET_NI -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 3/3] mips: gpio: mscc: Obsoleted gpio-mscc-bitbang-spi.c
With the new mscc_bb_spi.c driver, there is no longer use for the
gpio-mscc-bitbang-spi.c driver.
Signed-off-by: Lars Povlsen
Reviewed-by: Daniel Schwierzeck
---
drivers/gpio/Kconfig | 7 --
drivers/gpio/Makefile| 1 -
drivers/gpio/gpio-mscc-bitbang-spi.c | 122 ---
3 files changed, 130 deletions(-)
delete mode 100644 drivers/gpio/gpio-mscc-bitbang-spi.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index aa55ff43c4..14a14be917 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -99,13 +99,6 @@ config LPC32XX_GPIO
help
Support for the LPC32XX GPIO driver.
-config MSCC_BITBANG_SPI_GPIO
- bool "Microsemi bitbang spi GPIO driver"
- depends on DM_GPIO && SOC_VCOREIII
- help
- Support controlling the GPIO used for SPI bitbang by software. Can
- be used by the VCoreIII SoCs, but it was mainly useful for Luton.
-
config MSCC_SGPIO
bool "Microsemi Serial GPIO driver"
depends on DM_GPIO && SOC_VCOREIII
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index be2b3c792f..7c479efe2d 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -59,5 +59,4 @@ obj-$(CONFIG_MSM_GPIO)+= msm_gpio.o
obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o
obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o
-obj-$(CONFIG_MSCC_BITBANG_SPI_GPIO)+= gpio-mscc-bitbang-spi.o
obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o
diff --git a/drivers/gpio/gpio-mscc-bitbang-spi.c
b/drivers/gpio/gpio-mscc-bitbang-spi.c
deleted file mode 100644
index b675f9052c..00
--- a/drivers/gpio/gpio-mscc-bitbang-spi.c
+++ /dev/null
@@ -1,122 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Microsemi SoCs pinctrl driver
- *
- * Author:
- * License: Dual MIT/GPL
- * Copyright (c) 2018 Microsemi Corporation
- */
-
-#include
-#include
-#include
-#include
-#include
-
-enum {
- SDI,
- CS0,
- CS1,
- CS2,
- CS3,
- SDO,
- SCK
-};
-
-static const int pinmap[] = { 0, 5, 6, 7, 8, 10, 12 };
-
-#define SW_SPI_CSn_OE 0x1E /* bits 1 to 4 */
-#define SW_SPI_CS0_OE BIT(1)
-#define SW_SPI_SDO_OE BIT(9)
-#define SW_SPI_SCK_OE BIT(11)
-#define SW_PIN_CTRL_MODE BIT(13)
-
-struct mscc_bb_spi_gpio {
- void __iomem *regs;
- u32 cache_val;
-};
-
-static int mscc_bb_spi_gpio_set(struct udevice *dev, unsigned oft, int val)
-{
- struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
-
- if (val)
- gpio->cache_val |= BIT(pinmap[oft]);
- else
- gpio->cache_val &= ~BIT(pinmap[oft]);
-
- writel(gpio->cache_val, gpio->regs);
-
- return 0;
-}
-
-static int mscc_bb_spi_gpio_direction_output(struct udevice *dev, unsigned oft,
-int val)
-{
- if (oft == 0) {
- pr_err("SW_SPI_DSI can't be used as output\n");
- return -ENOTSUPP;
- }
-
- mscc_bb_spi_gpio_set(dev, oft, val);
-
- return 0;
-}
-
-static int mscc_bb_spi_gpio_direction_input(struct udevice *dev, unsigned oft)
-{
- return 0;
-}
-
-static int mscc_bb_spi_gpio_get(struct udevice *dev, unsigned int oft)
-{
- struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
- u32 val = readl(gpio->regs);
-
- return !!(val & BIT(pinmap[oft]));
-}
-
-static const struct dm_gpio_ops mscc_bb_spi_gpio_ops = {
- .direction_output = mscc_bb_spi_gpio_direction_output,
- .direction_input= mscc_bb_spi_gpio_direction_input,
- .set_value = mscc_bb_spi_gpio_set,
- .get_value = mscc_bb_spi_gpio_get,
-};
-
-static int mscc_bb_spi_gpio_probe(struct udevice *dev)
-{
- struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
- struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-
- gpio->regs = dev_remap_addr(dev);
- if (!gpio->regs)
- return -EINVAL;
-
- uc_priv->bank_name = dev->name;
- uc_priv->gpio_count = ARRAY_SIZE(pinmap);
- /*
-* Enable software mode to control the SPI pin, enables the
-* output mode for most of the pin and initialize the cache
-* value in the same time
-*/
-
- gpio->cache_val = SW_PIN_CTRL_MODE | SW_SPI_SCK_OE | SW_SPI_SDO_OE |
- SW_SPI_CS0_OE;
- writel(gpio->cache_val, gpio->regs);
-
- return 0;
-}
-
-static const struct udevice_id mscc_bb_spi_gpio_ids[] = {
- {.compatible = "mscc,spi-bitbang-gpio"},
- {}
-};
-
-U_BOOT_DRIVER(gpio_mscc_bb_spi) = {
- .name = "gpio-mscc-spi-bitbang",
- .id = UCLASS_GPIO,
- .ops= _bb_spi_gpio_ops,
- .probe = mscc_bb_spi_gpio_probe,
- .of_match = of
[U-Boot] [PATCH v3 2/3] mips: mscc: DT: Update luton device tree to use fast SPI driver
Thes patch change the luton base device tree to use the newly added
SPI bitbang driver.
It also updates the "mscc_luton_defconfig" to use the new driver.
Signed-off-by: Lars Povlsen
Reviewed-by: Daniel Schwierzeck
---
arch/mips/dts/mscc,luton.dtsi | 15 ++-
configs/mscc_luton_defconfig | 3 ++-
2 files changed, 4 insertions(+), 14 deletions(-)
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
index 87e27c6de5..d11ec4884d 100644
--- a/arch/mips/dts/mscc,luton.dtsi
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -84,21 +84,10 @@
gpio-ranges = < 0 0 64>;
};
- gpio_spi_bitbang: gpio@1064 {
- compatible = "mscc,spi-bitbang-gpio";
- reg = <0x1064 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
-
- };
-
spi0: spi-bitbang {
- compatible = "spi-gpio";
+ compatible = "mscc,luton-bb-spi";
status = "okay";
- gpio-sck = <_spi_bitbang 6 0>;
- gpio-miso = <_spi_bitbang 0 0>;
- gpio-mosi = <_spi_bitbang 5 0>;
- cs-gpios = <_spi_bitbang 1 0>;
+ reg = <0x1064 0x4>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig
index 65f0672c1e..d48a93a2a5 100644
--- a/configs/mscc_luton_defconfig
+++ b/configs/mscc_luton_defconfig
@@ -34,6 +34,7 @@ CONFIG_CMD_DHCP=y
# CONFIG_NET_TFTP_VARS is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:1m(UBoot),256k(Env),256k(Env.bk),512k(Unused),6m(linux)"
@@ -66,5 +67,5 @@ CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
-CONFIG_SOFT_SPI=y
+CONFIG_MSCC_BB_SPI=y
CONFIG_LZMA=y
--
2.19.2
___
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[U-Boot] [PATCH v3 1/3] mips: spi: mscc: Add fast bitbang SPI driver
This patch add a new SPI driver for MSCC SOCs that does not sport the
designware SPI hardware controller.
Performance gain: 7.664 seconds vs. 17.633 for 1 Mbyte write.
Signed-off-by: Lars Povlsen
Reviewed-by: Daniel Schwierzeck
---
MAINTAINERS | 1 +
arch/mips/mach-mscc/include/mach/common.h | 38
drivers/spi/Kconfig | 7 +
drivers/spi/Makefile | 1 +
drivers/spi/mscc_bb_spi.c | 236 ++
5 files changed, 283 insertions(+)
create mode 100644 drivers/spi/mscc_bb_spi.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 494962e9b3..0cee99ef56 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -524,6 +524,7 @@ F: arch/mips/dts/ocelot*
F: board/mscc/
F: configs/mscc*
F: drivers/gpio/mscc_sgpio.c
+F: drivers/spi/mscc_bb_spi.c
F: include/configs/vcoreiii.h
MIPS JZ4780
diff --git a/arch/mips/mach-mscc/include/mach/common.h
b/arch/mips/mach-mscc/include/mach/common.h
index d18ae78bfd..7765c060ed 100644
--- a/arch/mips/mach-mscc/include/mach/common.h
+++ b/arch/mips/mach-mscc/include/mach/common.h
@@ -29,6 +29,44 @@
/* Common utility functions */
+/*
+ * Perform a number of NOP instructions, blocks of 8 instructions.
+ * The (inlined) function will not affect cache or processor state.
+ */
+static inline void mscc_vcoreiii_nop_delay(int delay)
+{
+ while (delay > 0) {
+#define DELAY_8_NOPS() asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;")
+ switch (delay) {
+ case 8:
+ DELAY_8_NOPS();
+ /* fallthrough */
+ case 7:
+ DELAY_8_NOPS();
+ /* fallthrough */
+ case 6:
+ DELAY_8_NOPS();
+ /* fallthrough */
+ case 5:
+ DELAY_8_NOPS();
+ /* fallthrough */
+ case 4:
+ DELAY_8_NOPS();
+ /* fallthrough */
+ case 3:
+ DELAY_8_NOPS();
+ /* fallthrough */
+ case 2:
+ DELAY_8_NOPS();
+ /* fallthrough */
+ case 1:
+ DELAY_8_NOPS();
+ }
+ delay -= 8;
+#undef DELAY_8_NOPS
+ }
+}
+
int mscc_phy_rd_wr(u8 read,
u32 miim_controller,
u8 miim_addr,
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a7bb5b35c2..de4d62dd8f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -294,6 +294,13 @@ config SOFT_SPI
Enable Soft SPI driver. This driver is to use GPIO simulate
the SPI protocol.
+config MSCC_BB_SPI
+ bool "MSCC bitbang SPI driver"
+ depends on SOC_VCOREIII
+ help
+ Enable MSCC bitbang SPI driver. This driver can be used on
+ MSCC SOCs.
+
config CF_SPI
bool "ColdFire SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 392a925795..4acec3ea17 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MTK_QSPI) += mtk_qspi.o
obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
+obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
obj-$(CONFIG_MXS_SPI) += mxs_spi.o
diff --git a/drivers/spi/mscc_bb_spi.c b/drivers/spi/mscc_bb_spi.c
new file mode 100644
index 00..c3c7b80426
--- /dev/null
+++ b/drivers/spi/mscc_bb_spi.c
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs spi driver
+ *
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct mscc_bb_priv {
+ void __iomem *regs;
+ u32 deactivate_delay_us;
+ bool cs_active; /* State flag as to whether CS is asserted */
+ int cs_num;
+ u32 svalue; /* Value to start transfer with */
+ u32 clk1; /* Clock value start */
+ u32 clk2; /* Clock value 2nd phase */
+};
+
+/* Delay 24 instructions for this particular application */
+#define hold_time_delay() mscc_vcoreiii_nop_delay(3)
+
+static int mscc_bb_spi_cs_activate(struct mscc_bb_priv *priv, int mode, int cs)
+{
+ if (!priv->cs_active) {
+ int cpha = mode & SPI_CPHA;
+ u32 cs_value;
+
+ priv->cs_num = cs;
+
+ if (cpha) {
+ /* Initial clock starts SCK=1 */
+ priv->clk1 = ICPU_SW_MODE_SW_SPI_SCK;
+ priv->clk2 = 0;
+ } else {
+
[U-Boot] [PATCH v3 0/3] mips: spi: mscc: Add fast bitbang SPI driver
These 3 patches add an optimized SPI bitbang driver for MSCC SOCs that does not sport the designware SPI hardware controller. The driver more than doubles the performance for bulk SPI transfers. This is based off the u-boot-mips/next repository. v3 changes: - Dropped .ofdata_to_platdata support (DT only) v2 changes: - Moved lowlevel delay stuff into arch common header file - remove superfluous license and DECLARE_GLOBAL_DATA_PTR - Moved defconfig changes to DT patch - Removed obsoleted gpio-mscc-bitbang-spi driver Lars Povlsen (3): mips: spi: mscc: Add fast bitbang SPI driver mips: mscc: DT: Update luton device tree to use fast SPI driver mips: gpio: mscc: Obsoleted gpio-mscc-bitbang-spi.c MAINTAINERS | 1 + arch/mips/dts/mscc,luton.dtsi | 15 +- arch/mips/mach-mscc/include/mach/common.h | 38 configs/mscc_luton_defconfig | 3 +- drivers/gpio/Kconfig | 7 - drivers/gpio/Makefile | 1 - drivers/gpio/gpio-mscc-bitbang-spi.c | 122 --- drivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/mscc_bb_spi.c | 236 ++ 10 files changed, 287 insertions(+), 144 deletions(-) delete mode 100644 drivers/gpio/gpio-mscc-bitbang-spi.c create mode 100644 drivers/spi/mscc_bb_spi.c -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 3/3] mips: gpio: mscc: Obsoleted gpio-mscc-bitbang-spi.c
With the new mscc_bb_spi.c driver, there is no longer use for the
gpio-mscc-bitbang-spi.c driver.
Signed-off-by: Lars Povlsen
---
drivers/gpio/Kconfig | 7 --
drivers/gpio/Makefile| 1 -
drivers/gpio/gpio-mscc-bitbang-spi.c | 122 ---
3 files changed, 130 deletions(-)
delete mode 100644 drivers/gpio/gpio-mscc-bitbang-spi.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index aa55ff43c4..14a14be917 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -99,13 +99,6 @@ config LPC32XX_GPIO
help
Support for the LPC32XX GPIO driver.
-config MSCC_BITBANG_SPI_GPIO
- bool "Microsemi bitbang spi GPIO driver"
- depends on DM_GPIO && SOC_VCOREIII
- help
- Support controlling the GPIO used for SPI bitbang by software. Can
- be used by the VCoreIII SoCs, but it was mainly useful for Luton.
-
config MSCC_SGPIO
bool "Microsemi Serial GPIO driver"
depends on DM_GPIO && SOC_VCOREIII
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index be2b3c792f..7c479efe2d 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -59,5 +59,4 @@ obj-$(CONFIG_MSM_GPIO)+= msm_gpio.o
obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o
obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o
-obj-$(CONFIG_MSCC_BITBANG_SPI_GPIO)+= gpio-mscc-bitbang-spi.o
obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o
diff --git a/drivers/gpio/gpio-mscc-bitbang-spi.c
b/drivers/gpio/gpio-mscc-bitbang-spi.c
deleted file mode 100644
index b675f9052c..00
--- a/drivers/gpio/gpio-mscc-bitbang-spi.c
+++ /dev/null
@@ -1,122 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Microsemi SoCs pinctrl driver
- *
- * Author:
- * License: Dual MIT/GPL
- * Copyright (c) 2018 Microsemi Corporation
- */
-
-#include
-#include
-#include
-#include
-#include
-
-enum {
- SDI,
- CS0,
- CS1,
- CS2,
- CS3,
- SDO,
- SCK
-};
-
-static const int pinmap[] = { 0, 5, 6, 7, 8, 10, 12 };
-
-#define SW_SPI_CSn_OE 0x1E /* bits 1 to 4 */
-#define SW_SPI_CS0_OE BIT(1)
-#define SW_SPI_SDO_OE BIT(9)
-#define SW_SPI_SCK_OE BIT(11)
-#define SW_PIN_CTRL_MODE BIT(13)
-
-struct mscc_bb_spi_gpio {
- void __iomem *regs;
- u32 cache_val;
-};
-
-static int mscc_bb_spi_gpio_set(struct udevice *dev, unsigned oft, int val)
-{
- struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
-
- if (val)
- gpio->cache_val |= BIT(pinmap[oft]);
- else
- gpio->cache_val &= ~BIT(pinmap[oft]);
-
- writel(gpio->cache_val, gpio->regs);
-
- return 0;
-}
-
-static int mscc_bb_spi_gpio_direction_output(struct udevice *dev, unsigned oft,
-int val)
-{
- if (oft == 0) {
- pr_err("SW_SPI_DSI can't be used as output\n");
- return -ENOTSUPP;
- }
-
- mscc_bb_spi_gpio_set(dev, oft, val);
-
- return 0;
-}
-
-static int mscc_bb_spi_gpio_direction_input(struct udevice *dev, unsigned oft)
-{
- return 0;
-}
-
-static int mscc_bb_spi_gpio_get(struct udevice *dev, unsigned int oft)
-{
- struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
- u32 val = readl(gpio->regs);
-
- return !!(val & BIT(pinmap[oft]));
-}
-
-static const struct dm_gpio_ops mscc_bb_spi_gpio_ops = {
- .direction_output = mscc_bb_spi_gpio_direction_output,
- .direction_input= mscc_bb_spi_gpio_direction_input,
- .set_value = mscc_bb_spi_gpio_set,
- .get_value = mscc_bb_spi_gpio_get,
-};
-
-static int mscc_bb_spi_gpio_probe(struct udevice *dev)
-{
- struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
- struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-
- gpio->regs = dev_remap_addr(dev);
- if (!gpio->regs)
- return -EINVAL;
-
- uc_priv->bank_name = dev->name;
- uc_priv->gpio_count = ARRAY_SIZE(pinmap);
- /*
-* Enable software mode to control the SPI pin, enables the
-* output mode for most of the pin and initialize the cache
-* value in the same time
-*/
-
- gpio->cache_val = SW_PIN_CTRL_MODE | SW_SPI_SCK_OE | SW_SPI_SDO_OE |
- SW_SPI_CS0_OE;
- writel(gpio->cache_val, gpio->regs);
-
- return 0;
-}
-
-static const struct udevice_id mscc_bb_spi_gpio_ids[] = {
- {.compatible = "mscc,spi-bitbang-gpio"},
- {}
-};
-
-U_BOOT_DRIVER(gpio_mscc_bb_spi) = {
- .name = "gpio-mscc-spi-bitbang",
- .id = UCLASS_GPIO,
- .ops= _bb_spi_gpio_ops,
- .probe = mscc_bb_spi_gpio_probe,
- .of_match = of_match_ptr(mscc_bb_spi_gpio_ids),
- .priv_auto_all
[U-Boot] [PATCH v2 2/3] mips: mscc: DT: Update luton device tree to use fast SPI driver
Thes patch change the luton base device tree to use the newly added
SPI bitbang driver.
It also updates the "mscc_luton_defconfig" to use the new driver.
Signed-off-by: Lars Povlsen
---
arch/mips/dts/mscc,luton.dtsi | 15 ++-
configs/mscc_luton_defconfig | 3 ++-
2 files changed, 4 insertions(+), 14 deletions(-)
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
index 87e27c6de5..d11ec4884d 100644
--- a/arch/mips/dts/mscc,luton.dtsi
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -84,21 +84,10 @@
gpio-ranges = < 0 0 64>;
};
- gpio_spi_bitbang: gpio@1064 {
- compatible = "mscc,spi-bitbang-gpio";
- reg = <0x1064 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
-
- };
-
spi0: spi-bitbang {
- compatible = "spi-gpio";
+ compatible = "mscc,luton-bb-spi";
status = "okay";
- gpio-sck = <_spi_bitbang 6 0>;
- gpio-miso = <_spi_bitbang 0 0>;
- gpio-mosi = <_spi_bitbang 5 0>;
- cs-gpios = <_spi_bitbang 1 0>;
+ reg = <0x1064 0x4>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig
index 65f0672c1e..d48a93a2a5 100644
--- a/configs/mscc_luton_defconfig
+++ b/configs/mscc_luton_defconfig
@@ -34,6 +34,7 @@ CONFIG_CMD_DHCP=y
# CONFIG_NET_TFTP_VARS is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:1m(UBoot),256k(Env),256k(Env.bk),512k(Unused),6m(linux)"
@@ -66,5 +67,5 @@ CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
-CONFIG_SOFT_SPI=y
+CONFIG_MSCC_BB_SPI=y
CONFIG_LZMA=y
--
2.19.2
___
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https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 1/3] mips: spi: mscc: Add fast bitbang SPI driver
This patch add a new SPI driver for MSCC SOCs that does not sport the
designware SPI hardware controller.
Performance gain: 7.664 seconds vs. 17.633 for 1 Mbyte write.
Signed-off-by: Lars Povlsen
---
MAINTAINERS | 1 +
arch/mips/mach-mscc/include/mach/common.h | 38
drivers/spi/Kconfig | 7 +
drivers/spi/Makefile | 1 +
drivers/spi/mscc_bb_spi.c | 253 ++
5 files changed, 300 insertions(+)
create mode 100644 drivers/spi/mscc_bb_spi.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 494962e9b3..0cee99ef56 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -524,6 +524,7 @@ F: arch/mips/dts/ocelot*
F: board/mscc/
F: configs/mscc*
F: drivers/gpio/mscc_sgpio.c
+F: drivers/spi/mscc_bb_spi.c
F: include/configs/vcoreiii.h
MIPS JZ4780
diff --git a/arch/mips/mach-mscc/include/mach/common.h
b/arch/mips/mach-mscc/include/mach/common.h
index d18ae78bfd..7765c060ed 100644
--- a/arch/mips/mach-mscc/include/mach/common.h
+++ b/arch/mips/mach-mscc/include/mach/common.h
@@ -29,6 +29,44 @@
/* Common utility functions */
+/*
+ * Perform a number of NOP instructions, blocks of 8 instructions.
+ * The (inlined) function will not affect cache or processor state.
+ */
+static inline void mscc_vcoreiii_nop_delay(int delay)
+{
+ while (delay > 0) {
+#define DELAY_8_NOPS() asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;")
+ switch (delay) {
+ case 8:
+ DELAY_8_NOPS();
+ /* fallthrough */
+ case 7:
+ DELAY_8_NOPS();
+ /* fallthrough */
+ case 6:
+ DELAY_8_NOPS();
+ /* fallthrough */
+ case 5:
+ DELAY_8_NOPS();
+ /* fallthrough */
+ case 4:
+ DELAY_8_NOPS();
+ /* fallthrough */
+ case 3:
+ DELAY_8_NOPS();
+ /* fallthrough */
+ case 2:
+ DELAY_8_NOPS();
+ /* fallthrough */
+ case 1:
+ DELAY_8_NOPS();
+ }
+ delay -= 8;
+#undef DELAY_8_NOPS
+ }
+}
+
int mscc_phy_rd_wr(u8 read,
u32 miim_controller,
u8 miim_addr,
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a7bb5b35c2..de4d62dd8f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -294,6 +294,13 @@ config SOFT_SPI
Enable Soft SPI driver. This driver is to use GPIO simulate
the SPI protocol.
+config MSCC_BB_SPI
+ bool "MSCC bitbang SPI driver"
+ depends on SOC_VCOREIII
+ help
+ Enable MSCC bitbang SPI driver. This driver can be used on
+ MSCC SOCs.
+
config CF_SPI
bool "ColdFire SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 392a925795..4acec3ea17 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MTK_QSPI) += mtk_qspi.o
obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
+obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
obj-$(CONFIG_MXS_SPI) += mxs_spi.o
diff --git a/drivers/spi/mscc_bb_spi.c b/drivers/spi/mscc_bb_spi.c
new file mode 100644
index 00..5685878597
--- /dev/null
+++ b/drivers/spi/mscc_bb_spi.c
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs spi driver
+ *
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct mscc_bb_platdata {
+ void __iomem *regs;
+ u32 deactivate_delay_us;
+};
+
+struct mscc_bb_priv {
+ void __iomem *regs;
+ bool cs_active; /* State flag as to whether CS is asserted */
+ int cs_num;
+ u32 svalue; /* Value to start transfer with */
+ u32 clk1; /* Clock value start */
+ u32 clk2; /* Clock value 2nd phase */
+};
+
+/* Delay 24 instructions for this particular application */
+#define hold_time_delay() mscc_vcoreiii_nop_delay(3)
+
+static int mscc_bb_spi_cs_activate(struct mscc_bb_priv *priv, int mode, int cs)
+{
+ if (!priv->cs_active) {
+ int cpha = mode & SPI_CPHA;
+ u32 cs_value;
+
+ priv->cs_num = cs;
+
+ if (cpha) {
+ /* Initial clock starts SCK=1 */
+ priv->clk1 = ICPU_SW_MODE_SW_SPI_SCK;
+
[U-Boot] [PATCH v2 0/3] mips: spi: mscc: Add fast bitbang SPI driver
These 3 patches add an optimized SPI bitbang driver for MSCC SOCs that does not sport the designware SPI hardware controller. The driver more than doubles the performance for bulk SPI transfers. This is based off the u-boot-mips/next repository. v2 changes: - Moved lowlevel delay stuff into arch common header file - remove superfluous license and DECLARE_GLOBAL_DATA_PTR - Moved defconfig changes to DT patch - Removed obsoleted gpio-mscc-bitbang-spi driver Lars Povlsen (3): mips: spi: mscc: Add fast bitbang SPI driver mips: mscc: DT: Update luton device tree to use fast SPI driver mips: gpio: mscc: Obsoleted gpio-mscc-bitbang-spi.c MAINTAINERS | 1 + arch/mips/dts/mscc,luton.dtsi | 15 +- arch/mips/mach-mscc/include/mach/common.h | 38 configs/mscc_luton_defconfig | 3 +- drivers/gpio/Kconfig | 7 - drivers/gpio/Makefile | 1 - drivers/gpio/gpio-mscc-bitbang-spi.c | 122 --- drivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/mscc_bb_spi.c | 253 ++ 10 files changed, 304 insertions(+), 144 deletions(-) delete mode 100644 drivers/gpio/gpio-mscc-bitbang-spi.c create mode 100644 drivers/spi/mscc_bb_spi.c -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/2] mips: mscc: DT: Update luton device tree to use fast SPI driver
Thes patch change the luton base device tree to use the newly added
SPI bitbang driver.
Signed-off-by: Lars Povlsen
---
arch/mips/dts/mscc,luton.dtsi | 15 ++-
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
index 87e27c6de5..d11ec4884d 100644
--- a/arch/mips/dts/mscc,luton.dtsi
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -84,21 +84,10 @@
gpio-ranges = < 0 0 64>;
};
- gpio_spi_bitbang: gpio@1064 {
- compatible = "mscc,spi-bitbang-gpio";
- reg = <0x1064 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
-
- };
-
spi0: spi-bitbang {
- compatible = "spi-gpio";
+ compatible = "mscc,luton-bb-spi";
status = "okay";
- gpio-sck = <_spi_bitbang 6 0>;
- gpio-miso = <_spi_bitbang 0 0>;
- gpio-mosi = <_spi_bitbang 5 0>;
- cs-gpios = <_spi_bitbang 1 0>;
+ reg = <0x1064 0x4>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
--
2.19.2
___
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[U-Boot] [PATCH 1/2] mips: spi: mscc: Add fast bitbang SPI driver
From: Lars Povlsen
This patch add a new SPI driver for MSCC SOCs that does not sport the
designware SPI hardware controller.
Performance gain: 7.664 seconds vs. 17.633 for 1 Mbyte write -
measured on a Luton10 with a m25p128 NOR flash.
Signed-off-by: Lars Povlsen
---
MAINTAINERS | 1 +
configs/mscc_luton_defconfig | 3 +-
drivers/spi/Kconfig | 7 +
drivers/spi/Makefile | 1 +
drivers/spi/mscc_bb_spi.c| 258 +++
5 files changed, 269 insertions(+), 1 deletion(-)
create mode 100644 drivers/spi/mscc_bb_spi.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 494962e9b3..0cee99ef56 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -524,6 +524,7 @@ F: arch/mips/dts/ocelot*
F: board/mscc/
F: configs/mscc*
F: drivers/gpio/mscc_sgpio.c
+F: drivers/spi/mscc_bb_spi.c
F: include/configs/vcoreiii.h
MIPS JZ4780
diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig
index 65f0672c1e..d48a93a2a5 100644
--- a/configs/mscc_luton_defconfig
+++ b/configs/mscc_luton_defconfig
@@ -34,6 +34,7 @@ CONFIG_CMD_DHCP=y
# CONFIG_NET_TFTP_VARS is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:1m(UBoot),256k(Env),256k(Env.bk),512k(Unused),6m(linux)"
@@ -66,5 +67,5 @@ CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
-CONFIG_SOFT_SPI=y
+CONFIG_MSCC_BB_SPI=y
CONFIG_LZMA=y
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a7bb5b35c2..de4d62dd8f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -294,6 +294,13 @@ config SOFT_SPI
Enable Soft SPI driver. This driver is to use GPIO simulate
the SPI protocol.
+config MSCC_BB_SPI
+ bool "MSCC bitbang SPI driver"
+ depends on SOC_VCOREIII
+ help
+ Enable MSCC bitbang SPI driver. This driver can be used on
+ MSCC SOCs.
+
config CF_SPI
bool "ColdFire SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 392a925795..4acec3ea17 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MTK_QSPI) += mtk_qspi.o
obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
+obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
obj-$(CONFIG_MXS_SPI) += mxs_spi.o
diff --git a/drivers/spi/mscc_bb_spi.c b/drivers/spi/mscc_bb_spi.c
new file mode 100644
index 00..e0ed2c9725
--- /dev/null
+++ b/drivers/spi/mscc_bb_spi.c
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs spi driver
+ *
+ * License: Dual MIT/GPL
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mscc_bb_platdata {
+ void __iomem *regs;
+ u32 deactivate_delay_us;
+};
+
+struct mscc_bb_priv {
+ void __iomem *regs;
+ bool cs_active; /* State flag as to whether CS is asserted */
+ int cs_num;
+ u32 svalue; /* Value to start transfer with */
+ u32 clk1; /* Clock value start */
+ u32 clk2; /* Clock value 2nd phase */
+};
+
+#define DELAY() \
+ asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;" \
+"nop; nop; nop; nop; nop; nop; nop; nop;" \
+"nop; nop; nop; nop; nop; nop; nop; nop;")
+
+static int mscc_bb_spi_cs_activate(struct mscc_bb_priv *priv, int mode, int cs)
+{
+ if (!priv->cs_active) {
+ int cpha = mode & SPI_CPHA;
+ u32 cs_value;
+
+ priv->cs_num = cs;
+
+ if (cpha) {
+ /* Initial clock starts SCK=1 */
+ priv->clk1 = ICPU_SW_MODE_SW_SPI_SCK;
+ priv->clk2 = 0;
+ } else {
+ /* Initial clock starts SCK=0 */
+ priv->clk1 = 0;
+ priv->clk2 = ICPU_SW_MODE_SW_SPI_SCK;
+ }
+
+ /* Enable bitbang, SCK_OE, SDO_OE */
+ priv->svalue = (ICPU_SW_MODE_SW_PIN_CTRL_MODE | /* Bitbang */
+ ICPU_SW_MODE_SW_SPI_SCK_OE| /* SCK_OE */
+ ICPU_SW_MODE_SW_SPI_SDO_OE); /* SDO OE */
+
+ /* Add CS */
+ if (cs >= 0) {
+ cs_value =
+ ICPU_SW_MODE_SW_SPI_CS_OE(BIT(cs)) |
+ ICPU_SW_MODE_SW_SPI_CS(BIT(cs));
+ } else {
[U-Boot] [PATCH 0/2] mips: spi: mscc: Add fast bitbang SPI driver
These 2 patches add an optimized SPI bitbang driver for MSCC SOCs that does not sport the designware SPI hardware controller. The driver more than doubles the performance for bulk SPI transfers. This is based off the u-boot-mips/next repository. Lars Povlsen (2): mips: spi: mscc: Add fast bitbang SPI driver mips: mscc: DT: Update luton device tree to use fast SPI driver MAINTAINERS | 1 + arch/mips/dts/mscc,luton.dtsi | 15 +- configs/mscc_luton_defconfig | 3 +- drivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/mscc_bb_spi.c | 258 ++ 6 files changed, 271 insertions(+), 14 deletions(-) create mode 100644 drivers/spi/mscc_bb_spi.c -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 5/6] mips: ocelot: DT: Enable use of serial gpio
From: Lars Povlsen
This enables the use of the MSCC serial GPIO driver on the MSCC
VCoreIII 'ocelot' SOC, and add gpio-leds nodes to the pcb123 and
pcb120 DT.
Signed-off-by: Lars Povlsen
---
arch/mips/dts/mscc,ocelot.dtsi | 23 ++
arch/mips/dts/ocelot_pcb120.dts | 76 +
arch/mips/dts/ocelot_pcb123.dts | 25 +++
3 files changed, 124 insertions(+)
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
index 87b4736285..2592003103 100644
--- a/arch/mips/dts/mscc,ocelot.dtsi
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -37,6 +37,12 @@
clock-frequency = <5>;
};
+ sys_clk: sys-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000>;
+ };
+
ahb_clk: ahb-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -118,6 +124,11 @@
#gpio-cells = <2>;
gpio-ranges = < 0 0 22>;
+ sgpio_pins: sgpio-pins {
+ pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
+ function = "sg0";
+ };
+
uart_pins: uart-pins {
pins = "GPIO_6", "GPIO_7";
function = "uart";
@@ -148,5 +159,17 @@
function = "si";
};
};
+
+ sgpio: gpio@10700f8 {
+ compatible = "mscc,ocelot-sgpio";
+ status = "disabled";
+ clocks = <_clk>;
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ reg = <0x10700f8 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < 0 0 64>;
+ };
};
};
diff --git a/arch/mips/dts/ocelot_pcb120.dts b/arch/mips/dts/ocelot_pcb120.dts
index 47d305a614..658719e684 100644
--- a/arch/mips/dts/ocelot_pcb120.dts
+++ b/arch/mips/dts/ocelot_pcb120.dts
@@ -9,4 +9,80 @@
/ {
model = "Ocelot PCB120 Reference Board";
compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ poe_green {
+ label = "pcb120:green:poe";
+ gpios = < 44 1>; /* p12.1 */
+ default-state = "off";
+ };
+
+ poe_red {
+ label = "pcb120:red:poe";
+ gpios = < 12 1>; /* p12.0 */
+ default-state = "off";
+ };
+
+ alarm_green {
+ label = "pcb120:green:alarm";
+ gpios = < 45 1>; /* p13.1 */
+ default-state = "off";
+ };
+
+ alarm_red {
+ label = "pcb120:red:alarm";
+ gpios = < 13 1>; /* p13.0 */
+ default-state = "off";
+ };
+
+ dc_a_green {
+ label = "pcb120:green:dc_a";
+ gpios = < 46 1>; /* p14.1 */
+ default-state = "off";
+ };
+
+ dc_a_red {
+ label = "pcb120:red:dc_a";
+ gpios = < 14 1>; /* p14.0 */
+ default-state = "off";
+ };
+
+ dc_b_green {
+ label = "pcb120:green:dc_b";
+ gpios = < 47 1>; /* p15.1 */
+ default-state = "off";
+ };
+
+ dc_b_red {
+ label = "pcb120:red:dc_b";
+ gpios = < 15 1>; /* p15.0 */
+ default-state = "off";
+ };
+
+ status_green {
+ label = "pcb120:green:status";
+ gpios = < 48 1>; /* p16.1 */
+ default-state = "on";
+ };
+
+ status_red {
+ label = "pcb120:red:alarm";
+ gpios = < 16 1>; /* p16.0 */
+ default-state = &qu
[U-Boot] [PATCH v3 3/6] mips: luton: DT: Enable use of serial gpio
From: Lars Povlsen
This enables the use of the MSCC serial GPIO driver, and add gpio-leds
nodes to the 'luton' pcb090 and pcb091 DT.
Signed-off-by: Lars Povlsen
---
arch/mips/dts/luton_pcb090.dts | 21 +
arch/mips/dts/luton_pcb091.dts | 27 +++
arch/mips/dts/mscc,luton.dtsi | 20
3 files changed, 68 insertions(+)
diff --git a/arch/mips/dts/luton_pcb090.dts b/arch/mips/dts/luton_pcb090.dts
index a3f8926ad9..951d8da1be 100644
--- a/arch/mips/dts/luton_pcb090.dts
+++ b/arch/mips/dts/luton_pcb090.dts
@@ -18,6 +18,27 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ status_green {
+ label = "pcb090:green:status";
+ gpios = < 64 GPIO_ACTIVE_HIGH>; /* p0.2 */
+ default-state = "on";
+ };
+
+ status_red {
+ label = "pcb090:red:status";
+ gpios = < 65 GPIO_ACTIVE_HIGH>; /* p1.2 */
+ default-state = "off";
+ };
+ };
+};
+
+ {
+ status = "okay";
+ gpio-ranges = < 0 0 96>;
};
{
diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts
index 74f9274c21..bf638b2bc7 100644
--- a/arch/mips/dts/luton_pcb091.dts
+++ b/arch/mips/dts/luton_pcb091.dts
@@ -18,6 +18,33 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ top_dimmer {
+ label = "pcb091:top:dimmer";
+ gpios = < 29 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+
+ status_green {
+ label = "pcb091:green:status";
+ gpios = < 26 GPIO_ACTIVE_HIGH>; /* p26.0 */
+ default-state = "on";
+ };
+
+ status_red {
+ label = "pcb091:red:status";
+ gpios = < 58 GPIO_ACTIVE_HIGH>; /* p26.1 */
+ default-state = "off";
+ };
+ };
+};
+
+ {
+ status = "okay";
+ mscc,sgpio-ports = <0xFFF000FF>;
};
{
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
index 6a4ad2a5be..87e27c6de5 100644
--- a/arch/mips/dts/mscc,luton.dtsi
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -25,6 +25,11 @@
serial0 =
};
+ sys_clk: sys-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000>;
+ };
ahb_clk: ahb-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -57,11 +62,26 @@
#gpio-cells = <2>;
gpio-ranges = < 0 0 32>;
+ sgpio_pins: sgpio-pins {
+ pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
+ function = "sio";
+ };
uart_pins: uart-pins {
pins = "GPIO_30", "GPIO_31";
function = "uart";
};
+ };
+ sgpio: gpio@70130 {
+ compatible = "mscc,luton-sgpio";
+ status = "disabled";
+ clocks = <_clk>;
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ reg = <0x0070130 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < 0 0 64>;
};
gpio_spi_bitbang: gpio@1064 {
--
2.19.2
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[U-Boot] [PATCH v3 6/6] mips: ocelot: Enable use of serial gpio for LED
This enables the use of the MSCC serial GPIO driver to control the LEDs on the MSCC VCoreIII 'ocelot' pcb123 and pcb120. Signed-off-by: Lars Povlsen --- board/mscc/ocelot/ocelot.c| 6 ++ configs/mscc_ocelot_defconfig | 3 +++ 2 files changed, 9 insertions(+) diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c index a557cacd1b..a05c308669 100644 --- a/board/mscc/ocelot/ocelot.c +++ b/board/mscc/ocelot/ocelot.c @@ -9,6 +9,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -56,6 +57,11 @@ int board_early_init_r(void) /* Address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + + /* LED setup */ + if (IS_ENABLED(CONFIG_LED)) + led_default_state(); + return 0; } diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig index 66451000d9..fb6a5bdc31 100644 --- a/configs/mscc_ocelot_defconfig +++ b/configs/mscc_ocelot_defconfig @@ -48,6 +48,9 @@ CONFIG_CLK=y CONFIG_DM_GPIO=y CONFIG_MTD=y CONFIG_MTD_SPI_NAND=y +CONFIG_MSCC_SGPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 4/6] mips: luton: Enable use of serial gpio for LED
This enables the use of the MSCC serial GPIO driver to control the LEDs on the MSCC VCoreIII 'luton' SoC. Signed-off-by: Lars Povlsen --- board/mscc/luton/luton.c | 6 ++ configs/mscc_luton_defconfig | 3 +++ 2 files changed, 9 insertions(+) diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c index b509b6beb3..807c717e33 100644 --- a/board/mscc/luton/luton.c +++ b/board/mscc/luton/luton.c @@ -5,6 +5,7 @@ #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -27,6 +28,11 @@ int board_early_init_r(void) /* Address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + + /* LED setup */ + if (IS_ENABLED(CONFIG_LED)) + led_default_state(); + return 0; } diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig index 03922f5379..0b3eb3865c 100644 --- a/configs/mscc_luton_defconfig +++ b/configs/mscc_luton_defconfig @@ -46,6 +46,9 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y CONFIG_DM_GPIO=y +CONFIG_MSCC_SGPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 2/6] mips: mscc_sgpio: Add DT bindings documentation
From: Lars Povlsen
This add device tree binding documentation for the MSCC serial GPIO
driver.
Signed-off-by: Lars Povlsen
Acked-by: Linus Walleij
---
doc/device-tree-bindings/gpio/mscc_sgpio.txt | 45
1 file changed, 45 insertions(+)
create mode 100644 doc/device-tree-bindings/gpio/mscc_sgpio.txt
diff --git a/doc/device-tree-bindings/gpio/mscc_sgpio.txt
b/doc/device-tree-bindings/gpio/mscc_sgpio.txt
new file mode 100644
index 00..3d344d64ac
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/mscc_sgpio.txt
@@ -0,0 +1,45 @@
+Microsemi Corporation (MSCC) Serial GPIO driver
+
+The MSCC serial GPIO extends the number or GPIO's on the system by
+means of 4 dedicated pins: one input, one output, one clock and one
+strobe pin. By attaching a number of (external) shift registers, the
+effective GPIO count can be extended by up to 128 GPIO's per
+controller.
+
+Required properties:
+- compatible : "mscc,luton-sgpio" or "mscc,ocelot-sgpio"
+- clock: Reference clock used to generate clock divider setting. See
+ mscc,sgpio-frequency property.
+- reg : Physical base address and length of the controller's registers.
+- #gpio-cells : Should be two. The first cell is the pin number and the
+ second cell is used to specify optional parameters:
+ - bit 0 specifies polarity (0 for normal, 1 for inverted)
+- gpio-controller : Marks the device node as a GPIO controller.
+- gpio-ranges: Standard gpio range(s): phandle, gpio base, pinctrl base
+ and count.
+
+Optional properties:
+- ngpios: See gpio.txt
+- mscc,sgpio-frequency: The frequency at which the serial bitstream is
+ generated and sampled. Default: 1250 (Hz).
+- mscc,sgpio-ports: A bitmask (32 bits) of which ports are enabled in
+ the serialized gpio stream. One 'port' will transport from 1 to 4
+ gpio bits. Default: 0x.
+
+Typically the pinctrl-0 and pinctrl-names properties will also be
+present to enable the use of the SIO CLK, LD, DI and DO for some
+regular GPIO pins.
+
+Example:
+
+sgpio: gpio@10700f8 {
+ compatible = "mscc,ocelot-sgpio";
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ reg = <0x10700f8 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < 0 0 64>;
+ mscc,sgpio-frequency = <12500>;
+ mscc,sgpio-ports = <0x000F>;
+};
--
2.19.2
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[U-Boot] [PATCH v3 1/6] mips: mscc_sgpio: Add the MSCC serial GPIO device (SIO)
This add support for the the MSCC serial GPIO driver in MSCC
VCoreIII-based SOCs.
By using a serial interface, the SIO controller significantly extends
the number of available GPIOs with a minimum number of additional pins
on the device. The primary purpose of the SIO controller is to connect
control signals from SFP modules and to act as an LED controller.
This adds the base driver.
Signed-off-by: Lars Povlsen
---
MAINTAINERS | 1 +
drivers/gpio/Kconfig | 11 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/mscc_sgpio.c | 275 ++
4 files changed, 288 insertions(+)
create mode 100644 drivers/gpio/mscc_sgpio.c
diff --git a/MAINTAINERS b/MAINTAINERS
index ae825014bd..494962e9b3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -523,6 +523,7 @@ F: arch/mips/dts/mscc*
F: arch/mips/dts/ocelot*
F: board/mscc/
F: configs/mscc*
+F: drivers/gpio/mscc_sgpio.c
F: include/configs/vcoreiii.h
MIPS JZ4780
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c8c6c60623..aa55ff43c4 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -106,6 +106,17 @@ config MSCC_BITBANG_SPI_GPIO
Support controlling the GPIO used for SPI bitbang by software. Can
be used by the VCoreIII SoCs, but it was mainly useful for Luton.
+config MSCC_SGPIO
+ bool "Microsemi Serial GPIO driver"
+ depends on DM_GPIO && SOC_VCOREIII
+ help
+ Support for the VCoreIII SoC serial GPIO device. By using a
+ serial interface, the SIO controller significantly extends
+ the number of available GPIOs with a minimum number of
+ additional pins on the device. The primary purpose of the
+ SIO controller is to connect control signals from SFP
+ modules and to act as an LED controller.
+
config MSM_GPIO
bool "Qualcomm GPIO driver"
depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 61feda1537..be2b3c792f 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -60,3 +60,4 @@ obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o
obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o
obj-$(CONFIG_MSCC_BITBANG_SPI_GPIO)+= gpio-mscc-bitbang-spi.o
+obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o
diff --git a/drivers/gpio/mscc_sgpio.c b/drivers/gpio/mscc_sgpio.c
new file mode 100644
index 00..c899454ec4
--- /dev/null
+++ b/drivers/gpio/mscc_sgpio.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs serial gpio driver
+ *
+ * Author:
+ *
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MSCC_SGPIOS_PER_BANK 32
+#define MSCC_SGPIO_BANK_DEPTH 4
+
+enum {
+ REG_INPUT_DATA,
+ REG_PORT_CONFIG,
+ REG_PORT_ENABLE,
+ REG_SIO_CONFIG,
+ REG_SIO_CLOCK,
+ MAXREG
+};
+
+struct mscc_sgpio_bf {
+ u8 beg;
+ u8 end;
+};
+
+struct mscc_sgpio_props {
+ u8 regoff[MAXREG];
+ struct mscc_sgpio_bf auto_repeat;
+ struct mscc_sgpio_bf port_width;
+ struct mscc_sgpio_bf clk_freq;
+ struct mscc_sgpio_bf bit_source;
+};
+
+#define __M(bf)GENMASK((bf).end, (bf).beg)
+#define __F(bf, x) (__M(bf) & ((x) << (bf).beg))
+#define __X(bf, x) (((x) >> (bf).beg) & GENMASK(((bf).end - (bf).beg), 0))
+
+#define MSCC_M_CFG_SIO_AUTO_REPEAT(p) BIT(p->props->auto_repeat.beg)
+#define MSCC_F_CFG_SIO_PORT_WIDTH(p, x)
__F(p->props->port_width, x)
+#define MSCC_M_CFG_SIO_PORT_WIDTH(p) __M(p->props->port_width)
+#define MSCC_F_CLOCK_SIO_CLK_FREQ(p, x)__F(p->props->clk_freq,
x)
+#define MSCC_M_CLOCK_SIO_CLK_FREQ(p) __M(p->props->clk_freq)
+#define MSCC_F_PORT_CFG_BIT_SOURCE(p, x) __F(p->props->bit_source, x)
+#define MSCC_X_PORT_CFG_BIT_SOURCE(p, x) __X(p->props->bit_source, x)
+
+const struct mscc_sgpio_props props_luton = {
+ .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
+ .auto_repeat = { 5, 5 },
+ .port_width = { 2, 3 },
+ .clk_freq= { 0, 11 },
+ .bit_source = { 0, 11 },
+};
+
+const struct mscc_sgpio_props props_ocelot = {
+ .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
+ .auto_repeat = { 10, 10 },
+ .port_width = { 7, 8 },
+ .clk_freq= { 8, 19 },
+ .bit_source = { 12, 23 },
+};
+
+struct mscc_sgpio_priv {
+ u32 bitcount;
+ u32 ports;
+ u32 clock;
+ u32 mode[MSCC_SGPIOS_PER_BANK];
+ u32 __iomem *regs;
+ const struct mscc_sgpio_props *props;
+};
+
+static inline u32 sgpio_readl(struct mscc_sgpio_priv *priv, u32 rno, u32 off)
+{
+ u32 __iomem *reg = >regs[priv->props->regoff[rno] + of
[U-Boot] [PATCH v3 0/6] mips: mscc: gpio: Add MSCC serial GPIO driver
This patch series add the GPIO device (SIO) in the MSCC VCoreIII-based SOCs, and enables it on the supported platforms. By using a serial interface, the SIO controller significantly extends the number of available GPIOs with a minimum number of additional pins on the device. The primary purpose of the SIO controller is to connect control signals from SFP modules and to act as an LED controller. This version address comments from Daniel Schwierzeck and Linus Walleij . This is based off the u-boot-mips repository. v3 changes: - Fail driver load if clk_get_rate() fails - Use dev_remap_addr() instead of map_physmem() - Use dev_err instead of printf - (DT doc) ngpios: Refer to gpio.txt v2 changes: - Extended the DT bindings documentation - Eliminated the need for the "mscc,sgpio-bitcount" property. - Using dev_read_u32_default() instead of fdtdec_get_int() - Using map_physmem() - Added MAINTAINERS entry for driver Lars Povlsen (6): mips: mscc_sgpio: Add the MSCC serial GPIO device (SIO) mips: mscc_sgpio: Add DT bindings documentation mips: luton: DT: Enable use of serial gpio mips: luton: Enable use of serial gpio for LED mips: ocelot: DT: Enable use of serial gpio mips: ocelot: Enable use of serial gpio for LED MAINTAINERS | 1 + arch/mips/dts/luton_pcb090.dts | 21 ++ arch/mips/dts/luton_pcb091.dts | 27 ++ arch/mips/dts/mscc,luton.dtsi| 20 ++ arch/mips/dts/mscc,ocelot.dtsi | 23 ++ arch/mips/dts/ocelot_pcb120.dts | 76 + arch/mips/dts/ocelot_pcb123.dts | 25 ++ board/mscc/luton/luton.c | 6 + board/mscc/ocelot/ocelot.c | 6 + configs/mscc_luton_defconfig | 3 + configs/mscc_ocelot_defconfig| 3 + doc/device-tree-bindings/gpio/mscc_sgpio.txt | 45 +++ drivers/gpio/Kconfig | 11 + drivers/gpio/Makefile| 1 + drivers/gpio/mscc_sgpio.c| 275 +++ 15 files changed, 543 insertions(+) create mode 100644 doc/device-tree-bindings/gpio/mscc_sgpio.txt create mode 100644 drivers/gpio/mscc_sgpio.c -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 6/6] mips: ocelot: Enable use of serial gpio for LED
This enables the use of the MSCC serial GPIO driver to control the LEDs on the MSCC VCoreIII 'ocelot' pcb123 and pcb120. Signed-off-by: Lars Povlsen --- board/mscc/ocelot/ocelot.c| 6 ++ configs/mscc_ocelot_defconfig | 3 +++ 2 files changed, 9 insertions(+) diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c index a557cacd1b..a05c308669 100644 --- a/board/mscc/ocelot/ocelot.c +++ b/board/mscc/ocelot/ocelot.c @@ -9,6 +9,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -56,6 +57,11 @@ int board_early_init_r(void) /* Address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + + /* LED setup */ + if (IS_ENABLED(CONFIG_LED)) + led_default_state(); + return 0; } diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig index 66451000d9..fb6a5bdc31 100644 --- a/configs/mscc_ocelot_defconfig +++ b/configs/mscc_ocelot_defconfig @@ -48,6 +48,9 @@ CONFIG_CLK=y CONFIG_DM_GPIO=y CONFIG_MTD=y CONFIG_MTD_SPI_NAND=y +CONFIG_MSCC_SGPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 4/6] mips: luton: Enable use of serial gpio for LED
This enables the use of the MSCC serial GPIO driver to control the LEDs on the MSCC VCoreIII 'luton' SoC. Signed-off-by: Lars Povlsen --- board/mscc/luton/luton.c | 6 ++ configs/mscc_luton_defconfig | 3 +++ 2 files changed, 9 insertions(+) diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c index b509b6beb3..807c717e33 100644 --- a/board/mscc/luton/luton.c +++ b/board/mscc/luton/luton.c @@ -5,6 +5,7 @@ #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -27,6 +28,11 @@ int board_early_init_r(void) /* Address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + + /* LED setup */ + if (IS_ENABLED(CONFIG_LED)) + led_default_state(); + return 0; } diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig index 03922f5379..0b3eb3865c 100644 --- a/configs/mscc_luton_defconfig +++ b/configs/mscc_luton_defconfig @@ -46,6 +46,9 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y CONFIG_DM_GPIO=y +CONFIG_MSCC_SGPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 5/6] mips: ocelot: DT: Enable use of serial gpio
From: Lars Povlsen
This enables the use of the MSCC serial GPIO driver on the MSCC
VCoreIII 'ocelot' SOC, and add gpio-leds nodes to the pcb123 and
pcb120 DT.
Signed-off-by: Lars Povlsen
---
arch/mips/dts/mscc,ocelot.dtsi | 23 ++
arch/mips/dts/ocelot_pcb120.dts | 76 +
arch/mips/dts/ocelot_pcb123.dts | 25 +++
3 files changed, 124 insertions(+)
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
index 87b4736285..2592003103 100644
--- a/arch/mips/dts/mscc,ocelot.dtsi
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -37,6 +37,12 @@
clock-frequency = <5>;
};
+ sys_clk: sys-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000>;
+ };
+
ahb_clk: ahb-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -118,6 +124,11 @@
#gpio-cells = <2>;
gpio-ranges = < 0 0 22>;
+ sgpio_pins: sgpio-pins {
+ pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
+ function = "sg0";
+ };
+
uart_pins: uart-pins {
pins = "GPIO_6", "GPIO_7";
function = "uart";
@@ -148,5 +159,17 @@
function = "si";
};
};
+
+ sgpio: gpio@10700f8 {
+ compatible = "mscc,ocelot-sgpio";
+ status = "disabled";
+ clocks = <_clk>;
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ reg = <0x10700f8 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < 0 0 64>;
+ };
};
};
diff --git a/arch/mips/dts/ocelot_pcb120.dts b/arch/mips/dts/ocelot_pcb120.dts
index 47d305a614..658719e684 100644
--- a/arch/mips/dts/ocelot_pcb120.dts
+++ b/arch/mips/dts/ocelot_pcb120.dts
@@ -9,4 +9,80 @@
/ {
model = "Ocelot PCB120 Reference Board";
compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ poe_green {
+ label = "pcb120:green:poe";
+ gpios = < 44 1>; /* p12.1 */
+ default-state = "off";
+ };
+
+ poe_red {
+ label = "pcb120:red:poe";
+ gpios = < 12 1>; /* p12.0 */
+ default-state = "off";
+ };
+
+ alarm_green {
+ label = "pcb120:green:alarm";
+ gpios = < 45 1>; /* p13.1 */
+ default-state = "off";
+ };
+
+ alarm_red {
+ label = "pcb120:red:alarm";
+ gpios = < 13 1>; /* p13.0 */
+ default-state = "off";
+ };
+
+ dc_a_green {
+ label = "pcb120:green:dc_a";
+ gpios = < 46 1>; /* p14.1 */
+ default-state = "off";
+ };
+
+ dc_a_red {
+ label = "pcb120:red:dc_a";
+ gpios = < 14 1>; /* p14.0 */
+ default-state = "off";
+ };
+
+ dc_b_green {
+ label = "pcb120:green:dc_b";
+ gpios = < 47 1>; /* p15.1 */
+ default-state = "off";
+ };
+
+ dc_b_red {
+ label = "pcb120:red:dc_b";
+ gpios = < 15 1>; /* p15.0 */
+ default-state = "off";
+ };
+
+ status_green {
+ label = "pcb120:green:status";
+ gpios = < 48 1>; /* p16.1 */
+ default-state = "on";
+ };
+
+ status_red {
+ label = "pcb120:red:alarm";
+ gpios = < 16 1>; /* p16.0 */
+ default-state = &qu
[U-Boot] [PATCH v2 3/6] mips: luton: DT: Enable use of serial gpio
From: Lars Povlsen
This enables the use of the MSCC serial GPIO driver, and add gpio-leds
nodes to the 'luton' pcb090 and pcb091 DT.
Signed-off-by: Lars Povlsen
---
arch/mips/dts/luton_pcb090.dts | 21 +
arch/mips/dts/luton_pcb091.dts | 27 +++
arch/mips/dts/mscc,luton.dtsi | 20
3 files changed, 68 insertions(+)
diff --git a/arch/mips/dts/luton_pcb090.dts b/arch/mips/dts/luton_pcb090.dts
index a3f8926ad9..951d8da1be 100644
--- a/arch/mips/dts/luton_pcb090.dts
+++ b/arch/mips/dts/luton_pcb090.dts
@@ -18,6 +18,27 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ status_green {
+ label = "pcb090:green:status";
+ gpios = < 64 GPIO_ACTIVE_HIGH>; /* p0.2 */
+ default-state = "on";
+ };
+
+ status_red {
+ label = "pcb090:red:status";
+ gpios = < 65 GPIO_ACTIVE_HIGH>; /* p1.2 */
+ default-state = "off";
+ };
+ };
+};
+
+ {
+ status = "okay";
+ gpio-ranges = < 0 0 96>;
};
{
diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts
index 74f9274c21..bf638b2bc7 100644
--- a/arch/mips/dts/luton_pcb091.dts
+++ b/arch/mips/dts/luton_pcb091.dts
@@ -18,6 +18,33 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ top_dimmer {
+ label = "pcb091:top:dimmer";
+ gpios = < 29 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+
+ status_green {
+ label = "pcb091:green:status";
+ gpios = < 26 GPIO_ACTIVE_HIGH>; /* p26.0 */
+ default-state = "on";
+ };
+
+ status_red {
+ label = "pcb091:red:status";
+ gpios = < 58 GPIO_ACTIVE_HIGH>; /* p26.1 */
+ default-state = "off";
+ };
+ };
+};
+
+ {
+ status = "okay";
+ mscc,sgpio-ports = <0xFFF000FF>;
};
{
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
index 6a4ad2a5be..87e27c6de5 100644
--- a/arch/mips/dts/mscc,luton.dtsi
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -25,6 +25,11 @@
serial0 =
};
+ sys_clk: sys-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000>;
+ };
ahb_clk: ahb-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -57,11 +62,26 @@
#gpio-cells = <2>;
gpio-ranges = < 0 0 32>;
+ sgpio_pins: sgpio-pins {
+ pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
+ function = "sio";
+ };
uart_pins: uart-pins {
pins = "GPIO_30", "GPIO_31";
function = "uart";
};
+ };
+ sgpio: gpio@70130 {
+ compatible = "mscc,luton-sgpio";
+ status = "disabled";
+ clocks = <_clk>;
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ reg = <0x0070130 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < 0 0 64>;
};
gpio_spi_bitbang: gpio@1064 {
--
2.19.2
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[U-Boot] [PATCH v2 2/6] mips: mscc_sgpio: Add DT bindings documentation
From: Lars Povlsen
This add device tree binding documentation for the MSCC serial GPIO
driver.
Signed-off-by: Lars Povlsen
---
doc/device-tree-bindings/gpio/mscc_sgpio.txt | 45
1 file changed, 45 insertions(+)
create mode 100644 doc/device-tree-bindings/gpio/mscc_sgpio.txt
diff --git a/doc/device-tree-bindings/gpio/mscc_sgpio.txt
b/doc/device-tree-bindings/gpio/mscc_sgpio.txt
new file mode 100644
index 00..2db2d277a5
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/mscc_sgpio.txt
@@ -0,0 +1,45 @@
+Microsemi Corporation (MSCC) Serial GPIO driver
+
+The MSCC serial GPIO extends the number or GPIO's on the system by
+means of 4 dedicated pins: one input, one output, one clock and one
+strobe pin. By attaching a number of (external) shift registers, the
+effective GPIO count can be extended by up to 128 GPIO's per
+controller.
+
+Required properties:
+- compatible : "mscc,luton-sgpio" or "mscc,ocelot-sgpio"
+- clock: Reference clock used to generate clock divider setting. See
+ mscc,sgpio-frequency property.
+- reg : Physical base address and length of the controller's registers.
+- #gpio-cells : Should be two. The first cell is the pin number and the
+ second cell is used to specify optional parameters:
+ - bit 0 specifies polarity (0 for normal, 1 for inverted)
+- gpio-controller : Marks the device node as a GPIO controller.
+- gpio-ranges: Standard gpio range(s): phandle, gpio base, pinctrl base
+ and count.
+
+Optional properties:
+- ngpios: Set the number of GPIO's actually used.
+- mscc,sgpio-frequency: The frequency at which the serial bitstream is
+ generated and sampled. Default: 1250 (Hz).
+- mscc,sgpio-ports: A bitmask (32 bits) of which ports are enabled in
+ the serialized gpio stream. One 'port' will transport from 1 to 4
+ gpio bits. Default: 0x.
+
+Typically the pinctrl-0 and pinctrl-names properties will also be
+present to enable the use of the SIO CLK, LD, DI and DO for some
+regular GPIO pins.
+
+Example:
+
+sgpio: gpio@10700f8 {
+ compatible = "mscc,ocelot-sgpio";
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ reg = <0x10700f8 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < 0 0 64>;
+ mscc,sgpio-frequency = <12500>;
+ mscc,sgpio-ports = <0x000F>;
+};
--
2.19.2
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[U-Boot] [PATCH v2 1/6] mips: mscc_sgpio: Add the MSCC serial GPIO device (SIO)
This add support for the the MSCC serial GPIO driver in MSCC
VCoreIII-based SOCs.
By using a serial interface, the SIO controller significantly extends
the number of available GPIOs with a minimum number of additional pins
on the device. The primary purpose of the SIO controller is to connect
control signals from SFP modules and to act as an LED controller.
This adds the base driver.
Signed-off-by: Lars Povlsen
---
MAINTAINERS | 1 +
drivers/gpio/Kconfig | 11 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/mscc_sgpio.c | 274 ++
4 files changed, 287 insertions(+)
create mode 100644 drivers/gpio/mscc_sgpio.c
diff --git a/MAINTAINERS b/MAINTAINERS
index ae825014bd..494962e9b3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -523,6 +523,7 @@ F: arch/mips/dts/mscc*
F: arch/mips/dts/ocelot*
F: board/mscc/
F: configs/mscc*
+F: drivers/gpio/mscc_sgpio.c
F: include/configs/vcoreiii.h
MIPS JZ4780
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c8c6c60623..aa55ff43c4 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -106,6 +106,17 @@ config MSCC_BITBANG_SPI_GPIO
Support controlling the GPIO used for SPI bitbang by software. Can
be used by the VCoreIII SoCs, but it was mainly useful for Luton.
+config MSCC_SGPIO
+ bool "Microsemi Serial GPIO driver"
+ depends on DM_GPIO && SOC_VCOREIII
+ help
+ Support for the VCoreIII SoC serial GPIO device. By using a
+ serial interface, the SIO controller significantly extends
+ the number of available GPIOs with a minimum number of
+ additional pins on the device. The primary purpose of the
+ SIO controller is to connect control signals from SFP
+ modules and to act as an LED controller.
+
config MSM_GPIO
bool "Qualcomm GPIO driver"
depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 61feda1537..be2b3c792f 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -60,3 +60,4 @@ obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o
obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o
obj-$(CONFIG_MSCC_BITBANG_SPI_GPIO)+= gpio-mscc-bitbang-spi.o
+obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o
diff --git a/drivers/gpio/mscc_sgpio.c b/drivers/gpio/mscc_sgpio.c
new file mode 100644
index 00..134d36066c
--- /dev/null
+++ b/drivers/gpio/mscc_sgpio.c
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs serial gpio driver
+ *
+ * Author:
+ *
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MSCC_SGPIOS_PER_BANK 32
+#define MSCC_SGPIO_BANK_DEPTH 4
+
+enum {
+ REG_INPUT_DATA,
+ REG_PORT_CONFIG,
+ REG_PORT_ENABLE,
+ REG_SIO_CONFIG,
+ REG_SIO_CLOCK,
+ MAXREG
+};
+
+struct mscc_sgpio_bf {
+ u8 beg;
+ u8 end;
+};
+
+struct mscc_sgpio_props {
+ u8 regoff[MAXREG];
+ struct mscc_sgpio_bf auto_repeat;
+ struct mscc_sgpio_bf port_width;
+ struct mscc_sgpio_bf clk_freq;
+ struct mscc_sgpio_bf bit_source;
+};
+
+#define __M(bf)GENMASK((bf).end, (bf).beg)
+#define __F(bf, x) (__M(bf) & ((x) << (bf).beg))
+#define __X(bf, x) (((x) >> (bf).beg) & GENMASK(((bf).end - (bf).beg), 0))
+
+#define MSCC_M_CFG_SIO_AUTO_REPEAT(p) BIT(p->props->auto_repeat.beg)
+#define MSCC_F_CFG_SIO_PORT_WIDTH(p, x)
__F(p->props->port_width, x)
+#define MSCC_M_CFG_SIO_PORT_WIDTH(p) __M(p->props->port_width)
+#define MSCC_F_CLOCK_SIO_CLK_FREQ(p, x)__F(p->props->clk_freq,
x)
+#define MSCC_M_CLOCK_SIO_CLK_FREQ(p) __M(p->props->clk_freq)
+#define MSCC_F_PORT_CFG_BIT_SOURCE(p, x) __F(p->props->bit_source, x)
+#define MSCC_X_PORT_CFG_BIT_SOURCE(p, x) __X(p->props->bit_source, x)
+
+const struct mscc_sgpio_props props_luton = {
+ .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
+ .auto_repeat = { 5, 5 },
+ .port_width = { 2, 3 },
+ .clk_freq= { 0, 11 },
+ .bit_source = { 0, 11 },
+};
+
+const struct mscc_sgpio_props props_ocelot = {
+ .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
+ .auto_repeat = { 10, 10 },
+ .port_width = { 7, 8 },
+ .clk_freq= { 8, 19 },
+ .bit_source = { 12, 23 },
+};
+
+struct mscc_sgpio_priv {
+ u32 bitcount;
+ u32 ports;
+ u32 clock;
+ u32 mode[MSCC_SGPIOS_PER_BANK];
+ u32 __iomem *regs;
+ const struct mscc_sgpio_props *props;
+};
+
+static inline u32 sgpio_readl(struct mscc_sgpio_priv *priv, u32 rno, u32 off)
+{
+ u32 __iomem *reg = >regs[priv->props->regoff[rno] + of
[U-Boot] [PATCH v2 0/6] mips: mscc: gpio: Add MSCC serial GPIO driver
This patch series add the GPIO device (SIO) in the MSCC VCoreIII-based SOCs, and enables it on the supported platforms. By using a serial interface, the SIO controller significantly extends the number of available GPIOs with a minimum number of additional pins on the device. The primary purpose of the SIO controller is to connect control signals from SFP modules and to act as an LED controller. This version adress comments from Daniel Schwierzeck and Linus Walleij . This is based off the u-boot-mips repository. v2 changes: - Extended the DT bindings documentation - Eliminated the need for the "mscc,sgpio-bitcount" property. - Using dev_read_u32_default() instead of fdtdec_get_int() - Using map_physmem() - Added MAINTAINERS entry for driver Lars Povlsen (6): mips: mscc_sgpio: Add the MSCC serial GPIO device (SIO) mips: mscc_sgpio: Add DT bindings documentation mips: luton: DT: Enable use of serial gpio mips: luton: Enable use of serial gpio for LED mips: ocelot: DT: Enable use of serial gpio mips: ocelot: Enable use of serial gpio for LED MAINTAINERS | 1 + arch/mips/dts/luton_pcb090.dts | 21 ++ arch/mips/dts/luton_pcb091.dts | 27 ++ arch/mips/dts/mscc,luton.dtsi| 20 ++ arch/mips/dts/mscc,ocelot.dtsi | 23 ++ arch/mips/dts/ocelot_pcb120.dts | 76 + arch/mips/dts/ocelot_pcb123.dts | 25 ++ board/mscc/luton/luton.c | 6 + board/mscc/ocelot/ocelot.c | 6 + configs/mscc_luton_defconfig | 3 + configs/mscc_ocelot_defconfig| 3 + doc/device-tree-bindings/gpio/mscc_sgpio.txt | 45 +++ drivers/gpio/Kconfig | 11 + drivers/gpio/Makefile| 1 + drivers/gpio/mscc_sgpio.c| 274 +++ 15 files changed, 542 insertions(+) create mode 100644 doc/device-tree-bindings/gpio/mscc_sgpio.txt create mode 100644 drivers/gpio/mscc_sgpio.c -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 6/6] mips: ocelot: Enable use of serial gpio for LED
This enables the use of the MSCC serial GPIO driver to control the LEDs on the MSCC VCoreIII 'ocelot' pcb123 and pcb120. Signed-off-by: Lars Povlsen --- board/mscc/ocelot/ocelot.c| 6 ++ configs/mscc_ocelot_defconfig | 3 +++ 2 files changed, 9 insertions(+) diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c index a557cacd1b..a05c308669 100644 --- a/board/mscc/ocelot/ocelot.c +++ b/board/mscc/ocelot/ocelot.c @@ -9,6 +9,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -56,6 +57,11 @@ int board_early_init_r(void) /* Address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + + /* LED setup */ + if (IS_ENABLED(CONFIG_LED)) + led_default_state(); + return 0; } diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig index 66451000d9..fb6a5bdc31 100644 --- a/configs/mscc_ocelot_defconfig +++ b/configs/mscc_ocelot_defconfig @@ -48,6 +48,9 @@ CONFIG_CLK=y CONFIG_DM_GPIO=y CONFIG_MTD=y CONFIG_MTD_SPI_NAND=y +CONFIG_MSCC_SGPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 5/6] mips: ocelot: DT: Enable use of serial gpio
From: Lars Povlsen
This enables the use of the MSCC serial GPIO driver on the MSCC
VCoreIII 'ocelot' SOC, and add gpio-leds nodes to the pcb123 and
pcb120 DT.
Signed-off-by: Lars Povlsen
---
arch/mips/dts/mscc,ocelot.dtsi | 25 +++
arch/mips/dts/ocelot_pcb120.dts | 76 +
arch/mips/dts/ocelot_pcb123.dts | 25 +++
3 files changed, 126 insertions(+)
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
index 87b4736285..e22bd2c949 100644
--- a/arch/mips/dts/mscc,ocelot.dtsi
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -37,6 +37,12 @@
clock-frequency = <5>;
};
+ sys_clk: sys-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000>;
+ };
+
ahb_clk: ahb-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -118,6 +124,11 @@
#gpio-cells = <2>;
gpio-ranges = < 0 0 22>;
+ sgpio_pins: sgpio-pins {
+ pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
+ function = "sg0";
+ };
+
uart_pins: uart-pins {
pins = "GPIO_6", "GPIO_7";
function = "uart";
@@ -148,5 +159,19 @@
function = "si";
};
};
+
+ sgpio: gpio@10700f8 {
+ compatible = "mscc,ocelot-sgpio";
+ status = "disabled";
+ clocks = <_clk>;
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ reg = <0x10700f8 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < 0 0 64>; /* 32* */
+ mscc,sgpio-frequency = <1250>;
+ mscc,sgpio-bitcount = <2>;
+ };
};
};
diff --git a/arch/mips/dts/ocelot_pcb120.dts b/arch/mips/dts/ocelot_pcb120.dts
index 47d305a614..658719e684 100644
--- a/arch/mips/dts/ocelot_pcb120.dts
+++ b/arch/mips/dts/ocelot_pcb120.dts
@@ -9,4 +9,80 @@
/ {
model = "Ocelot PCB120 Reference Board";
compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ poe_green {
+ label = "pcb120:green:poe";
+ gpios = < 44 1>; /* p12.1 */
+ default-state = "off";
+ };
+
+ poe_red {
+ label = "pcb120:red:poe";
+ gpios = < 12 1>; /* p12.0 */
+ default-state = "off";
+ };
+
+ alarm_green {
+ label = "pcb120:green:alarm";
+ gpios = < 45 1>; /* p13.1 */
+ default-state = "off";
+ };
+
+ alarm_red {
+ label = "pcb120:red:alarm";
+ gpios = < 13 1>; /* p13.0 */
+ default-state = "off";
+ };
+
+ dc_a_green {
+ label = "pcb120:green:dc_a";
+ gpios = < 46 1>; /* p14.1 */
+ default-state = "off";
+ };
+
+ dc_a_red {
+ label = "pcb120:red:dc_a";
+ gpios = < 14 1>; /* p14.0 */
+ default-state = "off";
+ };
+
+ dc_b_green {
+ label = "pcb120:green:dc_b";
+ gpios = < 47 1>; /* p15.1 */
+ default-state = "off";
+ };
+
+ dc_b_red {
+ label = "pcb120:red:dc_b";
+ gpios = < 15 1>; /* p15.0 */
+ default-state = "off";
+ };
+
+ status_green {
+ label = "pcb120:green:status";
+ gpios = < 48 1>; /* p16.1 */
+ default-state = "on";
+ };
+
+ status_red {
+ l
[U-Boot] [PATCH 4/6] mips: luton: Enable use of serial gpio for LED
This enables the use of the MSCC serial GPIO driver to control the LEDs on the MSCC VCoreIII 'luton' SoC. Signed-off-by: Lars Povlsen --- board/mscc/luton/luton.c | 6 ++ configs/mscc_luton_defconfig | 3 +++ 2 files changed, 9 insertions(+) diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c index b509b6beb3..807c717e33 100644 --- a/board/mscc/luton/luton.c +++ b/board/mscc/luton/luton.c @@ -5,6 +5,7 @@ #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -27,6 +28,11 @@ int board_early_init_r(void) /* Address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + + /* LED setup */ + if (IS_ENABLED(CONFIG_LED)) + led_default_state(); + return 0; } diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig index 03922f5379..0b3eb3865c 100644 --- a/configs/mscc_luton_defconfig +++ b/configs/mscc_luton_defconfig @@ -46,6 +46,9 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y CONFIG_DM_GPIO=y +CONFIG_MSCC_SGPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/6] mips: luton: DT: Enable use of serial gpio
From: Lars Povlsen
This enables the use of the MSCC serial GPIO driver, and add gpio-leds
nodes to the 'luton' pcb090 and pcb091 DT.
Signed-off-by: Lars Povlsen
---
arch/mips/dts/luton_pcb090.dts | 23 +++
arch/mips/dts/luton_pcb091.dts | 26 ++
arch/mips/dts/mscc,luton.dtsi | 23 +++
3 files changed, 72 insertions(+)
diff --git a/arch/mips/dts/luton_pcb090.dts b/arch/mips/dts/luton_pcb090.dts
index a3f8926ad9..15fdb2a1cb 100644
--- a/arch/mips/dts/luton_pcb090.dts
+++ b/arch/mips/dts/luton_pcb090.dts
@@ -18,6 +18,29 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ status_green {
+ label = "pcb090:green:status";
+ gpios = < 64 GPIO_ACTIVE_HIGH>; // p0.2
+ default-state = "on";
+ };
+
+ status_red {
+ label = "pcb090:red:status";
+ gpios = < 65 GPIO_ACTIVE_HIGH>; // p1.2
+ default-state = "off";
+ };
+ };
+};
+
+ {
+ status = "okay";
+ gpio-ranges = < 0 0 96>; // 32*
+ sgpio-ports = <0x>;
+ sgpio-bitcount = <3>;
};
{
diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts
index 74f9274c21..a94e888f98 100644
--- a/arch/mips/dts/luton_pcb091.dts
+++ b/arch/mips/dts/luton_pcb091.dts
@@ -18,6 +18,32 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ top_dimmer {
+ label = "pcb091:top:dimmer";
+ gpios = < 29 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+
+ status_green {
+ label = "pcb091:green:status";
+ gpios = < 26 GPIO_ACTIVE_HIGH>; /* p26.0 */
+ default-state = "on";
+ };
+
+ status_red {
+ label = "pcb091:red:status";
+ gpios = < 58 GPIO_ACTIVE_HIGH>; /* p26.1 */
+ default-state = "off";
+ };
+ };
+};
+
+ {
+ status = "okay";
};
{
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
index 6a4ad2a5be..d2b6843a7a 100644
--- a/arch/mips/dts/mscc,luton.dtsi
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -25,6 +25,11 @@
serial0 =
};
+ sys_clk: sys-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000>;
+ };
ahb_clk: ahb-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -57,11 +62,29 @@
#gpio-cells = <2>;
gpio-ranges = < 0 0 32>;
+ sgpio_pins: sgpio-pins {
+ pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
+ function = "sio";
+ };
uart_pins: uart-pins {
pins = "GPIO_30", "GPIO_31";
function = "uart";
};
+ };
+ sgpio: gpio@70130 {
+ compatible = "mscc,luton-sgpio";
+ status = "disabled";
+ clocks = <_clk>;
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ reg = <0x0070130 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < 0 0 64>; /* 32* */
+ mscc,sgpio-ports = <0xFFF000FF>;
+ mscc,sgpio-frequency = <1250>;
+ mscc,sgpio-bitcount = <2>;
};
gpio_spi_bitbang: gpio@1064 {
--
2.19.2
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[U-Boot] [PATCH 2/6] mips: mscc_sgpio: Add DT bindings documentation
From: Lars Povlsen
This add device tree binding documentation for the MSCC serial GPIO
driver.
Signed-off-by: Lars Povlsen
---
doc/device-tree-bindings/gpio/mscc_sgpio.txt | 39
1 file changed, 39 insertions(+)
create mode 100644 doc/device-tree-bindings/gpio/mscc_sgpio.txt
diff --git a/doc/device-tree-bindings/gpio/mscc_sgpio.txt
b/doc/device-tree-bindings/gpio/mscc_sgpio.txt
new file mode 100644
index 00..24e6aa345e
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/mscc_sgpio.txt
@@ -0,0 +1,39 @@
+MSCC Serial GPIO driver
+
+Required properties:
+- compatible : "mscc,luton-sgpio" or "mscc,ocelot-sgpio"
+- clock: Reference clock used to generate clock divider setting. See
+ mscc,sgpio-frequency property.
+- reg : Physical base address and length of the controller's registers.
+- #gpio-cells : Should be two. The first cell is the pin number and the
+ second cell is used to specify optional parameters:
+ - bit 0 specifies polarity (0 for normal, 1 for inverted)
+- gpio-controller : Marks the device node as a GPIO controller.
+- gpio-ranges: The 4th cell will typically be 32*
+
+Optional properties:
+- mscc,sgpio-frequency: The frequency at which the serial bitstream is
+ generated and sampled. Default: 1250 (Hz).
+- mscc,sgpio-bitcount: The number of bits enabled per
+ port. (1-4). Default: 2.
+- mscc,sgpio-ports: A bitmask (32 bits) of which ports are enabled in
+ the serialized gpio stream. Default: 0x.
+
+Typically the pinctrl-0 and pinctrl-names properties will also be
+present to enable the use of the SIO CLK, LD, DI and DO for some
+regular GPIO pins.
+
+Example:
+
+sgpio: gpio@10700f8 {
+ compatible = "mscc,ocelot-sgpio";
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ reg = <0x10700f8 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < 0 0 64>; // 32*
+ mscc,sgpio-frequency = <12500>;
+ mscc,sgpio-bitcount = <2>;
+ mscc,sgpio-ports = <0x000F>;
+};
--
2.19.2
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[U-Boot] [PATCH 1/6] mips: mscc_sgpio: Add the MSCC serial GPIO device (SIO)
This add support for the the MSCC serial GPIO driver in MSCC
VCoreIII-based SOCs.
By using a serial interface, the SIO controller significantly extends
the number of available GPIOs with a minimum number of additional pins
on the device. The primary purpose of the SIO controller is to connect
control signals from SFP modules and to act as an LED controller.
This adds the base driver.
Signed-off-by: Lars Povlsen
---
drivers/gpio/Kconfig | 11 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/mscc_sgpio.c | 252 ++
3 files changed, 264 insertions(+)
create mode 100644 drivers/gpio/mscc_sgpio.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c8c6c60623..aa55ff43c4 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -106,6 +106,17 @@ config MSCC_BITBANG_SPI_GPIO
Support controlling the GPIO used for SPI bitbang by software. Can
be used by the VCoreIII SoCs, but it was mainly useful for Luton.
+config MSCC_SGPIO
+ bool "Microsemi Serial GPIO driver"
+ depends on DM_GPIO && SOC_VCOREIII
+ help
+ Support for the VCoreIII SoC serial GPIO device. By using a
+ serial interface, the SIO controller significantly extends
+ the number of available GPIOs with a minimum number of
+ additional pins on the device. The primary purpose of the
+ SIO controller is to connect control signals from SFP
+ modules and to act as an LED controller.
+
config MSM_GPIO
bool "Qualcomm GPIO driver"
depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 61feda1537..be2b3c792f 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -60,3 +60,4 @@ obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o
obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o
obj-$(CONFIG_MSCC_BITBANG_SPI_GPIO)+= gpio-mscc-bitbang-spi.o
+obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o
diff --git a/drivers/gpio/mscc_sgpio.c b/drivers/gpio/mscc_sgpio.c
new file mode 100644
index 00..28f60498fd
--- /dev/null
+++ b/drivers/gpio/mscc_sgpio.c
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs serial gpio driver
+ *
+ * Author:
+ * License: Dual MIT/GPL
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MSCC_SGPIOS_PER_BANK 32
+#define MSCC_SGPIO_BANK_DEPTH 4
+
+enum {
+ REG_INPUT_DATA,
+ REG_PORT_CONFIG,
+ REG_PORT_ENABLE,
+ REG_SIO_CONFIG,
+ REG_SIO_CLOCK,
+ MAXREG
+};
+
+struct mscc_sgpio_bf {
+ u8 beg;
+ u8 end;
+};
+
+struct mscc_sgpio_props {
+ u8 regoff[MAXREG];
+ struct mscc_sgpio_bf auto_repeat;
+ struct mscc_sgpio_bf port_width;
+ struct mscc_sgpio_bf clk_freq;
+ struct mscc_sgpio_bf bit_source;
+};
+
+#define __M(bf)GENMASK((bf).end, (bf).beg)
+#define __F(bf, x) (__M(bf) & ((x) << (bf).beg))
+#define __X(bf, x) (((x) >> (bf).beg) & GENMASK(((bf).end - (bf).beg), 0))
+
+#define MSCC_M_CFG_SIO_AUTO_REPEAT(p) BIT(p->props->auto_repeat.beg)
+#define MSCC_F_CFG_SIO_PORT_WIDTH(p, x)
__F(p->props->port_width, x)
+#define MSCC_M_CFG_SIO_PORT_WIDTH(p) __M(p->props->port_width)
+#define MSCC_F_CLOCK_SIO_CLK_FREQ(p, x)__F(p->props->clk_freq,
x)
+#define MSCC_M_CLOCK_SIO_CLK_FREQ(p) __M(p->props->clk_freq)
+#define MSCC_F_PORT_CFG_BIT_SOURCE(p, x) __F(p->props->bit_source, x)
+#define MSCC_X_PORT_CFG_BIT_SOURCE(p, x) __X(p->props->bit_source, x)
+
+const struct mscc_sgpio_props props_luton = {
+ .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
+ .auto_repeat = { 5, 5 },
+ .port_width = { 2, 3 },
+ .clk_freq= { 0, 11 },
+ .bit_source = { 0, 11 },
+};
+
+const struct mscc_sgpio_props props_ocelot = {
+ .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
+ .auto_repeat = { 10, 10 },
+ .port_width = { 7, 8 },
+ .clk_freq= { 8, 19 },
+ .bit_source = { 12, 23 },
+};
+
+struct mscc_sgpio_priv {
+ u32 bitcount;
+ u32 ports;
+ u32 clock;
+ u32 mode[MSCC_SGPIOS_PER_BANK];
+ u32 __iomem *regs;
+ const struct mscc_sgpio_props *props;
+};
+
+static inline u32 sgpio_readl(struct mscc_sgpio_priv *priv, u32 rno, u32 off)
+{
+ u32 __iomem *reg = >regs[priv->props->regoff[rno] + off];
+
+ return readl(reg);
+}
+
+static inline void sgpio_writel(struct mscc_sgpio_priv *priv,
+ u32 val, u32 rno, u32 off)
+{
+ u32 __iomem *reg = >regs[priv->props->regoff[rno] + off];
+
+ writel(val, reg);
+}
+
+static void sgpio_clrsetbits(struct mscc_sgpio_priv *priv,
+
[U-Boot] [PATCH 0/6] mips: mscc: gpio: Add MSCC serial GPIO driver
This patch series add the GPIO device (SIO) in the MSCC VCoreIII-based SOCs, and enables it on the supported platforms. Lars Povlsen (6): mips: mscc_sgpio: Add the MSCC serial GPIO device (SIO) mips: mscc_sgpio: Add DT bindings documentation mips: luton: DT: Enable use of serial gpio mips: luton: Enable use of serial gpio for LED mips: ocelot: DT: Enable use of serial gpio mips: ocelot: Enable use of serial gpio for LED arch/mips/dts/luton_pcb090.dts | 23 ++ arch/mips/dts/luton_pcb091.dts | 26 ++ arch/mips/dts/mscc,luton.dtsi| 23 ++ arch/mips/dts/mscc,ocelot.dtsi | 25 ++ arch/mips/dts/ocelot_pcb120.dts | 76 ++ arch/mips/dts/ocelot_pcb123.dts | 25 ++ board/mscc/luton/luton.c | 6 + board/mscc/ocelot/ocelot.c | 6 + configs/mscc_luton_defconfig | 3 + configs/mscc_ocelot_defconfig| 3 + doc/device-tree-bindings/gpio/mscc_sgpio.txt | 39 +++ drivers/gpio/Kconfig | 11 + drivers/gpio/Makefile| 1 + drivers/gpio/mscc_sgpio.c| 252 +++ 14 files changed, 519 insertions(+) create mode 100644 doc/device-tree-bindings/gpio/mscc_sgpio.txt create mode 100644 drivers/gpio/mscc_sgpio.c -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 4/4] mips: mscc: luton+ocelot: Remove board config options, do probing
As we are moving to multi-dtb and board detection, remove static board
config options, and introduce board probing instead.
Luton: This add single-binary support for the two MSCC luton-based
reference boards - pcb090 and pcb091. The SoC chip ID is used to
determine the board type.
Ocelot: This add single-binary support for the two MSCC ocelot-based
reference boards - pcb120 and pcb123. The PHY ids on specific ports
are used to determine the board type.
Signed-off-by: Lars Povlsen
---
arch/mips/dts/Makefile| 2 +
arch/mips/mach-mscc/Kconfig | 38
.../include/mach/luton/luton_devcpu_gcb.h | 2 +
board/mscc/luton/luton.c | 46 --
board/mscc/ocelot/ocelot.c| 52 ++--
configs/mscc_luton_defconfig | 7 ++-
configs/mscc_ocelot_defconfig | 7 ++-
configs/mscc_ocelot_pcb120_defconfig | 60 ---
include/configs/vcoreiii.h| 2 +
9 files changed, 113 insertions(+), 103 deletions(-)
delete mode 100644 configs/mscc_ocelot_pcb120_defconfig
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 647d2bf0d5..b61afe6504 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -17,6 +17,8 @@ dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) +=
netgear,dgnd3700v2.dtb
dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f...@st1704.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
+dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
+dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
targets += $(dtb-y)
diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
index 0e35b77c9d..37ef432e48 100644
--- a/arch/mips/mach-mscc/Kconfig
+++ b/arch/mips/mach-mscc/Kconfig
@@ -15,47 +15,29 @@ config SOC_VCOREIII
config SYS_SOC
default "mscc"
+choice
+
+ prompt "SOC Family Variant"
+
config SOC_OCELOT
- bool
+ bool "Ocelot SOC Family"
select SOC_VCOREIII
+ select DESIGNWARE_SPI
help
This supports MSCC Ocelot family of SOCs.
config SOC_LUTON
- bool
+ bool "Luton SOC Family"
select SOC_VCOREIII
+ select MSCC_BITBANG_SPI_GPIO
help
This supports MSCC Luton family of SOCs.
+endchoice
+
config SYS_CONFIG_NAME
default "vcoreiii"
-choice
- prompt "Board select"
-
-config TARGET_OCELOT_PCB120
- bool "MSCC PCB120 Reference Board (aka VSC5635EV)"
- select SOC_OCELOT
- help
- When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
- ocelot_pcb120
-
-config TARGET_OCELOT_PCB123
- bool "MSCC PCB123 Reference Board (aka VSC7514EV))"
- select SOC_OCELOT
- help
- When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
- ocelot_pcb123
-
-config TARGET_LUTON_PCB091
- bool "MSCC PCB091 Reference Board"
- select SOC_LUTON
- select MSCC_BITBANG_SPI_GPIO
- help
- When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
- luton_pcb091
-endchoice
-
choice
prompt "DDR type"
diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
index a06cf819b0..a74a68593d 100644
--- a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
+++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
@@ -13,4 +13,6 @@
#define GPIO_ALT(x)(0x88 + 4 * (x))
+#define CHIP_ID(0x08)
+
#endif
diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c
index 41fc6d56a7..b509b6beb3 100644
--- a/board/mscc/luton/luton.c
+++ b/board/mscc/luton/luton.c
@@ -6,15 +6,18 @@
#include
#include
-#define MSCC_GPIO_ALT0 0x88
-#define MSCC_GPIO_ALT1 0x8C
-
DECLARE_GLOBAL_DATA_PTR;
+enum {
+ BOARD_TYPE_PCB090 = 0xAABBCD00,
+ BOARD_TYPE_PCB091,
+};
+
void board_debug_uart_init(void)
{
/* too early for the pinctrl driver, so configure the UART pins here */
- setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(30) | BIT(31));
+ mscc_gpio_set_alternate(30, 1);
+ mscc_gpio_set_alternate(31, 1);
}
int board_early_init_r(void)
@@ -26,3 +29,38 @@ int board_early_init_r(void)
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
return 0;
}
+
+static void do_board_detect(void)
+{
+ u32 chipid = (readl(BASE_DEVCPU_GCB + CHIP_ID) >> 12) & 0x;
+
+ if (chipid == 0x7428 || chipid == 0x7424)
+ gd->board_type = BOARD_TYPE_PCB091;// Lu10
+ else
+ gd->board_type = BOARD_TYPE_PCB090;// Lu26
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config
[U-Boot] [PATCH v2 3/4] mips: luton: DT: Add pcb090
This prepares individual device trees for MSCC luton-based reference
boards - pcb090 and pcb091.
Note: Even though the devices trees are quite common, they will differ
significantly in coming patches.
Signed-off-by: Lars Povlsen
---
arch/mips/dts/luton_pcb090.dts | 36 ++
1 file changed, 36 insertions(+)
create mode 100644 arch/mips/dts/luton_pcb090.dts
diff --git a/arch/mips/dts/luton_pcb090.dts b/arch/mips/dts/luton_pcb090.dts
new file mode 100644
index 00..a3f8926ad9
--- /dev/null
+++ b/arch/mips/dts/luton_pcb090.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,luton.dtsi"
+
+/ {
+ model = "Luton26 PCB090 Reference Board";
+ compatible = "mscc,luton-pcb090", "mscc,luton";
+
+ aliases {
+ serial0 =
+ spi0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ spi-flash@0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <1800>; /* input clock */
+ reg = <0>; /* CS0 */
+ spi-cs-high;
+ };
+};
+
--
2.19.2
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[U-Boot] [PATCH v2 2/4] mips: mscc: Add generic GPIO control utility function
The GPIO control function can be used for controlling alternate
functions associated with a GPIO.
Signed-off-by: Lars Povlsen
---
arch/mips/mach-mscc/Makefile | 2 +-
arch/mips/mach-mscc/gpio.c| 33 +++
arch/mips/mach-mscc/include/mach/common.h | 2 ++
.../include/mach/luton/luton_devcpu_gcb.h | 2 ++
.../include/mach/ocelot/ocelot_devcpu_gcb.h | 2 ++
5 files changed, 40 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/mach-mscc/gpio.c
diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile
index 300c88b5cd..44538b7118 100644
--- a/arch/mips/mach-mscc/Makefile
+++ b/arch/mips/mach-mscc/Makefile
@@ -2,5 +2,5 @@
CFLAGS_cpu.o += -finline-limit=64000
-obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o
+obj-y += cpu.o dram.o reset.o phy.o gpio.o lowlevel_init.o
obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o
diff --git a/arch/mips/mach-mscc/gpio.c b/arch/mips/mach-mscc/gpio.c
new file mode 100644
index 00..5e3a53372d
--- /dev/null
+++ b/arch/mips/mach-mscc/gpio.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include
+
+void mscc_gpio_set_alternate(int gpio, int mode)
+{
+ u32 mask = BIT(gpio);
+ u32 val0, val1;
+
+ val0 = readl(BASE_DEVCPU_GCB + GPIO_ALT(0));
+ val1 = readl(BASE_DEVCPU_GCB + GPIO_ALT(1));
+
+ if (mode == 1) {
+ val0 |= mask;
+ val1 &= ~mask;
+ } else if (mode == 2) {
+ val0 &= ~mask;
+ val1 |= mask;
+ } else if (mode == 3) {
+ val0 |= mask;
+ val1 |= mask;
+ } else {
+ val0 &= ~mask;
+ val1 &= ~mask;
+ }
+
+ writel(val0, BASE_DEVCPU_GCB + GPIO_ALT(0));
+ writel(val1, BASE_DEVCPU_GCB + GPIO_ALT(1));
+}
diff --git a/arch/mips/mach-mscc/include/mach/common.h
b/arch/mips/mach-mscc/include/mach/common.h
index 92a055561e..d18ae78bfd 100644
--- a/arch/mips/mach-mscc/include/mach/common.h
+++ b/arch/mips/mach-mscc/include/mach/common.h
@@ -45,4 +45,6 @@ int mscc_phy_wr(u32 miim_controller,
u8 addr,
u16 value);
+void mscc_gpio_set_alternate(int gpio, int mode);
+
#endif /* __ASM_MACH_COMMON_H */
diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
index 8c0b612325..a06cf819b0 100644
--- a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
+++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
@@ -11,4 +11,6 @@
#define PERF_SOFT_RST_SOFT_SWC_RSTBIT(1)
#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0)
+#define GPIO_ALT(x)(0x88 + 4 * (x))
+
#endif
diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
index f8aa97ba26..d3a76412e2 100644
--- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
+++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
@@ -18,4 +18,6 @@
#define PERF_GPIO_OE 0x44
+#define GPIO_ALT(x)(0x54 + 4 * (x))
+
#endif
--
2.19.2
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[U-Boot] [PATCH v2 1/4] mips: mscc: Add generic PHY MIIM utility functions
The PHY MIIM utility functions can/will be used for board detection purposes. Signed-off-by: Lars Povlsen --- arch/mips/mach-mscc/Makefile | 2 +- arch/mips/mach-mscc/include/mach/common.h | 20 + .../mach/luton/luton_devcpu_gcb_miim_regs.h | 26 +++ .../mach/ocelot/ocelot_devcpu_gcb_miim_regs.h | 25 +++ arch/mips/mach-mscc/phy.c | 73 +++ 5 files changed, 145 insertions(+), 1 deletion(-) create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h create mode 100644 arch/mips/mach-mscc/phy.c diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile index 6c60f26ca4..300c88b5cd 100644 --- a/arch/mips/mach-mscc/Makefile +++ b/arch/mips/mach-mscc/Makefile @@ -2,5 +2,5 @@ CFLAGS_cpu.o += -finline-limit=64000 -obj-y += cpu.o dram.o reset.o lowlevel_init.o +obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o diff --git a/arch/mips/mach-mscc/include/mach/common.h b/arch/mips/mach-mscc/include/mach/common.h index 931ecd7985..92a055561e 100644 --- a/arch/mips/mach-mscc/include/mach/common.h +++ b/arch/mips/mach-mscc/include/mach/common.h @@ -9,10 +9,12 @@ #if defined(CONFIG_SOC_OCELOT) #include #include +#include #include #elif defined(CONFIG_SOC_LUTON) #include #include +#include #include #else #error Unsupported platform @@ -25,4 +27,22 @@ #define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */ +/* Common utility functions */ + +int mscc_phy_rd_wr(u8 read, + u32 miim_controller, + u8 miim_addr, + u8 addr, + u16 *value); + +int mscc_phy_rd(u32 miim_controller, + u8 miim_addr, + u8 addr, + u16 *value); + +int mscc_phy_wr(u32 miim_controller, + u8 miim_addr, + u8 addr, + u16 value); + #endif /* __ASM_MACH_COMMON_H */ diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h new file mode 100644 index 00..2303734894 --- /dev/null +++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Microsemi Ocelot Switch driver + * + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef _MSCC_LUTON_MIIM_REGS_H_ +#define _MSCC_LUTON_MIIM_REGS_H_ + +#define MIIM_MII_STATUS(gi) (0xa0 + (gi * 36)) +#define MIIM_MII_CMD(gi)(0xa8 + (gi * 36)) +#define MIIM_MII_DATA(gi) (0xac + (gi * 36)) + +#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) (x ? BIT(3) : 0) + +#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x)(x ? BIT(31) : 0) +#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & (x << 25)) +#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & (x << 20)) +#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & (x << 4)) +#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & (x << 1)) + +#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16) +#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) ((x >> 0) & GENMASK(15, 0)) + +#endif diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h new file mode 100644 index 00..4ad92214a3 --- /dev/null +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_ +#define _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_ + +#define MIIM_MII_STATUS(gi) (0x9c + (gi * 36)) +#define MIIM_MII_CMD(gi)(0xa4 + (gi * 36)) +#define MIIM_MII_DATA(gi) (0xa8 + (gi * 36)) + +#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0) + +#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x)((x) ? BIT(31) : 0) +#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25)) +#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20)) +#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4)) +#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1)) +#define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0) + +#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16) +#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0)) + +#endif diff --git a/arch/mips/mach-mscc/phy.c b/arch/mips/mach-mscc/phy.c new file mode 100644 index 00..add6280e38 --- /dev/null +++ b/arch/mips/mach-mscc/phy.c @@ -0,0 +1,73 @@ +// SPDX-License-Identi
[U-Boot] [PATCH v2 0/4] mips: mscc: Add multi-dtb support to luton+ocelot
This patch series add support for using multi-dtb on the MSCC luton and ocelot SOC reference boards. The appropriate board will be determined during startup, and the right DT will be selected. The patch is based off u-boot-mips repo. v1 => v2 changes: - squashed first and two last patches for bisectability Lars Povlsen (4): mips: mscc: Add generic PHY MIIM utility functions mips: mscc: Add generic GPIO control utility function mips: luton: DT: Add pcb090 mips: mscc: luton+ocelot: Remove board config options, do probing arch/mips/dts/Makefile| 2 + arch/mips/dts/luton_pcb090.dts| 36 + arch/mips/mach-mscc/Kconfig | 38 +++--- arch/mips/mach-mscc/Makefile | 2 +- arch/mips/mach-mscc/gpio.c| 33 + arch/mips/mach-mscc/include/mach/common.h | 22 ++ .../include/mach/luton/luton_devcpu_gcb.h | 4 + .../mach/luton/luton_devcpu_gcb_miim_regs.h | 26 +++ .../include/mach/ocelot/ocelot_devcpu_gcb.h | 2 + .../mach/ocelot/ocelot_devcpu_gcb_miim_regs.h | 25 +++ arch/mips/mach-mscc/phy.c | 73 +++ board/mscc/luton/luton.c | 46 +++- board/mscc/ocelot/ocelot.c| 52 +++-- configs/mscc_luton_defconfig | 7 +- configs/mscc_ocelot_defconfig | 7 +- configs/mscc_ocelot_pcb120_defconfig | 60 --- include/configs/vcoreiii.h| 2 + 17 files changed, 333 insertions(+), 104 deletions(-) create mode 100644 arch/mips/dts/luton_pcb090.dts create mode 100644 arch/mips/mach-mscc/gpio.c create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h create mode 100644 arch/mips/mach-mscc/phy.c delete mode 100644 configs/mscc_ocelot_pcb120_defconfig -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 6/6] mips: ocelot: Add multi-dtb support
This add single-binary support for the two MSCC ocelot-based reference
boards - pcb120 and pcb123.
The PHY ids on specific ports are used to determine the board type.
Signed-off-by: Lars Povlsen
---
arch/mips/dts/Makefile | 1 +
board/mscc/ocelot/ocelot.c | 52 +---
configs/mscc_ocelot_defconfig| 7 ++--
configs/mscc_ocelot_pcb120_defconfig | 60
4 files changed, 51 insertions(+), 69 deletions(-)
delete mode 100644 configs/mscc_ocelot_pcb120_defconfig
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 3d436b2248..b61afe6504 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -18,6 +18,7 @@ dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f...@st1704.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
+dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
targets += $(dtb-y)
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
index d521a61957..a557cacd1b 100644
--- a/board/mscc/ocelot/ocelot.c
+++ b/board/mscc/ocelot/ocelot.c
@@ -12,16 +12,18 @@
DECLARE_GLOBAL_DATA_PTR;
-#define MSCC_GPIO_ALT0 0x54
-#define MSCC_GPIO_ALT1 0x58
+enum {
+ BOARD_TYPE_PCB120 = 0xAABBCC00,
+ BOARD_TYPE_PCB123,
+};
void external_cs_manage(struct udevice *dev, bool enable)
{
u32 cs = spi_chip_select(dev);
/* IF_SI0_OWNER, select the owner of the SI interface
* Encoding: 0: SI Slave
-* 1: SI Boot Master
-* 2: SI Master Controller
+* 1: SI Boot Master
+* 2: SI Master Controller
*/
if (!enable) {
writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
@@ -40,8 +42,8 @@ void external_cs_manage(struct udevice *dev, bool enable)
void board_debug_uart_init(void)
{
/* too early for the pinctrl driver, so configure the UART pins here */
- setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(6) | BIT(7));
- clrbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT1, BIT(6) | BIT(7));
+ mscc_gpio_set_alternate(6, 1);
+ mscc_gpio_set_alternate(7, 1);
}
int board_early_init_r(void)
@@ -56,3 +58,41 @@ int board_early_init_r(void)
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
return 0;
}
+
+static void do_board_detect(void)
+{
+ u16 dummy = 0;
+
+ /* Enable MIIM */
+ mscc_gpio_set_alternate(14, 1);
+ mscc_gpio_set_alternate(15, 1);
+ if (mscc_phy_rd(1, 0, 0, ) == 0)
+ gd->board_type = BOARD_TYPE_PCB120;
+ else
+ gd->board_type = BOARD_TYPE_PCB123;
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ if (gd->board_type == BOARD_TYPE_PCB120 &&
+ strcmp(name, "ocelot_pcb120") == 0)
+ return 0;
+
+ if (gd->board_type == BOARD_TYPE_PCB123 &&
+ strcmp(name, "ocelot_pcb123") == 0)
+ return 0;
+
+ return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+ do_board_detect();
+ fdtdec_setup();
+
+ return 0;
+}
+#endif
diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig
index 5fa74db2ff..66451000d9 100644
--- a/configs/mscc_ocelot_defconfig
+++ b/configs/mscc_ocelot_defconfig
@@ -5,7 +5,6 @@ CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0x7010
CONFIG_DEBUG_UART_CLOCK=25000
CONFIG_ARCH_MSCC=y
-CONFIG_TARGET_OCELOT_PCB123=y
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
@@ -14,7 +13,7 @@ CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_LOGLEVEL=7
CONFIG_DISPLAY_CPUINFO=y
-CONFIG_SYS_PROMPT="pcb123 # "
+CONFIG_SYS_PROMPT="ocelot # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_ELF is not set
@@ -40,6 +39,9 @@ CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb123"
+CONFIG_OF_LIST="ocelot_pcb120 ocelot_pcb123"
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
@@ -63,5 +65,4 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
-CONFIG_DESIGNWARE_SPI=y
CONFIG_LZMA=y
diff --git a/configs/mscc_ocelot_pcb120_defconfig
b/configs/mscc_ocelot_pcb120_defconfig
deleted file mode 100644
index c5a9f96977..00
--- a/configs/mscc_ocelot_pcb120_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0x4000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ARCH_MSCC=y
-CONFIG_SYS_LITTLE_ENDIAN=y
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115
[U-Boot] [PATCH 5/6] mips: luton: Add multi-dtb support
This add single-binary support for the two MSCC luton-based reference
boards - pcb090 and pcb091.
Signed-off-by: Lars Povlsen
---
arch/mips/dts/Makefile| 1 +
.../include/mach/luton/luton_devcpu_gcb.h | 2 +
board/mscc/luton/luton.c | 46 +--
configs/mscc_luton_defconfig | 7 ++-
include/configs/vcoreiii.h| 2 +
5 files changed, 52 insertions(+), 6 deletions(-)
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 647d2bf0d5..3d436b2248 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -17,6 +17,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) +=
netgear,dgnd3700v2.dtb
dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f...@st1704.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
+dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
targets += $(dtb-y)
diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
index a06cf819b0..a74a68593d 100644
--- a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
+++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
@@ -13,4 +13,6 @@
#define GPIO_ALT(x)(0x88 + 4 * (x))
+#define CHIP_ID(0x08)
+
#endif
diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c
index 41fc6d56a7..b509b6beb3 100644
--- a/board/mscc/luton/luton.c
+++ b/board/mscc/luton/luton.c
@@ -6,15 +6,18 @@
#include
#include
-#define MSCC_GPIO_ALT0 0x88
-#define MSCC_GPIO_ALT1 0x8C
-
DECLARE_GLOBAL_DATA_PTR;
+enum {
+ BOARD_TYPE_PCB090 = 0xAABBCD00,
+ BOARD_TYPE_PCB091,
+};
+
void board_debug_uart_init(void)
{
/* too early for the pinctrl driver, so configure the UART pins here */
- setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(30) | BIT(31));
+ mscc_gpio_set_alternate(30, 1);
+ mscc_gpio_set_alternate(31, 1);
}
int board_early_init_r(void)
@@ -26,3 +29,38 @@ int board_early_init_r(void)
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
return 0;
}
+
+static void do_board_detect(void)
+{
+ u32 chipid = (readl(BASE_DEVCPU_GCB + CHIP_ID) >> 12) & 0x;
+
+ if (chipid == 0x7428 || chipid == 0x7424)
+ gd->board_type = BOARD_TYPE_PCB091;// Lu10
+ else
+ gd->board_type = BOARD_TYPE_PCB090;// Lu26
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ if (gd->board_type == BOARD_TYPE_PCB090 &&
+ strcmp(name, "luton_pcb090") == 0)
+ return 0;
+
+ if (gd->board_type == BOARD_TYPE_PCB091 &&
+ strcmp(name, "luton_pcb091") == 0)
+ return 0;
+
+ return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+ do_board_detect();
+ fdtdec_setup();
+
+ return 0;
+}
+#endif
diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig
index d7476c4863..03922f5379 100644
--- a/configs/mscc_luton_defconfig
+++ b/configs/mscc_luton_defconfig
@@ -5,7 +5,7 @@ CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0x7010
CONFIG_DEBUG_UART_CLOCK=20833
CONFIG_ARCH_MSCC=y
-CONFIG_TARGET_LUTON_PCB091=y
+CONFIG_SOC_LUTON=y
CONFIG_DDRTYPE_MT47H128M8HQ=y
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_MIPS_BOOT_FDT=y
@@ -16,7 +16,7 @@ CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_LOGLEVEL=7
CONFIG_DISPLAY_CPUINFO=y
-CONFIG_SYS_PROMPT="pcb091 # "
+CONFIG_SYS_PROMPT="luton # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_ELF is not set
@@ -39,6 +39,9 @@ CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m@1m(linux)"
# CONFIG_ISO_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091"
+CONFIG_OF_LIST="luton_pcb090 luton_pcb091"
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h
index df89cdaebf..4ea5f40ec5 100644
--- a/include/configs/vcoreiii.h
+++ b/include/configs/vcoreiii.h
@@ -22,6 +22,8 @@
#endif
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
+#define CONFIG_BOARD_TYPES
+
#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
#define CONFIG_ENV_OFFSET (1024 * 1024)
#define CONFIG_ENV_SIZE(256 * 1024)
--
2.19.2
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[U-Boot] [PATCH 4/6] mips: luton: DT: Add pcb090
This prepares individual device trees for MSCC luton-based reference
boards - pcb090 and pcb091.
Note: Even though the devices trees are quite common, they will differ
significantly in coming patches.
Signed-off-by: Lars Povlsen
---
arch/mips/dts/luton_pcb090.dts | 36 ++
1 file changed, 36 insertions(+)
create mode 100644 arch/mips/dts/luton_pcb090.dts
diff --git a/arch/mips/dts/luton_pcb090.dts b/arch/mips/dts/luton_pcb090.dts
new file mode 100644
index 00..a3f8926ad9
--- /dev/null
+++ b/arch/mips/dts/luton_pcb090.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,luton.dtsi"
+
+/ {
+ model = "Luton26 PCB090 Reference Board";
+ compatible = "mscc,luton-pcb090", "mscc,luton";
+
+ aliases {
+ serial0 =
+ spi0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ spi-flash@0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <1800>; /* input clock */
+ reg = <0>; /* CS0 */
+ spi-cs-high;
+ };
+};
+
--
2.19.2
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[U-Boot] [PATCH 3/6] mips: mscc: Add generic GPIO control utility function
The GPIO control function can be used for controlling alternate
functions associated with a GPIO.
Signed-off-by: Lars Povlsen
---
arch/mips/mach-mscc/Makefile | 2 +-
arch/mips/mach-mscc/gpio.c| 33 +++
arch/mips/mach-mscc/include/mach/common.h | 2 ++
.../include/mach/luton/luton_devcpu_gcb.h | 2 ++
.../include/mach/ocelot/ocelot_devcpu_gcb.h | 2 ++
5 files changed, 40 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/mach-mscc/gpio.c
diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile
index 300c88b5cd..44538b7118 100644
--- a/arch/mips/mach-mscc/Makefile
+++ b/arch/mips/mach-mscc/Makefile
@@ -2,5 +2,5 @@
CFLAGS_cpu.o += -finline-limit=64000
-obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o
+obj-y += cpu.o dram.o reset.o phy.o gpio.o lowlevel_init.o
obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o
diff --git a/arch/mips/mach-mscc/gpio.c b/arch/mips/mach-mscc/gpio.c
new file mode 100644
index 00..5e3a53372d
--- /dev/null
+++ b/arch/mips/mach-mscc/gpio.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include
+
+void mscc_gpio_set_alternate(int gpio, int mode)
+{
+ u32 mask = BIT(gpio);
+ u32 val0, val1;
+
+ val0 = readl(BASE_DEVCPU_GCB + GPIO_ALT(0));
+ val1 = readl(BASE_DEVCPU_GCB + GPIO_ALT(1));
+
+ if (mode == 1) {
+ val0 |= mask;
+ val1 &= ~mask;
+ } else if (mode == 2) {
+ val0 &= ~mask;
+ val1 |= mask;
+ } else if (mode == 3) {
+ val0 |= mask;
+ val1 |= mask;
+ } else {
+ val0 &= ~mask;
+ val1 &= ~mask;
+ }
+
+ writel(val0, BASE_DEVCPU_GCB + GPIO_ALT(0));
+ writel(val1, BASE_DEVCPU_GCB + GPIO_ALT(1));
+}
diff --git a/arch/mips/mach-mscc/include/mach/common.h
b/arch/mips/mach-mscc/include/mach/common.h
index 92a055561e..d18ae78bfd 100644
--- a/arch/mips/mach-mscc/include/mach/common.h
+++ b/arch/mips/mach-mscc/include/mach/common.h
@@ -45,4 +45,6 @@ int mscc_phy_wr(u32 miim_controller,
u8 addr,
u16 value);
+void mscc_gpio_set_alternate(int gpio, int mode);
+
#endif /* __ASM_MACH_COMMON_H */
diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
index 8c0b612325..a06cf819b0 100644
--- a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
+++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
@@ -11,4 +11,6 @@
#define PERF_SOFT_RST_SOFT_SWC_RSTBIT(1)
#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0)
+#define GPIO_ALT(x)(0x88 + 4 * (x))
+
#endif
diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
index f8aa97ba26..d3a76412e2 100644
--- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
+++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
@@ -18,4 +18,6 @@
#define PERF_GPIO_OE 0x44
+#define GPIO_ALT(x)(0x54 + 4 * (x))
+
#endif
--
2.19.2
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[U-Boot] [PATCH 2/6] mips: mscc: Add generic PHY MIIM utility functions
The PHY MIIM utility functions can/will be used for board detection purposes. Signed-off-by: Lars Povlsen --- arch/mips/mach-mscc/Makefile | 2 +- arch/mips/mach-mscc/include/mach/common.h | 20 + .../mach/luton/luton_devcpu_gcb_miim_regs.h | 26 +++ .../mach/ocelot/ocelot_devcpu_gcb_miim_regs.h | 25 +++ arch/mips/mach-mscc/phy.c | 73 +++ 5 files changed, 145 insertions(+), 1 deletion(-) create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h create mode 100644 arch/mips/mach-mscc/phy.c diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile index 6c60f26ca4..300c88b5cd 100644 --- a/arch/mips/mach-mscc/Makefile +++ b/arch/mips/mach-mscc/Makefile @@ -2,5 +2,5 @@ CFLAGS_cpu.o += -finline-limit=64000 -obj-y += cpu.o dram.o reset.o lowlevel_init.o +obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o diff --git a/arch/mips/mach-mscc/include/mach/common.h b/arch/mips/mach-mscc/include/mach/common.h index 931ecd7985..92a055561e 100644 --- a/arch/mips/mach-mscc/include/mach/common.h +++ b/arch/mips/mach-mscc/include/mach/common.h @@ -9,10 +9,12 @@ #if defined(CONFIG_SOC_OCELOT) #include #include +#include #include #elif defined(CONFIG_SOC_LUTON) #include #include +#include #include #else #error Unsupported platform @@ -25,4 +27,22 @@ #define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */ +/* Common utility functions */ + +int mscc_phy_rd_wr(u8 read, + u32 miim_controller, + u8 miim_addr, + u8 addr, + u16 *value); + +int mscc_phy_rd(u32 miim_controller, + u8 miim_addr, + u8 addr, + u16 *value); + +int mscc_phy_wr(u32 miim_controller, + u8 miim_addr, + u8 addr, + u16 value); + #endif /* __ASM_MACH_COMMON_H */ diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h new file mode 100644 index 00..2303734894 --- /dev/null +++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Microsemi Ocelot Switch driver + * + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef _MSCC_LUTON_MIIM_REGS_H_ +#define _MSCC_LUTON_MIIM_REGS_H_ + +#define MIIM_MII_STATUS(gi) (0xa0 + (gi * 36)) +#define MIIM_MII_CMD(gi)(0xa8 + (gi * 36)) +#define MIIM_MII_DATA(gi) (0xac + (gi * 36)) + +#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) (x ? BIT(3) : 0) + +#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x)(x ? BIT(31) : 0) +#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & (x << 25)) +#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & (x << 20)) +#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & (x << 4)) +#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & (x << 1)) + +#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16) +#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) ((x >> 0) & GENMASK(15, 0)) + +#endif diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h new file mode 100644 index 00..4ad92214a3 --- /dev/null +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_ +#define _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_ + +#define MIIM_MII_STATUS(gi) (0x9c + (gi * 36)) +#define MIIM_MII_CMD(gi)(0xa4 + (gi * 36)) +#define MIIM_MII_DATA(gi) (0xa8 + (gi * 36)) + +#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0) + +#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x)((x) ? BIT(31) : 0) +#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25)) +#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20)) +#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4)) +#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1)) +#define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0) + +#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16) +#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0)) + +#endif diff --git a/arch/mips/mach-mscc/phy.c b/arch/mips/mach-mscc/phy.c new file mode 100644 index 00..add6280e38 --- /dev/null +++ b/arch/mips/mach-mscc/phy.c @@ -0,0 +1,73 @@ +// SPDX-License-Identi
[U-Boot] [PATCH 1/6] mips: luton+ocelot: Remove board-specific config options
As we are moving to multi-dtb and board detection, remove static board config options. Signed-off-by: Lars Povlsen --- arch/mips/mach-mscc/Kconfig | 38 ++--- 1 file changed, 10 insertions(+), 28 deletions(-) diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig index 0e35b77c9d..37ef432e48 100644 --- a/arch/mips/mach-mscc/Kconfig +++ b/arch/mips/mach-mscc/Kconfig @@ -15,47 +15,29 @@ config SOC_VCOREIII config SYS_SOC default "mscc" +choice + + prompt "SOC Family Variant" + config SOC_OCELOT - bool + bool "Ocelot SOC Family" select SOC_VCOREIII + select DESIGNWARE_SPI help This supports MSCC Ocelot family of SOCs. config SOC_LUTON - bool + bool "Luton SOC Family" select SOC_VCOREIII + select MSCC_BITBANG_SPI_GPIO help This supports MSCC Luton family of SOCs. +endchoice + config SYS_CONFIG_NAME default "vcoreiii" -choice - prompt "Board select" - -config TARGET_OCELOT_PCB120 - bool "MSCC PCB120 Reference Board (aka VSC5635EV)" - select SOC_OCELOT - help - When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to - ocelot_pcb120 - -config TARGET_OCELOT_PCB123 - bool "MSCC PCB123 Reference Board (aka VSC7514EV))" - select SOC_OCELOT - help - When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to - ocelot_pcb123 - -config TARGET_LUTON_PCB091 - bool "MSCC PCB091 Reference Board" - select SOC_LUTON - select MSCC_BITBANG_SPI_GPIO - help - When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to - luton_pcb091 -endchoice - choice prompt "DDR type" -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 0/6] mips: mscc: Add multi-dtb support to luton+ocelot
This patch series add support for using multi-dtb on the MSCC luton and ocelot SOC reference boards. The appropriate board will be determined during startup, and the right DT will be selected. The patch is based off u-boot-mips repo. Lars Povlsen (6): mips: luton+ocelot: Remove board-specific config options mips: mscc: Add generic PHY MIIM utility functions mips: mscc: Add generic GPIO control utility function mips: luton: DT: Add pcb090 mips: luton: Add multi-dtb support mips: ocelot: Add multi-dtb support arch/mips/dts/Makefile| 2 + arch/mips/dts/luton_pcb090.dts| 36 + arch/mips/mach-mscc/Kconfig | 38 +++--- arch/mips/mach-mscc/Makefile | 2 +- arch/mips/mach-mscc/gpio.c| 33 + arch/mips/mach-mscc/include/mach/common.h | 22 ++ .../include/mach/luton/luton_devcpu_gcb.h | 4 + .../mach/luton/luton_devcpu_gcb_miim_regs.h | 26 +++ .../include/mach/ocelot/ocelot_devcpu_gcb.h | 2 + .../mach/ocelot/ocelot_devcpu_gcb_miim_regs.h | 25 +++ arch/mips/mach-mscc/phy.c | 73 +++ board/mscc/luton/luton.c | 46 +++- board/mscc/ocelot/ocelot.c| 52 +++-- configs/mscc_luton_defconfig | 7 +- configs/mscc_ocelot_defconfig | 7 +- configs/mscc_ocelot_pcb120_defconfig | 60 --- include/configs/vcoreiii.h| 2 + 17 files changed, 333 insertions(+), 104 deletions(-) create mode 100644 arch/mips/dts/luton_pcb090.dts create mode 100644 arch/mips/mach-mscc/gpio.c create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h create mode 100644 arch/mips/mach-mscc/phy.c delete mode 100644 configs/mscc_ocelot_pcb120_defconfig -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] Mips: When using CONFIG_OF_SEPARATE, mips-relocs mess up _end symbol
When converting some MIPS-based platforms from CONFIG_OF_EMBED to CONFIG_OF_SEPARATE and CONFIG_MULTI_DTB_FIT, I had trouble with getting to the right offset of the DTB blob. It turns out that the mips-relocs utility chops off unused space in the ".rel" section, but in doing so it bring the "_end" symbol out of sync with the actual end of the generated binary. When the DT blob is tacked on, the "_end" symbol will not point to the start of the blob as desired, but somewhere into the blob - causing the DT parse to fail. This fix skips the ".rel" section shrinking to keep "_end" pointing to the right place. Another possible solution would be to update "_end", but that is beyond my current skills I'm afraid. Signed-off-by: Lars Povlsen --- tools/Makefile | 1 + tools/mips-relocs.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/tools/Makefile b/tools/Makefile index 0c3341e..aabb5b8 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -196,6 +196,7 @@ hostprogs-y += fdtgrep fdtgrep-objs += $(LIBFDT_OBJS) fdtgrep.o hostprogs-$(CONFIG_MIPS) += mips-relocs +HOSTCFLAGS_mips-relocs.o := $(if $(CONFIG_OF_SEPARATE),-DCONFIG_OF_SEPARATE -Wno-unused-but-set-variable -Wno-unused-variable) # We build some files with extra pedantic flags to try to minimize things # that won't build on some weird host compiler -- though there are lots of diff --git a/tools/mips-relocs.c b/tools/mips-relocs.c index 442cc8f..9c5bf07 100644 --- a/tools/mips-relocs.c +++ b/tools/mips-relocs.c @@ -401,6 +401,8 @@ int main(int argc, char *argv[]) return -ENOMEM; } +// Shrinking the .rel section mess up the _end symbol when CONFIG_OF_SEPARATE used +#if !defined(CONFIG_OF_SEPARATE) /* Update the .rel section's size */ set_shdr_field(i_rel_shdr, sh_size, rel_actual_size); @@ -414,6 +416,7 @@ int main(int argc, char *argv[]) set_phdr_field(i, p_filesz, load_sz); break; } +#endif /* Make sure data is written back to the file */ err = msync(elf, st.st_size, MS_SYNC); -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 1/1] common: Compile error with CONFIG_MULTI_DTB_FIT and not SPL
common/common_fit.c is including , but not actually using it. The
inclusion will cuase compile error on platforms using CONFIG_OF_SEPARATE
and not SPL.
Signed-off-by: Lars Povlsen
---
common/common_fit.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/common/common_fit.c b/common/common_fit.c
index 577b352..a35c7e9 100644
--- a/common/common_fit.c
+++ b/common/common_fit.c
@@ -8,7 +8,6 @@
#include
#include
#include
-#include
ulong fdt_getprop_u32(const void *fdt, int node, const char *prop)
{
--
2.7.4
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[U-Boot] Compile error with CONFIG_MULTI_DTB_FIT and not SPL
When changing some MIPS configs from CONFIG_OF_EMBED to
CONFIG_OF_SEPARATE, I ran into this compile issue since SPL is not
enabled. The fix is to guard the header with the
CONFIG_SPL_LIBCOMMON_SUPPORT preprocessor symbol.
It seems that the is not needed even when SPL is enabled, but
I'm not 100% sure on that. The code at lines 55..57 guarded by
CONFIG_SPL_LIBCOMMON_SUPPORT does not require the header file.
Signed-off-by: Lars Povlsen
---
common/common_fit.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/common/common_fit.c b/common/common_fit.c
index 577b352..33e26cc 100644
--- a/common/common_fit.c
+++ b/common/common_fit.c
@@ -8,7 +8,9 @@
#include
#include
#include
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
#include
+#endif
ulong fdt_getprop_u32(const void *fdt, int node, const char *prop)
{
--
2.7.4
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