[U-Boot] [PATCH] powerpc/srio-pcie-boot: Adjust addresses for SRIO/PCIE boot
The new 768KB u-boot image size requires changes for SRIO/PCIE boot. These addresses need to be updated to appropriate locations. The updated addresses are used to configure the SRIO/PCIE inbound windows for the boot, and they must be aligned with the window size based on the SRIO/PCIE modules requirement. So for the 768KB u-boot image, the inbound window cannot be set with 0xfff4 base address and 0xc size, it should be extended to 1MB size and the base address can be aligned with the size. Signed-off-by: Liu Gang gang@freescale.com --- include/configs/B4860QDS.h | 10 +- include/configs/P2041RDB.h | 10 +- include/configs/T208xQDS.h | 10 +- include/configs/T208xRDB.h | 10 +- include/configs/T4240QDS.h | 10 +- include/configs/corenet_ds.h | 10 +- 6 files changed, 30 insertions(+), 30 deletions(-) diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index eecff98..fc90c53 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -559,15 +559,15 @@ unsigned long get_board_ddr_clk(void); * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef08ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff8ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x8 /* 512K */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff8ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef20ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff0ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x10 /* 1M */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff0ull /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef04ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef10ull #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe0ull #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x4 /* 256K */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 113bbb2..0616b20 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -383,15 +383,15 @@ unsigned long get_board_sys_clk(unsigned long dummy); * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef08ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff8ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x8 /* 512K */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff8ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef20ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff0ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x10 /* 1M */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff0ull /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef04ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef10ull #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe0ull #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x4 /* 256K */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 0332648..cf5406b 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -509,15 +509,15 @@ unsigned long get_board_ddr_clk(void); * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef08ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff8ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x8 /* 512K */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff8ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef20ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff0ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x10 /* 1M */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff0ull /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef04ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef10ull #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe0ull #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE0x4/* 256K */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 2c12eab..12c24d0 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -462,15 +462,15 @@ unsigned long get_board_ddr_clk(void); * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef08ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff8ull -#define
[U-Boot] [PATCH] powerpc/srio-pcie-boot: Avoid the NOR_BOOT macro when boot from SRIO/PCIE
When a board (slave) boots from SRIO/PCIE, it would get the instructions from a remote board (master) by SRIO/PCIE interface, and the slave's u-boot image should be built with the SYS_TEXT_BASE=0xFFF8; So the u-boot of the slave should avoid the NOR_BOOT branch at the booting stage. For example, when a P2041RDB boots from SRIO/PCIE, it will set TLB entry 15 from base address CONFIG_SYS_MONITOR_BASE 0xffc0, and with the 4M size as the boot window in NOR_BOOT branch. Because the CONFIG_SYS_MONITOR_BASE = CONFIG_SYS_TEXT_BASE = 0xFFF8, so the TLB entry will be from base address 0xffc0 and with 4M size. Then the u-boot will set TLB entry 14 from base address CONFIG_SYS_INIT_RAM_ADDR, and with the 16K size as the initial stack window. For the P2041RDB platform, the CONFIG_SYS_INIT_RAM_ADDR = 0xffd0. So the TLB entry 14 and 15 will be in confliction. There will be right TLB entries configurations when avoid the NOR_BOOT branch and set the boot window from 0xfff0 with 1M size space. Signed-off-by: Liu Gang gang@freescale.com --- arch/powerpc/cpu/mpc85xx/start.S |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 2657982..786b7e2 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -49,7 +49,8 @@ #define MINIMAL_SPL #endif -#if !defined(CONFIG_SPL) !defined(CONFIG_SYS_RAMBOOT) !defined(CONFIG_SECURE_BOOT) +#if !defined(CONFIG_SPL) !defined(CONFIG_SYS_RAMBOOT) \ + !defined(CONFIG_SECURE_BOOT) !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define NOR_BOOT #endif -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] powerpc/srio: Update the SRIO LIODN registers and ID table macro
For some PowerPC platforms, LIODN registers for SRIO ports are
in SRIO register address space. So the ccsr_rio structure should
be updated for those LIODN registers.
In addition, add a new macro SET_SRIO_LIODN_BASE to create
the SRIO LIODN ID table based on the SRIO LIODN register address.
Signed-off-by: Liu Gang gang@freescale.com
---
arch/powerpc/include/asm/fsl_liodn.h |7 +++
arch/powerpc/include/asm/immap_85xx.h | 16
2 files changed, 23 insertions(+)
diff --git a/arch/powerpc/include/asm/fsl_liodn.h
b/arch/powerpc/include/asm/fsl_liodn.h
index d759de9..926fa7c 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -45,6 +45,13 @@ struct srio_liodn_id_table {
+ CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
}
+#define SET_SRIO_LIODN_BASE(port, id_a) \
+ { .id = { id_a }, .num_ids = 1, .portid = port, \
+ .reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
+ + (port - 1) * 0x200 \
+ + CONFIG_SYS_FSL_SRIO_ADDR, \
+ }
+
struct liodn_id_table {
const char * compat;
u32 id[2];
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index db70d04..324e0f8 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1560,6 +1560,18 @@ struct rio_pw {
};
#endif
+#ifdef CONFIG_SYS_FSL_SRIO_LIODN
+struct rio_liodn {
+ u32 plbr;
+ u8 res0[28];
+ u32 plaor;
+ u8 res1[12];
+ u32 pludr;
+ u32 plldr;
+ u8 res2[456];
+};
+#endif
+
/* RapidIO Registers */
struct ccsr_rio {
struct rio_arch arch;
@@ -1582,6 +1594,10 @@ struct ccsr_rio {
u8 res7[100];
struct rio_pw pw;
#endif
+#ifdef CONFIG_SYS_FSL_SRIO_LIODN
+ u8 res5[8192];
+ struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+#endif
};
#endif
--
1.7.9.5
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[U-Boot] [PATCH 3/3] powerpc/t4: Correct LIODN assignment for SRIO
For T4 platform, the SRIO LIODN registers are in SRIO address space
and not in GUTs.
Signed-off-by: Liu Gang gang@freescale.com
---
arch/powerpc/cpu/mpc85xx/t4240_ids.c |4 ++--
arch/powerpc/include/asm/config_mpc85xx.h |1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c
b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
index a8f16b1..7e6d96e 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
@@ -81,8 +81,8 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
#endif
struct srio_liodn_id_table srio_liodn_tbl[] = {
- SET_SRIO_LIODN_1(1, 307),
- SET_SRIO_LIODN_1(2, 387),
+ SET_SRIO_LIODN_BASE(1, 307),
+ SET_SRIO_LIODN_BASE(2, 387),
};
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index bfcabab..8ba199f 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -550,6 +550,7 @@
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_SRIO_LIODN
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_A004468
--
1.7.9.5
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[U-Boot] [PATCH 2/3] powerpc/b4860: Correct LIODN assignment for SRIO
For B4, the SRIO LIODN registers are in SRIO address space and not
in GUTs.
Signed-off-by: Liu Gang gang@freescale.com
---
arch/powerpc/cpu/mpc85xx/b4860_ids.c |4 ++--
arch/powerpc/include/asm/config_mpc85xx.h |1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c
b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
index 0f4e82e..f910486 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
@@ -57,8 +57,8 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
#ifdef CONFIG_SYS_SRIO
struct srio_liodn_id_table srio_liodn_tbl[] = {
- SET_SRIO_LIODN_1(1, 307),
- SET_SRIO_LIODN_1(2, 387),
+ SET_SRIO_LIODN_BASE(1, 307),
+ SET_SRIO_LIODN_BASE(2, 387),
};
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
#endif
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 1d46b14..bfcabab 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -590,6 +590,7 @@
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_SRIO_LIODN
#else
#define CONFIG_MAX_CPUS2
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
--
1.7.9.5
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[U-Boot] [PATCH 6/6 v2] powerpc/t4qds: Slave module for boot from SRIO and PCIE
When a T4 board boots from SRIO or PCIE, it needs to finish these processes:
1. Set all the cores in holdoff status.
2. Set the boot location to one PCIE or SRIO interface by RCW.
3. Set a specific TLB entry for the boot process.
4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
5. Set a specific TLB entry in order to fetch ucode and ENV from
master.
6. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
7. Slave's u-boot image should be generated specifically by
make _SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF8 and other configurations.
For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang gang@freescale.com
---
changes for v2:
- No
arch/powerpc/include/asm/immap_85xx.h |1 +
board/freescale/t4qds/tlb.c | 19 ++
boards.cfg|1 +
include/configs/t4qds.h | 34 ++--
4 files changed, 48 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index eb28768..af9a846 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1840,6 +1840,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL0x00f8
#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
+#define FSL_CORENET_RCWSR6_BOOT_LOC0x0f80
#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL0xfe00
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c
index 80eb511..2370332 100644
--- a/board/freescale/t4qds/tlb.c
+++ b/board/freescale/t4qds/tlb.c
@@ -55,6 +55,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+ /*
+* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+* space is at 0xfff0, it covered the 0xf000.
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
#else
SET_TLB_ENTRY(1, 0xf000, 0xf000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -130,6 +139,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 17, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+ /*
+* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe0 for
+* fetching ucode and ENV from master
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 18, BOOKE_PAGESZ_1M, 1),
+#endif
};
diff --git a/boards.cfg b/boards.cfg
index 61acc3f..354738e 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -896,6 +896,7 @@ stxssa_4Mpowerpc mpc85xx stxssa
stx
T4240QDS powerpc mpc85xx t4qds
freescale
T4240QDS_SDCARD powerpc mpc85xx t4qds
freescale - T4240QDS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8
T4240QDS_SPIFLASHpowerpc mpc85xx t4qds
freescale - T4240QDS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
+T4240QDS_SRIO_PCIE_BOOT powerpc mpc85xx t4qds
freescale -
T4240QDS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF8
B4860QDS powerpc mpc85xx b4860qds
freescale - B4860QDS:PPC_B4860
B4860QDS_NAND powerpc mpc85xx b4860qds
freescale -
B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8
B4860QDS_SPIFLASHpowerpc mpc85xx b4860qds
freescale -
B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index a0c96f2..5077cf3 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -31,6 +31,15 @@
#define CONFIG_RESET_VECTOR_ADDRESS0xfffc
#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define
Re: [U-Boot] [PATCH 2/7] powerpc/boot: Change the macro of Boot from SRIO and PCIE master module
On Mon, 2013-05-06 at 13:58 -0500, Andy Fleming wrote: York has submitted a bunch of patches. I marked yours as superseded to note that I'll take his copy. There are others like that, but I'm holding off on deciding which copy to take until I can review them. Yes, I have known those patches about this feature in York's list, and pointed out to York and you. I transferred that mail to you, please find it. In addition, my patches about this feature have some updates compared with York's list, so please apply my patches for this feature, thanks! And I have sent the patches for version 2 based on your comments. Thanks a lot! Liu Gang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/6 v2] powerpc/doc: Update the README.srio-pcie-boot-corenet
1. Misalignment will be found in the doc/README.srio-pcie-boot-corenet file when the tabs are set to 8 characters. And the standard for u-boot should be 8 character tabs! So this issue should be amended. 2. Add a NOTE for the ENV parameters of the Slave. Signed-off-by: Liu Gang gang@freescale.com --- changes for v2: - No doc/README.srio-pcie-boot-corenet | 34 -- 1 files changed, 20 insertions(+), 14 deletions(-) diff --git a/doc/README.srio-pcie-boot-corenet b/doc/README.srio-pcie-boot-corenet index cd7e7ee..2b1f76b 100644 --- a/doc/README.srio-pcie-boot-corenet +++ b/doc/README.srio-pcie-boot-corenet @@ -21,13 +21,13 @@ Environment of the SRIO or PCIE boot: e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set the boot location to SRIO or PCIE, and holdoff all the cores. - ----- --- - | | | | | | - | | | | | | + --- --- --- + | | | | | | + | | | | | | | NorFlash|-| Master |SRIO or PCIE | Slave |[EEPROM] - | | | |===| | - | | | | | | - ----- --- + | | | |===| | + | | | | | | + --- --- --- The example based on P4080DS platform: Two P4080DS platforms can be used to implement the boot from SRIO or PCIE. @@ -87,26 +87,32 @@ How to use this feature: Please refer to the examples given above. 2. U-Boot image's compilation. - For master, U-Boot image should be generated normally. + For master, U-Boot image should be generated normally. - For example, master U-Boot image used on P4080DS should be compiled with + For example, master U-Boot image used on P4080DS should be compiled with make P4080DS_config. - For slave, U-Boot image should be generated specifically by + For slave, U-Boot image should be generated specifically by make _SRIO_PCIE_BOOT_config. - For example, slave U-Boot image used on P4080DS should be compiled with + For example, slave U-Boot image used on P4080DS should be compiled with make P4080DS_SRIO_PCIE_BOOT_config. 3. Necessary modifications based on a specific environment. - For a specific environment, the addresses of the slave's U-Boot image, - UCode, ENV stored in master's NorFlash, and any other configurations - can be modified in the file: - include/configs/corenet_ds.h. + For a specific environment, the addresses of the slave's U-Boot image, + UCode, ENV stored in master's NorFlash, and any other configurations + can be modified in the file: + include/configs/corenet_ds.h. 4. Set and save the environment variable bootmaster with SRIO1, SRIO2 or PCIE1, PCIE2, PCIE3 for master, and then restart it in order to perform the role as a master for boot from SRIO or PCIE. + +NOTE: When the Slave's ENV parameters are stored in Master's NorFlash, + it can fetch them through PCIE or SRIO interface. But the ENV + parameters can not be modified by saveenv or other commands under + the Slave's u-boot environment, because the Slave can not erase, + write Master's NorFlash by PCIE or SRIO link. -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/6 v2] powerpc/boot: Change the macro of Boot from SRIO and PCIE master module
Currently, the macro CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER can enable
the master module of Boot from SRIO and PCIE on a platform. But this
is not a silicon feature, it's just a specific booting mode based on
the SRIO and PCIE interfaces. So it's inappropriate to put the macro
into the file arch/powerpc/include/asm/config_mpc85xx.h.
Change the macro CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER to
CONFIG_SRIO_PCIE_BOOT_MASTER, remove them from
arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros
in configuration header file of each board which can support the
master module of Boot from SRIO and PCIE.
Signed-off-by: Liu Gang gang@freescale.com
---
changes for v2:
- Add the description for why the old macro should
be modified and removed from the config_mpc85xx.h
file.
README|3 +++
arch/powerpc/cpu/mpc85xx/cpu_init.c |2 +-
arch/powerpc/cpu/mpc8xxx/srio.c |4 ++--
arch/powerpc/include/asm/config_mpc85xx.h |4
drivers/pci/fsl_pci_init.c|6 +++---
include/configs/P2041RDB.h|1 +
include/configs/P3041DS.h |2 +-
include/configs/P4080DS.h |2 +-
include/configs/P5020DS.h |2 +-
9 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/README b/README
index 0d37d56..b25976a 100644
--- a/README
+++ b/README
@@ -3862,6 +3862,9 @@ Low Level (hardware related) configuration options:
- CONFIG_SRIO2:
Board has SRIO 2 port available
+- CONFIG_SRIO_PCIE_BOOT_MASTER
+ Board can support master function for Boot from SRIO and PCIE
+
- CONFIG_SYS_SRIOn_MEM_VIRT:
Virtual Address of SRIO port 'n' memory region
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 53713e3..9256449 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -564,7 +564,7 @@ skip_l2:
#ifdef CONFIG_SYS_SRIO
srio_init();
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
char *s = getenv(bootmaster);
if (s) {
if (!strcmp(s, SRIO1)) {
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 6e6f7dc..90d1065 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -24,7 +24,7 @@
#include asm/fsl_srio.h
#include asm/errno.h
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
#define SRIO_PORT_ACCEPT_ALL 0x1001
#define SRIO_IB_ATMU_AR 0x80f55000
#define SRIO_OB_ATMU_AR_MAINT 0x80077000
@@ -299,7 +299,7 @@ void srio_init(void)
}
}
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
void srio_boot_master(int port)
{
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 7267611..cfaa0e1 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -337,7 +337,6 @@
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -371,7 +370,6 @@
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -413,7 +411,6 @@
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -449,7 +446,6 @@
#define CONFIG_SYS_FSL_ERRATUM_USB14
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 77ac1f7..621c899 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -211,7 +211,7 @@ static int fsl_pci_setup_inbound_windows(struct
pci_controller *hose,
return 1;
}
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
static void fsl_pcie_boot_master(pit_t *pi)
{
/* configure inbound window for slave's u-boot image */
@@ -388,7 +388,7 @@ void fsl_pci_init(struct pci_controller *hose, struct
fsl_pci_info *pci_info
[U-Boot] [PATCH 4/6 v2] powerpc/b4860qds: Slave module for boot from SRIO and PCIE
When a b4860qds board boots from SRIO or PCIE, it needs to finish these
processes:
1. Set all the cores in holdoff status.
2. Set the boot location to one PCIE or SRIO interface by RCW.
3. Set a specific TLB entry for the boot process.
4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
5. Set a specific TLB entry in order to fetch ucode and ENV from
master.
6. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
7. Slave's u-boot image should be generated specifically by
make _SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF8 and other configurations.
For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang gang@freescale.com
---
changes for v2:
- No
arch/powerpc/include/asm/immap_85xx.h |1 +
board/freescale/b4860qds/tlb.c| 19 +++
boards.cfg|1 +
include/configs/B4860QDS.h| 32 +++-
4 files changed, 48 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index baaa9fe..eb28768 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1845,6 +1845,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL0x00ff
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
+#define FSL_CORENET_RCWSR6_BOOT_LOC0x0f80
#endif
#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL10x0080
#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL20x0040
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
index 6d634bf..9ea3c81 100644
--- a/board/freescale/b4860qds/tlb.c
+++ b/board/freescale/b4860qds/tlb.c
@@ -52,6 +52,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+ /*
+* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+* space is at 0xfff0, it covered the 0xf000.
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
#else
SET_TLB_ENTRY(1, 0xf000, 0xf000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -137,6 +146,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_256M, 1),
#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+ /*
+* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe0 for
+* fetching ucode and ENV from master
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 17, BOOKE_PAGESZ_1M, 1),
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 5d78064..61acc3f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -899,6 +899,7 @@ T4240QDS_SPIFLASHpowerpc mpc85xx t4qds
freesca
B4860QDS powerpc mpc85xx b4860qds
freescale - B4860QDS:PPC_B4860
B4860QDS_NAND powerpc mpc85xx b4860qds
freescale -
B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8
B4860QDS_SPIFLASHpowerpc mpc85xx b4860qds
freescale -
B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
+B4860QDS_SRIO_PCIE_BOOT powerpc mpc85xx b4860qds
freescale -
B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF8
B4420QDS powerpc mpc85xx b4860qds
freescale - B4860QDS:PPC_B4420
B4420QDS_NAND powerpc mpc85xx b4860qds
freescale -
B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8
B4420QDS_SPIFLASHpowerpc mpc85xx b4860qds
freescale -
B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 81cd584..00ee5ac 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -34,6 +34,15 @@
#define CONFIG_RESET_VECTOR_ADDRESS0xfffc
#endif
+#ifdef
[U-Boot] [PATCH 3/6 v2] powerpc/b4860qds: Enable master module for boot from SRIO and PCIE
B4860QDS can support the feature of Boot from SRIO/PCIE, and the macro CONFIG_SRIO_PCIE_BOOT_MASTER will enable the master module of this feature when building the u-boot image. You can get some description about this macro in README file, and for more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang gang@freescale.com --- changes for v2: - No include/configs/B4860QDS.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index b09119a..81cd584 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -64,6 +64,7 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ +#define CONFIG_SRIO_PCIE_BOOT_MASTER #endif #define CONFIG_FSL_LAW /* Use common FSL init code */ -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/6 v2] powerpc/t4qds: Enable master module for Boot from SRIO and PCIE
T4 can support the feature of Boot from SRIO/PCIE, and the macro CONFIG_SRIO_PCIE_BOOT_MASTER will enable the master module of this feature when building the u-boot image. You can get some description about this macro in README file, and for more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang gang@freescale.com --- changes for v2: - No include/configs/t4qds.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 2c665b8..a0c96f2 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -64,6 +64,7 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ +#define CONFIG_SRIO_PCIE_BOOT_MASTER #define CONFIG_FSL_LAW /* Use common FSL init code */ -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/7] powerpc/boot: Change the macro of Boot from SRIO and PCIE master module
On Tue, 2013-04-30 at 17:28 -0500, Andy Fleming wrote: On Fri, Mar 8, 2013 at 2:41 AM, Liu Gang gang@freescale.com wrote: Change the macro CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER to CONFIG_SRIO_PCIE_BOOT_MASTER, remove them from arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros in configuration header file of each board which can support the master module of Boot from SRIO and PCIE. Signed-off-by: Liu Gang gang@freescale.com More important than explaining what the patch does is explaining *why*. Why was this change necessary? Make sure the why includes what makes this feature a board feature, as opposed to an SoC feature? Andy Thanks, I'll updated the commit message. And in addition, why the state of the below patch is superseded? http://patchwork.ozlabs.org/patch/226046/ ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 7/7] powerpc/t4qds: Slave module for boot from SRIO and PCIE
When a T4 board boots from SRIO or PCIE, it needs to finish these processes:
1. Set all the cores in holdoff status.
2. Set the boot location to one PCIE or SRIO interface by RCW.
3. Set a specific TLB entry for the boot process.
4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
5. Set a specific TLB entry in order to fetch ucode and ENV from
master.
6. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
7. Slave's u-boot image should be generated specifically by
make _SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF8 and other configurations.
For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang gang@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h |1 +
board/freescale/t4qds/tlb.c | 19 ++
boards.cfg|1 +
include/configs/t4qds.h | 34 ++--
4 files changed, 48 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index d0a2eb0..8f86324 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1840,6 +1840,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL0x00f8
#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
+#define FSL_CORENET_RCWSR6_BOOT_LOC0x0f80
#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL0xfe00
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c
index 80eb511..58febf2 100644
--- a/board/freescale/t4qds/tlb.c
+++ b/board/freescale/t4qds/tlb.c
@@ -55,6 +55,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+ /*
+* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+* space is at 0xfff0, it covered the 0xf000.
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
#else
SET_TLB_ENTRY(1, 0xf000, 0xf000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -130,6 +139,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 17, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+ /*
+* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe0 for
+* fetching ucode and ENV from master
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 18, BOOKE_PAGESZ_1M, 1),
+#endif
};
diff --git a/boards.cfg b/boards.cfg
index 95b0c46..b163770 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -875,6 +875,7 @@ stxssa_4Mpowerpc mpc85xx stxssa
stx
T4240QDS powerpc mpc85xx t4qds
freescale
T4240QDS_SDCARD powerpc mpc85xx t4qds
freescale - T4240QDS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8
T4240QDS_SPIFLASHpowerpc mpc85xx t4qds
freescale - T4240QDS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
+T4240QDS_SRIO_PCIE_BOOT powerpc mpc85xx t4qds
freescale -
T4240QDS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF8
B4860QDS powerpc mpc85xx b4860qds
freescale - B4860QDS:PPC_B4860
B4860QDS_NAND powerpc mpc85xx b4860qds
freescale -
B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8
B4860QDS_SPIFLASHpowerpc mpc85xx b4860qds
freescale -
B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index a0c96f2..5077cf3 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -31,6 +31,15 @@
#define CONFIG_RESET_VECTOR_ADDRESS0xfffc
#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR
[U-Boot] [PATCH 1/7] powerpc/doc: Update the README.srio-pcie-boot-corenet
1. Misalignment will be found in the doc/README.srio-pcie-boot-corenet file when the tabs are set to 8 characters. And the standard for u-boot should be 8 character tabs! So this issue should be amended. 2. Add a NOTE for the ENV parameters of the Slave. Signed-off-by: Liu Gang gang@freescale.com --- doc/README.srio-pcie-boot-corenet | 34 -- 1 files changed, 20 insertions(+), 14 deletions(-) diff --git a/doc/README.srio-pcie-boot-corenet b/doc/README.srio-pcie-boot-corenet index cd7e7ee..2b1f76b 100644 --- a/doc/README.srio-pcie-boot-corenet +++ b/doc/README.srio-pcie-boot-corenet @@ -21,13 +21,13 @@ Environment of the SRIO or PCIE boot: e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set the boot location to SRIO or PCIE, and holdoff all the cores. - ----- --- - | | | | | | - | | | | | | + --- --- --- + | | | | | | + | | | | | | | NorFlash|-| Master |SRIO or PCIE | Slave |[EEPROM] - | | | |===| | - | | | | | | - ----- --- + | | | |===| | + | | | | | | + --- --- --- The example based on P4080DS platform: Two P4080DS platforms can be used to implement the boot from SRIO or PCIE. @@ -87,26 +87,32 @@ How to use this feature: Please refer to the examples given above. 2. U-Boot image's compilation. - For master, U-Boot image should be generated normally. + For master, U-Boot image should be generated normally. - For example, master U-Boot image used on P4080DS should be compiled with + For example, master U-Boot image used on P4080DS should be compiled with make P4080DS_config. - For slave, U-Boot image should be generated specifically by + For slave, U-Boot image should be generated specifically by make _SRIO_PCIE_BOOT_config. - For example, slave U-Boot image used on P4080DS should be compiled with + For example, slave U-Boot image used on P4080DS should be compiled with make P4080DS_SRIO_PCIE_BOOT_config. 3. Necessary modifications based on a specific environment. - For a specific environment, the addresses of the slave's U-Boot image, - UCode, ENV stored in master's NorFlash, and any other configurations - can be modified in the file: - include/configs/corenet_ds.h. + For a specific environment, the addresses of the slave's U-Boot image, + UCode, ENV stored in master's NorFlash, and any other configurations + can be modified in the file: + include/configs/corenet_ds.h. 4. Set and save the environment variable bootmaster with SRIO1, SRIO2 or PCIE1, PCIE2, PCIE3 for master, and then restart it in order to perform the role as a master for boot from SRIO or PCIE. + +NOTE: When the Slave's ENV parameters are stored in Master's NorFlash, + it can fetch them through PCIE or SRIO interface. But the ENV + parameters can not be modified by saveenv or other commands under + the Slave's u-boot environment, because the Slave can not erase, + write Master's NorFlash by PCIE or SRIO link. -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/7] powerpc/boot: Change the macro of Boot from SRIO and PCIE master module
Change the macro CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER to
CONFIG_SRIO_PCIE_BOOT_MASTER, remove them from
arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros
in configuration header file of each board which can support the
master module of Boot from SRIO and PCIE.
Signed-off-by: Liu Gang gang@freescale.com
---
README|3 +++
arch/powerpc/cpu/mpc85xx/cpu_init.c |2 +-
arch/powerpc/cpu/mpc8xxx/srio.c |4 ++--
arch/powerpc/include/asm/config_mpc85xx.h |4
drivers/pci/fsl_pci_init.c|6 +++---
include/configs/P2041RDB.h|1 +
include/configs/P3041DS.h |2 +-
include/configs/P4080DS.h |2 +-
include/configs/P5020DS.h |2 +-
9 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/README b/README
index 42544ce..a749094 100644
--- a/README
+++ b/README
@@ -3706,6 +3706,9 @@ Low Level (hardware related) configuration options:
- CONFIG_SRIO2:
Board has SRIO 2 port available
+- CONFIG_SRIO_PCIE_BOOT_MASTER
+ Board can support master function for Boot from SRIO and PCIE
+
- CONFIG_SYS_SRIOn_MEM_VIRT:
Virtual Address of SRIO port 'n' memory region
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index de9d916..d860eba 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -564,7 +564,7 @@ skip_l2:
#ifdef CONFIG_SYS_SRIO
srio_init();
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
char *s = getenv(bootmaster);
if (s) {
if (!strcmp(s, SRIO1)) {
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 6e6f7dc..90d1065 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -24,7 +24,7 @@
#include asm/fsl_srio.h
#include asm/errno.h
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
#define SRIO_PORT_ACCEPT_ALL 0x1001
#define SRIO_IB_ATMU_AR 0x80f55000
#define SRIO_OB_ATMU_AR_MAINT 0x80077000
@@ -299,7 +299,7 @@ void srio_init(void)
}
}
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
void srio_boot_master(int port)
{
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index d57c178..51daf80 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -335,7 +335,6 @@
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -367,7 +366,6 @@
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -409,7 +407,6 @@
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -443,7 +440,6 @@
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 77ac1f7..621c899 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -211,7 +211,7 @@ static int fsl_pci_setup_inbound_windows(struct
pci_controller *hose,
return 1;
}
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
static void fsl_pcie_boot_master(pit_t *pi)
{
/* configure inbound window for slave's u-boot image */
@@ -388,7 +388,7 @@ void fsl_pci_init(struct pci_controller *hose, struct
fsl_pci_info *pci_info)
/* see if we are a PCIe or PCI controller */
pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, pcie_cap);
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
/* boot from PCIE --master */
char *s = getenv(bootmaster);
char pcie[6];
@@ -624,7 +624,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
if (fsl_is_pci_agent(hose
[U-Boot] [PATCH 4/7] powerpc/b4860qds: Enable master module for boot from SRIO and PCIE
B4860QDS can support the feature of Boot from SRIO/PCIE, and the macro CONFIG_SRIO_PCIE_BOOT_MASTER will enable the master module of this feature when building the u-boot image. You can get some description about this macro in README file, and for more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang gang@freescale.com --- include/configs/B4860QDS.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index b09119a..81cd584 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -64,6 +64,7 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ +#define CONFIG_SRIO_PCIE_BOOT_MASTER #endif #define CONFIG_FSL_LAW /* Use common FSL init code */ -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/7] powerpc/b4860qds: Slave module for boot from SRIO and PCIE
When a b4860qds board boots from SRIO or PCIE, it needs to finish these
processes:
1. Set all the cores in holdoff status.
2. Set the boot location to one PCIE or SRIO interface by RCW.
3. Set a specific TLB entry for the boot process.
4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
5. Set a specific TLB entry in order to fetch ucode and ENV from
master.
6. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
7. Slave's u-boot image should be generated specifically by
make _SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF8 and other configurations.
For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang gang@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h |1 +
board/freescale/b4860qds/tlb.c| 19 +++
boards.cfg|1 +
include/configs/B4860QDS.h| 32 +++-
4 files changed, 48 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 4eb3f79..d0a2eb0 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1845,6 +1845,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL0x00ff
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
+#define FSL_CORENET_RCWSR6_BOOT_LOC0x0f80
#endif
#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL10x0080
#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL20x0040
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
index 6d634bf..0ea4976 100644
--- a/board/freescale/b4860qds/tlb.c
+++ b/board/freescale/b4860qds/tlb.c
@@ -52,6 +52,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+ /*
+* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+* space is at 0xfff0, it covered the 0xf000.
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
#else
SET_TLB_ENTRY(1, 0xf000, 0xf000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -137,6 +146,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_256M, 1),
#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+ /*
+* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe0 for
+* fetching ucode and ENV from master
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 17, BOOKE_PAGESZ_1M, 1),
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 136ea0a..95b0c46 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -878,6 +878,7 @@ T4240QDS_SPIFLASHpowerpc mpc85xx t4qds
freesca
B4860QDS powerpc mpc85xx b4860qds
freescale - B4860QDS:PPC_B4860
B4860QDS_NAND powerpc mpc85xx b4860qds
freescale -
B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8
B4860QDS_SPIFLASHpowerpc mpc85xx b4860qds
freescale -
B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
+B4860QDS_SRIO_PCIE_BOOT powerpc mpc85xx b4860qds
freescale -
B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF8
B4420QDS powerpc mpc85xx b4860qds
freescale - B4860QDS:PPC_B4420
B4420QDS_NAND powerpc mpc85xx b4860qds
freescale -
B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8
B4420QDS_SPIFLASHpowerpc mpc85xx b4860qds
freescale -
B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 81cd584..00ee5ac 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -34,6 +34,15 @@
#define CONFIG_RESET_VECTOR_ADDRESS0xfffc
#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space
[U-Boot] [PATCH 3/7] powerpc/b4860qds: Add the tlb entries for SRIO interfaces
Add the tlb entries based on the configuration of the SRIO interfaces.
Every SRIO interface has 256M space:
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa000
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc2000ull
#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb000
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc3000ull
Signed-off-by: Liu Gang gang@freescale.com
---
board/freescale/b4860qds/tlb.c | 19 +--
1 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
index 373cb78..6d634bf 100644
--- a/board/freescale/b4860qds/tlb.c
+++ b/board/freescale/b4860qds/tlb.c
@@ -111,8 +111,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
#ifdef CONFIG_SYS_NAND_BASE
/*
* *I*G - NAND
-* entry 14 and 15 has been used hard coded, they will be disabled
-* in cpu_init_f, so we use entry 16 for nand.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -122,6 +120,23 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_4K, 1),
+ /*
+* *I*G - SRIO
+* entry 14 and 15 has been used hard coded, they will be disabled
+* in cpu_init_f, so we use entry 16 for SRIO2.
+*/
+#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
+ /* *I*G* - SRIO1 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 13, BOOKE_PAGESZ_256M, 1),
+#endif
+#ifdef CONFIG_SYS_SRIO2_MEM_PHYS
+ /* *I*G* - SRIO2 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 16, BOOKE_PAGESZ_256M, 1),
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
--
1.7.1
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[U-Boot] [PATCH 6/7] powerpc/t4qds: Enable master module for Boot from SRIO and PCIE
T4 can support the feature of Boot from SRIO/PCIE, and the macro CONFIG_SRIO_PCIE_BOOT_MASTER will enable the master module of this feature when building the u-boot image. You can get some description about this macro in README file, and for more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang gang@freescale.com --- include/configs/t4qds.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 2c665b8..a0c96f2 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -64,6 +64,7 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ +#define CONFIG_SRIO_PCIE_BOOT_MASTER #define CONFIG_FSL_LAW /* Use common FSL init code */ -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/b4: Fix the wrong register offset of B4 PCIE module
B4420/B4860 PCIE can not work because of the wrong definition of
the PCIE register offset in the file:
arch/powerpc/include/asm/immap_85xx.h
Add the judgement of B4420/B4860 to make the register offset to:
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x20
Signed-off-by: Liu Gang gang@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 4eb3f79..1c8d1ac 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2914,7 +2914,8 @@ struct ccsr_pman {
#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x13
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e
-#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) !defined(CONFIG_PPC_B4860)\
+!defined(CONFIG_PPC_B4420)
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET0x24
#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET0x25
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET0x26
--
1.7.1
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[U-Boot] [PATCH] powerpc/boot: Change the compile macro for SRIO PCIE boot master module
Currently, the SRIO and PCIE boot master module will be compiled into the
u-boot image if the macro CONFIG_FSL_CORENET has been defined. And this
macro has been included by all the corenet architecture platform boards.
But in fact, it's uncertain whether all corenet platform boards support
this feature.
So it may be better to get rid of the macro CONFIG_FSL_CORENET, and add
a special macro for every board which can support the feature. This
special macro will be defined in the header file
arch/powerpc/include/asm/config_mpc85xx.h. It will decide if the SRIO
and PCIE boot master module should be compiled into the board u-boot image.
Signed-off-by: Liu Gang gang@freescale.com
---
arch/powerpc/cpu/mpc8xxx/srio.c |4 +++-
arch/powerpc/include/asm/config_mpc85xx.h |4
drivers/pci/fsl_pci_init.c|6 +++---
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 0cb65b3..45f73ca 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -23,6 +23,7 @@
#include asm/fsl_serdes.h
#include asm/fsl_srio.h
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define SRIO_PORT_ACCEPT_ALL 0x1001
#define SRIO_IB_ATMU_AR 0x80f55000
#define SRIO_OB_ATMU_AR_MAINT 0x80077000
@@ -31,6 +32,7 @@
#define SRIO_MAINT_WIN_SIZE 0x100 /* 16M */
#define SRIO_RW_WIN_SIZE 0x10 /* 1M */
#define SRIO_LCSBA1CSR 0x6000
+#endif
#if defined(CONFIG_FSL_CORENET)
#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
@@ -95,7 +97,7 @@ void srio_init(void)
}
}
-#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
void srio_boot_master(int port)
{
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index aa27741..00da000 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -331,6 +331,7 @@
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -360,6 +361,7 @@
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -398,6 +400,7 @@
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -426,6 +429,7 @@
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 0d46c96..42dfc4b 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -211,7 +211,7 @@ static int fsl_pci_setup_inbound_windows(struct
pci_controller *hose,
return 1;
}
-#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
static void fsl_pcie_boot_master(pit_t *pi)
{
/* configure inbound window for slave's u-boot image */
@@ -384,7 +384,7 @@ void fsl_pci_init(struct pci_controller *hose, struct
fsl_pci_info *pci_info)
/* see if we are a PCIe or PCI controller */
pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, pcie_cap);
-#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
/* boot from PCIE --master */
char *s = getenv(bootmaster);
char pcie[6];
@@ -594,7 +594,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
if (fsl_is_pci_agent(hose)) {
fsl_pci_config_unlock(hose);
hose-last_busno = hose-first_busno;
-#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
} else {
/* boot from PCIE --master releases slave's core 0 */
char *s = getenv(bootmaster);
--
1.7.0.4
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[U-Boot] [PATCH] powerpc/srio: Workaround for srio erratrm a004034
Erratum: A-004034
Affects: SRIO
Description: During port initialization, the SRIO port performs
lane synchronization (detecting valid symbols on a lane) and
lane alignment (coordinating multiple lanes to receive valid data
across lanes). Internal errors in lane synchronization and lane
alignment may cause failure to achieve link initialization at
the configured port width.
An SRIO port configured as a 4x port may see one of these scenarios:
1. One or more lanes fails to achieve lane synchronization.
Depending on which lanes fail, this may result in downtraining
from 4x to 1x on lane 0, 4x to 1x on lane R (redundant lane).
2. The link may fail to achieve lane alignment as a 4x, even
though all 4 lanes achieve lane synchronization, and downtrain
to a 1x. An SRIO port configured as a 1x port may fail to complete
port initialization (PnESCSR[PU] never deasserts) because of
scenario 1.
Impact: SRIO port may downtrain to 1x, or may fail to complete
link initialization. Once a port completes link initialization
successfully, it will operate normally.
Signed-off-by: Liu Gang gang@freescale.com
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 +
arch/powerpc/cpu/mpc8xxx/srio.c | 191 +
arch/powerpc/include/asm/config_mpc85xx.h |4 +
3 files changed, 198 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index e8989bd..98038a3 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -127,6 +127,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
puts(Work-around for Erratum A004510 enabled\n);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+ puts(Work-around for Erratum SRIO-A004034 enabled\n);
+#endif
return 0;
}
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 0cb65b3..e7ff59a 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -22,6 +22,7 @@
#include asm/fsl_law.h
#include asm/fsl_serdes.h
#include asm/fsl_srio.h
+#include asm/errno.h
#define SRIO_PORT_ACCEPT_ALL 0x1001
#define SRIO_IB_ATMU_AR 0x80f55000
@@ -52,6 +53,185 @@
#error No defines for DEVDISR_SRIO
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+/*
+ * Erratum A-004034
+ * Affects: SRIO
+ * Description: During port initialization, the SRIO port performs
+ * lane synchronization (detecting valid symbols on a lane) and
+ * lane alignment (coordinating multiple lanes to receive valid data
+ * across lanes). Internal errors in lane synchronization and lane
+ * alignment may cause failure to achieve link initialization at
+ * the configured port width.
+ * An SRIO port configured as a 4x port may see one of these scenarios:
+ * 1. One or more lanes fails to achieve lane synchronization. Depending
+ * on which lanes fail, this may result in downtraining from 4x to 1x
+ * on lane 0, 4x to 1x on lane R (redundant lane).
+ * 2. The link may fail to achieve lane alignment as a 4x, even though
+ * all 4 lanes achieve lane synchronization, and downtrain to a 1x.
+ * An SRIO port configured as a 1x port may fail to complete port
+ * initialization (PnESCSR[PU] never deasserts) because of scenario 1.
+ * Impact: SRIO port may downtrain to 1x, or may fail to complete
+ * link initialization. Once a port completes link initialization
+ * successfully, it will operate normally.
+ */
+static int srio_erratum_a004034(u8 port)
+{
+ serdes_corenet_t *srds_regs;
+ u32 conf_lane;
+ u32 init_lane;
+ int idx, first, last;
+ u32 i;
+ unsigned long long end_tick;
+ struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+
+ srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
+ conf_lane = (in_be32((void *)srds_regs-srdspccr0)
+(12 - port * 4)) 0x3;
+ init_lane = (in_be32((void *)srio_regs-lp_serial
+ .port[port].pccsr) 27) 0x7;
+
+ /*
+* Start a counter set to ~2 ms after the SERDES reset is
+* complete (SERDES SRDSBnRSTCTL[RST_DONE]=1 for n
+* corresponding to the SERDES bank/PLL for the SRIO port).
+*/
+if (in_be32((void *)srds_regs-bank[0].rstctl)
+SRDS_RSTCTL_RSTDONE) {
+ /*
+* Poll the port uninitialized status (SRIO PnESCSR[PO]) until
+* PO=1 or the counter expires. If the counter expires, the
+* port has failed initialization: go to recover steps. If PO=1
+* and the desired port width is 1x, go to normal steps. If
+* PO = 1 and the desired port width is 4x, go to recover steps.
+*/
+ end_tick = usec2ticks(2000) + get_ticks();
+ do
Re: [U-Boot] [PATCH 2/6] powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build target
Hi, Andy, I have sent the updated patches to the patchwork. Do you have more comments? And would you please help to check and apply the patches? http://patchwork.ozlabs.org/patch/176170/ Thanks a lot! Best Regards! Liu Gang On Thu, 2012-08-09 at 23:15 +0800, Liu Gang wrote: On Wed, 2012-08-08 at 18:31 -0500, Andy Fleming wrote: On Thu, Jun 7, 2012 at 1:43 AM, Liu Gang gang@freescale.com wrote: Signed-off-by: Liu Gang gang@freescale.com --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 17 +++-- arch/powerpc/cpu/mpc8xxx/srio.c | 137 --- The change here (and in fsl_pci_init.c in another patch) causes horrible build breakage if you aren't building with the CONFIG_SRIO_PCIE_BOOT_SLAVE option. Please rework so that you can build *without* that option! Andy Hi, Andy, Thanks a lot for your comment. You are right, there will be build breakage when building the non-corenet platform. I have resolved this issue in v2 and have sent the new patches to open source. Please help to check. Thanks! Best Regards, Liu Gang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/6 v2] powerpc/corenet_ds: Update README.srio-boot-corenet
Update some descriptions due to the implementation changes: For master: Get rid of the SRIOBOOT_MASTER build target, and to support for serving as a SRIO boot master via environment variable. For slave: 1. When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. 2. All slave's cores should be in hold off. Signed-off-by: Liu Gang gang@freescale.com --- Changes in v2: - No. doc/README.srio-boot-corenet | 70 -- 1 files changed, 33 insertions(+), 37 deletions(-) diff --git a/doc/README.srio-boot-corenet b/doc/README.srio-boot-corenet index 56b094c..6a13e9c 100644 --- a/doc/README.srio-boot-corenet +++ b/doc/README.srio-boot-corenet @@ -18,7 +18,7 @@ Environment of the SRIO boot: U-Boot images, UCodes will be stored in this flash. d) Slave has its own EEPROM for RCW and PBI. e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot - location to SRIO, and holdoff all the cores if needed. + location to SRIO, and holdoff all the cores. ----- --- | | | | | | @@ -30,63 +30,55 @@ Environment of the SRIO boot: The example based on P4080DS platform: Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO - ports 0 will be connected directly and will be used for the boot from SRIO. + ports 1 will be connected directly and will be used for the boot from SRIO. - 1. Slave's RCW example for boot from SRIO port 0 and core 0 not in holdoff. - : aa55 aa55 010e 0100 0c58 - 0010: 1818 1818 7440 4000 2000 - 0020: f400 0100 - 0030: 0083 - 0040: 0813 8040 698b 93fe - - 2. Slave's RCW example for boot from SRIO port 0 and all cores in holdoff. + 1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff. : aa55 aa55 010e 0100 0c58 0010: 1818 1818 7440 4000 2000 0020: f440 0100 0030: 0083 0040: 0813 8040 063c 778f - 3. Sequence in Step by Step. - a) Update RCW for slave with boot from SRIO port 0 configuration. + 2. Sequence in Step by Step. + a) Update RCW for slave with boot from SRIO port 1 configuration. b) Program slave's U-Boot image, UCode, and ENV parameters into master's NorFlash. - c) Start up master and it will boot up normally from its NorFlash. + c) Set environment variable bootmaster to SRIO1 and save environment + for master. + setenv bootmaster SRIO1 + saveenv + d) Restart up master and it will boot up normally from its NorFlash. Then, it will finish necessary configurations for slave's boot from - SRIO port 0. - d) Master will set inbound SRIO windows covered slave's U-Boot image stored + SRIO port 1. + e) Master will set inbound SRIO windows covered slave's U-Boot image stored in master's NorFlash. - e) Master will set an inbound SRIO window covered slave's UCode stored in - master's NorFlash. - f) Master will set an inbound SRIO window covered slave's ENV stored in - master's NorFlash. - g) If need to release slave's core, master will set outbound SRIO windows - in order to configure slave's registers for the core's releasing. - h) If all cores of slave in holdoff, slave should be powered on before all - the above master's steps, and wait to be released by master. If not all - cores in holdoff, that means core 0 will start up normally, slave should - be powered on after all the above master's steps. In the startup phase - of the slave from SRIO, it will finish some necessary configurations. + f) Master will set an inbound SRIO window covered slave's UCode and ENV + stored in master's NorFlash. + g) Master will set outbound SRIO windows in order to configure slave's + registers for the core's releasing. + h) Since all cores of slave in holdoff, slave should be powered on before all + the above master's
[U-Boot] [PATCH 2/6 v2] powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build target
Get rid of the SRIOBOOT_MASTER build target, and to support for serving as
a SRIO boot master via environment variable. Set the environment variable
bootmaster to SRIO1 or SRIO2 using the following command:
setenv bootmaster SRIO1
saveenv
The bootmaster will enable the function of the SRIO boot master, and
this has the following advantages compared with SRIOBOOT_MASTER build
configuration:
1. Reduce a build configuration item in boards.cfg file.
No longer need to build a special image for master, just use a
normal target image and set the bootmaster variable.
2. No longer need to rebuild an image when change the SRIO port for
boot from SRIO, just set the corresponding value to bootmaster
based on the using SRIO port.
Signed-off-by: Liu Gang gang@freescale.com
---
Changes in v2:
- Rebase.
- Resolve the building breakage for non-corenet platform
- Add the support for p2041rdb platform
arch/powerpc/cpu/mpc85xx/cpu_init.c | 17 +++--
arch/powerpc/cpu/mpc8xxx/srio.c | 137 ---
arch/powerpc/include/asm/fsl_srio.h |8 +--
boards.cfg |4 +-
include/configs/P2041RDB.h | 59 +++
include/configs/corenet_ds.h| 32 ++--
6 files changed, 131 insertions(+), 126 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index fc6c287..94a27f3 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -447,11 +447,18 @@ skip_l2:
#ifdef CONFIG_SYS_SRIO
srio_init();
-#ifdef CONFIG_SRIOBOOT_MASTER
- srio_boot_master();
-#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
- srio_boot_master_release_slave();
-#endif
+#ifdef CONFIG_FSL_CORENET
+ char *s = getenv(bootmaster);
+ if (s) {
+ if (!strcmp(s, SRIO1)) {
+ srio_boot_master(1);
+ srio_boot_master_release_slave(1);
+ }
+ if (!strcmp(s, SRIO2)) {
+ srio_boot_master(2);
+ srio_boot_master_release_slave(2);
+ }
+ }
#endif
#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index c7f3949..ae83d6e 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -95,126 +95,92 @@ void srio_init(void)
}
}
-#ifdef CONFIG_SRIOBOOT_MASTER
-void srio_boot_master(void)
+#ifdef CONFIG_FSL_CORENET
+void srio_boot_master(int port)
{
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
/* set port accept-all */
- out_be32((void *)srio-impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr,
+ out_be32((void *)srio-impl.port[port - 1].ptaacr,
SRIO_PORT_ACCEPT_ALL);
- debug(SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n,
- CONFIG_SRIOBOOT_MASTER_PORT);
+ debug(SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n, port);
/* configure inbound window for slave's u-boot image */
debug(SRIOBOOT - MASTER: Inbound window for slave's image;
Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
- out_be32((void *)srio-atmu
- .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar,
- CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 12);
- out_be32((void *)srio-atmu
- .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar,
- CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 12);
- out_be32((void *)srio-atmu
- .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar,
+ out_be32((void *)srio-atmu.port[port - 1].inbw[0].riwtar,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS 12);
+ out_be32((void *)srio-atmu.port[port - 1].inbw[0].riwbar,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1 12);
+ out_be32((void *)srio-atmu.port[port - 1].inbw[0].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
/* configure inbound window for slave's u-boot image */
debug(SRIOBOOT - MASTER: Inbound window for slave's image;
Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2,
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS,
+ (u64
[U-Boot] [PATCH 4/6 v2] powerpc/corenet_ds: Update README and README.srio-pcie-boot-corenet
Added descriptions about boot from PCIE in the files README and doc/README.srio-pcie-boot-corenet, and changed the name of the doc/README.srio-boot-corenet to doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang gang@freescale.com --- Changes in v2: - No. README| 12 ++-- doc/README.srio-boot-corenet | 99 doc/README.srio-pcie-boot-corenet | 112 + 3 files changed, 118 insertions(+), 105 deletions(-) delete mode 100644 doc/README.srio-boot-corenet create mode 100644 doc/README.srio-pcie-boot-corenet diff --git a/README b/README index fb9d904..81ee7d4 100644 --- a/README +++ b/README @@ -3092,12 +3092,12 @@ to save the current settings. These two #defines specify the address and size of the environment area within the remote memory space. The local device can get the environment from remote memory - space by SRIO or other links. + space by SRIO or PCIE links. BE CAREFUL! For some special cases, the local device can not use saveenv command. For example, the local device will get the -environment stored in a remote NOR flash by SRIO link, but it can -not erase, write this NOR flash by SRIO interface. +environment stored in a remote NOR flash by SRIO or PCIE link, +but it can not erase, write this NOR flash by SRIO or PCIE interface. - CONFIG_ENV_IS_IN_NAND: @@ -3538,9 +3538,9 @@ within that device. - CONFIG_SYS_QE_FMAN_FW_IN_REMOTE Specifies that QE/FMAN firmware is located in the remote (master) memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which - can be mapped from slave TLB-slave LAW-slave SRIO outbound window - -master inbound window-master LAW-the ucode address in master's - NOR flash. + can be mapped from slave TLB-slave LAW-slave SRIO or PCIE outbound + window-master inbound window-master LAW-the ucode address in + master's memory space. Building the Software: == diff --git a/doc/README.srio-boot-corenet b/doc/README.srio-boot-corenet deleted file mode 100644 index 6a13e9c..000 --- a/doc/README.srio-boot-corenet +++ /dev/null @@ -1,99 +0,0 @@ --- -SRIO Boot on Corenet Platforms --- - -For some PowerPC processors with SRIO interface, boot location can be configured -to SRIO by RCW. The processor booting from SRIO can do without flash for u-boot -image, ucode and ENV. All the images can be fetched from another processor's -memory space by SRIO link connected between them. - -This document describes the processes based on an example implemented on P4080DS -platforms and a RCW example with boot from SRIO configuration. - -Environment of the SRIO boot: - a) Master and slave can be SOCs in one board or SOCs in separate boards. - b) They are connected with SRIO links, whether 1x or 4x, and directly or - through switch system. - c) Only Master has NorFlash for booting, and all the Master's and Slave's - U-Boot images, UCodes will be stored in this flash. - d) Slave has its own EEPROM for RCW and PBI. - e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot - location to SRIO, and holdoff all the cores. - - ----- --- - | | | | | | - | | | | | | - | NorFlash|-| Master |SRIO | Slave |[EEPROM] - | | | |===| | - | | | | | | - ----- --- - -The example based on P4080DS platform: - Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO - ports 1 will be connected directly and will be used for the boot from SRIO. - - 1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff. - : aa55 aa55 010e 0100 0c58 - 0010: 1818 1818 7440 4000 2000 - 0020: f440 0100 - 0030: 0083 - 0040: 0813 8040 063c 778f - - 2. Sequence in Step by Step. - a) Update RCW for slave with boot from SRIO port 1 configuration. - b) Program slave's U-Boot image, UCode, and ENV parameters into master's - NorFlash. - c) Set environment variable bootmaster to SRIO1 and save environment - for master. - setenv bootmaster SRIO1 - saveenv - d) Restart up master and it will boot up
[U-Boot] [PATCH 3/6 v2] powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro
When compile the slave image for boot from SRIO, no longer need to
specify which SRIO port it will boot from. The code will get this
information from RCW and then finishes corresponding configurations.
This has the following advantages:
1. No longer need to rebuild an image when change the SRIO port for
boot from SRIO, just rewrite the new RCW with selected port,
then the code will get the port information by reading new RCW.
2. It will be easier to support other boot location options, for
example, boot from PCIE.
Signed-off-by: Liu Gang gang@freescale.com
---
Changes in v2:
- Rebase.
- Add the support for p2041rdb platform
arch/powerpc/include/asm/immap_85xx.h |1 +
board/freescale/common/p_corenet/law.c | 13 -
drivers/misc/fsl_law.c | 27 +++
include/configs/P2041RDB.h |3 ---
include/configs/corenet_ds.h |3 ---
5 files changed, 28 insertions(+), 19 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 53d563e..91228e7 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1758,6 +1758,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR5_DDR_SYNC0x0080
#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
#define FSL_CORENET_RCWSR5_SRDS_EN 0x2000
+#define FSL_CORENET_RCWSR6_BOOT_LOC0x0f80
#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c00 /* bits 162..165 */
#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c /* bits 170..173 */
#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x0040
diff --git a/board/freescale/common/p_corenet/law.c
b/board/freescale/common/p_corenet/law.c
index c4566dd..09ef561 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -48,19 +48,6 @@ struct law_entry law_table[] = {
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
-#ifdef CONFIG_SRIOBOOT_SLAVE
-#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
- SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
- SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
-#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
- SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
- SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
-#endif
-#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index a7d04b7..a71a0ce 100644
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -275,5 +275,32 @@ void init_laws(void)
law_table[i].size, law_table[i].trgt_id);
}
+#ifdef CONFIG_SRIOBOOT_SLAVE
+ /* check RCW to get which port is used for boot */
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u32 bootloc = in_be32(gur-rcwsr[6]);
+ /* in SRIO boot we need to set specail LAWs for SRIO interfaces */
+ switch ((bootloc FSL_CORENET_RCWSR6_BOOT_LOC) 23) {
+ case 0x8: /* boot from SRIO1 */
+ set_next_law(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_1);
+ set_next_law(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_1);
+ break;
+ case 0x9: /* boot from SRIO2 */
+ set_next_law(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_2);
+ set_next_law(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_2);
+ break;
+ default:
+ break;
+ }
+#endif
+
return ;
}
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index f67fbf7..abd9ae0 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -409,9 +409,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
* SRIOBOOT - SLAVE
*/
#ifdef CONFIG_SRIOBOOT_SLAVE
-/* slave port for srioboot */
-#define CONFIG_SRIOBOOT_SLAVE_PORT0
-/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */
#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE0
#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \
(0x3ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR)
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index ba2b0d6..6d4ce48 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs
[U-Boot] [PATCH 5/6 v2] powerpc/corenet_ds: Master module for boot from PCIE
For the powerpc processors with PCIE interface, boot location can be configured from one PCIE interface by RCW. The processor booting from PCIE can do without flash for u-boot image. The image can be fetched from another processor's memory space by PCIE link connected between them. The processor booting from PCIE is slave, the processor booting from normal flash memory space is master, and it can help slave to boot from master's memory space. When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the master module, need to finish these processes: 1. Initialize the PCIE port and address space. 2. Set inbound PCIE windows covered slave's u-boot image stored in master's NOR flash. 3. Set outbound windows in order to configure slave's registers for the core's releasing. 4. Should set the environment variable bootmaster to PCIE1, PCIE2 or PCIE3 using the following command: setenv bootmaster PCIE1 saveenv Signed-off-by: Liu Gang gang@freescale.com --- Changes in v2: - Rebase. - Resolve the building breakage for non-corenet platform. - Add the support for p2041rdb platform. arch/powerpc/cpu/mpc8xxx/srio.c | 44 +++--- drivers/pci/fsl_pci_init.c | 116 +++ include/configs/P2041RDB.h | 18 +++--- include/configs/corenet_ds.h| 18 +++--- 4 files changed, 156 insertions(+), 40 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index ae83d6e..0cb65b3 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -108,44 +108,44 @@ void srio_boot_master(int port) /* configure inbound window for slave's u-boot image */ debug(SRIOBOOT - MASTER: Inbound window for slave's image; Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n, - (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS, - (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1, - CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, + CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); out_be32((void *)srio-atmu.port[port - 1].inbw[0].riwtar, - CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS 12); + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 12); out_be32((void *)srio-atmu.port[port - 1].inbw[0].riwbar, - CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1 12); + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 12); out_be32((void *)srio-atmu.port[port - 1].inbw[0].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); + | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); /* configure inbound window for slave's u-boot image */ debug(SRIOBOOT - MASTER: Inbound window for slave's image; Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n, - (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS, - (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS2, - CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, + CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); out_be32((void *)srio-atmu.port[port - 1].inbw[1].riwtar, - CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS 12); + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 12); out_be32((void *)srio-atmu.port[port - 1].inbw[1].riwbar, - CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS2 12); + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 12); out_be32((void *)srio-atmu.port[port - 1].inbw[1].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); + | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); /* configure inbound window for slave's ucode and ENV */ debug(SRIOBOOT - MASTER
[U-Boot] [PATCH 6/6 v2] powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.
NOTE: Because the slave can not erase, write master's NOR flash by
PCIE interface, so it can not modify the ENV parameters stored
in master's NOR flash using saveenv or other commands.
environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Put the slave's ucode and ENV into it's own memory space.
4. Normally boot from local NOR flash.
5. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to one PCIE interface by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID of one PCIE for the boot.
4. Set a specific TLB entry in order to fetch ucode and ENV from
master.
5. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
6. Slave's u-boot image should be generated specifically by
make _SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF8 and other configurations.
In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
1. Updated the README.srio-boot-corenet to add descriptions about
boot from PCIE, and change the name to
README.srio-pcie-boot-corenet.
2. Changed the compile config _SRIOBOOT_SLAVE to
_SRIO_PCIE_BOOT, and the image builded with
_SRIO_PCIE_BOOT can support both the boot from SRIO and
from PCIE.
3. Updated other macros and documents if needed to add information
about boot from PCIE.
Signed-off-by: Liu Gang gang@freescale.com
---
Changes in v2:
- Rebase.
- Resolve the building breakage for non-corenet platform.
- Add the support for p2041rdb platform.
board/freescale/common/p_corenet/tlb.c | 18 +++---
boards.cfg |8 +++---
common/env_remote.c|4 +-
drivers/misc/fsl_law.c | 39 +++-
include/configs/P2041RDB.h | 28 +++---
include/configs/corenet_ds.h | 28 +++---
6 files changed, 76 insertions(+), 49 deletions(-)
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index da21627..e5cf208 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -66,13 +66,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
-#elif defined(CONFIG_SRIOBOOT_SLAVE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
-* SRIOBOOT-SLAVE. When slave boot, the address of the
+* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
* space is at 0xfff0, it covered the 0xf000.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR,
- CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#else
@@ -147,13 +147,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_1M, 1),
#endif
-#ifdef CONFIG_SRIOBOOT_SLAVE
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/*
-* SRIOBOOT-SLAVE. 1M space from 0xffe0 for fetching ucode
-* and ENV from master
+* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe0 for
+* fetching ucode and ENV from master
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR,
- CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ SET_TLB_ENTRY(1
Re: [U-Boot] [PATCH 2/6] powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build target
On Wed, 2012-08-08 at 18:31 -0500, Andy Fleming wrote: On Thu, Jun 7, 2012 at 1:43 AM, Liu Gang gang@freescale.com wrote: Signed-off-by: Liu Gang gang@freescale.com --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 17 +++-- arch/powerpc/cpu/mpc8xxx/srio.c | 137 --- The change here (and in fsl_pci_init.c in another patch) causes horrible build breakage if you aren't building with the CONFIG_SRIO_PCIE_BOOT_SLAVE option. Please rework so that you can build *without* that option! Andy Hi, Andy, Thanks a lot for your comment. You are right, there will be build breakage when building the non-corenet platform. I have resolved this issue in v2 and have sent the new patches to open source. Please help to check. Thanks! Best Regards, Liu Gang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] powerpc/corenet_ds: Update README.srio-boot-corenet
Hi Andy, It's so long time those patches resided in open source, and there are no any comments. http://patchwork.ozlabs.org/patch/163499/ So could you please help to apply them? Following are some descriptions for this set of patches excerpt from the e-mail sent to you at June 1. .. Now I finished the function based your comment and add the new module of boot from PCIE. Right now we just need to build master image for boot from SRIO and PCIE with normal configuration, for example with: P4080DS_config And then just need to set the environment bootmaster to SRIO1' or PCIE1. For slave image boot from SRIO and PCIE, just need one build target: P4080DS_SRIO_PCIE_BOOT_config Overall, we now just need one special build configuration P4080DS_SRIO_PCIE_BOOT_config for both boot from SRIO and PCIE. .. Thanks a lot! On Thu, 2012-06-07 at 14:43 +0800, Liu Gang wrote: Update some descriptions due to the implementation changes: For master: Get rid of the SRIOBOOT_MASTER build target, and to support for serving as a SRIO boot master via environment variable. For slave: 1. When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. 2. All slave's cores should be in hold off. Signed-off-by: Liu Gang gang@freescale.com --- doc/README.srio-boot-corenet | 70 -- 1 files changed, 33 insertions(+), 37 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/6] powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro
When compile the slave image for boot from SRIO, no longer need to
specify which SRIO port it will boot from. The code will get this
information from RCW and then finishes corresponding configurations.
This has the following advantages:
1. No longer need to rebuild an image when change the SRIO port for
boot from SRIO, just rewrite the new RCW with selected port,
then the code will get the port information by reading new RCW.
2. It will be easier to support other boot location options, for
example, boot from PCIE.
Signed-off-by: Liu Gang gang@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h |1 +
board/freescale/common/p_corenet/law.c | 13 -
drivers/misc/fsl_law.c | 27 +++
include/configs/corenet_ds.h |3 ---
4 files changed, 28 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 632e3c1..48a00b9 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1758,6 +1758,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR5_DDR_SYNC0x0080
#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
#define FSL_CORENET_RCWSR5_SRDS_EN 0x2000
+#define FSL_CORENET_RCWSR6_BOOT_LOC0x0f80
#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c00 /* bits 162..165 */
#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c /* bits 170..173 */
#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x0040
diff --git a/board/freescale/common/p_corenet/law.c
b/board/freescale/common/p_corenet/law.c
index c4566dd..09ef561 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -48,19 +48,6 @@ struct law_entry law_table[] = {
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
-#ifdef CONFIG_SRIOBOOT_SLAVE
-#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
- SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
- SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
-#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
- SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
- SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
-#endif
-#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index a7d04b7..a71a0ce 100644
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -275,5 +275,32 @@ void init_laws(void)
law_table[i].size, law_table[i].trgt_id);
}
+#ifdef CONFIG_SRIOBOOT_SLAVE
+ /* check RCW to get which port is used for boot */
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u32 bootloc = in_be32(gur-rcwsr[6]);
+ /* in SRIO boot we need to set specail LAWs for SRIO interfaces */
+ switch ((bootloc FSL_CORENET_RCWSR6_BOOT_LOC) 23) {
+ case 0x8: /* boot from SRIO1 */
+ set_next_law(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_1);
+ set_next_law(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_1);
+ break;
+ case 0x9: /* boot from SRIO2 */
+ set_next_law(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_2);
+ set_next_law(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_2);
+ break;
+ default:
+ break;
+ }
+#endif
+
return ;
}
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 1f9fdfd..f2e48f5 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -413,9 +413,6 @@
* SRIOBOOT - SLAVE
*/
#ifdef CONFIG_SRIOBOOT_SLAVE
-/* slave port for srioboot */
-#define CONFIG_SRIOBOOT_SLAVE_PORT0
-/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */
#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE0
#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \
(0x3ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR)
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/6] powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build target
Get rid of the SRIOBOOT_MASTER build target, and to support for serving as
a SRIO boot master via environment variable. Set the environment variable
bootmaster to SRIO1 or SRIO2 using the following command:
setenv bootmaster SRIO1
saveenv
The bootmaster will enable the function of the SRIO boot master, and
this has the following advantages compared with SRIOBOOT_MASTER build
configuration:
1. Reduce a build configuration item in boards.cfg file.
No longer need to build a special image for master, just use a
normal target image and set the bootmaster variable.
2. No longer need to rebuild an image when change the SRIO port for
boot from SRIO, just set the corresponding value to bootmaster
based on the using SRIO port.
Signed-off-by: Liu Gang gang@freescale.com
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 17 +++--
arch/powerpc/cpu/mpc8xxx/srio.c | 137 ---
arch/powerpc/include/asm/fsl_srio.h |8 +--
boards.cfg |3 -
include/configs/corenet_ds.h| 32 ++--
5 files changed, 68 insertions(+), 129 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 2cd5db7..4c8b005 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -442,12 +442,17 @@ skip_l2:
#ifdef CONFIG_SYS_SRIO
srio_init();
-#ifdef CONFIG_SRIOBOOT_MASTER
- srio_boot_master();
-#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
- srio_boot_master_release_slave();
-#endif
-#endif
+ char *s = getenv(bootmaster);
+ if (s) {
+ if (!strcmp(s, SRIO1)) {
+ srio_boot_master(1);
+ srio_boot_master_release_slave(1);
+ }
+ if (!strcmp(s, SRIO2)) {
+ srio_boot_master(2);
+ srio_boot_master_release_slave(2);
+ }
+ }
#endif
#if defined(CONFIG_MP)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index c7f3949..0ba7e2a 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -95,126 +95,91 @@ void srio_init(void)
}
}
-#ifdef CONFIG_SRIOBOOT_MASTER
-void srio_boot_master(void)
+void srio_boot_master(int port)
{
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
/* set port accept-all */
- out_be32((void *)srio-impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr,
+ out_be32((void *)srio-impl.port[port - 1].ptaacr,
SRIO_PORT_ACCEPT_ALL);
- debug(SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n,
- CONFIG_SRIOBOOT_MASTER_PORT);
+ debug(SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n, port);
/* configure inbound window for slave's u-boot image */
debug(SRIOBOOT - MASTER: Inbound window for slave's image;
Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
- out_be32((void *)srio-atmu
- .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar,
- CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 12);
- out_be32((void *)srio-atmu
- .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar,
- CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 12);
- out_be32((void *)srio-atmu
- .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar,
+ out_be32((void *)srio-atmu.port[port - 1].inbw[0].riwtar,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS 12);
+ out_be32((void *)srio-atmu.port[port - 1].inbw[0].riwbar,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1 12);
+ out_be32((void *)srio-atmu.port[port - 1].inbw[0].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
/* configure inbound window for slave's u-boot image */
debug(SRIOBOOT - MASTER: Inbound window for slave's image;
Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2,
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS2,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
- out_be32((void *)srio-atmu
- .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwtar
[U-Boot] [PATCH 1/6] powerpc/corenet_ds: Update README.srio-boot-corenet
Update some descriptions due to the implementation changes: For master: Get rid of the SRIOBOOT_MASTER build target, and to support for serving as a SRIO boot master via environment variable. For slave: 1. When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. 2. All slave's cores should be in hold off. Signed-off-by: Liu Gang gang@freescale.com --- doc/README.srio-boot-corenet | 70 -- 1 files changed, 33 insertions(+), 37 deletions(-) diff --git a/doc/README.srio-boot-corenet b/doc/README.srio-boot-corenet index 56b094c..6a13e9c 100644 --- a/doc/README.srio-boot-corenet +++ b/doc/README.srio-boot-corenet @@ -18,7 +18,7 @@ Environment of the SRIO boot: U-Boot images, UCodes will be stored in this flash. d) Slave has its own EEPROM for RCW and PBI. e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot - location to SRIO, and holdoff all the cores if needed. + location to SRIO, and holdoff all the cores. ----- --- | | | | | | @@ -30,63 +30,55 @@ Environment of the SRIO boot: The example based on P4080DS platform: Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO - ports 0 will be connected directly and will be used for the boot from SRIO. + ports 1 will be connected directly and will be used for the boot from SRIO. - 1. Slave's RCW example for boot from SRIO port 0 and core 0 not in holdoff. - : aa55 aa55 010e 0100 0c58 - 0010: 1818 1818 7440 4000 2000 - 0020: f400 0100 - 0030: 0083 - 0040: 0813 8040 698b 93fe - - 2. Slave's RCW example for boot from SRIO port 0 and all cores in holdoff. + 1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff. : aa55 aa55 010e 0100 0c58 0010: 1818 1818 7440 4000 2000 0020: f440 0100 0030: 0083 0040: 0813 8040 063c 778f - 3. Sequence in Step by Step. - a) Update RCW for slave with boot from SRIO port 0 configuration. + 2. Sequence in Step by Step. + a) Update RCW for slave with boot from SRIO port 1 configuration. b) Program slave's U-Boot image, UCode, and ENV parameters into master's NorFlash. - c) Start up master and it will boot up normally from its NorFlash. + c) Set environment variable bootmaster to SRIO1 and save environment + for master. + setenv bootmaster SRIO1 + saveenv + d) Restart up master and it will boot up normally from its NorFlash. Then, it will finish necessary configurations for slave's boot from - SRIO port 0. - d) Master will set inbound SRIO windows covered slave's U-Boot image stored + SRIO port 1. + e) Master will set inbound SRIO windows covered slave's U-Boot image stored in master's NorFlash. - e) Master will set an inbound SRIO window covered slave's UCode stored in - master's NorFlash. - f) Master will set an inbound SRIO window covered slave's ENV stored in - master's NorFlash. - g) If need to release slave's core, master will set outbound SRIO windows - in order to configure slave's registers for the core's releasing. - h) If all cores of slave in holdoff, slave should be powered on before all - the above master's steps, and wait to be released by master. If not all - cores in holdoff, that means core 0 will start up normally, slave should - be powered on after all the above master's steps. In the startup phase - of the slave from SRIO, it will finish some necessary configurations. + f) Master will set an inbound SRIO window covered slave's UCode and ENV + stored in master's NorFlash. + g) Master will set outbound SRIO windows in order to configure slave's + registers for the core's releasing. + h) Since all cores of slave in holdoff, slave should be powered on before all + the above master's steps, and wait
[U-Boot] [PATCH 4/6] powerpc/corenet_ds: Update README and README.srio-pcie-boot-corenet
Added descriptions about boot from PCIE in the files README and doc/README.srio-pcie-boot-corenet, and changed the name of the doc/README.srio-boot-corenet to doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang gang@freescale.com --- README| 12 ++-- doc/README.srio-boot-corenet | 99 doc/README.srio-pcie-boot-corenet | 112 + 3 files changed, 118 insertions(+), 105 deletions(-) delete mode 100644 doc/README.srio-boot-corenet create mode 100644 doc/README.srio-pcie-boot-corenet diff --git a/README b/README index 6919392..fda7ddc 100644 --- a/README +++ b/README @@ -3045,12 +3045,12 @@ to save the current settings. These two #defines specify the address and size of the environment area within the remote memory space. The local device can get the environment from remote memory - space by SRIO or other links. + space by SRIO or PCIE links. BE CAREFUL! For some special cases, the local device can not use saveenv command. For example, the local device will get the -environment stored in a remote NOR flash by SRIO link, but it can -not erase, write this NOR flash by SRIO interface. +environment stored in a remote NOR flash by SRIO or PCIE link, +but it can not erase, write this NOR flash by SRIO or PCIE interface. - CONFIG_ENV_IS_IN_NAND: @@ -3491,9 +3491,9 @@ within that device. - CONFIG_SYS_QE_FMAN_FW_IN_REMOTE Specifies that QE/FMAN firmware is located in the remote (master) memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which - can be mapped from slave TLB-slave LAW-slave SRIO outbound window - -master inbound window-master LAW-the ucode address in master's - NOR flash. + can be mapped from slave TLB-slave LAW-slave SRIO or PCIE outbound + window-master inbound window-master LAW-the ucode address in + master's memory space. Building the Software: == diff --git a/doc/README.srio-boot-corenet b/doc/README.srio-boot-corenet deleted file mode 100644 index 6a13e9c..000 --- a/doc/README.srio-boot-corenet +++ /dev/null @@ -1,99 +0,0 @@ --- -SRIO Boot on Corenet Platforms --- - -For some PowerPC processors with SRIO interface, boot location can be configured -to SRIO by RCW. The processor booting from SRIO can do without flash for u-boot -image, ucode and ENV. All the images can be fetched from another processor's -memory space by SRIO link connected between them. - -This document describes the processes based on an example implemented on P4080DS -platforms and a RCW example with boot from SRIO configuration. - -Environment of the SRIO boot: - a) Master and slave can be SOCs in one board or SOCs in separate boards. - b) They are connected with SRIO links, whether 1x or 4x, and directly or - through switch system. - c) Only Master has NorFlash for booting, and all the Master's and Slave's - U-Boot images, UCodes will be stored in this flash. - d) Slave has its own EEPROM for RCW and PBI. - e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot - location to SRIO, and holdoff all the cores. - - ----- --- - | | | | | | - | | | | | | - | NorFlash|-| Master |SRIO | Slave |[EEPROM] - | | | |===| | - | | | | | | - ----- --- - -The example based on P4080DS platform: - Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO - ports 1 will be connected directly and will be used for the boot from SRIO. - - 1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff. - : aa55 aa55 010e 0100 0c58 - 0010: 1818 1818 7440 4000 2000 - 0020: f440 0100 - 0030: 0083 - 0040: 0813 8040 063c 778f - - 2. Sequence in Step by Step. - a) Update RCW for slave with boot from SRIO port 1 configuration. - b) Program slave's U-Boot image, UCode, and ENV parameters into master's - NorFlash. - c) Set environment variable bootmaster to SRIO1 and save environment - for master. - setenv bootmaster SRIO1 - saveenv - d) Restart up master and it will boot up normally from its
[U-Boot] [PATCH 6/6] powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.
NOTE: Because the slave can not erase, write master's NOR flash by
PCIE interface, so it can not modify the ENV parameters stored
in master's NOR flash using saveenv or other commands.
environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Put the slave's ucode and ENV into it's own memory space.
4. Normally boot from local NOR flash.
5. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to one PCIE interface by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID of one PCIE for the boot.
4. Set a specific TLB entry in order to fetch ucode and ENV from
master.
5. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
6. Slave's u-boot image should be generated specifically by
make _SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF8 and other configurations.
In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
1. Updated the README.srio-boot-corenet to add descriptions about
boot from PCIE, and change the name to
README.srio-pcie-boot-corenet.
2. Changed the compile config _SRIOBOOT_SLAVE to
_SRIO_PCIE_BOOT, and the image builded with
_SRIO_PCIE_BOOT can support both the boot from SRIO and
from PCIE.
3. Updated other macros and documents if needed to add information
about boot from PCIE.
Signed-off-by: Liu Gang gang@freescale.com
---
board/freescale/common/p_corenet/tlb.c | 18 +++---
boards.cfg |6 ++--
common/env_remote.c|4 +-
drivers/misc/fsl_law.c | 39 +++-
include/configs/corenet_ds.h | 28 +++---
5 files changed, 61 insertions(+), 34 deletions(-)
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index da21627..e5cf208 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -66,13 +66,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
-#elif defined(CONFIG_SRIOBOOT_SLAVE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
-* SRIOBOOT-SLAVE. When slave boot, the address of the
+* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
* space is at 0xfff0, it covered the 0xf000.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR,
- CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#else
@@ -147,13 +147,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_1M, 1),
#endif
-#ifdef CONFIG_SRIOBOOT_SLAVE
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/*
-* SRIOBOOT-SLAVE. 1M space from 0xffe0 for fetching ucode
-* and ENV from master
+* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe0 for
+* fetching ucode and ENV from master
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR,
- CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 17, BOOKE_PAGESZ_1M, 1),
#endif
diff --git a/boards.cfg b
[U-Boot] [PATCH 5/6] powerpc/corenet_ds: Master module for boot from PCIE
For the powerpc processors with PCIE interface, boot location can be configured from one PCIE interface by RCW. The processor booting from PCIE can do without flash for u-boot image. The image can be fetched from another processor's memory space by PCIE link connected between them. The processor booting from PCIE is slave, the processor booting from normal flash memory space is master, and it can help slave to boot from master's memory space. When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the master module, need to finish these processes: 1. Initialize the PCIE port and address space. 2. Set inbound PCIE windows covered slave's u-boot image stored in master's NOR flash. 3. Set outbound windows in order to configure slave's registers for the core's releasing. 4. Should set the environment variable bootmaster to PCIE1, PCIE2 or PCIE3 using the following command: setenv bootmaster PCIE1 saveenv Signed-off-by: Liu Gang gang@freescale.com --- arch/powerpc/cpu/mpc8xxx/srio.c | 44 drivers/pci/fsl_pci_init.c | 111 ++- include/configs/corenet_ds.h| 18 +++--- 3 files changed, 140 insertions(+), 33 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index 0ba7e2a..02b830d 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -107,44 +107,44 @@ void srio_boot_master(int port) /* configure inbound window for slave's u-boot image */ debug(SRIOBOOT - MASTER: Inbound window for slave's image; Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n, - (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS, - (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1, - CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, + CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); out_be32((void *)srio-atmu.port[port - 1].inbw[0].riwtar, - CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS 12); + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 12); out_be32((void *)srio-atmu.port[port - 1].inbw[0].riwbar, - CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1 12); + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 12); out_be32((void *)srio-atmu.port[port - 1].inbw[0].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); + | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); /* configure inbound window for slave's u-boot image */ debug(SRIOBOOT - MASTER: Inbound window for slave's image; Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n, - (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS, - (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS2, - CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, + CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); out_be32((void *)srio-atmu.port[port - 1].inbw[1].riwtar, - CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS 12); + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 12); out_be32((void *)srio-atmu.port[port - 1].inbw[1].riwbar, - CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS2 12); + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 12); out_be32((void *)srio-atmu.port[port - 1].inbw[1].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); + | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); /* configure inbound window for slave's ucode and ENV */ debug(SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n, - (u64
Re: [U-Boot] [PATCH 3/4 V2] USB: Drop cache flush bloat in EHCI-HCD
Hi Marek, On Thu, 2012-05-24 at 15:21 +0200, Marek Vasut wrote: drivers/usb/host/ehci-hcd.c | 127 +-- 1 files changed, 27 insertions(+), 100 deletions(-) Unfortunately this patch breaks compiling for many powerpc boards, mpc512x, mpc83xx, mpc85xx and QorIQ Px based with USB support enabled. Because they have broken cache implementation, right? I mean, they have their own snooping methods, so they don't need the cache flushing at all, but then, if they don't, these methods (dcache_flush() etc) should be optimized to empty functions. Maybe we should implement them for these CPUs then? btw. I thought these compiled before, hm... Now this patch has been applied at master branch, but the building for powerpc boards as Anatolij mentioned will be failed. So Which platforms this patch applies to? If they all can not flush cache like the powerpc snooping methods? Thanks! Best Regards! Liu Gang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] MPC8xxx: Define cache ops for USB
Dear Marek, On Fri, 2012-05-25 at 14:24 +0200, Marek Vasut wrote: arch/powerpc/cpu/mpc83xx/Makefile |3 +++ arch/powerpc/cpu/mpc83xx/cache.c | 33 + arch/powerpc/cpu/mpc85xx/Makefile |3 +++ arch/powerpc/cpu/mpc85xx/cache.c | 33 + 4 files changed, 72 insertions(+) create mode 100644 arch/powerpc/cpu/mpc83xx/cache.c create mode 100644 arch/powerpc/cpu/mpc85xx/cache.c There is a cache.c at the path arch/powerpc/lib, and I think it may be better to put those dummy functions in this file. And thanks your information about this patch in another mail. Best Regards, Liu Gang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/8 v4] powerpc/srio: Rewrite the struct ccsr_rio
Hi, Andy, Can you help to apply this set of patches? Thanks a lot. --- Best Regards, Liu Gang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/8 v4] powerpc/corenet_ds: Correct the compilation errors about ENV
When defined CONFIG_ENV_IS_NOWHERE, there will be some compilation errors: ./common/env_nowhere.o: In function `env_relocate_spec': ./common/env_nowhere.c:38: multiple definition of `env_relocate_spec' ./common/env_flash.o: ./common/env_flash.c:326: first defined here ./common/env_nowhere.o: In function `env_get_char_spec': ./common/env_nowhere.c:42: multiple definition of `env_get_char_spec' ./common/env_flash.o:./common/env_flash.c:78: first defined here ./common/env_nowhere.o: In function `env_init': ./common/env_nowhere.c:51: multiple definition of `env_init' ./common/env_flash.o:./common/env_flash.c:237: first defined here make[1]: *** [./common/libcommon.o] Error 1 make[1]: Leaving directory `./common' make: *** [./common/libcommon.o] Error 2 Remove the CONFIG_ENV_IS_IN_FLASH if defined CONFIG_ENV_IS_NOWHERE. Signed-off-by: Liu Gang gang@freescale.com --- Changes in v2: - Subject changed to powerpc/corenet_ds. - Change the commit message more clearly. Changes in v3: - No Changes in v4: - No include/configs/corenet_ds.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 77dd0a2..fd8291e 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -97,6 +97,8 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZECONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE0x2000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -- 1.7.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/8 v4] powerpc/srio: Rewrite the struct ccsr_rio
Rewrite this struct for the support of two ports and two message
units registers.
Signed-off-by: Liu Gang gang@freescale.com
---
Changes in v2:
- Change the subject and commit message.
- Remove the offsets in the comments.
- Rewrite the struct for the support of two ports
and two message units registers.
Changes in v3:
- Move some SRIO macros to the appropriate board
configure header files.
Changes in v4:
- Move some SRIO macros to the file
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/config_mpc85xx.h | 34 +++
arch/powerpc/include/asm/immap_85xx.h | 384 +
2 files changed, 258 insertions(+), 160 deletions(-)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 8654625..94755c5 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -65,6 +65,11 @@
#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_MPC8555)
#define CONFIG_MAX_CPUS1
@@ -85,6 +90,11 @@
#define MAX_QE_RISC2
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_MPC8569)
#define CONFIG_MAX_CPUS1
@@ -94,6 +104,11 @@
#define MAX_QE_RISC4
#define QE_NUM_OF_SNUM 46
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_MPC8572)
#define CONFIG_MAX_CPUS2
@@ -298,6 +313,11 @@
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_PPC_P2040)
#define CONFIG_MAX_CPUS4
@@ -338,6 +358,9 @@
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_PPC_P3041)
#define CONFIG_MAX_CPUS4
@@ -359,6 +382,9 @@
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_PPC_P3060)
#define CONFIG_MAX_CPUS8
@@ -417,6 +443,11 @@
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
/* P5010 is single core version of P5020 */
#elif defined(CONFIG_PPC_P5010)
@@ -458,6 +489,9 @@
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#else
#error Processor type not defined for this platform
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 9b08cb8..c4d241b 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1353,171 +1353,235 @@ typedef struct ccsr_cpm {
} ccsr_cpm_t;
#endif
-/* RapidIO Registers */
-typedef struct ccsr_rio {
- u32 didcar; /* Device Identity Capability */
- u32 dicar; /* Device Information Capability */
- u32 aidcar; /* Assembly Identity Capability */
- u32 aicar; /* Assembly Information Capability */
- u32 pefcar; /* Processing Element Features Capability */
- u32 spicar; /* Switch Port Information Capability */
- u32 socar; /* Source
[U-Boot] [PATCH 3/8 v4] powerpc/corenet_ds: Document for the boot from SRIO
This document describes the implementation of the boot from SRIO, includes the introduction of envionment, an example based on P4080DS platform, an example of the slave's RCW, and the description about how to use this feature. Signed-off-by: Liu Gang gang@freescale.com --- Changes in v2: - Subject changed to powerpc/corenet_ds. - Change the name of the document for corenet platform. Changes in v3: - No Changes in v4: - No doc/README.srio-boot-corenet | 103 ++ 1 files changed, 103 insertions(+), 0 deletions(-) create mode 100644 doc/README.srio-boot-corenet diff --git a/doc/README.srio-boot-corenet b/doc/README.srio-boot-corenet new file mode 100644 index 000..56b094c --- /dev/null +++ b/doc/README.srio-boot-corenet @@ -0,0 +1,103 @@ +-- +SRIO Boot on Corenet Platforms +-- + +For some PowerPC processors with SRIO interface, boot location can be configured +to SRIO by RCW. The processor booting from SRIO can do without flash for u-boot +image, ucode and ENV. All the images can be fetched from another processor's +memory space by SRIO link connected between them. + +This document describes the processes based on an example implemented on P4080DS +platforms and a RCW example with boot from SRIO configuration. + +Environment of the SRIO boot: + a) Master and slave can be SOCs in one board or SOCs in separate boards. + b) They are connected with SRIO links, whether 1x or 4x, and directly or + through switch system. + c) Only Master has NorFlash for booting, and all the Master's and Slave's + U-Boot images, UCodes will be stored in this flash. + d) Slave has its own EEPROM for RCW and PBI. + e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot + location to SRIO, and holdoff all the cores if needed. + + ----- --- + | | | | | | + | | | | | | + | NorFlash|-| Master |SRIO | Slave |[EEPROM] + | | | |===| | + | | | | | | + ----- --- + +The example based on P4080DS platform: + Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO + ports 0 will be connected directly and will be used for the boot from SRIO. + + 1. Slave's RCW example for boot from SRIO port 0 and core 0 not in holdoff. + : aa55 aa55 010e 0100 0c58 + 0010: 1818 1818 7440 4000 2000 + 0020: f400 0100 + 0030: 0083 + 0040: 0813 8040 698b 93fe + + 2. Slave's RCW example for boot from SRIO port 0 and all cores in holdoff. + : aa55 aa55 010e 0100 0c58 + 0010: 1818 1818 7440 4000 2000 + 0020: f440 0100 + 0030: 0083 + 0040: 0813 8040 063c 778f + + 3. Sequence in Step by Step. + a) Update RCW for slave with boot from SRIO port 0 configuration. + b) Program slave's U-Boot image, UCode, and ENV parameters into master's + NorFlash. + c) Start up master and it will boot up normally from its NorFlash. + Then, it will finish necessary configurations for slave's boot from + SRIO port 0. + d) Master will set inbound SRIO windows covered slave's U-Boot image stored + in master's NorFlash. + e) Master will set an inbound SRIO window covered slave's UCode stored in + master's NorFlash. + f) Master will set an inbound SRIO window covered slave's ENV stored in + master's NorFlash. + g) If need to release slave's core, master will set outbound SRIO windows + in order to configure slave's registers for the core's releasing. + h) If all cores of slave in holdoff, slave should be powered on before all + the above master's steps, and wait to be released by master. If not all + cores in holdoff, that means core 0 will start up normally, slave should + be powered on after all the above master's steps. In the startup phase + of the slave from SRIO, it will finish some necessary configurations. + i) Slave will set a specific TLB entry for the boot process
[U-Boot] [PATCH 4/8 v4] powerpc/corenet_ds: Master module for boot from SRIO
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure SRIO switch system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to SRIO1 or SRIO2 by RCW.
3. RCW should configure the SerDes, SRIO interfaces correctly.
4. Slave must be powered on after master's boot.
For the master module, need to finish these processes:
1. Initialize the SRIO port and address space.
2. Set inbound SRIO windows covered slave's u-boot image stored in
master's NOR flash.
3. Master's u-boot image should be generated specifically by
make _SRIOBOOT_MASTER_config
4. Master must boot first, and then slave can be powered on.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Changes in v2:
- Subject changed to powerpc/corenet_ds.
- Use (void *) instead of (u32) when calling out_be32().
- Use NOR flash instead of Nor flash.
- Get rid of the base address + offset notation. Use C structs
instead.
- Get rid of hard coded magic numbers. Use macro instead.
- Use debug() instead of printf().
Changes in v3:
- No
Changes in v4:
- No
arch/powerpc/cpu/mpc85xx/cpu_init.c |6 ++-
arch/powerpc/cpu/mpc8xxx/srio.c | 51 +++
arch/powerpc/include/asm/fsl_srio.h | 61 +
arch/powerpc/include/asm/immap_85xx.h |3 ++
boards.cfg|3 ++
include/configs/corenet_ds.h | 18 ++
6 files changed, 140 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/include/asm/fsl_srio.h
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 2e4a06c..97a7fe1 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -37,6 +37,7 @@
#include asm/mmu.h
#include asm/fsl_law.h
#include asm/fsl_serdes.h
+#include asm/fsl_srio.h
#include linux/compiler.h
#include mp.h
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
@@ -48,8 +49,6 @@
DECLARE_GLOBAL_DATA_PTR;
-extern void srio_init(void);
-
#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -443,6 +442,9 @@ skip_l2:
#ifdef CONFIG_SYS_SRIO
srio_init();
+#ifdef CONFIG_SRIOBOOT_MASTER
+ srio_boot_master();
+#endif
#endif
#if defined(CONFIG_MP)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index e46d328..77fa32f 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -21,6 +21,10 @@
#include config.h
#include asm/fsl_law.h
#include asm/fsl_serdes.h
+#include asm/fsl_srio.h
+
+#define SRIO_PORT_ACCEPT_ALL 0x1001
+#define SRIO_IB_ATMU_AR 0x80f55000
#if defined(CONFIG_FSL_CORENET)
#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
@@ -84,3 +88,50 @@ void srio_init(void)
setbits_be32(gur-devdisr, _DEVDISR_RMU);
}
}
+
+#ifdef CONFIG_SRIOBOOT_MASTER
+void srio_boot_master(void)
+{
+ struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+
+ /* set port accept-all */
+ out_be32((void *)srio-impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr,
+ SRIO_PORT_ACCEPT_ALL);
+
+ debug(SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n,
+ CONFIG_SRIOBOOT_MASTER_PORT);
+ /* configure inbound window5 for slave's u-boot image */
+ debug(SRIOBOOT - MASTER: Inbound window 5 for slave's image;
+ Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar
[U-Boot] [PATCH 8/8 v4] powerpc/corenet_ds: Slave core in holdoff when boot from SRIO
When boot from SRIO, slave's core can be in holdoff after powered on for
some specific requirements. Master can release the slave's core at the
right time by SRIO interface.
Master needs to:
1. Set outbound SRIO windows in order to configure slave's registers
for the core's releasing.
2. Check the SRIO port status when release slave core, if no errors,
will implement the process of the slave core's releasing.
Slave needs to:
1. Set all the cores in holdoff by RCW.
2. Be powered on before master's boot.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Changes in v2:
- Subject changed to powerpc/corenet_ds.
- Use (void *) instead of (u32) when calling out_be32().
- Use NOR flash instead of Nor flash.
- Get rid of the base address + offset notation. Use C structs
instead.
- Get rid of hard coded magic numbers. Use macro instead.
- Use debug() instead of printf().
Changes in v3:
- No
Changes in v4:
- No
arch/powerpc/cpu/mpc85xx/cpu_init.c |3 +
arch/powerpc/cpu/mpc8xxx/srio.c | 125 +++
arch/powerpc/include/asm/fsl_srio.h |3 +
include/configs/corenet_ds.h|4 +
4 files changed, 135 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 97a7fe1..2cd5db7 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -444,6 +444,9 @@ skip_l2:
srio_init();
#ifdef CONFIG_SRIOBOOT_MASTER
srio_boot_master();
+#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
+ srio_boot_master_release_slave();
+#endif
#endif
#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 5694561..c7f3949 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -25,6 +25,12 @@
#define SRIO_PORT_ACCEPT_ALL 0x1001
#define SRIO_IB_ATMU_AR 0x80f55000
+#define SRIO_OB_ATMU_AR_MAINT 0x80077000
+#define SRIO_OB_ATMU_AR_RW 0x80045000
+#define SRIO_LCSBA1CSR_OFFSET 0x5c
+#define SRIO_MAINT_WIN_SIZE 0x100 /* 16M */
+#define SRIO_RW_WIN_SIZE 0x10 /* 1M */
+#define SRIO_LCSBA1CSR 0x6000
#if defined(CONFIG_FSL_CORENET)
#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
@@ -168,4 +174,123 @@ void srio_boot_master(void)
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE));
}
+
+#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
+void srio_boot_master_release_slave(void)
+{
+ struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+ u32 escsr;
+ debug(SRIOBOOT - MASTER:
+ Check the port status and release slave core ...\n);
+
+ escsr = in_be32((void *)srio-lp_serial
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].pescsr);
+ if (escsr 0x2) {
+ if (escsr 0x10100) {
+ debug(SRIOBOOT - MASTER: Port [ %d ] is error.\n,
+ CONFIG_SRIOBOOT_MASTER_PORT);
+ } else {
+ debug(SRIOBOOT - MASTER:
+ Port [ %d ] is ready, now release
slave's core ...\n,
+ CONFIG_SRIOBOOT_MASTER_PORT);
+ /*
+* configure outbound window
+* with maintenance attribute to set slave's LCSBA1CSR
+*/
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowtar, 0);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowtear, 0);
+ if (CONFIG_SRIOBOOT_MASTER_PORT)
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowbar,
+ CONFIG_SYS_SRIO2_MEM_PHYS 12);
+ else
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowbar,
+ CONFIG_SYS_SRIO1_MEM_PHYS 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowar,
+ SRIO_OB_ATMU_AR_MAINT
+ | atmu_size_mask(SRIO_MAINT_WIN_SIZE));
+
+ /*
+* configure outbound window
+* with R/W attribute to set slave's BRR
[U-Boot] [PATCH 5/8 v4] powerpc/corenet_ds: Slave module for boot from SRIO
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure SRIO switch system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to SRIO1 or SRIO2 by RCW.
3. RCW should configure the SerDes, SRIO interfaces correctly.
4. Slave must be powered on after master's boot.
5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode
locally.
For the slave module, need to finish these processes:
1. Set the boot location to SRIO1 or SRIO2 by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot.
4. Slave's u-boot image should be generated specifically by
make _SRIOBOOT_SLAVE_config.
This will set SYS_TEXT_BASE=0xFFF8 and other configurations.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Changes in v2:
- Subject changed to powerpc/corenet_ds.
- Use (void *) instead of (u32) when calling out_be32().
- Use NOR flash instead of Nor flash.
- Get rid of the base address + offset notation. Use C structs
instead.
- Get rid of hard coded magic numbers. Use macro instead.
- Use debug() instead of printf().
- Add the description for CONFIG_SYS_QE_FMAN_FW_IN_REMOTE and also
update the README for this.
Changes in v3:
- No
Changes in v4:
- No
README |6 ++
board/freescale/common/p_corenet/law.c |9 +
board/freescale/common/p_corenet/tlb.c |9 +
boards.cfg |3 +++
drivers/net/fm/fm.c|2 ++
include/configs/corenet_ds.h | 28
6 files changed, 57 insertions(+), 0 deletions(-)
diff --git a/README b/README
index 8964672..f8f6c0f 100644
--- a/README
+++ b/README
@@ -3384,6 +3384,12 @@ within that device.
Specifies that QE/FMAN firmware is located on the primary SPI
device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
+- CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+ Specifies that QE/FMAN firmware is located in the remote (master)
+ memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
+ can be mapped from slave TLB-slave LAW-slave SRIO outbound window
+ -master inbound window-master LAW-the ucode address in master's
+ NOR flash.
Building the Software:
==
diff --git a/board/freescale/common/p_corenet/law.c
b/board/freescale/common/p_corenet/law.c
index 09ef561..1fbab4d 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -48,6 +48,15 @@ struct law_entry law_table[] = {
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
+#ifdef CONFIG_SRIOBOOT_SLAVE
+#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
+ SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
+#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
+ SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
+#endif
+#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index 6a0026a..a8c8b3c 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -66,6 +66,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIOBOOT_SLAVE)
+ /*
+* SRIOBOOT-SLAVE. When slave boot, the address of the
+* space is at 0xfff0, it covered the 0xf000.
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
#else
SET_TLB_ENTRY(1, 0xf000, 0xf000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
diff --git a/boards.cfg b/boards.cfg
[U-Boot] [PATCH 6/8 v4] powerpc/corenet_ds: Slave uploads ucode when boot from SRIO
When boot from SRIO, slave's ucode can be stored in master's memory space,
then slave can fetch the ucode image through SRIO interface. For the
corenet platform, ucode is for Fman.
Master needs to:
1. Put the slave's ucode image into it's own memory space.
2. Set an inbound SRIO window covered slave's ucode stored in master's
memory space.
Slave needs to:
1. Set a specific TLB entry in order to fetch ucode from master.
2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Changes in v2:
- Subject changed to powerpc/corenet_ds.
- Use (void *) instead of (u32) when calling out_be32().
- Use NOR flash instead of Nor flash.
- Get rid of the base address + offset notation. Use C structs
instead.
- Get rid of hard coded magic numbers. Use macro instead.
- Use debug() instead of printf().
- Correct some comment style errors.
Changes in v3:
- No
Changes in v4:
- No
arch/powerpc/cpu/mpc8xxx/srio.c| 25 +
board/freescale/common/p_corenet/law.c |4
board/freescale/common/p_corenet/tlb.c | 10 ++
include/configs/corenet_ds.h | 12 +++-
4 files changed, 46 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 77fa32f..e593f22 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -100,8 +100,8 @@ void srio_boot_master(void)
debug(SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n,
CONFIG_SRIOBOOT_MASTER_PORT);
- /* configure inbound window5 for slave's u-boot image */
- debug(SRIOBOOT - MASTER: Inbound window 5 for slave's image;
+ /* configure inbound window for slave's u-boot image */
+ debug(SRIOBOOT - MASTER: Inbound window for slave's image;
Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,
@@ -117,8 +117,8 @@ void srio_boot_master(void)
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
- /* configure inbound window4 for slave's u-boot image */
- debug(SRIOBOOT - MASTER: Inbound window 4 for slave's image;
+ /* configure inbound window for slave's u-boot image */
+ debug(SRIOBOOT - MASTER: Inbound window for slave's image;
Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2,
@@ -133,5 +133,22 @@ void srio_boot_master(void)
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
+
+ /* configure inbound window for slave's ucode */
+ debug(SRIOBOOT - MASTER: Inbound window for slave's ucode;
+ Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
+ (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS,
+ (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS,
+ CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwtar,
+ CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwbar,
+ CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwar,
+ SRIO_IB_ATMU_AR
+ | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE));
}
#endif
diff --git a/board/freescale/common/p_corenet/law.c
b/board/freescale/common/p_corenet/law.c
index 1fbab4d..c4566dd 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -52,9 +52,13 @@ struct law_entry law_table[] = {
#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
+ SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
+ SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
#endif
#endif
};
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index a8c8b3c
[U-Boot] [PATCH 7/8 v4] powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO
When boot from SRIO, slave's ENV can be stored in master's memory space,
then slave can fetch the ENV through SRIO interface.
NOTE: Because the slave can not erase, write master's NOR flash by SRIO
interface, so it can not modify the ENV parameters stored in
master's NOR flash using saveenv or other commands.
Master needs to:
1. Put the slave's ENV into it's own memory space.
2. Set an inbound SRIO window covered slave's ENV stored in master's
memory space.
Slave needs to:
1. Set a specific TLB entry in order to fetch ucode and ENV from master.
2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Changes in v2:
- Subject changed to powerpc/corenet_ds.
- Update the README for CONFIG_ENV_IS_IN_REMOTE.
- Use (void *) instead of (u32) when calling out_be32().
- Use NOR flash instead of Nor flash.
- Get rid of the base address + offset notation. Use C structs
instead.
- Get rid of hard coded magic numbers. Use macro instead.
- Use debug() instead of printf().
- Some code styles changed.
Changes in v3:
- No
Changes in v4:
- No
README | 18 +
arch/powerpc/cpu/mpc8xxx/srio.c | 17
common/Makefile |1 +
common/cmd_nvedit.c |3 +-
common/env_remote.c | 79 +++
include/configs/corenet_ds.h| 13 ++
6 files changed, 130 insertions(+), 1 deletions(-)
create mode 100644 common/env_remote.c
diff --git a/README b/README
index f8f6c0f..6389371 100644
--- a/README
+++ b/README
@@ -2943,6 +2943,24 @@ to save the current settings.
environment area within the total memory of your DataFlash placed
at the specified address.
+- CONFIG_ENV_IS_IN_REMOTE:
+
+ Define this if you have a remote memory space which you
+ want to use for the local device's environment.
+
+ - CONFIG_ENV_ADDR:
+ - CONFIG_ENV_SIZE:
+
+ These two #defines specify the address and size of the
+ environment area within the remote memory space. The
+ local device can get the environment from remote memory
+ space by SRIO or other links.
+
+BE CAREFUL! For some special cases, the local device can not use
+saveenv command. For example, the local device will get the
+environment stored in a remote NOR flash by SRIO link, but it can
+not erase, write this NOR flash by SRIO interface.
+
- CONFIG_ENV_IS_IN_NAND:
Define this if you have a NAND device which you want to use
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index e593f22..5694561 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -150,5 +150,22 @@ void srio_boot_master(void)
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE));
+
+ /* configure inbound window for slave's ENV */
+ debug(SRIOBOOT - MASTER: Inbound window for slave's ENV;
+ Local = 0x%llx, Siro = 0x%llx, Size = 0x%x\n,
+ CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS,
+ CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS,
+ CONFIG_SRIOBOOT_SLAVE_ENV_SIZE);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwtar,
+ CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwbar,
+ CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwar,
+ SRIO_IB_ATMU_AR
+ | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE));
}
#endif
diff --git a/common/Makefile b/common/Makefile
index 2a31c62..4b6f054 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -58,6 +58,7 @@ COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o
COBJS-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
+COBJS-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
# command
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index 22f9821..5a0ddd0 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -65,9 +65,10 @@ DECLARE_GLOBAL_DATA_PTR;
!defined(CONFIG_ENV_IS_IN_NVRAM) \
!defined(CONFIG_ENV_IS_IN_ONENAND) \
!defined(CONFIG_ENV_IS_IN_SPI_FLASH) \
+ !defined(CONFIG_ENV_IS_IN_REMOTE)\
!defined(CONFIG_ENV_IS_NOWHERE)
# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH
Re: [U-Boot] [PATCH 1/8 v3] powerpc/srio: Rewrite the struct ccsr_rio
Hi, Andy, On Tue, 2012-03-06 at 16:30 -0600, Andy Fleming wrote: arch/powerpc/include/asm/immap_85xx.h | 384 +++-- include/configs/MPC8548CDS.h |5 + include/configs/MPC8568MDS.h |5 + include/configs/MPC8569MDS.h |5 + include/configs/P2020DS.h |5 + include/configs/P2041RDB.h|3 + include/configs/corenet_ds.h |7 + It occurs to me that these defines are really better suited for arch/powerpc/include/asm/config_mpc85xx.h. Notice that's where the other SOC-specific configs (like number of devices) are kept. Changing things there will make it easier to support different boards. Yeah,I think your comment should be better, and that may be clearer and easier for these defines to support different boards with the file .../config_mpc85xx.h. I'll do some tests and update the patches based on your comment. Thanks a lot! Liu Gang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/8 v3] powerpc/corenet_ds: Correct the compilation errors about ENV
When defined CONFIG_ENV_IS_NOWHERE, there will be some compilation errors: ./common/env_nowhere.o: In function `env_relocate_spec': ./common/env_nowhere.c:38: multiple definition of `env_relocate_spec' ./common/env_flash.o: ./common/env_flash.c:326: first defined here ./common/env_nowhere.o: In function `env_get_char_spec': ./common/env_nowhere.c:42: multiple definition of `env_get_char_spec' ./common/env_flash.o:./common/env_flash.c:78: first defined here ./common/env_nowhere.o: In function `env_init': ./common/env_nowhere.c:51: multiple definition of `env_init' ./common/env_flash.o:./common/env_flash.c:237: first defined here make[1]: *** [./common/libcommon.o] Error 1 make[1]: Leaving directory `./common' make: *** [./common/libcommon.o] Error 2 Remove the CONFIG_ENV_IS_IN_FLASH if defined CONFIG_ENV_IS_NOWHERE. Signed-off-by: Liu Gang gang@freescale.com --- Changes in v2: - Subject changed to powerpc/corenet_ds. - Change the commit message more clearly. Changes in v3: - No include/configs/corenet_ds.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 5067bb7..89e6b6e 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -104,6 +104,8 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZECONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE0x2000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -- 1.7.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/8 v3] powerpc/corenet_ds: Slave module for boot from SRIO
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure SRIO switch system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to SRIO1 or SRIO2 by RCW.
3. RCW should configure the SerDes, SRIO interfaces correctly.
4. Slave must be powered on after master's boot.
5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode
locally.
For the slave module, need to finish these processes:
1. Set the boot location to SRIO1 or SRIO2 by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot.
4. Slave's u-boot image should be generated specifically by
make _SRIOBOOT_SLAVE_config.
This will set SYS_TEXT_BASE=0xFFF8 and other configurations.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Changes in v2:
- Subject changed to powerpc/corenet_ds.
- Use (void *) instead of (u32) when calling out_be32().
- Use NOR flash instead of Nor flash.
- Get rid of the base address + offset notation. Use C structs
instead.
- Get rid of hard coded magic numbers. Use macro instead.
- Use debug() instead of printf().
- Add the description for CONFIG_SYS_QE_FMAN_FW_IN_REMOTE and also
update the README for this.
Changes in v3:
- No
README |6 ++
board/freescale/common/p_corenet/law.c |9 +
board/freescale/common/p_corenet/tlb.c |9 +
boards.cfg |3 +++
drivers/net/fm/fm.c|2 ++
include/configs/corenet_ds.h | 28
6 files changed, 57 insertions(+), 0 deletions(-)
diff --git a/README b/README
index eba6378..719cc20 100644
--- a/README
+++ b/README
@@ -3384,6 +3384,12 @@ within that device.
Specifies that QE/FMAN firmware is located on the primary SPI
device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
+- CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+ Specifies that QE/FMAN firmware is located in the remote (master)
+ memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
+ can be mapped from slave TLB-slave LAW-slave SRIO outbound window
+ -master inbound window-master LAW-the ucode address in master's
+ NOR flash.
Building the Software:
==
diff --git a/board/freescale/common/p_corenet/law.c
b/board/freescale/common/p_corenet/law.c
index 09ef561..1fbab4d 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -48,6 +48,15 @@ struct law_entry law_table[] = {
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
+#ifdef CONFIG_SRIOBOOT_SLAVE
+#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
+ SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
+#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
+ SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
+#endif
+#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index 6a0026a..a8c8b3c 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -66,6 +66,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIOBOOT_SLAVE)
+ /*
+* SRIOBOOT-SLAVE. When slave boot, the address of the
+* space is at 0xfff0, it covered the 0xf000.
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
#else
SET_TLB_ENTRY(1, 0xf000, 0xf000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
diff --git a/boards.cfg b/boards.cfg
index 30b9b51..11f9ef2
[U-Boot] [PATCH 6/8 v3] powerpc/corenet_ds: Slave uploads ucode when boot from SRIO
When boot from SRIO, slave's ucode can be stored in master's memory space,
then slave can fetch the ucode image through SRIO interface. For the
corenet platform, ucode is for Fman.
Master needs to:
1. Put the slave's ucode image into it's own memory space.
2. Set an inbound SRIO window covered slave's ucode stored in master's
memory space.
Slave needs to:
1. Set a specific TLB entry in order to fetch ucode from master.
2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Changes in v2:
- Subject changed to powerpc/corenet_ds.
- Use (void *) instead of (u32) when calling out_be32().
- Use NOR flash instead of Nor flash.
- Get rid of the base address + offset notation. Use C structs
instead.
- Get rid of hard coded magic numbers. Use macro instead.
- Use debug() instead of printf().
- Correct some comment style errors.
Changes in v3:
- No
arch/powerpc/cpu/mpc8xxx/srio.c| 25 +
board/freescale/common/p_corenet/law.c |4
board/freescale/common/p_corenet/tlb.c | 10 ++
include/configs/corenet_ds.h | 12 +++-
4 files changed, 46 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 77fa32f..e593f22 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -100,8 +100,8 @@ void srio_boot_master(void)
debug(SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n,
CONFIG_SRIOBOOT_MASTER_PORT);
- /* configure inbound window5 for slave's u-boot image */
- debug(SRIOBOOT - MASTER: Inbound window 5 for slave's image;
+ /* configure inbound window for slave's u-boot image */
+ debug(SRIOBOOT - MASTER: Inbound window for slave's image;
Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,
@@ -117,8 +117,8 @@ void srio_boot_master(void)
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
- /* configure inbound window4 for slave's u-boot image */
- debug(SRIOBOOT - MASTER: Inbound window 4 for slave's image;
+ /* configure inbound window for slave's u-boot image */
+ debug(SRIOBOOT - MASTER: Inbound window for slave's image;
Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2,
@@ -133,5 +133,22 @@ void srio_boot_master(void)
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
+
+ /* configure inbound window for slave's ucode */
+ debug(SRIOBOOT - MASTER: Inbound window for slave's ucode;
+ Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
+ (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS,
+ (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS,
+ CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwtar,
+ CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwbar,
+ CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwar,
+ SRIO_IB_ATMU_AR
+ | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE));
}
#endif
diff --git a/board/freescale/common/p_corenet/law.c
b/board/freescale/common/p_corenet/law.c
index 1fbab4d..c4566dd 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -52,9 +52,13 @@ struct law_entry law_table[] = {
#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
+ SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
+ SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
#endif
#endif
};
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index a8c8b3c..da21627 100644
[U-Boot] [PATCH 7/8 v3] powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO
When boot from SRIO, slave's ENV can be stored in master's memory space,
then slave can fetch the ENV through SRIO interface.
NOTE: Because the slave can not erase, write master's NOR flash by SRIO
interface, so it can not modify the ENV parameters stored in
master's NOR flash using saveenv or other commands.
Master needs to:
1. Put the slave's ENV into it's own memory space.
2. Set an inbound SRIO window covered slave's ENV stored in master's
memory space.
Slave needs to:
1. Set a specific TLB entry in order to fetch ucode and ENV from master.
2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Changes in v2:
- Subject changed to powerpc/corenet_ds.
- Update the README for CONFIG_ENV_IS_IN_REMOTE.
- Use (void *) instead of (u32) when calling out_be32().
- Use NOR flash instead of Nor flash.
- Get rid of the base address + offset notation. Use C structs
instead.
- Get rid of hard coded magic numbers. Use macro instead.
- Use debug() instead of printf().
- Some code styles changed.
Changes in v3:
- No
README | 18 +
arch/powerpc/cpu/mpc8xxx/srio.c | 17
common/Makefile |1 +
common/cmd_nvedit.c |3 +-
common/env_remote.c | 79 +++
include/configs/corenet_ds.h| 13 ++
6 files changed, 130 insertions(+), 1 deletions(-)
create mode 100644 common/env_remote.c
diff --git a/README b/README
index 719cc20..ab61ed2 100644
--- a/README
+++ b/README
@@ -2943,6 +2943,24 @@ to save the current settings.
environment area within the total memory of your DataFlash placed
at the specified address.
+- CONFIG_ENV_IS_IN_REMOTE:
+
+ Define this if you have a remote memory space which you
+ want to use for the local device's environment.
+
+ - CONFIG_ENV_ADDR:
+ - CONFIG_ENV_SIZE:
+
+ These two #defines specify the address and size of the
+ environment area within the remote memory space. The
+ local device can get the environment from remote memory
+ space by SRIO or other links.
+
+BE CAREFUL! For some special cases, the local device can not use
+saveenv command. For example, the local device will get the
+environment stored in a remote NOR flash by SRIO link, but it can
+not erase, write this NOR flash by SRIO interface.
+
- CONFIG_ENV_IS_IN_NAND:
Define this if you have a NAND device which you want to use
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index e593f22..5694561 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -150,5 +150,22 @@ void srio_boot_master(void)
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE));
+
+ /* configure inbound window for slave's ENV */
+ debug(SRIOBOOT - MASTER: Inbound window for slave's ENV;
+ Local = 0x%llx, Siro = 0x%llx, Size = 0x%x\n,
+ CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS,
+ CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS,
+ CONFIG_SRIOBOOT_SLAVE_ENV_SIZE);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwtar,
+ CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwbar,
+ CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwar,
+ SRIO_IB_ATMU_AR
+ | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE));
}
#endif
diff --git a/common/Makefile b/common/Makefile
index 2d9ae8c..bd9e8a3 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -58,6 +58,7 @@ COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o
COBJS-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
+COBJS-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
# command
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index 20080dc..359d1bf 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -65,9 +65,10 @@ DECLARE_GLOBAL_DATA_PTR;
!defined(CONFIG_ENV_IS_IN_NVRAM) \
!defined(CONFIG_ENV_IS_IN_ONENAND) \
!defined(CONFIG_ENV_IS_IN_SPI_FLASH) \
+ !defined(CONFIG_ENV_IS_IN_REMOTE)\
!defined(CONFIG_ENV_IS_NOWHERE)
# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND
[U-Boot] [PATCH 3/8 v3] powerpc/corenet_ds: Document for the boot from SRIO
This document describes the implementation of the boot from SRIO, includes the introduction of envionment, an example based on P4080DS platform, an example of the slave's RCW, and the description about how to use this feature. Signed-off-by: Liu Gang gang@freescale.com --- Changes in v2: - Subject changed to powerpc/corenet_ds. - Change the name of the document for corenet platform. Changes in v3: - No doc/README.srio-boot-corenet | 103 ++ 1 files changed, 103 insertions(+), 0 deletions(-) create mode 100644 doc/README.srio-boot-corenet diff --git a/doc/README.srio-boot-corenet b/doc/README.srio-boot-corenet new file mode 100644 index 000..56b094c --- /dev/null +++ b/doc/README.srio-boot-corenet @@ -0,0 +1,103 @@ +-- +SRIO Boot on Corenet Platforms +-- + +For some PowerPC processors with SRIO interface, boot location can be configured +to SRIO by RCW. The processor booting from SRIO can do without flash for u-boot +image, ucode and ENV. All the images can be fetched from another processor's +memory space by SRIO link connected between them. + +This document describes the processes based on an example implemented on P4080DS +platforms and a RCW example with boot from SRIO configuration. + +Environment of the SRIO boot: + a) Master and slave can be SOCs in one board or SOCs in separate boards. + b) They are connected with SRIO links, whether 1x or 4x, and directly or + through switch system. + c) Only Master has NorFlash for booting, and all the Master's and Slave's + U-Boot images, UCodes will be stored in this flash. + d) Slave has its own EEPROM for RCW and PBI. + e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot + location to SRIO, and holdoff all the cores if needed. + + ----- --- + | | | | | | + | | | | | | + | NorFlash|-| Master |SRIO | Slave |[EEPROM] + | | | |===| | + | | | | | | + ----- --- + +The example based on P4080DS platform: + Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO + ports 0 will be connected directly and will be used for the boot from SRIO. + + 1. Slave's RCW example for boot from SRIO port 0 and core 0 not in holdoff. + : aa55 aa55 010e 0100 0c58 + 0010: 1818 1818 7440 4000 2000 + 0020: f400 0100 + 0030: 0083 + 0040: 0813 8040 698b 93fe + + 2. Slave's RCW example for boot from SRIO port 0 and all cores in holdoff. + : aa55 aa55 010e 0100 0c58 + 0010: 1818 1818 7440 4000 2000 + 0020: f440 0100 + 0030: 0083 + 0040: 0813 8040 063c 778f + + 3. Sequence in Step by Step. + a) Update RCW for slave with boot from SRIO port 0 configuration. + b) Program slave's U-Boot image, UCode, and ENV parameters into master's + NorFlash. + c) Start up master and it will boot up normally from its NorFlash. + Then, it will finish necessary configurations for slave's boot from + SRIO port 0. + d) Master will set inbound SRIO windows covered slave's U-Boot image stored + in master's NorFlash. + e) Master will set an inbound SRIO window covered slave's UCode stored in + master's NorFlash. + f) Master will set an inbound SRIO window covered slave's ENV stored in + master's NorFlash. + g) If need to release slave's core, master will set outbound SRIO windows + in order to configure slave's registers for the core's releasing. + h) If all cores of slave in holdoff, slave should be powered on before all + the above master's steps, and wait to be released by master. If not all + cores in holdoff, that means core 0 will start up normally, slave should + be powered on after all the above master's steps. In the startup phase + of the slave from SRIO, it will finish some necessary configurations. + i) Slave will set a specific TLB entry for the boot process. + j) Slave
[U-Boot] [PATCH 4/8 v3] powerpc/corenet_ds: Master module for boot from SRIO
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure SRIO switch system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to SRIO1 or SRIO2 by RCW.
3. RCW should configure the SerDes, SRIO interfaces correctly.
4. Slave must be powered on after master's boot.
For the master module, need to finish these processes:
1. Initialize the SRIO port and address space.
2. Set inbound SRIO windows covered slave's u-boot image stored in
master's NOR flash.
3. Master's u-boot image should be generated specifically by
make _SRIOBOOT_MASTER_config
4. Master must boot first, and then slave can be powered on.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Changes in v2:
- Subject changed to powerpc/corenet_ds.
- Use (void *) instead of (u32) when calling out_be32().
- Use NOR flash instead of Nor flash.
- Get rid of the base address + offset notation. Use C structs
instead.
- Get rid of hard coded magic numbers. Use macro instead.
- Use debug() instead of printf().
Changes in v3:
- No
arch/powerpc/cpu/mpc85xx/cpu_init.c |6 ++-
arch/powerpc/cpu/mpc8xxx/srio.c | 51 +++
arch/powerpc/include/asm/fsl_srio.h | 61 +
arch/powerpc/include/asm/immap_85xx.h |3 ++
boards.cfg|3 ++
include/configs/corenet_ds.h | 18 ++
6 files changed, 140 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/include/asm/fsl_srio.h
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 2e4a06c..97a7fe1 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -37,6 +37,7 @@
#include asm/mmu.h
#include asm/fsl_law.h
#include asm/fsl_serdes.h
+#include asm/fsl_srio.h
#include linux/compiler.h
#include mp.h
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
@@ -48,8 +49,6 @@
DECLARE_GLOBAL_DATA_PTR;
-extern void srio_init(void);
-
#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -443,6 +442,9 @@ skip_l2:
#ifdef CONFIG_SYS_SRIO
srio_init();
+#ifdef CONFIG_SRIOBOOT_MASTER
+ srio_boot_master();
+#endif
#endif
#if defined(CONFIG_MP)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index e46d328..77fa32f 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -21,6 +21,10 @@
#include config.h
#include asm/fsl_law.h
#include asm/fsl_serdes.h
+#include asm/fsl_srio.h
+
+#define SRIO_PORT_ACCEPT_ALL 0x1001
+#define SRIO_IB_ATMU_AR 0x80f55000
#if defined(CONFIG_FSL_CORENET)
#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
@@ -84,3 +88,50 @@ void srio_init(void)
setbits_be32(gur-devdisr, _DEVDISR_RMU);
}
}
+
+#ifdef CONFIG_SRIOBOOT_MASTER
+void srio_boot_master(void)
+{
+ struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+
+ /* set port accept-all */
+ out_be32((void *)srio-impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr,
+ SRIO_PORT_ACCEPT_ALL);
+
+ debug(SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n,
+ CONFIG_SRIOBOOT_MASTER_PORT);
+ /* configure inbound window5 for slave's u-boot image */
+ debug(SRIOBOOT - MASTER: Inbound window 5 for slave's image;
+ Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar,
+ SRIO_IB_ATMU_AR
[U-Boot] [PATCH 8/8 v3] powerpc/corenet_ds: Slave core in holdoff when boot from SRIO
When boot from SRIO, slave's core can be in holdoff after powered on for
some specific requirements. Master can release the slave's core at the
right time by SRIO interface.
Master needs to:
1. Set outbound SRIO windows in order to configure slave's registers
for the core's releasing.
2. Check the SRIO port status when release slave core, if no errors,
will implement the process of the slave core's releasing.
Slave needs to:
1. Set all the cores in holdoff by RCW.
2. Be powered on before master's boot.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Changes in v2:
- Subject changed to powerpc/corenet_ds.
- Use (void *) instead of (u32) when calling out_be32().
- Use NOR flash instead of Nor flash.
- Get rid of the base address + offset notation. Use C structs
instead.
- Get rid of hard coded magic numbers. Use macro instead.
- Use debug() instead of printf().
Changes in v3:
- No
arch/powerpc/cpu/mpc85xx/cpu_init.c |3 +
arch/powerpc/cpu/mpc8xxx/srio.c | 125 +++
arch/powerpc/include/asm/fsl_srio.h |3 +
include/configs/corenet_ds.h|4 +
4 files changed, 135 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 97a7fe1..2cd5db7 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -444,6 +444,9 @@ skip_l2:
srio_init();
#ifdef CONFIG_SRIOBOOT_MASTER
srio_boot_master();
+#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
+ srio_boot_master_release_slave();
+#endif
#endif
#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 5694561..c7f3949 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -25,6 +25,12 @@
#define SRIO_PORT_ACCEPT_ALL 0x1001
#define SRIO_IB_ATMU_AR 0x80f55000
+#define SRIO_OB_ATMU_AR_MAINT 0x80077000
+#define SRIO_OB_ATMU_AR_RW 0x80045000
+#define SRIO_LCSBA1CSR_OFFSET 0x5c
+#define SRIO_MAINT_WIN_SIZE 0x100 /* 16M */
+#define SRIO_RW_WIN_SIZE 0x10 /* 1M */
+#define SRIO_LCSBA1CSR 0x6000
#if defined(CONFIG_FSL_CORENET)
#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
@@ -168,4 +174,123 @@ void srio_boot_master(void)
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE));
}
+
+#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
+void srio_boot_master_release_slave(void)
+{
+ struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+ u32 escsr;
+ debug(SRIOBOOT - MASTER:
+ Check the port status and release slave core ...\n);
+
+ escsr = in_be32((void *)srio-lp_serial
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].pescsr);
+ if (escsr 0x2) {
+ if (escsr 0x10100) {
+ debug(SRIOBOOT - MASTER: Port [ %d ] is error.\n,
+ CONFIG_SRIOBOOT_MASTER_PORT);
+ } else {
+ debug(SRIOBOOT - MASTER:
+ Port [ %d ] is ready, now release
slave's core ...\n,
+ CONFIG_SRIOBOOT_MASTER_PORT);
+ /*
+* configure outbound window
+* with maintenance attribute to set slave's LCSBA1CSR
+*/
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowtar, 0);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowtear, 0);
+ if (CONFIG_SRIOBOOT_MASTER_PORT)
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowbar,
+ CONFIG_SYS_SRIO2_MEM_PHYS 12);
+ else
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowbar,
+ CONFIG_SYS_SRIO1_MEM_PHYS 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowar,
+ SRIO_OB_ATMU_AR_MAINT
+ | atmu_size_mask(SRIO_MAINT_WIN_SIZE));
+
+ /*
+* configure outbound window
+* with R/W attribute to set slave's BRR
[U-Boot] [PATCH 1/8 v3] powerpc/srio: Rewrite the struct ccsr_rio
Rewrite this struct for the support of two ports and two message
units registers.
Signed-off-by: Liu Gang gang@freescale.com
---
Changes in v2:
- Change the subject and commit message.
- Remove the offsets in the comments.
- Rewrite the struct for the support of two ports
and two message units registers.
Changes in v3:
- Move some SRIO macros to the appropriate board
configure header files.
arch/powerpc/include/asm/immap_85xx.h | 384 +++--
include/configs/MPC8548CDS.h |5 +
include/configs/MPC8568MDS.h |5 +
include/configs/MPC8569MDS.h |5 +
include/configs/P2020DS.h |5 +
include/configs/P2041RDB.h|3 +
include/configs/corenet_ds.h |7 +
7 files changed, 254 insertions(+), 160 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 9b08cb8..42db6c9 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1353,171 +1353,235 @@ typedef struct ccsr_cpm {
} ccsr_cpm_t;
#endif
-/* RapidIO Registers */
-typedef struct ccsr_rio {
- u32 didcar; /* Device Identity Capability */
- u32 dicar; /* Device Information Capability */
- u32 aidcar; /* Assembly Identity Capability */
- u32 aicar; /* Assembly Information Capability */
- u32 pefcar; /* Processing Element Features Capability */
- u32 spicar; /* Switch Port Information Capability */
- u32 socar; /* Source Operations Capability */
- u32 docar; /* Destination Operations Capability */
+#ifdef CONFIG_SYS_SRIO
+/* Architectural regsiters */
+struct rio_arch {
+ u32 didcar; /* Device Identity CAR */
+ u32 dicar; /* Device Information CAR */
+ u32 aidcar; /* Assembly Identity CAR */
+ u32 aicar; /* Assembly Information CAR */
+ u32 pefcar; /* Processing Element Features CAR */
+ u8 res0[4];
+ u32 socar; /* Source Operations CAR */
+ u32 docar; /* Destination Operations CAR */
u8 res1[32];
- u32 msr;/* Mailbox Cmd And Status */
- u32 pwdcsr; /* Port-Write Doorbell Cmd And Status */
+ u32 mcsr; /* Mailbox CSR */
+ u32 pwdcsr; /* Port-Write and Doorbell CSR */
u8 res2[4];
u32 pellccsr; /* Processing Element Logic Layer CCSR */
u8 res3[12];
- u32 lcsbacsr; /* Local Cfg Space Base Addr Cmd Status */
- u32 bdidcsr;/* Base Device ID Cmd Status */
+ u32 lcsbacsr; /* Local Configuration Space BACSR */
+ u32 bdidcsr;/* Base Device ID CSR */
u8 res4[4];
- u32 hbdidlcsr; /* Host Base Device ID Lock Cmd Status */
- u32 ctcsr; /* Component Tag Cmd Status */
- u8 res5[144];
- u32 pmbh0csr; /* Port Maint. Block Hdr 0 Cmd Status */
- u8 res6[28];
- u32 pltoccsr; /* Port Link Time-out Ctrl Cmd Status */
- u32 prtoccsr; /* Port Response Time-out Ctrl Cmd Status */
- u8 res7[20];
- u32 pgccsr; /* Port General Cmd Status */
- u32 plmreqcsr; /* Port Link Maint. Request Cmd Status */
- u32 plmrespcsr; /* Port Link Maint. Response Cmd Status */
- u32 plascsr;/* Port Local Ackid Status Cmd Status */
- u8 res8[12];
- u32 pescsr; /* Port Error Status Cmd Status */
- u32 pccsr; /* Port Control Cmd Status */
- u8 res9[65184];
- u32 cr; /* Port Control Cmd Status */
- u8 res10[12];
- u32 pcr;/* Port Configuration */
- u32 peir; /* Port Error Injection */
- u8 res11[3048];
- u32 rowtar0;/* RIO Outbound Window Translation Addr 0 */
- u8 res12[12];
- u32 rowar0; /* RIO Outbound Attrs 0 */
- u8 res13[12];
- u32 rowtar1;/* RIO Outbound Window Translation Addr 1 */
- u8 res14[4];
- u32 rowbar1;/* RIO Outbound Window Base Addr 1 */
- u8 res15[4];
- u32 rowar1; /* RIO Outbound Attrs 1 */
- u8 res16[12];
- u32 rowtar2;/* RIO Outbound Window Translation Addr 2 */
- u8 res17[4];
- u32 rowbar2;/* RIO Outbound Window Base Addr 2 */
- u8 res18[4];
- u32 rowar2; /* RIO Outbound Attrs 2 */
- u8 res19[12];
- u32 rowtar3;/* RIO Outbound Window Translation Addr 3 */
- u8 res20[4];
- u32 rowbar3;/* RIO Outbound Window Base Addr 3 */
- u8
Re: [U-Boot] SRIO patches
Hi, Andy, Sorry for the late reply because of my mail system's problem. On Mon, 2012-02-13 at 02:09 -0600, Andy Fleming wrote: 1) I'm not convinced we need a MASTER build target. Isn't it possible to just add support for serving as an SRIO master, and to enable support from the command line, or via environment variable? In principle, it's feasible to add support of MASTER feature from the command line or environment variable. But the feature of Boot from SRIO is a new and special function currently. So I think it may be better don't compile the dependent code when we don't need this feature. 2) There are a number of constants being defined that seem very much like system options (ie something that will vary with different chips): +#define SRIO_PORT_MAX_NUM2 /* SRIO port max number */ +#define SRIO_OB_WIN_NUM 9 /* SRIO outbound window number */ +#define SRIO_IB_WIN_NUM 5 /* SRIO inbound window number */ +#define SRIO_MSG_UNIT_NUM2 /* SRIO message unit number */ Maybe these should be config options? Yes, I think your suggestion is better. I'll move these to asm/fsl_srio.h file. Do you think this OK? Best Regards, Liu Gang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 6/8 v2] powerpc/corenet_ds: Slave uploads ucode when boot from SRIO
When boot from SRIO, slave's ucode can be stored in master's memory space,
then slave can fetch the ucode image through SRIO interface. For the
corenet platform, ucode is for Fman.
Master needs to:
1. Put the slave's ucode image into it's own memory space.
2. Set an inbound SRIO window covered slave's ucode stored in master's
memory space.
Slave needs to:
1. Set a specific TLB entry in order to fetch ucode from master.
2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Changes in v2:
- Subject changed to powerpc/corenet_ds.
- Use (void *) instead of (u32) when calling out_be32().
- Use NOR flash instead of Nor flash.
- Get rid of the base address + offset notation. Use C structs
instead.
- Get rid of hard coded magic numbers. Use macro instead.
- Use debug() instead of printf().
- Correct some comment style errors.
arch/powerpc/cpu/mpc8xxx/srio.c| 25 +
board/freescale/common/p_corenet/law.c |4
board/freescale/common/p_corenet/tlb.c | 10 ++
include/configs/corenet_ds.h | 12 +++-
4 files changed, 46 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 77fa32f..e593f22 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -100,8 +100,8 @@ void srio_boot_master(void)
debug(SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n,
CONFIG_SRIOBOOT_MASTER_PORT);
- /* configure inbound window5 for slave's u-boot image */
- debug(SRIOBOOT - MASTER: Inbound window 5 for slave's image;
+ /* configure inbound window for slave's u-boot image */
+ debug(SRIOBOOT - MASTER: Inbound window for slave's image;
Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,
@@ -117,8 +117,8 @@ void srio_boot_master(void)
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
- /* configure inbound window4 for slave's u-boot image */
- debug(SRIOBOOT - MASTER: Inbound window 4 for slave's image;
+ /* configure inbound window for slave's u-boot image */
+ debug(SRIOBOOT - MASTER: Inbound window for slave's image;
Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2,
@@ -133,5 +133,22 @@ void srio_boot_master(void)
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
+
+ /* configure inbound window for slave's ucode */
+ debug(SRIOBOOT - MASTER: Inbound window for slave's ucode;
+ Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
+ (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS,
+ (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS,
+ CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwtar,
+ CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwbar,
+ CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwar,
+ SRIO_IB_ATMU_AR
+ | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE));
}
#endif
diff --git a/board/freescale/common/p_corenet/law.c
b/board/freescale/common/p_corenet/law.c
index 1fbab4d..c4566dd 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -52,9 +52,13 @@ struct law_entry law_table[] = {
#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
+ SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
+ SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
#endif
#endif
};
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index a8c8b3c..6bb4c3f 100644
--- a/board/freescale/common
[U-Boot] [PATCH 1/8 v2] powerpc/srio: Rewrite the struct ccsr_rio
Rewrite this struct for the support of two ports and two message
units registers.
Signed-off-by: Liu Gang gang@freescale.com
---
Changes in v2:
- Change the subject and commit message.
- Remove the offsets in the comments.
- Rewrite the struct for the support of two ports
and two message units registers.
arch/powerpc/include/asm/immap_85xx.h | 383 +++--
1 files changed, 223 insertions(+), 160 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 9b08cb8..a65fc1c 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1353,171 +1353,234 @@ typedef struct ccsr_cpm {
} ccsr_cpm_t;
#endif
-/* RapidIO Registers */
-typedef struct ccsr_rio {
- u32 didcar; /* Device Identity Capability */
- u32 dicar; /* Device Information Capability */
- u32 aidcar; /* Assembly Identity Capability */
- u32 aicar; /* Assembly Information Capability */
- u32 pefcar; /* Processing Element Features Capability */
- u32 spicar; /* Switch Port Information Capability */
- u32 socar; /* Source Operations Capability */
- u32 docar; /* Destination Operations Capability */
+#define SRIO_PORT_MAX_NUM 2 /* SRIO port max number */
+#define SRIO_OB_WIN_NUM9 /* SRIO outbound window number */
+#define SRIO_IB_WIN_NUM5 /* SRIO inbound window number */
+#define SRIO_MSG_UNIT_NUM 2 /* SRIO message unit number */
+
+/* Architectural regsiters */
+struct rio_arch {
+ u32 didcar; /* Device Identity CAR */
+ u32 dicar; /* Device Information CAR */
+ u32 aidcar; /* Assembly Identity CAR */
+ u32 aicar; /* Assembly Information CAR */
+ u32 pefcar; /* Processing Element Features CAR */
+ u8 res0[4];
+ u32 socar; /* Source Operations CAR */
+ u32 docar; /* Destination Operations CAR */
u8 res1[32];
- u32 msr;/* Mailbox Cmd And Status */
- u32 pwdcsr; /* Port-Write Doorbell Cmd And Status */
+ u32 mcsr; /* Mailbox CSR */
+ u32 pwdcsr; /* Port-Write and Doorbell CSR */
u8 res2[4];
u32 pellccsr; /* Processing Element Logic Layer CCSR */
u8 res3[12];
- u32 lcsbacsr; /* Local Cfg Space Base Addr Cmd Status */
- u32 bdidcsr;/* Base Device ID Cmd Status */
+ u32 lcsbacsr; /* Local Configuration Space BACSR */
+ u32 bdidcsr;/* Base Device ID CSR */
u8 res4[4];
- u32 hbdidlcsr; /* Host Base Device ID Lock Cmd Status */
- u32 ctcsr; /* Component Tag Cmd Status */
- u8 res5[144];
- u32 pmbh0csr; /* Port Maint. Block Hdr 0 Cmd Status */
- u8 res6[28];
- u32 pltoccsr; /* Port Link Time-out Ctrl Cmd Status */
- u32 prtoccsr; /* Port Response Time-out Ctrl Cmd Status */
- u8 res7[20];
- u32 pgccsr; /* Port General Cmd Status */
- u32 plmreqcsr; /* Port Link Maint. Request Cmd Status */
- u32 plmrespcsr; /* Port Link Maint. Response Cmd Status */
- u32 plascsr;/* Port Local Ackid Status Cmd Status */
- u8 res8[12];
- u32 pescsr; /* Port Error Status Cmd Status */
- u32 pccsr; /* Port Control Cmd Status */
- u8 res9[65184];
- u32 cr; /* Port Control Cmd Status */
- u8 res10[12];
- u32 pcr;/* Port Configuration */
- u32 peir; /* Port Error Injection */
- u8 res11[3048];
- u32 rowtar0;/* RIO Outbound Window Translation Addr 0 */
- u8 res12[12];
- u32 rowar0; /* RIO Outbound Attrs 0 */
- u8 res13[12];
- u32 rowtar1;/* RIO Outbound Window Translation Addr 1 */
- u8 res14[4];
- u32 rowbar1;/* RIO Outbound Window Base Addr 1 */
- u8 res15[4];
- u32 rowar1; /* RIO Outbound Attrs 1 */
- u8 res16[12];
- u32 rowtar2;/* RIO Outbound Window Translation Addr 2 */
- u8 res17[4];
- u32 rowbar2;/* RIO Outbound Window Base Addr 2 */
- u8 res18[4];
- u32 rowar2; /* RIO Outbound Attrs 2 */
- u8 res19[12];
- u32 rowtar3;/* RIO Outbound Window Translation Addr 3 */
- u8 res20[4];
- u32 rowbar3;/* RIO Outbound Window Base Addr 3 */
- u8 res21[4];
- u32 rowar3; /* RIO Outbound Attrs 3 */
- u8 res22[12];
- u32
[U-Boot] [PATCH 2/8 v2] powerpc/corenet_ds: Correct the compilation errors about ENV
When defined CONFIG_ENV_IS_NOWHERE, there will be some compilation errors: ./common/env_nowhere.o: In function `env_relocate_spec': ./common/env_nowhere.c:38: multiple definition of `env_relocate_spec' ./common/env_flash.o: ./common/env_flash.c:326: first defined here ./common/env_nowhere.o: In function `env_get_char_spec': ./common/env_nowhere.c:42: multiple definition of `env_get_char_spec' ./common/env_flash.o:./common/env_flash.c:78: first defined here ./common/env_nowhere.o: In function `env_init': ./common/env_nowhere.c:51: multiple definition of `env_init' ./common/env_flash.o:./common/env_flash.c:237: first defined here make[1]: *** [./common/libcommon.o] Error 1 make[1]: Leaving directory `./common' make: *** [./common/libcommon.o] Error 2 Remove the CONFIG_ENV_IS_IN_FLASH if defined CONFIG_ENV_IS_NOWHERE. Signed-off-by: Liu Gang gang@freescale.com --- Changes in v2: - Subject changed to powerpc/corenet_ds. - Change the commit message more clearly. include/configs/corenet_ds.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 7925b95..e38f69d 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -96,6 +96,8 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZECONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE0x2000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -- 1.7.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/8 v2] powerpc/corenet_ds: Document for the boot from SRIO
This document describes the implementation of the boot from SRIO, includes the introduction of envionment, an example based on P4080DS platform, an example of the slave's RCW, and the description about how to use this feature. Signed-off-by: Liu Gang gang@freescale.com --- Changes in v2: - Subject changed to powerpc/corenet_ds. - Change the name of the document for corenet platform. doc/README.srio-boot-corenet | 103 ++ 1 files changed, 103 insertions(+), 0 deletions(-) create mode 100644 doc/README.srio-boot-corenet diff --git a/doc/README.srio-boot-corenet b/doc/README.srio-boot-corenet new file mode 100644 index 000..56b094c --- /dev/null +++ b/doc/README.srio-boot-corenet @@ -0,0 +1,103 @@ +-- +SRIO Boot on Corenet Platforms +-- + +For some PowerPC processors with SRIO interface, boot location can be configured +to SRIO by RCW. The processor booting from SRIO can do without flash for u-boot +image, ucode and ENV. All the images can be fetched from another processor's +memory space by SRIO link connected between them. + +This document describes the processes based on an example implemented on P4080DS +platforms and a RCW example with boot from SRIO configuration. + +Environment of the SRIO boot: + a) Master and slave can be SOCs in one board or SOCs in separate boards. + b) They are connected with SRIO links, whether 1x or 4x, and directly or + through switch system. + c) Only Master has NorFlash for booting, and all the Master's and Slave's + U-Boot images, UCodes will be stored in this flash. + d) Slave has its own EEPROM for RCW and PBI. + e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot + location to SRIO, and holdoff all the cores if needed. + + ----- --- + | | | | | | + | | | | | | + | NorFlash|-| Master |SRIO | Slave |[EEPROM] + | | | |===| | + | | | | | | + ----- --- + +The example based on P4080DS platform: + Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO + ports 0 will be connected directly and will be used for the boot from SRIO. + + 1. Slave's RCW example for boot from SRIO port 0 and core 0 not in holdoff. + : aa55 aa55 010e 0100 0c58 + 0010: 1818 1818 7440 4000 2000 + 0020: f400 0100 + 0030: 0083 + 0040: 0813 8040 698b 93fe + + 2. Slave's RCW example for boot from SRIO port 0 and all cores in holdoff. + : aa55 aa55 010e 0100 0c58 + 0010: 1818 1818 7440 4000 2000 + 0020: f440 0100 + 0030: 0083 + 0040: 0813 8040 063c 778f + + 3. Sequence in Step by Step. + a) Update RCW for slave with boot from SRIO port 0 configuration. + b) Program slave's U-Boot image, UCode, and ENV parameters into master's + NorFlash. + c) Start up master and it will boot up normally from its NorFlash. + Then, it will finish necessary configurations for slave's boot from + SRIO port 0. + d) Master will set inbound SRIO windows covered slave's U-Boot image stored + in master's NorFlash. + e) Master will set an inbound SRIO window covered slave's UCode stored in + master's NorFlash. + f) Master will set an inbound SRIO window covered slave's ENV stored in + master's NorFlash. + g) If need to release slave's core, master will set outbound SRIO windows + in order to configure slave's registers for the core's releasing. + h) If all cores of slave in holdoff, slave should be powered on before all + the above master's steps, and wait to be released by master. If not all + cores in holdoff, that means core 0 will start up normally, slave should + be powered on after all the above master's steps. In the startup phase + of the slave from SRIO, it will finish some necessary configurations. + i) Slave will set a specific TLB entry for the boot process. + j) Slave will set a LAW entry
[U-Boot] [PATCH 4/8 v2] powerpc/corenet_ds: Master module for boot from SRIO
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure SRIO switch system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to SRIO1 or SRIO2 by RCW.
3. RCW should configure the SerDes, SRIO interfaces correctly.
4. Slave must be powered on after master's boot.
For the master module, need to finish these processes:
1. Initialize the SRIO port and address space.
2. Set inbound SRIO windows covered slave's u-boot image stored in
master's NOR flash.
3. Master's u-boot image should be generated specifically by
make _SRIOBOOT_MASTER_config
4. Master must boot first, and then slave can be powered on.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Changes in v2:
- Subject changed to powerpc/corenet_ds.
- Use (void *) instead of (u32) when calling out_be32().
- Use NOR flash instead of Nor flash.
- Get rid of the base address + offset notation. Use C structs
instead.
- Get rid of hard coded magic numbers. Use macro instead.
- Use debug() instead of printf().
arch/powerpc/cpu/mpc85xx/cpu_init.c |6 ++-
arch/powerpc/cpu/mpc8xxx/srio.c | 51 +++
arch/powerpc/include/asm/fsl_srio.h | 61 +
arch/powerpc/include/asm/immap_85xx.h |3 ++
boards.cfg|3 ++
include/configs/corenet_ds.h | 18 ++
6 files changed, 140 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/include/asm/fsl_srio.h
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 2e4a06c..97a7fe1 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -37,6 +37,7 @@
#include asm/mmu.h
#include asm/fsl_law.h
#include asm/fsl_serdes.h
+#include asm/fsl_srio.h
#include linux/compiler.h
#include mp.h
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
@@ -48,8 +49,6 @@
DECLARE_GLOBAL_DATA_PTR;
-extern void srio_init(void);
-
#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -443,6 +442,9 @@ skip_l2:
#ifdef CONFIG_SYS_SRIO
srio_init();
+#ifdef CONFIG_SRIOBOOT_MASTER
+ srio_boot_master();
+#endif
#endif
#if defined(CONFIG_MP)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index e46d328..77fa32f 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -21,6 +21,10 @@
#include config.h
#include asm/fsl_law.h
#include asm/fsl_serdes.h
+#include asm/fsl_srio.h
+
+#define SRIO_PORT_ACCEPT_ALL 0x1001
+#define SRIO_IB_ATMU_AR 0x80f55000
#if defined(CONFIG_FSL_CORENET)
#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
@@ -84,3 +88,50 @@ void srio_init(void)
setbits_be32(gur-devdisr, _DEVDISR_RMU);
}
}
+
+#ifdef CONFIG_SRIOBOOT_MASTER
+void srio_boot_master(void)
+{
+ struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+
+ /* set port accept-all */
+ out_be32((void *)srio-impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr,
+ SRIO_PORT_ACCEPT_ALL);
+
+ debug(SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n,
+ CONFIG_SRIOBOOT_MASTER_PORT);
+ /* configure inbound window5 for slave's u-boot image */
+ debug(SRIOBOOT - MASTER: Inbound window 5 for slave's image;
+ Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar,
+ SRIO_IB_ATMU_AR
[U-Boot] [PATCH 5/8 v2] powerpc/corenet_ds: Slave module for boot from SRIO
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure SRIO switch system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to SRIO1 or SRIO2 by RCW.
3. RCW should configure the SerDes, SRIO interfaces correctly.
4. Slave must be powered on after master's boot.
5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode
locally.
For the slave module, need to finish these processes:
1. Set the boot location to SRIO1 or SRIO2 by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot.
4. Slave's u-boot image should be generated specifically by
make _SRIOBOOT_SLAVE_config.
This will set SYS_TEXT_BASE=0xFFF8 and other configurations.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Changes in v2:
- Subject changed to powerpc/corenet_ds.
- Use (void *) instead of (u32) when calling out_be32().
- Use NOR flash instead of Nor flash.
- Get rid of the base address + offset notation. Use C structs
instead.
- Get rid of hard coded magic numbers. Use macro instead.
- Use debug() instead of printf().
- Add the description for CONFIG_SYS_QE_FMAN_FW_IN_REMOTE and also
update the README for this.
README |6 ++
board/freescale/common/p_corenet/law.c |9 +
board/freescale/common/p_corenet/tlb.c |9 +
boards.cfg |3 +++
drivers/net/fm/fm.c|2 ++
include/configs/corenet_ds.h | 28
6 files changed, 57 insertions(+), 0 deletions(-)
diff --git a/README b/README
index 9d713e8..f4f0d64 100644
--- a/README
+++ b/README
@@ -3358,6 +3358,12 @@ within that device.
Specifies that QE/FMAN firmware is located on the primary SPI
device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
+- CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+ Specifies that QE/FMAN firmware is located in the remote (master)
+ memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
+ can be mapped from slave TLB-slave LAW-slave SRIO outbound window
+ -master inbound window-master LAW-the ucode address in master's
+ NOR flash.
Building the Software:
==
diff --git a/board/freescale/common/p_corenet/law.c
b/board/freescale/common/p_corenet/law.c
index 09ef561..1fbab4d 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -48,6 +48,15 @@ struct law_entry law_table[] = {
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
+#ifdef CONFIG_SRIOBOOT_SLAVE
+#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
+ SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
+#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
+ SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
+#endif
+#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index 6a0026a..a8c8b3c 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -66,6 +66,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIOBOOT_SLAVE)
+ /*
+* SRIOBOOT-SLAVE. When slave boot, the address of the
+* space is at 0xfff0, it covered the 0xf000.
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
#else
SET_TLB_ENTRY(1, 0xf000, 0xf000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
diff --git a/boards.cfg b/boards.cfg
index 446f0eb..798466e 100644
--- a/boards.cfg
[U-Boot] [PATCH 7/8 v2] powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO
When boot from SRIO, slave's ENV can be stored in master's memory space,
then slave can fetch the ENV through SRIO interface.
NOTE: Because the slave can not erase, write master's NOR flash by SRIO
interface, so it can not modify the ENV parameters stored in
master's NOR flash using saveenv or other commands.
Master needs to:
1. Put the slave's ENV into it's own memory space.
2. Set an inbound SRIO window covered slave's ENV stored in master's
memory space.
Slave needs to:
1. Set a specific TLB entry in order to fetch ucode and ENV from master.
2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Changes in v2:
- Subject changed to powerpc/corenet_ds.
- Update the README for CONFIG_ENV_IS_IN_REMOTE.
- Use (void *) instead of (u32) when calling out_be32().
- Use NOR flash instead of Nor flash.
- Get rid of the base address + offset notation. Use C structs
instead.
- Get rid of hard coded magic numbers. Use macro instead.
- Use debug() instead of printf().
- Some code styles changed.
README | 18 +
arch/powerpc/cpu/mpc8xxx/srio.c | 17
common/Makefile |1 +
common/cmd_nvedit.c |3 +-
common/env_remote.c | 79 +++
include/configs/corenet_ds.h| 13 ++
6 files changed, 130 insertions(+), 1 deletions(-)
create mode 100644 common/env_remote.c
diff --git a/README b/README
index f4f0d64..1b699c9 100644
--- a/README
+++ b/README
@@ -2917,6 +2917,24 @@ to save the current settings.
environment area within the total memory of your DataFlash placed
at the specified address.
+- CONFIG_ENV_IS_IN_REMOTE:
+
+ Define this if you have a remote memory space which you
+ want to use for the local device's environment.
+
+ - CONFIG_ENV_ADDR:
+ - CONFIG_ENV_SIZE:
+
+ These two #defines specify the address and size of the
+ environment area within the remote memory space. The
+ local device can get the environment from remote memory
+ space by SRIO or other links.
+
+BE CAREFUL! For some special cases, the local device can not use
+saveenv command. For example, the local device will get the
+environment stored in a remote NOR flash by SRIO link, but it can
+not erase, write this NOR flash by SRIO interface.
+
- CONFIG_ENV_IS_IN_NAND:
Define this if you have a NAND device which you want to use
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index e593f22..5694561 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -150,5 +150,22 @@ void srio_boot_master(void)
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE));
+
+ /* configure inbound window for slave's ENV */
+ debug(SRIOBOOT - MASTER: Inbound window for slave's ENV;
+ Local = 0x%llx, Siro = 0x%llx, Size = 0x%x\n,
+ CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS,
+ CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS,
+ CONFIG_SRIOBOOT_SLAVE_ENV_SIZE);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwtar,
+ CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwbar,
+ CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwar,
+ SRIO_IB_ATMU_AR
+ | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE));
}
#endif
diff --git a/common/Makefile b/common/Makefile
index 2d9ae8c..bd9e8a3 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -58,6 +58,7 @@ COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o
COBJS-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
+COBJS-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
# command
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index 63afc82..c2fd8fa 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -65,9 +65,10 @@ DECLARE_GLOBAL_DATA_PTR;
!defined(CONFIG_ENV_IS_IN_NVRAM) \
!defined(CONFIG_ENV_IS_IN_ONENAND) \
!defined(CONFIG_ENV_IS_IN_SPI_FLASH) \
+ !defined(CONFIG_ENV_IS_IN_REMOTE)\
!defined(CONFIG_ENV_IS_NOWHERE)
# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\
-SPI_FLASH|MG_DISK|NVRAM|MMC
[U-Boot] [PATCH 8/8 v2] powerpc/corenet_ds: Slave core in holdoff when boot from SRIO
When boot from SRIO, slave's core can be in holdoff after powered on for
some specific requirements. Master can release the slave's core at the
right time by SRIO interface.
Master needs to:
1. Set outbound SRIO windows in order to configure slave's registers
for the core's releasing.
2. Check the SRIO port status when release slave core, if no errors,
will implement the process of the slave core's releasing.
Slave needs to:
1. Set all the cores in holdoff by RCW.
2. Be powered on before master's boot.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Changes in v2:
- Subject changed to powerpc/corenet_ds.
- Use (void *) instead of (u32) when calling out_be32().
- Use NOR flash instead of Nor flash.
- Get rid of the base address + offset notation. Use C structs
instead.
- Get rid of hard coded magic numbers. Use macro instead.
- Use debug() instead of printf().
arch/powerpc/cpu/mpc85xx/cpu_init.c |3 +
arch/powerpc/cpu/mpc8xxx/srio.c | 126 +++
arch/powerpc/include/asm/fsl_srio.h |3 +
include/configs/corenet_ds.h|4 +
4 files changed, 136 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 97a7fe1..2cd5db7 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -444,6 +444,9 @@ skip_l2:
srio_init();
#ifdef CONFIG_SRIOBOOT_MASTER
srio_boot_master();
+#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
+ srio_boot_master_release_slave();
+#endif
#endif
#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 5694561..e132c69 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -25,6 +25,12 @@
#define SRIO_PORT_ACCEPT_ALL 0x1001
#define SRIO_IB_ATMU_AR 0x80f55000
+#define SRIO_OB_ATMU_AR_MAINT 0x80077000
+#define SRIO_OB_ATMU_AR_RW 0x80045000
+#define SRIO_LCSBA1CSR_OFFSET 0x5c
+#define SRIO_MAINT_WIN_SIZE 0x100 /* 16M */
+#define SRIO_RW_WIN_SIZE 0x10 /* 1M */
+#define SRIO_LCSBA1CSR 0x6000
#if defined(CONFIG_FSL_CORENET)
#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
@@ -168,4 +174,124 @@ void srio_boot_master(void)
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE));
}
+
+#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
+void srio_boot_master_release_slave(void)
+{
+ struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+ u32 escsr;
+ u32 addr;
+ debug(SRIOBOOT - MASTER:
+ Check the port status and release slave core ...\n);
+
+ escsr = in_be32((void *)srio-lp_serial
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].pescsr);
+ if (escsr 0x2) {
+ if (escsr 0x10100) {
+ debug(SRIOBOOT - MASTER: Port [ %d ] is error.\n,
+ CONFIG_SRIOBOOT_MASTER_PORT);
+ } else {
+ debug(SRIOBOOT - MASTER:
+ Port [ %d ] is ready, now release
slave's core ...\n,
+ CONFIG_SRIOBOOT_MASTER_PORT);
+ /*
+* configure outbound window
+* with maintenance attribute to set slave's LCSBA1CSR
+*/
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowtar, 0);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowtear, 0);
+ if (CONFIG_SRIOBOOT_MASTER_PORT)
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowbar,
+ CONFIG_SYS_SRIO2_MEM_PHYS 12);
+ else
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowbar,
+ CONFIG_SYS_SRIO1_MEM_PHYS 12);
+ out_be32((void *)srio-atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowar,
+ SRIO_OB_ATMU_AR_MAINT
+ | atmu_size_mask(SRIO_MAINT_WIN_SIZE));
+
+ /*
+* configure outbound window
+* with R/W attribute to set slave's BRR
Re: [U-Boot] [PATCH 5/8] powerpc/boot: Slave module for boot from SRIO
Dear Wolfgang, On Wed, 2012-01-11 at 08:27 +0100, Wolfgang Denk wrote: Where is CONFIG_SYS_QE_FMAN_FW_IN_REMOTE documented? And where is the code that uses it? [Liu Gang-B34182] Sorry I documented this definition in [PATCH 6/8] powerpc/boot: Slave uploads ucode when boot from SRIO, I'll add descriptions about this definition in PATCH 5/8. The function fm_init_common in the file drivers/net/fm/fm.c uses the CONFIG_SYS_QE_FMAN_FW_IN_REMOTE. Please: - do not full-quote. - restrict your line length to some 70 characters or so - use proper quoting; see http://www.netmeister.org/news/learn2quote.html I'm sorry for the late reply because of some e-mail problem of my system. I'm learning the information you provided, it's very useful. Thanks very much! Best Regards, Liu Gang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/8] powerpc/boot: Master module for boot from SRIO
Dear Wolfgang, On Wed, 2012-01-11 at 08:31 +0100, Wolfgang Denk wrote: 3. Normally boot from local Nor flash. Please use NOR flash (or nor flash, if you insist). Nor makes no sense. Please fix globally. Thanks, will modify. + printf(SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n, + CONFIG_SRIOBOOT_MASTER_PORT); + /* configure inbound window1 for slave's u-boot image */ + printf(SRIOBOOT - MASTER: Inbound window1 for slave's image; + Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n, + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1, + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); As mentioned before, this looks a lot like debug code, that should be removed from a production version. Use debug() instead? These parameters are very important for the boot from srio, for the different productions may should be different values. So I think that would be better to keep these informations. I'll use debug() instead! This comment applies to the whole patch series: - Get rid of the base address + oofset notation. User C structs instead. - Get rid of hard coded magic numbers. #define the needed values in a readable way. Thanks, will modify. Best Regards, Liu Gang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/8] powerpc/boot: Slave uploads ucode when boot from SRIO
Dear Wolfgang, On Wed, 2012-01-11 at 08:23 +0100, Wolfgang Denk wrote: +#ifdef CONFIG_SRIOBOOT_SLAVE + /* +* *I*G - SRIOBOOT-SLAVE. 1M space from 0xffe0 for fetching ucode +* and ENV from master +*/ What is this *I*G - doing here? This means that the TLB entry will be set with attribute MAS2_I and MAS2_G. This follows the existing style of the file. +/* + *for slave UCODE instored in master memory space, + *PHYS must be aligned based on the SIZE + */ Please add a space between the '*' anf the text. Please fix globally. Thanks, will add. Best Regards, Liu Gang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/8] powerpc/srio: Correct the register defined errors in the struct ccsr_rio_t
Hi, Kumar, On Thu, 2012-01-12 at 10:47 -0600, Kumar Gala wrote: On Jan 10, 2012, at 5:42 AM, Liu Gang wrote: + u32 didcar; /* 0xc - Device Identity CAR */ Drop the '0xc' prefix in the comment, same comment for all registers. Thanks, I'll rewrite this struct. Best Regards, Liu Gang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/8] powerpc/env: Correct the compilation errors when defined CONFIG_ENV_IS_NOWHERE
When defined CONFIG_ENV_IS_NOWHERE, there will be some compilation errors: ./common/env_nowhere.o: In function `env_relocate_spec': ./common/env_nowhere.c:38: multiple definition of `env_relocate_spec' ./common/env_flash.o: ./common/env_flash.c:326: first defined here ./common/env_nowhere.o: In function `env_get_char_spec': ./common/env_nowhere.c:42: multiple definition of `env_get_char_spec' ./common/env_flash.o:./common/env_flash.c:78: first defined here ./common/env_nowhere.o: In function `env_init': ./common/env_nowhere.c:51: multiple definition of `env_init' ./common/env_flash.o:./common/env_flash.c:237: first defined here make[1]: *** [./common/libcommon.o] Error 1 make[1]: Leaving directory `./common' make: *** [./common/libcommon.o] Error 2 There will be a confict if defined CONFIG_ENV_IS_NOWHERE and CONFIG_ENV_IS_IN_FLASH. Signed-off-by: Liu Gang gang@freescale.com --- include/configs/corenet_ds.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 7925b95..e38f69d 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -96,6 +96,8 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZECONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE0x2000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -- 1.7.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 6/8] powerpc/boot: Slave uploads ucode when boot from SRIO
When boot from SRIO, slave's ucode can be stored in master's memory space,
then slave can fetch the ucode image through SRIO interface.
Master needs to:
1. Put the slave's ucode image into it's own memory space.
2. Set an inbound SRIO window covered slave's ucode stored in master's
memory space.
Slave needs to:
1. Set a specific TLB entry in order to fetch ucode from master.
2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
arch/powerpc/cpu/mpc8xxx/srio.c| 14 ++
board/freescale/common/p_corenet/law.c |4
board/freescale/common/p_corenet/tlb.c | 10 ++
include/configs/corenet_ds.h | 17 -
4 files changed, 44 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index e8ce3a3..740d28a 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -124,5 +124,19 @@ void srio_boot_master(void)
out_be32((u32)srio-riwar2 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
0x80f55000
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
+
+ /* configure inbound window for slave's ucode */
+ printf(SRIOBOOT - MASTER: Inbound window for slave's ucode;
+ Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
+ (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS,
+ (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS,
+ CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE);
+ out_be32((u32)srio-riwtar3 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
+ CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 12);
+ out_be32((u32)srio-riwbar3 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
+ CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 12);
+ out_be32((u32)srio-riwar3 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
+ 0x80f55000
+ | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE));
}
#endif
diff --git a/board/freescale/common/p_corenet/law.c
b/board/freescale/common/p_corenet/law.c
index 1fbab4d..c4566dd 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -52,9 +52,13 @@ struct law_entry law_table[] = {
#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
+ SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
+ SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
#endif
#endif
};
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index cb4339f..70779f1 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -147,6 +147,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_1M, 1),
#endif
+#ifdef CONFIG_SRIOBOOT_SLAVE
+ /*
+* *I*G - SRIOBOOT-SLAVE. 1M space from 0xffe0 for fetching ucode
+* and ENV from master
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 17, BOOKE_PAGESZ_1M, 1),
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index e4f562c..3b2ff15 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -398,6 +398,13 @@
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x8 /* 512K */
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef08ull
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff8ull
+/*
+ *for slave UCODE instored in master memory space,
+ *PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 0xfef02ull
+#define CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 0x3ffe0ull
+#define CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE 0x1 /* 64K */
#endif
/*
@@ -407,6 +414,9 @@
/* slave port for srioboot*/
#define CONFIG_SRIOBOOT_SLAVE_PORT0
/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */
+#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE0
+#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \
+ (0x3ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR)
#endif
/*
@@ -530,8 +540,13 @@
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_QE_FMAN_FW_ADDR (6
[U-Boot] [PATCH 3/8] powerpc/boot: Document for the boot from SRIO
This document describes the implementation of the boot from SRIO, includes the introduction of envionment, an example based on P4080DS platform, an example of the slave's RCW, and the description about how to use this feature. Signed-off-by: Liu Gang gang@freescale.com --- doc/README.srio-boot-mpc85xx | 103 ++ 1 files changed, 103 insertions(+), 0 deletions(-) create mode 100644 doc/README.srio-boot-mpc85xx diff --git a/doc/README.srio-boot-mpc85xx b/doc/README.srio-boot-mpc85xx new file mode 100644 index 000..1c6b0c9 --- /dev/null +++ b/doc/README.srio-boot-mpc85xx @@ -0,0 +1,103 @@ +-- +SRIO Boot on MPC85xx Platforms +-- + +For some PowerPC processors with SRIO interface, boot location can be configured +to SRIO by RCW. The processor booting from SRIO can do without flash for u-boot +image, ucode and ENV. All the images can be fetched from another processor's +memory space by SRIO link connected between them. + +This document describes the processes based on an example implemented on P4080DS +platforms and a RCW example with boot from SRIO configuration. + +Environment of the SRIO boot: + a) Master and slave can be SOCs in one board or SOCs in separate boards. + b) They are connected with SRIO links, whether 1x or 4x, and directly or + through switch system. + c) Only Master has NorFlash for booting, and all the Master's and Slave's + U-Boot images, UCodes will be stored in this flash. + d) Slave has its own EEPROM for RCW and PBI. + e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot + location to SRIO, and holdoff all the cores if needed. + + ----- --- + | | | | | | + | | | | | | + | NorFlash|-| Master |SRIO | Slave |[EEPROM] + | | | |===| | + | | | | | | + ----- --- + +The example based on P4080DS platform: + Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO + ports 0 will be connected directly and will be used for the boot from SRIO. + + 1. Slave's RCW example for boot from SRIO port 0 and core 0 not in holdoff. + : aa55 aa55 010e 0100 0c58 + 0010: 1818 1818 7440 4000 2000 + 0020: f400 0100 + 0030: 0083 + 0040: 0813 8040 698b 93fe + + 2. Slave's RCW example for boot from SRIO port 0 and all cores in holdoff. + : aa55 aa55 010e 0100 0c58 + 0010: 1818 1818 7440 4000 2000 + 0020: f440 0100 + 0030: 0083 + 0040: 0813 8040 063c 778f + + 3. Sequence in Step by Step. + a) Update RCW for slave with boot from SRIO port 0 configuration. + b) Program slave's U-Boot image, UCode, and ENV parameters into master's + NorFlash. + c) Start up master and it will boot up normally from its NorFlash. + Then, it will finish necessary configurations for slave's boot from + SRIO port 0. + d) Master will set inbound SRIO windows covered slave's U-Boot image stored + in master's NorFlash. + e) Master will set an inbound SRIO window covered slave's UCode stored in + master's NorFlash. + f) Master will set an inbound SRIO window covered slave's ENV stored in + master's NorFlash. + g) If need to release slave's core, master will set outbound SRIO windows + in order to configure slave's registers for the core's releasing. + h) If all cores of slave in holdoff, slave should be powered on before all + the above master's steps, and wait to be released by master. If not all + cores in holdoff, that means core 0 will start up normally, slave should + be powered on after all the above master's steps. In the startup phase + of the slave from SRIO, it will finish some necessary configurations. + i) Slave will set a specific TLB entry for the boot process. + j) Slave will set a LAW entry with the TargetID SRIO port 0 for the boot. + k) Slave will set a specific TLB entry in order to fetch
[U-Boot] [PATCH 4/8] powerpc/boot: Master module for boot from SRIO
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:
master:
1. Nor flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image in master Nor flash.
3. Normally boot from local Nor flash.
4. Configure SRIO switch system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to SRIO1 or SRIO2 by RCW.
3. RCW should configure the SerDes, SRIO interfaces correctly.
4. Slave must be powered on after master's boot.
For the master module, need to finish these processes:
1. Initialize the SRIO port and address space.
2. Set inbound SRIO windows covered slave's u-boot image stored in
master's Nor flash.
3. Master's u-boot image should be generated specifically by
make _SRIOBOOT_MASTER_config
4. Master must boot first, and then slave can be powered on.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
arch/powerpc/cpu/mpc85xx/cpu_init.c |6 ++-
arch/powerpc/cpu/mpc8xxx/srio.c | 42 ++
arch/powerpc/include/asm/fsl_srio.h | 61 +
arch/powerpc/include/asm/immap_85xx.h |3 ++
boards.cfg|3 ++
include/configs/corenet_ds.h | 18 ++
6 files changed, 131 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/include/asm/fsl_srio.h
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 9141ba4..42d6475 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -37,6 +37,7 @@
#include asm/mmu.h
#include asm/fsl_law.h
#include asm/fsl_serdes.h
+#include asm/fsl_srio.h
#include linux/compiler.h
#include mp.h
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
@@ -48,8 +49,6 @@
DECLARE_GLOBAL_DATA_PTR;
-extern void srio_init(void);
-
#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -443,6 +442,9 @@ skip_l2:
#ifdef CONFIG_SYS_SRIO
srio_init();
+#ifdef CONFIG_SRIOBOOT_MASTER
+ srio_boot_master();
+#endif
#endif
#if defined(CONFIG_MP)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index e46d328..e8ce3a3 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -21,6 +21,7 @@
#include config.h
#include asm/fsl_law.h
#include asm/fsl_serdes.h
+#include asm/fsl_srio.h
#if defined(CONFIG_FSL_CORENET)
#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
@@ -84,3 +85,44 @@ void srio_init(void)
setbits_be32(gur-devdisr, _DEVDISR_RMU);
}
}
+
+#ifdef CONFIG_SRIOBOOT_MASTER
+void srio_boot_master(void)
+{
+ ccsr_rio_t *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+
+ /* set port accept-all */
+ out_be32((u32)srio-ptaacr + CONFIG_SRIOBOOT_MASTER_PORT * 0x80,
+ 0x1001);
+
+ printf(SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n,
+ CONFIG_SRIOBOOT_MASTER_PORT);
+ /* configure inbound window1 for slave's u-boot image */
+ printf(SRIOBOOT - MASTER: Inbound window1 for slave's image;
+ Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
+ out_be32((u32)srio-riwtar1 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 12);
+ out_be32((u32)srio-riwbar1 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 12);
+ out_be32((u32)srio-riwar1 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
+ 0x80f55000
+ | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
+
+ /* configure inbound window2 for slave's u-boot image */
+ printf(SRIOBOOT - MASTER: Inbound window2 for slave's image;
+ Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
+ out_be32((u32)srio-riwtar2 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200
[U-Boot] [PATCH 1/8] powerpc/srio: Correct the register defined errors in the struct ccsr_rio_t
Many registers were not defined in the struct ccsr_rio_t in the file
arch/powerpc/include/asm/immap_85xx.h. For example it lacks registers
from offset 0xc0600 to 0xd0160. Accordingly, some register's offset
need to be modified in the struct.
In addition, add the register's offset in the comments.
Signed-off-by: Liu Gang gang@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h | 338 -
1 files changed, 202 insertions(+), 136 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 92da130..623be17 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1355,168 +1355,234 @@ typedef struct ccsr_cpm {
/* RapidIO Registers */
typedef struct ccsr_rio {
- u32 didcar; /* Device Identity Capability */
- u32 dicar; /* Device Information Capability */
- u32 aidcar; /* Assembly Identity Capability */
- u32 aicar; /* Assembly Information Capability */
- u32 pefcar; /* Processing Element Features Capability */
- u32 spicar; /* Switch Port Information Capability */
- u32 socar; /* Source Operations Capability */
- u32 docar; /* Destination Operations Capability */
+ u32 didcar; /* 0xc - Device Identity CAR */
+ u32 dicar; /* 0xc0004 - Device Information CAR */
+ u32 aidcar; /* 0xc0008 - Assembly Identity CAR */
+ u32 aicar; /* 0xc000c - Assembly Information CAR */
+ u32 pefcar; /* 0xc0010 - Processing Element Features CAR */
+ u32 spicar; /* 0xc0014 - Switch Port Information CAR */
+ u32 socar; /* 0xc0018 - Source Operations CAR */
+ u32 docar; /* 0xc001c - Destination Operations CAR */
u8 res1[32];
- u32 msr;/* Mailbox Cmd And Status */
- u32 pwdcsr; /* Port-Write Doorbell Cmd And Status */
+ u32 mcsr; /* 0xc0040 - Mailbox CSR */
+ u32 pwdcsr; /* 0xc0044 - Port-Write and Doorbell CSR */
u8 res2[4];
- u32 pellccsr; /* Processing Element Logic Layer CCSR */
+ u32 pellccsr; /* 0xc004c - Processing Element Logic Layer CCSR */
u8 res3[12];
- u32 lcsbacsr; /* Local Cfg Space Base Addr Cmd Status */
- u32 bdidcsr;/* Base Device ID Cmd Status */
+ u32 lcsbacsr; /* 0xc005c - Local Configuration Space BACSR */
+ u32 bdidcsr; /* 0xc0060 - Base Device ID CSR */
u8 res4[4];
- u32 hbdidlcsr; /* Host Base Device ID Lock Cmd Status */
- u32 ctcsr; /* Component Tag Cmd Status */
+ u32 hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock CSR */
+ u32 ctcsr; /* 0xc006c - Component Tag CSR */
u8 res5[144];
- u32 pmbh0csr; /* Port Maint. Block Hdr 0 Cmd Status */
+ u32 pmbh0csr; /* 0xc0100 - Port Maintenance Block Header 0 CSR */
u8 res6[28];
- u32 pltoccsr; /* Port Link Time-out Ctrl Cmd Status */
- u32 prtoccsr; /* Port Response Time-out Ctrl Cmd Status */
+ u32 pltoccsr; /* 0xc0120 - Port Link Time-out CCSR */
+ u32 prtoccsr; /* 0xc0124 - Port Response Time-out CCSR */
u8 res7[20];
- u32 pgccsr; /* Port General Cmd Status */
- u32 plmreqcsr; /* Port Link Maint. Request Cmd Status */
- u32 plmrespcsr; /* Port Link Maint. Response Cmd Status */
- u32 plascsr;/* Port Local Ackid Status Cmd Status */
+ u32 pgccsr; /* 0xc013c - Port General CSR */
+ u32 plmreqcsr; /* 0xc0140 - Port Link Maintenance Request CSR */
+ u32 plmrespcsr; /* 0xc0144 - Port Link Maintenance Response CSR */
+ u32 plascsr; /* 0xc0148 - Port Local Ackid Status CSR */
u8 res8[12];
- u32 pescsr; /* Port Error Status Cmd Status */
- u32 pccsr; /* Port Control Cmd Status */
- u8 res9[65184];
- u32 cr; /* Port Control Cmd Status */
- u8 res10[12];
- u32 pcr;/* Port Configuration */
- u32 peir; /* Port Error Injection */
- u8 res11[3048];
- u32 rowtar0;/* RIO Outbound Window Translation Addr 0 */
- u8 res12[12];
- u32 rowar0; /* RIO Outbound Attrs 0 */
+ u32 pescsr; /* 0xc0158 - Port Error and Status CSR */
+ u32 pccsr; /* 0xc015c - Port Control CSR */
+ u8 res9[1184];
+ u32 erbh; /* 0xc0600 - Error Reporting Block Header Register */
+ u8 res10[4];
+ u32 ltledcsr; /* 0xc0608 - Logical/Transport layer error DCSR */
+ u32 ltleecsr; /* 0xc060c - Logical
[U-Boot] [PATCH 5/8] powerpc/boot: Slave module for boot from SRIO
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:
master:
1. Nor flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image in master Nor flash.
3. Normally boot from local Nor flash.
4. Configure SRIO switch system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to SRIO1 or SRIO2 by RCW.
3. RCW should configure the SerDes, SRIO interfaces correctly.
4. Slave must be powered on after master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to SRIO1 or SRIO2 by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot.
4. Slave's u-boot image should be generated specifically by
make _SRIOBOOT_SLAVE_config.
This will set SYS_TEXT_BASE=0xFFF8 and other configurations.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
board/freescale/common/p_corenet/law.c |9 +
board/freescale/common/p_corenet/tlb.c |9 +
boards.cfg |3 +++
drivers/net/fm/fm.c|2 ++
include/configs/corenet_ds.h | 21 +
5 files changed, 44 insertions(+), 0 deletions(-)
diff --git a/board/freescale/common/p_corenet/law.c
b/board/freescale/common/p_corenet/law.c
index 09ef561..1fbab4d 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -48,6 +48,15 @@ struct law_entry law_table[] = {
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
+#ifdef CONFIG_SRIOBOOT_SLAVE
+#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
+ SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
+#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
+ SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
+#endif
+#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index 6a0026a..cb4339f 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -66,6 +66,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIOBOOT_SLAVE)
+ /*
+* *I*G - SRIOBOOT-SLAVE. When slave boot, the address of the
+* space is at 0xfff0, it covered the 0xf000.
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
#else
SET_TLB_ENTRY(1, 0xf000, 0xf000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
diff --git a/boards.cfg b/boards.cfg
index 27f3900..0ea8988 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -735,6 +735,7 @@ P3041DS_SDCARD powerpc mpc85xx
corenet_ds freescale
P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds
freescale - P3041DS:SECURE_BOOT
P3041DS_SPIFLASHpowerpc mpc85xx corenet_ds
freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
P3041DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds
freescale - P3041DS:SRIOBOOT_MASTER
+P3041DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds
freescale - P3041DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF8
P3060QDSpowerpc mpc85xx p3060qds
freescale
P3060QDS_NAND powerpc mpc85xx p3060qds
freescale - P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8
P3060QDS_SECURE_BOOT powerpc mpc85xx p3060qds
freescale - P3060QDS:SECURE_BOOT
@@ -743,12 +744,14 @@ P4080DS_SDCARD powerpc mpc85xx
corenet_ds freescale
P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds
freescale
[U-Boot] [PATCH 7/8] powerpc/boot: Slave reads ENV from master when boot from SRIO
When boot from SRIO, slave's ENV can be stored in master's memory space,
then slave can fetch the ENV through SRIO interface.
NOTE: Because the slave can not erase, write master's Norflash by SRIO
interface, so it can not modify the ENV parameters stored in
master's Norflash using saveenv or other commands.
Master needs to:
1. Put the slave's ENV into it's own memory space.
2. Set an inbound SRIO window covered slave's ENV stored in master's
memory space.
Slave needs to:
1. Set a specific TLB entry in order to fetch ucode and ENV from master.
2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
arch/powerpc/cpu/mpc8xxx/srio.c | 14 +++
common/Makefile |1 +
common/cmd_nvedit.c |3 +-
common/env_remote.c | 78 +++
include/configs/corenet_ds.h| 14 +++
5 files changed, 109 insertions(+), 1 deletions(-)
create mode 100644 common/env_remote.c
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 740d28a..c899480 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -138,5 +138,19 @@ void srio_boot_master(void)
out_be32((u32)srio-riwar3 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
0x80f55000
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE));
+
+ /* configure inbound window for slave's ENV */
+ printf(SRIOBOOT - MASTER: Inbound window for slave's ENV;
+ Local = 0x%llx, Siro = 0x%llx, Size = 0x%x\n,
+ CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS,
+ CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS,
+ CONFIG_SRIOBOOT_SLAVE_ENV_SIZE);
+ out_be32((u32)srio-riwtar4 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
+ CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 12);
+ out_be32((u32)srio-riwbar4 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
+ CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 12);
+ out_be32((u32)srio-riwar4 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
+ 0x80f55000
+ | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE));
}
#endif
diff --git a/common/Makefile b/common/Makefile
index 1b672ad..5c99450 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -61,6 +61,7 @@ COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o
COBJS-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
+COBJS-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
# command
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index 5995354..d8372fd 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -65,9 +65,10 @@ DECLARE_GLOBAL_DATA_PTR;
!defined(CONFIG_ENV_IS_IN_NVRAM) \
!defined(CONFIG_ENV_IS_IN_ONENAND) \
!defined(CONFIG_ENV_IS_IN_SPI_FLASH) \
+ !defined(CONFIG_ENV_IS_IN_REMOTE)\
!defined(CONFIG_ENV_IS_NOWHERE)
# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\
-SPI_FLASH|MG_DISK|NVRAM|MMC} or CONFIG_ENV_IS_NOWHERE
+SPI_FLASH|MG_DISK|NVRAM|MMC|REMOTE} or CONFIG_ENV_IS_NOWHERE
#endif
#define XMK_STR(x) #x
diff --git a/common/env_remote.c b/common/env_remote.c
new file mode 100644
index 000..4c6b781
--- /dev/null
+++ b/common/env_remote.c
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include common.h
+#include command.h
+#include environment.h
+#include linux/stddef.h
+
+char *env_name_spec = Remote;
+
+#ifdef ENV_IS_EMBEDDED
+env_t *env_ptr = environment;
+#else /* ! ENV_IS_EMBEDDED */
+env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR;
+#endif /* ENV_IS_EMBEDDED */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !defined(CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_OFFSET 0
+#endif
+
+uchar env_get_char_spec(int index
[U-Boot] [PATCH 8/8] powerpc/boot: Slave core in holdoff when boot from SRIO
When boot from SRIO, slave's core can be in holdoff after powered on for
some specific requirements. Master can release the slave's core at the
right time by SRIO interface.
Master needs to:
1. Set outbound SRIO windows in order to configure slave's registers
for the core's releasing.
2. Check the SRIO port status when release slave core, if no errors,
will implement the process of the slave core's releasing.
Slave needs to:
1. Set all the cores in holdoff by RCW.
2. Be powered on before master's boot.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
arch/powerpc/cpu/mpc85xx/cpu_init.c |3 +
arch/powerpc/cpu/mpc8xxx/srio.c | 114 +++
arch/powerpc/include/asm/fsl_srio.h |3 +
include/configs/corenet_ds.h|4 +
4 files changed, 124 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 42d6475..9284e443 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -444,6 +444,9 @@ skip_l2:
srio_init();
#ifdef CONFIG_SRIOBOOT_MASTER
srio_boot_master();
+#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
+ srio_boot_master_release_slave();
+#endif
#endif
#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index c899480..66ecf0b 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -23,6 +23,11 @@
#include asm/fsl_serdes.h
#include asm/fsl_srio.h
+#define RIO_LCSBA1CSR_OFFSET 0x5c
+#define RIO_MAINT_WIN_SIZE 0x100 /* 16M */
+#define RIO_RW_WIN_SIZE 0x10 /* 1M */
+#define RIO_LCSBA1CSR 0x6000
+
#if defined(CONFIG_FSL_CORENET)
#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
@@ -153,4 +158,113 @@ void srio_boot_master(void)
0x80f55000
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE));
}
+
+#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
+void srio_boot_master_release_slave(void)
+{
+ ccsr_rio_t *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+ u32 escsr;
+
+ printf(SRIOBOOT - MASTER:
+ Check the port status and release slave core ...\n);
+
+ escsr = in_be32((u32)srio-pescsr
+ + CONFIG_SRIOBOOT_MASTER_PORT * 0x20);
+ if (escsr 0x2) {
+ if (escsr 0x10100) {
+ printf(SRIOBOOT - MASTER: Port [ %d ] is error.\n,
+ CONFIG_SRIOBOOT_MASTER_PORT);
+ } else {
+ printf(SRIOBOOT - MASTER:
+ Port [ %d ] is ready, now release
slave's core ...\n,
+ CONFIG_SRIOBOOT_MASTER_PORT);
+ /*
+* configure outbound window
+* with maintenance attribute to set slave's LCSBA1CSR
+*/
+ out_be32((u32)srio-rowtar1
+ + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, 0);
+ out_be32((u32)srio-rowtear1
+ + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, 0);
+ if (CONFIG_SRIOBOOT_MASTER_PORT)
+ out_be32((u32)srio-rowbar1
+ + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
+ CONFIG_SYS_SRIO2_MEM_PHYS 12);
+ else
+ out_be32((u32)srio-rowbar1
+ + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
+ CONFIG_SYS_SRIO1_MEM_PHYS 12);
+ out_be32((u32)srio-rowar1
+ + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
+ 0x80077000
+ | atmu_size_mask(RIO_MAINT_WIN_SIZE));
+
+ /*
+* configure outbound window
+* with R/W attribute to set slave's BRR
+*/
+ out_be32((u32)srio-rowtar2
+ + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
+ RIO_LCSBA1CSR 9);
+ out_be32((u32)srio-rowtear2
+ + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, 0);
+ if (CONFIG_SRIOBOOT_MASTER_PORT)
+ out_be32((u32)srio-rowbar2
+ + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
+ (CONFIG_SYS_SRIO2_MEM_PHYS
+ + RIO_MAINT_WIN_SIZE) 12);
+ else
Re: [U-Boot] [PATCH 6/8] powerpc/boot: Slave uploads ucode when boot from SRIO
-Original Message- From: Tabi Timur-B04825 Sent: Wednesday, January 11, 2012 1:03 AM To: Liu Gang-B34182 Cc: u-boot@lists.denx.de; alexandre.boun...@idt.com; Gala Kumar-B11780; Zang Roy-R61911; Xie Shaohui-B21989 Subject: Re: [U-Boot] [PATCH 6/8] powerpc/boot: Slave uploads ucode when boot from SRIO On Tue, Jan 10, 2012 at 5:42 AM, Liu Gang gang@freescale.com wrote: When boot from SRIO, slave's ucode can be stored in master's memory space, then slave can fetch the ucode image through SRIO interface. What kind of ucode is this? Fman or QE? [Liu Gang-B34182] Right now the ucode is for Fman. + + /* configure inbound window for slave's ucode */ + printf(SRIOBOOT - MASTER: Inbound window for slave's ucode; + Local = 0x%llx, Srio = 0x%llx, Size = + 0x%x\n, + (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS, + (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS, + CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE); + out_be32((u32)srio-riwtar3 + CONFIG_SRIOBOOT_MASTER_PORT * + 0x200, These should be (void *) instead of (u32). [Liu Gang-B34182] Thanks very much! -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/8] powerpc/env: Correct the compilation errors when defined CONFIG_ENV_IS_NOWHERE
Hi, Timur, Thanks for your comments. Please find my replies inline. Best Regards, Liu Gang -Original Message- From: Tabi Timur-B04825 Sent: Wednesday, January 11, 2012 12:48 AM To: Liu Gang-B34182 Cc: u-boot@lists.denx.de; alexandre.boun...@idt.com; Gala Kumar-B11780; Zang Roy-R61911 Subject: Re: [U-Boot] [PATCH 2/8] powerpc/env: Correct the compilation errors when defined CONFIG_ENV_IS_NOWHERE On Tue, Jan 10, 2012 at 5:42 AM, Liu Gang gang@freescale.com wrote: There will be a confict if defined CONFIG_ENV_IS_NOWHERE and CONFIG_ENV_IS_IN_FLASH. This doesn't make any sense. How can the environment be nowhere *and* also in flash, at the same time? [Liu Gang-B34182] The environment cannot be nowhere *and* also in flash at the same time! So we should not re-defined CONFIG_ENV_IS_IN_FLASH if the CONFIG_ENV_IS_NOWHERE has been defined. But the code will still define CONFIG_ENV_IS_IN_FLASH if the CONFIG_ENV_IS_NOWHERE has been defined. This will cause a compilation error described in this patch. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/8] powerpc/boot: Slave module for boot from SRIO
-Original Message- From: Tabi Timur-B04825 Sent: Wednesday, January 11, 2012 1:11 AM To: Liu Gang-B34182 Cc: u-boot@lists.denx.de; alexandre.boun...@idt.com; Gala Kumar-B11780; Zang Roy-R61911; Xie Shaohui-B21989 Subject: Re: [U-Boot] [PATCH 5/8] powerpc/boot: Slave module for boot from SRIO On Tue, Jan 10, 2012 at 5:42 AM, Liu Gang gang@freescale.com wrote: +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE #define +CONFIG_SYS_QE_FMAN_FW_ADDR 0 Where is CONFIG_SYS_QE_FMAN_FW_IN_REMOTE documented? And where is the code that uses it? [Liu Gang-B34182] Sorry I documented this definition in [PATCH 6/8] powerpc/boot: Slave uploads ucode when boot from SRIO, I'll add descriptions about this definition in PATCH 5/8. The function fm_init_common in the file drivers/net/fm/fm.c uses the CONFIG_SYS_QE_FMAN_FW_IN_REMOTE. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/8] powerpc/boot: Slave module for boot from SRIO
Thanks very much! I'll update the patch based on your comments. Best Regards, Liu Gang -Original Message- From: Tabi Timur-B04825 Sent: Wednesday, January 11, 2012 11:00 AM To: Liu Gang-B34182 Cc: 'u-boot@lists.denx.de'; 'alexandre.boun...@idt.com'; Gala Kumar-B11780; Zang Roy-R61911; Xie Shaohui-B21989 Subject: Re: [U-Boot] [PATCH 5/8] powerpc/boot: Slave module for boot from SRIO Liu Gang-B34182 wrote: Where is CONFIG_SYS_QE_FMAN_FW_IN_REMOTE documented? And where is the code that uses it? [Liu Gang-B34182] Sorry I documented this definition in [PATCH 6/8] powerpc/boot: Slave uploads ucode when boot from SRIO, You need to update the README. That's where all the other CONFIG_SYS_QE_FMAN_FW_xxx macros are documented. I'll add descriptions about this definition in PATCH 5/8. The function fm_init_common in the file drivers/net/fm/fm.c uses the CONFIG_SYS_QE_FMAN_FW_IN_REMOTE. The code which adds CONFIG_SYS_QE_FMAN_FW_IN_REMOTE support should be its own patch. And the patch summary should say CONFIG_SYS_QE_FMAN_FW_IN_REMOTE. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
