Re: [PATCH 11/11] vexpress64: Add ARMv8R-64 board variant

[Liviu Dudau]

On Fri, Mar 04, 2022 at 04:30:18PM +, Andre Przywara wrote:
> From: Peter Hoyes 
> 
> The ARMv8-R64 architecture introduces optional VMSA (paging based MMU)
> support in the EL1/0 translation regime, which makes that part mostly
> compatible to ARMv8-A.
> 
> Add a new board variant to describe the "BASE-R64" FVP model, which
> inherits a lot from the existing v8-A FVP support. One major difference
> is that the memory map in "inverted": DRAM starts at 0x0, MMIO is at
> 2GB [1].
> 
>  * Create new TARGET_VEXPRESS64_BASER_FVP target, sharing most of the
>exising configuration.

I know I'm arguing about the colour of the shed, but can we make the new target
easier to distinguish from the TARGET_VEXPRESS64_BASE_FVP by inserting an 
underscore
between BASE and R?

Best regards,
Liviu


>  * Implement inverted memory map in vexpress_aemv8.h
>  * Create vexpress_aemv8r defconfig
>  * Provide an MMU memory map for the BASER_FVP
>  * Update vexpress64 documentation
> 
> At the moment the boot-wrapper is the only supported secure firmware. As
> there is no official DT for the board yet, we rely on it being supplied
> by the boot-wrapper into U-Boot, so use OF_HAS_PRIOR_STAGE, and go with
> a dummy DT for now.
> 
> [1] 
> https://developer.arm.com/documentation/100964/1114/Base-Platform/Base---memory/BaseR-Platform-memory-map
> 
> Signed-off-by: Peter Hoyes 
> [Andre: rebase and add Linux kernel header]
> Signed-off-by: Andre Przywara 
> ---
>  arch/arm/dts/Makefile |  1 +
>  arch/arm/dts/arm_fvp.dts  | 11 +++
>  board/armltd/vexpress64/Kconfig   | 22 +-
>  configs/vexpress_aemv8r_defconfig | 14 ++
>  doc/arch/arm64.rst|  3 ++-
>  doc/board/armltd/vexpress64.rst   |  1 +
>  include/configs/vexpress_aemv8.h  | 23 +++
>  7 files changed, 69 insertions(+), 6 deletions(-)
>  create mode 100644 arch/arm/dts/arm_fvp.dts
>  create mode 100644 configs/vexpress_aemv8r_defconfig
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 4c8492cd7d..77e08d5331 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -1181,6 +1181,7 @@ dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
>  # Kconfig option to build all of these. See examples above.
>  dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb
>  dtb-$(CONFIG_TARGET_VEXPRESS64_BASE_FVP) += fvp-base-revc.dtb
> +dtb-$(CONFIG_TARGET_VEXPRESS64_BASER_FVP) += arm_fvp.dtb
>  dtb-$(CONFIG_TARGET_VEXPRESS64_JUNO) += juno-r2.dtb
>  
>  dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
> diff --git a/arch/arm/dts/arm_fvp.dts b/arch/arm/dts/arm_fvp.dts
> new file mode 100644
> index 00..3a4ad5d180
> --- /dev/null
> +++ b/arch/arm/dts/arm_fvp.dts
> @@ -0,0 +1,11 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> +/*
> + * Empty device tree for the Arm Ltd FVP platform model
> +
> + * Copyright 2022 Arm Ltd.
> + */
> +
> +/dts-v1/;
> +
> +/ {
> +};
> diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig
> index 512bbbe72e..a0314c6537 100644
> --- a/board/armltd/vexpress64/Kconfig
> +++ b/board/armltd/vexpress64/Kconfig
> @@ -9,19 +9,28 @@ config SYS_VENDOR
>  config SYS_CONFIG_NAME
>   default "vexpress_aemv8"
>  
> -choice
> - prompt "VExpress64 board variant"
> -
> -config TARGET_VEXPRESS64_BASE_FVP
> - bool "Support Versatile Express ARMv8a FVP BASE model"
> +config VEXPRESS64_BASE_MODEL
> + bool
>   select SEMIHOSTING
>   select VIRTIO_BLK if VIRTIO_MMIO
>   select VIRTIO_NET if VIRTIO_MMIO
>   select DM_ETH if VIRTIO_NET
>   select LINUX_KERNEL_IMAGE_HEADER
>   select POSITION_INDEPENDENT
> +
> +choice
> + prompt "VExpress64 board variant"
> +
> +config TARGET_VEXPRESS64_BASE_FVP
> + bool "Support Versatile Express ARMv8a FVP BASE model"
> + select VEXPRESS64_BASE_MODEL
>   select OF_BOARD
>  
> +config TARGET_VEXPRESS64_BASER_FVP
> + bool "Support Versatile Express ARMv8r64 FVP BASE model"
> + select VEXPRESS64_BASE_MODEL
> + imply OF_HAS_PRIOR_STAGE
> +
>  config TARGET_VEXPRESS64_JUNO
>   bool "Support Versatile Express Juno Development Platform"
>   select PCIE_ECAM_GENERIC if PCI
> @@ -50,6 +59,7 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE
>  config SYS_TEXT_BASE
>   default 0x8800 if TARGET_VEXPRESS64_BASE_FVP
>   default 0xe000 if TARGET_VEXPRESS64_JUNO
> + default 0x1000 if TARGET_VEXPRESS64_BASER_FVP
>  
>  config SYS_MALLOC_LEN
>   default 0x81 if TARGET_VEXPRESS64_JUNO
> @@ -59,11 +69,13 @@ config SYS_MALLOC_F_LEN
>   default 0x2000
>  
>  config SYS_LOAD_ADDR
> + default 0x1000 if TARGET_VEXPRESS64_BASER_FVP
>   default 0x9000
>  
>  config ENV_ADDR
>   default 0x0BFC if TARGET_VEXPRESS64_JUNO
>   default 0x0FFC if TARGET_VEXPRESS64_BASE_FVP
> + default 0x8FFC if TARGET_VEXPRESS64_BASER_FVP
>  
>  config ENV_SIZE
>   default 0x1 if 

Re: [U-Boot] [PATCH] vexpress64: fix a typo of SPDX-License-Identifier

[Liviu Dudau]

On Tue, Jun 18, 2019 at 12:25:51PM +0900, Masahiro Yamada wrote:
> Misspelling of SPDX-License-Identifier is rather fatal than other
> general typos, so must be fixed.
> 
> This file spells SPDX-Licence-Identifier.
>^
> 
> I also moved it to the very top of the file with // comment style.
> 
> Detected by grepping the source tree:
> 
> $ git grep --not -e SPDX-License-Identifier --and -e SPDX-
> board/armltd/vexpress64/pcie.c: * SPDX-Licence-Identifier:  GPL-2.0+
> 
> Signed-off-by: Masahiro Yamada 

Acked-by: Liviu Dudau 

Thanks for the fix!

Best regards,
Liviu

> ---
> 
>  board/armltd/vexpress64/pcie.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c
> index 0608a5a88b94..21156a4ca94f 100644
> --- a/board/armltd/vexpress64/pcie.c
> +++ b/board/armltd/vexpress64/pcie.c
> @@ -1,9 +1,8 @@
> +// SPDX-License-Identifier: GPL-2.0+
>  /*
>   * Copyright (C) ARM Ltd 2015
>   *
>   * Author: Liviu Dudau 
> - *
> - * SPDX-Licence-Identifier:  GPL-2.0+
>   */
>  
>  #include 
> -- 
> 2.17.1
> 

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Re: [U-Boot] Booting linux zImage on vexpress-a15

[Liviu Dudau]

On Thu, Feb 07, 2019 at 01:55:00PM +0100, Andre Wagner wrote:
> Hi Liviu,
> 
> thank you very much for your reply. A very good hint was that I need to set
> the extra kernel parameter earlyprintk for showing further debug output. I
> expected that setting the 'Early Printk' option in Kconfig is enough. After
> adding this kernel parameter i can see the kernel boot messages, but the
> kernel stucks now at 'smp: Bringing up secondary CPUs ...'. As a cross-check
> I booted the kernel directly on the qemu vexpress machine and there are also
> error messages at the SMP step shown, but the boot process continues. In the
> running system I can only see one CPU, so SMP does not work at all. So I
> disabled all CPUs expect the first one in the device tree, so my boot
> procedure in u-boot is as following:
> 
> 1. Set boot args: setenv bootargs console=ttyAMA0 earlyprintk debug verbose

May I suggest you use

   $ setenv bootargs 'console=ttyAMA0 earlyprintk debug verbose'

i.e. put single quotes around the value of the variable.

> 
> 2. Load the zImage at start of RAM + 8000h offset: ext4load mmc 0:1 80008000
> zImage
> 
> 3. Load Device Tree: ext4load mmc 0:1 8a00 vexpress-v2p-ca15-tc1.dtb
> 
> 4. Init fdt subsystem: fdt addr 8a00

In my test with mainline kernel and U-Boot from yesterday I didn't had to do
this, because 

> 
> 5. Deactivate second CPU:  fdt rm /cpus/cpu@1

I didn't have to disable the other CPUs either.


> 
> 6. Boot with bootz command: bootz 80008000 - 8a00
> 
> 7. In the SMP boot step only one CPU it recognized, the boot process
> continues
> 
> 8. Now the boot process stucks at 'DMA: preallocated 256 KiB pool for atomic
> coherent allocations'
> 
> 
> Further I found that:
> 
> 1. The space between kernel loadaddr and DTB load address of 2ff8000h Bytes
> (about 50MB) was big enough, since there is no difference if I use the old
> (8500h) or the new DTB loadaddr (8a00h). Just for being on the sure
> site I continue using 8a00 for DTB load address
> 
> 2. All vexpress DTBs contain a ARM HBI number with seems to be a
> identificator for the ARM board. The ARM HBI of vexpress-v2p-ca15-tc1.dtb
> fits the expected ARM HBI of the qemu vexpress-a15, the
> vexpress-v2p-ca15_a7.dtb fits not. So I keep using the
> vexpress-v2p-ca15-tc1.dtb device tree

Like I've said, those dtbs are for real hardware CoreTiles placed inside the
Versatile Express motherboard. I don't know (or remember exactly) if qemu
emulates all the aspects, but it should not matter much.

> 
> 3. I recompiled the vexpress-v2p-ca15-tc1.dtb device tree without the
> /cpus/cpu@1 and let it run directly by qemu. The boot process succeeds. The
> next message after 'DMA: preallocated 256 KiB pool for atomic coherent
> allocations' is in this case 'cpuidle: using governor ladder'
> 
> 4. I didn't mentioned the versions I'm using: It's qemu version
> 2.11.1(Debian 1:2.11+dfsg-1ubuntu7.8), Linux version 5.0.0-rc5 and U-Boot
> version 2019.01-00523-ge5fd39c886. I'm aware that these are development
> versions.

My versions are qemu 3.1.0, U-Boot 2019.01-00058-g23b00a07fc-dirty, 
Linux version 5.0.0-rc5+. Attached is a log of my session.

Best regards,
Liviu

> 
> 
> At this point I assume that kernel and DTB are loaded correctly, but I
> haven't any idea what influence u-boot can have initializing DMA and/or
> cpuidle. Any suggestions?
> 
> 
> P.S. I will continue testing other stable vanilla kernels.
> 
> P.S. I attached the boot logs: The file boot_qemu_only is the successful
> boot with qemu only via kernel and dtb option, the file boot_qemu_uboot is
> the boot with qemu + u-boot.
> 
> 
> Thanks for your help.
> 
> Greetings,
> 
> André
> 
> 
> 
> 
> On 06.02.19 17:58, Liviu Dudau wrote:
> > On Tue, Feb 05, 2019 at 07:05:55PM +0100, Andre Wagner wrote:
> > > Hi @all,
> > Hi Andre,
> > 
> 
> > > I'm trying to build a linux kernel as zImage and boot it with u-boot on a
> > > qemu vexpress-a15 machine. The host machine is a Ubuntu 18.04.
> > > 
> > > What I tried until now:
> > > 
> > > 1. Get Linux from git, export ARCH=arm and
> > > CROSS_COMPILE=arm-linux-gnueabihf-
> > > 
> > > 2. Make Defconfig: make vexpress_defconfig
> > > 
> > > 3. Enable 'Early Printk' with make menuconfig
> > > 
> > > 4. Make Kernel: make
> > > 
> > > 5. Get U-Boot from git, export ARCH=arm and
> > > CROSS_COMPILE=arm-linux-gnueabihf-
> > > 
> > > 6. Make Defconfig: make vexpress_ca15_tc2_defconfig
> > > 
> > > 7. Make U-Boot: make
> > > 
> > > 8. Generate empty image file and mount

Re: [U-Boot] Booting linux zImage on vexpress-a15

[Liviu Dudau]

On Tue, Feb 05, 2019 at 07:05:55PM +0100, Andre Wagner wrote:
> Hi @all,

Hi Andre,

> 
> I'm trying to build a linux kernel as zImage and boot it with u-boot on a
> qemu vexpress-a15 machine. The host machine is a Ubuntu 18.04.
> 
> What I tried until now:
> 
> 1. Get Linux from git, export ARCH=arm and
> CROSS_COMPILE=arm-linux-gnueabihf-
> 
> 2. Make Defconfig: make vexpress_defconfig
> 
> 3. Enable 'Early Printk' with make menuconfig
> 
> 4. Make Kernel: make
> 
> 5. Get U-Boot from git, export ARCH=arm and
> CROSS_COMPILE=arm-linux-gnueabihf-
> 
> 6. Make Defconfig: make vexpress_ca15_tc2_defconfig
> 
> 7. Make U-Boot: make
> 
> 8. Generate empty image file and mount it: truncate -s 100M image; mkfs.ext4
> image; mount -o loop image /mnt
> 
> 9. Copy zImage and DTB to image: cp arch/arm/boot/zImage /mnt ; cp
> arch/arm/boot/dts/vexpress-v2p-ca15_a7.dtb /mnt
> 
> 10. Unmount Image: umount /mnt
> 
> 11. Start u-boot in qemu: qemu-system-arm -m 1024M -M vexpress-a15 -cpu
> cortex-a15 -kernel u-boot -serial stdio -sd image => U-Boot comes up and I
> can hit a key to stop automount, ok so far
> 
> 12. In u-boot, checking filesystem on image: ext4ls mmc 0:0 => I can see my
> zImage and my DTB file, ok so far
> 
> 13. In u-boot, loading kernel: ext4load mmc 0:0 82008000 zImage => 
> bytes read is shown, ok so far
> 
> 14. In u-boot, loading DTB: ext4load mmc 0:0 8500
> vexpress-v2p-ca15_a7.dtb =>  bytes read, ok so far
> 
> 15. In u-boot, boot: bootz 82008000 - 8500 => 'Starting kernel ' and
> 'Uncompressing kernel done' is shown and then nothing at all...

I think your problem is that you're putting the device tree too close to the
kernel, so it might be trampled on by the kernel decompression.

Steps I suggest you try that worked in my environment:

  1. set the bootargs variable in U-Boot to 'console=ttyAMA0 earlyprintk debug 
verbose'
  2. Load the kernel at 0x80008000

> 
> 
> Cross-checks I have done right now:
> 
> - Booting kernel and DTB directly from qemu with 'qemu-system-arm -m 1024M
> -M vexpress-a15 -cpu cortex-a15 -kernel arch/arm/boot/zImage  -dtb
> arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dtb -serial stdio' works, normal
> boot output is shown. Also the standard console device ttyAMA0 is available
> after mounting devtmpfs.
> 
> - Same setup with vexpress-a9  (uboot with vexpress_ca9x4_defconfig, linux
> with vexpress_defconfig and DTB vexpress-v2p-ca9.dtb. The kernel was loaded
> to 62008000 and the DTB to 6500) worked, Normal boot output was shown.
> 
> 
> What I don't understand right now is:
> 
> - Am I using the corrected DTB? vexpress-v2p-ca15-tc1.dtb or
> vexpress-v2p-ca15_a7.dtb ? Which is the right one?

None is the right one, as they are DTBs for actual hardware that QEMU doesn't
emulate correctly with your parameters. However, the emulation should be close
enough to allow you to boot the kernel.

> 
> - What are the addresses I need to load kernel and the DTB? In the working
> vexpress-a9 sample the kernel was loaded with a offset of 2008000h and the
> DTB with a offset of 500h to start of RAM at 6000h. So I decided use
> the same offsets with the alternate start of RAM address of 800h of
> vexpress-a15, i.e. kernel at 82008000 and DTB at 8500. Is this
> assumption correct?

No, the offset should be 0x8000 from the start of your memory, because the 
kernel
for arm arch expects to be loaded at the beginning of the RAM. For DTB it 
doesn't
matter (other than probably faster if it is 32bit aligned).

> 
> - 'Starting kernel...' is a last message from u-boot and 'Uncompressing
> kernel done' the first from the kernels self extractor?

Correct.

> 
> - Where in RAM is the zImage decompressed by u-boot bootz? Between start of
> RAM at 8000h and kernels loadaddr at 82008000h?

I might be wrong but I believe it decompresses in memory *after* the kernel 
image,
not before (otherwise the decompression might generate an image that overwrites
 the start of the kernel, which is where the decompressor lives).

> 
> - What are the differences between loading kernel and DTB by qemu directly
> and loading kernel and DTB indirectly via u-boot?

Placement in memory of the kernel image :)

Best regards,
Liviu

> 
> 
> Thank you very very much for your replies in advance.
> 
> 
> Greetings,
> 
> André
> 
> 
> +++
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Re: [U-Boot] [PATCH] dm: Tidy up 'dm tree' output when there are many devices

[Liviu Dudau]

On Wed, Dec 05, 2018 at 06:42:52PM -0700, Simon Glass wrote:
> At present the 'Index' column assumes there is only one digit. But on some
> devices (e.g. snow) there are a lot of regulators and GPIO banks. Adjust
> the output to allow for two digits without messing up the display.
> 
> Also capatalise the heading to match.
> 
> Fixes: 5197dafc42 (dm: core: Widen the dump tree to show more of the
> driver's name.)
> 
> Signed-off-by: Simon Glass 

Reviewed-by: Liviu Dudau 

Best regards,
Liviu

> ---
> 
>  drivers/core/dump.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/core/dump.c b/drivers/core/dump.c
> index 04217cbde87..8fbfd93fb5e 100644
> --- a/drivers/core/dump.c
> +++ b/drivers/core/dump.c
> @@ -16,7 +16,7 @@ static void show_devices(struct udevice *dev, int depth, 
> int last_flag)
>   struct udevice *child;
>  
>   /* print the first 20 characters to not break the tree-format. */
> - printf(" %-10.10s  %d  [ %c ]   %-20.20s  ", dev->uclass->uc_drv->name,
> + printf(" %-10.10s  %2d  [ %c ]   %-20.20s  ", dev->uclass->uc_drv->name,
>  dev_get_uclass_index(dev, NULL),
>  dev->flags & DM_FLAG_ACTIVATED ? '+' : ' ', dev->driver->name);
>  
> @@ -49,7 +49,7 @@ void dm_dump_all(void)
>  
>   root = dm_root();
>   if (root) {
> - printf(" Classindex  Probed  DriverName\n");
> + printf(" Class Index  Probed  Driver
> Name\n");
>   
> printf("---\n");
>   show_devices(root, -1, 0);
>   }
> -- 
> 2.20.0.rc1.387.gf8505762e3-goog
> 

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Re: [U-Boot] [PATCH v2] ARM: vexpress_*_defconfig: Enable CMD_UBI support

[Liviu Dudau]

On Tue, Nov 20, 2018 at 04:47:12PM -0200, Otavio Salvador wrote:
> This allow for convenient use of QEMU machine to test loading of UBI
> filesystem. There are a couple of changes made together of this which
> are required:
> 
>  1) The malloc must be at least 512 KiB to allow the use of UBI
> filesystem. We are going to enable it in a next patch.
> 
>  2) MTD_DEVICE must be enabled, otherwise we get missing symbols
> during the build
> 
> Following configs were change:
> 
>  - vexpress_aemv8a_dram_defconfig
>  - vexpress_aemv8a_juno_defconfig
>  - vexpress_aemv8a_semi_defconfig
>  - vexpress_ca15_tc2_defconfig
>  - vexpress_ca5x2_defconfig
>  - vexpress_ca9x4_defconfig
> 
> Signed-off-by: Otavio Salvador 

Acked-by: Liviu Dudau 

I don't have a git tree to send pull requests from, usually Linaro
(Linus?) handled these, so I need to know if you're OK with getting this
patch merged into U-Boot mainline.

Best regards,
Liviu

> ---
> 
> Changes in v2:
> - Add env size to the malloc size (Liviu Dudau)
> 
>  configs/vexpress_aemv8a_dram_defconfig | 2 ++
>  configs/vexpress_aemv8a_juno_defconfig | 2 ++
>  configs/vexpress_aemv8a_semi_defconfig | 2 ++
>  configs/vexpress_ca15_tc2_defconfig| 2 ++
>  configs/vexpress_ca5x2_defconfig   | 2 ++
>  configs/vexpress_ca9x4_defconfig   | 2 ++
>  include/configs/vexpress_common.h  | 2 +-
>  7 files changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/configs/vexpress_aemv8a_dram_defconfig 
> b/configs/vexpress_aemv8a_dram_defconfig
> index 9848f96293..0f0f138303 100644
> --- a/configs/vexpress_aemv8a_dram_defconfig
> +++ b/configs/vexpress_aemv8a_dram_defconfig
> @@ -23,12 +23,14 @@ CONFIG_CMD_ARMFLASH=y
>  # CONFIG_CMD_NFS is not set
>  CONFIG_CMD_CACHE=y
>  # CONFIG_CMD_MISC is not set
> +CONFIG_CMD_UBI=y
>  # CONFIG_ISO_PARTITION is not set
>  # CONFIG_EFI_PARTITION is not set
>  CONFIG_ENV_IS_IN_FLASH=y
>  CONFIG_DM=y
>  # CONFIG_MMC is not set
>  CONFIG_MTD_NOR_FLASH=y
> +CONFIG_MTD_DEVICE=y
>  CONFIG_FLASH_CFI_DRIVER=y
>  CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
>  CONFIG_SYS_FLASH_PROTECTION=y
> diff --git a/configs/vexpress_aemv8a_juno_defconfig 
> b/configs/vexpress_aemv8a_juno_defconfig
> index ef38915955..ed611fea7c 100644
> --- a/configs/vexpress_aemv8a_juno_defconfig
> +++ b/configs/vexpress_aemv8a_juno_defconfig
> @@ -23,12 +23,14 @@ CONFIG_CMD_ARMFLASH=y
>  # CONFIG_CMD_NFS is not set
>  CONFIG_CMD_CACHE=y
>  # CONFIG_CMD_MISC is not set
> +CONFIG_CMD_UBI=y
>  # CONFIG_ISO_PARTITION is not set
>  # CONFIG_EFI_PARTITION is not set
>  CONFIG_ENV_IS_IN_FLASH=y
>  CONFIG_DM=y
>  # CONFIG_MMC is not set
>  CONFIG_MTD_NOR_FLASH=y
> +CONFIG_MTD_DEVICE=y
>  CONFIG_FLASH_CFI_DRIVER=y
>  CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
>  CONFIG_SYS_FLASH_PROTECTION=y
> diff --git a/configs/vexpress_aemv8a_semi_defconfig 
> b/configs/vexpress_aemv8a_semi_defconfig
> index a4d1233cd5..0b3bb65ee6 100644
> --- a/configs/vexpress_aemv8a_semi_defconfig
> +++ b/configs/vexpress_aemv8a_semi_defconfig
> @@ -23,12 +23,14 @@ CONFIG_CMD_ARMFLASH=y
>  # CONFIG_CMD_NFS is not set
>  CONFIG_CMD_CACHE=y
>  # CONFIG_CMD_MISC is not set
> +CONFIG_CMD_UBI=y
>  # CONFIG_ISO_PARTITION is not set
>  # CONFIG_EFI_PARTITION is not set
>  CONFIG_ENV_IS_IN_FLASH=y
>  CONFIG_DM=y
>  # CONFIG_MMC is not set
>  CONFIG_MTD_NOR_FLASH=y
> +CONFIG_MTD_DEVICE=y
>  CONFIG_FLASH_CFI_DRIVER=y
>  CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
>  CONFIG_SYS_FLASH_PROTECTION=y
> diff --git a/configs/vexpress_ca15_tc2_defconfig 
> b/configs/vexpress_ca15_tc2_defconfig
> index f4d555be48..cabc0c4577 100644
> --- a/configs/vexpress_ca15_tc2_defconfig
> +++ b/configs/vexpress_ca15_tc2_defconfig
> @@ -18,8 +18,10 @@ CONFIG_CMD_MMC=y
>  # CONFIG_CMD_SETEXPR is not set
>  # CONFIG_CMD_NFS is not set
>  # CONFIG_CMD_MISC is not set
> +CONFIG_CMD_UBI=y
>  CONFIG_ENV_IS_IN_FLASH=y
>  CONFIG_MTD_NOR_FLASH=y
> +CONFIG_MTD_DEVICE=y
>  CONFIG_FLASH_CFI_DRIVER=y
>  CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
>  CONFIG_SYS_FLASH_PROTECTION=y
> diff --git a/configs/vexpress_ca5x2_defconfig 
> b/configs/vexpress_ca5x2_defconfig
> index bdacc60c2c..dc4411d6f5 100644
> --- a/configs/vexpress_ca5x2_defconfig
> +++ b/configs/vexpress_ca5x2_defconfig
> @@ -17,8 +17,10 @@ CONFIG_CMD_MMC=y
>  # CONFIG_CMD_SETEXPR is not set
>  # CONFIG_CMD_NFS is not set
>  # CONFIG_CMD_MISC is not set
> +CONFIG_CMD_UBI=y
>  CONFIG_ENV_IS_IN_FLASH=y
>  CONFIG_MTD_NOR_FLASH=y
> +CONFIG_MTD_DEVICE=y
>  CONFIG_FLASH_CFI_DRIVER=y
>  CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
>  CONFIG_SYS_FLASH_PROTECTION=y
> diff --git a/configs/vexpress_ca9x4_defconfig 
> b/c

Re: [U-Boot] [PATCH] ARM: vexpress_*: Enable CMD_UBI support

[Liviu Dudau]

Hi Otavio,

On Sun, Nov 18, 2018 at 06:48:07PM -0200, Otavio Salvador wrote:
> This allow for convenient use of QEMU machine to test loading of UBI
> filesystem. There are a couple of changes made together of this which
> are required:
> 
>  1) The malloc must be at least 512 KiB to allow the use of UBI
> filesystem. We are going to enable it in a next patch.
> 
>  2) MTD_DEVICE must be enabled, otherwise we get missing symbols
> during the build
> 
> Following configs were change:
> 
>  - vexpress_aemv8a_dram_defconfig
>  - vexpress_aemv8a_juno_defconfig
>  - vexpress_aemv8a_semi_defconfig
>  - vexpress_ca15_tc2_defconfig
>  - vexpress_ca5x2_defconfig
>  - vexpress_ca9x4_defconfig
> 
> Signed-off-by: Otavio Salvador 
> ---
> 
>  configs/vexpress_aemv8a_dram_defconfig | 2 ++
>  configs/vexpress_aemv8a_juno_defconfig | 2 ++
>  configs/vexpress_aemv8a_semi_defconfig | 2 ++
>  configs/vexpress_ca15_tc2_defconfig| 2 ++
>  configs/vexpress_ca5x2_defconfig   | 2 ++
>  configs/vexpress_ca9x4_defconfig   | 2 ++
>  include/configs/vexpress_common.h  | 2 +-
>  7 files changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/configs/vexpress_aemv8a_dram_defconfig 
> b/configs/vexpress_aemv8a_dram_defconfig
> index 9848f96293..0f0f138303 100644
> --- a/configs/vexpress_aemv8a_dram_defconfig
> +++ b/configs/vexpress_aemv8a_dram_defconfig
> @@ -23,12 +23,14 @@ CONFIG_CMD_ARMFLASH=y
>  # CONFIG_CMD_NFS is not set
>  CONFIG_CMD_CACHE=y
>  # CONFIG_CMD_MISC is not set
> +CONFIG_CMD_UBI=y
>  # CONFIG_ISO_PARTITION is not set
>  # CONFIG_EFI_PARTITION is not set
>  CONFIG_ENV_IS_IN_FLASH=y
>  CONFIG_DM=y
>  # CONFIG_MMC is not set
>  CONFIG_MTD_NOR_FLASH=y
> +CONFIG_MTD_DEVICE=y
>  CONFIG_FLASH_CFI_DRIVER=y
>  CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
>  CONFIG_SYS_FLASH_PROTECTION=y
> diff --git a/configs/vexpress_aemv8a_juno_defconfig 
> b/configs/vexpress_aemv8a_juno_defconfig
> index ef38915955..ed611fea7c 100644
> --- a/configs/vexpress_aemv8a_juno_defconfig
> +++ b/configs/vexpress_aemv8a_juno_defconfig
> @@ -23,12 +23,14 @@ CONFIG_CMD_ARMFLASH=y
>  # CONFIG_CMD_NFS is not set
>  CONFIG_CMD_CACHE=y
>  # CONFIG_CMD_MISC is not set
> +CONFIG_CMD_UBI=y
>  # CONFIG_ISO_PARTITION is not set
>  # CONFIG_EFI_PARTITION is not set
>  CONFIG_ENV_IS_IN_FLASH=y
>  CONFIG_DM=y
>  # CONFIG_MMC is not set
>  CONFIG_MTD_NOR_FLASH=y
> +CONFIG_MTD_DEVICE=y
>  CONFIG_FLASH_CFI_DRIVER=y
>  CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
>  CONFIG_SYS_FLASH_PROTECTION=y
> diff --git a/configs/vexpress_aemv8a_semi_defconfig 
> b/configs/vexpress_aemv8a_semi_defconfig
> index a4d1233cd5..0b3bb65ee6 100644
> --- a/configs/vexpress_aemv8a_semi_defconfig
> +++ b/configs/vexpress_aemv8a_semi_defconfig
> @@ -23,12 +23,14 @@ CONFIG_CMD_ARMFLASH=y
>  # CONFIG_CMD_NFS is not set
>  CONFIG_CMD_CACHE=y
>  # CONFIG_CMD_MISC is not set
> +CONFIG_CMD_UBI=y
>  # CONFIG_ISO_PARTITION is not set
>  # CONFIG_EFI_PARTITION is not set
>  CONFIG_ENV_IS_IN_FLASH=y
>  CONFIG_DM=y
>  # CONFIG_MMC is not set
>  CONFIG_MTD_NOR_FLASH=y
> +CONFIG_MTD_DEVICE=y
>  CONFIG_FLASH_CFI_DRIVER=y
>  CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
>  CONFIG_SYS_FLASH_PROTECTION=y
> diff --git a/configs/vexpress_ca15_tc2_defconfig 
> b/configs/vexpress_ca15_tc2_defconfig
> index f4d555be48..cabc0c4577 100644
> --- a/configs/vexpress_ca15_tc2_defconfig
> +++ b/configs/vexpress_ca15_tc2_defconfig
> @@ -18,8 +18,10 @@ CONFIG_CMD_MMC=y
>  # CONFIG_CMD_SETEXPR is not set
>  # CONFIG_CMD_NFS is not set
>  # CONFIG_CMD_MISC is not set
> +CONFIG_CMD_UBI=y
>  CONFIG_ENV_IS_IN_FLASH=y
>  CONFIG_MTD_NOR_FLASH=y
> +CONFIG_MTD_DEVICE=y
>  CONFIG_FLASH_CFI_DRIVER=y
>  CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
>  CONFIG_SYS_FLASH_PROTECTION=y
> diff --git a/configs/vexpress_ca5x2_defconfig 
> b/configs/vexpress_ca5x2_defconfig
> index bdacc60c2c..dc4411d6f5 100644
> --- a/configs/vexpress_ca5x2_defconfig
> +++ b/configs/vexpress_ca5x2_defconfig
> @@ -17,8 +17,10 @@ CONFIG_CMD_MMC=y
>  # CONFIG_CMD_SETEXPR is not set
>  # CONFIG_CMD_NFS is not set
>  # CONFIG_CMD_MISC is not set
> +CONFIG_CMD_UBI=y
>  CONFIG_ENV_IS_IN_FLASH=y
>  CONFIG_MTD_NOR_FLASH=y
> +CONFIG_MTD_DEVICE=y
>  CONFIG_FLASH_CFI_DRIVER=y
>  CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
>  CONFIG_SYS_FLASH_PROTECTION=y
> diff --git a/configs/vexpress_ca9x4_defconfig 
> b/configs/vexpress_ca9x4_defconfig
> index 7a90831918..9390cf61d1 100644
> --- a/configs/vexpress_ca9x4_defconfig
> +++ b/configs/vexpress_ca9x4_defconfig
> @@ -17,8 +17,10 @@ CONFIG_CMD_MMC=y
>  # CONFIG_CMD_SETEXPR is not set
>  # CONFIG_CMD_NFS is not set
>  # CONFIG_CMD_MISC is not set
> +CONFIG_CMD_UBI=y
>  CONFIG_ENV_IS_IN_FLASH=y
>  CONFIG_MTD_NOR_FLASH=y
> +CONFIG_MTD_DEVICE=y
>  CONFIG_FLASH_CFI_DRIVER=y
>  CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
>  CONFIG_SYS_FLASH_PROTECTION=y
> diff --git a/include/configs/vexpress_common.h 
> b/include/configs/vexpress_common.h
> index 267b230fda..f277e80578 100644
> --- a/include/configs/vexpress_common.h
> +++ 

[U-Boot] [PATCH v2] dm: core: Widen the dump tree to show more of the driver's name.

[Liviu Dudau]

With drivers that have prefix names that are quite long (like
'versatile_') it is useful to have a wider column for the driver's
name when dumping the device driver tree.

Also update the tests to take into account the wider output format.

Signed-off-by: Liviu Dudau 
Reviewed-by: Simon Glass 
---

Changelog:
 - v2: merged the patch introducing the wider output with the patch
   updating the tests so that they can be applied in one go.

 drivers/core/dump.c|  8 
 test/py/tests/test_bind.py | 28 ++--
 2 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/core/dump.c b/drivers/core/dump.c
index d7cdb1475d..9d59fa90b2 100644
--- a/drivers/core/dump.c
+++ b/drivers/core/dump.c
@@ -15,8 +15,8 @@ static void show_devices(struct udevice *dev, int depth, int 
last_flag)
int i, is_last;
struct udevice *child;
 
-   /* print the first 11 characters to not break the tree-format. */
-   printf(" %-10.10s  %d  [ %c ]   %-10.10s  ", dev->uclass->uc_drv->name,
+   /* print the first 20 characters to not break the tree-format. */
+   printf(" %-10.10s  %d  [ %c ]   %-20.20s  ", dev->uclass->uc_drv->name,
   dev_get_uclass_index(dev, NULL),
   dev->flags & DM_FLAG_ACTIVATED ? '+' : ' ', dev->driver->name);
 
@@ -49,8 +49,8 @@ void dm_dump_all(void)
 
root = dm_root();
if (root) {
-   printf(" Classindex  Probed  Driver  Name\n");
-   printf("-\n");
+   printf(" Classindex  Probed  DriverName\n");
+   
printf("---\n");
show_devices(root, -1, 0);
}
 }
diff --git a/test/py/tests/test_bind.py b/test/py/tests/test_bind.py
index f21b7059ea..dee3fee566 100644
--- a/test/py/tests/test_bind.py
+++ b/test/py/tests/test_bind.py
@@ -13,7 +13,7 @@ def in_tree(response, name, uclass, drv, depth, last_child):
else:
leaf = leaf + '`'
leaf = leaf + '-- ' + name
-   line = ' *{:10.10}  [0-9]*  \[ [ +] \]   {:10.10}  {}$'.format(uclass, 
drv,leaf)
+   line = ' *{:10.10}  [0-9]*  \[ [ +] \]   {:20.20}  {}$'.format(uclass, 
drv, leaf)
prog = re.compile(line)
for l in lines:
if prog.match(l):
@@ -28,31 +28,31 @@ def test_bind_unbind_with_node(u_boot_console):
response = u_boot_console.run_command("bind  /bind-test 
generic_simple_bus")
assert response == ''
tree = u_boot_console.run_command("dm tree")
-   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple", 0, 
True)
+   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple_bus", 
0, True)
assert in_tree(tree, "bind-test-child1", "phy", "phy_sandbox", 1, False)
-   assert in_tree(tree, "bind-test-child2", "simple_bus", 
"generic_simple", 1, True)
+   assert in_tree(tree, "bind-test-child2", "simple_bus", 
"generic_simple_bus", 1, True)
 
#Unbind child #1. No error expected and all devices should be there 
except for bind-test-child1
response = u_boot_console.run_command("unbind  
/bind-test/bind-test-child1")
assert response == ''
tree = u_boot_console.run_command("dm tree")
-   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple", 0, 
True)
+   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple_bus", 
0, True)
assert "bind-test-child1" not in tree
-   assert in_tree(tree, "bind-test-child2", "simple_bus", 
"generic_simple", 1, True)
+   assert in_tree(tree, "bind-test-child2", "simple_bus", 
"generic_simple_bus", 1, True)
 
#bind child #1. No error expected and all devices should be there
response = u_boot_console.run_command("bind  
/bind-test/bind-test-child1 phy_sandbox")
assert response == ''
tree = u_boot_console.run_command("dm tree")
-   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple", 0, 
True)
+   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple_bus", 
0, True)
assert in_tree(tree, "bind-test-child1", "phy", "phy_sandbox", 1, True)
-   assert in_tree(tree, "bind-test-child2", "simple_bus", 
"generic_simple", 1, False)
+   assert in_tree(tree, "bind-test-child2", "simple_bus", 
"generic_

[U-Boot] [PATCH v2] dm: core: Widen the dump tree to show more of the driver's name.

[Liviu Dudau]

From: Liviu Dudau 

With drivers that have prefix names that are quite long (like
'versatile_') it is useful to have a wider column for the driver's
name when dumping the device driver tree.

Also update the tests to take into account the wider output format.

Signed-off-by: Liviu Dudau 
Reviewed-by: Simon Glass 
---
(Looks like foss.arm.com server is having troubles delivering emails,
this patch is stuck for a while in the send queue, so I'm using my private 
email)

Changelog:
 - v2: merged the patch introducing the wider output with the patch
   updating the tests so that they can be applied in one go.

 drivers/core/dump.c|  8 
 test/py/tests/test_bind.py | 28 ++--
 2 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/core/dump.c b/drivers/core/dump.c
index d7cdb1475d..9d59fa90b2 100644
--- a/drivers/core/dump.c
+++ b/drivers/core/dump.c
@@ -15,8 +15,8 @@ static void show_devices(struct udevice *dev, int depth, int 
last_flag)
int i, is_last;
struct udevice *child;
 
-   /* print the first 11 characters to not break the tree-format. */
-   printf(" %-10.10s  %d  [ %c ]   %-10.10s  ", dev->uclass->uc_drv->name,
+   /* print the first 20 characters to not break the tree-format. */
+   printf(" %-10.10s  %d  [ %c ]   %-20.20s  ", dev->uclass->uc_drv->name,
   dev_get_uclass_index(dev, NULL),
   dev->flags & DM_FLAG_ACTIVATED ? '+' : ' ', dev->driver->name);
 
@@ -49,8 +49,8 @@ void dm_dump_all(void)
 
root = dm_root();
if (root) {
-   printf(" Classindex  Probed  Driver  Name\n");
-   printf("-\n");
+   printf(" Classindex  Probed  DriverName\n");
+   
printf("---\n");
show_devices(root, -1, 0);
}
 }
diff --git a/test/py/tests/test_bind.py b/test/py/tests/test_bind.py
index f21b7059ea..dee3fee566 100644
--- a/test/py/tests/test_bind.py
+++ b/test/py/tests/test_bind.py
@@ -13,7 +13,7 @@ def in_tree(response, name, uclass, drv, depth, last_child):
else:
leaf = leaf + '`'
leaf = leaf + '-- ' + name
-   line = ' *{:10.10}  [0-9]*  \[ [ +] \]   {:10.10}  {}$'.format(uclass, 
drv,leaf)
+   line = ' *{:10.10}  [0-9]*  \[ [ +] \]   {:20.20}  {}$'.format(uclass, 
drv, leaf)
prog = re.compile(line)
for l in lines:
if prog.match(l):
@@ -28,31 +28,31 @@ def test_bind_unbind_with_node(u_boot_console):
response = u_boot_console.run_command("bind  /bind-test 
generic_simple_bus")
assert response == ''
tree = u_boot_console.run_command("dm tree")
-   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple", 0, 
True)
+   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple_bus", 
0, True)
assert in_tree(tree, "bind-test-child1", "phy", "phy_sandbox", 1, False)
-   assert in_tree(tree, "bind-test-child2", "simple_bus", 
"generic_simple", 1, True)
+   assert in_tree(tree, "bind-test-child2", "simple_bus", 
"generic_simple_bus", 1, True)
 
#Unbind child #1. No error expected and all devices should be there 
except for bind-test-child1
response = u_boot_console.run_command("unbind  
/bind-test/bind-test-child1")
assert response == ''
tree = u_boot_console.run_command("dm tree")
-   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple", 0, 
True)
+   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple_bus", 
0, True)
assert "bind-test-child1" not in tree
-   assert in_tree(tree, "bind-test-child2", "simple_bus", 
"generic_simple", 1, True)
+   assert in_tree(tree, "bind-test-child2", "simple_bus", 
"generic_simple_bus", 1, True)
 
#bind child #1. No error expected and all devices should be there
response = u_boot_console.run_command("bind  
/bind-test/bind-test-child1 phy_sandbox")
assert response == ''
tree = u_boot_console.run_command("dm tree")
-   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple", 0, 
True)
+   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple_bus", 
0, True)
assert in_tree(tree, "bind-test-child1", "phy", "phy_sandbox", 1, True)
-   assert in_tree(tree, "bind-test-chil

Re: [U-Boot] [PATCH] i2c: fix: Add support for the Arm's Versatile Express I2C controller

[Liviu Dudau]

On Thu, Oct 11, 2018 at 07:26:33AM +0200, Heiko Schocher wrote:
> accidentially while fixing merge errors for patch:
> https://lists.denx.de/pipermail/u-boot/2018-September/342278.html
> 
> missed to add files:
> 
> MAINTAINERS
> drivers/i2c/Kconfig
> drivers/i2c/Makefile
> 
> add them with this patch.
> 
> Signed-off-by: Heiko Schocher 

Acked-by: Liviu Dudau 

> ---
> 
>  MAINTAINERS  | 1 +
>  drivers/i2c/Kconfig  | 7 +++
>  drivers/i2c/Makefile | 1 +
>  3 files changed, 9 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index ace7d9a4b6..cc71a8f6be 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -453,6 +453,7 @@ M:Liviu Dudau 
>  S:   Supported
>  T:   git git://github.com/ARM-software/u-boot.git
>  F:   drivers/video/mali_dp.c
> +F:   drivers/i2c/i2c-versatile.c
>  
>  MICROBLAZE
>  M:   Michal Simek 
> diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
> index ae3b501555..1ef22e6bcd 100644
> --- a/drivers/i2c/Kconfig
> +++ b/drivers/i2c/Kconfig
> @@ -416,6 +416,13 @@ config SYS_I2C_UNIPHIER_F
> Support for UniPhier FIFO-builtin I2C controller driver.
> This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
>  
> +config SYS_I2C_VERSATILE
> + bool "Arm Ltd Versatile I2C bus driver"
> + depends on DM_I2C && (TARGET_VEXPRESS_CA15_TC2 || 
> TARGET_VEXPRESS64_JUNO)
> + help
> +   Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
> +   controller is present in the development boards manufactured by Arm 
> Ltd.
> +
>  config SYS_I2C_MVTWSI
>   bool "Marvell I2C driver"
>   depends on DM_I2C
> diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
> index f2cbe78c53..d3637bcd8d 100644
> --- a/drivers/i2c/Makefile
> +++ b/drivers/i2c/Makefile
> @@ -36,6 +36,7 @@ obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o
>  obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
>  obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
>  obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
> +obj-$(CONFIG_SYS_I2C_VERSATILE) += i2c-versatile.o
>  obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
>  obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o
>  
> -- 
> 2.14.4
> 

-- 

| I would like to |
| fix the world,  |
| but they're not |
| giving me the   |
 \ source code!  /
  ---
¯\_(ツ)_/¯
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] tests/test_bind.py: Update test to match the wider 'dm tree' output

[Liviu Dudau]

Commit ("dm: core: Widen the dump tree to show more of the driver's
name") has widened the field reserved for the name of a driver, so
we need to update the test to match.

Signed-off-by: Liviu Dudau 
---
 test/py/tests/test_bind.py | 28 ++--
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/test/py/tests/test_bind.py b/test/py/tests/test_bind.py
index f21b7059ea..dee3fee566 100644
--- a/test/py/tests/test_bind.py
+++ b/test/py/tests/test_bind.py
@@ -13,7 +13,7 @@ def in_tree(response, name, uclass, drv, depth, last_child):
else:
leaf = leaf + '`'
leaf = leaf + '-- ' + name
-   line = ' *{:10.10}  [0-9]*  \[ [ +] \]   {:10.10}  {}$'.format(uclass, 
drv,leaf)
+   line = ' *{:10.10}  [0-9]*  \[ [ +] \]   {:20.20}  {}$'.format(uclass, 
drv, leaf)
prog = re.compile(line)
for l in lines:
if prog.match(l):
@@ -28,31 +28,31 @@ def test_bind_unbind_with_node(u_boot_console):
response = u_boot_console.run_command("bind  /bind-test 
generic_simple_bus")
assert response == ''
tree = u_boot_console.run_command("dm tree")
-   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple", 0, 
True)
+   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple_bus", 
0, True)
assert in_tree(tree, "bind-test-child1", "phy", "phy_sandbox", 1, False)
-   assert in_tree(tree, "bind-test-child2", "simple_bus", 
"generic_simple", 1, True)
+   assert in_tree(tree, "bind-test-child2", "simple_bus", 
"generic_simple_bus", 1, True)
 
#Unbind child #1. No error expected and all devices should be there 
except for bind-test-child1
response = u_boot_console.run_command("unbind  
/bind-test/bind-test-child1")
assert response == ''
tree = u_boot_console.run_command("dm tree")
-   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple", 0, 
True)
+   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple_bus", 
0, True)
assert "bind-test-child1" not in tree
-   assert in_tree(tree, "bind-test-child2", "simple_bus", 
"generic_simple", 1, True)
+   assert in_tree(tree, "bind-test-child2", "simple_bus", 
"generic_simple_bus", 1, True)
 
#bind child #1. No error expected and all devices should be there
response = u_boot_console.run_command("bind  
/bind-test/bind-test-child1 phy_sandbox")
assert response == ''
tree = u_boot_console.run_command("dm tree")
-   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple", 0, 
True)
+   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple_bus", 
0, True)
assert in_tree(tree, "bind-test-child1", "phy", "phy_sandbox", 1, True)
-   assert in_tree(tree, "bind-test-child2", "simple_bus", 
"generic_simple", 1, False)
+   assert in_tree(tree, "bind-test-child2", "simple_bus", 
"generic_simple_bus", 1, False)
 
#Unbind child #2. No error expected and all devices should be there 
except for bind-test-child2
response = u_boot_console.run_command("unbind  
/bind-test/bind-test-child2")
assert response == ''
tree = u_boot_console.run_command("dm tree")
-   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple", 0, 
True)
+   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple_bus", 
0, True)
assert in_tree(tree, "bind-test-child1", "phy", "phy_sandbox", 1, True)
assert "bind-test-child2" not in tree
 
@@ -61,9 +61,9 @@ def test_bind_unbind_with_node(u_boot_console):
response = u_boot_console.run_command("bind /bind-test/bind-test-child2 
generic_simple_bus")
assert response == ''
tree = u_boot_console.run_command("dm tree")
-   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple", 0, 
True)
+   assert in_tree(tree, "bind-test", "simple_bus", "generic_simple_bus", 
0, True)
assert in_tree(tree, "bind-test-child1", "phy", "phy_sandbox", 1, False)
-   assert in_tree(tree, "bind-test-child2", "simple_bus", 
"generic_simple", 1, True)
+   assert in_tree(tree, "bind-test-child2", "simple_bus", 
"ge

Re: [U-Boot] [PATCH] dm: core: Widen the dump tree to show more of the driver's name.

[Liviu Dudau]

On Tue, Oct 02, 2018 at 04:22:25AM -0700, Simon Glass wrote:
> Hi Liviu,
> 
> On 2 October 2018 at 03:46, Liviu Dudau  wrote:
> > On Fri, Sep 28, 2018 at 04:14:12PM -0600, Simon Glass wrote:
> >> Hi,
> >
> > Hi Simon,
> >
> >>
> >> On 17 September 2018 at 20:06, Simon Glass  wrote:
> >> > On 17 September 2018 at 10:57, Liviu Dudau  
> >> > wrote:
> >> >> With drivers that have prefix names that are quite long (like
> >> >> 'versatile_') it is useful to have a wider column for the driver's
> >> >> name when dumping the device driver tree.
> >> >>
> >> >> Signed-off-by: Liviu Dudau 
> >> >> ---
> >> >>  drivers/core/dump.c | 8 
> >> >>  1 file changed, 4 insertions(+), 4 deletions(-)
> >> >
> >> > Reviewed-by: Simon Glass 
> >>
> >> Unfortunately this seems to break some tests (make tests). Please can
> >> you take a look?
> >
> > I've had a go at trying to run 'make tests' on my machine but things
> > fail miserably for me. Attached is the output of the command. U-Boot is
> > v2018.11-rc1 plus my remaining patches that have not yet been merged.
> >
> > It looks to me like the 'sandbox' board (or defconfig) needs some
> > updating? Please advise!
> 
> I cannot explain your build log - it looks completely wrong.
> 
> Can you try:
> 
> make O=sandbox sandbox_defconfig
> make O=sandbox
> 
> ?
> 
> Maybe try 'make mrproper' first?

I've done that before.

> 
> But still, the errors seems to make no sense. E.g.
> CONFIG_SANDBOX_SPI_MAX_BUS is defined in a config file.

I think I have fixed the issue. I believe it was due to some stray
include/config.mk file that was a leftover from the times I switched to
an old Exynos tree trying to update an SMDK4422 board.

I can now see the relevant errors and I will come up with a patch.

Many thanks,
Liviu

> 
> Also what gcc version are you using on your computer?
> 
> Regards,
> Simon

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Re: [U-Boot] clk: Add support for Arm's Versatile Express OSC clock generators

[Liviu Dudau]

On Mon, Oct 01, 2018 at 11:26:37AM -0400, Tom Rini wrote:
> On Mon, Oct 01, 2018 at 04:16:45PM +0100, Liviu Dudau wrote:
> > On Mon, Oct 01, 2018 at 07:36:12AM -0400, Tom Rini wrote:
> > > On Mon, Oct 01, 2018 at 10:20:22AM +0100, Liviu Dudau wrote:
> > > > On Sun, Sep 30, 2018 at 03:24:56PM -0400, Tom Rini wrote:
> > > > > On Mon, Sep 17, 2018 at 05:50:00PM +0100, Liviu Dudau wrote:
> > > > > 
> > > > > > The Arm Versatile Express and Juno development boards contain an
> > > > > > OSC clock generator that can be accessed through the Versatile
> > > > > > Express config bus. The generators are quite often being controlled
> > > > > > by some MCU and the config bus offers a uniform way of exposing 
> > > > > > them.
> > > > > > 
> > > > > > Signed-off-by: Liviu Dudau 
> > > > > > Reviewed-by: Heiko Schocher 
> > > > > 
> > > > > Applied to u-boot/master, thanks!
> > > > 
> > > > Thanks! The MAINTAINERS entry will get applied at a different time, I
> > > > guess? (I know there is some implicit order there, with the
> > > > vexpress_config.c driver introducing the entry, but the OSC driver is
> > > > not useful without that driver)
> > > 
> > > I don't see a patch that update the MAINTAINERS file right now, can you
> > > please resend it?  Thanks!
> > 
> > Apologies, I was under the impression that I have sent the v2 for this
> > patch as well, which had the MAINTAINERS update.
> > 
> > Do you want me to send a patch only for the MAINTAINERS update? Should
> > that patch add the VExpress config bus entry as well (will conflict with
> > v2 of that patch anyway)?
> 
> Ah, OK, I see now.  Let me also bring in Linus Walleij on this too.
> U-Boot has split the MAINTAINERS file up for a while now and stuff like
> these platform specific drivers should get popped into
> board/armltd/vexpress/MAINTAINERS or board/armltd/vexpress64/MAINTAINERS
> (I'd also be open, I suppose, to creating board/armltd/MAINTAINERS if
> it's more sensical, but... could we squash vexpress64 into the main
> vexpress directory or does that make no sense?).  And, oops, I see that
> Linus should have been cc'd on this patch and I should wait for him to
> review the others[1] too.

I'm a bit confused on how this would work. The MAINTAINERS entry I'm
talking about is for the OSC clk driver. Does this mean I will have to
update both board files with the same info? I thought board specific
MAINTAINERS files are for specifying who's looking over the board
functionality overall?

Best regards,
Liviu


> 
> [1]: https://patchwork.ozlabs.org/project/uboot/list/?submitter=67396
> 
> -- 
> Tom



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Re: [U-Boot] [PATCH] dm: core: Widen the dump tree to show more of the driver's name.

[Liviu Dudau]

On Fri, Sep 28, 2018 at 04:14:12PM -0600, Simon Glass wrote:
> Hi,

Hi Simon,

> 
> On 17 September 2018 at 20:06, Simon Glass  wrote:
> > On 17 September 2018 at 10:57, Liviu Dudau  wrote:
> >> With drivers that have prefix names that are quite long (like
> >> 'versatile_') it is useful to have a wider column for the driver's
> >> name when dumping the device driver tree.
> >>
> >> Signed-off-by: Liviu Dudau 
> >> ---
> >>  drivers/core/dump.c | 8 
> >>  1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > Reviewed-by: Simon Glass 
> 
> Unfortunately this seems to break some tests (make tests). Please can
> you take a look?

I've had a go at trying to run 'make tests' on my machine but things
fail miserably for me. Attached is the output of the command. U-Boot is
v2018.11-rc1 plus my remaining patches that have not yet been merged.

It looks to me like the 'sandbox' board (or defconfig) needs some
updating? Please advise!

Best regards,
Liviu

> 
> Regards,
> Simon

-- 

| I would like to |
| fix the world,  |
| but they're not |
| giving me the   |
 \ source code!  /
  ---
¯\_(ツ)_/¯
./test/run
+make O=/work/repositories/u-boot/build-sandbox -s sandbox_defconfig
+make O=/work/repositories/u-boot/build-sandbox -s -j8
In file included from ../arch/sandbox/cpu/os.c:26:
../arch/sandbox/include/asm/state.h:94:30: error: ‘CONFIG_SANDBOX_SPI_MAX_BUS’ 
undeclared here (not in a function); did you mean ‘CONFIG_SANDBOX_SPI’?
  struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS]
  ^~
  CONFIG_SANDBOX_SPI
../arch/sandbox/include/asm/state.h:95:7: error: ‘CONFIG_SANDBOX_SPI_MAX_CS’ 
undeclared here (not in a function); did you mean ‘CONFIG_SANDBOX_SPI’?
  [CONFIG_SANDBOX_SPI_MAX_CS];
   ^
   CONFIG_SANDBOX_SPI
../arch/sandbox/cpu/os.c: In function ‘os_parse_args’:
../arch/sandbox/cpu/os.c:217:43: error: ‘__u_boot_sandbox_option_start’ 
undeclared (first use in this function)
  struct sandbox_cmdline_option **sb_opt = __u_boot_sandbox_option_start;
   ^
../arch/sandbox/cpu/os.c:217:43: note: each undeclared identifier is reported 
only once for each function it appears in
../arch/sandbox/cpu/os.c:218:23: warning: implicit declaration of function 
‘__u_boot_sandbox_option_count’ [-Wimplicit-function-declaration]
  size_t num_options = __u_boot_sandbox_option_count();
   ^
In file included from ../include/common.h:49,
 from ../arch/sandbox/cpu/cpu.c:6:
../include/asm/global_data.h:108:58: warning: call-clobbered register used for 
global register variable
 #define DECLARE_GLOBAL_DATA_PTR  register volatile gd_t *gd asm ("r9")
  ^~
../include/dm/of.h:86:1: note: in expansion of macro ‘DECLARE_GLOBAL_DATA_PTR’
 DECLARE_GLOBAL_DATA_PTR;
 ^~~
make[3]: *** [../arch/sandbox/cpu/Makefile:20: arch/sandbox/cpu/os.o] Error 1
make[3]: *** Waiting for unfinished jobs
In file included from ../arch/sandbox/cpu/start.c:14:
../arch/sandbox/include/asm/state.h:94:30: error: ‘CONFIG_SANDBOX_SPI_MAX_BUS’ 
undeclared here (not in a function); did you mean ‘CONFIG_SANDBOX_SPI’?
  struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS]
  ^~
  CONFIG_SANDBOX_SPI
In file included from ../include/cros_ec.h:14,
 from ../board/sandbox/sandbox.c:7:
../include/asm/gpio.h:3:10: fatal error: asm/arch/gpio.h: No such file or 
directory
 #include 
  ^
compilation terminated.
In file included from ../arch/sandbox/cpu/state.c:10:
../arch/sandbox/include/asm/state.h:94:30: error: ‘CONFIG_SANDBOX_SPI_MAX_BUS’ 
undeclared here (not in a function); did you mean ‘CONFIG_SANDBOX_SPI’?
  struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS]
  ^~
  CONFIG_SANDBOX_SPI
make[3]: *** [../scripts/Makefile.build:279: board/sandbox/sandbox.o] Error 1
make[2]: *** [/work/repositories/u-boot/Makefile:1403: board/sandbox] Error 2
make[2]: *** Waiting for unfinished jobs
../arch/sandbox/include/asm/state.h:95:7: error: ‘CONFIG_SANDBOX_SPI_MAX_CS’ 
undeclared here (not in a function); did you mean ‘CONFIG_SANDBOX_SPI’?
  [CONFIG_SANDBOX_SPI_MAX_CS];
   ^
   CONFIG_SANDBOX_SPI
In file included from ../include/common.h:49,
 from ../arch/sandbox/cpu/start.c:6:
../include/asm/global_data.h:108:58: warning: call-clobbered register used for 
global register variable
 #define DECLARE_GLOBAL_DATA_PTR  register volatile gd_t *

Re: [U-Boot] clk: Add support for Arm's Versatile Express OSC clock generators

[Liviu Dudau]

On Mon, Oct 01, 2018 at 07:36:12AM -0400, Tom Rini wrote:
> On Mon, Oct 01, 2018 at 10:20:22AM +0100, Liviu Dudau wrote:
> > On Sun, Sep 30, 2018 at 03:24:56PM -0400, Tom Rini wrote:
> > > On Mon, Sep 17, 2018 at 05:50:00PM +0100, Liviu Dudau wrote:
> > > 
> > > > The Arm Versatile Express and Juno development boards contain an
> > > > OSC clock generator that can be accessed through the Versatile
> > > > Express config bus. The generators are quite often being controlled
> > > > by some MCU and the config bus offers a uniform way of exposing them.
> > > > 
> > > > Signed-off-by: Liviu Dudau 
> > > > Reviewed-by: Heiko Schocher 
> > > 
> > > Applied to u-boot/master, thanks!
> > 
> > Thanks! The MAINTAINERS entry will get applied at a different time, I
> > guess? (I know there is some implicit order there, with the
> > vexpress_config.c driver introducing the entry, but the OSC driver is
> > not useful without that driver)
> 
> I don't see a patch that update the MAINTAINERS file right now, can you
> please resend it?  Thanks!

Apologies, I was under the impression that I have sent the v2 for this
patch as well, which had the MAINTAINERS update.

Do you want me to send a patch only for the MAINTAINERS update? Should
that patch add the VExpress config bus entry as well (will conflict with
v2 of that patch anyway)?

Best regards,
Liviu

> 
> -- 
> Tom



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 \ source code!  /
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Re: [U-Boot] clk: Add support for Arm's Versatile Express OSC clock generators

[Liviu Dudau]

On Sun, Sep 30, 2018 at 03:24:56PM -0400, Tom Rini wrote:
> On Mon, Sep 17, 2018 at 05:50:00PM +0100, Liviu Dudau wrote:
> 
> > The Arm Versatile Express and Juno development boards contain an
> > OSC clock generator that can be accessed through the Versatile
> > Express config bus. The generators are quite often being controlled
> > by some MCU and the config bus offers a uniform way of exposing them.
> > 
> > Signed-off-by: Liviu Dudau 
> > Reviewed-by: Heiko Schocher 
> 
> Applied to u-boot/master, thanks!

Thanks! The MAINTAINERS entry will get applied at a different time, I
guess? (I know there is some implicit order there, with the
vexpress_config.c driver introducing the entry, but the OSC driver is
not useful without that driver)

Best regards,
Liviu

> 
> -- 
> Tom



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Re: [U-Boot] [PATCH v2] uclass: Use uclass_foreach_dev() macro instead of open coding

[Liviu Dudau]

On Fri, Sep 28, 2018 at 09:57:49AM -0600, Simon Glass wrote:
> On 28 September 2018 at 06:12, Liviu Dudau  wrote:
> > Use the uclass_foreach_dev() macro instead of the open coded version.
> >
> > Signed-off-by: Liviu Dudau 
> > ---
> > Changelog:
> >  - v2: Find more places where the open coded version exists and
> >replace them with the macro
> >
> >  drivers/core/dump.c   |  2 +-
> >  drivers/core/uclass.c | 18 +-
> >  2 files changed, 10 insertions(+), 10 deletions(-)
> 
> Reviewed-by: Simon Glass 
> 
> I wonder how you got that email address?!

Which one? Mine or yours?

Mine comes from the new setup that Arm has for dealing with FOSS, where
the email servers don't send the standard Arm disclaimer.

Best regards,
Liviu

> 
> - Simon

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[U-Boot] [PATCH v2] uclass: Use uclass_foreach_dev() macro instead of open coding

[Liviu Dudau]

Use the uclass_foreach_dev() macro instead of the open coded version.

Signed-off-by: Liviu Dudau 
---
Changelog:
 - v2: Find more places where the open coded version exists and
   replace them with the macro

 drivers/core/dump.c   |  2 +-
 drivers/core/uclass.c | 18 +-
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/core/dump.c b/drivers/core/dump.c
index d7cdb1475d..9068084404 100644
--- a/drivers/core/dump.c
+++ b/drivers/core/dump.c
@@ -89,7 +89,7 @@ void dm_dump_uclass(void)
printf("uclass %d: %s\n", id, uc->uc_drv->name);
if (list_empty(>dev_head))
continue;
-   list_for_each_entry(dev, >dev_head, uclass_node) {
+   uclass_foreach_dev(dev, uc) {
dm_display_line(dev, i);
i++;
}
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 3113d6a56b..d90bdde54e 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -180,7 +180,7 @@ int dev_get_uclass_index(struct udevice *dev, struct uclass 
**ucp)
if (list_empty(>dev_head))
return -ENODEV;
 
-   list_for_each_entry(iter, >dev_head, uclass_node) {
+   uclass_foreach_dev(iter, uc) {
if (iter == dev) {
if (ucp)
*ucp = uc;
@@ -205,7 +205,7 @@ int uclass_find_device(enum uclass_id id, int index, struct 
udevice **devp)
if (list_empty(>dev_head))
return -ENODEV;
 
-   list_for_each_entry(dev, >dev_head, uclass_node) {
+   uclass_foreach_dev(dev, uc) {
if (!index--) {
*devp = dev;
return 0;
@@ -259,7 +259,7 @@ int uclass_find_device_by_name(enum uclass_id id, const 
char *name,
if (ret)
return ret;
 
-   list_for_each_entry(dev, >dev_head, uclass_node) {
+   uclass_foreach_dev(dev, uc) {
if (!strncmp(dev->name, name, strlen(name))) {
*devp = dev;
return 0;
@@ -284,7 +284,7 @@ int uclass_find_device_by_seq(enum uclass_id id, int 
seq_or_req_seq,
if (ret)
return ret;
 
-   list_for_each_entry(dev, >dev_head, uclass_node) {
+   uclass_foreach_dev(dev, uc) {
debug("   - %d %d '%s'\n", dev->req_seq, dev->seq, dev->name);
if ((find_req_seq ? dev->req_seq : dev->seq) ==
seq_or_req_seq) {
@@ -312,7 +312,7 @@ int uclass_find_device_by_of_offset(enum uclass_id id, int 
node,
if (ret)
return ret;
 
-   list_for_each_entry(dev, >dev_head, uclass_node) {
+   uclass_foreach_dev(dev, uc) {
if (dev_of_offset(dev) == node) {
*devp = dev;
return 0;
@@ -337,7 +337,7 @@ int uclass_find_device_by_ofnode(enum uclass_id id, ofnode 
node,
if (ret)
return ret;
 
-   list_for_each_entry(dev, >dev_head, uclass_node) {
+   uclass_foreach_dev(dev, uc) {
log(LOGC_DM, LOGL_DEBUG_CONTENT, "  - checking %s\n",
dev->name);
if (ofnode_equal(dev_ofnode(dev), node)) {
@@ -372,7 +372,7 @@ static int uclass_find_device_by_phandle(enum uclass_id id,
if (ret)
return ret;
 
-   list_for_each_entry(dev, >dev_head, uclass_node) {
+   uclass_foreach_dev(dev, uc) {
uint phandle;
 
phandle = dev_read_phandle(dev);
@@ -399,7 +399,7 @@ int uclass_get_device_by_driver(enum uclass_id id,
if (ret)
return ret;
 
-   list_for_each_entry(dev, >dev_head, uclass_node) {
+   uclass_foreach_dev(dev, uc) {
if (dev->driver == find_drv)
return uclass_get_device_tail(dev, 0, devp);
}
@@ -499,7 +499,7 @@ int uclass_get_device_by_phandle_id(enum uclass_id id, uint 
phandle_id,
if (ret)
return ret;
 
-   list_for_each_entry(dev, >dev_head, uclass_node) {
+   uclass_foreach_dev(dev, uc) {
uint phandle;
 
phandle = dev_read_phandle(dev);
-- 
2.18.0

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[U-Boot] [PATCH v2] video: Add support for Arm's Mali Display Processors

[Liviu Dudau]

Add support for Arm Mali Display Processors DP500, DP550 and DP650.
Only one layer is being used to display the console or boot logo,
even if more layers are supported in the hardware.

Signed-off-by: Liviu Dudau 
---
Changelog:
  - v2: Added MAINTAINERS entry and fixed checkpatch warnings.

 MAINTAINERS |   6 +
 drivers/video/Kconfig   |   8 +
 drivers/video/Makefile  |   1 +
 drivers/video/mali_dp.c | 405 
 4 files changed, 420 insertions(+)
 create mode 100644 drivers/video/mali_dp.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 112e41d2c3..fe08365ca8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -449,6 +449,12 @@ F: cmd/log.c
 F: test/log/log_test.c
 F: test/py/tests/test_log.py
 
+MALI DISPLAY PROCESSORS
+M: Liviu Dudau 
+S: Supported
+T: git git://github.com/ARM-software/u-boot.git
+F: drivers/video/mali_dp.c
+
 MICROBLAZE
 M: Michal Simek 
 S: Maintained
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 5d932072a8..ccf7cf83ed 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -497,6 +497,14 @@ config VIDEO_FSL_DCU_MAX_FB_SIZE_MB
 
 source "drivers/video/rockchip/Kconfig"
 
+config VIDEO_ARM_MALIDP
+   bool "Enable Arm Mali Display Processor support"
+   depends on DM_VIDEO && OF_CONTROL
+   select VEXPRESS_CLK
+   help
+ This enables support for Arm Ltd Mali Display Processors from
+ the DP500, DP550 and DP650 family.
+
 config VIDEO_SANDBOX_SDL
bool "Enable sandbox video console using SDL"
depends on SANDBOX
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 4c130e179d..e19e6dad1f 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_NXP_TDA19988) += tda19988.o
 obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
 obj-$(CONFIG_S6E8AX0) += s6e8ax0.o
 obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o
+obj-$(CONFIG_VIDEO_ARM_MALIDP) += mali_dp.o
 obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o
 obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o
 obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
diff --git a/drivers/video/mali_dp.c b/drivers/video/mali_dp.c
new file mode 100644
index 00..71151a87aa
--- /dev/null
+++ b/drivers/video/mali_dp.c
@@ -0,0 +1,405 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016-2018 ARM Ltd.
+ * Author: Liviu Dudau 
+ *
+ */
+#define DEBUG
+#include 
+#include 
+#include 
+#ifdef CONFIG_DISPLAY
+#include 
+#endif
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define MALIDP_CORE_ID 0x0018
+#define MALIDP_REG_BG_COLOR0x0044
+#define MALIDP_LAYER_LV1   0x0100
+#define MALIDP_DC_STATUS   0xc000
+#define MALIDP_DC_CONTROL  0xc010
+#define MALIDP_DC_CFG_VALID0xc014
+
+/* offsets inside the modesetting register block */
+#define MALIDP_H_INTERVALS 0x
+#define MALIDP_V_INTERVALS 0x0004
+#define MALIDP_SYNC_CONTROL0x0008
+#define MALIDP_HV_ACTIVESIZE   0x000c
+#define MALIDP_OUTPUT_DEPTH0x001c
+
+/* offsets inside the layer register block */
+#define MALIDP_LAYER_FORMAT0x
+#define MALIDP_LAYER_CONTROL   0x0004
+#define MALIDP_LAYER_IN_SIZE   0x000c
+#define MALIDP_LAYER_CMP_SIZE  0x0010
+#define MALIDP_LAYER_STRIDE0x0018
+#define MALIDP_LAYER_PTR_LOW   0x0024
+#define MALIDP_LAYER_PTR_HIGH  0x0028
+
+/* offsets inside the IRQ control blocks */
+#define MALIDP_REG_MASKIRQ 0x0008
+#define MALIDP_REG_CLEARIRQ0x000c
+
+#define M1BITS 0x0001
+#define M2BITS 0x0003
+#define M4BITS 0x000f
+#define M8BITS 0x00ff
+#define M10BITS0x03ff
+#define M12BITS0x0fff
+#define M13BITS0x1fff
+#define M16BITS0x
+#define M17BITS0x1
+
+#define MALIDP_H_FRONTPORCH(x) (((x) & M12BITS) << 0)
+#define MALIDP_H_BACKPORCH(x)  (((x) & M10BITS) << 16)
+#define MALIDP_V_FRONTPORCH(x) (((x) & M12BITS) << 0)
+#define MALIDP_V_BACKPORCH(x)  (((x) & M8BITS) << 16)
+#define MALIDP_H_SYNCWIDTH(x)  (((x) & M10BITS) << 0)
+#define MALIDP_V_SYNCWIDTH(x)  (((x) & M8BITS) << 16)
+#define MALIDP_H_ACTIVE(x) (((x) & M13BITS) << 0)
+#define MALIDP_V_ACTIVE(x) (((x) & M13BITS) << 16)
+
+#define MALIDP_CMP_V_SIZE(x)   (((x) & M13BITS) << 16)
+#define MALIDP_CMP_H_SIZE(x)   (((x) & M13BITS) << 0)
+
+#define MALIDP_IN_V_SIZE(x)(((x) & M13BITS) << 16)
+#define MALIDP_IN_H_SIZE(x)(((x) & M13BITS) << 0)
+
+#define MALIDP_DC_CM_CONTROL(x)((x) & M1BITS) << 16, 1 << 16
+#define MALIDP_DC_STATUS_GET_CM(reg) (((reg) >> 16) & M1BITS)
+
+#define MALIDP_FORMAT_ARGB 0x08
+#define MALIDP_DEFAULT_BG_R 0x0
+#define MALIDP_DEFAULT_BG_G 0x0
+#define MALIDP_DEFAULT_BG_B 0x0
+
+#define MALIDP_PRODUCT_ID(core_id) ((u32)(core_id) >> 16)
+
+#define MALIDP500  0x500
+
+DECLARE_GLOBAL_D

[U-Boot] [PATCH v2] video: Add support for NXP's TDA19988 HDMI encoder

[Liviu Dudau]

Add support for the NXP TDA19988 HDMI encoder as used on the Juno
development board from Arm.

Signed-off-by: Liviu Dudau 
---
Changelog:
  - v2: Added MAINTAINERS entry and fixed checkpatch warnings.

 MAINTAINERS  |   5 +
 drivers/video/Kconfig|   8 +
 drivers/video/Makefile   |   1 +
 drivers/video/tda19988.c | 653 +++
 4 files changed, 667 insertions(+)
 create mode 100644 drivers/video/tda19988.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 11fc404167..112e41d2c3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -598,6 +598,11 @@ S: Maintained
 F: drivers/spmi/
 F: include/spmi/
 
+TDA19988 HDMI ENCODER
+M: Liviu Dudau 
+S: Maintained
+F: drivers/video/tda19988.c
+
 TI SYSTEM SECURITY
 M: Andrew F. Davis 
 S: Supported
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index ed0b21f2a7..5d932072a8 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -431,6 +431,14 @@ config DISPLAY
   The devices provide a simple interface to start up the display,
   read display information and enable it.
 
+config NXP_TDA19988
+   bool "Enable NXP TDA19988 support"
+   depends on DISPLAY
+   default n
+   help
+ This enables support for the NXP TDA19988 HDMI encoder. This encoder
+ will convert RGB data streams into HDMI-encoded signals.
+
 config ATMEL_HLCD
bool "Enable ATMEL video support using HLCDC"
depends on DM_VIDEO
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 0f41a23193..4c130e179d 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
 obj-$(CONFIG_LD9040) += ld9040.o
 obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_LOGICORE_DP_TX) += logicore_dp_tx.o
+obj-$(CONFIG_NXP_TDA19988) += tda19988.o
 obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
 obj-$(CONFIG_S6E8AX0) += s6e8ax0.o
 obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o
diff --git a/drivers/video/tda19988.c b/drivers/video/tda19988.c
new file mode 100644
index 00..01ed6193ea
--- /dev/null
+++ b/drivers/video/tda19988.c
@@ -0,0 +1,653 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 Liviu Dudau 
+ *
+ * Based on the Linux driver, (C) 2012 Texas Instruments
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * TDA19988 uses paged registers. We encode the page# in the upper
+ * bits of the register#. It also means that reads/writes to a register
+ * have to ensure that the register's page is selected as the current
+ * page.
+ */
+#define REG(page, addr)(((page) << 8) | (addr))
+#define REG2ADDR(reg)  ((reg) & 0xff)
+#define REG2PAGE(reg)  (((reg) >> 8) & 0xff)
+
+/* register for setting current page */
+#define REG_CURRENT_PAGE   0xff
+
+/* Page 00h: General Control */
+#define REG_VERSION_LSBREG(0x00, 0x00) /* read */
+#define REG_MAIN_CNTRL0REG(0x00, 0x01) /* read/write */
+#define  MAIN_CNTRL0_SRBIT(0)
+#define  MAIN_CNTRL0_DECS  BIT(1)
+#define  MAIN_CNTRL0_DEHS  BIT(2)
+#define  MAIN_CNTRL0_CECS  BIT(3)
+#define  MAIN_CNTRL0_CEHS  BIT(4)
+#define  MAIN_CNTRL0_SCALERBIT(7)
+#define REG_VERSION_MSBREG(0x00, 0x02) /* read */
+#define REG_SOFTRESET  REG(0x00, 0x0a) /* write */
+#define  SOFTRESET_AUDIO   BIT(0)
+#define  SOFTRESET_I2C_MASTER  BIT(1)
+#define REG_DDC_DISABLEREG(0x00, 0x0b) /* read/write */
+#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
+#define  I2C_MASTER_DIS_MM BIT(0)
+#define  I2C_MASTER_DIS_FILT   BIT(1)
+#define  I2C_MASTER_APP_STRT_LAT BIT(2)
+#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
+#define  FEAT_POWERDOWN_PREFILTBIT(0)
+#define  FEAT_POWERDOWN_CSCBIT(1)
+#define  FEAT_POWERDOWN_SPDIF  BIT(3)
+#define REG_INT_FLAGS_0REG(0x00, 0x0f) /* read/write */
+#define REG_INT_FLAGS_1REG(0x00, 0x10) /* read/write */
+#define REG_INT_FLAGS_2REG(0x00, 0x11) /* read/write */
+#define  INT_FLAGS_2_EDID_BLK_RD  BIT(1)
+#define REG_ENA_VP_0   REG(0x00, 0x18) /* read/write */
+#define REG_ENA_VP_1   REG(0x00, 0x19) /* read/write */
+#define REG_ENA_VP_2   REG(0x00, 0x1a) /* read/write */
+#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
+#define REG_VIP_CNTRL_0REG(0x00, 0x20) /* write */
+#define  VIP_CNTRL_0_MIRR_ABIT(7)
+#define  VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
+#define  VIP_CNTRL_0_MIRR_BBIT(3)
+#define  VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
+#define REG_VIP_CNTRL_1REG(0x00, 0x21) /* write */
+#define  VIP_CNTRL_1_MIRR_CBIT(7)
+#define  VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
+#define  VIP_CN

[U-Boot] [PATCH v2] i2c: Add support for the Arm's Versatile Express I2C controller.

[Liviu Dudau]

The Arm Versatile Express I2C controller is a simple register-based
controller that uses a register to control the state of the SCL and
SDA lines. Add support for it.

Signed-off-by: Liviu Dudau 
Reviewed-by: Heiko Schocher 
---
Changelog:
  - v2: Added MAINTAINERS entry and fixed checkpatch warnings.

 MAINTAINERS |   1 +
 drivers/i2c/Kconfig |   7 +
 drivers/i2c/Makefile|   1 +
 drivers/i2c/i2c-versatile.c | 280 
 4 files changed, 289 insertions(+)
 create mode 100644 drivers/i2c/i2c-versatile.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1aa68e8135..11fc404167 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -291,6 +291,7 @@ M:  Liviu Dudau 
 S: Maintained
 T: git git://github.com/ARM-software/u-boot.git
 F: drivers/clk/clk_vexpress_osc.c
+F: drivers/i2c/i2c-versatile.c
 F: drivers/misc/vexpress_config.c
 N: vexpress
 
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index ae3b501555..1ef22e6bcd 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -416,6 +416,13 @@ config SYS_I2C_UNIPHIER_F
  Support for UniPhier FIFO-builtin I2C controller driver.
  This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
 
+config SYS_I2C_VERSATILE
+   bool "Arm Ltd Versatile I2C bus driver"
+   depends on DM_I2C && (TARGET_VEXPRESS_CA15_TC2 || 
TARGET_VEXPRESS64_JUNO)
+   help
+ Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
+ controller is present in the development boards manufactured by Arm 
Ltd.
+
 config SYS_I2C_MVTWSI
bool "Marvell I2C driver"
depends on DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index f2cbe78c53..d3637bcd8d 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o
 obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
 obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
 obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
+obj-$(CONFIG_SYS_I2C_VERSATILE) += i2c-versatile.o
 obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
 obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o
 
diff --git a/drivers/i2c/i2c-versatile.c b/drivers/i2c/i2c-versatile.c
new file mode 100644
index 00..f523844204
--- /dev/null
+++ b/drivers/i2c/i2c-versatile.c
@@ -0,0 +1,280 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2018 Arm Ltd.
+ * Author: Liviu Dudau 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define I2C_CONTROL_REG0x00
+#define I2C_SET_REG0x00
+#define I2C_CLEAR_REG  0x04
+
+#define SCLBIT(0)
+#define SDABIT(1)
+
+struct versatile_i2c_priv {
+   phys_addr_t base;
+   u32 delay;
+};
+
+static inline void versatile_sda_set(struct versatile_i2c_priv *priv, u8 state)
+{
+   writel(SDA, priv->base + (state ? I2C_SET_REG : I2C_CLEAR_REG));
+   udelay(priv->delay);
+}
+
+static inline int versatile_sda_get(struct versatile_i2c_priv *priv)
+{
+   int v = !!(readl(priv->base + I2C_CONTROL_REG) & SDA);
+
+   udelay(priv->delay);
+   return v;
+}
+
+static inline void versatile_scl_set(struct versatile_i2c_priv *priv, u8 state)
+{
+   writel(SCL, priv->base + (state ? I2C_SET_REG : I2C_CLEAR_REG));
+   udelay(priv->delay);
+}
+
+static inline int versatile_scl_get(struct versatile_i2c_priv *priv)
+{
+   int v = !!(readl(priv->base + I2C_CONTROL_REG) & SCL);
+
+   udelay(priv->delay);
+   return v;
+}
+
+/* start: SDA goes from high to low while SCL is high */
+static void versatile_i2c_start(struct versatile_i2c_priv *priv)
+{
+   udelay(priv->delay);
+   versatile_sda_set(priv, 1);
+   versatile_scl_set(priv, 1);
+   versatile_sda_set(priv, 0);
+}
+
+/* stop: SDA goes from low to high while SCL is high */
+static void versatile_i2c_stop(struct versatile_i2c_priv *priv)
+{
+   versatile_scl_set(priv, 0);
+   versatile_sda_set(priv, 0);
+   versatile_scl_set(priv, 1);
+   versatile_sda_set(priv, 1);
+}
+
+/* read a bit from the SDA line (data or ACK/NACK) */
+static u8 versatile_i2c_read_bit(struct versatile_i2c_priv *priv)
+{
+   versatile_scl_set(priv, 0);
+   versatile_sda_set(priv, 1);
+   versatile_scl_set(priv, 1);
+   udelay(priv->delay);
+   return (u8)versatile_sda_get(priv);
+}
+
+/* write a bit on the SDA line */
+static void versatile_i2c_write_bit(struct versatile_i2c_priv *priv, u8 bit)
+{
+   versatile_scl_set(priv, 0);
+   versatile_sda_set(priv, bit);
+   versatile_scl_set(priv, 1);
+   udelay(priv->delay);
+}
+
+/* send a reset sequence of 9 clocks with SDA high */
+static void versatile_i2c_reset_bus(struct versatile_i2c_priv *priv)
+{
+   int i;
+
+   for (i = 0; i < 9; i++)
+   versatile_i2c_write_bit(priv, 1);
+

[U-Boot] [PATCH v3] misc: Add support for the Arm Versatile Express config bus

[Liviu Dudau]

Add support for the Arm Versatile Express config bus that is
being used for exposing various subsystems via a generic
configuration bus. This driver adds support for generating
transactions on this configuration bus and can be used by
other drivers to abstract the communication with the actual
function providers.

Signed-off-by: Liviu Dudau 
Reviewed-by: Heiko Schocher 
---

Changelog:
 - v3: Added MAINTAINERS entry and Reviewed-by tag
 - v2: removed #define DEBUG line leftover

 MAINTAINERS|   7 ++
 drivers/misc/Kconfig   |   8 +++
 drivers/misc/Makefile  |   1 +
 drivers/misc/vexpress_config.c | 128 +
 4 files changed, 144 insertions(+)
 create mode 100644 drivers/misc/vexpress_config.c

diff --git a/MAINTAINERS b/MAINTAINERS
index ea21d59f1e..613d7b29a0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -286,6 +286,13 @@ F: arch/arm/mach-uniphier/
 F: configs/uniphier_*_defconfig
 N: uniphier
 
+ARM VERSATILE EXPRESS DRIVERS
+M: Liviu Dudau 
+S: Maintained
+T: git git://github.com/ARM-software/u-boot.git
+F: drivers/misc/vexpress_config.c
+N: vexpress
+
 ARM ZYNQ
 M: Michal Simek 
 S: Maintained
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index bfa5c91687..78dc9264f9 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -41,6 +41,14 @@ config ROCKCHIP_EFUSE
  extended (by porting the read function from the Linux kernel sources)
  to support other recent Rockchip devices.
 
+config VEXPRESS_CONFIG
+   bool "Enable support for Arm Versatile Express config bus"
+   depends on MISC
+   help
+ If you say Y here, you will get support for accessing the
+ configuration bus on the Arm Versatile Express boards via
+ a sysreg driver.
+
 config CMD_CROS_EC
bool "Enable crosec command"
depends on CROS_EC
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index da4666fdfc..50b52f9aa5 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -55,4 +55,5 @@ obj-$(CONFIG_STM32MP_FUSE) += stm32mp_fuse.o
 obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o
 obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
 obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
+obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o
 obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
diff --git a/drivers/misc/vexpress_config.c b/drivers/misc/vexpress_config.c
new file mode 100644
index 00..9f5baa5288
--- /dev/null
+++ b/drivers/misc/vexpress_config.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Arm Ltd
+ * Author: Liviu Dudau 
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SYS_CFGDATA0xa0
+
+#define SYS_CFGCTRL0xa4
+#define SYS_CFGCTRL_START  BIT(31)
+#define SYS_CFGCTRL_WRITE  BIT(30)
+
+#define SYS_CFGSTAT0xa8
+#define SYS_CFGSTAT_ERRBIT(1)
+#define SYS_CFGSTAT_COMPLETE   BIT(0)
+
+struct vexpress_config_sysreg {
+   phys_addr_t addr;
+   u32 site;
+};
+
+static int vexpress_config_exec(struct vexpress_config_sysreg *syscfg,
+   bool write, void *buf, int size)
+{
+   u32 cmd, status, tries = 100;
+
+   cmd = (*(u32 *)buf) | SYS_CFGCTRL_START | (syscfg->site << 16);
+
+   if (!write) {
+   /* write a canary in the data register for reads */
+   writel(0xdeadbeef, syscfg->addr + SYS_CFGDATA);
+   } else {
+   cmd |= SYS_CFGCTRL_WRITE;
+   writel(((u32 *)buf)[1], syscfg->addr + SYS_CFGDATA);
+   }
+   writel(0, syscfg->addr + SYS_CFGSTAT);
+   writel(cmd, syscfg->addr + SYS_CFGCTRL);
+
+   /* completion of command takes ages, go to sleep (150us) */
+   do {
+   udelay(150);
+   status = readl(syscfg->addr + SYS_CFGSTAT);
+   if (status & SYS_CFGSTAT_ERR)
+   return -EFAULT;
+   } while (--tries && !(status & SYS_CFGSTAT_COMPLETE));
+
+   if (!tries)
+   return -ETIMEDOUT;
+
+   if (!write)
+   (*(u32 *)buf) = readl(syscfg->addr + SYS_CFGDATA);
+
+   return 0;
+}
+
+static int vexpress_config_read(struct udevice *dev,
+   int offset, void *buf, int size)
+{
+   struct vexpress_config_sysreg *priv = dev_get_uclass_priv(dev);
+
+   if (size != sizeof(u32))
+   return -EINVAL;
+
+   return vexpress_config_exec(priv, false, buf, size);
+}
+
+static int vexpress_config_write(struct udevice *dev,
+int offset, const void *buf, int size)
+{
+   struct vexpress_config_sysreg *priv = dev_get_uclass_priv(dev);
+
+   if (size != sizeof(u32) * 2)
+   return -EINVAL;
+
+   return vexpress_config_exec(priv, true, (void *)buf, size);
+}

[U-Boot] [PATCH v2] misc: Add support for the Arm Versatile Express config bus

[Liviu Dudau]

Add support for the Arm Versatile Express config bus that is
being used for exposing various subsystems via a generic
configuration bus. This driver adds support for generating
transactions on this configuration bus and can be used by
other drivers to abstract the communication with the actual
function providers.

Signed-off-by: Liviu Dudau 
---

Changelog:
 - v2: removed #define DEBUG line leftover

 drivers/misc/Kconfig   |   8 +++
 drivers/misc/Makefile  |   1 +
 drivers/misc/vexpress_config.c | 126 +
 3 files changed, 136 insertions(+)
 create mode 100644 drivers/misc/vexpress_config.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index c2b7cc15db..468a5682e3 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -41,6 +41,14 @@ config ROCKCHIP_EFUSE
  extended (by porting the read function from the Linux kernel sources)
  to support other recent Rockchip devices.
 
+config VEXPRESS_CONFIG
+   bool "Enable support for Arm Versatile Express config bus"
+   depends on MISC
+   help
+ If you say Y here, you will get support for accessing the
+ configuration bus on the Arm Versatile Express boards via
+ a sysreg driver.
+
 config CMD_CROS_EC
bool "Enable crosec command"
depends on CROS_EC
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 32ef4a53c7..6d3418efc7 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_STM32MP_FUSE) += stm32mp_fuse.o
 obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o
 obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
 obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
+obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o
diff --git a/drivers/misc/vexpress_config.c b/drivers/misc/vexpress_config.c
new file mode 100644
index 00..2cd433d01e
--- /dev/null
+++ b/drivers/misc/vexpress_config.c
@@ -0,1 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Arm Ltd
+ * Author: Liviu Dudau 
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SYS_CFGDATA0xa0
+
+#define SYS_CFGCTRL0xa4
+#define SYS_CFGCTRL_START  BIT(31)
+#define SYS_CFGCTRL_WRITE  BIT(30)
+
+#define SYS_CFGSTAT0xa8
+#define SYS_CFGSTAT_ERRBIT(1)
+#define SYS_CFGSTAT_COMPLETE   BIT(0)
+
+struct vexpress_config_sysreg {
+   phys_addr_t addr;
+   u32 site;
+};
+
+static int vexpress_config_exec(struct vexpress_config_sysreg *syscfg,
+   bool write, void *buf, int size)
+{
+   u32 cmd, status, tries = 100;
+
+   cmd = (*(u32 *)buf) | SYS_CFGCTRL_START | (syscfg->site << 16);
+
+   if (!write) {
+   /* write a canary in the data register for reads */
+   writel(0xdeadbeef, syscfg->addr + SYS_CFGDATA);
+   } else {
+   cmd |= SYS_CFGCTRL_WRITE;
+   writel(((u32 *)buf)[1], syscfg->addr + SYS_CFGDATA);
+   }
+   writel(0, syscfg->addr + SYS_CFGSTAT);
+   writel(cmd, syscfg->addr + SYS_CFGCTRL);
+
+   /* completion of command takes ages, go to sleep (150us) */
+   do {
+   udelay(150);
+   status = readl(syscfg->addr + SYS_CFGSTAT);
+   if (status & SYS_CFGSTAT_ERR)
+   return -EFAULT;
+   } while (--tries && !(status & SYS_CFGSTAT_COMPLETE));
+
+   if (!tries)
+   return -ETIMEDOUT;
+
+   if (!write)
+   (*(u32 *)buf) = readl(syscfg->addr + SYS_CFGDATA);
+
+   return 0;
+}
+
+static int vexpress_config_read(struct udevice *dev, int offset, void *buf, 
int size)
+{
+   struct vexpress_config_sysreg *priv = dev_get_uclass_priv(dev);
+
+   if (size != sizeof(u32))
+   return -EINVAL;
+
+   return vexpress_config_exec(priv, false, buf, size);
+}
+
+static int vexpress_config_write(struct udevice *dev, int offset, const void 
*buf, int size)
+{
+   struct vexpress_config_sysreg *priv = dev_get_uclass_priv(dev);
+
+   if (size != sizeof(u32) * 2)
+   return -EINVAL;
+
+   return vexpress_config_exec(priv, true, (void *)buf, size);
+}
+
+static struct misc_ops vexpress_config_ops = {
+   .read = vexpress_config_read,
+   .write = vexpress_config_write,
+};
+
+static int vexpress_config_probe(struct udevice *dev)
+{
+   struct ofnode_phandle_args args;
+   struct vexpress_config_sysreg *priv;
+   const char *prop;
+   int err, prop_size;
+
+   err = dev_read_phandle_with_args(dev, "arm,vexpress,config-bridge",
+NULL, 0, 0, );
+   if (err)
+   return err;
+
+   prop = ofnode_get_property(args.node, "compatible", _size);
+   if (!prop || (strncmp(prop, "arm,vexpress-sysreg", 19) != 0))

Re: [U-Boot] [PATCH] uclass: Use uclass_foreach_dev() macro instead of open coding

[Liviu Dudau]

On Wed, Sep 19, 2018 at 09:30:37AM -0600, Simon Glass wrote:
> Hi,
> 
> On 18 September 2018 at 02:08, Liviu Dudau  wrote:
> >
> > On Tue, Sep 18, 2018 at 04:06:13AM +0200, Simon Glass wrote:
> > > On 17 September 2018 at 10:44, Liviu Dudau  
> > > wrote:
> > > > Use the uclass_foreach_dev() macro instead of the open coded version.
> > > >
> > > > Signed-off-by: Liviu Dudau 
> > > > ---
> > > >  drivers/core/uclass.c | 2 +-
> > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > Reviewed-by: Simon Glass 
> > >
> > > Perhaps you could also convert a few usages?
> >
> > Not sure what you mean. Are you suggesting that I should convert more of
> > the code that uses the open coded version into uclass_foreach_dev() ?
> 
> Yes. After all, at present your macro is just dead code :-)

I think there is some confusion here. I didn't write the macro, it is
present in include/dm/uclass.h since you have introduced it in commit 
6494d708bfc630ac0
("dm: Add base driver model support"). All I have done was to notice
that in uclass.c the list_for_each_entry() line can be replaced by the
macro with the same effect.

I also didn't get what you meant by "your macro is just dead code".

Best regards,
Liviu

> 
> Regards,
> Simon

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Re: [U-Boot] [PATCH] i2c: Add support for the Arm's Versatile Express I2C controller.

[Liviu Dudau]

On Tue, Sep 18, 2018 at 06:21:17AM +0200, Heiko Schocher wrote:
> Hello Liviu,
> 
> Am 17.09.2018 um 18:51 schrieb Liviu Dudau:
> > The Arm Versatile Express I2C controller is a simple register-based
> > controller that uses a register to control the state of the SCL and
> > SDA lines. Add support for it.
> > 
> > Signed-off-by: Liviu Dudau 
> > ---
> >   drivers/i2c/Kconfig |   7 +
> >   drivers/i2c/Makefile|   1 +
> >   drivers/i2c/i2c-versatile.c | 270 
> >   3 files changed, 278 insertions(+)
> >   create mode 100644 drivers/i2c/i2c-versatile.c
> 
> Reviewed-by: Heiko Schocher 
> 
> I am unsure here, if all your patches are a patchserie, or if this
> i2c patch can go seperately through i2c tree ...

The patches adding support for Arm Versatile express hardware can indeed
be considered as part of a series (adding support for Mali DP, where I
also need I2C to do EDID and clock generators for pixel clocks).
However, there is no dependency between patches, so they could go
individually into different trees.

Best regards,
Liviu

> 
> bye,
> Heiko
> -- 
> DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

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Re: [U-Boot] [PATCH] misc: Add support for the Arm Versatile Express config bus

[Liviu Dudau]

On Tue, Sep 18, 2018 at 06:18:48AM +0200, Heiko Schocher wrote:
> Hello Liviu,
> 
> Am 17.09.2018 um 18:48 schrieb Liviu Dudau:
> > Add support for the Arm Versatile Express config bus that is
> > being used for exposing various subsystems via a generic
> > configuration bus. This driver adds support for generating
> > transactions on this configuration bus and can be used by
> > other drivers to abstract the communication with the actual
> > function providers.
> > 
> > Signed-off-by: Liviu Dudau 
> > ---
> >   drivers/misc/Kconfig   |   8 +++
> >   drivers/misc/Makefile  |   1 +
> >   drivers/misc/vexpress_config.c | 127 +
> >   3 files changed, 136 insertions(+)
> >   create mode 100644 drivers/misc/vexpress_config.c
> > 
> 
> Beside of a nitpick
> 
> Reviewed-by: Heiko Schocher 
> 
> [...]
> > diff --git a/drivers/misc/vexpress_config.c b/drivers/misc/vexpress_config.c
> > new file mode 100644
> > index 00..2cd433d01e
> > --- /dev/null
> > +++ b/drivers/misc/vexpress_config.c
> > @@ -0,1 +1,127 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2018 Arm Ltd
> > + * Author: Liviu Dudau 
> > + *
> > + */
> > +#define DEBUG
> 
> Really enable debug?

Sorry, left over from development, I will remove it and re-submit.

Best regards,
Liviu

> 
> bye,
> Heiko
> -- 
> DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de

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Re: [U-Boot] [PATCH] uclass: Use uclass_foreach_dev() macro instead of open coding

[Liviu Dudau]

On Tue, Sep 18, 2018 at 04:06:13AM +0200, Simon Glass wrote:
> On 17 September 2018 at 10:44, Liviu Dudau  wrote:
> > Use the uclass_foreach_dev() macro instead of the open coded version.
> >
> > Signed-off-by: Liviu Dudau 
> > ---
> >  drivers/core/uclass.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> Reviewed-by: Simon Glass 
> 
> Perhaps you could also convert a few usages?

Not sure what you mean. Are you suggesting that I should convert more of
the code that uses the open coded version into uclass_foreach_dev() ?

Best regards,
Liviu


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 \ source code!  /
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[U-Boot] [PATCH] dm: core: Widen the dump tree to show more of the driver's name.

[Liviu Dudau]

With drivers that have prefix names that are quite long (like
'versatile_') it is useful to have a wider column for the driver's
name when dumping the device driver tree.

Signed-off-by: Liviu Dudau 
---
 drivers/core/dump.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/core/dump.c b/drivers/core/dump.c
index d7cdb1475d..9d59fa90b2 100644
--- a/drivers/core/dump.c
+++ b/drivers/core/dump.c
@@ -15,8 +15,8 @@ static void show_devices(struct udevice *dev, int depth, int 
last_flag)
int i, is_last;
struct udevice *child;
 
-   /* print the first 11 characters to not break the tree-format. */
-   printf(" %-10.10s  %d  [ %c ]   %-10.10s  ", dev->uclass->uc_drv->name,
+   /* print the first 20 characters to not break the tree-format. */
+   printf(" %-10.10s  %d  [ %c ]   %-20.20s  ", dev->uclass->uc_drv->name,
   dev_get_uclass_index(dev, NULL),
   dev->flags & DM_FLAG_ACTIVATED ? '+' : ' ', dev->driver->name);
 
@@ -49,8 +49,8 @@ void dm_dump_all(void)
 
root = dm_root();
if (root) {
-   printf(" Classindex  Probed  Driver  Name\n");
-   printf("-\n");
+   printf(" Classindex  Probed  DriverName\n");
+   
printf("---\n");
show_devices(root, -1, 0);
}
 }
-- 
2.18.0

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[U-Boot] [PATCH] video: Add support for Arm's Mali Display Processors

[Liviu Dudau]

Add support for Arm Mali Display Processors DP500, DP550 and DP650.
Only one layer is being used to display the console or boot logo,
even if more layers are supported in the hardware.

Signed-off-by: Liviu Dudau 
---
 drivers/video/Kconfig   |   8 +
 drivers/video/Makefile  |   1 +
 drivers/video/mali_dp.c | 387 
 3 files changed, 396 insertions(+)
 create mode 100644 drivers/video/mali_dp.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 9f21ef30a9..66fc6641af 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -496,6 +496,14 @@ config VIDEO_FSL_DCU_MAX_FB_SIZE_MB
 
 source "drivers/video/rockchip/Kconfig"
 
+config VIDEO_ARM_MALIDP
+   bool "Enable Arm Mali Display Processor support"
+   depends on DM_VIDEO && OF_CONTROL
+   select VEXPRESS_CLK
+   help
+ This enables support for Arm Ltd Mali Display Processors from
+ the DP500, DP550 and DP650 family.
+
 config VIDEO_SANDBOX_SDL
bool "Enable sandbox video console using SDL"
depends on SANDBOX
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 4c130e179d..e19e6dad1f 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_NXP_TDA19988) += tda19988.o
 obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
 obj-$(CONFIG_S6E8AX0) += s6e8ax0.o
 obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o
+obj-$(CONFIG_VIDEO_ARM_MALIDP) += mali_dp.o
 obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o
 obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o
 obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
diff --git a/drivers/video/mali_dp.c b/drivers/video/mali_dp.c
new file mode 100644
index 00..8e830e0fae
--- /dev/null
+++ b/drivers/video/mali_dp.c
@@ -0,1 +1,387 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016-2018 ARM Ltd.
+ * Author: Liviu Dudau 
+ *
+ */
+#define DEBUG
+#include 
+#include 
+#include 
+#ifdef CONFIG_DISPLAY
+#include 
+#endif
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define MALIDP_CORE_ID 0x0018
+#define MALIDP_REG_BG_COLOR0x0044
+#define MALIDP_LAYER_LV1   0x0100
+#define MALIDP_DC_STATUS   0xc000
+#define MALIDP_DC_CONTROL  0xc010
+#define MALIDP_DC_CFG_VALID0xc014
+
+/* offsets inside the modesetting register block */
+#define MALIDP_H_INTERVALS 0x
+#define MALIDP_V_INTERVALS 0x0004
+#define MALIDP_SYNC_CONTROL0x0008
+#define MALIDP_HV_ACTIVESIZE   0x000c
+#define MALIDP_OUTPUT_DEPTH0x001c
+
+/* offsets inside the layer register block */
+#define MALIDP_LAYER_FORMAT0x
+#define MALIDP_LAYER_CONTROL   0x0004
+#define MALIDP_LAYER_IN_SIZE   0x000c
+#define MALIDP_LAYER_CMP_SIZE  0x0010
+#define MALIDP_LAYER_STRIDE0x0018
+#define MALIDP_LAYER_PTR_LOW   0x0024
+#define MALIDP_LAYER_PTR_HIGH  0x0028
+
+/* offsets inside the IRQ control blocks */
+#define MALIDP_REG_MASKIRQ 0x0008
+#define MALIDP_REG_CLEARIRQ0x000c
+
+#define M1BITS 0x0001
+#define M2BITS 0x0003
+#define M4BITS 0x000f
+#define M8BITS 0x00ff
+#define M10BITS0x03ff
+#define M12BITS0x0fff
+#define M13BITS0x1fff
+#define M16BITS0x
+#define M17BITS0x1
+
+#define MALIDP_H_FRONTPORCH(x) (((x) & M12BITS) << 0)
+#define MALIDP_H_BACKPORCH(x)  (((x) & M10BITS) << 16)
+#define MALIDP_V_FRONTPORCH(x) (((x) & M12BITS) << 0)
+#define MALIDP_V_BACKPORCH(x)  (((x) & M8BITS) << 16)
+#define MALIDP_H_SYNCWIDTH(x)  (((x) & M10BITS) << 0)
+#define MALIDP_V_SYNCWIDTH(x)  (((x) & M8BITS) << 16)
+#define MALIDP_H_ACTIVE(x) (((x) & M13BITS) << 0)
+#define MALIDP_V_ACTIVE(x) (((x) & M13BITS) << 16)
+
+#define MALIDP_CMP_V_SIZE(x)   (((x) & M13BITS) << 16)
+#define MALIDP_CMP_H_SIZE(x)   (((x) & M13BITS) << 0)
+
+#define MALIDP_IN_V_SIZE(x)(((x) & M13BITS) << 16)
+#define MALIDP_IN_H_SIZE(x)(((x) & M13BITS) << 0)
+
+#define MALIDP_DC_CM_CONTROL(x)((x) & M1BITS) << 16, 1 << 16
+#define MALIDP_DC_STATUS_GET_CM(reg) (((reg) >> 16) & M1BITS)
+
+#define MALIDP_FORMAT_ARGB 0x08
+#define MALIDP_DEFAULT_BG_R 0x0
+#define MALIDP_DEFAULT_BG_G 0x0
+#define MALIDP_DEFAULT_BG_B 0x0
+
+#define MALIDP_PRODUCT_ID(core_id) ((u32)(core_id) >> 16)
+
+#define MALIDP500  0x500
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct malidp_priv {
+   phys_addr_t base_addr;
+   phys_addr_t dc_status_addr;
+   phys_addr_t dc_control_addr;
+   phys_addr_t cval_addr;
+   struct udevice *display;/* display device attached */
+   struct clk aclk;
+   struct clk pxlclk;
+   u16 modeset_regs_offset;
+   u8 config_bit_shift;
+   u8 clear_irq;   /* offset for IRQ clear register */
+};
+
+static const struct video_ops malidp_ops = {
+};
+
+static int ma

[U-Boot] [PATCH] video: Add support for NXP's TDA19988 HDMI encoder

[Liviu Dudau]

Add support for the NXP TDA19988 HDMI encoder as used on the Juno
development board from Arm.

Signed-off-by: Liviu Dudau 
---
 drivers/video/Kconfig|   7 +
 drivers/video/Makefile   |   1 +
 drivers/video/tda19988.c | 637 +++
 3 files changed, 645 insertions(+)
 create mode 100644 drivers/video/tda19988.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index ed0b21f2a7..9f21ef30a9 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -431,6 +431,13 @@ config DISPLAY
   The devices provide a simple interface to start up the display,
   read display information and enable it.
 
+config NXP_TDA19988
+   bool "Enable NXP TDA19988 support"
+   depends on DISPLAY
+   default n
+   help
+ This enables support for the NXP TDA19988 HDMI encoder.
+
 config ATMEL_HLCD
bool "Enable ATMEL video support using HLCDC"
depends on DM_VIDEO
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 0f41a23193..4c130e179d 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
 obj-$(CONFIG_LD9040) += ld9040.o
 obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_LOGICORE_DP_TX) += logicore_dp_tx.o
+obj-$(CONFIG_NXP_TDA19988) += tda19988.o
 obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
 obj-$(CONFIG_S6E8AX0) += s6e8ax0.o
 obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o
diff --git a/drivers/video/tda19988.c b/drivers/video/tda19988.c
new file mode 100644
index 00..b6a895ac37
--- /dev/null
+++ b/drivers/video/tda19988.c
@@ -0,1 +1,637 @@
+/*
+ * (C) Copyright 2018 Liviu Dudau 
+ *
+ * Based on the Linux driver, (C) 2012 Texas Instruments
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * TDA19988 uses paged registers. We encode the page# in the upper
+ * bits of the register#. It also means that reads/writes to a register
+ * have to ensure that the register's page is selected as the current
+ * page.
+ */
+#define REG(page, addr)(((page) << 8) | (addr))
+#define REG2ADDR(reg)  ((reg) & 0xff)
+#define REG2PAGE(reg)  (((reg) >> 8) & 0xff)
+
+/* register for setting current page */
+#define REG_CURRENT_PAGE   0xff
+
+/* Page 00h: General Control */
+#define REG_VERSION_LSBREG(0x00, 0x00) /* read */
+#define REG_MAIN_CNTRL0REG(0x00, 0x01) /* read/write */
+#define  MAIN_CNTRL0_SRBIT(0)
+#define  MAIN_CNTRL0_DECS  BIT(1)
+#define  MAIN_CNTRL0_DEHS  BIT(2)
+#define  MAIN_CNTRL0_CECS  BIT(3)
+#define  MAIN_CNTRL0_CEHS  BIT(4)
+#define  MAIN_CNTRL0_SCALERBIT(7)
+#define REG_VERSION_MSBREG(0x00, 0x02) /* read */
+#define REG_SOFTRESET  REG(0x00, 0x0a) /* write */
+#define  SOFTRESET_AUDIO   BIT(0)
+#define  SOFTRESET_I2C_MASTER  BIT(1)
+#define REG_DDC_DISABLEREG(0x00, 0x0b) /* read/write */
+#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
+#define  I2C_MASTER_DIS_MM BIT(0)
+#define  I2C_MASTER_DIS_FILT   BIT(1)
+#define  I2C_MASTER_APP_STRT_LAT BIT(2)
+#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
+#define  FEAT_POWERDOWN_PREFILTBIT(0)
+#define  FEAT_POWERDOWN_CSCBIT(1)
+#define  FEAT_POWERDOWN_SPDIF  BIT(3)
+#define REG_INT_FLAGS_0REG(0x00, 0x0f) /* read/write */
+#define REG_INT_FLAGS_1REG(0x00, 0x10) /* read/write */
+#define REG_INT_FLAGS_2REG(0x00, 0x11) /* read/write */
+#define  INT_FLAGS_2_EDID_BLK_RD  BIT(1)
+#define REG_ENA_VP_0   REG(0x00, 0x18) /* read/write */
+#define REG_ENA_VP_1   REG(0x00, 0x19) /* read/write */
+#define REG_ENA_VP_2   REG(0x00, 0x1a) /* read/write */
+#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
+#define REG_VIP_CNTRL_0REG(0x00, 0x20) /* write */
+#define  VIP_CNTRL_0_MIRR_ABIT(7)
+#define  VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
+#define  VIP_CNTRL_0_MIRR_BBIT(3)
+#define  VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
+#define REG_VIP_CNTRL_1REG(0x00, 0x21) /* write */
+#define  VIP_CNTRL_1_MIRR_CBIT(7)
+#define  VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
+#define  VIP_CNTRL_1_MIRR_DBIT(3)
+#define  VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
+#define REG_VIP_CNTRL_2REG(0x00, 0x22) /* write */
+#define  VIP_CNTRL_2_MIRR_EBIT(7)
+#define  VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
+#define  VIP_CNTRL_2_MIRR_FBIT(3)
+#define  VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
+#define REG_VIP_CNTRL_3REG(0x00, 0x23) /* write */
+#define  VIP_CNTRL_3_X_TGL BIT(0)
+#define  VIP_CNTRL_3_H_TGL BIT(1)
+#define  VIP_CNTRL_3_V_T

[U-Boot] [PATCH] i2c: Add support for the Arm's Versatile Express I2C controller.

[Liviu Dudau]

The Arm Versatile Express I2C controller is a simple register-based
controller that uses a register to control the state of the SCL and
SDA lines. Add support for it.

Signed-off-by: Liviu Dudau 
---
 drivers/i2c/Kconfig |   7 +
 drivers/i2c/Makefile|   1 +
 drivers/i2c/i2c-versatile.c | 270 
 3 files changed, 278 insertions(+)
 create mode 100644 drivers/i2c/i2c-versatile.c

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index ae3b501555..1ef22e6bcd 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -416,6 +416,13 @@ config SYS_I2C_UNIPHIER_F
  Support for UniPhier FIFO-builtin I2C controller driver.
  This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
 
+config SYS_I2C_VERSATILE
+   bool "Arm Ltd Versatile I2C bus driver"
+   depends on DM_I2C && (TARGET_VEXPRESS_CA15_TC2 || 
TARGET_VEXPRESS64_JUNO)
+   help
+ Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
+ controller is present in the development boards manufactured by Arm 
Ltd.
+
 config SYS_I2C_MVTWSI
bool "Marvell I2C driver"
depends on DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index f2cbe78c53..d3637bcd8d 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o
 obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
 obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
 obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
+obj-$(CONFIG_SYS_I2C_VERSATILE) += i2c-versatile.o
 obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
 obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o
 
diff --git a/drivers/i2c/i2c-versatile.c b/drivers/i2c/i2c-versatile.c
new file mode 100644
index 00..5faa5c93e2
--- /dev/null
+++ b/drivers/i2c/i2c-versatile.c
@@ -0,1 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2018 Arm Ltd.
+ * Author: Liviu Dudau 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define I2C_CONTROL_REG0x00
+#define I2C_SET_REG0x00
+#define I2C_CLEAR_REG  0x04
+
+#define SCLBIT(0)
+#define SDABIT(1)
+
+struct versatile_i2c_priv {
+   phys_addr_t base;
+   u32 delay;
+};
+
+static inline void versatile_sda_set(struct versatile_i2c_priv *priv, u8 state)
+{
+   writel(SDA, priv->base + (state ? I2C_SET_REG : I2C_CLEAR_REG));
+   udelay(priv->delay);
+}
+
+static inline int versatile_sda_get(struct versatile_i2c_priv *priv)
+{
+   int v = !!(readl(priv->base + I2C_CONTROL_REG) & SDA);
+   udelay(priv->delay);
+   return v;
+}
+
+static inline void versatile_scl_set(struct versatile_i2c_priv *priv, u8 state)
+{
+   writel(SCL, priv->base + (state ? I2C_SET_REG : I2C_CLEAR_REG));
+   udelay(priv->delay);
+}
+
+static inline int versatile_scl_get(struct versatile_i2c_priv *priv)
+{
+   int v = !!(readl(priv->base + I2C_CONTROL_REG) & SCL);
+   udelay(priv->delay);
+   return v;
+}
+
+/* start: SDA goes from high to low while SCL is high */
+static void versatile_i2c_start(struct versatile_i2c_priv *priv)
+{
+   udelay(priv->delay);
+   versatile_sda_set(priv, 1);
+   versatile_scl_set(priv, 1);
+   versatile_sda_set(priv, 0);
+}
+
+/* stop: SDA goes from low to high while SCL is high */
+static void versatile_i2c_stop(struct versatile_i2c_priv *priv)
+{
+   versatile_scl_set(priv, 0);
+   versatile_sda_set(priv, 0);
+   versatile_scl_set(priv, 1);
+   versatile_sda_set(priv, 1);
+}
+
+/* read a bit from the SDA line (data or ACK/NACK) */
+static u8 versatile_i2c_read_bit(struct versatile_i2c_priv *priv)
+{
+   versatile_scl_set(priv, 0);
+   versatile_sda_set(priv, 1);
+   versatile_scl_set(priv, 1);
+   udelay(priv->delay);
+   return (u8)versatile_sda_get(priv);
+}
+
+/* write a bit on the SDA line */
+static void versatile_i2c_write_bit(struct versatile_i2c_priv *priv, u8 bit)
+{
+   versatile_scl_set(priv, 0);
+   versatile_sda_set(priv, bit);
+   versatile_scl_set(priv, 1);
+   udelay(priv->delay);
+}
+
+/* send a reset sequence of 9 clocks with SDA high */
+static void versatile_i2c_reset_bus(struct versatile_i2c_priv *priv)
+{
+   int i;
+
+   for (i = 0; i < 9; i++)
+   versatile_i2c_write_bit(priv, 1);
+
+   versatile_i2c_stop(priv);
+}
+
+/* write byte without start/stop sequence */
+static int versatile_i2c_write_byte(struct versatile_i2c_priv *priv, u8 byte)
+{
+   u8 nak, i;
+
+   for (i = 0; i < 8; i++) {
+   versatile_i2c_write_bit(priv, byte & 0x80);
+   byte <<= 1;
+   }
+
+   /* read ACK */
+   nak = versatile_i2c_read_bit(priv);
+   versatile_scl_set(priv, 0);
+
+   return nak; /* not a nack is an ack */
+}
+
+

[U-Boot] [PATCH] clk: Add support for Arm's Versatile Express OSC clock generators

[Liviu Dudau]

The Arm Versatile Express and Juno development boards contain an
OSC clock generator that can be accessed through the Versatile
Express config bus. The generators are quite often being controlled
by some MCU and the config bus offers a uniform way of exposing them.

Signed-off-by: Liviu Dudau 
---
 drivers/clk/Kconfig|   7 +++
 drivers/clk/Makefile   |   1 +
 drivers/clk/clk_vexpress_osc.c | 109 +
 3 files changed, 117 insertions(+)
 create mode 100644 drivers/clk/clk_vexpress_osc.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 809eb3dacf..008cd1186e 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -68,6 +68,13 @@ config CLK_HSDK
help
  Enable this to support the cgu clocks on Synopsys ARC HSDK
 
+config CLK_VEXPRESS_OSC
+   bool "Enable driver for Arm Versatile Express OSC clock generators"
+   depends on CLK && VEXPRESS_CONFIG
+   help
+ This clock driver adds support for clock generators present on
+ Arm Versatile Express platforms.
+
 config CLK_ZYNQ
bool "Enable clock driver support for Zynq"
depends on CLK && ARCH_ZYNQ
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 82c36b7478..2975e21120 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_CLK_RENESAS) += renesas/
 obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
 obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
 obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
+obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
 obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
 obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
 obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
diff --git a/drivers/clk/clk_vexpress_osc.c b/drivers/clk/clk_vexpress_osc.c
new file mode 100644
index 00..450f47ac3d
--- /dev/null
+++ b/drivers/clk/clk_vexpress_osc.c
@@ -0,1 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Arm Ltd
+ * Author: Liviu Dudau 
+ *
+ */
+#define DEBUG
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CLK_FUNCTION   BIT(20)
+
+struct vexpress_osc_clk_priv {
+   u8 osc;
+   ulong rate_min;
+   ulong rate_max;
+};
+
+static ulong vexpress_osc_clk_get_rate(struct clk *clk)
+{
+   int err;
+   u32 data;
+   struct udevice *vexpress_cfg = dev_get_parent(clk->dev);
+   struct vexpress_osc_clk_priv *priv = dev_get_priv(clk->dev);
+
+   data = CLK_FUNCTION | priv->osc;
+   err = misc_read(vexpress_cfg, 0, , sizeof(data));
+   if (err)
+   return err;
+
+   return data;
+}
+
+#ifndef CONFIG_SPL_BUILD
+static ulong vexpress_osc_clk_set_rate(struct clk *clk, ulong rate)
+{
+   int err;
+   u32 buffer[2];
+   struct udevice *vexpress_cfg = dev_get_parent(clk->dev);
+   struct vexpress_osc_clk_priv *priv = dev_get_priv(clk->dev);
+
+   if (rate < priv->rate_min || rate > priv->rate_max)
+   return -EINVAL;
+
+   /*
+* we are sending the parent the info about the oscillator
+* and the value we want to set
+*/
+   buffer[0] = CLK_FUNCTION | priv->osc;
+   buffer[1] = rate;
+   err = misc_write(vexpress_cfg, 0, buffer, 2 * sizeof(u32));
+   if (err)
+   return err;
+
+   return rate;
+}
+#endif
+
+static struct clk_ops vexpress_osc_clk_ops = {
+   .get_rate = vexpress_osc_clk_get_rate,
+#ifndef CONFIG_SPL_BUILD
+   .set_rate = vexpress_osc_clk_set_rate,
+#endif
+};
+
+static int vexpress_osc_clk_probe(struct udevice *dev)
+{
+   struct vexpress_osc_clk_priv *priv = dev_get_priv(dev);
+   u32 values[2];
+   int err;
+
+   err = dev_read_u32_array(dev, "freq-range", values, 2);
+   if (err)
+   return err;
+   priv->rate_min = values[0];
+   priv->rate_max = values[1];
+
+   err = dev_read_u32_array(dev, "arm,vexpress-sysreg,func", values, 2);
+   if (err)
+   return err;
+
+   if (values[0] != 1) {
+   dev_err(dev, "Invalid VExpress function for clock, must be 
'1'");
+   return -EINVAL;
+   }
+   priv->osc = values[1];
+   debug("clk \"%s%d\", min freq %luHz, max freq %luHz\n", dev->name,
+ priv->osc, priv->rate_min, priv->rate_max);
+
+   return 0;
+}
+
+static const struct udevice_id vexpress_osc_clk_ids[] = {
+   { .compatible = "arm,vexpress-osc", },
+   {}
+};
+
+U_BOOT_DRIVER(vexpress_osc_clk) = {
+   .name = "vexpress_osc_clk",
+   .id = UCLASS_CLK,
+   .of_match = vexpress_osc_clk_ids,
+   .ops = _osc_clk_ops,
+   .priv_auto_alloc_size = sizeof(struct vexpress_osc_clk_priv),
+   .probe = vexpress_osc_clk_probe,
+};
-- 
2.18.0

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[U-Boot] [PATCH] misc: Add support for the Arm Versatile Express config bus

[Liviu Dudau]

Add support for the Arm Versatile Express config bus that is
being used for exposing various subsystems via a generic
configuration bus. This driver adds support for generating
transactions on this configuration bus and can be used by
other drivers to abstract the communication with the actual
function providers.

Signed-off-by: Liviu Dudau 
---
 drivers/misc/Kconfig   |   8 +++
 drivers/misc/Makefile  |   1 +
 drivers/misc/vexpress_config.c | 127 +
 3 files changed, 136 insertions(+)
 create mode 100644 drivers/misc/vexpress_config.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index c2b7cc15db..468a5682e3 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -41,6 +41,14 @@ config ROCKCHIP_EFUSE
  extended (by porting the read function from the Linux kernel sources)
  to support other recent Rockchip devices.
 
+config VEXPRESS_CONFIG
+   bool "Enable support for Arm Versatile Express config bus"
+   depends on MISC
+   help
+ If you say Y here, you will get support for accessing the
+ configuration bus on the Arm Versatile Express boards via
+ a sysreg driver.
+
 config CMD_CROS_EC
bool "Enable crosec command"
depends on CROS_EC
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 32ef4a53c7..6d3418efc7 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_STM32MP_FUSE) += stm32mp_fuse.o
 obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o
 obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
 obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
+obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o
diff --git a/drivers/misc/vexpress_config.c b/drivers/misc/vexpress_config.c
new file mode 100644
index 00..2cd433d01e
--- /dev/null
+++ b/drivers/misc/vexpress_config.c
@@ -0,1 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Arm Ltd
+ * Author: Liviu Dudau 
+ *
+ */
+#define DEBUG
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SYS_CFGDATA0xa0
+
+#define SYS_CFGCTRL0xa4
+#define SYS_CFGCTRL_START  BIT(31)
+#define SYS_CFGCTRL_WRITE  BIT(30)
+
+#define SYS_CFGSTAT0xa8
+#define SYS_CFGSTAT_ERRBIT(1)
+#define SYS_CFGSTAT_COMPLETE   BIT(0)
+
+struct vexpress_config_sysreg {
+   phys_addr_t addr;
+   u32 site;
+};
+
+static int vexpress_config_exec(struct vexpress_config_sysreg *syscfg,
+   bool write, void *buf, int size)
+{
+   u32 cmd, status, tries = 100;
+
+   cmd = (*(u32 *)buf) | SYS_CFGCTRL_START | (syscfg->site << 16);
+
+   if (!write) {
+   /* write a canary in the data register for reads */
+   writel(0xdeadbeef, syscfg->addr + SYS_CFGDATA);
+   } else {
+   cmd |= SYS_CFGCTRL_WRITE;
+   writel(((u32 *)buf)[1], syscfg->addr + SYS_CFGDATA);
+   }
+   writel(0, syscfg->addr + SYS_CFGSTAT);
+   writel(cmd, syscfg->addr + SYS_CFGCTRL);
+
+   /* completion of command takes ages, go to sleep (150us) */
+   do {
+   udelay(150);
+   status = readl(syscfg->addr + SYS_CFGSTAT);
+   if (status & SYS_CFGSTAT_ERR)
+   return -EFAULT;
+   } while (--tries && !(status & SYS_CFGSTAT_COMPLETE));
+
+   if (!tries)
+   return -ETIMEDOUT;
+
+   if (!write)
+   (*(u32 *)buf) = readl(syscfg->addr + SYS_CFGDATA);
+
+   return 0;
+}
+
+static int vexpress_config_read(struct udevice *dev, int offset, void *buf, 
int size)
+{
+   struct vexpress_config_sysreg *priv = dev_get_uclass_priv(dev);
+
+   if (size != sizeof(u32))
+   return -EINVAL;
+
+   return vexpress_config_exec(priv, false, buf, size);
+}
+
+static int vexpress_config_write(struct udevice *dev, int offset, const void 
*buf, int size)
+{
+   struct vexpress_config_sysreg *priv = dev_get_uclass_priv(dev);
+
+   if (size != sizeof(u32) * 2)
+   return -EINVAL;
+
+   return vexpress_config_exec(priv, true, (void *)buf, size);
+}
+
+static struct misc_ops vexpress_config_ops = {
+   .read = vexpress_config_read,
+   .write = vexpress_config_write,
+};
+
+static int vexpress_config_probe(struct udevice *dev)
+{
+   struct ofnode_phandle_args args;
+   struct vexpress_config_sysreg *priv;
+   const char *prop;
+   int err, prop_size;
+
+   err = dev_read_phandle_with_args(dev, "arm,vexpress,config-bridge",
+NULL, 0, 0, );
+   if (err)
+   return err;
+
+   prop = ofnode_get_property(args.node, "compatible", _size);
+   if (!prop || (strncmp(prop, "arm,vexpress-sysreg", 19) != 0))
+   return -ENOENT;
+
+   priv

[U-Boot] [PATCH] include/dm.h: Remove duplicated include directive.

[Liviu Dudau]

Remove duplicated inclusion of dm/ofnode.h

Signed-off-by: Liviu Dudau 
---
 include/dm.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/dm.h b/include/dm.h
index bf4b07d28f..2e1afda440 100644
--- a/include/dm.h
+++ b/include/dm.h
@@ -6,7 +6,6 @@
 #ifndef _DM_H_
 #define _DM_H_
 
-#include 
 #include 
 #include 
 #include 
-- 
2.18.0

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[U-Boot] [PATCH] include/video.h: Remove declaration of functions that don't exist.

[Liviu Dudau]

video_init, video_putc and video_puts functions are not implemented
anywhere, remove their declaration from the header.

Signed-off-by: Liviu Dudau 
---
 include/video.h | 6 --
 1 file changed, 6 deletions(-)

diff --git a/include/video.h b/include/video.h
index ddc2eeb5a9..e7fc5c94e2 100644
--- a/include/video.h
+++ b/include/video.h
@@ -198,12 +198,6 @@ void video_set_default_colors(struct video_priv *priv);
 
 /* Video functions */
 
-struct stdio_dev;
-
-intvideo_init(void *videobase);
-void   video_putc(struct stdio_dev *dev, const char c);
-void   video_puts(struct stdio_dev *dev, const char *s);
-
 /**
  * Display a BMP format bitmap on the screen
  *
-- 
2.18.0

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[U-Boot] [PATCH] uclass: Use uclass_foreach_dev() macro instead of open coding

[Liviu Dudau]

Use the uclass_foreach_dev() macro instead of the open coded version.

Signed-off-by: Liviu Dudau 
---
 drivers/core/uclass.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 3113d6a56b..081571951d 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -337,7 +337,7 @@ int uclass_find_device_by_ofnode(enum uclass_id id, ofnode 
node,
if (ret)
return ret;
 
-   list_for_each_entry(dev, >dev_head, uclass_node) {
+   uclass_foreach_dev(dev, uc) {
log(LOGC_DM, LOGL_DEBUG_CONTENT, "  - checking %s\n",
dev->name);
if (ofnode_equal(dev_ofnode(dev), node)) {
-- 
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[U-Boot] [PATCH] include/clk.h: Fix the name of the clock uclass in comment.

[Liviu Dudau]

The comment references a structure name that doesn't exist. Use
the name of the actual uclass.

Signed-off-by: Liviu Dudau 
---
 include/clk.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/clk.h b/include/clk.h
index c0a20cd47a..8e366163f9 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -21,7 +21,7 @@
  *
  * A driver that implements UCLASS_CLOCK is a clock provider. A provider will
  * often implement multiple separate clocks, since the hardware it manages
- * often has this capability. clock_uclass.h describes the interface which
+ * often has this capability. clk-uclass.h describes the interface which
  * clock providers must implement.
  *
  * Clock consumers/clients are the HW modules driven by the clock signals. This
-- 
2.18.0

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Re: [U-Boot] [PATCH v2 2/2] rockchip: use spl_early_init instead of spl_init

[Liviu Dudau]

On Tue, Mar 14, 2017 at 04:18:45PM -0600, Simon Glass wrote:
> Hi,
> 
> On 14 March 2017 at 16:13, Liviu Dudau <li...@dudau.co.uk> wrote:
> > On Tue, Mar 14, 2017 at 01:54:41PM -0600, Simon Glass wrote:
> >> From: Eddie Cai <eddie.cai.li...@gmail.com>
> >>
> >> use spl_early_init to avoid malloc_base, limit, ptr not initualized.
> >>
> >> Signed-off-by: Eddie Cai <eddie.cai.li...@gmail.com>
> >> Signed-off-by: Simon Glass <s...@chromium.org>
> >> ---
> >>
> >> Changes in v2:
> >> - Add v2 to the series since this is a new version
> >
> > Hi Simon,
> >
> > If you are doing this and spending the time to respin, can I suggest
> > that you improve the readability of this commit message and
> > s/initualized/initialized/ as a spell fix?
> >
> > Also, now that I'm bikeshedding: the first commit message in the
> > series makes reference to "below patch" and one needs to read the
> > Fixes line to figure out which patch is referred. Linux kernel's
> > convention is to name the patch's sha1 directly.
> 
> OK I'll tidy these two commit messages up a little more.

Cheers, I'll look at v4 tonight when I can get access to my Firefly and give my 
feedback.

> 
> >
> > I'm trying to boot Firefly RK3288 Plus with v2017.03 without success.
> > I've applied this series and it made no difference. I have also
> > removed CONFIG_SPL_OF_PLATDATA from firefly-rk3288_defconfig (otherwise
> > doc/README.rockchip makes no sense because there is no 
> > spl/u-boot-spl-dtb.bin
> > and spl/u-boot-spl.bin is the same as spl/u-boot-spl-nodtb.bin), without
> > any success.
> >
> > So, for what is worth, you can also add my Tested-by: Liviu Dudau 
> > <li...@dudau.co.uk>
> 
> For my testing I enable CONFIG_SPL_OF_PLATDATA and disable
> CONFIG_ROCKCHIP_SPL_BACK_TO_BROM.
> 
> How are you creating the SD card (or whatever you boot from)?

Yeah, that was something that I screwed up, but found the solution. In the end 
I went with
CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y and CONFIG_SPL_OF_PLATDATA=n, but that also 
needs
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=n otherwise (I guess) SPL still 
wants to load u-boot.

Now I have an RK3288 SD card that boots on both Firefly and (surprisingly) some 
TV box that I have
(Kingnovel K-R68 or just R6, both names been used by the sellers). I have this 
patch applied though,
so I need to go back and test without it to see if it makes any difference.

Best regards,
Liviu

> 
> Regards,
> Simon
> 
> >
> > Best regards,
> > Liviu
> >
> >>
> >>  arch/arm/mach-rockchip/rk3288-board-spl.c | 2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c 
> >> b/arch/arm/mach-rockchip/rk3288-board-spl.c
> >> index e51e19bb2d..f494843663 100644
> >> --- a/arch/arm/mach-rockchip/rk3288-board-spl.c
> >> +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
> >> @@ -185,7 +185,7 @@ void board_init_f(ulong dummy)
> >>   debug_uart_init();
> >>  #endif
> >>
> >> - ret = spl_init();
> >> + ret = spl_early_init();
> >>   if (ret) {
> >>   debug("spl_init() failed: %d\n", ret);
> >>   hang();
> >> --
> >> 2.12.0.367.g23dc2f6d3c-goog
> >>
> >> ___
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> >> U-Boot@lists.denx.de
> >> https://lists.denx.de/listinfo/u-boot
> >
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Re: [U-Boot] [PATCH v2 2/2] rockchip: use spl_early_init instead of spl_init

[Liviu Dudau]

On Tue, Mar 14, 2017 at 01:54:41PM -0600, Simon Glass wrote:
> From: Eddie Cai <eddie.cai.li...@gmail.com>
> 
> use spl_early_init to avoid malloc_base, limit, ptr not initualized.
> 
> Signed-off-by: Eddie Cai <eddie.cai.li...@gmail.com>
> Signed-off-by: Simon Glass <s...@chromium.org>
> ---
> 
> Changes in v2:
> - Add v2 to the series since this is a new version

Hi Simon,

If you are doing this and spending the time to respin, can I suggest
that you improve the readability of this commit message and
s/initualized/initialized/ as a spell fix?

Also, now that I'm bikeshedding: the first commit message in the
series makes reference to "below patch" and one needs to read the
Fixes line to figure out which patch is referred. Linux kernel's 
convention is to name the patch's sha1 directly.

I'm trying to boot Firefly RK3288 Plus with v2017.03 without success.
I've applied this series and it made no difference. I have also
removed CONFIG_SPL_OF_PLATDATA from firefly-rk3288_defconfig (otherwise
doc/README.rockchip makes no sense because there is no spl/u-boot-spl-dtb.bin
and spl/u-boot-spl.bin is the same as spl/u-boot-spl-nodtb.bin), without
any success.

So, for what is worth, you can also add my Tested-by: Liviu Dudau 
<li...@dudau.co.uk>

Best regards,
Liviu

> 
>  arch/arm/mach-rockchip/rk3288-board-spl.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c 
> b/arch/arm/mach-rockchip/rk3288-board-spl.c
> index e51e19bb2d..f494843663 100644
> --- a/arch/arm/mach-rockchip/rk3288-board-spl.c
> +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
> @@ -185,7 +185,7 @@ void board_init_f(ulong dummy)
>   debug_uart_init();
>  #endif
>  
> - ret = spl_init();
> + ret = spl_early_init();
>   if (ret) {
>   debug("spl_init() failed: %d\n", ret);
>   hang();
> -- 
> 2.12.0.367.g23dc2f6d3c-goog
> 
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Re: [U-Boot] [PATCH] vexpress64: Juno: Change PCI buss addresses for IO to start from zero.

[Liviu Dudau]

On Tue, Nov 22, 2016 at 11:29:20AM +, Sudeep Holla wrote:
> Hi Liviu,
> 
> On Tue, Nov 22, 2016 at 11:19 AM, Liviu Dudau <liviu.du...@foss.arm.com> 
> wrote:
> > Juno uses a 1:1 mapping between CPU and PCI addresses for IO. First,
> > that will trip devices that cannot use more than 16 bits of addresses
> > for IO, second it is un-necessary as the system can handle zero-based
> > PCI addresses just fine.
> >
> > Change the mapping to start IO bus addresses from zero.
> >
> 
> I assume this require corresponding DT change, shout if that's not true.
> If that's true, then does this patch not require patching of DT so
> that systems not
> running Uboot with this patch continue to work and we retain the
> mainline DT as is ?

Yes, it does require DT changes, Jeremy Linton has a patch 

> 
> --
> Regards,
> Sudeep

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[U-Boot] [PATCH] vexpress64: Juno: Change PCI buss addresses for IO to start from zero.

[Liviu Dudau]

Juno uses a 1:1 mapping between CPU and PCI addresses for IO. First,
that will trip devices that cannot use more than 16 bits of addresses
for IO, second it is un-necessary as the system can handle zero-based
PCI addresses just fine.

Change the mapping to start IO bus addresses from zero.

Signed-off-by: Liviu Dudau <liviu.du...@foss.arm.com>
---
 board/armltd/vexpress64/pcie.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c
index b3fb09c..0608a5a 100644
--- a/board/armltd/vexpress64/pcie.c
+++ b/board/armltd/vexpress64/pcie.c
@@ -123,7 +123,7 @@ void xr3pci_setup_atr(void)
base += XR3PCI_ATR_TABLE_SIZE;
 
/* setup IO space translation */
-   xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, XR3_PCI_IOSPACE_START,
+   xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, 0,
 XR3_PCI_IOSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_IO);
 
base += XR3PCI_ATR_TABLE_SIZE;
-- 
2.10.2

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Re: [U-Boot] [PATCH] vexpress64: use 2nd DRAM bank only on juno

[Liviu Dudau]

On Fri, Oct 23, 2015 at 04:47:04PM +0100, Ryan Harkin wrote:
> This patch makes the 2nd DRAM bank available on Juno only and not on
> other vexpress64 targets, eg. the FVP models.
> 
> The commit below added a 2nd bank of NOR flash for Juno, but also for
> all vexpress64 targets:
> 
> commit 2d0cee1ca2b9d977fa3214896bb2e30cfec77059
> Author: Liviu Dudau <liviu.du...@foss.arm.com>
> Date:   Mon Oct 19 11:08:31 2015 +0100
> 
> vexpress64: Juno: Declare all 8GB of RAM and make them visible to the 
> kernel.
> 
> Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
> Declare a secondary memory bank and set the sizes correctly.
> 
> Signed-off-by: Liviu Dudau <liviu.du...@foss.arm.com>
> Reviewed-by: Linus Walleij <linus.wall...@linaro.org>
> Reviewed-by: Ryan Harkin <ryan.har...@linaro.org>
> Tested-by: Ryan Harkin <ryan.har...@linaro.org>
> 
> Unfortunately, I only fully tested on Juno R0, R1 and the FVP Foundation
> model.  Whilst FVP Base AEMV8 models run U-Boot OK, they fail to boot
> the kernel.

Hi Ryan,

Thanks for testing this on FVPs. Only a small question on the patch, otherwise:

Acked-by: Liviu Dudau <liviu.du...@foss.arm.com>

Best regards,
Liviu

> 
> Signed-off-by: Ryan Harkin <ryan.har...@linaro.org>
> ---
>  board/armltd/vexpress64/vexpress64.c |  2 ++
>  include/configs/vexpress_aemv8a.h| 13 ++---
>  2 files changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/board/armltd/vexpress64/vexpress64.c 
> b/board/armltd/vexpress64/vexpress64.c
> index f4e8084..22d7e6c 100644
> --- a/board/armltd/vexpress64/vexpress64.c
> +++ b/board/armltd/vexpress64/vexpress64.c
> @@ -44,8 +44,10 @@ void dram_init_banksize(void)
>  {
>   gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
>   gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> +#ifdef PHYS_SDRAM_2
>   gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
>   gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
> +#endif
>  }
>  
>  /*
> diff --git a/include/configs/vexpress_aemv8a.h 
> b/include/configs/vexpress_aemv8a.h
> index 0f2f1a3..18ab915 100644
> --- a/include/configs/vexpress_aemv8a.h
> +++ b/include/configs/vexpress_aemv8a.h
> @@ -168,15 +168,22 @@
>  #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x1000)
>  
>  /* Physical Memory Map */
> -#define CONFIG_NR_DRAM_BANKS 2
>  #define PHYS_SDRAM_1 (V2M_BASE)  /* SDRAM Bank #1 */
> -#define PHYS_SDRAM_2 (0x88000)
>  /* Top 16MB reserved for secure world use */
>  #define DRAM_SEC_SIZE0x0100
>  #define PHYS_SDRAM_1_SIZE0x8000 - DRAM_SEC_SIZE
> -#define PHYS_SDRAM_2_SIZE0x18000
>  #define CONFIG_SYS_SDRAM_BASEPHYS_SDRAM_1
>  
> +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
> +#define CONFIG_NR_DRAM_BANKS 2
> +#define PHYS_SDRAM_2 (0x88000)
> +#define PHYS_SDRAM_2_SIZE0x18000
> +#define CONFIG_NR_DRAM_BANKS_LIST{ PHYS_SDRAM_1 , PHYS_SDRAM_2}

Here

> +#else
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define CONFIG_NR_DRAM_BANKS_LIST{ PHYS_SDRAM_1 }

And here. I could not find any other instance of CONFIG_NR_DRAM_BANKS_LIST 
usage. Is that something
that has splilled from Linaro's version?

Best regards,
Liviu

> +#endif
> +
>  /* Enable memtest */
>  #define CONFIG_CMD_MEMTEST
>  #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
> -- 
> 2.1.4
> 

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[U-Boot] [PATCH v3 2/2] vexpress64: Juno: Add initialisation code for Juno R1 PCIe host bridge.

[Liviu Dudau]

Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
in order for the Linux kernel to be able to enumerate the bus. Add
support code here that enables the host bridge, trains the links and
sets up the Address Translation Tables.

Signed-off-by: Liviu Dudau <liviu.du...@foss.arm.com>
Tested-by: Ryan Harkin <ryan.har...@linaro.org>
---
 board/armltd/vexpress64/Makefile |   2 +-
 board/armltd/vexpress64/pcie.c   | 197 +++
 board/armltd/vexpress64/pcie.h   |  12 +++
 board/armltd/vexpress64/vexpress64.c |   2 +
 4 files changed, 212 insertions(+), 1 deletion(-)
 create mode 100644 board/armltd/vexpress64/pcie.c
 create mode 100644 board/armltd/vexpress64/pcie.h

diff --git a/board/armltd/vexpress64/Makefile b/board/armltd/vexpress64/Makefile
index e009141..a35db40 100644
--- a/board/armltd/vexpress64/Makefile
+++ b/board/armltd/vexpress64/Makefile
@@ -5,4 +5,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  := vexpress64.o
+obj-y  := vexpress64.o pcie.o
diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c
new file mode 100644
index 000..7b999e8
--- /dev/null
+++ b/board/armltd/vexpress64/pcie.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) ARM Ltd 2015
+ *
+ * Author: Liviu Dudau <liviu.du...@arm.com>
+ *
+ * SPDX-Licence-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include "pcie.h"
+
+/* XpressRICH3 support */
+#define XR3_CONFIG_BASE0x7ff3
+#define XR3_RESET_BASE 0x7ff2
+
+#define XR3_PCI_ECAM_START 0x4000
+#define XR3_PCI_ECAM_SIZE  28  /* as power of 2 = 0x1000 */
+#define XR3_PCI_IOSPACE_START  0x5f80
+#define XR3_PCI_IOSPACE_SIZE   23  /* as power of 2 = 0x80 */
+#define XR3_PCI_MEMSPACE_START 0x5000
+#define XR3_PCI_MEMSPACE_SIZE  27  /* as power of 2 = 0x800 */
+#define XR3_PCI_MEMSPACE64_START   0x40
+#define XR3_PCI_MEMSPACE64_SIZE33  /* as power of 2 = 
0x2 */
+
+#define JUNO_V2M_MSI_START 0x2c1c
+#define JUNO_V2M_MSI_SIZE  12  /* as power of 2 = 4096 */
+
+#define XR3PCI_BASIC_STATUS0x18
+#define XR3PCI_BS_GEN_MASK (0xf << 8)
+#define XR3PCI_BS_LINK_MASK0xff
+
+#define XR3PCI_VIRTCHAN_CREDITS0x90
+#define XR3PCI_BRIDGE_PCI_IDS  0x9c
+#define XR3PCI_PEX_SPC20xd8
+
+#define XR3PCI_ATR_PCIE_WIN0   0x600
+#define XR3PCI_ATR_PCIE_WIN1   0x700
+#define XR3PCI_ATR_AXI4_SLV0   0x800
+
+#define XR3PCI_ATR_TABLE_SIZE  0x20
+#define XR3PCI_ATR_SRC_ADDR_LOW0x0
+#define XR3PCI_ATR_SRC_ADDR_HIGH   0x4
+#define XR3PCI_ATR_TRSL_ADDR_LOW   0x8
+#define XR3PCI_ATR_TRSL_ADDR_HIGH  0xc
+#define XR3PCI_ATR_TRSL_PARAM  0x10
+
+/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
+#define XR3PCI_ATR_TRSLID_AXIDEVICE(0x420004)
+#define XR3PCI_ATR_TRSLID_AXIMEMORY(0x4e0004)  /* Write-through, 
read/write allocate */
+#define XR3PCI_ATR_TRSLID_PCIE_CONF(0x01)
+#define XR3PCI_ATR_TRSLID_PCIE_IO  (0x02)
+#define XR3PCI_ATR_TRSLID_PCIE_MEMORY  (0x00)
+
+#define XR3PCI_ECAM_OFFSET(b, d, o)(((b) << 20) | \
+   (PCI_SLOT(d) << 15) | \
+   (PCI_FUNC(d) << 12) | o)
+
+#define JUNO_RESET_CTRL0x1004
+#define JUNO_RESET_CTRL_PHYBIT(0)
+#define JUNO_RESET_CTRL_RC BIT(1)
+
+#define JUNO_RESET_STATUS  0x1008
+#define JUNO_RESET_STATUS_PLL  BIT(0)
+#define JUNO_RESET_STATUS_PHY  BIT(1)
+#define JUNO_RESET_STATUS_RC   BIT(2)
+#define JUNO_RESET_STATUS_MASK (JUNO_RESET_STATUS_PLL | \
+JUNO_RESET_STATUS_PHY | \
+JUNO_RESET_STATUS_RC)
+
+void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
+   unsigned long trsl_addr, int window_size,
+   int trsl_param)
+{
+   /* X3PCI_ATR_SRC_ADDR_LOW:
+- bit 0: enable entry,
+- bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
+- bits 7-11: reserved
+- bits 12-31: start of source address
+   */
+   writel((u32)(src_addr & 0xf000) | (window_size - 1) << 1 | 1,
+  base + XR3PCI_ATR_SRC_ADDR_LOW);
+   writel((u32)(src_addr >> 32), base + XR3PCI_ATR_SRC_ADDR_HIGH);
+   writel((u32)(trsl_addr & 0xf000), base + XR3PCI_ATR_TRSL_ADDR_LOW);
+   writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
+   writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
+
+   printf("ATR entry: 0x%010lx %s 0x%01

[U-Boot] [PATCH v3 1/2] vexpress64: Juno: Declare all 8GB of RAM and make them visible to the kernel.

[Liviu Dudau]

Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
Declare a secondary memory bank and set the sizes correctly.

Signed-off-by: Liviu Dudau <liviu.du...@foss.arm.com>
Reviewed-by: Linus Walleij <linus.wall...@linaro.org>
Reviewed-by: Ryan Harkin <ryan.har...@linaro.org>
Tested-by: Ryan Harkin <ryan.har...@linaro.org>
---
 board/armltd/vexpress64/vexpress64.c | 8 
 include/configs/vexpress_aemv8a.h| 4 +++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/board/armltd/vexpress64/vexpress64.c 
b/board/armltd/vexpress64/vexpress64.c
index 7cb4e00..6df9d60 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -38,6 +38,14 @@ int dram_init(void)
return 0;
 }
 
+void dram_init_banksize(void)
+{
+   gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+   gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+   gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+   gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
 /*
  * Board specific reset that is system reset.
  */
diff --git a/include/configs/vexpress_aemv8a.h 
b/include/configs/vexpress_aemv8a.h
index ef3014d..0f2f1a3 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -168,11 +168,13 @@
 #define CONFIG_SYS_LOAD_ADDR   (V2M_BASE + 0x1000)
 
 /* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS   1
+#define CONFIG_NR_DRAM_BANKS   2
 #define PHYS_SDRAM_1   (V2M_BASE)  /* SDRAM Bank #1 */
+#define PHYS_SDRAM_2   (0x88000)
 /* Top 16MB reserved for secure world use */
 #define DRAM_SEC_SIZE  0x0100
 #define PHYS_SDRAM_1_SIZE  0x8000 - DRAM_SEC_SIZE
+#define PHYS_SDRAM_2_SIZE  0x18000
 #define CONFIG_SYS_SDRAM_BASE  PHYS_SDRAM_1
 
 /* Enable memtest */
-- 
2.6.0

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[U-Boot] [PATCH v3 0/2] vexpress64: Juno: Add support for PCIe on Juno

[Liviu Dudau]

Hello,

This patchset enables PCIe for ARM's Juno boards and configures the
host bridge's address translation block. This enables the Linux kernel
to boot on Juno r1 using just a device tree and the generic host bridge
driver.

No support has been added at this phase for the SATA or Ethernet devices
present on the PCIe bus.

Changelog:
 - v3: Fix the error reported by Ryan Harkin on setting the virtual channel
   credits.
 - v3: fixed the check_patch.pl warnings on blank lines and use BIT() macro
 - v3: change from udelay() to mdelay()
 - v3: spelling fixes
 - v2: Split XpressRICH3 code into pcie.c file and introduce 
vexpress64_pcie_init()
   that can be called from board_init(). Suggested by Linus Walleij.
 - v2: Set up the XpressRICH3 bridge class code to a valid value to correct the
   incorrect reset value.
 - v1: Original submission 
http://lists.denx.de/pipermail/u-boot/2015-October/229669.html

Liviu Dudau (2):
  vexpress64: Juno: Declare all 8GB of RAM and make them visible to the kernel.
  vexpress64: Juno: Add initialisation code for Juno R1 PCIe host bridge.

 board/armltd/vexpress64/Makefile |   2 +-
 board/armltd/vexpress64/pcie.c   | 197 +++
 board/armltd/vexpress64/pcie.h   |  12 +++
 board/armltd/vexpress64/vexpress64.c |  10 ++
 include/configs/vexpress_aemv8a.h|   4 +-
 5 files changed, 223 insertions(+), 2 deletions(-)
 create mode 100644 board/armltd/vexpress64/pcie.c
 create mode 100644 board/armltd/vexpress64/pcie.h

-- 
2.6.0

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Re: [U-Boot] [PATCH v2 2/2] vexpress64: Juno: Add initialisation code for Juno R1 PCIe host bridge.

[Liviu Dudau]

On Fri, 16 Oct 2015 17:58:44 +0100
Ryan Harkin <ryan.har...@linaro.org> wrote:

> Hi Liviu,
> 
> These patches work well for me, so at the very least, you can add my
> Test-by for both:
> 
> Tested-by: Ryan Harkin <ryan.har...@linaro.org>

Hi Ryan,

Thanks for testing this patchset.

> 
> But...
> 
> I ran checkpatch.pl across your patches and this one throws a few trivial
> warnings, mostly about 80 character lines and a few like this:
> 
> CHECK: Prefer using the BIT macro
> #97: FILE: board/armltd/vexpress64/pcie.c:60:
> +#define JUNO_RESET_CTRL_PHY(1 << 0)
> 
> But also these:
> 
> WARNING: long udelay - prefer mdelay; see arch/arm/include/asm/delay.h
> #208: FILE: board/armltd/vexpress64/pcie.c:171:
> +udelay(2);
> 
> CHECK: Please don't use multiple blank lines
> #227: FILE: board/armltd/vexpress64/pcie.c:190:
> +
> +
> 
> CHECK: Please don't use multiple blank lines
> #251: FILE: board/armltd/vexpress64/pcie.h:12:
> +
> +

Interesting, when running ./scripts/checkpatch.pl in my copy of U-Boot I
get the 7 warnings about lines over 80 characters long, and the
following message:

NOTE: Ignored message types: COMPLEX_MACRO CONSIDER_KSTRTO MINMAX 
MULTISTATEMENT_MACRO_USE_DO_WHILE NETWORKING_BLOCK_COMMENT_STYLE USLEEP_RANGE

Not sure how to enable all the types by default and also the reason why
I've missed them.

> 
> I'm not sure who strict the rules are followed for these types of warning.
> But if you are fixing up, I also noticed a couple of whitespace nits below.
> 
> 
> On 16 October 2015 at 15:41, Liviu Dudau <liviu.du...@foss.arm.com> wrote:
> 
> > Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
> > in order for the Linux kernel to be able to enumerate the bus. Add
> > support code here that enables the host bridge, trains the links and
> > sets up the Address Translation Tables.
> >
> > Signed-off-by: Liviu Dudau <liviu.du...@foss.arm.com>
> > ---
> >  board/armltd/vexpress64/Makefile |   2 +-
> >  board/armltd/vexpress64/pcie.c   | 196
> > +++
> >  board/armltd/vexpress64/pcie.h   |  13 +++
> >  board/armltd/vexpress64/vexpress64.c |   2 +
> >  4 files changed, 212 insertions(+), 1 deletion(-)
> >  create mode 100644 board/armltd/vexpress64/pcie.c
> >  create mode 100644 board/armltd/vexpress64/pcie.h
> >
> > diff --git a/board/armltd/vexpress64/Makefile
> > b/board/armltd/vexpress64/Makefile
> > index e009141..a35db40 100644
> > --- a/board/armltd/vexpress64/Makefile
> > +++ b/board/armltd/vexpress64/Makefile
> > @@ -5,4 +5,4 @@
> >  # SPDX-License-Identifier: GPL-2.0+
> >  #
> >
> > -obj-y  := vexpress64.o
> > +obj-y  := vexpress64.o pcie.o
> > diff --git a/board/armltd/vexpress64/pcie.c
> > b/board/armltd/vexpress64/pcie.c
> > new file mode 100644
> > index 000..367efd4
> > --- /dev/null
> > +++ b/board/armltd/vexpress64/pcie.c
> > @@ -0,0 +1,196 @@
> > +/*
> > + * Copyright (C) ARM Ltd 2015
> > + *
> > + * Author: Liviu Dudau <liviu.du...@arm.com>
> > + *
> > + * SPDX-Licence-Identifier:GPL-2.0+
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include "pcie.h"
> > +
> > +/* XpressRICH3 support */
> > +#define XR3_CONFIG_BASE0x7ff3
> > +#define XR3_RESET_BASE 0x7ff2
> > +
> > +#define XR3_PCI_ECAM_START 0x4000
> > +#define XR3_PCI_ECAM_SIZE  28  /* as power of 2 =
> > 0x1000 */
> > +#define XR3_PCI_IOSPACE_START  0x5f80
> > +#define XR3_PCI_IOSPACE_SIZE   23  /* as power of 2 =
> > 0x80 */
> > +#define XR3_PCI_MEMSPACE_START 0x5000
> > +#define XR3_PCI_MEMSPACE_SIZE  27  /* as power of 2 =
> > 0x800 */
> > +#define XR3_PCI_MEMSPACE64_START   0x40
> > +#define XR3_PCI_MEMSPACE64_SIZE33  /* as power of 2 =
> > 0x2 */
> > +
> > +#define JUNO_V2M_MSI_START 0x2c1c
> > +#define JUNO_V2M_MSI_SIZE  12  /* as power of 2 = 4096 */
> > +
> > +#define XR3PCI_BASIC_STATUS0x18
> > +#defineXR3PCI_BS_GEN_MASK  (0xf << 8)
> > +#defineXR3PCI_BS_LINK_MASK 0xff
> >
> 
> There's some strange extra whitespace in there...
> 
> +
> > +#define XR3PCI_VIRTCHAN_CREDITS0x90
> > +#define XR3PCI_BRIDGE_PCI_IDS  0x9c
> > +

[U-Boot] [PATCH v2 2/2] vexpress64: Juno: Add initialisation code for Juno R1 PCIe host bridge.

[Liviu Dudau]

Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
in order for the Linux kernel to be able to enumerate the bus. Add
support code here that enables the host bridge, trains the links and
sets up the Address Translation Tables.

Signed-off-by: Liviu Dudau <liviu.du...@foss.arm.com>
---
 board/armltd/vexpress64/Makefile |   2 +-
 board/armltd/vexpress64/pcie.c   | 196 +++
 board/armltd/vexpress64/pcie.h   |  13 +++
 board/armltd/vexpress64/vexpress64.c |   2 +
 4 files changed, 212 insertions(+), 1 deletion(-)
 create mode 100644 board/armltd/vexpress64/pcie.c
 create mode 100644 board/armltd/vexpress64/pcie.h

diff --git a/board/armltd/vexpress64/Makefile b/board/armltd/vexpress64/Makefile
index e009141..a35db40 100644
--- a/board/armltd/vexpress64/Makefile
+++ b/board/armltd/vexpress64/Makefile
@@ -5,4 +5,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  := vexpress64.o
+obj-y  := vexpress64.o pcie.o
diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c
new file mode 100644
index 000..367efd4
--- /dev/null
+++ b/board/armltd/vexpress64/pcie.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright (C) ARM Ltd 2015
+ *
+ * Author: Liviu Dudau <liviu.du...@arm.com>
+ *
+ * SPDX-Licence-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include "pcie.h"
+
+/* XpressRICH3 support */
+#define XR3_CONFIG_BASE0x7ff3
+#define XR3_RESET_BASE 0x7ff2
+
+#define XR3_PCI_ECAM_START 0x4000
+#define XR3_PCI_ECAM_SIZE  28  /* as power of 2 = 0x1000 */
+#define XR3_PCI_IOSPACE_START  0x5f80
+#define XR3_PCI_IOSPACE_SIZE   23  /* as power of 2 = 0x80 */
+#define XR3_PCI_MEMSPACE_START 0x5000
+#define XR3_PCI_MEMSPACE_SIZE  27  /* as power of 2 = 0x800 */
+#define XR3_PCI_MEMSPACE64_START   0x40
+#define XR3_PCI_MEMSPACE64_SIZE33  /* as power of 2 = 
0x2 */
+
+#define JUNO_V2M_MSI_START 0x2c1c
+#define JUNO_V2M_MSI_SIZE  12  /* as power of 2 = 4096 */
+
+#define XR3PCI_BASIC_STATUS0x18
+#defineXR3PCI_BS_GEN_MASK  (0xf << 8)
+#defineXR3PCI_BS_LINK_MASK 0xff
+
+#define XR3PCI_VIRTCHAN_CREDITS0x90
+#define XR3PCI_BRIDGE_PCI_IDS  0x9c
+#define XR3PCI_PEX_SPC20xd8
+
+#define XR3PCI_ATR_PCIE_WIN0   0x600
+#define XR3PCI_ATR_PCIE_WIN1   0x700
+#define XR3PCI_ATR_AXI4_SLV0   0x800
+
+#define XR3PCI_ATR_TABLE_SIZE  0x20
+#define XR3PCI_ATR_SRC_ADDR_LOW0x0
+#define XR3PCI_ATR_SRC_ADDR_HIGH   0x4
+#define XR3PCI_ATR_TRSL_ADDR_LOW   0x8
+#define XR3PCI_ATR_TRSL_ADDR_HIGH  0xc
+#define XR3PCI_ATR_TRSL_PARAM  0x10
+/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
+#define XR3PCI_ATR_TRSLID_AXIDEVICE(0x420004)
+#define XR3PCI_ATR_TRSLID_AXIMEMORY(0x4e0004)  /* Write-through, 
read/write allocate */
+#define XR3PCI_ATR_TRSLID_PCIE_CONF(0x01)
+#define XR3PCI_ATR_TRSLID_PCIE_IO  (0x02)
+#define XR3PCI_ATR_TRSLID_PCIE_MEMORY  (0x00)
+
+#define XR3PCI_ECAM_OFFSET(b, d, o)(((b) << 20) | \
+   (PCI_SLOT(d) << 15) | \
+   (PCI_FUNC(d) << 12) | o)
+
+#define JUNO_RESET_CTRL0x1004
+#define JUNO_RESET_CTRL_PHY(1 << 0)
+#define JUNO_RESET_CTRL_RC (1 << 1)
+
+#define JUNO_RESET_STATUS  0x1008
+#define JUNO_RESET_STATUS_PLL  (1 << 0)
+#define JUNO_RESET_STATUS_PHY  (1 << 1)
+#define JUNO_RESET_STATUS_RC   (1 << 2)
+#define JUNO_RESET_STATUS_MASK (JUNO_RESET_STATUS_PLL | \
+JUNO_RESET_STATUS_PHY | \
+JUNO_RESET_STATUS_RC)
+
+void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
+   unsigned long trsl_addr, int window_size,
+   int trsl_param)
+{
+   /* X3PCI_ATR_SRC_ADDR_LOW:
+- bit 0: enable entry,
+- bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
+- bits 7-11: reserved
+- bits 12-31: start of source address
+   */
+   writel((u32)(src_addr & 0xf000) | (window_size - 1) << 1 | 1,
+  base + XR3PCI_ATR_SRC_ADDR_LOW);
+   writel((u32)(trsl_addr & 0xf000), base + XR3PCI_ATR_TRSL_ADDR_LOW);
+   writel((u32)(src_addr >> 32), base + XR3PCI_ATR_SRC_ADDR_HIGH);
+   writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
+   writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
+
+   printf("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n",
+

[U-Boot] [PATCH v2 0/2] vexpress64: Juno: Add support for PCIe on Juno

[Liviu Dudau]

Hello,

This patchset enables PCIe for ARM's Juno boards and configures the
host bridge's address translation block. This enables the Linux kernel
to boot on Juno r1 using just a device tree and the generic host bridge
driver.

No support has been added at this phase for the SATA or Ethernet devices
present on the PCIe bus.

Changelog:
 - v2: Split XpressRICH3 code into pcie.c file and introduce 
vexpress64_pcie_init()
   that can be called from board_init(). Suggested by Linus Walleij.
 - v2: Set up the XpressRICH3 bridge class code to a valid value to correct the
   incorrect reset value.
 - v1: Original submission 
http://lists.denx.de/pipermail/u-boot/2015-October/229669.html

Liviu Dudau (2):
  vexpress64: Juno: Declare all 8GB of RAM and make them visible to the kernel.
  vexpress64: Juno: Add initialisation code for Juno R1 PCIe host bridge.

 board/armltd/vexpress64/Makefile |   2 +-
 board/armltd/vexpress64/pcie.c   | 196 +++
 board/armltd/vexpress64/pcie.h   |  13 +++
 board/armltd/vexpress64/vexpress64.c |  10 ++
 include/configs/vexpress_aemv8a.h|   4 +-
 5 files changed, 223 insertions(+), 2 deletions(-)
 create mode 100644 board/armltd/vexpress64/pcie.c
 create mode 100644 board/armltd/vexpress64/pcie.h

-- 
2.6.0

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[U-Boot] [PATCH v2 1/2] vexpress64: Juno: Declare all 8GB of RAM and make them visible to the kernel.

[Liviu Dudau]

Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
Declare a secondary memory bank and set the sizes correctly.

Signed-off-by: Liviu Dudau <liviu.du...@foss.arm.com>
Reviewed-by: Linus Walleij <linus.wall...@linaro.org>
---
 board/armltd/vexpress64/vexpress64.c | 8 
 include/configs/vexpress_aemv8a.h| 4 +++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/board/armltd/vexpress64/vexpress64.c 
b/board/armltd/vexpress64/vexpress64.c
index 7cb4e00..6df9d60 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -38,6 +38,14 @@ int dram_init(void)
return 0;
 }
 
+void dram_init_banksize(void)
+{
+   gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+   gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+   gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+   gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
 /*
  * Board specific reset that is system reset.
  */
diff --git a/include/configs/vexpress_aemv8a.h 
b/include/configs/vexpress_aemv8a.h
index ef3014d..0f2f1a3 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -168,11 +168,13 @@
 #define CONFIG_SYS_LOAD_ADDR   (V2M_BASE + 0x1000)
 
 /* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS   1
+#define CONFIG_NR_DRAM_BANKS   2
 #define PHYS_SDRAM_1   (V2M_BASE)  /* SDRAM Bank #1 */
+#define PHYS_SDRAM_2   (0x88000)
 /* Top 16MB reserved for secure world use */
 #define DRAM_SEC_SIZE  0x0100
 #define PHYS_SDRAM_1_SIZE  0x8000 - DRAM_SEC_SIZE
+#define PHYS_SDRAM_2_SIZE  0x18000
 #define CONFIG_SYS_SDRAM_BASE  PHYS_SDRAM_1
 
 /* Enable memtest */
-- 
2.6.0

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Re: [U-Boot] [PATCH 2/2] vexpress64: Juno: Add initialisation code for Juno R1 PCIe host bridge.

[Liviu Dudau]

On Thu, 15 Oct 2015 16:42:19 +0200
Linus Walleij <linus.wall...@linaro.org> wrote:

> On Fri, Oct 9, 2015 at 3:09 PM, Liviu Dudau <liviu.du...@foss.arm.com> wrote:
> 
> > Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
> > in order for the Linux kernel to be able to enumerate the bus. Add
> > support code here that enables the host bridge, trains the links and
> > sets up the Address Translation Tables.
> >
> > Signed-off-by: Liviu Dudau <liviu.du...@foss.arm.com>
> 
> Very nice! Now we (soon) have PCIe on the Juno.
> 
> Did you:
> 
> - Test with compiling in e.g. network cards and booting off of
>   ethernet on PCIe?
> 
> - Test what happens with a simple VGA card on PCIe?
>   Sometimes the VGA card BIOS need to be initialized using
>   an emulator running the x86 ROM and I never got that working
>   on anything ARM :( (Maybe PCIe doesn't suffer from this? Just
>   vanilla PCI has this problem? What do I know.)

Hi Linus,

Please note that this patchset does not enable enough functionality in
U-Boot to allow for PCIe testing.

However, together with my Linux patchset series[1] I have tested U-Boot
plus mainline Linux v4.3-rc5 on Juno r1 with 3x USB-to-PCIe cards and
a Radeon HD6400 card. I have even got framebuffer out of the Radeon
card :)


> 
> > +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
> > +void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
> > +   unsigned long trsl_addr, int window_size,
> > +   int trsl_param)
> > +{
> (...)
> >  int board_init(void)
> >  {
> > +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
> (...)
> > +#endif
> > return 0;
> >  }
> 
> > +++ b/board/armltd/vexpress64/vexpress64.h
> > @@ -0,0 +1,60 @@
> > +#ifndef __VEXPRESS64_H__
> > +#define __VEXPRESS64_H__
> 
> Instead of peppering with #ifdefs I suggest you do like this:
> 
> - Create two new files named
>   board/armltd/vexpress64/pcie.c
>   board/armltd/vexpress64/pcie.h
> 
> - Move all the #defines from the vexpress64.h file into
>   the top of the pcie.c file.
> 
> - Use the pcie.h file for prototypes + stubs like this:
> 
> #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
> void vexpress64_pcie_init(void);
> #else
> static inline void vexpress64_pcie_init(void)
> {
> }
> #endif
> 
> Then board_init() can unconditionallt call these functions and
> they will be stubbed out if compiled for anything else than Juno.
> 
> Yours,
> Linus Walleij

OK, I will do that. I'm waiting on some feedback from Ryan Harkin that
wanted to test the patchset with some Linaro kernels and I will post
a v2.

Best regards,
Liviu


-- 

| I would like to |
| fix the world,  |
| but they're not |
| giving me the   |
 \ source code!  /
  ---
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[U-Boot] [PATCH 2/2] vexpress64: Juno: Add initialisation code for Juno R1 PCIe host bridge.

[Liviu Dudau]

Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
in order for the Linux kernel to be able to enumerate the bus. Add
support code here that enables the host bridge, trains the links and
sets up the Address Translation Tables.

Signed-off-by: Liviu Dudau <liviu.du...@foss.arm.com>
---
 board/armltd/vexpress64/vexpress64.c | 120 +++
 board/armltd/vexpress64/vexpress64.h |  60 ++
 2 files changed, 180 insertions(+)
 create mode 100644 board/armltd/vexpress64/vexpress64.h

diff --git a/board/armltd/vexpress64/vexpress64.c 
b/board/armltd/vexpress64/vexpress64.c
index 6df9d60..a90fa65 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include "vexpress64.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -27,8 +28,127 @@ U_BOOT_DEVICE(vexpress_serials) = {
.platdata = _platdata,
 };
 
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
+   unsigned long trsl_addr, int window_size,
+   int trsl_param)
+{
+   /* X3PCI_ATR_SRC_ADDR_LOW:
+- bit 0: enable entry,
+- bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
+- bits 7-11: reserved
+- bits 12-31: start of source address
+   */
+   writel((u32)(src_addr & 0xf000) | (window_size - 1) << 1 | 1,
+  base + XR3PCI_ATR_SRC_ADDR_LOW);
+   writel((u32)(trsl_addr & 0xf000), base + XR3PCI_ATR_TRSL_ADDR_LOW);
+   writel((u32)(src_addr >> 32), base + XR3PCI_ATR_SRC_ADDR_HIGH);
+   writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
+   writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
+
+   printf("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n",
+  src_addr, (trsl_param & 0x40) ? "<-" : "->", trsl_addr,
+  ((u64)1) << window_size, trsl_param);
+}
+
+void xr3pci_setup_atr(void)
+{
+   /* setup PCIe to CPU address translation tables */
+   unsigned long base = XR3_CONFIG_BASE + XR3PCI_ATR_PCIE_WIN0;
+
+   /* forward all writes from PCIe to GIC V2M (used for MSI) */
+   xr3pci_set_atr_entry(base, JUNO_V2M_MSI_START, JUNO_V2M_MSI_START,
+JUNO_V2M_MSI_SIZE, XR3PCI_ATR_TRSLID_AXIDEVICE);
+
+   base += XR3PCI_ATR_TABLE_SIZE;
+
+   /* PCIe devices can write anywhere in memory */
+   xr3pci_set_atr_entry(base, PHYS_SDRAM_1, PHYS_SDRAM_1,
+31 /* grant access to all RAM under 4GB */,
+XR3PCI_ATR_TRSLID_AXIMEMORY);
+   base += XR3PCI_ATR_TABLE_SIZE;
+   xr3pci_set_atr_entry(base, PHYS_SDRAM_2, PHYS_SDRAM_2,
+XR3_PCI_MEMSPACE64_SIZE,
+XR3PCI_ATR_TRSLID_AXIMEMORY);
+
+
+   /* setup CPU to PCIe address translation table */
+   base = XR3_CONFIG_BASE + XR3PCI_ATR_AXI4_SLV0;
+
+   /* setup ECAM space to bus configuration interface */
+   xr3pci_set_atr_entry(base, XR3_PCI_ECAM_START, 0, XR3_PCI_ECAM_SIZE,
+XR3PCI_ATR_TRSLID_PCIE_CONF);
+
+   base += XR3PCI_ATR_TABLE_SIZE;
+
+   /* setup IO space translation */
+   xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, XR3_PCI_IOSPACE_START,
+XR3_PCI_IOSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_IO);
+
+   base += XR3PCI_ATR_TABLE_SIZE;
+
+   /* setup 32bit MEM space translation */
+   xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE_START, 
XR3_PCI_MEMSPACE_START,
+XR3_PCI_MEMSPACE_SIZE, 
XR3PCI_ATR_TRSLID_PCIE_MEMORY);
+
+   base += XR3PCI_ATR_TABLE_SIZE;
+
+   /* setup 64bit MEM space translation */
+   xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE64_START, 
XR3_PCI_MEMSPACE64_START,
+XR3_PCI_MEMSPACE64_SIZE, 
XR3PCI_ATR_TRSLID_PCIE_MEMORY);
+}
+#endif
+
 int board_init(void)
 {
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+   u32 val;
+   int timeout = 200;
+
+   /* Initialise the XpressRICH3 PCIe host bridge */
+
+   /* add credits */
+   writel(0x00f0b818, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS);
+   writel(0x1, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS);
+   /* allow ECRC */
+   writel(0x6006, XR3_CONFIG_BASE + XR3PCI_PEX_SPC2);
+
+   /* reset phy and root complex */
+   writel(JUNO_RESET_CTRL_PHY | JUNO_RESET_CTRL_RC,
+  XR3_RESET_BASE + JUNO_RESET_CTRL);
+
+   do {
+   udelay(1000);
+   val = readl(XR3_RESET_BASE + JUNO_RESET_STATUS);
+   } while (--timeout &&
+   (val & JUNO_RESET_STATUS_MASK) != JUNO_RESET_STATUS_MASK);
+
+   if (!timeout) {
+   printf("PCI XR3 Root compl

[U-Boot] [PATCH 0/2] vexpress64: Juno: Add support for PCIe on Juno

[Liviu Dudau]

Hello,

This patchset enables PCIe for ARM's Juno boards and configures the
host bridge's address translation block. This enables the Linux kernel
to boot on Juno r1 using just a device tree and the generic host bridge
driver.

No support has been added at this phase for the SATA or Ethernet devices
present on the PCIe bus.

Liviu Dudau (2):
  vexpress64: Juno: Declare all 8GB of RAM and make them visible to the kernel.
  vexpress64: Juno: Add initialisation code for Juno R1 PCIe host bridge.

 board/armltd/vexpress64/vexpress64.c | 128 +++
 board/armltd/vexpress64/vexpress64.h |  60 
 include/configs/vexpress_aemv8a.h|   4 +-
 3 files changed, 191 insertions(+), 1 deletion(-)
 create mode 100644 board/armltd/vexpress64/vexpress64.h

-- 
2.6.0

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[U-Boot] [PATCH 1/2] vexpress64: Juno: Declare all 8GB of RAM and make them visible to the kernel.

[Liviu Dudau]

Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
Declare a secondary memory bank and set the sizes correctly.

Signed-off-by: Liviu Dudau <liviu.du...@foss.arm.com>
---
 board/armltd/vexpress64/vexpress64.c | 8 
 include/configs/vexpress_aemv8a.h| 4 +++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/board/armltd/vexpress64/vexpress64.c 
b/board/armltd/vexpress64/vexpress64.c
index 7cb4e00..6df9d60 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -38,6 +38,14 @@ int dram_init(void)
return 0;
 }
 
+void dram_init_banksize(void)
+{
+   gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+   gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+   gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+   gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
 /*
  * Board specific reset that is system reset.
  */
diff --git a/include/configs/vexpress_aemv8a.h 
b/include/configs/vexpress_aemv8a.h
index 6107c64..f06344a 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -164,11 +164,13 @@
 #define CONFIG_SYS_LOAD_ADDR   (V2M_BASE + 0x1000)
 
 /* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS   1
+#define CONFIG_NR_DRAM_BANKS   2
 #define PHYS_SDRAM_1   (V2M_BASE)  /* SDRAM Bank #1 */
+#define PHYS_SDRAM_2   (0x88000)
 /* Top 16MB reserved for secure world use */
 #define DRAM_SEC_SIZE  0x0100
 #define PHYS_SDRAM_1_SIZE  0x8000 - DRAM_SEC_SIZE
+#define PHYS_SDRAM_2_SIZE  0x18000
 #define CONFIG_SYS_SDRAM_BASE  PHYS_SDRAM_1
 
 /* Enable memtest */
-- 
2.6.0

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Re: [U-Boot] [PATCH v3 09/10] vexpress64: juno: add alternate kernel and device tree filenames

[Liviu Dudau]

Hi Ryan,

On Thu, Oct 01, 2015 at 06:43:35PM +0100, Ryan Harkin wrote:
> The default Juno firmware has renamed the kernel and device tree
> filenames to norkern and board.dtb.
> 
> Rather than change the default configuration to use the new names,
> breaking those with the old firmware, attempt to load the existing
> filename first.  If that fails, attempt to load the alternate filename.

How about future proofing this and add a board.scr image in Juno firmware
where a script can be stored (can the image be used by UEFI as well?).

Now that you are adding support for testing if an image is present we can
then source the script at boot.scr. That would allow Juno r1 for example
to have a different boot script than r0 (smc911x ethernet port was designed
as a backup solution until PCIe was functional, so one might not want to
use it for booting).

Thoughts?

Best regards,
Liviu

> 
> I've echo'd that we are loading the alternate file to counter the
> output from "afs load" when the first load attempt fails.  For example,
> I see this output on my Juno board:
> 
> image "Image" not found in flash
> Loading norkern instead of Image
> loaded region 0 from 0850 to 8000, 00AB6318 bytes
> image "juno" not found in flash
> Loading board.dtb instead of juno
> loaded region 0 from 0A00 to 8300, 3188 bytes
> 
> Signed-off-by: Ryan Harkin 
> Reviewed-by: Linus Walleij 
> CC: David Feng 
> CC: Bhupesh Sharma 
> CC: Linus Walleij 
> ---
>  include/configs/vexpress_aemv8a.h | 16 ++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/include/configs/vexpress_aemv8a.h 
> b/include/configs/vexpress_aemv8a.h
> index c62c3ac..192568a 100644
> --- a/include/configs/vexpress_aemv8a.h
> +++ b/include/configs/vexpress_aemv8a.h
> @@ -185,11 +185,13 @@
>   * be copied into DRAM
>   */
>  #define CONFIG_EXTRA_ENV_SETTINGS\
> - "kernel_name=Image\0"   \
> + "kernel_name=norkern\0" \
> + "kernel_alt_name=Image\0"   \
>   "kernel_addr=0x8000\0" \
>   "initrd_name=ramdisk.img\0" \
>   "initrd_addr=0x8400\0"  \
> - "fdt_name=juno\0" \
> + "fdt_name=board.dtb\0" \
> + "fdt_alt_name=juno\0" \
>   "fdt_addr=0x8300\0" \
>   "fdt_high=0x\0" \
>   "initrd_high=0x\0" \
> @@ -205,7 +207,17 @@
>  
>  /* Copy the kernel and FDT to DRAM memory and boot */
>  #define CONFIG_BOOTCOMMAND   "afs load ${kernel_name} ${kernel_addr} ; " \
> + "if test $? -eq 1; then "\
> + "  echo Loading ${kernel_alt_name} instead of "\
> + "${kernel_name}; "\
> + "  afs load ${kernel_alt_name} ${kernel_addr};"\
> + "fi ; "\
>   "afs load  ${fdt_name} ${fdt_addr} ; " \
> + "if test $? -eq 1; then "\
> + "  echo Loading ${fdt_alt_name} instead of "\
> + "${fdt_name}; "\
> + "  afs load ${fdt_alt_name} ${fdt_addr}; "\
> + "fi ; "\
>   "fdt addr ${fdt_addr}; fdt resize; " \
>   "if afs load  ${initrd_name} ${initrd_addr} ; "\
>   "then "\
> -- 
> 2.1.0
> 
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