Re: [PATCH] board: add InnoComm i.MX8MM WB15EVK

[Matt Porter]

On Thu, Apr 16, 2020 at 02:33:17PM -0300, Fabio Estevam wrote:
> Hi Matt,

Hi Fabio, thanks for the review!

> On Thu, Apr 9, 2020 at 6:51 PM Matt Porter  wrote:
> 
> Hopefully this dts will be sent upstream.

Yes, this just made it out first. Updating both accordingly below.

> 
> > +/ {
> > +   model = "InnoComm i.MX8MM WB15EVK";
> > +   compatible = "fsl,imx8mm-wb15evk", "fsl,imx8mm";
> 
> Should be "innocomm,imx8mm-wb15evk", "fsl,imx8mm" instead, since the
> board manufacturer is InnoComm.

Oops, yeah, will fix that.

> 
> > + {
> > +   phy_en {
> > +   gpio-hog;
> > +   gpios = <10 GPIO_ACTIVE_HIGH>;
> > +   output-high;
> > +   pinctrl-names = "default";
> > +   pinctrl-0 = <_phy_en>;
> > +   };
> 
> Shouldn't this be modelled as a phy-supply GPIO controlled regulator instead?

Yes, converting it to a regulator will be better.

> > +CONFIG_SPL_SYS_ICACHE_OFF=y
> > +CONFIG_SPL_SYS_DCACHE_OFF=y

> Can't we work with caches enabled by now?

Yes, I verified we're fine with cache on so I'll fix that.

> > +/* USDHC */
> > +#define CONFIG_FSL_USDHC
> 
> Better put it in the defconfig instead.

Ok.
> 
> > +#define CONFIG_FEC_XCV_TYPE RGMII
> > +#define FEC_QUIRK_ENET_MAC
> 
> Shouldn't this be moved to a SoC header instead of each board file?

It does look like it should be moved to imx-regs.h like imx6/7 do.

> > +
> > +#define IMX_FEC_BASE0x30BE
> 
> Not needed as you are using FEC DM.

Ok.

-Matt

[PATCH] board: add InnoComm i.MX8MM WB15EVK

[Matt Porter]

Add support for the InnoComm i.MX8MM WB15EVK board
(https://www.innocomm.com/product_inner.aspx?num=2233).

The following functionality is supported:
- eMMC
- MMC/SD
- GPIO
- I2C
- Ethernet

Signed-off-by: Matt Porter 
---
 arch/arm/dts/Makefile |1 +
 arch/arm/dts/imx8mm-wb15evk-u-boot.dtsi   |  120 ++
 arch/arm/dts/imx8mm-wb15evk.dts   |  390 
 arch/arm/mach-imx/imx8m/Kconfig   |7 +
 board/innocomm/imx8mm_wb15evk/Kconfig |   16 +
 board/innocomm/imx8mm_wb15evk/MAINTAINERS |6 +
 board/innocomm/imx8mm_wb15evk/Makefile|   14 +
 board/innocomm/imx8mm_wb15evk/README.rst  |   46 +
 .../innocomm/imx8mm_wb15evk/imx8mm_wb15evk.c  |   35 +
 .../imx8mm_wb15evk/lpddr4_timing-2400mts.c| 1849 +
 board/innocomm/imx8mm_wb15evk/lpddr4_timing.c | 1849 +
 board/innocomm/imx8mm_wb15evk/spl.c   |  173 ++
 configs/imx8mm_wb15evk_defconfig  |   83 +
 include/configs/imx8mm_wb15evk.h  |  156 ++
 14 files changed, 4745 insertions(+)
 create mode 100644 arch/arm/dts/imx8mm-wb15evk-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mm-wb15evk.dts
 create mode 100644 board/innocomm/imx8mm_wb15evk/Kconfig
 create mode 100644 board/innocomm/imx8mm_wb15evk/MAINTAINERS
 create mode 100644 board/innocomm/imx8mm_wb15evk/Makefile
 create mode 100644 board/innocomm/imx8mm_wb15evk/README.rst
 create mode 100644 board/innocomm/imx8mm_wb15evk/imx8mm_wb15evk.c
 create mode 100644 board/innocomm/imx8mm_wb15evk/lpddr4_timing-2400mts.c
 create mode 100644 board/innocomm/imx8mm_wb15evk/lpddr4_timing.c
 create mode 100644 board/innocomm/imx8mm_wb15evk/spl.c
 create mode 100644 configs/imx8mm_wb15evk_defconfig
 create mode 100644 include/configs/imx8mm_wb15evk.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 820ee9733a..128c118ac3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -721,6 +721,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \
 dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-evk.dtb \
imx8mm-verdin.dtb \
+   imx8mm-wb15evk.dtb \
imx8mn-ddr4-evk.dtb \
imx8mq-evk.dtb \
imx8mp-evk.dtb
diff --git a/arch/arm/dts/imx8mm-wb15evk-u-boot.dtsi 
b/arch/arm/dts/imx8mm-wb15evk-u-boot.dtsi
new file mode 100644
index 00..67dce571e5
--- /dev/null
+++ b/arch/arm/dts/imx8mm-wb15evk-u-boot.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Copyright 2020 Konsulko Group
+ */
+
+&{/soc@0} {
+   u-boot,dm-pre-reloc;
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+   u-boot,dm-pre-reloc;
+   /delete-property/ assigned-clocks;
+   /delete-property/ assigned-clock-parents;
+   /delete-property/ assigned-clock-rates;
+};
+
+_24m {
+   u-boot,dm-spl;
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-spl;
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+_reg_usdhc2_vmmc {
+   u-boot,dm-spl;
+};
+
+_uart2 {
+   u-boot,dm-spl;
+};
+
+_usdhc2_gpio {
+   u-boot,dm-spl;
+};
+
+_usdhc2 {
+   u-boot,dm-spl;
+};
+
+_usdhc3 {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
+   u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
+   u-boot,dm-spl;
+};
+
+_i2c1 {
+   u-boot,dm-spl;
+};
+
+_pmic {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-wb15evk.dts b/arch/arm/dts/imx8mm-wb15evk.dts
new file mode 100644
index 00..38e49ea11b
--- /dev/null
+++ b/arch/arm/dts/imx8mm-wb15evk.dts
@@ -0,0 +1,390 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include 
+#include "imx8mm.dtsi"
+
+/ {
+   model = "InnoComm i.MX8MM WB15EVK";
+   compatible = "fsl,imx8mm-wb15evk", "fsl,imx8mm";
+
+   chosen {
+   stdout-path = 
+   };
+
+   reg_usdhc2_vmmc: regulator-usdhc2 {
+   compatible = "regulator-fixed";
+   pinctrl-names = "default";
+   pinctrl-0 = <_reg_usdhc2_vmmc>;
+   regulator-name = "VSD_3V3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = < 19 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+};
+
+_0 {
+   cpu-supply = <_reg>;
+};
+
+ {
+   pinctrl-names = "default

Re: [PATCH] imx: Fix imx8m FIT script issue

[Matt Porter]

On Thu, Apr 09, 2020 at 01:44:43AM -0700, Ye Li wrote:
> The FIT config node has reversed ATF and u-boot: ATF is set to
> firmware but u-boot is set to loadable.
> This script can work previously because spl fit driver wrongly
> appends fdt to all loadable images. With the issue fixed, the u-boot
> in loadable does not have fdt appended and fails to work.
> So correct script by moving u-boot to firmware and ATF to loadable.
> 
> Signed-off-by: Ye Li 

Hi Ye Li,

Thanks, this patch does fix the issue.

Tested-by: Matt Porter 

-Matt

Re: [PATCH] Revert "common: spl_fit: Default to IH_OS_U_BOOT if FIT_IMAGE_TINY enabled"

[Matt Porter]

On Tue, Mar 31, 2020 at 01:59:20AM -0700, Ye Li wrote:
> The patch in commit cf8dcc5d02c32173b74bf1b7600dd2b990a90b13 is not correct,
> it will append fdt to each loadable image.
> Actually when using TINY FIT, the first loadable image is thought as u-boot
> and already have fdt appended.
> 
> Signed-off-by: Ye Li 

Hi,

I just rebased an i.mx8mm board from v2020.04-rc4 to v2020.04-rc5 that
I'm preparing for submission upstream and noticed that this commit
broke start of U-Boot. Reverting this or disabling FIT_IMAGE_TINY fixes
it.

-Matt

> ---
>  common/spl/spl_fit.c | 4 
>  1 file changed, 4 deletions(-)
> 
> diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
> index aef1dbd..69dabd2 100644
> --- a/common/spl/spl_fit.c
> +++ b/common/spl/spl_fit.c
> @@ -646,10 +646,6 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
>  
>   if (!spl_fit_image_get_os(fit, node, _type))
>   debug("Loadable is %s\n", genimg_get_os_name(os_type));
> -#if CONFIG_IS_ENABLED(FIT_IMAGE_TINY)
> - else
> - os_type = IH_OS_U_BOOT;
> -#endif
>  
>   if (os_type == IH_OS_U_BOOT) {
>   spl_fit_append_fdt(_info, info, sector,
> -- 
> 2.7.4
> 

Re: [U-Boot] Remove STM32F1 support ?

[Matt Porter]

On Sat, Aug 5, 2017 at 11:35 AM, Tom Rini  wrote:
> On Fri, Aug 04, 2017 at 04:05:58PM +, Patrice CHOTARD wrote:
>> Hi Matt, Kamil
>>
>> I currently doing some work on STM32 SoCs on U-boot, more
>> precisely code factorization between STYM32F4, STM32F7 and STM32H7
>>
>> I noticed you added STM32F1 SoCs support few years ago :
>>
>> 0144caf22ce6acd5c  gpio: stm32: add stm32f1 support
>> 2d18ef2364fd3561a  ARMv7M: add STM32F1 support
>>
>> But neither STM32F1 dedicated defconfig nor board was associated to
>> these commits.
>>
>> In order to facilitate the cleaning work i am currently doing, can i
>> removed STM32F1 support ? (ie all files located in
>> arch/arm/mach-stm32/stm32f1 and in arch/arm/include/asm/arch-stm32f1)
>
> I know for Matt's side, a few more changes were needed in some of the
> board code, and then the particular project we were working on wrapped
> up, and he's moved on to other things for fun-time projects.  Unless
> Kamil wants to step up and fix / clean-up STM32F1 stuff as needed for
> your clean-ups, yes, lets go with removal.  Thanks!

Agreed, works for me. If I have time again for STM32F1 I can always
resubmit the whole thing.

Thanks,
Matt
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Re: [U-Boot] [PATCH] pci: Configure expansion ROM during auto config process

[Matt Porter]

On Fri, Jun 19, 2015 at 04:15:04PM +0800, Bin Meng wrote:
 Currently PCI expansion ROM address is assigned by a call to
 pciauto_setup_rom() outside of the pci auto config process.
 This does not work when expansion ROM is on a device behind
 PCI bridge where bridge's memory limit register was already
 programmed to a value that does not cover the newly assigned
 expansion ROM address. To fix this, we should configure the
 ROM address during the auto config process.

Definitely the correct approach for the reason mentioned. There's
an issue though with the behavior of the existing expansion ROM
probe code that should be mentioned, see below.

Otherwise, looks good.

Reviewed-by: Matt Porter mpor...@konsulko.com

 Signed-off-by: Bin Meng bmeng...@gmail.com
 ---
 
  drivers/pci/pci_auto.c | 40 ++--
  drivers/pci/pci_rom.c  |  5 -
  include/pci.h  |  9 -
  3 files changed, 14 insertions(+), 40 deletions(-)
 
 diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
 index 7c10983..92b4933 100644
 --- a/drivers/pci/pci_auto.c
 +++ b/drivers/pci/pci_auto.c
 @@ -182,36 +182,24 @@ void pciauto_setup_device(struct pci_controller *hose,
   bar_nr++;
   }
  
 - pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
 - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
 - CONFIG_SYS_PCI_CACHE_LINE_SIZE);
 - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 -}
 -
 -int pciauto_setup_rom(struct pci_controller *hose, pci_dev_t dev)
 -{
 - pci_addr_t bar_value;
 - pci_size_t bar_size;
 - u32 bar_response;
 - u16 cmdstat = 0;
 -
 + /* Configure the expansion ROM address */
   pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS, 0xfffe);
   pci_hose_read_config_dword(hose, dev, PCI_ROM_ADDRESS, bar_response);
 - if (!bar_response)
 - return -ENOENT;
 -
 - bar_size = -(bar_response  ~1);
 - DEBUGF(PCI Autoconfig: ROM, size=%#x, , bar_size);
 - if (pciauto_region_allocate(hose-pci_mem, bar_size, bar_value) == 0) {
 - pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS,
 - bar_value);
 + if (bar_response) {
 + bar_size = -(bar_response  ~1);
 + DEBUGF(PCI Autoconfig: ROM, size=%#x, , bar_size);
 + if (pciauto_region_allocate(mem, bar_size, bar_value) == 0) {
 + pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS,
 + bar_value);
 + }
 + cmdstat |= PCI_COMMAND_MEMORY;

 + DEBUGF(\n);
   }
 - DEBUGF(\n);
 - pci_hose_read_config_word(hose, dev, PCI_COMMAND, cmdstat);
 - cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 - pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
  
 - return 0;
 + pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
 + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
 +CONFIG_SYS_PCI_CACHE_LINE_SIZE);
 + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);

This is a good place to mention that there's a (IMHO) latent bug in the
existing expansion ROM support. The spec mentions that simply having
a BAR decoder active does not mean there's an expansion ROM present as
it could be depoped whether socketed (old school) or not. The
pci_rom_probe() code does properly check for the ROM header signature
after ROM address decoding is enabled but does not exhibit proper error
handling on exit. Rather than leaving the ROM expansion address active
it should disable decoding on an invalid header signature. e.g.:

if (le16_to_cpu(rom_header-signature) != PCI_ROM_HDR) {
printf(Incorrect expansion ROM header signature %04x, 
disabling\n,
   le16_to_cpu(rom_header-signature));
+   /* Disable expansion ROM address decoding */
+   pci_write_config_dword(dev, PCI_ROM_ADDRESS, rom_address);
return -EINVAL;
}

I don't have a way to test this effectively other than by inspection but
I could send a proper patch.

-Matt
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[U-Boot] [PATCH v3 6/6] board: add stm3210e-eval board support

[Matt Porter]

Add support for the STM32F1-based stm3210e-eval boards
from ST. UART, Flash, GPIO, and LEDs are supported.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
v3:
- Update copyright notices

 arch/arm/Kconfig   |   5 ++
 board/st/stm3210e-eval/Kconfig |  19 ++
 board/st/stm3210e-eval/MAINTAINERS |   5 ++
 board/st/stm3210e-eval/Makefile|  14 
 board/st/stm3210e-eval/stm3210e-eval.c |  86 
 configs/stm3210e-eval_defconfig|   3 +
 include/configs/stm3210e-eval.h| 118 +
 7 files changed, 250 insertions(+)
 create mode 100644 board/st/stm3210e-eval/Kconfig
 create mode 100644 board/st/stm3210e-eval/MAINTAINERS
 create mode 100644 board/st/stm3210e-eval/Makefile
 create mode 100644 board/st/stm3210e-eval/stm3210e-eval.c
 create mode 100644 configs/stm3210e-eval_defconfig
 create mode 100644 include/configs/stm3210e-eval.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4eb047c..bcf4e46 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -731,6 +731,10 @@ config ARCH_UNIPHIER
select SPL
select OF_CONTROL
 
+config TARGET_STM3210E_EVAL
+   bool Support STM3210E-EVAL board
+   select CPU_V7M
+
 config TARGET_STM32F429_DISCOVERY
bool Support STM32F429 Discovery
select CPU_V7M
@@ -872,6 +876,7 @@ source board/spear/spear600/Kconfig
 source board/spear/x600/Kconfig
 source board/st-ericsson/snowball/Kconfig
 source board/st-ericsson/u8500/Kconfig
+source board/st/stm3210e-eval/Kconfig
 source board/st/stm32f429-discovery/Kconfig
 source board/st/stv0991/Kconfig
 source board/sunxi/Kconfig
diff --git a/board/st/stm3210e-eval/Kconfig b/board/st/stm3210e-eval/Kconfig
new file mode 100644
index 000..49bc770
--- /dev/null
+++ b/board/st/stm3210e-eval/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_STM3210E_EVAL
+
+config SYS_BOARD
+   string
+   default stm3210e-eval
+
+config SYS_VENDOR
+   string
+   default st
+
+config SYS_SOC
+   string
+   default stm32f1
+
+config SYS_CONFIG_NAME
+   string
+   default stm3210e-eval
+
+endif
diff --git a/board/st/stm3210e-eval/MAINTAINERS 
b/board/st/stm3210e-eval/MAINTAINERS
new file mode 100644
index 000..0f9f31b
--- /dev/null
+++ b/board/st/stm3210e-eval/MAINTAINERS
@@ -0,0 +1,5 @@
+M: Matt Porter mpor...@konsulko.com
+S: Maintained
+F: board/st/stm3210e-eval/
+F: include/configs/stm3210e-eval.h
+F: configs/stm3210e-eval_defconfig
diff --git a/board/st/stm3210e-eval/Makefile b/board/st/stm3210e-eval/Makefile
new file mode 100644
index 000..15e5ee3
--- /dev/null
+++ b/board/st/stm3210e-eval/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# (C) Copyright 2015
+# Kamil Lulko, re...@wp.pl
+#
+# Copyright 2015 ATS Advanced Telematics Systems GmbH
+# Copyright 2015 Konsulko Group, Matt Porter mpor...@konsulko.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := stm3210e-eval.o
diff --git a/board/st/stm3210e-eval/stm3210e-eval.c 
b/board/st/stm3210e-eval/stm3210e-eval.c
new file mode 100644
index 000..43761aa
--- /dev/null
+++ b/board/st/stm3210e-eval/stm3210e-eval.c
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2011, 2012, 2013
+ * Yuri Tikhonov, Emcraft Systems, y...@emcraft.com
+ * Alexander Potashev, Emcraft Systems, aspotas...@emcraft.com
+ * Vladimir Khusainov, Emcraft Systems, v...@emcraft.com
+ * Pavel Boldin, Emcraft Systems, pabol...@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, re...@wp.pl
+ *
+ * Copyright 2015 ATS Advanced Telematics Systems GmbH
+ * Copyright 2015 Konsulko Group, Matt Porter mpor...@konsulko.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/armv7m.h
+#include asm/arch/stm32.h
+#include asm/arch/gpio.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct stm32_gpio_ctl gpio_ctl_usart[] = {
+   /* TX */
+   {
+   .mode = STM32_GPIO_MODE_OUT_50M,
+   .ocnf = STM32_GPIO_OCNF_AF_PP,
+   },
+   /* RX */
+   {
+   .mode = STM32_GPIO_MODE_IN,
+   .icnf = STM32_GPIO_ICNF_IN_FLT,
+   }
+};
+
+static const struct stm32_gpio_dsc usart1_gpio[] = {
+   {STM32_GPIO_PORT_A, STM32_GPIO_PIN_9},  /* TX */
+   {STM32_GPIO_PORT_A, STM32_GPIO_PIN_10}, /* RX */
+};
+
+int uart2_setup_gpio(void)
+{
+   int i;
+   int rv = 0;
+
+   for (i = 0; i  ARRAY_SIZE(usart1_gpio); i++) {
+   rv = stm32_gpio_config(usart1_gpio[i], gpio_ctl_usart[i]);
+   if (rv)
+   goto out;
+   }
+
+out:
+   return rv;
+}
+
+int dram_init(void)
+{
+   gd-ram_size = CONFIG_SYS_RAM_SIZE;
+
+   return 0;
+}
+
+u32 get_board_rev(void)
+{
+   return 0;
+}
+
+int board_early_init_f(void)
+{
+   int res;
+
+   res = uart2_setup_gpio();
+   if (res)
+   return res

[U-Boot] [PATCH v3 3/6] ARMv7M: add STM32F1 support

[Matt Porter]

Add ARMv7M STM32F1 support including clocks, timer, gpio, and flash.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
v3:
- Update copyright notices

 arch/arm/cpu/armv7m/Makefile  |   1 +
 arch/arm/cpu/armv7m/stm32f1/Makefile  |  14 +++
 arch/arm/cpu/armv7m/stm32f1/clock.c   | 196 ++
 arch/arm/cpu/armv7m/stm32f1/flash.c   | 180 +++
 arch/arm/cpu/armv7m/stm32f1/soc.c |  36 ++
 arch/arm/cpu/armv7m/stm32f1/timer.c   | 121 ++
 arch/arm/include/asm/arch-stm32f1/gpio.h  | 118 ++
 arch/arm/include/asm/arch-stm32f1/stm32.h | 116 ++
 include/flash.h   |   1 +
 9 files changed, 783 insertions(+)
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/Makefile
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/clock.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/flash.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/soc.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/timer.c
 create mode 100644 arch/arm/include/asm/arch-stm32f1/gpio.h
 create mode 100644 arch/arm/include/asm/arch-stm32f1/stm32.h

diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile
index b662e03..93a1956 100644
--- a/arch/arm/cpu/armv7m/Makefile
+++ b/arch/arm/cpu/armv7m/Makefile
@@ -8,4 +8,5 @@
 extra-y := start.o
 obj-y += cpu.o
 
+obj-$(CONFIG_STM32F1) += stm32f1/
 obj-$(CONFIG_STM32F4) += stm32f4/
diff --git a/arch/arm/cpu/armv7m/stm32f1/Makefile 
b/arch/arm/cpu/armv7m/stm32f1/Makefile
new file mode 100644
index 000..4faf435
--- /dev/null
+++ b/arch/arm/cpu/armv7m/stm32f1/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# (C) Copyright 2015
+# Kamil Lulko, re...@wp.pl
+#
+# Copyright 2015 ATS Advanced Telematics Systems GmbH
+# Copyright 2015 Konsulko Group, Matt Porter mpor...@konsulko.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += soc.o clock.o timer.o flash.o
diff --git a/arch/arm/cpu/armv7m/stm32f1/clock.c 
b/arch/arm/cpu/armv7m/stm32f1/clock.c
new file mode 100644
index 000..acad116
--- /dev/null
+++ b/arch/arm/cpu/armv7m/stm32f1/clock.c
@@ -0,0 +1,196 @@
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, re...@wp.pl
+ *
+ * Copyright 2015 ATS Advanced Telematics Systems GmbH
+ * Copyright 2015 Konsulko Group, Matt Porter mpor...@konsulko.com
+ *
+ * (C) Copyright 2014
+ * STMicroelectronics
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/stm32.h
+
+#define RCC_CR_HSION   (1  0)
+#define RCC_CR_HSEON   (1  16)
+#define RCC_CR_HSERDY  (1  17)
+#define RCC_CR_HSEBYP  (1  18)
+#define RCC_CR_CSSON   (1  19)
+#define RCC_CR_PLLON   (1  24)
+#define RCC_CR_PLLRDY  (1  25)
+
+#define RCC_CFGR_PLLMUL_MASK   0x3C
+#define RCC_CFGR_PLLMUL_SHIFT  18
+#define RCC_CFGR_PLLSRC_HSE(1  16)
+
+#define RCC_CFGR_AHB_PSC_MASK  0xF0
+#define RCC_CFGR_APB1_PSC_MASK 0x700
+#define RCC_CFGR_APB2_PSC_MASK 0x3800
+#define RCC_CFGR_SW0   (1  0)
+#define RCC_CFGR_SW1   (1  1)
+#define RCC_CFGR_SW_MASK   0x3
+#define RCC_CFGR_SW_HSI0
+#define RCC_CFGR_SW_HSERCC_CFGR_SW0
+#define RCC_CFGR_SW_PLLRCC_CFGR_SW1
+#define RCC_CFGR_SWS0  (1  2)
+#define RCC_CFGR_SWS1  (1  3)
+#define RCC_CFGR_SWS_MASK  0xC
+#define RCC_CFGR_SWS_HSI   0
+#define RCC_CFGR_SWS_HSE   RCC_CFGR_SWS0
+#define RCC_CFGR_SWS_PLL   RCC_CFGR_SWS1
+#define RCC_CFGR_HPRE_SHIFT4
+#define RCC_CFGR_PPRE1_SHIFT   8
+#define RCC_CFGR_PPRE2_SHIFT   11
+
+#define RCC_APB1ENR_PWREN  (1  28)
+
+#define PWR_CR_VOS0(1  14)
+#define PWR_CR_VOS1(1  15)
+#define PWR_CR_VOS_MASK0xC000
+#define PWR_CR_VOS_SCALE_MODE_1(PWR_CR_VOS0 | PWR_CR_VOS1)
+#define PWR_CR_VOS_SCALE_MODE_2(PWR_CR_VOS1)
+#define PWR_CR_VOS_SCALE_MODE_3(PWR_CR_VOS0)
+
+#define FLASH_ACR_WS(n)n
+#define FLASH_ACR_PRFTEN   (1  8)
+#define FLASH_ACR_ICEN (1  9)
+#define FLASH_ACR_DCEN (1  10)
+
+struct psc {
+   u8  ahb_psc;
+   u8  apb1_psc;
+   u8  apb2_psc;
+};
+
+#define AHB_PSC_1  0
+#define AHB_PSC_2  0x8
+#define AHB_PSC_4  0x9
+#define AHB_PSC_8  0xA
+#define AHB_PSC_16 0xB
+#define AHB_PSC_64 0xC
+#define AHB_PSC_1280xD
+#define AHB_PSC_2560xE
+#define AHB_PSC_5120xF
+
+#define APB_PSC_1  0
+#define APB_PSC_2  0x4
+#define APB_PSC_4  0x5
+#define APB_PSC_8  0x6
+#define APB_PSC_16 0x7
+
+#if !defined(CONFIG_STM32_HSE_HZ)
+#error CONFIG_STM32_HSE_HZ not defined!
+#else
+#if (CONFIG_STM32_HSE_HZ == 800)
+#define RCC_CFGR_PLLMUL_CFG0x7
+struct psc

[U-Boot] [PATCH v3 1/6] image: fix build when CONFIG_NR_DRAM_BANKS is disabled on ARM

[Matt Porter]

common/image.c currently implicitly depends on CONFIG_NR_DRAM_BANKS
when CONFIG_ARM is enabled. Make this requirement explicit.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
 common/image.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/image.c b/common/image.c
index 162b682..73c24f5 100644
--- a/common/image.c
+++ b/common/image.c
@@ -461,7 +461,7 @@ phys_size_t getenv_bootm_size(void)
tmp = 0;
 
 
-#if defined(CONFIG_ARM)
+#if defined(CONFIG_ARM)  defined(CONFIG_NR_DRAM_BANKS)
return gd-bd-bi_dram[0].size - tmp;
 #else
return gd-bd-bi_memsize - tmp;
-- 
2.1.0

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[U-Boot] [PATCH v3 4/6] gpio: stm32: add stm32f1 support

[Matt Porter]

Add support for the STM32F1 family to the STM32 gpio driver.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
v3:
- Update copyright notice
v2:
- Explicitly check for F4/F1 family and error if not
  set to a supported STM32 family.

 drivers/gpio/stm32_gpio.c | 110 +-
 1 file changed, 109 insertions(+), 1 deletion(-)

diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c
index d3497e9..86bb19e 100644
--- a/drivers/gpio/stm32_gpio.c
+++ b/drivers/gpio/stm32_gpio.c
@@ -5,6 +5,9 @@
  * (C) Copyright 2015
  * Kamil Lulko, re...@wp.pl
  *
+ * Copyright 2015 ATS Advanced Telematics Systems GmbH
+ * Copyright 2015 Konsulko Group, Matt Porter mpor...@konsulko.com
+ *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
@@ -16,6 +19,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_STM32F4)
 #define STM32_GPIOA_BASE   (STM32_AHB1PERIPH_BASE + 0x)
 #define STM32_GPIOB_BASE   (STM32_AHB1PERIPH_BASE + 0x0400)
 #define STM32_GPIOC_BASE   (STM32_AHB1PERIPH_BASE + 0x0800)
@@ -90,6 +94,92 @@ int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
 out:
return rv;
 }
+#elif defined(CONFIG_STM32F1)
+#define STM32_GPIOA_BASE   (STM32_APB2PERIPH_BASE + 0x0800)
+#define STM32_GPIOB_BASE   (STM32_APB2PERIPH_BASE + 0x0C00)
+#define STM32_GPIOC_BASE   (STM32_APB2PERIPH_BASE + 0x1000)
+#define STM32_GPIOD_BASE   (STM32_APB2PERIPH_BASE + 0x1400)
+#define STM32_GPIOE_BASE   (STM32_APB2PERIPH_BASE + 0x1800)
+#define STM32_GPIOF_BASE   (STM32_APB2PERIPH_BASE + 0x1C00)
+#define STM32_GPIOG_BASE   (STM32_APB2PERIPH_BASE + 0x2000)
+
+static const unsigned long io_base[] = {
+   STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
+   STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
+   STM32_GPIOG_BASE
+};
+
+#define STM32_GPIO_CR_MODE_MASK0x3
+#define STM32_GPIO_CR_MODE_SHIFT(p)(p * 4)
+#define STM32_GPIO_CR_CNF_MASK 0x3
+#define STM32_GPIO_CR_CNF_SHIFT(p) (p * 4 + 2)
+
+struct stm32_gpio_regs {
+   u32 crl;/* GPIO port configuration low */
+   u32 crh;/* GPIO port configuration high */
+   u32 idr;/* GPIO port input data */
+   u32 odr;/* GPIO port output data */
+   u32 bsrr;   /* GPIO port bit set/reset */
+   u32 brr;/* GPIO port bit reset */
+   u32 lckr;   /* GPIO port configuration lock */
+};
+
+#define CHECK_DSC(x)   (!x || x-port  6 || x-pin  15)
+#define CHECK_CTL(x)   (!x || x-mode  3 || x-icnf  3 || x-ocnf  3 || \
+x-pupd  1)
+
+int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
+   const struct stm32_gpio_ctl *ctl)
+{
+   struct stm32_gpio_regs *gpio_regs;
+   u32 *cr;
+   int p, crp;
+   int rv;
+
+   if (CHECK_DSC(dsc)) {
+   rv = -EINVAL;
+   goto out;
+   }
+   if (CHECK_CTL(ctl)) {
+   rv = -EINVAL;
+   goto out;
+   }
+
+   p = dsc-pin;
+
+   gpio_regs = (struct stm32_gpio_regs *)io_base[dsc-port];
+
+   /* Enable clock for GPIO port */
+   setbits_le32(STM32_RCC-apb2enr, 0x04  dsc-port);
+
+   if (p  8) {
+   cr = gpio_regs-crl;
+   crp = p;
+   } else {
+   cr = gpio_regs-crh;
+   crp = p - 8;
+   }
+
+   clrbits_le32(cr, 0x3  STM32_GPIO_CR_MODE_SHIFT(crp));
+   setbits_le32(cr, ctl-mode  STM32_GPIO_CR_MODE_SHIFT(crp));
+
+   clrbits_le32(cr, 0x3  STM32_GPIO_CR_CNF_SHIFT(crp));
+   /* Inputs set the optional pull up / pull down */
+   if (ctl-mode == STM32_GPIO_MODE_IN) {
+   setbits_le32(cr, ctl-icnf  STM32_GPIO_CR_CNF_SHIFT(crp));
+   clrbits_le32(gpio_regs-odr, 0x1  p);
+   setbits_le32(gpio_regs-odr, ctl-pupd  p);
+   } else {
+   setbits_le32(cr, ctl-ocnf  STM32_GPIO_CR_CNF_SHIFT(crp));
+   }
+
+   rv = 0;
+out:
+   return rv;
+}
+#else
+#error STM32 family not supported
+#endif
 
 int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state)
 {
@@ -148,10 +238,20 @@ int gpio_direction_input(unsigned gpio)
 
dsc.port = stm32_gpio_to_port(gpio);
dsc.pin = stm32_gpio_to_pin(gpio);
+#if defined(CONFIG_STM32F4)
ctl.af = STM32_GPIO_AF0;
ctl.mode = STM32_GPIO_MODE_IN;
+   ctl.otype = STM32_GPIO_OTYPE_PP;
ctl.pupd = STM32_GPIO_PUPD_NO;
ctl.speed = STM32_GPIO_SPEED_50M;
+#elif defined(CONFIG_STM32F1)
+   ctl.mode = STM32_GPIO_MODE_IN;
+   ctl.icnf = STM32_GPIO_ICNF_IN_FLT;
+   ctl.ocnf = STM32_GPIO_OCNF_GP_PP;   /* ignored for input */
+   ctl.pupd = STM32_GPIO_PUPD_UP;  /* ignored for floating */
+#else
+#error STM32 family not supported
+#endif
 
return stm32_gpio_config(dsc, ctl);
 }
@@ -164,11 +264,19 @@ int gpio_direction_output(unsigned gpio, int value)
 
dsc.port

[U-Boot] [PATCH v3 0/6] Add ARMv7M STM32F1 and STM3210E-EVAL board support

[Matt Porter]

This series adds support for the STM32F1 SoC family and the STM3210E-EVAL
board on top of the STM32F4 SoC family support [1].

Since this board has no DRAM the first patch fixes the build when
CONFIG_NR_DRAM_BANKS is not set. A patch is also required to force the
processor to stay in Thumb mode when 'go'ing to an application.

As the STM32F1 differs greatly from STM32F4 in flash and clock layout,
there's a separate subdirectory for the STM32F1 family. The gpio and
serial drivers are shared as these peripherals are mostly similar with
only the pinmux bits being significantly different in the gpio driver.

The STM3210E-EVAL board is supported with 1MiB Flash and 96KiB of SRAM
on the STM32F103ZGT6, USART1 for console, and four user LEDs.

[1] http://lists.denx.de/pipermail/u-boot/2015-March/206640.html

Matt Porter (6):
  image: fix build when CONFIG_NR_DRAM_BANKS is disabled on ARM
  common/cmd_boot: keep ARM v7M in thumb mode during do_go_exec()
  ARMv7M: add STM32F1 support
  gpio: stm32: add stm32f1 support
  serial: stm32: add stm32f1 support
  board: add stm3210e-eval board support

 arch/arm/Kconfig  |   5 +
 arch/arm/cpu/armv7m/Makefile  |   1 +
 arch/arm/cpu/armv7m/stm32f1/Makefile  |  14 +++
 arch/arm/cpu/armv7m/stm32f1/clock.c   | 196 ++
 arch/arm/cpu/armv7m/stm32f1/flash.c   | 180 +++
 arch/arm/cpu/armv7m/stm32f1/soc.c |  36 ++
 arch/arm/cpu/armv7m/stm32f1/timer.c   | 121 ++
 arch/arm/include/asm/arch-stm32f1/gpio.h  | 118 ++
 arch/arm/include/asm/arch-stm32f1/stm32.h | 116 ++
 arch/arm/lib/Makefile |   1 +
 arch/arm/lib/cmd_boot.c   |  44 +++
 board/st/stm3210e-eval/Kconfig|  19 +++
 board/st/stm3210e-eval/MAINTAINERS|   5 +
 board/st/stm3210e-eval/Makefile   |  14 +++
 board/st/stm3210e-eval/stm3210e-eval.c|  86 +
 common/image.c|   2 +-
 configs/stm3210e-eval_defconfig   |   3 +
 drivers/gpio/stm32_gpio.c | 110 -
 drivers/serial/serial_stm32.c |  10 ++
 include/configs/stm3210e-eval.h   | 118 ++
 include/flash.h   |   1 +
 21 files changed, 1198 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/Makefile
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/clock.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/flash.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/soc.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/timer.c
 create mode 100644 arch/arm/include/asm/arch-stm32f1/gpio.h
 create mode 100644 arch/arm/include/asm/arch-stm32f1/stm32.h
 create mode 100644 arch/arm/lib/cmd_boot.c
 create mode 100644 board/st/stm3210e-eval/Kconfig
 create mode 100644 board/st/stm3210e-eval/MAINTAINERS
 create mode 100644 board/st/stm3210e-eval/Makefile
 create mode 100644 board/st/stm3210e-eval/stm3210e-eval.c
 create mode 100644 configs/stm3210e-eval_defconfig
 create mode 100644 include/configs/stm3210e-eval.h

-- 
2.1.0

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[U-Boot] [PATCH v3 2/6] common/cmd_boot: keep ARM v7M in thumb mode during do_go_exec()

[Matt Porter]

On ARM v7M, the processor will return to ARM mode when executing
a blx instruction with bit 0 of the address == 0. Always set it
to 1 to stay in thumb mode.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
v3:
- Implement using an override of the weak do_go_exec() when
  building for ARMv7-M.

 arch/arm/lib/Makefile   |  1 +
 arch/arm/lib/cmd_boot.c | 44 
 2 files changed, 45 insertions(+)
 create mode 100644 arch/arm/lib/cmd_boot.c

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 8288d2f..4c95a77 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -26,6 +26,7 @@ ifndef CONFIG_SYS_GENERIC_BOARD
 obj-y  += board.o
 endif
 
+obj-$(CONFIG_CPU_V7M) += cmd_boot.o
 obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
diff --git a/arch/arm/lib/cmd_boot.c b/arch/arm/lib/cmd_boot.c
new file mode 100644
index 000..37bb6a5
--- /dev/null
+++ b/arch/arm/lib/cmd_boot.c
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2008-2011
+ * Graeme Russ, graeme.r...@gmail.com
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, dan...@omicron.se
+ *
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH www.elinos.com
+ * Marius Groeger mgroe...@sysgo.de
+ *
+ * Copyright 2015 ATS Advanced Telematics Systems GmbH
+ * Copyright 2015 Konsulko Group, Matt Porter mpor...@konsulko.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include command.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * ARMv7M does not support ARM instruction mode. However, the
+ * interworking BLX and BX instructions do encode the ARM/Thumb
+ * field in bit 0. This means that when executing any Branch
+ * and eXchange instruction we must set bit 0 to one to guarantee
+ * that we keep the processor in Thumb instruction mode. From The
+ * ARMv7-M Instruction Set A4.1.1:
+ *   ARMv7-M only supports the Thumb instruction execution state,
+ *therefore the value of address bit [0] must be 1 in interworking
+ *instructions, otherwise a fault occurs.
+ */
+unsigned long do_go_exec(ulong (*entry)(int, char * const []),
+int argc, char * const argv[])
+{
+   ulong addr = (ulong)entry | 1;
+   entry = (void *)addr;
+
+   return entry(argc, argv);
+}
-- 
2.1.0

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[U-Boot] [PATCH v3 5/6] serial: stm32: add stm32f1 support

[Matt Porter]

Add support for the STM32F1 famly to the STM32 serial driver.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
v3:
- Update copyright notice
v2:
- Explicitly check for F4/F1 family and error if not
  set to a supported STM32 family.

 drivers/serial/serial_stm32.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
index 3c80096..2a029ce 100644
--- a/drivers/serial/serial_stm32.c
+++ b/drivers/serial/serial_stm32.c
@@ -2,6 +2,9 @@
  * (C) Copyright 2015
  * Kamil Lulko, re...@wp.pl
  *
+ * Copyright 2015 ATS Advanced Telematics Systems GmbH
+ * Copyright 2015 Konsulko Group, Matt Porter mpor...@konsulko.com
+ *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
@@ -10,8 +13,15 @@
 #include serial.h
 #include asm/arch/stm32.h
 
+#if defined(CONFIG_STM32F4)
 #define STM32_USART1_BASE  (STM32_APB2PERIPH_BASE + 0x1000)
 #define RCC_APB2ENR_USART1EN   (1  4)
+#elif defined(CONFIG_STM32F1)
+#define STM32_USART1_BASE  (STM32_APB2PERIPH_BASE + 0x3800)
+#define RCC_APB2ENR_USART1EN   (1  14)
+#else
+#error STM32 family not supported
+#endif
 
 #define USART_BASE STM32_USART1_BASE
 #define RCC_USART_ENABLE   RCC_APB2ENR_USART1EN
-- 
2.1.0

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[U-Boot] [PATCH v2 3/6] ARMv7M: add STM32F1 support

[Matt Porter]

Add ARMv7M STM32F1 support including clocks, timer, gpio, and flash.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
 arch/arm/cpu/armv7m/Makefile  |   1 +
 arch/arm/cpu/armv7m/stm32f1/Makefile  |  13 ++
 arch/arm/cpu/armv7m/stm32f1/clock.c   | 195 ++
 arch/arm/cpu/armv7m/stm32f1/flash.c   | 179 +++
 arch/arm/cpu/armv7m/stm32f1/soc.c |  35 ++
 arch/arm/cpu/armv7m/stm32f1/timer.c   | 120 ++
 arch/arm/include/asm/arch-stm32f1/gpio.h  | 117 ++
 arch/arm/include/asm/arch-stm32f1/stm32.h | 115 ++
 include/flash.h   |   1 +
 9 files changed, 776 insertions(+)
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/Makefile
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/clock.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/flash.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/soc.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/timer.c
 create mode 100644 arch/arm/include/asm/arch-stm32f1/gpio.h
 create mode 100644 arch/arm/include/asm/arch-stm32f1/stm32.h

diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile
index b662e03..93a1956 100644
--- a/arch/arm/cpu/armv7m/Makefile
+++ b/arch/arm/cpu/armv7m/Makefile
@@ -8,4 +8,5 @@
 extra-y := start.o
 obj-y += cpu.o
 
+obj-$(CONFIG_STM32F1) += stm32f1/
 obj-$(CONFIG_STM32F4) += stm32f4/
diff --git a/arch/arm/cpu/armv7m/stm32f1/Makefile 
b/arch/arm/cpu/armv7m/stm32f1/Makefile
new file mode 100644
index 000..7b43761
--- /dev/null
+++ b/arch/arm/cpu/armv7m/stm32f1/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# (C) Copyright 2015
+# Kamil Lulko, re...@wp.pl
+#
+# Copyright 2015 Konsulko Group, Matt Porter mpor...@konsulko.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += soc.o clock.o timer.o flash.o
diff --git a/arch/arm/cpu/armv7m/stm32f1/clock.c 
b/arch/arm/cpu/armv7m/stm32f1/clock.c
new file mode 100644
index 000..b921eff
--- /dev/null
+++ b/arch/arm/cpu/armv7m/stm32f1/clock.c
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, re...@wp.pl
+ *
+ * Copyright 2015 Konsulko Group, Matt Porter mpor...@konsulko.com
+ *
+ * (C) Copyright 2014
+ * STMicroelectronics
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/stm32.h
+
+#define RCC_CR_HSION   (1  0)
+#define RCC_CR_HSEON   (1  16)
+#define RCC_CR_HSERDY  (1  17)
+#define RCC_CR_HSEBYP  (1  18)
+#define RCC_CR_CSSON   (1  19)
+#define RCC_CR_PLLON   (1  24)
+#define RCC_CR_PLLRDY  (1  25)
+
+#define RCC_CFGR_PLLMUL_MASK   0x3C
+#define RCC_CFGR_PLLMUL_SHIFT  18
+#define RCC_CFGR_PLLSRC_HSE(1  16)
+
+#define RCC_CFGR_AHB_PSC_MASK  0xF0
+#define RCC_CFGR_APB1_PSC_MASK 0x700
+#define RCC_CFGR_APB2_PSC_MASK 0x3800
+#define RCC_CFGR_SW0   (1  0)
+#define RCC_CFGR_SW1   (1  1)
+#define RCC_CFGR_SW_MASK   0x3
+#define RCC_CFGR_SW_HSI0
+#define RCC_CFGR_SW_HSERCC_CFGR_SW0
+#define RCC_CFGR_SW_PLLRCC_CFGR_SW1
+#define RCC_CFGR_SWS0  (1  2)
+#define RCC_CFGR_SWS1  (1  3)
+#define RCC_CFGR_SWS_MASK  0xC
+#define RCC_CFGR_SWS_HSI   0
+#define RCC_CFGR_SWS_HSE   RCC_CFGR_SWS0
+#define RCC_CFGR_SWS_PLL   RCC_CFGR_SWS1
+#define RCC_CFGR_HPRE_SHIFT4
+#define RCC_CFGR_PPRE1_SHIFT   8
+#define RCC_CFGR_PPRE2_SHIFT   11
+
+#define RCC_APB1ENR_PWREN  (1  28)
+
+#define PWR_CR_VOS0(1  14)
+#define PWR_CR_VOS1(1  15)
+#define PWR_CR_VOS_MASK0xC000
+#define PWR_CR_VOS_SCALE_MODE_1(PWR_CR_VOS0 | PWR_CR_VOS1)
+#define PWR_CR_VOS_SCALE_MODE_2(PWR_CR_VOS1)
+#define PWR_CR_VOS_SCALE_MODE_3(PWR_CR_VOS0)
+
+#define FLASH_ACR_WS(n)n
+#define FLASH_ACR_PRFTEN   (1  8)
+#define FLASH_ACR_ICEN (1  9)
+#define FLASH_ACR_DCEN (1  10)
+
+struct psc {
+   u8  ahb_psc;
+   u8  apb1_psc;
+   u8  apb2_psc;
+};
+
+#define AHB_PSC_1  0
+#define AHB_PSC_2  0x8
+#define AHB_PSC_4  0x9
+#define AHB_PSC_8  0xA
+#define AHB_PSC_16 0xB
+#define AHB_PSC_64 0xC
+#define AHB_PSC_1280xD
+#define AHB_PSC_2560xE
+#define AHB_PSC_5120xF
+
+#define APB_PSC_1  0
+#define APB_PSC_2  0x4
+#define APB_PSC_4  0x5
+#define APB_PSC_8  0x6
+#define APB_PSC_16 0x7
+
+#if !defined(CONFIG_STM32_HSE_HZ)
+#error CONFIG_STM32_HSE_HZ not defined!
+#else
+#if (CONFIG_STM32_HSE_HZ == 800)
+#define RCC_CFGR_PLLMUL_CFG0x7
+struct psc psc_hse = {
+   .ahb_psc = AHB_PSC_1,
+   .apb1_psc = APB_PSC_2,
+   .apb2_psc = APB_PSC_1
+};
+#else
+#error No PLL/Prescaler configuration

[U-Boot] [PATCH v2 4/6] gpio: stm32: add stm32f1 support

[Matt Porter]

Add support for the STM32F1 family to the STM32 gpio driver.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
Since v1:
- Explicitly check for F4/F1 family and error if not
  set to a supported STM32 family.

 drivers/gpio/stm32_gpio.c | 109 +-
 1 file changed, 108 insertions(+), 1 deletion(-)

diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c
index d3497e9..f426727 100644
--- a/drivers/gpio/stm32_gpio.c
+++ b/drivers/gpio/stm32_gpio.c
@@ -5,6 +5,8 @@
  * (C) Copyright 2015
  * Kamil Lulko, re...@wp.pl
  *
+ * Copyright 2015 Konsulko Group, Matt Porter mpor...@konsulko.com
+ *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
@@ -16,6 +18,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_STM32F4)
 #define STM32_GPIOA_BASE   (STM32_AHB1PERIPH_BASE + 0x)
 #define STM32_GPIOB_BASE   (STM32_AHB1PERIPH_BASE + 0x0400)
 #define STM32_GPIOC_BASE   (STM32_AHB1PERIPH_BASE + 0x0800)
@@ -90,6 +93,92 @@ int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
 out:
return rv;
 }
+#elif defined(CONFIG_STM32F1)
+#define STM32_GPIOA_BASE   (STM32_APB2PERIPH_BASE + 0x0800)
+#define STM32_GPIOB_BASE   (STM32_APB2PERIPH_BASE + 0x0C00)
+#define STM32_GPIOC_BASE   (STM32_APB2PERIPH_BASE + 0x1000)
+#define STM32_GPIOD_BASE   (STM32_APB2PERIPH_BASE + 0x1400)
+#define STM32_GPIOE_BASE   (STM32_APB2PERIPH_BASE + 0x1800)
+#define STM32_GPIOF_BASE   (STM32_APB2PERIPH_BASE + 0x1C00)
+#define STM32_GPIOG_BASE   (STM32_APB2PERIPH_BASE + 0x2000)
+
+static const unsigned long io_base[] = {
+   STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
+   STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
+   STM32_GPIOG_BASE
+};
+
+#define STM32_GPIO_CR_MODE_MASK0x3
+#define STM32_GPIO_CR_MODE_SHIFT(p)(p * 4)
+#define STM32_GPIO_CR_CNF_MASK 0x3
+#define STM32_GPIO_CR_CNF_SHIFT(p) (p * 4 + 2)
+
+struct stm32_gpio_regs {
+   u32 crl;/* GPIO port configuration low */
+   u32 crh;/* GPIO port configuration high */
+   u32 idr;/* GPIO port input data */
+   u32 odr;/* GPIO port output data */
+   u32 bsrr;   /* GPIO port bit set/reset */
+   u32 brr;/* GPIO port bit reset */
+   u32 lckr;   /* GPIO port configuration lock */
+};
+
+#define CHECK_DSC(x)   (!x || x-port  6 || x-pin  15)
+#define CHECK_CTL(x)   (!x || x-mode  3 || x-icnf  3 || x-ocnf  3 || \
+x-pupd  1)
+
+int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
+   const struct stm32_gpio_ctl *ctl)
+{
+   struct stm32_gpio_regs *gpio_regs;
+   u32 *cr;
+   int p, crp;
+   int rv;
+
+   if (CHECK_DSC(dsc)) {
+   rv = -EINVAL;
+   goto out;
+   }
+   if (CHECK_CTL(ctl)) {
+   rv = -EINVAL;
+   goto out;
+   }
+
+   p = dsc-pin;
+
+   gpio_regs = (struct stm32_gpio_regs *)io_base[dsc-port];
+
+   /* Enable clock for GPIO port */
+   setbits_le32(STM32_RCC-apb2enr, 0x04  dsc-port);
+
+   if (p  8) {
+   cr = gpio_regs-crl;
+   crp = p;
+   } else {
+   cr = gpio_regs-crh;
+   crp = p - 8;
+   }
+
+   clrbits_le32(cr, 0x3  STM32_GPIO_CR_MODE_SHIFT(crp));
+   setbits_le32(cr, ctl-mode  STM32_GPIO_CR_MODE_SHIFT(crp));
+
+   clrbits_le32(cr, 0x3  STM32_GPIO_CR_CNF_SHIFT(crp));
+   /* Inputs set the optional pull up / pull down */
+   if (ctl-mode == STM32_GPIO_MODE_IN) {
+   setbits_le32(cr, ctl-icnf  STM32_GPIO_CR_CNF_SHIFT(crp));
+   clrbits_le32(gpio_regs-odr, 0x1  p);
+   setbits_le32(gpio_regs-odr, ctl-pupd  p);
+   } else {
+   setbits_le32(cr, ctl-ocnf  STM32_GPIO_CR_CNF_SHIFT(crp));
+   }
+
+   rv = 0;
+out:
+   return rv;
+}
+#else
+#error STM32 family not supported
+#endif
 
 int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state)
 {
@@ -148,10 +237,20 @@ int gpio_direction_input(unsigned gpio)
 
dsc.port = stm32_gpio_to_port(gpio);
dsc.pin = stm32_gpio_to_pin(gpio);
+#if defined(CONFIG_STM32F4)
ctl.af = STM32_GPIO_AF0;
ctl.mode = STM32_GPIO_MODE_IN;
+   ctl.otype = STM32_GPIO_OTYPE_PP;
ctl.pupd = STM32_GPIO_PUPD_NO;
ctl.speed = STM32_GPIO_SPEED_50M;
+#elif defined(CONFIG_STM32F1)
+   ctl.mode = STM32_GPIO_MODE_IN;
+   ctl.icnf = STM32_GPIO_ICNF_IN_FLT;
+   ctl.ocnf = STM32_GPIO_OCNF_GP_PP;   /* ignored for input */
+   ctl.pupd = STM32_GPIO_PUPD_UP;  /* ignored for floating */
+#else
+#error STM32 family not supported
+#endif
 
return stm32_gpio_config(dsc, ctl);
 }
@@ -164,11 +263,19 @@ int gpio_direction_output(unsigned gpio, int value)
 
dsc.port = stm32_gpio_to_port(gpio);
dsc.pin = stm32_gpio_to_pin(gpio);
+#if defined(CONFIG_STM32F4

[U-Boot] [PATCH v2 0/6] Add ARMv7M STM32F1 and STM3210E-EVAL board support

[Matt Porter]

This series adds support for the STM32F1 SoC family and the STM3210E-EVAL
board on top of the STM32F4 SoC family support [1].

Since this board has no DRAM the first patch fixes the build when
CONFIG_NR_DRAM_BANKS is not set. A patch is also required to force the
processor to stay in Thumb mode when 'go'ing to an application.

As the STM32F1 differs greatly from STM32F4 in flash and clock layout,
there's a separate subdirectory for the STM32F1 family. The gpio and
serial drivers are shared as these peripherals are mostly similar with
only the pinmux bits being significantly different in the gpio driver.

The STM3210E-EVAL board is supported with 1MiB Flash and 96KiB of SRAM
on the STM32F103ZGT6, USART1 for console, and four user LEDs.

[1] http://lists.denx.de/pipermail/u-boot/2015-March/206640.html

Matt Porter (6):
  image: fix build when CONFIG_NR_DRAM_BANKS is disabled on ARM
  common/cmd_boot: keep ARM v7M in thumb mode during do_go_exec()
  ARMv7M: add STM32F1 support
  gpio: stm32: add stm32f1 support
  serial: stm32: add stm32f1 support
  board: add stm3210e-eval board support

 arch/arm/Kconfig  |   5 +
 arch/arm/cpu/armv7m/Makefile  |   1 +
 arch/arm/cpu/armv7m/stm32f1/Makefile  |  13 ++
 arch/arm/cpu/armv7m/stm32f1/clock.c   | 195 ++
 arch/arm/cpu/armv7m/stm32f1/flash.c   | 179 +++
 arch/arm/cpu/armv7m/stm32f1/soc.c |  35 ++
 arch/arm/cpu/armv7m/stm32f1/timer.c   | 120 ++
 arch/arm/include/asm/arch-stm32f1/gpio.h  | 117 ++
 arch/arm/include/asm/arch-stm32f1/stm32.h | 115 ++
 board/st/stm3210e-eval/Kconfig|  19 +++
 board/st/stm3210e-eval/MAINTAINERS|   5 +
 board/st/stm3210e-eval/Makefile   |  13 ++
 board/st/stm3210e-eval/stm3210e-eval.c|  85 +
 common/cmd_boot.c |   4 +
 common/image.c|   2 +-
 configs/stm3210e-eval_defconfig   |   3 +
 drivers/gpio/stm32_gpio.c | 109 -
 drivers/serial/serial_stm32.c |   9 ++
 include/configs/stm3210e-eval.h   | 117 ++
 include/flash.h   |   1 +
 20 files changed, 1145 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/Makefile
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/clock.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/flash.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/soc.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/timer.c
 create mode 100644 arch/arm/include/asm/arch-stm32f1/gpio.h
 create mode 100644 arch/arm/include/asm/arch-stm32f1/stm32.h
 create mode 100644 board/st/stm3210e-eval/Kconfig
 create mode 100644 board/st/stm3210e-eval/MAINTAINERS
 create mode 100644 board/st/stm3210e-eval/Makefile
 create mode 100644 board/st/stm3210e-eval/stm3210e-eval.c
 create mode 100644 configs/stm3210e-eval_defconfig
 create mode 100644 include/configs/stm3210e-eval.h

-- 
2.1.0

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[U-Boot] [PATCH v2 5/6] serial: stm32: add stm32f1 support

[Matt Porter]

Add support for the STM32F1 famly to the STM32 serial driver.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
Since v1:
- Explicitly check for F4/F1 family and error if not
  set to a supported STM32 family.

 drivers/serial/serial_stm32.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
index 3c80096..9b19b68 100644
--- a/drivers/serial/serial_stm32.c
+++ b/drivers/serial/serial_stm32.c
@@ -2,6 +2,8 @@
  * (C) Copyright 2015
  * Kamil Lulko, re...@wp.pl
  *
+ * Copyright 2015 Konsulko Group, Matt Porter mpor...@konsulko.com
+ *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
@@ -10,8 +12,15 @@
 #include serial.h
 #include asm/arch/stm32.h
 
+#if defined(CONFIG_STM32F4)
 #define STM32_USART1_BASE  (STM32_APB2PERIPH_BASE + 0x1000)
 #define RCC_APB2ENR_USART1EN   (1  4)
+#elif defined(CONFIG_STM32F1)
+#define STM32_USART1_BASE  (STM32_APB2PERIPH_BASE + 0x3800)
+#define RCC_APB2ENR_USART1EN   (1  14)
+#else
+#error STM32 family not supported
+#endif
 
 #define USART_BASE STM32_USART1_BASE
 #define RCC_USART_ENABLE   RCC_APB2ENR_USART1EN
-- 
2.1.0

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[U-Boot] [PATCH v2 6/6] board: add stm3210e-eval board support

[Matt Porter]

Add support for the STM32F1-based stm3210e-eval boards
from ST. UART, Flash, GPIO, and LEDs are supported.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
 arch/arm/Kconfig   |   5 ++
 board/st/stm3210e-eval/Kconfig |  19 ++
 board/st/stm3210e-eval/MAINTAINERS |   5 ++
 board/st/stm3210e-eval/Makefile|  13 
 board/st/stm3210e-eval/stm3210e-eval.c |  85 
 configs/stm3210e-eval_defconfig|   3 +
 include/configs/stm3210e-eval.h| 117 +
 7 files changed, 247 insertions(+)
 create mode 100644 board/st/stm3210e-eval/Kconfig
 create mode 100644 board/st/stm3210e-eval/MAINTAINERS
 create mode 100644 board/st/stm3210e-eval/Makefile
 create mode 100644 board/st/stm3210e-eval/stm3210e-eval.c
 create mode 100644 configs/stm3210e-eval_defconfig
 create mode 100644 include/configs/stm3210e-eval.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4eb047c..bcf4e46 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -731,6 +731,10 @@ config ARCH_UNIPHIER
select SPL
select OF_CONTROL
 
+config TARGET_STM3210E_EVAL
+   bool Support STM3210E-EVAL board
+   select CPU_V7M
+
 config TARGET_STM32F429_DISCOVERY
bool Support STM32F429 Discovery
select CPU_V7M
@@ -872,6 +876,7 @@ source board/spear/spear600/Kconfig
 source board/spear/x600/Kconfig
 source board/st-ericsson/snowball/Kconfig
 source board/st-ericsson/u8500/Kconfig
+source board/st/stm3210e-eval/Kconfig
 source board/st/stm32f429-discovery/Kconfig
 source board/st/stv0991/Kconfig
 source board/sunxi/Kconfig
diff --git a/board/st/stm3210e-eval/Kconfig b/board/st/stm3210e-eval/Kconfig
new file mode 100644
index 000..49bc770
--- /dev/null
+++ b/board/st/stm3210e-eval/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_STM3210E_EVAL
+
+config SYS_BOARD
+   string
+   default stm3210e-eval
+
+config SYS_VENDOR
+   string
+   default st
+
+config SYS_SOC
+   string
+   default stm32f1
+
+config SYS_CONFIG_NAME
+   string
+   default stm3210e-eval
+
+endif
diff --git a/board/st/stm3210e-eval/MAINTAINERS 
b/board/st/stm3210e-eval/MAINTAINERS
new file mode 100644
index 000..0f9f31b
--- /dev/null
+++ b/board/st/stm3210e-eval/MAINTAINERS
@@ -0,0 +1,5 @@
+M: Matt Porter mpor...@konsulko.com
+S: Maintained
+F: board/st/stm3210e-eval/
+F: include/configs/stm3210e-eval.h
+F: configs/stm3210e-eval_defconfig
diff --git a/board/st/stm3210e-eval/Makefile b/board/st/stm3210e-eval/Makefile
new file mode 100644
index 000..b018e08
--- /dev/null
+++ b/board/st/stm3210e-eval/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# (C) Copyright 2015
+# Kamil Lulko, re...@wp.pl
+#
+# Copyright 2015 Konsulko Group, Matt Porter mpor...@konsulko.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := stm3210e-eval.o
diff --git a/board/st/stm3210e-eval/stm3210e-eval.c 
b/board/st/stm3210e-eval/stm3210e-eval.c
new file mode 100644
index 000..a801983
--- /dev/null
+++ b/board/st/stm3210e-eval/stm3210e-eval.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2011, 2012, 2013
+ * Yuri Tikhonov, Emcraft Systems, y...@emcraft.com
+ * Alexander Potashev, Emcraft Systems, aspotas...@emcraft.com
+ * Vladimir Khusainov, Emcraft Systems, v...@emcraft.com
+ * Pavel Boldin, Emcraft Systems, pabol...@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, re...@wp.pl
+ *
+ * Copyright 2015 Konsulko Group, Matt Porter mpor...@konsulko.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/armv7m.h
+#include asm/arch/stm32.h
+#include asm/arch/gpio.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct stm32_gpio_ctl gpio_ctl_usart[] = {
+   /* TX */
+   {
+   .mode = STM32_GPIO_MODE_OUT_50M,
+   .ocnf = STM32_GPIO_OCNF_AF_PP,
+   },
+   /* RX */
+   {
+   .mode = STM32_GPIO_MODE_IN,
+   .icnf = STM32_GPIO_ICNF_IN_FLT,
+   }
+};
+
+static const struct stm32_gpio_dsc usart1_gpio[] = {
+   {STM32_GPIO_PORT_A, STM32_GPIO_PIN_9},  /* TX */
+   {STM32_GPIO_PORT_A, STM32_GPIO_PIN_10}, /* RX */
+};
+
+int uart2_setup_gpio(void)
+{
+   int i;
+   int rv = 0;
+
+   for (i = 0; i  ARRAY_SIZE(usart1_gpio); i++) {
+   rv = stm32_gpio_config(usart1_gpio[i], gpio_ctl_usart[i]);
+   if (rv)
+   goto out;
+   }
+
+out:
+   return rv;
+}
+
+int dram_init(void)
+{
+   gd-ram_size = CONFIG_SYS_RAM_SIZE;
+
+   return 0;
+}
+
+u32 get_board_rev(void)
+{
+   return 0;
+}
+
+int board_early_init_f(void)
+{
+   int res;
+
+   res = uart2_setup_gpio();
+   if (res)
+   return res;
+
+   return 0;
+}
+
+int board_init(void)
+{
+   gd-bd-bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+   return 0;
+}
diff --git a/configs

[U-Boot] [PATCH v2 1/6] image: fix build when CONFIG_NR_DRAM_BANKS is disabled on ARM

[Matt Porter]

common/image.c currently implicitly depends on CONFIG_NR_DRAM_BANKS
when CONFIG_ARM is enabled. Make this requirement explicit.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
 common/image.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/image.c b/common/image.c
index 162b682..73c24f5 100644
--- a/common/image.c
+++ b/common/image.c
@@ -461,7 +461,7 @@ phys_size_t getenv_bootm_size(void)
tmp = 0;
 
 
-#if defined(CONFIG_ARM)
+#if defined(CONFIG_ARM)  defined(CONFIG_NR_DRAM_BANKS)
return gd-bd-bi_dram[0].size - tmp;
 #else
return gd-bd-bi_memsize - tmp;
-- 
2.1.0

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[U-Boot] [PATCH v2 2/6] common/cmd_boot: keep ARM v7M in thumb mode during do_go_exec()

[Matt Porter]

On ARM v7M, the processor will return to ARM mode when executing
a blx instruction with bit 0 of the address == 0. Always set it
to 1 to stay in thumb mode.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
 common/cmd_boot.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/common/cmd_boot.c b/common/cmd_boot.c
index 8f2e070..20ce652 100644
--- a/common/cmd_boot.c
+++ b/common/cmd_boot.c
@@ -38,6 +38,10 @@ static int do_go(cmd_tbl_t *cmdtp, int flag, int argc, char 
* const argv[])
 * pass address parameter as argv[0] (aka command name),
 * and all remaining args
 */
+#ifdef CONFIG_CPU_V7M
+   /* For ARM V7M, set bit zero to stay in Thumb mode */
+   addr++;
+#endif
rc = do_go_exec ((void *)addr, argc - 1, argv + 1);
if (rc != 0) rcode = 1;
 
-- 
2.1.0

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Re: [U-Boot] [PATCH v2 2/6] common/cmd_boot: keep ARM v7M in thumb mode during do_go_exec()

[Matt Porter]

On Tue, Apr 21, 2015 at 01:05:24PM -0500, Felipe Balbi wrote:
 On Tue, Apr 21, 2015 at 02:01:31PM -0400, Matt Porter wrote:
  On Tue, Apr 21, 2015 at 12:47:24PM -0500, Felipe Balbi wrote:
   On Tue, Apr 21, 2015 at 01:36:54PM -0400, Matt Porter wrote:
On ARM v7M, the processor will return to ARM mode when executing
a blx instruction with bit 0 of the address == 0. Always set it
   
   but that's what the 'x' is for, right ? eXchange the CPU mode.
  
  Yes.
  
to 1 to stay in thumb mode.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
 common/cmd_boot.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/common/cmd_boot.c b/common/cmd_boot.c
index 8f2e070..20ce652 100644
--- a/common/cmd_boot.c
+++ b/common/cmd_boot.c
@@ -38,6 +38,10 @@ static int do_go(cmd_tbl_t *cmdtp, int flag, int 
argc, char * const argv[])
 * pass address parameter as argv[0] (aka command name),
 * and all remaining args
 */
+#ifdef CONFIG_CPU_V7M
+   /* For ARM V7M, set bit zero to stay in Thumb mode */
+   addr++;
+#endif
   
   what if we were in ARM state when we reached this point ? You're now
   telling CPU to always switch to Thumb. Is this really what we want ?
  
  We have no ARM state on this core so that's not possible.
  
   From ARM's instruction manual:
   
   
   
   
   The BX and BLX instructions can change the processor state from ARM to
   Thumb, or from Thumb to ARM.
   
   BLX label always changes the state.
   
   BX Rm and BLX Rm derive the target state from bit[0] of Rm:
   
   if bit[0] of Rm is 0, the processor changes to, or remains in, ARM
   state
   
   if bit[0] of Rm is 1, the processor changes to, or remains in, Thumb
   state.
  
  Correct. The last statement is why this patch exists. There is no ARM
  mode on M3, we immediately fault. Having bit[0]=0 for BX/BLX is not
  permitted on V7M...something not covered in the generic description
  of these instructions.
 
 it just seems weird that bit0 wouldn't just be assume 1 by the core
 itself. I suppose as a consequence we can't use blx label with v7m
 either ? :-s

It also seems weird to me that it wouldn't just be ignored on anything
armv7-m. Yes, blx label would be very bad which is why it is not
supported on ARMv7-m :)

And to clarify for those listening at home... From The ARMv7-M
Instruction Set Appendix A4.1.1:


Thumb interworking is held as bit [0] of an interworking address.
Interworking addresses are used in the following instructions:
• BX or BLX
• an LDR or LDM that loads the PC.
ARMv7-M only supports the Thumb instruction execution state, therefore
the value of address bit [0] must be 1 in interworking instructions,
otherwise a fault occurs. All instructions ignore bit [0] and write bits
[31:1]:’0’ when updating the PC.


Also:


A7.7.19 BLX (register)
Branch with Link and Exchange calls a subroutine at an address and
instruction set specified by a register.
ARMv7-M only supports the Thumb instruction set. An attempt to change
the instruction execution state
causes the processor to take an exception on the instruction at the
target address.


-Matt


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Re: [U-Boot] [PATCH v2 2/6] common/cmd_boot: keep ARM v7M in thumb mode during do_go_exec()

[Matt Porter]

On Tue, Apr 21, 2015 at 12:47:24PM -0500, Felipe Balbi wrote:
 On Tue, Apr 21, 2015 at 01:36:54PM -0400, Matt Porter wrote:
  On ARM v7M, the processor will return to ARM mode when executing
  a blx instruction with bit 0 of the address == 0. Always set it
 
 but that's what the 'x' is for, right ? eXchange the CPU mode.

Yes.

  to 1 to stay in thumb mode.
  
  Signed-off-by: Matt Porter mpor...@konsulko.com
  ---
   common/cmd_boot.c | 4 
   1 file changed, 4 insertions(+)
  
  diff --git a/common/cmd_boot.c b/common/cmd_boot.c
  index 8f2e070..20ce652 100644
  --- a/common/cmd_boot.c
  +++ b/common/cmd_boot.c
  @@ -38,6 +38,10 @@ static int do_go(cmd_tbl_t *cmdtp, int flag, int argc, 
  char * const argv[])
   * pass address parameter as argv[0] (aka command name),
   * and all remaining args
   */
  +#ifdef CONFIG_CPU_V7M
  +   /* For ARM V7M, set bit zero to stay in Thumb mode */
  +   addr++;
  +#endif
 
 what if we were in ARM state when we reached this point ? You're now
 telling CPU to always switch to Thumb. Is this really what we want ?

We have no ARM state on this core so that's not possible.

 From ARM's instruction manual:
 
 
 
 
 The BX and BLX instructions can change the processor state from ARM to
 Thumb, or from Thumb to ARM.
 
 BLX label always changes the state.
 
 BX Rm and BLX Rm derive the target state from bit[0] of Rm:
 
 if bit[0] of Rm is 0, the processor changes to, or remains in, ARM
 state
 
 if bit[0] of Rm is 1, the processor changes to, or remains in, Thumb
 state.

Correct. The last statement is why this patch exists. There is no ARM
mode on M3, we immediately fault. Having bit[0]=0 for BX/BLX is not
permitted on V7M...something not covered in the generic description
of these instructions.

Incidentally, I forgot to update this with Kamil's comment that it
should be implemented as |1 and will address that now.

-Matt


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Re: [U-Boot] [PATCH v2 2/6] common/cmd_boot: keep ARM v7M in thumb mode during do_go_exec()

[Matt Porter]

On Tue, Apr 21, 2015 at 12:57:09PM -0500, Felipe Balbi wrote:
 On Tue, Apr 21, 2015 at 12:54:26PM -0500, Felipe Balbi wrote:
  On Tue, Apr 21, 2015 at 12:47:24PM -0500, Felipe Balbi wrote:
   On Tue, Apr 21, 2015 at 01:36:54PM -0400, Matt Porter wrote:
On ARM v7M, the processor will return to ARM mode when executing
a blx instruction with bit 0 of the address == 0. Always set it
   
   but that's what the 'x' is for, right ? eXchange the CPU mode.
   
to 1 to stay in thumb mode.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
 common/cmd_boot.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/common/cmd_boot.c b/common/cmd_boot.c
index 8f2e070..20ce652 100644
--- a/common/cmd_boot.c
+++ b/common/cmd_boot.c
@@ -38,6 +38,10 @@ static int do_go(cmd_tbl_t *cmdtp, int flag, int 
argc, char * const argv[])
 * pass address parameter as argv[0] (aka command name),
 * and all remaining args
 */
+#ifdef CONFIG_CPU_V7M
+   /* For ARM V7M, set bit zero to stay in Thumb mode */
+   addr++;
+#endif
   
   what if we were in ARM state when we reached this point ? You're now
   telling CPU to always switch to Thumb. Is this really what we want ?
   
   From ARM's instruction manual:
   
   
   
   
   The BX and BLX instructions can change the processor state from ARM to
   Thumb, or from Thumb to ARM.
   
   BLX label always changes the state.
   
   BX Rm and BLX Rm derive the target state from bit[0] of Rm:
   
   if bit[0] of Rm is 0, the processor changes to, or remains in, ARM
   state
   
   if bit[0] of Rm is 1, the processor changes to, or remains in, Thumb
   state.
   
  
  oh wait, this is cortex-m, it's supposed to be thumb2 only, why do we
  even need that bit ?
 
 seems like it must be set for cortex-m, but then shouldn't this be done
 by GCC ? Are we, perhaps, using wrong GCC arguments when building for
 cortex-m ?

From make V=1:

... -march=armv7-m -mthumb ...

$ arm-none-eabi-gcc -v
...
gcc version 4.8.3 20140913 (release) (4.8.3-11ubuntu1+11)

-Matt


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Re: [U-Boot] [PATCH 2/6] common/cmd_boot: keep ARM v7M in thumb mode during do_go_exec()

[Matt Porter]

On Wed, Apr 15, 2015 at 08:34:30AM -0400, Tom Rini wrote:
 On Wed, Apr 15, 2015 at 12:33:43PM +0200, Kamil Lulko wrote:
  2015-04-14 20:07 GMT+02:00 Matt Porter mpor...@konsulko.com:
  
   On ARM v7M, the processor will return to ARM mode when executing
   a blx instruction with bit 0 of the address == 0. Always set it
   to 1 to stay in thumb mode.
  
   Signed-off-by: Matt Porter mpor...@konsulko.com
   ---
common/cmd_boot.c | 4 
1 file changed, 4 insertions(+)
  
   diff --git a/common/cmd_boot.c b/common/cmd_boot.c
   index 8f2e070..20ce652 100644
   --- a/common/cmd_boot.c
   +++ b/common/cmd_boot.c
   @@ -38,6 +38,10 @@ static int do_go(cmd_tbl_t *cmdtp, int flag, int argc, 
   char * const argv[])
* pass address parameter as argv[0] (aka command name),
* and all remaining args
*/
   +#ifdef CONFIG_CPU_V7M
   +   /* For ARM V7M, set bit zero to stay in Thumb mode */
   +   addr++;
   +#endif
   rc = do_go_exec ((void *)addr, argc - 1, argv + 1);
   if (rc != 0) rcode = 1;
  
  I think addr |= 1 would be better - there is always a possibility that
  kernel image has the zero bit already set (this is the case in my own
  Buildroot build setup I am using for STM32F4 builds). Anyways -
  keeping this bit set should be the responsibility of kernel image
  build process so such machine specific quirk can be kept out of the
  common code.
 
 I'd agree about |='ing in 1.  But it's not a machine quirk, it's a
 requirement of the Cortex-M family that you not exit Thumb-mode (since
 it's Thumb-only) and given how we end up trying to jump to the address
 (here or in 'go' which Matt didn't post the patch for, but same logic)
 we can / will have problems if we don't do this.  You can work around it
 for images we throw a header into but 'go' is where this gets really
 annoying.

|1 is indeed much better, I will update it for that implementation. Just
to be clear, this patch *is* for the go command which is what I use to
load my RTOS. Kamil's comment implies the bootm path which I don't touch
at all since I don't even support it in this config (we're running full
U-Boot from SRAM and the CMD_BOOTM support is quite large and not
necessary for my application).

I understand the concern about cluttering up common code with this. An
alternative is to force this knowledge on the user such that they need
to go 080203a9 to run a Thumb-2 application located at 0x080203a8.
It's ugly, but could be documented. I'd rather see an address fixup
function or similar approach if we want to avoid cluttering the common
path with ifdefry.

-Matt


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[U-Boot] [PATCH 0/6] Add ARMv7M STM32F1 and STM3210E-EVAL board support

[Matt Porter]

This series adds support for the STM32F1 SoC family and the STM3210E-EVAL
board on top of the STM32F4 SoC family support [1].

Since this board has no DRAM the first patch fixes the build when
CONFIG_NR_DRAM_BANKS is not set. A patch is also required to force the
processor to stay in Thumb mode when 'go'ing to an application.

As the STM32F1 differs greatly from STM32F4 in flash and clock layout,
there's a separate subdirectory for the STM32F1 family. The gpio and
serial drivers are shared as these peripherals are mostly similar with
only the pinmux bits being significantly different in the gpio driver.

The STM3210E-EVAL board is supported with 1MiB Flash and 96KiB of SRAM
on the STM32F103ZGT6, USART1 for console, and four user LEDs.

[1] http://lists.denx.de/pipermail/u-boot/2015-March/206640.html

Matt Porter (6):
  image: fix build when CONFIG_NR_DRAM_BANKS is disabled on ARM
  common/cmd_boot: keep ARM v7M in thumb mode during do_go_exec()
  ARMv7M: add STM32F1 support
  gpio: stm32: add stm32f1 support
  serial: stm32: add stm32f1 support
  board: add stm3210e-eval board support

 arch/arm/Kconfig  |   5 +
 arch/arm/cpu/armv7m/Makefile  |   1 +
 arch/arm/cpu/armv7m/stm32f1/Makefile  |  13 ++
 arch/arm/cpu/armv7m/stm32f1/clock.c   | 195 ++
 arch/arm/cpu/armv7m/stm32f1/flash.c   | 179 +++
 arch/arm/cpu/armv7m/stm32f1/soc.c |  35 ++
 arch/arm/cpu/armv7m/stm32f1/timer.c   | 120 ++
 arch/arm/include/asm/arch-stm32f1/gpio.h  | 117 ++
 arch/arm/include/asm/arch-stm32f1/stm32.h | 115 ++
 board/st/stm3210e-eval/Kconfig|  19 +++
 board/st/stm3210e-eval/MAINTAINERS|   5 +
 board/st/stm3210e-eval/Makefile   |  13 ++
 board/st/stm3210e-eval/stm3210e-eval.c|  85 +
 common/cmd_boot.c |   4 +
 common/image.c|   2 +-
 configs/stm3210e-eval_defconfig   |   3 +
 drivers/gpio/stm32_gpio.c | 103 +++-
 drivers/serial/serial_stm32.c |   7 ++
 include/configs/stm3210e-eval.h   | 117 ++
 include/flash.h   |   1 +
 20 files changed, 1137 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/Makefile
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/clock.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/flash.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/soc.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/timer.c
 create mode 100644 arch/arm/include/asm/arch-stm32f1/gpio.h
 create mode 100644 arch/arm/include/asm/arch-stm32f1/stm32.h
 create mode 100644 board/st/stm3210e-eval/Kconfig
 create mode 100644 board/st/stm3210e-eval/MAINTAINERS
 create mode 100644 board/st/stm3210e-eval/Makefile
 create mode 100644 board/st/stm3210e-eval/stm3210e-eval.c
 create mode 100644 configs/stm3210e-eval_defconfig
 create mode 100644 include/configs/stm3210e-eval.h

-- 
2.1.0

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[U-Boot] [PATCH 2/6] common/cmd_boot: keep ARM v7M in thumb mode during do_go_exec()

[Matt Porter]

On ARM v7M, the processor will return to ARM mode when executing
a blx instruction with bit 0 of the address == 0. Always set it
to 1 to stay in thumb mode.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
 common/cmd_boot.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/common/cmd_boot.c b/common/cmd_boot.c
index 8f2e070..20ce652 100644
--- a/common/cmd_boot.c
+++ b/common/cmd_boot.c
@@ -38,6 +38,10 @@ static int do_go(cmd_tbl_t *cmdtp, int flag, int argc, char 
* const argv[])
 * pass address parameter as argv[0] (aka command name),
 * and all remaining args
 */
+#ifdef CONFIG_CPU_V7M
+   /* For ARM V7M, set bit zero to stay in Thumb mode */
+   addr++;
+#endif
rc = do_go_exec ((void *)addr, argc - 1, argv + 1);
if (rc != 0) rcode = 1;
 
-- 
2.1.0

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[U-Boot] [PATCH 1/6] image: fix build when CONFIG_NR_DRAM_BANKS is disabled on ARM

[Matt Porter]

common/image.c currently implicitly depends on CONFIG_NR_DRAM_BANKS
when CONFIG_ARM is enabled. Make this requirement explicit.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
 common/image.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/image.c b/common/image.c
index 162b682..73c24f5 100644
--- a/common/image.c
+++ b/common/image.c
@@ -461,7 +461,7 @@ phys_size_t getenv_bootm_size(void)
tmp = 0;
 
 
-#if defined(CONFIG_ARM)
+#if defined(CONFIG_ARM)  defined(CONFIG_NR_DRAM_BANKS)
return gd-bd-bi_dram[0].size - tmp;
 #else
return gd-bd-bi_memsize - tmp;
-- 
2.1.0

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[U-Boot] [PATCH 3/6] ARMv7M: add STM32F1 support

[Matt Porter]

Add ARMv7M STM32F1 support including clocks, timer, gpio, and flash.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
 arch/arm/cpu/armv7m/Makefile  |   1 +
 arch/arm/cpu/armv7m/stm32f1/Makefile  |  13 ++
 arch/arm/cpu/armv7m/stm32f1/clock.c   | 195 ++
 arch/arm/cpu/armv7m/stm32f1/flash.c   | 179 +++
 arch/arm/cpu/armv7m/stm32f1/soc.c |  35 ++
 arch/arm/cpu/armv7m/stm32f1/timer.c   | 120 ++
 arch/arm/include/asm/arch-stm32f1/gpio.h  | 117 ++
 arch/arm/include/asm/arch-stm32f1/stm32.h | 115 ++
 include/flash.h   |   1 +
 9 files changed, 776 insertions(+)
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/Makefile
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/clock.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/flash.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/soc.c
 create mode 100644 arch/arm/cpu/armv7m/stm32f1/timer.c
 create mode 100644 arch/arm/include/asm/arch-stm32f1/gpio.h
 create mode 100644 arch/arm/include/asm/arch-stm32f1/stm32.h

diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile
index b662e03..93a1956 100644
--- a/arch/arm/cpu/armv7m/Makefile
+++ b/arch/arm/cpu/armv7m/Makefile
@@ -8,4 +8,5 @@
 extra-y := start.o
 obj-y += cpu.o
 
+obj-$(CONFIG_STM32F1) += stm32f1/
 obj-$(CONFIG_STM32F4) += stm32f4/
diff --git a/arch/arm/cpu/armv7m/stm32f1/Makefile 
b/arch/arm/cpu/armv7m/stm32f1/Makefile
new file mode 100644
index 000..7b43761
--- /dev/null
+++ b/arch/arm/cpu/armv7m/stm32f1/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# (C) Copyright 2015
+# Kamil Lulko, re...@wp.pl
+#
+# Copyright 2015 Konsulko Group, Matt Porter mpor...@konsulko.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += soc.o clock.o timer.o flash.o
diff --git a/arch/arm/cpu/armv7m/stm32f1/clock.c 
b/arch/arm/cpu/armv7m/stm32f1/clock.c
new file mode 100644
index 000..b921eff
--- /dev/null
+++ b/arch/arm/cpu/armv7m/stm32f1/clock.c
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, re...@wp.pl
+ *
+ * Copyright 2015 Konsulko Group, Matt Porter mpor...@konsulko.com
+ *
+ * (C) Copyright 2014
+ * STMicroelectronics
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/stm32.h
+
+#define RCC_CR_HSION   (1  0)
+#define RCC_CR_HSEON   (1  16)
+#define RCC_CR_HSERDY  (1  17)
+#define RCC_CR_HSEBYP  (1  18)
+#define RCC_CR_CSSON   (1  19)
+#define RCC_CR_PLLON   (1  24)
+#define RCC_CR_PLLRDY  (1  25)
+
+#define RCC_CFGR_PLLMUL_MASK   0x3C
+#define RCC_CFGR_PLLMUL_SHIFT  18
+#define RCC_CFGR_PLLSRC_HSE(1  16)
+
+#define RCC_CFGR_AHB_PSC_MASK  0xF0
+#define RCC_CFGR_APB1_PSC_MASK 0x700
+#define RCC_CFGR_APB2_PSC_MASK 0x3800
+#define RCC_CFGR_SW0   (1  0)
+#define RCC_CFGR_SW1   (1  1)
+#define RCC_CFGR_SW_MASK   0x3
+#define RCC_CFGR_SW_HSI0
+#define RCC_CFGR_SW_HSERCC_CFGR_SW0
+#define RCC_CFGR_SW_PLLRCC_CFGR_SW1
+#define RCC_CFGR_SWS0  (1  2)
+#define RCC_CFGR_SWS1  (1  3)
+#define RCC_CFGR_SWS_MASK  0xC
+#define RCC_CFGR_SWS_HSI   0
+#define RCC_CFGR_SWS_HSE   RCC_CFGR_SWS0
+#define RCC_CFGR_SWS_PLL   RCC_CFGR_SWS1
+#define RCC_CFGR_HPRE_SHIFT4
+#define RCC_CFGR_PPRE1_SHIFT   8
+#define RCC_CFGR_PPRE2_SHIFT   11
+
+#define RCC_APB1ENR_PWREN  (1  28)
+
+#define PWR_CR_VOS0(1  14)
+#define PWR_CR_VOS1(1  15)
+#define PWR_CR_VOS_MASK0xC000
+#define PWR_CR_VOS_SCALE_MODE_1(PWR_CR_VOS0 | PWR_CR_VOS1)
+#define PWR_CR_VOS_SCALE_MODE_2(PWR_CR_VOS1)
+#define PWR_CR_VOS_SCALE_MODE_3(PWR_CR_VOS0)
+
+#define FLASH_ACR_WS(n)n
+#define FLASH_ACR_PRFTEN   (1  8)
+#define FLASH_ACR_ICEN (1  9)
+#define FLASH_ACR_DCEN (1  10)
+
+struct psc {
+   u8  ahb_psc;
+   u8  apb1_psc;
+   u8  apb2_psc;
+};
+
+#define AHB_PSC_1  0
+#define AHB_PSC_2  0x8
+#define AHB_PSC_4  0x9
+#define AHB_PSC_8  0xA
+#define AHB_PSC_16 0xB
+#define AHB_PSC_64 0xC
+#define AHB_PSC_1280xD
+#define AHB_PSC_2560xE
+#define AHB_PSC_5120xF
+
+#define APB_PSC_1  0
+#define APB_PSC_2  0x4
+#define APB_PSC_4  0x5
+#define APB_PSC_8  0x6
+#define APB_PSC_16 0x7
+
+#if !defined(CONFIG_STM32_HSE_HZ)
+#error CONFIG_STM32_HSE_HZ not defined!
+#else
+#if (CONFIG_STM32_HSE_HZ == 800)
+#define RCC_CFGR_PLLMUL_CFG0x7
+struct psc psc_hse = {
+   .ahb_psc = AHB_PSC_1,
+   .apb1_psc = APB_PSC_2,
+   .apb2_psc = APB_PSC_1
+};
+#else
+#error No PLL/Prescaler configuration

[U-Boot] [PATCH 5/6] serial: stm32: add stm32f1 support

[Matt Porter]

Add support for the STM32F1 famly to the STM32 serial driver.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
 drivers/serial/serial_stm32.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
index 3c80096..a0397e1 100644
--- a/drivers/serial/serial_stm32.c
+++ b/drivers/serial/serial_stm32.c
@@ -2,6 +2,8 @@
  * (C) Copyright 2015
  * Kamil Lulko, re...@wp.pl
  *
+ * Copyright 2015 Konsulko Group, Matt Porter mpor...@konsulko.com
+ *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
@@ -10,8 +12,13 @@
 #include serial.h
 #include asm/arch/stm32.h
 
+#ifdef CONFIG_STM32F4
 #define STM32_USART1_BASE  (STM32_APB2PERIPH_BASE + 0x1000)
 #define RCC_APB2ENR_USART1EN   (1  4)
+#else
+#define STM32_USART1_BASE  (STM32_APB2PERIPH_BASE + 0x3800)
+#define RCC_APB2ENR_USART1EN   (1  14)
+#endif
 
 #define USART_BASE STM32_USART1_BASE
 #define RCC_USART_ENABLE   RCC_APB2ENR_USART1EN
-- 
2.1.0

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[U-Boot] [PATCH 6/6] board: add stm3210e-eval board support

[Matt Porter]

Add support for the STM32F1-based stm3210e-eval boards
from ST. UART, Flash, GPIO, and LEDs are supported.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
 arch/arm/Kconfig   |   5 ++
 board/st/stm3210e-eval/Kconfig |  19 ++
 board/st/stm3210e-eval/MAINTAINERS |   5 ++
 board/st/stm3210e-eval/Makefile|  13 
 board/st/stm3210e-eval/stm3210e-eval.c |  85 
 configs/stm3210e-eval_defconfig|   3 +
 include/configs/stm3210e-eval.h| 117 +
 7 files changed, 247 insertions(+)
 create mode 100644 board/st/stm3210e-eval/Kconfig
 create mode 100644 board/st/stm3210e-eval/MAINTAINERS
 create mode 100644 board/st/stm3210e-eval/Makefile
 create mode 100644 board/st/stm3210e-eval/stm3210e-eval.c
 create mode 100644 configs/stm3210e-eval_defconfig
 create mode 100644 include/configs/stm3210e-eval.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4eb047c..bcf4e46 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -731,6 +731,10 @@ config ARCH_UNIPHIER
select SPL
select OF_CONTROL
 
+config TARGET_STM3210E_EVAL
+   bool Support STM3210E-EVAL board
+   select CPU_V7M
+
 config TARGET_STM32F429_DISCOVERY
bool Support STM32F429 Discovery
select CPU_V7M
@@ -872,6 +876,7 @@ source board/spear/spear600/Kconfig
 source board/spear/x600/Kconfig
 source board/st-ericsson/snowball/Kconfig
 source board/st-ericsson/u8500/Kconfig
+source board/st/stm3210e-eval/Kconfig
 source board/st/stm32f429-discovery/Kconfig
 source board/st/stv0991/Kconfig
 source board/sunxi/Kconfig
diff --git a/board/st/stm3210e-eval/Kconfig b/board/st/stm3210e-eval/Kconfig
new file mode 100644
index 000..49bc770
--- /dev/null
+++ b/board/st/stm3210e-eval/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_STM3210E_EVAL
+
+config SYS_BOARD
+   string
+   default stm3210e-eval
+
+config SYS_VENDOR
+   string
+   default st
+
+config SYS_SOC
+   string
+   default stm32f1
+
+config SYS_CONFIG_NAME
+   string
+   default stm3210e-eval
+
+endif
diff --git a/board/st/stm3210e-eval/MAINTAINERS 
b/board/st/stm3210e-eval/MAINTAINERS
new file mode 100644
index 000..0f9f31b
--- /dev/null
+++ b/board/st/stm3210e-eval/MAINTAINERS
@@ -0,0 +1,5 @@
+M: Matt Porter mpor...@konsulko.com
+S: Maintained
+F: board/st/stm3210e-eval/
+F: include/configs/stm3210e-eval.h
+F: configs/stm3210e-eval_defconfig
diff --git a/board/st/stm3210e-eval/Makefile b/board/st/stm3210e-eval/Makefile
new file mode 100644
index 000..b018e08
--- /dev/null
+++ b/board/st/stm3210e-eval/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# (C) Copyright 2015
+# Kamil Lulko, re...@wp.pl
+#
+# Copyright 2015 Konsulko Group, Matt Porter mpor...@konsulko.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := stm3210e-eval.o
diff --git a/board/st/stm3210e-eval/stm3210e-eval.c 
b/board/st/stm3210e-eval/stm3210e-eval.c
new file mode 100644
index 000..a801983
--- /dev/null
+++ b/board/st/stm3210e-eval/stm3210e-eval.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2011, 2012, 2013
+ * Yuri Tikhonov, Emcraft Systems, y...@emcraft.com
+ * Alexander Potashev, Emcraft Systems, aspotas...@emcraft.com
+ * Vladimir Khusainov, Emcraft Systems, v...@emcraft.com
+ * Pavel Boldin, Emcraft Systems, pabol...@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, re...@wp.pl
+ *
+ * Copyright 2015 Konsulko Group, Matt Porter mpor...@konsulko.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/armv7m.h
+#include asm/arch/stm32.h
+#include asm/arch/gpio.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct stm32_gpio_ctl gpio_ctl_usart[] = {
+   /* TX */
+   {
+   .mode = STM32_GPIO_MODE_OUT_50M,
+   .ocnf = STM32_GPIO_OCNF_AF_PP,
+   },
+   /* RX */
+   {
+   .mode = STM32_GPIO_MODE_IN,
+   .icnf = STM32_GPIO_ICNF_IN_FLT,
+   }
+};
+
+static const struct stm32_gpio_dsc usart1_gpio[] = {
+   {STM32_GPIO_PORT_A, STM32_GPIO_PIN_9},  /* TX */
+   {STM32_GPIO_PORT_A, STM32_GPIO_PIN_10}, /* RX */
+};
+
+int uart2_setup_gpio(void)
+{
+   int i;
+   int rv = 0;
+
+   for (i = 0; i  ARRAY_SIZE(usart1_gpio); i++) {
+   rv = stm32_gpio_config(usart1_gpio[i], gpio_ctl_usart[i]);
+   if (rv)
+   goto out;
+   }
+
+out:
+   return rv;
+}
+
+int dram_init(void)
+{
+   gd-ram_size = CONFIG_SYS_RAM_SIZE;
+
+   return 0;
+}
+
+u32 get_board_rev(void)
+{
+   return 0;
+}
+
+int board_early_init_f(void)
+{
+   int res;
+
+   res = uart2_setup_gpio();
+   if (res)
+   return res;
+
+   return 0;
+}
+
+int board_init(void)
+{
+   gd-bd-bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+   return 0;
+}
diff --git a/configs

[U-Boot] [PATCH 4/6] gpio: stm32: add stm32f1 support

[Matt Porter]

Add support for the STM32F1 family to the STM32 gpio driver.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
 drivers/gpio/stm32_gpio.c | 103 +-
 1 file changed, 102 insertions(+), 1 deletion(-)

diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c
index d3497e9..9174414 100644
--- a/drivers/gpio/stm32_gpio.c
+++ b/drivers/gpio/stm32_gpio.c
@@ -5,6 +5,8 @@
  * (C) Copyright 2015
  * Kamil Lulko, re...@wp.pl
  *
+ * Copyright 2015 Konsulko Group, Matt Porter mpor...@konsulko.com
+ *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
@@ -16,6 +18,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef STM32_F4
 #define STM32_GPIOA_BASE   (STM32_AHB1PERIPH_BASE + 0x)
 #define STM32_GPIOB_BASE   (STM32_AHB1PERIPH_BASE + 0x0400)
 #define STM32_GPIOC_BASE   (STM32_AHB1PERIPH_BASE + 0x0800)
@@ -90,6 +93,90 @@ int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
 out:
return rv;
 }
+#else
+#define STM32_GPIOA_BASE   (STM32_APB2PERIPH_BASE + 0x0800)
+#define STM32_GPIOB_BASE   (STM32_APB2PERIPH_BASE + 0x0C00)
+#define STM32_GPIOC_BASE   (STM32_APB2PERIPH_BASE + 0x1000)
+#define STM32_GPIOD_BASE   (STM32_APB2PERIPH_BASE + 0x1400)
+#define STM32_GPIOE_BASE   (STM32_APB2PERIPH_BASE + 0x1800)
+#define STM32_GPIOF_BASE   (STM32_APB2PERIPH_BASE + 0x1C00)
+#define STM32_GPIOG_BASE   (STM32_APB2PERIPH_BASE + 0x2000)
+
+static const unsigned long io_base[] = {
+   STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
+   STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
+   STM32_GPIOG_BASE
+};
+
+#define STM32_GPIO_CR_MODE_MASK0x3
+#define STM32_GPIO_CR_MODE_SHIFT(p)(p * 4)
+#define STM32_GPIO_CR_CNF_MASK 0x3
+#define STM32_GPIO_CR_CNF_SHIFT(p) (p * 4 + 2)
+
+struct stm32_gpio_regs {
+   u32 crl;/* GPIO port configuration low */
+   u32 crh;/* GPIO port configuration high */
+   u32 idr;/* GPIO port input data */
+   u32 odr;/* GPIO port output data */
+   u32 bsrr;   /* GPIO port bit set/reset */
+   u32 brr;/* GPIO port bit reset */
+   u32 lckr;   /* GPIO port configuration lock */
+};
+
+#define CHECK_DSC(x)   (!x || x-port  6 || x-pin  15)
+#define CHECK_CTL(x)   (!x || x-mode  3 || x-icnf  3 || x-ocnf  3 || \
+x-pupd  1)
+
+int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
+   const struct stm32_gpio_ctl *ctl)
+{
+   struct stm32_gpio_regs *gpio_regs;
+   u32 *cr;
+   int p, crp;
+   int rv;
+
+   if (CHECK_DSC(dsc)) {
+   rv = -EINVAL;
+   goto out;
+   }
+   if (CHECK_CTL(ctl)) {
+   rv = -EINVAL;
+   goto out;
+   }
+
+   p = dsc-pin;
+
+   gpio_regs = (struct stm32_gpio_regs *)io_base[dsc-port];
+
+   /* Enable clock for GPIO port */
+   setbits_le32(STM32_RCC-apb2enr, 0x04  dsc-port);
+
+   if (p  8) {
+   cr = gpio_regs-crl;
+   crp = p;
+   } else {
+   cr = gpio_regs-crh;
+   crp = p - 8;
+   }
+
+   clrbits_le32(cr, 0x3  STM32_GPIO_CR_MODE_SHIFT(crp));
+   setbits_le32(cr, ctl-mode  STM32_GPIO_CR_MODE_SHIFT(crp));
+
+   clrbits_le32(cr, 0x3  STM32_GPIO_CR_CNF_SHIFT(crp));
+   /* Inputs set the optional pull up / pull down */
+   if (ctl-mode == STM32_GPIO_MODE_IN) {
+   setbits_le32(cr, ctl-icnf  STM32_GPIO_CR_CNF_SHIFT(crp));
+   clrbits_le32(gpio_regs-odr, 0x1  p);
+   setbits_le32(gpio_regs-odr, ctl-pupd  p);
+   } else {
+   setbits_le32(cr, ctl-ocnf  STM32_GPIO_CR_CNF_SHIFT(crp));
+   }
+
+   rv = 0;
+out:
+   return rv;
+}
+#endif
 
 int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state)
 {
@@ -148,10 +235,18 @@ int gpio_direction_input(unsigned gpio)
 
dsc.port = stm32_gpio_to_port(gpio);
dsc.pin = stm32_gpio_to_pin(gpio);
+#ifdef STM32_F4
ctl.af = STM32_GPIO_AF0;
ctl.mode = STM32_GPIO_MODE_IN;
+   ctl.otype = STM32_GPIO_OTYPE_PP;
ctl.pupd = STM32_GPIO_PUPD_NO;
ctl.speed = STM32_GPIO_SPEED_50M;
+#else
+   ctl.mode = STM32_GPIO_MODE_IN;
+   ctl.icnf = STM32_GPIO_ICNF_IN_FLT;
+   ctl.ocnf = STM32_GPIO_OCNF_GP_PP;   /* ignored for input */
+   ctl.pupd = STM32_GPIO_PUPD_UP;  /* ignored for floating */
+#endif
 
return stm32_gpio_config(dsc, ctl);
 }
@@ -164,11 +259,17 @@ int gpio_direction_output(unsigned gpio, int value)
 
dsc.port = stm32_gpio_to_port(gpio);
dsc.pin = stm32_gpio_to_pin(gpio);
+#ifdef STM32_F4
ctl.af = STM32_GPIO_AF0;
ctl.mode = STM32_GPIO_MODE_OUT;
-   ctl.otype = STM32_GPIO_OTYPE_PP;
ctl.pupd = STM32_GPIO_PUPD_NO;
ctl.speed = STM32_GPIO_SPEED_50M;
+#else
+   ctl.mode = STM32_GPIO_MODE_OUT_50M;
+   ctl.ocnf = STM32_GPIO_OCNF_GP_PP

[U-Boot] [PATCH] image: fix build when CONFIG_NR_DRAM_BANKS is disabled on ARM

[Matt Porter]

common/image.c currently implicitly depends on CONFIG_NR_DRAM_BANKS
when CONFIG_ARM is enabled. Make this requirement explicit.

Signed-off-by: Matt Porter mpor...@konsulko.com
---
 common/image.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/image.c b/common/image.c
index a911aa9..13e68a0 100644
--- a/common/image.c
+++ b/common/image.c
@@ -460,7 +460,7 @@ phys_size_t getenv_bootm_size(void)
tmp = 0;
 
 
-#if defined(CONFIG_ARM)
+#if defined(CONFIG_ARM)  defined(CONFIG_NR_DRAM_BANKS)
return gd-bd-bi_dram[0].size - tmp;
 #else
return gd-bd-bi_memsize - tmp;
-- 
2.1.4

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Re: [U-Boot] [PATCH V6 00/11] ARM: OMAP3-DRA7: CP15 erratum workarounds and improvements

[Matt Porter]

On Wed, Mar 11, 2015 at 12:00:59PM -0400, Tom Rini wrote:
 On Wed, Mar 11, 2015 at 10:51:12AM -0500, Nishanth Menon wrote:
  On Wed, Mar 11, 2015 at 10:48 AM, Tom Rini tr...@konsulko.com wrote:
   On Mon, Mar 09, 2015 at 05:11:58PM -0500, Nishanth Menon wrote:
  
   The sixth revision should be proper, I hope. (skipping all the
   blurb and pointing to v1 for the blurb).
  
   Changes since v5:
 - omap_smc1 is now in omap_common.h
 - I hope we can pick up Matt's Tested-by tag from previous rev..
 
   http://article.gmane.org/gmane.comp.boot-loaders.u-boot/214277
  
   In the future please collect those :)  Or would that be too different
   from kernel policy?
  
  I did change code as per rev5 review comments, so was'nt too sure if i
  could carry the tested-by tag over..
 
 Ah yes.  Matt, would you have time to test it all again?  Thanks!

Yes.

Reconfirmed that v6 is working properly on both beagles. The xM has
the erratum workaround applied and the omap3530 beagleboard does not
have it applied as expected. Feel free to keep my Tested-by.

-Matt


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Re: [U-Boot] [PATCH V5 00/11] ARM: OMAP3-DRA7: CP15 erratum workarounds and improvements

[Matt Porter]

On Thu, Mar 05, 2015 at 10:40:55PM -0600, Nishanth Menon wrote:
 The fifth incarnation should be proper, I hope. (skipping all the
 blurb and pointing to v1 for the blurb).
 
 Changes since v4:
   - smc is back to handassembled thanks to gcc versions
   - fixes in multiple call handling within cpu_init_cp15 - thanks to 
 Matt Porter's test log showing fail on r1p3 cortex-a8 (where the errata must 
 be applied)
 
 v4: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/213863
 V3: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/213207/focus=213307
 V2: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213060
 V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174
 
 This time, the series is based on u-boot master
 git://git.denx.de/u-boot.git
 master 694cc87b76b1 arm, da8xx: convert ipam390 board to generic board support
 
 Git tree: https://gitorious.org/nm-kernel/u-boot-nm (at least till gitorious 
 is around..)
 branch errata-v5-master-694cc87b76b1
 
 Git link: https://gitorious.org/nm-kernel/u-boot-nm.git 
 errata-v5-master-694cc87b76b1
 
 Testing: with http://paste.ubuntu.org.cn/2522971 (4.0-rc1 patch)
 
 BeagleBoard-X15:
   Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x 
 L2PFR=0x09b0 ACTLR=0x0040
   After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x0198 
 L2PFR=0x09b0 ACTLR=0x0040
 
 OMAP5uEVM:
   Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x 
 L2PFR=0x09b0 ACTLR=0x0040
   After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x0198 
 L2PFR=0x09b0 ACTLR=0x0040
 
 Beagle-XM: this is a r3p2 cortex-a8
   Before: CPUID=0x413fc082 ACR=0x00e2 L2AUXCR=0x0042
   After: CPUID=0x413fc082 ACR=0x0042 L2AUXCR=0x0042
   To emulate matt's board, I hacked u-boot to force the code flow.
   Testing with (hack http://paste.ubuntu.org.cn/2525559): 
 CPUID=0x413fc082 ACR=0x00e2 L2AUXCR=0x0042
 
 I dont have access to other omap3 platforms to give a better coverage,
 so, I welcome as much testing as possible.

Also verified again here on my r1p2 Beagle.  No more build issues on
any of my toolchains, thanks.

Tested-by: Matt Porter mpor...@konsulko.com

 Nishanth Menon (10):
   ARM: Introduce erratum workaround for 798870
   ARM: Introduce erratum workaround for 454179
   ARM: Introduce erratum workaround for 430973
   ARM: Introduce erratum workaround for 621766
   ARM: OMAP: Change set_pl310_ctrl_reg to be generic
   ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs
   ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with
 omap_smc1
   ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended
 configuration
   ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766
   ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973,
 621766
 
 Praveen Rao (1):
   ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
 
  README |8 +++
  arch/arm/cpu/armv7/Makefile|2 +-
  arch/arm/cpu/armv7/cp15.c  |   29 +
  arch/arm/cpu/armv7/omap-common/Makefile|2 +-
  arch/arm/cpu/armv7/omap-common/lowlevel_init.S |   20 +++---
  arch/arm/cpu/armv7/omap3/board.c   |   60 +++---
  arch/arm/cpu/armv7/omap3/lowlevel_init.S   |   11 
  arch/arm/cpu/armv7/omap4/hwinit.c  |4 +-
  arch/arm/cpu/armv7/omap5/hwinit.c  |   23 +++
  arch/arm/cpu/armv7/start.S |   64 
 +++-
  .../arm/include/asm/arch-omap3/{omap3.h = omap.h} |0
  arch/arm/include/asm/arch-omap3/sys_proto.h|3 +-
  arch/arm/include/asm/arch-omap4/sys_proto.h|5 +-
  arch/arm/include/asm/arch-omap5/sys_proto.h|4 ++
  arch/arm/include/asm/armv7.h   |5 ++
  board/nokia/rx51/rx51.c|   19 +++---
  include/configs/am3517_crane.h |6 +-
  include/configs/am3517_evm.h   |6 +-
  include/configs/cm_t35.h   |6 +-
  include/configs/cm_t3517.h |6 +-
  include/configs/dig297.h   |6 +-
  include/configs/mcx.h  |6 +-
  include/configs/nokia_rx51.h   |6 +-
  include/configs/omap3_evm.h|2 +-
  include/configs/omap3_evm_common.h |4 ++
  include/configs/omap3_evm_quick_mmc.h  |2 +-
  include/configs/omap3_evm_quick_nand.h |2 +-
  include/configs/omap3_logic.h  |6 +-
  include/configs/omap3_mvblx.h  |6 +-
  include/configs/omap3_pandora.h|6 +-
  include/configs/omap3_sdp3430.h|6 +-
  include/configs

Re: [U-Boot] [PATCH V4 00/11] ARM: OMAP3-DRA7: CP15 erratum workarounds and improvements

[Matt Porter]

On Thu, Mar 05, 2015 at 11:56:54AM -0600, Nishanth Menon wrote:
 On 03/05/2015 10:21 AM, Matt Porter wrote:
  On Tue, Mar 03, 2015 at 04:26:17PM -0600, Nishanth Menon wrote:
  The fourth incarnation of this series to address review comments on V3
 
  With all the usual disclaimers and request to see V1 of the series for a
  detailed blurb.. As usual additional testing preferred.. Sorry, I dont have
  access to all possible variants atm..
 
  changes since v3:
 - few corrections - i have tried to do a push-pop of register params.
   hopefully, they should do the job
 - smc with a makefile handling of secure-ext enablement.. (stolen from 
  kernel).
 
  V3: 
  http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/213207/focus=213307
  V2: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213060
  V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174
 
  Testing: with http://paste.ubuntu.org.cn/2522971 (4.0-rc1 patch)
 
  BeagleBoard-X15: http://pastebin.ubuntu.com/10518934/
 Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x 
  L2PFR=0x09b0 ACTLR=0x0040
 After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x0198 
  L2PFR=0x09b0 ACTLR=0x0040
 
  OMAP5uEVM: http://pastebin.ubuntu.com/10518958/
 Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x 
  L2PFR=0x09b0 ACTLR=0x0040
 After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x0198 
  L2PFR=0x09b0 ACTLR=0x0040
 
  Beagle-XM: http://pastebin.ubuntu.com/10519417/ (this is a r2p3 device)
 Before: CPUID=0x413fc082 ACR=0x00e2 L2AUXCR=0x0042
 After: CPUID=0x413fc082 ACR=0x0042 L2AUXCR=0x0042
  
  I also got the same results on a Beagle-XM Rev. C1
   
  I dont have access to other omap3 platforms to give a better coverage
  
  Beagle Rev. C2 (OMAP3530): http://pastebin.com/f5JcvRf4 
  Before: CPUID=0x411fc083 ACR=0x00e2 L2AUXCR=0x0042
  After: CPUID=0x411fc083 ACR=0x0042 L2AUXCR=0x0042
  
  Tested-by: Matt Porter mpor...@konsulko.com
 
 Thanks for testing.
 
  [With build workaround I noted elsewhere in the thread]
  
 that should have been a r1p3 device(needs errata), right and mine
 should really be a r3p2?

Correct. My 3530 beagle is r1p3 and your xM is r3p2.

 Did i get the code wrong here? Need some additional eyes here :(

I verified by inspection that your code below is fine but I also shoved
it into a command line app with some doctored r1 content and confirmed
that it really does work for the r3p2 case. So I'm not yet clear as
to why it's engaging the erratum fix for r3p2.

-Matt

 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/Bhccjgga.html
 
 mrc p15, 0, r1, c0, c0, 0   @ r1 has Read Main ID Register (MIDR)
 mov r3, r1, lsr #20 @ get variant field
 and r3, r3, #0xf@ r3 has CPU variant
 and r4, r1, #0xf@ r4 has CPU revision
 
 mov r2, r3, lsl #4  @ shift variant field for combined value
 orr r2, r4, r2  @ r2 has combined CPU variant + revision
 
  cmp r2, #0x21   @ Only on  r2p1
  bge skip_errata_621766
 
 
 -- 
 Regards,
 Nishanth Menon
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Re: [U-Boot] [PATCH V4 05/11] ARM: OMAP: Change set_pl310_ctrl_reg to be generic

[Matt Porter]

On Thu, Mar 05, 2015 at 11:49:05AM -0600, Nishanth Menon wrote:
 On 03/05/2015 08:00 AM, Matt Porter wrote:
  On Tue, Mar 03, 2015 at 04:26:22PM -0600, Nishanth Menon wrote:
  set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
  PL310 control register, however, that is something that is generic
  enough to be used for OMAP5 generation of processors as well. The only
  difference being the service being invoked for the function.
 
  So, convert the service to a macro and use a generic name (same as
  that used in Linux for some consistency). While at that, also add a
  data barrier which is necessary as per recommendation.
 
  While at this, switch over to smc #0 instead of handcoded assembly.
  To ensure gcc compatibility, steal the strategy used by Linux kernel
  for sec extension builds (NOTE: we no longer use '-march=armv5' as the
  legacy comment claims).
  
  Hi Nishanth,
  
  I applied this series with fuzz and fixed a minor conflict on master. I
  ran into a build issue for omap3 beagle with the sec extension scheme on
  the gcc version 4.7.4 (Ubuntu/Linaro 4.7.4-2ubuntu1) toolchain:
  
   arm-linux-gnueabi-gcc
  -Wp,-MD,arch/arm/cpu/armv7/omap3/.lowlevel_init.o.d  -nostdinc -isystem
  /usr/lib/gcc-cross/arm-linux-gnueabi/4.7/include -Iinclude  -I../include
  -I../arch/arm/include -include ../include/linux/kconfig.h -D__KERNEL__
  -D__UBOOT__ -DCONFIG_SYS_TEXT_BASE=0x8010 -D__ASSEMBLY__ -g
  -D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux
  -mword-relocations -march=armv7-a -mno-unaligned-access
  -ffunction-sections -fdata-sections -fno-common -ffixed-r9 -msoft-float
  -pipe   -c -o arch/arm/cpu/armv7/omap3/lowlevel_init.o
  ../arch/arm/cpu/armv7/omap3/lowlevel_init.S
  
  ../arch/arm/cpu/armv7/omap-common/lowlevel_init.S: Assembler messages:
  ../arch/arm/cpu/armv7/omap-common/lowlevel_init.S:34: Error: selected
  processor does not support ARM mode `smc #0'
  
  I've worked around this for the moment by placing an explicit
  .arch_extension sec in lowlevel_init.S but hopefully you have some
  thoughts on why those flags don't seem to be picked up. I'll continue
  to take a look at it in the meantime.
  
 
 
 Uggh.. this is weird. I had considered .arch_extension sec in
 lowlevel_init.S

Yeah, no worries, I'm not suggesting that. Just a temporary workaround.

  +plus_sec := $(call as-instr,.arch_extension sec,+sec)
  +AFLAGS_lowlevel_init.o   :=-Wa,-march=armv7-a$(plus_sec)
 
 seems to be what we have in kernel and seems to do the job for me on

right

 $ arm-linux-gnueabi-gcc --version
 arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.6.3-1ubuntu5) 4.6.3
 
 $ git clean -fdx; make omap3_beagle_defconfig;
 make V=1 arch/arm/cpu/armv7/omap-common/lowlevel_init.o
 
 with gcc 4.6:
 arm-linux-gnueabi-gcc
 -Wp,-MD,arch/arm/cpu/armv7/omap-common/.lowlevel_init.o.d  -nostdinc
 -isystem /usr/lib/gcc/arm-linux-gnueabi/4.6/include -Iinclude
 -I./arch/arm/include -include ./include/linux/kconfig.h -D__KERNEL__
 -D__UBOOT__ -DCONFIG_SYS_TEXT_BASE=0x8010  -D__ASSEMBLY__ -g
 -D__ARM__ -marm -mno-thumb-interwork  -mabi=aapcs-linux
 -mword-relocations  -march=armv7-a  -mno-unaligned-access
 -ffunction-sections -fdata-sections -fno-common -ffixed-r9
 -msoft-float  -pipe   -Wa,-march=armv7-a+sec   -c -o
 arch/arm/cpu/armv7/omap-common/lowlevel_init.o
 arch/arm/cpu/armv7/omap-common/lowlevel_init.S

I also succeed here..and on a gcc 4.8.2 toolchain
 
 with gcc 4.7:
 arm-linux-gnueabi-gcc
 -Wp,-MD,arch/arm/cpu/armv7/omap-common/.lowlevel_init.o.d  -nostdinc
 -isystem /usr/lib/gcc-cross/arm-linux-gnueabi/4.7/include -Iinclude
 -I./arch/arm/include -include ./include/linux/kconfig.h -D__KERNEL__
 -D__UBOOT__ -DCONFIG_SYS_TEXT_BASE=0x8010  -D__ASSEMBLY__ -g
 -D__ARM__ -marm -mno-thumb-interwork  -mabi=aapcs-linux
 -mword-relocations  -march=armv7-a  -mno-unaligned-access
 -ffunction-sections -fdata-sections -fno-common -ffixed-r9
 -msoft-float  -pipe  -Wa,-march=armv7-a   -c -o
 arch/arm/cpu/armv7/omap-common/lowlevel_init.o
 arch/arm/cpu/armv7/omap-common/lowlevel_init.S
 arch/arm/cpu/armv7/omap-common/lowlevel_init.S: Assembler messages:
 arch/arm/cpu/armv7/omap-common/lowlevel_init.S:34: Error: selected
 processor does not support ARM mode `smc #0'
 make[1]: *** [arch/arm/cpu/armv7/omap-common/lowlevel_init.o] Error 1
 make: *** [arch/arm/cpu/armv7/omap-common/lowlevel_init.o] Error 2
 
 I thought I stole the exact code from kernel, but as you can probably
 see -march=armv7-a+sec was generated for gcc 4.6 but -march=armv7-a
 without +sec for gcc 4.7!

Yeah, so I played a bit with the low-level checks and noted the
following results.

gcc version 4.7.4 (Ubuntu/Linaro 4.7.4-2ubuntu1):

$ printf %b\n .arch_extension sec | arm-linux-gnueabi-gcc -c -x
assembler -; echo $?
{standard input}: Assembler messages:
{standard input}:1: Error: architectural extension `sec' is not allowed
for the current base architecture
1

gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4)

$ printf %b\n

Re: [U-Boot] [PATCH V4 00/11] ARM: OMAP3-DRA7: CP15 erratum workarounds and improvements

[Matt Porter]

On Tue, Mar 03, 2015 at 04:26:17PM -0600, Nishanth Menon wrote:
 The fourth incarnation of this series to address review comments on V3
 
 With all the usual disclaimers and request to see V1 of the series for a
 detailed blurb.. As usual additional testing preferred.. Sorry, I dont have
 access to all possible variants atm..
 
 changes since v3:
   - few corrections - i have tried to do a push-pop of register params.
 hopefully, they should do the job
   - smc with a makefile handling of secure-ext enablement.. (stolen from 
 kernel).
 
 V3: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/213207/focus=213307
 V2: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213060
 V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174
 
 Testing: with http://paste.ubuntu.org.cn/2522971 (4.0-rc1 patch)
 
 BeagleBoard-X15: http://pastebin.ubuntu.com/10518934/
   Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x 
 L2PFR=0x09b0 ACTLR=0x0040
   After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x0198 
 L2PFR=0x09b0 ACTLR=0x0040
 
 OMAP5uEVM: http://pastebin.ubuntu.com/10518958/
   Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x 
 L2PFR=0x09b0 ACTLR=0x0040
   After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x0198 
 L2PFR=0x09b0 ACTLR=0x0040
 
 Beagle-XM: http://pastebin.ubuntu.com/10519417/ (this is a r2p3 device)
   Before: CPUID=0x413fc082 ACR=0x00e2 L2AUXCR=0x0042
   After: CPUID=0x413fc082 ACR=0x0042 L2AUXCR=0x0042

I also got the same results on a Beagle-XM Rev. C1
 
 I dont have access to other omap3 platforms to give a better coverage

Beagle Rev. C2 (OMAP3530): http://pastebin.com/f5JcvRf4 
Before: CPUID=0x411fc083 ACR=0x00e2 L2AUXCR=0x0042
After: CPUID=0x411fc083 ACR=0x0042 L2AUXCR=0x0042

Tested-by: Matt Porter mpor...@konsulko.com
[With build workaround I noted elsewhere in the thread]

-Matt

 Sanity check:
 OMAP4Panda-ES: http://pastebin.ubuntu.com/10518971/
 
 Nishanth Menon (10):
   ARM: Introduce erratum workaround for 798870
   ARM: Introduce erratum workaround for 454179
   ARM: Introduce erratum workaround for 430973
   ARM: Introduce erratum workaround for 621766
   ARM: OMAP: Change set_pl310_ctrl_reg to be generic
   ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs
   ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with
 omap_smc1
   ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended
 configuration
   ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766
   ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973,
 621766
 
 Praveen Rao (1):
   ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
 
  README |8 +++
  arch/arm/cpu/armv7/Makefile|2 +-
  arch/arm/cpu/armv7/cp15.c  |   29 ++
  arch/arm/cpu/armv7/omap-common/Makefile|5 +-
  arch/arm/cpu/armv7/omap-common/lowlevel_init.S |   19 +++---
  arch/arm/cpu/armv7/omap3/board.c   |   60 +++
  arch/arm/cpu/armv7/omap3/lowlevel_init.S   |   11 
  arch/arm/cpu/armv7/omap4/hwinit.c  |4 +-
  arch/arm/cpu/armv7/omap5/hwinit.c  |   23 
  arch/arm/cpu/armv7/start.S |   61 
 
  .../arm/include/asm/arch-omap3/{omap3.h = omap.h} |0
  arch/arm/include/asm/arch-omap3/sys_proto.h|3 +-
  arch/arm/include/asm/arch-omap4/sys_proto.h|5 +-
  arch/arm/include/asm/arch-omap5/sys_proto.h|4 ++
  arch/arm/include/asm/armv7.h   |5 ++
  board/nokia/rx51/rx51.c|   19 +++---
  include/configs/am3517_crane.h |6 +-
  include/configs/am3517_evm.h   |6 +-
  include/configs/cm_t35.h   |6 +-
  include/configs/cm_t3517.h |6 +-
  include/configs/dig297.h   |6 +-
  include/configs/mcx.h  |6 +-
  include/configs/nokia_rx51.h   |6 +-
  include/configs/omap3_evm.h|2 +-
  include/configs/omap3_evm_common.h |4 ++
  include/configs/omap3_evm_quick_mmc.h  |2 +-
  include/configs/omap3_evm_quick_nand.h |2 +-
  include/configs/omap3_logic.h  |6 +-
  include/configs/omap3_mvblx.h  |6 +-
  include/configs/omap3_pandora.h|6 +-
  include/configs/omap3_sdp3430.h|6 +-
  include/configs/omap3_zoom1.h  |2 +-
  include/configs/tam3517-common.h   |6 +-
  include/configs/tao3530.h

Re: [U-Boot] [PATCH V4 05/11] ARM: OMAP: Change set_pl310_ctrl_reg to be generic

[Matt Porter]

On Tue, Mar 03, 2015 at 04:26:22PM -0600, Nishanth Menon wrote:
 set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
 PL310 control register, however, that is something that is generic
 enough to be used for OMAP5 generation of processors as well. The only
 difference being the service being invoked for the function.
 
 So, convert the service to a macro and use a generic name (same as
 that used in Linux for some consistency). While at that, also add a
 data barrier which is necessary as per recommendation.
 
 While at this, switch over to smc #0 instead of handcoded assembly.
 To ensure gcc compatibility, steal the strategy used by Linux kernel
 for sec extension builds (NOTE: we no longer use '-march=armv5' as the
 legacy comment claims).

Hi Nishanth,

I applied this series with fuzz and fixed a minor conflict on master. I
ran into a build issue for omap3 beagle with the sec extension scheme on
the gcc version 4.7.4 (Ubuntu/Linaro 4.7.4-2ubuntu1) toolchain:

 arm-linux-gnueabi-gcc
-Wp,-MD,arch/arm/cpu/armv7/omap3/.lowlevel_init.o.d  -nostdinc -isystem
/usr/lib/gcc-cross/arm-linux-gnueabi/4.7/include -Iinclude  -I../include
-I../arch/arm/include -include ../include/linux/kconfig.h -D__KERNEL__
-D__UBOOT__ -DCONFIG_SYS_TEXT_BASE=0x8010 -D__ASSEMBLY__ -g
-D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux
-mword-relocations -march=armv7-a -mno-unaligned-access
-ffunction-sections -fdata-sections -fno-common -ffixed-r9 -msoft-float
-pipe   -c -o arch/arm/cpu/armv7/omap3/lowlevel_init.o
../arch/arm/cpu/armv7/omap3/lowlevel_init.S

../arch/arm/cpu/armv7/omap-common/lowlevel_init.S: Assembler messages:
../arch/arm/cpu/armv7/omap-common/lowlevel_init.S:34: Error: selected
processor does not support ARM mode `smc #0'

I've worked around this for the moment by placing an explicit
.arch_extension sec in lowlevel_init.S but hopefully you have some
thoughts on why those flags don't seem to be picked up. I'll continue
to take a look at it in the meantime.

-Matt

 Signed-off-by: Nishanth Menon n...@ti.com
 ---
  arch/arm/cpu/armv7/omap-common/Makefile|3 +++
  arch/arm/cpu/armv7/omap-common/lowlevel_init.S |   17 ++---
  arch/arm/cpu/armv7/omap4/hwinit.c  |4 ++--
  arch/arm/include/asm/arch-omap4/sys_proto.h|5 -
  4 files changed, 19 insertions(+), 10 deletions(-)
 
 diff --git a/arch/arm/cpu/armv7/omap-common/Makefile 
 b/arch/arm/cpu/armv7/omap-common/Makefile
 index 7695e16d36f5..b36e85d25f3f 100644
 --- a/arch/arm/cpu/armv7/omap-common/Makefile
 +++ b/arch/arm/cpu/armv7/omap-common/Makefile
 @@ -26,6 +26,9 @@ ifeq ($(CONFIG_SYS_DCACHE_OFF),)
  obj-y+= omap-cache.o
  endif
  
 +plus_sec := $(call as-instr,.arch_extension sec,+sec)
 +AFLAGS_lowlevel_init.o   :=-Wa,-march=armv7-a$(plus_sec)
 +
  ifeq ($(CONFIG_OMAP34XX),)
  obj-y+= boot-common.o
  obj-y+= lowlevel_init.o
 diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S 
 b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
 index 86c0e4217478..83426291b22d 100644
 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
 +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
 @@ -22,11 +22,14 @@ ENTRY(save_boot_params)
   bx  lr
  ENDPROC(save_boot_params)
  
 -ENTRY(set_pl310_ctrl_reg)
 - PUSH{r4-r11, lr}@ save registers - ROM code may pollute
 +ENTRY(omap_smc1)
 + PUSH{r4-r12, lr}@ save registers - ROM code may pollute
   @ our registers
 - LDR r12, =0x102 @ Set PL310 control register - value in R0
 - .word   0xe1600070  @ SMC #0 - hand assembled because -march=armv5
 - @ call ROM Code API to set control register
 - POP {r4-r11, pc}
 -ENDPROC(set_pl310_ctrl_reg)
 + MOV r12, r0 @ Service
 + MOV r0, r1  @ Argument
 + DSB
 + DMB
 + SMC #0  @ Call the secure monitor for the service
 +
 + POP {r4-r12, pc}
 +ENDPROC(omap_smc1)
 diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c 
 b/arch/arm/cpu/armv7/omap4/hwinit.c
 index db16548fac49..9792761d40a0 100644
 --- a/arch/arm/cpu/armv7/omap4/hwinit.c
 +++ b/arch/arm/cpu/armv7/omap4/hwinit.c
 @@ -159,11 +159,11 @@ void init_omap_revision(void)
  #ifndef CONFIG_SYS_L2CACHE_OFF
  void v7_outer_cache_enable(void)
  {
 - set_pl310_ctrl_reg(1);
 + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1);
  }
  
  void v7_outer_cache_disable(void)
  {
 - set_pl310_ctrl_reg(0);
 + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0);
  }
  #endif /* !CONFIG_SYS_L2CACHE_OFF */
 diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h 
 b/arch/arm/include/asm/arch-omap4/sys_proto.h
 index e19975efaf50..f425e3af54f5 100644
 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h
 +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
 @@ -37,7 +37,7 @@ void do_set_mux(u32 base, struct pad_conf_entry const 
 *array, int size);
  void 

Re: [U-Boot] [PATCH][RFC v2] add pci 64 bit prefechable mem support

[Matt Porter]

On Fri, Feb 14, 2014 at 10:36:20AM +0800, FengHua wrote:
 
 
 
  -Original Messages-
  From: Wolfgang Denk w...@denx.de
  Sent Time: 2014-02-14 00:30:24 (Friday)
  To: feng...@phytium.com.cn
  Cc: u-boot@lists.denx.de, tr...@ti.com, albert.u.b...@aribaud.net
  Subject: Re: [PATCH][RFC v2] add pci 64 bit prefechable mem support
  
  Dear feng...@phytium.com.cn,
  
  In message 1392282108-56485-1-git-send-email-feng...@phytium.com.cn you 
  wrote:
   From: David Feng feng...@phytium.com.cn
   
   u-boot did not program the upper 32 bits of prefetchable base and limit
   in pci bridge config space. I think it's needed when 64 bit address space
   is used.
  
  You write I think it's needed - is it or not?
  
  Do you have a specific test case that fails without your patch, and
  works with it?
  
  Best regards,
  
  Wolfgang Denk. 
 There's no test case now (maybe a few days later I could make a test).
 PCI-to-PCI Bridge Architecture Specification require that the upper 32 bit 
 of prefetchable space
 must be initialized by configuration software. But usually the default value 
 is zero already.
 A board using 64 bit pci prefetchable memory space and a pci device with 64 
 bit prefetchable space
 are needed. I think u-boot did not encounter this situation before.

There's two things happening here.

1) You are adding support to explicitly program the upper32 prefetch
limit/base to zero (in the 64-bit prefetch memory 4GB case) which is
a completely theoretical fix. I can more or less confirm that this
doesn't cause a problem in practice for prefetch memory 4GB. When I
wrote the original code in-kernel, I had noticed this on the 21154
bridges and others when I was trying out WIP prefetch support (which
I never finished to upstream because we let the kernel subsystem fix
up prefetch later). If we look at the history of the prefetch support
added to the U-Boot version of pci_auto.c it's also proven on real h/w
that this is only a theoretical fix. To be fair, it is best to be safe,
but as Wolfgang points out it appears you are fixing something that's
not practically broken

2) 64-bit prefetch support for prefetch memory 4GB. It's up to the
maintainers, but given that this is untested code, I don't see a good
reason to merge it. I have reviewed it and the implementation looks
correct to me per spec. However, I believe that you should resubmit this
patch along with support for a platform that actually makes use of it as
you describe above. At that time, it would be appropriate to fix the
possible latent bug (for a not-yet-known p2p bridge that doesn't default
upper32 limit/base to 0) in the 4GB case just as part of handling the
4GB case.

-Matt
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Re: [U-Boot] [PATCH 2/6] arch: bcm281xx: Initial commit of bcm281xx architecture code

[Matt Porter]

On Wed, Jan 29, 2014 at 05:32:30PM -0500, Tom Rini wrote:
 On Mon, Jan 27, 2014 at 10:53:26AM -0800, Darwin Rambo wrote:
 
  Add bcm281xx architecture support code including a clock framework and
  chip reset.  Define register block base addresses for the bcm281xx
  architecture and create an empty gpio header file required when
  CONFIG_CMD_GPIO is set.
 [snip]
  +/* Bitfield operations */
  +
  +/* Produces a mask of set bits covering a range of a 32-bit value */
  +static inline u32 bitfield_mask(u32 shift, u32 width)
  +{
  +   return ((1  width) - 1)  shift;
  +}
  +
  +/* Extract the value of a bitfield found within a given register value */
  +static inline u32 bitfield_extract(u32 reg_val, u32 shift, u32 width)
  +{
  +   return (reg_val  bitfield_mask(shift, width))  shift;
  +}
  +
  +/* Replace the value of a bitfield found within a given register value */
  +static inline u32 bitfield_replace(u32 reg_val, u32 shift, u32 width, u32 
  val)
  +{
  +   u32 mask = bitfield_mask(shift, width);
  +
  +   return (reg_val  ~mask) | (val  shift);
  +}
 
 This all feels horribly generic, isn't there some linux header we've
 already got that I can't think off of the top of my head that gives us
 these kind of functions?

To add to what Darwin mentioned about bitops.h being insufficient...

The equivalent kernel implementations are wrapped up in the
regmap/regmap-mmio helpers. That implementation is *very* heavyweight,
and IMHO simply not appropriate for U-Boot (and often not useful in the
kernel as well).  A homegrown generic set of inline ops would seem to be
ideal for U-Boot.

-Matt
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Re: [U-Boot] Illegal use of FP ops in clock_ti814x.c

[Matt Porter]

On Tue, Oct 29, 2013 at 08:23:07AM -0400, Tom Rini wrote:
 -BEGIN PGP SIGNED MESSAGE-
 Hash: SHA1
 
 On 10/29/2013 06:48 AM, Wolfgang Denk wrote:
  Dear Måns Rullgård,
  
  In message yw1x8uxc28y9@unicorn.mansr.com you wrote:
  
  Something like this should be equivalent.  That said, it
  looks suspiciously like it's meant to simply do a division
  and round up.  If that is the case, +225 should be +249.  It
  probably makes no difference for the values actually
  encountered.
  
  Umm... this is the part which I do not understand.
  
  The original code adds 90%; you add 90%, too.  However, to
  round up, one usually adds only 50% ?
  
  Adding 50% would round to nearest.  For integer division to round
  up, you must add one less than the divisor.
  
  Agreed.  But do we want to round up?  The original code used +90%, 
  which is something else, too...
 
 And I imagine it's unlikely the original author of the code is around
 anymore, or recalls exactly why.  I'm pretty sure Matt just lifted the
 code from the vendor tree and since it wasn't throwing warnings didn't
 notice the floating point part.
 
  Where are these 90% coming from? Are they in any way
  meaningful, or even critical?
  
  My guess is that it was someone's approximation of 249 / 250.  I
  don't know the hardware, so it's conceivable that it really
  should be this way, although it seems unlikely.
  
  Are you able to test such a modificationon actual hardware?
 
 I suspect Matt can, after Linaro Connect.  I don't have one of these
 platforms handy but I think he still does.

Thankfully Tom reminded me of this because I lost some of the list
traffic due to some local mail issues.

Although not explicitly mentioned in the TRM or any application
notes I can find, the 90% appears to come from jitter compensation for
the delta sigma fractional divider. I see some comments that imply this
in various old vendor kernel tree clock implementations where they are
rounding various pll constants. I can't be 100% sure without some
insight from TI folks. Given that it's working for our known users, I'd
like to preserve that until we get somebody that can shed some light on
that.

As Tom guessed, I low-level cherry-picked a lot of pieces from long-lost
authors in this area. I obviously missed this floating point math in the
cleanup.

I tested this patch on my TI8148 EVM and it works as expected.

Acked-by: Matt Porter mpor...@linaro.org

-Matt
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Re: [U-Boot] [PATCH] am33xx: Stop modifying certain EMIF4D registers

[Matt Porter]

On Thu, Nov 07, 2013 at 11:42:57AM -0500, Tom Rini wrote:
 Based on the definitive guide to EMIF configuration[1] certain registers
 that we have been modifying (and are documented registers) should be
 left in their reset values rather than modified.  This has been tested
 on AM335x GP EVM and Beaglebone White.
 
 [1]: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
 Cc: Enric Balletbo i Serra eballe...@iseebcn.com
 Cc: Javier Martinez Canillas jav...@dowhile0.org
 Cc: Heiko Schocher h...@denx.de
 Cc: Matt Porter matt.por...@linaro.org
 Cc: Lars Poeschel poesc...@lemonage.de
 Signed-off-by: Tom Rini tr...@ti.com
 ---
  arch/arm/cpu/armv7/am33xx/ddr.c |7 --
  arch/arm/include/asm/arch-am33xx/ddr_defs.h |   31 
 ++-
  board/isee/igep0033/board.c |4 
  board/phytec/pcm051/board.c |4 
  board/siemens/dxr2/board.c  |4 
  board/siemens/pxm2/board.c  |5 -
  board/siemens/rut/board.c   |5 -
  board/ti/am335x/board.c |   17 ---
  board/ti/ti814x/evm.c   |5 -
  board/ti/ti816x/evm.c   |   17 ---
  10 files changed, 6 insertions(+), 93 deletions(-)

Working on my PG1.0 TI814x EVM

Tested-by: Matt Porter matt.por...@linaro.org

-Matt
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Re: [U-Boot] [PATCH] am33xx: Stop modifying certain EMIF4D registers

[Matt Porter]

On Thu, Nov 07, 2013 at 04:16:40PM -0500, Tom Rini wrote:
 -BEGIN PGP SIGNED MESSAGE-
 Hash: SHA1
 
 On 11/07/2013 04:12 PM, Vaibhav Bedia wrote:
  Hi Tom,
  
  On Thu, Nov 7, 2013 at 11:42 AM, Tom Rini tr...@ti.com wrote:
  Based on the definitive guide to EMIF configuration[1] certain registers
  that we have been modifying (and are documented registers) should be
  left in their reset values rather than modified.  This has been tested
  on AM335x GP EVM and Beaglebone White.
 
  
  [...]
 [snip]
  @@ -198,11 +188,6 @@ void sdram_init(void)
  config_dmm(evm_lisa_map_regs);
 
   #ifdef CONFIG_TI816X_EVM_DDR2
  -   ddr2_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
  -   ddr2_ctrl.cmd0dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
  -   ddr2_ctrl.cmd1dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
  -   ddr2_ctrl.cmd2dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
  -
  if (CONFIG_TI816X_USE_EMIF0) {
  ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
  (get_cpu_rev() == 0x1 ? 0x010B : 0x030B);
  @@ -217,8 +202,6 @@ void sdram_init(void)
   #endif
 
   #ifdef CONFIG_TI816X_EVM_DDR3
  -   ddr3_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
  -
  
  From a quick glance it looks like at least earlier variants of TI81xx
  used these registers to work around some bugs? This might end up
  breaking those. Note that TI81xx DDR frequencies are much higher
  compared to AM335x so issues related to this might not show up
  right now.
 
 It's an open question on if TI81xx needs these set or was simply also
 setting them for historical reasons (and in turn was inherited by am335x).

I will doublecheck on my early TI8148...out of time today but tomorrow.

-Matt
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[U-Boot] [PATCH] boards.cfg: update email address for ti814x_evm maintainer

[Matt Porter]

Update my email address as ti814x_evm maintainer to save
people some frustrating bounces and non-response.

Signed-off-by: Matt Porter matt.por...@linaro.org
---
 boards.cfg | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/boards.cfg b/boards.cfg
index 5e10125..cd6bec4 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -264,7 +264,7 @@ Active  arm armv7  am33xx  ti   
   am335x
 Active  arm armv7  am33xx  ti  am335x  
am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=1,NAND   

   Tom Rini tr...@ti.com
 Active  arm armv7  am33xx  ti  am335x  
am335x_evm_usbspl
am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT 
  Tom Rini tr...@ti.com
 Active  arm armv7  am33xx  ti  am43xx  
am43xx_evm   am43xx_evm:SERIAL1,CONS_INDEX=1

   -
-Active  arm armv7  am33xx  ti  ti814x  
ti814x_evm   -  

   Matt Porter mpor...@ti.com
+Active  arm armv7  am33xx  ti  ti814x  
ti814x_evm   -  

   Matt Porter matt.por...@linaro.org
 Active  arm armv7  am33xx  ti  ti816x  
ti816x_evm   -  

   -
 Active  arm armv7  at91atmel   sama5d3xek  
sama5d3xek_mmc   sama5d3xek:SAMA5D3,SYS_USE_MMC 

   Bo Shen voice.s...@atmel.com
 Active  arm armv7  at91atmel   sama5d3xek  
sama5d3xek_nandflash sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH   

   Bo Shen voice.s...@atmel.com
-- 
1.8.4

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Re: [U-Boot] [PATCH 3/4] phy: add support for ET1011C phys

[Matt Porter]

On Fri, Mar 15, 2013 at 09:11:28PM +, Tom Rini wrote:
 On Fri, Mar 15, 2013 at 04:58:19PM -0400, Matt Porter wrote:
 
  Adds an ET1011C PHY driver which is derived from
  the current Linux kernel PHY driver. Note that an
  errata workaround config option is implemented to
  allow for TX_CLK to be enabled even when gigabit
  mode is negotiated. This workaround is used on the
  TI814x-EVM.
 
 You need to specify the git hash or tag, not just current.

Updated in v2

 The code itself is fine, so
 
 Reviewed-by: Tom Rini tr...@ti.com

-Matt
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Re: [U-Boot] [PATCH 1/4] am33xx: add pll and clock support for TI814x CPSW

[Matt Porter]

On Fri, Mar 15, 2013 at 09:13:54PM +, Tom Rini wrote:
 On Fri, Mar 15, 2013 at 04:58:17PM -0400, Matt Porter wrote:
 
 [snip]
  +   /* Ethernet */
  +   writel(PRCM_MOD_EN, cmalwon-l3slowclkstctrl);
  +   while ((readl(cmalwon-l3slowclkstctrl)  0x2100) != 0x2100)
  +   ;
  +   writel(PRCM_MOD_EN, cmalwon-ethclkstctrl);
  +   writel(PRCM_MOD_EN, cmalwon-ethernet0clkctrl);
  +   while ((readl(cmalwon-ethernet0clkctrl)  0x3) != 0)
  +   ;
  +   writel(PRCM_MOD_EN, cmalwon-ethernet1clkctrl);
  +   while ((readl(cmalwon-ethernet1clkctrl)  0x3) != 0)
 
 Please define away the magic numbers.
 
 [snip]
  +void sata_pll_config(void)
  +{
  +   /* TRM 21.3.1 */
  +   writel(0xc12c003c, spll-pllcfg1);
 
 I'm OK with comments, but please make it a multi-line thing that
 explains what's going on so that it's clear that yes, really, we
 shouldn't have defined these.

I'll address this with gratuitous defines in v2...and expand the
comment.

-Matt
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[U-Boot] [PATCH v2 0/4] Enable CPSW on TI814x EVM

[Matt Porter]

This series adds support for CPSW on the PG1.0 TI814x EVM board. 
The V1 CPSW on TI814x requires minor register changes to the
existing driver as well as TI814x-specific pll/clock support.
An ET1011C phy driver is added to support the PHY present on the
PG1.0 EVM.

It has been tested loading/booting a Linux kernel and regression
tested on BeagleBone and EVM-SK AM33XX boards. It has also been
MAKEALL tested for all am33xx platforms.

The series applies on top of the following patches:
- am33xx: Add required includes to some omap/am33xx code
  http://patchwork.ozlabs.org/patch/227804/
- Add TI814x EVM Support v4
  http://www.mail-archive.com/u-boot@lists.denx.de/msg108356.html

Changes since v1:
- Improved sata pll config comment and defined magic clock values
- Added the kernel tag that the et1011c.c driver is derived from

Matt Porter (4):
  am33xx: add pll and clock support for TI814x CPSW
  cpsw: add support for TI814x slave_regs differences
  phy: add support for ET1011C phys
  ti814x_evm: enable CPSW support

 arch/arm/cpu/armv7/am33xx/clock_ti814x.c   |  103 +-
 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |1 +
 board/ti/ti814x/evm.c  |   75 +
 board/ti/ti814x/evm.h  |1 +
 board/ti/ti814x/mux.c  |   35 +++
 drivers/net/cpsw.c |6 ++
 drivers/net/phy/Makefile   |1 +
 drivers/net/phy/et1011c.c  |  110 
 drivers/net/phy/phy.c  |3 +
 include/configs/ti814x_evm.h   |   21 
 include/phy.h  |1 +
 11 files changed, 355 insertions(+), 2 deletions(-)
 create mode 100644 drivers/net/phy/et1011c.c

-- 
1.7.9.5

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[U-Boot] [PATCH v2 1/4] am33xx: add pll and clock support for TI814x CPSW

[Matt Porter]

Enables required PLLs and clocks for CPSW on TI814x.

Signed-off-by: Matt Porter mpor...@ti.com
---
v2: improved sata pll comment and added defines for magic values
---
 arch/arm/cpu/armv7/am33xx/clock_ti814x.c   |  103 +++-
 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |1 +
 board/ti/ti814x/evm.c  |3 +
 3 files changed, 105 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c 
b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
index cb4210f..8b2878d 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -109,6 +109,8 @@ struct ad_pll {
 #define OSC_SRC_CTRL   (PLL_SUBSYS_BASE + 0x2C0)
 
 /* PRCM */
+#define ENET_CLKCTRL_CMPL  0x3
+
 #define CM_DEFAULT_BASE(PRCM_BASE + 0x0500)
 
 struct cm_def {
@@ -183,7 +185,7 @@ struct cm_alwon {
unsigned int resv5[2];
unsigned int gpmcclkctrl;
unsigned int ethernet0clkctrl;
-   unsigned int resv6[1];
+   unsigned int ethernet1clkctrl;
unsigned int mpuclkctrl;
unsigned int debugssclkctrl;
unsigned int l3clkctrl;
@@ -203,9 +205,67 @@ struct cm_alwon {
unsigned int custefuseclkctrl;
 };
 
+#define SATA_PLL_BASE  (CTRL_BASE + 0x0720)
+
+struct sata_pll {
+   unsigned int pllcfg0;
+   unsigned int pllcfg1;
+   unsigned int pllcfg2;
+   unsigned int pllcfg3;
+   unsigned int pllcfg4;
+   unsigned int pllstatus;
+   unsigned int rxstatus;
+   unsigned int txstatus;
+   unsigned int testcfg;
+};
+
+#define SEL_IN_FREQ(0x1  31)
+#define DIGCLRZ(0x1  30)
+#define ENDIGLDO   (0x1  4)
+#define APLL_CP_CURR   (0x1  3)
+#define ENBGSC_REF (0x1  2)
+#define ENPLLLDO   (0x1  1)
+#define ENPLL  (0x1  0)
+
+#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
+#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
+#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
+#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
+   ENPLLLDO | ENPLL)
+
+#define PLL_LOCK   (0x1  0)
+
+#define ENSATAMODE (0x1  31)
+#define PLLREFSEL  (0x1  30)
+#define MDIVINT(0x4b  18)
+#define EN_CLKAUX  (0x1  5)
+#define EN_CLK125M (0x1  4)
+#define EN_CLK100M (0x1  3)
+#define EN_CLK50M  (0x1  2)
+
+#define SATA_PLLCFG1 (ENSATAMODE | \
+ PLLREFSEL |   \
+ MDIVINT | \
+ EN_CLKAUX |   \
+ EN_CLK125M |  \
+ EN_CLK100M |  \
+ EN_CLK50M)
+
+#define DIGLDO_EN_CAPLESSMODE  (0x1  22)
+#define PLLDO_EN_LDO_STABLE(0x1  11)
+#define PLLDO_EN_BUF_CUR   (0x1  7)
+#define PLLDO_EN_LP(0x1  6)
+#define PLLDO_CTRL_TRIM_1_4V   (0x10  1)
+
+#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE |  \
+ PLLDO_EN_LDO_STABLE | \
+ PLLDO_EN_BUF_CUR |\
+ PLLDO_EN_LP | \
+ PLLDO_CTRL_TRIM_1_4V)
 
 const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
 const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
+const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
 
 /*
  * Enable the peripheral clock for required peripherals
@@ -221,6 +281,15 @@ static void enable_per_clocks(void)
writel(PRCM_MOD_EN, cmalwon-mmchs1clkctrl);
while (readl(cmalwon-mmchs1clkctrl) != PRCM_MOD_EN)
;
+
+   /* Ethernet */
+   writel(PRCM_MOD_EN, cmalwon-ethclkstctrl);
+   writel(PRCM_MOD_EN, cmalwon-ethernet0clkctrl);
+   while ((readl(cmalwon-ethernet0clkctrl)  ENET_CLKCTRL_CMPL) != 0)
+   ;
+   writel(PRCM_MOD_EN, cmalwon-ethernet1clkctrl);
+   while ((readl(cmalwon-ethernet1clkctrl)  ENET_CLKCTRL_CMPL) != 0)
+   ;
 }
 
 /*
@@ -365,6 +434,35 @@ void ddr_pll_config(unsigned int ddrpll_m)
pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
 }
 
+void sata_pll_config(void)
+{
+   /*
+* This sequence for configuring the SATA PLL
+* resident in the control module is documented
+* in TI8148 TRM section 21.3.1
+*/
+   writel(SATA_PLLCFG1, spll-pllcfg1);
+   udelay(50);
+
+   writel(SATA_PLLCFG3, spll-pllcfg3);
+   udelay(50);
+
+   writel(SATA_PLLCFG0_1, spll-pllcfg0);
+   udelay(50);
+
+   writel(SATA_PLLCFG0_2, spll-pllcfg0);
+   udelay(50);
+
+   writel(SATA_PLLCFG0_3, spll-pllcfg0);
+   udelay(50);
+
+   writel(SATA_PLLCFG0_4, spll-pllcfg0);
+   udelay(50);
+
+   while (((readl(spll-pllstatus)  PLL_LOCK) == 0

[U-Boot] [PATCH v2 2/4] cpsw: add support for TI814x slave_regs differences

[Matt Porter]

TI814x's version 1 CPSW has a different slave_regs layout.
Add support for the differing registers.

Signed-off-by: Matt Porter mpor...@ti.com
Reviewed-by: Tom Rini tr...@ti.com
---
v2: no changes
---
 drivers/net/cpsw.c |6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index f5c5b9a..34c9fdd 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -109,7 +109,13 @@ struct cpsw_slave_regs {
u32 flow_thresh;
u32 port_vlan;
u32 tx_pri_map;
+#ifdef CONFIG_AM33XX
u32 gap_thresh;
+#elif defined(CONFIG_TI814X)
+   u32 ts_ctl;
+   u32 ts_seq_ltype;
+   u32 ts_vlan;
+#endif
u32 sa_lo;
u32 sa_hi;
 };
-- 
1.7.9.5

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[U-Boot] [PATCH v2 3/4] phy: add support for ET1011C phys

[Matt Porter]

Adds an ET1011C PHY driver which is derived from the
Linux kernel PHY driver (drivers/net/phy/et1011c.c)
from the v3.9-rc2 tag. Note that an errata workaround
config option is implemented to allow for TX_CLK to be
enabled even when gigabit mode is negotiated. This
workaround is used on the PG1.0 TI814X EVM.

Signed-off-by: Matt Porter mpor...@ti.com
Reviewed-by: Tom Rini tr...@ti.com
--
v2: updated description with the kernel driver's tag
---
 drivers/net/phy/Makefile  |1 +
 drivers/net/phy/et1011c.c |  110 +
 drivers/net/phy/phy.c |3 ++
 include/phy.h |1 +
 4 files changed, 115 insertions(+)
 create mode 100644 drivers/net/phy/et1011c.c

diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 5e90d70..af5f4b8 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -34,6 +34,7 @@ COBJS-$(CONFIG_PHYLIB_10G) += generic_10g.o
 COBJS-$(CONFIG_PHY_ATHEROS) += atheros.o
 COBJS-$(CONFIG_PHY_BROADCOM) += broadcom.o
 COBJS-$(CONFIG_PHY_DAVICOM) += davicom.o
+COBJS-$(CONFIG_PHY_ET1011C) += et1011c.o
 COBJS-$(CONFIG_PHY_LXT) += lxt.o
 COBJS-$(CONFIG_PHY_MARVELL) += marvell.o
 COBJS-$(CONFIG_PHY_MICREL) += micrel.o
diff --git a/drivers/net/phy/et1011c.c b/drivers/net/phy/et1011c.c
new file mode 100644
index 000..5e22399
--- /dev/null
+++ b/drivers/net/phy/et1011c.c
@@ -0,0 +1,110 @@
+/*
+ * ET1011C PHY driver
+ *
+ * Derived from Linux kernel driver by Chaithrika U S
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include config.h
+#include phy.h
+
+#define ET1011C_CONFIG_REG (0x16)
+#define ET1011C_TX_FIFO_MASK   (0x3  12)
+#define ET1011C_TX_FIFO_DEPTH_8(0x0  12)
+#define ET1011C_TX_FIFO_DEPTH_16   (0x1  12)
+#define ET1011C_INTERFACE_MASK (0x7  0)
+#define ET1011C_GMII_INTERFACE (0x2  0)
+#define ET1011C_SYS_CLK_EN (0x1  4)
+#define ET1011C_TX_CLK_EN  (0x1  5)
+
+#define ET1011C_STATUS_REG (0x1A)
+#define ET1011C_DUPLEX_STATUS  (0x1  7)
+#define ET1011C_SPEED_MASK (0x3  8)
+#define ET1011C_SPEED_1000 (0x2  8)
+#define ET1011C_SPEED_100  (0x1  8)
+#define ET1011C_SPEED_10   (0x0  8)
+
+static int et1011c_config(struct phy_device *phydev)
+{
+   int ctl = 0;
+   ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
+   if (ctl  0)
+   return ctl;
+   ctl = ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 |
+BMCR_ANENABLE);
+   /* First clear the PHY */
+   phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET);
+
+   return genphy_config_aneg(phydev);
+}
+
+static int et1011c_parse_status(struct phy_device *phydev)
+{
+   int mii_reg;
+   int speed;
+
+   mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_STATUS_REG);
+
+   if (mii_reg  ET1011C_DUPLEX_STATUS)
+   phydev-duplex = DUPLEX_FULL;
+   else
+   phydev-duplex = DUPLEX_HALF;
+
+   speed = mii_reg  ET1011C_SPEED_MASK;
+   switch (speed) {
+   case ET1011C_SPEED_1000:
+   phydev-speed = SPEED_1000;
+   mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG);
+   mii_reg = ~ET1011C_TX_FIFO_MASK;
+   phy_write(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG,
+ mii_reg |
+ ET1011C_GMII_INTERFACE |
+ ET1011C_SYS_CLK_EN |
+#ifdef CONFIG_PHY_ET1011C_TX_CLK_FIX
+ ET1011C_TX_CLK_EN |
+#endif
+ ET1011C_TX_FIFO_DEPTH_16);
+   break;
+   case ET1011C_SPEED_100:
+   phydev-speed = SPEED_100;
+   break;
+   case ET1011C_SPEED_10:
+   phydev-speed = SPEED_10;
+   break;
+   }
+
+   return 0;
+}
+
+static int et1011c_startup(struct phy_device *phydev)
+{
+   genphy_update_link(phydev);
+   et1011c_parse_status(phydev);
+   return 0;
+}
+
+static struct phy_driver et1011c_driver = {
+   .name   = ET1011C,
+   .uid= 0x0282f014,
+   .mask   = 0xfff0,
+   .features   = PHY_GBIT_FEATURES,
+   .config = et1011c_config,
+   .startup= et1011c_startup,
+};
+
+int phy_et1011c_init(void)
+{
+   phy_register(et1011c_driver);
+
+   return 0

[U-Boot] [PATCH v2 4/4] ti814x_evm: enable CPSW support

[Matt Porter]

Adds CPSW support to the TI814X EVM configured with
an ET1011C PHY in GMII mode.

Signed-off-by: Matt Porter mpor...@ti.com
Reviewed-by: Tom Rini tr...@ti.com
---
v2: no changes
---
 board/ti/ti814x/evm.c|   72 ++
 board/ti/ti814x/evm.h|1 +
 board/ti/ti814x/mux.c|   35 
 include/configs/ti814x_evm.h |   21 
 4 files changed, 129 insertions(+)

diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index 8513220..d6c19f5 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -17,6 +17,7 @@
  */
 
 #include common.h
+#include cpsw.h
 #include errno.h
 #include spl.h
 #include asm/arch/cpu.h
@@ -39,6 +40,8 @@ static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 #endif
 
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
 /* UART Defines */
 #ifdef CONFIG_SPL_BUILD
 #define UART_RESET (0x1  1)
@@ -166,6 +169,9 @@ void s_init(void)
/* Set MMC pins */
enable_mmc1_pin_mux();
 
+   /* Set Ethernet pins */
+   enable_enet_pin_mux();
+
/* Enable UART */
uart_enable();
 
@@ -199,3 +205,69 @@ int board_mmc_init(bd_t *bis)
return 0;
 }
 #endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+   /* VTP can be added here */
+
+   return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+   {
+   .slave_reg_ofs  = 0x50,
+   .sliver_reg_ofs = 0x700,
+   .phy_id = 1,
+   },
+   {
+   .slave_reg_ofs  = 0x90,
+   .sliver_reg_ofs = 0x740,
+   .phy_id = 0,
+   },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+   .mdio_base  = CPSW_MDIO_BASE,
+   .cpsw_base  = CPSW_BASE,
+   .mdio_div   = 0xff,
+   .channels   = 8,
+   .cpdma_reg_ofs  = 0x100,
+   .slaves = 1,
+   .slave_data = cpsw_slaves,
+   .ale_reg_ofs= 0x600,
+   .ale_entries= 1024,
+   .host_port_reg_ofs  = 0x28,
+   .hw_stats_reg_ofs   = 0x400,
+   .mac_control= (1  5),
+   .control= cpsw_control,
+   .host_port_num  = 0,
+   .version= CPSW_CTRL_VERSION_1,
+};
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+   uint8_t mac_addr[6];
+   uint32_t mac_hi, mac_lo;
+
+   if (!eth_getenv_enetaddr(ethaddr, mac_addr)) {
+   printf(ethaddr not set. Reading from E-fuse\n);
+   /* try reading mac address from efuse */
+   mac_lo = readl(cdev-macid0l);
+   mac_hi = readl(cdev-macid0h);
+   mac_addr[0] = mac_hi  0xFF;
+   mac_addr[1] = (mac_hi  0xFF00)  8;
+   mac_addr[2] = (mac_hi  0xFF)  16;
+   mac_addr[3] = (mac_hi  0xFF00)  24;
+   mac_addr[4] = mac_lo  0xFF;
+   mac_addr[5] = (mac_lo  0xFF00)  8;
+
+   if (is_valid_ether_addr(mac_addr))
+   eth_setenv_enetaddr(ethaddr, mac_addr);
+   else
+   printf(Unable to read MAC address. Set ethaddr\n);
+   }
+
+   return cpsw_register(cpsw_data);
+}
diff --git a/board/ti/ti814x/evm.h b/board/ti/ti814x/evm.h
index 40f8710..6aebec6 100644
--- a/board/ti/ti814x/evm.h
+++ b/board/ti/ti814x/evm.h
@@ -3,5 +3,6 @@
 
 void enable_uart0_pin_mux(void);
 void enable_mmc1_pin_mux(void);
+void enable_enet_pin_mux(void);
 
 #endif /* _EVM_H */
diff --git a/board/ti/ti814x/mux.c b/board/ti/ti814x/mux.c
index 137acb4..fd9f364 100644
--- a/board/ti/ti814x/mux.c
+++ b/board/ti/ti814x/mux.c
@@ -40,6 +40,36 @@ static struct module_pin_mux mmc1_pin_mux[] = {
{-1},
 };
 
+static struct module_pin_mux enet_pin_mux[] = {
+   {OFFSET(pincntl232), MODE(0x01)},   /* EMAC_RMREFCLK */
+   {OFFSET(pincntl233), PULLUP_EN | MODE(0x01)},   /* MDCLK */
+   {OFFSET(pincntl234), PULLUP_EN | MODE(0x01)},   /* MDIO */
+   {OFFSET(pincntl235), MODE(0x01)},   /* EMAC[0]_MTCLK */
+   {OFFSET(pincntl236), MODE(0x01)},   /* EMAC[0]_MCOL */
+   {OFFSET(pincntl237), MODE(0x01)},   /* EMAC[0]_MCRS */
+   {OFFSET(pincntl238), MODE(0x01)},   /* EMAC[0]_MRXER */
+   {OFFSET(pincntl239), MODE(0x01)},   /* EMAC[0]_MRCLK */
+   {OFFSET(pincntl240), MODE(0x01)},   /* EMAC[0]_MRXD[0] */
+   {OFFSET(pincntl241), MODE(0x01)},   /* EMAC[0]_MRXD[1] */
+   {OFFSET(pincntl242), MODE(0x01)},   /* EMAC[0]_MRXD[2] */
+   {OFFSET(pincntl243), MODE(0x01)},   /* EMAC[0]_MRXD[3] */
+   {OFFSET(pincntl244), MODE(0x01)},   /* EMAC[0]_MRXD[4] */
+   {OFFSET

[U-Boot] [PATCH v4 0/9] Add TI814x EVM Support

[Matt Porter]

This series adds support for the PG1.0 TI814x EVM board. TI814x
fits into the existing AM33XX SoC support with some refactoring
of the AM33XX-specific emif4, clock, and mux code.

It has been tested booting up a Linux kernel and regression tested
on BeagleBone and EVM-SK AM33XX boards. It has also been MAKEALL
tested for all am33xx platforms.

The series applies on top of the add required includes patch from
Tom Rini at http://patchwork.ozlabs.org/patch/227804/

Changes since v3:
- Fix pcm051 build breakage
- Fix unused variable warning in emif4 support
- Remove unused includes (fixed by required includes patch)
- Remove unused CONFIG_FS_* options (fixed by above patch)

Changes since v2:
- Fix EMIF/L3F clock enable ordering issue

Changes since v1:
- Fix warnings in ddr.c
- Split hardware.h - hardware_am33xx.h/ti814x.h
- Remove unused dmtimer support
- Add register structs bit definitions
- Rename soc-specific clock files for consistency
- Move soc-specific defs only used in one place to clock_*.c
- fix copyright dates and filenames in headers
- remove clocks_*.h and go back to clock.h
- Rename mux includes for consistency
- Correct mmc reference clock for ti814x
- Squash MAINTAINERS and build bits to board support commit
- Config fixes (copyright, mtest, findfdt, fs options, cleanups)
- Fix wdtimer warning

Matt Porter (9):
  am33xx: convert defines from am33xx-specific to generic names
  am33xx: refactor emif4/ddr to support multiple EMIF instances
  am33xx: refactor am33xx clocks and add ti814x support
  am33xx: refactor am33xx mux support and add ti814x support
  am33xx: add ti814x specific register definitions
  am33xx: add dmm support to emif4 library
  am33xx: support ti814x mmc reference clock
  ns16550: enable quirks for ti814x
  ti814x_evm: add ti814x evm board support

 MAINTAINERS|4 +
 Makefile   |2 +-
 arch/arm/cpu/armv7/Makefile|2 +-
 arch/arm/cpu/armv7/am33xx/Makefile |3 +-
 arch/arm/cpu/armv7/am33xx/board.c  |4 +-
 .../cpu/armv7/am33xx/{clock.c = clock_am33xx.c}   |   34 +-
 arch/arm/cpu/armv7/am33xx/clock_ti814x.c   |  406 
 arch/arm/cpu/armv7/am33xx/ddr.c|   99 +++--
 arch/arm/cpu/armv7/am33xx/emif4.c  |   57 ++-
 arch/arm/cpu/armv7/am33xx/sys_info.c   |3 +
 arch/arm/cpu/armv7/omap-common/Makefile|2 +-
 arch/arm/include/asm/arch-am33xx/clock.h   |2 +-
 arch/arm/include/asm/arch-am33xx/clocks_am33xx.h   |   33 +-
 arch/arm/include/asm/arch-am33xx/cpu.h |   11 +-
 arch/arm/include/asm/arch-am33xx/ddr_defs.h|   57 ++-
 arch/arm/include/asm/arch-am33xx/hardware.h|   40 +-
 arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |   54 +++
 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |   53 +++
 arch/arm/include/asm/arch-am33xx/mmc_host_def.h|4 +
 arch/arm/include/asm/arch-am33xx/mux.h |  235 +--
 arch/arm/include/asm/arch-am33xx/mux_am33xx.h  |  247 
 arch/arm/include/asm/arch-am33xx/mux_ti814x.h  |  311 +++
 arch/arm/include/asm/arch-am33xx/omap.h|5 +
 arch/arm/include/asm/arch-am33xx/spl.h |5 +
 board/phytec/pcm051/board.c|8 +-
 board/ti/am335x/board.c|   12 +-
 board/ti/ti814x/Makefile   |   46 +++
 board/ti/ti814x/evm.c  |  198 ++
 board/ti/ti814x/evm.h  |7 +
 board/ti/ti814x/mux.c  |   51 +++
 boards.cfg |1 +
 drivers/serial/ns16550.c   |5 +-
 include/configs/ti814x_evm.h   |  220 +++
 spl/Makefile   |2 +-
 34 files changed, 1851 insertions(+), 372 deletions(-)
 rename arch/arm/cpu/armv7/am33xx/{clock.c = clock_am33xx.c} (91%)
 create mode 100644 arch/arm/cpu/armv7/am33xx/clock_ti814x.c
 create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/mux_am33xx.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/mux_ti814x.h
 create mode 100644 board/ti/ti814x/Makefile
 create mode 100644 board/ti/ti814x/evm.c
 create mode 100644 board/ti/ti814x/evm.h
 create mode 100644 board/ti/ti814x/mux.c
 create mode 100644 include/configs/ti814x_evm.h

-- 
1.7.9.5

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[U-Boot] [PATCH v4 1/9] am33xx: convert defines from am33xx-specific to generic names

[Matt Porter]

Eliminate AM33xx specific names to prepare for TI814x support
within AM33xx-land.

Signed-off-by: Matt Porter mpor...@ti.com
Reviewed-by: Tom Rini tr...@ti.com

---
v4: fix pcm051 build breakage
v3: no changes
v2: no changes
---
 arch/arm/cpu/armv7/am33xx/board.c   |4 ++--
 arch/arm/include/asm/arch-am33xx/hardware.h |   10 +-
 board/phytec/pcm051/board.c |6 +++---
 board/ti/am335x/board.c |6 +++---
 4 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/board.c 
b/arch/arm/cpu/armv7/am33xx/board.c
index ab31326..b186b32 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -141,11 +141,11 @@ int arch_misc_init(void)
 {
 #ifdef CONFIG_AM335X_USB0
musb_register(otg0_plat, otg0_board_data,
-   (void *)AM335X_USB0_OTG_BASE);
+   (void *)USB0_OTG_BASE);
 #endif
 #ifdef CONFIG_AM335X_USB1
musb_register(otg1_plat, otg1_board_data,
-   (void *)AM335X_USB1_OTG_BASE);
+   (void *)USB1_OTG_BASE);
 #endif
return 0;
 }
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h 
b/arch/arm/include/asm/arch-am33xx/hardware.h
index 6dd3296..7016e25 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -84,14 +84,14 @@
 #define GPMC_BASE  0x5000
 
 /* CPSW Config space */
-#define AM335X_CPSW_BASE   0x4A10
-#define AM335X_CPSW_MDIO_BASE  0x4A101000
+#define CPSW_BASE  0x4A10
+#define CPSW_MDIO_BASE 0x4A101000
 
 /* RTC base address */
-#define AM335X_RTC_BASE0x44E3E000
+#define RTC_BASE   0x44E3E000
 
 /* OTG */
-#define AM335X_USB0_OTG_BASE   0x47401000
-#define AM335X_USB1_OTG_BASE   0x47401800
+#define USB0_OTG_BASE  0x47401000
+#define USB1_OTG_BASE  0x47401800
 
 #endif /* __AM33XX_HARDWARE_H */
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 55bc018..471725a 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -61,7 +61,7 @@ static struct ctrl_dev *cdev = (struct ctrl_dev 
*)CTRL_DEVICE_BASE;
 
 static void rtc32k_enable(void)
 {
-   struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
+   struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
 
/*
 * Unlock the RTC's registers.  For more details please see the
@@ -199,8 +199,8 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 };
 
 static struct cpsw_platform_data cpsw_data = {
-   .mdio_base  = AM335X_CPSW_MDIO_BASE,
-   .cpsw_base  = AM335X_CPSW_BASE,
+   .mdio_base  = CPSW_MDIO_BASE,
+   .cpsw_base  = CPSW_BASE,
.mdio_div   = 0xff,
.channels   = 8,
.cpdma_reg_ofs  = 0x800,
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 48e6896..0948889 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -134,7 +134,7 @@ static int read_eeprom(void)
 
 static void rtc32k_enable(void)
 {
-   struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
+   struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
 
/*
 * Unlock the RTC's registers.  For more details please see the
@@ -411,8 +411,8 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 };
 
 static struct cpsw_platform_data cpsw_data = {
-   .mdio_base  = AM335X_CPSW_MDIO_BASE,
-   .cpsw_base  = AM335X_CPSW_BASE,
+   .mdio_base  = CPSW_MDIO_BASE,
+   .cpsw_base  = CPSW_BASE,
.mdio_div   = 0xff,
.channels   = 8,
.cpdma_reg_ofs  = 0x800,
-- 
1.7.9.5

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[U-Boot] [PATCH v4 2/9] am33xx: refactor emif4/ddr to support multiple EMIF instances

[Matt Porter]

The AM33xx emif4/ddr support closely matches what is need to support
TI814x except that TI814x has two EMIF instances. Refactor all the
emif4 helper calls and the config_ddr() init function to use an
additional instance number argument.

Signed-off-by: Matt Porter mpor...@ti.com
Reviewed-by: Tom Rini tr...@ti.com

---
v4:
* fix unused variable warning
* fix pcm051 build breakage
v3: no change
v2:
* fix bad cast causing ddr.c warnings
* Split hardware.h - hardware_am33xx.h/ti814x.h
---
 arch/arm/cpu/armv7/am33xx/ddr.c|   99 
 arch/arm/cpu/armv7/am33xx/emif4.c  |   40 
 arch/arm/include/asm/arch-am33xx/ddr_defs.h|   52 --
 arch/arm/include/asm/arch-am33xx/hardware.h|   13 ++-
 arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |   30 ++
 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |   30 ++
 board/phytec/pcm051/board.c|2 +-
 board/ti/am335x/board.c|6 +-
 8 files changed, 200 insertions(+), 72 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index fd9fc4a..4b771c8 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -24,15 +24,20 @@ http://www.ti.com/
 /**
  * Base address for EMIF instances
  */
-static struct emif_reg_struct *emif_reg = {
-   (struct emif_reg_struct *)EMIF4_0_CFG_BASE};
+static struct emif_reg_struct *emif_reg[2] = {
+   (struct emif_reg_struct *)EMIF4_0_CFG_BASE,
+   (struct emif_reg_struct *)EMIF4_1_CFG_BASE};
 
 /**
- * Base address for DDR instance
+ * Base addresses for DDR PHY cmd/data regs
  */
-static struct ddr_regs *ddr_reg[2] = {
-   (struct ddr_regs *)DDR_PHY_BASE_ADDR,
-   (struct ddr_regs *)DDR_PHY_BASE_ADDR2};
+static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
+   (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
+   (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
+
+static struct ddr_data_regs *ddr_data_reg[2] = {
+   (struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
+   (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
 
 /**
  * Base address for ddr io control instances
@@ -43,70 +48,84 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
 /**
  * Configure SDRAM
  */
-void config_sdram(const struct emif_regs *regs)
+void config_sdram(const struct emif_regs *regs, int nr)
 {
-   writel(regs-ref_ctrl, emif_reg-emif_sdram_ref_ctrl);
-   writel(regs-ref_ctrl, emif_reg-emif_sdram_ref_ctrl_shdw);
+   writel(regs-ref_ctrl, emif_reg[nr]-emif_sdram_ref_ctrl);
+   writel(regs-ref_ctrl, emif_reg[nr]-emif_sdram_ref_ctrl_shdw);
if (regs-zq_config){
-   writel(regs-zq_config, emif_reg-emif_zq_config);
+   writel(regs-zq_config, emif_reg[nr]-emif_zq_config);
writel(regs-sdram_config, cstat-secure_emif_sdram_config);
}
-   writel(regs-sdram_config, emif_reg-emif_sdram_config);
+   writel(regs-sdram_config, emif_reg[nr]-emif_sdram_config);
 }
 
 /**
  * Set SDRAM timings
  */
-void set_sdram_timings(const struct emif_regs *regs)
+void set_sdram_timings(const struct emif_regs *regs, int nr)
 {
-   writel(regs-sdram_tim1, emif_reg-emif_sdram_tim_1);
-   writel(regs-sdram_tim1, emif_reg-emif_sdram_tim_1_shdw);
-   writel(regs-sdram_tim2, emif_reg-emif_sdram_tim_2);
-   writel(regs-sdram_tim2, emif_reg-emif_sdram_tim_2_shdw);
-   writel(regs-sdram_tim3, emif_reg-emif_sdram_tim_3);
-   writel(regs-sdram_tim3, emif_reg-emif_sdram_tim_3_shdw);
+   writel(regs-sdram_tim1, emif_reg[nr]-emif_sdram_tim_1);
+   writel(regs-sdram_tim1, emif_reg[nr]-emif_sdram_tim_1_shdw);
+   writel(regs-sdram_tim2, emif_reg[nr]-emif_sdram_tim_2);
+   writel(regs-sdram_tim2, emif_reg[nr]-emif_sdram_tim_2_shdw);
+   writel(regs-sdram_tim3, emif_reg[nr]-emif_sdram_tim_3);
+   writel(regs-sdram_tim3, emif_reg[nr]-emif_sdram_tim_3_shdw);
 }
 
 /**
  * Configure DDR PHY
  */
-void config_ddr_phy(const struct emif_regs *regs)
+void config_ddr_phy(const struct emif_regs *regs, int nr)
 {
-   writel(regs-emif_ddr_phy_ctlr_1, emif_reg-emif_ddr_phy_ctrl_1);
-   writel(regs-emif_ddr_phy_ctlr_1, emif_reg-emif_ddr_phy_ctrl_1_shdw);
+   writel(regs-emif_ddr_phy_ctlr_1,
+   emif_reg[nr]-emif_ddr_phy_ctrl_1);
+   writel(regs-emif_ddr_phy_ctlr_1,
+   emif_reg[nr]-emif_ddr_phy_ctrl_1_shdw);
 }
 
 /**
  * Configure DDR CMD control registers
  */
-void config_cmd_ctrl(const struct cmd_control *cmd)
+void config_cmd_ctrl(const struct cmd_control *cmd

[U-Boot] [PATCH v4 3/9] am33xx: refactor am33xx clocks and add ti814x support

[Matt Porter]

Split clock.c for am335x and ti814x and add ti814x specific
clock support.

Signed-off-by: Matt Porter mpor...@ti.com

---
v4: no changes
v3:
* Fix EMIF/L3F clock enable ordering issue
  (Exposed on UART boot with hang at check for L3F enabled)
v2:
* remove unused dmtimer support
* add register structs bit definitions
* rename soc-specific clock files for consistency
* move ti814x specific defs to clock_ti814x.c
* move am335x specific defs to clock_am335x.c
* fix copyright date
* remove clocks_*.h and go back to clock.h
---
 arch/arm/cpu/armv7/am33xx/Makefile |3 +-
 .../cpu/armv7/am33xx/{clock.c = clock_am33xx.c}   |   34 +-
 arch/arm/cpu/armv7/am33xx/clock_ti814x.c   |  406 
 arch/arm/include/asm/arch-am33xx/clock.h   |2 +-
 arch/arm/include/asm/arch-am33xx/clocks_am33xx.h   |   33 +-
 5 files changed, 443 insertions(+), 35 deletions(-)
 rename arch/arm/cpu/armv7/am33xx/{clock.c = clock_am33xx.c} (91%)
 create mode 100644 arch/arm/cpu/armv7/am33xx/clock_ti814x.c

diff --git a/arch/arm/cpu/armv7/am33xx/Makefile 
b/arch/arm/cpu/armv7/am33xx/Makefile
index 70c443e..c97e30d 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -16,7 +16,8 @@ include $(TOPDIR)/config.mk
 
 LIB= $(obj)lib$(SOC).o
 
-COBJS  += clock.o
+COBJS-$(CONFIG_AM33XX) += clock_am33xx.o
+COBJS-$(CONFIG_TI814X) += clock_ti814x.o
 COBJS  += sys_info.o
 COBJS  += mem.o
 COBJS  += ddr.o
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c 
b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
similarity index 91%
rename from arch/arm/cpu/armv7/am33xx/clock.c
rename to arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index d7d98d1..65cb9f8 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -1,9 +1,9 @@
 /*
- * clock.c
+ * clock_am33xx.c
  *
  * clocks for AM33XX based boards
  *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -42,6 +42,36 @@
 #define CPGMAC0_IDLE   0x3
 #define DPLL_CLKDCOLDO_GATE_CTRL0x300
 
+#define OSC(V_OSCK/100)
+
+/* MAIN PLL Fdll = 550 MHZ, */
+#define MPUPLL_M   550
+#define MPUPLL_N   (OSC-1)
+#define MPUPLL_M2  1
+
+/* Core PLL Fdll = 1 GHZ, */
+#define COREPLL_M  1000
+#define COREPLL_N  (OSC-1)
+
+#define COREPLL_M4 10  /* CORE_CLKOUTM4 = 200 MHZ */
+#define COREPLL_M5 8   /* CORE_CLKOUTM5 = 250 MHZ */
+#define COREPLL_M6 4   /* CORE_CLKOUTM6 = 500 MHZ */
+
+/*
+ * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
+ * frequency needs to be set to 960 MHZ. Hence,
+ * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
+ */
+#define PERPLL_M   960
+#define PERPLL_N   (OSC-1)
+#define PERPLL_M2  5
+
+/* DDR Freq is 266 MHZ for now */
+/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) 
*/
+#define DDRPLL_M   266
+#define DDRPLL_N   (OSC-1)
+#define DDRPLL_M2  1
+
 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c 
b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
new file mode 100644
index 000..cb4210f
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -0,0 +1,406 @@
+/*
+ * clock_ti814x.c
+ *
+ * Clocks for TI814X based boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include asm/arch/cpu.h
+#include asm/arch/clock.h
+#include asm/arch/hardware.h
+#include asm/io.h
+
+/* PRCM */
+#define PRCM_MOD_EN0x2
+
+/* CLK_SRC */
+#define OSC_SRC0   0
+#define OSC_SRC1   1
+
+#define L3_OSC_SRC OSC_SRC0
+
+#define OSC_0_FREQ 20
+
+#define DCO_HS2_MIN500
+#define DCO_HS2_MAX1000
+#define DCO_HS1_MIN1000
+#define DCO_HS1_MAX2000
+
+#define SELFREQDCO_HS2 0x0801
+#define SELFREQDCO_HS1 0x1001
+
+#define MPU_N  0x1
+#define MPU_M

[U-Boot] [PATCH v4 4/9] am33xx: refactor am33xx mux support and add ti814x support

[Matt Porter]

AM33XX and TI814X have a similar mux though the pinmux register
layout and address space differ. Add a separate ti814x mux include
to support the TI814X-specific differences.

Signed-off-by: Matt Porter mpor...@ti.com
Reviewed-by: Tom Rini tr...@ti.com
Acked-by: Peter Korsgaard jac...@sunsite.dk

---
v4: no changes
v3: no changes
v2:
* fixed copyright date and file header
* rename split mux includes for consistency
---
 arch/arm/include/asm/arch-am33xx/mux.h|  235 +--
 arch/arm/include/asm/arch-am33xx/mux_am33xx.h |  247 
 arch/arm/include/asm/arch-am33xx/mux_ti814x.h |  311 +
 3 files changed, 566 insertions(+), 227 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-am33xx/mux_am33xx.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/mux_ti814x.h

diff --git a/arch/arm/include/asm/arch-am33xx/mux.h 
b/arch/arm/include/asm/arch-am33xx/mux.h
index 460ac1c..1c6b65f 100644
--- a/arch/arm/include/asm/arch-am33xx/mux.h
+++ b/arch/arm/include/asm/arch-am33xx/mux.h
@@ -1,7 +1,7 @@
 /*
  * mux.h
  *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -19,234 +19,15 @@
 #include common.h
 #include asm/io.h
 
-#define MUX_CFG(value, offset) \
-   __raw_writel(value, (CTRL_BASE + offset));
-
-/* PAD Control Fields */
-#define SLEWCTRL   (0x1  6)
-#define RXACTIVE   (0x1  5)
-#define PULLDOWN_EN(0x0  4) /* Pull Down Selection */
-#define PULLUP_EN  (0x1  4) /* Pull Up Selection */
-#define PULLUDEN   (0x0  3) /* Pull up enabled */
-#define PULLUDDIS  (0x1  3) /* Pull up disabled */
-#define MODE(val)  val /* used for Readability */
-
-/*
- * PAD CONTROL OFFSETS
- * Field names corresponds to the pad signal name
- */
-struct pad_signals {
-   int gpmc_ad0;
-   int gpmc_ad1;
-   int gpmc_ad2;
-   int gpmc_ad3;
-   int gpmc_ad4;
-   int gpmc_ad5;
-   int gpmc_ad6;
-   int gpmc_ad7;
-   int gpmc_ad8;
-   int gpmc_ad9;
-   int gpmc_ad10;
-   int gpmc_ad11;
-   int gpmc_ad12;
-   int gpmc_ad13;
-   int gpmc_ad14;
-   int gpmc_ad15;
-   int gpmc_a0;
-   int gpmc_a1;
-   int gpmc_a2;
-   int gpmc_a3;
-   int gpmc_a4;
-   int gpmc_a5;
-   int gpmc_a6;
-   int gpmc_a7;
-   int gpmc_a8;
-   int gpmc_a9;
-   int gpmc_a10;
-   int gpmc_a11;
-   int gpmc_wait0;
-   int gpmc_wpn;
-   int gpmc_be1n;
-   int gpmc_csn0;
-   int gpmc_csn1;
-   int gpmc_csn2;
-   int gpmc_csn3;
-   int gpmc_clk;
-   int gpmc_advn_ale;
-   int gpmc_oen_ren;
-   int gpmc_wen;
-   int gpmc_be0n_cle;
-   int lcd_data0;
-   int lcd_data1;
-   int lcd_data2;
-   int lcd_data3;
-   int lcd_data4;
-   int lcd_data5;
-   int lcd_data6;
-   int lcd_data7;
-   int lcd_data8;
-   int lcd_data9;
-   int lcd_data10;
-   int lcd_data11;
-   int lcd_data12;
-   int lcd_data13;
-   int lcd_data14;
-   int lcd_data15;
-   int lcd_vsync;
-   int lcd_hsync;
-   int lcd_pclk;
-   int lcd_ac_bias_en;
-   int mmc0_dat3;
-   int mmc0_dat2;
-   int mmc0_dat1;
-   int mmc0_dat0;
-   int mmc0_clk;
-   int mmc0_cmd;
-   int mii1_col;
-   int mii1_crs;
-   int mii1_rxerr;
-   int mii1_txen;
-   int mii1_rxdv;
-   int mii1_txd3;
-   int mii1_txd2;
-   int mii1_txd1;
-   int mii1_txd0;
-   int mii1_txclk;
-   int mii1_rxclk;
-   int mii1_rxd3;
-   int mii1_rxd2;
-   int mii1_rxd1;
-   int mii1_rxd0;
-   int rmii1_refclk;
-   int mdio_data;
-   int mdio_clk;
-   int spi0_sclk;
-   int spi0_d0;
-   int spi0_d1;
-   int spi0_cs0;
-   int spi0_cs1;
-   int ecap0_in_pwm0_out;
-   int uart0_ctsn;
-   int uart0_rtsn;
-   int uart0_rxd;
-   int uart0_txd;
-   int uart1_ctsn;
-   int uart1_rtsn;
-   int uart1_rxd;
-   int uart1_txd;
-   int i2c0_sda;
-   int i2c0_scl;
-   int mcasp0_aclkx;
-   int mcasp0_fsx;
-   int mcasp0_axr0;
-   int mcasp0_ahclkr;
-   int mcasp0_aclkr;
-   int mcasp0_fsr;
-   int mcasp0_axr1;
-   int mcasp0_ahclkx;
-   int xdma_event_intr0;
-   int xdma_event_intr1;
-   int nresetin_out;
-   int porz;
-   int nnmi;
-   int osc0_in;
-   int osc0_out;
-   int rsvd1;
-   int tms;
-   int tdi;
-   int tdo;
-   int tck;
-   int ntrst;
-   int emu0;
-   int emu1;
-   int osc1_in;
-   int osc1_out;
-   int pmic_power_en;
-   int rtc_porz;
-   int rsvd2;
-   int ext_wakeup;
-   int enz_kaldo_1p8v

[U-Boot] [PATCH v4 5/9] am33xx: add ti814x specific register definitions

[Matt Porter]

Support the ti814x specific register definitions within
arch-am33xx.

Signed-off-by: Matt Porter mpor...@ti.com
Reviewed-by: Tom Rini tr...@ti.com

---
v4: Removed config.h from omap.h
v3: no changes
v2: Update for hardware.h split
---
 arch/arm/cpu/armv7/am33xx/sys_info.c   |3 +++
 arch/arm/include/asm/arch-am33xx/cpu.h |   11 +
 arch/arm/include/asm/arch-am33xx/hardware.h|   21 -
 arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |   24 
 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |   23 +++
 arch/arm/include/asm/arch-am33xx/omap.h|5 
 arch/arm/include/asm/arch-am33xx/spl.h |5 
 7 files changed, 71 insertions(+), 21 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c 
b/arch/arm/cpu/armv7/am33xx/sys_info.c
index 507b618..402127c 100644
--- a/arch/arm/cpu/armv7/am33xx/sys_info.c
+++ b/arch/arm/cpu/armv7/am33xx/sys_info.c
@@ -98,6 +98,9 @@ int print_cpuinfo(void)
case AM335X:
cpu_s = AM335X;
break;
+   case TI81XX:
+   cpu_s = TI81XX;
+   break;
default:
cpu_s = Unknown cpu type;
break;
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h 
b/arch/arm/include/asm/arch-am33xx/cpu.h
index 16e8a80..3d3a7c8 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -42,9 +42,10 @@
 #define HS_DEVICE  0x2
 #define GP_DEVICE  0x3
 
-/* cpu-id for AM33XX family */
+/* cpu-id for AM33XX and TI81XX family */
 #define AM335X 0xB944
-#define DEVICE_ID  0x44E10600
+#define TI81XX 0xB81E
+#define DEVICE_ID  (CTRL_BASE + 0x0600)
 
 /* This gives the status of the boot mode pins on the evm */
 #define SYSBOOT_MASK   (BIT(0) | BIT(1) | BIT(2)\
@@ -52,9 +53,11 @@
 
 /* Reset control */
 #ifdef CONFIG_AM33XX
-#define PRM_RSTCTRL0x44E00F00
-#define PRM_RSTST  0x44E00F08
+#define PRM_RSTCTRL(PRCM_BASE + 0x0F00)
+#elif defined(CONFIG_TI814X)
+#define PRM_RSTCTRL(PRCM_BASE + 0x00A0)
 #endif
+#define PRM_RSTST  (PRM_RSTCTRL + 8)
 #define PRM_RSTCTRL_RESET  0x01
 #define PRM_RSTST_WARM_RESET_MASK  0x232
 
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h 
b/arch/arm/include/asm/arch-am33xx/hardware.h
index 24a9b8d..5a27f9c 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -19,6 +19,7 @@
 #ifndef __AM33XX_HARDWARE_H
 #define __AM33XX_HARDWARE_H
 
+#include config.h
 #include asm/arch/omap.h
 #ifdef CONFIG_AM33XX
 #include asm/arch/hardware_am33xx.h
@@ -26,8 +27,9 @@
 #include asm/arch/hardware_ti814x.h
 #endif
 
-/* Module base addresses */
-#define UART0_BASE 0x44E09000
+/*
+ * Common hardware definitions
+ */
 
 /* DM Timer base addresses */
 #define DM_TIMER0_BASE 0x4802C000
@@ -42,21 +44,10 @@
 /* GPIO Base address */
 #define GPIO0_BASE 0x48032000
 #define GPIO1_BASE 0x4804C000
-#define GPIO2_BASE 0x481AC000
 
 /* BCH Error Location Module */
 #define ELM_BASE   0x4808
 
-/* Watchdog Timer */
-#define WDT_BASE   0x44E35000
-
-/* Control Module Base Address */
-#define CTRL_BASE  0x44E1
-#define CTRL_DEVICE_BASE   0x44E10600
-
-/* PRCM Base Address */
-#define PRCM_BASE  0x44E0
-
 /* EMIF Base address */
 #define EMIF4_0_CFG_BASE   0x4C00
 #define EMIF4_1_CFG_BASE   0x4D00
@@ -90,10 +81,6 @@
 
 /* CPSW Config space */
 #define CPSW_BASE  0x4A10
-#define CPSW_MDIO_BASE 0x4A101000
-
-/* RTC base address */
-#define RTC_BASE   0x44E3E000
 
 /* OTG */
 #define USB0_OTG_BASE  0x47401000
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h 
b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
index 7a4070c..fa02f19 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
@@ -19,6 +19,24 @@
 #ifndef __AM33XX_HARDWARE_AM33XX_H
 #define __AM33XX_HARDWARE_AM33XX_H
 
+/* Module base addresses */
+
+/* UART Base Address */
+#define UART0_BASE 0x44E09000
+
+/* GPIO Base address */
+#define GPIO2_BASE 0x481AC000
+
+/* Watchdog Timer */
+#define WDT_BASE   0x44E35000
+
+/* Control Module Base Address */
+#define CTRL_BASE  0x44E1
+#define CTRL_DEVICE_BASE   0x44E10600
+
+/* PRCM Base Address */
+#define PRCM_BASE  0x44E0

[U-Boot] [PATCH v4 7/9] am33xx: support ti814x mmc reference clock

[Matt Porter]

TI814x has a 192MHz hsmmc reference clock. Select that clock rate
when building for TI814x.

Signed-off-by: Matt Porter mpor...@ti.com

---
v4: no changes
v3: no changes
v2: no changes, new to the series
---
 arch/arm/include/asm/arch-am33xx/mmc_host_def.h |4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h 
b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
index 1f597c0..e0a3b8b 100644
--- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -153,7 +153,11 @@ typedef struct hsmmc {
 #define MMC_CMD0   (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
 
 /* Clock Configurations and Macros */
+#ifdef CONFIG_AM33XX
 #define MMC_CLOCK_REFERENCE96 /* MHz */
+#elif defined(CONFIG_TI814X)
+#define MMC_CLOCK_REFERENCE192 /* MHz */
+#endif
 
 #define mmc_reg_out(addr, mask, val)\
writel((readl(addr)  (~(mask))) | ((val)  (mask)), (addr))
-- 
1.7.9.5

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[U-Boot] [PATCH v4 6/9] am33xx: add dmm support to emif4 library

[Matt Porter]

Adds a config_dmm() routine to support TI814X DMM configuration.

Signed-off-by: Matt Porter mpor...@ti.com
Reviewed-by: Tom Rini tr...@ti.com

---
v4: no changes
v3: no changes
v2: no changes
---
 arch/arm/cpu/armv7/am33xx/emif4.c   |   17 +
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |5 +
 2 files changed, 22 insertions(+)

diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c 
b/arch/arm/cpu/armv7/am33xx/emif4.c
index 76459d8..aa84e96 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -44,6 +44,8 @@ void dram_init_banksize(void)
 
 
 #ifdef CONFIG_SPL_BUILD
+static struct dmm_lisa_map_regs *hw_lisa_map_regs =
+   (struct dmm_lisa_map_regs *)DMM_BASE;
 static struct vtp_reg *vtpreg[2] = {
(struct vtp_reg *)VTP0_CTRL_ADDR,
(struct vtp_reg *)VTP1_CTRL_ADDR};
@@ -51,6 +53,21 @@ static struct vtp_reg *vtpreg[2] = {
 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
 #endif
 
+void config_dmm(const struct dmm_lisa_map_regs *regs)
+{
+   enable_dmm_clocks();
+
+   writel(0, hw_lisa_map_regs-dmm_lisa_map_3);
+   writel(0, hw_lisa_map_regs-dmm_lisa_map_2);
+   writel(0, hw_lisa_map_regs-dmm_lisa_map_1);
+   writel(0, hw_lisa_map_regs-dmm_lisa_map_0);
+
+   writel(regs-dmm_lisa_map_3, hw_lisa_map_regs-dmm_lisa_map_3);
+   writel(regs-dmm_lisa_map_2, hw_lisa_map_regs-dmm_lisa_map_2);
+   writel(regs-dmm_lisa_map_1, hw_lisa_map_regs-dmm_lisa_map_1);
+   writel(regs-dmm_lisa_map_0, hw_lisa_map_regs-dmm_lisa_map_0);
+}
+
 static void config_vtp(int nr)
 {
writel(readl(vtpreg[nr]-vtp0ctrlreg) | VTP_CTRL_ENABLE,
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h 
b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 1cbadff..15ca4c1 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -100,6 +100,11 @@
 #define MT41J512M8RH125_IOCTRL_VALUE   0x18B
 
 /**
+ * Configure DMM
+ */
+void config_dmm(const struct dmm_lisa_map_regs *regs);
+
+/**
  * Configure SDRAM
  */
 void config_sdram(const struct emif_regs *regs, int nr);
-- 
1.7.9.5

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[U-Boot] [PATCH v4 8/9] ns16550: enable quirks for ti814x

[Matt Porter]

TI814X requires the same quirks as AM33XX to be enabled.

Signed-off-by: Matt Porter mpor...@ti.com
Reviewed-by: Tom Rini tr...@ti.com

---
v4: no changes
v3: no changes
v2: no changes
---
 drivers/serial/ns16550.c |5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 87a0917..02bc85b 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -43,7 +43,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
 
serial_out(CONFIG_SYS_NS16550_IER, com_port-ier);
 #if (defined(CONFIG_OMAP)  !defined(CONFIG_OMAP3_ZOOM2)) || \
-   defined(CONFIG_AM33XX)
+   defined(CONFIG_AM33XX) || defined(CONFIG_TI814X)
serial_out(0x7, com_port-mdr1);   /* mode select reset TL16C750*/
 #endif
serial_out(UART_LCR_BKSE | UART_LCRVAL, (ulong)com_port-lcr);
@@ -57,7 +57,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
serial_out((baud_divisor  8)  0xff, com_port-dlm);
serial_out(UART_LCRVAL, com_port-lcr);
 #if (defined(CONFIG_OMAP)  !defined(CONFIG_OMAP3_ZOOM2)) || \
-   defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX)
+   defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \
+   defined(CONFIG_TI814X)
 
 #if defined(CONFIG_APTIX)
/* /13 mode so Aptix 6MHz can hit 115200 */
-- 
1.7.9.5

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[U-Boot] [PATCH v4 9/9] ti814x_evm: add ti814x evm board support

[Matt Porter]

Add TI814X EVM board directory, config file, and MAINTAINERS
entry. Enable build.

Signed-off-by: Matt Porter mpor...@ti.com
Reviewed-by: Tom Rini tr...@ti.com

---
v4: * Removed unused include
* Removed CONFIG_FS_* options to use fallbacks
v3: no change
v2:
* squash MAINTAINERS and Makefile commits here
* config file fixes (copyright, mtest, findfdt, fs options, cleanups)
* move wdtimer variable under SPL build
---
 MAINTAINERS |4 +
 Makefile|2 +-
 arch/arm/cpu/armv7/Makefile |2 +-
 arch/arm/cpu/armv7/omap-common/Makefile |2 +-
 board/ti/ti814x/Makefile|   46 +++
 board/ti/ti814x/evm.c   |  198 
 board/ti/ti814x/evm.h   |7 +
 board/ti/ti814x/mux.c   |   51 +++
 boards.cfg  |1 +
 include/configs/ti814x_evm.h|  220 +++
 spl/Makefile|2 +-
 11 files changed, 531 insertions(+), 4 deletions(-)
 create mode 100644 board/ti/ti814x/Makefile
 create mode 100644 board/ti/ti814x/evm.c
 create mode 100644 board/ti/ti814x/evm.h
 create mode 100644 board/ti/ti814x/mux.c
 create mode 100644 include/configs/ti814x_evm.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 6b1f657..3a59c6c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -832,6 +832,10 @@ Stelian Pop stel...@popies.net
at91sam9263ek   ARM926EJS (AT91SAM9263 SoC)
at91sam9rlekARM926EJS (AT91SAM9RL SoC)
 
+Matt Porter mpor...@ti.com
+
+   ti814x_evm  ARM ARMV7 (TI814x Soc)
+
 Dave Purdy david.c.pu...@gmail.com
 
pogo_e02ARM926EJS (Kirkwood SoC)
diff --git a/Makefile b/Makefile
index 55bd55c..4e3e242 100644
--- a/Makefile
+++ b/Makefile
@@ -331,7 +331,7 @@ LIBS-y += api/libapi.o
 LIBS-y += post/libpost.o
 LIBS-y += test/libtest.o
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+ifneq 
($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
 
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index ee8c2b3..c961247 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,7 @@ COBJS += cache_v7.o
 COBJS  += cpu.o
 COBJS  += syslib.o
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA),)
+ifneq 
($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_TI814X),)
 SOBJS  += lowlevel_init.o
 endif
 
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile 
b/arch/arm/cpu/armv7/omap-common/Makefile
index 0efc80d..55e82ba 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -36,7 +36,7 @@ COBJS += emif-common.o
 COBJS  += vc.o
 endif
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
 COBJS  += boot-common.o
 SOBJS  += lowlevel_init.o
 endif
diff --git a/board/ti/ti814x/Makefile b/board/ti/ti814x/Makefile
new file mode 100644
index 000..09d2422
--- /dev/null
+++ b/board/ti/ti814x/Makefile
@@ -0,0 +1,46 @@
+#
+# Makefile
+#
+# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed as is WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS  := mux.o
+endif
+
+COBJS  += evm.o
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+   $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+   rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+   rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
new file mode 100644
index 000..acc18fb
--- /dev/null
+++ b/board/ti/ti814x/evm.c
@@ -0,0 +1,198 @@
+/*
+ * evm.c
+ *
+ * Board functions for TI814x EVM
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute

[U-Boot] [PATCH] .checkpatch.conf: ignore udelay-usleep_range warnings

[Matt Porter]

usleep_range() is a Linux facility, ignore it when udelay()
is encountered.

Signed-off-by: Matt Porter mpor...@ti.com
---
 .checkpatch.conf |3 +++
 1 file changed, 3 insertions(+)

diff --git a/.checkpatch.conf b/.checkpatch.conf
index 38386b3..d88af57 100644
--- a/.checkpatch.conf
+++ b/.checkpatch.conf
@@ -15,3 +15,6 @@
 
 # enable more tests
 --strict
+
+# Not Linux, so we don't recommend usleep_range() over udelay()
+--ignore USLEEP_RANGE
-- 
1.7.9.5

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[U-Boot] [PATCH 0/4] Enable CPSW on TI814x EVM

[Matt Porter]

This series adds support for CPSW on the PG1.0 TI814x EVM board. 
The V1 CPSW on TI814x requires minor register changes to the
existing driver as well as TI814x-specific pll/clock support.
An ET1011C phy driver is added to support the PHY present on the
PG1.0 EVM.

It has been tested loading/booting a Linux kernel and regression
tested on BeagleBone and EVM-SK AM33XX boards. It has also been
MAKEALL tested for all am33xx platforms.

The series applies on top of the following patches:
- am33xx: Add required includes to some omap/am33xx code
  http://patchwork.ozlabs.org/patch/227804/
- Add TI814x EVM Support v4
  http://www.mail-archive.com/u-boot@lists.denx.de/msg108356.html

Matt Porter (4):
  am33xx: add pll and clock support for TI814x CPSW
  cpsw: add support for TI814x slave_regs differences
  phy: add support for ET1011C phys
  ti814x_evm: enable CPSW support

 arch/arm/cpu/armv7/am33xx/clock_ti814x.c   |   56 +-
 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |1 +
 board/ti/ti814x/evm.c  |   75 +
 board/ti/ti814x/evm.h  |1 +
 board/ti/ti814x/mux.c  |   35 +++
 drivers/net/cpsw.c |6 ++
 drivers/net/phy/Makefile   |1 +
 drivers/net/phy/et1011c.c  |  110 
 drivers/net/phy/phy.c  |3 +
 include/configs/ti814x_evm.h   |   21 
 include/phy.h  |1 +
 11 files changed, 308 insertions(+), 2 deletions(-)
 create mode 100644 drivers/net/phy/et1011c.c

-- 
1.7.9.5

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[U-Boot] [PATCH 1/4] am33xx: add pll and clock support for TI814x CPSW

[Matt Porter]

Enables required PLLs and clocks for CPSW on TI814x.

Signed-off-by: Matt Porter mpor...@ti.com
---
 arch/arm/cpu/armv7/am33xx/clock_ti814x.c   |   56 +++-
 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |1 +
 board/ti/ti814x/evm.c  |3 ++
 3 files changed, 58 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c 
b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
index cb4210f..69ecf72 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -183,7 +183,7 @@ struct cm_alwon {
unsigned int resv5[2];
unsigned int gpmcclkctrl;
unsigned int ethernet0clkctrl;
-   unsigned int resv6[1];
+   unsigned int ethernet1clkctrl;
unsigned int mpuclkctrl;
unsigned int debugssclkctrl;
unsigned int l3clkctrl;
@@ -203,9 +203,23 @@ struct cm_alwon {
unsigned int custefuseclkctrl;
 };
 
+#define SATA_PLL_BASE  (CTRL_BASE + 0x0720)
+
+struct sata_pll {
+   unsigned int pllcfg0;
+   unsigned int pllcfg1;
+   unsigned int pllcfg2;
+   unsigned int pllcfg3;
+   unsigned int pllcfg4;
+   unsigned int pllstatus;
+   unsigned int rxstatus;
+   unsigned int txstatus;
+   unsigned int testcfg;
+};
 
 const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
 const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
+const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
 
 /*
  * Enable the peripheral clock for required peripherals
@@ -221,6 +235,18 @@ static void enable_per_clocks(void)
writel(PRCM_MOD_EN, cmalwon-mmchs1clkctrl);
while (readl(cmalwon-mmchs1clkctrl) != PRCM_MOD_EN)
;
+
+   /* Ethernet */
+   writel(PRCM_MOD_EN, cmalwon-l3slowclkstctrl);
+   while ((readl(cmalwon-l3slowclkstctrl)  0x2100) != 0x2100)
+   ;
+   writel(PRCM_MOD_EN, cmalwon-ethclkstctrl);
+   writel(PRCM_MOD_EN, cmalwon-ethernet0clkctrl);
+   while ((readl(cmalwon-ethernet0clkctrl)  0x3) != 0)
+   ;
+   writel(PRCM_MOD_EN, cmalwon-ethernet1clkctrl);
+   while ((readl(cmalwon-ethernet1clkctrl)  0x3) != 0)
+   ;
 }
 
 /*
@@ -365,6 +391,31 @@ void ddr_pll_config(unsigned int ddrpll_m)
pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
 }
 
+void sata_pll_config(void)
+{
+   /* TRM 21.3.1 */
+   writel(0xc12c003c, spll-pllcfg1);
+   udelay(50);
+
+   writel(0x004008e0, spll-pllcfg3);
+   udelay(50);
+
+   writel(0x8004, spll-pllcfg0);
+   udelay(50);
+
+   writel(0x8014, spll-pllcfg0);
+   udelay(50);
+
+   writel(0x8016, spll-pllcfg0);
+   udelay(50);
+
+   writel(0xc017, spll-pllcfg0);
+   udelay(50);
+
+   while (((readl(spll-pllstatus)  0x01) == 0))
+   ;
+}
+
 void enable_emif_clocks(void) {};
 
 void enable_dmm_clocks(void)
@@ -397,9 +448,10 @@ void pll_init()
/* Enable the control module */
writel(PRCM_MOD_EN, cmalwon-controlclkctrl);
 
+   /* Configure PLLs */
mpu_pll_config();
-
l3_pll_config();
+   sata_pll_config();
 
/* Enable the required peripherals */
enable_per_clocks();
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h 
b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
index a950ac3..8f9315c 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
@@ -29,6 +29,7 @@
 
 /* Control Module Base Address */
 #define CTRL_BASE  0x4814
+#define CTRL_DEVICE_BASE   0x48140600
 
 /* PRCM Base Address */
 #define PRCM_BASE  0x4818
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index acc18fb..8513220 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -151,6 +151,9 @@ void s_init(void)
 */
wdt_disable();
 
+   /* Enable timer */
+   timer_init();
+
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
 
-- 
1.7.9.5

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[U-Boot] [PATCH 2/4] cpsw: add support for TI814x slave_regs differences

[Matt Porter]

TI814x's version 1 CPSW has a different slave_regs layout.
Add support for the differing registers.

Signed-off-by: Matt Porter mpor...@ti.com
---
 drivers/net/cpsw.c |6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index f5c5b9a..34c9fdd 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -109,7 +109,13 @@ struct cpsw_slave_regs {
u32 flow_thresh;
u32 port_vlan;
u32 tx_pri_map;
+#ifdef CONFIG_AM33XX
u32 gap_thresh;
+#elif defined(CONFIG_TI814X)
+   u32 ts_ctl;
+   u32 ts_seq_ltype;
+   u32 ts_vlan;
+#endif
u32 sa_lo;
u32 sa_hi;
 };
-- 
1.7.9.5

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[U-Boot] [PATCH 4/4] ti814x_evm: enable CPSW support

[Matt Porter]

Adds CPSW support to the TI814X EVM configured with
an ET1011C PHY in GMII mode.

Signed-off-by: Matt Porter mpor...@ti.com
---
 board/ti/ti814x/evm.c|   72 ++
 board/ti/ti814x/evm.h|1 +
 board/ti/ti814x/mux.c|   35 
 include/configs/ti814x_evm.h |   21 
 4 files changed, 129 insertions(+)

diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index 8513220..d6c19f5 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -17,6 +17,7 @@
  */
 
 #include common.h
+#include cpsw.h
 #include errno.h
 #include spl.h
 #include asm/arch/cpu.h
@@ -39,6 +40,8 @@ static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 #endif
 
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
 /* UART Defines */
 #ifdef CONFIG_SPL_BUILD
 #define UART_RESET (0x1  1)
@@ -166,6 +169,9 @@ void s_init(void)
/* Set MMC pins */
enable_mmc1_pin_mux();
 
+   /* Set Ethernet pins */
+   enable_enet_pin_mux();
+
/* Enable UART */
uart_enable();
 
@@ -199,3 +205,69 @@ int board_mmc_init(bd_t *bis)
return 0;
 }
 #endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+   /* VTP can be added here */
+
+   return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+   {
+   .slave_reg_ofs  = 0x50,
+   .sliver_reg_ofs = 0x700,
+   .phy_id = 1,
+   },
+   {
+   .slave_reg_ofs  = 0x90,
+   .sliver_reg_ofs = 0x740,
+   .phy_id = 0,
+   },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+   .mdio_base  = CPSW_MDIO_BASE,
+   .cpsw_base  = CPSW_BASE,
+   .mdio_div   = 0xff,
+   .channels   = 8,
+   .cpdma_reg_ofs  = 0x100,
+   .slaves = 1,
+   .slave_data = cpsw_slaves,
+   .ale_reg_ofs= 0x600,
+   .ale_entries= 1024,
+   .host_port_reg_ofs  = 0x28,
+   .hw_stats_reg_ofs   = 0x400,
+   .mac_control= (1  5),
+   .control= cpsw_control,
+   .host_port_num  = 0,
+   .version= CPSW_CTRL_VERSION_1,
+};
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+   uint8_t mac_addr[6];
+   uint32_t mac_hi, mac_lo;
+
+   if (!eth_getenv_enetaddr(ethaddr, mac_addr)) {
+   printf(ethaddr not set. Reading from E-fuse\n);
+   /* try reading mac address from efuse */
+   mac_lo = readl(cdev-macid0l);
+   mac_hi = readl(cdev-macid0h);
+   mac_addr[0] = mac_hi  0xFF;
+   mac_addr[1] = (mac_hi  0xFF00)  8;
+   mac_addr[2] = (mac_hi  0xFF)  16;
+   mac_addr[3] = (mac_hi  0xFF00)  24;
+   mac_addr[4] = mac_lo  0xFF;
+   mac_addr[5] = (mac_lo  0xFF00)  8;
+
+   if (is_valid_ether_addr(mac_addr))
+   eth_setenv_enetaddr(ethaddr, mac_addr);
+   else
+   printf(Unable to read MAC address. Set ethaddr\n);
+   }
+
+   return cpsw_register(cpsw_data);
+}
diff --git a/board/ti/ti814x/evm.h b/board/ti/ti814x/evm.h
index 40f8710..6aebec6 100644
--- a/board/ti/ti814x/evm.h
+++ b/board/ti/ti814x/evm.h
@@ -3,5 +3,6 @@
 
 void enable_uart0_pin_mux(void);
 void enable_mmc1_pin_mux(void);
+void enable_enet_pin_mux(void);
 
 #endif /* _EVM_H */
diff --git a/board/ti/ti814x/mux.c b/board/ti/ti814x/mux.c
index 137acb4..fd9f364 100644
--- a/board/ti/ti814x/mux.c
+++ b/board/ti/ti814x/mux.c
@@ -40,6 +40,36 @@ static struct module_pin_mux mmc1_pin_mux[] = {
{-1},
 };
 
+static struct module_pin_mux enet_pin_mux[] = {
+   {OFFSET(pincntl232), MODE(0x01)},   /* EMAC_RMREFCLK */
+   {OFFSET(pincntl233), PULLUP_EN | MODE(0x01)},   /* MDCLK */
+   {OFFSET(pincntl234), PULLUP_EN | MODE(0x01)},   /* MDIO */
+   {OFFSET(pincntl235), MODE(0x01)},   /* EMAC[0]_MTCLK */
+   {OFFSET(pincntl236), MODE(0x01)},   /* EMAC[0]_MCOL */
+   {OFFSET(pincntl237), MODE(0x01)},   /* EMAC[0]_MCRS */
+   {OFFSET(pincntl238), MODE(0x01)},   /* EMAC[0]_MRXER */
+   {OFFSET(pincntl239), MODE(0x01)},   /* EMAC[0]_MRCLK */
+   {OFFSET(pincntl240), MODE(0x01)},   /* EMAC[0]_MRXD[0] */
+   {OFFSET(pincntl241), MODE(0x01)},   /* EMAC[0]_MRXD[1] */
+   {OFFSET(pincntl242), MODE(0x01)},   /* EMAC[0]_MRXD[2] */
+   {OFFSET(pincntl243), MODE(0x01)},   /* EMAC[0]_MRXD[3] */
+   {OFFSET(pincntl244), MODE(0x01)},   /* EMAC[0]_MRXD[4] */
+   {OFFSET(pincntl245), MODE(0x01)},   /* EMAC[0]_MRXD[5

[U-Boot] [PATCH 3/4] phy: add support for ET1011C phys

[Matt Porter]

Adds an ET1011C PHY driver which is derived from
the current Linux kernel PHY driver. Note that an
errata workaround config option is implemented to
allow for TX_CLK to be enabled even when gigabit
mode is negotiated. This workaround is used on the
TI814x-EVM.

Signed-off-by: Matt Porter mpor...@ti.com
---
 drivers/net/phy/Makefile  |1 +
 drivers/net/phy/et1011c.c |  110 +
 drivers/net/phy/phy.c |3 ++
 include/phy.h |1 +
 4 files changed, 115 insertions(+)
 create mode 100644 drivers/net/phy/et1011c.c

diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 5e90d70..af5f4b8 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -34,6 +34,7 @@ COBJS-$(CONFIG_PHYLIB_10G) += generic_10g.o
 COBJS-$(CONFIG_PHY_ATHEROS) += atheros.o
 COBJS-$(CONFIG_PHY_BROADCOM) += broadcom.o
 COBJS-$(CONFIG_PHY_DAVICOM) += davicom.o
+COBJS-$(CONFIG_PHY_ET1011C) += et1011c.o
 COBJS-$(CONFIG_PHY_LXT) += lxt.o
 COBJS-$(CONFIG_PHY_MARVELL) += marvell.o
 COBJS-$(CONFIG_PHY_MICREL) += micrel.o
diff --git a/drivers/net/phy/et1011c.c b/drivers/net/phy/et1011c.c
new file mode 100644
index 000..5e22399
--- /dev/null
+++ b/drivers/net/phy/et1011c.c
@@ -0,0 +1,110 @@
+/*
+ * ET1011C PHY driver
+ *
+ * Derived from Linux kernel driver by Chaithrika U S
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include config.h
+#include phy.h
+
+#define ET1011C_CONFIG_REG (0x16)
+#define ET1011C_TX_FIFO_MASK   (0x3  12)
+#define ET1011C_TX_FIFO_DEPTH_8(0x0  12)
+#define ET1011C_TX_FIFO_DEPTH_16   (0x1  12)
+#define ET1011C_INTERFACE_MASK (0x7  0)
+#define ET1011C_GMII_INTERFACE (0x2  0)
+#define ET1011C_SYS_CLK_EN (0x1  4)
+#define ET1011C_TX_CLK_EN  (0x1  5)
+
+#define ET1011C_STATUS_REG (0x1A)
+#define ET1011C_DUPLEX_STATUS  (0x1  7)
+#define ET1011C_SPEED_MASK (0x3  8)
+#define ET1011C_SPEED_1000 (0x2  8)
+#define ET1011C_SPEED_100  (0x1  8)
+#define ET1011C_SPEED_10   (0x0  8)
+
+static int et1011c_config(struct phy_device *phydev)
+{
+   int ctl = 0;
+   ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
+   if (ctl  0)
+   return ctl;
+   ctl = ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 |
+BMCR_ANENABLE);
+   /* First clear the PHY */
+   phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET);
+
+   return genphy_config_aneg(phydev);
+}
+
+static int et1011c_parse_status(struct phy_device *phydev)
+{
+   int mii_reg;
+   int speed;
+
+   mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_STATUS_REG);
+
+   if (mii_reg  ET1011C_DUPLEX_STATUS)
+   phydev-duplex = DUPLEX_FULL;
+   else
+   phydev-duplex = DUPLEX_HALF;
+
+   speed = mii_reg  ET1011C_SPEED_MASK;
+   switch (speed) {
+   case ET1011C_SPEED_1000:
+   phydev-speed = SPEED_1000;
+   mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG);
+   mii_reg = ~ET1011C_TX_FIFO_MASK;
+   phy_write(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG,
+ mii_reg |
+ ET1011C_GMII_INTERFACE |
+ ET1011C_SYS_CLK_EN |
+#ifdef CONFIG_PHY_ET1011C_TX_CLK_FIX
+ ET1011C_TX_CLK_EN |
+#endif
+ ET1011C_TX_FIFO_DEPTH_16);
+   break;
+   case ET1011C_SPEED_100:
+   phydev-speed = SPEED_100;
+   break;
+   case ET1011C_SPEED_10:
+   phydev-speed = SPEED_10;
+   break;
+   }
+
+   return 0;
+}
+
+static int et1011c_startup(struct phy_device *phydev)
+{
+   genphy_update_link(phydev);
+   et1011c_parse_status(phydev);
+   return 0;
+}
+
+static struct phy_driver et1011c_driver = {
+   .name   = ET1011C,
+   .uid= 0x0282f014,
+   .mask   = 0xfff0,
+   .features   = PHY_GBIT_FEATURES,
+   .config = et1011c_config,
+   .startup= et1011c_startup,
+};
+
+int phy_et1011c_init(void)
+{
+   phy_register(et1011c_driver);
+
+   return 0;
+}
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index d0ed766..f8c5481 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net

Re: [U-Boot] [PATCH v2 1/3] am335x_evm: add support for BeagleBone Black DT name

[Matt Porter]

On Thu, Mar 14, 2013 at 07:53:07AM +0100, Koen Kooi wrote:
 
 Op 13 mrt. 2013, om 21:19 heeft Matt Porter mpor...@ti.com het volgende 
 geschreven:
 
  On Wed, Mar 13, 2013 at 08:02:26PM +0100, Koen Kooi wrote:
  
  Op 13 mrt. 2013, om 16:07 heeft Nishanth Menon n...@ti.com het volgende 
  geschreven:
  
  On 16:05-20130313, Koen Kooi wrote:
  
  Op 13 mrt. 2013, om 16:02 heeft Nishanth Menon n...@ti.com het 
  volgende geschreven:
  
  On Wed, Mar 13, 2013 at 9:57 AM, Koen Kooi k...@dominion.thruhere.net 
  wrote:
  
  Op 13 mrt. 2013, om 15:35 heeft Nishanth Menon n...@ti.com het 
  volgende geschreven:
  
  On 10:20-20130313, Tom Rini wrote:
  From: Koen Kooi k...@dominion.thruhere.net
  
  Signed-off-by: Koen Kooi k...@dominion.thruhere.net
  Acked-by: Peter Korsgaard jac...@sunsite.dk
  ---
  include/configs/am335x_evm.h |2 ++
  1 file changed, 2 insertions(+)
  
  diff --git a/include/configs/am335x_evm.h 
  b/include/configs/am335x_evm.h
  index 33ee2c4..abf4e39 100644
  --- a/include/configs/am335x_evm.h
  +++ b/include/configs/am335x_evm.h
  @@ -87,6 +87,8 @@
findfdt=\
if test $board_name = A335BONE; then  \
setenv fdtfile am335x-bone.dtb; fi;  \
  +if test $board_name = A335BNLT; then  \
  +setenv fdtfile am335x-bonelt.dtb; fi;  \
  could we not use am335x-boneblack.dtb instead?
  
  it's bonelt in the kernel, so boneblack would fail to load a dtb
  $ git describe
  v3.9-rc2
  $ ls arch/arm/boot/dts/*bone*.dts*
  arch/arm/boot/dts/am335x-bone.dts
  ???
  
  What a surprise, missing stuff in mainline! It's present in the vendor 
  kernel, which is what is shipping with the board.
  No surprise there as marketing names are finalized close to product
  launches. If there is an vendor u-boot, it can remain in sync with what
  ever the vendor kernel is. If it is upstream, we might want to think
  longterm.
  
  I'm in charge of pushing the am335x-bonelt.dts upstream to Linus and I'd 
  like to keep everything in sync. I'm not fond of renaming it again, the 
  EEPROM says BNLT, not BNB :)
  
  That's a horrible reason to confuse users. The EEPROM contents are
  irrelevant. Users look for something to match the board name, this
  does not. It's wrong.
 
 It is stupid, but that's what you get for renaming boards. The real problem 
 with this is that it is a flag day, the kernel and u-boot need to change both 
 at the same time. And after that you'll have a mismatch if you use different 
 versions.
 
 Anyway, patches welcome for the vendor kernel to rename it.

The pull request is https://github.com/beagleboard/kernel/pull/33

Should be easy to keep those in sync as you control the s/w going
out on all the new BeagleBones. The type of people that have early
boards can all handle s/w changes like this otherwise they shouldn't
be in the alpha test group.

Anything else that prevents us from fixing this fdtfile hunk now?

-Matt
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Re: [U-Boot] [PATCH v3 1/3] am335x_evm: add support for BeagleBone Black DT name

[Matt Porter]

On Thu, Mar 14, 2013 at 11:55:19AM -0400, Tom Rini wrote:
 From: Koen Kooi k...@dominion.thruhere.net
 
 Cc: Matt Porter mpor...@ti.com
 Cc: Nishanth Menon n...@ti.com
 Signed-off-by: Koen Kooi k...@dominion.thruhere.net
 Signed-off-by: Tom Rini tr...@ti.com
 ---
  include/configs/am335x_evm.h |2 ++
  1 file changed, 2 insertions(+)
 
 diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
 index 33ee2c4..377a3c5 100644
 --- a/include/configs/am335x_evm.h
 +++ b/include/configs/am335x_evm.h
 @@ -87,6 +87,8 @@
   findfdt=\
   if test $board_name = A335BONE; then  \
   setenv fdtfile am335x-bone.dtb; fi;  \
 + if test $board_name = A335BNLT; then  \
 + setenv fdtfile am335x-boneblack.dtb; fi;  \
   if test $board_name = A33515BB; then  \
   setenv fdtfile am335x-evm.dtb; fi;  \
   if test $board_name = A335X_SK; then  \

Koen has merged my pull request to the beagleboard/kernel tree so...

Acked-by: Matt Porter mpor...@ti.com
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Re: [U-Boot] [PATCH v2 1/3] am335x_evm: add support for BeagleBone Black DT name

[Matt Porter]

On Wed, Mar 13, 2013 at 08:02:26PM +0100, Koen Kooi wrote:
 
 Op 13 mrt. 2013, om 16:07 heeft Nishanth Menon n...@ti.com het volgende 
 geschreven:
 
  On 16:05-20130313, Koen Kooi wrote:
  
  Op 13 mrt. 2013, om 16:02 heeft Nishanth Menon n...@ti.com het volgende 
  geschreven:
  
  On Wed, Mar 13, 2013 at 9:57 AM, Koen Kooi k...@dominion.thruhere.net 
  wrote:
  
  Op 13 mrt. 2013, om 15:35 heeft Nishanth Menon n...@ti.com het 
  volgende geschreven:
  
  On 10:20-20130313, Tom Rini wrote:
  From: Koen Kooi k...@dominion.thruhere.net
  
  Signed-off-by: Koen Kooi k...@dominion.thruhere.net
  Acked-by: Peter Korsgaard jac...@sunsite.dk
  ---
  include/configs/am335x_evm.h |2 ++
  1 file changed, 2 insertions(+)
  
  diff --git a/include/configs/am335x_evm.h 
  b/include/configs/am335x_evm.h
  index 33ee2c4..abf4e39 100644
  --- a/include/configs/am335x_evm.h
  +++ b/include/configs/am335x_evm.h
  @@ -87,6 +87,8 @@
 findfdt=\
 if test $board_name = A335BONE; then  \
 setenv fdtfile am335x-bone.dtb; fi;  \
  +if test $board_name = A335BNLT; then  \
  +setenv fdtfile am335x-bonelt.dtb; fi;  \
  could we not use am335x-boneblack.dtb instead?
  
  it's bonelt in the kernel, so boneblack would fail to load a dtb
  $ git describe
  v3.9-rc2
  $ ls arch/arm/boot/dts/*bone*.dts*
  arch/arm/boot/dts/am335x-bone.dts
  ???
  
  What a surprise, missing stuff in mainline! It's present in the vendor 
  kernel, which is what is shipping with the board.
  No surprise there as marketing names are finalized close to product
  launches. If there is an vendor u-boot, it can remain in sync with what
  ever the vendor kernel is. If it is upstream, we might want to think
  longterm.
 
 I'm in charge of pushing the am335x-bonelt.dts upstream to Linus and I'd like 
 to keep everything in sync. I'm not fond of renaming it again, the EEPROM 
 says BNLT, not BNB :)

That's a horrible reason to confuse users. The EEPROM contents are
irrelevant. Users look for something to match the board name, this
does not. It's wrong.

-Matt
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Re: [U-Boot] [PATCH v2 7/9] am33xx: support ti814x mmc reference clock

[Matt Porter]

On Sun, Mar 03, 2013 at 10:34:08PM +, Peter Korsgaard wrote:
  Matt == Matt Porter mpor...@ti.com writes:
 
  Matt TI814x has a 192MHz hsmmc reference clock. Select that clock rate
  Matt when building for TI814x.
 
  Matt Signed-off-by: Matt Porter mpor...@ti.com
 
 Acked-by: Peter Korsgaard jac...@sunsite.dk
 
 Did you figure out why it was working for you with 96 MHz ref?

Unfortunately not at a root cause level. Unless I'm missing something I
would have expected the calculations from the supplied 96 MHz ref clock
to result in 2x the clock the SD card can handle due to the incorrect
divider. However, with the LA attached, I found that a 2-3 MHz SDCLK was
being generated after the capability probe occurs. Odd and incorrect,
but functional. After switching to 192MHz I was able to sample a
nominal 25MHz SDCLK as expected on a regular SD card advertising that as
its capability. I don't like it but I'm going to mark this down as
something undocumented as I only have PG1.0 silicon but can't find an
errata sheet for that version right now.

-Matt
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[U-Boot] [PATCH v3 3/9] am33xx: refactor am33xx clocks and add ti814x support

[Matt Porter]

Split clock.c for am335x and ti814x and add ti814x specific
clock support.

Signed-off-by: Matt Porter mpor...@ti.com

---
v3:
* Fix EMIF/L3F clock enable ordering issue
  (Exposed on UART boot with hang at check for L3F enabled)
v2:
* remove unused dmtimer support
* add register structs bit definitions
* rename soc-specific clock files for consistency
* move ti814x specific defs to clock_ti814x.c
* move am335x specific defs to clock_am335x.c
* fix copyright date
* remove clocks_*.h and go back to clock.h
---
 arch/arm/cpu/armv7/am33xx/Makefile |3 +-
 .../cpu/armv7/am33xx/{clock.c = clock_am33xx.c}   |   34 +-
 arch/arm/cpu/armv7/am33xx/clock_ti814x.c   |  406 
 arch/arm/include/asm/arch-am33xx/clock.h   |2 +-
 arch/arm/include/asm/arch-am33xx/clocks_am33xx.h   |   33 +-
 5 files changed, 443 insertions(+), 35 deletions(-)
 rename arch/arm/cpu/armv7/am33xx/{clock.c = clock_am33xx.c} (91%)
 create mode 100644 arch/arm/cpu/armv7/am33xx/clock_ti814x.c

diff --git a/arch/arm/cpu/armv7/am33xx/Makefile 
b/arch/arm/cpu/armv7/am33xx/Makefile
index 70c443e..c97e30d 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -16,7 +16,8 @@ include $(TOPDIR)/config.mk
 
 LIB= $(obj)lib$(SOC).o
 
-COBJS  += clock.o
+COBJS-$(CONFIG_AM33XX) += clock_am33xx.o
+COBJS-$(CONFIG_TI814X) += clock_ti814x.o
 COBJS  += sys_info.o
 COBJS  += mem.o
 COBJS  += ddr.o
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c 
b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
similarity index 91%
rename from arch/arm/cpu/armv7/am33xx/clock.c
rename to arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index d7d98d1..65cb9f8 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -1,9 +1,9 @@
 /*
- * clock.c
+ * clock_am33xx.c
  *
  * clocks for AM33XX based boards
  *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -42,6 +42,36 @@
 #define CPGMAC0_IDLE   0x3
 #define DPLL_CLKDCOLDO_GATE_CTRL0x300
 
+#define OSC(V_OSCK/100)
+
+/* MAIN PLL Fdll = 550 MHZ, */
+#define MPUPLL_M   550
+#define MPUPLL_N   (OSC-1)
+#define MPUPLL_M2  1
+
+/* Core PLL Fdll = 1 GHZ, */
+#define COREPLL_M  1000
+#define COREPLL_N  (OSC-1)
+
+#define COREPLL_M4 10  /* CORE_CLKOUTM4 = 200 MHZ */
+#define COREPLL_M5 8   /* CORE_CLKOUTM5 = 250 MHZ */
+#define COREPLL_M6 4   /* CORE_CLKOUTM6 = 500 MHZ */
+
+/*
+ * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
+ * frequency needs to be set to 960 MHZ. Hence,
+ * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
+ */
+#define PERPLL_M   960
+#define PERPLL_N   (OSC-1)
+#define PERPLL_M2  5
+
+/* DDR Freq is 266 MHZ for now */
+/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) 
*/
+#define DDRPLL_M   266
+#define DDRPLL_N   (OSC-1)
+#define DDRPLL_M2  1
+
 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c 
b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
new file mode 100644
index 000..cb4210f
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -0,0 +1,406 @@
+/*
+ * clock_ti814x.c
+ *
+ * Clocks for TI814X based boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include asm/arch/cpu.h
+#include asm/arch/clock.h
+#include asm/arch/hardware.h
+#include asm/io.h
+
+/* PRCM */
+#define PRCM_MOD_EN0x2
+
+/* CLK_SRC */
+#define OSC_SRC0   0
+#define OSC_SRC1   1
+
+#define L3_OSC_SRC OSC_SRC0
+
+#define OSC_0_FREQ 20
+
+#define DCO_HS2_MIN500
+#define DCO_HS2_MAX1000
+#define DCO_HS1_MIN1000
+#define DCO_HS1_MAX2000
+
+#define SELFREQDCO_HS2 0x0801
+#define SELFREQDCO_HS1 0x1001
+
+#define MPU_N  0x1
+#define MPU_M  0x3C
+#define MPU_M2

[U-Boot] [PATCH v2 1/9] am33xx: convert defines from am33xx-specific to generic names

[Matt Porter]

Eliminate AM33xx specific names to prepare for TI814x support
within AM33xx-land.

Signed-off-by: Matt Porter mpor...@ti.com
Reviewed-by: Tom Rini tr...@ti.com

---
v2: no changes
---
 arch/arm/cpu/armv7/am33xx/board.c   |4 ++--
 arch/arm/include/asm/arch-am33xx/hardware.h |   10 +-
 board/ti/am335x/board.c |6 +++---
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/board.c 
b/arch/arm/cpu/armv7/am33xx/board.c
index ab31326..b186b32 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -141,11 +141,11 @@ int arch_misc_init(void)
 {
 #ifdef CONFIG_AM335X_USB0
musb_register(otg0_plat, otg0_board_data,
-   (void *)AM335X_USB0_OTG_BASE);
+   (void *)USB0_OTG_BASE);
 #endif
 #ifdef CONFIG_AM335X_USB1
musb_register(otg1_plat, otg1_board_data,
-   (void *)AM335X_USB1_OTG_BASE);
+   (void *)USB1_OTG_BASE);
 #endif
return 0;
 }
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h 
b/arch/arm/include/asm/arch-am33xx/hardware.h
index 6dd3296..7016e25 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -84,14 +84,14 @@
 #define GPMC_BASE  0x5000
 
 /* CPSW Config space */
-#define AM335X_CPSW_BASE   0x4A10
-#define AM335X_CPSW_MDIO_BASE  0x4A101000
+#define CPSW_BASE  0x4A10
+#define CPSW_MDIO_BASE 0x4A101000
 
 /* RTC base address */
-#define AM335X_RTC_BASE0x44E3E000
+#define RTC_BASE   0x44E3E000
 
 /* OTG */
-#define AM335X_USB0_OTG_BASE   0x47401000
-#define AM335X_USB1_OTG_BASE   0x47401800
+#define USB0_OTG_BASE  0x47401000
+#define USB1_OTG_BASE  0x47401800
 
 #endif /* __AM33XX_HARDWARE_H */
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 48e6896..0948889 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -134,7 +134,7 @@ static int read_eeprom(void)
 
 static void rtc32k_enable(void)
 {
-   struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
+   struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
 
/*
 * Unlock the RTC's registers.  For more details please see the
@@ -411,8 +411,8 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 };
 
 static struct cpsw_platform_data cpsw_data = {
-   .mdio_base  = AM335X_CPSW_MDIO_BASE,
-   .cpsw_base  = AM335X_CPSW_BASE,
+   .mdio_base  = CPSW_MDIO_BASE,
+   .cpsw_base  = CPSW_BASE,
.mdio_div   = 0xff,
.channels   = 8,
.cpdma_reg_ofs  = 0x800,
-- 
1.7.9.5

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[U-Boot] [PATCH v2 0/9] Add TI814x EVM Support

[Matt Porter]

This series adds support for the PG1.0 TI814x EVM board. TI814x
fits into the existing AM33XX SoC support with some refactoring
of the AM33XX-specific emif4, clock, and mux code.

It has been tested booting up a Linux kernel and regression tested
on BeagleBone and EVM-SK AM33XX boards.

Changes since v1:
- Fix warnings in ddr.c
- Split hardware.h - hardware_am33xx.h/ti814x.h
- Remove unused dmtimer support
- Add register structs bit definitions
- Rename soc-specific clock files for consistency
- Move soc-specific defs only used in one place to clock_*.c
- fix copyright dates and filenames in headers
- remove clocks_*.h and go back to clock.h
- Rename mux includes for consistency
- Correct mmc reference clock for ti814x
- Squash MAINTAINERS and build bits to board support commit
- Config fixes (copyright, mtest, findfdt, fs options, cleanups)
- Fix wdtimer warning

Matt Porter (9):
  am33xx: convert defines from am33xx-specific to generic names
  am33xx: refactor emif4/ddr to support multiple EMIF instances
  am33xx: refactor am33xx clocks and add ti814x support
  am33xx: refactor am33xx mux support and add ti814x support
  am33xx: add ti814x specific register definitions
  am33xx: add dmm support to emif4 library
  am33xx: support ti814x mmc reference clock
  ns16550: enable quirks for ti814x
  ti814x_evm: add ti814x evm board support

 MAINTAINERS|4 +
 Makefile   |2 +-
 arch/arm/cpu/armv7/Makefile|2 +-
 arch/arm/cpu/armv7/am33xx/Makefile |3 +-
 arch/arm/cpu/armv7/am33xx/board.c  |4 +-
 .../cpu/armv7/am33xx/{clock.c = clock_am33xx.c}   |   34 +-
 arch/arm/cpu/armv7/am33xx/clock_ti814x.c   |  408 
 arch/arm/cpu/armv7/am33xx/ddr.c|   99 +++--
 arch/arm/cpu/armv7/am33xx/emif4.c  |   55 ++-
 arch/arm/cpu/armv7/am33xx/sys_info.c   |3 +
 arch/arm/cpu/armv7/omap-common/Makefile|2 +-
 arch/arm/include/asm/arch-am33xx/clock.h   |2 +-
 arch/arm/include/asm/arch-am33xx/clocks_am33xx.h   |   33 +-
 arch/arm/include/asm/arch-am33xx/cpu.h |   11 +-
 arch/arm/include/asm/arch-am33xx/ddr_defs.h|   57 ++-
 arch/arm/include/asm/arch-am33xx/hardware.h|   40 +-
 arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |   54 +++
 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |   53 +++
 arch/arm/include/asm/arch-am33xx/mmc_host_def.h|4 +
 arch/arm/include/asm/arch-am33xx/mux.h |  235 +--
 arch/arm/include/asm/arch-am33xx/mux_am33xx.h  |  247 
 arch/arm/include/asm/arch-am33xx/mux_ti814x.h  |  311 +++
 arch/arm/include/asm/arch-am33xx/omap.h|7 +
 arch/arm/include/asm/arch-am33xx/spl.h |5 +
 board/ti/am335x/board.c|   12 +-
 board/ti/ti814x/Makefile   |   46 +++
 board/ti/ti814x/evm.c  |  198 ++
 board/ti/ti814x/evm.h  |7 +
 board/ti/ti814x/mux.c  |   51 +++
 boards.cfg |1 +
 drivers/serial/ns16550.c   |5 +-
 include/configs/ti814x_evm.h   |  223 +++
 spl/Makefile   |2 +-
 33 files changed, 1852 insertions(+), 368 deletions(-)
 rename arch/arm/cpu/armv7/am33xx/{clock.c = clock_am33xx.c} (91%)
 create mode 100644 arch/arm/cpu/armv7/am33xx/clock_ti814x.c
 create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/mux_am33xx.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/mux_ti814x.h
 create mode 100644 board/ti/ti814x/Makefile
 create mode 100644 board/ti/ti814x/evm.c
 create mode 100644 board/ti/ti814x/evm.h
 create mode 100644 board/ti/ti814x/mux.c
 create mode 100644 include/configs/ti814x_evm.h

-- 
1.7.9.5

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[U-Boot] [PATCH v2 3/9] am33xx: refactor am33xx clocks and add ti814x support

[Matt Porter]

Split clock.c for am335x and ti814x and add ti814x specific
clock support.

Signed-off-by: Matt Porter mpor...@ti.com

---
v2:
* remove unused dmtimer support
* add register structs bit definitions
* rename soc-specific clock files for consistency
* move ti814x specific defs to clock_ti814x.c
* move am335x specific defs to clock_am335x.c
* fix copyright date
* remove clocks_*.h and go back to clock.h
---
 arch/arm/cpu/armv7/am33xx/Makefile |3 +-
 .../cpu/armv7/am33xx/{clock.c = clock_am33xx.c}   |   34 +-
 arch/arm/cpu/armv7/am33xx/clock_ti814x.c   |  408 
 arch/arm/include/asm/arch-am33xx/clock.h   |2 +-
 arch/arm/include/asm/arch-am33xx/clocks_am33xx.h   |   33 +-
 5 files changed, 445 insertions(+), 35 deletions(-)
 rename arch/arm/cpu/armv7/am33xx/{clock.c = clock_am33xx.c} (91%)
 create mode 100644 arch/arm/cpu/armv7/am33xx/clock_ti814x.c

diff --git a/arch/arm/cpu/armv7/am33xx/Makefile 
b/arch/arm/cpu/armv7/am33xx/Makefile
index 70c443e..c97e30d 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -16,7 +16,8 @@ include $(TOPDIR)/config.mk
 
 LIB= $(obj)lib$(SOC).o
 
-COBJS  += clock.o
+COBJS-$(CONFIG_AM33XX) += clock_am33xx.o
+COBJS-$(CONFIG_TI814X) += clock_ti814x.o
 COBJS  += sys_info.o
 COBJS  += mem.o
 COBJS  += ddr.o
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c 
b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
similarity index 91%
rename from arch/arm/cpu/armv7/am33xx/clock.c
rename to arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index d7d98d1..65cb9f8 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -1,9 +1,9 @@
 /*
- * clock.c
+ * clock_am33xx.c
  *
  * clocks for AM33XX based boards
  *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -42,6 +42,36 @@
 #define CPGMAC0_IDLE   0x3
 #define DPLL_CLKDCOLDO_GATE_CTRL0x300
 
+#define OSC(V_OSCK/100)
+
+/* MAIN PLL Fdll = 550 MHZ, */
+#define MPUPLL_M   550
+#define MPUPLL_N   (OSC-1)
+#define MPUPLL_M2  1
+
+/* Core PLL Fdll = 1 GHZ, */
+#define COREPLL_M  1000
+#define COREPLL_N  (OSC-1)
+
+#define COREPLL_M4 10  /* CORE_CLKOUTM4 = 200 MHZ */
+#define COREPLL_M5 8   /* CORE_CLKOUTM5 = 250 MHZ */
+#define COREPLL_M6 4   /* CORE_CLKOUTM6 = 500 MHZ */
+
+/*
+ * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
+ * frequency needs to be set to 960 MHZ. Hence,
+ * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
+ */
+#define PERPLL_M   960
+#define PERPLL_N   (OSC-1)
+#define PERPLL_M2  5
+
+/* DDR Freq is 266 MHZ for now */
+/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) 
*/
+#define DDRPLL_M   266
+#define DDRPLL_N   (OSC-1)
+#define DDRPLL_M2  1
+
 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c 
b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
new file mode 100644
index 000..a85241a
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -0,0 +1,408 @@
+/*
+ * clock_ti814x.c
+ *
+ * Clocks for TI814X based boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include asm/arch/cpu.h
+#include asm/arch/clock.h
+#include asm/arch/hardware.h
+#include asm/io.h
+
+/* PRCM */
+#define PRCM_MOD_EN0x2
+
+/* CLK_SRC */
+#define OSC_SRC0   0
+#define OSC_SRC1   1
+
+#define L3_OSC_SRC OSC_SRC0
+
+#define OSC_0_FREQ 20
+
+#define DCO_HS2_MIN500
+#define DCO_HS2_MAX1000
+#define DCO_HS1_MIN1000
+#define DCO_HS1_MAX2000
+
+#define SELFREQDCO_HS2 0x0801
+#define SELFREQDCO_HS1 0x1001
+
+#define MPU_N  0x1
+#define MPU_M  0x3C
+#define MPU_M2 1
+#define MPU_CLKCTRL0x1
+
+#define L3_N   19
+#define L3_M

[U-Boot] [PATCH v2 4/9] am33xx: refactor am33xx mux support and add ti814x support

[Matt Porter]

AM33XX and TI814X have a similar mux though the pinmux register
layout and address space differ. Add a separate ti814x mux include
to support the TI814X-specific differences.

Signed-off-by: Matt Porter mpor...@ti.com
Reviewed-by: Tom Rini tr...@ti.com
Acked-by: Peter Korsgaard jac...@sunsite.dk

---
v2:
* fixed copyright date and file header
* rename split mux includes for consistency
---
 arch/arm/include/asm/arch-am33xx/mux.h|  235 +--
 arch/arm/include/asm/arch-am33xx/mux_am33xx.h |  247 
 arch/arm/include/asm/arch-am33xx/mux_ti814x.h |  311 +
 3 files changed, 566 insertions(+), 227 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-am33xx/mux_am33xx.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/mux_ti814x.h

diff --git a/arch/arm/include/asm/arch-am33xx/mux.h 
b/arch/arm/include/asm/arch-am33xx/mux.h
index 460ac1c..1c6b65f 100644
--- a/arch/arm/include/asm/arch-am33xx/mux.h
+++ b/arch/arm/include/asm/arch-am33xx/mux.h
@@ -1,7 +1,7 @@
 /*
  * mux.h
  *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -19,234 +19,15 @@
 #include common.h
 #include asm/io.h
 
-#define MUX_CFG(value, offset) \
-   __raw_writel(value, (CTRL_BASE + offset));
-
-/* PAD Control Fields */
-#define SLEWCTRL   (0x1  6)
-#define RXACTIVE   (0x1  5)
-#define PULLDOWN_EN(0x0  4) /* Pull Down Selection */
-#define PULLUP_EN  (0x1  4) /* Pull Up Selection */
-#define PULLUDEN   (0x0  3) /* Pull up enabled */
-#define PULLUDDIS  (0x1  3) /* Pull up disabled */
-#define MODE(val)  val /* used for Readability */
-
-/*
- * PAD CONTROL OFFSETS
- * Field names corresponds to the pad signal name
- */
-struct pad_signals {
-   int gpmc_ad0;
-   int gpmc_ad1;
-   int gpmc_ad2;
-   int gpmc_ad3;
-   int gpmc_ad4;
-   int gpmc_ad5;
-   int gpmc_ad6;
-   int gpmc_ad7;
-   int gpmc_ad8;
-   int gpmc_ad9;
-   int gpmc_ad10;
-   int gpmc_ad11;
-   int gpmc_ad12;
-   int gpmc_ad13;
-   int gpmc_ad14;
-   int gpmc_ad15;
-   int gpmc_a0;
-   int gpmc_a1;
-   int gpmc_a2;
-   int gpmc_a3;
-   int gpmc_a4;
-   int gpmc_a5;
-   int gpmc_a6;
-   int gpmc_a7;
-   int gpmc_a8;
-   int gpmc_a9;
-   int gpmc_a10;
-   int gpmc_a11;
-   int gpmc_wait0;
-   int gpmc_wpn;
-   int gpmc_be1n;
-   int gpmc_csn0;
-   int gpmc_csn1;
-   int gpmc_csn2;
-   int gpmc_csn3;
-   int gpmc_clk;
-   int gpmc_advn_ale;
-   int gpmc_oen_ren;
-   int gpmc_wen;
-   int gpmc_be0n_cle;
-   int lcd_data0;
-   int lcd_data1;
-   int lcd_data2;
-   int lcd_data3;
-   int lcd_data4;
-   int lcd_data5;
-   int lcd_data6;
-   int lcd_data7;
-   int lcd_data8;
-   int lcd_data9;
-   int lcd_data10;
-   int lcd_data11;
-   int lcd_data12;
-   int lcd_data13;
-   int lcd_data14;
-   int lcd_data15;
-   int lcd_vsync;
-   int lcd_hsync;
-   int lcd_pclk;
-   int lcd_ac_bias_en;
-   int mmc0_dat3;
-   int mmc0_dat2;
-   int mmc0_dat1;
-   int mmc0_dat0;
-   int mmc0_clk;
-   int mmc0_cmd;
-   int mii1_col;
-   int mii1_crs;
-   int mii1_rxerr;
-   int mii1_txen;
-   int mii1_rxdv;
-   int mii1_txd3;
-   int mii1_txd2;
-   int mii1_txd1;
-   int mii1_txd0;
-   int mii1_txclk;
-   int mii1_rxclk;
-   int mii1_rxd3;
-   int mii1_rxd2;
-   int mii1_rxd1;
-   int mii1_rxd0;
-   int rmii1_refclk;
-   int mdio_data;
-   int mdio_clk;
-   int spi0_sclk;
-   int spi0_d0;
-   int spi0_d1;
-   int spi0_cs0;
-   int spi0_cs1;
-   int ecap0_in_pwm0_out;
-   int uart0_ctsn;
-   int uart0_rtsn;
-   int uart0_rxd;
-   int uart0_txd;
-   int uart1_ctsn;
-   int uart1_rtsn;
-   int uart1_rxd;
-   int uart1_txd;
-   int i2c0_sda;
-   int i2c0_scl;
-   int mcasp0_aclkx;
-   int mcasp0_fsx;
-   int mcasp0_axr0;
-   int mcasp0_ahclkr;
-   int mcasp0_aclkr;
-   int mcasp0_fsr;
-   int mcasp0_axr1;
-   int mcasp0_ahclkx;
-   int xdma_event_intr0;
-   int xdma_event_intr1;
-   int nresetin_out;
-   int porz;
-   int nnmi;
-   int osc0_in;
-   int osc0_out;
-   int rsvd1;
-   int tms;
-   int tdi;
-   int tdo;
-   int tck;
-   int ntrst;
-   int emu0;
-   int emu1;
-   int osc1_in;
-   int osc1_out;
-   int pmic_power_en;
-   int rtc_porz;
-   int rsvd2;
-   int ext_wakeup;
-   int enz_kaldo_1p8v;
-   int usb0_dm;
-   int

[U-Boot] [PATCH v2 2/9] am33xx: refactor emif4/ddr to support multiple EMIF instances

[Matt Porter]

The AM33xx emif4/ddr support closely matches what is need to support
TI814x except that TI814x has two EMIF instances. Refactor all the
emif4 helper calls and the config_ddr() init function to use an
additional instance number argument.

Signed-off-by: Matt Porter mpor...@ti.com
Reviewed-by: Tom Rini tr...@ti.com

---
v2:
* fix bad cast causing ddr.c warnings
* Split hardware.h - hardware_am33xx.h/ti814x.h
---
 arch/arm/cpu/armv7/am33xx/ddr.c|   99 
 arch/arm/cpu/armv7/am33xx/emif4.c  |   38 
 arch/arm/include/asm/arch-am33xx/ddr_defs.h|   52 --
 arch/arm/include/asm/arch-am33xx/hardware.h|   13 ++-
 arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |   30 ++
 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |   30 ++
 board/ti/am335x/board.c|6 +-
 7 files changed, 197 insertions(+), 71 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index fd9fc4a..4b771c8 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -24,15 +24,20 @@ http://www.ti.com/
 /**
  * Base address for EMIF instances
  */
-static struct emif_reg_struct *emif_reg = {
-   (struct emif_reg_struct *)EMIF4_0_CFG_BASE};
+static struct emif_reg_struct *emif_reg[2] = {
+   (struct emif_reg_struct *)EMIF4_0_CFG_BASE,
+   (struct emif_reg_struct *)EMIF4_1_CFG_BASE};
 
 /**
- * Base address for DDR instance
+ * Base addresses for DDR PHY cmd/data regs
  */
-static struct ddr_regs *ddr_reg[2] = {
-   (struct ddr_regs *)DDR_PHY_BASE_ADDR,
-   (struct ddr_regs *)DDR_PHY_BASE_ADDR2};
+static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
+   (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
+   (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
+
+static struct ddr_data_regs *ddr_data_reg[2] = {
+   (struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
+   (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
 
 /**
  * Base address for ddr io control instances
@@ -43,70 +48,84 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
 /**
  * Configure SDRAM
  */
-void config_sdram(const struct emif_regs *regs)
+void config_sdram(const struct emif_regs *regs, int nr)
 {
-   writel(regs-ref_ctrl, emif_reg-emif_sdram_ref_ctrl);
-   writel(regs-ref_ctrl, emif_reg-emif_sdram_ref_ctrl_shdw);
+   writel(regs-ref_ctrl, emif_reg[nr]-emif_sdram_ref_ctrl);
+   writel(regs-ref_ctrl, emif_reg[nr]-emif_sdram_ref_ctrl_shdw);
if (regs-zq_config){
-   writel(regs-zq_config, emif_reg-emif_zq_config);
+   writel(regs-zq_config, emif_reg[nr]-emif_zq_config);
writel(regs-sdram_config, cstat-secure_emif_sdram_config);
}
-   writel(regs-sdram_config, emif_reg-emif_sdram_config);
+   writel(regs-sdram_config, emif_reg[nr]-emif_sdram_config);
 }
 
 /**
  * Set SDRAM timings
  */
-void set_sdram_timings(const struct emif_regs *regs)
+void set_sdram_timings(const struct emif_regs *regs, int nr)
 {
-   writel(regs-sdram_tim1, emif_reg-emif_sdram_tim_1);
-   writel(regs-sdram_tim1, emif_reg-emif_sdram_tim_1_shdw);
-   writel(regs-sdram_tim2, emif_reg-emif_sdram_tim_2);
-   writel(regs-sdram_tim2, emif_reg-emif_sdram_tim_2_shdw);
-   writel(regs-sdram_tim3, emif_reg-emif_sdram_tim_3);
-   writel(regs-sdram_tim3, emif_reg-emif_sdram_tim_3_shdw);
+   writel(regs-sdram_tim1, emif_reg[nr]-emif_sdram_tim_1);
+   writel(regs-sdram_tim1, emif_reg[nr]-emif_sdram_tim_1_shdw);
+   writel(regs-sdram_tim2, emif_reg[nr]-emif_sdram_tim_2);
+   writel(regs-sdram_tim2, emif_reg[nr]-emif_sdram_tim_2_shdw);
+   writel(regs-sdram_tim3, emif_reg[nr]-emif_sdram_tim_3);
+   writel(regs-sdram_tim3, emif_reg[nr]-emif_sdram_tim_3_shdw);
 }
 
 /**
  * Configure DDR PHY
  */
-void config_ddr_phy(const struct emif_regs *regs)
+void config_ddr_phy(const struct emif_regs *regs, int nr)
 {
-   writel(regs-emif_ddr_phy_ctlr_1, emif_reg-emif_ddr_phy_ctrl_1);
-   writel(regs-emif_ddr_phy_ctlr_1, emif_reg-emif_ddr_phy_ctrl_1_shdw);
+   writel(regs-emif_ddr_phy_ctlr_1,
+   emif_reg[nr]-emif_ddr_phy_ctrl_1);
+   writel(regs-emif_ddr_phy_ctlr_1,
+   emif_reg[nr]-emif_ddr_phy_ctrl_1_shdw);
 }
 
 /**
  * Configure DDR CMD control registers
  */
-void config_cmd_ctrl(const struct cmd_control *cmd)
+void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
 {
-   writel(cmd-cmd0csratio, ddr_reg[0]-cm0csratio);
-   writel(cmd-cmd0dldiff, ddr_reg[0]-cm0dldiff);
-   writel(cmd-cmd0iclkout

[U-Boot] [PATCH v2 5/9] am33xx: add ti814x specific register definitions

[Matt Porter]

Support the ti814x specific register definitions within
arch-am33xx.

Signed-off-by: Matt Porter mpor...@ti.com
Reviewed-by: Tom Rini tr...@ti.com

---
v2: Update for hardware.h split
---
 arch/arm/cpu/armv7/am33xx/sys_info.c   |3 +++
 arch/arm/include/asm/arch-am33xx/cpu.h |   11 +
 arch/arm/include/asm/arch-am33xx/hardware.h|   21 -
 arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |   24 
 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |   23 +++
 arch/arm/include/asm/arch-am33xx/omap.h|7 ++
 arch/arm/include/asm/arch-am33xx/spl.h |5 
 7 files changed, 73 insertions(+), 21 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c 
b/arch/arm/cpu/armv7/am33xx/sys_info.c
index 507b618..402127c 100644
--- a/arch/arm/cpu/armv7/am33xx/sys_info.c
+++ b/arch/arm/cpu/armv7/am33xx/sys_info.c
@@ -98,6 +98,9 @@ int print_cpuinfo(void)
case AM335X:
cpu_s = AM335X;
break;
+   case TI81XX:
+   cpu_s = TI81XX;
+   break;
default:
cpu_s = Unknown cpu type;
break;
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h 
b/arch/arm/include/asm/arch-am33xx/cpu.h
index 16e8a80..3d3a7c8 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -42,9 +42,10 @@
 #define HS_DEVICE  0x2
 #define GP_DEVICE  0x3
 
-/* cpu-id for AM33XX family */
+/* cpu-id for AM33XX and TI81XX family */
 #define AM335X 0xB944
-#define DEVICE_ID  0x44E10600
+#define TI81XX 0xB81E
+#define DEVICE_ID  (CTRL_BASE + 0x0600)
 
 /* This gives the status of the boot mode pins on the evm */
 #define SYSBOOT_MASK   (BIT(0) | BIT(1) | BIT(2)\
@@ -52,9 +53,11 @@
 
 /* Reset control */
 #ifdef CONFIG_AM33XX
-#define PRM_RSTCTRL0x44E00F00
-#define PRM_RSTST  0x44E00F08
+#define PRM_RSTCTRL(PRCM_BASE + 0x0F00)
+#elif defined(CONFIG_TI814X)
+#define PRM_RSTCTRL(PRCM_BASE + 0x00A0)
 #endif
+#define PRM_RSTST  (PRM_RSTCTRL + 8)
 #define PRM_RSTCTRL_RESET  0x01
 #define PRM_RSTST_WARM_RESET_MASK  0x232
 
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h 
b/arch/arm/include/asm/arch-am33xx/hardware.h
index 24a9b8d..5a27f9c 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -19,6 +19,7 @@
 #ifndef __AM33XX_HARDWARE_H
 #define __AM33XX_HARDWARE_H
 
+#include config.h
 #include asm/arch/omap.h
 #ifdef CONFIG_AM33XX
 #include asm/arch/hardware_am33xx.h
@@ -26,8 +27,9 @@
 #include asm/arch/hardware_ti814x.h
 #endif
 
-/* Module base addresses */
-#define UART0_BASE 0x44E09000
+/*
+ * Common hardware definitions
+ */
 
 /* DM Timer base addresses */
 #define DM_TIMER0_BASE 0x4802C000
@@ -42,21 +44,10 @@
 /* GPIO Base address */
 #define GPIO0_BASE 0x48032000
 #define GPIO1_BASE 0x4804C000
-#define GPIO2_BASE 0x481AC000
 
 /* BCH Error Location Module */
 #define ELM_BASE   0x4808
 
-/* Watchdog Timer */
-#define WDT_BASE   0x44E35000
-
-/* Control Module Base Address */
-#define CTRL_BASE  0x44E1
-#define CTRL_DEVICE_BASE   0x44E10600
-
-/* PRCM Base Address */
-#define PRCM_BASE  0x44E0
-
 /* EMIF Base address */
 #define EMIF4_0_CFG_BASE   0x4C00
 #define EMIF4_1_CFG_BASE   0x4D00
@@ -90,10 +81,6 @@
 
 /* CPSW Config space */
 #define CPSW_BASE  0x4A10
-#define CPSW_MDIO_BASE 0x4A101000
-
-/* RTC base address */
-#define RTC_BASE   0x44E3E000
 
 /* OTG */
 #define USB0_OTG_BASE  0x47401000
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h 
b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
index 7a4070c..fa02f19 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
@@ -19,6 +19,24 @@
 #ifndef __AM33XX_HARDWARE_AM33XX_H
 #define __AM33XX_HARDWARE_AM33XX_H
 
+/* Module base addresses */
+
+/* UART Base Address */
+#define UART0_BASE 0x44E09000
+
+/* GPIO Base address */
+#define GPIO2_BASE 0x481AC000
+
+/* Watchdog Timer */
+#define WDT_BASE   0x44E35000
+
+/* Control Module Base Address */
+#define CTRL_BASE  0x44E1
+#define CTRL_DEVICE_BASE   0x44E10600
+
+/* PRCM Base Address */
+#define PRCM_BASE  0x44E0
+
 /* VTP Base address */
 #define VTP0_CTRL_ADDR

[U-Boot] [PATCH v2 6/9] am33xx: add dmm support to emif4 library

[Matt Porter]

Adds a config_dmm() routine to support TI814X DMM configuration.

Signed-off-by: Matt Porter mpor...@ti.com
Reviewed-by: Tom Rini tr...@ti.com

---
v2: no changes
---
 arch/arm/cpu/armv7/am33xx/emif4.c   |   17 +
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |5 +
 2 files changed, 22 insertions(+)

diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c 
b/arch/arm/cpu/armv7/am33xx/emif4.c
index 0c617fa..27547be 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -44,11 +44,28 @@ void dram_init_banksize(void)
 
 
 #ifdef CONFIG_SPL_BUILD
+static struct dmm_lisa_map_regs *hw_lisa_map_regs =
+   (struct dmm_lisa_map_regs *)DMM_BASE;
 static struct vtp_reg *vtpreg[2] = {
(struct vtp_reg *)VTP0_CTRL_ADDR,
(struct vtp_reg *)VTP1_CTRL_ADDR};
 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
 
+void config_dmm(const struct dmm_lisa_map_regs *regs)
+{
+   enable_dmm_clocks();
+
+   writel(0, hw_lisa_map_regs-dmm_lisa_map_3);
+   writel(0, hw_lisa_map_regs-dmm_lisa_map_2);
+   writel(0, hw_lisa_map_regs-dmm_lisa_map_1);
+   writel(0, hw_lisa_map_regs-dmm_lisa_map_0);
+
+   writel(regs-dmm_lisa_map_3, hw_lisa_map_regs-dmm_lisa_map_3);
+   writel(regs-dmm_lisa_map_2, hw_lisa_map_regs-dmm_lisa_map_2);
+   writel(regs-dmm_lisa_map_1, hw_lisa_map_regs-dmm_lisa_map_1);
+   writel(regs-dmm_lisa_map_0, hw_lisa_map_regs-dmm_lisa_map_0);
+}
+
 static void config_vtp(int nr)
 {
writel(readl(vtpreg[nr]-vtp0ctrlreg) | VTP_CTRL_ENABLE,
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h 
b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 1cbadff..15ca4c1 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -100,6 +100,11 @@
 #define MT41J512M8RH125_IOCTRL_VALUE   0x18B
 
 /**
+ * Configure DMM
+ */
+void config_dmm(const struct dmm_lisa_map_regs *regs);
+
+/**
  * Configure SDRAM
  */
 void config_sdram(const struct emif_regs *regs, int nr);
-- 
1.7.9.5

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[U-Boot] [PATCH v2 7/9] am33xx: support ti814x mmc reference clock

[Matt Porter]

TI814x has a 192MHz hsmmc reference clock. Select that clock rate
when building for TI814x.

Signed-off-by: Matt Porter mpor...@ti.com

---
v2: no changes, new to the series
---
 arch/arm/include/asm/arch-am33xx/mmc_host_def.h |4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h 
b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
index 1f597c0..e0a3b8b 100644
--- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -153,7 +153,11 @@ typedef struct hsmmc {
 #define MMC_CMD0   (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
 
 /* Clock Configurations and Macros */
+#ifdef CONFIG_AM33XX
 #define MMC_CLOCK_REFERENCE96 /* MHz */
+#elif defined(CONFIG_TI814X)
+#define MMC_CLOCK_REFERENCE192 /* MHz */
+#endif
 
 #define mmc_reg_out(addr, mask, val)\
writel((readl(addr)  (~(mask))) | ((val)  (mask)), (addr))
-- 
1.7.9.5

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[U-Boot] [PATCH v2 8/9] ns16550: enable quirks for ti814x

[Matt Porter]

TI814X requires the same quirks as AM33XX to be enabled.

Signed-off-by: Matt Porter mpor...@ti.com
Reviewed-by: Tom Rini tr...@ti.com

---
v2: no changes
---
 drivers/serial/ns16550.c |5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 87a0917..02bc85b 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -43,7 +43,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
 
serial_out(CONFIG_SYS_NS16550_IER, com_port-ier);
 #if (defined(CONFIG_OMAP)  !defined(CONFIG_OMAP3_ZOOM2)) || \
-   defined(CONFIG_AM33XX)
+   defined(CONFIG_AM33XX) || defined(CONFIG_TI814X)
serial_out(0x7, com_port-mdr1);   /* mode select reset TL16C750*/
 #endif
serial_out(UART_LCR_BKSE | UART_LCRVAL, (ulong)com_port-lcr);
@@ -57,7 +57,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
serial_out((baud_divisor  8)  0xff, com_port-dlm);
serial_out(UART_LCRVAL, com_port-lcr);
 #if (defined(CONFIG_OMAP)  !defined(CONFIG_OMAP3_ZOOM2)) || \
-   defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX)
+   defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \
+   defined(CONFIG_TI814X)
 
 #if defined(CONFIG_APTIX)
/* /13 mode so Aptix 6MHz can hit 115200 */
-- 
1.7.9.5

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[U-Boot] [PATCH v2 9/9] ti814x_evm: add ti814x evm board support

[Matt Porter]

Add TI814X EVM board directory, config file, and MAINTAINERS
entry. Enable build.

Signed-off-by: Matt Porter mpor...@ti.com
Reviewed-by: Tom Rini tr...@ti.com

---
v2:
* squash MAINTAINERS and Makefile commits here
* config file fixes (copyright, mtest, findfdt, fs options, cleanups)
* move wdtimer variable under SPL build
---
 MAINTAINERS |4 +
 Makefile|2 +-
 arch/arm/cpu/armv7/Makefile |2 +-
 arch/arm/cpu/armv7/omap-common/Makefile |2 +-
 board/ti/ti814x/Makefile|   46 +++
 board/ti/ti814x/evm.c   |  198 +++
 board/ti/ti814x/evm.h   |7 +
 board/ti/ti814x/mux.c   |   51 +++
 boards.cfg  |1 +
 include/configs/ti814x_evm.h|  223 +++
 spl/Makefile|2 +-
 11 files changed, 534 insertions(+), 4 deletions(-)
 create mode 100644 board/ti/ti814x/Makefile
 create mode 100644 board/ti/ti814x/evm.c
 create mode 100644 board/ti/ti814x/evm.h
 create mode 100644 board/ti/ti814x/mux.c
 create mode 100644 include/configs/ti814x_evm.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 45e2dd4..6b2202c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -833,6 +833,10 @@ Stelian Pop stel...@popies.net
at91sam9263ek   ARM926EJS (AT91SAM9263 SoC)
at91sam9rlekARM926EJS (AT91SAM9RL SoC)
 
+Matt Porter mpor...@ti.com
+
+   ti814x_evm  ARM ARMV7 (TI814x Soc)
+
 Dave Purdy david.c.pu...@gmail.com
 
pogo_e02ARM926EJS (Kirkwood SoC)
diff --git a/Makefile b/Makefile
index fc18dd4..7273fa4 100644
--- a/Makefile
+++ b/Makefile
@@ -330,7 +330,7 @@ LIBS-y += api/libapi.o
 LIBS-y += post/libpost.o
 LIBS-y += test/libtest.o
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+ifneq 
($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
 
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index ee8c2b3..c961247 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,7 @@ COBJS += cache_v7.o
 COBJS  += cpu.o
 COBJS  += syslib.o
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA),)
+ifneq 
($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_TI814X),)
 SOBJS  += lowlevel_init.o
 endif
 
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile 
b/arch/arm/cpu/armv7/omap-common/Makefile
index 0efc80d..55e82ba 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -36,7 +36,7 @@ COBJS += emif-common.o
 COBJS  += vc.o
 endif
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
 COBJS  += boot-common.o
 SOBJS  += lowlevel_init.o
 endif
diff --git a/board/ti/ti814x/Makefile b/board/ti/ti814x/Makefile
new file mode 100644
index 000..09d2422
--- /dev/null
+++ b/board/ti/ti814x/Makefile
@@ -0,0 +1,46 @@
+#
+# Makefile
+#
+# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed as is WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS  := mux.o
+endif
+
+COBJS  += evm.o
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+   $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+   rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+   rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
new file mode 100644
index 000..acc18fb
--- /dev/null
+++ b/board/ti/ti814x/evm.c
@@ -0,0 +1,198 @@
+/*
+ * evm.c
+ *
+ * Board functions for TI814x EVM
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software

Re: [U-Boot] [PATCH 03/10] am33xx: refactor am33xx clocks and add ti814x support

[Matt Porter]

On Sun, Feb 17, 2013 at 09:17:01PM +0100, Peter Korsgaard wrote:
  Matt == Matt Porter mpor...@ti.com writes:
 
  Matt Split clock.c for am335x and ti814x and add the ti814x include file.
  Matt Signed-off-by: Matt Porter mpor...@ti.com
  Matt ---
  Matt  arch/arm/cpu/armv7/am33xx/Makefile   |3 +-
  Matt  arch/arm/cpu/armv7/am33xx/clock-am335x.c |  374 
 ++
  Matt  arch/arm/cpu/armv7/am33xx/clock-ti814x.c |  234 ++
  Matt  arch/arm/cpu/armv7/am33xx/clock.c|  374 
 --
  Matt  arch/arm/include/asm/arch-am33xx/clock.h |4 +
  Matt  arch/arm/include/asm/arch-am33xx/clocks_ti814x.h |  112 +++
  Matt  6 files changed, 726 insertions(+), 375 deletions(-)
  Matt  create mode 100644 arch/arm/cpu/armv7/am33xx/clock-am335x.c
  Matt  create mode 100644 arch/arm/cpu/armv7/am33xx/clock-ti814x.c
  Matt  delete mode 100644 arch/arm/cpu/armv7/am33xx/clock.c
  Matt  create mode 100644 arch/arm/include/asm/arch-am33xx/clocks_ti814x.h

Hi Peter...thanks for reviewing this.

 Do you have rename detection enabled? I would have imagined
 clock-am335x.c to show up as a copy of clock.c

On any given day I forget to format-patch with rename detection enabled.
You caught me...will be fixed in v2.

  Matt +++ b/arch/arm/cpu/armv7/am33xx/clock-am335x.c
  Matt @@ -0,0 +1,374 @@
  Matt +/*
  Matt + * clock.c
  Matt + *
  Matt + * clocks for AM33XX based boards
  Matt + *
  Matt + * Copyright (C) 2011, Texas Instruments, Incorporated - 
 http://www.ti.com/
 
 This is no longer clock.c or 2011. Care to update the header?

Ok

 
  Matt +++ b/arch/arm/cpu/armv7/am33xx/clock-ti814x.c
  Matt @@ -0,0 +1,234 @@
  Matt +/*
  Matt + * clock.c
  Matt + *
  Matt + * clocks for TI814X based boards
  Matt + *
  Matt + * Copyright (C) 2011, Texas Instruments, Incorporated - 
 http://www.ti.com/
 
 Same here.

Ok

-Matt
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Re: [U-Boot] [PATCH 04/10] am33xx: refactor am33xx mux support and add ti814x support

[Matt Porter]

On Sun, Feb 17, 2013 at 08:18:57PM +, Peter Korsgaard wrote:
  Matt == Matt Porter mpor...@ti.com writes:
 
  Matt AM33XX and TI814X have a similar mux though the pinmux register
  Matt layout and address space differ. Add a separate ti814x mux include
  Matt to support the TI814X-specific differences.
 
 Same comment about the file headers as patch 03, otherwise it looks
 good.

Will clean the headers.

-Matt

 Acked-by: Peter Korsgaard jac...@sunsite.dk
 
 -- 
 Bye, Peter Korsgaard
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Re: [U-Boot] [PATCH 05/10] am33xx: add ti814x specific register definitions

[Matt Porter]

On Mon, Feb 18, 2013 at 03:18:42PM +, Tom Rini wrote:
 On Sun, Feb 17, 2013 at 09:28:33PM +0100, Peter Korsgaard wrote:
   Matt == Matt Porter mpor...@ti.com writes:
  
   Matt Support the ti814x specific register definitions within
   Matt arch-am33xx.
  
   Matt Signed-off-by: Matt Porter mpor...@ti.com
   Matt ---
   Matt  arch/arm/cpu/armv7/am33xx/sys_info.c|3 +++
   Matt  arch/arm/include/asm/arch-am33xx/cpu.h  |   11 +
   Matt  arch/arm/include/asm/arch-am33xx/hardware.h |   32 
  +++
   Matt  arch/arm/include/asm/arch-am33xx/omap.h |7 ++
   Matt  arch/arm/include/asm/arch-am33xx/spl.h  |5 +
   Matt  5 files changed, 54 insertions(+), 4 deletions(-)
   
   Matt diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h 
  b/arch/arm/include/asm/arch-am33xx/hardware.h
   Matt index 41ab2c0..786c159 100644
   Matt --- a/arch/arm/include/asm/arch-am33xx/hardware.h
   Matt +++ b/arch/arm/include/asm/arch-am33xx/hardware.h
   Matt @@ -20,9 +20,14 @@
   Matt  #define __AM33XX_HARDWARE_H
   
   Matt  #include asm/arch/omap.h
   Matt +#include config.h
  
  Quite some of the base addresses are similar, but I wonder if it
  wouldn't be cleaner to simply have a hardware-am33xx.h /
  hardware-ti814x.h instead of all these ifdef / elif?
 
 Since I suspect the things common from ti814x and am33xx are also common
 to ti816x (which has been left as an exercise to whomever needs that
 next), I think we can re-structure this into something like that, but
 keeping the common parts within hardware.h still.

Sounds good. I'll restructure with only the common parts in hardware.h.

   Matt  /* Control Module Base Address */
   Matt +#ifdef CONFIG_AM33XX
   Matt  #define CTRL_BASE   0x44E1
   Matt  #define CTRL_DEVICE_BASE0x44E10600
   Matt +#elif defined(CONFIG_TI814X)
   Matt +#define CTRL_BASE   0x4814
   Matt +#endif
  
  No CTRL_DEVICE_BASE on ti814x?
 
 I think this is a side-effect of Matt not supporting the things attached
 to it (USB in the case of am335x).

I tried to avoid defining things I'm not yet using. For CTRL_DEVICE_BASE,
I would add it once I get to adding cpsw support as we need to read the
efused macid value from that area.

   Matt --- a/arch/arm/include/asm/arch-am33xx/spl.h
   Matt +++ b/arch/arm/include/asm/arch-am33xx/spl.h
   Matt @@ -25,8 +25,13 @@
   
   Matt  #define BOOT_DEVICE_XIP 2
   Matt  #define BOOT_DEVICE_NAND5
   Matt +#ifdef CONFIG_AM33XX
   Matt  #define BOOT_DEVICE_MMC18
   Matt  #define BOOT_DEVICE_MMC29   /* eMMC or daughter card */
   Matt +#elif defined(CONFIG_TI814X)
   Matt +#define BOOT_DEVICE_MMC19
   Matt +#define BOOT_DEVICE_MMC28   /* ROM only supports 2nd 
  instance */
  
  Argh! Couldn't we just swap the meaning of mmc1/mmc2 or would that be
  too confusing?
 
 IMHO, that will lead to further confusion down the line.  I talked with
 Matt about this before and well, it's funky.

This is definitely a quirky area wrt TI814x. AFAIK it's the only
OMAP-ish part where the ROM only allows boot from a single MMC instance.
Further, that single MMC instance is actually the 2nd one as noted in
the comment. This means to keep all the existing SPL mmc init logic
intact, we need to define as above so that the unimplemented first MMC
instance (which does exist on the part) does not get intialized when the
ROM drops a bootdevice of 8.

-Matt
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Re: [U-Boot] [PATCH 03/10] am33xx: refactor am33xx clocks and add ti814x support

[Matt Porter]

On Fri, Feb 15, 2013 at 04:37:33PM +, Tom Rini wrote:
 On Wed, Feb 13, 2013 at 09:43:57AM -0500, Matt Porter wrote:
 
  Split clock.c for am335x and ti814x and add the ti814x include file.
  
  Signed-off-by: Matt Porter mpor...@ti.com
 
 [snip]
  +++ b/arch/arm/cpu/armv7/am33xx/clock-am335x.c
 [snip]
  +#define PRCM_MOD_EN0x2
  +#define PRCM_FORCE_WAKEUP  0x2
  +#define PRCM_FUNCTL0x0
  +
  +#define PRCM_EMIF_CLK_ACTIVITY BIT(2)
  +#define PRCM_L3_GCLK_ACTIVITY  BIT(4)
  +
  +#define PLL_BYPASS_MODE0x4
  +#define ST_MN_BYPASS   0x0100
  +#define ST_DPLL_CLK0x0001
  +#define CLK_SEL_MASK   0x7
  +#define CLK_DIV_MASK   0x1f
  +#define CLK_DIV2_MASK  0x7f
  +#define CLK_SEL_SHIFT  0x8
  +#define CLK_MODE_SEL   0x7
  +#define CLK_MODE_MASK  0xfff8
  +#define CLK_DIV_SEL0xFFE0
  +#define CPGMAC0_IDLE   0x3
  +#define DPLL_CLKDCOLDO_GATE_CTRL0x300
 [snip]
  +++ b/arch/arm/cpu/armv7/am33xx/clock-ti814x.c
 [snip]
  +   /* Selects OSC0 (20MHz) for DMTIMER1 */
  +   temp = readl(DMTIMER_CLKSRC);
  +   temp = ~(0x7  3);
  +   temp |= (0x4  3);
  +   writel(temp, DMTIMER_CLKSRC);
  +
  +   writel(0x2, DM_TIMER1_BASE + 0x54);
 
 Magic values are defined for clock-am335x.c but not in clock-ti814x.c,
 please fix clock-ti814x.c to define out the magic values ala am335x.c.
 Thanks!

Ok, will clean this up.

-Matt
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Re: [U-Boot] [PATCH 07/10] ti814x_evm: add ti814x evm board support

[Matt Porter]

On Fri, Feb 15, 2013 at 04:38:22PM +, Tom Rini wrote:
 On Wed, Feb 13, 2013 at 09:44:01AM -0500, Matt Porter wrote:
 
  Add TI814X EVM board directory and config file.
  
  Signed-off-by: Matt Porter mpor...@ti.com
 [snip]
  +++ b/board/ti/ti814x/evm.h
  @@ -0,0 +1,7 @@
  +#ifndef _EVM_H
 [snip]
  +++ b/include/configs/ti814x_evm.h
  @@ -0,0 +1,213 @@
  +#define __CONFIG_TI814X_EVM_H
 
 Needs GPLv2 or later boilerplate.

Ok.

 
 [snip]
  +#define CONFIG_CMDLINE_TAG 1   /* enable passing of ATAGs  */
  +#define CONFIG_SETUP_MEMORY_TAGS   1
  +#define CONFIG_INITRD_TAG  1   /* for ramdisk support */
 
 Just #define CONFIG_FOO in these cases (and some others that follow)

Ok.
 
 [snip]
  +   findfdt=\
  +   if test $board_name = A335BONE; then  \
  +   setenv fdtfile am335x-bone.dtb; fi;  \
  +   if test $board_name = A33515BB; then  \
  +   setenv fdtfile am335x-evm.dtb; fi;  \
  +   if test $board_name = A335X_SK; then  \
  +   setenv fdtfile am335x-evmsk.dtb; fi\0 \
 
 That's not right :)

LOL, indeed..forgot about that am335x specific stuff. Will fix.

 [snip]
  +/* memtest works on 8 MB in DRAM offset 32MB from start of ram disk*/
  +#define CONFIG_SYS_MEMTEST_START   (PHYS_DRAM_1 + (64 * 1024 * 1024))
  +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
  +   + (8 * 1024 * 1024))
 
 This isn't your mistake initially, but this should just be start of
 memory to smallest possible config the evm can come with - 4MB.

Ok.

 
 [snip]
  +#undef CONFIG_NAND_OMAP_GPMC
 
 Just leave it out.

Ok.

  +#define CONFIG_SYS_BAUDRATE_TABLE  { 110, 300, 600, 1200, 2400, \
  +4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
 
 Leave that out and get the generic table.  am335x needs to be updated
 for that.

Ok, will do. I even saw something about this and forgot to update this
config.

 [snip]
  +/* Since SPL did pll and ddr initialization for us,
  + * we don't need to do it twice.
  + */
 
 /*
  * Must be like
  * this.
  */

Ok.
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Re: [U-Boot] [PATCH 09/10] ti814x_evm: enable ti814x evm build

[Matt Porter]

On Fri, Feb 15, 2013 at 11:39:01AM -0500, Tom Rini wrote:
 On Wed, Feb 13, 2013 at 09:44:03AM -0500, Matt Porter wrote:
 
  Enable TI814X EVM build via ti814x_evm target.
  
  Signed-off-by: Matt Porter mpor...@ti.com
 
 This should just get squashed into the patch that adds the board code.
 Otherwise,
 
 Reviewed-by: Tom Rini tr...@ti.com

Sounds good. I'll squash it in there.

-Matt
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Re: [U-Boot] [PATCH 10/10] MAINTAINERS: add ti814x_evm maintainer

[Matt Porter]

On Fri, Feb 15, 2013 at 11:39:13AM -0500, Tom Rini wrote:
 On Wed, Feb 13, 2013 at 09:44:04AM -0500, Matt Porter wrote:
 
  Add a maintainer entry for the TI814x EVM.
  
  Signed-off-by: Matt Porter mpor...@ti.com
 
 Please squash this into the patch which adds the EVM, thanks.

Will do, thanks for the review.

-Matt
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[U-Boot] [PATCH 04/10] am33xx: refactor am33xx mux support and add ti814x support

[Matt Porter]

AM33XX and TI814X have a similar mux though the pinmux register
layout and address space differ. Add a separate ti814x mux include
to support the TI814X-specific differences.

Signed-off-by: Matt Porter mpor...@ti.com
---
 arch/arm/include/asm/arch-am33xx/mux-am335x.h |  246 
 arch/arm/include/asm/arch-am33xx/mux-ti814x.h |  310 +
 arch/arm/include/asm/arch-am33xx/mux.h|  230 +-
 3 files changed, 562 insertions(+), 224 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-am33xx/mux-am335x.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/mux-ti814x.h

diff --git a/arch/arm/include/asm/arch-am33xx/mux-am335x.h 
b/arch/arm/include/asm/arch-am33xx/mux-am335x.h
new file mode 100644
index 000..7258135
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mux-am335x.h
@@ -0,0 +1,246 @@
+/*
+ * mux.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_AM335X_H_
+#define _MUX_AM335X_H_
+
+#include common.h
+#include asm/io.h
+
+#define MUX_CFG(value, offset) \
+   __raw_writel(value, (CTRL_BASE + offset));
+
+/* PAD Control Fields */
+#define SLEWCTRL   (0x1  6)
+#define RXACTIVE   (0x1  5)
+#define PULLUP_EN  (0x1  4) /* Pull UP Selection */
+#define PULLUDEN   (0x0  3) /* Pull up enabled */
+#define PULLUDDIS  (0x1  3) /* Pull up disabled */
+#define MODE(val)  val /* used for Readability */
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+   int gpmc_ad0;
+   int gpmc_ad1;
+   int gpmc_ad2;
+   int gpmc_ad3;
+   int gpmc_ad4;
+   int gpmc_ad5;
+   int gpmc_ad6;
+   int gpmc_ad7;
+   int gpmc_ad8;
+   int gpmc_ad9;
+   int gpmc_ad10;
+   int gpmc_ad11;
+   int gpmc_ad12;
+   int gpmc_ad13;
+   int gpmc_ad14;
+   int gpmc_ad15;
+   int gpmc_a0;
+   int gpmc_a1;
+   int gpmc_a2;
+   int gpmc_a3;
+   int gpmc_a4;
+   int gpmc_a5;
+   int gpmc_a6;
+   int gpmc_a7;
+   int gpmc_a8;
+   int gpmc_a9;
+   int gpmc_a10;
+   int gpmc_a11;
+   int gpmc_wait0;
+   int gpmc_wpn;
+   int gpmc_be1n;
+   int gpmc_csn0;
+   int gpmc_csn1;
+   int gpmc_csn2;
+   int gpmc_csn3;
+   int gpmc_clk;
+   int gpmc_advn_ale;
+   int gpmc_oen_ren;
+   int gpmc_wen;
+   int gpmc_be0n_cle;
+   int lcd_data0;
+   int lcd_data1;
+   int lcd_data2;
+   int lcd_data3;
+   int lcd_data4;
+   int lcd_data5;
+   int lcd_data6;
+   int lcd_data7;
+   int lcd_data8;
+   int lcd_data9;
+   int lcd_data10;
+   int lcd_data11;
+   int lcd_data12;
+   int lcd_data13;
+   int lcd_data14;
+   int lcd_data15;
+   int lcd_vsync;
+   int lcd_hsync;
+   int lcd_pclk;
+   int lcd_ac_bias_en;
+   int mmc0_dat3;
+   int mmc0_dat2;
+   int mmc0_dat1;
+   int mmc0_dat0;
+   int mmc0_clk;
+   int mmc0_cmd;
+   int mii1_col;
+   int mii1_crs;
+   int mii1_rxerr;
+   int mii1_txen;
+   int mii1_rxdv;
+   int mii1_txd3;
+   int mii1_txd2;
+   int mii1_txd1;
+   int mii1_txd0;
+   int mii1_txclk;
+   int mii1_rxclk;
+   int mii1_rxd3;
+   int mii1_rxd2;
+   int mii1_rxd1;
+   int mii1_rxd0;
+   int rmii1_refclk;
+   int mdio_data;
+   int mdio_clk;
+   int spi0_sclk;
+   int spi0_d0;
+   int spi0_d1;
+   int spi0_cs0;
+   int spi0_cs1;
+   int ecap0_in_pwm0_out;
+   int uart0_ctsn;
+   int uart0_rtsn;
+   int uart0_rxd;
+   int uart0_txd;
+   int uart1_ctsn;
+   int uart1_rtsn;
+   int uart1_rxd;
+   int uart1_txd;
+   int i2c0_sda;
+   int i2c0_scl;
+   int mcasp0_aclkx;
+   int mcasp0_fsx;
+   int mcasp0_axr0;
+   int mcasp0_ahclkr;
+   int mcasp0_aclkr;
+   int mcasp0_fsr;
+   int mcasp0_axr1;
+   int mcasp0_ahclkx;
+   int xdma_event_intr0;
+   int xdma_event_intr1;
+   int nresetin_out;
+   int porz;
+   int nnmi;
+   int osc0_in;
+   int osc0_out;
+   int rsvd1;
+   int tms;
+   int tdi;
+   int tdo;
+   int tck;
+   int ntrst;
+   int emu0;
+   int emu1;
+   int osc1_in;
+   int osc1_out;
+   int pmic_power_en;
+   int rtc_porz;
+   int rsvd2;
+   int ext_wakeup;
+   int enz_kaldo_1p8v

[U-Boot] [PATCH 00/10] Add TI814x EVM Support

[Matt Porter]

This series adds support for the PG1.0 TI814x EVM board. TI814x
fits into the existing AM33XX SoC support with some refactoring
of the AM33XX-specific emif4, clock, and mux code.

It has been tested booting up a Linux kernel and regression tested
on BeagleBone and EVM-SK AM33XX boards.

Matt Porter (10):
  am33xx: convert defines from am33xx-specific to generic names
  am33xx: refactor emif4/ddr to support multiple EMIF instances
  am33xx: refactor am33xx clocks and add ti814x support
  am33xx: refactor am33xx mux support and add ti814x support
  am33xx: add ti814x specific register definitions
  am33xx: add dmm support to emif4 library
  ti814x_evm: add ti814x evm board support
  ns16550: enable quirks for ti814x
  ti814x_evm: enable ti814x evm build
  MAINTAINERS: add ti814x_evm maintainer

 MAINTAINERS  |4 +
 Makefile |2 +-
 arch/arm/cpu/armv7/Makefile  |2 +-
 arch/arm/cpu/armv7/am33xx/Makefile   |3 +-
 arch/arm/cpu/armv7/am33xx/board.c|4 +-
 arch/arm/cpu/armv7/am33xx/clock-am335x.c |  374 ++
 arch/arm/cpu/armv7/am33xx/clock-ti814x.c |  234 ++
 arch/arm/cpu/armv7/am33xx/clock.c|  374 --
 arch/arm/cpu/armv7/am33xx/ddr.c  |   99 +++---
 arch/arm/cpu/armv7/am33xx/emif4.c|   55 ++--
 arch/arm/cpu/armv7/am33xx/sys_info.c |3 +
 arch/arm/cpu/armv7/omap-common/Makefile  |2 +-
 arch/arm/include/asm/arch-am33xx/clock.h |4 +
 arch/arm/include/asm/arch-am33xx/clocks_ti814x.h |  112 +++
 arch/arm/include/asm/arch-am33xx/cpu.h   |   11 +-
 arch/arm/include/asm/arch-am33xx/ddr_defs.h  |   57 +++-
 arch/arm/include/asm/arch-am33xx/hardware.h  |   60 +++-
 arch/arm/include/asm/arch-am33xx/mux-am335x.h|  246 ++
 arch/arm/include/asm/arch-am33xx/mux-ti814x.h|  310 ++
 arch/arm/include/asm/arch-am33xx/mux.h   |  230 +
 arch/arm/include/asm/arch-am33xx/omap.h  |7 +
 arch/arm/include/asm/arch-am33xx/spl.h   |5 +
 board/ti/am335x/board.c  |   10 +-
 board/ti/ti814x/Makefile |   46 +++
 board/ti/ti814x/evm.c|  198 
 board/ti/ti814x/evm.h|7 +
 board/ti/ti814x/mux.c|   51 +++
 boards.cfg   |1 +
 drivers/serial/ns16550.c |5 +-
 include/configs/ti814x_evm.h |  213 
 spl/Makefile |2 +-
 31 files changed, 2044 insertions(+), 687 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/am33xx/clock-am335x.c
 create mode 100644 arch/arm/cpu/armv7/am33xx/clock-ti814x.c
 delete mode 100644 arch/arm/cpu/armv7/am33xx/clock.c
 create mode 100644 arch/arm/include/asm/arch-am33xx/clocks_ti814x.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/mux-am335x.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/mux-ti814x.h
 create mode 100644 board/ti/ti814x/Makefile
 create mode 100644 board/ti/ti814x/evm.c
 create mode 100644 board/ti/ti814x/evm.h
 create mode 100644 board/ti/ti814x/mux.c
 create mode 100644 include/configs/ti814x_evm.h

-- 
1.7.9.5

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[U-Boot] [PATCH 09/10] ti814x_evm: enable ti814x evm build

[Matt Porter]

Enable TI814X EVM build via ti814x_evm target.

Signed-off-by: Matt Porter mpor...@ti.com
---
 Makefile|2 +-
 arch/arm/cpu/armv7/Makefile |2 +-
 arch/arm/cpu/armv7/omap-common/Makefile |2 +-
 boards.cfg  |1 +
 spl/Makefile|2 +-
 5 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/Makefile b/Makefile
index 51bd918..120ab31 100644
--- a/Makefile
+++ b/Makefile
@@ -334,7 +334,7 @@ LIBS-y += api/libapi.o
 LIBS-y += post/libpost.o
 LIBS-y += test/libtest.o
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+ifneq 
($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
 
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 4fdbee4..156a5ba 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,7 @@ COBJS += cache_v7.o
 COBJS  += cpu.o
 COBJS  += syslib.o
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
+ifneq 
($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20)$(CONFIG_TI814X),)
 SOBJS  += lowlevel_init.o
 endif
 
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile 
b/arch/arm/cpu/armv7/omap-common/Makefile
index 0efc80d..55e82ba 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -36,7 +36,7 @@ COBJS += emif-common.o
 COBJS  += vc.o
 endif
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
 COBJS  += boot-common.o
 SOBJS  += lowlevel_init.o
 endif
diff --git a/boards.cfg b/boards.cfg
index 98f7a14..0eabae9 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -236,6 +236,7 @@ am335x_evm_uart2 arm armv7   am335x 
 ti
 am335x_evm_uart3 arm armv7   am335x  ti
 am33xx  am335x_evm:SERIAL4,CONS_INDEX=4
 am335x_evm_uart4 arm armv7   am335x  ti
 am33xx  am335x_evm:SERIAL5,CONS_INDEX=5
 am335x_evm_uart5 arm armv7   am335x  ti
 am33xx  am335x_evm:SERIAL6,CONS_INDEX=6
+ti814x_evm   arm armv7   ti814x  ti
 am33xx
 highbank arm armv7   highbank- 
 highbank
 mx51_efikamx arm armv7   mx51_efikamx
genesi mx5
mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
 mx51_efikasb arm armv7   mx51_efikamx
genesi mx5
mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg
diff --git a/spl/Makefile b/spl/Makefile
index 6dbb105..9761e7d 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -82,7 +82,7 @@ LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/libnet.o
 LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o
 LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+ifneq 
($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
 
-- 
1.7.9.5

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[U-Boot] [PATCH 10/10] MAINTAINERS: add ti814x_evm maintainer

[Matt Porter]

Add a maintainer entry for the TI814x EVM.

Signed-off-by: Matt Porter mpor...@ti.com
---
 MAINTAINERS |4 
 1 file changed, 4 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d3ed390..282dead 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -830,6 +830,10 @@ Stelian Pop stel...@popies.net
at91sam9263ek   ARM926EJS (AT91SAM9263 SoC)
at91sam9rlekARM926EJS (AT91SAM9RL SoC)
 
+Matt Porter mpor...@ti.com
+
+   ti814x_evm  ARM ARMV7 (TI814x Soc)
+
 Dave Purdy david.c.pu...@gmail.com
 
pogo_e02ARM926EJS (Kirkwood SoC)
-- 
1.7.9.5

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[U-Boot] [PATCH 06/10] am33xx: add dmm support to emif4 library

[Matt Porter]

Adds a config_dmm() routine to support TI814X DMM configuration.

Signed-off-by: Matt Porter mpor...@ti.com
---
 arch/arm/cpu/armv7/am33xx/emif4.c   |   17 +
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |5 +
 2 files changed, 22 insertions(+)

diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c 
b/arch/arm/cpu/armv7/am33xx/emif4.c
index 0c617fa..27547be 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -44,11 +44,28 @@ void dram_init_banksize(void)
 
 
 #ifdef CONFIG_SPL_BUILD
+static struct dmm_lisa_map_regs *hw_lisa_map_regs =
+   (struct dmm_lisa_map_regs *)DMM_BASE;
 static struct vtp_reg *vtpreg[2] = {
(struct vtp_reg *)VTP0_CTRL_ADDR,
(struct vtp_reg *)VTP1_CTRL_ADDR};
 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
 
+void config_dmm(const struct dmm_lisa_map_regs *regs)
+{
+   enable_dmm_clocks();
+
+   writel(0, hw_lisa_map_regs-dmm_lisa_map_3);
+   writel(0, hw_lisa_map_regs-dmm_lisa_map_2);
+   writel(0, hw_lisa_map_regs-dmm_lisa_map_1);
+   writel(0, hw_lisa_map_regs-dmm_lisa_map_0);
+
+   writel(regs-dmm_lisa_map_3, hw_lisa_map_regs-dmm_lisa_map_3);
+   writel(regs-dmm_lisa_map_2, hw_lisa_map_regs-dmm_lisa_map_2);
+   writel(regs-dmm_lisa_map_1, hw_lisa_map_regs-dmm_lisa_map_1);
+   writel(regs-dmm_lisa_map_0, hw_lisa_map_regs-dmm_lisa_map_0);
+}
+
 static void config_vtp(int nr)
 {
writel(readl(vtpreg[nr]-vtp0ctrlreg) | VTP_CTRL_ENABLE,
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h 
b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 8bf25a0..943b4ce 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -66,6 +66,11 @@
 #define MT41J128MJT125_IOCTRL_VALUE0x18B
 
 /**
+ * Configure DMM
+ */
+void config_dmm(const struct dmm_lisa_map_regs *regs);
+
+/**
  * Configure SDRAM
  */
 void config_sdram(const struct emif_regs *regs, int nr);
-- 
1.7.9.5

___
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[U-Boot] [PATCH 05/10] am33xx: add ti814x specific register definitions

[Matt Porter]

Support the ti814x specific register definitions within
arch-am33xx.

Signed-off-by: Matt Porter mpor...@ti.com
---
 arch/arm/cpu/armv7/am33xx/sys_info.c|3 +++
 arch/arm/include/asm/arch-am33xx/cpu.h  |   11 +
 arch/arm/include/asm/arch-am33xx/hardware.h |   32 +++
 arch/arm/include/asm/arch-am33xx/omap.h |7 ++
 arch/arm/include/asm/arch-am33xx/spl.h  |5 +
 5 files changed, 54 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c 
b/arch/arm/cpu/armv7/am33xx/sys_info.c
index 507b618..402127c 100644
--- a/arch/arm/cpu/armv7/am33xx/sys_info.c
+++ b/arch/arm/cpu/armv7/am33xx/sys_info.c
@@ -98,6 +98,9 @@ int print_cpuinfo(void)
case AM335X:
cpu_s = AM335X;
break;
+   case TI81XX:
+   cpu_s = TI81XX;
+   break;
default:
cpu_s = Unknown cpu type;
break;
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h 
b/arch/arm/include/asm/arch-am33xx/cpu.h
index 16e8a80..3d3a7c8 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -42,9 +42,10 @@
 #define HS_DEVICE  0x2
 #define GP_DEVICE  0x3
 
-/* cpu-id for AM33XX family */
+/* cpu-id for AM33XX and TI81XX family */
 #define AM335X 0xB944
-#define DEVICE_ID  0x44E10600
+#define TI81XX 0xB81E
+#define DEVICE_ID  (CTRL_BASE + 0x0600)
 
 /* This gives the status of the boot mode pins on the evm */
 #define SYSBOOT_MASK   (BIT(0) | BIT(1) | BIT(2)\
@@ -52,9 +53,11 @@
 
 /* Reset control */
 #ifdef CONFIG_AM33XX
-#define PRM_RSTCTRL0x44E00F00
-#define PRM_RSTST  0x44E00F08
+#define PRM_RSTCTRL(PRCM_BASE + 0x0F00)
+#elif defined(CONFIG_TI814X)
+#define PRM_RSTCTRL(PRCM_BASE + 0x00A0)
 #endif
+#define PRM_RSTST  (PRM_RSTCTRL + 8)
 #define PRM_RSTCTRL_RESET  0x01
 #define PRM_RSTST_WARM_RESET_MASK  0x232
 
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h 
b/arch/arm/include/asm/arch-am33xx/hardware.h
index 41ab2c0..786c159 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -20,9 +20,14 @@
 #define __AM33XX_HARDWARE_H
 
 #include asm/arch/omap.h
+#include config.h
 
 /* Module base addresses */
+#ifdef CONFIG_AM33XX
 #define UART0_BASE 0x44E09000
+#elif defined(CONFIG_TI814X)
+#define UART0_BASE 0x4802
+#endif
 
 /* DM Timer base addresses */
 #define DM_TIMER0_BASE 0x4802C000
@@ -37,20 +42,39 @@
 /* GPIO Base address */
 #define GPIO0_BASE 0x48032000
 #define GPIO1_BASE 0x4804C000
+#ifdef CONFIG_AM33XX
 #define GPIO2_BASE 0x481AC000
+#endif
 
 /* BCH Error Location Module */
 #define ELM_BASE   0x4808
 
 /* Watchdog Timer */
+#ifdef CONFIG_AM33XX
 #define WDT_BASE   0x44E35000
+#elif defined(CONFIG_TI814X)
+#define WDT_BASE   0x481C7000
+#endif
 
 /* Control Module Base Address */
+#ifdef CONFIG_AM33XX
 #define CTRL_BASE  0x44E1
 #define CTRL_DEVICE_BASE   0x44E10600
+#elif defined(CONFIG_TI814X)
+#define CTRL_BASE  0x4814
+#endif
 
 /* PRCM Base Address */
+#ifdef CONFIG_AM33XX
 #define PRCM_BASE  0x44E0
+#elif defined(CONFIG_TI814X)
+#define PRCM_BASE  0x4818
+#endif
+
+/* PLL Subsystem Base Address */
+#ifdef CONFIG_TI814X
+#define PLL_SUBSYS_BASE0x481C5000
+#endif
 
 /* EMIF Base address */
 #define EMIF4_0_CFG_BASE   0x4C00
@@ -99,10 +123,18 @@
 
 /* CPSW Config space */
 #define CPSW_BASE  0x4A10
+#ifdef CONFIG_AM33XX
 #define CPSW_MDIO_BASE 0x4A101000
+#elif defined(CONFIG_TI814X)
+#define CPSW_MDIO_BASE 0x4A100800
+#endif
 
 /* RTC base address */
+#ifdef CONFIG_AM33XX
 #define RTC_BASE   0x44E3E000
+#elif defined(CONFIG_TI814X)
+#define RTC_BASE   0x480C
+#endif
 
 /* OTG */
 #define USB0_OTG_BASE  0x47401000
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h 
b/arch/arm/include/asm/arch-am33xx/omap.h
index 850f8a5..ba4f6d2 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -23,13 +23,20 @@
 #ifndef _OMAP_H_
 #define _OMAP_H_
 
+#include config.h
+
 /*
  * Non-secure SRAM Addresses
  * Non-secure RAM starts at 0x4030 for GP devices. But we keep SRAM_BASE
  * at 0x40304000(EMU base) so that our code works for both EMU and GP
  */
+#ifdef CONFIG_AM33XX
 #define NON_SECURE_SRAM_START  0x40304000
 #define

[U-Boot] [PATCH 02/10] am33xx: refactor emif4/ddr to support multiple EMIF instances

[Matt Porter]

The AM33xx emif4/ddr support closely matches what is need to support
TI814x except that TI814x has two EMIF instances. Refactor all the
emif4 helper calls and the config_ddr() init function to use an
additional instance number argument.

Signed-off-by: Matt Porter mpor...@ti.com
---
 arch/arm/cpu/armv7/am33xx/ddr.c |   99 ---
 arch/arm/cpu/armv7/am33xx/emif4.c   |   38 +-
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |   52 --
 arch/arm/include/asm/arch-am33xx/hardware.h |   18 -
 board/ti/am335x/board.c |4 +-
 5 files changed, 143 insertions(+), 68 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index fd9fc4a..493b99b 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -24,15 +24,20 @@ http://www.ti.com/
 /**
  * Base address for EMIF instances
  */
-static struct emif_reg_struct *emif_reg = {
-   (struct emif_reg_struct *)EMIF4_0_CFG_BASE};
+static struct emif_reg_struct *emif_reg[2] = {
+   (struct emif_reg_struct *)EMIF4_0_CFG_BASE,
+   (struct emif_reg_struct *)EMIF4_1_CFG_BASE};
 
 /**
- * Base address for DDR instance
+ * Base addresses for DDR PHY cmd/data regs
  */
-static struct ddr_regs *ddr_reg[2] = {
-   (struct ddr_regs *)DDR_PHY_BASE_ADDR,
-   (struct ddr_regs *)DDR_PHY_BASE_ADDR2};
+static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
+   (struct ddr_regs *)DDR_PHY_CMD_ADDR,
+   (struct ddr_regs *)DDR_PHY_CMD_ADDR2};
+
+static struct ddr_data_regs *ddr_data_reg[2] = {
+   (struct ddr_regs *)DDR_PHY_DATA_ADDR,
+   (struct ddr_regs *)DDR_PHY_DATA_ADDR2};
 
 /**
  * Base address for ddr io control instances
@@ -43,70 +48,84 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
 /**
  * Configure SDRAM
  */
-void config_sdram(const struct emif_regs *regs)
+void config_sdram(const struct emif_regs *regs, int nr)
 {
-   writel(regs-ref_ctrl, emif_reg-emif_sdram_ref_ctrl);
-   writel(regs-ref_ctrl, emif_reg-emif_sdram_ref_ctrl_shdw);
+   writel(regs-ref_ctrl, emif_reg[nr]-emif_sdram_ref_ctrl);
+   writel(regs-ref_ctrl, emif_reg[nr]-emif_sdram_ref_ctrl_shdw);
if (regs-zq_config){
-   writel(regs-zq_config, emif_reg-emif_zq_config);
+   writel(regs-zq_config, emif_reg[nr]-emif_zq_config);
writel(regs-sdram_config, cstat-secure_emif_sdram_config);
}
-   writel(regs-sdram_config, emif_reg-emif_sdram_config);
+   writel(regs-sdram_config, emif_reg[nr]-emif_sdram_config);
 }
 
 /**
  * Set SDRAM timings
  */
-void set_sdram_timings(const struct emif_regs *regs)
+void set_sdram_timings(const struct emif_regs *regs, int nr)
 {
-   writel(regs-sdram_tim1, emif_reg-emif_sdram_tim_1);
-   writel(regs-sdram_tim1, emif_reg-emif_sdram_tim_1_shdw);
-   writel(regs-sdram_tim2, emif_reg-emif_sdram_tim_2);
-   writel(regs-sdram_tim2, emif_reg-emif_sdram_tim_2_shdw);
-   writel(regs-sdram_tim3, emif_reg-emif_sdram_tim_3);
-   writel(regs-sdram_tim3, emif_reg-emif_sdram_tim_3_shdw);
+   writel(regs-sdram_tim1, emif_reg[nr]-emif_sdram_tim_1);
+   writel(regs-sdram_tim1, emif_reg[nr]-emif_sdram_tim_1_shdw);
+   writel(regs-sdram_tim2, emif_reg[nr]-emif_sdram_tim_2);
+   writel(regs-sdram_tim2, emif_reg[nr]-emif_sdram_tim_2_shdw);
+   writel(regs-sdram_tim3, emif_reg[nr]-emif_sdram_tim_3);
+   writel(regs-sdram_tim3, emif_reg[nr]-emif_sdram_tim_3_shdw);
 }
 
 /**
  * Configure DDR PHY
  */
-void config_ddr_phy(const struct emif_regs *regs)
+void config_ddr_phy(const struct emif_regs *regs, int nr)
 {
-   writel(regs-emif_ddr_phy_ctlr_1, emif_reg-emif_ddr_phy_ctrl_1);
-   writel(regs-emif_ddr_phy_ctlr_1, emif_reg-emif_ddr_phy_ctrl_1_shdw);
+   writel(regs-emif_ddr_phy_ctlr_1,
+   emif_reg[nr]-emif_ddr_phy_ctrl_1);
+   writel(regs-emif_ddr_phy_ctlr_1,
+   emif_reg[nr]-emif_ddr_phy_ctrl_1_shdw);
 }
 
 /**
  * Configure DDR CMD control registers
  */
-void config_cmd_ctrl(const struct cmd_control *cmd)
+void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
 {
-   writel(cmd-cmd0csratio, ddr_reg[0]-cm0csratio);
-   writel(cmd-cmd0dldiff, ddr_reg[0]-cm0dldiff);
-   writel(cmd-cmd0iclkout, ddr_reg[0]-cm0iclkout);
+   writel(cmd-cmd0csratio, ddr_cmd_reg[nr]-cm0csratio);
+   writel(cmd-cmd0dldiff, ddr_cmd_reg[nr]-cm0dldiff);
+   writel(cmd-cmd0iclkout, ddr_cmd_reg[nr]-cm0iclkout);
 
-   writel(cmd-cmd1csratio, ddr_reg[0]-cm1csratio);
-   writel(cmd-cmd1dldiff, ddr_reg[0]-cm1dldiff);
-   writel(cmd-cmd1iclkout, ddr_reg[0]-cm1iclkout);
+   writel(cmd-cmd1csratio, ddr_cmd_reg[nr]-cm1csratio);
+   writel(cmd

[U-Boot] [PATCH 03/10] am33xx: refactor am33xx clocks and add ti814x support

[Matt Porter]

Split clock.c for am335x and ti814x and add the ti814x include file.

Signed-off-by: Matt Porter mpor...@ti.com
---
 arch/arm/cpu/armv7/am33xx/Makefile   |3 +-
 arch/arm/cpu/armv7/am33xx/clock-am335x.c |  374 ++
 arch/arm/cpu/armv7/am33xx/clock-ti814x.c |  234 ++
 arch/arm/cpu/armv7/am33xx/clock.c|  374 --
 arch/arm/include/asm/arch-am33xx/clock.h |4 +
 arch/arm/include/asm/arch-am33xx/clocks_ti814x.h |  112 +++
 6 files changed, 726 insertions(+), 375 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/am33xx/clock-am335x.c
 create mode 100644 arch/arm/cpu/armv7/am33xx/clock-ti814x.c
 delete mode 100644 arch/arm/cpu/armv7/am33xx/clock.c
 create mode 100644 arch/arm/include/asm/arch-am33xx/clocks_ti814x.h

diff --git a/arch/arm/cpu/armv7/am33xx/Makefile 
b/arch/arm/cpu/armv7/am33xx/Makefile
index 70c443e..7051029 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -16,7 +16,8 @@ include $(TOPDIR)/config.mk
 
 LIB= $(obj)lib$(SOC).o
 
-COBJS  += clock.o
+COBJS-$(CONFIG_AM33XX) += clock-am335x.o
+COBJS-$(CONFIG_TI814X) += clock-ti814x.o
 COBJS  += sys_info.o
 COBJS  += mem.o
 COBJS  += ddr.o
diff --git a/arch/arm/cpu/armv7/am33xx/clock-am335x.c 
b/arch/arm/cpu/armv7/am33xx/clock-am335x.c
new file mode 100644
index 000..d7d98d1
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock-am335x.c
@@ -0,0 +1,374 @@
+/*
+ * clock.c
+ *
+ * clocks for AM33XX based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include asm/arch/cpu.h
+#include asm/arch/clock.h
+#include asm/arch/hardware.h
+#include asm/io.h
+
+#define PRCM_MOD_EN0x2
+#define PRCM_FORCE_WAKEUP  0x2
+#define PRCM_FUNCTL0x0
+
+#define PRCM_EMIF_CLK_ACTIVITY BIT(2)
+#define PRCM_L3_GCLK_ACTIVITY  BIT(4)
+
+#define PLL_BYPASS_MODE0x4
+#define ST_MN_BYPASS   0x0100
+#define ST_DPLL_CLK0x0001
+#define CLK_SEL_MASK   0x7
+#define CLK_DIV_MASK   0x1f
+#define CLK_DIV2_MASK  0x7f
+#define CLK_SEL_SHIFT  0x8
+#define CLK_MODE_SEL   0x7
+#define CLK_MODE_MASK  0xfff8
+#define CLK_DIV_SEL0xFFE0
+#define CPGMAC0_IDLE   0x3
+#define DPLL_CLKDCOLDO_GATE_CTRL0x300
+
+const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
+const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
+const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
+const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
+
+static void enable_interface_clocks(void)
+{
+   /* Enable all the Interconnect Modules */
+   writel(PRCM_MOD_EN, cmper-l3clkctrl);
+   while (readl(cmper-l3clkctrl) != PRCM_MOD_EN)
+   ;
+
+   writel(PRCM_MOD_EN, cmper-l4lsclkctrl);
+   while (readl(cmper-l4lsclkctrl) != PRCM_MOD_EN)
+   ;
+
+   writel(PRCM_MOD_EN, cmper-l4fwclkctrl);
+   while (readl(cmper-l4fwclkctrl) != PRCM_MOD_EN)
+   ;
+
+   writel(PRCM_MOD_EN, cmwkup-wkl4wkclkctrl);
+   while (readl(cmwkup-wkl4wkclkctrl) != PRCM_MOD_EN)
+   ;
+
+   writel(PRCM_MOD_EN, cmper-l3instrclkctrl);
+   while (readl(cmper-l3instrclkctrl) != PRCM_MOD_EN)
+   ;
+
+   writel(PRCM_MOD_EN, cmper-l4hsclkctrl);
+   while (readl(cmper-l4hsclkctrl) != PRCM_MOD_EN)
+   ;
+
+   writel(PRCM_MOD_EN, cmwkup-wkgpio0clkctrl);
+   while (readl(cmwkup-wkgpio0clkctrl) != PRCM_MOD_EN)
+   ;
+}
+
+/*
+ * Force power domain wake up transition
+ * Ensure that the corresponding interface clock is active before
+ * using the peripheral
+ */
+static void power_domain_wkup_transition(void)
+{
+   writel(PRCM_FORCE_WAKEUP, cmper-l3clkstctrl);
+   writel(PRCM_FORCE_WAKEUP, cmper-l4lsclkstctrl);
+   writel(PRCM_FORCE_WAKEUP, cmwkup-wkclkstctrl);
+   writel(PRCM_FORCE_WAKEUP, cmper-l4fwclkstctrl);
+   writel(PRCM_FORCE_WAKEUP, cmper-l3sclkstctrl);
+}
+
+/*
+ * Enable the peripheral clock for required peripherals
+ */
+static void enable_per_clocks(void)
+{
+   /* Enable the control module though RBL would have done it*/
+   writel(PRCM_MOD_EN, cmwkup-wkctrlclkctrl);
+   while (readl(cmwkup-wkctrlclkctrl) != PRCM_MOD_EN)
+   ;
+
+   /* Enable the module clock

[U-Boot] [PATCH 07/10] ti814x_evm: add ti814x evm board support

[Matt Porter]

Add TI814X EVM board directory and config file.

Signed-off-by: Matt Porter mpor...@ti.com
---
 board/ti/ti814x/Makefile |   46 +
 board/ti/ti814x/evm.c|  198 +++
 board/ti/ti814x/evm.h|7 ++
 board/ti/ti814x/mux.c|   51 ++
 include/configs/ti814x_evm.h |  213 ++
 5 files changed, 515 insertions(+)
 create mode 100644 board/ti/ti814x/Makefile
 create mode 100644 board/ti/ti814x/evm.c
 create mode 100644 board/ti/ti814x/evm.h
 create mode 100644 board/ti/ti814x/mux.c
 create mode 100644 include/configs/ti814x_evm.h

diff --git a/board/ti/ti814x/Makefile b/board/ti/ti814x/Makefile
new file mode 100644
index 000..09d2422
--- /dev/null
+++ b/board/ti/ti814x/Makefile
@@ -0,0 +1,46 @@
+#
+# Makefile
+#
+# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed as is WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS  := mux.o
+endif
+
+COBJS  += evm.o
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+   $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+   rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+   rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
new file mode 100644
index 000..53912d1
--- /dev/null
+++ b/board/ti/ti814x/evm.c
@@ -0,0 +1,198 @@
+/*
+ * evm.c
+ *
+ * Board functions for TI814x EVM
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include errno.h
+#include spl.h
+#include asm/arch/cpu.h
+#include asm/arch/hardware.h
+#include asm/arch/omap.h
+#include asm/arch/ddr_defs.h
+#include asm/arch/clock.h
+#include asm/arch/gpio.h
+#include asm/arch/mmc_host_def.h
+#include asm/arch/sys_proto.h
+#include asm/io.h
+#include asm/emif.h
+#include asm/gpio.h
+#include evm.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+#ifdef CONFIG_SPL_BUILD
+static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+#endif
+
+/* UART Defines */
+#ifdef CONFIG_SPL_BUILD
+#define UART_RESET (0x1  1)
+#define UART_CLK_RUNNING_MASK  0x1
+#define UART_SMART_IDLE_EN (0x1  0x3)
+
+static void rtc32k_enable(void)
+{
+   struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
+
+   /*
+* Unlock the RTC's registers.  For more details please see the
+* RTC_SS section of the TRM.  In order to unlock we need to
+* write these specific values (keys) in this order.
+*/
+   writel(0x83e70b13, rtc-kick0r);
+   writel(0x95a4f1e0, rtc-kick1r);
+
+   /* Enable the RTC 32K OSC by setting bits 3 and 6. */
+   writel((1  3) | (1  6), rtc-osc);
+}
+
+static void uart_enable(void)
+{
+   u32 regVal;
+
+   /* UART softreset */
+   regVal = readl(uart_base-uartsyscfg);
+   regVal |= UART_RESET;
+   writel(regVal, uart_base-uartsyscfg);
+   while ((readl(uart_base-uartsyssts) 
+   UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+   ;
+
+   /* Disable smart idle */
+   regVal = readl(uart_base-uartsyscfg);
+   regVal |= UART_SMART_IDLE_EN;
+   writel(regVal, uart_base-uartsyscfg);
+}
+
+static void wdt_disable(void)
+{
+   writel(0x, wdtimer-wdtwspr);
+   while (readl(wdtimer-wdtwwps) != 0x0)
+   ;
+   writel(0x, wdtimer-wdtwspr);
+   while (readl(wdtimer-wdtwwps) != 0x0)
+   ;
+}
+
+static const struct cmd_control evm_ddr2_cctrl_data

[U-Boot] [PATCH 01/10] am33xx: convert defines from am33xx-specific to generic names

[Matt Porter]

Eliminate AM33xx specific names to prepare for TI814x support
within AM33xx-land.

Signed-off-by: Matt Porter mpor...@ti.com
---
 arch/arm/cpu/armv7/am33xx/board.c   |4 ++--
 arch/arm/include/asm/arch-am33xx/hardware.h |   10 +-
 board/ti/am335x/board.c |6 +++---
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/board.c 
b/arch/arm/cpu/armv7/am33xx/board.c
index ab31326..b186b32 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -141,11 +141,11 @@ int arch_misc_init(void)
 {
 #ifdef CONFIG_AM335X_USB0
musb_register(otg0_plat, otg0_board_data,
-   (void *)AM335X_USB0_OTG_BASE);
+   (void *)USB0_OTG_BASE);
 #endif
 #ifdef CONFIG_AM335X_USB1
musb_register(otg1_plat, otg1_board_data,
-   (void *)AM335X_USB1_OTG_BASE);
+   (void *)USB1_OTG_BASE);
 #endif
return 0;
 }
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h 
b/arch/arm/include/asm/arch-am33xx/hardware.h
index 6dd3296..7016e25 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -84,14 +84,14 @@
 #define GPMC_BASE  0x5000
 
 /* CPSW Config space */
-#define AM335X_CPSW_BASE   0x4A10
-#define AM335X_CPSW_MDIO_BASE  0x4A101000
+#define CPSW_BASE  0x4A10
+#define CPSW_MDIO_BASE 0x4A101000
 
 /* RTC base address */
-#define AM335X_RTC_BASE0x44E3E000
+#define RTC_BASE   0x44E3E000
 
 /* OTG */
-#define AM335X_USB0_OTG_BASE   0x47401000
-#define AM335X_USB1_OTG_BASE   0x47401800
+#define USB0_OTG_BASE  0x47401000
+#define USB1_OTG_BASE  0x47401800
 
 #endif /* __AM33XX_HARDWARE_H */
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index ed4229e..1e698df 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -123,7 +123,7 @@ static int read_eeprom(void)
 
 static void rtc32k_enable(void)
 {
-   struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
+   struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
 
/*
 * Unlock the RTC's registers.  For more details please see the
@@ -365,8 +365,8 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 };
 
 static struct cpsw_platform_data cpsw_data = {
-   .mdio_base  = AM335X_CPSW_MDIO_BASE,
-   .cpsw_base  = AM335X_CPSW_BASE,
+   .mdio_base  = CPSW_MDIO_BASE,
+   .cpsw_base  = CPSW_BASE,
.mdio_div   = 0xff,
.channels   = 8,
.cpdma_reg_ofs  = 0x800,
-- 
1.7.9.5

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[U-Boot] [PATCH 08/10] ns16550: enable quirks for ti814x

[Matt Porter]

TI814X requires the same quirks as AM33XX to be enabled.

Signed-off-by: Matt Porter mpor...@ti.com
---
 drivers/serial/ns16550.c |5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 87a0917..02bc85b 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -43,7 +43,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
 
serial_out(CONFIG_SYS_NS16550_IER, com_port-ier);
 #if (defined(CONFIG_OMAP)  !defined(CONFIG_OMAP3_ZOOM2)) || \
-   defined(CONFIG_AM33XX)
+   defined(CONFIG_AM33XX) || defined(CONFIG_TI814X)
serial_out(0x7, com_port-mdr1);   /* mode select reset TL16C750*/
 #endif
serial_out(UART_LCR_BKSE | UART_LCRVAL, (ulong)com_port-lcr);
@@ -57,7 +57,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
serial_out((baud_divisor  8)  0xff, com_port-dlm);
serial_out(UART_LCRVAL, com_port-lcr);
 #if (defined(CONFIG_OMAP)  !defined(CONFIG_OMAP3_ZOOM2)) || \
-   defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX)
+   defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \
+   defined(CONFIG_TI814X)
 
 #if defined(CONFIG_APTIX)
/* /13 mode so Aptix 6MHz can hit 115200 */
-- 
1.7.9.5

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