[U-Boot] [PATCH] mkimage: Set correct FDT type and ramdisk architecture in FIT auto mode

2019-09-13 Thread Michal Sojka 
From: Michal Sojka 

When running the following command

mkimage -f auto -A arm -O linux -T kernel -C none -a 0x8000 -e 0x8000 \
-d zImage -b zynq-microzed.dtb -i initramfs.cpio image.ub

the type of fdt subimage is the same as of the main kernel image and
the architecture of the initramfs image is not set. Such an image is
refused by U-Boot when booting. This commits sets the mentioned
attributes, allowing to use the "-f auto" mode in this case instead of
writing full .its file.

Following is the diff of mkimage output without and with this commit:

 FIT description: Kernel Image image with one or more FDT blobs
 Created: Thu Sep 12 23:23:16 2019
  Image 0 (kernel-1)
   Description:
   Created:  Thu Sep 12 23:23:16 2019
   Type: Kernel Image
   Compression:  uncompressed
   Data Size:4192744 Bytes = 4094.48 KiB = 4.00 MiB
   Architecture: ARM
   OS:   Linux
   Load Address: 0x8000
   Entry Point:  0x8000
  Image 1 (fdt-1)
   Description:  zynq-microzed
   Created:  Thu Sep 12 23:23:16 2019
-  Type: Kernel Image
+  Type: Flat Device Tree
   Compression:  uncompressed
   Data Size:9398 Bytes = 9.18 KiB = 0.01 MiB
   Architecture: ARM
-  OS:   Unknown OS
-  Load Address: unavailable
-  Entry Point:  unavailable
  Image 2 (ramdisk-1)
   Description:  unavailable
   Created:  Thu Sep 12 23:23:16 2019
   Type: RAMDisk Image
   Compression:  Unknown Compression
   Data Size:760672 Bytes = 742.84 KiB = 0.73 MiB
-  Architecture: Unknown Architecture
+  Architecture: ARM
   OS:   Linux
   Load Address: unavailable
   Entry Point:  unavailable
  Default Configuration: 'conf-1'
  Configuration 0 (conf-1)
   Description:  zynq-microzed
   Kernel:   kernel-1
   Init Ramdisk: ramdisk-1
   FDT:  fdt-1
   Loadables:kernel-1

Signed-off-by: Michal Sojka 
---
 tools/fit_image.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tools/fit_image.c b/tools/fit_image.c
index 5aca634b5e..0201cc44d8 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -229,6 +229,7 @@ static int fit_write_images(struct image_tool_params 
*params, char *fdt)
for (cont = params->content_head; cont; cont = cont->next) {
if (cont->type != IH_TYPE_FLATDT)
continue;
+   typename = genimg_get_type_short_name(cont->type);
snprintf(str, sizeof(str), "%s-%d", FIT_FDT_PROP, ++upto);
fdt_begin_node(fdt, str);
 
@@ -253,6 +254,8 @@ static int fit_write_images(struct image_tool_params 
*params, char *fdt)
fdt_property_string(fdt, FIT_TYPE_PROP, FIT_RAMDISK_PROP);
fdt_property_string(fdt, FIT_OS_PROP,
genimg_get_os_short_name(params->os));
+   fdt_property_string(fdt, FIT_ARCH_PROP,
+   genimg_get_arch_short_name(params->arch));
 
ret = fdt_property_file(params, fdt, FIT_DATA_PROP,
params->fit_ramdisk);
-- 
2.23.0

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Re: [U-Boot] [PATCH] mtd: nand: omap_gpmc: Make ready/busy pins configurable

2015-02-17 Thread Michal Sojka 
Hi Stefan,

On Wed, Feb 11 2015, Stefan Roese wrote:
 On 10.02.2015 14:21, Michal Sojka wrote:
 Commit fb384c4720ca7496775d6578f184bf628db73456 introduced the use of
 WAIT0 pin for determining whether the NAND is ready or not. This only
 works if all NAND chips are connected to WAIT0. If some chips are
 connected to the other available pin WAIT1, nand_wait() does not really
 wait and prints a WARN_ON message.

 This patch allows the board to provide configuration of which chip is
 connected to which WAITx signal. For example, one can define in
 include/configs/foo.h:

  #define CONFIG_NAND_OMAP_GPMC_WSCFG 0,0,1,1

 This would mean that chips using to CS0 and 1 are connected to WAIT0 and
 chips with CS2 and 3 are connected to WAIT1.

 Signed-off-by: Michal Sojka so...@merica.cz

 Cc: Tom Rini tr...@ti.com
 Cc: Stefan Roese s...@denx.de
 ---
   drivers/mtd/nand/omap_gpmc.c | 13 +++--
   1 file changed, 11 insertions(+), 2 deletions(-)

 diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
 index 459904d..57fc7b9 100644
 --- a/drivers/mtd/nand/omap_gpmc.c
 +++ b/drivers/mtd/nand/omap_gpmc.c
 @@ -36,7 +36,8 @@ static __maybe_unused struct nand_ecclayout omap_ecclayout;
   struct omap_nand_info {
  struct bch_control *control;
  enum omap_ecc ecc_scheme;
 -int cs;
 +uint8_t cs;
 +uint8_t ws; /* wait status pin (0,1) */
   };

   /* We are wasting a bit of memory but al least we are safe */
 @@ -76,7 +77,9 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, 
 int32_t cmd,
   /* Check wait pin as dev ready indicator */
   static int omap_dev_ready(struct mtd_info *mtd)
   {
 -return gpmc_cfg-status  (1  8);
 +register struct nand_chip *this = mtd-priv;
 +struct omap_nand_info *info = this-priv;
 +return gpmc_cfg-status  (1  (8 + info-ws));
   }

   /*
 @@ -853,6 +856,12 @@ int board_nand_init(struct nand_chip *nand)
  nand-IO_ADDR_W = (void __iomem *)gpmc_cfg-cs[cs].nand_cmd;
  omap_nand_info[cs].control = NULL;
  omap_nand_info[cs].cs = cs;
 +#if !defined(CONFIG_NAND_OMAP_GPMC_WSCFG)
 +omap_nand_info[cs].ws = 0;
 +#else
 +int8_t ws[CONFIG_SYS_MAX_NAND_DEVICE] = { CONFIG_NAND_OMAP_GPMC_WSCFG };

 Doesn't this declaration trigger a compilation warning?

Not with gcc-4.8.3 that we use.

 +omap_nand_info[cs].ws = ws[cs];
 +#endif

 I've attached a new version of this patch. It removed the ifdef from the
 code. Please take a look at it and let me know what you think.

Yes, it's better and it works for us. Just one point - what about making
the variable const as in the patch below?

Thanks,
-Michal

-8--
Commit fb384c4720ca7496775d6578f184bf628db73456 introduced the use of
WAIT0 pin for determining whether the NAND is ready or not. This only
works if all NAND chips are connected to WAIT0. If some chips are
connected to the other available pin WAIT1, nand_wait() does not really
wait and prints a WARN_ON message.

This patch allows the board to provide configuration of which chip is
connected to which WAITx signal. For example, one can define in
include/configs/foo.h:

#define CONFIG_NAND_OMAP_GPMC_WSCFG 0,0,1,1

This would mean that chips using to CS0 and 1 are connected to WAIT0 and
chips with CS2 and 3 are connected to WAIT1.

Signed-off-by: Michal Sojka so...@merica.cz

Cc: Tom Rini tr...@ti.com
Cc: Stefan Roese s...@denx.de
---
 drivers/mtd/nand/omap_gpmc.c | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 459904d..4f9120d 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -30,13 +30,22 @@ static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 
0xed, 0x93, 0x9a, 0xc2,
 static uint8_t cs_next;
 static __maybe_unused struct nand_ecclayout omap_ecclayout;
 
+#if defined(CONFIG_NAND_OMAP_GPMC_WSCFG)
+static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] =
+   { CONFIG_NAND_OMAP_GPMC_WSCFG };
+#else
+/* wscfg is preset to zero since its a static variable */
+static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE];
+#endif
+
 /*
  * Driver configurations
  */
 struct omap_nand_info {
struct bch_control *control;
enum omap_ecc ecc_scheme;
-   int cs;
+   uint8_t cs;
+   uint8_t ws; /* wait status pin (0,1) */
 };
 
 /* We are wasting a bit of memory but al least we are safe */
@@ -76,7 +85,9 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t 
cmd,
 /* Check wait pin as dev ready indicator */
 static int omap_dev_ready(struct mtd_info *mtd)
 {
-   return gpmc_cfg-status  (1  8);
+   register struct nand_chip *this = mtd-priv;
+   struct omap_nand_info *info = this-priv;
+   return gpmc_cfg-status  (1  (8 + info-ws));
 }
 
 /*
@@ -853,6 +864,7 @@ int board_nand_init(struct nand_chip *nand)
nand-IO_ADDR_W = (void __iomem *)gpmc_cfg-cs[cs].nand_cmd

[U-Boot] [PATCH] mtd: nand: omap_gpmc: Make ready/busy pins configurable

2015-02-10 Thread Michal Sojka 
Commit fb384c4720ca7496775d6578f184bf628db73456 introduced the use of
WAIT0 pin for determining whether the NAND is ready or not. This only
works if all NAND chips are connected to WAIT0. If some chips are
connected to the other available pin WAIT1, nand_wait() does not really
wait and prints a WARN_ON message.

This patch allows the board to provide configuration of which chip is
connected to which WAITx signal. For example, one can define in
include/configs/foo.h:

#define CONFIG_NAND_OMAP_GPMC_WSCFG 0,0,1,1

This would mean that chips using to CS0 and 1 are connected to WAIT0 and
chips with CS2 and 3 are connected to WAIT1.

Signed-off-by: Michal Sojka so...@merica.cz

Cc: Tom Rini tr...@ti.com
Cc: Stefan Roese s...@denx.de
---
 drivers/mtd/nand/omap_gpmc.c | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 459904d..57fc7b9 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -36,7 +36,8 @@ static __maybe_unused struct nand_ecclayout omap_ecclayout;
 struct omap_nand_info {
struct bch_control *control;
enum omap_ecc ecc_scheme;
-   int cs;
+   uint8_t cs;
+   uint8_t ws; /* wait status pin (0,1) */
 };
 
 /* We are wasting a bit of memory but al least we are safe */
@@ -76,7 +77,9 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t 
cmd,
 /* Check wait pin as dev ready indicator */
 static int omap_dev_ready(struct mtd_info *mtd)
 {
-   return gpmc_cfg-status  (1  8);
+   register struct nand_chip *this = mtd-priv;
+   struct omap_nand_info *info = this-priv;
+   return gpmc_cfg-status  (1  (8 + info-ws));
 }
 
 /*
@@ -853,6 +856,12 @@ int board_nand_init(struct nand_chip *nand)
nand-IO_ADDR_W = (void __iomem *)gpmc_cfg-cs[cs].nand_cmd;
omap_nand_info[cs].control = NULL;
omap_nand_info[cs].cs = cs;
+#if !defined(CONFIG_NAND_OMAP_GPMC_WSCFG)
+   omap_nand_info[cs].ws = 0;
+#else
+   int8_t ws[CONFIG_SYS_MAX_NAND_DEVICE] = { CONFIG_NAND_OMAP_GPMC_WSCFG };
+   omap_nand_info[cs].ws = ws[cs];
+#endif
nand-priv  = omap_nand_info[cs];
nand-cmd_ctrl  = omap_nand_hwcontrol;
nand-options   |= NAND_NO_PADDING | NAND_CACHEPRG;
-- 
2.1.4

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