Re: [PATCH 3/3] sunxi: H616: Add OrangePi Zero 3 board support
On 26.11.2023 03:23, Andre Przywara wrote: Hi Andre, On Sat, 25 Nov 2023 20:43:12 +0300 Mikhail Kalashnikov wrote: Hi Mikhail, Hi Andre! Thanks for your patches. I started checking and noticed that USB storage was not working: => usb reset resetting USB... Bus usb@520: USB EHCI 1.00 Bus usb@5200400: USB OHCI 1.0 scanning bus usb@520 for devices... 1 USB Device(s) found scanning bus usb@5200400 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found => usb storage No storage devices, perhaps not 'usb start'ed..? Ah, thanks for the report, seems I didn't even test this! So digging around I figured it's working in Linux, and it's the right USB port, but we are missing the VBUS power switch, which is a GPIO controlled regulator. There are pending patches to pick this from the devicetree[1], but we are not there yet, so we need: CONFIG_USB1_VBUS_PIN="PC16" With that usb storage work. Also I successfully loaded u-boot image to spi with command: sunxi-fel -p spiflash-write 0 u-boot-sunxi-with-spl.bin 100% [] 828 kB, 74.7 kB/s After that u-boot successful started from spi. Best regards, Mikhail in the defconfig, for now. I will update the file. The same is actually missing from the OrangePi Zero2 defconfig, I will send a patch ASAP. Otherwise my OpiZero3 (4GB) board looks working. Ethernet works with my 10 Mbps usb-dongle. sf probe detect spi nor flash: => sf probe SF: Detected zb25vq128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB Loading the kernel and running the operating system (from microsd) also without problems. Tested-by: Mikhail Kalashnikov Great, thanks for the tag! Cheers, Andre On 14.11.2023 04:31, Andre Przywara wrote: The OrangePi Zero 3 is a small development board featuring the Allwinner H618 SoC, shipping with up to 4GB of DRAM, Gigabit Ethernet, a micro-HDMI connector and two USB sockets. The board uses LPDDR4 DRAM and an X-Powers AXP313a PMIC, support for which was recently added to U-Boot. Add a defconfig file selecting the right drivers and DRAM options. Since the .dts file was synced from the Linux kernel repo already, we just need to add one line to the Makefile to actually build the .dtb. The DRAM parameters were derived from the values found in the BSP DRAM drivers on the SPI NOR flash. Signed-off-by: Andre Przywara --- arch/arm/dts/Makefile| 1 + board/sunxi/MAINTAINERS | 5 + configs/orangepi_zero3_defconfig | 30 ++ 3 files changed, 36 insertions(+) create mode 100644 configs/orangepi_zero3_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1be08c5fdc2..5fc888680b3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -835,6 +835,7 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \ sun50i-h6-tanix-tx6-mini.dtb dtb-$(CONFIG_MACH_SUN50I_H616) += \ sun50i-h616-orangepi-zero2.dtb \ + sun50i-h618-orangepi-zero3.dtb \ sun50i-h616-x96-mate.dtb dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-amarula-relic.dtb \ diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 00614372119..f556857a391 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -455,6 +455,11 @@ M: Jernej Skrabec S: Maintained F: configs/orangepi_zero2_defconfig +ORANGEPI ZERO 3 BOARD +M: Andre Przywara +S: Maintained +F: configs/orangepi_zero3_defconfig + ORANGEPI PC 2 BOARD M: Andre Przywara S: Maintained diff --git a/configs/orangepi_zero3_defconfig b/configs/orangepi_zero3_defconfig new file mode 100644 index 000..e59044f6639 --- /dev/null +++ b/configs/orangepi_zero3_defconfig @@ -0,0 +1,30 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-orangepi-zero3" +CONFIG_SPL=y +CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707 +CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e +CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e +CONFIG_DRAM_SUN50I_H616_ODT_EN=0x +CONFIG_DRAM_SUN50I_H616_TPR6=0x4400 +CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6663 +CONFIG_DRAM_SUN50I_H616_TPR11=0x24242624 +CONFIG_DRAM_SUN50I_H616_TPR12=0x0f0f100f +CONFIG_MACH_SUN50I_H616=y +CONFIG_SUNXI_DRAM_H616_LPDDR4=y +CONFIG_R_I2C_ENABLE=y +CONFIG_SPL_SPI_SUNXI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=40 +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_SUN8I_EMAC=y +CONFIG_AXP313_POWER=y +CONFIG_SPI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y
Re: [PATCH 3/3] sunxi: H616: Add OrangePi Zero 3 board support
Hi Andre! Thanks for your patches. I started checking and noticed that USB storage was not working: => usb reset resetting USB... Bus usb@520: USB EHCI 1.00 Bus usb@5200400: USB OHCI 1.0 scanning bus usb@520 for devices... 1 USB Device(s) found scanning bus usb@5200400 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found => usb storage No storage devices, perhaps not 'usb start'ed..? Otherwise my OpiZero3 (4GB) board looks working. Ethernet works with my 10 Mbps usb-dongle. sf probe detect spi nor flash: => sf probe SF: Detected zb25vq128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB Loading the kernel and running the operating system (from microsd) also without problems. Tested-by: Mikhail Kalashnikov On 14.11.2023 04:31, Andre Przywara wrote: The OrangePi Zero 3 is a small development board featuring the Allwinner H618 SoC, shipping with up to 4GB of DRAM, Gigabit Ethernet, a micro-HDMI connector and two USB sockets. The board uses LPDDR4 DRAM and an X-Powers AXP313a PMIC, support for which was recently added to U-Boot. Add a defconfig file selecting the right drivers and DRAM options. Since the .dts file was synced from the Linux kernel repo already, we just need to add one line to the Makefile to actually build the .dtb. The DRAM parameters were derived from the values found in the BSP DRAM drivers on the SPI NOR flash. Signed-off-by: Andre Przywara --- arch/arm/dts/Makefile| 1 + board/sunxi/MAINTAINERS | 5 + configs/orangepi_zero3_defconfig | 30 ++ 3 files changed, 36 insertions(+) create mode 100644 configs/orangepi_zero3_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1be08c5fdc2..5fc888680b3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -835,6 +835,7 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \ sun50i-h6-tanix-tx6-mini.dtb dtb-$(CONFIG_MACH_SUN50I_H616) += \ sun50i-h616-orangepi-zero2.dtb \ + sun50i-h618-orangepi-zero3.dtb \ sun50i-h616-x96-mate.dtb dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-amarula-relic.dtb \ diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 00614372119..f556857a391 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -455,6 +455,11 @@ M: Jernej Skrabec S:Maintained F:configs/orangepi_zero2_defconfig +ORANGEPI ZERO 3 BOARD +M: Andre Przywara +S: Maintained +F: configs/orangepi_zero3_defconfig + ORANGEPI PC 2 BOARD M:Andre Przywara S:Maintained diff --git a/configs/orangepi_zero3_defconfig b/configs/orangepi_zero3_defconfig new file mode 100644 index 000..e59044f6639 --- /dev/null +++ b/configs/orangepi_zero3_defconfig @@ -0,0 +1,30 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-orangepi-zero3" +CONFIG_SPL=y +CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707 +CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e +CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e +CONFIG_DRAM_SUN50I_H616_ODT_EN=0x +CONFIG_DRAM_SUN50I_H616_TPR6=0x4400 +CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6663 +CONFIG_DRAM_SUN50I_H616_TPR11=0x24242624 +CONFIG_DRAM_SUN50I_H616_TPR12=0x0f0f100f +CONFIG_MACH_SUN50I_H616=y +CONFIG_SUNXI_DRAM_H616_LPDDR4=y +CONFIG_R_I2C_ENABLE=y +CONFIG_SPL_SPI_SUNXI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=40 +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_SUN8I_EMAC=y +CONFIG_AXP313_POWER=y +CONFIG_SPI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y
Re: orangepi zero3
On 24.11.2023 03:11, Andre Przywara wrote:
On Thu, 23 Nov 2023 11:12:25 -0800
Stephen Graf wrote:
Hi Stephen,
Thank you for your reply.
Thanks for coming back. Please keep the list(s) on CC:, as this is also
interesting for others, and more eyes help to find issues faster.
CC:ing Piotr and Mikhail, who were debugging the LPDDR4 DRAM setup
before.
I built u-boot with the proposed changes and it seems to work. It does
however report "DRAM: 2048 MiB" although I have a board with only 1G.
Ah, that's a good report! I actually saw the same issue (reporting 8GB
instead of 4GB), and my hunch is that it's related to some missing
barriers or delays, as seen on other boards.
Can you try to add a "dsb();" to the beginning of
arch/arm/mach-sunxi/dram_helpers.c:mctl_mem_matches(), before the first
writel()?
I am still not convinced this is the right place to put the barrier,
but it would confirm that this is the issue.
Also I didn't see this effect consistently, so did this happen for you
every time?
I tried using an additional barrier as you described:
diff --git a/arch/arm/mach-sunxi/dram_helpers.c
b/arch/arm/mach-sunxi/dram_helpers.c
index cdf2750..16938fa 100644
--- a/arch/arm/mach-sunxi/dram_helpers.c
+++ b/arch/arm/mach-sunxi/dram_helpers.c
@@ -34,6 +34,7 @@ bool mctl_mem_matches(u32 offset)
{
/* Try to write different values to RAM at two addresses */
writel(0, CFG_SYS_SDRAM_BASE);
+ dsb();
writel(0xaa55aa55, (ulong)CFG_SYS_SDRAM_BASE + offset);
dsb();
/* Check if the same value is actually observed when reading back */
After this I did not notice any problems with incorrect configuration.
As I understand it, the problem occurs most often during a hot plug.
Another thing you could try is to increase the voltage to 1150mV, this
is what Piotr needed for reliable operation.
When I built u-boot with the config that I used it reported 1G
correctly. The Zunlong distros do have different images for various RAM
configurations.
Yeah, I saw this, and I hope we can avoid this. I am not sure if you
are the first one with a 1GB board, so your testing is definitely
helpful.
I do not know enough about the details to determine which differences in
the two configs result in the change.
I am more than willing to test and report if someone can direct me a bit.
sysadmin@ubuntu:~/defconfgs$ diff sg.txt andre.txt
(please use "diff -u", that's easier to read and people are more used
to its output style)
9d8
< CONFIG_DRAM_SUN50I_H616_TPR0=0x0
11,13c10,12
< CONFIG_DRAM_SUN50I_H616_TPR10=0x402f0663
< CONFIG_DRAM_SUN50I_H616_TPR11=0x24242323
< CONFIG_DRAM_SUN50I_H616_TPR12=0x0e0e0e0e
---
> CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6663
> CONFIG_DRAM_SUN50I_H616_TPR11=0x24242624
> CONFIG_DRAM_SUN50I_H616_TPR12=0x0f0f100f
I don't think those minor timing differences matter much, but you can
try to experiment with both set of values.
16d14
< CONFIG_DRAM_CLK=792
Not specifying DRAM_CLK means it uses the default 720 MHz. In the past
lowering the DRAM frequency was an easy way to stabilise the DRAM
setup, even though this might somewhat paper over other issues.
25c23
< CONFIG_SPI_FLASH_MACRONIX=y
---
> CONFIG_SPI_FLASH_ZBIT=y
Please double check, but I think all new OrangePi boards now use a zBIT
flash chip? Should have a small "Z" like logo on that 8 pin chip with
the large pins on top.
27a26
> CONFIG_AXP313_POWER=y
32,34c31
< CONFIG_AXP313_POWER=y
< CONFIG_AXP_DCDC3_VOLT=1100
1100mV is the default, so putting exactly this value in doesn't change
anything.
< CONFIG_CMD_BOOTZ=y
Why do you need bootz? I don't think this doing anything useful in
mainline U-Boot. Don't know if OrangePi was just confused and had an
actual use case for this.
---
>
A second issue that I discovered with both builds is that the Ethernet
does not come up on a 1Gb switch, but works on a 100Mb switch.
There is a pending patch for mainline Linux, can you try to apply those
DT changes to U-Boot's DT copy and see if that helps?
https://lore.kernel.org/linux-sunxi/2303336.ElGaqSPkdT@jernej-laptop/T/#m77ee30923cb0351f2d701a463a940dc7c00fa8b7
Cheers,
Andre
Output from the patch defconfig (1Gb LAN):
U-Boot SPL 2024.01-rc3-9-g9e53e45292-dirty (Nov 23 2023 - 18:08:24
+)
DRAM: 2048 MiB
Trying to boot from MMC1
NOTICE: BL31: v2.10.0 (debug):v2.10.0
NOTICE: BL31: Built : 18:07:18, Nov 23 2023
NOTICE: BL31: Detected Allwinner H616 SoC (1823)
NOTICE: BL31: Found U-Boot DTB at 0x4a0b2750, model: OrangePi Zero3
INFO: ARM GICv2 driver initialized
INFO: Configuring SPC Controller
INFO: PMIC: Probing AXP305 on RSB
ERROR: RSB: set run-time address: 0x10003
INFO: Could not init RSB: -65539
INFO: BL31: Platform setup done
INFO: BL31: Initializing runtime services
INFO: BL31: cortex_a53: CPU workaround for erratum 855873 was applied
INFO: BL31: cortex_a53: CPU workaround for erratum 1530924 was applied
INFO: PSCI: Suspend is unavailable
INFO: BL31: Preparing
[PATCH v4 1/1] sunxi: H616: add LPDDR4 DRAM support
From: iuncuim
The H616 SoC family has support for several types of DRAM: DDR3,
LPDDR3, DDR4 and LPDDR4.
At the moment, the driver only supports DDR3 and LPDDR3 memory.
Let's extend the driver to support the LPDDR4 memory. This type
of memory widely used in device with T507(-H) SoC and new orangepi
zero3 with H618.
The compatibility with T507 is not yet complete, because there
is difference in the phy_init array.
The LPDDR4-2133 timings correspond to DRAM Rayson RS1G32LO4D2BDS-53BT
found on the NOR SPI from the Orangepi Zero 3 4GB.
Signed-off-by: Mikhail Kalashnikov
---
.../include/asm/arch-sunxi/dram_sun50i_h616.h | 2 +
arch/arm/mach-sunxi/Kconfig | 17 ++
arch/arm/mach-sunxi/dram_sun50i_h616.c| 218 ++
arch/arm/mach-sunxi/dram_timings/Makefile | 1 +
.../dram_timings/h616_lpddr4_2133.c | 95
5 files changed, 294 insertions(+), 39 deletions(-)
create mode 100644 arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
index 11774deded..a8fdda124a 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
@@ -130,6 +130,7 @@ check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240);
#define MSTR_DEVICETYPE_LPDDR2 BIT(2)
#define MSTR_DEVICETYPE_LPDDR3 BIT(3)
#define MSTR_DEVICETYPE_DDR4 BIT(4)
+#define MSTR_DEVICETYPE_LPDDR4 BIT(5)
#define MSTR_DEVICETYPE_MASK GENMASK(5, 0)
#define MSTR_2TMODEBIT(10)
#define MSTR_BUSWIDTH_FULL (0 << 12)
@@ -154,6 +155,7 @@ struct dram_para {
u32 odt_en;
u32 tpr0;
u32 tpr2;
+ u32 tpr6;
u32 tpr10;
u32 tpr11;
u32 tpr12;
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 9d5df2c102..e65bcb36a2 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -85,6 +85,12 @@ config DRAM_SUN50I_H616_TPR2
help
TPR2 value from vendor DRAM settings.
+config DRAM_SUN50I_H616_TPR6
+ hex "H616 DRAM TPR6 parameter"
+ default 0x3300c080
+ help
+ TPR6 value from vendor DRAM settings.
+
config DRAM_SUN50I_H616_TPR10
hex "H616 DRAM TPR10 parameter"
help
@@ -441,6 +447,9 @@ config SUNXI_DRAM_DDR2
config SUNXI_DRAM_LPDDR3
bool
+config SUNXI_DRAM_LPDDR4
+ bool
+
choice
prompt "DRAM Type and Timing"
default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
@@ -484,6 +493,14 @@ config SUNXI_DRAM_H616_LPDDR3
This option is the LPDDR3 timing used by the stock boot0 by
Allwinner.
+config SUNXI_DRAM_H616_LPDDR4
+ bool "LPDDR4 DRAM chips on the H616 DRAM controller"
+ select SUNXI_DRAM_LPDDR4
+ depends on DRAM_SUN50I_H616
+ help
+ This option is the LPDDR4 timing used by the stock boot0 by
+ Allwinner.
+
config SUNXI_DRAM_H616_DDR3_1333
bool "DDR3-1333 boot0 timings on the H616 DRAM controller"
select SUNXI_DRAM_DDR3
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index ba5659d409..e7e39d3f6a 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -6,8 +6,8 @@
* unknown. That's why this driver has plenty of magic numbers. Some
* meaning was nevertheless deduced from strings found in boot0 and
* known meaning of some dram parameters.
- * This driver only supports DDR3 memory and omits logic for all
- * other supported types supported by hardware.
+ * This driver supports DDR3, LPDDR3 and LPDDR4 memory. There is no
+ * DDR4 support yet.
*
* (C) Copyright 2020 Jernej Skrabec
*
@@ -238,6 +238,11 @@ static const u8 phy_init[] = {
0x08, 0x01, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07,
0x17, 0x19, 0x1a
+#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4)
+ 0x02, 0x00, 0x17, 0x05, 0x04, 0x19, 0x06, 0x07,
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01,
+ 0x18, 0x03, 0x1a
#endif
};
@@ -246,8 +251,20 @@ static void mctl_phy_configure_odt(const struct dram_para
*para)
{
uint32_t val_lo, val_hi;
+ /*
+* This part should be applicable to all memory types, but is
+* usually found in LPDDR4 bootloaders. Therefore, we will leave
+* only for this type of memory.
+*/
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR4) {
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x390, BIT(5), BIT(4));
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x3d0, BIT(5), BIT(4));
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x410, BIT(5), BIT(4));
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x450, BIT(5), BIT(4));
+ }
+
[PATCH v4 0/1] sunxi: H616: add LPDDR4 support
From: iuncuim At the moment, the driver only supports DDR3 and LPDDR3 memory. Add support for a new type DRAM. These changes have been successfully tested by me with orangepi zero3 4GB (DRAM: Rayson RS1G32LO4D2BDS-53BT). This patch should be applied after this: https://lore.kernel.org/all/20231014170236.16211-1-andre.przyw...@arm.com/ Changes from v3: * added LPDDR4 part for mctl_phy_read_training() * added the new part in mctl_phy_configure_odt() as LPDDR4 specific to avoid possible problems with existing devices https://lore.kernel.org/u-boot/20231104062248.32938-1-iunc...@gmail.com/ Changes from v2: * added default value for TPR6 parameter * added panic for unsupported DRAM types in switch/case conditions * added new line at the end of the timings file, changed the description * added a few small missing parts obtained from boot0 https://lore.kernel.org/u-boot/20231016053441.3197087-2-iunc...@gmail.com/ Changes from v1: * replaced the phy_init array with one compatible with opizero3 * added DRAM TPR6 parameter * adaptation to new mctl_phy_configure_odt() * added timings for the board orangepi zero3 4GB https://lore.kernel.org/u-boot/20230729111331.173768-2-iunc...@gmail.com/ Signed-off-by: Mikhail Kalashnikov iuncuim (1): sunxi: H616: add LPDDR4 support .../include/asm/arch-sunxi/dram_sun50i_h616.h | 2 + arch/arm/mach-sunxi/Kconfig | 17 ++ arch/arm/mach-sunxi/dram_sun50i_h616.c| 218 ++ arch/arm/mach-sunxi/dram_timings/Makefile | 1 + .../dram_timings/h616_lpddr4_2133.c | 95 5 files changed, 294 insertions(+), 39 deletions(-) create mode 100644 arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c -- 2.42.0
Re: [PATCH v3 1/1] sunxi: H616: add LPDDR4 DRAM support
Hi Jernej,
On 04.11.2023 11:31, Jernej Škrabec wrote:
Hi Mikhail,
I have some notes on LPDDR4 from a long time ago. It mostly matches to your
code, but please take a look at comments below.
Note that I have extra code, not included in this patch, for
mctl_phy_read_training(). At the very beginning, before any other register
access is done, this should be added:
if (para->type == SUNXI_DRAM_TYPE_LPDDR4) {
writel(0, SUNXI_DRAM_PHY0_BASE + 0x800);
writel(0, SUNXI_DRAM_PHY0_BASE + 0x81c);
}
Maybe that will help with other LPDDR4 boards?
Current H618 and t507 boards do not yet require this feature. Yes, this
feature may be required for future devices. I will add it in the next
version.
@@ -246,8 +251,13 @@ static void mctl_phy_configure_odt(const struct
dram_para *para) {
uint32_t val_lo, val_hi;
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x390, BIT(5), BIT(4));
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x3d0, BIT(5), BIT(4));
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x410, BIT(5), BIT(4));
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x450, BIT(5), BIT(4));
I don't have above block. Something from newer libdram? Is it applicable to
all DRAM types?
This function is present in the RE code for all types of memory. Binary
file dumped from orangepi zero3 nor spi.I paid attention to this area
code when comparing the sunxi u-boot dump (md.l) with the resulting
mainline u-boot. Now I checked my tvbox with H616 and LPDDR3 and it
doesn't have this block. In this case, maybe it would be better to make
it only for devices with LPDDR4?
+ case SUNXI_DRAM_TYPE_LPDDR4:
+ writel(0x0, _ctl->mrctrl1);
+ writel(0x8030, _ctl->mrctrl0);
+ mctl_await_completion(_ctl->mrctrl0, BIT(31), 0);
I don't have above block. Maybe difference from newer version of libdram
code?
This block was present in the sunxi t507 binaries for which the driver
was originally intended. Now I checked original dump from orangepi zero3 NOR SPI.
This is also present here.
writel(reg_val, _ctl->odtcfg);
writel(reg_val, _ctl->unk_0x2240);
writel(reg_val, _ctl->unk_0x3240);
I have extra "writel(BIT(31), _com->cr);" after this block for all DRAM
types. Not sure if it changes anything.
Looks like this has already been done in previous patches.
+ u16 trfc= ns_to_t(280);
My notes say 180 instead of 280. Did you check if register value matches if
booted with boot0
I booted from NOR SPI of the sunxi u-boot and made a dump with md.l
0x047fb064. It show me value 0030006f, where 0x6f trfc value. Based on
the transformation function - 111*1000/(792/2)=280,30(30) So, obtained
value looks correct. Best regards,
Mikhail
[PATCH v3 1/1] sunxi: H616: add LPDDR4 DRAM support
From: iuncuim
The H616 SoC family has support for several types of DRAM: DDR3,
LPDDR3, DDR4 and LPDDR4.
At the moment, the driver only supports DDR3 and LPDDR3 memory.
Let's extend the driver to support the LPDDR4 memory. This type
of memory widely used in device with T507(-H) SoC and new orangepi
zero3 with H618.
The compatibility with T507 is not yet complete, because there
is difference in the phy_init array.
The LPDDR4-2133 timings correspond to DRAM Rayson RS1G32LO4D2BDS-53BT
found on the NOR SPI from the Orangepi Zero 3 4GB.
Signed-off-by: Mikhail Kalashnikov
---
.../include/asm/arch-sunxi/dram_sun50i_h616.h | 2 +
arch/arm/mach-sunxi/Kconfig | 17 ++
arch/arm/mach-sunxi/dram_sun50i_h616.c| 197 ++
arch/arm/mach-sunxi/dram_timings/Makefile | 1 +
.../dram_timings/h616_lpddr4_2133.c | 95 +
5 files changed, 277 insertions(+), 35 deletions(-)
create mode 100644 arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
index 11774deded..a8fdda124a 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
@@ -130,6 +130,7 @@ check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240);
#define MSTR_DEVICETYPE_LPDDR2 BIT(2)
#define MSTR_DEVICETYPE_LPDDR3 BIT(3)
#define MSTR_DEVICETYPE_DDR4 BIT(4)
+#define MSTR_DEVICETYPE_LPDDR4 BIT(5)
#define MSTR_DEVICETYPE_MASK GENMASK(5, 0)
#define MSTR_2TMODEBIT(10)
#define MSTR_BUSWIDTH_FULL (0 << 12)
@@ -154,6 +155,7 @@ struct dram_para {
u32 odt_en;
u32 tpr0;
u32 tpr2;
+ u32 tpr6;
u32 tpr10;
u32 tpr11;
u32 tpr12;
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 9d5df2c102..e65bcb36a2 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -85,6 +85,12 @@ config DRAM_SUN50I_H616_TPR2
help
TPR2 value from vendor DRAM settings.
+config DRAM_SUN50I_H616_TPR6
+ hex "H616 DRAM TPR6 parameter"
+ default 0x3300c080
+ help
+ TPR6 value from vendor DRAM settings.
+
config DRAM_SUN50I_H616_TPR10
hex "H616 DRAM TPR10 parameter"
help
@@ -441,6 +447,9 @@ config SUNXI_DRAM_DDR2
config SUNXI_DRAM_LPDDR3
bool
+config SUNXI_DRAM_LPDDR4
+ bool
+
choice
prompt "DRAM Type and Timing"
default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
@@ -484,6 +493,14 @@ config SUNXI_DRAM_H616_LPDDR3
This option is the LPDDR3 timing used by the stock boot0 by
Allwinner.
+config SUNXI_DRAM_H616_LPDDR4
+ bool "LPDDR4 DRAM chips on the H616 DRAM controller"
+ select SUNXI_DRAM_LPDDR4
+ depends on DRAM_SUN50I_H616
+ help
+ This option is the LPDDR4 timing used by the stock boot0 by
+ Allwinner.
+
config SUNXI_DRAM_H616_DDR3_1333
bool "DDR3-1333 boot0 timings on the H616 DRAM controller"
select SUNXI_DRAM_DDR3
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index ba5659d409..185f35850a 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -238,6 +238,11 @@ static const u8 phy_init[] = {
0x08, 0x01, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07,
0x17, 0x19, 0x1a
+#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4)
+ 0x02, 0x00, 0x17, 0x05, 0x04, 0x19, 0x06, 0x07,
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01,
+ 0x18, 0x03, 0x1a
#endif
};
@@ -246,8 +251,13 @@ static void mctl_phy_configure_odt(const struct dram_para
*para)
{
uint32_t val_lo, val_hi;
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x390, BIT(5), BIT(4));
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x3d0, BIT(5), BIT(4));
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x410, BIT(5), BIT(4));
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x450, BIT(5), BIT(4));
+
val_lo = para->dx_dri;
- val_hi = para->dx_dri;
+ val_hi = (para->type == SUNXI_DRAM_TYPE_LPDDR4) ? 0x04040404 :
para->dx_dri;
writel_relaxed(MASK_BYTE(val_lo, 0), SUNXI_DRAM_PHY0_BASE + 0x388);
writel_relaxed(MASK_BYTE(val_hi, 0), SUNXI_DRAM_PHY0_BASE + 0x38c);
writel_relaxed(MASK_BYTE(val_lo, 1), SUNXI_DRAM_PHY0_BASE + 0x3c8);
@@ -265,7 +275,7 @@ static void mctl_phy_configure_odt(const struct dram_para
*para)
writel_relaxed(MASK_BYTE(val_hi, 1), SUNXI_DRAM_PHY0_BASE + 0x34c);
val_lo = (para->type == SUNXI_DRAM_TYPE_LPDDR3) ? 0 : para->dx_odt;
- val_hi = para->dx_odt;
+ val_hi = (para->type == SUNXI_DRAM_TYPE_LPDDR4) ? 0 : para->dx_odt;
writel_
[PATCH v3 0/1] sunxi: H616: add LPDDR4 support
From: iuncuim At the moment, the driver only supports DDR3 and LPDDR3 memory. Add support for a new type DRAM. These changes have been successfully tested by me with orangepi zero3 4GB (DRAM: Rayson RS1G32LO4D2BDS-53BT). This patch should be applied after this: https://lore.kernel.org/all/20231014170236.16211-1-andre.przyw...@arm.com/ Changes from v2: * added default value for TPR6 parameter * added panic for unsupported DRAM types in switch/case conditions * added new line at the end of the timings file, changed the description * added a few small missing parts obtained from boot0 https://lore.kernel.org/u-boot/20231016053441.3197087-2-iunc...@gmail.com/ Changes from v1: * replaced the phy_init array with one compatible with opizero3 * added DRAM TPR6 parameter * adaptation to new mctl_phy_configure_odt() * added timings for the board orangepi zero3 4GB https://lore.kernel.org/u-boot/20230729111331.173768-2-iunc...@gmail.com/ Signed-off-by: Mikhail Kalashnikov iuncuim (1): sunxi: H616: add LPDDR4 DRAM support .../include/asm/arch-sunxi/dram_sun50i_h616.h | 2 + arch/arm/mach-sunxi/Kconfig | 17 ++ arch/arm/mach-sunxi/dram_sun50i_h616.c| 197 ++ arch/arm/mach-sunxi/dram_timings/Makefile | 1 + .../dram_timings/h616_lpddr4_2133.c | 95 + 5 files changed, 277 insertions(+), 35 deletions(-) create mode 100644 arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c -- 2.42.0
[PATCH v2 1/1] sunxi: H616: add LPDDR4 DRAM support
From: iuncuim
The H616 SoC family has support for several types of DRAM: DDR3,
LPDDR3, DDR4 and LPDDR4.
At the moment, the driver only supports DDR3 and LPDDR3 memory.
Let's extend the driver to support the LPDDR4 memory. This type
of memory widely used in device with T507(-H) SoC and new orangepi
zero3 with H618.
The compatibility with T507 is not yet complete, because there
is difference in the phy_init array.
The LPDDR4-2133 timings correspond to DRAM Rayson RS1G32LO4D2BDS-53BT
found on the Orangepi Zero 3 4GB.
Signed-off-by: Mikhail Kalashnikov
---
.../include/asm/arch-sunxi/dram_sun50i_h616.h | 2 +
arch/arm/mach-sunxi/Kconfig | 16 ++
arch/arm/mach-sunxi/dram_sun50i_h616.c| 176 ++
arch/arm/mach-sunxi/dram_timings/Makefile | 1 +
.../dram_timings/h616_lpddr4_2133.c | 97 ++
5 files changed, 258 insertions(+), 34 deletions(-)
create mode 100644 arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
index 11774deded..a8fdda124a 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
@@ -130,6 +130,7 @@ check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240);
#define MSTR_DEVICETYPE_LPDDR2 BIT(2)
#define MSTR_DEVICETYPE_LPDDR3 BIT(3)
#define MSTR_DEVICETYPE_DDR4 BIT(4)
+#define MSTR_DEVICETYPE_LPDDR4 BIT(5)
#define MSTR_DEVICETYPE_MASK GENMASK(5, 0)
#define MSTR_2TMODEBIT(10)
#define MSTR_BUSWIDTH_FULL (0 << 12)
@@ -154,6 +155,7 @@ struct dram_para {
u32 odt_en;
u32 tpr0;
u32 tpr2;
+ u32 tpr6;
u32 tpr10;
u32 tpr11;
u32 tpr12;
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 9d5df2c102..71e2f40b9e 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -85,6 +85,11 @@ config DRAM_SUN50I_H616_TPR2
help
TPR2 value from vendor DRAM settings.
+config DRAM_SUN50I_H616_TPR6
+ hex "H616 DRAM TPR6 parameter"
+ help
+ TPR6 value from vendor DRAM settings.
+
config DRAM_SUN50I_H616_TPR10
hex "H616 DRAM TPR10 parameter"
help
@@ -441,6 +446,9 @@ config SUNXI_DRAM_DDR2
config SUNXI_DRAM_LPDDR3
bool
+config SUNXI_DRAM_LPDDR4
+ bool
+
choice
prompt "DRAM Type and Timing"
default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
@@ -484,6 +492,14 @@ config SUNXI_DRAM_H616_LPDDR3
This option is the LPDDR3 timing used by the stock boot0 by
Allwinner.
+config SUNXI_DRAM_H616_LPDDR4
+ bool "LPDDR4 DRAM chips on the H616 DRAM controller"
+ select SUNXI_DRAM_LPDDR4
+ depends on DRAM_SUN50I_H616
+ help
+ This option is the LPDDR4 timing used by the stock boot0 by
+ Allwinner.
+
config SUNXI_DRAM_H616_DDR3_1333
bool "DDR3-1333 boot0 timings on the H616 DRAM controller"
select SUNXI_DRAM_DDR3
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index ba5659d409..2c4b47bae7 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -238,6 +238,11 @@ static const u8 phy_init[] = {
0x08, 0x01, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07,
0x17, 0x19, 0x1a
+#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4)
+ 0x02, 0x00, 0x17, 0x05, 0x04, 0x19, 0x06, 0x07,
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01,
+ 0x18, 0x03, 0x1a
#endif
};
@@ -246,8 +251,13 @@ static void mctl_phy_configure_odt(const struct dram_para
*para)
{
uint32_t val_lo, val_hi;
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x390, BIT(5), BIT(4));
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x3d0, BIT(5), BIT(4));
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x410, BIT(5), BIT(4));
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x450, BIT(5), BIT(4));
+
val_lo = para->dx_dri;
- val_hi = para->dx_dri;
+ val_hi = (para->type == SUNXI_DRAM_TYPE_LPDDR4) ? 0x04040404 :
para->dx_dri;
writel_relaxed(MASK_BYTE(val_lo, 0), SUNXI_DRAM_PHY0_BASE + 0x388);
writel_relaxed(MASK_BYTE(val_hi, 0), SUNXI_DRAM_PHY0_BASE + 0x38c);
writel_relaxed(MASK_BYTE(val_lo, 1), SUNXI_DRAM_PHY0_BASE + 0x3c8);
@@ -265,7 +275,7 @@ static void mctl_phy_configure_odt(const struct dram_para
*para)
writel_relaxed(MASK_BYTE(val_hi, 1), SUNXI_DRAM_PHY0_BASE + 0x34c);
val_lo = (para->type == SUNXI_DRAM_TYPE_LPDDR3) ? 0 : para->dx_odt;
- val_hi = para->dx_odt;
+ val_hi = (para->type == SUNXI_DRAM_TYPE_LPDDR4) ? 0 : para->dx_odt;
writel_relaxed(MASK_BYTE(val_lo, 0), SUNXI_DRAM_PH
[PATCH v2 0/1] sunxi: H616: add LPDDR4 support
From: iuncuim At the moment, the driver only supports DDR3 and LPDDR3 memory. Add support for a new type DRAM. These changes have been successfully tested by me with orangepi zero3 4GB (DRAM: Rayson RS1G32LO4D2BDS-53BT). This patch should be applied after this: https://lore.kernel.org/all/20231014170236.16211-1-andre.przyw...@arm.com/ Changes from v1: * replaced the phy_init array with one compatible with opizero3 * added DRAM TPR6 parameter * adaptation to new mctl_phy_configure_odt() * added timings for the board orangepi zero3 4GB https://lore.kernel.org/u-boot/20230729111331.173768-2-iunc...@gmail.com/ Signed-off-by: Mikhail Kalashnikov iuncuim (1): sunxi: H616: add LPDDR4 DRAM support .../include/asm/arch-sunxi/dram_sun50i_h616.h | 2 + arch/arm/mach-sunxi/Kconfig | 16 ++ arch/arm/mach-sunxi/dram_sun50i_h616.c| 176 ++ arch/arm/mach-sunxi/dram_timings/Makefile | 1 + .../dram_timings/h616_lpddr4_2133.c | 97 ++ 5 files changed, 258 insertions(+), 34 deletions(-) create mode 100644 arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c -- 2.42.0
Re: [PATCH] sunxi: H616: DRAM: refactor mctl_phy_configure_odt()
Yes, this patch allows to reduce code size and make it easier to read.
To further integrate the code for LPDDR4, will need to change two lines
instead of adding 24 lines.
Reviewed-by: Mikhail Kalashnikov
On 14.10.2023 20:02, Andre Przywara wrote:
The original H616 DDR3 ODT configuration code wrote board specific values
into a sequence of paired registers.
For LPDDR3 support we needed to special-case one group of registers,
because for that DRAM type we need to write 0 into the lower register of
each pair. That already made the code less readable.
LPDDR4 support will make things even messier, so let's refactor that
code now: We allow to write different values into the lower and upper
half of each pair. The masking is moved into a macro, and used in each
write statement.
The effect is not as obvious yet, as we don't need the full flexibility at
the moment, but the motivation will become clearer with LPDDR4 support.
The generated binary is identical with and without the patch.
Signed-off-by: Andre Przywara
---
arch/arm/mach-sunxi/dram_sun50i_h616.c | 84 ++
1 file changed, 31 insertions(+), 53 deletions(-)
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 7e580b62dca..ba5659d4094 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -241,61 +241,39 @@ static const u8 phy_init[] = {
#endif
};
+#define MASK_BYTE(reg, nr) (((reg) >> ((nr) * 8)) & 0x1f)
static void mctl_phy_configure_odt(const struct dram_para *para)
{
- unsigned int val;
-
- val = para->dx_dri & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x388);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x38c);
-
- val = (para->dx_dri >> 8) & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c8);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3cc);
-
- val = (para->dx_dri >> 16) & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x408);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x40c);
-
- val = (para->dx_dri >> 24) & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x448);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x44c);
-
- val = para->ca_dri & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x340);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x344);
-
- val = (para->ca_dri >> 8) & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x348);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x34c);
-
- val = para->dx_odt & 0x1f;
- if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
- writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x380);
- else
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x380);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x384);
-
- val = (para->dx_odt >> 8) & 0x1f;
- if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
- writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x3c0);
- else
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c0);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c4);
-
- val = (para->dx_odt >> 16) & 0x1f;
- if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
- writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x400);
- else
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x400);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x404);
-
- val = (para->dx_odt >> 24) & 0x1f;
- if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
- writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x440);
- else
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x440);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x444);
+ uint32_t val_lo, val_hi;
+
+ val_lo = para->dx_dri;
+ val_hi = para->dx_dri;
+ writel_relaxed(MASK_BYTE(val_lo, 0), SUNXI_DRAM_PHY0_BASE + 0x388);
+ writel_relaxed(MASK_BYTE(val_hi, 0), SUNXI_DRAM_PHY0_BASE + 0x38c);
+ writel_relaxed(MASK_BYTE(val_lo, 1), SUNXI_DRAM_PHY0_BASE + 0x3c8);
+ writel_relaxed(MASK_BYTE(val_hi, 1), SUNXI_DRAM_PHY0_BASE + 0x3cc);
+ writel_relaxed(MASK_BYTE(val_lo, 2), SUNXI_DRAM_PHY0_BASE + 0x408);
+ writel_relaxed(MASK_BYTE(val_hi, 2), SUNXI_DRAM_PHY0_BASE + 0x40c);
+ writel_relaxed(MASK_BYTE(val_lo, 3), SUNXI_DRAM_PHY0_BASE + 0x448);
+ writel_relaxed(MASK_BYTE(val_hi, 3), SUNXI_DRAM_PHY0_BASE + 0x44c);
+
+ val_lo = para->ca_dri;
+ val_hi = para->ca_dri;
+ writel_relaxed(MASK_BYTE(val_lo, 0), SUNXI_DRAM_PHY0_BASE + 0x340);
+ writel_relaxed(MASK_BYTE(val_hi, 0), SUNXI_DRAM_PHY0_BASE + 0x344);
+ writel_relaxed(MASK_BYTE(val_lo, 1), SUNXI_DRAM_PHY0_BASE + 0x348);
+ writel_relaxed(MASK_BYTE(val_hi, 1), SUNXI_DRAM_PHY0_BASE + 0x34c);
+
+
[PATCH 1/1] sunxi: H616: add LPDDR4 DRAM support
From: iuncuim
The H616 SoC family has support for several types of DRAM: DDR3,
LPDDR3, DDR4 and LPDDR4.
At the moment, the driver only supports DDR3 and LPDDR3 memory.
Let's extend the driver to support the LPDDR4 memory. This type
of memory widely used in device with T507(-H) SoC. All "magic"
values obtained from the boot0.
These changes have been successfully tested by me with MYiR MYB-YT507
(1GB ARTMEM ATL4B08323M62) and 9tripod X507BV4 (2GB FORESEE NCLDXC2MG512M32).
Signed-off-by: Mikhail Kalashnikov
---
.../include/asm/arch-sunxi/dram_sun50i_h616.h | 1 +
arch/arm/mach-sunxi/Kconfig | 11 +
arch/arm/mach-sunxi/dram_sun50i_h616.c| 200 ++
arch/arm/mach-sunxi/dram_timings/Makefile | 1 +
.../dram_timings/h616_lpddr4_1200.c | 96 +
5 files changed, 270 insertions(+), 39 deletions(-)
create mode 100644 arch/arm/mach-sunxi/dram_timings/h616_lpddr4_1200.c
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
index 11774deded..ee25c324ff 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
@@ -130,6 +130,7 @@ check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240);
#define MSTR_DEVICETYPE_LPDDR2 BIT(2)
#define MSTR_DEVICETYPE_LPDDR3 BIT(3)
#define MSTR_DEVICETYPE_DDR4 BIT(4)
+#define MSTR_DEVICETYPE_LPDDR4 BIT(5)
#define MSTR_DEVICETYPE_MASK GENMASK(5, 0)
#define MSTR_2TMODEBIT(10)
#define MSTR_BUSWIDTH_FULL (0 << 12)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index e20c3a3ee9..0e82edeeab 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -441,6 +441,9 @@ config SUNXI_DRAM_DDR2
config SUNXI_DRAM_LPDDR3
bool
+config SUNXI_DRAM_LPDDR4
+ bool
+
choice
prompt "DRAM Type and Timing"
default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
@@ -484,6 +487,14 @@ config SUNXI_DRAM_H616_LPDDR3
This option is the LPDDR3 timing used by the stock boot0 by
Allwinner.
+config SUNXI_DRAM_H616_LPDDR4
+ bool "LPDDR4 DRAM chips on the H616 DRAM controller"
+ select SUNXI_DRAM_LPDDR4
+ depends on DRAM_SUN50I_H616
+ help
+ This option is the LPDDR4 timing used by the stock boot0 by
+ Allwinner.
+
config SUNXI_DRAM_H616_DDR3_1333
bool "DDR3-1333 boot0 timings on the H616 DRAM controller"
select SUNXI_DRAM_DDR3
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 7e580b62dc..7b8799460b 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -238,6 +238,11 @@ static const u8 phy_init[] = {
0x08, 0x01, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07,
0x17, 0x19, 0x1a
+#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4)
+ 0x03, 0x00, 0x17, 0x05, 0x02, 0x19, 0x06, 0x07,
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01,
+ 0x18, 0x04, 0x1a
#endif
};
@@ -247,19 +252,31 @@ static void mctl_phy_configure_odt(const struct dram_para
*para)
val = para->dx_dri & 0x1f;
writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x388);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x38c);
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR4)
+ writel_relaxed(4, SUNXI_DRAM_PHY0_BASE + 0x38c);
+ else
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x38c);
val = (para->dx_dri >> 8) & 0x1f;
writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c8);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3cc);
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR4)
+ writel_relaxed(4, SUNXI_DRAM_PHY0_BASE + 0x3cc);
+ else
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3cc);
val = (para->dx_dri >> 16) & 0x1f;
writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x408);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x40c);
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR4)
+ writel_relaxed(4, SUNXI_DRAM_PHY0_BASE + 0x40c);
+ else
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x40c);
val = (para->dx_dri >> 24) & 0x1f;
writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x448);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x44c);
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR4)
+ writel_relaxed(4, SUNXI_DRAM_PHY0_BASE + 0x44c);
+ else
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x44c);
val = para->ca_dri & 0x1f;
writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x340);
@@ -274,28 +291,40 @@ static void mctl_phy_configure_odt(const struct dram_para
*para)
[PATCH 0/1] sunxi: H616: add LPDDR4 support
From: iuncuim At the moment, the driver only supports DDR3 and LPDDR3 memory. Add support for a new type DRAM. Signed-off-by: Mikhail Kalashnikov iuncuim (1): dram: h616: add LPDDR4 DRAM support .../include/asm/arch-sunxi/dram_sun50i_h616.h | 1 + arch/arm/mach-sunxi/Kconfig | 11 + arch/arm/mach-sunxi/dram_sun50i_h616.c| 200 ++ arch/arm/mach-sunxi/dram_timings/Makefile | 1 + .../dram_timings/h616_lpddr4_1200.c | 96 + 5 files changed, 270 insertions(+), 39 deletions(-) create mode 100644 arch/arm/mach-sunxi/dram_timings/h616_lpddr4_1200.c -- 2.41.0
[PATCH 2/2] sunxi: H616: add LPDDR3 DRAM support
From: iuncuim
The H616 SoC has support for several types of DRAM: DDR3, LPDDR3,
DDR4 and LPDDR4.
At the moment, the driver only supports DDR3 memory.
Let's extend the driver to support the LPDDR3 memory. All "magic"
values obtained from the boot0.
---
.../include/asm/arch-sunxi/dram_sun50i_h616.h | 1 +
arch/arm/mach-sunxi/Kconfig | 10 +-
arch/arm/mach-sunxi/dram_sun50i_h616.c| 215 --
arch/arm/mach-sunxi/dram_timings/Makefile | 1 +
.../arm/mach-sunxi/dram_timings/h616_lpddr3.c | 95
5 files changed, 255 insertions(+), 67 deletions(-)
create mode 100644 arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
index 6db869c098..bf4188fa89 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
@@ -148,6 +148,7 @@ check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240);
struct dram_para {
u32 clk;
enum sunxi_dram_type type;
+ u8 phy_init[27];
u8 cols;
u8 rows;
u8 ranks;
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 3ad37ef6ba..5ce82a955c 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -487,6 +487,14 @@ config SUNXI_DRAM_H6_DDR3_1333
This option is the DDR3 timing used by the boot0 on H6 TV boxes
which use a DDR3-1333 timing.
+config SUNXI_DRAM_H616_LPDDR3
+ bool "LPDDR3 DRAM chips on the H616 DRAM controller"
+ select SUNXI_DRAM_LPDDR3
+ depends on DRAM_SUN50I_H616
+ ---help---
+ This option is the LPDDR3 timing used by the stock boot0 by
+ Allwinner.
+
config SUNXI_DRAM_H616_DDR3_1333
bool "DDR3-1333 boot0 timings on the H616 DRAM controller"
select SUNXI_DRAM_DDR3
@@ -1083,4 +1091,4 @@ config CHIP_DIP_SCAN
select W1_GPIO
select W1_EEPROM
select W1_EEPROM_DS24XXX
- select CMD_EXTENSION
\ No newline at end of file
+ select CMD_EXTENSION
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 1f9416d6ea..d34b218ee5 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -227,13 +227,6 @@ static void mctl_set_addrmap(struct dram_para *para)
mctl_ctl->addrmap[8] = 0x3F3F;
}
-static const u8 phy_init[] = {
- 0x07, 0x0b, 0x02, 0x16, 0x0d, 0x0e, 0x14, 0x19,
- 0x0a, 0x15, 0x03, 0x13, 0x04, 0x0c, 0x10, 0x06,
- 0x0f, 0x11, 0x1a, 0x01, 0x12, 0x17, 0x00, 0x08,
- 0x09, 0x05, 0x18
-};
-
static void mctl_phy_configure_odt(struct dram_para *para)
{
unsigned int val;
@@ -263,19 +256,31 @@ static void mctl_phy_configure_odt(struct dram_para *para)
writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x34c);
val = para->dx_odt & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x380);
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
+ writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x380);
+ else
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x380);
writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x384);
val = (para->dx_odt >> 8) & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c0);
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
+ writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x3c0);
+ else
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c0);
writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c4);
val = (para->dx_odt >> 16) & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x400);
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
+ writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x400);
+ else
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x400);
writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x404);
val = (para->dx_odt >> 24) & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x440);
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
+ writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x440);
+ else
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x440);
writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x444);
dmb();
@@ -793,31 +798,47 @@ static void mctl_phy_ca_bit_delay_compensation(struct
dram_para *para)
writel(val, SUNXI_DRAM_PHY0_BASE + 0x7e0);
writel(val, SUNXI_DRAM_PHY0_BASE + 0x7f4);
- /* following configuration is DDR3 specific */
- val = (para->tpr10 >> 7) & 0x1e;
- if (para->tpr2 & 1) {
- writel(val, SUNXI_DRAM_PHY0_BASE + 0x794);
- if (para->ranks == 2) {
- val = (para->tpr10 >> 11) & 0x1e;
- writel(val, SUNXI_DRAM_PHY0_BASE + 0x7e4);
- }
- if (para->tpr0 & BIT(31)) {
- val =
[PATCH 1/2] sunxi: H616: add DRAM type selection
From: iuncuim Allwinner H616 SoC supports several types of DRAM memory. To further integrate other types of memory, we need to add this delimitation. --- arch/arm/mach-sunxi/Kconfig | 12 ++-- arch/arm/mach-sunxi/dram_timings/Makefile | 3 +-- configs/orangepi_zero2_defconfig | 1 + configs/x96_mate_defconfig| 1 + 4 files changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 6dcbb096f7..3ad37ef6ba 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -442,7 +442,7 @@ config ARM_BOOT_HOOK_RMR This allows both the SPL and the U-Boot proper to be entered in either mode and switch to AArch64 if needed. -if SUNXI_DRAM_DW || DRAM_SUN50I_H6 +if SUNXI_DRAM_DW || DRAM_SUN50I_H6 || DRAM_SUN50I_H616 config SUNXI_DRAM_DDR3 bool @@ -487,6 +487,14 @@ config SUNXI_DRAM_H6_DDR3_1333 This option is the DDR3 timing used by the boot0 on H6 TV boxes which use a DDR3-1333 timing. +config SUNXI_DRAM_H616_DDR3_1333 + bool "DDR3-1333 boot0 timings on the H616 DRAM controller" + select SUNXI_DRAM_DDR3 + depends on DRAM_SUN50I_H616 + ---help--- + This option is the DDR3 timing used by the boot0 on H616 TV boxes + which use a DDR3-1333 timing. + config SUNXI_DRAM_DDR2_V3S bool "DDR2 found in V3s chip" select SUNXI_DRAM_DDR2 @@ -1075,4 +1083,4 @@ config CHIP_DIP_SCAN select W1_GPIO select W1_EEPROM select W1_EEPROM_DS24XXX - select CMD_EXTENSION + select CMD_EXTENSION \ No newline at end of file diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile index 39a8756c29..4d78c04c9a 100644 --- a/arch/arm/mach-sunxi/dram_timings/Makefile +++ b/arch/arm/mach-sunxi/dram_timings/Makefile @@ -3,5 +3,4 @@ obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK) += lpddr3_stock.o obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o obj-$(CONFIG_SUNXI_DRAM_H6_LPDDR3) += h6_lpddr3.o obj-$(CONFIG_SUNXI_DRAM_H6_DDR3_1333) += h6_ddr3_1333.o -# currently only DDR3 is supported on H616 -obj-$(CONFIG_MACH_SUN50I_H616) += h616_ddr3_1333.o +obj-$(CONFIG_SUNXI_DRAM_H616_DDR3_1333)+= h616_ddr3_1333.o diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig index 6cb942f511..e38cc20ac7 100644 --- a/configs/orangepi_zero2_defconfig +++ b/configs/orangepi_zero2_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e CONFIG_DRAM_SUN50I_H616_TPR10=0xf83438 CONFIG_MACH_SUN50I_H616=y +CONFIG_SUNXI_DRAM_H616_DDR3_1333=y CONFIG_R_I2C_ENABLE=y CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig index aedb327702..2a326bf202 100644 --- a/configs/x96_mate_defconfig +++ b/configs/x96_mate_defconfig @@ -11,6 +11,7 @@ CONFIG_DRAM_SUN50I_H616_TPR10=0x2f0007 CONFIG_DRAM_SUN50I_H616_TPR11=0x CONFIG_DRAM_SUN50I_H616_TPR12=0xfedf7557 CONFIG_MACH_SUN50I_H616=y +CONFIG_SUNXI_DRAM_H616_DDR3_1333=y CONFIG_R_I2C_ENABLE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y -- 2.40.1
[PATCH 0/2] sunxi: H616: Add LPDDR3 DRAM type
From: iuncuim At the moment, the driver only supports DDR3 memory. Add support for a new type DRAM. These changes have been successfully tested by me with tvbox tra###eed t98-h2b-lp3. iuncuim (2): sunxi: H616: add DRAM type selection sunxi: H616: add LPDDR3 DRAM support .../include/asm/arch-sunxi/dram_sun50i_h616.h | 1 + arch/arm/mach-sunxi/Kconfig | 18 +- arch/arm/mach-sunxi/dram_sun50i_h616.c| 215 -- arch/arm/mach-sunxi/dram_timings/Makefile | 4 +- .../arm/mach-sunxi/dram_timings/h616_lpddr3.c | 95 configs/orangepi_zero2_defconfig | 1 + configs/x96_mate_defconfig| 1 + 7 files changed, 266 insertions(+), 69 deletions(-) create mode 100644 arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c -- 2.40.1
