Re: [PATCH 19/33] arm: meson: Remove and add needed includes
On 30/04/2024 15:35, Tom Rini wrote: Remove from all mach-meson files and when needed add missing include files directly. Signed-off-by: Tom Rini --- Cc: Neil Armstrong Cc: u-boot-amlo...@groups.io --- arch/arm/mach-meson/board-a1.c | 2 +- arch/arm/mach-meson/board-axg.c| 1 - arch/arm/mach-meson/board-common.c | 1 - arch/arm/mach-meson/board-g12a.c | 1 - arch/arm/mach-meson/board-gx.c | 1 - arch/arm/mach-meson/board-info.c | 1 - arch/arm/mach-meson/sm.c | 1 - 7 files changed, 1 insertion(+), 7 deletions(-) diff --git a/arch/arm/mach-meson/board-a1.c b/arch/arm/mach-meson/board-a1.c index 967bb671822e..f848c0f068ed 100644 --- a/arch/arm/mach-meson/board-a1.c +++ b/arch/arm/mach-meson/board-a1.c @@ -3,12 +3,12 @@ * (C) Copyright 2023 SberDevices, Inc. */ -#include #include #include #include #include #include +#include #include phys_size_t get_effective_memsize(void) diff --git a/arch/arm/mach-meson/board-axg.c b/arch/arm/mach-meson/board-axg.c index fdf18752cdd0..6535539184cc 100644 --- a/arch/arm/mach-meson/board-axg.c +++ b/arch/arm/mach-meson/board-axg.c @@ -4,7 +4,6 @@ * (C) Copyright 2018 Neil Armstrong */ -#include #include #include #include diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c index 7ceba7cede85..39774c43049a 100644 --- a/arch/arm/mach-meson/board-common.c +++ b/arch/arm/mach-meson/board-common.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Beniamino Galvani */ -#include #include #include #include diff --git a/arch/arm/mach-meson/board-g12a.c b/arch/arm/mach-meson/board-g12a.c index d5a830fb1db8..dc4abe1e1074 100644 --- a/arch/arm/mach-meson/board-g12a.c +++ b/arch/arm/mach-meson/board-g12a.c @@ -4,7 +4,6 @@ * (C) Copyright 2018 Neil Armstrong */ -#include #include #include #include diff --git a/arch/arm/mach-meson/board-gx.c b/arch/arm/mach-meson/board-gx.c index c3fbdfffeae8..0370ed57e205 100644 --- a/arch/arm/mach-meson/board-gx.c +++ b/arch/arm/mach-meson/board-gx.c @@ -4,7 +4,6 @@ * (C) Copyright 2018 Neil Armstrong */ -#include #include #include #include diff --git a/arch/arm/mach-meson/board-info.c b/arch/arm/mach-meson/board-info.c index d51d9b8f0645..b4058f593234 100644 --- a/arch/arm/mach-meson/board-info.c +++ b/arch/arm/mach-meson/board-info.c @@ -4,7 +4,6 @@ * (C) Copyright 2019 Neil Armstrong */ -#include #include #include #include diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c index 914fd11c9894..4d9f83d3b38d 100644 --- a/arch/arm/mach-meson/sm.c +++ b/arch/arm/mach-meson/sm.c @@ -5,7 +5,6 @@ * Secure monitor calls. */ -#include #include #include #include Reviewed-by: Neil Armstrong
Re: [PATCH v1] arm: dts: meson-axg: add NAND controller node for AXG
On 26/04/2024 10:40, Arseniy Krasnov wrote:
Hi,
On 26.04.2024 11:21, Neil Armstrong wrote:
Hi,
On 25/04/2024 19:50, Arseniy Krasnov wrote:
nfc: Synced from Linux commit 7ca2ef33179f ("Linux 6.6-rc1")
nand_all_pins: Synced from Linux commit be18d53c32b2 ("Linux 6.7-rc3")
No need to sync DT anymore, this is handled by OF_UPSTREAM and for next release
it's already aligned with v6.9 DT.
Please try your patches with master or next branch of U-Boot repo.
Ok, so I can remove "Synced from" from commit description, thus make it empty,
and test that patch applies correctly
on uboot master/ next ?
It won't apply because arch/arm/dts/meson-axg.dtsi doesn't exist anymore, DT
comes
from dts/upstream, however if you need to add u-boot specific changes you can
still update arch/arm/dts/meson-axgi-u-boot.dtsi
Neil
Thanks
Neil
Signed-off-by: Arseniy Krasnov
---
arch/arm/dts/meson-axg.dtsi | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm/dts/meson-axg.dtsi b/arch/arm/dts/meson-axg.dtsi
index 3f5254eeb4..4f6fdd5523 100644
--- a/arch/arm/dts/meson-axg.dtsi
+++ b/arch/arm/dts/meson-axg.dtsi
@@ -430,6 +430,27 @@
};
};
+ nand_all_pins: nand_all_pins {
+ mux {
+ groups = "emmc_nand_d0",
+ "emmc_nand_d1",
+ "emmc_nand_d2",
+ "emmc_nand_d3",
+ "emmc_nand_d4",
+ "emmc_nand_d5",
+ "emmc_nand_d6",
+ "emmc_nand_d7",
+ "nand_ce0",
+ "nand_ale",
+ "nand_cle",
+ "nand_wen_clk",
+ "nand_ren_wr";
+ function = "nand";
+ input-enable;
+ bias-pull-up;
+ };
+ };
+
emmc_ds_pins: emmc_ds {
mux {
groups = "emmc_ds";
@@ -1906,6 +1927,21 @@
resets = < RESET_SD_EMMC_C>;
};
+ nfc: nand-controller@7800 {
+ compatible = "amlogic,meson-axg-nfc";
+ reg = <0x0 0x7800 0x0 0x100>,
+ <0x0 0x7000 0x0 0x800>;
+ reg-names = "nfc", "emmc";
+ pinctrl-0 = <_all_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = ;
+ clocks = < CLKID_SD_EMMC_C>,
+ < CLKID_FCLK_DIV2>;
+ clock-names = "core", "device";
+ };
+
usb2_phy1: phy@9020 {
compatible = "amlogic,meson-gxl-usb2-phy";
#phy-cells = <0>;
Re: [PATCH v1] arm: dts: meson-axg: add NAND controller node for AXG
Hi,
On 25/04/2024 19:50, Arseniy Krasnov wrote:
nfc: Synced from Linux commit 7ca2ef33179f ("Linux 6.6-rc1")
nand_all_pins: Synced from Linux commit be18d53c32b2 ("Linux 6.7-rc3")
No need to sync DT anymore, this is handled by OF_UPSTREAM and for next release
it's already aligned with v6.9 DT.
Please try your patches with master or next branch of U-Boot repo.
Neil
Signed-off-by: Arseniy Krasnov
---
arch/arm/dts/meson-axg.dtsi | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm/dts/meson-axg.dtsi b/arch/arm/dts/meson-axg.dtsi
index 3f5254eeb4..4f6fdd5523 100644
--- a/arch/arm/dts/meson-axg.dtsi
+++ b/arch/arm/dts/meson-axg.dtsi
@@ -430,6 +430,27 @@
};
};
+nand_all_pins: nand_all_pins {
+ mux {
+ groups = "emmc_nand_d0",
+"emmc_nand_d1",
+"emmc_nand_d2",
+"emmc_nand_d3",
+"emmc_nand_d4",
+"emmc_nand_d5",
+"emmc_nand_d6",
+"emmc_nand_d7",
+"nand_ce0",
+"nand_ale",
+"nand_cle",
+"nand_wen_clk",
+"nand_ren_wr";
+ function = "nand";
+ input-enable;
+ bias-pull-up;
+ };
+ };
+
emmc_ds_pins: emmc_ds {
mux {
groups = "emmc_ds";
@@ -1906,6 +1927,21 @@
resets = < RESET_SD_EMMC_C>;
};
+ nfc: nand-controller@7800 {
+ compatible = "amlogic,meson-axg-nfc";
+ reg = <0x0 0x7800 0x0 0x100>,
+ <0x0 0x7000 0x0 0x800>;
+ reg-names = "nfc", "emmc";
+ pinctrl-0 = <_all_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = ;
+ clocks = < CLKID_SD_EMMC_C>,
+< CLKID_FCLK_DIV2>;
+ clock-names = "core", "device";
+ };
+
usb2_phy1: phy@9020 {
compatible = "amlogic,meson-gxl-usb2-phy";
#phy-cells = <0>;
[PATCH v2 1/2] i2c: Add support for Qualcomm Generic Interface (GENI) I2C controller
Add Support for the Qualcomm Generic Interface (GENI) I2C interface
found on newer Qualcomm SoCs.
The Generic Interface (GENI) is a firmware based Qualcomm Universal
Peripherals (QUP) Serial Engine (SE) Wrapper which can support multiple
bus protocols depending on the firmware type loaded at early boot time
based on system configuration.
It also supports the "I2C Master Hub" which is a single function Wrapper
that only FIFO mode I2C.
It replaces the fixed-function QUP Wrapper found on older SoCs.
The geni-se.h containing the generic GENI Serial Engine registers defines
is imported from Linux.
Only FIFO mode is implemented, neither SE DMA nor GPI DMA are implemented.
Signed-off-by: Neil Armstrong
---
drivers/i2c/Kconfig| 10 +
drivers/i2c/Makefile | 1 +
drivers/i2c/geni_i2c.c | 575 +
include/soc/qcom/geni-se.h | 265 +
4 files changed, 851 insertions(+)
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 59c635af80b..34b02114dc6 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -638,6 +638,16 @@ config SYS_I2C_QUP
Technical Reference Manual, chapter "6.1 Qualcomm Universal
Peripherals Engine (QUP)".
+config SYS_I2C_GENI
+ bool "Qualcomm Generic Interface (GENI) I2C controller"
+ depends on ARCH_SNAPDRAGON
+ help
+ Support for the Qualcomm Generic Interface (GENI) I2C interface.
+ The Generic Interface (GENI) is a firmware based Qualcomm Universal
+ Peripherals (QUP) Serial Engine (SE) Wrapper which can support
multiple
+ bus protocols depending on the firmware type loaded at early boot time
+ based on system configuration.
+
config SYS_I2C_S3C24X0
bool "Samsung I2C driver"
depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 692f63bafd0..00b90523c62 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
obj-$(CONFIG_SYS_I2C_DW_PCI) += designware_i2c_pci.o
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
+obj-$(CONFIG_SYS_I2C_GENI) += geni_i2c.o
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o
diff --git a/drivers/i2c/geni_i2c.c b/drivers/i2c/geni_i2c.c
new file mode 100644
index 000..eabf5c76c21
--- /dev/null
+++ b/drivers/i2c/geni_i2c.c
@@ -0,0 +1,575 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Linaro Limited
+ * Author: Neil Armstrong
+ *
+ * Based on Linux driver: drivers/i2c/busses/i2c-qcom-geni.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SE_I2C_TX_TRANS_LEN0x26c
+#define SE_I2C_RX_TRANS_LEN0x270
+#define SE_I2C_SCL_COUNTERS0x278
+
+#define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
+ M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
+#define SE_I2C_ABORT BIT(1)
+
+/* M_CMD OP codes for I2C */
+#define I2C_WRITE 0x1
+#define I2C_READ 0x2
+#define I2C_WRITE_READ 0x3
+#define I2C_ADDR_ONLY 0x4
+#define I2C_BUS_CLEAR 0x6
+#define I2C_STOP_ON_BUS0x7
+/* M_CMD params for I2C */
+#define PRE_CMD_DELAY BIT(0)
+#define TIMESTAMP_BEFORE BIT(1)
+#define STOP_STRETCH BIT(2)
+#define TIMESTAMP_AFTERBIT(3)
+#define POST_COMMAND_DELAY BIT(4)
+#define IGNORE_ADD_NACKBIT(6)
+#define READ_FINISHED_WITH_ACK BIT(7)
+#define BYPASS_ADDR_PHASE BIT(8)
+#define SLV_ADDR_MSK GENMASK(15, 9)
+#define SLV_ADDR_SHFT 9
+/* I2C SCL COUNTER fields */
+#define HIGH_COUNTER_MSK GENMASK(29, 20)
+#define HIGH_COUNTER_SHFT 20
+#define LOW_COUNTER_MSKGENMASK(19, 10)
+#define LOW_COUNTER_SHFT 10
+#define CYCLE_COUNTER_MSK GENMASK(9, 0)
+
+#define I2C_PACK_TXBIT(0)
+#define I2C_PACK_RXBIT(1)
+
+#define PACKING_BYTES_PW 4
+
+#define GENI_I2C_IS_MASTER_HUB BIT(0)
+
+#define I2C_TIMEOUT_MS 100
+
+struct geni_i2c_clk_fld {
+ u32 clk_freq_out;
+ u8 clk_div;
+ u8 t_high_cnt;
+ u8 t_low_cnt;
+ u8 t_cycle_cnt;
+};
+
+struct geni_i2c_priv {
+ fdt_addr_t wrapper;
+ phys_addr_t base;
+ struct clk core;
+ struct clk se;
+ u32 tx_wm;
+ bool is_master_hub;
+ const struct geni_i2c_clk_fld *clk_fld;
+};
+
+/*
+ * Hardware uses the underlying formula to calculate time periods of
+ * SCL clock cycl
[PATCH v2 2/2] configs: qcom_defconfig: enable GENI I2C Driver
Enable the GENI I2C driver in the default Qualcomm defconfig. Reviewed-by: Caleb Connolly Signed-off-by: Neil Armstrong --- configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 1abb57345ff..8d440b23625 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -41,6 +41,7 @@ CONFIG_MSM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_QUP=y +CONFIG_SYS_I2C_GENI=y CONFIG_I2C_MUX=y CONFIG_DM_KEYBOARD=y CONFIG_BUTTON_KEYBOARD=y -- 2.34.1
[PATCH v2 0/2] i2c: Add support for Qualcomm Generic Interface (GENI) I2C controller
Add Support for the Qualcomm Generic Interface (GENI) I2C interface found on newer Qualcomm SoCs. The Generic Interface (GENI) is a firmware based Qualcomm Universal Peripherals (QUP) Serial Engine (SE) Wrapper which can support multiple bus protocols depending on the firmware type loaded at early boot time based on system configuration. It also supports the "I2C Master Hub" which is a single function Wrapper that only FIFO mode I2C. It replaces the fixed-function QUP Wrapper found on older SoCs. The geni-se.h containing the generic GENI Serial Engine registers defines is imported from Linux. Only FIFO mode is implemented, neither SE DMA nor GPI DMA are implemented. Finally enable the driver in the default Qualcomm defconfig. Signed-off-by: Neil Armstrong --- Changes in v2: - Fixed commit msg, removed useless debug, switched to dev_err() in probe - Fixed some possible issues & typos and W=1 build warning - Link to v1: https://lore.kernel.org/r/20240419-topic-sm8x50-i2c-v1-0-67651e27f...@linaro.org --- Neil Armstrong (2): i2c: Add support for Qualcomm Generic Interface (GENI) I2C controller configs: qcom_defconfig: enable GENI I2C Driver configs/qcom_defconfig | 1 + drivers/i2c/Kconfig| 10 + drivers/i2c/Makefile | 1 + drivers/i2c/geni_i2c.c | 575 + include/soc/qcom/geni-se.h | 265 + 5 files changed, 852 insertions(+) --- base-commit: b2511143fba4c0631446c968fb4c0d962b01d850 change-id: 20240419-topic-sm8x50-i2c-b51e576d5f57 Best regards, -- Neil Armstrong
Re: [PATCH 1/2] i2c: Add support for Qualcomm Generic Interface (GENI) I2C controller
On 19/04/2024 13:47, Caleb Connolly wrote:
Hi Neil,
On 18/04/2024 23:47, Neil Armstrong wrote:
Add Support for the Qualcomm Generic Interface (GENI) I2C interface
found on newer Qualcomm SoCs.
\o/
The Generic Interface (GENI) is a firmware based Qualcomm Universal
Peripherals (QUP) Serial Engine (SE) Wrapper which can support multiple
bus protocols depending on the firmware type loaded at early boot time
based on system configuration.
It also supports the "I2C Master Hub" which is a single function Wrapper
that only FIFO mode I2C.
It replaces the fixed-function QUP Wrapper found on older SoCs.
The geni-se.h containing the generic GENI Serial Engine registers defines
is imported from Linux.
Only FIFO mode is implemented, nor SE DMA nor GPI DMA is implemented.
nit: "neither SE DMA nor GPI DMA are implemented"
Thx!
A few minor things below, but otherwise LGTM!
Signed-off-by: Neil Armstrong
---
drivers/i2c/Kconfig| 10 +
drivers/i2c/Makefile | 1 +
drivers/i2c/geni_i2c.c | 576 +
include/soc/qcom/geni-se.h | 265 +
4 files changed, 852 insertions(+)
[...]
diff --git a/drivers/i2c/geni_i2c.c b/drivers/i2c/geni_i2c.c
new file mode 100644
index 000..8c3ed3bef89
--- /dev/null
+++ b/drivers/i2c/geni_i2c.c
@@ -0,0 +1,576 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Linaro Limited
+ * Author: Neil Armstrong
+ *
+ * Based on Linux driver: drivers/i2c/busses/i2c-qcom-geni.c
+ */
+
[...]
+static int geni_i2c_fifo_tx_fill(struct geni_i2c_priv *geni, struct i2c_msg
*msg)
+{
+ ulong start = get_timer(0);
+ ulong cur_xfer = 0;
+ int i;
+
+ while (get_timer(start) < I2C_TIMEOUT_MS) {
+ u32 status = readl(geni->base + SE_GENI_M_IRQ_STATUS);
+
+ if (status & (M_CMD_ABORT_EN |
+ M_CMD_OVERRUN_EN |
+ M_ILLEGAL_CMD_EN |
+ M_CMD_FAILURE_EN |
+ M_GP_IRQ_1_EN |
+ M_GP_IRQ_3_EN |
+ M_GP_IRQ_4_EN)) {
+ debug("%s:%d cmd err\n", __func__, __LINE__);
How likely are we to hit this? Would it make sense to promote it to a
pr_warn()?
Please drop the __LINE__ and (if it makes sense to?) print the value of
status.
It's used when the tranactions is nacked, so it would spam, so I rather remove
the print entirely. It's verly unlikely we see any of the other errors.
+ writel(status, geni->base + SE_GENI_M_IRQ_CLEAR);
+ writel(0, geni->base + SE_GENI_TX_WATERMARK_REG);
+ return -EREMOTEIO;
+ }
+
+ if ((status & M_TX_FIFO_WATERMARK_EN) == 0) {
+ udelay(1);
+ goto skip_fill;
+ }
+
+ for (i = 0; i < geni->tx_wm; i++) {
+ u32 temp, tx = 0;
+ unsigned int p = 0;
+
+ while (cur_xfer < msg->len && p < sizeof(tx)) {
+ temp = msg->buf[cur_xfer++];
+ tx |= temp << (p * 8);
+ p++;
+ }
+
+ writel(tx, geni->base + SE_GENI_TX_FIFOn);
+
+ if (cur_xfer == msg->len) {
+ writel(0, geni->base +
SE_GENI_TX_WATERMARK_REG);
+ break;
+ }
+ }
+
+skip_fill:
+ writel(status, geni->base + SE_GENI_M_IRQ_CLEAR);
+
+ if (status & M_CMD_DONE_EN)
+ return 0;
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int geni_i2c_fifo_rx_drain(struct geni_i2c_priv *geni, struct i2c_msg
*msg)
+{
+ ulong start = get_timer(0);
+ ulong cur_xfer = 0;
+ int i;
+
+ while (get_timer(start) < I2C_TIMEOUT_MS) {
+ u32 status = readl(geni->base + SE_GENI_M_IRQ_STATUS);
+ u32 rxstatus = readl(geni->base + SE_GENI_RX_FIFO_STATUS);
+ u32 rxcnt = rxstatus & RX_FIFO_WC_MSK;
+
+ if (status & (M_CMD_ABORT_EN |
+ M_CMD_FAILURE_EN |
+ M_CMD_OVERRUN_EN |
+ M_ILLEGAL_CMD_EN |
+ M_GP_IRQ_1_EN |
+ M_GP_IRQ_3_EN |
+ M_GP_IRQ_4_EN)) {
+ debug("%s:%d cmd err\n", __func__, __LINE__);
Ditto
+ writel(status, geni->base + SE_GENI_M_IRQ_CLEAR);
+ return -EIO;
+
Re: [PATCH v4 3/3] dts: support building all dtb files for a specific vendor
On 18/04/2024 20:39, Caleb Connolly wrote: This adjusts OF_UPSTREAM to behave more like the kernel by allowing for all the devicetree files for a given vendor to be compiled. This is useful for Qualcomm in particular as most boards are supported by a single U-Boot build just provided with a different DT. Signed-off-by: Caleb Connolly --- dts/Kconfig | 24 scripts/Makefile.dts | 13 + 2 files changed, 37 insertions(+) diff --git a/dts/Kconfig b/dts/Kconfig index b9b6367154ef..6883a000a052 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -100,8 +100,32 @@ config OF_UPSTREAM However, newer boards whose devicetree source files haven't landed in the dts/upstream subtree, they can override this option to have the DT build from existing U-Boot tree location instead. +config OF_UPSTREAM_BUILD_VENDOR + bool "Build all devicetree files for a particular vendor" + depends on OF_UPSTREAM + help + Enable building all devicetree files for a particular vendor. This + is useful for generic U-Boot configurations where many boards can + be supported with a single binary. + + This is only available for platforms using upstream devicetree. + +config OF_UPSTREAM_VENDOR + string "Vendor to build all upstream devicetree files for" + depends on OF_UPSTREAM_BUILD_VENDOR + default "qcom" if ARCH_SNAPDRAGON + default "rockchip" if ARCH_ROCKCHIP + default "amlogic" if ARCH_MESON + default "allwinner" if ARCH_SUNXI + default "mediatek" if ARCH_MEDIATEK + default "marvell" if ARCH_MVEBU || ARCH_KIRKWOOD + default "xilinx" if ARCH_VERSAL || ARCH_ZYNQ + default "nvidia" if ARCH_TEGRA + help + Select the vendor to build all devicetree files for. + choice prompt "Provider of DTB for DT control" depends on OF_CONTROL diff --git a/scripts/Makefile.dts b/scripts/Makefile.dts index 5e2429c6170c..790f3c508f19 100644 --- a/scripts/Makefile.dts +++ b/scripts/Makefile.dts @@ -1,3 +1,16 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-y += $(patsubst %,%.dtb,$(subst ",,$(CONFIG_DEFAULT_DEVICE_TREE) $(CONFIG_OF_LIST) $(CONFIG_SPL_OF_LIST))) + +ifeq ($(CONFIG_OF_UPSTREAM_BUILD_VENDOR),y) +ifeq ($(CONFIG_ARM64),y) +dt_dir := $(srctree)/dts/upstream/src/arm64 +else +dt_dir := $(srctree)/dts/upstream/src/$(ARCH) +endif + +dtb-vendor_dts := $(patsubst %.dts,%.dtb,$(wildcard $(dt_dir)/$(subst ",,$(CONFIG_OF_UPSTREAM_VENDOR))/*.dts)) + +dtb-y += $(subst $(dt_dir)/,,$(dtb-vendor_dts)) + +endif Reviewed-by: Neil Armstrong Tested-by: Neil Armstrong # on Amlogic boards builds Reduced the whole Amlogic buildman build from 4.50 minutes to 2.30minutes! Thanks, Neil
Re: [PATCH v4 2/3] dt-bindings: drop generic headers
On 18/04/2024 20:39, Caleb Connolly wrote: Drop all the subsystem headers that are compatible with the headers in dts/upstream. Signed-off-by: Caleb Connolly --- include/dt-bindings/ata/ahci.h | 20 - include/dt-bindings/gpio/gpio.h| 42 -- include/dt-bindings/input/gpio-keys.h | 13 - include/dt-bindings/input/input.h | 17 - include/dt-bindings/input/linux-event-codes.h | 806 - include/dt-bindings/interrupt-controller/irq.h | 19 - include/dt-bindings/leds/common.h | 106 include/dt-bindings/mux/mux.h | 17 - include/dt-bindings/phy/phy.h | 26 - include/dt-bindings/pwm/pwm.h | 14 - include/dt-bindings/spmi/spmi.h| 10 - include/dt-bindings/thermal/thermal.h | 15 - include/dt-bindings/usb/pd.h | 88 --- 13 files changed, 1193 deletions(-) Reviewed-by: Neil Armstrong
Re: [PATCH 3/3] qcom_defconfig: set SYS_INIT_SP_BSS_OFFSET
On 18/04/2024 19:24, Caleb Connolly wrote: Give us lots of room for the appended FDT. Signed-off-by: Caleb Connolly --- configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 218a9a769682..7b589f0bf7a7 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -3,8 +3,9 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_SNAPDRAGON=y CONFIG_DEFAULT_DEVICE_TREE="qcom/sdm845-db845c" CONFIG_SYS_LOAD_ADDR=0x0 +CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 CONFIG_BUTTON_CMD=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTSTD_FULL=y Reviewed-by: Neil Armstrong
Re: [PATCH 2/3] arm: dts: drop qcom dts files
On 18/04/2024 19:24, Caleb Connolly wrote: These files are all identical (or older) than those in dts/upstream. Drop them as we now use upstream DTS files with OF_UPSTREAM. Signed-off-by: Caleb Connolly --- arch/arm/dts/apq8016-sbc.dts| 729 arch/arm/dts/apq8096-db820c.dts | 1137 -- arch/arm/dts/msm8916-pm8916.dtsi| 157 - arch/arm/dts/msm8916.dtsi | 2702 - arch/arm/dts/msm8996.dtsi | 3884 -- arch/arm/dts/pm8916.dtsi| 178 - arch/arm/dts/pm8994.dtsi| 152 - arch/arm/dts/pm8998.dtsi| 130 - arch/arm/dts/pmi8994.dtsi | 65 - arch/arm/dts/pmi8998.dtsi | 98 - arch/arm/dts/pms405.dtsi| 149 - arch/arm/dts/qcs404-evb-4000.dts| 96 - arch/arm/dts/qcs404-evb.dtsi| 389 -- arch/arm/dts/qcs404.dtsi| 1829 - arch/arm/dts/sdm845-db845c.dts | 1190 -- arch/arm/dts/sdm845-samsung-starqltechn.dts | 460 --- arch/arm/dts/sdm845-wcd9340.dtsi| 86 - arch/arm/dts/sdm845.dtsi| 5752 --- 18 files changed, 19183 deletions(-) Reviewed-by: Neil Armstrong
Re: [PATCH 1/3] mach-snapdragon: use OF_UPSTREAM
On 18/04/2024 19:24, Caleb Connolly wrote: Switch to using upstream DT from dts/upstream. Signed-off-by: Caleb Connolly --- MAINTAINERS | 4 arch/arm/Kconfig | 1 + configs/dragonboard410c_defconfig | 2 +- configs/dragonboard820c_defconfig | 2 +- configs/qcom_defconfig| 2 +- 5 files changed, 4 insertions(+), 7 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index c0d2b5138fca..d0a4a28b401d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -605,12 +605,8 @@ M: Neil Armstrong R:Sumit Garg L:u-boot-q...@groups.io S:Maintained T:git https://source.denx.de/u-boot/custodians/u-boot-snapdragon.git -F: arch/arm/dts/msm8*.dtsi -F: arch/arm/dts/pm8???.dtsi -F: arch/arm/dts/pms405.dtsi -F: arch/arm/dts/sdm845.dtsi F:drivers/*/*/pm8???-* F:drivers/gpio/msm_gpio.c F:drivers/mmc/msm_sdhci.c F:drivers/phy/msm8916-usbh-phy.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 23ee25269a24..2931c82eb11f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1088,8 +1088,9 @@ config ARCH_SNAPDRAGON select BOARD_LATE_INIT select OF_BOARD select SAVE_PREV_BL_FDT_ADDR select LINUX_KERNEL_IMAGE_HEADER + imply OF_UPSTREAM imply CMD_DM config ARCH_SOCFPGA bool "Altera SOCFPGA family" diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index 260a8349d3b2..9ef04fd45546 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -8,9 +8,9 @@ CONFIG_SYS_MALLOC_LEN=0x802000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 -CONFIG_DEFAULT_DEVICE_TREE="apq8016-sbc" +CONFIG_DEFAULT_DEVICE_TREE="qcom/apq8016-sbc" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C" CONFIG_SYS_LOAD_ADDR=0x8008 CONFIG_REMAKE_ELF=y diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig index ebc80eb2a464..f6b2cb09ba31 100644 --- a/configs/dragonboard820c_defconfig +++ b/configs/dragonboard820c_defconfig @@ -6,9 +6,9 @@ CONFIG_TEXT_BASE=0x8008 CONFIG_SYS_MALLOC_LEN=0x804000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0 CONFIG_ENV_SIZE=0x4000 -CONFIG_DEFAULT_DEVICE_TREE="apq8096-db820c" +CONFIG_DEFAULT_DEVICE_TREE="qcom/apq8096-db820c" CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 820C" CONFIG_SYS_LOAD_ADDR=0x8008 CONFIG_DISTRO_DEFAULTS=y CONFIG_USE_BOOTARGS=y diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index ee3ed89cbc8a..218a9a769682 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -1,9 +1,9 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_SNAPDRAGON=y -CONFIG_DEFAULT_DEVICE_TREE="sdm845-db845c" +CONFIG_DEFAULT_DEVICE_TREE="qcom/sdm845-db845c" CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_BUTTON_CMD=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y Reviewed-by: Neil Armstrong
[PATCH 2/2] configs: qcom_defconfig: enable GENI I2C Driver
Enable the GENI I2C driver in the default Qualcomm defconfig. Signed-off-by: Neil Armstrong --- configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 1abb57345ff..8d440b23625 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -41,6 +41,7 @@ CONFIG_MSM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_QUP=y +CONFIG_SYS_I2C_GENI=y CONFIG_I2C_MUX=y CONFIG_DM_KEYBOARD=y CONFIG_BUTTON_KEYBOARD=y -- 2.34.1
[PATCH 1/2] i2c: Add support for Qualcomm Generic Interface (GENI) I2C controller
Add Support for the Qualcomm Generic Interface (GENI) I2C interface
found on newer Qualcomm SoCs.
The Generic Interface (GENI) is a firmware based Qualcomm Universal
Peripherals (QUP) Serial Engine (SE) Wrapper which can support multiple
bus protocols depending on the firmware type loaded at early boot time
based on system configuration.
It also supports the "I2C Master Hub" which is a single function Wrapper
that only FIFO mode I2C.
It replaces the fixed-function QUP Wrapper found on older SoCs.
The geni-se.h containing the generic GENI Serial Engine registers defines
is imported from Linux.
Only FIFO mode is implemented, nor SE DMA nor GPI DMA is implemented.
Signed-off-by: Neil Armstrong
---
drivers/i2c/Kconfig| 10 +
drivers/i2c/Makefile | 1 +
drivers/i2c/geni_i2c.c | 576 +
include/soc/qcom/geni-se.h | 265 +
4 files changed, 852 insertions(+)
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 59c635af80b..34b02114dc6 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -638,6 +638,16 @@ config SYS_I2C_QUP
Technical Reference Manual, chapter "6.1 Qualcomm Universal
Peripherals Engine (QUP)".
+config SYS_I2C_GENI
+ bool "Qualcomm Generic Interface (GENI) I2C controller"
+ depends on ARCH_SNAPDRAGON
+ help
+ Support for the Qualcomm Generic Interface (GENI) I2C interface.
+ The Generic Interface (GENI) is a firmware based Qualcomm Universal
+ Peripherals (QUP) Serial Engine (SE) Wrapper which can support
multiple
+ bus protocols depending on the firmware type loaded at early boot time
+ based on system configuration.
+
config SYS_I2C_S3C24X0
bool "Samsung I2C driver"
depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 692f63bafd0..00b90523c62 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
obj-$(CONFIG_SYS_I2C_DW_PCI) += designware_i2c_pci.o
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
+obj-$(CONFIG_SYS_I2C_GENI) += geni_i2c.o
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o
diff --git a/drivers/i2c/geni_i2c.c b/drivers/i2c/geni_i2c.c
new file mode 100644
index 000..8c3ed3bef89
--- /dev/null
+++ b/drivers/i2c/geni_i2c.c
@@ -0,0 +1,576 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Linaro Limited
+ * Author: Neil Armstrong
+ *
+ * Based on Linux driver: drivers/i2c/busses/i2c-qcom-geni.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SE_I2C_TX_TRANS_LEN0x26c
+#define SE_I2C_RX_TRANS_LEN0x270
+#define SE_I2C_SCL_COUNTERS0x278
+
+#define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
+ M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
+#define SE_I2C_ABORT BIT(1)
+
+/* M_CMD OP codes for I2C */
+#define I2C_WRITE 0x1
+#define I2C_READ 0x2
+#define I2C_WRITE_READ 0x3
+#define I2C_ADDR_ONLY 0x4
+#define I2C_BUS_CLEAR 0x6
+#define I2C_STOP_ON_BUS0x7
+/* M_CMD params for I2C */
+#define PRE_CMD_DELAY BIT(0)
+#define TIMESTAMP_BEFORE BIT(1)
+#define STOP_STRETCH BIT(2)
+#define TIMESTAMP_AFTERBIT(3)
+#define POST_COMMAND_DELAY BIT(4)
+#define IGNORE_ADD_NACKBIT(6)
+#define READ_FINISHED_WITH_ACK BIT(7)
+#define BYPASS_ADDR_PHASE BIT(8)
+#define SLV_ADDR_MSK GENMASK(15, 9)
+#define SLV_ADDR_SHFT 9
+/* I2C SCL COUNTER fields */
+#define HIGH_COUNTER_MSK GENMASK(29, 20)
+#define HIGH_COUNTER_SHFT 20
+#define LOW_COUNTER_MSKGENMASK(19, 10)
+#define LOW_COUNTER_SHFT 10
+#define CYCLE_COUNTER_MSK GENMASK(9, 0)
+
+#define I2C_PACK_TXBIT(0)
+#define I2C_PACK_RXBIT(1)
+
+#define PACKING_BYTES_PW 4
+
+#define GENI_I2C_IS_MASTER_HUB BIT(0)
+
+#define I2C_TIMEOUT_MS 100
+
+struct geni_i2c_clk_fld {
+ u32 clk_freq_out;
+ u8 clk_div;
+ u8 t_high_cnt;
+ u8 t_low_cnt;
+ u8 t_cycle_cnt;
+};
+
+struct geni_i2c_priv {
+ fdt_addr_t wrapper;
+ phys_addr_t base;
+ struct clk core;
+ struct clk se;
+ u32 tx_wm;
+ bool is_master_hub;
+ const struct geni_i2c_clk_fld *clk_fld;
+};
+
+/*
+ * Hardware uses the underlying formula to calculate time periods of
+ * SCL clock cycle. Fi
[PATCH 0/2] i2c: Add support for Qualcomm Generic Interface (GENI) I2C controller
Add Support for the Qualcomm Generic Interface (GENI) I2C interface found on newer Qualcomm SoCs. The Generic Interface (GENI) is a firmware based Qualcomm Universal Peripherals (QUP) Serial Engine (SE) Wrapper which can support multiple bus protocols depending on the firmware type loaded at early boot time based on system configuration. It also supports the "I2C Master Hub" which is a single function Wrapper that only FIFO mode I2C. It replaces the fixed-function QUP Wrapper found on older SoCs. The geni-se.h containing the generic GENI Serial Engine registers defines is imported from Linux. Only FIFO mode is implemented, nor SE DMA nor GPI DMA is implemented. Finally enable the driver in the default Qualcomm defconfig. Signed-off-by: Neil Armstrong --- Neil Armstrong (2): i2c: Add support for Qualcomm Generic Interface (GENI) I2C controller configs: qcom_defconfig: enable GENI I2C Driver configs/qcom_defconfig | 1 + drivers/i2c/Kconfig| 10 + drivers/i2c/Makefile | 1 + drivers/i2c/geni_i2c.c | 576 + include/soc/qcom/geni-se.h | 265 + 5 files changed, 853 insertions(+) --- base-commit: b2511143fba4c0631446c968fb4c0d962b01d850 change-id: 20240419-topic-sm8x50-i2c-b51e576d5f57 Best regards, -- Neil Armstrong
Re: [PATCH v4 4/7] pinctrl: qcom: Add support for driving GPIO pins output
On 12/04/2024 11:54, Sumit Garg wrote:
Add support for driving the GPIO pins as output low or high.
Signed-off-by: Sumit Garg
---
drivers/pinctrl/qcom/pinctrl-qcom.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c
b/drivers/pinctrl/qcom/pinctrl-qcom.c
index 909e566acf5..e68971b37ff 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
@@ -29,15 +29,24 @@ struct msm_pinctrl_priv {
#define GPIO_CONFIG_REG(priv, x) \
(qcom_pin_offset((priv)->data->pin_data.pin_offsets, x))
-#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
-#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
-#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
-#define TLMM_GPIO_DISABLE BIT(9)
+#define GPIO_IN_OUT_REG(priv, x) \
+ (GPIO_CONFIG_REG(priv, x) + 0x4)
+
+#define TLMM_GPIO_PULL_MASKGENMASK(1, 0)
+#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
+#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
+#define TLMM_GPIO_OUTPUT_MASK BIT(1)
+#define TLMM_GPIO_OE_MASK BIT(9)
+
+/* GPIO register shifts. */
+#define GPIO_OUT_SHIFT 1
static const struct pinconf_param msm_conf_params[] = {
{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },
{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 },
+ { "output-high", PIN_CONFIG_OUTPUT, 1, },
+ { "output-low", PIN_CONFIG_OUTPUT, 0, },
};
static int msm_get_functions_count(struct udevice *dev)
@@ -90,7 +99,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int
pin_selector,
return 0;
clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
- TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, func << 2);
+ TLMM_FUNC_SEL_MASK | TLMM_GPIO_OE_MASK, func << 2);
return 0;
}
@@ -117,6 +126,12 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv,
pin_selector),
TLMM_GPIO_PULL_MASK, argument);
break;
+ case PIN_CONFIG_OUTPUT:
+ writel(argument << GPIO_OUT_SHIFT,
+ priv->base + GPIO_IN_OUT_REG(priv, pin_selector));
+ setbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
+TLMM_GPIO_OE_MASK);
+ break;
default:
return 0;
}
Reviewed-by: Neil Armstrong
Re: [PATCH 1/7] mmc: msm_sdhci: correct vendor_spec_cap0 register for v5
On 11/04/2024 15:59, Sumit Garg wrote:
On Tue, 9 Apr 2024 at 23:33, Caleb Connolly wrote:
The V4 and V5 controllers have quite varied register layouts. Inherit
the register offsets and naming from the Linux driver. More version
specific offsets can be inherited from Linux as needed.
Fixes: 364c22a ("mmc: msm_sdhci: Add SDCC version 5.0.0 support")
Signed-off-by: Caleb Connolly
---
drivers/mmc/msm_sdhci.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
This patch broke booting on the HMIBSC board, have you tested it on
db410c? It's very likely that this has caused regression there too.
Error observed:
sdhci_send_command: Timeout for status update: 0001
Indeed swapping the core_vendor_spec_capabilities0 between msm_sdhc_v5_var &
msm_sdhc_mci_var
fixes this and I'm now able to enable SDCard on the SM8550-HDK
Neil
-Sumit
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index 059cb3da77c5..f23d425144ef 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -32,11 +32,8 @@
#define SDCC_MCI_STATUS2 0x6C
#define SDCC_MCI_STATUS2_MCI_ACT 0x1
#define SDCC_MCI_HC_MODE 0x78
-/* Non standard (?) SDHCI register */
-#define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c
-
struct msm_sdhc_plat {
struct mmc_config cfg;
struct mmc mmc;
};
@@ -48,8 +45,10 @@ struct msm_sdhc {
};
struct msm_sdhc_variant_info {
bool mci_removed;
+
+ u32 core_vendor_spec_capabilities0;
};
DECLARE_GLOBAL_DATA_PTR;
@@ -180,9 +179,9 @@ static int msm_sdc_probe(struct udevice *dev)
*/
if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
- writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0);
+ writel(caps, host->ioaddr +
var_info->core_vendor_spec_capabilities0);
}
ret = mmc_of_parse(dev, >cfg);
if (ret)
@@ -243,12 +242,16 @@ static int msm_sdc_bind(struct udevice *dev)
}
static const struct msm_sdhc_variant_info msm_sdhc_mci_var = {
.mci_removed = false,
+
+ .core_vendor_spec_capabilities0 = 0x21c,
};
static const struct msm_sdhc_variant_info msm_sdhc_v5_var = {
.mci_removed = true,
+
+ .core_vendor_spec_capabilities0 = 0x11c,
};
static const struct udevice_id msm_mmc_ids[] = {
{ .compatible = "qcom,sdhci-msm-v4", .data = (ulong)_sdhc_mci_var
},
--
2.44.0
Re: [PATCH] usb: dwc3: support USB 3.1 controllers
On 11/04/2024 18:05, Caleb Connolly wrote:
The revision is different for these, add the additional check as in
xhci-dwc3 core_init code.
Signed-off-by: Caleb Connolly
---
drivers/usb/dwc3/core.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 96e850b7170f..db045f5822d4 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -594,9 +594,10 @@ static int dwc3_core_init(struct dwc3 *dwc)
int ret;
reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
/* This should read as U3 followed by revision number */
- if ((reg & DWC3_GSNPSID_MASK) != 0x5533) {
+ if ((reg & DWC3_GSNPSID_MASK) != 0x5533 &&
+ (reg & DWC3_GSNPSID_MASK) != 0x3331) {
dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
ret = -ENODEV;
goto err0;
}
Reviewed-by: Neil Armstrong
Tested-by: Neil Armstrong # on SM8550
Re: [PATCH v2 0/4] qcom: pinctrl drivers for qcm2290/sm6115/sm8250
On 10/04/2024 19:52, Caleb Connolly wrote: Introduce pinctrl drivers for three new SoCs and enable them. Signed-off-by: Caleb Connolly --- Changes in v2: - Fix a few formatting issues - Link to v1: https://lore.kernel.org/r/20240408-b4-qcom-rbx-soc-v1-0-900db37b8...@linaro.org --- Caleb Connolly (4): pinctrl: qcom: add qcm2290 pinctrl driver pinctrl: qcom: add sm6115 pinctrl driver pinctrl: qcom: add sm8250 pinctrl driver qcom_defconfig: enable pinctrl for new qcm2290/sm6115/sm8250 configs/qcom_defconfig | 3 + drivers/pinctrl/qcom/Kconfig | 21 drivers/pinctrl/qcom/Makefile | 3 + drivers/pinctrl/qcom/pinctrl-qcm2290.c | 70 drivers/pinctrl/qcom/pinctrl-sm6115.c | 200 + drivers/pinctrl/qcom/pinctrl-sm8250.c | 99 6 files changed, 396 insertions(+) --- change-id: 20240408-b4-qcom-rbx-soc-44ee99c8b799 base-commit: 4ba549b0a4e67c563785ab144edf47e108b34822 // Caleb (they/them) Reviewed-by: Neil Armstrong
[PATCH v2 2/2] qcom_defconfig: enable the Qualcomm Synopsys eUSB2 PHY driver
Enable the Qualcomm Synopsys eUSB2 PHY driver in Qualcomm defconfig. Signed-off-by: Neil Armstrong --- configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 1abb57345ff..b0ae5eb4df3 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -63,6 +63,7 @@ CONFIG_RGMII=y CONFIG_PHY=y CONFIG_PHY_QCOM_QUSB2=y CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y +CONFIG_PHY_QCOM_SNPS_EUSB2=y CONFIG_PINCTRL=y CONFIG_PINCTRL_QCOM_QCS404=y CONFIG_PINCTRL_QCOM_SDM845=y -- 2.34.1
[PATCH v2 1/2] phy: qcom: add Synopsys eUSB2 PHY driver
Add a driver for the new Synopsys eUSB2 PHY found in the SM8550 and SM8650 SoCs. Signed-off-by: Neil Armstrong --- drivers/phy/qcom/Kconfig | 8 + drivers/phy/qcom/Makefile | 1 + drivers/phy/qcom/phy-qcom-snps-eusb2.c | 366 + 3 files changed, 375 insertions(+) diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig index b9fe608c279..3aae1813352 100644 --- a/drivers/phy/qcom/Kconfig +++ b/drivers/phy/qcom/Kconfig @@ -27,6 +27,14 @@ config PHY_QCOM_USB_SNPS_FEMTO_V2 High-Speed PHY driver. This driver supports the Hi-Speed PHY which is usually paired with Synopsys DWC3 USB IPs on MSM SOCs. +config PHY_QCOM_SNPS_EUSB2 + tristate "Qualcomm Synopsys eUSB2 High-Speed PHY" + depends on PHY && ARCH_SNAPDRAGON + help + Enable this to support the Qualcomm Synopsys DesignWare eUSB2 + High-Speed PHY driver. This driver supports the Hi-Speed PHY which + is usually paired with Synopsys DWC3 USB IPs on MSM SOCs. + config PHY_QCOM_USB_HS_28NM tristate "Qualcomm 28nm High-Speed PHY" depends on PHY && ARCH_SNAPDRAGON diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile index 5f4db4a5378..a5153061dfb 100644 --- a/drivers/phy/qcom/Makefile +++ b/drivers/phy/qcom/Makefile @@ -2,5 +2,6 @@ obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2) += phy-qcom-snps-femto-v2.o +obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o diff --git a/drivers/phy/qcom/phy-qcom-snps-eusb2.c b/drivers/phy/qcom/phy-qcom-snps-eusb2.c new file mode 100644 index 000..b2655ac007c --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-snps-eusb2.c @@ -0,0 +1,366 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023-2024, Linaro Limited + * + * Based on the Linux phy-qcom-snps-eusb2.c driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define USB_PHY_UTMI_CTRL0 (0x3c) +#define SLEEPM BIT(0) +#define OPMODE_MASKGENMASK(4, 3) +#define OPMODE_NONDRIVING BIT(3) + +#define USB_PHY_UTMI_CTRL5 (0x50) +#define PORBIT(1) + +#define USB_PHY_HS_PHY_CTRL_COMMON0(0x54) +#define PHY_ENABLE BIT(0) +#define SIDDQ_SEL BIT(1) +#define SIDDQ BIT(2) +#define RETENABLEN BIT(3) +#define FSEL_MASK GENMASK(6, 4) +#define FSEL_19_2_MHZ_VAL (0x0) +#define FSEL_38_4_MHZ_VAL (0x4) + +#define USB_PHY_CFG_CTRL_1 (0x58) +#define PHY_CFG_PLL_CPBIAS_CNTRL_MASK GENMASK(7, 1) + +#define USB_PHY_CFG_CTRL_2 (0x5c) +#define PHY_CFG_PLL_FB_DIV_7_0_MASKGENMASK(7, 0) +#define DIV_7_0_19_2_MHZ_VAL (0x90) +#define DIV_7_0_38_4_MHZ_VAL (0xc8) + +#define USB_PHY_CFG_CTRL_3 (0x60) +#define PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(3, 0) +#define DIV_11_8_19_2_MHZ_VAL (0x1) +#define DIV_11_8_38_4_MHZ_VAL (0x0) + +#define PHY_CFG_PLL_REF_DIVGENMASK(7, 4) +#define PLL_REF_DIV_VAL(0x0) + +#define USB_PHY_HS_PHY_CTRL2 (0x64) +#define VBUSVLDEXT0BIT(0) +#define USB2_SUSPEND_N BIT(2) +#define USB2_SUSPEND_N_SEL BIT(3) +#define VBUS_DET_EXT_SEL BIT(4) + +#define USB_PHY_CFG_CTRL_4 (0x68) +#define PHY_CFG_PLL_GMP_CNTRL_MASK GENMASK(1, 0) +#define PHY_CFG_PLL_INT_CNTRL_MASK GENMASK(7, 2) + +#define USB_PHY_CFG_CTRL_5 (0x6c) +#define PHY_CFG_PLL_PROP_CNTRL_MASKGENMASK(4, 0) +#define PHY_CFG_PLL_VREF_TUNE_MASK GENMASK(7, 6) + +#define USB_PHY_CFG_CTRL_6 (0x70) +#define PHY_CFG_PLL_VCO_CNTRL_MASK GENMASK(2, 0) + +#define USB_PHY_CFG_CTRL_7 (0x74) + +#define USB_PHY_CFG_CTRL_8 (0x78) +#define PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(1, 0) +#define PHY_CFG_TX_FSLS_VREG_BYPASSBIT(2) +#define PHY_CFG_TX_HS_VREF_TUNE_MASK GENMASK(5, 3) +#define PHY_CFG_TX_HS_XV_TUNE_MASK GENMASK(7, 6) + +#define USB_PHY_CFG_CTRL_9 (0x7c) +#define PHY_CFG_TX_PREEMP_TUNE_MASKGENMASK(2, 0) +#define PHY_CFG_TX_RES_TUNE_MASK GENMASK(4, 3) +#define PHY_CFG_TX_RISE_TUNE_MASK GENMASK(6, 5) +#define PHY_CFG_RCAL_BYPASSBIT(7) + +#define USB_PHY_CFG_CTRL_10(0x80) + +#define USB_PHY_CFG0 (0x94) +#define DATAPATH_CTRL_OVERRIDE_EN BIT(0) +#define CMN_CTRL_OVE
[PATCH v2 0/2] phy: qcom: add support for the Qualcomm Synopsys eUSB2 PHY
Add support for the new Qualcomm Synopsys eUSB2 PHY found in the SM8550 and SM8650 SoCs. Finally enable the driver in the Qualcomm defconfig. Signed-off-by: Neil Armstrong --- Changes in v2: - fixed driver build failure due to missin } - Link to v1: https://lore.kernel.org/r/20240405-topic-sm8x50-usb-phy-v1-0-8a8604bf8...@linaro.org --- Neil Armstrong (2): phy: qcom: add Synopsys eUSB2 PHY driver qcom_defconfig: enable the Qualcomm Synopsys eUSB2 PHY driver configs/qcom_defconfig | 1 + drivers/phy/qcom/Kconfig | 8 + drivers/phy/qcom/Makefile | 1 + drivers/phy/qcom/phy-qcom-snps-eusb2.c | 366 + 4 files changed, 376 insertions(+) --- base-commit: f0e6aba1218bca578605697eed8aa94582bf57bb change-id: 20240404-topic-sm8x50-usb-phy-d09a98f72d1b Best regards, -- Neil Armstrong
[PATCH v2 3/3] button: qcom-pmic: add support for pmk8350 button configs
Finally add the entries for the qcom,pmk8350-pwrkey and qcom,pmk8350-resin
found on PMICs used with SM8350 and later SoCs.
Signed-off-by: Neil Armstrong
---
drivers/button/button-qcom-pmic.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/button/button-qcom-pmic.c
b/drivers/button/button-qcom-pmic.c
index f6da958097c..ad7fed3ddaa 100644
--- a/drivers/button/button-qcom-pmic.c
+++ b/drivers/button/button-qcom-pmic.c
@@ -36,6 +36,8 @@ struct qcom_pmic_btn_priv {
#define PON_INT_RT_STS0x10
#define PON_KPDPWR_N_SET 0
#define PON_RESIN_N_SET 1
+#define PON_GEN3_RESIN_N_SET 6
+#define PON_GEN3_KPDPWR_N_SET 7
static enum button_state_t qcom_pwrkey_get_state(struct udevice *dev)
{
@@ -69,6 +71,18 @@ static const struct qcom_pmic_btn_data
qcom_pmic_btn_data_table[] = {
.code = KEY_DOWN,
.label = "vol_down",
},
+ {
+ .compatible = "qcom,pmk8350-pwrkey",
+ .status_bit = PON_GEN3_KPDPWR_N_SET,
+ .code = KEY_ENTER,
+ .label = "pwrkey",
+ },
+ {
+ .compatible = "qcom,pmk8350-resin",
+ .status_bit = PON_GEN3_RESIN_N_SET,
+ .code = KEY_DOWN,
+ .label = "vol_down",
+ },
};
static const struct qcom_pmic_btn_data *button_qcom_pmic_match(ofnode node)
@@ -179,6 +193,7 @@ static const struct udevice_id qcom_pwrkey_ids[] = {
{ .compatible = "qcom,pm8916-pon" },
{ .compatible = "qcom,pm8941-pon" },
{ .compatible = "qcom,pm8998-pon" },
+ { .compatible = "qcom,pmk8350-pon" },
{ }
};
--
2.34.1
[PATCH v2 2/3] button: qcom-pmic: move node name checks to btn_data struct
Move node name checks to a proper data struct with all information
for the supported subnodes.
Replace the key offset defines with the Linux driver ones.
Signed-off-by: Neil Armstrong
---
drivers/button/button-qcom-pmic.c | 84 ++-
1 file changed, 56 insertions(+), 28 deletions(-)
diff --git a/drivers/button/button-qcom-pmic.c
b/drivers/button/button-qcom-pmic.c
index bad445efa86..f6da958097c 100644
--- a/drivers/button/button-qcom-pmic.c
+++ b/drivers/button/button-qcom-pmic.c
@@ -19,6 +19,13 @@
#define REG_TYPE 0x4
#define REG_SUBTYPE0x5
+struct qcom_pmic_btn_data {
+ char *compatible;
+ unsigned int status_bit;
+ int code;
+ char *label;
+};
+
struct qcom_pmic_btn_priv {
u32 base;
u32 status_bit;
@@ -27,11 +34,8 @@ struct qcom_pmic_btn_priv {
};
#define PON_INT_RT_STS0x10
-#define KPDPWR_ON_INT_BIT 0
-#define RESIN_ON_INT_BIT 1
-
-#define NODE_IS_PWRKEY(node) (!strncmp(ofnode_get_name(node), "pwrkey",
strlen("pwrkey")))
-#define NODE_IS_RESIN(node) (!strncmp(ofnode_get_name(node), "resin",
strlen("resin")))
+#define PON_KPDPWR_N_SET 0
+#define PON_RESIN_N_SET 1
static enum button_state_t qcom_pwrkey_get_state(struct udevice *dev)
{
@@ -52,10 +56,39 @@ static int qcom_pwrkey_get_code(struct udevice *dev)
return priv->code;
}
+static const struct qcom_pmic_btn_data qcom_pmic_btn_data_table[] = {
+ {
+ .compatible = "qcom,pm8941-pwrkey",
+ .status_bit = PON_KPDPWR_N_SET,
+ .code = KEY_ENTER,
+ .label = "pwrkey",
+ },
+ {
+ .compatible = "qcom,pm8941-resin",
+ .status_bit = PON_RESIN_N_SET,
+ .code = KEY_DOWN,
+ .label = "vol_down",
+ },
+};
+
+static const struct qcom_pmic_btn_data *button_qcom_pmic_match(ofnode node)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(qcom_pmic_btn_data_table); ++i) {
+ if (ofnode_device_is_compatible(node,
+
qcom_pmic_btn_data_table[i].compatible))
+ return _pmic_btn_data_table[i];
+ }
+
+ return NULL;
+}
+
static int qcom_pwrkey_probe(struct udevice *dev)
{
struct button_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct qcom_pmic_btn_priv *priv = dev_get_priv(dev);
+ const struct qcom_pmic_btn_data *btn_data;
ofnode node = dev_ofnode(dev);
int ret;
u64 base;
@@ -64,6 +97,14 @@ static int qcom_pwrkey_probe(struct udevice *dev)
if (!uc_plat->label)
return 0;
+ /* Get the data for the node compatible */
+ btn_data = button_qcom_pmic_match(node);
+ if (!btn_data)
+ return -EINVAL;
+
+ priv->status_bit = btn_data->status_bit;
+ priv->code = btn_data->code;
+
/* the pwrkey and resin nodes are children of the "pon" node, get the
* PMIC device to use in pmic_reg_* calls.
*/
@@ -87,23 +128,10 @@ static int qcom_pwrkey_probe(struct udevice *dev)
ret = pmic_reg_read(priv->pmic, priv->base + REG_SUBTYPE);
if (ret < 0 || (ret & 0x7) == 0) {
- printf("%s: unexpected PMCI function subtype %d\n", dev->name,
ret);
+ printf("%s: unexpected PMIC function subtype %d\n", dev->name,
ret);
return -ENXIO;
}
- if (NODE_IS_PWRKEY(node)) {
- priv->status_bit = 0;
- priv->code = KEY_ENTER;
- } else if (NODE_IS_RESIN(node)) {
- priv->status_bit = 1;
- priv->code = KEY_DOWN;
- } else {
- /* Should not get here! */
- printf("Invalid pon node '%s' should be 'pwrkey' or 'resin'\n",
- ofnode_get_name(node));
- return -EINVAL;
- }
-
return 0;
}
@@ -114,12 +142,20 @@ static int button_qcom_pmic_bind(struct udevice *parent)
int ret;
dev_for_each_subnode(node, parent) {
+ const struct qcom_pmic_btn_data *btn_data;
struct button_uc_plat *uc_plat;
const char *label;
if (!ofnode_is_enabled(node))
continue;
+ /* Get the data for the node compatible */
+ btn_data = button_qcom_pmic_match(node);
+ if (!btn_data) {
+ debug("Unknown button node '%s'\n",
ofnode_get_name(node));
+ continue;
+ }
+
ret = device_bind_driver_to_node(parent, "qcom_pwrkey",
[PATCH v2 1/3] gpio: qcom_pmic_gpio: add support for pm8550-gpio
Add support for PM8550 GPIO controller variant, keep read-only
until the GPIO and Pinctrl setup is fixed for new PMICs.
Signed-off-by: Neil Armstrong
---
drivers/gpio/qcom_pmic_gpio.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index 14a8210522b..dfb70faf94b 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -35,6 +35,8 @@
#define REG_SUBTYPE_GPIOC_8CH 0xd
#define REG_SUBTYPE_GPIO_LV0x10
#define REG_SUBTYPE_GPIO_MV0x11
+#define REG_SUBTYPE_GPIO_LV_VIN2 0x12
+#define REG_SUBTYPE_GPIO_MV_VIN3 0x13
#define REG_STATUS 0x08
#define REG_STATUS_VAL_MASK0x1
@@ -322,9 +324,20 @@ static int qcom_gpio_probe(struct udevice *dev)
return log_msg_ret("bad type", -ENXIO);
val = pmic_reg_read(plat->pmic, plat->pid + REG_SUBTYPE);
- if (val != REG_SUBTYPE_GPIO_4CH && val != REG_SUBTYPE_GPIOC_4CH &&
- val != REG_SUBTYPE_GPIO_LV && val != REG_SUBTYPE_GPIO_MV)
+ switch (val) {
+ case REG_SUBTYPE_GPIO_4CH:
+ case REG_SUBTYPE_GPIOC_4CH:
+ plat->lv_mv_type = false;
+ break;
+ case REG_SUBTYPE_GPIO_LV:
+ case REG_SUBTYPE_GPIO_MV:
+ case REG_SUBTYPE_GPIO_LV_VIN2:
+ case REG_SUBTYPE_GPIO_MV_VIN3:
+ plat->lv_mv_type = true;
+ break;
+ default:
return log_msg_ret("bad subtype", -ENXIO);
+ }
plat->lv_mv_type = val == REG_SUBTYPE_GPIO_LV ||
val == REG_SUBTYPE_GPIO_MV;
@@ -351,6 +364,7 @@ static const struct udevice_id qcom_gpio_ids[] = {
{ .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
{ .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
{ .compatible = "qcom,pms405-gpio" },
+ { .compatible = "qcom,pm8550-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
{ }
};
--
2.34.1
[PATCH v2 0/3] qcom: support SPMI buttons on SM8550 and SM8650
First add PMIC gpio variant on pm8550-gpio, then rework the qcom-pmic button driver to support data structs for each PMIC variant and finally add the data for the pmk8350 button configs. Signed-off-by: Neil Armstrong --- Changes in v2: - added missing qcom,pmk8350-pon compatible - Link to v1: https://lore.kernel.org/r/20240405-topic-sm8x50-spmi-clients-v1-0-c28603ebc...@linaro.org --- Neil Armstrong (3): gpio: qcom_pmic_gpio: add support for pm8550-gpio button: qcom-pmic: move node name checks to btn_data struct button: qcom-pmic: add support for pmk8350 button configs drivers/button/button-qcom-pmic.c | 99 --- drivers/gpio/qcom_pmic_gpio.c | 18 ++- 2 files changed, 87 insertions(+), 30 deletions(-) --- base-commit: f0e6aba1218bca578605697eed8aa94582bf57bb change-id: 20240404-topic-sm8x50-spmi-clients-d9a085aae979 Best regards, -- Neil Armstrong
Re: [PATCH 1/3] clk: qcom: Add SM8550 clock driver
On 10/04/2024 11:27, Sumit Garg wrote:
On Wed, 10 Apr 2024 at 14:46, Neil Armstrong wrote:
On 10/04/2024 11:13, Sumit Garg wrote:
Hi Neil,
On Thu, 4 Apr 2024 at 22:16, Neil Armstrong wrote:
Add the GCC and TCSRCC clock driver for the SM8550 SoC.
The GCC driver uses the clk-qcom infrastructure to support GDSCs,
Resets and gates. While the TCSRCC is a simpler clock driver which
only supports gates.
The GCC enable and set_rate callbacks contains some tweaks to
setup clocks for Debug UART, SDCard controller and USB.
Okay so these are the peripherals you intend to support to begin with.
The TCSRCC gates returns the XO frequency, which is used by the
Synopsys eUSB2 driver to determine the PHY configuration.
Signed-off-by: Neil Armstrong
---
drivers/clk/qcom/Kconfig| 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clock-sm8550.c | 335
3 files changed, 344 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 8dae635ac2c..c908a3d19c9 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -47,6 +47,14 @@ config CLK_QCOM_SDM845
on the Snapdragon 845 SoC. This driver supports the clocks
and resets exposed by the GCC hardware block.
+config CLK_QCOM_SM8550
+ bool "Qualcomm SM8550 GCC"
+ select CLK_QCOM
+ help
+ Say Y here to enable support for the Global Clock Controller
+ on the Snapdragon SM8550 SoC. This driver supports the clocks
+ and resets exposed by the GCC hardware block.
+
endmenu
endif
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index cb179fdac58..d9ac5719f49 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
+obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o
diff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c
new file mode 100644
index 000..c0249925cc7
--- /dev/null
+++ b/drivers/clk/qcom/clock-sm8550.c
@@ -0,0 +1,335 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Clock drivers for Qualcomm sm8550
+ *
+ * (C) Copyright 2024 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clock-qcom.h"
+
+/* On-board TCXO, TOFIX get from DT */
+#define TCXO_RATE 3840
+
+/* bi_tcxo_div2 divided after RPMh output */
+#define TCXO_DIV2_RATE (TCXO_RATE / 2)
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s2_clk_src[] = {
+ F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
+ F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
+ F(1920, CFG_CLK_SRC_CXO, 1, 0, 0),
+ F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
+ F(3200, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
+ F(4800, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
+ F(5120, CFG_CLK_SRC_GPLL0_EVEN, 1, 64, 375),
+ F(6400, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
+ F(7500, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
+ F(8000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
+ F(9600, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
+ F(1, CFG_CLK_SRC_GPLL0, 6, 0, 0),
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
+ F(40, CFG_CLK_SRC_CXO, 12, 1, 4),
+ F(2500, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
+ F(3750, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0),
+ F(5000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
+ F(1, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
+ /* TOFIX F(20200, CFG_CLK_SRC_GPLL9, 4, 0, 0), */
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
+ F(6667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
+ F(1, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
+ F(2, CFG_CLK_SRC_GPLL0, 3, 0, 0),
+ F(24000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static ulong sm8550_set_rate(struct clk *clk, ulong rate)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+ const struct freq_tbl *freq;
+
+ switch (clk->id) {
+ case GCC_QUPV3_WRAP1_S7_CLK: /* UART7 */
+ freq = qcom_find_freq(ftbl_gcc_qupv3_wrap1_s2_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x18898,
+freq->pre_div, freq->m, freq->n,
freq->src, 16);
+ return freq->freq;
+ case GCC_SDCC2_APPS_CLK:
+ freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x14018,
+freq->pre_div, freq->m, freq->n,
freq->src, 8);
+ return freq->freq
Re: [PATCH 1/3] clk: qcom: Add SM8550 clock driver
On 10/04/2024 11:13, Sumit Garg wrote:
Hi Neil,
On Thu, 4 Apr 2024 at 22:16, Neil Armstrong wrote:
Add the GCC and TCSRCC clock driver for the SM8550 SoC.
The GCC driver uses the clk-qcom infrastructure to support GDSCs,
Resets and gates. While the TCSRCC is a simpler clock driver which
only supports gates.
The GCC enable and set_rate callbacks contains some tweaks to
setup clocks for Debug UART, SDCard controller and USB.
Okay so these are the peripherals you intend to support to begin with.
The TCSRCC gates returns the XO frequency, which is used by the
Synopsys eUSB2 driver to determine the PHY configuration.
Signed-off-by: Neil Armstrong
---
drivers/clk/qcom/Kconfig| 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clock-sm8550.c | 335
3 files changed, 344 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 8dae635ac2c..c908a3d19c9 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -47,6 +47,14 @@ config CLK_QCOM_SDM845
on the Snapdragon 845 SoC. This driver supports the clocks
and resets exposed by the GCC hardware block.
+config CLK_QCOM_SM8550
+ bool "Qualcomm SM8550 GCC"
+ select CLK_QCOM
+ help
+ Say Y here to enable support for the Global Clock Controller
+ on the Snapdragon SM8550 SoC. This driver supports the clocks
+ and resets exposed by the GCC hardware block.
+
endmenu
endif
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index cb179fdac58..d9ac5719f49 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
+obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o
diff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c
new file mode 100644
index 000..c0249925cc7
--- /dev/null
+++ b/drivers/clk/qcom/clock-sm8550.c
@@ -0,0 +1,335 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Clock drivers for Qualcomm sm8550
+ *
+ * (C) Copyright 2024 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clock-qcom.h"
+
+/* On-board TCXO, TOFIX get from DT */
+#define TCXO_RATE 3840
+
+/* bi_tcxo_div2 divided after RPMh output */
+#define TCXO_DIV2_RATE (TCXO_RATE / 2)
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s2_clk_src[] = {
+ F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
+ F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
+ F(1920, CFG_CLK_SRC_CXO, 1, 0, 0),
+ F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
+ F(3200, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
+ F(4800, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
+ F(5120, CFG_CLK_SRC_GPLL0_EVEN, 1, 64, 375),
+ F(6400, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
+ F(7500, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
+ F(8000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
+ F(9600, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
+ F(1, CFG_CLK_SRC_GPLL0, 6, 0, 0),
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
+ F(40, CFG_CLK_SRC_CXO, 12, 1, 4),
+ F(2500, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
+ F(3750, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0),
+ F(5000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
+ F(1, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
+ /* TOFIX F(20200, CFG_CLK_SRC_GPLL9, 4, 0, 0), */
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
+ F(6667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
+ F(1, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
+ F(2, CFG_CLK_SRC_GPLL0, 3, 0, 0),
+ F(24000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static ulong sm8550_set_rate(struct clk *clk, ulong rate)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+ const struct freq_tbl *freq;
+
+ switch (clk->id) {
+ case GCC_QUPV3_WRAP1_S7_CLK: /* UART7 */
+ freq = qcom_find_freq(ftbl_gcc_qupv3_wrap1_s2_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x18898,
+freq->pre_div, freq->m, freq->n,
freq->src, 16);
+ return freq->freq;
+ case GCC_SDCC2_APPS_CLK:
+ freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x14018,
+freq->pre_div, freq->m, freq->n,
freq->src, 8);
+ return freq->freq;
+ case GCC_USB30_PRIM_MASTER_CLK:
+ freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, r
Re: [PATCH 6/7] pinctrl: qcom: sdm845: add special pin names
On 09/04/2024 20:03, Caleb Connolly wrote:
Adjust sdm845_get_pin_name() to return the correct names for the special
pins. This fixes a non-fatal -ENOSYS error when probing MMC.
Signed-off-by: Caleb Connolly
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c
b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 459a4329ec80..c1e5cc01fded 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
@@ -65,9 +65,20 @@ static const char *sdm845_get_function_name(struct udevice
*dev,
static const char *sdm845_get_pin_name(struct udevice *dev,
unsigned int selector)
{
- snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+ static const char *special_pins_names[] = {
+ "ufs_reset",
+ "sdc2_clk",
+ "sdc2_cmd",
+ "sdc2_data",
+ };
+
+ if (selector >= 150 && selector <= 154)
+ snprintf(pin_name, MAX_PIN_NAME_LEN,
special_pins_names[selector - 150]);
+ else
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+
return pin_name;
}
static unsigned int sdm845_get_function_mux(__maybe_unused unsigned int pin,
At some point we should add the pinconf settings for SDC and UFS, but for now
it's ok!
Reviewed-by: Neil Armstrong
Re: [PATCH 1/7] mmc: msm_sdhci: correct vendor_spec_cap0 register for v5
On 09/04/2024 20:03, Caleb Connolly wrote:
The V4 and V5 controllers have quite varied register layouts. Inherit
the register offsets and naming from the Linux driver. More version
specific offsets can be inherited from Linux as needed.
Fixes: 364c22a ("mmc: msm_sdhci: Add SDCC version 5.0.0 support")
Signed-off-by: Caleb Connolly
---
drivers/mmc/msm_sdhci.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index 059cb3da77c5..f23d425144ef 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -32,11 +32,8 @@
#define SDCC_MCI_STATUS2 0x6C
#define SDCC_MCI_STATUS2_MCI_ACT 0x1
#define SDCC_MCI_HC_MODE 0x78
-/* Non standard (?) SDHCI register */
-#define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c
-
struct msm_sdhc_plat {
struct mmc_config cfg;
struct mmc mmc;
};
@@ -48,8 +45,10 @@ struct msm_sdhc {
};
struct msm_sdhc_variant_info {
bool mci_removed;
+
+ u32 core_vendor_spec_capabilities0;
};
DECLARE_GLOBAL_DATA_PTR;
@@ -180,9 +179,9 @@ static int msm_sdc_probe(struct udevice *dev)
*/
if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
- writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0);
+ writel(caps, host->ioaddr +
var_info->core_vendor_spec_capabilities0);
}
ret = mmc_of_parse(dev, >cfg);
if (ret)
@@ -243,12 +242,16 @@ static int msm_sdc_bind(struct udevice *dev)
}
static const struct msm_sdhc_variant_info msm_sdhc_mci_var = {
.mci_removed = false,
+
+ .core_vendor_spec_capabilities0 = 0x21c,
};
static const struct msm_sdhc_variant_info msm_sdhc_v5_var = {
.mci_removed = true,
+
+ .core_vendor_spec_capabilities0 = 0x11c,
};
static const struct udevice_id msm_mmc_ids[] = {
{ .compatible = "qcom,sdhci-msm-v4", .data = (ulong)_sdhc_mci_var },
Reviewed-by: Neil Armstrong
Re: [PATCH 2/7] mmc: msm_sdhci: use modern DT handling
On 09/04/2024 20:03, Caleb Connolly wrote:
using fdtdec_* functions is incompatible with OF_LIVE and generally
offers a less friendly interface. Update to use dev_read_* functions
instead.
Signed-off-by: Caleb Connolly
---
drivers/mmc/msm_sdhci.c | 28 +++-
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index f23d425144ef..5689b4765122 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -205,9 +205,9 @@ static int msm_sdc_remove(struct udevice *dev)
var_info = (void *)dev_get_driver_data(dev);
/* Disable host-controller mode */
- if (!var_info->mci_removed)
+ if (!var_info->mci_removed && priv->base)
writel(0, priv->base + SDCC_MCI_HC_MODE);
clk_release_bulk(>clks);
@@ -215,23 +215,33 @@ static int msm_sdc_remove(struct udevice *dev)
}
static int msm_of_to_plat(struct udevice *dev)
{
- struct udevice *parent = dev->parent;
struct msm_sdhc *priv = dev_get_priv(dev);
+ const struct msm_sdhc_variant_info *var_info;
struct sdhci_host *host = >host;
- int node = dev_of_offset(dev);
+ int ret;
+
+ var_info = (void*)dev_get_driver_data(dev);
host->name = strdup(dev->name);
host->ioaddr = dev_read_addr_ptr(dev);
- host->bus_width = fdtdec_get_int(gd->fdt_blob, node, "bus-width", 4);
- host->index = fdtdec_get_uint(gd->fdt_blob, node, "index", 0);
- priv->base = (void *)fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
- dev_of_offset(parent), node, "reg", 1, NULL, false);
- if (priv->base == (void *)FDT_ADDR_T_NONE ||
- host->ioaddr == (void *)FDT_ADDR_T_NONE)
+ ret = dev_read_u32(dev, "bus-width", >bus_width);
+ if (ret)
+ host->bus_width = 4;
+ ret = dev_read_u32(dev, "index", >index);
+ if (ret)
+ host->index = 0;
+ priv->base = dev_read_addr_index_ptr(dev, 1);
+
+ if (!host->ioaddr)
return -EINVAL;
+ if (!var_info->mci_removed && !priv->base) {
+ printf("msm_sdhci: MCI base address not found\n");
+ return -EINVAL;
+ }
+
return 0;
}
static int msm_sdc_bind(struct udevice *dev)
Reviewed-by: Neil Armstrong
Re: [PATCH 3/7] mmc: msm_sdhci: print core version
On 09/04/2024 20:03, Caleb Connolly wrote:
This is useful for debugging.
Signed-off-by: Caleb Connolly
---
drivers/mmc/msm_sdhci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index 5689b4765122..ea5d6b4cbbee 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -172,8 +172,10 @@ static int msm_sdc_probe(struct udevice *dev)
core_major >>= SDCC_VERSION_MAJOR_SHIFT;
core_minor = core_version & SDCC_VERSION_MINOR_MASK;
+ log_debug("SDCC version %d.%d\n", core_major, core_minor);
+
/*
* Support for some capabilities is not advertised by newer
* controller versions and must be explicitly enabled.
*/
Reviewed-by: Neil Armstrong
Re: [PATCH 4/7] mmc: msm_sdhci: use a more sensible default clock rate
Hi,
On 09/04/2024 20:03, Caleb Connolly wrote:
We currently default to the lowest rate but this actually doesn't work
on most platforms. Default to the HS400 speed instead which is most
common on Qualcomm platforms.
Signed-off-by: Caleb Connolly
---
drivers/mmc/msm_sdhci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index ea5d6b4cbbee..2144772ac325 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -61,9 +61,9 @@ static int msm_sdc_clk_init(struct udevice *dev)
const char *clk_name;
ret = ofnode_read_u32(node, "clock-frequency", (uint *)(_rate));
if (ret)
- clk_rate = 40;
+ clk_rate = 20150;
I think we may either use INT_MAX so the clock driver uses the max freq in the
table,
or we could also parse the DT OPPs and take the max frequency ?
ret = clk_get_bulk(dev, >clks);
if (ret) {
log_warning("Couldn't get mmc clocks: %d\n", ret);
Re: [PATCH] MAINTAINERS: add Qualcomm mailing list
On 09/04/2024 17:02, Caleb Connolly wrote: Add the newly created u-boot-qcom mailing list to keep track of Qualcomm patches. Additionally, link to the U-Boot Snapdragon custodian tree. Signed-off-by: Caleb Connolly --- Cc: Neil Armstrong Cc: Sumit Garg Cc: u-boot@lists.denx.de --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0462ade4ac60..c0d2b5138fca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -602,9 +602,11 @@ F: arch/arm/dts/am335x-sancloud* ARM SNAPDRAGON M:Caleb Connolly M:Neil Armstrong R:Sumit Garg +L: u-boot-q...@groups.io S:Maintained +T: git https://source.denx.de/u-boot/custodians/u-boot-snapdragon.git F:arch/arm/dts/msm8*.dtsi F:arch/arm/dts/pm8???.dtsi F:arch/arm/dts/pms405.dtsi F:arch/arm/dts/sdm845.dtsi Reviewed-by: Neil Armstrong
Re: [PATCH 3/4] pinctrl: qcom: add sm8250 pinctrl driver
On 08/04/2024 15:07, Caleb Connolly wrote:
This SoC features a pinctrl block with north, south, and west tiles
accessible to the AP.
Signed-off-by: Caleb Connolly
---
drivers/pinctrl/qcom/Kconfig | 7 +++
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-sm8250.c | 96 +++
3 files changed, 104 insertions(+)
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index e7a9853ce47a..33c355ad3b24 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -54,7 +54,14 @@ config PINCTRL_QCOM_SM6115
help
Say Y here to enable support for pinctrl on the Snapdragon SM6115 SoC,
as well as the associated GPIO driver.
+config PINCTRL_QCOM_SM8250
+ bool "Qualcomm SM8250 GCC"
+ select PINCTRL_QCOM
+ help
+ Say Y here to enable support for pinctrl on the Snapdragon SM8250 SoC,
+ as well as the associated GPIO driver.
+
endmenu
endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index f00c4e6e10cc..7dce95e5acb2 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o
obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o
+obj-$(CONFIG_PINCTRL_QCOM_SM8250) += pinctrl-sm8250.o
\ No newline at end of file
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c
b/drivers/pinctrl/qcom/pinctrl-sm8250.c
new file mode 100644
index ..1a9d4534fa12
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm sm8250 pinctrl
+ *
+ * (C) Copyright 2024 Linaro Ltd.
+ *
+ */
+
+#include
+
+#include "pinctrl-qcom.h"
+
+#define WEST 0x
+#define SOUTH 0x0040
+#define NORTH 0x0080
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+static const struct pinctrl_function msm_pinctrl_functions[] = { { "qup12", 1
},
+{ "gpio", 0 },
+{
+
"sdc2_clk",
+} };
+
+static const unsigned int sm8250_pin_offsets[] = {
+ [0] = SOUTH, [1] = SOUTH, [2] = SOUTH, [3] = SOUTH, [4] =
NORTH, [5] = NORTH,
+ [6] = NORTH, [7] = NORTH, [8] = NORTH, [9] = NORTH, [10] =
NORTH, [11] = NORTH,
+ [12] = NORTH, [13] = NORTH, [14] = NORTH, [15] = NORTH, [16] =
NORTH, [17] = NORTH,
+ [18] = NORTH, [19] = NORTH, [20] = NORTH, [21] = NORTH, [22] =
NORTH, [23] = NORTH,
+ [24] = SOUTH, [25] = SOUTH, [26] = SOUTH, [27] = SOUTH, [28] =
NORTH, [29] = NORTH,
+ [30] = NORTH, [31] = NORTH, [32] = SOUTH, [33] = SOUTH, [34] =
SOUTH, [35] = SOUTH,
+ [36] = SOUTH, [37] = SOUTH, [38] = SOUTH, [39] = SOUTH, [40] =
SOUTH, [41] = SOUTH,
+ [42] = SOUTH, [43] = SOUTH, [44] = SOUTH, [45] = SOUTH, [46] =
SOUTH, [47] = SOUTH,
+ [48] = SOUTH, [49] = SOUTH, [50] = SOUTH, [51] = SOUTH, [52] =
SOUTH, [53] = SOUTH,
+ [54] = SOUTH, [55] = SOUTH, [56] = SOUTH, [57] = SOUTH, [58] =
SOUTH, [59] = SOUTH,
+ [60] = SOUTH, [61] = SOUTH, [62] = SOUTH, [63] = SOUTH, [64] =
SOUTH, [65] = SOUTH,
+ [66] = NORTH, [67] = NORTH, [68] = NORTH, [69] = SOUTH, [70] =
SOUTH, [71] = SOUTH,
+ [72] = SOUTH, [73] = SOUTH, [74] = SOUTH, [75] = SOUTH, [76] =
SOUTH, [77] = NORTH,
+ [78] = NORTH, [79] = NORTH, [80] = NORTH, [81] = NORTH, [82] =
NORTH, [83] = NORTH,
+ [84] = NORTH, [85] = SOUTH, [86] = SOUTH, [87] = SOUTH, [88] =
SOUTH, [89] = SOUTH,
+ [90] = SOUTH, [91] = SOUTH, [92] = NORTH, [93] = NORTH, [94] =
NORTH, [95] = NORTH,
+ [96] = NORTH, [97] = NORTH, [98] = NORTH, [99] = NORTH, [100] =
NORTH, [101] = NORTH,
+ [102] = NORTH, [103] = NORTH, [104] = NORTH, [105] = NORTH, [106] =
NORTH, [107] = NORTH,
+ [108] = NORTH, [109] = NORTH, [110] = NORTH, [111] = NORTH, [112] =
NORTH, [113] = NORTH,
+ [114] = NORTH, [115] = NORTH, [116] = NORTH, [117] = NORTH, [118] =
NORTH, [119] = NORTH,
+ [120] = NORTH, [121] = NORTH, [122] = NORTH, [123] = NORTH, [124] =
NORTH, [125] = SOUTH,
+ [126] = SOUTH, [127] = SOUTH, [128] = SOUTH, [129] = SOUTH, [130] =
SOUTH, [131] = SOUTH,
+ [132] = SOUTH, [133] = WEST, [134] = WEST, [135] = WEST, [136] =
WEST, [137] = WEST,
+ [138] = WEST, [139] = WEST, [140] = WEST, [141] = WEST, [142] =
WEST, [143] = WEST,
+ [144] = WEST, [145] = WEST, [146] = WEST, [147] =
Re: [PATCH 3/3] button: qcom-pmic: add support for pmk8350 button configs
On 05/04/2024 10:27, Neil Armstrong wrote:
Finally add the entries for the qcom,pmk8350-pwrkey and qcom,pmk8350-resin
found on PMICs used with SM8350 and later SoCs.
Signed-off-by: Neil Armstrong
---
drivers/button/button-qcom-pmic.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/button/button-qcom-pmic.c
b/drivers/button/button-qcom-pmic.c
index f6da958097c..6153601017b 100644
--- a/drivers/button/button-qcom-pmic.c
+++ b/drivers/button/button-qcom-pmic.c
@@ -36,6 +36,8 @@ struct qcom_pmic_btn_priv {
#define PON_INT_RT_STS0x10
#define PON_KPDPWR_N_SET 0
#define PON_RESIN_N_SET 1
+#define PON_GEN3_RESIN_N_SET 6
+#define PON_GEN3_KPDPWR_N_SET 7
static enum button_state_t qcom_pwrkey_get_state(struct udevice *dev)
{
@@ -69,6 +71,18 @@ static const struct qcom_pmic_btn_data
qcom_pmic_btn_data_table[] = {
.code = KEY_DOWN,
.label = "vol_down",
},
+ {
+ .compatible = "qcom,pmk8350-pwrkey",
+ .status_bit = PON_GEN3_KPDPWR_N_SET,
+ .code = KEY_ENTER,
+ .label = "pwrkey",
+ },
+ {
+ .compatible = "qcom,pmk8350-resin",
+ .status_bit = PON_GEN3_RESIN_N_SET,
+ .code = KEY_DOWN,
+ .label = "vol_down",
+ },
};
static const struct qcom_pmic_btn_data *button_qcom_pmic_match(ofnode node)
Missing change:
diff --git a/drivers/button/button-qcom-pmic.c
b/drivers/button/button-qcom-pmic.c
index 6153601017b..ad7fed3ddaa 100644
--- a/drivers/button/button-qcom-pmic.c
+++ b/drivers/button/button-qcom-pmic.c
@@ -193,6 +193,7 @@ static const struct udevice_id qcom_pwrkey_ids[] = {
{ .compatible = "qcom,pm8916-pon" },
{ .compatible = "qcom,pm8941-pon" },
{ .compatible = "qcom,pm8998-pon" },
+ { .compatible = "qcom,pmk8350-pon" },
{ }
};
Will send a v2 in a few days.
Neil
Re: [PATCH 1/2] phy: qcom: add Synopsys eUSB2 PHY driver
On 05/04/2024 10:35, Neil Armstrong wrote: Add a driver for the new Synopsys eUSB2 PHY found in the SM8550 and SM8650 SoCs. Signed-off-by: Neil Armstrong --- drivers/phy/qcom/Kconfig | 8 + drivers/phy/qcom/Makefile | 1 + drivers/phy/qcom/phy-qcom-snps-eusb2.c | 365 + 3 files changed, 374 insertions(+) diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig index b9fe608c279..3aae1813352 100644 --- a/drivers/phy/qcom/Kconfig +++ b/drivers/phy/qcom/Kconfig @@ -27,6 +27,14 @@ config PHY_QCOM_USB_SNPS_FEMTO_V2 High-Speed PHY driver. This driver supports the Hi-Speed PHY which is usually paired with Synopsys DWC3 USB IPs on MSM SOCs. +config PHY_QCOM_SNPS_EUSB2 + tristate "Qualcomm Synopsys eUSB2 High-Speed PHY" + depends on PHY && ARCH_SNAPDRAGON + help + Enable this to support the Qualcomm Synopsys DesignWare eUSB2 + High-Speed PHY driver. This driver supports the Hi-Speed PHY which + is usually paired with Synopsys DWC3 USB IPs on MSM SOCs. + config PHY_QCOM_USB_HS_28NM tristate "Qualcomm 28nm High-Speed PHY" depends on PHY && ARCH_SNAPDRAGON diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile index 5f4db4a5378..a5153061dfb 100644 --- a/drivers/phy/qcom/Makefile +++ b/drivers/phy/qcom/Makefile @@ -2,5 +2,6 @@ obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2) += phy-qcom-snps-femto-v2.o +obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o diff --git a/drivers/phy/qcom/phy-qcom-snps-eusb2.c b/drivers/phy/qcom/phy-qcom-snps-eusb2.c new file mode 100644 index 000..853b88458b7 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-snps-eusb2.c @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023-2024, Linaro Limited + * + * Based on the Linux phy-qcom-snps-eusb2.c driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define USB_PHY_UTMI_CTRL0 (0x3c) +#define SLEEPM BIT(0) +#define OPMODE_MASKGENMASK(4, 3) +#define OPMODE_NONDRIVING BIT(3) + +#define USB_PHY_UTMI_CTRL5 (0x50) +#define PORBIT(1) + +#define USB_PHY_HS_PHY_CTRL_COMMON0(0x54) +#define PHY_ENABLE BIT(0) +#define SIDDQ_SEL BIT(1) +#define SIDDQ BIT(2) +#define RETENABLEN BIT(3) +#define FSEL_MASK GENMASK(6, 4) +#define FSEL_19_2_MHZ_VAL (0x0) +#define FSEL_38_4_MHZ_VAL (0x4) + +#define USB_PHY_CFG_CTRL_1 (0x58) +#define PHY_CFG_PLL_CPBIAS_CNTRL_MASK GENMASK(7, 1) + +#define USB_PHY_CFG_CTRL_2 (0x5c) +#define PHY_CFG_PLL_FB_DIV_7_0_MASKGENMASK(7, 0) +#define DIV_7_0_19_2_MHZ_VAL (0x90) +#define DIV_7_0_38_4_MHZ_VAL (0xc8) + +#define USB_PHY_CFG_CTRL_3 (0x60) +#define PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(3, 0) +#define DIV_11_8_19_2_MHZ_VAL (0x1) +#define DIV_11_8_38_4_MHZ_VAL (0x0) + +#define PHY_CFG_PLL_REF_DIVGENMASK(7, 4) +#define PLL_REF_DIV_VAL(0x0) + +#define USB_PHY_HS_PHY_CTRL2 (0x64) +#define VBUSVLDEXT0BIT(0) +#define USB2_SUSPEND_N BIT(2) +#define USB2_SUSPEND_N_SEL BIT(3) +#define VBUS_DET_EXT_SEL BIT(4) + +#define USB_PHY_CFG_CTRL_4 (0x68) +#define PHY_CFG_PLL_GMP_CNTRL_MASK GENMASK(1, 0) +#define PHY_CFG_PLL_INT_CNTRL_MASK GENMASK(7, 2) + +#define USB_PHY_CFG_CTRL_5 (0x6c) +#define PHY_CFG_PLL_PROP_CNTRL_MASKGENMASK(4, 0) +#define PHY_CFG_PLL_VREF_TUNE_MASK GENMASK(7, 6) + +#define USB_PHY_CFG_CTRL_6 (0x70) +#define PHY_CFG_PLL_VCO_CNTRL_MASK GENMASK(2, 0) + +#define USB_PHY_CFG_CTRL_7 (0x74) + +#define USB_PHY_CFG_CTRL_8 (0x78) +#define PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(1, 0) +#define PHY_CFG_TX_FSLS_VREG_BYPASSBIT(2) +#define PHY_CFG_TX_HS_VREF_TUNE_MASK GENMASK(5, 3) +#define PHY_CFG_TX_HS_XV_TUNE_MASK GENMASK(7, 6) + +#define USB_PHY_CFG_CTRL_9 (0x7c) +#define PHY_CFG_TX_PREEMP_TUNE_MASKGENMASK(2, 0) +#define PHY_CFG_TX_RES_TUNE_MASK GENMASK(4, 3) +#define PHY_CFG_TX_RISE_TUNE_MASK GENMASK(6, 5) +#define PHY_CFG_RCAL_BYPASSBIT(7) + +#define USB_PHY_CFG_CTRL_10(0x80) + +#define USB_PHY_CFG0 (0x94) +#define DATAPATH_C
[PATCH 2/2] qcom_defconfig: enable the Qualcomm Synopsys eUSB2 PHY driver
Enable the Qualcomm Synopsys eUSB2 PHY driver in Qualcomm defconfig. Signed-off-by: Neil Armstrong --- configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 1abb57345ff..b0ae5eb4df3 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -63,6 +63,7 @@ CONFIG_RGMII=y CONFIG_PHY=y CONFIG_PHY_QCOM_QUSB2=y CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y +CONFIG_PHY_QCOM_SNPS_EUSB2=y CONFIG_PINCTRL=y CONFIG_PINCTRL_QCOM_QCS404=y CONFIG_PINCTRL_QCOM_SDM845=y -- 2.34.1
[PATCH 1/2] phy: qcom: add Synopsys eUSB2 PHY driver
Add a driver for the new Synopsys eUSB2 PHY found in the SM8550 and SM8650 SoCs. Signed-off-by: Neil Armstrong --- drivers/phy/qcom/Kconfig | 8 + drivers/phy/qcom/Makefile | 1 + drivers/phy/qcom/phy-qcom-snps-eusb2.c | 365 + 3 files changed, 374 insertions(+) diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig index b9fe608c279..3aae1813352 100644 --- a/drivers/phy/qcom/Kconfig +++ b/drivers/phy/qcom/Kconfig @@ -27,6 +27,14 @@ config PHY_QCOM_USB_SNPS_FEMTO_V2 High-Speed PHY driver. This driver supports the Hi-Speed PHY which is usually paired with Synopsys DWC3 USB IPs on MSM SOCs. +config PHY_QCOM_SNPS_EUSB2 + tristate "Qualcomm Synopsys eUSB2 High-Speed PHY" + depends on PHY && ARCH_SNAPDRAGON + help + Enable this to support the Qualcomm Synopsys DesignWare eUSB2 + High-Speed PHY driver. This driver supports the Hi-Speed PHY which + is usually paired with Synopsys DWC3 USB IPs on MSM SOCs. + config PHY_QCOM_USB_HS_28NM tristate "Qualcomm 28nm High-Speed PHY" depends on PHY && ARCH_SNAPDRAGON diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile index 5f4db4a5378..a5153061dfb 100644 --- a/drivers/phy/qcom/Makefile +++ b/drivers/phy/qcom/Makefile @@ -2,5 +2,6 @@ obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2) += phy-qcom-snps-femto-v2.o +obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o diff --git a/drivers/phy/qcom/phy-qcom-snps-eusb2.c b/drivers/phy/qcom/phy-qcom-snps-eusb2.c new file mode 100644 index 000..853b88458b7 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-snps-eusb2.c @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023-2024, Linaro Limited + * + * Based on the Linux phy-qcom-snps-eusb2.c driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define USB_PHY_UTMI_CTRL0 (0x3c) +#define SLEEPM BIT(0) +#define OPMODE_MASKGENMASK(4, 3) +#define OPMODE_NONDRIVING BIT(3) + +#define USB_PHY_UTMI_CTRL5 (0x50) +#define PORBIT(1) + +#define USB_PHY_HS_PHY_CTRL_COMMON0(0x54) +#define PHY_ENABLE BIT(0) +#define SIDDQ_SEL BIT(1) +#define SIDDQ BIT(2) +#define RETENABLEN BIT(3) +#define FSEL_MASK GENMASK(6, 4) +#define FSEL_19_2_MHZ_VAL (0x0) +#define FSEL_38_4_MHZ_VAL (0x4) + +#define USB_PHY_CFG_CTRL_1 (0x58) +#define PHY_CFG_PLL_CPBIAS_CNTRL_MASK GENMASK(7, 1) + +#define USB_PHY_CFG_CTRL_2 (0x5c) +#define PHY_CFG_PLL_FB_DIV_7_0_MASKGENMASK(7, 0) +#define DIV_7_0_19_2_MHZ_VAL (0x90) +#define DIV_7_0_38_4_MHZ_VAL (0xc8) + +#define USB_PHY_CFG_CTRL_3 (0x60) +#define PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(3, 0) +#define DIV_11_8_19_2_MHZ_VAL (0x1) +#define DIV_11_8_38_4_MHZ_VAL (0x0) + +#define PHY_CFG_PLL_REF_DIVGENMASK(7, 4) +#define PLL_REF_DIV_VAL(0x0) + +#define USB_PHY_HS_PHY_CTRL2 (0x64) +#define VBUSVLDEXT0BIT(0) +#define USB2_SUSPEND_N BIT(2) +#define USB2_SUSPEND_N_SEL BIT(3) +#define VBUS_DET_EXT_SEL BIT(4) + +#define USB_PHY_CFG_CTRL_4 (0x68) +#define PHY_CFG_PLL_GMP_CNTRL_MASK GENMASK(1, 0) +#define PHY_CFG_PLL_INT_CNTRL_MASK GENMASK(7, 2) + +#define USB_PHY_CFG_CTRL_5 (0x6c) +#define PHY_CFG_PLL_PROP_CNTRL_MASKGENMASK(4, 0) +#define PHY_CFG_PLL_VREF_TUNE_MASK GENMASK(7, 6) + +#define USB_PHY_CFG_CTRL_6 (0x70) +#define PHY_CFG_PLL_VCO_CNTRL_MASK GENMASK(2, 0) + +#define USB_PHY_CFG_CTRL_7 (0x74) + +#define USB_PHY_CFG_CTRL_8 (0x78) +#define PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(1, 0) +#define PHY_CFG_TX_FSLS_VREG_BYPASSBIT(2) +#define PHY_CFG_TX_HS_VREF_TUNE_MASK GENMASK(5, 3) +#define PHY_CFG_TX_HS_XV_TUNE_MASK GENMASK(7, 6) + +#define USB_PHY_CFG_CTRL_9 (0x7c) +#define PHY_CFG_TX_PREEMP_TUNE_MASKGENMASK(2, 0) +#define PHY_CFG_TX_RES_TUNE_MASK GENMASK(4, 3) +#define PHY_CFG_TX_RISE_TUNE_MASK GENMASK(6, 5) +#define PHY_CFG_RCAL_BYPASSBIT(7) + +#define USB_PHY_CFG_CTRL_10(0x80) + +#define USB_PHY_CFG0 (0x94) +#define DATAPATH_CTRL_OVERRIDE_EN BIT(0) +#define CMN_CTRL_OVE
[PATCH 0/2] phy: qcom: add support for the Qualcomm Synopsys eUSB2 PHY
Add support for the new Qualcomm Synopsys eUSB2 PHY found in the SM8550 and SM8650 SoCs. Finally enable the driver in the Qualcomm defconfig. Signed-off-by: Neil Armstrong --- Neil Armstrong (2): phy: qcom: add Synopsys eUSB2 PHY driver qcom_defconfig: enable the Qualcomm Synopsys eUSB2 PHY driver configs/qcom_defconfig | 1 + drivers/phy/qcom/Kconfig | 8 + drivers/phy/qcom/Makefile | 1 + drivers/phy/qcom/phy-qcom-snps-eusb2.c | 365 + 4 files changed, 375 insertions(+) --- base-commit: f0e6aba1218bca578605697eed8aa94582bf57bb change-id: 20240404-topic-sm8x50-usb-phy-d09a98f72d1b Best regards, -- Neil Armstrong
[PATCH 3/3] button: qcom-pmic: add support for pmk8350 button configs
Finally add the entries for the qcom,pmk8350-pwrkey and qcom,pmk8350-resin
found on PMICs used with SM8350 and later SoCs.
Signed-off-by: Neil Armstrong
---
drivers/button/button-qcom-pmic.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/button/button-qcom-pmic.c
b/drivers/button/button-qcom-pmic.c
index f6da958097c..6153601017b 100644
--- a/drivers/button/button-qcom-pmic.c
+++ b/drivers/button/button-qcom-pmic.c
@@ -36,6 +36,8 @@ struct qcom_pmic_btn_priv {
#define PON_INT_RT_STS0x10
#define PON_KPDPWR_N_SET 0
#define PON_RESIN_N_SET 1
+#define PON_GEN3_RESIN_N_SET 6
+#define PON_GEN3_KPDPWR_N_SET 7
static enum button_state_t qcom_pwrkey_get_state(struct udevice *dev)
{
@@ -69,6 +71,18 @@ static const struct qcom_pmic_btn_data
qcom_pmic_btn_data_table[] = {
.code = KEY_DOWN,
.label = "vol_down",
},
+ {
+ .compatible = "qcom,pmk8350-pwrkey",
+ .status_bit = PON_GEN3_KPDPWR_N_SET,
+ .code = KEY_ENTER,
+ .label = "pwrkey",
+ },
+ {
+ .compatible = "qcom,pmk8350-resin",
+ .status_bit = PON_GEN3_RESIN_N_SET,
+ .code = KEY_DOWN,
+ .label = "vol_down",
+ },
};
static const struct qcom_pmic_btn_data *button_qcom_pmic_match(ofnode node)
--
2.34.1
[PATCH 2/3] button: qcom-pmic: move node name checks to btn_data struct
Move node name checks to a proper data struct with all information
for the supported subnodes.
Replace the key offset defines with the Linux driver ones.
Signed-off-by: Neil Armstrong
---
drivers/button/button-qcom-pmic.c | 84 ++-
1 file changed, 56 insertions(+), 28 deletions(-)
diff --git a/drivers/button/button-qcom-pmic.c
b/drivers/button/button-qcom-pmic.c
index bad445efa86..f6da958097c 100644
--- a/drivers/button/button-qcom-pmic.c
+++ b/drivers/button/button-qcom-pmic.c
@@ -19,6 +19,13 @@
#define REG_TYPE 0x4
#define REG_SUBTYPE0x5
+struct qcom_pmic_btn_data {
+ char *compatible;
+ unsigned int status_bit;
+ int code;
+ char *label;
+};
+
struct qcom_pmic_btn_priv {
u32 base;
u32 status_bit;
@@ -27,11 +34,8 @@ struct qcom_pmic_btn_priv {
};
#define PON_INT_RT_STS0x10
-#define KPDPWR_ON_INT_BIT 0
-#define RESIN_ON_INT_BIT 1
-
-#define NODE_IS_PWRKEY(node) (!strncmp(ofnode_get_name(node), "pwrkey",
strlen("pwrkey")))
-#define NODE_IS_RESIN(node) (!strncmp(ofnode_get_name(node), "resin",
strlen("resin")))
+#define PON_KPDPWR_N_SET 0
+#define PON_RESIN_N_SET 1
static enum button_state_t qcom_pwrkey_get_state(struct udevice *dev)
{
@@ -52,10 +56,39 @@ static int qcom_pwrkey_get_code(struct udevice *dev)
return priv->code;
}
+static const struct qcom_pmic_btn_data qcom_pmic_btn_data_table[] = {
+ {
+ .compatible = "qcom,pm8941-pwrkey",
+ .status_bit = PON_KPDPWR_N_SET,
+ .code = KEY_ENTER,
+ .label = "pwrkey",
+ },
+ {
+ .compatible = "qcom,pm8941-resin",
+ .status_bit = PON_RESIN_N_SET,
+ .code = KEY_DOWN,
+ .label = "vol_down",
+ },
+};
+
+static const struct qcom_pmic_btn_data *button_qcom_pmic_match(ofnode node)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(qcom_pmic_btn_data_table); ++i) {
+ if (ofnode_device_is_compatible(node,
+
qcom_pmic_btn_data_table[i].compatible))
+ return _pmic_btn_data_table[i];
+ }
+
+ return NULL;
+}
+
static int qcom_pwrkey_probe(struct udevice *dev)
{
struct button_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct qcom_pmic_btn_priv *priv = dev_get_priv(dev);
+ const struct qcom_pmic_btn_data *btn_data;
ofnode node = dev_ofnode(dev);
int ret;
u64 base;
@@ -64,6 +97,14 @@ static int qcom_pwrkey_probe(struct udevice *dev)
if (!uc_plat->label)
return 0;
+ /* Get the data for the node compatible */
+ btn_data = button_qcom_pmic_match(node);
+ if (!btn_data)
+ return -EINVAL;
+
+ priv->status_bit = btn_data->status_bit;
+ priv->code = btn_data->code;
+
/* the pwrkey and resin nodes are children of the "pon" node, get the
* PMIC device to use in pmic_reg_* calls.
*/
@@ -87,23 +128,10 @@ static int qcom_pwrkey_probe(struct udevice *dev)
ret = pmic_reg_read(priv->pmic, priv->base + REG_SUBTYPE);
if (ret < 0 || (ret & 0x7) == 0) {
- printf("%s: unexpected PMCI function subtype %d\n", dev->name,
ret);
+ printf("%s: unexpected PMIC function subtype %d\n", dev->name,
ret);
return -ENXIO;
}
- if (NODE_IS_PWRKEY(node)) {
- priv->status_bit = 0;
- priv->code = KEY_ENTER;
- } else if (NODE_IS_RESIN(node)) {
- priv->status_bit = 1;
- priv->code = KEY_DOWN;
- } else {
- /* Should not get here! */
- printf("Invalid pon node '%s' should be 'pwrkey' or 'resin'\n",
- ofnode_get_name(node));
- return -EINVAL;
- }
-
return 0;
}
@@ -114,12 +142,20 @@ static int button_qcom_pmic_bind(struct udevice *parent)
int ret;
dev_for_each_subnode(node, parent) {
+ const struct qcom_pmic_btn_data *btn_data;
struct button_uc_plat *uc_plat;
const char *label;
if (!ofnode_is_enabled(node))
continue;
+ /* Get the data for the node compatible */
+ btn_data = button_qcom_pmic_match(node);
+ if (!btn_data) {
+ debug("Unknown button node '%s'\n",
ofnode_get_name(node));
+ continue;
+ }
+
ret = device_bind_driver_to_node(parent, "qcom_pwrkey",
[PATCH 1/3] gpio: qcom_pmic_gpio: add support for pm8550-gpio
Add support for PM8550 GPIO controller variant, keep read-only
until the GPIO and Pinctrl setup is fixed for new PMICs.
Signed-off-by: Neil Armstrong
---
drivers/gpio/qcom_pmic_gpio.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index 14a8210522b..dfb70faf94b 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -35,6 +35,8 @@
#define REG_SUBTYPE_GPIOC_8CH 0xd
#define REG_SUBTYPE_GPIO_LV0x10
#define REG_SUBTYPE_GPIO_MV0x11
+#define REG_SUBTYPE_GPIO_LV_VIN2 0x12
+#define REG_SUBTYPE_GPIO_MV_VIN3 0x13
#define REG_STATUS 0x08
#define REG_STATUS_VAL_MASK0x1
@@ -322,9 +324,20 @@ static int qcom_gpio_probe(struct udevice *dev)
return log_msg_ret("bad type", -ENXIO);
val = pmic_reg_read(plat->pmic, plat->pid + REG_SUBTYPE);
- if (val != REG_SUBTYPE_GPIO_4CH && val != REG_SUBTYPE_GPIOC_4CH &&
- val != REG_SUBTYPE_GPIO_LV && val != REG_SUBTYPE_GPIO_MV)
+ switch (val) {
+ case REG_SUBTYPE_GPIO_4CH:
+ case REG_SUBTYPE_GPIOC_4CH:
+ plat->lv_mv_type = false;
+ break;
+ case REG_SUBTYPE_GPIO_LV:
+ case REG_SUBTYPE_GPIO_MV:
+ case REG_SUBTYPE_GPIO_LV_VIN2:
+ case REG_SUBTYPE_GPIO_MV_VIN3:
+ plat->lv_mv_type = true;
+ break;
+ default:
return log_msg_ret("bad subtype", -ENXIO);
+ }
plat->lv_mv_type = val == REG_SUBTYPE_GPIO_LV ||
val == REG_SUBTYPE_GPIO_MV;
@@ -351,6 +364,7 @@ static const struct udevice_id qcom_gpio_ids[] = {
{ .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
{ .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
{ .compatible = "qcom,pms405-gpio" },
+ { .compatible = "qcom,pm8550-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
{ }
};
--
2.34.1
[PATCH 0/3] qcom: support SPMI buttons on SM8550 and SM8650
First add PMIC gpio variant on pm8550-gpio, then rework the qcom-pmic button driver to support data structs for each PMIC variant and finally add the data for the pmk8350 button configs. Signed-off-by: Neil Armstrong --- Neil Armstrong (3): gpio: qcom_pmic_gpio: add support for pm8550-gpio button: qcom-pmic: move node name checks to btn_data struct button: qcom-pmic: add support for pmk8350 button configs drivers/button/button-qcom-pmic.c | 98 --- drivers/gpio/qcom_pmic_gpio.c | 18 ++- 2 files changed, 86 insertions(+), 30 deletions(-) --- base-commit: f0e6aba1218bca578605697eed8aa94582bf57bb change-id: 20240404-topic-sm8x50-spmi-clients-d9a085aae979 Best regards, -- Neil Armstrong
[PATCH 4/4] spmi: msm: support controller version 7
Add the defines and support for SPMI arbiters version 7,
which can handle up to 1024 peripherals, and can also drive
a secondary bus which is not implemented yet.
Signed-off-by: Neil Armstrong
---
drivers/spmi/spmi-msm.c | 33 +
1 file changed, 29 insertions(+), 4 deletions(-)
diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
index 46e2e09dc26..244de69b359 100644
--- a/drivers/spmi/spmi-msm.c
+++ b/drivers/spmi/spmi-msm.c
@@ -23,13 +23,17 @@ DECLARE_GLOBAL_DATA_PTR;
#define PMIC_ARB_VERSION_V2_MIN 0x2001
#define PMIC_ARB_VERSION_V3_MIN 0x3000
#define PMIC_ARB_VERSION_V5_MIN 0x5000
+#define PMIC_ARB_VERSION_V7_MIN0x7000
#define APID_MAP_OFFSET_V1_V2_V3 (0x800)
#define APID_MAP_OFFSET_V5 (0x900)
+#define APID_MAP_OFFSET_V7 (0x2000)
#define ARB_CHANNEL_OFFSET(n) (0x4 * (n))
#define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
#define SPMI_V5_OBS_CH_OFFSET(chnl) ((chnl) * 0x80)
+#define SPMI_V7_OBS_CH_OFFSET(chnl) ((chnl) * 0x20)
#define SPMI_V5_RW_CH_OFFSET(chnl) ((chnl) * 0x1)
+#define SPMI_V7_RW_CH_OFFSET(chnl) ((chnl) * 0x1000)
#define SPMI_OWNERSHIP_PERIPH2OWNER(x) ((x) & 0x7)
@@ -52,6 +56,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define SPMI_MAX_CHANNELS 128
#define SPMI_MAX_CHANNELS_V5 512
+#define SPMI_MAX_CHANNELS_V7 1024
#define SPMI_MAX_SLAVES 16
#define SPMI_MAX_PERIPH 256
@@ -62,7 +67,8 @@ enum arb_ver {
V1 = 1,
V2,
V3,
- V5 = 5
+ V5 = 5,
+ V7 = 7
};
/*
@@ -133,6 +139,12 @@ static int msm_spmi_write(struct udevice *dev, int usid,
int pid, int off,
case V5:
ch_offset = SPMI_V5_RW_CH_OFFSET(channel);
+ reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_WRITE_LONG, off);
+ break;
+
+ case V7:
+ ch_offset = SPMI_V7_RW_CH_OFFSET(channel);
+
reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_WRITE_LONG, off);
break;
}
@@ -196,6 +208,13 @@ static int msm_spmi_read(struct udevice *dev, int usid,
int pid, int off)
case V5:
ch_offset = SPMI_V5_OBS_CH_OFFSET(channel);
+ /* Prepare read command */
+ reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_READ_LONG, off);
+ break;
+
+ case V7:
+ ch_offset = SPMI_V7_OBS_CH_OFFSET(channel);
+
/* Prepare read command */
reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_READ_LONG, off);
break;
@@ -250,10 +269,16 @@ static int msm_spmi_probe(struct udevice *dev)
priv->arb_ver = V3;
priv->arb_chnl = core_addr + APID_MAP_OFFSET_V1_V2_V3;
priv->max_channels = SPMI_MAX_CHANNELS;
- } else {
+ } else if (hw_ver < PMIC_ARB_VERSION_V7_MIN) {
priv->arb_ver = V5;
priv->arb_chnl = core_addr + APID_MAP_OFFSET_V5;
- priv->max_channels = SPMI_MAX_CHANNELS_V5;
+ priv->max_channels = SPMI_MAX_CHANNELS;
+ priv->spmi_cnfg = dev_read_addr_name(dev, "cnfg");
+ } else {
+ /* TOFIX: handle second bus */
+ priv->arb_ver = V7;
+ priv->arb_chnl = core_addr + APID_MAP_OFFSET_V7;
+ priv->max_channels = SPMI_MAX_CHANNELS_V7;
priv->spmi_cnfg = dev_read_addr_name(dev, "cnfg");
}
@@ -276,7 +301,7 @@ static int msm_spmi_probe(struct udevice *dev)
priv->channel_map[slave_id][pid] = i;
/* Mark channels read-only when from different owner */
- if (priv->arb_ver == V5) {
+ if (priv->arb_ver == V5 || priv->arb_ver == V7) {
uint32_t cnfg = readl(priv->spmi_cnfg +
ARB_CHANNEL_OFFSET(i));
uint8_t owner = SPMI_OWNERSHIP_PERIPH2OWNER(cnfg);
--
2.34.1
[PATCH 3/4] spmi: msm: handle peripheral ownership
The cnfg registers provides the owner id for each peripheral,
so we can use this id to check if we're allowed to write register
to each peripherals.
Since the v5 can handle more peripherals, add the max_channels to
scan more starting from version 5, make the channel_map store
32bit values and introduce the SPMI_CHANNEL_READ_ONLY flag to
mark a peripheral as read-only.
Signed-off-by: Neil Armstrong
---
drivers/spmi/spmi-msm.c | 33 +
1 file changed, 29 insertions(+), 4 deletions(-)
diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
index 68bb8a38c3c..46e2e09dc26 100644
--- a/drivers/spmi/spmi-msm.c
+++ b/drivers/spmi/spmi-msm.c
@@ -31,6 +31,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define SPMI_V5_OBS_CH_OFFSET(chnl) ((chnl) * 0x80)
#define SPMI_V5_RW_CH_OFFSET(chnl) ((chnl) * 0x1)
+#define SPMI_OWNERSHIP_PERIPH2OWNER(x) ((x) & 0x7)
+
#define SPMI_REG_CMD0 0x0
#define SPMI_REG_CONFIG 0x4
#define SPMI_REG_STATUS 0x8
@@ -49,9 +51,13 @@ DECLARE_GLOBAL_DATA_PTR;
#define SPMI_STATUS_DONE 0x1
#define SPMI_MAX_CHANNELS 128
+#define SPMI_MAX_CHANNELS_V5 512
#define SPMI_MAX_SLAVES 16
#define SPMI_MAX_PERIPH 256
+#define SPMI_CHANNEL_READ_ONLY BIT(31)
+#define SPMI_CHANNEL_MASK 0x
+
enum arb_ver {
V1 = 1,
V2,
@@ -72,8 +78,11 @@ struct msm_spmi_priv {
phys_addr_t arb_chnl; /* ARB channel mapping base */
phys_addr_t spmi_chnls; /* SPMI channels */
phys_addr_t spmi_obs; /* SPMI observer */
+ phys_addr_t spmi_cnfg; /* SPMI config */
+ u32 owner; /* Current owner */
+ unsigned int max_channels; /* Max channels */
/* SPMI channel map */
- uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
+ uint32_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
/* SPMI bus arbiter version */
u32 arb_ver;
};
@@ -100,8 +109,10 @@ static int msm_spmi_write(struct udevice *dev, int usid,
int pid, int off,
return -EIO;
if (pid >= SPMI_MAX_PERIPH)
return -EIO;
+ if (priv->channel_map[usid][pid] & SPMI_CHANNEL_READ_ONLY)
+ return -EPERM;
- channel = priv->channel_map[usid][pid];
+ channel = priv->channel_map[usid][pid] & SPMI_CHANNEL_MASK;
dev_dbg(dev, "[%d:%d] %s: channel %d\n", usid, pid, __func__, channel);
@@ -162,7 +173,7 @@ static int msm_spmi_read(struct udevice *dev, int usid, int
pid, int off)
if (pid >= SPMI_MAX_PERIPH)
return -EIO;
- channel = priv->channel_map[usid][pid];
+ channel = priv->channel_map[usid][pid] & SPMI_CHANNEL_MASK;
dev_dbg(dev, "[%d:%d] %s: channel %d\n", usid, pid, __func__, channel);
@@ -227,18 +238,23 @@ static int msm_spmi_probe(struct udevice *dev)
core_addr = dev_read_addr_name(dev, "core");
priv->spmi_chnls = dev_read_addr_name(dev, "chnls");
priv->spmi_obs = dev_read_addr_name(dev, "obsrvr");
+ dev_read_u32(dev, "qcom,ee", >owner);
hw_ver = readl(core_addr + PMIC_ARB_VERSION);
if (hw_ver < PMIC_ARB_VERSION_V3_MIN) {
priv->arb_ver = V2;
priv->arb_chnl = core_addr + APID_MAP_OFFSET_V1_V2_V3;
+ priv->max_channels = SPMI_MAX_CHANNELS;
} else if (hw_ver < PMIC_ARB_VERSION_V5_MIN) {
priv->arb_ver = V3;
priv->arb_chnl = core_addr + APID_MAP_OFFSET_V1_V2_V3;
+ priv->max_channels = SPMI_MAX_CHANNELS;
} else {
priv->arb_ver = V5;
priv->arb_chnl = core_addr + APID_MAP_OFFSET_V5;
+ priv->max_channels = SPMI_MAX_CHANNELS_V5;
+ priv->spmi_cnfg = dev_read_addr_name(dev, "cnfg");
}
dev_dbg(dev, "PMIC Arb Version-%d (%#x)\n", hw_ver >> 28, hw_ver);
@@ -252,12 +268,21 @@ static int msm_spmi_probe(struct udevice *dev)
dev_dbg(dev, "priv->spmi_chnls address (%#08llx)\n", priv->spmi_chnls);
dev_dbg(dev, "priv->spmi_obs address (%#08llx)\n", priv->spmi_obs);
/* Scan peripherals connected to each SPMI channel */
- for (i = 0; i < SPMI_MAX_PERIPH; i++) {
+ for (i = 0; i < priv->max_channels; i++) {
uint32_t periph = readl(priv->arb_chnl + ARB_CHANNEL_OFFSET(i));
uint8_t slave_id = (periph & 0xf) >> 16;
uint8_t pid = (periph & 0xff00) >> 8;
priv->channel_map[slave_id][pid] = i;
+
+ /* Mark channels read-only when from different owner */
+ if (priv->arb_ver == V5) {
+ uint32_t cnfg = readl(priv->spmi_cnfg +
ARB_CHANNEL_OFFSET(i));
+ uint8_t owner = SPMI_OWNERSHIP_PERIPH2OWNER(cnfg);
+
+ if (owner != priv->owner)
+ priv->channel_map[slave_id][pid] |=
SPMI_CHANNEL_READ_ONLY;
+ }
}
return 0;
}
--
2.34.1
[PATCH 2/4] spmi: msm: properly format command
Since version 2, the cmd format has changed, takes helpers
from Linux driver and use a switch/case to handle all
versions in msm_spmi_write/read() command.
Signed-off-by: Neil Armstrong
---
drivers/spmi/spmi-msm.c | 75 -
1 file changed, 55 insertions(+), 20 deletions(-)
diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
index 97383d8c7b8..68bb8a38c3c 100644
--- a/drivers/spmi/spmi-msm.c
+++ b/drivers/spmi/spmi-msm.c
@@ -78,6 +78,16 @@ struct msm_spmi_priv {
u32 arb_ver;
};
+static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u8 pid, u8 off)
+{
+ return (opc << 27) | (sid << 20) | (pid << 12) | (off << 4) | 1;
+}
+
+static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 off)
+{
+ return (opc << 27) | (off << 4) | 1;
+}
+
static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
uint8_t val)
{
@@ -93,24 +103,35 @@ static int msm_spmi_write(struct udevice *dev, int usid,
int pid, int off,
channel = priv->channel_map[usid][pid];
- if (priv->arb_ver == V5)
- ch_offset = SPMI_V5_RW_CH_OFFSET(channel);
- else
+ dev_dbg(dev, "[%d:%d] %s: channel %d\n", usid, pid, __func__, channel);
+
+ switch (priv->arb_ver) {
+ case V1:
+ ch_offset = SPMI_CH_OFFSET(channel);
+
+ reg = pmic_arb_fmt_cmd_v1(SPMI_CMD_EXT_REG_WRITE_LONG,
+ usid, pid, off);
+ break;
+
+ case V2:
ch_offset = SPMI_CH_OFFSET(channel);
+ reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_WRITE_LONG, off);
+ break;
+
+ case V5:
+ ch_offset = SPMI_V5_RW_CH_OFFSET(channel);
+
+ reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_WRITE_LONG, off);
+ break;
+ }
+
/* Disable IRQ mode for the current channel*/
writel(0x0, priv->spmi_chnls + ch_offset + SPMI_REG_CONFIG);
/* Write single byte */
writel(val, priv->spmi_chnls + ch_offset + SPMI_REG_WDATA);
- /* Prepare write command */
- reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
- reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
- reg |= (pid << SPMI_CMD_ADDR_SHIFT);
- reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
- reg |= 1; /* byte count */
-
/* Send write command */
writel(reg, priv->spmi_chnls + ch_offset + SPMI_REG_CMD0);
@@ -143,21 +164,35 @@ static int msm_spmi_read(struct udevice *dev, int usid,
int pid, int off)
channel = priv->channel_map[usid][pid];
- if (priv->arb_ver == V5)
- ch_offset = SPMI_V5_OBS_CH_OFFSET(channel);
- else
+ dev_dbg(dev, "[%d:%d] %s: channel %d\n", usid, pid, __func__, channel);
+
+ switch (priv->arb_ver) {
+ case V1:
+ ch_offset = SPMI_CH_OFFSET(channel);
+
+ /* Prepare read command */
+ reg = pmic_arb_fmt_cmd_v1(SPMI_CMD_EXT_REG_READ_LONG,
+ usid, pid, off);
+ break;
+
+ case V2:
ch_offset = SPMI_CH_OFFSET(channel);
+ /* Prepare read command */
+ reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_READ_LONG, off);
+ break;
+
+ case V5:
+ ch_offset = SPMI_V5_OBS_CH_OFFSET(channel);
+
+ /* Prepare read command */
+ reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_READ_LONG, off);
+ break;
+ }
+
/* Disable IRQ mode for the current channel*/
writel(0x0, priv->spmi_obs + ch_offset + SPMI_REG_CONFIG);
- /* Prepare read command */
- reg |= SPMI_CMD_EXT_REG_READ_LONG << SPMI_CMD_OPCODE_SHIFT;
- reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
- reg |= (pid << SPMI_CMD_ADDR_SHIFT);
- reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
- reg |= 1; /* byte count */
-
/* Request read */
writel(reg, priv->spmi_obs + ch_offset + SPMI_REG_CMD0);
--
2.34.1
[PATCH 1/4] spmi: msm: fix version 5 support
Properly use ch_offset in msm_spmi_write() reg access.
Fixes: f5a2d6b4b03 ("spmi: msm: add arbiter version 5 support")
Signed-off-by: Neil Armstrong
---
drivers/spmi/spmi-msm.c | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
index 5fe8a70abca..97383d8c7b8 100644
--- a/drivers/spmi/spmi-msm.c
+++ b/drivers/spmi/spmi-msm.c
@@ -93,12 +93,16 @@ static int msm_spmi_write(struct udevice *dev, int usid,
int pid, int off,
channel = priv->channel_map[usid][pid];
+ if (priv->arb_ver == V5)
+ ch_offset = SPMI_V5_RW_CH_OFFSET(channel);
+ else
+ ch_offset = SPMI_CH_OFFSET(channel);
+
/* Disable IRQ mode for the current channel*/
- writel(0x0,
- priv->spmi_chnls + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
+ writel(0x0, priv->spmi_chnls + ch_offset + SPMI_REG_CONFIG);
/* Write single byte */
- writel(val, priv->spmi_chnls + SPMI_CH_OFFSET(channel) +
SPMI_REG_WDATA);
+ writel(val, priv->spmi_chnls + ch_offset + SPMI_REG_WDATA);
/* Prepare write command */
reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
@@ -107,18 +111,13 @@ static int msm_spmi_write(struct udevice *dev, int usid,
int pid, int off,
reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
reg |= 1; /* byte count */
- if (priv->arb_ver == V5)
- ch_offset = SPMI_V5_RW_CH_OFFSET(channel);
- else
- ch_offset = SPMI_CH_OFFSET(channel);
-
/* Send write command */
- writel(reg, priv->spmi_chnls + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
+ writel(reg, priv->spmi_chnls + ch_offset + SPMI_REG_CMD0);
/* Wait till CMD DONE status */
reg = 0;
while (!reg) {
- reg = readl(priv->spmi_chnls + SPMI_CH_OFFSET(channel) +
+ reg = readl(priv->spmi_chnls + ch_offset +
SPMI_REG_STATUS);
}
--
2.34.1
[PATCH 0/4] smpi: msm: fix version 5 and add version 7 support
First, fix version 5 support by using the right ch_offset in then msm_spmi_write() reg accesses. Then: - properly format command by importing helpers from Linux driver and use a switch/case to handle all versions in msm_spmi_write/read() command. - handle peripheral ownership by poking into the cnfg registers and mark periperal as read-only when the owner id doesn't match - finally add version 7 defines SPMI Arbiter Version 7 is present on SM8450, SM8550 and SM8650 SoC. Signed-off-by: Neil Armstrong --- Neil Armstrong (4): spmi: msm: fix version 5 support spmi: msm: properly format command spmi: msm: handle peripheral ownership spmi: msm: support controller version 7 drivers/spmi/spmi-msm.c | 148 +--- 1 file changed, 116 insertions(+), 32 deletions(-) --- base-commit: f0e6aba1218bca578605697eed8aa94582bf57bb change-id: 20240404-topic-sm8x50-spmi-fixes-aec9b392813b Best regards, -- Neil Armstrong
[PATCH 2/3] pinctrl: qcom: Add SM8650 pinctrl driver
Add pinctrl driver for the TLMM block found in the SM8650 SoC.
This driver only handles the gpio and qup2_se7 pinmux, and makes sure
the pinconf applies on SDC2 pins.
Signed-off-by: Neil Armstrong
---
drivers/pinctrl/qcom/Kconfig | 7
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-sm8650.c | 75 +++
3 files changed, 83 insertions(+)
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index f760bbcdd52..e0196a83e60 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -48,6 +48,13 @@ config PINCTRL_QCOM_SM8550
Say Y here to enable support for pinctrl on the Snapdragon SM8550 SoC,
as well as the associated GPIO driver.
+config PINCTRL_QCOM_SM8650
+ bool "Qualcomm SM8650 GCC"
+ select PINCTRL_QCOM
+ help
+ Say Y here to enable support for pinctrl on the Snapdragon SM8650 SoC,
+ as well as the associated GPIO driver.
+
endmenu
endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 970902e28c8..d83e89ef4f0 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o
+obj-$(CONFIG_PINCTRL_QCOM_SM8650) += pinctrl-sm8650.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c
b/drivers/pinctrl/qcom/pinctrl-sm8650.c
new file mode 100644
index 000..932132fa4a6
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm sm8650 pinctrl
+ *
+ * (C) Copyright 2024 Linaro Ltd.
+ *
+ */
+
+#include
+#include
+
+#include "pinctrl-qcom.h"
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+ {"qup2_se7", 1},
+ {"gpio", 0},
+};
+
+static const char *sm8650_get_function_name(struct udevice *dev,
+unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].name;
+}
+
+static const char *sm8650_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ static const char *special_pins_names[] = {
+ "ufs_reset",
+ "sdc2_clk",
+ "sdc2_cmd",
+ "sdc2_data",
+ };
+
+ if (selector >= 210 && selector <= 213)
+ snprintf(pin_name, MAX_PIN_NAME_LEN,
special_pins_names[selector - 210]);
+ else
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+
+ return pin_name;
+}
+
+static unsigned int sm8650_get_function_mux(__maybe_unused unsigned int pin,
+ unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].val;
+}
+
+static struct msm_pinctrl_data sm8650_data = {
+ .pin_data = {
+ .pin_count = 214,
+ .special_pins_start = 210,
+ },
+ .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+ .get_function_name = sm8650_get_function_name,
+ .get_function_mux = sm8650_get_function_mux,
+ .get_pin_name = sm8650_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+ { .compatible = "qcom,sm8650-tlmm", .data = (ulong)_data },
+ { /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(pinctrl_sm8650) = {
+ .name = "pinctrl_sm8650",
+ .id = UCLASS_NOP,
+ .of_match = msm_pinctrl_ids,
+ .ops= _pinctrl_ops,
+ .bind = msm_pinctrl_bind,
+};
+
--
2.34.1
[PATCH 3/3] qcom_defconfig: enable SM8550 & SM8650 pinctrl driver
Enable the SM8550 & SM8650 pinctrl drivers for Qualcomm defconfig. Signed-off-by: Neil Armstrong --- configs/qcom_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 222db6448ab..a92b6ef7911 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -43,6 +43,8 @@ CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_QCOM_QCS404=y CONFIG_PINCTRL_QCOM_SDM845=y +CONFIG_PINCTRL_QCOM_SM8550=y +CONFIG_PINCTRL_QCOM_SM8650=y CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y CONFIG_SCSI=y -- 2.34.1
[PATCH 1/3] pinctrl: qcom: Add SM8550 pinctrl driver
Add pinctrl driver for the TLMM block found in the SM8550 SoC.
This driver only handles the gpio and qup1_se7 pinmux, and makes sure
the pinconf applies on SDC2 pins.
Signed-off-by: Neil Armstrong
---
drivers/pinctrl/qcom/Kconfig | 7
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-sm8550.c | 75 +++
3 files changed, 83 insertions(+)
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 2fe63981478..f760bbcdd52 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -41,6 +41,13 @@ config PINCTRL_QCOM_SDM845
Say Y here to enable support for pinctrl on the Snapdragon 845 SoC,
as well as the associated GPIO driver.
+config PINCTRL_QCOM_SM8550
+ bool "Qualcomm SM8550 GCC"
+ select PINCTRL_QCOM
+ help
+ Say Y here to enable support for pinctrl on the Snapdragon SM8550 SoC,
+ as well as the associated GPIO driver.
+
endmenu
endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 6d9aca6d7b7..970902e28c8 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
+obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c
b/drivers/pinctrl/qcom/pinctrl-sm8550.c
new file mode 100644
index 000..d9a8a652111
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm sm8550 pinctrl
+ *
+ * (C) Copyright 2024 Linaro Ltd.
+ *
+ */
+
+#include
+#include
+
+#include "pinctrl-qcom.h"
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+ {"qup1_se7", 1},
+ {"gpio", 0},
+};
+
+static const char *sm8550_get_function_name(struct udevice *dev,
+unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].name;
+}
+
+static const char *sm8550_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ static const char *special_pins_names[] = {
+ "ufs_reset",
+ "sdc2_clk",
+ "sdc2_cmd",
+ "sdc2_data",
+ };
+
+ if (selector >= 210 && selector <= 213)
+ snprintf(pin_name, MAX_PIN_NAME_LEN,
special_pins_names[selector - 210]);
+ else
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+
+ return pin_name;
+}
+
+static unsigned int sm8550_get_function_mux(__maybe_unused unsigned int pin,
+ unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].val;
+}
+
+static struct msm_pinctrl_data sm8550_data = {
+ .pin_data = {
+ .pin_count = 214,
+ .special_pins_start = 210,
+ },
+ .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+ .get_function_name = sm8550_get_function_name,
+ .get_function_mux = sm8550_get_function_mux,
+ .get_pin_name = sm8550_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+ { .compatible = "qcom,sm8550-tlmm", .data = (ulong)_data },
+ { /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(pinctrl_sm8550) = {
+ .name = "pinctrl_sm8550",
+ .id = UCLASS_NOP,
+ .of_match = msm_pinctrl_ids,
+ .ops= _pinctrl_ops,
+ .bind = msm_pinctrl_bind,
+};
+
--
2.34.1
[PATCH 0/3] qcom: add pinctrl driver for SM8550 and SM8650
Add pinctrl driver for the TLMM block found in the SM8550 & SM8650 SoCs. This driver only handles the gpio and qup debug uart pinmux, and makes sure the pinconf applies on SDC2 pins. Finally enable both drivers in the Qualcomm defconfig Signed-off-by: Neil Armstrong --- Neil Armstrong (3): pinctrl: qcom: Add SM8550 pinctrl driver pinctrl: qcom: Add SM8650 pinctrl driver qcom_defconfig: enable SM8550 & SM8650 pinctrl driver configs/qcom_defconfig| 2 + drivers/pinctrl/qcom/Kconfig | 14 +++ drivers/pinctrl/qcom/Makefile | 2 + drivers/pinctrl/qcom/pinctrl-sm8550.c | 75 +++ drivers/pinctrl/qcom/pinctrl-sm8650.c | 75 +++ 5 files changed, 168 insertions(+) --- base-commit: cec1c47bdaf84a643f318d480b1218bfff1041ff change-id: 20240404-topic-sm8x50-pinctrl-101fac729d23 Best regards, -- Neil Armstrong
[GIT PULL] Please pull u-boot-amlogic-next-20240404
Hi Tom, Please pull this migration to OF_UPSTREAM for all Amlogic SoCs family except the newer A1 family. In Addition, there's a few fixes & updates for the jethubj100 board. Thanks, Neil The following changes since commit cdfcc37428e06f4730ab9a17cc084eeb7676ea1a: Merge tag 'u-boot-dfu-next-20240402' of https://source.denx.de/u-boot/custodians/u-boot-dfu (2024-04-02 22:37:23 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-amlogic.git tags/u-boot-amlogic-20240404 for you to fetch changes up to 114df8b5339e503b50b6ac1a61bf1daac57c2e11: dts: meson: Drop redundant G12A, G12B & SM1 devicetree files (2024-04-04 18:48:46 +0200) - jethubj100: fix config, MAINTAINERS & update docs - Switch GXL, GXM, AXG, G12A, G12B & SM1 to using upstream DT ---- Neil Armstrong (5): configs: meson64: remove amlogic prefix in fdtfile when CONFIG_OF_UPSTREAM is selected dts: meson: Switch GXL, GXM & AXG to using upstream DT dts: meson: Drop redundant GXL, GXM & AXG devicetree files dts: meson-g12a: Switch to using upstream DT dts: meson: Drop redundant G12A, G12B & SM1 devicetree files Viacheslav Bocharov (3): board: amlogic: jethubj100: fix common config header board: amlogic: jethubj100: update MAINTAINERS board: amlogic: jethubj100: update docs arch/arm/dts/Makefile | 36 +- arch/arm/dts/meson-axg-jethome-jethub-j100.dts | 361 --- arch/arm/dts/meson-axg-s400.dts| 602 - arch/arm/dts/meson-axg.dtsi| 1957 --- arch/arm/dts/meson-g12-common.dtsi | 2493 arch/arm/dts/meson-g12.dtsi| 385 --- arch/arm/dts/meson-g12a-radxa-zero.dts | 405 arch/arm/dts/meson-g12a-sei510.dts | 566 - arch/arm/dts/meson-g12a-u200.dts | 308 --- arch/arm/dts/meson-g12a.dtsi | 140 -- arch/arm/dts/meson-g12b-a311d-bananapi-m2s.dts | 33 - arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts | 41 - arch/arm/dts/meson-g12b-a311d.dtsi | 149 -- arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts | 165 -- arch/arm/dts/meson-g12b-bananapi-cm4.dtsi | 388 --- arch/arm/dts/meson-g12b-bananapi.dtsi | 521 arch/arm/dts/meson-g12b-gsking-x.dts | 133 -- arch/arm/dts/meson-g12b-gtking-pro.dts | 142 -- arch/arm/dts/meson-g12b-gtking.dts | 163 -- arch/arm/dts/meson-g12b-khadas-vim3.dtsi | 107 - arch/arm/dts/meson-g12b-odroid-go-ultra.dts| 722 -- arch/arm/dts/meson-g12b-odroid-n2-plus.dts | 31 - arch/arm/dts/meson-g12b-odroid-n2.dts | 15 - arch/arm/dts/meson-g12b-odroid-n2.dtsi | 303 --- arch/arm/dts/meson-g12b-odroid-n2l.dts | 125 - arch/arm/dts/meson-g12b-odroid.dtsi| 445 arch/arm/dts/meson-g12b-radxa-zero2.dts| 489 arch/arm/dts/meson-g12b-s922x-bananapi-m2s.dts | 14 - arch/arm/dts/meson-g12b-s922x.dtsi | 139 -- arch/arm/dts/meson-g12b-w400.dtsi | 425 arch/arm/dts/meson-g12b.dtsi | 146 -- arch/arm/dts/meson-gx-libretech-pc.dtsi| 447 arch/arm/dts/meson-gx-mali450.dtsi | 61 - arch/arm/dts/meson-gx-p23x-q20x.dtsi | 324 --- arch/arm/dts/meson-gx.dtsi | 675 -- arch/arm/dts/meson-gxl-mali.dtsi | 17 - arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 319 --- arch/arm/dts/meson-gxl-s805x.dtsi | 23 - arch/arm/dts/meson-gxl-s905d-libretech-pc.dts | 16 - arch/arm/dts/meson-gxl-s905d.dtsi | 12 - .../arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts | 247 -- arch/arm/dts/meson-gxl-s905x-khadas-vim.dts| 237 -- arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts | 313 --- arch/arm/dts/meson-gxl-s905x-libretech-cc.dts | 356 --- arch/arm/dts/meson-gxl-s905x-p212.dts | 134 -- arch/arm/dts/meson-gxl-s905x-p212.dtsi | 213 -- arch/arm/dts/meson-gxl-s905x.dtsi | 18 - arch/arm/dts/meson-gxl.dtsi| 940 arch/arm/dts/meson-gxm-gt1-ultimate.dts| 91 - arch/arm/dts/meson-gxm-khadas-vim2.dts | 424 arch/arm/dts/meson-gxm-s912-libretech-pc.dts | 62 - arch/arm/dts/meson-gxm-wetek-core2.dts | 85 - arch/arm/dts/meson-gxm.dtsi| 216 -- arch/arm/dts/meson-khadas-vim3.dtsi| 534 - arch/arm/dts/meson-sm1-bananapi-m2-pro.dts | 97 - arch/arm/d
[PATCH 3/3] qcom_defconfig: enable SM8550 & SM8650 clock driver
Enable the SM8550 & SM8650 clock driver in the Qualcomm defconfig. Signed-off-by: Neil Armstrong --- configs/qcom_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 1abb57345ff..993c2d25f07 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -37,6 +37,8 @@ CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y CONFIG_CLK_QCOM_QCS404=y CONFIG_CLK_QCOM_SDM845=y +CONFIG_CLK_QCOM_SM8550=y +CONFIG_CLK_QCOM_SM8650=y CONFIG_MSM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y CONFIG_DM_I2C=y -- 2.34.1
[PATCH 2/3] clk: qcom: Add SM8650 clock driver
Add the GCC and TCSRCC clock driver for the SM8650 SoC.
The GCC driver uses the clk-qcom infrastructure to support GDSCs,
Resets and gates. While the TCSRCC is a simpler clock driver which
only supports gates.
The GCC enable and set_rate callbacks contains some tweaks to
setup clocks for Debug UART, SDCard controller and USB.
The TCSRCC gates returns the XO frequency, which is used by the
Synopsys eUSB2 driver to determine the PHY configuration.
Signed-off-by: Neil Armstrong
---
drivers/clk/qcom/Kconfig| 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clock-sm8650.c | 332
3 files changed, 341 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index c908a3d19c9..a9216ea30d4 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -55,6 +55,14 @@ config CLK_QCOM_SM8550
on the Snapdragon SM8550 SoC. This driver supports the clocks
and resets exposed by the GCC hardware block.
+config CLK_QCOM_SM8650
+ bool "Qualcomm SM8650 GCC"
+ select CLK_QCOM
+ help
+ Say Y here to enable support for the Global Clock Controller
+ on the Snapdragon SM8650 SoC. This driver supports the clocks
+ and resets exposed by the GCC hardware block.
+
endmenu
endif
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index d9ac5719f49..3ccb4ffae76 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o
+obj-$(CONFIG_CLK_QCOM_SM8650) += clock-sm8650.o
diff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c
new file mode 100644
index 000..0ce83e9b243
--- /dev/null
+++ b/drivers/clk/qcom/clock-sm8650.c
@@ -0,0 +1,332 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Clock drivers for Qualcomm sm8650
+ *
+ * (C) Copyright 2024 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clock-qcom.h"
+
+/* On-board TCXO, TOFIX get from DT */
+#define TCXO_RATE 3840
+
+/* bi_tcxo_div2 divided after RPMh output */
+#define TCXO_DIV2_RATE (TCXO_RATE / 2)
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s3_clk_src[] = {
+ F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
+ F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
+ F(1920, CFG_CLK_SRC_CXO, 1, 0, 0),
+ F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
+ F(3200, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
+ F(4800, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
+ F(6400, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
+ F(7500, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
+ F(8000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
+ F(9600, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
+ F(1, CFG_CLK_SRC_GPLL0, 6, 0, 0),
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
+ F(40, CFG_CLK_SRC_CXO, 12, 1, 4),
+ F(2500, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
+ F(1, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
+ /* TOFIX F(20200, CFG_CLK_SRC_GPLL9, 4, 0, 0), */
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
+ F(6667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
+ F(1, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
+ F(2, CFG_CLK_SRC_GPLL0, 3, 0, 0),
+ F(24000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static ulong sm8650_set_rate(struct clk *clk, ulong rate)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+ const struct freq_tbl *freq;
+
+ switch (clk->id) {
+ case GCC_QUPV3_WRAP2_S7_CLK: /* UART15 */
+ freq = qcom_find_freq(ftbl_gcc_qupv3_wrap1_s3_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x1e898,
+freq->pre_div, freq->m, freq->n,
freq->src, 16);
+ return freq->freq;
+ case GCC_SDCC2_APPS_CLK:
+ freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x14018,
+freq->pre_div, freq->m, freq->n,
freq->src, 8);
+ return freq->freq;
+ case GCC_USB30_PRIM_MASTER_CLK:
+ freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x3902c,
+freq->pre_div, freq->m, freq->n,
freq->src, 8);
+ return freq->freq;
+ case GCC_USB30_PRIM_MOCK_UTMI_CLK:
+ clk_rcg_set_rate(priv->base, 0x39044, 0, 0);
+ return TCXO_DIV2_RATE
[PATCH 1/3] clk: qcom: Add SM8550 clock driver
Add the GCC and TCSRCC clock driver for the SM8550 SoC.
The GCC driver uses the clk-qcom infrastructure to support GDSCs,
Resets and gates. While the TCSRCC is a simpler clock driver which
only supports gates.
The GCC enable and set_rate callbacks contains some tweaks to
setup clocks for Debug UART, SDCard controller and USB.
The TCSRCC gates returns the XO frequency, which is used by the
Synopsys eUSB2 driver to determine the PHY configuration.
Signed-off-by: Neil Armstrong
---
drivers/clk/qcom/Kconfig| 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clock-sm8550.c | 335
3 files changed, 344 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 8dae635ac2c..c908a3d19c9 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -47,6 +47,14 @@ config CLK_QCOM_SDM845
on the Snapdragon 845 SoC. This driver supports the clocks
and resets exposed by the GCC hardware block.
+config CLK_QCOM_SM8550
+ bool "Qualcomm SM8550 GCC"
+ select CLK_QCOM
+ help
+ Say Y here to enable support for the Global Clock Controller
+ on the Snapdragon SM8550 SoC. This driver supports the clocks
+ and resets exposed by the GCC hardware block.
+
endmenu
endif
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index cb179fdac58..d9ac5719f49 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
+obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o
diff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c
new file mode 100644
index 000..c0249925cc7
--- /dev/null
+++ b/drivers/clk/qcom/clock-sm8550.c
@@ -0,0 +1,335 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Clock drivers for Qualcomm sm8550
+ *
+ * (C) Copyright 2024 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clock-qcom.h"
+
+/* On-board TCXO, TOFIX get from DT */
+#define TCXO_RATE 3840
+
+/* bi_tcxo_div2 divided after RPMh output */
+#define TCXO_DIV2_RATE (TCXO_RATE / 2)
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s2_clk_src[] = {
+ F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
+ F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
+ F(1920, CFG_CLK_SRC_CXO, 1, 0, 0),
+ F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
+ F(3200, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
+ F(4800, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
+ F(5120, CFG_CLK_SRC_GPLL0_EVEN, 1, 64, 375),
+ F(6400, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
+ F(7500, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
+ F(8000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
+ F(9600, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
+ F(1, CFG_CLK_SRC_GPLL0, 6, 0, 0),
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
+ F(40, CFG_CLK_SRC_CXO, 12, 1, 4),
+ F(2500, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
+ F(3750, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0),
+ F(5000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
+ F(1, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
+ /* TOFIX F(20200, CFG_CLK_SRC_GPLL9, 4, 0, 0), */
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
+ F(6667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
+ F(1, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
+ F(2, CFG_CLK_SRC_GPLL0, 3, 0, 0),
+ F(24000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static ulong sm8550_set_rate(struct clk *clk, ulong rate)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+ const struct freq_tbl *freq;
+
+ switch (clk->id) {
+ case GCC_QUPV3_WRAP1_S7_CLK: /* UART7 */
+ freq = qcom_find_freq(ftbl_gcc_qupv3_wrap1_s2_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x18898,
+freq->pre_div, freq->m, freq->n,
freq->src, 16);
+ return freq->freq;
+ case GCC_SDCC2_APPS_CLK:
+ freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x14018,
+freq->pre_div, freq->m, freq->n,
freq->src, 8);
+ return freq->freq;
+ case GCC_USB30_PRIM_MASTER_CLK:
+ freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x3902c,
+freq->pre_div, freq->m, freq->n,
freq->src, 8);
[PATCH 0/3] qcom: add clock driver support for SM8550 and SM8650 SoCc
Add the GCC and TCSRCC clock driver for the SM8550 & SM8650 SoCs. The GCC driver uses the clk-qcom infrastructure to support GDSCs, Resets and gates. While the TCSRCC is a simpler clock driver which only supports gates. The GCC enable and set_rate callbacks contains some tweaks to setup clocks for Debug UART, SDCard controller and USB. The TCSRCC gates returns the XO frequency, which is used by the Synopsys eUSB2 driver to determine the PHY configuration. In addition, the drivers are enabled in the Qualcomm defconfig. Signed-off-by: Neil Armstrong --- Neil Armstrong (3): clk: qcom: Add SM8550 clock driver clk: qcom: Add SM8650 clock driver qcom_defconfig: enable SM8550 & SM8650 clock driver configs/qcom_defconfig | 2 + drivers/clk/qcom/Kconfig| 16 ++ drivers/clk/qcom/Makefile | 2 + drivers/clk/qcom/clock-sm8550.c | 335 drivers/clk/qcom/clock-sm8650.c | 332 +++ 5 files changed, 687 insertions(+) --- base-commit: f0e6aba1218bca578605697eed8aa94582bf57bb change-id: 20240404-topic-sm8x50-clock-a76f8359b5fb Best regards, -- Neil Armstrong
Re: [PATCH v5 13/16] dts: sdm845-db845c: add u-boot fixups
On 28/03/2024 18:59, Caleb Connolly wrote:
The USB VBUS supply for the type-A port is enabled via a GPIO regulator.
This is incorrectly modelled in Linux where only the PCIe dependency is
expressed. The correct way to handle this will be through a
usb-connector node, but for now we'll just mark the regulator as
always-on so that it will be enabled automatically during boot.
Signed-off-by: Caleb Connolly
---
arch/arm/dts/sdm845-db845c-u-boot.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/sdm845-db845c-u-boot.dtsi
b/arch/arm/dts/sdm845-db845c-u-boot.dtsi
new file mode 100644
index ..906f9faa5451
--- /dev/null
+++ b/arch/arm/dts/sdm845-db845c-u-boot.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Needed for Linux to boot from USB, otherwise if PCIe driver is not in
initramfs
+ * the VBUS supply will never get turned on.
+ *
https://lore.kernel.org/linux-arm-msm/20240320122515.3243711-1-caleb.conno...@linaro.org/
+ */
+_3p3v_dual {
+ regulator-always-on;
+};
Reviewed-by: Neil Armstrong
Re: [PATCH v5 12/16] mach-snapdragon: call regulators_enable_boot_on()
On 28/03/2024 18:59, Caleb Connolly wrote:
Make sure we power on any boot-on or always-on regulators. These are
used for peripherals like USB on some platforms.
Signed-off-by: Caleb Connolly
---
arch/arm/mach-snapdragon/board.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index 65e4c61e866a..3d5994c87886 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -15,8 +15,9 @@
#include
#include
#include
#include
+#include
#include
#include
#include
#include
@@ -160,8 +161,9 @@ void __weak qcom_board_init(void)
}
int board_init(void)
{
+ regulators_enable_boot_on(false);
show_psci_version();
qcom_of_fixup_nodes();
qcom_board_init();
return 0;
Reviewed-by: Neil Armstrong
Re: [PATCH v5 11/16] mach-snapdragon: fixup power-domains
On 28/03/2024 18:59, Caleb Connolly wrote:
We don't support the RPM(h)PD power domains in U-Boot, and we don't need
to - the necessary resources are on, and we aren't going to enter any
low power modes.
We could try using a no-op device, but this requires adding a compatible
for every platform, and just pollutes the driver model. So instead let's
just remove every "power-domains" property that references the RPM(h)pd
power controller. This takes <1ms as we're using OF_LIVE.
Of note, this only applies to drivers which are loading post-relocation.
Drivers loaded pre-reloc that reference the rpm(h)pd still need
DM_FLAG_DEFAULT_PD_CTRL_OFF in their flags.
Signed-off-by: Caleb Connolly
---
arch/arm/mach-snapdragon/of_fixup.c | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/mach-snapdragon/of_fixup.c
b/arch/arm/mach-snapdragon/of_fixup.c
index 4fdfed2dff16..3f7ac227bd09 100644
--- a/arch/arm/mach-snapdragon/of_fixup.c
+++ b/arch/arm/mach-snapdragon/of_fixup.c
@@ -21,8 +21,9 @@
#include
#include
#include
#include
+#include
#include
/* U-Boot only supports USB high-speed mode on Qualcomm platforms with DWC3
* USB controllers. Rather than requiring source level DT changes, we fix up
@@ -109,8 +110,38 @@ static void fixup_usb_nodes(void)
log_warning("Failed to fixup node %s: %d\n",
glue_np->name, ret);
}
}
+/* Remove all references to the rpmhpd device */
+static void fixup_power_domains(void)
+{
+ struct device_node *pd = NULL, *np = NULL;
+ struct property *prop;
+ const __be32 *val;
+
+ /* All Qualcomm platforms name the rpm(h)pd "power-controller" */
+ for_each_of_allnodes(pd) {
+ if (pd->name && !strcmp("power-controller", pd->name))
+ break;
+ }
+
+ /* Sanity check that this is indeed a power domain controller */
+ if (!of_find_property(pd, "#power-domain-cells", NULL)) {
+ log_err("Found power-controller but it doesn't have
#power-domain-cells\n");
+ return;
+ }
+
+ /* Remove all references to the power domain controller */
+ for_each_of_allnodes(np) {
+ if (!(prop = of_find_property(np, "power-domains", NULL)))
+ continue;
+
+ val = prop->value;
+ if (val[0] == cpu_to_fdt32(pd->phandle))
+ of_remove_property(np, prop);
+ }
+}
+
#define time_call(func, ...) \
do { \
u64 start = timer_get_us(); \
func(__VA_ARGS__); \
@@ -119,5 +150,6 @@ static void fixup_usb_nodes(void)
void qcom_of_fixup_nodes(void)
{
time_call(fixup_usb_nodes);
+ time_call(fixup_power_domains);
}
Reviewed-by: Neil Armstrong
Also tested on SM8550 & SM8650, so:
Tested-by: Neil Armstrong
Re: [PATCH v5 10/16] mach-snapdragon: fixup USB nodes
}
+
+ /* Overwrite the "phys" property to only contain the high-speed phy */
+ ret = of_write_prop(dwc3, "phys", sizeof(*phandles), phandles +
hsphy_idx);
+ if (ret) {
+ log_err("Failed to overwrite 'phys' property: %d\n", ret);
+ return ret;
+ }
+
+ /* Overwrite "phy-names" to only contain a single entry */
+ ret = of_write_prop(dwc3, "phy-names", strlen("usb2-phy"), "usb2-phy");
+ if (ret) {
+ log_err("Failed to overwrite 'phy-names' property: %d\n", ret);
+ return ret;
+ }
+
+ ret = of_write_prop(dwc3, "maximum-speed", strlen("high-speed"),
"high-speed");
+ if (ret) {
+ log_err("Failed to set 'maximum-speed' property: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void fixup_usb_nodes(void)
+{
+ struct device_node *glue_np = NULL;
+ int ret;
+
+ while ((glue_np = of_find_compatible_node(glue_np, NULL, "qcom,dwc3")))
{
+ ret = fixup_qcom_dwc3(glue_np);
+ if (ret)
+ log_warning("Failed to fixup node %s: %d\n",
glue_np->name, ret);
+ }
+}
+
+#define time_call(func, ...) \
+ do { \
+ u64 start = timer_get_us(); \
+ func(__VA_ARGS__); \
+ debug(#func " took %lluus\n", timer_get_us() - start); \
+ } while (0)
+
+void qcom_of_fixup_nodes(void)
+{
+ time_call(fixup_usb_nodes);
+}
diff --git a/arch/arm/mach-snapdragon/qcom-priv.h
b/arch/arm/mach-snapdragon/qcom-priv.h
new file mode 100644
index ..0a7ed5eff8b8
--- /dev/null
+++ b/arch/arm/mach-snapdragon/qcom-priv.h
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#ifndef __QCOM_PRIV_H__
+#define __QCOM_PRIV_H__
+
+#if CONFIG_IS_ENABLED(OF_LIVE)
+/**
+ * qcom_of_fixup_nodes() - Fixup Qualcomm DT nodes
+ *
+ * Adjusts nodes in the live tree to improve compatibility with U-Boot.
+ */
+void qcom_of_fixup_nodes(void);
+#else
+static inline void qcom_of_fixup_nodes(void)
+{
+ log_debug("Unable to dynamically fixup USB nodes, please enable
CONFIG_OF_LIVE\n");
+}
+#endif /* OF_LIVE */
+
+#endif /* __QCOM_PRIV_H__ */
Reviewed-by: Neil Armstrong
Also tested on SM8550 & SM8650, so:
Tested-by: Neil Armstrong
Re: [PATCH v2 0/5] arm: meson: Switch to using upstream DT for GXL, GXM, AXG, G12A, G12B & SM1 SoCs
Hi, On Fri, 29 Mar 2024 18:51:47 +0100, Neil Armstrong wrote: > Enable OF_UPSTREAM to use upstream DT and add amlogic/ prefix to the > DEFAULT_DEVICE_TREE. And thereby directly build DTB from dts/upstream/src/ > including *-u-boot.dtsi files from arch/$(ARCH)/dts/ directory and > drop redundant files from arch/arm/dts directory. Only *-u-boot.dtsi files > kept in arch/arm/dts directory for these boards. > > Keep A1 DTs locally since the architecture is still young. > > [...] Thanks, Applied to https://source.denx.de/u-boot/custodians/u-boot-amlogic (u-boot-amlogic-next) [1/5] configs: meson64: remove amlogic prefix in fdtfile when CONFIG_OF_UPSTREAM is selected https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/commit/a219eb8c314811b7cab06e6169ccf765da0b2d60 [2/5] dts: meson: Switch GXL, GXM & AXG to using upstream DT https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/commit/227c586e80c77d8aaefe415c2abab11f58f41854 [3/5] dts: meson: Drop redundant GXL, GXM & AXG devicetree files https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/commit/e747bfc48cc74fd944a1e2a603cf089ec58f20cf [4/5] dts: meson-g12a: Switch to using upstream DT https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/commit/01f661e46bf8a6837fa1801f09f1da79abda80bb [5/5] dts: meson: Drop redundant G12A, G12B & SM1 devicetree files https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/commit/7b098c305e51086db906a07c5bdc983c8e9ae3f6 -- Neil
Re: [PATCH 0/4] arm: meson: Switch to using upstream DT for GXL, GXM, AXG, G12A, G12B & SM1 SoCs
Hi, On Tue, 19 Mar 2024 15:42:59 +0100, Neil Armstrong wrote: > Enable OF_UPSTREAM to use upstream DT and add amlogic/ prefix to the > DEFAULT_DEVICE_TREE. And thereby directly build DTB from dts/upstream/src/ > including *-u-boot.dtsi files from arch/$(ARCH)/dts/ directory and > drop redundant files from arch/arm/dts directory. Only *-u-boot.dtsi files > kept in arch/arm/dts directory for these boards. > > Keep A1 DTs locally since the architecture is still young. > > [...] Thanks, Applied to https://source.denx.de/u-boot/custodians/u-boot-amlogic (u-boot-amlogic-next) [1/4] dts: meson: Switch GXL, GXM & AXG to using upstream DT https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/commit/227c586e80c77d8aaefe415c2abab11f58f41854 [2/4] dts: meson: Drop redundant GXL, GXM & AXG devicetree files https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/commit/e747bfc48cc74fd944a1e2a603cf089ec58f20cf [3/4] dts: meson-g12a: Switch to using upstream DT https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/commit/01f661e46bf8a6837fa1801f09f1da79abda80bb [4/4] dts: meson: Drop redundant G12A, G12B & SM1 devicetree files https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/commit/7b098c305e51086db906a07c5bdc983c8e9ae3f6 -- Neil
[PATCH v2 4/5] dts: meson-g12a: Switch to using upstream DT
Enable OF_UPSTREAM to use upstream DT and add amlogic/ prefix to the DEFAULT_DEVICE_TREE. And thereby directly build DTB from dts/upstream/src/ including *-u-boot.dtsi files from arch/$(ARCH)/dts/ directory. Cc: Sumit Garg Acked-by: Viacheslav Bocharov Reviewed-by: Sumit Garg Signed-off-by: Neil Armstrong --- arch/arm/mach-meson/Kconfig | 1 + configs/bananapi-cm4-cm4io_defconfig | 2 +- configs/bananapi-m2-pro_defconfig | 2 +- configs/bananapi-m2s_defconfig| 2 +- configs/bananapi-m5_defconfig | 2 +- configs/beelink-gsking-x_defconfig| 2 +- configs/beelink-gtking_defconfig | 2 +- configs/beelink-gtkingpro_defconfig | 2 +- configs/khadas-vim3_android_ab_defconfig | 2 +- configs/khadas-vim3_android_defconfig | 2 +- configs/khadas-vim3_defconfig | 2 +- configs/khadas-vim3l_android_ab_defconfig | 2 +- configs/khadas-vim3l_android_defconfig| 2 +- configs/khadas-vim3l_defconfig| 2 +- configs/odroid-c4_defconfig | 2 +- configs/odroid-go-ultra_defconfig | 2 +- configs/odroid-hc4_defconfig | 2 +- configs/odroid-n2_defconfig | 2 +- configs/odroid-n2l_defconfig | 2 +- configs/radxa-zero2_defconfig | 2 +- configs/radxa-zero_defconfig | 2 +- configs/sei510_defconfig | 2 +- configs/sei610_defconfig | 2 +- configs/u200_defconfig| 2 +- 24 files changed, 24 insertions(+), 23 deletions(-) diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 1d837ae0f3..7570f48e25 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -53,6 +53,7 @@ config MESON_AXG config MESON_G12A bool "G12A" select MESON64_COMMON + imply OF_UPSTREAM help Select this if your SoC is an S905X/D2 diff --git a/configs/bananapi-cm4-cm4io_defconfig b/configs/bananapi-cm4-cm4io_defconfig index 116147fc9a..cb78dabc13 100644 --- a/configs/bananapi-cm4-cm4io_defconfig +++ b/configs/bananapi-cm4-cm4io_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-bananapi-cm4-cm4io" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-bananapi-cm4-cm4io" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/bananapi-m2-pro_defconfig b/configs/bananapi-m2-pro_defconfig index 755bccb4a7..196bc4077d 100644 --- a/configs/bananapi-m2-pro_defconfig +++ b/configs/bananapi-m2-pro_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-bananapi-m2-pro" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-bananapi-m2-pro" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/bananapi-m2s_defconfig b/configs/bananapi-m2s_defconfig index af8daced62..7b137d5e1c 100644 --- a/configs/bananapi-m2s_defconfig +++ b/configs/bananapi-m2s_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-bananapi-m2s" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-a311d-bananapi-m2s" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/bananapi-m5_defconfig b/configs/bananapi-m5_defconfig index 6de5d5fe7b..99ed7c9669 100644 --- a/configs/bananapi-m5_defconfig +++ b/configs/bananapi-m5_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-bananapi-m5" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-bananapi-m5" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/beelink-gsking-x_defconfig b/configs/beelink-gsking-x_defconfig index 99e36e970a..c1e60ede4a 100644 --- a/configs/beelink-gsking-x_defconfig +++ b/configs/beelink-gsking-x_defconfig @@ -7,7 +7,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-gsking-x" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-gsking-x" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/beelink-gtking_defconfig b/configs/beelink-gtking_defconfig index 5c21d8eeab..0b644f0e34 100644 --- a/configs/beelink-gtking_defconfig +++ b/configs/beelink-gtking_defconfig @@ -7,7 +7,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM
[PATCH v2 2/5] dts: meson: Switch GXL, GXM & AXG to using upstream DT
Enable OF_UPSTREAM to use upstream DT and add amlogic/ prefix to the DEFAULT_DEVICE_TREE. And thereby directly build DTB from dts/upstream/src/ including *-u-boot.dtsi files from arch/$(ARCH)/dts/ directory. Cc: Sumit Garg Acked-by: Viacheslav Bocharov Reviewed-by: Sumit Garg Signed-off-by: Neil Armstrong --- arch/arm/mach-meson/Kconfig| 3 +++ configs/beelink-gt1-ultimate_defconfig | 2 +- configs/jethub_j100_defconfig | 2 +- configs/jethub_j80_defconfig | 2 +- configs/khadas-vim2_defconfig | 2 +- configs/khadas-vim_defconfig | 2 +- configs/libretech-ac_defconfig | 2 +- configs/libretech-cc_defconfig | 2 +- configs/libretech-cc_v2_defconfig | 2 +- configs/libretech-s905d-pc_defconfig | 2 +- configs/libretech-s912-pc_defconfig| 2 +- configs/p212_defconfig | 2 +- configs/s400_defconfig | 2 +- configs/wetek-core2_defconfig | 2 +- 14 files changed, 16 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 95e7b019ce..1d837ae0f3 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -32,18 +32,21 @@ config MESON_GXBB config MESON_GXL bool "GXL" select MESON_GX + imply OF_UPSTREAM help Select this if your SoC is an S905X/D or S805X config MESON_GXM bool "GXM" select MESON_GX + imply OF_UPSTREAM help Select this if your SoC is an S912 config MESON_AXG bool "AXG" select MESON64_COMMON + imply OF_UPSTREAM help Select this if your SoC is an A113X/D diff --git a/configs/beelink-gt1-ultimate_defconfig b/configs/beelink-gt1-ultimate_defconfig index 00fdad8544..0e30e13c82 100644 --- a/configs/beelink-gt1-ultimate_defconfig +++ b/configs/beelink-gt1-ultimate_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-gt1-ultimate" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxm-gt1-ultimate" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXM=y diff --git a/configs/jethub_j100_defconfig b/configs/jethub_j100_defconfig index 863245430a..9de6b4b44d 100644 --- a/configs/jethub_j100_defconfig +++ b/configs/jethub_j100_defconfig @@ -8,7 +8,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-axg-jethome-jethub-j100" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-axg-jethome-jethub-j100" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_AXG=y diff --git a/configs/jethub_j80_defconfig b/configs/jethub_j80_defconfig index ca0808f712..85306872f9 100644 --- a/configs/jethub_j80_defconfig +++ b/configs/jethub_j80_defconfig @@ -8,7 +8,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905w-jethome-jethub-j80" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s905w-jethome-jethub-j80" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXL=y diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig index 59ef33723e..50f8b30650 100644 --- a/configs/khadas-vim2_defconfig +++ b/configs/khadas-vim2_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-khadas-vim2" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxm-khadas-vim2" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXM=y diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig index 5ed7c1a408..ac00e8975e 100644 --- a/configs/khadas-vim_defconfig +++ b/configs/khadas-vim_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-khadas-vim" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s905x-khadas-vim" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXL=y diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig index f0ab19580c..6ad0457002 100644 --- a/configs/libretech-ac_defconfig +++ b/configs/libretech-ac_defconfig @@ -9,7 +9,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x CONFIG_ENV_SECT_SIZE=0x1 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s805x-libretech-ac" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s805x-libretech-ac" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXL=y diff --git a/configs/libretech-cc_defconfig b/con
[PATCH v2 1/5] configs: meson64: remove amlogic prefix in fdtfile when CONFIG_OF_UPSTREAM is selected
Remove amlogic/ path prefix in CFG_EXTRA_ENV_SETTINGS fdtfile when using CONFIG_OF_UPSTREAM, otherwise amlogic/ is added twice. Signed-off-by: Neil Armstrong --- include/configs/meson64.h | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/include/configs/meson64.h b/include/configs/meson64.h index efab9a624d..65fa5f3d6d 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -120,6 +120,12 @@ #include +#ifdef CONFIG_OF_UPSTREAM +#define FDTFILE_NAME CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#else +#define FDTFILE_NAME "amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#endif + #ifndef CFG_EXTRA_ENV_SETTINGS #define CFG_EXTRA_ENV_SETTINGS \ "stdin=" STDIN_CFG "\0" \ @@ -133,7 +139,7 @@ "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ "fdtoverlay_addr_r=" FDTOVERLAY_ADDR_R "\0" \ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ - "fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "fdtfile=" FDTFILE_NAME "\0" \ "dfu_alt_info=fitimage ram " KERNEL_ADDR_R " 0x400 \0" \ BOOTENV #endif -- 2.34.1
[PATCH v2 0/5] arm: meson: Switch to using upstream DT for GXL, GXM, AXG, G12A, G12B & SM1 SoCs
Enable OF_UPSTREAM to use upstream DT and add amlogic/ prefix to the DEFAULT_DEVICE_TREE. And thereby directly build DTB from dts/upstream/src/ including *-u-boot.dtsi files from arch/$(ARCH)/dts/ directory and drop redundant files from arch/arm/dts directory. Only *-u-boot.dtsi files kept in arch/arm/dts directory for these boards. Keep A1 DTs locally since the architecture is still young. CI built & tested at: https://gitlab.com/amlogic-foss/amlogic-u-boot-autotest/-/pipelines/1233461384 Signed-off-by: Neil Armstrong --- Changes in v2: - add change to remove prefix in fdtfile - collected review tags - Link to v1: https://lore.kernel.org/r/20240319-u-boot-of-upstream-v1-0-f82bc9fe6...@linaro.org --- Neil Armstrong (5): configs: meson64: remove amlogic prefix in fdtfile when CONFIG_OF_UPSTREAM is selected dts: meson: Switch GXL, GXM & AXG to using upstream DT dts: meson: Drop redundant GXL, GXM & AXG devicetree files dts: meson-g12a: Switch to using upstream DT dts: meson: Drop redundant G12A, G12B & SM1 devicetree files arch/arm/dts/Makefile | 36 +- arch/arm/dts/meson-axg-jethome-jethub-j100.dts | 361 --- arch/arm/dts/meson-axg-s400.dts| 602 - arch/arm/dts/meson-axg.dtsi| 1957 --- arch/arm/dts/meson-g12-common.dtsi | 2493 arch/arm/dts/meson-g12.dtsi| 385 --- arch/arm/dts/meson-g12a-radxa-zero.dts | 405 arch/arm/dts/meson-g12a-sei510.dts | 566 - arch/arm/dts/meson-g12a-u200.dts | 308 --- arch/arm/dts/meson-g12a.dtsi | 140 -- arch/arm/dts/meson-g12b-a311d-bananapi-m2s.dts | 33 - arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts | 41 - arch/arm/dts/meson-g12b-a311d.dtsi | 149 -- arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts | 165 -- arch/arm/dts/meson-g12b-bananapi-cm4.dtsi | 388 --- arch/arm/dts/meson-g12b-bananapi.dtsi | 521 arch/arm/dts/meson-g12b-gsking-x.dts | 133 -- arch/arm/dts/meson-g12b-gtking-pro.dts | 142 -- arch/arm/dts/meson-g12b-gtking.dts | 163 -- arch/arm/dts/meson-g12b-khadas-vim3.dtsi | 107 - arch/arm/dts/meson-g12b-odroid-go-ultra.dts| 722 -- arch/arm/dts/meson-g12b-odroid-n2-plus.dts | 31 - arch/arm/dts/meson-g12b-odroid-n2.dts | 15 - arch/arm/dts/meson-g12b-odroid-n2.dtsi | 303 --- arch/arm/dts/meson-g12b-odroid-n2l.dts | 125 - arch/arm/dts/meson-g12b-odroid.dtsi| 445 arch/arm/dts/meson-g12b-radxa-zero2.dts| 489 arch/arm/dts/meson-g12b-s922x-bananapi-m2s.dts | 14 - arch/arm/dts/meson-g12b-s922x.dtsi | 139 -- arch/arm/dts/meson-g12b-w400.dtsi | 425 arch/arm/dts/meson-g12b.dtsi | 146 -- arch/arm/dts/meson-gx-libretech-pc.dtsi| 447 arch/arm/dts/meson-gx-mali450.dtsi | 61 - arch/arm/dts/meson-gx-p23x-q20x.dtsi | 324 --- arch/arm/dts/meson-gx.dtsi | 675 -- arch/arm/dts/meson-gxl-mali.dtsi | 17 - arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 319 --- arch/arm/dts/meson-gxl-s805x.dtsi | 23 - arch/arm/dts/meson-gxl-s905d-libretech-pc.dts | 16 - arch/arm/dts/meson-gxl-s905d.dtsi | 12 - .../arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts | 247 -- arch/arm/dts/meson-gxl-s905x-khadas-vim.dts| 237 -- arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts | 313 --- arch/arm/dts/meson-gxl-s905x-libretech-cc.dts | 356 --- arch/arm/dts/meson-gxl-s905x-p212.dts | 134 -- arch/arm/dts/meson-gxl-s905x-p212.dtsi | 213 -- arch/arm/dts/meson-gxl-s905x.dtsi | 18 - arch/arm/dts/meson-gxl.dtsi| 940 arch/arm/dts/meson-gxm-gt1-ultimate.dts| 91 - arch/arm/dts/meson-gxm-khadas-vim2.dts | 424 arch/arm/dts/meson-gxm-s912-libretech-pc.dts | 62 - arch/arm/dts/meson-gxm-wetek-core2.dts | 85 - arch/arm/dts/meson-gxm.dtsi| 216 -- arch/arm/dts/meson-khadas-vim3.dtsi| 534 - arch/arm/dts/meson-sm1-bananapi-m2-pro.dts | 97 - arch/arm/dts/meson-sm1-bananapi-m5.dts | 221 -- arch/arm/dts/meson-sm1-bananapi.dtsi | 435 arch/arm/dts/meson-sm1-khadas-vim3l.dts| 113 - arch/arm/dts/meson-sm1-odroid-c4.dts | 48 - arch/arm/dts/meson-sm1-odroid-hc4.dts | 140 -- arch/arm/dts/meson-sm1-odroid.dtsi | 449 arch/arm/dts/meson-sm1-sei610.dts | 616 ---
Re: [PATCH 0/4] arm: meson: Switch to using upstream DT for GXL, GXM, AXG, G12A, G12B & SM1 SoCs
On 28/03/2024 09:36, Viacheslav wrote: Builds and run ok. for related: Acked-by: Viacheslav Bocharov Thanks ! I'll send a v2 with this fix and your ack! Neil 28/03/2024 10.50, neil.armstr...@linaro.org wrote: Hi, On 28/03/2024 07:58, Viacheslav wrote: Hi, Neil! With this patchset I got wrong fdt link in env with double prefix: fdtfile=amlogic/amlogic/meson-gxl-s905w-jethome-jethub-j80.dtb but if i remove "amlogic" prefix in config it does not build --- a/configs/jethub_j80_defconfig +++ b/configs/jethub_j80_defconfig -CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s905w-jethome-jethub-j80" +CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905w-jethome-jethub-j80" Error: make[2]: *** No rule to make target 'dts/upstream/src/arm64/meson-gxl-s905w-jethome-jethub-j80.dtb', needed by 'dtbs'. Stop. make[1]: *** [dts/Makefile:54: arch-dtbs] Error 2 make: *** [Makefile:1166: dts/dt.dtb] Error 2 You're right, I forgot to remove the fdtfile prefix, can you retry with: =><=== diff --git a/include/configs/meson64.h b/include/configs/meson64.h index efab9a624d..65fa5f3d6d 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -120,6 +120,12 @@ #include +#ifdef CONFIG_OF_UPSTREAM +#define FDTFILE_NAME CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#else +#define FDTFILE_NAME "amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#endif + #ifndef CFG_EXTRA_ENV_SETTINGS #define CFG_EXTRA_ENV_SETTINGS \ "stdin=" STDIN_CFG "\0" \ @@ -133,7 +139,7 @@ "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ "fdtoverlay_addr_r=" FDTOVERLAY_ADDR_R "\0" \ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ - "fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "fdtfile=" FDTFILE_NAME "\0" \ "dfu_alt_info=fitimage ram " KERNEL_ADDR_R " 0x400 \0" \ BOOTENV #endif =><=== Thanks, Neil 22/03/2024 12.03, Neil Armstrong: Hi Viacheslav, On 19/03/2024 15:42, Neil Armstrong wrote: Enable OF_UPSTREAM to use upstream DT and add amlogic/ prefix to the DEFAULT_DEVICE_TREE. And thereby directly build DTB from dts/upstream/src/ including *-u-boot.dtsi files from arch/$(ARCH)/dts/ directory and drop redundant files from arch/arm/dts directory. Only *-u-boot.dtsi files kept in arch/arm/dts directory for these boards. Keep A1 DTs locally since the architecture is still young. CI built & tested at: https://gitlab.com/amlogic-foss/amlogic-u-boot-autotest/-/pipelines/1219273552 Signed-off-by: Neil Armstrong --- Neil Armstrong (4): dts: meson: Switch GXL, GXM & AXG to using upstream DT dts: meson: Drop redundant GXL, GXM & AXG devicetree files Could you run a test run on your boards so make sure is still boots fine ? Thanks, Neil dts: meson-g12a: Switch to using upstream DT dts: meson: Drop redundant G12A, G12B & SM1 devicetree files arch/arm/dts/Makefile | 36 +- arch/arm/dts/meson-axg-jethome-jethub-j100.dts | 361 --- arch/arm/dts/meson-axg-s400.dts | 602 - arch/arm/dts/meson-axg.dtsi | 1957 --- arch/arm/dts/meson-g12-common.dtsi | 2493 arch/arm/dts/meson-g12.dtsi | 385 --- arch/arm/dts/meson-g12a-radxa-zero.dts | 405 arch/arm/dts/meson-g12a-sei510.dts | 566 - arch/arm/dts/meson-g12a-u200.dts | 308 --- arch/arm/dts/meson-g12a.dtsi | 140 -- arch/arm/dts/meson-g12b-a311d-bananapi-m2s.dts | 33 - arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts | 41 - arch/arm/dts/meson-g12b-a311d.dtsi | 149 -- arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts | 165 -- arch/arm/dts/meson-g12b-bananapi-cm4.dtsi | 388 --- arch/arm/dts/meson-g12b-bananapi.dtsi | 521 arch/arm/dts/meson-g12b-gsking-x.dts | 133 -- arch/arm/dts/meson-g12b-gtking-pro.dts | 142 -- arch/arm/dts/meson-g12b-gtking.dts | 163 -- arch/arm/dts/meson-g12b-khadas-vim3.dtsi | 107 - arch/arm/dts/meson-g12b-odroid-go-ultra.dts | 722 -- arch/arm/dts/meson-g12b-odroid-n2-plus.dts | 31 - arch/arm/dts/meson-g12b-odroid-n2.dts | 15 - arch/arm/dts/meson-g12b-odroid-n2.dtsi | 303 --- arch/arm/dts/meson-g12b-odroid-n2l.dts | 125 - arch/arm/dts/meson-g12b-odroid.dtsi | 445 arch/arm/dts/meson-g12b-radxa-zero2.dts | 489 arch/arm/dts/meson-g12b-s922x-bananapi-m2s.dts
Re: [PATCH 0/4] arm: meson: Switch to using upstream DT for GXL, GXM, AXG, G12A, G12B & SM1 SoCs
Hi Mattijs, On 19/03/2024 15:42, Neil Armstrong wrote: Enable OF_UPSTREAM to use upstream DT and add amlogic/ prefix to the DEFAULT_DEVICE_TREE. And thereby directly build DTB from dts/upstream/src/ including *-u-boot.dtsi files from arch/$(ARCH)/dts/ directory and drop redundant files from arch/arm/dts directory. Only *-u-boot.dtsi files kept in arch/arm/dts directory for these boards. Keep A1 DTs locally since the architecture is still young. CI built & tested at: https://gitlab.com/amlogic-foss/amlogic-u-boot-autotest/-/pipelines/1219273552 Can you check it doesn't break android boot ? Neil Signed-off-by: Neil Armstrong --- Neil Armstrong (4): dts: meson: Switch GXL, GXM & AXG to using upstream DT dts: meson: Drop redundant GXL, GXM & AXG devicetree files dts: meson-g12a: Switch to using upstream DT dts: meson: Drop redundant G12A, G12B & SM1 devicetree files arch/arm/dts/Makefile | 36 +- arch/arm/dts/meson-axg-jethome-jethub-j100.dts | 361 --- arch/arm/dts/meson-axg-s400.dts| 602 - arch/arm/dts/meson-axg.dtsi| 1957 --- arch/arm/dts/meson-g12-common.dtsi | 2493 arch/arm/dts/meson-g12.dtsi| 385 --- arch/arm/dts/meson-g12a-radxa-zero.dts | 405 arch/arm/dts/meson-g12a-sei510.dts | 566 - arch/arm/dts/meson-g12a-u200.dts | 308 --- arch/arm/dts/meson-g12a.dtsi | 140 -- arch/arm/dts/meson-g12b-a311d-bananapi-m2s.dts | 33 - arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts | 41 - arch/arm/dts/meson-g12b-a311d.dtsi | 149 -- arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts | 165 -- arch/arm/dts/meson-g12b-bananapi-cm4.dtsi | 388 --- arch/arm/dts/meson-g12b-bananapi.dtsi | 521 arch/arm/dts/meson-g12b-gsking-x.dts | 133 -- arch/arm/dts/meson-g12b-gtking-pro.dts | 142 -- arch/arm/dts/meson-g12b-gtking.dts | 163 -- arch/arm/dts/meson-g12b-khadas-vim3.dtsi | 107 - arch/arm/dts/meson-g12b-odroid-go-ultra.dts| 722 -- arch/arm/dts/meson-g12b-odroid-n2-plus.dts | 31 - arch/arm/dts/meson-g12b-odroid-n2.dts | 15 - arch/arm/dts/meson-g12b-odroid-n2.dtsi | 303 --- arch/arm/dts/meson-g12b-odroid-n2l.dts | 125 - arch/arm/dts/meson-g12b-odroid.dtsi| 445 arch/arm/dts/meson-g12b-radxa-zero2.dts| 489 arch/arm/dts/meson-g12b-s922x-bananapi-m2s.dts | 14 - arch/arm/dts/meson-g12b-s922x.dtsi | 139 -- arch/arm/dts/meson-g12b-w400.dtsi | 425 arch/arm/dts/meson-g12b.dtsi | 146 -- arch/arm/dts/meson-gx-libretech-pc.dtsi| 447 arch/arm/dts/meson-gx-mali450.dtsi | 61 - arch/arm/dts/meson-gx-p23x-q20x.dtsi | 324 --- arch/arm/dts/meson-gx.dtsi | 675 -- arch/arm/dts/meson-gxl-mali.dtsi | 17 - arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 319 --- arch/arm/dts/meson-gxl-s805x.dtsi | 23 - arch/arm/dts/meson-gxl-s905d-libretech-pc.dts | 16 - arch/arm/dts/meson-gxl-s905d.dtsi | 12 - .../arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts | 247 -- arch/arm/dts/meson-gxl-s905x-khadas-vim.dts| 237 -- arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts | 313 --- arch/arm/dts/meson-gxl-s905x-libretech-cc.dts | 356 --- arch/arm/dts/meson-gxl-s905x-p212.dts | 134 -- arch/arm/dts/meson-gxl-s905x-p212.dtsi | 213 -- arch/arm/dts/meson-gxl-s905x.dtsi | 18 - arch/arm/dts/meson-gxl.dtsi| 940 arch/arm/dts/meson-gxm-gt1-ultimate.dts| 91 - arch/arm/dts/meson-gxm-khadas-vim2.dts | 424 arch/arm/dts/meson-gxm-s912-libretech-pc.dts | 62 - arch/arm/dts/meson-gxm-wetek-core2.dts | 85 - arch/arm/dts/meson-gxm.dtsi| 216 -- arch/arm/dts/meson-khadas-vim3.dtsi| 534 - arch/arm/dts/meson-sm1-bananapi-m2-pro.dts | 97 - arch/arm/dts/meson-sm1-bananapi-m5.dts | 221 -- arch/arm/dts/meson-sm1-bananapi.dtsi | 435 arch/arm/dts/meson-sm1-khadas-vim3l.dts| 113 - arch/arm/dts/meson-sm1-odroid-c4.dts | 48 - arch/arm/dts/meson-sm1-odroid-hc4.dts | 140 -- arch/arm/dts/meson-sm1-odroid.dtsi | 449 arch/arm/dts/meson-sm1-sei610.dts | 616 - arch/arm/dts/meson-sm1.dtsi| 550 - arch/arm/ma
Re: [PATCH 0/4] arm: meson: Switch to using upstream DT for GXL, GXM, AXG, G12A, G12B & SM1 SoCs
Hi, On 28/03/2024 07:58, Viacheslav wrote: Hi, Neil! With this patchset I got wrong fdt link in env with double prefix: fdtfile=amlogic/amlogic/meson-gxl-s905w-jethome-jethub-j80.dtb but if i remove "amlogic" prefix in config it does not build --- a/configs/jethub_j80_defconfig +++ b/configs/jethub_j80_defconfig -CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s905w-jethome-jethub-j80" +CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905w-jethome-jethub-j80" Error: make[2]: *** No rule to make target 'dts/upstream/src/arm64/meson-gxl-s905w-jethome-jethub-j80.dtb', needed by 'dtbs'. Stop. make[1]: *** [dts/Makefile:54: arch-dtbs] Error 2 make: *** [Makefile:1166: dts/dt.dtb] Error 2 You're right, I forgot to remove the fdtfile prefix, can you retry with: =><=== diff --git a/include/configs/meson64.h b/include/configs/meson64.h index efab9a624d..65fa5f3d6d 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -120,6 +120,12 @@ #include +#ifdef CONFIG_OF_UPSTREAM +#define FDTFILE_NAME CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#else +#define FDTFILE_NAME "amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#endif + #ifndef CFG_EXTRA_ENV_SETTINGS #define CFG_EXTRA_ENV_SETTINGS \ "stdin=" STDIN_CFG "\0" \ @@ -133,7 +139,7 @@ "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ "fdtoverlay_addr_r=" FDTOVERLAY_ADDR_R "\0" \ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ - "fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "fdtfile=" FDTFILE_NAME "\0" \ "dfu_alt_info=fitimage ram " KERNEL_ADDR_R " 0x400 \0" \ BOOTENV #endif =><=== Thanks, Neil 22/03/2024 12.03, Neil Armstrong: Hi Viacheslav, On 19/03/2024 15:42, Neil Armstrong wrote: Enable OF_UPSTREAM to use upstream DT and add amlogic/ prefix to the DEFAULT_DEVICE_TREE. And thereby directly build DTB from dts/upstream/src/ including *-u-boot.dtsi files from arch/$(ARCH)/dts/ directory and drop redundant files from arch/arm/dts directory. Only *-u-boot.dtsi files kept in arch/arm/dts directory for these boards. Keep A1 DTs locally since the architecture is still young. CI built & tested at: https://gitlab.com/amlogic-foss/amlogic-u-boot-autotest/-/pipelines/1219273552 Signed-off-by: Neil Armstrong --- Neil Armstrong (4): dts: meson: Switch GXL, GXM & AXG to using upstream DT dts: meson: Drop redundant GXL, GXM & AXG devicetree files Could you run a test run on your boards so make sure is still boots fine ? Thanks, Neil dts: meson-g12a: Switch to using upstream DT dts: meson: Drop redundant G12A, G12B & SM1 devicetree files arch/arm/dts/Makefile | 36 +- arch/arm/dts/meson-axg-jethome-jethub-j100.dts | 361 --- arch/arm/dts/meson-axg-s400.dts | 602 - arch/arm/dts/meson-axg.dtsi | 1957 --- arch/arm/dts/meson-g12-common.dtsi | 2493 arch/arm/dts/meson-g12.dtsi | 385 --- arch/arm/dts/meson-g12a-radxa-zero.dts | 405 arch/arm/dts/meson-g12a-sei510.dts | 566 - arch/arm/dts/meson-g12a-u200.dts | 308 --- arch/arm/dts/meson-g12a.dtsi | 140 -- arch/arm/dts/meson-g12b-a311d-bananapi-m2s.dts | 33 - arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts | 41 - arch/arm/dts/meson-g12b-a311d.dtsi | 149 -- arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts | 165 -- arch/arm/dts/meson-g12b-bananapi-cm4.dtsi | 388 --- arch/arm/dts/meson-g12b-bananapi.dtsi | 521 arch/arm/dts/meson-g12b-gsking-x.dts | 133 -- arch/arm/dts/meson-g12b-gtking-pro.dts | 142 -- arch/arm/dts/meson-g12b-gtking.dts | 163 -- arch/arm/dts/meson-g12b-khadas-vim3.dtsi | 107 - arch/arm/dts/meson-g12b-odroid-go-ultra.dts | 722 -- arch/arm/dts/meson-g12b-odroid-n2-plus.dts | 31 - arch/arm/dts/meson-g12b-odroid-n2.dts | 15 - arch/arm/dts/meson-g12b-odroid-n2.dtsi | 303 --- arch/arm/dts/meson-g12b-odroid-n2l.dts | 125 - arch/arm/dts/meson-g12b-odroid.dtsi | 445 arch/arm/dts/meson-g12b-radxa-zero2.dts | 489 arch/arm/dts/meson-g12b-s922x-bananapi-m2s.dts | 14 - arch/arm/dts/meson-g12b-s922x.dtsi | 139 -- arch/arm/dts/meson-g12b-w400.dtsi | 425 arch/arm/dts/meson-g12b.dtsi | 146 -- arch/arm/dts/meson-g
Re: [PATCH v1] board: amlogic: jethubj100: fix update docs
On 26/03/2024 09:19, Viacheslav Bocharov wrote: Fix linter errors Fixes: 2fc5e3c1668cffdb4b894986e98c1ee10f6e9955 Signed-off-by: Viacheslav Bocharov --- doc/board/amlogic/jethub-j100.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/board/amlogic/jethub-j100.rst b/doc/board/amlogic/jethub-j100.rst index 80bed6e919e..cbf1ea76107 100644 --- a/doc/board/amlogic/jethub-j100.rst +++ b/doc/board/amlogic/jethub-j100.rst @@ -1,7 +1,7 @@ .. SPDX-License-Identifier: GPL-2.0+ U-Boot for JetHub J100/J110 (A113X) -== +=== JetHome Jethub D1/D1+ (http://jethome.ru/jethub-d1p) is a home automation controller device manufactured by JetHome with the following specifications: Thanks, squashed! Neil
[GIT PULL] Please pull u-boot-amlogic-fixes-20240325
Hi Tom,
Please pull this set of last minute fixes
Thanks,
Neil
The following changes since commit bd0aedde3ea3691616c17c720e2d25351308c0a1:
board: toradex: verdin-am62_r5: Increase SPL_STACK_R_MALLOC_SIMPLE_LEN
(2024-03-22 11:10:51 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-amlogic.git
tags/u-boot-amlogic-fixes-20240325
for you to fetch changes up to d54f87f09a36ac20154955297b7c999b368b0443:
board: amlogic: fix buffler overflow in seria, mac & usid read (2024-03-25
09:16:19 +0100)
- fix Ethernet and random MAC's on WeTek Hub/Play2
- fix buffer overflow in serial, mac & usid read
Christian Hewitt (2):
ARM: dts: fix Ethernet on WeTek Hub/Play2
board: amlogic: add meson_generate_serial_ethaddr fallback to p200
Neil Armstrong (1):
board: amlogic: fix buffler overflow in seria, mac & usid read
...b-wetek-u-boot.dtsi => meson-gxbb-wetek-hub-u-boot.dtsi} | 0
arch/arm/dts/meson-gxbb-wetek-play2-u-boot.dtsi | 13 +
board/amlogic/beelink-s922x/beelink-s922x.c | 3 ++-
board/amlogic/jethub-j100/jethub-j100.c | 3 ++-
board/amlogic/jethub-j80/jethub-j80.c | 9 ++---
board/amlogic/odroid-n2/odroid-n2.c | 3 ++-
board/amlogic/p200/p200.c | 8 ++--
board/amlogic/p201/p201.c | 6 --
board/amlogic/p212/p212.c | 6 --
board/amlogic/q200/q200.c | 6 --
board/amlogic/vim3/vim3.c | 3 ++-
11 files changed, 45 insertions(+), 15 deletions(-)
rename arch/arm/dts/{meson-gxbb-wetek-u-boot.dtsi =>
meson-gxbb-wetek-hub-u-boot.dtsi} (100%)
create mode 100644 arch/arm/dts/meson-gxbb-wetek-play2-u-boot.dtsi
Re: [PATCH v1 3/3] board: amlogic: jethubj100: update docs
On 27/02/2024 07:54, Viacheslav Bocharov wrote: Improove documentation, add new revision. Signed-off-by: Viacheslav Bocharov --- doc/board/amlogic/jethub-j100.rst | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/doc/board/amlogic/jethub-j100.rst b/doc/board/amlogic/jethub-j100.rst index 86acdafa06f..80bed6e919e 100644 --- a/doc/board/amlogic/jethub-j100.rst +++ b/doc/board/amlogic/jethub-j100.rst @@ -1,9 +1,9 @@ .. SPDX-License-Identifier: GPL-2.0+ -U-Boot for JetHub J100 (A113X) +U-Boot for JetHub J100/J110 (A113X) == I have a CI failure: https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/jobs/804174 /builds/u-boot/custodians/u-boot-amlogic/doc/board/amlogic/jethub-j100.rst:4:Title underline too short. U-Boot for JetHub J100/J110 (A113X) Could you check and send a follow-up patch I can squash on top? Thanks, Neil
Re: [PATCH v2] board: amlogic: fix buffler overflow in seria, mac & usid read
Hi, On Wed, 20 Mar 2024 09:46:11 +0100, Neil Armstrong wrote: > While meson_sm_read_efuse() doesn't overflow, the string is not > zero terminated and env_set*() will buffer overflow and add random > characters to environment. > > Thanks, Applied to https://source.denx.de/u-boot/custodians/u-boot-amlogic (u-boot-amlogic) [1/1] board: amlogic: fix buffler overflow in seria, mac & usid read https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/commit/d54f87f09a36ac20154955297b7c999b368b0443 -- Neil
Re: [PATCH v2 0/2] ARM: dts: fix Ethernet and random MAC's on WeTek Hub/Play2
Hi, On Sun, 24 Mar 2024 15:19:03 +, Christian Hewitt wrote: > In submitting the original patches for WeTek Hub/Play2 I appear to have > squashed an experimental change to place the u-boot.dtsi file on the common > board dtsi, but this was incorrect and results in broken Ethernet. Patch 1 > creates per-board u-boot.dtsi files to fix that. However, while the NIC is > now probed correctly the current p200.c board file doesn't find the MAC in > efuse and we get random MAC addresses. Patch 2 adds a fallback method for > generating a MAC from the CPU serial. > > [...] Thanks, Applied to https://source.denx.de/u-boot/custodians/u-boot-amlogic (u-boot-amlogic) [1/2] ARM: dts: fix Ethernet on WeTek Hub/Play2 https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/commit/cac77418d6be11445c3e1139f6763b5f5f5fe9fb [2/2] board: amlogic: add meson_generate_serial_ethaddr fallback to p200 https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/commit/65d5c367b00cb392bda560c3da1834979adcf137 -- Neil
Re: [PATCH v1 0/3] board: amlogic: jethubj100: small updates
Hi, On Tue, 27 Feb 2024 09:54:03 +0300, Viacheslav Bocharov wrote: > Update JetHub D1/D1+ board support files. > > Viacheslav Bocharov (3): > board: amlogic: jethubj100: fix common config header > board: amlogic: jethubj100: update MAINTAINERS > board: amlogic: jethubj100: update docs > > [...] Thanks, Applied to https://source.denx.de/u-boot/custodians/u-boot-amlogic (u-boot-amlogic-next) [1/3] board: amlogic: jethubj100: fix common config header https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/commit/803fc9955164e17e8c6d1896ac2770e17c251f11 [2/3] board: amlogic: jethubj100: update MAINTAINERS https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/commit/5e61fedf3424374a065eb23fb48963df2606bb73 [3/3] board: amlogic: jethubj100: update docs https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/commit/2fc5e3c1668cffdb4b894986e98c1ee10f6e9955 -- Neil
Re: [PATCH 0/4] arm: meson: Switch to using upstream DT for GXL, GXM, AXG, G12A, G12B & SM1 SoCs
Hi Viacheslav, On 19/03/2024 15:42, Neil Armstrong wrote: Enable OF_UPSTREAM to use upstream DT and add amlogic/ prefix to the DEFAULT_DEVICE_TREE. And thereby directly build DTB from dts/upstream/src/ including *-u-boot.dtsi files from arch/$(ARCH)/dts/ directory and drop redundant files from arch/arm/dts directory. Only *-u-boot.dtsi files kept in arch/arm/dts directory for these boards. Keep A1 DTs locally since the architecture is still young. CI built & tested at: https://gitlab.com/amlogic-foss/amlogic-u-boot-autotest/-/pipelines/1219273552 Signed-off-by: Neil Armstrong --- Neil Armstrong (4): dts: meson: Switch GXL, GXM & AXG to using upstream DT dts: meson: Drop redundant GXL, GXM & AXG devicetree files Could you run a test run on your boards so make sure is still boots fine ? Thanks, Neil dts: meson-g12a: Switch to using upstream DT dts: meson: Drop redundant G12A, G12B & SM1 devicetree files arch/arm/dts/Makefile | 36 +- arch/arm/dts/meson-axg-jethome-jethub-j100.dts | 361 --- arch/arm/dts/meson-axg-s400.dts| 602 - arch/arm/dts/meson-axg.dtsi| 1957 --- arch/arm/dts/meson-g12-common.dtsi | 2493 arch/arm/dts/meson-g12.dtsi| 385 --- arch/arm/dts/meson-g12a-radxa-zero.dts | 405 arch/arm/dts/meson-g12a-sei510.dts | 566 - arch/arm/dts/meson-g12a-u200.dts | 308 --- arch/arm/dts/meson-g12a.dtsi | 140 -- arch/arm/dts/meson-g12b-a311d-bananapi-m2s.dts | 33 - arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts | 41 - arch/arm/dts/meson-g12b-a311d.dtsi | 149 -- arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts | 165 -- arch/arm/dts/meson-g12b-bananapi-cm4.dtsi | 388 --- arch/arm/dts/meson-g12b-bananapi.dtsi | 521 arch/arm/dts/meson-g12b-gsking-x.dts | 133 -- arch/arm/dts/meson-g12b-gtking-pro.dts | 142 -- arch/arm/dts/meson-g12b-gtking.dts | 163 -- arch/arm/dts/meson-g12b-khadas-vim3.dtsi | 107 - arch/arm/dts/meson-g12b-odroid-go-ultra.dts| 722 -- arch/arm/dts/meson-g12b-odroid-n2-plus.dts | 31 - arch/arm/dts/meson-g12b-odroid-n2.dts | 15 - arch/arm/dts/meson-g12b-odroid-n2.dtsi | 303 --- arch/arm/dts/meson-g12b-odroid-n2l.dts | 125 - arch/arm/dts/meson-g12b-odroid.dtsi| 445 arch/arm/dts/meson-g12b-radxa-zero2.dts| 489 arch/arm/dts/meson-g12b-s922x-bananapi-m2s.dts | 14 - arch/arm/dts/meson-g12b-s922x.dtsi | 139 -- arch/arm/dts/meson-g12b-w400.dtsi | 425 arch/arm/dts/meson-g12b.dtsi | 146 -- arch/arm/dts/meson-gx-libretech-pc.dtsi| 447 arch/arm/dts/meson-gx-mali450.dtsi | 61 - arch/arm/dts/meson-gx-p23x-q20x.dtsi | 324 --- arch/arm/dts/meson-gx.dtsi | 675 -- arch/arm/dts/meson-gxl-mali.dtsi | 17 - arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 319 --- arch/arm/dts/meson-gxl-s805x.dtsi | 23 - arch/arm/dts/meson-gxl-s905d-libretech-pc.dts | 16 - arch/arm/dts/meson-gxl-s905d.dtsi | 12 - .../arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts | 247 -- arch/arm/dts/meson-gxl-s905x-khadas-vim.dts| 237 -- arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts | 313 --- arch/arm/dts/meson-gxl-s905x-libretech-cc.dts | 356 --- arch/arm/dts/meson-gxl-s905x-p212.dts | 134 -- arch/arm/dts/meson-gxl-s905x-p212.dtsi | 213 -- arch/arm/dts/meson-gxl-s905x.dtsi | 18 - arch/arm/dts/meson-gxl.dtsi| 940 arch/arm/dts/meson-gxm-gt1-ultimate.dts| 91 - arch/arm/dts/meson-gxm-khadas-vim2.dts | 424 arch/arm/dts/meson-gxm-s912-libretech-pc.dts | 62 - arch/arm/dts/meson-gxm-wetek-core2.dts | 85 - arch/arm/dts/meson-gxm.dtsi| 216 -- arch/arm/dts/meson-khadas-vim3.dtsi| 534 - arch/arm/dts/meson-sm1-bananapi-m2-pro.dts | 97 - arch/arm/dts/meson-sm1-bananapi-m5.dts | 221 -- arch/arm/dts/meson-sm1-bananapi.dtsi | 435 arch/arm/dts/meson-sm1-khadas-vim3l.dts| 113 - arch/arm/dts/meson-sm1-odroid-c4.dts | 48 - arch/arm/dts/meson-sm1-odroid-hc4.dts | 140 -- arch/arm/dts/meson-sm1-odroid.dtsi | 449 arch/arm/dts/meson-sm1-sei610.dts | 616 - arch/arm/dts/meson-sm1.dtsi
[PATCH v2] board: amlogic: fix buffler overflow in seria, mac & usid read
While meson_sm_read_efuse() doesn't overflow, the string is not
zero terminated and env_set*() will buffer overflow and add random
characters to environment.
Signed-off-by: Neil Armstrong
---
Changes in v2:
- Also fix mac_addr
- Link to v1:
https://lore.kernel.org/r/20240319-u-boot-fix-p200-serial-v1-1-9a4e06815...@linaro.org
---
board/amlogic/beelink-s922x/beelink-s922x.c | 3 ++-
board/amlogic/jethub-j100/jethub-j100.c | 3 ++-
board/amlogic/jethub-j80/jethub-j80.c | 9 ++---
board/amlogic/odroid-n2/odroid-n2.c | 3 ++-
board/amlogic/p200/p200.c | 6 --
board/amlogic/p201/p201.c | 6 --
board/amlogic/p212/p212.c | 6 --
board/amlogic/q200/q200.c | 6 --
board/amlogic/vim3/vim3.c | 3 ++-
9 files changed, 30 insertions(+), 15 deletions(-)
diff --git a/board/amlogic/beelink-s922x/beelink-s922x.c
b/board/amlogic/beelink-s922x/beelink-s922x.c
index adae27fc7e..c2776310a3 100644
--- a/board/amlogic/beelink-s922x/beelink-s922x.c
+++ b/board/amlogic/beelink-s922x/beelink-s922x.c
@@ -20,7 +20,7 @@
int misc_init_r(void)
{
- u8 mac_addr[MAC_ADDR_LEN];
+ u8 mac_addr[MAC_ADDR_LEN + 1];
char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3];
ssize_t len;
@@ -41,6 +41,7 @@ int misc_init_r(void)
tmp[2] = '\0';
mac_addr[i] = hextoul(tmp, NULL);
}
+ mac_addr[MAC_ADDR_LEN] = '\0';
if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
diff --git a/board/amlogic/jethub-j100/jethub-j100.c
b/board/amlogic/jethub-j100/jethub-j100.c
index 6a2c4ad4c3..010fc0df7d 100644
--- a/board/amlogic/jethub-j100/jethub-j100.c
+++ b/board/amlogic/jethub-j100/jethub-j100.c
@@ -17,7 +17,7 @@
int misc_init_r(void)
{
- u8 mac_addr[ARP_HLEN];
+ u8 mac_addr[ARP_HLEN + 1];
char serial[SM_SERIAL_SIZE];
u32 sid;
@@ -34,6 +34,7 @@ int misc_init_r(void)
mac_addr[3] = (sid >> 16) & 0xff;
mac_addr[4] = (sid >> 8) & 0xff;
mac_addr[5] = (sid >> 0) & 0xff;
+ mac_addr[ARP_HLEN] = '\0';
eth_env_set_enetaddr("ethaddr", mac_addr);
}
diff --git a/board/amlogic/jethub-j80/jethub-j80.c
b/board/amlogic/jethub-j80/jethub-j80.c
index 185880de13..0b781666e9 100644
--- a/board/amlogic/jethub-j80/jethub-j80.c
+++ b/board/amlogic/jethub-j80/jethub-j80.c
@@ -27,9 +27,9 @@
int misc_init_r(void)
{
- u8 mac_addr[EFUSE_MAC_SIZE];
- char serial[EFUSE_SN_SIZE];
- char usid[EFUSE_USID_SIZE];
+ u8 mac_addr[EFUSE_MAC_SIZE + 1];
+ char serial[EFUSE_SN_SIZE + 1];
+ char usid[EFUSE_USID_SIZE + 1];
ssize_t len;
unsigned int adcval;
int ret;
@@ -37,6 +37,7 @@ int misc_init_r(void)
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);
+ mac_addr[len] = '\0';
if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
else
@@ -46,6 +47,7 @@ int misc_init_r(void)
if (!env_get("serial")) {
len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
EFUSE_SN_SIZE);
+ serial[len] = '\0';
if (len == EFUSE_SN_SIZE)
env_set("serial", serial);
}
@@ -53,6 +55,7 @@ int misc_init_r(void)
if (!env_get("usid")) {
len = meson_sm_read_efuse(EFUSE_USID_OFFSET, usid,
EFUSE_USID_SIZE);
+ usid[len] = '\0';
if (len == EFUSE_USID_SIZE)
env_set("usid", usid);
}
diff --git a/board/amlogic/odroid-n2/odroid-n2.c
b/board/amlogic/odroid-n2/odroid-n2.c
index 2135457edd..a4bcc62174 100644
--- a/board/amlogic/odroid-n2/odroid-n2.c
+++ b/board/amlogic/odroid-n2/odroid-n2.c
@@ -107,7 +107,7 @@ static int odroid_detect_variant(void)
int misc_init_r(void)
{
- u8 mac_addr[MAC_ADDR_LEN];
+ u8 mac_addr[MAC_ADDR_LEN + 1];
char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3];
ssize_t len;
@@ -128,6 +128,7 @@ int misc_init_r(void)
tmp[2] = '\0';
mac_addr[i] = hextoul(tmp, NULL);
}
+ mac_addr[MAC_ADDR_LEN] = '\0';
if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
diff --git a/board/amlogic/p200/p200.c b/board/amlogic/p200/p200.c
index 7c432f9d28..769e2735d2 100644
---
Re: [PATCH] board: amlogic: fix buffler overflow in serial & usid read
On 20/03/2024 06:28, Dan Carpenter wrote:
On Tue, Mar 19, 2024 at 03:53:24PM +0100, Neil Armstrong wrote:
While meson_sm_read_efuse() doesn't overflow, the string is not
zero terminated and env_set() will buffer overflow and add random
characters to environment.
In the Linux kernel we would give this a CVE because it's information
disclosure bug...
Yes probably
Signed-off-by: Neil Armstrong
---
board/amlogic/jethub-j80/jethub-j80.c | 6 --
board/amlogic/p200/p200.c | 3 ++-
board/amlogic/p201/p201.c | 3 ++-
board/amlogic/p212/p212.c | 3 ++-
board/amlogic/q200/q200.c | 3 ++-
5 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/board/amlogic/jethub-j80/jethub-j80.c
b/board/amlogic/jethub-j80/jethub-j80.c
index 185880de13..d10492cc46 100644
--- a/board/amlogic/jethub-j80/jethub-j80.c
+++ b/board/amlogic/jethub-j80/jethub-j80.c
@@ -28,8 +28,8 @@
int misc_init_r(void)
{
u8 mac_addr[EFUSE_MAC_SIZE];
This one is also a problem. You can't pass non-terminated strings to
eth_env_set_enetaddr(). We call strlen() on it in either hsearch_r() or
env_get_from_linear().
All the other functions had a mac_addr[] issue as well.
Ack, I'll also fix those, I should have checked before...
Btw, this kind of bug is a good candidate for a static checker warning.
I can create a Smatch check for this. It would probably be easier in
Coccinelle even, but I'm the Smatch maintainer.
Would be nice!
regards,
dan carpenter
- char serial[EFUSE_SN_SIZE];
- char usid[EFUSE_USID_SIZE];
+ char serial[EFUSE_SN_SIZE + 1];
+ char usid[EFUSE_USID_SIZE + 1];
ssize_t len;
unsigned int adcval;
int ret;
@@ -46,6 +46,7 @@ int misc_init_r(void)
if (!env_get("serial")) {
len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
EFUSE_SN_SIZE);
+ serial[len] = '\0';
if (len == EFUSE_SN_SIZE)
env_set("serial", serial);
Thanks,
Neil
[PATCH] board: amlogic: fix buffler overflow in serial & usid read
While meson_sm_read_efuse() doesn't overflow, the string is not
zero terminated and env_set() will buffer overflow and add random
characters to environment.
Signed-off-by: Neil Armstrong
---
board/amlogic/jethub-j80/jethub-j80.c | 6 --
board/amlogic/p200/p200.c | 3 ++-
board/amlogic/p201/p201.c | 3 ++-
board/amlogic/p212/p212.c | 3 ++-
board/amlogic/q200/q200.c | 3 ++-
5 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/board/amlogic/jethub-j80/jethub-j80.c
b/board/amlogic/jethub-j80/jethub-j80.c
index 185880de13..d10492cc46 100644
--- a/board/amlogic/jethub-j80/jethub-j80.c
+++ b/board/amlogic/jethub-j80/jethub-j80.c
@@ -28,8 +28,8 @@
int misc_init_r(void)
{
u8 mac_addr[EFUSE_MAC_SIZE];
- char serial[EFUSE_SN_SIZE];
- char usid[EFUSE_USID_SIZE];
+ char serial[EFUSE_SN_SIZE + 1];
+ char usid[EFUSE_USID_SIZE + 1];
ssize_t len;
unsigned int adcval;
int ret;
@@ -46,6 +46,7 @@ int misc_init_r(void)
if (!env_get("serial")) {
len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
EFUSE_SN_SIZE);
+ serial[len] = '\0';
if (len == EFUSE_SN_SIZE)
env_set("serial", serial);
}
@@ -53,6 +54,7 @@ int misc_init_r(void)
if (!env_get("usid")) {
len = meson_sm_read_efuse(EFUSE_USID_OFFSET, usid,
EFUSE_USID_SIZE);
+ usid[len] = '\0';
if (len == EFUSE_USID_SIZE)
env_set("usid", usid);
}
diff --git a/board/amlogic/p200/p200.c b/board/amlogic/p200/p200.c
index 7c432f9d28..37a54e715c 100644
--- a/board/amlogic/p200/p200.c
+++ b/board/amlogic/p200/p200.c
@@ -22,7 +22,7 @@
int misc_init_r(void)
{
u8 mac_addr[EFUSE_MAC_SIZE];
- char serial[EFUSE_SN_SIZE];
+ char serial[EFUSE_SN_SIZE + 1];
ssize_t len;
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
@@ -35,6 +35,7 @@ int misc_init_r(void)
if (!env_get("serial#")) {
len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
EFUSE_SN_SIZE);
+ serial[len] = '\0';
if (len == EFUSE_SN_SIZE)
env_set("serial#", serial);
}
diff --git a/board/amlogic/p201/p201.c b/board/amlogic/p201/p201.c
index 7c432f9d28..37a54e715c 100644
--- a/board/amlogic/p201/p201.c
+++ b/board/amlogic/p201/p201.c
@@ -22,7 +22,7 @@
int misc_init_r(void)
{
u8 mac_addr[EFUSE_MAC_SIZE];
- char serial[EFUSE_SN_SIZE];
+ char serial[EFUSE_SN_SIZE + 1];
ssize_t len;
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
@@ -35,6 +35,7 @@ int misc_init_r(void)
if (!env_get("serial#")) {
len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
EFUSE_SN_SIZE);
+ serial[len] = '\0';
if (len == EFUSE_SN_SIZE)
env_set("serial#", serial);
}
diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c
index fcef90bce5..90ac9f885d 100644
--- a/board/amlogic/p212/p212.c
+++ b/board/amlogic/p212/p212.c
@@ -23,7 +23,7 @@
int misc_init_r(void)
{
u8 mac_addr[EFUSE_MAC_SIZE];
- char serial[EFUSE_SN_SIZE];
+ char serial[EFUSE_SN_SIZE + 1];
ssize_t len;
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
@@ -38,6 +38,7 @@ int misc_init_r(void)
if (!env_get("serial#")) {
len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
EFUSE_SN_SIZE);
+ serial[len] = '\0';
if (len == EFUSE_SN_SIZE)
env_set("serial#", serial);
}
diff --git a/board/amlogic/q200/q200.c b/board/amlogic/q200/q200.c
index 3aa6d8f200..1c47f4645f 100644
--- a/board/amlogic/q200/q200.c
+++ b/board/amlogic/q200/q200.c
@@ -23,7 +23,7 @@
int misc_init_r(void)
{
u8 mac_addr[EFUSE_MAC_SIZE];
- char serial[EFUSE_SN_SIZE];
+ char serial[EFUSE_SN_SIZE + 1];
ssize_t len;
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
@@ -38,6 +38,7 @@ int misc_init_r(void)
if (!env_get("serial#")) {
len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
EFUSE_SN_SIZE);
+ serial[len] = '\0';
if (len == EFUSE_SN_SIZE)
env_set("serial#", serial);
}
---
base-commit: b145877c22b391a4872c875145a8f86f6ffebaba
change-id: 20240319-u-boot-fix-p200-serial-a017f57caf88
Best regards,
--
Neil Armstrong
[PATCH 3/4] dts: meson-g12a: Switch to using upstream DT
Enable OF_UPSTREAM to use upstream DT and add amlogic/ prefix to the DEFAULT_DEVICE_TREE. And thereby directly build DTB from dts/upstream/src/ including *-u-boot.dtsi files from arch/$(ARCH)/dts/ directory. Cc: Sumit Garg Signed-off-by: Neil Armstrong --- arch/arm/mach-meson/Kconfig | 1 + configs/bananapi-cm4-cm4io_defconfig | 2 +- configs/bananapi-m2-pro_defconfig | 2 +- configs/bananapi-m2s_defconfig| 2 +- configs/bananapi-m5_defconfig | 2 +- configs/beelink-gsking-x_defconfig| 2 +- configs/beelink-gtking_defconfig | 2 +- configs/beelink-gtkingpro_defconfig | 2 +- configs/khadas-vim3_android_ab_defconfig | 2 +- configs/khadas-vim3_android_defconfig | 2 +- configs/khadas-vim3_defconfig | 2 +- configs/khadas-vim3l_android_ab_defconfig | 2 +- configs/khadas-vim3l_android_defconfig| 2 +- configs/khadas-vim3l_defconfig| 2 +- configs/odroid-c4_defconfig | 2 +- configs/odroid-go-ultra_defconfig | 2 +- configs/odroid-hc4_defconfig | 2 +- configs/odroid-n2_defconfig | 2 +- configs/odroid-n2l_defconfig | 2 +- configs/radxa-zero2_defconfig | 2 +- configs/radxa-zero_defconfig | 2 +- configs/sei510_defconfig | 2 +- configs/sei610_defconfig | 2 +- configs/u200_defconfig| 2 +- 24 files changed, 24 insertions(+), 23 deletions(-) diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 1d837ae0f3..7570f48e25 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -53,6 +53,7 @@ config MESON_AXG config MESON_G12A bool "G12A" select MESON64_COMMON + imply OF_UPSTREAM help Select this if your SoC is an S905X/D2 diff --git a/configs/bananapi-cm4-cm4io_defconfig b/configs/bananapi-cm4-cm4io_defconfig index 116147fc9a..cb78dabc13 100644 --- a/configs/bananapi-cm4-cm4io_defconfig +++ b/configs/bananapi-cm4-cm4io_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-bananapi-cm4-cm4io" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-bananapi-cm4-cm4io" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/bananapi-m2-pro_defconfig b/configs/bananapi-m2-pro_defconfig index 755bccb4a7..196bc4077d 100644 --- a/configs/bananapi-m2-pro_defconfig +++ b/configs/bananapi-m2-pro_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-bananapi-m2-pro" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-bananapi-m2-pro" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/bananapi-m2s_defconfig b/configs/bananapi-m2s_defconfig index af8daced62..7b137d5e1c 100644 --- a/configs/bananapi-m2s_defconfig +++ b/configs/bananapi-m2s_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-bananapi-m2s" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-a311d-bananapi-m2s" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/bananapi-m5_defconfig b/configs/bananapi-m5_defconfig index 6de5d5fe7b..99ed7c9669 100644 --- a/configs/bananapi-m5_defconfig +++ b/configs/bananapi-m5_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-bananapi-m5" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-bananapi-m5" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/beelink-gsking-x_defconfig b/configs/beelink-gsking-x_defconfig index 99e36e970a..c1e60ede4a 100644 --- a/configs/beelink-gsking-x_defconfig +++ b/configs/beelink-gsking-x_defconfig @@ -7,7 +7,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-gsking-x" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-gsking-x" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/beelink-gtking_defconfig b/configs/beelink-gtking_defconfig index 5c21d8eeab..0b644f0e34 100644 --- a/configs/beelink-gtking_defconfig +++ b/configs/beelink-gtking_defconfig @@ -7,7 +7,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-gtking" +CO
[PATCH 1/4] dts: meson: Switch GXL, GXM & AXG to using upstream DT
Enable OF_UPSTREAM to use upstream DT and add amlogic/ prefix to the DEFAULT_DEVICE_TREE. And thereby directly build DTB from dts/upstream/src/ including *-u-boot.dtsi files from arch/$(ARCH)/dts/ directory. Cc: Sumit Garg Signed-off-by: Neil Armstrong --- arch/arm/mach-meson/Kconfig| 3 +++ configs/beelink-gt1-ultimate_defconfig | 2 +- configs/jethub_j100_defconfig | 2 +- configs/jethub_j80_defconfig | 2 +- configs/khadas-vim2_defconfig | 2 +- configs/khadas-vim_defconfig | 2 +- configs/libretech-ac_defconfig | 2 +- configs/libretech-cc_defconfig | 2 +- configs/libretech-cc_v2_defconfig | 2 +- configs/libretech-s905d-pc_defconfig | 2 +- configs/libretech-s912-pc_defconfig| 2 +- configs/p212_defconfig | 2 +- configs/s400_defconfig | 2 +- configs/wetek-core2_defconfig | 2 +- 14 files changed, 16 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 95e7b019ce..1d837ae0f3 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -32,18 +32,21 @@ config MESON_GXBB config MESON_GXL bool "GXL" select MESON_GX + imply OF_UPSTREAM help Select this if your SoC is an S905X/D or S805X config MESON_GXM bool "GXM" select MESON_GX + imply OF_UPSTREAM help Select this if your SoC is an S912 config MESON_AXG bool "AXG" select MESON64_COMMON + imply OF_UPSTREAM help Select this if your SoC is an A113X/D diff --git a/configs/beelink-gt1-ultimate_defconfig b/configs/beelink-gt1-ultimate_defconfig index 00fdad8544..0e30e13c82 100644 --- a/configs/beelink-gt1-ultimate_defconfig +++ b/configs/beelink-gt1-ultimate_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-gt1-ultimate" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxm-gt1-ultimate" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXM=y diff --git a/configs/jethub_j100_defconfig b/configs/jethub_j100_defconfig index 863245430a..9de6b4b44d 100644 --- a/configs/jethub_j100_defconfig +++ b/configs/jethub_j100_defconfig @@ -8,7 +8,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-axg-jethome-jethub-j100" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-axg-jethome-jethub-j100" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_AXG=y diff --git a/configs/jethub_j80_defconfig b/configs/jethub_j80_defconfig index ca0808f712..85306872f9 100644 --- a/configs/jethub_j80_defconfig +++ b/configs/jethub_j80_defconfig @@ -8,7 +8,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905w-jethome-jethub-j80" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s905w-jethome-jethub-j80" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXL=y diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig index 59ef33723e..50f8b30650 100644 --- a/configs/khadas-vim2_defconfig +++ b/configs/khadas-vim2_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-khadas-vim2" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxm-khadas-vim2" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXM=y diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig index 5ed7c1a408..ac00e8975e 100644 --- a/configs/khadas-vim_defconfig +++ b/configs/khadas-vim_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-khadas-vim" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s905x-khadas-vim" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXL=y diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig index f0ab19580c..6ad0457002 100644 --- a/configs/libretech-ac_defconfig +++ b/configs/libretech-ac_defconfig @@ -9,7 +9,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x CONFIG_ENV_SECT_SIZE=0x1 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s805x-libretech-ac" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s805x-libretech-ac" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXL=y diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig index bb1a37
[PATCH 0/4] arm: meson: Switch to using upstream DT for GXL, GXM, AXG, G12A, G12B & SM1 SoCs
Enable OF_UPSTREAM to use upstream DT and add amlogic/ prefix to the DEFAULT_DEVICE_TREE. And thereby directly build DTB from dts/upstream/src/ including *-u-boot.dtsi files from arch/$(ARCH)/dts/ directory and drop redundant files from arch/arm/dts directory. Only *-u-boot.dtsi files kept in arch/arm/dts directory for these boards. Keep A1 DTs locally since the architecture is still young. CI built & tested at: https://gitlab.com/amlogic-foss/amlogic-u-boot-autotest/-/pipelines/1219273552 Signed-off-by: Neil Armstrong --- Neil Armstrong (4): dts: meson: Switch GXL, GXM & AXG to using upstream DT dts: meson: Drop redundant GXL, GXM & AXG devicetree files dts: meson-g12a: Switch to using upstream DT dts: meson: Drop redundant G12A, G12B & SM1 devicetree files arch/arm/dts/Makefile | 36 +- arch/arm/dts/meson-axg-jethome-jethub-j100.dts | 361 --- arch/arm/dts/meson-axg-s400.dts| 602 - arch/arm/dts/meson-axg.dtsi| 1957 --- arch/arm/dts/meson-g12-common.dtsi | 2493 arch/arm/dts/meson-g12.dtsi| 385 --- arch/arm/dts/meson-g12a-radxa-zero.dts | 405 arch/arm/dts/meson-g12a-sei510.dts | 566 - arch/arm/dts/meson-g12a-u200.dts | 308 --- arch/arm/dts/meson-g12a.dtsi | 140 -- arch/arm/dts/meson-g12b-a311d-bananapi-m2s.dts | 33 - arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts | 41 - arch/arm/dts/meson-g12b-a311d.dtsi | 149 -- arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts | 165 -- arch/arm/dts/meson-g12b-bananapi-cm4.dtsi | 388 --- arch/arm/dts/meson-g12b-bananapi.dtsi | 521 arch/arm/dts/meson-g12b-gsking-x.dts | 133 -- arch/arm/dts/meson-g12b-gtking-pro.dts | 142 -- arch/arm/dts/meson-g12b-gtking.dts | 163 -- arch/arm/dts/meson-g12b-khadas-vim3.dtsi | 107 - arch/arm/dts/meson-g12b-odroid-go-ultra.dts| 722 -- arch/arm/dts/meson-g12b-odroid-n2-plus.dts | 31 - arch/arm/dts/meson-g12b-odroid-n2.dts | 15 - arch/arm/dts/meson-g12b-odroid-n2.dtsi | 303 --- arch/arm/dts/meson-g12b-odroid-n2l.dts | 125 - arch/arm/dts/meson-g12b-odroid.dtsi| 445 arch/arm/dts/meson-g12b-radxa-zero2.dts| 489 arch/arm/dts/meson-g12b-s922x-bananapi-m2s.dts | 14 - arch/arm/dts/meson-g12b-s922x.dtsi | 139 -- arch/arm/dts/meson-g12b-w400.dtsi | 425 arch/arm/dts/meson-g12b.dtsi | 146 -- arch/arm/dts/meson-gx-libretech-pc.dtsi| 447 arch/arm/dts/meson-gx-mali450.dtsi | 61 - arch/arm/dts/meson-gx-p23x-q20x.dtsi | 324 --- arch/arm/dts/meson-gx.dtsi | 675 -- arch/arm/dts/meson-gxl-mali.dtsi | 17 - arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 319 --- arch/arm/dts/meson-gxl-s805x.dtsi | 23 - arch/arm/dts/meson-gxl-s905d-libretech-pc.dts | 16 - arch/arm/dts/meson-gxl-s905d.dtsi | 12 - .../arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts | 247 -- arch/arm/dts/meson-gxl-s905x-khadas-vim.dts| 237 -- arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts | 313 --- arch/arm/dts/meson-gxl-s905x-libretech-cc.dts | 356 --- arch/arm/dts/meson-gxl-s905x-p212.dts | 134 -- arch/arm/dts/meson-gxl-s905x-p212.dtsi | 213 -- arch/arm/dts/meson-gxl-s905x.dtsi | 18 - arch/arm/dts/meson-gxl.dtsi| 940 arch/arm/dts/meson-gxm-gt1-ultimate.dts| 91 - arch/arm/dts/meson-gxm-khadas-vim2.dts | 424 arch/arm/dts/meson-gxm-s912-libretech-pc.dts | 62 - arch/arm/dts/meson-gxm-wetek-core2.dts | 85 - arch/arm/dts/meson-gxm.dtsi| 216 -- arch/arm/dts/meson-khadas-vim3.dtsi| 534 - arch/arm/dts/meson-sm1-bananapi-m2-pro.dts | 97 - arch/arm/dts/meson-sm1-bananapi-m5.dts | 221 -- arch/arm/dts/meson-sm1-bananapi.dtsi | 435 arch/arm/dts/meson-sm1-khadas-vim3l.dts| 113 - arch/arm/dts/meson-sm1-odroid-c4.dts | 48 - arch/arm/dts/meson-sm1-odroid-hc4.dts | 140 -- arch/arm/dts/meson-sm1-odroid.dtsi | 449 arch/arm/dts/meson-sm1-sei610.dts | 616 - arch/arm/dts/meson-sm1.dtsi| 550 - arch/arm/mach-meson/Kconfig|4 + configs/bananapi-cm4-cm4io_defconfig |2 +- configs/bananapi-m2-pro_defconfig |2 +- configs/banana
Re: [PATCH 3/3] configs: amlogic: set board family to avoid random MAC on WeTek Hub/Play2
Hi, On 16/03/2024 14:54, Christian Hewitt wrote: Add CONFIG_SYS_BOARD="p200" to the Hub/Play2 board configs to ensure the factory programmed MAC is correctly read from efuse. Signed-off-by: Christian Hewitt --- configs/wetek-hub_defconfig | 1 + configs/wetek-play2_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/wetek-hub_defconfig b/configs/wetek-hub_defconfig index fd92b041e73..413bbfe9ab7 100644 --- a/configs/wetek-hub_defconfig +++ b/configs/wetek-hub_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_MESON=y +CONFIG_SYS_BOARD="p200" CONFIG_TEXT_BASE=0x0100 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/wetek-play2_defconfig b/configs/wetek-play2_defconfig index b887419a6ba..dd98929444c 100644 --- a/configs/wetek-play2_defconfig +++ b/configs/wetek-play2_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_MESON=y +CONFIG_SYS_BOARD="p200" CONFIG_TEXT_BASE=0x0100 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_SYS_BOARD="p200" is already the default value for MESON_GXBB, see arch/arm/mach-meson/Kconfig Neil
Re: [PATCH 2/3] ARM: board: meson: update efuse MAC reading code
Hi,
On 16/03/2024 14:54, Christian Hewitt wrote:
Current code used for reading the factory programmed MAC from efuse on
p200 boards does not appear to work resulting in a random MAC being
generated. Update the p200 board data reusing the function from the VIM3
source.
I'm pretty sure this code works on the Odroid-C2, but hardkernel had a custom
way to store the mac address so perhaps you should move this code to an
odroid-c2
board file first ?
Or try both methods ? if first method doesn't give a valid mac address
try the ASCII format.
Neil
Signed-off-by: Christian Hewitt
---
board/amlogic/p200/p200.c | 35 +--
1 file changed, 21 insertions(+), 14 deletions(-)
diff --git a/board/amlogic/p200/p200.c b/board/amlogic/p200/p200.c
index 7c432f9d281..fb07eefa532 100644
--- a/board/amlogic/p200/p200.c
+++ b/board/amlogic/p200/p200.c
@@ -14,29 +14,36 @@
#include
#include
-#define EFUSE_SN_OFFSET 20
-#define EFUSE_SN_SIZE 16
-#define EFUSE_MAC_OFFSET 52
-#define EFUSE_MAC_SIZE 6
+#define EFUSE_MAC_OFFSET 0
+#define EFUSE_MAC_SIZE 12
+#define MAC_ADDR_LEN 6
int misc_init_r(void)
{
- u8 mac_addr[EFUSE_MAC_SIZE];
- char serial[EFUSE_SN_SIZE];
+ u8 mac_addr[MAC_ADDR_LEN];
+ char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3];
ssize_t len;
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
- mac_addr, EFUSE_MAC_SIZE);
- if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
+ efuse_mac_addr, EFUSE_MAC_SIZE);
+ if (len != EFUSE_MAC_SIZE)
+ return 0;
+
+ /* MAC is stored in ASCII format, 1bytes = 2characters */
+ for (int i = 0; i < 6; i++) {
+ tmp[0] = efuse_mac_addr[i * 2];
+ tmp[1] = efuse_mac_addr[i * 2 + 1];
+ tmp[2] = '\0';
+ mac_addr[i] = simple_strtoul(tmp, NULL, 16);
+ }
+
+ if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
- }
+ else
+ meson_generate_serial_ethaddr();
- if (!env_get("serial#")) {
- len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
- EFUSE_SN_SIZE);
- if (len == EFUSE_SN_SIZE)
- env_set("serial#", serial);
+ eth_env_get_enetaddr("ethaddr", mac_addr);
}
return 0;
Re: [PATCH 1/3] ARM: dts: fix Ethernet on WeTek Hub/Play2
On 16/03/2024 14:54, Christian Hewitt wrote:
Placing the snps,reset content needed for Ethernet to probe in a common
uboot.dtsi results in the content not being used and broken Ethernet. Fix
this by creating two board specific dtsi files with the right content.
Fixes: 67d5128df950 ("ARM: dts: add support for WeTek Hub and WeTek Play2")
Signed-off-by: Christian Hewitt
---
...u-boot.dtsi => meson-gxbb-wetek-hub-u-boot.dtsi} | 0
arch/arm/dts/meson-gxbb-wetek-play2-u-boot.dtsi | 13 +
2 files changed, 13 insertions(+)
rename arch/arm/dts/{meson-gxbb-wetek-u-boot.dtsi =>
meson-gxbb-wetek-hub-u-boot.dtsi} (100%)
create mode 100644 arch/arm/dts/meson-gxbb-wetek-play2-u-boot.dtsi
diff --git a/arch/arm/dts/meson-gxbb-wetek-u-boot.dtsi
b/arch/arm/dts/meson-gxbb-wetek-hub-u-boot.dtsi
similarity index 100%
rename from arch/arm/dts/meson-gxbb-wetek-u-boot.dtsi
rename to arch/arm/dts/meson-gxbb-wetek-hub-u-boot.dtsi
diff --git a/arch/arm/dts/meson-gxbb-wetek-play2-u-boot.dtsi
b/arch/arm/dts/meson-gxbb-wetek-play2-u-boot.dtsi
new file mode 100644
index 000..3743053eb9c
--- /dev/null
+++ b/arch/arm/dts/meson-gxbb-wetek-play2-u-boot.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong
+ */
+
+#include "meson-gx-u-boot.dtsi"
+
+ {
+ snps,reset-gpio = < GPIOZ_14 0>;
+ snps,reset-delays-us = <0 1 100>;
+ snps,reset-active-low;
+};
Reviewed-by: Neil Armstrong
Re: [PATCH v2 14/14] qcom_defconfig: enable USB
On 15/03/2024 16:10, Caleb Connolly wrote: Enable support for the DWC3 USB controller and required dependencies for Qualcomm boards, specifically the DB845c: * IOMMU / SMMU * USB high-speed PHYs * Mass storage and ACM gadgets I don't see configs for ACM ? Neil Signed-off-by: Caleb Connolly --- configs/qcom_defconfig | 12 1 file changed, 12 insertions(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index eebd0d74bd51..3979c19052db 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -12,8 +12,9 @@ CONFIG_BOOTSTD_FULL=y CONFIG_BOOTDELAY=1 CONFIG_USE_PREBOOT=y CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y CONFIG_SYS_CBSIZE=512 +# CONFIG_SYS_DEVICE_NULLDEV is not set CONFIG_LOG_MAX_LEVEL=9 CONFIG_LOG_DEFAULT_LEVEL=4 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -22,14 +23,17 @@ CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_UFS=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y CONFIG_CMD_CAT=y CONFIG_CMD_BMP=y CONFIG_CMD_LOG=y CONFIG_OF_LIVE=y # CONFIG_NET is not set # CONFIG_OFNODE_MULTI_TREE is not set +CONFIG_DM_WARN=y CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y CONFIG_CLK_QCOM_QCS404=y CONFIG_CLK_QCOM_SDM845=y @@ -37,17 +41,24 @@ CONFIG_MSM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y CONFIG_DM_KEYBOARD=y CONFIG_BUTTON_KEYBOARD=y CONFIG_MMC_HS200_SUPPORT=y +CONFIG_IOMMU=y +CONFIG_QCOM_HYP_SMMU=y +CONFIG_MISC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_MSM=y CONFIG_PHY=y +CONFIG_PHY_QCOM_QUSB2=y +CONFIG_PHY_QCOM_USB_HS_7NM=y CONFIG_PINCTRL=y CONFIG_PINCTRL_QCOM_QCS404=y CONFIG_PINCTRL_QCOM_SDM845=y CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_SCSI=y CONFIG_MSM_SERIAL=y CONFIG_MSM_GENI_SERIAL=y CONFIG_SPMI_MSM=y @@ -56,8 +67,9 @@ CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_UFS=y CONFIG_VIDEO=y # CONFIG_VIDEO_FONT_8X16 is not set CONFIG_VIDEO_FONT_16X32=y
Re: [PATCH v2 13/14] qcom_defconfig: enable livetree
On 15/03/2024 16:10, Caleb Connolly wrote: Qualcomm FDTs are on the larger size, and with the addition of DT modifications during board_init() it makes sense to enable OF_LIVE globally. The cost of building the tree should be offset by the increased efficiency at which we can walk it. Some rough measurements with CONFIG_BOOTSTAGE suggests that this might add 0.1-0.2ms to the boot-to-console time. However the reset-to-reset timer difference is in the range of 0.5ms so this could just be noise. Suffice to say, no significant slow down. Signed-off-by: Caleb Connolly --- configs/qcom_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index cbc612b44bd9..eebd0d74bd51 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -25,8 +25,11 @@ CONFIG_CMD_UFS=y CONFIG_CMD_USB=y CONFIG_CMD_CAT=y CONFIG_CMD_BMP=y CONFIG_CMD_LOG=y +CONFIG_OF_LIVE=y +# CONFIG_NET is not set +# CONFIG_OFNODE_MULTI_TREE is not set CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y CONFIG_CLK_QCOM_QCS404=y CONFIG_CLK_QCOM_SDM845=y Reviewed-by: Neil Armstrong
Re: [PATCH v2 09/14] serial: msm-geni: support livetree
On 15/03/2024 16:10, Caleb Connolly wrote:
When using OF_LIVE, the debug UART driver won't be probed if it's a
subnode of the geni-se-qup controller. Add a NOP driver for the
controller to correctly discover its child nodes.
Signed-off-by: Caleb Connolly
---
drivers/serial/serial_msm_geni.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index 4aa0bc8c72bc..5260474fb9a4 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -605,8 +605,21 @@ U_BOOT_DRIVER(serial_msm_geni) = {
.ops = _serial_ops,
.flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
};
+static const struct udevice_id geniqup_ids[] = {
+ { .compatible = "qcom,geni-se-qup" },
+ { }
+};
+
+U_BOOT_DRIVER(geni_se_qup) = {
+ .name = "geni-se-qup",
+ .id = UCLASS_NOP,
+ .of_match = geniqup_ids,
+ .bind = dm_scan_fdt_dev,
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
+
#ifdef CONFIG_DEBUG_UART_MSM_GENI
static struct msm_serial_data init_serial_data = {
.base = CONFIG_VAL(DEBUG_UART_BASE)
Reviewed-by: Neil Armstrong
Re: [PATCH v2 06/14] clk/qcom: sdm845: add gdscs
On 15/03/2024 16:10, Caleb Connolly wrote:
Define the GDSC power domains for SDM845.
Signed-off-by: Caleb Connolly
---
drivers/clk/qcom/clock-sdm845.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
index ccb0cf245d33..b7154360894a 100644
--- a/drivers/clk/qcom/clock-sdm845.c
+++ b/drivers/clk/qcom/clock-sdm845.c
@@ -145,13 +145,31 @@ static const struct qcom_reset_map sdm845_gcc_resets[] = {
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
};
+static const struct qcom_power_map sdm845_gdscs[] = {
+ [PCIE_0_GDSC] = { 0x6b004 },
+ [PCIE_1_GDSC] = { 0x8d004 },
+ [UFS_CARD_GDSC] = { 0x75004 },
+ [UFS_PHY_GDSC] = { 0x77004 },
+ [USB30_PRIM_GDSC] = { 0xf004 },
+ [USB30_SEC_GDSC] = { 0x10004 },
+ [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { 0x7d030 },
+ [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = { 0x7d03c },
+ [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { 0x7d034 },
+ [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { 0x7d038 },
+ [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { 0x7d040 },
+ [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 },
+ [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 },
+};
+
static struct msm_clk_data sdm845_clk_data = {
.resets = sdm845_gcc_resets,
.num_resets = ARRAY_SIZE(sdm845_gcc_resets),
.clks = sdm845_clks,
.num_clks = ARRAY_SIZE(sdm845_clks),
+ .power_domains = sdm845_gdscs,
+ .num_power_domains = ARRAY_SIZE(sdm845_gdscs),
.enable = sdm845_clk_enable,
.set_rate = sdm845_clk_set_rate,
};
Reviewed-by: Neil Armstrong
Re: [PATCH v2 01/14] mailmap: update Bhupesh's email address
On 15/03/2024 16:10, Caleb Connolly wrote: Update Bhupesh's email to his new one. Signed-off-by: Caleb Connolly --- Cc: Bhupesh Sharma --- .mailmap | 1 + 1 file changed, 1 insertion(+) diff --git a/.mailmap b/.mailmap index d1f08f3eca8a..f6e0847b2168 100644 --- a/.mailmap +++ b/.mailmap @@ -29,8 +29,9 @@ Ashok Reddy Soma Atish Patra Bharat Kumar Gogada Bharat Kumar Gogada Bhargava Sreekantappa Gayathri +Bhupesh Sharma Bin Meng Boris Brezillon Boris Brezillon Christian Kohn Reviewed-by: Neil Armstrong
Re: [PATCH v2 0/5] Qualcomm DWC3 USB support
On 15/03/2024 16:05, Caleb Connolly wrote: This series enables support for Qualcomm platforms in the DWC3 driver, adds support for arbitrary sector sizes to the USB mass storage gadget, and fixes an issue with the CDC ACM driver where it wouldn't initialise the USB device. Additionally, it fixes a syntax bug in the Qualcomm SMMU driver, and makes USB_DWC3_GADGET select DM_USB_GADGET to fix compilation with gadget mode. This is part of a larger series enabling DWC3 USB support on Qualcomm platforms, a feature branch with all patches can be found at [1]. [1]: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/tree/b4/qcom-livetree --- Changes in v2: - Drop custom set/clrbits implementation in qcom dwc3 glue. - Additional minor cleanup based on Marek's comments. - Link to v1: https://lore.kernel.org/r/20240131-b4-qcom-usb-v1-0-6438b2a22...@linaro.org --- Caleb Connolly (5): usb: dwc3-generic: implement Qualcomm wrapper usb: dwc3: select DM_USB_GADGET usb: gadget: CDC ACM: call usb_gadget_initialize usb: gadget: UMS: support multiple sector sizes iommu: qcom-smmu: fix debugging cmd/usb_mass_storage.c | 4 -- drivers/iommu/qcom-hyp-smmu.c | 2 +- drivers/usb/dwc3/Kconfig| 1 + drivers/usb/dwc3/dwc3-generic.c | 81 - drivers/usb/gadget/f_acm.c | 9 drivers/usb/gadget/f_mass_storage.c | 101 drivers/usb/gadget/storage_common.c | 12 +++-- include/usb_mass_storage.h | 1 - 8 files changed, 156 insertions(+), 55 deletions(-) --- base-commit: e03a71b2cefd86ba58df166d4ea820a215ebb655 // Caleb (they/them) LGTM Reviewed-by: Neil Armstrong
Re: [PATCH RFC 00/26] Drop DT upstream compatible dt-binding headers
On 04/03/2024 17:51, Caleb Connolly wrote: Many of the dt-binding headers in U-Boot are based on the upstream ones from Linux, occasionally with minor changes. Although some have additional things defined or are totally different. This series attempts to drop as many of these headers as is easily possible. Those with differing APIs were left as-is. Most of this work was done with a script, with some manual fixing at the end. All-in, we're dropping 393 of the 489 headers from include/dt-bindings. Due to how the include paths are configured, U-Boot headers override upstream ones by the same name, resulting in some upstream DTBs failing to compile (e.g. those that use newer linux-event-codes.h). Swapping the include order would conversely break a bunch of U-Boot DTS files and drivers. Hopefully this makes a good dent, and future efforts to align more architectures with upstream DT will help drop the remaining headers. In addition, the final patch in this series adds support for compiling all upstream DTS files for a given vendor. This is useful in cases where a single U-Boot binary can support many boards, and maintaining a list of supported DTB files would quickly become arduous (as is the case with Qualcomm). To: Tom Rini To: Neil Armstrong To: Sumit Garg To: Patrice Chotard To: Patrick Delaunay To: Jagan Teki To: Simon Glass To: Philipp Tomsich To: Kever Yang To: Lukasz Majewski To: Sean Anderson To: Sam Protsenko To: Matthias Brugger To: Peter Robinson To: Joe Hershberger To: Ramon Fried To: Thierry Reding To: Svyatoslav Ryhel To: Michal Simek To: Paul Barker To: Weijie Gao To: GSS_MTK_Uboot_upstream To: Ryder Lee To: Chunfeng Yun To: Eugen Hristev To: Rick Chen To: Leo To: Ryan Chen To: Chia-Wei Wang To: Aspeed BMC SW team To: Joel Stanley To: Kunihiko Hayashi To: Dai Okamura To: Eugeniy Paltsev Cc: u-boot@lists.denx.de Cc: u-boot-amlo...@groups.io Cc: uboot-st...@st-md-mailman.stormreply.com Cc: uboot-snps-...@synopsys.com Signed-off-by: Caleb Connolly --- Caleb Connolly (26): qcom: drop clock dt-binding headers qcom: drop remaining dt-binding headers sunxi: drop clock dt-binding headers sunxi: drop remaining dt-binding headers imx: drop clock dt-binding headers imx: drop dt-binding headers amlogic: drop dt-binding headers stm: drop dt-binding headers rockchip: drop clock dt-binding headers rockchip: drop remaining dt-binding headers exynos: drop dt-binding headers bcm: drop dt-binding headers ti: drop dt-binding headers tegra: drop clock dt-binding headers tegra: drop dt-binding headers xlnx: drop dt-binding headers renesas: drop clock dt-binding headers renesas: drop remaining dt-binding headers mtk: drop dt-binding headers microchip: drop dt-binding headers hisi: drop dt-binding headers sifive: drop clock headers dt-bindings: drop clock headers dt-bindings: drop remaining device headers dt-bindings: drop generic headers dts: support building all dtb files for a specific vendor arch/arm/dts/exynos7420.dtsi | 2 +- arch/arm/dts/rk3399-u-boot.dtsi| 2 +- arch/arm/dts/tegra186.dtsi | 2 +- arch/riscv/dts/fu540-c000-u-boot.dtsi | 26 +- drivers/clk/exynos/clk-exynos7420.c| 2 +- drivers/clk/rockchip/clk_rk3399.c | 2 +- drivers/clk/sifive/fu540-prci.c| 8 +- drivers/mailbox/tegra-hsp.c| 2 +- drivers/net/phy/dp83869.c | 2 + drivers/pinctrl/rockchip/pinctrl-rk3568.c | 15 + dts/Kconfig| 24 + include/dt-bindings/arm/coresight-cti-dt.h | 37 - include/dt-bindings/arm/ux500_pm_domains.h | 15 - include/dt-bindings/ata/ahci.h | 20 - include/dt-bindings/bus/moxtet.h | 16 - include/dt-bindings/bus/ti-sysc.h | 28 - include/dt-bindings/clk/ti-dra7-atl.h | 40 - include/dt-bindings/clock/actions,s700-cmu.h | 118 --- include/dt-bindings/clock/actions,s900-cmu.h | 129 --- include/dt-bindings/clock/agilex-clock.h | 71 -- include/dt-bindings/clock/am3.h| 227 - .../clock/amlogic,a1-peripherals-clkc.h| 168 include/dt-bindings/clock/amlogic,a1-pll-clkc.h| 25 - include/dt-bindings/clock/ast2600-clock.h | 62 -- include/dt-bindings/clock/at91.h | 23 - include/dt-bindings/clock/axg-aoclkc.h | 31 - include/dt-bindings/clock/axg-audio-clkc.h | 94 --- include/dt-bindings/clock/axg-clkc.h | 100 --- include/dt-bindings/clock/bcm-nsp.h| 51 -- include/dt-bindings/clock/bcm2835
Re: [PATCH RFC 07/26] amlogic: drop dt-binding headers
On 11/03/2024 09:51, Caleb Connolly wrote: Dropped in favour of dts/upstream Signed-off-by: Caleb Connolly --- .../clock/amlogic,a1-peripherals-clkc.h| 168 - include/dt-bindings/clock/amlogic,a1-pll-clkc.h| 25 --- include/dt-bindings/clock/axg-aoclkc.h | 31 include/dt-bindings/clock/axg-audio-clkc.h | 94 include/dt-bindings/clock/axg-clkc.h | 100 include/dt-bindings/clock/g12a-aoclkc.h| 36 - include/dt-bindings/clock/g12a-clkc.h | 153 --- include/dt-bindings/clock/gxbb-aoclkc.h| 74 - include/dt-bindings/clock/gxbb-clkc.h | 151 -- include/dt-bindings/gpio/meson-a1-gpio.h | 73 - include/dt-bindings/gpio/meson-axg-gpio.h | 116 -- include/dt-bindings/gpio/meson-g12a-gpio.h | 114 -- include/dt-bindings/gpio/meson-gxbb-gpio.h | 148 -- include/dt-bindings/gpio/meson-gxl-gpio.h | 125 --- include/dt-bindings/power/meson-a1-power.h | 32 include/dt-bindings/power/meson-axg-power.h| 14 -- include/dt-bindings/power/meson-g12a-power.h | 13 -- include/dt-bindings/power/meson-gxbb-power.h | 13 -- include/dt-bindings/power/meson-sm1-power.h| 18 --- include/dt-bindings/reset/amlogic,meson-a1-reset.h | 76 -- .../reset/amlogic,meson-axg-audio-arb.h| 19 --- .../dt-bindings/reset/amlogic,meson-axg-reset.h| 123 --- .../reset/amlogic,meson-g12a-audio-reset.h | 53 --- .../dt-bindings/reset/amlogic,meson-g12a-reset.h | 137 - .../dt-bindings/reset/amlogic,meson-gxbb-reset.h | 161 include/dt-bindings/reset/axg-aoclkc.h | 20 --- include/dt-bindings/reset/g12a-aoclkc.h| 18 --- include/dt-bindings/reset/gxbb-aoclkc.h| 66 include/dt-bindings/sound/meson-aiu.h | 18 --- include/dt-bindings/sound/meson-g12a-toacodec.h| 10 -- include/dt-bindings/sound/meson-g12a-tohdmitx.h| 13 -- 31 files changed, 2212 deletions(-) Reviewed-by: Neil Armstrong
Re: [PATCH v6 00/11] An effort to bring DT bindings compliance within U-Boot
On 01/03/2024 14:30, Sumit Garg wrote: On Fri, 1 Mar 2024 at 18:27, Tom Rini wrote: On Thu, 22 Feb 2024 15:05:56 +0530, Sumit Garg wrote: Changes in v6: -- - v6_dt: https://github.com/b49020/u-boot/tree/v6_dt - Patch #3: Incorporate fix for sandbox CI failure. - Patch #6: Incorporate shell script comments from Marek. - Patch #8: Incorporate documentation review comments from Paul. [...] Applied to u-boot/next, thanks! Thanks Tom and everyone involved with the reviews. I hope we can carry forward from this effort towards a healthy devicetree story for U-Boot. Thanks Sumit! I'll try to submit patches for Amlogic GXL & G12A to switch to this! Neil -Sumit -- Tom
Re: [PATCH v1 0/3] board: amlogic: jethubj100: small updates
On 27/02/2024 07:54, Viacheslav Bocharov wrote: Update JetHub D1/D1+ board support files. Viacheslav Bocharov (3): board: amlogic: jethubj100: fix common config header board: amlogic: jethubj100: update MAINTAINERS board: amlogic: jethubj100: update docs board/amlogic/jethub-j100/MAINTAINERS | 2 +- doc/board/amlogic/jethub-j100.rst | 9 ++--- include/configs/jethub.h | 2 +- 3 files changed, 8 insertions(+), 5 deletions(-) base-commit: d49fa3defa50c6d3f04acbb52fd486c13c14ab6a Reviewed-by: Neil Armstrong
[PULL] Please pull u-boot-amlogic-fixes-20240223
From: Neil Armstrong Please pull this simple config fixes for the Khadas VIM3 Android setup to fix an Out Of Memory error for AVB. Thanks, Neil The following changes since commit 5e4a0c7f4a2c9d4670b75a6a2056243b1a56512b: Merge branch 'qcom-fixes-2024.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-snapdragon (2024-02-22 11:34:59 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-amlogic.git tags/u-boot-amlogic-fixes-20240223 for you to fetch changes up to fc0a7431e1729f456690468f2e9570fcc2c18175: configs: khadas-vim3*_android: fix AVB oom error (2024-02-23 18:22:50 +0100) - fix AVB oom error for Khadas VIM3 Android configs Mattijs Korpershoek (1): configs: khadas-vim3*_android: fix AVB oom error configs/khadas-vim3_android_ab_defconfig | 1 + configs/khadas-vim3_android_defconfig | 1 + configs/khadas-vim3l_android_ab_defconfig | 1 + configs/khadas-vim3l_android_defconfig| 1 + 4 files changed, 4 insertions(+)
Re: [PATCH] configs: khadas-vim3*_android: fix AVB oom error
Hi,
On Fri, 09 Feb 2024 09:58:35 +0100, Mattijs Korpershoek wrote:
> When booting Android with AVB enabled, an OOM is observed:
>
> => avb init ${mmcdev}
> => avb verify _a
> ## Android Verified Boot 2.0 version 1.1.0
> read_is_device_unlocked not supported yet
> read_rollback_index not supported yet
> avb_util.c:182: ERROR: Failed to allocate memory.
> OOM error occurred during verification
>
> [...]
Thanks, Applied to https://source.denx.de/u-boot/custodians/u-boot-amlogic
(u-boot-amlogic)
[1/1] configs: khadas-vim3*_android: fix AVB oom error
https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/commit/fc0a7431e1729f456690468f2e9570fcc2c18175
--
Neil
Re: [PATCH v4 10/39] gpio: qcom_pmic: add a quirk to skip GPIO configuration
On 20/02/2024 06:56, Sumit Garg wrote:
On Fri, 16 Feb 2024 at 02:22, Caleb Connolly wrote:
Some platforms hard reset when attempting to configure PMIC GPIOs. Add
support for quirks specified in match data with a single quirk to skip
this configuration. We rely on the GPIO already be configured correctly,
which is always the case for volume up (the only current user of these
GPIOs).
I can't find a similar quirk in the counterpart Linux driver
(drivers/pinctrl/qcom/pinctrl-spmi-gpio.c). Is there anything we are
missing in the U-Boot driver?
It's not ideal, it's fine to have it at first but at some point a proper
solution should be found.
Neil
-Sumit
Signed-off-by: Caleb Connolly
---
drivers/gpio/qcom_pmic_gpio.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index 2a4fef8d28cb..198cd84bc31e 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -64,6 +64,15 @@
#define REG_EN_CTL 0x46
#define REG_EN_CTL_ENABLE (1 << 7)
+/**
+ * pmic_gpio_match_data - platform specific configuration
+ *
+ * @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to
configure them
+ */
+enum pmic_gpio_quirks {
+ QCOM_PMIC_QUIRK_READONLY = (1 << 0),
+};
+
struct qcom_gpio_bank {
uint32_t pid; /* Peripheral ID on SPMI bus */
bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */
@@ -75,7 +84,12 @@ static int qcom_gpio_set_direction(struct udevice *dev,
unsigned offset,
struct qcom_gpio_bank *priv = dev_get_priv(dev);
uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
uint32_t reg_ctl_val;
- int ret;
+ ulong quirks = dev_get_driver_data(dev);
+ int ret = 0;
+
+ /* Some PMICs don't like their GPIOs being configured */
+ if (quirks & QCOM_PMIC_QUIRK_READONLY)
+ return 0;
/* Disable the GPIO */
ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
@@ -304,7 +318,7 @@ static int qcom_gpio_of_to_plat(struct udevice *dev)
static const struct udevice_id qcom_gpio_ids[] = {
{ .compatible = "qcom,pm8916-gpio" },
{ .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
- { .compatible = "qcom,pm8998-gpio" },
+ { .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
{ .compatible = "qcom,pms405-gpio" },
{ }
};
--
2.43.1
