[U-Boot] [PATCH 1/4][v2] config: lsch3: Define CONFIG_SYS_CACHELINE_SIZE for LS2085A
Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by USB XHCI stack for alignment Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- changes for v2 : None arch/arm/include/asm/arch-fsl-lsch3/config.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index ca8d38c..02332dc 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -10,6 +10,7 @@ #include fsl_ddrc_version.h #define CONFIG_SYS_PAGE_SIZE 0x1 +#define CONFIG_SYS_CACHELINE_SIZE 64 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/4][v2] config: lsch3: Define USB XHCI controller base address for LS2085A
Define base address of both usb xhci controllers in lsch3 config in the format (IMMR + offset) for LS2085A Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- Changes for v2 : - Descriptive commit message arch/arm/include/asm/arch-fsl-lsch3/config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 02332dc..992dc11 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -64,6 +64,9 @@ #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x0102) #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x0103) +#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x0210) +#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x0211) + /* TZ Protection Controller Definitions */ #define TZPC_BASE 0x0220 #define TZPCR0SIZE_BASE(TZPC_BASE) -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/4][v2] config: ls2085ardb: Add USB support for ls2085ardb
Add USB XHCI support for ls2085rdb platform Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- Changes for v2: None include/configs/ls2085ardb.h | 13 + 1 file changed, 13 insertions(+) diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h index a0f0f6c..a81653c 100644 --- a/include/configs/ls2085ardb.h +++ b/include/configs/ls2085ardb.h @@ -288,6 +288,19 @@ unsigned long get_board_sys_clk(void); #define CONFIG_MISC_INIT_R +/* + * USB + */ +#define CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_EXT2 + /* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4][v2] config: ls2085aqds: Add USB support for ls2085aqds
Add USB XHCI support for ls2085qds platform Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- Changes for v2 : None include/configs/ls2085aqds.h | 13 + 1 file changed, 13 insertions(+) diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h index 731eca2..7b77fb4 100644 --- a/include/configs/ls2085aqds.h +++ b/include/configs/ls2085aqds.h @@ -354,4 +354,17 @@ unsigned long get_board_ddr_clk(void); #endif +/* + * USB + */ +#define CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT2 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_EXT2 + #endif /* __LS2_QDS_H */ -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] drivers: usb: fsl: Remove LS102XA immap inclusion
Remove LS102XA immap header inclusion from xhci fsl driver. It removes redefinition warnings when built for platforms other than LS102XA Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- drivers/usb/host/xhci-fsl.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c index 6781b94..6481e07 100644 --- a/drivers/usb/host/xhci-fsl.c +++ b/drivers/usb/host/xhci-fsl.c @@ -11,7 +11,6 @@ #include common.h #include usb.h #include asm-generic/errno.h -#include asm/arch-ls102xa/immap_ls102xa.h #include linux/compat.h #include linux/usb/xhci-fsl.h #include linux/usb/dwc3.h -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/4] include: usb: Map USB controller base addresses for LS2085A
Map USB XHCI controller base addresses for LS2085A SOC
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
include/linux/usb/xhci-fsl.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index b07bf19..602a413 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -54,6 +54,9 @@ struct fsl_xhci {
#if defined(CONFIG_LS102XA)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#elif defined(CONFIG_LS2085A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2085A_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2085A_XHCI_USB2_ADDR
#endif
#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
--
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[U-Boot] [PATCH 2/4] drivers: usb: fsl: Implement Erratum A-009116 for XHCI controller
This adjusts (micro)frame length to appropriate value thus
avoiding USB devices to time out over a longer run
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
drivers/usb/host/xhci-dwc3.c | 6 ++
drivers/usb/host/xhci-fsl.c | 3 +++
include/linux/usb/dwc3.h | 22 --
3 files changed, 25 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index 67147cb..c722c50 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -89,3 +89,9 @@ int dwc3_core_init(struct dwc3 *dwc3_reg)
return 0;
}
+
+void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
+{
+ setbits_le32(dwc3_reg-g_fladj, GFLADJ_30MHZ_REG_SEL |
+ GFLADJ_30MHZ(val));
+}
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index 385422a..6781b94 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -58,6 +58,9 @@ static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
/* We are hard-coding DWC3 core to Host Mode */
dwc3_set_mode(fsl_xhci-dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+ /* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
+ dwc3_set_fladj(fsl_xhci-dwc3_reg, GFLADJ_30MHZ_DEFAULT);
+
return ret;
}
diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
index ba7f314..dd934a0 100644
--- a/include/linux/usb/dwc3.h
+++ b/include/linux/usb/dwc3.h
@@ -109,7 +109,11 @@ struct dwc3 { /*
offset: 0xC100 */
u32 g_hwparams8;
- u32 reserved4[63];
+ u32 reserved4[11];
+
+ u32 g_fladj;
+
+ u32 reserved5[51];
u32 d_cfg;
u32 d_ctl;
@@ -118,15 +122,15 @@ struct dwc3 { /*
offset: 0xC100 */
u32 d_gcmdpar;
u32 d_gcmd;
- u32 reserved5[2];
+ u32 reserved6[2];
u32 d_alepena;
- u32 reserved6[55];
+ u32 reserved7[55];
struct d_physical_endpoint d_phy_ep_cmd[32];
- u32 reserved7[128];
+ u32 reserved8[128];
u32 o_cfg;
u32 o_ctl;
@@ -134,7 +138,7 @@ struct dwc3 { /*
offset: 0xC100 */
u32 o_evten;
u32 o_sts;
- u32 reserved8[3];
+ u32 reserved9[3];
u32 adp_cfg;
u32 adp_ctl;
@@ -143,7 +147,7 @@ struct dwc3 { /*
offset: 0xC100 */
u32 bc_cfg;
- u32 reserved9;
+ u32 reserved10;
u32 bc_evt;
u32 bc_evten;
@@ -191,10 +195,16 @@ struct dwc3 { /*
offset: 0xC100 */
#define DWC3_DCTL_CSFTRST (1 30)
#define DWC3_DCTL_LSFTRST (1 29)
+/* Global Frame Length Adjustment Register */
+#define GFLADJ_30MHZ_REG_SEL (1 7)
+#define GFLADJ_30MHZ(n)((n) 0x3f)
+#define GFLADJ_30MHZ_DEFAULT 0x20
+
#ifdef CONFIG_USB_XHCI_DWC3
void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
int dwc3_core_init(struct dwc3 *dwc3_reg);
void usb_phy_reset(struct dwc3 *dwc3_reg);
+void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val);
#endif
#endif /* __DWC3_H_ */
--
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[U-Boot] [PATCH 1/4] drivers: usb: fsl: Remove warnings for 64-bit architectures
Replace uint32_t with uintptr_t to remove compilation warnings for 64-bit architectures. Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- Depends on commit ec3faf7e2c0671b906018b3c481be2a490bf2bb3 in u-boot-usb/next drivers/usb/host/xhci-fsl.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c index f624c90..385422a 100644 --- a/drivers/usb/host/xhci-fsl.c +++ b/drivers/usb/host/xhci-fsl.c @@ -91,12 +91,12 @@ int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) } *hccr = (struct xhci_hccr *)ctx-hcd; - *hcor = (struct xhci_hcor *)((uint32_t) *hccr + *hcor = (struct xhci_hcor *)((uintptr_t) *hccr + HC_LENGTH(xhci_readl((*hccr)-cr_capbase))); - debug(fsl-xhci: init hccr %x and hcor %x hc_length %d\n, - (uint32_t)*hccr, (uint32_t)*hcor, - (uint32_t)HC_LENGTH(xhci_readl((*hccr)-cr_capbase))); + debug(fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n, + (uintptr_t)*hccr, (uintptr_t)*hcor, + (uintptr_t)HC_LENGTH(xhci_readl((*hccr)-cr_capbase))); return ret; } -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4] config: ls2085aqds: Add USB support for ls2085aqds
Add USB XHCI support for ls2085qds platform Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- include/configs/ls2085aqds.h | 13 + 1 file changed, 13 insertions(+) diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h index 731eca2..7b77fb4 100644 --- a/include/configs/ls2085aqds.h +++ b/include/configs/ls2085aqds.h @@ -354,4 +354,17 @@ unsigned long get_board_ddr_clk(void); #endif +/* + * USB + */ +#define CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT2 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_EXT2 + #endif /* __LS2_QDS_H */ -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/4] config: ls2085ardb: Add USB support for ls2085ardb
Add USB XHCI support for ls2085rdb platform Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- include/configs/ls2085ardb.h | 13 + 1 file changed, 13 insertions(+) diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h index a0f0f6c..a81653c 100644 --- a/include/configs/ls2085ardb.h +++ b/include/configs/ls2085ardb.h @@ -288,6 +288,19 @@ unsigned long get_board_sys_clk(void); #define CONFIG_MISC_INIT_R +/* + * USB + */ +#define CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_EXT2 + /* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/4] config: lsch3: Define USB XHCI controller base address for LS2085A
Define base address of usb xhci controllers for LS2085A SOC Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 02332dc..992dc11 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -64,6 +64,9 @@ #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x0102) #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x0103) +#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x0210) +#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x0211) + /* TZ Protection Controller Definitions */ #define TZPC_BASE 0x0220 #define TZPCR0SIZE_BASE(TZPC_BASE) -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4] include: usb: Move USB controller base address mapping
Move USB controller Base address mapping from ls102xa immap
to fsl xhci header. This is required to remove any warnings when
controller base addresses are mapped for multiple platforms
in their respective files.
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 9 -
include/linux/usb/xhci-fsl.h | 7 +++
2 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 8e5fcdc..2abfc4d 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -396,13 +396,4 @@ struct ccsr_cci400 {
u8 res_e004[0x1 - 0xe004];
};
-/* USB-XHCI */
-#define FSL_XHCI_BASE 0x310
-#define FSL_OCP1_SCP_BASE 0x4a084c00
-#define FSL_OTG_WRAPPER_BASE 0x4A02
-
-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
-#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
- CONFIG_SYS_FSL_XHCI_USB2_ADDR}
#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index 8eaab2c..b07bf19 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -51,4 +51,11 @@ struct fsl_xhci {
struct dwc3 *dwc3_reg;
};
+#if defined(CONFIG_LS102XA)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#endif
+
+#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
+ CONFIG_SYS_FSL_XHCI_USB2_ADDR}
#endif /* _ASM_ARCH_XHCI_FSL_H_ */
--
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[U-Boot] [PATCH 1/4] config: lsch3: Define CONFIG_SYS_CACHELINE_SIZE for LS2085A
Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by USB XHCI stack for alignment Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- This patchset depends on a patchset sent to u-boot-usb/next http://patchwork.ozlabs.org/patch/487462/ arch/arm/include/asm/arch-fsl-lsch3/config.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index ca8d38c..02332dc 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -10,6 +10,7 @@ #include fsl_ddrc_version.h #define CONFIG_SYS_PAGE_SIZE 0x1 +#define CONFIG_SYS_CACHELINE_SIZE 64 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH][v2] drivers: usb: fsl: Return if USB_MAX_CONTROLLER_COUNT is incorrect
Return if USB_MAX_CONTROLLER_COUNT hence the index of the controller to be initialised is incorrect Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- Changes for v2 - Added space between tags in Subject - Replaced return value from -1 to -EINVAL drivers/usb/host/ehci-fsl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 5fd618d..97b7f14 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -76,7 +76,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, break; default: printf(ERROR: wrong controller index!!\n); - break; + return -EINVAL; }; *hccr = (struct ehci_hccr *)((uint32_t)ehci-caplength); -- 1.7.11.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc: mpc85xx: Correct CONFIG_USB_MAX_CONTROLLER_COUNT for p1025
Correct the value CONFIG_USB_MAX_CONTROLLER_COUNT macro to 1 for p1025 as it has one USB controller Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- arch/powerpc/include/asm/config_mpc85xx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 9d56bc1..349146f 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -334,7 +334,7 @@ #elif defined(CONFIG_P1025) #define CONFIG_MAX_CPUS2 #define CONFIG_SYS_FSL_NUM_LAWS12 -#define CONFIG_USB_MAX_CONTROLLER_COUNT2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT1 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM -- 1.7.11.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] drivers:usb:fsl: Return if USB_MAX_CONTROLLER_COUNT is incorrect
Return if USB_MAX_CONTROLLER_COUNT hence the index of the controller to be initialised is incorrect Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- drivers/usb/host/ehci-fsl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index ed83eb4..1973e0b 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -76,7 +76,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, break; default: printf(ERROR: wrong controller index!!\n); - break; + return -1; }; *hccr = (struct ehci_hccr *)((uint32_t)ehci-caplength); -- 1.7.11.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] drivers:usb:fsl: Implement Erratum A-009116 for XHCI controller
This adjusts (micro)frame length to appropriate value thus
avoiding USB devices to time out over a longer run
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Depends on fsl/usb: Add USB XHCI support
http://patchwork.ozlabs.org/patch/373593/
drivers/usb/host/xhci-fsl.c | 9 +
include/linux/usb/dwc3.h | 19 +--
include/linux/usb/xhci-fsl.h | 2 ++
3 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index 1d25084..981cf17 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -29,6 +29,12 @@ inline int __board_usb_init(int index, enum usb_init_type
init)
int board_usb_init(int index, enum usb_init_type init)
__attribute__((weak, alias(__board_usb_init)));
+static void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
+{
+ setbits_le32(dwc3_reg-g_fladj, GFLADJ_30MHZ_REG_SEL |
+GFLADJ_30MHZ(val));
+}
+
static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
{
clrsetbits_le32(dwc3_reg-g_ctl,
@@ -100,6 +106,9 @@ static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
/* We are hard-coding DWC3 core to Host Mode */
dwc3_set_mode(fsl_xhci-dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+ /* Set GFLADJ_30MHZ value as per Erratum A009116 */
+ dwc3_set_fladj(fsl_xhci-dwc3_reg, GFLADJ_30MHZ_DEFAULT);
+
return ret;
}
diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
index 7edc760..13d58e9 100644
--- a/include/linux/usb/dwc3.h
+++ b/include/linux/usb/dwc3.h
@@ -109,7 +109,11 @@ struct dwc3 { /*
offset: 0xC100 */
u32 g_hwparams8;
- u32 reserved4[63];
+ u32 reserved4[11];
+
+ u32 g_fladj;
+
+ u32 reserved5[51];
u32 d_cfg;
u32 d_ctl;
@@ -118,15 +122,15 @@ struct dwc3 { /*
offset: 0xC100 */
u32 d_gcmdpar;
u32 d_gcmd;
- u32 reserved5[2];
+ u32 reserved6[2];
u32 d_alepena;
- u32 reserved6[55];
+ u32 reserved7[55];
struct d_physical_endpoint d_phy_ep_cmd[32];
- u32 reserved7[128];
+ u32 reserved8[128];
u32 o_cfg;
u32 o_ctl;
@@ -134,7 +138,7 @@ struct dwc3 { /*
offset: 0xC100 */
u32 o_evten;
u32 o_sts;
- u32 reserved8[3];
+ u32 reserved9[3];
u32 adp_cfg;
u32 adp_ctl;
@@ -143,7 +147,7 @@ struct dwc3 { /*
offset: 0xC100 */
u32 bc_cfg;
- u32 reserved9;
+ u32 reserved10;
u32 bc_evt;
u32 bc_evten;
@@ -191,4 +195,7 @@ struct dwc3 { /*
offset: 0xC100 */
#define DWC3_DCTL_CSFTRST (1 30)
#define DWC3_DCTL_LSFTRST (1 29)
+/* Global Frame Length Adjustment Register */
+#define GFLADJ_30MHZ_REG_SEL (1 7)
+#define GFLADJ_30MHZ(n)((n) 0x3f)
#endif /* __DWC3_H_ */
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index 54b7e8b..22a65e9 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -10,6 +10,8 @@
#ifndef _ASM_ARCH_XHCI_FSL_H_
#define _ASM_ARCH_XHCI_FSL_H_
+#define GFLADJ_30MHZ_DEFAULT 0x20
+
/* USBOTGSS_WRAPPER definitions */
#define USBOTGSS_WRAPRESET (1 17)
#define USBOTGSS_DMADISABLE (1 16)
--
1.7.11.7
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[U-Boot] [PATCH] drivers:usb: Check if USB Erratum A005697 is applicable on BSC913x
Check if USB Erratum A005697 is applicable on BSC913x and
add corresponding property in the device tree via device
tree fixup which is used by linux driver
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Depends on drivers:usb:fsl: Add affected SOCs for USB Erratum A007792
http://patchwork.ozlabs.org/patch/448965/
drivers/usb/host/ehci-fsl.c | 9 +
include/fsl_usb.h | 18 ++
2 files changed, 27 insertions(+)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index ed83eb4..2dca524 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -263,6 +263,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
int usb_erratum_a006261_off = -1;
int usb_erratum_a007075_off = -1;
int usb_erratum_a007792_off = -1;
+ int usb_erratum_a005697_off = -1;
int usb_mode_off = -1;
int usb_phy_off = -1;
char str[5];
@@ -346,6 +347,14 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
if (usb_erratum_a007792_off 0)
return;
}
+ if (has_erratum_a005697()) {
+ usb_erratum_a005697_off = fdt_fixup_usb_erratum
+ (blob,
+ fsl,usb-erratum-a005697,
+ usb_erratum_a005697_off);
+ if (usb_erratum_a005697_off 0)
+ return;
+ }
}
}
#endif
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index 92751dd..33d9f03 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -196,6 +196,19 @@ static inline bool has_erratum_a007792(void)
return false;
}
+static inline bool has_erratum_a005697(void)
+{
+ u32 svr = get_svr();
+ u32 soc = SVR_SOC_VER(svr);
+
+ switch (soc) {
+ case SVR_9131:
+ case SVR_9132:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+ }
+ return false;
+}
+
#else
static inline bool has_dual_phy(void)
{
@@ -221,5 +234,10 @@ static inline bool has_erratum_a007792(void)
{
return false;
}
+
+static inline bool has_erratum_a005697(void)
+{
+ return false;
+}
#endif
#endif /*_ASM_FSL_USB_H_ */
--
1.7.11.7
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[U-Boot] [PATCH 2/2] ls102xa: config: Add USB XHCI controller base address for LS102XA
Define base address of usb xhci controller
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/config.h | 1 +
include/linux/usb/xhci-fsl.h | 5 +
2 files changed, 6 insertions(+)
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
b/arch/arm/include/asm/arch-ls102xa/config.h
index 6561ce6..f672341 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -35,6 +35,7 @@
#define CONFIG_SYS_NS16550_COM1(CONFIG_SYS_IMMR +
0x011c0500)
#define CONFIG_SYS_NS16550_COM2(CONFIG_SYS_IMMR +
0x011d0500)
#define CONFIG_SYS_DCU_ADDR(CONFIG_SYS_IMMR + 0x01ce)
+#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x0210)
#define CONFIG_SYS_LS102XA_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index 0019a16..54b7e8b 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -35,6 +35,11 @@
#define USBOTGSS_IRQ_SET_1_OEVT_EN (1 16)
#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN(1 17)
+#ifdef CONFIG_LS102XA
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#endif
+
struct fsl_xhci {
struct xhci_hccr *hcd;
struct dwc3 *dwc3_reg;
--
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[U-Boot] [PATCH 1/2] drivers: usb: fsl: Add support for two USB XHCI controllers
Add support for two USB XHCI controllers for fsl platforms
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Depends on fsl/usb: Add USB XHCI support
drivers/usb/host/xhci-fsl.c | 17 ++---
include/linux/usb/xhci-fsl.h | 5 -
2 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index 381c322..1d25084 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -113,8 +113,19 @@ int xhci_hcd_init(int index, struct xhci_hccr **hccr,
struct xhci_hcor **hcor)
struct fsl_xhci *ctx = fsl_xhci;
int ret = 0;
- ctx-hcd = (struct xhci_hccr *)FSL_XHCI_BASE;
- ctx-dwc3_reg = (struct dwc3 *)(FSL_XHCI_BASE + DWC3_REG_OFFSET);
+ switch (index) {
+ case 0:
+ ctx-hcd = (struct xhci_hccr *)CONFIG_SYS_FSL_XHCI_USB1_ADDR;
+ break;
+ case 1:
+ ctx-hcd = (struct xhci_hccr *)CONFIG_SYS_FSL_XHCI_USB2_ADDR;
+ break;
+ default:
+ printf(ERROR: wrong controller index!!\n);
+ break;
+ };
+
+ ctx-dwc3_reg = (struct dwc3 *)((char *)(ctx-hcd) + DWC3_REG_OFFSET);
ret = board_usb_init(index, USB_INIT_HOST);
if (ret != 0) {
@@ -128,7 +139,7 @@ int xhci_hcd_init(int index, struct xhci_hccr **hccr,
struct xhci_hcor **hcor)
return ret;
}
- *hccr = (struct xhci_hccr *)(FSL_XHCI_BASE);
+ *hccr = (ctx-hcd);
*hcor = (struct xhci_hcor *)((uint32_t) *hccr
+ HC_LENGTH(xhci_readl((*hccr)-cr_capbase)));
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index 1dc1e12..0019a16 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -10,9 +10,6 @@
#ifndef _ASM_ARCH_XHCI_FSL_H_
#define _ASM_ARCH_XHCI_FSL_H_
-/* Default to the FSL XHCI defines */
-#define FSL_XHCI_BASE 0x310
-
/* USBOTGSS_WRAPPER definitions */
#define USBOTGSS_WRAPRESET (1 17)
#define USBOTGSS_DMADISABLE (1 16)
@@ -38,8 +35,6 @@
#define USBOTGSS_IRQ_SET_1_OEVT_EN (1 16)
#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN(1 17)
-#define DWC3_REG_OFFSET0xc100
-
struct fsl_xhci {
struct xhci_hccr *hcd;
struct dwc3 *dwc3_reg;
--
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[U-Boot] [PATCH 1/2] drivers:usb: Add device-tree fixup to identify socs having dual phy
Identify soc(s) having dual phy so as to add utmi_dual as phy_mode
for all these socs. This is required for supporting deel-sleep feature
in linux for usb driver
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
drivers/usb/host/ehci-fsl.c | 7 ++-
include/fsl_usb.h | 32
2 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 5d4288d..ed83eb4 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -259,7 +259,7 @@ static int fdt_fixup_usb_erratum(void *blob, const char
*prop_erratum,
void fdt_fixup_dr_usb(void *blob, bd_t *bd)
{
static const char * const modes[] = { host, peripheral, otg };
- static const char * const phys[] = { ulpi, utmi };
+ static const char * const phys[] = { ulpi, utmi, utmi_dual };
int usb_erratum_a006261_off = -1;
int usb_erratum_a007075_off = -1;
int usb_erratum_a007792_off = -1;
@@ -303,6 +303,9 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
dr_phy_type = phys[phy_idx];
}
+ if (has_dual_phy())
+ dr_phy_type = phys[2];
+
usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
dr_mode_type, NULL,
usb_mode_off);
@@ -325,6 +328,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
if (usb_erratum_a006261_off 0)
return;
}
+
if (has_erratum_a007075()) {
usb_erratum_a007075_off = fdt_fixup_usb_erratum
(blob,
@@ -333,6 +337,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
if (usb_erratum_a007075_off 0)
return;
}
+
if (has_erratum_a007792()) {
usb_erratum_a007792_off = fdt_fixup_usb_erratum
(blob,
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index d251f5d..d24ffa7 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -87,6 +87,33 @@ struct ccsr_usb_phy {
/* USB Erratum Checking code */
#ifdef CONFIG_PPC
+static inline bool has_dual_phy(void)
+{
+ u32 svr = get_svr();
+ u32 soc = SVR_SOC_VER(svr);
+
+ switch (soc) {
+ case SVR_T1023:
+ case SVR_T1024:
+ case SVR_T1013:
+ case SVR_T1014:
+ return IS_SVR_REV(svr, 1, 0);
+ case SVR_T1040:
+ case SVR_T1042:
+ case SVR_T1020:
+ case SVR_T1022:
+ case SVR_T2080:
+ case SVR_T2081:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+ case SVR_T4240:
+ case SVR_T4160:
+ case SVR_T4080:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+ }
+
+ return false;
+}
+
static inline bool has_erratum_a006261(void)
{
u32 svr = get_svr();
@@ -165,6 +192,11 @@ static inline bool has_erratum_a007792(void)
}
#else
+static inline bool has_dual_phy(void)
+{
+ return false;
+}
+
static inline bool has_erratum_a006261(void)
{
return false;
--
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[U-Boot] [PATCH 2/2] drivers:usb:fsl: Add affected SOCs for USB Erratum A007792
Add following affected SOCs and their personalities for USB Erratum A007792 : T1040 Rev 1.1 T1024 Rev 1.0 Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- include/fsl_usb.h | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/fsl_usb.h b/include/fsl_usb.h index d24ffa7..92751dd 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -182,8 +182,13 @@ static inline bool has_erratum_a007792(void) case SVR_T4240: case SVR_T4160: return IS_SVR_REV(svr, 2, 0); - case SVR_T1040: + case SVR_T1024: + case SVR_T1023: return IS_SVR_REV(svr, 1, 0); + case SVR_T1040: + case SVR_T1042: + case SVR_T1020: + case SVR_T1022: case SVR_T2080: case SVR_T2081: return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); -- 1.7.11.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] configs: LS1012XA: Modify CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS for LS102XA
Change CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS value to 2 for LS102XAQDS and LS102XATWR. The XHCI controller has 2 ports; one for 2.0 and the other for 3.0 USB transactions Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- Depends on patch https://patchwork.ozlabs.org/patch/401448/ and https://patchwork.ozlabs.org/patch/401449/ include/configs/ls1021aqds.h | 2 +- include/configs/ls1021atwr.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 1389b00..3cd4a9f 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -298,7 +298,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_MAX_CONTROLLER_COUNT1 -#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #endif #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 2b23cc9..4098214 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -46,7 +46,7 @@ #define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_MAX_CONTROLLER_COUNT1 -#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #endif #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) -- 1.7.11.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] drivers: usb: fsl: Workaround for Erratum A004477
Add a delay of 1 microsecond before issuing soft reset to the
controller to let ongoing ULPI transaction complete.
This prevents corruption of ULPI Function Control Register which
eventually prevents phy clock from entering to low power mode
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Depends on patch https://patchwork.ozlabs.org/patch/404879/
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4
arch/powerpc/include/asm/config_mpc85xx.h | 6 ++
drivers/usb/host/ehci-fsl.c | 10 ++
include/fsl_usb.h | 29 +
4 files changed, 49 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index fe3eb06..bc59352 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -298,6 +298,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
if (has_erratum_a007798())
puts(Work-around for Erratum A007798 enabled\n);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004477
+ if (has_erratum_a004477())
+ puts(Work-around for Erratum A004477 enabled\n);
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
if ((SVR_SOC_VER(svr) == SVR_8548 IS_SVR_REV(svr, 3, 1)) ||
(SVR_REV(svr) = CONFIG_SYS_FSL_A004447_SVR_REV))
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 7860b40..fe9e9c1 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -161,6 +161,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_ERRATUM_A006261
+#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
#define CONFIG_ESDHC_HC_BLK_ADDR
@@ -292,6 +293,7 @@
#define CONFIG_FSL_SATA_ERRATUM_A001
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A004477
#elif defined(CONFIG_P1023)
#define CONFIG_MAX_CPUS2
@@ -372,6 +374,7 @@
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_USB_MAX_CONTROLLER_COUNT1
#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
@@ -589,6 +592,7 @@
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_BSC9132)
@@ -613,6 +617,7 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT fsl,qoriq-pcie-v2.2
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_A005434
+#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#define CONFIG_ESDHC_HC_BLK_ADDR
@@ -712,6 +717,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A006475
#define CONFIG_SYS_FSL_ERRATUM_A006384
#define CONFIG_SYS_FSL_ERRATUM_A007212
+#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe00
#define CONFIG_SYS_FSL_SFP_VER_3_0
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 5d4288d..41ff1a7 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -138,6 +138,16 @@ int ehci_hcd_init(int index, enum usb_init_type init,
if (has_erratum_a007798())
set_txfifothresh(ehci, TXFIFOTHRESH);
+ if (has_erratum_a004477()) {
+ /*
+* When reset is issued while any ULPI transaction is ongoing
+* then it may result to corruption of ULPI Function Control
+* Register which eventually causes phy clock to enter low
+* power mode which stops the clock. Thus delay is required
+* before reset to let ongoing ULPI transaction complete.
+*/
+ udelay(1);
+ }
return 0;
}
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index d251f5d..88d8a8b 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -164,6 +164,30 @@ static inline bool has_erratum_a007792(void)
return false;
}
+static inline bool has_erratum_a004477(void)
+{
+ u32 svr = get_svr();
+ u32 soc = SVR_SOC_VER(svr);
+
+ switch (soc) {
+ case SVR_P1010:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+ case SVR_P1022:
+ case SVR_9131:
+ case SVR_9132:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+ case SVR_P2020:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0) ||
+ IS_SVR_REV(svr, 2, 1);
+ case SVR_B4860:
+ case SVR_B4420:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+ case
[U-Boot] [PATCH] drivers: usb: fsl: Check USB Erratum A007792 applicability
Check USB Erratum A007792 applicability. If applicable, add
corresponding property in the device tree via device tree fixup
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Depends on http://patchwork.ozlabs.org/patch/400407/
drivers/usb/host/ehci-fsl.c | 9 +
include/fsl_usb.h | 23 +++
2 files changed, 32 insertions(+)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 61cd168..5d4288d 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -262,6 +262,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
static const char * const phys[] = { ulpi, utmi };
int usb_erratum_a006261_off = -1;
int usb_erratum_a007075_off = -1;
+ int usb_erratum_a007792_off = -1;
int usb_mode_off = -1;
int usb_phy_off = -1;
char str[5];
@@ -332,6 +333,14 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
if (usb_erratum_a007075_off 0)
return;
}
+ if (has_erratum_a007792()) {
+ usb_erratum_a007792_off = fdt_fixup_usb_erratum
+ (blob,
+ fsl,usb-erratum-a007792,
+ usb_erratum_a007792_off);
+ if (usb_erratum_a007792_off 0)
+ return;
+ }
}
}
#endif
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index e4902aa..d251f5d 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -145,6 +145,25 @@ static inline bool has_erratum_a007798(void)
return SVR_SOC_VER(get_svr()) == SVR_T4240
IS_SVR_REV(get_svr(), 2, 0);
}
+
+static inline bool has_erratum_a007792(void)
+{
+ u32 svr = get_svr();
+ u32 soc = SVR_SOC_VER(svr);
+
+ switch (soc) {
+ case SVR_T4240:
+ case SVR_T4160:
+ return IS_SVR_REV(svr, 2, 0);
+ case SVR_T1040:
+ return IS_SVR_REV(svr, 1, 0);
+ case SVR_T2080:
+ case SVR_T2081:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+ }
+ return false;
+}
+
#else
static inline bool has_erratum_a006261(void)
{
@@ -161,5 +180,9 @@ static inline bool has_erratum_a007798(void)
return false;
}
+static inline bool has_erratum_a007792(void)
+{
+ return false;
+}
#endif
#endif /*_ASM_FSL_USB_H_ */
--
1.7.11.7
___
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[U-Boot] [PATCH] config: MPC837X : Add complete USB EHCI support
Add complete USB EHCI support for MPC837XEMDS and MPC837XERDB Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- include/configs/MPC837XEMDS.h | 5 + include/configs/MPC837XERDB.h | 5 + 2 files changed, 10 insertions(+) diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 695e47b..832c10f 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -387,6 +387,11 @@ extern int board_pci_host_broken(void); #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_PCI_PNP /* do pci plug-and-play */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 1d1f4c0..8ed0f7c 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -685,6 +685,11 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_HAS_FSL_DR_USB +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_NETDEV eth1 -- 1.7.11.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3][v2] drivers: usb: Make usb device-tree fixup code architecture independent
move usb device tree fixup code from arch/powerpc/ to drivers/usb/
so that it works independent of architecture it is running on
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Changes for v2 :
- Fixed compilation error for Platforms with
CONFIG_USB_MAX_CONTROLLER_COUNT not defined
- Depends on https://patchwork.ozlabs.org/patch/401063/
arch/powerpc/cpu/mpc8xxx/fdt.c | 104 -
drivers/usb/host/ehci-fsl.c| 113 +
2 files changed, 113 insertions(+), 104 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 4cec5e1..65fde3f 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -73,110 +73,6 @@ void ft_fixup_num_cores(void *blob) {
}
#endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
- const char *phy_type, int start_offset)
-{
- const char *compat_dr = fsl-usb2-dr;
- const char *compat_mph = fsl-usb2-mph;
- const char *prop_mode = dr_mode;
- const char *prop_type = phy_type;
- const char *node_type = NULL;
- int node_offset;
- int err;
-
- node_offset = fdt_node_offset_by_compatible(blob,
- start_offset, compat_mph);
- if (node_offset 0) {
- node_offset = fdt_node_offset_by_compatible(blob,
- start_offset, compat_dr);
- if (node_offset 0) {
- printf(WARNING: could not find compatible
-node %s or %s: %s.\n, compat_mph,
- compat_dr, fdt_strerror(node_offset));
- return -1;
- } else
- node_type = compat_dr;
- } else
- node_type = compat_mph;
-
- if (mode) {
- err = fdt_setprop(blob, node_offset, prop_mode, mode,
- strlen(mode) + 1);
- if (err 0)
- printf(WARNING: could not set %s for %s: %s.\n,
- prop_mode, node_type, fdt_strerror(err));
- }
-
- if (phy_type) {
- err = fdt_setprop(blob, node_offset, prop_type, phy_type,
- strlen(phy_type) + 1);
- if (err 0)
- printf(WARNING: could not set %s for %s: %s.\n,
- prop_type, node_type, fdt_strerror(err));
- }
-
- return node_offset;
-}
-
-void fdt_fixup_dr_usb(void *blob, bd_t *bd)
-{
- const char *modes[] = { host, peripheral, otg };
- const char *phys[] = { ulpi, utmi };
- int usb_mode_off = -1;
- int usb_phy_off = -1;
- char str[5];
- int i, j;
-
- for (i = 1; i = CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
- const char *dr_mode_type = NULL;
- const char *dr_phy_type = NULL;
- int mode_idx = -1, phy_idx = -1;
- snprintf(str, 5, %s%d, usb, i);
- if (hwconfig(str)) {
- for (j = 0; j ARRAY_SIZE(modes); j++) {
- if (hwconfig_subarg_cmp(str, dr_mode,
- modes[j])) {
- mode_idx = j;
- break;
- }
- }
-
- for (j = 0; j ARRAY_SIZE(phys); j++) {
- if (hwconfig_subarg_cmp(str, phy_type,
- phys[j])) {
- phy_idx = j;
- break;
- }
- }
-
- if (mode_idx 0 phy_idx 0) {
- printf(WARNING: invalid phy or mode\n);
- return;
- }
-
- if (mode_idx -1)
- dr_mode_type = modes[mode_idx];
-
- if (phy_idx -1)
- dr_phy_type = phys[phy_idx];
- }
-
- usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
- dr_mode_type, NULL, usb_mode_off);
-
- if (usb_mode_off 0)
- return;
-
- usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
- NULL, dr_phy_type, usb_phy_off);
-
- if (usb_phy_off 0)
- return;
- }
-}
-#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
-
/*
* update crypto node
[U-Boot] [PATCH 1/2] drivers: usb: fsl: Define USB configs for LS102XA
Define USB configs for LS1021XA such as CONFIG_SYS_FSL_USB1_ADDR, CONFIG_USB_MAX_CONTROLLER_COUNT Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- arch/arm/include/asm/arch-ls102xa/config.h | 4 include/usb/ehci-fsl.h | 3 +++ 2 files changed, 7 insertions(+) diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index a500b5b..cbf41da 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -25,7 +25,10 @@ #define CONFIG_SYS_NS16550_COM1(CONFIG_SYS_IMMR + 0x011c0500) #define CONFIG_SYS_NS16550_COM2(CONFIG_SYS_IMMR + 0x011d0500) #define CONFIG_SYS_DCU_ADDR(CONFIG_SYS_IMMR + 0x01ce) +#define CONFIG_SYS_LS102XA_USB1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET) +#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x0760 #define CONFIG_SYS_TSEC1_OFFSET0x01d1 #define CONFIG_SYS_TSEC2_OFFSET0x01d5 #define CONFIG_SYS_TSEC3_OFFSET0x01d9 @@ -76,6 +79,7 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT1 #else #error SoC not defined #endif diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h index dd77ad6..897018b 100644 --- a/include/usb/ehci-fsl.h +++ b/include/usb/ehci-fsl.h @@ -163,6 +163,9 @@ #elif defined(CONFIG_MPC512X) #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR 0 +#elif defined(CONFIG_LS102XA) +#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR +#define CONFIG_SYS_FSL_USB2_ADDR0 #endif /* -- 1.7.11.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] ls1: config: Enable USB EHCI Host on LS1021AQDS
Enable USB EHCI Host on LS1021AQDS Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- include/configs/ls1021aqds.h | 17 + 1 file changed, 17 insertions(+) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index bb47813..fd43a3e 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -273,6 +273,23 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_GENERIC_MMC /* + * USB + */ +#define CONFIG_HAS_FSL_DR_USB + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#endif +#endif + +/* * eTSEC */ #define CONFIG_TSEC_ENET -- 1.7.11.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] drivers : usb: fsl: Implement usb Erratum A007798 workaround
Set TXFIFOTHRESH to adjust ddr pipeline delay for successful large
usb writes
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Depends on patch https://patchwork.ozlabs.org/patch/394797/
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4
arch/powerpc/include/asm/config_mpc85xx.h | 1 +
drivers/usb/host/ehci-fsl.c | 3 +--
include/fsl_usb.h | 11 +++
4 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 349ce52..fe3eb06 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -294,6 +294,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
if (has_erratum_a007075())
puts(Work-around for Erratum A007075 enabled\n);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007798
+ if (has_erratum_a007798())
+ puts(Work-around for Erratum A007798 enabled\n);
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
if ((SVR_SOC_VER(svr) == SVR_8548 IS_SVR_REV(svr, 3, 1)) ||
(SVR_REV(svr) = CONFIG_SYS_FSL_A004447_SVR_REV))
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 712f2ef..486bc53 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -677,6 +677,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A006379
#define CONFIG_SYS_FSL_ERRATUM_A007186
#define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A007798
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe00
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_PCI_VER_3_X
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index c125e2c..7101202 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -131,8 +131,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
in_le32(ehci-usbmode);
- if (SVR_SOC_VER(get_svr()) == SVR_T4240
- IS_SVR_REV(get_svr(), 2, 0))
+ if (has_erratum_a007798())
set_txfifothresh(ehci, TXFIFOTHRESH);
return 0;
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index 66f8934..e4902aa 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -139,6 +139,12 @@ static inline bool has_erratum_a007075(void)
}
return false;
}
+
+static inline bool has_erratum_a007798(void)
+{
+ return SVR_SOC_VER(get_svr()) == SVR_T4240
+ IS_SVR_REV(get_svr(), 2, 0);
+}
#else
static inline bool has_erratum_a006261(void)
{
@@ -150,5 +156,10 @@ static inline bool has_erratum_a007075(void)
return false;
}
+static inline bool has_erratum_a007798(void)
+{
+ return false;
+}
+
#endif
#endif /*_ASM_FSL_USB_H_ */
--
1.7.11.7
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] drivers: usb: Make usb device-tree fixup code architecture independent
move usb device tree fixup code from arch/powerpc/ to drivers/usb/
so that it works independent of architecture it is running on
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/fdt.c | 104 ---
drivers/usb/host/ehci-fsl.c| 109 +
2 files changed, 109 insertions(+), 104 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 4cec5e1..65fde3f 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -73,110 +73,6 @@ void ft_fixup_num_cores(void *blob) {
}
#endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
- const char *phy_type, int start_offset)
-{
- const char *compat_dr = fsl-usb2-dr;
- const char *compat_mph = fsl-usb2-mph;
- const char *prop_mode = dr_mode;
- const char *prop_type = phy_type;
- const char *node_type = NULL;
- int node_offset;
- int err;
-
- node_offset = fdt_node_offset_by_compatible(blob,
- start_offset, compat_mph);
- if (node_offset 0) {
- node_offset = fdt_node_offset_by_compatible(blob,
- start_offset, compat_dr);
- if (node_offset 0) {
- printf(WARNING: could not find compatible
-node %s or %s: %s.\n, compat_mph,
- compat_dr, fdt_strerror(node_offset));
- return -1;
- } else
- node_type = compat_dr;
- } else
- node_type = compat_mph;
-
- if (mode) {
- err = fdt_setprop(blob, node_offset, prop_mode, mode,
- strlen(mode) + 1);
- if (err 0)
- printf(WARNING: could not set %s for %s: %s.\n,
- prop_mode, node_type, fdt_strerror(err));
- }
-
- if (phy_type) {
- err = fdt_setprop(blob, node_offset, prop_type, phy_type,
- strlen(phy_type) + 1);
- if (err 0)
- printf(WARNING: could not set %s for %s: %s.\n,
- prop_type, node_type, fdt_strerror(err));
- }
-
- return node_offset;
-}
-
-void fdt_fixup_dr_usb(void *blob, bd_t *bd)
-{
- const char *modes[] = { host, peripheral, otg };
- const char *phys[] = { ulpi, utmi };
- int usb_mode_off = -1;
- int usb_phy_off = -1;
- char str[5];
- int i, j;
-
- for (i = 1; i = CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
- const char *dr_mode_type = NULL;
- const char *dr_phy_type = NULL;
- int mode_idx = -1, phy_idx = -1;
- snprintf(str, 5, %s%d, usb, i);
- if (hwconfig(str)) {
- for (j = 0; j ARRAY_SIZE(modes); j++) {
- if (hwconfig_subarg_cmp(str, dr_mode,
- modes[j])) {
- mode_idx = j;
- break;
- }
- }
-
- for (j = 0; j ARRAY_SIZE(phys); j++) {
- if (hwconfig_subarg_cmp(str, phy_type,
- phys[j])) {
- phy_idx = j;
- break;
- }
- }
-
- if (mode_idx 0 phy_idx 0) {
- printf(WARNING: invalid phy or mode\n);
- return;
- }
-
- if (mode_idx -1)
- dr_mode_type = modes[mode_idx];
-
- if (phy_idx -1)
- dr_phy_type = phys[phy_idx];
- }
-
- usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
- dr_mode_type, NULL, usb_mode_off);
-
- if (usb_mode_off 0)
- return;
-
- usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
- NULL, dr_phy_type, usb_phy_off);
-
- if (usb_phy_off 0)
- return;
- }
-}
-#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
-
/*
* update crypto node properties to a specified revision of the SEC
* called with sec_rev == 0 if not on an E processor
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index d5361d7..295250a
[U-Boot] [PATCH 1/3] drivers: usb: fsl: Move USB Errata checking code
Move USB Errata checking code from arch/powerpc to architecture independent
file fsl_usb.h so that errata(s) become independent of the architecture.
For each erratum checking function for PPC arch, define a nop function for
non PPC arch for successful compilation in either case
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 1 +
arch/powerpc/include/asm/fsl_errata.h | 55 -
drivers/usb/host/ehci-fsl.c | 2 +-
include/fsl_usb.h | 66 +++
4 files changed, 68 insertions(+), 56 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 3a04a89..349ce52 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -9,6 +9,7 @@
#include linux/compiler.h
#include asm/fsl_errata.h
#include asm/processor.h
+#include fsl_usb.h
#include fsl_corenet_serdes.h
#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
diff --git a/arch/powerpc/include/asm/fsl_errata.h
b/arch/powerpc/include/asm/fsl_errata.h
index 64da4bb..b9e2fb0 100644
--- a/arch/powerpc/include/asm/fsl_errata.h
+++ b/arch/powerpc/include/asm/fsl_errata.h
@@ -26,59 +26,4 @@ static inline bool has_erratum_a006379(void)
return false;
}
#endif
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
-static inline bool has_erratum_a006261(void)
-{
- u32 svr = get_svr();
- u32 soc = SVR_SOC_VER(svr);
-
- switch (soc) {
- case SVR_P1010:
- return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
- case SVR_P2041:
- case SVR_P2040:
- return IS_SVR_REV(svr, 1, 0) ||
- IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
- case SVR_P3041:
- return IS_SVR_REV(svr, 1, 0) ||
- IS_SVR_REV(svr, 1, 1) ||
- IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
- case SVR_P5010:
- case SVR_P5020:
- case SVR_P5021:
- return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
- case SVR_T4240:
- case SVR_T4160:
- case SVR_T4080:
- return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
- case SVR_T1040:
- return IS_SVR_REV(svr, 1, 0);
- case SVR_T2080:
- case SVR_T2081:
- return IS_SVR_REV(svr, 1, 0);
- case SVR_P5040:
- return IS_SVR_REV(svr, 1, 0);
- }
-
- return false;
-}
-#endif
-
-static inline bool has_erratum_a007075(void)
-{
- u32 svr = get_svr();
- u32 soc = SVR_SOC_VER(svr);
-
- switch (soc) {
- case SVR_B4860:
- case SVR_B4420:
- return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
- case SVR_P1010:
- return IS_SVR_REV(svr, 1, 0);
- case SVR_P4080:
- return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
- }
- return false;
-}
#endif
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 45062e6..d5361d7 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -14,7 +14,7 @@
#include asm/io.h
#include usb/ehci-fsl.h
#include hwconfig.h
-#include asm/fsl_errata.h
+#include fsl_usb.h
#include ehci.h
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index 1a6c9c1..66f8934 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -85,4 +85,70 @@ struct ccsr_usb_phy {
#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
#endif
+/* USB Erratum Checking code */
+#ifdef CONFIG_PPC
+static inline bool has_erratum_a006261(void)
+{
+ u32 svr = get_svr();
+ u32 soc = SVR_SOC_VER(svr);
+
+ switch (soc) {
+ case SVR_P1010:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+ case SVR_P2041:
+ case SVR_P2040:
+ return IS_SVR_REV(svr, 1, 0) ||
+ IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
+ case SVR_P3041:
+ return IS_SVR_REV(svr, 1, 0) ||
+ IS_SVR_REV(svr, 1, 1) ||
+ IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
+ case SVR_P5010:
+ case SVR_P5020:
+ case SVR_P5021:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+ case SVR_T4240:
+ case SVR_T4160:
+ case SVR_T4080:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+ case SVR_T1040:
+ return IS_SVR_REV(svr, 1, 0);
+ case SVR_T2080:
+ case SVR_T2081:
+ return IS_SVR_REV(svr, 1, 0);
+ case SVR_P5040:
+ return IS_SVR_REV(svr, 1, 0);
+ }
+
+ return false;
+}
+
+static inline bool has_erratum_a007075(void)
+{
+ u32 svr = get_svr();
+ u32 soc = SVR_SOC_VER(svr);
+
+ switch (soc) {
+ case SVR_B4860:
+ case SVR_B4420:
+ return IS_SVR_REV(svr
[U-Boot] [PATCH 3/3] drivers: usb: fsl: Add USB device-tree errata framework
Add a new framework for fsl usb erratum handling to standardize
erratum checking only inside Uboot. Information to kernel is passed
via a boolean property corresponding to erratum, hence eliminating
need for code duplication inside kernel
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
drivers/usb/host/ehci-fsl.c | 64 +
1 file changed, 64 insertions(+)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 295250a..c125e2c 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -208,10 +208,57 @@ static int fdt_fixup_usb_mode_phy_type(void *blob, const
char *mode,
return node_offset;
}
+static const char *fdt_usb_get_node_type(void *blob, int start_offset,
+int *node_offset)
+{
+ const char *compat_dr = fsl-usb2-dr;
+ const char *compat_mph = fsl-usb2-mph;
+ const char *node_type = NULL;
+
+ *node_offset = fdt_node_offset_by_compatible(blob, start_offset,
+compat_mph);
+ if (*node_offset 0) {
+ *node_offset = fdt_node_offset_by_compatible(blob,
+start_offset,
+compat_dr);
+ if (*node_offset 0) {
+ printf(ERROR: could not find compatible node: %s\n,
+ fdt_strerror(*node_offset));
+ } else {
+ node_type = compat_dr;
+ }
+ } else {
+ node_type = compat_mph;
+ }
+
+ return node_type;
+}
+
+static int fdt_fixup_usb_erratum(void *blob, const char *prop_erratum,
+int start_offset)
+{
+ int node_offset, err;
+ const char *node_type = NULL;
+
+ node_type = fdt_usb_get_node_type(blob, start_offset, node_offset);
+ if (!node_type)
+ return -1;
+
+ err = fdt_setprop(blob, node_offset, prop_erratum, NULL, 0);
+ if (err 0) {
+ printf(ERROR: could not set %s for %s: %s.\n,
+ prop_erratum, node_type, fdt_strerror(err));
+ }
+
+ return node_offset;
+}
+
void fdt_fixup_dr_usb(void *blob, bd_t *bd)
{
static const char * const modes[] = { host, peripheral, otg };
static const char * const phys[] = { ulpi, utmi };
+ int usb_erratum_a006261_off = -1;
+ int usb_erratum_a007075_off = -1;
int usb_mode_off = -1;
int usb_phy_off = -1;
char str[5];
@@ -265,6 +312,23 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
if (usb_phy_off 0)
return;
+
+ if (has_erratum_a006261()) {
+ usb_erratum_a006261_off = fdt_fixup_usb_erratum
+ (blob,
+ fsl,usb-erratum-a006261,
+ usb_erratum_a006261_off);
+ if (usb_erratum_a006261_off 0)
+ return;
+ }
+ if (has_erratum_a007075()) {
+ usb_erratum_a007075_off = fdt_fixup_usb_erratum
+ (blob,
+ fsl,usb-erratum-a007075,
+ usb_erratum_a007075_off);
+ if (usb_erratum_a007075_off 0)
+ return;
+ }
}
}
#endif
--
1.7.11.7
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[U-Boot] [PATCH][v2] drivers/usb : Define usb control register mask for w1c bits
Define and use CONTROL_REGISTER_W1C_MASK to make sure that
w1c bits of usb control register do not get reset while
writing any other bit
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Changes for v2:
- Using clrsetbits_be32() instead of new API
drivers/usb/host/ehci-fsl.c | 15 ++-
include/usb/ehci-fsl.h | 2 ++
2 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 6cb4d98..45062e6 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -104,15 +104,20 @@ int ehci_hcd_init(int index, enum usb_init_type init,
if (!strncmp(phy_type, utmi, 4)) {
#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
- setbits_be32(ehci-control, PHY_CLK_SEL_UTMI);
- setbits_be32(ehci-control, UTMI_PHY_EN);
+ clrsetbits_be32(ehci-control, CONTROL_REGISTER_W1C_MASK,
+ PHY_CLK_SEL_UTMI);
+ clrsetbits_be32(ehci-control, CONTROL_REGISTER_W1C_MASK,
+ UTMI_PHY_EN);
udelay(1000); /* delay required for PHY Clk to appear */
#endif
out_le32((*hcor)-or_portsc[0], PORT_PTS_UTMI);
- setbits_be32(ehci-control, USB_EN);
+ clrsetbits_be32(ehci-control, CONTROL_REGISTER_W1C_MASK,
+ USB_EN);
} else {
- setbits_be32(ehci-control, PHY_CLK_SEL_ULPI);
- clrsetbits_be32(ehci-control, UTMI_PHY_EN, USB_EN);
+ clrsetbits_be32(ehci-control, CONTROL_REGISTER_W1C_MASK,
+ PHY_CLK_SEL_ULPI);
+ clrsetbits_be32(ehci-control, UTMI_PHY_EN |
+ CONTROL_REGISTER_W1C_MASK, USB_EN);
udelay(1000); /* delay required for PHY Clk to appear */
if (!usb_phy_clk_valid(ehci))
return -EINVAL;
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index c9ee1d5..dd77ad6 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -11,6 +11,8 @@
#include asm/processor.h
+#define CONTROL_REGISTER_W1C_MASK 0x0002 /* W1C: PHY_CLK_VALID */
+
/* Global offsets */
#define FSL_SKIP_PCI 0x100
--
1.7.11.7
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[U-Boot] [PATCH] drivers/usb : Introduce APIs for fsl usb registers
Introduce new APIs to write fsl usb registers that have w1c bits.
Existing API framework do not take care of w1c bits
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
drivers/usb/host/ehci-fsl.c | 17 -
include/usb/ehci-fsl.h | 6 ++
2 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 6cb4d98..3be69c4 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -104,15 +104,22 @@ int ehci_hcd_init(int index, enum usb_init_type init,
if (!strncmp(phy_type, utmi, 4)) {
#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
- setbits_be32(ehci-control, PHY_CLK_SEL_UTMI);
- setbits_be32(ehci-control, UTMI_PHY_EN);
+ fsl_usb_setbits(ehci-control, PHY_CLK_SEL_UTMI,
+ CONTROL_REGISTER_W1C_MASK);
+ fsl_usb_setbits(ehci-control, UTMI_PHY_EN,
+ CONTROL_REGISTER_W1C_MASK);
udelay(1000); /* delay required for PHY Clk to appear */
#endif
out_le32((*hcor)-or_portsc[0], PORT_PTS_UTMI);
- setbits_be32(ehci-control, USB_EN);
+ fsl_usb_setbits(ehci-control, USB_EN,
+ CONTROL_REGISTER_W1C_MASK);
} else {
- setbits_be32(ehci-control, PHY_CLK_SEL_ULPI);
- clrsetbits_be32(ehci-control, UTMI_PHY_EN, USB_EN);
+ fsl_usb_setbits(ehci-control, PHY_CLK_SEL_ULPI,
+ CONTROL_REGISTER_W1C_MASK);
+ fsl_usb_clrbits(ehci-control, UTMI_PHY_EN,
+ CONTROL_REGISTER_W1C_MASK);
+ fsl_usb_setbits(ehci-control, USB_EN,
+ CONTROL_REGISTER_W1C_MASK);
udelay(1000); /* delay required for PHY Clk to appear */
if (!usb_phy_clk_valid(ehci))
return -EINVAL;
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index c9ee1d5..fb3d6b4 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -11,6 +11,12 @@
#include asm/processor.h
+#define CONTROL_REGISTER_W1C_MASK 0x0002 /* W1C: PHY_CLK_VALID */
+#define fsl_usb_setbits(_addr, _v, _mask) out_be32((_addr), \
+ ((in_be32(_addr) ~_mask) | _v))
+#define fsl_usb_clrbits(_addr, _v, _mask) out_be32((_addr), \
+ ((in_be32(_addr) ~_mask) ~_v))
+
/* Global offsets */
#define FSL_SKIP_PCI 0x100
--
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[U-Boot] [PATCH] fsl/usb: Add Differential SYSCLK config support T1040
Adds support for clock sourcing from sysclk(100MHz) for usb
on T104xRDB and T1040QDS. This requires changing reference divisor
and multiplication factor to derive usb clock from sysclk.
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Dependency on patch http://patchwork.ozlabs.org/patch/339164/
arch/powerpc/cpu/mpc85xx/cpu_init.c | 26 ++
include/fsl_usb.h | 5 +
2 files changed, 31 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 81aeadd..0e11a0b 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -36,6 +36,29 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+/*
+ * For deriving usb clock from 100MHz sysclk, reference divisor is set
+ * to a value of 5, which gives an intermediate value 20(100/5). The
+ * multiplication factor integer is set to 24, which when multiplied to
+ * above intermediate value provides clock for usb ip.
+ */
+void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
+{
+ sys_info_t sysinfo;
+
+ get_sys_info(sysinfo);
+ if (sysinfo.diff_sysclk == 1) {
+ clrbits_be32(usb_phy-pllprg[1],
+CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
+ setbits_be32(usb_phy-pllprg[1],
+CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
+CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
+CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
+ }
+}
+#endif
+
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
{
@@ -716,6 +739,9 @@ skip_l2:
CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+ usb_single_source_clk_configure(usb_phy);
+#endif
setbits_be32(usb_phy-port1.ctrl,
CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
setbits_be32(usb_phy-port1.drvvbuscfg,
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index 8b63cdd..1a6c9c1 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -48,6 +48,11 @@ struct ccsr_usb_phy {
#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 0)
#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 1)
#define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 13)
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 4)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 16)
+#define CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 20)
+#endif
#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 4)
#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 16)
#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 21)
--
1.7.11.7
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[U-Boot] [PATCH][v2] powerpc/mpc85xx: Add Differential SYSCLK config support T1040
Adds support for clock sourcing from sysclk(100MHz) for usb
on T104xRDB and T1040QDS. This requires changing reference divisor
and multiplication factor to derive usb clock from sysclk.
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Dependency on patch http://patchwork.ozlabs.org/patch/339164/
Changes for v2:
- Changed patch heading
arch/powerpc/cpu/mpc85xx/cpu_init.c | 26 ++
include/fsl_usb.h | 5 +
2 files changed, 31 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 81aeadd..0e11a0b 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -36,6 +36,29 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+/*
+ * For deriving usb clock from 100MHz sysclk, reference divisor is set
+ * to a value of 5, which gives an intermediate value 20(100/5). The
+ * multiplication factor integer is set to 24, which when multiplied to
+ * above intermediate value provides clock for usb ip.
+ */
+void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
+{
+ sys_info_t sysinfo;
+
+ get_sys_info(sysinfo);
+ if (sysinfo.diff_sysclk == 1) {
+ clrbits_be32(usb_phy-pllprg[1],
+CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
+ setbits_be32(usb_phy-pllprg[1],
+CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
+CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
+CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
+ }
+}
+#endif
+
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
{
@@ -716,6 +739,9 @@ skip_l2:
CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+ usb_single_source_clk_configure(usb_phy);
+#endif
setbits_be32(usb_phy-port1.ctrl,
CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
setbits_be32(usb_phy-port1.drvvbuscfg,
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index 8b63cdd..1a6c9c1 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -48,6 +48,11 @@ struct ccsr_usb_phy {
#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 0)
#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 1)
#define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 13)
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 4)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 16)
+#define CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 20)
+#endif
#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 4)
#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 16)
#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 21)
--
1.7.11.7
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[U-Boot] [PATCH] fsl/usb: Increase TXFIFOTHRESH value for usb write in T4 Rev 2.0
Increase TXFIFOTHRES field value in TXFILLTUNING register of usb for T4 Rev 2.0.
This decreases data burst rate with which data packets are posted from the TX
latency FIFO to compensate for latencies in DDR pipeline during DMA.
This avoids Tx buffer underruns and leads to successful usb writes
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
drivers/usb/host/ehci-fsl.c | 20
include/usb/ehci-fsl.h | 7 +++
2 files changed, 27 insertions(+)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 1ca7cf5..991b43b 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -17,6 +17,8 @@
#include ehci.h
+static void set_txfifothresh(struct usb_ehci *, u32);
+
/* Check USB PHY clock valid */
static int usb_phy_clk_valid(struct usb_ehci *ehci)
{
@@ -109,6 +111,10 @@ int ehci_hcd_init(int index, enum usb_init_type init,
in_le32(ehci-usbmode);
+ if (SVR_SOC_VER(get_svr()) == SVR_T4240
+ IS_SVR_REV(get_svr(), 2, 0))
+ set_txfifothresh(ehci, TXFIFOTHRESH);
+
return 0;
}
@@ -120,3 +126,17 @@ int ehci_hcd_stop(int index)
{
return 0;
}
+
+/*
+ * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
+ * to counter DDR latencies in writing data into Tx buffer.
+ * This prevents Tx buffer from getting underrun
+ */
+static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
+{
+ u32 cmd;
+ cmd = ehci_readl(ehci-txfilltuning);
+ cmd = ~TXFIFO_THRESH_MASK;
+ cmd |= TXFIFO_THRESH(txfifo_thresh);
+ ehci_writel(ehci-txfilltuning, cmd);
+}
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 734305b..c9ee1d5 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -164,6 +164,13 @@
#endif
/*
+ * Increasing TX FIFO threshold value from 2 to 4 decreases
+ * data burst rate with which data packets are posted from the TX
+ * latency FIFO to compensate for latencies in DDR pipeline during DMA
+ */
+#define TXFIFOTHRESH 4
+
+/*
* USB Registers
*/
struct usb_ehci {
--
1.7.11.7
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[U-Boot] [PATCH] fsl/usb: Workaround for USB erratum-A007075
Put a delay of 5 millisecond after reset so that ULPI phy
gets enough time to come out of reset. Erratum A007075 applies
to following SOCs and their variants, if any
P1010 rev 1.0
B4860 rev 1.0, 2.0
P4080 rev 2.0, 3.0
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4
arch/powerpc/include/asm/config_mpc85xx.h | 3 +++
arch/powerpc/include/asm/fsl_errata.h | 16
drivers/usb/host/ehci-fsl.c | 9 +
4 files changed, 32 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 7693899..c23707b 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -260,6 +260,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
puts(Work-around for Erratum A005125 enabled\n);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007075
+ if (has_erratum_a007075())
+ puts(Work-around for Erratum A007075 enabled\n);
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
if ((SVR_SOC_VER(svr) == SVR_8548 IS_SVR_REV(svr, 3, 1)) ||
(SVR_REV(svr) = CONFIG_SYS_FSL_A004447_SVR_REV))
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 56587ae..9d41d3b 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -154,6 +154,7 @@
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
#define CONFIG_ESDHC_HC_BLK_ADDR
@@ -473,6 +474,7 @@
#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
#define CONFIG_SYS_FSL_ERRATUM_A005812
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
@@ -662,6 +664,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_FSL_ERRATUM_A006379
#define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe00
#ifdef CONFIG_PPC_B4860
diff --git a/arch/powerpc/include/asm/fsl_errata.h
b/arch/powerpc/include/asm/fsl_errata.h
index a590919..5599680 100644
--- a/arch/powerpc/include/asm/fsl_errata.h
+++ b/arch/powerpc/include/asm/fsl_errata.h
@@ -26,4 +26,20 @@ static inline bool has_erratum_a006379(void)
}
#endif
+static inline bool has_erratum_a007075(void)
+{
+ u32 svr = get_svr();
+ u32 soc = SVR_SOC_VER(svr);
+
+ switch (soc) {
+ case SVR_B4860:
+ case SVR_B4420:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+ case SVR_P1010:
+ return IS_SVR_REV(svr, 1, 0);
+ case SVR_P4080:
+ return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
+ }
+ return false;
+}
#endif
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 45e5d6a..afd61f1 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -14,6 +14,7 @@
#include asm/io.h
#include usb/ehci-fsl.h
#include hwconfig.h
+#include asm/fsl_errata.h
#include ehci.h
@@ -46,6 +47,14 @@ int ehci_hcd_init(int index, enum usb_init_type init,
usb_phy[0] = '\0';
#endif
+ if (has_erratum_a007075())
+ /*
+* A 5ms delay is needed after applying soft-reset to the
+* controller to let external ULPI phy come out of reset.
+* This delay needs to be added before re-initializing
+* the controller after soft-resetting completes
+*/
+ mdelay(5);
switch (index) {
case 0:
--
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[U-Boot] [PATCH] fsl/usb: fix phy_type checking
Strcmp should not be used to check the argument of phy_type which maybe parsed
by hwconfig_subarg. Hwconfig_subarg returns part of hwconfig starting from the
argument
(if it has the argument) till the end of the string. Since phy_type could be
either
'utmi' or 'ulpi', strncmp should be used along with length limited to 4
Signed-off-by: Shaohui Xie shaohui@freescale.com
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
drivers/usb/host/ehci-fsl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 45e5d6a..1ca7cf5 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -86,7 +86,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
#endif
}
- if (!strcmp(phy_type, utmi)) {
+ if (!strncmp(phy_type, utmi, 4)) {
#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
setbits_be32(ehci-control, PHY_CLK_SEL_UTMI);
setbits_be32(ehci-control, UTMI_PHY_EN);
--
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[U-Boot] [PATCH][v2] fsl/usb: Limit phy_type comparison to first four characters
Use first four characters for phy_type comparison. Strcmp() should not
be used to check the phy_type string which maybe parsed by hwconfig_subarg().
Hwconfig_subarg() returns part of hwconfig string starting from
phy_type value till the end of the string. Since phy_type could be
either utmi or ulpi, strncmp() should be used so that a comparison
of utmi;fsl_ddr:bank_intlv=auto with utmi will succeed.
Signed-off-by: Shaohui Xie shaohui@freescale.com
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Changes for v2:
- Changed patch heading
- Changed patch commit message
drivers/usb/host/ehci-fsl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 45e5d6a..1ca7cf5 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -86,7 +86,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
#endif
}
- if (!strcmp(phy_type, utmi)) {
+ if (!strncmp(phy_type, utmi, 4)) {
#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
setbits_be32(ehci-control, PHY_CLK_SEL_UTMI);
setbits_be32(ehci-control, UTMI_PHY_EN);
--
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[U-Boot] [PATCH] powerpc/usb: Enable dual phy for T1040
Define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE macro for enabling dual phy in t1040 Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- arch/powerpc/include/asm/config_mpc85xx.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index be1d9d2..32e19be 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -717,8 +717,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT fsl,qoriq-pcie-v2.4 -#define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe00 -- 1.7.11.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH][v2] powerpc/83xx: Add support for get_svr() for 83xx devices
From: Ramneek Mehresh ramneek.mehr...@freescale.com Defines get_svr() for 83xx devices Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com --- Changes for v2: - Changed patch heading arch/powerpc/cpu/mpc83xx/start.S | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index b4fafe6..7f74a50 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -120,6 +120,11 @@ disable_addr_trans: mtspr SRR1, r3 rfi + .globl get_svr +get_svr: + mfspr r3, SVR + blr + .globl get_pvr get_pvr: mfspr r3, PVR -- 1.7.11.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/83xx: fix compilation error for MPC8315ERDB
From: Ramneek Mehresh ramneek.mehr...@freescale.com Defines get_svr() for 83xx devices Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com --- arch/powerpc/cpu/mpc83xx/start.S | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index b4fafe6..7f74a50 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -120,6 +120,11 @@ disable_addr_trans: mtspr SRR1, r3 rfi + .globl get_svr +get_svr: + mfspr r3, SVR + blr + .globl get_pvr get_pvr: mfspr r3, PVR -- 1.7.11.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] fsl/usb: Fix phy type for Second USB controller
Set correct phy_type value for second USB controller.
This is required for supporting SOCs having 2 USB controllers
working simultaneously, one with UTMI phy and other with ULPI phy
Signed-off-by: Nikhil Badola b46...@freescale.com
---
drivers/usb/host/ehci-fsl.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 45e5d6a..0d19daa 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -41,11 +41,14 @@ int ehci_hcd_init(int index, enum usb_init_type init,
struct usb_ehci *ehci = NULL;
const char *phy_type = NULL;
size_t len;
+ char current_usb_controller[5];
#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
char usb_phy[5];
usb_phy[0] = '\0';
#endif
+ memset(current_usb_controller, '\0', 5);
+ snprintf(current_usb_controller, 4, usb%d, index+1);
switch (index) {
case 0:
@@ -70,8 +73,9 @@ int ehci_hcd_init(int index, enum usb_init_type init,
out_be32(ehci-snoop2, 0x8000 | SNOOP_SIZE_2GB);
/* Init phy */
- if (hwconfig_sub(usb1, phy_type))
- phy_type = hwconfig_subarg(usb1, phy_type, len);
+ if (hwconfig_sub(current_usb_controller, phy_type))
+ phy_type = hwconfig_subarg(current_usb_controller,
+ phy_type, len);
else
phy_type = getenv(usb_phy_type);
--
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