[PATCH v2 5/5] microblaze: drop remnants of manual reloc
Runtime relocation has been made the default for microblaze, so do the following cleanups: - drop all manual reloc codepaths in start.S - drop all STATIC_RELA ifdefs, as it is now enabled unconditionally in Kconfig Reviewed-by: Michal Simek Signed-off-by: Ovidiu Panait --- (no changes since v1) arch/microblaze/config.mk| 4 arch/microblaze/cpu/Makefile | 3 +-- arch/microblaze/cpu/start.S | 28 3 files changed, 1 insertion(+), 34 deletions(-) diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk index 467c5ca1b1..64c3f31319 100644 --- a/arch/microblaze/config.mk +++ b/arch/microblaze/config.mk @@ -13,10 +13,6 @@ LDFLAGS_FINAL += --gc-sections ifeq ($(CONFIG_SPL_BUILD),) PLATFORM_CPPFLAGS += -fPIC -endif - -ifeq ($(CONFIG_STATIC_RELA),y) -PLATFORM_CPPFLAGS += -fPIC LDFLAGS_u-boot += -pic endif diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile index 1c586a7de0..b8c1dcbe14 100644 --- a/arch/microblaze/cpu/Makefile +++ b/arch/microblaze/cpu/Makefile @@ -5,7 +5,6 @@ extra-y= start.o obj-y = irq.o -obj-y += interrupts.o cache.o exception.o cpuinfo.o -obj-$(CONFIG_STATIC_RELA) += relocate.o +obj-y += interrupts.o cache.o exception.o cpuinfo.o relocate.o obj-$(CONFIG_XILINX_MICROBLAZE0_PVR) += pvr.o obj-$(CONFIG_SPL_BUILD)+= spl.o diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 7079d9e170..c1e0fcda0a 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -10,16 +10,11 @@ #include #include -#if defined(CONFIG_STATIC_RELA) #define SYM_ADDR(reg, reg_add, symbol) \ mfs r20, rpc; \ addik r20, r20, _GLOBAL_OFFSET_TABLE_ + 8; \ lwi reg, r20, symbol@GOT; \ addkreg, reg reg_add; -#else -#define SYM_ADDR(reg, reg_add, symbol) \ - addireg, reg_add, symbol -#endif .text .global _start @@ -35,7 +30,6 @@ _start: addir1, r0, CONFIG_SPL_STACK #else add r1, r0, r20 -#if defined(CONFIG_STATIC_RELA) bri 1f /* Force alignment for easier ASM code below */ @@ -67,7 +61,6 @@ uboot_sym_start: brlid r15, mb_fix_rela nop -#endif #endif addir1, r1, -4 /* Decrement SP to top of memory */ @@ -310,7 +303,6 @@ relocate_code: brlid r15, __setup_exceptions nop -#if defined(CONFIG_STATIC_RELA) /* reloc_offset is current location */ SYM_ADDR(r10, r0, _start) @@ -331,27 +323,7 @@ relocate_code: add r9, r9, r5 brlid r15, mb_fix_rela nop - /* end of code which does relocation */ -#else - /* Check if GOT exist */ - addik r21, r23, _got_start - addik r22, r23, _got_end - cmpur12, r21, r22 - beqir12, 2f /* No GOT table - jump over */ - - /* Skip last 3 entries plus 1 because of loop boundary below */ - addik r22, r22, -0x10 - -/* Relocate the GOT. */ -3: lw r12, r21, r0 /* Load entry */ - addkr12, r12, r23 /* Add reloc offset */ - sw r12, r21, r0 /* Save entry back */ - - cmpur12, r21, r22 /* Check if this cross boundary */ - bneid r12, 3b - addik r21. r21, 4 -#endif /* Flush caches to ensure consistency */ brlid r15, flush_cache_all -- 2.25.1
[PATCH v2 4/5] microblaze: drop CONFIG_NEEDS_MANUAL_RELOC
Microblaze and m68k are the only remaining architectures that still enable
CONFIG_NEEDS_MANUAL_RELOC by default.
Microblaze has had runtime relocation support using CONFIG_STATIC_RELA for
quite some time, since commit d58c007498 ("microblaze: Add support for run
time relocation"). Drop support for CONFIG_NEEDS_MANUAL_RELOC and make
runtime relocation the default, as the rest of the architectures do.
Reviewed-by: Michal Simek
Signed-off-by: Ovidiu Panait
---
(no changes since v1)
arch/microblaze/Kconfig | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index ce157a79cc..e38c9f6d71 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -4,19 +4,8 @@ menu "MicroBlaze architecture"
config SYS_ARCH
default "microblaze"
-config NEEDS_MANUAL_RELOC
- bool "Disable position-independent pre-relocation code"
- default y
- help
- U-Boot expects to be linked to a specific hard-coded address, and to
- be loaded to and run from that address. This option lifts that
- restriction, thus allowing the code to be loaded to and executed from
- almost any 4K aligned address. This logic relies on the relocation
- information that is embedded in the binary to support U-Boot
- relocating itself to the top-of-RAM later during execution.
-
config STATIC_RELA
- def_bool y if !NEEDS_MANUAL_RELOC
+ def_bool y
choice
prompt "Target select"
--
2.25.1
[PATCH v2 3/5] tools: relocate-rela: add support for handling 32-bit big endian files
Currently, a microblaze build with CONFIG_SYS_BIG_ENDIAN=y and
CONFIG_STATIC_RELA=y fails with:
tools/relocate-rela: Not supported machine type
ELF decoding failed
make[2]: *** [u-boot/Makefile:1306: u-boot-nodtb.bin] Error 1
To fix this, convert the 32-bit codepath to use the previously added
elf{16,32}_to_cpu() functions. The aarch64 codepath is left untouched.
This commit ensures that CI doesn't fail for the next patches which enable
runtime relocation by default for microblaze.
Reviewed-by: Michal Simek
Signed-off-by: Ovidiu Panait
---
(no changes since v1)
tools/relocate-rela.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c
index b27c41b96f..fe8cd6bda9 100644
--- a/tools/relocate-rela.c
+++ b/tools/relocate-rela.c
@@ -251,7 +251,7 @@ static int decode_elf32(FILE *felf, char **argv)
return 25;
}
- machine = le16_to_cpu(header.e_machine);
+ machine = elf16_to_cpu(header.e_machine);
debug("Machine %d\n", machine);
if (machine != EM_MICROBLAZE) {
@@ -259,10 +259,10 @@ static int decode_elf32(FILE *felf, char **argv)
return 30;
}
- text_base = le32_to_cpu(header.e_entry);
- section_header_base = le32_to_cpu(header.e_shoff);
- section_header_size = le16_to_cpu(header.e_shentsize) *
- le16_to_cpu(header.e_shnum);
+ text_base = elf32_to_cpu(header.e_entry);
+ section_header_base = elf32_to_cpu(header.e_shoff);
+ section_header_size = elf16_to_cpu(header.e_shentsize) *
+ elf16_to_cpu(header.e_shnum);
sh_table = malloc(section_header_size);
if (!sh_table) {
@@ -290,8 +290,8 @@ static int decode_elf32(FILE *felf, char **argv)
return 27;
}
- sh_index = le16_to_cpu(header.e_shstrndx);
- sh_size = le32_to_cpu(sh_table[sh_index].sh_size);
+ sh_index = elf16_to_cpu(header.e_shstrndx);
+ sh_size = elf32_to_cpu(sh_table[sh_index].sh_size);
debug("e_shstrndx %x, sh_size %lx\n", sh_index, sh_size);
sh_str = malloc(sh_size);
@@ -306,8 +306,8 @@ static int decode_elf32(FILE *felf, char **argv)
* Specifies the byte offset from the beginning of the file
* to the first byte in the section.
*/
- sh_offset = le32_to_cpu(sh_table[sh_index].sh_offset);
- sh_num = le16_to_cpu(header.e_shnum);
+ sh_offset = elf32_to_cpu(sh_table[sh_index].sh_offset);
+ sh_num = elf16_to_cpu(header.e_shnum);
ret = fseek(felf, sh_offset, SEEK_SET);
if (ret) {
@@ -329,13 +329,13 @@ static int decode_elf32(FILE *felf, char **argv)
}
for (i = 0; i < sh_num; i++) {
- char *sh_name = sh_str + le32_to_cpu(sh_table[i].sh_name);
+ char *sh_name = sh_str + elf32_to_cpu(sh_table[i].sh_name);
debug("%s\n", sh_name);
- sh_addr = le32_to_cpu(sh_table[i].sh_addr);
- sh_offset = le32_to_cpu(sh_table[i].sh_offset);
- sh_size = le32_to_cpu(sh_table[i].sh_size);
+ sh_addr = elf32_to_cpu(sh_table[i].sh_addr);
+ sh_offset = elf32_to_cpu(sh_table[i].sh_offset);
+ sh_size = elf32_to_cpu(sh_table[i].sh_size);
if (!strcmp(".rela.dyn", sh_name)) {
debug("Found section\t\".rela_dyn\"\n");
@@ -540,9 +540,9 @@ static int rela_elf32(char **argv, FILE *f)
PRIu32 " r_addend:\t%" PRIx32 "\n",
rela.r_offset, rela.r_info, rela.r_addend);
- swrela.r_offset = le32_to_cpu(rela.r_offset);
- swrela.r_info = le32_to_cpu(rela.r_info);
- swrela.r_addend = le32_to_cpu(rela.r_addend);
+ swrela.r_offset = elf32_to_cpu(rela.r_offset);
+ swrela.r_info = elf32_to_cpu(rela.r_info);
+ swrela.r_addend = elf32_to_cpu(rela.r_addend);
debug("SWRela:\toffset:\t%" PRIx32 " r_info:\t%"
PRIu32 " r_addend:\t%" PRIx32 "\n",
--
2.25.1
[PATCH v2 2/5] tools: relocate-rela: introduce elf16_to_cpu() and elf32_to_cpu()
Add elf16_to_cpu() and elf32_to_cpu() functions that allow to read data in
both big-endian and little-endian formats.
Reviewed-by: Michal Simek
Signed-off-by: Ovidiu Panait
---
Changes in v2:
Replaced hardcoded 0x1 values with ELFDATA2LSB.
tools/relocate-rela.c | 20
1 file changed, 20 insertions(+)
diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c
index 689e2d4655..b27c41b96f 100644
--- a/tools/relocate-rela.c
+++ b/tools/relocate-rela.c
@@ -45,6 +45,7 @@
#endif
static int ei_class;
+static int ei_data;
static uint64_t rela_start, rela_end, text_base, dyn_start;
@@ -61,6 +62,22 @@ static void debug(const char *fmt, ...)
}
}
+static uint16_t elf16_to_cpu(uint16_t data)
+{
+ if (ei_data == ELFDATA2LSB)
+ return le16_to_cpu(data);
+
+ return be16_to_cpu(data);
+}
+
+static uint32_t elf32_to_cpu(uint32_t data)
+{
+ if (ei_data == ELFDATA2LSB)
+ return le32_to_cpu(data);
+
+ return be32_to_cpu(data);
+}
+
static bool supported_rela(Elf64_Rela *rela)
{
uint64_t mask = 0xULL; /* would be different on 32-bit */
@@ -384,6 +401,9 @@ static int decode_elf(char **argv)
ei_class = e_ident[4];
debug("EI_CLASS(1=32bit, 2=64bit) %d\n", ei_class);
+ ei_data = e_ident[5];
+ debug("EI_DATA(1=little endian, 2=big endian) %d\n", ei_data);
+
if (ei_class == 2)
return decode_elf64(felf, argv);
--
2.25.1
[PATCH v2 1/5] tools: relocate-rela: adjust le64_to_cpu -> le32_to_cpu in decode_elf32()
The sh_addr/sh_offset/sh_size fields in Elf32_Shdr are 32-bits wide, so
use le32_to_cpu() instead of the 64-bit variant.
Fixes: 5e0e1a86d327 ("tools: relocate-rela: Fix ELF decoding on big-endian
hosts")
Reviewed-by: Michal Simek
Signed-off-by: Ovidiu Panait
---
(no changes since v1)
tools/relocate-rela.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c
index 2d2a2ed277..689e2d4655 100644
--- a/tools/relocate-rela.c
+++ b/tools/relocate-rela.c
@@ -316,9 +316,9 @@ static int decode_elf32(FILE *felf, char **argv)
debug("%s\n", sh_name);
- sh_addr = le64_to_cpu(sh_table[i].sh_addr);
- sh_offset = le64_to_cpu(sh_table[i].sh_offset);
- sh_size = le64_to_cpu(sh_table[i].sh_size);
+ sh_addr = le32_to_cpu(sh_table[i].sh_addr);
+ sh_offset = le32_to_cpu(sh_table[i].sh_offset);
+ sh_size = le32_to_cpu(sh_table[i].sh_size);
if (!strcmp(".rela.dyn", sh_name)) {
debug("Found section\t\".rela_dyn\"\n");
--
2.25.1
[PATCH 4/5] microblaze: drop CONFIG_NEEDS_MANUAL_RELOC
Microblaze and m68k are the only remaining architectures that still enable
CONFIG_NEEDS_MANUAL_RELOC by default.
Microblaze has had runtime relocation support using CONFIG_STATIC_RELA for
quite some time, since commit d58c007498 ("microblaze: Add support for run
time relocation"). Drop support for CONFIG_NEEDS_MANUAL_RELOC and make
runtime relocation the default, as the rest of the architectures do.
Signed-off-by: Ovidiu Panait
---
arch/microblaze/Kconfig | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index ce157a79cc..e38c9f6d71 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -4,19 +4,8 @@ menu "MicroBlaze architecture"
config SYS_ARCH
default "microblaze"
-config NEEDS_MANUAL_RELOC
- bool "Disable position-independent pre-relocation code"
- default y
- help
- U-Boot expects to be linked to a specific hard-coded address, and to
- be loaded to and run from that address. This option lifts that
- restriction, thus allowing the code to be loaded to and executed from
- almost any 4K aligned address. This logic relies on the relocation
- information that is embedded in the binary to support U-Boot
- relocating itself to the top-of-RAM later during execution.
-
config STATIC_RELA
- def_bool y if !NEEDS_MANUAL_RELOC
+ def_bool y
choice
prompt "Target select"
--
2.25.1
[PATCH 5/5] microblaze: drop remnants of manual reloc
Runtime relocation has been made the default for microblaze, so do the following cleanups: - drop all manual reloc codepaths in start.S - drop all STATIC_RELA ifdefs, as it is now enabled unconditionally in Kconfig Signed-off-by: Ovidiu Panait --- arch/microblaze/config.mk| 4 arch/microblaze/cpu/Makefile | 3 +-- arch/microblaze/cpu/start.S | 28 3 files changed, 1 insertion(+), 34 deletions(-) diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk index 467c5ca1b1..64c3f31319 100644 --- a/arch/microblaze/config.mk +++ b/arch/microblaze/config.mk @@ -13,10 +13,6 @@ LDFLAGS_FINAL += --gc-sections ifeq ($(CONFIG_SPL_BUILD),) PLATFORM_CPPFLAGS += -fPIC -endif - -ifeq ($(CONFIG_STATIC_RELA),y) -PLATFORM_CPPFLAGS += -fPIC LDFLAGS_u-boot += -pic endif diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile index 1c586a7de0..b8c1dcbe14 100644 --- a/arch/microblaze/cpu/Makefile +++ b/arch/microblaze/cpu/Makefile @@ -5,7 +5,6 @@ extra-y= start.o obj-y = irq.o -obj-y += interrupts.o cache.o exception.o cpuinfo.o -obj-$(CONFIG_STATIC_RELA) += relocate.o +obj-y += interrupts.o cache.o exception.o cpuinfo.o relocate.o obj-$(CONFIG_XILINX_MICROBLAZE0_PVR) += pvr.o obj-$(CONFIG_SPL_BUILD)+= spl.o diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 7079d9e170..c1e0fcda0a 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -10,16 +10,11 @@ #include #include -#if defined(CONFIG_STATIC_RELA) #define SYM_ADDR(reg, reg_add, symbol) \ mfs r20, rpc; \ addik r20, r20, _GLOBAL_OFFSET_TABLE_ + 8; \ lwi reg, r20, symbol@GOT; \ addkreg, reg reg_add; -#else -#define SYM_ADDR(reg, reg_add, symbol) \ - addireg, reg_add, symbol -#endif .text .global _start @@ -35,7 +30,6 @@ _start: addir1, r0, CONFIG_SPL_STACK #else add r1, r0, r20 -#if defined(CONFIG_STATIC_RELA) bri 1f /* Force alignment for easier ASM code below */ @@ -67,7 +61,6 @@ uboot_sym_start: brlid r15, mb_fix_rela nop -#endif #endif addir1, r1, -4 /* Decrement SP to top of memory */ @@ -310,7 +303,6 @@ relocate_code: brlid r15, __setup_exceptions nop -#if defined(CONFIG_STATIC_RELA) /* reloc_offset is current location */ SYM_ADDR(r10, r0, _start) @@ -331,27 +323,7 @@ relocate_code: add r9, r9, r5 brlid r15, mb_fix_rela nop - /* end of code which does relocation */ -#else - /* Check if GOT exist */ - addik r21, r23, _got_start - addik r22, r23, _got_end - cmpur12, r21, r22 - beqir12, 2f /* No GOT table - jump over */ - - /* Skip last 3 entries plus 1 because of loop boundary below */ - addik r22, r22, -0x10 - -/* Relocate the GOT. */ -3: lw r12, r21, r0 /* Load entry */ - addkr12, r12, r23 /* Add reloc offset */ - sw r12, r21, r0 /* Save entry back */ - - cmpur12, r21, r22 /* Check if this cross boundary */ - bneid r12, 3b - addik r21. r21, 4 -#endif /* Flush caches to ensure consistency */ brlid r15, flush_cache_all -- 2.25.1
[PATCH 3/5] tools: relocate-rela: add support for handling 32-bit big endian files
Currently, a microblaze build with CONFIG_SYS_BIG_ENDIAN=y and
CONFIG_STATIC_RELA=y fails with:
tools/relocate-rela: Not supported machine type
ELF decoding failed
make[2]: *** [u-boot/Makefile:1306: u-boot-nodtb.bin] Error 1
To fix this, convert the 32-bit codepath to use the previously added
elf{16,32}_to_cpu() functions. The aarch64 codepath is left untouched.
This commit ensures that CI doesn't fail for the next patches which enable
runtime relocation by default for microblaze.
Signed-off-by: Ovidiu Panait
---
tools/relocate-rela.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c
index 84531b23a6..2bc46a12d7 100644
--- a/tools/relocate-rela.c
+++ b/tools/relocate-rela.c
@@ -251,7 +251,7 @@ static int decode_elf32(FILE *felf, char **argv)
return 25;
}
- machine = le16_to_cpu(header.e_machine);
+ machine = elf16_to_cpu(header.e_machine);
debug("Machine %d\n", machine);
if (machine != EM_MICROBLAZE) {
@@ -259,10 +259,10 @@ static int decode_elf32(FILE *felf, char **argv)
return 30;
}
- text_base = le32_to_cpu(header.e_entry);
- section_header_base = le32_to_cpu(header.e_shoff);
- section_header_size = le16_to_cpu(header.e_shentsize) *
- le16_to_cpu(header.e_shnum);
+ text_base = elf32_to_cpu(header.e_entry);
+ section_header_base = elf32_to_cpu(header.e_shoff);
+ section_header_size = elf16_to_cpu(header.e_shentsize) *
+ elf16_to_cpu(header.e_shnum);
sh_table = malloc(section_header_size);
if (!sh_table) {
@@ -290,8 +290,8 @@ static int decode_elf32(FILE *felf, char **argv)
return 27;
}
- sh_index = le16_to_cpu(header.e_shstrndx);
- sh_size = le32_to_cpu(sh_table[sh_index].sh_size);
+ sh_index = elf16_to_cpu(header.e_shstrndx);
+ sh_size = elf32_to_cpu(sh_table[sh_index].sh_size);
debug("e_shstrndx %x, sh_size %lx\n", sh_index, sh_size);
sh_str = malloc(sh_size);
@@ -306,8 +306,8 @@ static int decode_elf32(FILE *felf, char **argv)
* Specifies the byte offset from the beginning of the file
* to the first byte in the section.
*/
- sh_offset = le32_to_cpu(sh_table[sh_index].sh_offset);
- sh_num = le16_to_cpu(header.e_shnum);
+ sh_offset = elf32_to_cpu(sh_table[sh_index].sh_offset);
+ sh_num = elf16_to_cpu(header.e_shnum);
ret = fseek(felf, sh_offset, SEEK_SET);
if (ret) {
@@ -329,13 +329,13 @@ static int decode_elf32(FILE *felf, char **argv)
}
for (i = 0; i < sh_num; i++) {
- char *sh_name = sh_str + le32_to_cpu(sh_table[i].sh_name);
+ char *sh_name = sh_str + elf32_to_cpu(sh_table[i].sh_name);
debug("%s\n", sh_name);
- sh_addr = le32_to_cpu(sh_table[i].sh_addr);
- sh_offset = le32_to_cpu(sh_table[i].sh_offset);
- sh_size = le32_to_cpu(sh_table[i].sh_size);
+ sh_addr = elf32_to_cpu(sh_table[i].sh_addr);
+ sh_offset = elf32_to_cpu(sh_table[i].sh_offset);
+ sh_size = elf32_to_cpu(sh_table[i].sh_size);
if (!strcmp(".rela.dyn", sh_name)) {
debug("Found section\t\".rela_dyn\"\n");
@@ -540,9 +540,9 @@ static int rela_elf32(char **argv, FILE *f)
PRIu32 " r_addend:\t%" PRIx32 "\n",
rela.r_offset, rela.r_info, rela.r_addend);
- swrela.r_offset = le32_to_cpu(rela.r_offset);
- swrela.r_info = le32_to_cpu(rela.r_info);
- swrela.r_addend = le32_to_cpu(rela.r_addend);
+ swrela.r_offset = elf32_to_cpu(rela.r_offset);
+ swrela.r_info = elf32_to_cpu(rela.r_info);
+ swrela.r_addend = elf32_to_cpu(rela.r_addend);
debug("SWRela:\toffset:\t%" PRIx32 " r_info:\t%"
PRIu32 " r_addend:\t%" PRIx32 "\n",
--
2.25.1
[PATCH 2/5] tools: relocate-rela: introduce elf16_to_cpu() and elf32_to_cpu()
Add elf16_to_cpu() and elf32_to_cpu() functions that allow to read data in
both big-endian and little-endian formats.
Signed-off-by: Ovidiu Panait
---
tools/relocate-rela.c | 20
1 file changed, 20 insertions(+)
diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c
index 689e2d4655..84531b23a6 100644
--- a/tools/relocate-rela.c
+++ b/tools/relocate-rela.c
@@ -45,6 +45,7 @@
#endif
static int ei_class;
+static int ei_data;
static uint64_t rela_start, rela_end, text_base, dyn_start;
@@ -61,6 +62,22 @@ static void debug(const char *fmt, ...)
}
}
+static uint16_t elf16_to_cpu(uint16_t data)
+{
+ if (ei_data == 0x01)
+ return le16_to_cpu(data);
+
+ return be16_to_cpu(data);
+}
+
+static uint32_t elf32_to_cpu(uint32_t data)
+{
+ if (ei_data == 0x01)
+ return le32_to_cpu(data);
+
+ return be32_to_cpu(data);
+}
+
static bool supported_rela(Elf64_Rela *rela)
{
uint64_t mask = 0xULL; /* would be different on 32-bit */
@@ -384,6 +401,9 @@ static int decode_elf(char **argv)
ei_class = e_ident[4];
debug("EI_CLASS(1=32bit, 2=64bit) %d\n", ei_class);
+ ei_data = e_ident[5];
+ debug("EI_DATA(1=little endian, 2=big endian) %d\n", ei_data);
+
if (ei_class == 2)
return decode_elf64(felf, argv);
--
2.25.1
[PATCH 1/5] tools: relocate-rela: adjust le64_to_cpu -> le32_to_cpu in decode_elf32()
The sh_addr/sh_offset/sh_size fields in Elf32_Shdr are 32-bits wide, so
use le32_to_cpu() instead of the 64-bit variant.
Fixes: 5e0e1a86d327 ("tools: relocate-rela: Fix ELF decoding on big-endian
hosts")
Signed-off-by: Ovidiu Panait
---
tools/relocate-rela.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c
index 2d2a2ed277..689e2d4655 100644
--- a/tools/relocate-rela.c
+++ b/tools/relocate-rela.c
@@ -316,9 +316,9 @@ static int decode_elf32(FILE *felf, char **argv)
debug("%s\n", sh_name);
- sh_addr = le64_to_cpu(sh_table[i].sh_addr);
- sh_offset = le64_to_cpu(sh_table[i].sh_offset);
- sh_size = le64_to_cpu(sh_table[i].sh_size);
+ sh_addr = le32_to_cpu(sh_table[i].sh_addr);
+ sh_offset = le32_to_cpu(sh_table[i].sh_offset);
+ sh_size = le32_to_cpu(sh_table[i].sh_size);
if (!strcmp(".rela.dyn", sh_name)) {
debug("Found section\t\".rela_dyn\"\n");
--
2.25.1
[PATCH v2 3/3] microblaze: spl: disable falcon mode by default
Drop falcon mode configs from microblaze-generic_defconfig, so that a defconfig build will still boot into u-boot proper. Signed-off-by: Ovidiu Panait --- Changes in v2: New patch. configs/microblaze-generic_defconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index be34941805..438540fbe4 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -33,9 +33,6 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK=0x10 CONFIG_SPL_NOR_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_SPL_ARGS_ADDR=0x2a00 -CONFIG_SYS_OS_BASE=0x2c06 CONFIG_SYS_MAXARGS=15 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=544 -- 2.25.1
[PATCH v2 2/3] microblaze: spl: drop boot_linux
Drop boot_linux variable as it is not assigned anywhere. Now that there is
no variable controlling linux boot in spl_start_uboot(), make this
function always return false when falcon mode is enabled.
Signed-off-by: Ovidiu Panait
---
Changes in v2:
New patch.
arch/microblaze/cpu/spl.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c
index b9ff9c3702..eaa095ba99 100644
--- a/arch/microblaze/cpu/spl.c
+++ b/arch/microblaze/cpu/spl.c
@@ -14,8 +14,6 @@
#include
#include
-bool boot_linux;
-
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = BOOT_DEVICE_NOR;
@@ -44,10 +42,7 @@ void __noreturn jump_to_image_linux(struct spl_image_info
*spl_image)
int spl_start_uboot(void)
{
- if (boot_linux)
- return 0;
-
- return 1;
+ return 0;
}
#endif /* CONFIG_SPL_OS_BOOT */
--
2.25.1
[PATCH v2 1/3] microblaze: spl: wrap spl_start_uboot() in SPL_OS_BOOT ifdefs
Make spl_start_uboot() available only if CONFIG_SPL_OS_BOOT is enabled,
since it is only used for falcon mode.
Signed-off-by: Ovidiu Panait
---
Changes in v2:
New patch.
arch/microblaze/cpu/spl.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c
index cea6d56f16..b9ff9c3702 100644
--- a/arch/microblaze/cpu/spl.c
+++ b/arch/microblaze/cpu/spl.c
@@ -41,17 +41,15 @@ void __noreturn jump_to_image_linux(struct spl_image_info
*spl_image)
image_entry(NULL, 0, (ulong)spl_image->arg);
}
-#endif /* CONFIG_SPL_OS_BOOT */
int spl_start_uboot(void)
{
-#ifdef CONFIG_SPL_OS_BOOT
if (boot_linux)
return 0;
-#endif
return 1;
}
+#endif /* CONFIG_SPL_OS_BOOT */
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
--
2.25.1
[PATCH] microblaze: spl: drop boot_linux and disable falcon mode by default
Make spl_start_uboot() available only if CONFIG_SPL_OS_BOOT is enabled
and drop boot_linux, as the variable is not assigned anywhere.
Also, disable CONFIG_SPL_OS_BOOT in defconfig so that a
microblaze-generic_defconfig build will still boot into u-boot proper, as
it does currently.
Signed-off-by: Ovidiu Panait
---
arch/microblaze/cpu/spl.c| 11 ++-
common/spl/Kconfig | 2 ++
configs/microblaze-generic_defconfig | 3 ---
3 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c
index cea6d56f16..eaa095ba99 100644
--- a/arch/microblaze/cpu/spl.c
+++ b/arch/microblaze/cpu/spl.c
@@ -14,8 +14,6 @@
#include
#include
-bool boot_linux;
-
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = BOOT_DEVICE_NOR;
@@ -41,17 +39,12 @@ void __noreturn jump_to_image_linux(struct spl_image_info
*spl_image)
image_entry(NULL, 0, (ulong)spl_image->arg);
}
-#endif /* CONFIG_SPL_OS_BOOT */
int spl_start_uboot(void)
{
-#ifdef CONFIG_SPL_OS_BOOT
- if (boot_linux)
- return 0;
-#endif
-
- return 1;
+ return 0;
}
+#endif /* CONFIG_SPL_OS_BOOT */
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 3c2af453ab..de6d8c3a18 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -1081,6 +1081,7 @@ config SYS_SPL_ARGS_ADDR
hex "Address in memory to load 'args' file for Falcon Mode to"
depends on SPL_OS_BOOT
default 0x8800 if ARCH_OMAP2PLUS
+ default 0x2a00 if MICROBLAZE
help
Address in memory where the 'args' file, typically a device tree
will be loaded in to memory.
@@ -1092,6 +1093,7 @@ config SYS_NAND_SPL_KERNEL_OFFS
config SYS_OS_BASE
hex "addr, where OS is found"
depends on SPL_OS_BOOT && SPL_NOR_SUPPORT
+ default 0x2c06 if MICROBLAZE
help
Specify the address, where the OS image is found, which
gets booted.
diff --git a/configs/microblaze-generic_defconfig
b/configs/microblaze-generic_defconfig
index be34941805..438540fbe4 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -33,9 +33,6 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK=0x10
CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_SPL_ARGS_ADDR=0x2a00
-CONFIG_SYS_OS_BASE=0x2c06
CONFIG_SYS_MAXARGS=15
CONFIG_SYS_CBSIZE=512
CONFIG_SYS_PBSIZE=544
--
2.25.1
[PATCH] spl: doc: use correct name in jump_to_image_optee() description
The actual function being documented is jump_to_image_optee(), not jump_to_image_linux(). Signed-off-by: Ovidiu Panait --- include/spl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/spl.h b/include/spl.h index fb8c279d72..827bd25c88 100644 --- a/include/spl.h +++ b/include/spl.h @@ -535,7 +535,7 @@ const char *spl_board_loader_name(u32 boot_device); void __noreturn jump_to_image_linux(struct spl_image_info *spl_image); /** - * jump_to_image_linux() - Jump to OP-TEE OS from SPL + * jump_to_image_optee() - Jump to OP-TEE OS from SPL * * This jumps into OP-TEE OS using the information in @spl_image. * -- 2.25.1
Re: [PATCH 2/3] timer-uclass: relocate ops pointers for CONFIG_NEEDS_MANUAL_RELOC
Hi Simon, On 10/12/22 15:59, Simon Glass wrote: On Tue, 11 Oct 2022 at 23:37, Ovidiu Panait wrote: Relocate timer_ops pointers when CONFIG_NEEDS_MANUAL_RELOC is enabled. The (gd->flags & GD_FLG_RELOC) check was added to make sure the reloc_done logic works for drivers that use DM_FLAG_PRE_RELOC. Signed-off-by: Ovidiu Panait --- drivers/timer/timer-uclass.c | 14 ++ 1 file changed, 14 insertions(+) Reviewed-by: Simon Glass Which (broken) toolchain are you using? Microblaze and m68k still use CONFIG_NEEDS_MANUAL_RELOC=y by default. I was testing on microblaze. Ovidiu
[PATCH 3/3] timer: xilinx-timer: use timer_conv_64() to fix timer wrap around
Current xilinx_timer_get_count() implementation does not take into account
the periodic 32-bit wrap arounds, as it directly returns the 32-bit counter
register value. The roll-overs cause problems in the upper timer layers, as
generic timer code expects an incrementing 64-bit value from get_count() to
work correctly.
Add the missing 64-bit up-conversion to fix random hangs/delays in
__udelay().
Fixes: a36d86720f ("microblaze: Convert axi timer to DM driver")
Signed-off-by: Ovidiu Panait
---
drivers/timer/xilinx-timer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/timer/xilinx-timer.c b/drivers/timer/xilinx-timer.c
index 75b4473b63..172fd9f929 100644
--- a/drivers/timer/xilinx-timer.c
+++ b/drivers/timer/xilinx-timer.c
@@ -40,7 +40,7 @@ static u64 xilinx_timer_get_count(struct udevice *dev)
regmap_read(priv->regs, TIMER_COUNTER_OFFSET, );
- return value;
+ return timer_conv_64(value);
}
static int xilinx_timer_probe(struct udevice *dev)
--
2.25.1
[PATCH 2/3] timer-uclass: relocate ops pointers for CONFIG_NEEDS_MANUAL_RELOC
Relocate timer_ops pointers when CONFIG_NEEDS_MANUAL_RELOC is enabled.
The (gd->flags & GD_FLG_RELOC) check was added to make sure the reloc_done
logic works for drivers that use DM_FLAG_PRE_RELOC.
Signed-off-by: Ovidiu Panait
---
drivers/timer/timer-uclass.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index bdc77b3822..bb71979213 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -50,6 +51,19 @@ unsigned long notrace timer_get_rate(struct udevice *dev)
static int timer_pre_probe(struct udevice *dev)
{
+ if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC) &&
+ (gd->flags & GD_FLG_RELOC)) {
+ struct timer_ops *ops = timer_get_ops(dev);
+ static int reloc_done;
+
+ if (!reloc_done) {
+ if (ops->get_count)
+ MANUAL_RELOC(ops->get_count);
+
+ reloc_done++;
+ }
+ }
+
if (CONFIG_IS_ENABLED(OF_REAL)) {
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct clk timer_clk;
--
2.25.1
[PATCH 1/3] timer-uclass: add timer_get_ops() macro
Align timer uclass with the other subsystems and provide a timer_get_ops()
convenience macro.
Using this instead of the generic device_get_ops() also prevents
-Wdiscarded-qualifiers warnings when used with non-const variables.
Signed-off-by: Ovidiu Panait
---
drivers/timer/timer-uclass.c | 2 +-
include/timer.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index cbc3647698..bdc77b3822 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR;
int notrace timer_get_count(struct udevice *dev, u64 *count)
{
- const struct timer_ops *ops = device_get_ops(dev);
+ struct timer_ops *ops = timer_get_ops(dev);
if (!ops->get_count)
return -ENOSYS;
diff --git a/include/timer.h b/include/timer.h
index a044cb034e..d33a26e28f 100644
--- a/include/timer.h
+++ b/include/timer.h
@@ -6,6 +6,8 @@
#ifndef _TIMER_H_
#define _TIMER_H_
+#define timer_get_ops(dev) ((struct timer_ops *)(dev)->driver->ops)
+
/**
* dm_timer_init() - initialize a timer for time keeping. On success
* initializes gd->timer so that lib/timer can use it for future
--
2.25.1
[PATCH v2 4/4] common/board_f: drop ifdefs around header includes
Drop the remaining ifdef around spl.h include. Reviewed-by: Simon Glass Signed-off-by: Ovidiu Panait --- Changes in v2: - add "Reviewed-by" tag from Simon common/board_f.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/common/board_f.c b/common/board_f.c index 96458c5151..4db1626c29 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -35,9 +35,7 @@ #include #include #include -#ifdef CONFIG_SPL #include -#endif #include #include #include -- 2.25.1
[PATCH v2 3/4] common/board_f: introduce arch_setup_dest_addr()
In order to move ppc-specific code out of setup_dest_addr(), provide an
arch-specific variant arch_setup_dest_addr(), that can be used by
architecture code to fix up the initial reloc address.
It is called at the end of setup_dest_addr() initcall and the default
implementation is a nop stub.
Reviewed-by: Simon Glass
Signed-off-by: Ovidiu Panait
---
Changes in v2:
- add "Reviewed-by" tag from Simon
arch/powerpc/lib/stack.c | 17 +
common/board_f.c | 21 +++--
include/init.h | 13 +
3 files changed, 37 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/lib/stack.c b/arch/powerpc/lib/stack.c
index f2a4652e08..2e731aa870 100644
--- a/arch/powerpc/lib/stack.c
+++ b/arch/powerpc/lib/stack.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -30,3 +31,19 @@ int arch_reserve_stacks(void)
return 0;
}
+
+int arch_setup_dest_addr(void)
+{
+#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
+ /*
+* We need to make sure the location we intend to put secondary core
+* boot code is reserved and not used by any part of u-boot
+*/
+ if (gd->relocaddr > determine_mp_bootpg(NULL)) {
+ gd->relocaddr = determine_mp_bootpg(NULL);
+ debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
+ }
+#endif
+
+ return 0;
+}
diff --git a/common/board_f.c b/common/board_f.c
index 3789708a30..96458c5151 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -45,9 +45,6 @@
#include
#include
#include
-#if defined(CONFIG_MP) && defined(CONFIG_PPC)
-#include
-#endif
#include
#include
#include
@@ -307,6 +304,11 @@ __weak ulong board_get_usable_ram_top(ulong total_size)
return gd->ram_top;
}
+__weak int arch_setup_dest_addr(void)
+{
+ return 0;
+}
+
static int setup_dest_addr(void)
{
debug("Monitor len: %08lX\n", gd->mon_len);
@@ -334,17 +336,8 @@ static int setup_dest_addr(void)
gd->ram_top = board_get_usable_ram_top(gd->mon_len);
gd->relocaddr = gd->ram_top;
debug("Ram top: %08lX\n", (ulong)gd->ram_top);
-#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
- /*
-* We need to make sure the location we intend to put secondary core
-* boot code is reserved and not used by any part of u-boot
-*/
- if (gd->relocaddr > determine_mp_bootpg(NULL)) {
- gd->relocaddr = determine_mp_bootpg(NULL);
- debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
- }
-#endif
- return 0;
+
+ return arch_setup_dest_addr();
}
#ifdef CONFIG_PRAM
diff --git a/include/init.h b/include/init.h
index 7b8f62c121..448da34b46 100644
--- a/include/init.h
+++ b/include/init.h
@@ -103,6 +103,19 @@ phys_size_t get_effective_memsize(void);
int testdram(void);
+/**
+ * arch_setup_dest_addr() - Fix up initial reloc address
+ *
+ * This is called in generic board init sequence in common/board_f.c at the end
+ * of the setup_dest_addr() initcall. Each architecture could provide this
+ * function to make adjustments to the initial reloc address.
+ *
+ * If an implementation is not provided, it will just be a nop stub.
+ *
+ * Return: 0 if OK
+ */
+int arch_setup_dest_addr(void);
+
/**
* arch_reserve_stacks() - Reserve all necessary stacks
*
--
2.25.1
[PATCH v2 2/4] common/board_f: move CONFIG_MACH_TYPE logic to arch/arm/lib/bdinfo.c
asm/mach_type.h header and CONFIG_MACH_TYPE macro are arm-specific, so move
related bdinfo logic to arch_setup_bdinfo() in arch/arm/lib/bdinfo.c.
Reviewed-by: Simon Glass
Signed-off-by: Ovidiu Panait
---
Changes in v2:
- add "Reviewed-by" tag from Simon
arch/arm/lib/bdinfo.c | 12
common/board_f.c | 7 ---
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c
index b22ee07b85..826e09e72c 100644
--- a/arch/arm/lib/bdinfo.c
+++ b/arch/arm/lib/bdinfo.c
@@ -9,9 +9,21 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
+int arch_setup_bdinfo(void)
+{
+#ifdef CONFIG_MACH_TYPE
+ struct bd_info *bd = gd->bd;
+
+ bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
+#endif
+
+ return 0;
+}
+
void arch_print_bdinfo(void)
{
struct bd_info *bd = gd->bd;
diff --git a/common/board_f.c b/common/board_f.c
index f4238d4c90..3789708a30 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -45,9 +45,6 @@
#include
#include
#include
-#ifdef CONFIG_MACH_TYPE
-#include
-#endif
#if defined(CONFIG_MP) && defined(CONFIG_PPC)
#include
#endif
@@ -588,10 +585,6 @@ int setup_bdinfo(void)
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
}
-#ifdef CONFIG_MACH_TYPE
- bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
-#endif
-
return arch_setup_bdinfo();
}
--
2.25.1
[PATCH v2 1/4] common/board_f: remove XTRN_DECLARE_GLOBAL_DATA_PTR dead code
The XTRN_DECLARE_GLOBAL_DATA_PTR declarations in ppc code are permanently
commented out, so there are no users for this macro:
#if 1
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
#else /* We could use plain global data, but the resulting code is bigger */
#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
gd_t *gd
#endif
Remove all references to this macro, but add a documentation note regarding
the possibility of using plain global data for the GD pointer.
Signed-off-by: Ovidiu Panait
---
Changes in v2:
- update global data documentation with the info provided by Wolfgang
arch/powerpc/include/asm/global_data.h | 6 --
common/board_f.c | 11 ---
doc/develop/global_data.rst| 5 +
3 files changed, 5 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/include/asm/global_data.h
b/arch/powerpc/include/asm/global_data.h
index 6709e692e6..6ed21c781f 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -92,12 +92,6 @@ struct arch_global_data {
#include
-#if 1
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
-#else /* We could use plain global data, but the resulting code is bigger */
-#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
-#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
- gd_t *gd
-#endif
#endif /* __ASM_GBL_DATA_H */
diff --git a/common/board_f.c b/common/board_f.c
index 18e2246733..f4238d4c90 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -57,18 +57,7 @@
#include
#include
-/*
- * Pointer to initial global data area
- *
- * Here we initialize it if needed.
- */
-#ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
-#undef XTRN_DECLARE_GLOBAL_DATA_PTR
-#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
-DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
-#else
DECLARE_GLOBAL_DATA_PTR;
-#endif
/*
* TODO(s...@chromium.org): IMO this code should be
diff --git a/doc/develop/global_data.rst b/doc/develop/global_data.rst
index 2ac893de49..d143f27eed 100644
--- a/doc/develop/global_data.rst
+++ b/doc/develop/global_data.rst
@@ -36,6 +36,11 @@ On most architectures the global data pointer is stored in a
register.
The sandbox, x86_64, and Xtensa are notable exceptions.
+Current implementation uses a register for the GD pointer because this results
+in smaller code. However, using plain global data for the GD pointer would be
+possible too (and simpler, as it does not require the reservation of a specific
+register for it), but the resulting code is bigger.
+
Clang for ARM does not support assigning a global register. When using Clang
gd is defined as an inline function using assembly code. This adds a few bytes
to the code size.
--
2.25.1
[PATCH 4/4] common/board_f: drop ifdefs around header includes
Drop the remaining ifdef around spl.h include. Signed-off-by: Ovidiu Panait --- common/board_f.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/common/board_f.c b/common/board_f.c index 96458c5151..4db1626c29 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -35,9 +35,7 @@ #include #include #include -#ifdef CONFIG_SPL #include -#endif #include #include #include -- 2.25.1
[PATCH 3/4] common/board_f: introduce arch_setup_dest_addr()
In order to move ppc-specific code out of setup_dest_addr(), provide an
arch-specific variant arch_setup_dest_addr(), that can be used by
architecture code to fix up the initial reloc address.
It is called at the end of setup_dest_addr() initcall and the default
implementation is a nop stub.
Signed-off-by: Ovidiu Panait
---
arch/powerpc/lib/stack.c | 17 +
common/board_f.c | 21 +++--
include/init.h | 13 +
3 files changed, 37 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/lib/stack.c b/arch/powerpc/lib/stack.c
index f2a4652e08..2e731aa870 100644
--- a/arch/powerpc/lib/stack.c
+++ b/arch/powerpc/lib/stack.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -30,3 +31,19 @@ int arch_reserve_stacks(void)
return 0;
}
+
+int arch_setup_dest_addr(void)
+{
+#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
+ /*
+* We need to make sure the location we intend to put secondary core
+* boot code is reserved and not used by any part of u-boot
+*/
+ if (gd->relocaddr > determine_mp_bootpg(NULL)) {
+ gd->relocaddr = determine_mp_bootpg(NULL);
+ debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
+ }
+#endif
+
+ return 0;
+}
diff --git a/common/board_f.c b/common/board_f.c
index 3789708a30..96458c5151 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -45,9 +45,6 @@
#include
#include
#include
-#if defined(CONFIG_MP) && defined(CONFIG_PPC)
-#include
-#endif
#include
#include
#include
@@ -307,6 +304,11 @@ __weak ulong board_get_usable_ram_top(ulong total_size)
return gd->ram_top;
}
+__weak int arch_setup_dest_addr(void)
+{
+ return 0;
+}
+
static int setup_dest_addr(void)
{
debug("Monitor len: %08lX\n", gd->mon_len);
@@ -334,17 +336,8 @@ static int setup_dest_addr(void)
gd->ram_top = board_get_usable_ram_top(gd->mon_len);
gd->relocaddr = gd->ram_top;
debug("Ram top: %08lX\n", (ulong)gd->ram_top);
-#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
- /*
-* We need to make sure the location we intend to put secondary core
-* boot code is reserved and not used by any part of u-boot
-*/
- if (gd->relocaddr > determine_mp_bootpg(NULL)) {
- gd->relocaddr = determine_mp_bootpg(NULL);
- debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
- }
-#endif
- return 0;
+
+ return arch_setup_dest_addr();
}
#ifdef CONFIG_PRAM
diff --git a/include/init.h b/include/init.h
index 7b8f62c121..448da34b46 100644
--- a/include/init.h
+++ b/include/init.h
@@ -103,6 +103,19 @@ phys_size_t get_effective_memsize(void);
int testdram(void);
+/**
+ * arch_setup_dest_addr() - Fix up initial reloc address
+ *
+ * This is called in generic board init sequence in common/board_f.c at the end
+ * of the setup_dest_addr() initcall. Each architecture could provide this
+ * function to make adjustments to the initial reloc address.
+ *
+ * If an implementation is not provided, it will just be a nop stub.
+ *
+ * Return: 0 if OK
+ */
+int arch_setup_dest_addr(void);
+
/**
* arch_reserve_stacks() - Reserve all necessary stacks
*
--
2.25.1
[PATCH 1/4] common/board_f: remove XTRN_DECLARE_GLOBAL_DATA_PTR dead code
The XTRN_DECLARE_GLOBAL_DATA_PTR declarations in ppc code are permanently
commented out, so there are no users for this macro:
#if 1
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
#else
#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
gd_t *gd
#endif
Remove all references.
Signed-off-by: Ovidiu Panait
---
arch/powerpc/include/asm/global_data.h | 6 --
common/board_f.c | 11 ---
2 files changed, 17 deletions(-)
diff --git a/arch/powerpc/include/asm/global_data.h
b/arch/powerpc/include/asm/global_data.h
index 6709e692e6..6ed21c781f 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -92,12 +92,6 @@ struct arch_global_data {
#include
-#if 1
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
-#else /* We could use plain global data, but the resulting code is bigger */
-#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
-#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
- gd_t *gd
-#endif
#endif /* __ASM_GBL_DATA_H */
diff --git a/common/board_f.c b/common/board_f.c
index 18e2246733..f4238d4c90 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -57,18 +57,7 @@
#include
#include
-/*
- * Pointer to initial global data area
- *
- * Here we initialize it if needed.
- */
-#ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
-#undef XTRN_DECLARE_GLOBAL_DATA_PTR
-#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
-DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
-#else
DECLARE_GLOBAL_DATA_PTR;
-#endif
/*
* TODO(s...@chromium.org): IMO this code should be
--
2.25.1
[PATCH 2/4] common/board_f: move CONFIG_MACH_TYPE logic to arch/arm/lib/bdinfo.c
asm/mach_type.h header and CONFIG_MACH_TYPE macro are arm-specific, so move
related bdinfo logic to arch_setup_bdinfo() in arch/arm/lib/bdinfo.c.
Signed-off-by: Ovidiu Panait
---
arch/arm/lib/bdinfo.c | 12
common/board_f.c | 7 ---
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c
index b22ee07b85..826e09e72c 100644
--- a/arch/arm/lib/bdinfo.c
+++ b/arch/arm/lib/bdinfo.c
@@ -9,9 +9,21 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
+int arch_setup_bdinfo(void)
+{
+#ifdef CONFIG_MACH_TYPE
+ struct bd_info *bd = gd->bd;
+
+ bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
+#endif
+
+ return 0;
+}
+
void arch_print_bdinfo(void)
{
struct bd_info *bd = gd->bd;
diff --git a/common/board_f.c b/common/board_f.c
index f4238d4c90..3789708a30 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -45,9 +45,6 @@
#include
#include
#include
-#ifdef CONFIG_MACH_TYPE
-#include
-#endif
#if defined(CONFIG_MP) && defined(CONFIG_PPC)
#include
#endif
@@ -588,10 +585,6 @@ int setup_bdinfo(void)
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
}
-#ifdef CONFIG_MACH_TYPE
- bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
-#endif
-
return arch_setup_bdinfo();
}
--
2.25.1
[PATCH v2 4/4] microblaze: add arch_print_bdinfo() implementation
Allow bdinfo command to print icache/dcache information:
U-Boot-mONStR> bdinfo
boot_params = 0x
DRAM bank = 0x
-> start= 0x0400
-> size = 0x0400
flashstart = 0x
flashsize = 0x
flashoffset = 0x
baudrate= 9600 bps
relocaddr = 0x07f76000
reloc off = 0x02f76000
Build = 32-bit
current eth = unknown
ethaddr = (not set)
IP addr =
fdt_blob= 0x07fec7e0
new_fdt = 0x
fdt_size= 0x
lmb_dump_all:
memory.cnt = 0x1
memory[0] [0x400-0x7ff], 0x0400 bytes flags: 0
reserved.cnt = 0x1
reserved[0][0x7e94b8c-0x7ff], 0x0016b474 bytes flags: 0
devicetree = embed
icache = 32 KiB
icache line = 4 Bytes
dcache = 32 KiB
dcache line = 4 Bytes
Signed-off-by: Ovidiu Panait
---
(no changes since v1)
arch/microblaze/lib/Makefile | 1 +
arch/microblaze/lib/bdinfo.c | 24
2 files changed, 25 insertions(+)
create mode 100644 arch/microblaze/lib/bdinfo.c
diff --git a/arch/microblaze/lib/Makefile b/arch/microblaze/lib/Makefile
index 05f447abba..dfd8135f4f 100644
--- a/arch/microblaze/lib/Makefile
+++ b/arch/microblaze/lib/Makefile
@@ -4,4 +4,5 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BDI) += bdinfo.o
obj-y += muldi3.o
diff --git a/arch/microblaze/lib/bdinfo.c b/arch/microblaze/lib/bdinfo.c
new file mode 100644
index 00..41b7a216a4
--- /dev/null
+++ b/arch/microblaze/lib/bdinfo.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022, Ovidiu Panait
+ */
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void arch_print_bdinfo(void)
+{
+ struct microblaze_cpuinfo *ci = gd_cpuinfo();
+
+ if (ci->icache_size) {
+ bdinfo_print_size("icache", ci->icache_size);
+ bdinfo_print_size("icache line", ci->icache_line_length);
+ }
+
+ if (ci->dcache_size) {
+ bdinfo_print_size("dcache", ci->dcache_size);
+ bdinfo_print_size("dcache line", ci->dcache_line_length);
+ }
+}
--
2.25.1
[PATCH v2 3/4] cmd: bdinfo: introduce bdinfo_print_size() helper
Add bdinfo_print_size() helper to display size variables (such as cache
sizes) in bdinfo format. The size is printed as "xxx Bytes", "xxx KiB",
"xxx MiB", "xxx GiB", etc as needed;
Reviewed-by: Simon Glass
Signed-off-by: Ovidiu Panait
---
Changes in v2:
Added "Reviewed-by" tag from Simon.
cmd/bdinfo.c | 7 +++
include/init.h | 13 +
2 files changed, 20 insertions(+)
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 37cd8a57eb..9e23c4dd8f 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -16,9 +16,16 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
+void bdinfo_print_size(const char *name, uint64_t size)
+{
+ printf("%-12s= ", name);
+ print_size(size, "\n");
+}
+
void bdinfo_print_num_l(const char *name, ulong value)
{
printf("%-12s= 0x%0*lx\n", name, 2 * (int)sizeof(value), value);
diff --git a/include/init.h b/include/init.h
index 7b8f62c121..02bb4ce13e 100644
--- a/include/init.h
+++ b/include/init.h
@@ -343,6 +343,19 @@ void bdinfo_print_num_ll(const char *name, unsigned long
long value);
/* Print a clock speed in MHz */
void bdinfo_print_mhz(const char *name, unsigned long hz);
+/**
+ * bdinfo_print_size - print size variables in bdinfo format
+ * @name: string to print before the size
+ * @size: size to print
+ *
+ * Helper function for displaying size variables as properly formatted bdinfo
+ * entries. The size is printed as "xxx Bytes", "xxx KiB", "xxx MiB",
+ * "xxx GiB", etc. as needed;
+ *
+ * For use in arch_print_bdinfo().
+ */
+void bdinfo_print_size(const char *name, uint64_t size);
+
/* Show arch-specific information for the 'bd' command */
void arch_print_bdinfo(void);
--
2.25.1
[PATCH v2 2/4] cpu: microblaze: add error handling in microblaze_cpu_get_desc()
Check snprintf() return value for errors.
Make microblaze_cpu_get_desc() directly return snprintf() error code if
ret < 0. Otherwise, if the return value is greater than or equal to size,
the resulting string is truncated, so return -ENOSPC.
Fixes: 816226d27e ("cpu: add CPU driver for microblaze")
Signed-off-by: Ovidiu Panait
---
Changes in v2:
New patch.
drivers/cpu/microblaze_cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/cpu/microblaze_cpu.c b/drivers/cpu/microblaze_cpu.c
index 969a1047e5..b9d0792822 100644
--- a/drivers/cpu/microblaze_cpu.c
+++ b/drivers/cpu/microblaze_cpu.c
@@ -97,8 +97,10 @@ static int microblaze_cpu_get_desc(const struct udevice
*dev, char *buf,
ret = snprintf(buf, size,
"MicroBlaze @ %uMHz, Rev: %s, FPGA family: %s",
cpu_freq_mhz, cpu_ver, fpga_family);
+ if (ret < 0)
+ return ret;
- return 0;
+ return (ret >= size) ? -ENOSPC : 0;
}
static int microblaze_cpu_get_info(const struct udevice *dev,
--
2.25.1
[PATCH v2 1/4] microblaze: drop CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE
These macros are not used anymore in microblaze code since commit
f113d7d303467 ("Convert CONFIG_SPL_STACK to Kconfig"), so remove them.
Fixes: f113d7d303467 ("Convert CONFIG_SPL_STACK to Kconfig")
Signed-off-by: Ovidiu Panait
---
Changes in v2:
Improved commit message, added "Fixes" tag.
include/configs/microblaze-generic.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/include/configs/microblaze-generic.h
b/include/configs/microblaze-generic.h
index 8eaac4f8bc..dfae8cea7b 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -97,10 +97,4 @@
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
-/* SP location before relocation, must use scratch RAM */
-/* BRAM start */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x0
-/* BRAM size - will be generated */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10
-
#endif /* __CONFIG_H */
--
2.25.1
Re: [PATCH 2/4] cpu: microblaze: remove unused ret variable
Hi Michal, On 8/25/22 11:59, Michal Simek wrote: On 8/25/22 08:41, Ovidiu Panait wrote: Drop the unused ret variable from microblaze_cpu_get_desc(). Signed-off-by: Ovidiu Panait --- drivers/cpu/microblaze_cpu.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/cpu/microblaze_cpu.c b/drivers/cpu/microblaze_cpu.c index 969a1047e5..4eae06a8a6 100644 --- a/drivers/cpu/microblaze_cpu.c +++ b/drivers/cpu/microblaze_cpu.c @@ -88,15 +88,14 @@ static int microblaze_cpu_get_desc(const struct udevice *dev, char *buf, struct microblaze_cpuinfo *ci = gd_cpuinfo(); const char *cpu_ver, *fpga_family; u32 cpu_freq_mhz; - int ret; cpu_freq_mhz = ci->cpu_freq / 100; cpu_ver = microblaze_lookup_cpu_version_string(ci->ver_code); fpga_family = microblaze_lookup_fpga_family_string(ci->fpga_code); - ret = snprintf(buf, size, - "MicroBlaze @ %uMHz, Rev: %s, FPGA family: %s", - cpu_freq_mhz, cpu_ver, fpga_family); + snprintf(buf, size, + "MicroBlaze @ %uMHz, Rev: %s, FPGA family: %s", + cpu_freq_mhz, cpu_ver, fpga_family); return 0; } First of all I think you can remove DECLARE_GLOBAL_DATA_PTR from drivers/cpu/microblaze_cpu.c gd_cpuinfo() macro expands to "(struct microblaze_cpuinfo *)>arch.cpuinfo", so we need the declaration for gd. I looked at the code and I think that there are some things what should happen. First of all I would memset by 0 that buf which is passed and I think this should be done in uclass to make sure that you won't show anything what it is on the stack where buf is allocated in cmd/cpu.c for example. I don't think that the memset is necessary, snprintf will overwrite any previous contents and append the terminating null character after the last byte that was written to the buffer. So no garbage previously present on the stack should be printed when buf is used afterwards, as the string is null-terminated. The second if snprintf fails we shouldn't ignore that error because if you do that that means that buffer is valid and you can print content. For cpu_freq_mhz I think that make sense to allocate some space in string. For example %4u gives you exact size GHz should be fine for now. cpu_ver has max size 6 now and family string has 18 chars now. It means change string to this with some chars on the top should be fine for me. ret = snprintf(buf, size, "MicroBlaze @ %5uMHz, Rev: %7s, FPGA family: %20s", cpu_freq_mhz, cpu_ver, fpga_family); And then check that ret is equal XX size would be easy for checking and returning 0 if they match. I agree, the snprintf errors should be handled properly here. Thanks, Ovidiu Thanks, Michal
[PATCH 4/4] microblaze: add arch_print_bdinfo() implementation
Allow bdinfo command to print icache/dcache information:
U-Boot-mONStR> bdinfo
boot_params = 0x
DRAM bank = 0x
-> start= 0x0400
-> size = 0x0400
flashstart = 0x
flashsize = 0x
flashoffset = 0x
baudrate= 9600 bps
relocaddr = 0x07f76000
reloc off = 0x02f76000
Build = 32-bit
current eth = unknown
ethaddr = (not set)
IP addr =
fdt_blob= 0x07fec7e0
new_fdt = 0x
fdt_size= 0x
lmb_dump_all:
memory.cnt = 0x1
memory[0] [0x400-0x7ff], 0x0400 bytes flags: 0
reserved.cnt = 0x1
reserved[0][0x7e94b8c-0x7ff], 0x0016b474 bytes flags: 0
devicetree = embed
icache = 32 KiB
icache line = 4 Bytes
dcache = 32 KiB
dcache line = 4 Bytes
Signed-off-by: Ovidiu Panait
---
arch/microblaze/lib/Makefile | 1 +
arch/microblaze/lib/bdinfo.c | 24
2 files changed, 25 insertions(+)
create mode 100644 arch/microblaze/lib/bdinfo.c
diff --git a/arch/microblaze/lib/Makefile b/arch/microblaze/lib/Makefile
index 05f447abba..dfd8135f4f 100644
--- a/arch/microblaze/lib/Makefile
+++ b/arch/microblaze/lib/Makefile
@@ -4,4 +4,5 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BDI) += bdinfo.o
obj-y += muldi3.o
diff --git a/arch/microblaze/lib/bdinfo.c b/arch/microblaze/lib/bdinfo.c
new file mode 100644
index 00..41b7a216a4
--- /dev/null
+++ b/arch/microblaze/lib/bdinfo.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022, Ovidiu Panait
+ */
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void arch_print_bdinfo(void)
+{
+ struct microblaze_cpuinfo *ci = gd_cpuinfo();
+
+ if (ci->icache_size) {
+ bdinfo_print_size("icache", ci->icache_size);
+ bdinfo_print_size("icache line", ci->icache_line_length);
+ }
+
+ if (ci->dcache_size) {
+ bdinfo_print_size("dcache", ci->dcache_size);
+ bdinfo_print_size("dcache line", ci->dcache_line_length);
+ }
+}
--
2.25.1
[PATCH 3/4] cmd: bdinfo: introduce bdinfo_print_size() helper
Add bdinfo_print_size() helper to display size variables (such as cache
sizes) in bdinfo format. The size is printed as "xxx Bytes", "xxx KiB",
"xxx MiB", "xxx GiB", etc as needed;
Signed-off-by: Ovidiu Panait
---
cmd/bdinfo.c | 7 +++
include/init.h | 13 +
2 files changed, 20 insertions(+)
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 37cd8a57eb..9e23c4dd8f 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -16,9 +16,16 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
+void bdinfo_print_size(const char *name, uint64_t size)
+{
+ printf("%-12s= ", name);
+ print_size(size, "\n");
+}
+
void bdinfo_print_num_l(const char *name, ulong value)
{
printf("%-12s= 0x%0*lx\n", name, 2 * (int)sizeof(value), value);
diff --git a/include/init.h b/include/init.h
index 7b8f62c121..02bb4ce13e 100644
--- a/include/init.h
+++ b/include/init.h
@@ -343,6 +343,19 @@ void bdinfo_print_num_ll(const char *name, unsigned long
long value);
/* Print a clock speed in MHz */
void bdinfo_print_mhz(const char *name, unsigned long hz);
+/**
+ * bdinfo_print_size - print size variables in bdinfo format
+ * @name: string to print before the size
+ * @size: size to print
+ *
+ * Helper function for displaying size variables as properly formatted bdinfo
+ * entries. The size is printed as "xxx Bytes", "xxx KiB", "xxx MiB",
+ * "xxx GiB", etc. as needed;
+ *
+ * For use in arch_print_bdinfo().
+ */
+void bdinfo_print_size(const char *name, uint64_t size);
+
/* Show arch-specific information for the 'bd' command */
void arch_print_bdinfo(void);
--
2.25.1
[PATCH 2/4] cpu: microblaze: remove unused ret variable
Drop the unused ret variable from microblaze_cpu_get_desc(). Signed-off-by: Ovidiu Panait --- drivers/cpu/microblaze_cpu.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/cpu/microblaze_cpu.c b/drivers/cpu/microblaze_cpu.c index 969a1047e5..4eae06a8a6 100644 --- a/drivers/cpu/microblaze_cpu.c +++ b/drivers/cpu/microblaze_cpu.c @@ -88,15 +88,14 @@ static int microblaze_cpu_get_desc(const struct udevice *dev, char *buf, struct microblaze_cpuinfo *ci = gd_cpuinfo(); const char *cpu_ver, *fpga_family; u32 cpu_freq_mhz; - int ret; cpu_freq_mhz = ci->cpu_freq / 100; cpu_ver = microblaze_lookup_cpu_version_string(ci->ver_code); fpga_family = microblaze_lookup_fpga_family_string(ci->fpga_code); - ret = snprintf(buf, size, - "MicroBlaze @ %uMHz, Rev: %s, FPGA family: %s", - cpu_freq_mhz, cpu_ver, fpga_family); + snprintf(buf, size, +"MicroBlaze @ %uMHz, Rev: %s, FPGA family: %s", +cpu_freq_mhz, cpu_ver, fpga_family); return 0; } -- 2.25.1
[PATCH 1/4] microblaze: drop CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE
These macros don't seem to be used by microblaze code anymore, so remove them. Signed-off-by: Ovidiu Panait --- include/configs/microblaze-generic.h | 6 -- 1 file changed, 6 deletions(-) diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 8eaac4f8bc..dfae8cea7b 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -97,10 +97,4 @@ #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE -/* SP location before relocation, must use scratch RAM */ -/* BRAM start */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x0 -/* BRAM size - will be generated */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x10 - #endif /* __CONFIG_H */ -- 2.25.1
Re: [PATCH 1/2] microblaze: Convert axi timer to DM driver
Hi Michal,
On 6/8/22 13:38, Michal Simek wrote:
[...]
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 7b8ab56ed323..44d1a81bad3d 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -272,4 +272,12 @@ config IMX_GPT_TIMER
Select this to enable support for the timer found on
NXP i.MX devices.
+config XILINX_TIMER
+ bool "Xilinx timer support"
+ depends on TIMER
+ select REGMAP
Tested-by: Ovidiu Panait
I think the SPL select should also be added:
select SPL_REGMAP if SPL
This will fix the spl link errors with the following config:
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_XILINX_TIMER=y
...
microblazeel-linux-ld.bfd: drivers/timer/xilinx-timer.o: in function
`xilinx_timer_get_count':
drivers/timer/xilinx-timer.c:41: undefined reference to `regmap_read'
microblazeel-linux-ld.bfd: drivers/timer/xilinx-timer.o: in function
`xilinx_timer_probe':
drivers/timer/xilinx-timer.c:52: undefined reference to `regmap_init_mem'
microblazeel-linux-ld.bfd: drivers/timer/xilinx-timer.c:58: undefined
reference to `regmap_write'
microblazeel-linux-ld.bfd: drivers/timer/xilinx-timer.c:59: undefined
reference to `regmap_write'
microblazeel-linux-ld.bfd: drivers/timer/xilinx-timer.c:60: undefined
reference to `regmap_write'
make[1]: *** [scripts/Makefile.spl:525: spl/u-boot-spl] Error 1
Thanks,
Ovidiu
+ help
+ Select this to enable support for the timer found on
+ any Xilinx boards (axi timer).
+
endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index b2f002d59789..4d06375317e1 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -27,3 +27,4 @@ obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
obj-$(CONFIG_MCHP_PIT64B_TIMER)+= mchp-pit64b-timer.o
obj-$(CONFIG_IMX_GPT_TIMER)+= imx-gpt-timer.o
+obj-$(CONFIG_XILINX_TIMER) += xilinx-timer.o
diff --git a/drivers/timer/xilinx-timer.c b/drivers/timer/xilinx-timer.c
new file mode 100644
index ..75b4473b6397
--- /dev/null
+++ b/drivers/timer/xilinx-timer.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022 Advanced Micro Devices, Inc
+ * Michal Simek
+ *
+ * (C) Copyright 2007 Michal Simek
+ * Michal SIMEK
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define TIMER_ENABLE_ALL0x400 /* ENALL */
+#define TIMER_PWM 0x200 /* PWMA0 */
+#define TIMER_INTERRUPT 0x100 /* T0INT */
+#define TIMER_ENABLE0x080 /* ENT0 */
+#define TIMER_ENABLE_INTR 0x040 /* ENIT0 */
+#define TIMER_RESET 0x020 /* LOAD0 */
+#define TIMER_RELOAD0x010 /* ARHT0 */
+#define TIMER_EXT_CAPTURE 0x008 /* CAPT0 */
+#define TIMER_EXT_COMPARE 0x004 /* GENT0 */
+#define TIMER_DOWN_COUNT0x002 /* UDT0 */
+#define TIMER_CAPTURE_MODE 0x001 /* MDT0 */
+
+#define TIMER_CONTROL_OFFSET 0
+#define TIMER_LOADREG_OFFSET 4
+#define TIMER_COUNTER_OFFSET 8
+
+struct xilinx_timer_priv {
+ struct regmap *regs;
+};
+
+static u64 xilinx_timer_get_count(struct udevice *dev)
+{
+ struct xilinx_timer_priv *priv = dev_get_priv(dev);
+ u32 value;
+
+ regmap_read(priv->regs, TIMER_COUNTER_OFFSET, );
+
+ return value;
+}
+
+static int xilinx_timer_probe(struct udevice *dev)
+{
+ struct xilinx_timer_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ /* uc_priv->clock_rate has already clock rate */
+ ret = regmap_init_mem(dev_ofnode(dev), >regs);
+ if (ret) {
+ dev_dbg(dev, "failed to get regbase of timer\n");
+ return ret;
+ }
+
+ regmap_write(priv->regs, TIMER_LOADREG_OFFSET, 0);
+ regmap_write(priv->regs, TIMER_CONTROL_OFFSET, TIMER_RESET);
+ regmap_write(priv->regs, TIMER_CONTROL_OFFSET,
+TIMER_ENABLE | TIMER_RELOAD);
+
+ return 0;
+}
+
+static const struct timer_ops xilinx_timer_ops = {
+ .get_count = xilinx_timer_get_count,
+};
+
+static const struct udevice_id xilinx_timer_ids[] = {
+ { .compatible = "xlnx,xps-timer-1.00.a" },
+ {}
+};
+
+U_BOOT_DRIVER(xilinx_timer) = {
+ .name = "xilinx_timer",
+ .id = UCLASS_TIMER,
+ .of_match = xilinx_timer_ids,
+ .priv_auto = sizeof(struct xilinx_timer_priv),
+ .probe = xilinx_timer_probe,
+ .ops = _timer_ops,
+};
--
2.36.1
Re: [PATCH v2 01/14] cmd: cpu: migrate cpu command to U_BOOT_CMD_WITH_SUBCMDS()
Hi Michal, On 07.06.2022 11:33, Michal Simek wrote: [Please note: This e-mail is from an EXTERNAL e-mail address] út 31. 5. 2022 v 20:14 odesílatel Ovidiu Panait napsal: Migrate cpu command to use U_BOOT_CMD_WITH_SUBCMDS() helper macro, to reduce duplicated code. This also fixes the cpu command on boards that enable CONFIG_NEEDS_MANUAL_RELOC. Signed-off-by: Ovidiu Panait --- NOTE: this series depends on the following "events" patch: https://lore.kernel.org/u-boot/20220515184029.2169025-2-ovpan...@gmail.com/ [...] From my point of view this series looks good. I have sent v2 of mb conversion rela and I prefer to apply this on the top. There is actually one change needed bralid/brlid in one patch but I have already did it and test it on the HW. Will queue for the next u-boot version. Thanks for the feedback! Could you also take in the following event patch that fixes the pointers after relocation (the cpu driver makes use of the events feature)? Without this, in my testing the event handlers are not called at all after relocation: https://lore.kernel.org/u-boot/20220515184029.2169025-2-ovpan...@gmail.com/ It seems it is not currently applied to the 20220607-cache branch of u-boot-microblaze repo. Thanks! Ovidiu Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
[PATCH v2 14/14] cpu: add CPU driver for microblaze
Add a basic CPU driver that retrieves information about the microblaze CPU
core. cpu_ops handlers are implemented so that the "cpu" command can work
properly:
U-Boot-mONStR> cpu list
0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000
U-Boot-mONStR> cpu detail
0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000
ID = 0, freq = 50 MHz: L1 cache, MMU
Note: cpu_ver_lookup[] and family_string_lookup[] arrays were imported from
linux.
Signed-off-by: Ovidiu Panait
---
Changes in v2:
- Refactored completely.
- Fixed v9.X version codes.
- Added support for cross-checking PVR and static data.
- Added support for "cpu" command.
arch/microblaze/cpu/cpuinfo.c | 111
arch/microblaze/include/asm/cpuinfo.h | 79 +++
drivers/cpu/Kconfig | 9 ++
drivers/cpu/Makefile | 1 +
drivers/cpu/microblaze_cpu.c | 180 ++
5 files changed, 380 insertions(+)
create mode 100644 drivers/cpu/microblaze_cpu.c
diff --git a/arch/microblaze/cpu/cpuinfo.c b/arch/microblaze/cpu/cpuinfo.c
index 3f0b1d2c04..f021f4e5e2 100644
--- a/arch/microblaze/cpu/cpuinfo.c
+++ b/arch/microblaze/cpu/cpuinfo.c
@@ -8,6 +8,117 @@
DECLARE_GLOBAL_DATA_PTR;
+#if CONFIG_IS_ENABLED(CPU_MICROBLAZE)
+/* These key value are as per MBV field in PVR0 */
+static const struct microblaze_version_map cpu_ver_lookup[] = {
+ {"5.00.a", 0x01},
+ {"5.00.b", 0x02},
+ {"5.00.c", 0x03},
+ {"6.00.a", 0x04},
+ {"6.00.b", 0x06},
+ {"7.00.a", 0x05},
+ {"7.00.b", 0x07},
+ {"7.10.a", 0x08},
+ {"7.10.b", 0x09},
+ {"7.10.c", 0x0a},
+ {"7.10.d", 0x0b},
+ {"7.20.a", 0x0c},
+ {"7.20.b", 0x0d},
+ {"7.20.c", 0x0e},
+ {"7.20.d", 0x0f},
+ {"7.30.a", 0x10},
+ {"7.30.b", 0x11},
+ {"8.00.a", 0x12},
+ {"8.00.b", 0x13},
+ {"8.10.a", 0x14},
+ {"8.20.a", 0x15},
+ {"8.20.b", 0x16},
+ {"8.30.a", 0x17},
+ {"8.40.a", 0x18},
+ {"8.40.b", 0x19},
+ {"8.50.a", 0x1a},
+ {"8.50.b", 0x1c},
+ {"8.50.c", 0x1e},
+ {"9.0", 0x1b},
+ {"9.1", 0x1d},
+ {"9.2", 0x1f},
+ {"9.3", 0x20},
+ {"9.4", 0x21},
+ {"9.5", 0x22},
+ {"9.6", 0x23},
+ {"10.0", 0x24},
+ {"11.0", 0x25},
+ {NULL, 0},
+};
+
+static const struct microblaze_version_map family_string_lookup[] = {
+ {"virtex2", 0x4},
+ {"virtex2pro", 0x5},
+ {"spartan3", 0x6},
+ {"virtex4", 0x7},
+ {"virtex5", 0x8},
+ {"spartan3e", 0x9},
+ {"spartan3a", 0xa},
+ {"spartan3an", 0xb},
+ {"spartan3adsp", 0xc},
+ {"spartan6", 0xd},
+ {"virtex6", 0xe},
+ {"virtex7", 0xf},
+ /* FIXME There is no key code defined for spartan2 */
+ {"spartan2", 0xf0},
+ {"kintex7", 0x10},
+ {"artix7", 0x11},
+ {"zynq7000", 0x12},
+ {"UltraScale Virtex", 0x13},
+ {"UltraScale Kintex", 0x14},
+ {"UltraScale+ Zynq", 0x15},
+ {"UltraScale+ Virtex", 0x16},
+ {"UltraScale+ Kintex", 0x17},
+ {"Spartan7", 0x18},
+ {NULL, 0},
+};
+
+static const char *lookup_string(u32 code,
+const struct microblaze_version_map *entry)
+{
+ for (; entry->string; ++entry)
+ if (entry->code == code)
+ return entry->string;
+
+ return "(unknown)";
+}
+
+static const u32 lookup_code(const char *string,
+const struct microblaze_version_map *entry)
+{
+ for (; entry->string; ++entry)
+ if (!strcmp(entry->string, string))
+ return entry->code;
+
+ return 0;
+}
+
+const char *microblaze_lookup_fpga_family_string(const u32 code)
+{
+ return lookup_string(code, family_string_lookup);
+}
+
+const char *microblaze_lookup_cpu_version_string(const u32 code)
+{
+ return lookup_string(code, cpu_ver_lookup);
+}
+
+const u32 microblaze_lookup_fpga_family_code(const char *string)
+{
+ return lookup_code(string, family_string_lookup);
+}
+
+const u32 microblaze_lookup_cpu_version_code(const char *string)
+{
+ return lookup_code(string, cpu_ver_lookup);
+}
+#endif /* CONFIG_CPU_MICROBLAZE */
+
void microblaz
[PATCH v2 12/14] microblaze: Kconfig: introduce XILINX_MICROBLAZE0_FPGA_FAMILY option
Provide a static Kconfig value for the target FPGA archtitecture, as it is done in Linux. The cpu-uclass driver will cross-check it with the value read from PVR10 register. Signed-off-by: Ovidiu Panait --- Changes in v2: - New patch. board/xilinx/microblaze-generic/Kconfig | 8 1 file changed, 8 insertions(+) diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig index a6743cadf4..90f79cfb94 100644 --- a/board/xilinx/microblaze-generic/Kconfig +++ b/board/xilinx/microblaze-generic/Kconfig @@ -38,6 +38,14 @@ config XILINX_MICROBLAZE0_HW_VER string "Core version number" default "7.10.d" +config XILINX_MICROBLAZE0_FPGA_FAMILY + string "Targeted FPGA family" + default "virtex5" + help + This option contains info about the target FPGA architecture + (Zynq-7000, UltraScale+ Kintex, etc) that the MicroBlaze soft core is + implemented on. It corresponds to the C_FAMILY hdl parameter. + config XILINX_MICROBLAZE0_USR_EXCEP bool "MicroBlaze user exception support" default y -- 2.25.1
[PATCH v2 13/14] microblaze: add support for handling PVR data
Add helper code for PVR (Processor Version Register) data handling. It
will be used by the UCLASS_CPU driver to populate cpuinfo fields at
runtime.
Signed-off-by: Ovidiu Panait
---
Changes in v2:
- New patch.
arch/microblaze/cpu/Makefile| 1 +
arch/microblaze/cpu/pvr.c | 41 ++
arch/microblaze/include/asm/pvr.h | 75 +
board/xilinx/microblaze-generic/Kconfig | 8 +++
4 files changed, 125 insertions(+)
create mode 100644 arch/microblaze/cpu/pvr.c
create mode 100644 arch/microblaze/include/asm/pvr.h
diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile
index 5388a21550..96eb40f6f2 100644
--- a/arch/microblaze/cpu/Makefile
+++ b/arch/microblaze/cpu/Makefile
@@ -6,4 +6,5 @@
extra-y= start.o
obj-y = irq.o
obj-y += interrupts.o cache.o exception.o timer.o cpuinfo.o
+obj-$(CONFIG_XILINX_MICROBLAZE0_PVR) += pvr.o
obj-$(CONFIG_SPL_BUILD)+= spl.o
diff --git a/arch/microblaze/cpu/pvr.c b/arch/microblaze/cpu/pvr.c
new file mode 100644
index 00..23c0f912d4
--- /dev/null
+++ b/arch/microblaze/cpu/pvr.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022, Ovidiu Panait
+ */
+#include
+#include
+#include
+
+int microblaze_cpu_has_pvr_full(void)
+{
+ u32 msr, pvr0;
+
+ MFS(msr, rmsr);
+ if (!(msr & PVR_MSR_BIT))
+ return 0;
+
+ get_pvr(0, pvr0);
+ debug("%s: pvr0 is 0x%08x\n", __func__, pvr0);
+
+ if (!(pvr0 & PVR0_PVR_FULL_MASK))
+ return 0;
+
+ return 1;
+}
+
+void microblaze_get_all_pvrs(u32 pvr[PVR_FULL_COUNT])
+{
+ get_pvr(0, pvr[0]);
+ get_pvr(1, pvr[1]);
+ get_pvr(2, pvr[2]);
+ get_pvr(3, pvr[3]);
+ get_pvr(4, pvr[4]);
+ get_pvr(5, pvr[5]);
+ get_pvr(6, pvr[6]);
+ get_pvr(7, pvr[7]);
+ get_pvr(8, pvr[8]);
+ get_pvr(9, pvr[9]);
+ get_pvr(10, pvr[10]);
+ get_pvr(11, pvr[11]);
+ get_pvr(12, pvr[12]);
+}
diff --git a/arch/microblaze/include/asm/pvr.h
b/arch/microblaze/include/asm/pvr.h
new file mode 100644
index 00..bfe159af79
--- /dev/null
+++ b/arch/microblaze/include/asm/pvr.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022, Ovidiu Panait
+ */
+
+#ifndef __ASM_MICROBLAZE_PVR_H
+#define __ASM_MICROBLAZE_PVR_H
+
+#include
+
+#define PVR_FULL_COUNT 13 /* PVR0 - PVR12 */
+
+#define __get_pvr(val, reg)\
+ __asm__ __volatile__ ("mfs %0," #reg : "=r" (val) :: "memory")
+#define get_pvr(pvrid, val)\
+ __get_pvr(val, rpvr ## pvrid)
+
+#define PVR_MSR_BIT0x0400
+
+/* PVR0 masks */
+#define PVR0_PVR_FULL_MASK 0x8000
+#define PVR0_VERSION_MASK 0xFF00
+
+/* PVR4 masks - ICache configs */
+#define PVR4_ICACHE_LINE_LEN_MASK 0x00E0 /* ICLL */
+#define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F /* ICBS */
+
+/* PVR5 masks - DCache configs */
+#define PVR5_DCACHE_LINE_LEN_MASK 0x00E0 /* DCLL */
+#define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F /* DCBS */
+
+/* PVR10 masks - FPGA family */
+#define PVR10_TARGET_FAMILY_MASK 0xFF00
+
+/* PVR11 masks - MMU */
+#define PVR11_USE_MMU 0xC000
+
+/* PVR access macros */
+#define PVR_VERSION(pvr) \
+ ((pvr[0] & PVR0_VERSION_MASK) >> 8)
+
+#define PVR_ICACHE_LINE_LEN(pvr) \
+ ((1 << ((pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21)) << 2)
+#define PVR_ICACHE_BYTE_SIZE(pvr) \
+ (1 << ((pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
+
+#define PVR_DCACHE_LINE_LEN(pvr) \
+ ((1 << ((pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21)) << 2)
+#define PVR_DCACHE_BYTE_SIZE(pvr) \
+ (1 << ((pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
+
+#define PVR_USE_MMU(pvr) \
+ ((pvr[11] & PVR11_USE_MMU) >> 30)
+
+#define PVR_TARGET_FAMILY(pvr) \
+ ((pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24)
+
+/**
+ * microblaze_cpu_has_pvr_full() - Check for full PVR support
+ *
+ * Check MSR register for PVR support and, if applicable, check the PVR0
+ * register for full PVR support.
+ *
+ * Return: 1 if there is full PVR support, 0 otherwise.
+ */
+int microblaze_cpu_has_pvr_full(void);
+
+/**
+ * microblaze_get_all_pvrs() - Copy PVR0-PVR12 to destination array
+ *
+ * @pvr: destination array of size PVR_FULL_COUNT
+ */
+void microblaze_get_all_pvrs(u32 pvr[PVR_FULL_COUNT]);
+
+#endif /* __ASM_MICROBLAZE_PVR_H
[PATCH v2 10/14] microblaze: cache: introduce cpuinfo structure
Introduce a minimal cpuinfo structure to hold cache related info. The
instruction/data cache size and cache line size are initialized early in
the boot to default Kconfig values. They will be overwritten with data
from PVR/dtb if the microblaze UCLASS_CPU driver is enabled.
The cpuinfo struct was placed in global_data to allow the microblaze
UCLASS_CPU driver to also run before relocation (initialized global data
should be read-only before relocation).
gd_cpuinfo() helper macro was added to avoid volatile
"-Wdiscarded-qualifiers" warnings when using the pointer directly.
Signed-off-by: Ovidiu Panait
---
Changes in v2:
- New patch.
arch/microblaze/cpu/Makefile | 2 +-
arch/microblaze/cpu/cache.c | 14 ++---
arch/microblaze/cpu/cpuinfo.c | 20 +
arch/microblaze/cpu/start.S | 7 +
arch/microblaze/include/asm/cpuinfo.h | 35 +++
arch/microblaze/include/asm/global_data.h | 5
6 files changed, 78 insertions(+), 5 deletions(-)
create mode 100644 arch/microblaze/cpu/cpuinfo.c
create mode 100644 arch/microblaze/include/asm/cpuinfo.h
diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile
index f7a83d07b6..5388a21550 100644
--- a/arch/microblaze/cpu/Makefile
+++ b/arch/microblaze/cpu/Makefile
@@ -5,5 +5,5 @@
extra-y= start.o
obj-y = irq.o
-obj-y += interrupts.o cache.o exception.o timer.o
+obj-y += interrupts.o cache.o exception.o timer.o cpuinfo.o
obj-$(CONFIG_SPL_BUILD)+= spl.o
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index b99b8c1706..cd8507901d 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -9,11 +9,16 @@
#include
#include
#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
static void __invalidate_icache(ulong addr, ulong size)
{
if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WIC)) {
- for (int i = 0; i < size; i += 4) {
+ for (int i = 0; i < size;
+i += gd_cpuinfo()->icache_line_length) {
asm volatile (
"wic%0, r0;"
"nop;"
@@ -26,13 +31,14 @@ static void __invalidate_icache(ulong addr, ulong size)
void invalidate_icache_all(void)
{
- __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE);
+ __invalidate_icache(0, gd_cpuinfo()->icache_size);
}
static void __flush_dcache(ulong addr, ulong size)
{
if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) {
- for (int i = 0; i < size; i += 4) {
+ for (int i = 0; i < size;
+i += gd_cpuinfo()->dcache_line_length) {
asm volatile (
"wdc.flush %0, r0;"
"nop;"
@@ -45,7 +51,7 @@ static void __flush_dcache(ulong addr, ulong size)
void flush_dcache_all(void)
{
- __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE);
+ __flush_dcache(0, gd_cpuinfo()->dcache_size);
}
int dcache_status(void)
diff --git a/arch/microblaze/cpu/cpuinfo.c b/arch/microblaze/cpu/cpuinfo.c
new file mode 100644
index 00..3f0b1d2c04
--- /dev/null
+++ b/arch/microblaze/cpu/cpuinfo.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022, Ovidiu Panait
+ */
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void microblaze_early_cpuinfo_init(void)
+{
+ struct microblaze_cpuinfo *ci = gd_cpuinfo();
+
+ ci->icache_size = CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE;
+ ci->icache_line_length = 4;
+
+ ci->dcache_size = CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE;
+ ci->dcache_line_length = 4;
+}
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 7f7b5f5cb5..ad400a4be5 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -51,6 +51,13 @@ _start:
nop
#endif
+ /*
+* Initialize global data cpuinfo with default values (cache
+* size, cache line size, etc).
+*/
+ bralid r15, microblaze_early_cpuinfo_init
+ nop
+
/* Flush cache before enable cache */
bralid r15, flush_cache_all
nop
diff --git a/arch/microblaze/include/asm/cpuinfo.h
b/arch/microblaze/include/asm/cpuinfo.h
new file mode 100644
index 00..c27dd40af7
--- /dev/null
+++ b/arch/microblaze/include/asm/cpuinfo.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022, Ovidiu Panait
+ */
+
+#ifndef __ASM_MICROBLAZE_CPUINFO_H
+#define __ASM_MICROBLAZE_CPUINFO_H
+
+/**
+ * struct microblaze_cpuinfo - CPU info for microblaze processor core.
+ *
+ * @icache_size: Size of instruction cache memory in bytes.
+ * @icache_line_length: Instruction cache line length in bytes.
+ * @dcache_siz
[PATCH v2 09/14] microblaze: cache: introduce flush_cache_all()
All flush_cache() calls in microblaze code are supposed to flush the
entire instruction and data caches, so introduce flush_cache_all()
helper to handle this.
Also, provide implementations for flush_dcache_all() and
invalidate_icache_all() so that icache and dcache u-boot commands can
work.
Signed-off-by: Ovidiu Panait
---
Changes in v2:
- adjusted for newly added CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE and
CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE Kconfig symbols
arch/microblaze/cpu/cache.c | 20 ++--
arch/microblaze/cpu/start.S | 8 ++--
arch/microblaze/include/asm/cache.h | 5 +
arch/microblaze/lib/bootm.c | 2 +-
4 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index d5c0afd935..b99b8c1706 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -24,6 +24,11 @@ static void __invalidate_icache(ulong addr, ulong size)
}
}
+void invalidate_icache_all(void)
+{
+ __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE);
+}
+
static void __flush_dcache(ulong addr, ulong size)
{
if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) {
@@ -38,6 +43,11 @@ static void __flush_dcache(ulong addr, ulong size)
}
}
+void flush_dcache_all(void)
+{
+ __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE);
+}
+
int dcache_status(void)
{
int i = 0;
@@ -65,7 +75,7 @@ void icache_enable(void)
void icache_disable(void)
{
- __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE);
+ invalidate_icache_all();
MSRCLR(0x20);
}
@@ -77,7 +87,7 @@ void dcache_enable(void)
void dcache_disable(void)
{
- __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE);
+ flush_dcache_all();
MSRCLR(0x80);
}
@@ -87,3 +97,9 @@ void flush_cache(ulong addr, ulong size)
__invalidate_icache(addr, size);
__flush_dcache(addr, size);
}
+
+void flush_cache_all(void)
+{
+ invalidate_icache_all();
+ flush_dcache_all();
+}
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 356ca05392..7f7b5f5cb5 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -52,9 +52,7 @@ _start:
#endif
/* Flush cache before enable cache */
- addik r5, r0, 0
- addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE
- bralid r15, flush_cache
+ bralid r15, flush_cache_all
nop
/* enable instruction and data cache */
@@ -283,9 +281,7 @@ relocate_code:
addkr20, r20, r23
/* Flush caches to ensure consistency */
- addik r5, r0, 0
- addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE
- bralid r15, flush_cache
+ bralid r15, flush_cache_all
nop
2: addir5, r31, 0 /* gd is initialized in board_r.c */
diff --git a/arch/microblaze/include/asm/cache.h
b/arch/microblaze/include/asm/cache.h
index baee01a0e2..c39b66dd7d 100644
--- a/arch/microblaze/include/asm/cache.h
+++ b/arch/microblaze/include/asm/cache.h
@@ -18,4 +18,9 @@
#define ARCH_DMA_MINALIGN 16
#endif
+/**
+ * flush_cache_all - flush the entire instruction/data caches
+ */
+void flush_cache_all(void);
+
#endif /* __MICROBLAZE_CACHE_H__ */
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index 48e05333a6..af946b8642 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -57,7 +57,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
"(fake run for tracing)" : "");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
- flush_cache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE);
+ flush_cache_all();
if (!fake) {
/*
--
2.25.1
[PATCH v2 08/14] microblaze: cache: introduce Kconfig options for icache/dcache sizes
Replace XILINX_DCACHE_BYTE_SIZE macro with two Kconfig symbols for
instruction and data caches sizes, respectively:
CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE
CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE
Also, get rid of the hardcoded value in icache_disable().
Signed-off-by: Ovidiu Panait
---
Changes in v2:
- added separate Kconfig symbols for icache/dcache
arch/microblaze/cpu/cache.c | 5 ++---
arch/microblaze/cpu/start.S | 4 ++--
arch/microblaze/lib/bootm.c | 2 +-
board/xilinx/microblaze-generic/Kconfig | 16
include/configs/microblaze-generic.h| 4
5 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index e362a34a79..d5c0afd935 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -65,8 +65,7 @@ void icache_enable(void)
void icache_disable(void)
{
- /* we are not generate ICACHE size -> flush whole cache */
- __invalidate_icache(0, 32768);
+ __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE);
MSRCLR(0x20);
}
@@ -78,7 +77,7 @@ void dcache_enable(void)
void dcache_disable(void)
{
- __flush_dcache(0, XILINX_DCACHE_BYTE_SIZE);
+ __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE);
MSRCLR(0x80);
}
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index d1b0453caf..356ca05392 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -53,7 +53,7 @@ _start:
/* Flush cache before enable cache */
addik r5, r0, 0
- addik r6, r0, XILINX_DCACHE_BYTE_SIZE
+ addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE
bralid r15, flush_cache
nop
@@ -284,7 +284,7 @@ relocate_code:
/* Flush caches to ensure consistency */
addik r5, r0, 0
- addik r6, r0, XILINX_DCACHE_BYTE_SIZE
+ addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE
bralid r15, flush_cache
nop
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index dba6226ce5..48e05333a6 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -57,7 +57,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
"(fake run for tracing)" : "");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
- flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
+ flush_cache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE);
if (!fake) {
/*
diff --git a/board/xilinx/microblaze-generic/Kconfig
b/board/xilinx/microblaze-generic/Kconfig
index 98b4814b95..a6743cadf4 100644
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -85,4 +85,20 @@ config SPL_XILINX_MICROBLAZE0_USE_WIC
bool
default XILINX_MICROBLAZE0_USE_WIC
+config XILINX_MICROBLAZE0_DCACHE_SIZE
+ int "Default data cache size"
+ default 32768
+ help
+ This fallback size will be used when no dcache info can be found in
+ the device tree, or when the data cache is flushed very early in the
+ boot process, before device tree is available.
+
+config XILINX_MICROBLAZE0_ICACHE_SIZE
+ int "Default instruction cache size"
+ default 32768
+ help
+ This fallback size will be used when no icache info can be found in
+ the device tree, or when the instruction cache is flushed very early
+ in the boot process, before device tree is available.
+
endif
diff --git a/include/configs/microblaze-generic.h
b/include/configs/microblaze-generic.h
index 663837f33d..7b064eacb2 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -30,10 +30,6 @@
# define CONFIG_SYS_MAX_FLASH_SECT 2048
#endif
-#ifndef XILINX_DCACHE_BYTE_SIZE
-#define XILINX_DCACHE_BYTE_SIZE32768
-#endif
-
/* size of console buffer */
#defineCONFIG_SYS_CBSIZE 512
/* max number of command args */
--
2.25.1
[PATCH v2 11/14] microblaze: cache: introduce flush_dcache_range()
Align microblaze with the other architectures and provide an
implementation for flush_dcache_range(). Also, remove the microblaze
exception in drivers/core/device.c.
Signed-off-by: Ovidiu Panait
---
Changes in v2:
- Added debug message for invalid range.
arch/microblaze/cpu/cache.c | 11 +++
drivers/core/device.c | 5 -
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index cd8507901d..829e6c7ae6 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -49,6 +49,17 @@ static void __flush_dcache(ulong addr, ulong size)
}
}
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+ if (start >= end) {
+ debug("Invalid dcache range - start: 0x%08lx end: 0x%08lx\n",
+ start, end);
+ return;
+ }
+
+ __flush_dcache(start, end - start);
+}
+
void flush_dcache_all(void)
{
__flush_dcache(0, gd_cpuinfo()->dcache_size);
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 3ab2583df3..03155e9867 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -328,13 +328,8 @@ static void *alloc_priv(int size, uint flags)
* within this range at the start. The driver can then
* use normal flush-after-write, invalidate-before-read
* procedures.
-*
-* TODO(s...@chromium.org): Drop this microblaze
-* exception.
*/
-#ifndef CONFIG_MICROBLAZE
flush_dcache_range((ulong)priv, (ulong)priv + size);
-#endif
}
} else {
priv = calloc(1, size);
--
2.25.1
[PATCH v2 07/14] microblaze: cache: split flush_cache() function
Factor out icache/dcache components from flush_cache() function. Call the
newly added __flush_icache()/__flush_dcache() functions inside
icache_disable() and dcache_disable(), respectively. There is no need to
flush both caches when disabling a particular cache type.
Signed-off-by: Ovidiu Panait
---
(no changes since v1)
arch/microblaze/cpu/cache.c | 55 ++---
1 file changed, 33 insertions(+), 22 deletions(-)
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index b6bbc215b3..e362a34a79 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -10,6 +10,34 @@
#include
#include
+static void __invalidate_icache(ulong addr, ulong size)
+{
+ if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WIC)) {
+ for (int i = 0; i < size; i += 4) {
+ asm volatile (
+ "wic%0, r0;"
+ "nop;"
+ :
+ : "r" (addr + i)
+ : "memory");
+ }
+ }
+}
+
+static void __flush_dcache(ulong addr, ulong size)
+{
+ if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) {
+ for (int i = 0; i < size; i += 4) {
+ asm volatile (
+ "wdc.flush %0, r0;"
+ "nop;"
+ :
+ : "r" (addr + i)
+ : "memory");
+ }
+ }
+}
+
int dcache_status(void)
{
int i = 0;
@@ -38,7 +66,8 @@ void icache_enable(void)
void icache_disable(void)
{
/* we are not generate ICACHE size -> flush whole cache */
- flush_cache(0, 32768);
+ __invalidate_icache(0, 32768);
+
MSRCLR(0x20);
}
@@ -49,31 +78,13 @@ void dcache_enable(void)
void dcache_disable(void)
{
- flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
+ __flush_dcache(0, XILINX_DCACHE_BYTE_SIZE);
MSRCLR(0x80);
}
void flush_cache(ulong addr, ulong size)
{
- int i;
- for (i = 0; i < size; i += 4) {
- if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WIC)) {
- asm volatile (
- "wic%0, r0;"
- "nop;"
- :
- : "r" (addr + i)
- : "memory");
- }
-
- if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) {
- asm volatile (
- "wdc.flush %0, r0;"
- "nop;"
- :
- : "r" (addr + i)
- : "memory");
- }
- }
+ __invalidate_icache(addr, size);
+ __flush_dcache(addr, size);
}
--
2.25.1
[PATCH v2 06/14] microblaze: cache: improve icache Kconfig options
Replace CONFIG_ICACHE with a Kconfig option more limited in scope -
XILINX_MICROBLAZE0_USE_WIC. It should be enabled if the processor supports
the "wic" (Write to Instruction Cache) instruction. It will be used to
guard "wic" invocations in microblaze cache code.
Signed-off-by: Ovidiu Panait
---
Changes in v2:
- added CONFIG_SPL_XILINX_MICROBLAZE0_USE_WIC symbol
arch/microblaze/Kconfig | 4
arch/microblaze/cpu/cache.c | 6 +++---
board/xilinx/microblaze-generic/Kconfig | 11 +++
3 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 5a2e91104f..a25a95a013 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -25,10 +25,6 @@ config TARGET_MICROBLAZE_GENERIC
endchoice
-config ICACHE
- bool "Enable icache support"
- default y
-
source "board/xilinx/Kconfig"
source "board/xilinx/microblaze-generic/Kconfig"
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index 4e8e228a22..b6bbc215b3 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -58,14 +58,14 @@ void flush_cache(ulong addr, ulong size)
{
int i;
for (i = 0; i < size; i += 4) {
- asm volatile (
-#ifdef CONFIG_ICACHE
+ if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WIC)) {
+ asm volatile (
"wic%0, r0;"
-#endif
"nop;"
:
: "r" (addr + i)
: "memory");
+ }
if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) {
asm volatile (
diff --git a/board/xilinx/microblaze-generic/Kconfig
b/board/xilinx/microblaze-generic/Kconfig
index b00ce6f59a..98b4814b95 100644
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -74,4 +74,15 @@ config SPL_XILINX_MICROBLAZE0_USE_WDC
bool
default XILINX_MICROBLAZE0_USE_WDC
+config XILINX_MICROBLAZE0_USE_WIC
+ bool "MicroBlaze wic instruction support"
+ default y
+ help
+ Enable this option if the MicroBlaze processor is configured with
+ support for the "wic" (Write to Instruction Cache) instruction.
+
+config SPL_XILINX_MICROBLAZE0_USE_WIC
+ bool
+ default XILINX_MICROBLAZE0_USE_WIC
+
endif
--
2.25.1
[PATCH v2 05/14] microblaze: cache: improve dcache Kconfig options
Replace CONFIG_DCACHE with a Kconfig option more limited in scope -
XILINX_MICROBLAZE0_USE_WDC. It should be enabled if the processor supports
the "wdc" (Write to Data Cache) instruction. It will be used to guard
"wdc" invocations in microblaze cache code.
Also, drop all ifdefs around flush_cache() calls and only keep one
CONFIG_IS_ENABLED() guard within flush_cache() itself.
Signed-off-by: Ovidiu Panait
---
Changes in v2:
- added CONFIG_SPL_XILINX_MICROBLAZE0_USE_WDC symbol
arch/microblaze/Kconfig | 4
arch/microblaze/cpu/cache.c | 15 ++-
arch/microblaze/lib/bootm.c | 2 --
board/xilinx/microblaze-generic/Kconfig | 11 +++
4 files changed, 21 insertions(+), 11 deletions(-)
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index d7d1b21970..5a2e91104f 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -25,10 +25,6 @@ config TARGET_MICROBLAZE_GENERIC
endchoice
-config DCACHE
- bool "Enable dcache support"
- default y
-
config ICACHE
bool "Enable icache support"
default y
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index b6126de194..4e8e228a22 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -49,26 +49,31 @@ void dcache_enable(void)
void dcache_disable(void)
{
-#ifdef CONFIG_DCACHE
flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
-#endif
+
MSRCLR(0x80);
}
void flush_cache(ulong addr, ulong size)
{
int i;
- for (i = 0; i < size; i += 4)
+ for (i = 0; i < size; i += 4) {
asm volatile (
#ifdef CONFIG_ICACHE
"wic%0, r0;"
#endif
"nop;"
-#ifdef CONFIG_DCACHE
+ :
+ : "r" (addr + i)
+ : "memory");
+
+ if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) {
+ asm volatile (
"wdc.flush %0, r0;"
-#endif
"nop;"
:
: "r" (addr + i)
: "memory");
+ }
+ }
}
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index b652d2767a..dba6226ce5 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -57,9 +57,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
"(fake run for tracing)" : "");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
-#ifdef CONFIG_DCACHE
flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
-#endif
if (!fake) {
/*
diff --git a/board/xilinx/microblaze-generic/Kconfig
b/board/xilinx/microblaze-generic/Kconfig
index 117b476f3f..b00ce6f59a 100644
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -63,4 +63,15 @@ config XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
Memory address location of the exception vector table. It is
configurable via the C_BASE_VECTORS hdl parameter.
+config XILINX_MICROBLAZE0_USE_WDC
+ bool "MicroBlaze wdc instruction support"
+ default y
+ help
+ Enable this option if the MicroBlaze processor is configured with
+ support for the "wdc" (Write to Data Cache) instruction.
+
+config SPL_XILINX_MICROBLAZE0_USE_WDC
+ bool
+ default XILINX_MICROBLAZE0_USE_WDC
+
endif
--
2.25.1
[PATCH v2 03/14] microblaze: start.S: remove unused code
in16/out16 routines seem to not be used anywhere in microblaze code, so remove them. Signed-off-by: Ovidiu Panait --- (no changes since v1) arch/microblaze/cpu/start.S | 33 - 1 file changed, 33 deletions(-) diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 645f7cb038..d1b0453caf 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -220,39 +220,6 @@ __setup_exceptions: or r0, r0, r0 .end__setup_exceptions -/* - * Read 16bit little endian - */ - .text - .global in16 - .entin16 - .align 2 -in16: lhu r3, r0, r5 - bslli r4, r3, 8 - bsrli r3, r3, 8 - andir4, r4, 0x - or r3, r3, r4 - rtsdr15, 8 - sext16 r3, r3 - .endin16 - -/* - * Write 16bit little endian - * first parameter(r5) - address, second(r6) - short value - */ - .text - .global out16 - .entout16 - .align 2 -out16: bslli r3, r6, 8 - bsrli r6, r6, 8 - andir3, r3, 0x - or r3, r3, r6 - sh r3, r0, r5 - rtsdr15, 8 - or r0, r0, r0 - .endout16 - /* * Relocate u-boot */ -- 2.25.1
[PATCH v2 04/14] microblaze: cache: replace XILINX_USE_DCACHE -> CONFIG_DCACHE
XILINX_USE_DCACHE macro was removed in 7556fa09e0e ("microblaze: Simplify
cache handling"), but it was still used in a couple of places.
Replace those occurences with CONFIG_DCACHE.
Signed-off-by: Ovidiu Panait
---
(no changes since v1)
arch/microblaze/cpu/cache.c | 2 +-
arch/microblaze/lib/bootm.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index aa832d6be6..b6126de194 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -49,7 +49,7 @@ void dcache_enable(void)
void dcache_disable(void)
{
-#ifdef XILINX_USE_DCACHE
+#ifdef CONFIG_DCACHE
flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
#endif
MSRCLR(0x80);
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index 12ea32488e..b652d2767a 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -57,7 +57,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
"(fake run for tracing)" : "");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
-#ifdef XILINX_USE_DCACHE
+#ifdef CONFIG_DCACHE
flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
#endif
--
2.25.1
[PATCH v2 01/14] cmd: cpu: migrate cpu command to U_BOOT_CMD_WITH_SUBCMDS()
Migrate cpu command to use U_BOOT_CMD_WITH_SUBCMDS() helper macro, to
reduce duplicated code. This also fixes the cpu command on boards that
enable CONFIG_NEEDS_MANUAL_RELOC.
Signed-off-by: Ovidiu Panait
---
NOTE: this series depends on the following "events" patch:
https://lore.kernel.org/u-boot/20220515184029.2169025-2-ovpan...@gmail.com/
Changes in v2:
- New patch.
cmd/cpu.c | 39 ---
1 file changed, 8 insertions(+), 31 deletions(-)
diff --git a/cmd/cpu.c b/cmd/cpu.c
index 67dbb044b5..2ca4d05ae8 100644
--- a/cmd/cpu.c
+++ b/cmd/cpu.c
@@ -82,36 +82,13 @@ static int do_cpu_detail(struct cmd_tbl *cmdtp, int flag,
int argc,
return 0;
}
-static struct cmd_tbl cmd_cpu_sub[] = {
- U_BOOT_CMD_MKENT(list, 2, 1, do_cpu_list, "", ""),
- U_BOOT_CMD_MKENT(detail, 4, 0, do_cpu_detail, "", ""),
-};
-
-/*
- * Process a cpu sub-command
- */
-static int do_cpu(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- struct cmd_tbl *c = NULL;
-
- /* Strip off leading 'cpu' command argument */
- argc--;
- argv++;
-
- if (argc)
- c = find_cmd_tbl(argv[0], cmd_cpu_sub,
-ARRAY_SIZE(cmd_cpu_sub));
-
- if (c)
- return c->cmd(cmdtp, flag, argc, argv);
- else
- return CMD_RET_USAGE;
-}
-
-U_BOOT_CMD(
- cpu, 2, 1, do_cpu,
- "display information about CPUs",
+#if CONFIG_IS_ENABLED(SYS_LONGHELP)
+static char cpu_help_text[] =
"list - list available CPUs\n"
"cpu detail - show CPU detail"
-);
+ ;
+#endif
+
+U_BOOT_CMD_WITH_SUBCMDS(cpu, "display information about CPUs", cpu_help_text,
+ U_BOOT_SUBCMD_MKENT(list, 1, 1, do_cpu_list),
+ U_BOOT_SUBCMD_MKENT(detail, 1, 0, do_cpu_detail));
--
2.25.1
[PATCH v2 02/14] cpu-uclass: relocate ops pointers for CONFIG_NEEDS_MANUAL_RELOC
Relocate cpu_ops pointers when CONFIG_NEEDS_MANUAL_RELOC is enabled.
The (gd->flags & GD_FLG_RELOC) check was added to make sure the reloc_done
logic works for drivers that use DM_FLAG_PRE_RELOC.
Signed-off-by: Ovidiu Panait
---
Changes in v2:
- New patch.
drivers/cpu/cpu-uclass.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c
index a5cda6a62c..71e5900d70 100644
--- a/drivers/cpu/cpu-uclass.c
+++ b/drivers/cpu/cpu-uclass.c
@@ -14,6 +14,9 @@
#include
#include
#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
int cpu_probe_all(void)
{
@@ -136,9 +139,36 @@ static int uclass_cpu_init(struct uclass *uc)
return ret;
}
+static int uclass_cpu_post_bind(struct udevice *dev)
+{
+ if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC) &&
+ (gd->flags & GD_FLG_RELOC)) {
+ struct cpu_ops *ops = cpu_get_ops(dev);
+ static int reloc_done;
+
+ if (!reloc_done) {
+ if (ops->get_desc)
+ MANUAL_RELOC(ops->get_desc);
+ if (ops->get_info)
+ MANUAL_RELOC(ops->get_info);
+ if (ops->get_count)
+ MANUAL_RELOC(ops->get_count);
+ if (ops->get_vendor)
+ MANUAL_RELOC(ops->get_vendor);
+ if (ops->is_current)
+ MANUAL_RELOC(ops->is_current);
+
+ reloc_done++;
+ }
+ }
+
+ return 0;
+}
+
UCLASS_DRIVER(cpu) = {
.id = UCLASS_CPU,
.name = "cpu",
.flags = DM_UC_FLAG_SEQ_ALIAS,
.init = uclass_cpu_init,
+ .post_bind = uclass_cpu_post_bind,
};
--
2.25.1
[PATCH 2/2] event: fix static events for CONFIG_NEEDS_MANUAL_RELOC
Static events do not currently work post-relocation for boards that enable
CONFIG_NEEDS_MANUAL_RELOC. Relocate event handler pointers for all event
spies to fix this.
Tested on Microblaze.
Signed-off-by: Ovidiu Panait
---
common/board_r.c | 3 +++
common/event.c | 15 +++
include/event.h | 10 ++
3 files changed, 28 insertions(+)
diff --git a/common/board_r.c b/common/board_r.c
index 6f4aca2077..01a1728c3f 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -612,6 +612,9 @@ static init_fnc_t init_sequence_r[] = {
*/
#endif
initr_reloc_global_data,
+#if CONFIG_IS_ENABLED(NEEDS_MANUAL_RELOC) && CONFIG_IS_ENABLED(EVENT)
+ event_manual_reloc,
+#endif
#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
initr_unlock_ram_in_cache,
#endif
diff --git a/common/event.c b/common/event.c
index 063647447d..af1ed4121d 100644
--- a/common/event.c
+++ b/common/event.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -148,6 +149,20 @@ void event_show_spy_list(void)
}
}
+#if CONFIG_IS_ENABLED(NEEDS_MANUAL_RELOC)
+int event_manual_reloc(void)
+{
+ struct evspy_info *spy, *end;
+
+ spy = ll_entry_start(struct evspy_info, evspy_info);
+ end = ll_entry_end(struct evspy_info, evspy_info);
+ for (; spy < end; spy++)
+ MANUAL_RELOC(spy->func);
+
+ return 0;
+}
+#endif
+
#if CONFIG_IS_ENABLED(EVENT_DYNAMIC)
static void spy_free(struct event_spy *spy)
{
diff --git a/include/event.h b/include/event.h
index 62e72a7bd3..a8f0c3fa2b 100644
--- a/include/event.h
+++ b/include/event.h
@@ -144,6 +144,16 @@ int event_register(const char *id, enum event_t type,
event_handler_t func,
/** event_show_spy_list( - Show a list of event spies */
void event_show_spy_list(void);
+/**
+ * event_manual_reloc() - Relocate event handler pointers
+ *
+ * Relocate event handler pointers for all static event spies. It is called
+ * during the generic board init sequence, after relocation.
+ *
+ * Return: 0 if OK
+ */
+int event_manual_reloc(void);
+
#if CONFIG_IS_ENABLED(EVENT)
/**
* event_notify() - notify spies about an event
--
2.25.1
[PATCH 1/2] event: remove CONFIG_EVENT_DYNAMIC check in event_register()
The whole event_register() function is wrapped in EVENT_DYNAMIC #ifdef
checks, so the inner check is not needed:
#if CONFIG_IS_ENABLED(EVENT_DYNAMIC)
...
int event_register(...)
{
...
if (!CONFIG_IS_ENABLED(EVENT_DYNAMIC))
return -ENOSYS;
}
#endif
Signed-off-by: Ovidiu Panait
---
common/event.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/common/event.c b/common/event.c
index 9d67a060a0..063647447d 100644
--- a/common/event.c
+++ b/common/event.c
@@ -159,8 +159,6 @@ int event_register(const char *id, enum event_t type,
event_handler_t func, void
struct event_state *state = gd_event_state();
struct event_spy *spy;
- if (!CONFIG_IS_ENABLED(EVENT_DYNAMIC))
- return -ENOSYS;
spy = malloc(sizeof(*spy));
if (!spy)
return log_msg_ret("alloc", -ENOMEM);
--
2.25.1
[PATCH] cmd: dm: migrate dm command to use U_BOOT_CMD_WITH_SUBCMDS()
Migrate dm command to use U_BOOT_CMD_WITH_SUBCMDS() helper macro, to reduce
duplicated code. We can also drop the CONFIG_NEEDS_MANUAL_RELOC exception,
as the command list is updated post relocation in board_r.c initcall
initr_manual_reloc_cmdtable().
Signed-off-by: Ovidiu Panait
---
cmd/dm.c | 64 +++-
1 file changed, 12 insertions(+), 52 deletions(-)
diff --git a/cmd/dm.c b/cmd/dm.c
index 1dd19fe45b..ca609224f5 100644
--- a/cmd/dm.c
+++ b/cmd/dm.c
@@ -8,12 +8,6 @@
#include
#include
-#include
-#include
-#include
-#include
-#include
-#include
#include
static int do_dm_dump_all(struct cmd_tbl *cmdtp, int flag, int argc,
@@ -64,55 +58,21 @@ static int do_dm_dump_static_driver_info(struct cmd_tbl
*cmdtp, int flag, int ar
return 0;
}
-static struct cmd_tbl test_commands[] = {
- U_BOOT_CMD_MKENT(tree, 0, 1, do_dm_dump_all, "", ""),
- U_BOOT_CMD_MKENT(uclass, 1, 1, do_dm_dump_uclass, "", ""),
- U_BOOT_CMD_MKENT(devres, 1, 1, do_dm_dump_devres, "", ""),
- U_BOOT_CMD_MKENT(drivers, 1, 1, do_dm_dump_drivers, "", ""),
- U_BOOT_CMD_MKENT(compat, 1, 1, do_dm_dump_driver_compat, "", ""),
- U_BOOT_CMD_MKENT(static, 1, 1, do_dm_dump_static_driver_info, "", ""),
-};
-
-static __maybe_unused void dm_reloc(void)
-{
- static int relocated;
-
- if (!relocated) {
- fixup_cmdtable(test_commands, ARRAY_SIZE(test_commands));
- relocated = 1;
- }
-}
-
-static int do_dm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- struct cmd_tbl *test_cmd;
- int ret;
-
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- dm_reloc();
-#endif
-
- if (argc < 2)
- return CMD_RET_USAGE;
- test_cmd = find_cmd_tbl(argv[1], test_commands,
- ARRAY_SIZE(test_commands));
- argc -= 2;
- argv += 2;
- if (!test_cmd || argc > test_cmd->maxargs)
- return CMD_RET_USAGE;
-
- ret = test_cmd->cmd(test_cmd, flag, argc, argv);
-
- return cmd_process_error(test_cmd, ret);
-}
-
-U_BOOT_CMD(
- dm, 3, 1, do_dm,
- "Driver model low level access",
+#if CONFIG_IS_ENABLED(SYS_LONGHELP)
+static char dm_help_text[] =
"tree Dump driver model tree ('*' = activated)\n"
"dm uclassDump list of instances for each uclass\n"
"dm devresDump list of device resources for each device\n"
"dm drivers Dump list of drivers with uclass and instances\n"
"dm compatDump list of drivers with compatibility strings\n"
"dm staticDump list of drivers with static platform data"
-);
+ ;
+#endif
+
+U_BOOT_CMD_WITH_SUBCMDS(dm, "Driver model low level access", dm_help_text,
+ U_BOOT_SUBCMD_MKENT(tree, 1, 1, do_dm_dump_all),
+ U_BOOT_SUBCMD_MKENT(uclass, 1, 1, do_dm_dump_uclass),
+ U_BOOT_SUBCMD_MKENT(devres, 1, 1, do_dm_dump_devres),
+ U_BOOT_SUBCMD_MKENT(drivers, 1, 1, do_dm_dump_drivers),
+ U_BOOT_SUBCMD_MKENT(compat, 1, 1, do_dm_dump_driver_compat),
+ U_BOOT_SUBCMD_MKENT(static, 1, 1, do_dm_dump_static_driver_info));
--
2.25.1
[PATCH] board_r: use IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC) in board_init_r()
Drop CONFIG_NEEDS_MANUAL_RELOC ifdefs in board_init_r() and use
IS_ENABLED() instead. Also, use the MANUAL_RELOC() macro to update the
initcall pointers.
Signed-off-by: Ovidiu Panait
---
common/board_r.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/common/board_r.c b/common/board_r.c
index 93c9c2e50d..6f4aca2077 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -61,6 +61,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -810,19 +811,15 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
if (CONFIG_IS_ENABLED(X86_64) && !IS_ENABLED(CONFIG_EFI_APP))
arch_setup_gd(new_gd);
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- int i;
-#endif
-
#if !defined(CONFIG_X86) && !defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
gd = new_gd;
#endif
gd->flags &= ~GD_FLG_LOG_READY;
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- for (i = 0; i < ARRAY_SIZE(init_sequence_r); i++)
- init_sequence_r[i] += gd->reloc_off;
-#endif
+ if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC)) {
+ for (int i = 0; i < ARRAY_SIZE(init_sequence_r); i++)
+ MANUAL_RELOC(init_sequence_r[i]);
+ }
if (initcall_run_list(init_sequence_r))
hang();
--
2.36.0
[PATCH 10/10] microblaze: cache: use fdt cache size info if available
If CONFIG_CPU_MICROBLAZE is enabled, the cache size and cache line size are
retrieved from the fdt by the microblaze cpu driver. Adjust cache flush
code to use those values if available.
If a cache flush is requested very early in the boot (for example the
flush_cache_all() call in start.S) or before dm is ready, the default size
of CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE will be used instead.
Signed-off-by: Ovidiu Panait
---
arch/microblaze/cpu/cache.c | 45 +
1 file changed, 41 insertions(+), 4 deletions(-)
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index cce33a6eb5..8b7e212a26 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -9,11 +9,21 @@
#include
#include
#include
+#include
static void __invalidate_icache(ulong addr, ulong size)
{
if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WIC)) {
- for (int i = 0; i < size; i += 4) {
+ int line_length = 4;
+
+ if (CONFIG_IS_ENABLED(CPU_MICROBLAZE)) {
+ int size = microblaze_cpu_get_cacheline_size(ICACHE);
+
+ if (size > 0)
+ line_length = size;
+ }
+
+ for (int i = 0; i < size; i += line_length) {
asm volatile (
"wic%0, r0;"
"nop;"
@@ -26,13 +36,31 @@ static void __invalidate_icache(ulong addr, ulong size)
void invalidate_icache_all(void)
{
- __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE);
+ int cache_size = CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE;
+
+ if (CONFIG_IS_ENABLED(CPU_MICROBLAZE)) {
+ int size = microblaze_cpu_get_cache_size(ICACHE);
+
+ if (size >= 0)
+ cache_size = size;
+ }
+
+ __invalidate_icache(0, cache_size);
}
static void __flush_dcache(ulong addr, ulong size)
{
if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) {
- for (int i = 0; i < size; i += 4) {
+ int line_length = 4;
+
+ if (CONFIG_IS_ENABLED(CPU_MICROBLAZE)) {
+ int size = microblaze_cpu_get_cacheline_size(DCACHE);
+
+ if (size > 0)
+ line_length = size;
+ }
+
+ for (int i = 0; i < size; i += line_length) {
asm volatile (
"wdc.flush %0, r0;"
"nop;"
@@ -53,7 +81,16 @@ void flush_dcache_range(unsigned long start, unsigned long
end)
void flush_dcache_all(void)
{
- __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE);
+ int cache_size = CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE;
+
+ if (CONFIG_IS_ENABLED(CPU_MICROBLAZE)) {
+ int size = microblaze_cpu_get_cache_size(DCACHE);
+
+ if (size >= 0)
+ cache_size = size;
+ }
+
+ __flush_dcache(0, cache_size);
}
int dcache_status(void)
--
2.25.1
[PATCH 09/10] cpu: microblaze: add driver for CPU
Add a basic CPU driver that retrieves information about the microblaze CPU
core. At this time, only data related to instruction/data caches
is extracted from fdt.
Signed-off-by: Ovidiu Panait
---
arch/microblaze/include/asm/cache.h | 5 +
arch/microblaze/include/asm/microblaze_cpu.h | 53 +
drivers/cpu/Kconfig | 6 +
drivers/cpu/Makefile | 1 +
drivers/cpu/microblaze_cpu.c | 109 +++
5 files changed, 174 insertions(+)
create mode 100644 arch/microblaze/include/asm/microblaze_cpu.h
create mode 100644 drivers/cpu/microblaze_cpu.c
diff --git a/arch/microblaze/include/asm/cache.h
b/arch/microblaze/include/asm/cache.h
index c39b66dd7d..58ec69603e 100644
--- a/arch/microblaze/include/asm/cache.h
+++ b/arch/microblaze/include/asm/cache.h
@@ -23,4 +23,9 @@
*/
void flush_cache_all(void);
+enum cache_type {
+ DCACHE,
+ ICACHE
+};
+
#endif /* __MICROBLAZE_CACHE_H__ */
diff --git a/arch/microblaze/include/asm/microblaze_cpu.h
b/arch/microblaze/include/asm/microblaze_cpu.h
new file mode 100644
index 00..8aad966e54
--- /dev/null
+++ b/arch/microblaze/include/asm/microblaze_cpu.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022, Ovidiu Panait
+ */
+
+#ifndef __MICROBLAZE_CPU_H
+#define __MICROBLAZE_CPU_H
+
+#include
+
+/**
+ * struct microblaze_cpu_plat - Platform data for microblaze processor core.
+ *
+ * @icache_size: Size of instruction cache memory in bytes.
+ * @icache_line_length: Instruction cache line length in bytes.
+ * @dcache_size: Size of data cache memory in bytes.
+ * @dcache_line_length: Data cache line length in bytes.
+ */
+struct microblaze_cpu_plat {
+ u32 icache_size;
+ u32 icache_line_length;
+
+ u32 dcache_size;
+ u32 dcache_line_length;
+};
+
+/**
+ * microblaze_cpu_get_cacheline_size() - Get the cache line size
+ *
+ * Returns the cache line size in bytes for the cache memory type specified in
+ * @type (dcache or icache). Probes the first UCLASS CPU device via
+ * uclass_get_device() if not already active.
+ *
+ * @type: Cache type (dcache or icache)
+ * Return:
+ * >= 0 if OK, -ENODEV if there is an error getting cpu device data
+ */
+int microblaze_cpu_get_cacheline_size(enum cache_type type);
+
+/**
+ * microblaze_cpu_get_cache_size() - Get the cache size
+ *
+ * Returns the cache size in bytes for the cache memory type specified in @type
+ * (dcache or icache). Probes the first UCLASS CPU device via
+ * uclass_get_device() if not already active.
+ *
+ * @type: Cache type (dcache or icache)
+ * Return:
+ * >= 0 if OK, -ENODEV if there is an error getting cpu device data
+ */
+int microblaze_cpu_get_cache_size(enum cache_type type);
+
+#endif /* __MICROBLAZE_CPU_H */
diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig
index 3d5729f6dc..c4b124da3f 100644
--- a/drivers/cpu/Kconfig
+++ b/drivers/cpu/Kconfig
@@ -19,3 +19,9 @@ config CPU_RISCV
depends on CPU && RISCV
help
Support CPU cores for RISC-V architecture.
+
+config CPU_MICROBLAZE
+ bool "Enable Microblaze CPU driver"
+ depends on CPU && MICROBLAZE
+ help
+ Support CPU cores for Microblaze architecture.
diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile
index c8532637ca..20884b1795 100644
--- a/drivers/cpu/Makefile
+++ b/drivers/cpu/Makefile
@@ -11,4 +11,5 @@ obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o
obj-$(CONFIG_ARCH_AT91) += at91_cpu.o
obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o
obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o
+obj-$(CONFIG_CPU_MICROBLAZE) += microblaze_cpu.o
obj-$(CONFIG_SANDBOX) += cpu_sandbox.o
diff --git a/drivers/cpu/microblaze_cpu.c b/drivers/cpu/microblaze_cpu.c
new file mode 100644
index 00..823ac5671e
--- /dev/null
+++ b/drivers/cpu/microblaze_cpu.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022, Ovidiu Panait
+ */
+#include
+#include
+
+static struct microblaze_cpu_plat *get_cpu0_plat(void)
+{
+ struct udevice *dev;
+
+ if (uclass_get_device(UCLASS_CPU, 0, ) == 0)
+ return dev_get_plat(dev);
+
+ return NULL;
+}
+
+int microblaze_cpu_get_cacheline_size(enum cache_type type)
+{
+ struct microblaze_cpu_plat *plat = get_cpu0_plat();
+
+ if (!plat)
+ return -ENODEV;
+
+ if (type == DCACHE)
+ return plat->dcache_line_length;
+
+ return plat->icache_line_length;
+}
+
+int microblaze_cpu_get_cache_size(enum cache_type type)
+{
+ struct microblaze_cpu_plat *plat = get_cpu0_plat();
+
+ if (!plat)
+ return -ENODEV;
+
+ if (type == DCACHE)
+ return plat->dcache_size;
+
+ return plat->icache_size;
+}
+
+static int microblaze_cpu_of_to_plat(struct udevice *dev)
+{
+ struct microblaze_cpu_plat *plat = dev_get_plat(dev);
+
+ plat->icache_siz
[PATCH 07/10] microblaze: cache: introduce flush_cache_all()
All flush_cache() calls in microblaze code are supposed to flush the
entire instruction and data caches, so introduce flush_cache_all()
helper to handle this.
Also, provide implementations for flush_dcache_all() and
invalidate_icache_all() so that icache and dcache u-boot commands can
work.
Signed-off-by: Ovidiu Panait
---
arch/microblaze/cpu/cache.c | 20 ++--
arch/microblaze/cpu/start.S | 8 ++--
arch/microblaze/include/asm/cache.h | 5 +
arch/microblaze/lib/bootm.c | 2 +-
4 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index 2814c1dc07..60b6d549d7 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -24,6 +24,11 @@ static void __invalidate_icache(ulong addr, ulong size)
}
}
+void invalidate_icache_all(void)
+{
+ __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE);
+}
+
static void __flush_dcache(ulong addr, ulong size)
{
if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) {
@@ -38,6 +43,11 @@ static void __flush_dcache(ulong addr, ulong size)
}
}
+void flush_dcache_all(void)
+{
+ __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE);
+}
+
int dcache_status(void)
{
int i = 0;
@@ -65,7 +75,7 @@ void icache_enable(void)
void icache_disable(void)
{
- __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE);
+ invalidate_icache_all();
MSRCLR(0x20);
}
@@ -77,7 +87,7 @@ void dcache_enable(void)
void dcache_disable(void)
{
- __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE);
+ flush_dcache_all();
MSRCLR(0x80);
}
@@ -87,3 +97,9 @@ void flush_cache(ulong addr, ulong size)
__invalidate_icache(addr, size);
__flush_dcache(addr, size);
}
+
+void flush_cache_all(void)
+{
+ invalidate_icache_all();
+ flush_dcache_all();
+}
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 94984148de..7f7b5f5cb5 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -52,9 +52,7 @@ _start:
#endif
/* Flush cache before enable cache */
- addik r5, r0, 0
- addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE
- bralid r15, flush_cache
+ bralid r15, flush_cache_all
nop
/* enable instruction and data cache */
@@ -283,9 +281,7 @@ relocate_code:
addkr20, r20, r23
/* Flush caches to ensure consistency */
- addik r5, r0, 0
- addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE
- bralid r15, flush_cache
+ bralid r15, flush_cache_all
nop
2: addir5, r31, 0 /* gd is initialized in board_r.c */
diff --git a/arch/microblaze/include/asm/cache.h
b/arch/microblaze/include/asm/cache.h
index baee01a0e2..c39b66dd7d 100644
--- a/arch/microblaze/include/asm/cache.h
+++ b/arch/microblaze/include/asm/cache.h
@@ -18,4 +18,9 @@
#define ARCH_DMA_MINALIGN 16
#endif
+/**
+ * flush_cache_all - flush the entire instruction/data caches
+ */
+void flush_cache_all(void);
+
#endif /* __MICROBLAZE_CACHE_H__ */
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index 59b757c857..af946b8642 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -57,7 +57,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
"(fake run for tracing)" : "");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
- flush_cache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE);
+ flush_cache_all();
if (!fake) {
/*
--
2.25.1
[PATCH 08/10] microblaze: cache: introduce flush_dcache_range()
Align microblaze with the other architectures and provide an
implementation for flush_dcache_range(). Also, remove the microblaze
exception in drivers/core/device.c.
Signed-off-by: Ovidiu Panait
---
arch/microblaze/cpu/cache.c | 8
drivers/core/device.c | 5 -
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index 60b6d549d7..cce33a6eb5 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -43,6 +43,14 @@ static void __flush_dcache(ulong addr, ulong size)
}
}
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+ if (start >= end)
+ return;
+
+ __flush_dcache(start, end - start);
+}
+
void flush_dcache_all(void)
{
__flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE);
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 1b356f12dd..16f808f2be 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -328,13 +328,8 @@ static void *alloc_priv(int size, uint flags)
* within this range at the start. The driver can then
* use normal flush-after-write, invalidate-before-read
* procedures.
-*
-* TODO(s...@chromium.org): Drop this microblaze
-* exception.
*/
-#ifndef CONFIG_MICROBLAZE
flush_dcache_range((ulong)priv, (ulong)priv + size);
-#endif
}
} else {
priv = calloc(1, size);
--
2.25.1
[PATCH 06/10] microblaze: cache: migrate XILINX_DCACHE_BYTE_SIZE to Kconfig
Migrate XILINX_DCACHE_BYTE_SIZE to Kconfig and rename it to
XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE. Use it as the default size
for both instruction/data caches and get rid of the hardcoded value
in icache_disable().
Signed-off-by: Ovidiu Panait
---
arch/microblaze/cpu/cache.c | 5 ++---
arch/microblaze/cpu/start.S | 4 ++--
arch/microblaze/lib/bootm.c | 2 +-
board/xilinx/microblaze-generic/Kconfig | 8
include/configs/microblaze-generic.h| 4
5 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index e362a34a79..2814c1dc07 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -65,8 +65,7 @@ void icache_enable(void)
void icache_disable(void)
{
- /* we are not generate ICACHE size -> flush whole cache */
- __invalidate_icache(0, 32768);
+ __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE);
MSRCLR(0x20);
}
@@ -78,7 +77,7 @@ void dcache_enable(void)
void dcache_disable(void)
{
- __flush_dcache(0, XILINX_DCACHE_BYTE_SIZE);
+ __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE);
MSRCLR(0x80);
}
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index d1b0453caf..94984148de 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -53,7 +53,7 @@ _start:
/* Flush cache before enable cache */
addik r5, r0, 0
- addik r6, r0, XILINX_DCACHE_BYTE_SIZE
+ addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE
bralid r15, flush_cache
nop
@@ -284,7 +284,7 @@ relocate_code:
/* Flush caches to ensure consistency */
addik r5, r0, 0
- addik r6, r0, XILINX_DCACHE_BYTE_SIZE
+ addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE
bralid r15, flush_cache
nop
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index dba6226ce5..59b757c857 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -57,7 +57,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
"(fake run for tracing)" : "");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
- flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
+ flush_cache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE);
if (!fake) {
/*
diff --git a/board/xilinx/microblaze-generic/Kconfig
b/board/xilinx/microblaze-generic/Kconfig
index 89af8d714f..505a3d59cf 100644
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -77,4 +77,12 @@ config XILINX_MICROBLAZE0_USE_WIC
Enable this option if the MicroBlaze processor is configured with
support for the "wic" (Write to Instruction Cache) instruction.
+config XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE
+ int "Default instruction/data cache size"
+ default 32768
+ help
+ This fallback size will be used when no cache info can be found in
+ the device tree, or when the caches are flushed very early in the
+ boot process, before device tree is available.
+
endif
diff --git a/include/configs/microblaze-generic.h
b/include/configs/microblaze-generic.h
index 663837f33d..7b064eacb2 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -30,10 +30,6 @@
# define CONFIG_SYS_MAX_FLASH_SECT 2048
#endif
-#ifndef XILINX_DCACHE_BYTE_SIZE
-#define XILINX_DCACHE_BYTE_SIZE32768
-#endif
-
/* size of console buffer */
#defineCONFIG_SYS_CBSIZE 512
/* max number of command args */
--
2.25.1
[PATCH 05/10] microblaze: cache: split flush_cache() function
Factor out icache/dcache components from flush_cache() function. Call the
newly added __flush_icache()/__flush_dcache() functions inside
icache_disable() and dcache_disable(), respectively. There is no need to
flush both caches when disabling a particular cache type.
Signed-off-by: Ovidiu Panait
---
arch/microblaze/cpu/cache.c | 55 ++---
1 file changed, 33 insertions(+), 22 deletions(-)
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index b6bbc215b3..e362a34a79 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -10,6 +10,34 @@
#include
#include
+static void __invalidate_icache(ulong addr, ulong size)
+{
+ if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WIC)) {
+ for (int i = 0; i < size; i += 4) {
+ asm volatile (
+ "wic%0, r0;"
+ "nop;"
+ :
+ : "r" (addr + i)
+ : "memory");
+ }
+ }
+}
+
+static void __flush_dcache(ulong addr, ulong size)
+{
+ if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) {
+ for (int i = 0; i < size; i += 4) {
+ asm volatile (
+ "wdc.flush %0, r0;"
+ "nop;"
+ :
+ : "r" (addr + i)
+ : "memory");
+ }
+ }
+}
+
int dcache_status(void)
{
int i = 0;
@@ -38,7 +66,8 @@ void icache_enable(void)
void icache_disable(void)
{
/* we are not generate ICACHE size -> flush whole cache */
- flush_cache(0, 32768);
+ __invalidate_icache(0, 32768);
+
MSRCLR(0x20);
}
@@ -49,31 +78,13 @@ void dcache_enable(void)
void dcache_disable(void)
{
- flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
+ __flush_dcache(0, XILINX_DCACHE_BYTE_SIZE);
MSRCLR(0x80);
}
void flush_cache(ulong addr, ulong size)
{
- int i;
- for (i = 0; i < size; i += 4) {
- if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WIC)) {
- asm volatile (
- "wic%0, r0;"
- "nop;"
- :
- : "r" (addr + i)
- : "memory");
- }
-
- if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) {
- asm volatile (
- "wdc.flush %0, r0;"
- "nop;"
- :
- : "r" (addr + i)
- : "memory");
- }
- }
+ __invalidate_icache(addr, size);
+ __flush_dcache(addr, size);
}
--
2.25.1
[PATCH 04/10] microblaze: cache: improve icache Kconfig options
Replace CONFIG_ICACHE with a Kconfig option more limited in scope -
XILINX_MICROBLAZE0_USE_WIC. It should be enabled if the processor supports
the "wic" (Write to Instruction Cache) instruction. It will be used to
guard "wic" invocations in microblaze cache code.
Signed-off-by: Ovidiu Panait
---
arch/microblaze/Kconfig | 4
arch/microblaze/cpu/cache.c | 6 +++---
board/xilinx/microblaze-generic/Kconfig | 7 +++
3 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 5a2e91104f..a25a95a013 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -25,10 +25,6 @@ config TARGET_MICROBLAZE_GENERIC
endchoice
-config ICACHE
- bool "Enable icache support"
- default y
-
source "board/xilinx/Kconfig"
source "board/xilinx/microblaze-generic/Kconfig"
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index 4e8e228a22..b6bbc215b3 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -58,14 +58,14 @@ void flush_cache(ulong addr, ulong size)
{
int i;
for (i = 0; i < size; i += 4) {
- asm volatile (
-#ifdef CONFIG_ICACHE
+ if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WIC)) {
+ asm volatile (
"wic%0, r0;"
-#endif
"nop;"
:
: "r" (addr + i)
: "memory");
+ }
if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) {
asm volatile (
diff --git a/board/xilinx/microblaze-generic/Kconfig
b/board/xilinx/microblaze-generic/Kconfig
index 0d756ac7ba..89af8d714f 100644
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -70,4 +70,11 @@ config XILINX_MICROBLAZE0_USE_WDC
Enable this option if the MicroBlaze processor is configured with
support for the "wdc" (Write to Data Cache) instruction.
+config XILINX_MICROBLAZE0_USE_WIC
+ bool "MicroBlaze wic instruction support"
+ default y
+ help
+ Enable this option if the MicroBlaze processor is configured with
+ support for the "wic" (Write to Instruction Cache) instruction.
+
endif
--
2.25.1
[PATCH 03/10] microblaze: cache: improve dcache Kconfig options
Replace CONFIG_DCACHE with a Kconfig option more limited in scope -
XILINX_MICROBLAZE0_USE_WDC. It should be enabled if the processor supports
the "wdc" (Write to Data Cache) instruction. It will be used to guard
"wdc" invocations in microblaze cache code.
Also, drop all ifdefs around flush_cache() calls and only keep one
CONFIG_IS_ENABLED() guard within flush_cache() itself.
Signed-off-by: Ovidiu Panait
---
arch/microblaze/Kconfig | 4
arch/microblaze/cpu/cache.c | 15 ++-
arch/microblaze/lib/bootm.c | 2 --
board/xilinx/microblaze-generic/Kconfig | 7 +++
4 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index d7d1b21970..5a2e91104f 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -25,10 +25,6 @@ config TARGET_MICROBLAZE_GENERIC
endchoice
-config DCACHE
- bool "Enable dcache support"
- default y
-
config ICACHE
bool "Enable icache support"
default y
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index b6126de194..4e8e228a22 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -49,26 +49,31 @@ void dcache_enable(void)
void dcache_disable(void)
{
-#ifdef CONFIG_DCACHE
flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
-#endif
+
MSRCLR(0x80);
}
void flush_cache(ulong addr, ulong size)
{
int i;
- for (i = 0; i < size; i += 4)
+ for (i = 0; i < size; i += 4) {
asm volatile (
#ifdef CONFIG_ICACHE
"wic%0, r0;"
#endif
"nop;"
-#ifdef CONFIG_DCACHE
+ :
+ : "r" (addr + i)
+ : "memory");
+
+ if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) {
+ asm volatile (
"wdc.flush %0, r0;"
-#endif
"nop;"
:
: "r" (addr + i)
: "memory");
+ }
+ }
}
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index b652d2767a..dba6226ce5 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -57,9 +57,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
"(fake run for tracing)" : "");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
-#ifdef CONFIG_DCACHE
flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
-#endif
if (!fake) {
/*
diff --git a/board/xilinx/microblaze-generic/Kconfig
b/board/xilinx/microblaze-generic/Kconfig
index 117b476f3f..0d756ac7ba 100644
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -63,4 +63,11 @@ config XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
Memory address location of the exception vector table. It is
configurable via the C_BASE_VECTORS hdl parameter.
+config XILINX_MICROBLAZE0_USE_WDC
+ bool "MicroBlaze wdc instruction support"
+ default y
+ help
+ Enable this option if the MicroBlaze processor is configured with
+ support for the "wdc" (Write to Data Cache) instruction.
+
endif
--
2.25.1
[PATCH 02/10] microblaze: cache: replace XILINX_USE_DCACHE -> CONFIG_DCACHE
XILINX_USE_DCACHE macro was removed in 7556fa09e0e ("microblaze: Simplify
cache handling"), but it was still used in a couple of places.
Replace those occurences with CONFIG_DCACHE.
Signed-off-by: Ovidiu Panait
---
arch/microblaze/cpu/cache.c | 2 +-
arch/microblaze/lib/bootm.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index aa832d6be6..b6126de194 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -49,7 +49,7 @@ void dcache_enable(void)
void dcache_disable(void)
{
-#ifdef XILINX_USE_DCACHE
+#ifdef CONFIG_DCACHE
flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
#endif
MSRCLR(0x80);
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index 12ea32488e..b652d2767a 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -57,7 +57,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
"(fake run for tracing)" : "");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
-#ifdef XILINX_USE_DCACHE
+#ifdef CONFIG_DCACHE
flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
#endif
--
2.25.1
[PATCH 01/10] microblaze: start.S: remove unused code
in16/out16 routines seem to not be used anywhere in microblaze code, so remove them. Signed-off-by: Ovidiu Panait --- arch/microblaze/cpu/start.S | 33 - 1 file changed, 33 deletions(-) diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 645f7cb038..d1b0453caf 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -220,39 +220,6 @@ __setup_exceptions: or r0, r0, r0 .end__setup_exceptions -/* - * Read 16bit little endian - */ - .text - .global in16 - .entin16 - .align 2 -in16: lhu r3, r0, r5 - bslli r4, r3, 8 - bsrli r3, r3, 8 - andir4, r4, 0x - or r3, r3, r4 - rtsdr15, 8 - sext16 r3, r3 - .endin16 - -/* - * Write 16bit little endian - * first parameter(r5) - address, second(r6) - short value - */ - .text - .global out16 - .entout16 - .align 2 -out16: bslli r3, r6, 8 - bsrli r6, r6, 8 - andir3, r3, 0x - or r3, r3, r6 - sh r3, r0, r5 - rtsdr15, 8 - or r0, r0, r0 - .endout16 - /* * Relocate u-boot */ -- 2.25.1
Re: [PATCH 7/7] microblaze: exception: drop user exception support
Hi Michal, On 2/15/22 14:16, Michal Simek wrote: [Please note: This e-mail is from an EXTERNAL e-mail address] On 2/13/22 09:09, Ovidiu Panait wrote: A user exception is triggered by inserting a bralid/brki jump to "C_BASE_VECTORS+0x8" in the software flow. Because u-boot microblaze code does not deal with MMU-related features such as user-mode/privileged-mode separation, there are no code sequences that call into the user exception handler. It seems there is no real usecase for having user exception support in u-boot, so drop the code that installs the nop handler. U-Boot still supports to run user code on the top of u-boot which doesn't need to handle these kind of exceptions. That's why it is good to jump to this code and let you know about it. Thanks for the feedback, this patch should just be ignored then. The rest of this series I think it's still a good addition to the microblaze exception code. Ovidiu M
[PATCH 4/7] microblaze: exception: fix return address for delay slot exceptions
According to the MicroBlaze reference manual (xilinx2021.2/ug984/page-37):
"""
If an exception is caused by an instruction in a delay slot (that is,
ESR[DS]=1), the exception handler should return execution to
the address stored in BTR instead of the normal exception return
address stored in R17.
"""
Adjust the code to print the proper return address for delay slot
exceptions.
Signed-off-by: Ovidiu Panait
---
arch/microblaze/cpu/exception.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
index 64d5fe4a80..f79e465e1f 100644
--- a/arch/microblaze/cpu/exception.c
+++ b/arch/microblaze/cpu/exception.c
@@ -20,11 +20,17 @@ void _hw_exception_handler (void)
MFS(state, resr);
printf("Hardware exception at 0x%x address\n", address);
R17(address);
- printf("Return address from exception 0x%x\n", address);
if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP) &&
- (state & 0x1000))
+ (state & 0x1000)) {
+ /*
+* For exceptions in delay slots, the return address is stored
+* in the Branch Target Register (BTR), rather than R17.
+*/
+ MFS(address, rbtr);
+
puts("Exception in delay slot\n");
+ }
switch (state & 0x1f) { /* mask on exception cause */
case 0x1:
@@ -49,6 +55,8 @@ void _hw_exception_handler (void)
puts("Undefined cause\n");
break;
}
+
+ printf("Return address from exception 0x%x\n", address);
printf("Unaligned %sword access\n", ((state & 0x800) ? "" : "half"));
printf("Unaligned %s access\n", ((state & 0x400) ? "store" : "load"));
printf("Register R%x\n", (state & 0x3E) >> 5);
--
2.25.1
[PATCH 2/7] microblaze: exception: migrate MICROBLAZE_V5 to Kconfig
Also, rename it to XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP, since it only
covers delay slot exception support.
Signed-off-by: Ovidiu Panait
---
arch/microblaze/cpu/exception.c | 2 +-
board/xilinx/microblaze-generic/Kconfig | 9 +
include/configs/microblaze-generic.h| 3 ---
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
index f60f1fc693..5601dde5b4 100644
--- a/arch/microblaze/cpu/exception.c
+++ b/arch/microblaze/cpu/exception.c
@@ -40,7 +40,7 @@ void _hw_exception_handler (void)
case 0x7:
puts("Priviledged or stack protection violation exception\n");
break;
-#ifdef MICROBLAZE_V5
+#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP)
case 0x1000:
puts("Exception in delay slot\n");
break;
diff --git a/board/xilinx/microblaze-generic/Kconfig
b/board/xilinx/microblaze-generic/Kconfig
index e31257d335..117b476f3f 100644
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -47,6 +47,15 @@ config XILINX_MICROBLAZE0_USR_EXCEP
the exception vector table. The user exception vector is located at
C_BASE_VECTORS + 0x8 address.
+config XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP
+ bool "MicroBlaze delay slot exception support"
+ default y
+ help
+ Enable this option if the MicroBlaze processor supports exceptions
+ caused by delay slot instructions (processor version >= v5.00). When
+ enabled, the hw exception handler will print a message indicating
+ whether the exception was triggered by a delay slot instruction.
+
config XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
hex "Location of MicroBlaze vectors"
default 0x0
diff --git a/include/configs/microblaze-generic.h
b/include/configs/microblaze-generic.h
index ca749ed18a..fd5a9cf8b8 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -11,9 +11,6 @@
/* Microblaze is microblaze_0 */
#define XILINX_FSL_NUMBER 3
-/* MicroBlaze CPU */
-#defineMICROBLAZE_V5 1
-
#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024)
/* uart */
--
2.25.1
[PATCH 6/7] microblaze: exception: fix unaligned data access register mask
The correct mask for getting the source/destination register from ESR in
the case of an unaligned access exception is 0x3E0. With this change, a
dummy unaligned store produces the expected info:
"""
>> swi r5, r0, 0x111
...
Hardware exception at 0x111 address
Unaligned data access exception
Unaligned word access
Unaligned store access
Register R5
Return address from exception 0x7f99dfc
### ERROR ### Please RESET the board ###
"""
Signed-off-by: Ovidiu Panait
---
arch/microblaze/cpu/exception.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
index d37f04364a..d3640d3903 100644
--- a/arch/microblaze/cpu/exception.c
+++ b/arch/microblaze/cpu/exception.c
@@ -38,7 +38,7 @@ void _hw_exception_handler (void)
printf("Unaligned %sword access\n", ((state & 0x800) ? "" :
"half"));
printf("Unaligned %s access\n", ((state & 0x400) ? "store" :
"load"));
- printf("Register R%x\n", (state & 0x3E) >> 5);
+ printf("Register R%x\n", (state & 0x3E0) >> 5);
break;
case 0x2:
puts("Illegal op-code exception\n");
--
2.25.1
[PATCH 7/7] microblaze: exception: drop user exception support
A user exception is triggered by inserting a bralid/brki jump to
"C_BASE_VECTORS+0x8" in the software flow. Because u-boot microblaze code
does not deal with MMU-related features such as user-mode/privileged-mode
separation, there are no code sequences that call into the user exception
handler.
It seems there is no real usecase for having user exception support in
u-boot, so drop the code that installs the nop handler.
Signed-off-by: Ovidiu Panait
---
arch/microblaze/cpu/exception.c | 8 -
arch/microblaze/cpu/start.S | 40 ++---
board/xilinx/microblaze-generic/Kconfig | 9 --
3 files changed, 3 insertions(+), 54 deletions(-)
diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
index d3640d3903..1f7c44d1f3 100644
--- a/arch/microblaze/cpu/exception.c
+++ b/arch/microblaze/cpu/exception.c
@@ -63,11 +63,3 @@ void _hw_exception_handler (void)
printf("Return address from exception 0x%x\n", address);
hang();
}
-
-#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP)
-void _exception_handler (void)
-{
- puts("User vector_exception\n");
- hang();
-}
-#endif
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 645f7cb038..0ea0b78da9 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -97,9 +97,9 @@ clear_bss:
* r5 - relocation offset (zero when setting up vectors before
* relocation, and gd->reloc_off when setting up vectors after
* relocation)
- *- the relocation offset is added to the _exception_handler,
- * _interrupt_handler and _hw_exception_handler symbols to reflect the
- * post-relocation memory addresses
+ *- the relocation offset is added to the _interrupt_handler and
+ * _hw_exception_handler symbols to reflect the post-relocation memory
+ * addresses
*
* Reserve registers:
* r10: Stores little/big endian offset for vectors
@@ -149,40 +149,6 @@ __setup_exceptions:
rsubi r8, r10, 0x6
sh r6, r4, r8
-#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP)
- /* user_vector_exception */
- swi r2, r4, 0x8 /* user vector exception - imm opcode */
- swi r3, r4, 0xC /* user vector exception - brai opcode */
-
- addik r6, r5, _exception_handler
- sw r6, r1, r0
- /*
-* BIG ENDIAN memory map for user exception
-* 0x8: 0xB000
-* 0xC: 0xB808
-*
-* then it is necessary to count address for storing the most
significant
-* 16bits from _exception_handler address and copy it to
-* 0xa address. Big endian use offset in r10=0 that's why is it just
-* 0xa address. The same is done for the least significant 16 bits
-* for 0xe address.
-*
-* LITTLE ENDIAN memory map for user exception
-* 0x8: 0x00B0
-* 0xC: 0x08B8
-*
-* Offset is for little endian setup to 0x2. rsubi instruction decrease
-* address value to ensure that points to proper place which is
-* 0x8 for the most significant 16 bits and
-* 0xC for the least significant 16 bits
-*/
- lhu r7, r1, r10
- rsubi r8, r10, 0xa
- sh r7, r4, r8
- rsubi r8, r10, 0xe
- sh r6, r4, r8
-#endif
-
/* interrupt_handler */
swi r2, r4, 0x10/* interrupt - imm opcode */
swi r3, r4, 0x14/* interrupt - brai opcode */
diff --git a/board/xilinx/microblaze-generic/Kconfig
b/board/xilinx/microblaze-generic/Kconfig
index 117b476f3f..a0af2e9abd 100644
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -38,15 +38,6 @@ config XILINX_MICROBLAZE0_HW_VER
string "Core version number"
default "7.10.d"
-config XILINX_MICROBLAZE0_USR_EXCEP
- bool "MicroBlaze user exception support"
- default y
- help
- Enable this option in order to install the user exception handler
- (_exception_handler routine from arch/microblaze/cpu/exception.c) in
- the exception vector table. The user exception vector is located at
- C_BASE_VECTORS + 0x8 address.
-
config XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP
bool "MicroBlaze delay slot exception support"
default y
--
2.25.1
[PATCH 3/7] microblaze: exception: fix delay slot exception handling
The switch statement in _hw_exception_handler() only covers the
rightmost 5 bits that encode the exception cause:
switch (state & 0x1f)
{
...
}
For this reason, the "0x1000" case will never be reached, because the 13th
bit was zeroed out. To fix this, move delay slot exception handling before
the switch statement (delay slot (DS) bit in Exception Status Register is
independent of the exception cause (EC)).
Signed-off-by: Ovidiu Panait
---
arch/microblaze/cpu/exception.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
index 5601dde5b4..64d5fe4a80 100644
--- a/arch/microblaze/cpu/exception.c
+++ b/arch/microblaze/cpu/exception.c
@@ -21,6 +21,11 @@ void _hw_exception_handler (void)
printf("Hardware exception at 0x%x address\n", address);
R17(address);
printf("Return address from exception 0x%x\n", address);
+
+ if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP) &&
+ (state & 0x1000))
+ puts("Exception in delay slot\n");
+
switch (state & 0x1f) { /* mask on exception cause */
case 0x1:
puts("Unaligned data access exception\n");
@@ -40,11 +45,6 @@ void _hw_exception_handler (void)
case 0x7:
puts("Priviledged or stack protection violation exception\n");
break;
-#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP)
- case 0x1000:
- puts("Exception in delay slot\n");
- break;
-#endif
default:
puts("Undefined cause\n");
break;
--
2.25.1
[PATCH 5/7] microblaze: exception: move unaligned access printfs inside switch case
The unaligned access messages are only valid in the case of an unaligned
data access exception. Do not print them for other types of hw exceptions.
Signed-off-by: Ovidiu Panait
---
arch/microblaze/cpu/exception.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
index f79e465e1f..d37f04364a 100644
--- a/arch/microblaze/cpu/exception.c
+++ b/arch/microblaze/cpu/exception.c
@@ -35,6 +35,10 @@ void _hw_exception_handler (void)
switch (state & 0x1f) { /* mask on exception cause */
case 0x1:
puts("Unaligned data access exception\n");
+
+ printf("Unaligned %sword access\n", ((state & 0x800) ? "" :
"half"));
+ printf("Unaligned %s access\n", ((state & 0x400) ? "store" :
"load"));
+ printf("Register R%x\n", (state & 0x3E) >> 5);
break;
case 0x2:
puts("Illegal op-code exception\n");
@@ -57,9 +61,6 @@ void _hw_exception_handler (void)
}
printf("Return address from exception 0x%x\n", address);
- printf("Unaligned %sword access\n", ((state & 0x800) ? "" : "half"));
- printf("Unaligned %s access\n", ((state & 0x400) ? "store" : "load"));
- printf("Register R%x\n", (state & 0x3E) >> 5);
hang();
}
--
2.25.1
[PATCH 1/7] microblaze: exception: move privileged instruction exception out of v5 ifdef
The privileged instruction exception seems to have been introduced in
microblaze v7.00 along with MMU support, so having it wrapped in
MICROBLAZE_v5 ifdefs seems incorrect. Move it out of the ifdef, since all
recent microblaze versions support it.
Signed-off-by: Ovidiu Panait
---
arch/microblaze/cpu/exception.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
index e9476abedb..f60f1fc693 100644
--- a/arch/microblaze/cpu/exception.c
+++ b/arch/microblaze/cpu/exception.c
@@ -37,10 +37,10 @@ void _hw_exception_handler (void)
case 0x5:
puts("Divide by zero exception\n");
break;
-#ifdef MICROBLAZE_V5
case 0x7:
puts("Priviledged or stack protection violation exception\n");
break;
+#ifdef MICROBLAZE_V5
case 0x1000:
puts("Exception in delay slot\n");
break;
--
2.25.1
[PATCH 1/2] powerpc: mpc8xx: drop CONFIG_SYS_RESET_ADDRESS
There are no boards that define CONFIG_SYS_RESET_ADDRESS, so drop the associated mpc8xx code that checks for it. Signed-off-by: Ovidiu Panait --- arch/powerpc/cpu/mpc8xx/cpu.c | 11 ++- scripts/config_whitelist.txt | 1 - 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c index 893aecef21..6d16ed084e 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu.c +++ b/arch/powerpc/cpu/mpc8xx/cpu.c @@ -215,19 +215,12 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) /* * Trying to execute the next instruction at a non-existing address * should cause a machine check, resulting in reset -*/ -#ifdef CONFIG_SYS_RESET_ADDRESS - addr = CONFIG_SYS_RESET_ADDRESS; -#else - /* +* * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address. -* Better pick an address known to be invalid on your system and assign -* it to CONFIG_SYS_RESET_ADDRESS. -* "(ulong)-1" used to be a good choice for many systems... */ addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong); -#endif + ((void (*)(void)) addr)(); return 1; } diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 7b45d578a3..84e46e3763 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1837,7 +1837,6 @@ CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C3_BASE CONFIG_SYS_RESET_ADDR -CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_RFD CONFIG_SYS_RGMII1_PHY_ADDR CONFIG_SYS_RGMII2_PHY_ADDR -- 2.25.1
[PATCH 2/2] common: drop CONFIG_SYS_RESET_ADDR
There are no boards that define CONFIG_SYS_RESET_ADDR, so drop the remaining comments referencing it and also the config_whitelist.txt entry. Signed-off-by: Ovidiu Panait --- include/configs/10m50_devboard.h | 9 - include/configs/3c120_devboard.h | 9 - scripts/config_whitelist.txt | 1 - 3 files changed, 19 deletions(-) diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index 04ce88c9dd..3b4d1fd626 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -47,13 +47,4 @@ CONFIG_SYS_SDRAM_SIZE - \ CONFIG_SYS_MONITOR_LEN) -/* - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - */ - - #endif /* __CONFIG_H */ diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h index e12e54fe4f..763cb8db7c 100644 --- a/include/configs/3c120_devboard.h +++ b/include/configs/3c120_devboard.h @@ -47,13 +47,4 @@ CONFIG_SYS_SDRAM_SIZE - \ CONFIG_SYS_MONITOR_LEN) -/* - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - */ - - #endif /* __CONFIG_H */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 84e46e3763..4bd298694a 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1836,7 +1836,6 @@ CONFIG_SYS_RCAR_I2C0_BASE CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C3_BASE -CONFIG_SYS_RESET_ADDR CONFIG_SYS_RFD CONFIG_SYS_RGMII1_PHY_ADDR CONFIG_SYS_RGMII2_PHY_ADDR -- 2.25.1
[PATCH v2 2/7] common: remove bedbug debugger support
Commit 98f705c9cefd ("powerpc: remove 4xx support") removed (in 2017) the
last code that made use of bedbug debugger support. Since there aren't
any boards left that define either CONFIG_CMD_BEDBUG or a real
bedbug_init(), drop this feature from u-boot.
Signed-off-by: Ovidiu Panait
---
Changes in v2:
- new patch
arch/powerpc/cpu/mpc83xx/traps.c |7 -
arch/powerpc/cpu/mpc85xx/traps.c |7 -
cmd/Kconfig |7 -
cmd/Makefile |1 -
cmd/bedbug.c | 410 --
common/Makefile |1 -
common/bedbug.c | 1254 --
common/board_r.c |9 +-
doc/README.bedbug| 56 --
include/bedbug/bedbug.h | 40 -
include/bedbug/ppc.h | 408 --
include/bedbug/regs.h| 400 --
include/bedbug/tables.h | 601 --
include/bedbug/type.h| 29 -
post/lib_powerpc/string.c|1 -
15 files changed, 1 insertion(+), 3230 deletions(-)
delete mode 100644 cmd/bedbug.c
delete mode 100644 common/bedbug.c
delete mode 100644 doc/README.bedbug
delete mode 100644 include/bedbug/bedbug.h
delete mode 100644 include/bedbug/ppc.h
delete mode 100644 include/bedbug/regs.h
delete mode 100644 include/bedbug/tables.h
delete mode 100644 include/bedbug/type.h
diff --git a/arch/powerpc/cpu/mpc83xx/traps.c b/arch/powerpc/cpu/mpc83xx/traps.c
index 22e451c58d..94e6323d73 100644
--- a/arch/powerpc/cpu/mpc83xx/traps.c
+++ b/arch/powerpc/cpu/mpc83xx/traps.c
@@ -204,15 +204,8 @@ void UnknownException(struct pt_regs *regs)
_exception(0, regs);
}
-#if defined(CONFIG_CMD_BEDBUG)
-extern void do_bedbug_breakpoint(struct pt_regs *);
-#endif
-
void DebugException(struct pt_regs *regs)
{
printf("Debugger trap at @ %lx\n", regs->nip );
show_regs(regs);
-#if defined(CONFIG_CMD_BEDBUG)
- do_bedbug_breakpoint( regs );
-#endif
}
diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c
index def47285ba..97ed24a6eb 100644
--- a/arch/powerpc/cpu/mpc85xx/traps.c
+++ b/arch/powerpc/cpu/mpc85xx/traps.c
@@ -60,10 +60,6 @@ static __inline__ unsigned long get_esr(void)
#define ESR_DIZ 0x0040
#define ESR_U0F 0x8000
-#if defined(CONFIG_CMD_BEDBUG)
-extern void do_bedbug_breakpoint(struct pt_regs *);
-#endif
-
/*
* Trap & Exception support
*/
@@ -285,7 +281,4 @@ void DebugException(struct pt_regs *regs)
{
printf("Debugger trap at @ %lx\n", regs->nip );
show_regs(regs);
-#if defined(CONFIG_CMD_BEDBUG)
- do_bedbug_breakpoint( regs );
-#endif
}
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 02c298fdbe..a6f95b1813 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -2303,13 +2303,6 @@ endmenu
menu "Debug commands"
-config CMD_BEDBUG
- bool "bedbug"
- help
- The bedbug (emBEDded deBUGger) command provides debugging features
- for some PowerPC processors. For details please see the
- documentation in doc/README.bedbug.
-
config CMD_CBSYSINFO
bool "cbsysinfo"
depends on X86
diff --git a/cmd/Makefile b/cmd/Makefile
index e31ac15ef7..abf5d2a55d 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -22,7 +22,6 @@ obj-$(CONFIG_HAVE_BLOCK_DEVICE) += blk_common.o
obj-$(CONFIG_CMD_SOURCE) += source.o
obj-$(CONFIG_CMD_BCB) += bcb.o
obj-$(CONFIG_CMD_BDI) += bdinfo.o
-obj-$(CONFIG_CMD_BEDBUG) += bedbug.o
obj-$(CONFIG_CMD_BIND) += bind.o
obj-$(CONFIG_CMD_BINOP) += binop.o
obj-$(CONFIG_CMD_BLOBLIST) += bloblist.o
diff --git a/cmd/bedbug.c b/cmd/bedbug.c
deleted file mode 100644
index 0bd67fcf47..00
--- a/cmd/bedbug.c
+++ /dev/null
@@ -1,410 +0,0 @@
-/*
- * BedBug Functions
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void show_regs __P ((struct pt_regs *));
-extern int run_command __P ((const char *, int));
-
-ulong dis_last_addr = 0; /* Last address disassembled */
-ulong dis_last_len = 20; /* Default disassembler length */
-CPU_DEBUG_CTX bug_ctx; /* Bedbug context structure*/
-
-
-/* ==
- * U-Boot's puts function does not append a newline, so the bedbug stuff
- * will use this for the output of the dis/assembler.
- * == */
-
-int bedbug_puts (const char *str)
-{
- /* -- */
-
- printf ("%s\r\n", str);
- return 0;
-} /* bedbug_puts */
-
-
-/* ==
- * Initialize the bug_ctx structure used by the bedbug debugger. This is
-
[PATCH v2 5/7] common: board_r: move init_addr_map() to init.h
asm/mmu.h include is currently guarded by CONFIG_ADDR_MAP ifdef because
the header is only present on arm and powerpc. In order to remove the
dependency on this header and the associated ifdef, move init_addr_map()
declaration to init.h, since it is only called during the common init
sequence.
Reviewed-by: Simon Glass
Signed-off-by: Ovidiu Panait
---
(no changes since v1)
arch/arm/include/asm/mmu.h | 8
arch/powerpc/cpu/mpc85xx/tlb.c | 1 +
arch/powerpc/include/asm/mmu.h | 4
board/freescale/common/fsl_chain_of_trust.c | 5 +
common/board_r.c| 3 ---
include/init.h | 10 ++
6 files changed, 12 insertions(+), 19 deletions(-)
delete mode 100644 arch/arm/include/asm/mmu.h
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
deleted file mode 100644
index 8449720fad..00
--- a/arch/arm/include/asm/mmu.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-
-#ifndef __ASM_ARM_MMU_H
-#define __ASM_ARM_MMU_H
-
-int init_addr_map(void);
-
-#endif
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index aa9b59d487..550d45da0e 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -7,6 +7,7 @@
*/
#include
+#include
#include
#include
#include
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index cb5b26cd77..2e6255f0d6 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -137,10 +137,6 @@ typedef struct _MMU_context {
extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
extern void _tlbia(void); /* invalidate all TLB entries */
-#ifdef CONFIG_ADDR_MAP
-extern int init_addr_map(void);
-#endif
-
typedef enum {
IBAT0 = 0, IBAT1, IBAT2, IBAT3,
DBAT0, DBAT1, DBAT2, DBAT3,
diff --git a/board/freescale/common/fsl_chain_of_trust.c
b/board/freescale/common/fsl_chain_of_trust.c
index cafb24971b..7ffb315bc9 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -16,10 +17,6 @@
#include
#endif
-#ifdef CONFIG_ADDR_MAP
-#include
-#endif
-
#ifdef CONFIG_FSL_CORENET
#include
#endif
diff --git a/common/board_r.c b/common/board_r.c
index b0840c70b2..7c45e494ed 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -59,9 +59,6 @@
#ifdef CONFIG_XEN
#include
#endif
-#ifdef CONFIG_ADDR_MAP
-#include
-#endif
#include
#include
#include
diff --git a/include/init.h b/include/init.h
index f2cd46dead..d8278f1c00 100644
--- a/include/init.h
+++ b/include/init.h
@@ -307,6 +307,16 @@ int board_early_init_r(void);
*/
int arch_initr_trap(void);
+/**
+ * init_addr_map()
+ *
+ * Initialize non-identity virtual-physical memory mappings for 32bit CPUs.
+ * It is called during the generic board init sequence, after relocation.
+ *
+ * Return: 0 if OK
+ */
+int init_addr_map(void);
+
/**
* main_loop() - Enter the main loop of U-Boot
*
--
2.25.1
[PATCH v2 7/7] common: board_r: drop ifdefs around header includes
Drop the remaining ifdefs around header includes, to fix an old TODO. Reviewed-by: Simon Glass Signed-off-by: Ovidiu Panait --- (no changes since v1) common/board_r.c | 9 - 1 file changed, 9 deletions(-) diff --git a/common/board_r.c b/common/board_r.c index be225d8f87..bac386f021 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -33,16 +33,11 @@ #include #include #include -/* TODO: can we just include all these headers whether needed or not? */ -#if defined(CONFIG_CMD_KGDB) #include -#endif #include #include #include -#ifdef CONFIG_BITBANGMII #include -#endif #include #include #include @@ -56,9 +51,7 @@ #include #include #include -#ifdef CONFIG_XEN #include -#endif #include #include #include @@ -67,9 +60,7 @@ #include #include #include -#ifdef CONFIG_EFI_SETUP_EARLY #include -#endif DECLARE_GLOBAL_DATA_PTR; -- 2.25.1
[PATCH v2 1/7] common: spl: move armv7m-specific code to spl_perform_fixups()
Factor out armv7m fragment to spl_perform_fixups(), which is an arch/board
specific function designed for this purpose.
Reviewed-by: Simon Glass
Signed-off-by: Ovidiu Panait
---
(no changes since v1)
arch/arm/cpu/armv7m/cpu.c | 6 ++
common/spl/spl.c | 3 ---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c
index 63721018c1..65427b5312 100644
--- a/arch/arm/cpu/armv7m/cpu.c
+++ b/arch/arm/cpu/armv7m/cpu.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
/*
* This is called right before passing control to
@@ -56,3 +57,8 @@ void reset_cpu(void)
| (V7M_SCB->aircr & V7M_AIRCR_PRIGROUP_MSK)
| V7M_AIRCR_SYSRESET, _SCB->aircr);
}
+
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+ spl_image->entry_point |= 0x1;
+}
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 4c101ec5d3..dab0f5fe38 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -770,9 +770,6 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
ret);
}
-#ifdef CONFIG_CPU_V7M
- spl_image.entry_point |= 0x1;
-#endif
switch (spl_image.os) {
case IH_OS_U_BOOT:
debug("Jumping to %s...\n", spl_phase_name(spl_next_phase()));
--
2.25.1
[PATCH v2 6/7] common: board_r: include asm-generic/gpio.h
Not all architectures define and even on those that do, the header cannot be included for all boards without causing various build failures. Since common/board_r.c only needs gpio_hog_probe_all() declaration, include and drop the associated ifdef. Reviewed-by: Simon Glass Signed-off-by: Ovidiu Panait --- (no changes since v1) common/board_r.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/common/board_r.c b/common/board_r.c index 7c45e494ed..be225d8f87 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -66,9 +66,7 @@ #include #include #include -#if defined(CONFIG_GPIO_HOG) -#include -#endif +#include #ifdef CONFIG_EFI_SETUP_EARLY #include #endif -- 2.25.1
[PATCH v2 4/7] common: board_r: drop initr_addr_map wrapper
Add a return value to init_addr_map and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.
Reviewed-by: Matthias Brugger
Reviewed-by: Simon Glass
Signed-off-by: Ovidiu Panait
---
(no changes since v1)
arch/arm/include/asm/mmu.h | 2 +-
arch/arm/mach-bcm283x/init.c | 4 +++-
arch/powerpc/cpu/mpc85xx/tlb.c | 4 ++--
arch/powerpc/include/asm/mmu.h | 2 +-
common/board_r.c | 11 +--
5 files changed, 8 insertions(+), 15 deletions(-)
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index 9ac16f599e..8449720fad 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -3,6 +3,6 @@
#ifndef __ASM_ARM_MMU_H
#define __ASM_ARM_MMU_H
-void init_addr_map(void);
+int init_addr_map(void);
#endif
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 9803499985..183650a90a 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -152,7 +152,7 @@ int mach_cpu_init(void)
#include
#include
-void init_addr_map(void)
+int init_addr_map(void)
{
mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
@@ -165,6 +165,8 @@ void init_addr_map(void)
addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
+
+ return 0;
}
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 973b6fbe4b..aa9b59d487 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -219,7 +219,7 @@ int find_tlb_idx(void *addr, u8 tlbsel)
}
#ifdef CONFIG_ADDR_MAP
-void init_addr_map(void)
+int init_addr_map(void)
{
int i;
unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
@@ -235,7 +235,7 @@ void init_addr_map(void)
addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i);
}
- return ;
+ return 0;
}
#endif
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 353dc4e874..cb5b26cd77 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -138,7 +138,7 @@ extern void _tlbie(unsigned long va); /* invalidate a
TLB entry */
extern void _tlbia(void); /* invalidate all TLB entries */
#ifdef CONFIG_ADDR_MAP
-extern void init_addr_map(void);
+extern int init_addr_map(void);
#endif
typedef enum {
diff --git a/common/board_r.c b/common/board_r.c
index 5905921caa..b0840c70b2 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -186,15 +186,6 @@ __weak int arch_initr_trap(void)
return 0;
}
-#ifdef CONFIG_ADDR_MAP
-static int initr_addr_map(void)
-{
- init_addr_map();
-
- return 0;
-}
-#endif
-
#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
static int initr_unlock_ram_in_cache(void)
{
@@ -623,7 +614,7 @@ static init_fnc_t init_sequence_r[] = {
initr_dm,
#endif
#ifdef CONFIG_ADDR_MAP
- initr_addr_map,
+ init_addr_map,
#endif
#if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || defined(CONFIG_RISCV) || \
defined(CONFIG_SANDBOX)
--
2.25.1
[PATCH v2 3/7] common: board_r: drop initr_kgdb wrapper
Add a return value to kgdb_init and use it directly in the post-relocation
init sequence, rather than using a wrapper stub. Also, move the "KGDB"
print message inside kgdb_init().
Reviewed-by: Simon Glass
Signed-off-by: Ovidiu Panait
---
Changes in v2:
- drop extern and add function comment
common/board_r.c | 11 +--
common/kgdb.c| 7 +--
include/kgdb.h | 11 ++-
3 files changed, 16 insertions(+), 13 deletions(-)
diff --git a/common/board_r.c b/common/board_r.c
index cc0e6fa92e..5905921caa 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -498,15 +498,6 @@ static int initr_ethaddr(void)
}
#endif /* CONFIG_CMD_NET */
-#ifdef CONFIG_CMD_KGDB
-static int initr_kgdb(void)
-{
- puts("KGDB: ");
- kgdb_init();
- return 0;
-}
-#endif
-
#if defined(CONFIG_LED_STATUS)
static int initr_status_led(void)
{
@@ -745,7 +736,7 @@ static init_fnc_t init_sequence_r[] = {
#endif
INIT_FUNC_WATCHDOG_RESET
#ifdef CONFIG_CMD_KGDB
- initr_kgdb,
+ kgdb_init,
#endif
interrupt_init,
#if defined(CONFIG_MICROBLAZE) || defined(CONFIG_M68K)
diff --git a/common/kgdb.c b/common/kgdb.c
index 4493a15919..29b09fcfe5 100644
--- a/common/kgdb.c
+++ b/common/kgdb.c
@@ -527,15 +527,18 @@ handle_exception (struct pt_regs *regs)
* kgdb_init must be called *after* the
* monitor is relocated into ram
*/
-void
-kgdb_init(void)
+int kgdb_init(void)
{
+ puts("KGDB: ");
+
kgdb_serial_init();
debugger_exception_handler = handle_exception;
initialized = 1;
putDebugStr("kgdb ready\n");
puts("ready\n");
+
+ return 0;
}
void
diff --git a/include/kgdb.h b/include/kgdb.h
index 616ce4451f..bdba347a7f 100644
--- a/include/kgdb.h
+++ b/include/kgdb.h
@@ -39,7 +39,16 @@ typedef
kgdb_data;
/* these functions are provided by the generic kgdb support */
-extern void kgdb_init(void);
+/**
+ * kgdb_init()
+ *
+ * Perform initializations to allow debugging U-Boot with gdb over a serial
+ * link. It is called during the generic board init sequence.
+ *
+ * Return: 0 if OK
+ */
+int kgdb_init(void);
+
extern void kgdb_error(int);
extern int kgdb_output_string(const char *, unsigned int);
extern void breakpoint(void);
--
2.25.1
[RESEND PATCH 1/7] common: spl: move armv7m-specific code to spl_perform_fixups()
Factor out armv7m fragment to spl_perform_fixups(), which is an arch/board
specific function designed for this purpose.
Signed-off-by: Ovidiu Panait
---
arch/arm/cpu/armv7m/cpu.c | 6 ++
common/spl/spl.c | 3 ---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c
index 63721018c1..65427b5312 100644
--- a/arch/arm/cpu/armv7m/cpu.c
+++ b/arch/arm/cpu/armv7m/cpu.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
/*
* This is called right before passing control to
@@ -56,3 +57,8 @@ void reset_cpu(void)
| (V7M_SCB->aircr & V7M_AIRCR_PRIGROUP_MSK)
| V7M_AIRCR_SYSRESET, _SCB->aircr);
}
+
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+ spl_image->entry_point |= 0x1;
+}
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 4c101ec5d3..dab0f5fe38 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -770,9 +770,6 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
ret);
}
-#ifdef CONFIG_CPU_V7M
- spl_image.entry_point |= 0x1;
-#endif
switch (spl_image.os) {
case IH_OS_U_BOOT:
debug("Jumping to %s...\n", spl_phase_name(spl_next_phase()));
--
2.25.1
[RESEND PATCH 7/7] common: board_r: drop ifdefs around header includes
Drop the remaining ifdefs around header includes, to fix an old TODO. Signed-off-by: Ovidiu Panait --- common/board_r.c | 9 - 1 file changed, 9 deletions(-) diff --git a/common/board_r.c b/common/board_r.c index 506aa446fc..18a4849420 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -33,16 +33,11 @@ #include #include #include -/* TODO: can we just include all these headers whether needed or not? */ -#if defined(CONFIG_CMD_KGDB) #include -#endif #include #include #include -#ifdef CONFIG_BITBANGMII #include -#endif #include #include #include @@ -56,9 +51,7 @@ #include #include #include -#ifdef CONFIG_XEN #include -#endif #include #include #include @@ -67,9 +60,7 @@ #include #include #include -#ifdef CONFIG_EFI_SETUP_EARLY #include -#endif DECLARE_GLOBAL_DATA_PTR; -- 2.25.1
[RESEND PATCH 5/7] common: board_r: move init_addr_map() to init.h
asm/mmu.h include is currently guarded by CONFIG_ADDR_MAP ifdef because
the header is only present on arm and powerpc. In order to remove the
dependency on this header and the associated ifdef, move init_addr_map()
declaration to init.h, since it is only called during the common init sequence.
Signed-off-by: Ovidiu Panait
---
arch/arm/include/asm/mmu.h | 8
arch/powerpc/cpu/mpc85xx/tlb.c | 1 +
arch/powerpc/include/asm/mmu.h | 4
board/freescale/common/fsl_chain_of_trust.c | 5 +
common/board_r.c| 3 ---
include/init.h | 10 ++
6 files changed, 12 insertions(+), 19 deletions(-)
delete mode 100644 arch/arm/include/asm/mmu.h
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
deleted file mode 100644
index 8449720fad..00
--- a/arch/arm/include/asm/mmu.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-
-#ifndef __ASM_ARM_MMU_H
-#define __ASM_ARM_MMU_H
-
-int init_addr_map(void);
-
-#endif
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index aa9b59d487..550d45da0e 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -7,6 +7,7 @@
*/
#include
+#include
#include
#include
#include
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index cb5b26cd77..2e6255f0d6 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -137,10 +137,6 @@ typedef struct _MMU_context {
extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
extern void _tlbia(void); /* invalidate all TLB entries */
-#ifdef CONFIG_ADDR_MAP
-extern int init_addr_map(void);
-#endif
-
typedef enum {
IBAT0 = 0, IBAT1, IBAT2, IBAT3,
DBAT0, DBAT1, DBAT2, DBAT3,
diff --git a/board/freescale/common/fsl_chain_of_trust.c
b/board/freescale/common/fsl_chain_of_trust.c
index cafb24971b..7ffb315bc9 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -16,10 +17,6 @@
#include
#endif
-#ifdef CONFIG_ADDR_MAP
-#include
-#endif
-
#ifdef CONFIG_FSL_CORENET
#include
#endif
diff --git a/common/board_r.c b/common/board_r.c
index 0b8f2a0b91..af900e2c6e 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -59,9 +59,6 @@
#ifdef CONFIG_XEN
#include
#endif
-#ifdef CONFIG_ADDR_MAP
-#include
-#endif
#include
#include
#include
diff --git a/include/init.h b/include/init.h
index 7e0149c004..41ff3f435b 100644
--- a/include/init.h
+++ b/include/init.h
@@ -318,6 +318,16 @@ int arch_initr_trap(void);
*/
int bedbug_init(void);
+/**
+ * init_addr_map()
+ *
+ * Initialize non-identity virtual-physical memory mappings for 32bit CPUs.
+ * It is called during the generic board init sequence, after relocation.
+ *
+ * Return: 0 if OK
+ */
+int init_addr_map(void);
+
/**
* main_loop() - Enter the main loop of U-Boot
*
--
2.25.1
[RESEND PATCH 2/7] common: board_r: move bedbug_init() to common code
bedbug/types.h is included to provide bedbug_init() declaration, which is
an empty stub that is only called from the common init sequence. In order
to get rid of this dependency and the associated #ifdef:
* move the bedbug_init() declaration from include/bedbug/type.h to
include/init.h
* provide a weak stub for bedbug_init() in board_r.c, so each CPU can
provide its own implementation, as explained in the function comment
Signed-off-by: Ovidiu Panait
---
cmd/bedbug.c | 14 --
common/board_r.c | 10 ++
include/bedbug/type.h | 1 -
include/init.h| 11 +++
4 files changed, 17 insertions(+), 19 deletions(-)
diff --git a/cmd/bedbug.c b/cmd/bedbug.c
index 0bd67fcf47..7fc206bd26 100644
--- a/cmd/bedbug.c
+++ b/cmd/bedbug.c
@@ -38,20 +38,6 @@ int bedbug_puts (const char *str)
return 0;
} /* bedbug_puts */
-
-/* ==
- * Initialize the bug_ctx structure used by the bedbug debugger. This is
- * specific to the CPU since each has different debug registers and
- * settings.
- * == */
-
-int bedbug_init(void)
-{
- /* -- */
- return 0;
-} /* bedbug_init */
-
-
/* ==
* Entry point from the interpreter to the disassembler. Repeated calls
* will resume from the last disassembled address.
diff --git a/common/board_r.c b/common/board_r.c
index 31a59c585a..a5c1af9c1f 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -23,10 +23,6 @@
#include
#include
#include
-/* TODO: can we just include all these headers whether needed or not? */
-#if defined(CONFIG_CMD_BEDBUG)
-#include
-#endif
#include
#include
#include
@@ -37,6 +33,7 @@
#include
#include
#include
+/* TODO: can we just include all these headers whether needed or not? */
#if defined(CONFIG_CMD_KGDB)
#include
#endif
@@ -568,6 +565,11 @@ static int initr_ide(void)
}
#endif
+__weak int bedbug_init(void)
+{
+ return 0;
+}
+
#if defined(CONFIG_PRAM)
/*
* Export available size of memory for Linux, taking into account the
diff --git a/include/bedbug/type.h b/include/bedbug/type.h
index f7a719caf0..99c3d4d83e 100644
--- a/include/bedbug/type.h
+++ b/include/bedbug/type.h
@@ -5,7 +5,6 @@ struct cmd_tbl;
/* Supporting routines */
int bedbug_puts (const char *);
-int bedbug_init(void);
void bedbug860_init (void);
void do_bedbug_breakpoint (struct pt_regs *);
void bedbug_main_loop (unsigned long, struct pt_regs *);
diff --git a/include/init.h b/include/init.h
index f2cd46dead..7e0149c004 100644
--- a/include/init.h
+++ b/include/init.h
@@ -307,6 +307,17 @@ int board_early_init_r(void);
*/
int arch_initr_trap(void);
+/**
+ * bedbug_init() - init bedbug debugger
+ *
+ * Initialize the bug_ctx structure used by the bedbug debugger. This is
+ * specific to the CPU since each has different debug registers and
+ * settings.
+ *
+ * Return: 0 if OK
+ */
+int bedbug_init(void);
+
/**
* main_loop() - Enter the main loop of U-Boot
*
--
2.25.1
[RESEND PATCH 4/7] common: board_r: drop initr_addr_map wrapper
Add a return value to init_addr_map and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.
Reviewed-by: Matthias Brugger
Reviewed-by: Simon Glass
Signed-off-by: Ovidiu Panait
---
arch/arm/include/asm/mmu.h | 2 +-
arch/arm/mach-bcm283x/init.c | 4 +++-
arch/powerpc/cpu/mpc85xx/tlb.c | 4 ++--
arch/powerpc/include/asm/mmu.h | 2 +-
common/board_r.c | 11 +--
5 files changed, 8 insertions(+), 15 deletions(-)
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index 9ac16f599e..8449720fad 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -3,6 +3,6 @@
#ifndef __ASM_ARM_MMU_H
#define __ASM_ARM_MMU_H
-void init_addr_map(void);
+int init_addr_map(void);
#endif
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 9803499985..183650a90a 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -152,7 +152,7 @@ int mach_cpu_init(void)
#include
#include
-void init_addr_map(void)
+int init_addr_map(void)
{
mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
@@ -165,6 +165,8 @@ void init_addr_map(void)
addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
+
+ return 0;
}
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 973b6fbe4b..aa9b59d487 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -219,7 +219,7 @@ int find_tlb_idx(void *addr, u8 tlbsel)
}
#ifdef CONFIG_ADDR_MAP
-void init_addr_map(void)
+int init_addr_map(void)
{
int i;
unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
@@ -235,7 +235,7 @@ void init_addr_map(void)
addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i);
}
- return ;
+ return 0;
}
#endif
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 353dc4e874..cb5b26cd77 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -138,7 +138,7 @@ extern void _tlbie(unsigned long va); /* invalidate a
TLB entry */
extern void _tlbia(void); /* invalidate all TLB entries */
#ifdef CONFIG_ADDR_MAP
-extern void init_addr_map(void);
+extern int init_addr_map(void);
#endif
typedef enum {
diff --git a/common/board_r.c b/common/board_r.c
index 1c7397b29e..0b8f2a0b91 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -186,15 +186,6 @@ __weak int arch_initr_trap(void)
return 0;
}
-#ifdef CONFIG_ADDR_MAP
-static int initr_addr_map(void)
-{
- init_addr_map();
-
- return 0;
-}
-#endif
-
#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
static int initr_unlock_ram_in_cache(void)
{
@@ -628,7 +619,7 @@ static init_fnc_t init_sequence_r[] = {
initr_dm,
#endif
#ifdef CONFIG_ADDR_MAP
- initr_addr_map,
+ init_addr_map,
#endif
#if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || defined(CONFIG_RISCV) || \
defined(CONFIG_SANDBOX)
--
2.25.1
[RESEND PATCH 6/7] common: board_r: include asm-generic/gpio.h
Not all architectures define and even on those that do, the header cannot be included for all boards without causing various build failures. Since common/board_r.c only needs gpio_hog_probe_all() declaration, include and drop the associated ifdef. Signed-off-by: Ovidiu Panait --- common/board_r.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/common/board_r.c b/common/board_r.c index af900e2c6e..506aa446fc 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -66,9 +66,7 @@ #include #include #include -#if defined(CONFIG_GPIO_HOG) -#include -#endif +#include #ifdef CONFIG_EFI_SETUP_EARLY #include #endif -- 2.25.1
[RESEND PATCH 3/7] common: board_r: drop initr_kgdb wrapper
Add a return value to kgdb_init and use it directly in the post-relocation
init sequence, rather than using a wrapper stub. Also, move the "KGDB"
print message inside kgdb_init().
Signed-off-by: Ovidiu Panait
---
common/board_r.c | 11 +--
common/kgdb.c| 7 +--
include/kgdb.h | 2 +-
3 files changed, 7 insertions(+), 13 deletions(-)
diff --git a/common/board_r.c b/common/board_r.c
index a5c1af9c1f..1c7397b29e 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -498,15 +498,6 @@ static int initr_ethaddr(void)
}
#endif /* CONFIG_CMD_NET */
-#ifdef CONFIG_CMD_KGDB
-static int initr_kgdb(void)
-{
- puts("KGDB: ");
- kgdb_init();
- return 0;
-}
-#endif
-
#if defined(CONFIG_LED_STATUS)
static int initr_status_led(void)
{
@@ -750,7 +741,7 @@ static init_fnc_t init_sequence_r[] = {
#endif
INIT_FUNC_WATCHDOG_RESET
#ifdef CONFIG_CMD_KGDB
- initr_kgdb,
+ kgdb_init,
#endif
interrupt_init,
#if defined(CONFIG_MICROBLAZE) || defined(CONFIG_M68K)
diff --git a/common/kgdb.c b/common/kgdb.c
index 4493a15919..29b09fcfe5 100644
--- a/common/kgdb.c
+++ b/common/kgdb.c
@@ -527,15 +527,18 @@ handle_exception (struct pt_regs *regs)
* kgdb_init must be called *after* the
* monitor is relocated into ram
*/
-void
-kgdb_init(void)
+int kgdb_init(void)
{
+ puts("KGDB: ");
+
kgdb_serial_init();
debugger_exception_handler = handle_exception;
initialized = 1;
putDebugStr("kgdb ready\n");
puts("ready\n");
+
+ return 0;
}
void
diff --git a/include/kgdb.h b/include/kgdb.h
index 616ce4451f..0609eadade 100644
--- a/include/kgdb.h
+++ b/include/kgdb.h
@@ -39,7 +39,7 @@ typedef
kgdb_data;
/* these functions are provided by the generic kgdb support */
-extern void kgdb_init(void);
+extern int kgdb_init(void);
extern void kgdb_error(int);
extern int kgdb_output_string(const char *, unsigned int);
extern void breakpoint(void);
--
2.25.1
[PATCH v3] xilinx: Kconfig: add XILINX_OF_BOARD_DTB_ADDR default value for microblaze
The xilinx board_fdt_blob_setup() implementation makes use of XILINX_OF_BOARD_DTB_ADDR, but no default value is currently defined for microblaze. Add one so that microblaze could also work with CONFIG_OF_SEPARATE. Signed-off-by: Ovidiu Panait --- board/xilinx/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index 64507b5d84..1788066173 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -43,6 +43,7 @@ endif config XILINX_OF_BOARD_DTB_ADDR hex "Default DTB pickup address" default 0x1000 if ARCH_VERSAL + default 0x8000 if MICROBLAZE default 0x10 if ARCH_ZYNQ || ARCH_ZYNQMP depends on OF_BOARD || OF_SEPARATE help -- 2.25.1
Re: [PATCH v2 01/10] xilinx: Kconfig: add XILINX_OF_BOARD_DTB_ADDR default value for microblaze
Hi Michal, On 12/1/21 12:10 PM, Michal Simek wrote: [Please note: This e-mail is from an EXTERNAL e-mail address] On 11/30/21 17:33, Ovidiu Panait wrote: Xilinx board_fdt_blob_setup() implementation makes use of XILINX_OF_BOARD_DTB_ADDR Kconfig option, but no default value is currently defined for microblaze. Add one so that microblaze could also be configured with CONFIG_OF_SEPARATE. Signed-off-by: Ovidiu Panait --- (no changes since v1) board/xilinx/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index 64507b5d84..9e69166903 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -43,7 +43,7 @@ endif config XILINX_OF_BOARD_DTB_ADDR hex "Default DTB pickup address" default 0x1000 if ARCH_VERSAL - default 0x10 if ARCH_ZYNQ || ARCH_ZYNQMP + default 0x10 if ARCH_ZYNQ || ARCH_ZYNQMP || MICROBLAZE depends on OF_BOARD || OF_SEPARATE help Offset in the memory where the board configuration DTB is placed. First of all I applied patches 2-10. And let's have short discussion about this default address. 1MB is quite high for DTB. In standard system when you have brams you likely don't have more 1MB. That's why this default is not the best. I didn't use microblaze spl for a while but from build it has ~30kB. Not sure where I did setup stack, early malloc area but I think having place around 32kB/64kB would be more reasonable default because you will have brams there. And having dtb in bram is likely better because it can be the part of bitstream. Can you please elaborate a little bit why you choose 1M for microblaze? You're right, 1MB is not appropriate for microblaze. I can respin this patch and change it to 32kB. My initial intention with patches 1/10 and 2/10 was to switch microblaze from CONFIG_OF_EMBEDDED -> CONFIG_OF_SEPARATE, but then I realized that the updatemem utility used to bundle spl and bitstream together can only operate on ELF files. Since for CONFIG_OF_SEPARATE the generated u-boot-spl ELF does not contain the dtb, I abandoned the idea, but I still included the patches to at least fix the compilation errors. So I haven't really put much thought into what default address would be appropriate for microblaze. Ovidiu Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
[PATCH v2 07/10] microblaze: migrate CONFIG_SYS_USR_EXCEP to Kconfig
Migrate CONFIG_SYS_USR_EXCEP to Kconfig. Also, rename it to
XILINX_MICROBLAZE0_USR_EXCEP in order to match the naming convention of
microblaze-generic Kconfig options.
Signed-off-by: Ovidiu Panait
---
Changes in v2:
Added Kconfig option description.
arch/microblaze/cpu/exception.c | 2 +-
arch/microblaze/cpu/start.S | 2 +-
board/xilinx/microblaze-generic/Kconfig | 9 +
include/configs/microblaze-generic.h| 2 --
scripts/config_whitelist.txt| 1 -
5 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
index b8dedc4e19..e9476abedb 100644
--- a/arch/microblaze/cpu/exception.c
+++ b/arch/microblaze/cpu/exception.c
@@ -55,7 +55,7 @@ void _hw_exception_handler (void)
hang();
}
-#ifdef CONFIG_SYS_USR_EXCEP
+#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP)
void _exception_handler (void)
{
puts("User vector_exception\n");
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 74ed998c55..68f97f426c 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -144,7 +144,7 @@ __setup_exceptions:
rsubi r8, r10, 0x6
sh r6, r0, r8
-#ifdef CONFIG_SYS_USR_EXCEP
+#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP)
/* user_vector_exception */
swi r2, r0, 0x8 /* user vector exception - imm opcode */
swi r3, r0, 0xC /* user vector exception - brai opcode */
diff --git a/board/xilinx/microblaze-generic/Kconfig
b/board/xilinx/microblaze-generic/Kconfig
index f2fa0f72b1..3e3eca0e80 100644
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -38,4 +38,13 @@ config XILINX_MICROBLAZE0_HW_VER
string "Core version number"
default "7.10.d"
+config XILINX_MICROBLAZE0_USR_EXCEP
+ bool "MicroBlaze user exception support"
+ default y
+ help
+ Enable this option in order to install the user exception handler
+ (_exception_handler routine from arch/microblaze/cpu/exception.c) in
+ the exception vector table. The user exception vector is located at
+ C_BASE_VECTORS + 0x8 address.
+
endif
diff --git a/include/configs/microblaze-generic.h
b/include/configs/microblaze-generic.h
index 975580e4d4..28f67e30d5 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -54,8 +54,6 @@
#defineCONFIG_HOSTNAME "microblaze-generic"
/* architecture dependent code */
-#defineCONFIG_SYS_USR_EXCEP/* user exception */
-
#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
#else
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index b9c1c61e13..c53c2c3801 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -2870,7 +2870,6 @@ CONFIG_SYS_USE_MMC
CONFIG_SYS_USE_NAND
CONFIG_SYS_USE_NANDFLASH
CONFIG_SYS_USE_NORFLASH
-CONFIG_SYS_USR_EXCEP
CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR
CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN
CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT
--
2.25.1
[PATCH v2 09/10] microblaze: start.S: add support for configurable vector base address
Current code assumes that the vector base address is always at 0x0. However, this value is configurable for MicroBlaze, so update the __setup_exceptions routine to work with any vector base address. The r4 register is reserved for the vector base address inside __setup_exceptions and the function prologe/epilogue are also updated to save and restore r4. Signed-off-by: Ovidiu Panait --- (no changes since v1) arch/microblaze/cpu/start.S | 58 - 1 file changed, 32 insertions(+), 26 deletions(-) diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 68f97f426c..645f7cb038 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -105,15 +105,17 @@ clear_bss: * r10: Stores little/big endian offset for vectors * r2: Stores imm opcode * r3: Stores brai opcode + * r4: Stores the vector base address */ __setup_exceptions: - addik r1, r1, -28 + addik r1, r1, -32 swi r2, r1, 4 swi r3, r1, 8 - swi r6, r1, 12 - swi r7, r1, 16 - swi r8, r1, 20 - swi r10, r1, 24 + swi r4, r1, 12 + swi r6, r1, 16 + swi r7, r1, 20 + swi r8, r1, 24 + swi r10, r1, 28 /* Find-out if u-boot is running on BIG/LITTLE endian platform * There are some steps which is necessary to keep in mind: @@ -132,22 +134,25 @@ __setup_exceptions: addir2, r0, 0xb000 /* hex b000 opcode imm */ addir3, r0, 0xb808 /* hew b808 opcode brai */ + /* Store the vector base address in r4 */ + addir4, r0, CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR + /* reset address */ - swi r2, r0, 0x0 /* reset address - imm opcode */ - swi r3, r0, 0x4 /* reset address - brai opcode */ + swi r2, r4, 0x0 /* reset address - imm opcode */ + swi r3, r4, 0x4 /* reset address - brai opcode */ addik r6, r0, CONFIG_SYS_TEXT_BASE sw r6, r1, r0 lhu r7, r1, r10 rsubi r8, r10, 0x2 - sh r7, r0, r8 + sh r7, r4, r8 rsubi r8, r10, 0x6 - sh r6, r0, r8 + sh r6, r4, r8 #if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP) /* user_vector_exception */ - swi r2, r0, 0x8 /* user vector exception - imm opcode */ - swi r3, r0, 0xC /* user vector exception - brai opcode */ + swi r2, r4, 0x8 /* user vector exception - imm opcode */ + swi r3, r4, 0xC /* user vector exception - brai opcode */ addik r6, r5, _exception_handler sw r6, r1, r0 @@ -173,42 +178,43 @@ __setup_exceptions: */ lhu r7, r1, r10 rsubi r8, r10, 0xa - sh r7, r0, r8 + sh r7, r4, r8 rsubi r8, r10, 0xe - sh r6, r0, r8 + sh r6, r4, r8 #endif /* interrupt_handler */ - swi r2, r0, 0x10/* interrupt - imm opcode */ - swi r3, r0, 0x14/* interrupt - brai opcode */ + swi r2, r4, 0x10/* interrupt - imm opcode */ + swi r3, r4, 0x14/* interrupt - brai opcode */ addik r6, r5, _interrupt_handler sw r6, r1, r0 lhu r7, r1, r10 rsubi r8, r10, 0x12 - sh r7, r0, r8 + sh r7, r4, r8 rsubi r8, r10, 0x16 - sh r6, r0, r8 + sh r6, r4, r8 /* hardware exception */ - swi r2, r0, 0x20/* hardware exception - imm opcode */ - swi r3, r0, 0x24/* hardware exception - brai opcode */ + swi r2, r4, 0x20/* hardware exception - imm opcode */ + swi r3, r4, 0x24/* hardware exception - brai opcode */ addik r6, r5, _hw_exception_handler sw r6, r1, r0 lhu r7, r1, r10 rsubi r8, r10, 0x22 - sh r7, r0, r8 + sh r7, r4, r8 rsubi r8, r10, 0x26 - sh r6, r0, r8 + sh r6, r4, r8 - lwi r10, r1, 24 - lwi r8, r1, 20 - lwi r7, r1, 16 - lwi r6, r1, 12 + lwi r10, r1, 28 + lwi r8, r1, 24 + lwi r7, r1, 20 + lwi r6, r1, 16 + lwi r4, r1, 12 lwi r3, r1, 8 lwi r2, r1, 4 - addik r1, r1, 28 + addik r1, r1, 32 rtsdr15, 8 or r0, r0, r0 -- 2.25.1
[PATCH v2 10/10] microblaze: branch to base vector address on reset
Current code assumes that the vector base address is always at 0x0.
However, this value is configurable for MicroBlaze using the
CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR Kconfig option. Update the
reset routines to branch to this location instead.
Signed-off-by: Ovidiu Panait
---
(no changes since v1)
arch/microblaze/cpu/spl.c | 6 --
drivers/sysreset/sysreset_microblaze.c | 6 --
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c
index 06d4af99b2..cea6d56f16 100644
--- a/arch/microblaze/cpu/spl.c
+++ b/arch/microblaze/cpu/spl.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
bool boot_linux;
@@ -54,8 +55,9 @@ int spl_start_uboot(void)
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
- __asm__ __volatile__ ("mts rmsr, r0;" \
- "bra r0");
+ __asm__ __volatile__ (
+ "mts rmsr, r0;" \
+ "brai " __stringify(CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR));
return 0;
}
diff --git a/drivers/sysreset/sysreset_microblaze.c
b/drivers/sysreset/sysreset_microblaze.c
index 514c95817f..83a7f77ac4 100644
--- a/drivers/sysreset/sysreset_microblaze.c
+++ b/drivers/sysreset/sysreset_microblaze.c
@@ -8,13 +8,15 @@
#include
#include
#include
+#include
static int microblaze_sysreset_request(struct udevice *dev,
enum sysreset_t type)
{
puts("Microblaze soft reset sysreset\n");
- __asm__ __volatile__ (" mts rmsr, r0;" \
- "bra r0");
+ __asm__ __volatile__ (
+ "mts rmsr, r0;" \
+ "brai " __stringify(CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR));
return -EINPROGRESS;
}
--
2.25.1
[PATCH v2 08/10] microblaze: add Kconfig symbol for the vector base address
MicroBlaze vector base address is configurable (hdl C_BASE_VECTORS configuration parameter). Current code assumes that the reset vector location is always 0x0. Add the XILINX_MICROBLAZE0_VECTOR_BASE_ADDR Kconfig option so the user can adjust the reset vector address. Signed-off-by: Ovidiu Panait --- Changes in v2: Added Kconfig option description. board/xilinx/microblaze-generic/Kconfig | 7 +++ 1 file changed, 7 insertions(+) diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig index 3e3eca0e80..e31257d335 100644 --- a/board/xilinx/microblaze-generic/Kconfig +++ b/board/xilinx/microblaze-generic/Kconfig @@ -47,4 +47,11 @@ config XILINX_MICROBLAZE0_USR_EXCEP the exception vector table. The user exception vector is located at C_BASE_VECTORS + 0x8 address. +config XILINX_MICROBLAZE0_VECTOR_BASE_ADDR + hex "Location of MicroBlaze vectors" + default 0x0 + help + Memory address location of the exception vector table. It is + configurable via the C_BASE_VECTORS hdl parameter. + endif -- 2.25.1
[PATCH v2 06/10] microblaze: drop CONFIG_SYS_RESET_ADDRESS macro
Microblaze is one the last two users of the CONFIG_SYS_RESET_ADDRESS
macro (the other is arch/powerpc/cpu/mpc8xx/cpu.c, but the macro is not
defined anywhere in powerpc code, so it should be removed there too).
Replace CONFIG_SYS_RESET_ADDRESS usage in start.S with
CONFIG_SYS_TEXT_BASE. If the reset address should really be
user-configurable, a new Kconfig option could be added.
Signed-off-by: Ovidiu Panait
---
(no changes since v1)
arch/microblaze/cpu/start.S | 4 +---
include/configs/microblaze-generic.h | 3 ---
2 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index a1c06108d7..74ed998c55 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -132,19 +132,17 @@ __setup_exceptions:
addir2, r0, 0xb000 /* hex b000 opcode imm */
addir3, r0, 0xb808 /* hew b808 opcode brai */
-#ifdef CONFIG_SYS_RESET_ADDRESS
/* reset address */
swi r2, r0, 0x0 /* reset address - imm opcode */
swi r3, r0, 0x4 /* reset address - brai opcode */
- addik r6, r0, CONFIG_SYS_RESET_ADDRESS
+ addik r6, r0, CONFIG_SYS_TEXT_BASE
sw r6, r1, r0
lhu r7, r1, r10
rsubi r8, r10, 0x2
sh r7, r0, r8
rsubi r8, r10, 0x6
sh r6, r0, r8
-#endif
#ifdef CONFIG_SYS_USR_EXCEP
/* user_vector_exception */
diff --git a/include/configs/microblaze-generic.h
b/include/configs/microblaze-generic.h
index e7882fb607..975580e4d4 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -21,9 +21,6 @@
# define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-/* setting reset address */
-/*#define CONFIG_SYS_RESET_ADDRESSCONFIG_SYS_TEXT_BASE*/
-
/* Stack location before relocation */
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_F_LEN)
--
2.25.1
[PATCH v2 03/10] microblaze: spl: add board_boot_order() implementation
Microblaze has three boot modes defined in microblaze/include/asm/spl.h,
but only booting from NOR flash is currently useable. Add a custom
board_boot_order() implementation so that RAM and SPI boot modes can also
be selected if the corresponding load-image support is present.
Signed-off-by: Ovidiu Panait
---
(no changes since v1)
arch/microblaze/cpu/spl.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c
index 86522f8447..06d4af99b2 100644
--- a/arch/microblaze/cpu/spl.c
+++ b/arch/microblaze/cpu/spl.c
@@ -15,9 +15,11 @@
bool boot_linux;
-u32 spl_boot_device(void)
+void board_boot_order(u32 *spl_boot_list)
{
- return BOOT_DEVICE_NOR;
+ spl_boot_list[0] = BOOT_DEVICE_NOR;
+ spl_boot_list[1] = BOOT_DEVICE_RAM;
+ spl_boot_list[2] = BOOT_DEVICE_SPI;
}
/* Board initialization after bss clearance */
--
2.25.1
[PATCH v2 05/10] microblaze: start.S: use stack space as scratch memory for endian offset
To simpify the code, use stack space as scratch memory for endian offset calculation, rather than saving/restoring the first unused MB vector. Signed-off-by: Ovidiu Panait --- (no changes since v1) arch/microblaze/cpu/start.S | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 463e0feba4..a1c06108d7 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -125,10 +125,8 @@ __setup_exceptions: * 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3 */ addik r6, r0, 0x2 /* BIG/LITTLE endian offset */ - lwi r7, r0, 0x28 - swi r6, r0, 0x28 /* used first unused MB vector */ - lbuir10, r0, 0x28 /* used first unused MB vector */ - swi r7, r0, 0x28 + sw r6, r1, r0 + lbu r10, r1, r0 /* add opcode instruction for 32bit jump - 2 instruction imm & brai */ addir2, r0, 0xb000 /* hex b000 opcode imm */ -- 2.25.1
[PATCH v2 04/10] microblaze: Kconfig: SPL dependencies fixup
Enable SPL_LIBCOMMON_SUPPORT and SPL_LIBGENERIC_SUPPORT if CONFIG_SPL=y, in order to fix the following link failures: common/spl/spl.o: in function `board_init_r': common/spl/spl.c:755: undefined reference to `puts' ... common/spl/spl.o: in function `board_init_r': common/spl/spl.c:756: undefined reference to `hang' common/spl/spl.c:740: undefined reference to `memset' Signed-off-by: Ovidiu Panait --- (no changes since v1) arch/microblaze/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 99a17bccb3..a25a95a013 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -15,6 +15,8 @@ config TARGET_MICROBLAZE_GENERIC select DM_SERIAL select OF_CONTROL select SUPPORT_SPL + select SPL_LIBCOMMON_SUPPORT if SPL + select SPL_LIBGENERIC_SUPPORT if SPL select SYSRESET select DM_SPI select DM_SPI_FLASH -- 2.25.1
