Re: [PATCH v2] riscv: Add support for AMD/Xilinx MicroBlaze V
On Mon, 2023-11-06 at 12:56 +0100, Michal Simek wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
> It is hardware compatible with classic MicroBlaze processor.
>
> The patch contains initial wiring and configuration for initial HW
> design
> with memory, cpu, interrupt controller, timers and uartlite console
> (interrupt controller is listed but U-Boot is not using it).
>
> Provided DT is just describing one configuration and should be taken
> only
> as example.
>
> Signed-off-by: Michal Simek
> ---
>
> Changes in v2:
> - Extend commit message
> - DT changes, add interrupt controller, check agains dt schema
> - The patch for amd,mbv32 compatible string is here
> https://lore.kernel.org/r/d442d916204d26f82c1c3a924a4cdfb117960e1b.1699270661.git.michal.si...@amd.com
> - The patch for board compatibility is here
> https://lore.kernel.org/r/50c277c92c41a582ef171fb75efc6a6a4f860be2.1699271616.git.michal.si...@amd.com
>
> xlnx,xps-intc-1.00.a driver exists in the Linux kernel but DT binding
> is
> missing. That's something what we need to work on.
> arch/arm64/boot/dts/xilinx/xilinx-mbv32.dtb:
> /axi/interrupt-controller@4120: failed to match any schema with
> compatible: ['xlnx,xps-intc-1.00.a']
>
> Public annoucement is available here if someone is interested.
> https://www.xilinx.com/products/design-tools/microblaze-v.html?utm_source=marketo_medium=email_campaign=EN-EM-2023-11-02-New-MicroBlaze-V-Processor_term=btn_tok=NDA5LVdZWC03MjQAAAGPMMJYuPPscCags7WdvOeUSWy-_mC9aOwrobFaZRf5ok_eHoQUvTLBzJdHrkcBId9tQ4a-odfnU91WjUkIxx-iSG4OKGofjK5iZcAiK_VN8_xK
>
> ---
> arch/riscv/Kconfig | 4 +
> arch/riscv/dts/Makefile | 2 +
> arch/riscv/dts/xilinx-mbv32.dts | 106
> +++
> board/xilinx/Kconfig | 3 +-
> board/xilinx/common/board.c | 5 ++
> board/xilinx/mbv/Kconfig | 28 +++
> board/xilinx/mbv/MAINTAINERS | 7 ++
> board/xilinx/mbv/Makefile| 5 ++
> board/xilinx/mbv/board.c | 11 +++
> configs/xilinx_mbv32_defconfig | 30
> configs/xilinx_mbv32_smode_defconfig | 32
> include/configs/xilinx_mbv.h | 6 ++
> 12 files changed, 238 insertions(+), 1 deletion(-)
> create mode 100644 arch/riscv/dts/xilinx-mbv32.dts
> create mode 100644 board/xilinx/mbv/Kconfig
> create mode 100644 board/xilinx/mbv/MAINTAINERS
> create mode 100644 board/xilinx/mbv/Makefile
> create mode 100644 board/xilinx/mbv/board.c
> create mode 100644 configs/xilinx_mbv32_defconfig
> create mode 100644 configs/xilinx_mbv32_smode_defconfig
> create mode 100644 include/configs/xilinx_mbv.h
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 6d0d812ddb55..67126d96af89 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -39,6 +39,9 @@ config TARGET_TH1520_LPI4A
> bool "Support Sipeed's TH1520 Lichee PI 4A Board"
> select SYS_CACHE_SHIFT_6
>
> +config TARGET_XILINX_MBV
> + bool "Support AMD/Xilinx MicroBlaze V"
> +
> endchoice
>
> config SYS_ICACHE_OFF
> @@ -82,6 +85,7 @@ source "board/sifive/unmatched/Kconfig"
> source "board/sipeed/maix/Kconfig"
> source "board/starfive/visionfive2/Kconfig"
> source "board/thead/th1520_lpi4a/Kconfig"
> +source "board/xilinx/mbv/Kconfig"
>
> # platform-specific options below
> source "arch/riscv/cpu/andesv5/Kconfig"
> diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> index be6c8a422729..b05bb5607f06 100644
> --- a/arch/riscv/dts/Makefile
> +++ b/arch/riscv/dts/Makefile
> @@ -9,6 +9,8 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-
> unmatched-a00.dtb
> dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-
> visionfive-2.dtb
> dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
> +dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
> +
> include $(srctree)/scripts/Makefile.dts
>
> targets += $(dtb-y)
> diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-
> mbv32.dts
> new file mode 100644
> index ..6a6b8b694bd1
> --- /dev/null
> +++ b/arch/riscv/dts/xilinx-mbv32.dts
> @@ -0,0 +1,106 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * dts file for AMD MicroBlaze V
> + *
> + * (C) Copyright 2023, Advanced Micro Devices, Inc.
> + *
> + * Michal Simek
> + */
> +
> +/dts-v1/;
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + model = "AMD MicroBlaze V 32bit";
> + compatible = "amd,mbv";
> +
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <10200>;
> + cpu_0: cpu@0 {
> + compatible = "amd,mbv32", "riscv";
> + device_type = "cpu";
> +
Re: [PATCH v1 3/3] board: microchip: set mac address for ethernet1 on icicle
> On Wed, 2023-06-07 at 11:06 +0100, Conor Dooley wrote:
> The dts sync from Linux leaves mac0/ethernet1 enabled on icicle, but
> U-Boot does not currently set a mac address for it. Expand on the
> code
> which currently sets the mac for mac1/ethernet0 to optionally set the
> mac address for the second ethernet.
>
> Signed-off-by: Conor Dooley
> ---
> board/microchip/mpfs_icicle/mpfs_icicle.c | 15 ---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c
> b/board/microchip/mpfs_icicle/mpfs_icicle.c
> index e74c9fb03c..b4072acb18 100644
> --- a/board/microchip/mpfs_icicle/mpfs_icicle.c
> +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c
> @@ -80,7 +80,7 @@ int board_late_init(void)
> char icicle_mac_addr[20];
> void *blob = (void *)gd->fdt_blob;
>
> - node = fdt_path_offset(blob, "ethernet0");
> + node = fdt_path_offset(blob, "/soc/ethernet@20112000");
> if (node < 0) {
> printf("No ethernet0 path offset\n");
> return -ENODEV;
> @@ -88,7 +88,7 @@ int board_late_init(void)
>
> ret = fdtdec_get_byte_array(blob, node, "local-mac-address",
> mac_addr, 6);
> if (ret) {
> - printf("No local-mac-address property\n");
> + printf("No local-mac-address property for
> ethernet@20112000\n");
> return -EINVAL;
> }
>
> @@ -104,7 +104,7 @@ int board_late_init(void)
>
> ret = fdt_setprop(blob, node, "local-mac-address", mac_addr,
> 6);
> if (ret) {
> - printf("Error setting local-mac-address property\n");
> + printf("Error setting local-mac-address property for
> ethernet@20112000\n");
> return -ENODEV;
> }
>
> @@ -123,6 +123,15 @@ int board_late_init(void)
>
> mac_addr[5] = device_serial_number[0] + 1;
>
> + node = fdt_path_offset(blob, "/soc/ethernet@2011");
> + if (node >= 0) {
> + ret = fdt_setprop(blob, node, "local-mac-address",
> mac_addr, 6);
> + if (ret) {
> + printf("Error setting local-mac-address
> property for ethernet@20112000\n");
The print error is for ethernet@2011 not ethernet@20112000.
Other than that:
Reviewed-by: Padmarao Begari
Tested-by: Padmarao Begari
> + return -ENODEV;
> + }
> + }
> +
> icicle_mac_addr[0] = '[';
>
> sprintf(_mac_addr[1], "%pM", mac_addr);
Re: [PATCH v1 2/3] riscv: dts: sync mpfs-icicle devicetree with linux
> On Wed, 2023-06-07 at 11:06 +0100, Conor Dooley wrote:
> The "notable" disappearances are:
> - the pac193x stanza - there's nothing in mainline linux w.r.t.
> bindings
> for this & what is going to appear in mainline linux is going to be
> incompatible with what is currently in U-Boot.
> - operating points - these operating points should not be set at the
> soc.dtsi level as they may not be possible depending on the design
> programmed to the FPGA
> - clock output names - there are defines for the clock indices, these
> should not be needed
> - the dt maintainers in linux NAKed using defines for IRQ numbers
> - the qspi nand, which is not part of the icicle's default
> configuration
> is removed.
>
> Signed-off-by: Conor Dooley
> ---
> arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi| 71 +++
> arch/riscv/dts/mpfs-icicle-kit.dts| 190 +---
> arch/riscv/dts/mpfs.dtsi | 442 --
>
> .../dt-bindings/clock/microchip-mpfs-clock.h | 29 +-
> .../microchip-mpfs-plic.h | 196
> .../interrupt-controller/riscv-hart.h | 17 -
> 6 files changed, 420 insertions(+), 525 deletions(-)
> create mode 100644 arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
> delete mode 100644 include/dt-bindings/interrupt-
> controller/microchip-mpfs-plic.h
> delete mode 100644 include/dt-bindings/interrupt-controller/riscv-
> hart.h
>
Reviewed-by: Padmarao Begari
Tested-by: Padmarao Begari
> diff --git a/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
> b/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
> new file mode 100644
> index 00..1069134f2e
> --- /dev/null
> +++ b/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
> @@ -0,0 +1,71 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
> +
> +/ {
> + compatible = "microchip,mpfs-icicle-reference-rtlv2210",
> "microchip,mpfs-icicle-kit",
> + "microchip,mpfs";
> +
> + core_pwm0: pwm@4000 {
> + compatible = "microchip,corepwm-rtl-v4";
> + reg = <0x0 0x4000 0x0 0xF0>;
> + microchip,sync-update-mask = /bits/ 32 <0>;
> + #pwm-cells = <3>;
> + clocks = <_nw CLK_CCC_PLL0_OUT3>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c@4200 {
> + compatible = "microchip,corei2c-rtl-v7";
> + reg = <0x0 0x4200 0x0 0x100>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <_nw CLK_CCC_PLL0_OUT3>;
> + interrupt-parent = <>;
> + interrupts = <122>;
> + clock-frequency = <10>;
> + status = "disabled";
> + };
> +
> + pcie: pcie@30 {
> + compatible = "microchip,pcie-host-1.0";
> + #address-cells = <0x3>;
> + #interrupt-cells = <0x1>;
> + #size-cells = <0x2>;
> + device_type = "pci";
> + reg = <0x30 0x0 0x0 0x800>, <0x0 0x4300 0x0
> 0x1>;
> + reg-names = "cfg", "apb";
> + bus-range = <0x0 0x7f>;
> + interrupt-parent = <>;
> + interrupts = <119>;
> + interrupt-map = <0 0 0 1 _intc 0>,
> + <0 0 0 2 _intc 1>,
> + <0 0 0 3 _intc 2>,
> + <0 0 0 4 _intc 3>;
> + interrupt-map-mask = <0 0 0 7>;
> + clocks = <_nw CLK_CCC_PLL0_OUT1>, <_nw
> CLK_CCC_PLL0_OUT3>;
> + clock-names = "fic1", "fic3";
> + ranges = <0x300 0x0 0x800 0x30 0x800 0x0
> 0x8000>;
> + dma-ranges = <0x0200 0x0 0x 0x0 0x
> 0x1 0x>;
> + msi-parent = <>;
> + msi-controller;
> + status = "disabled";
> + pcie_intc: interrupt-controller {
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +
> + refclk_ccc: cccrefclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +};
> +
> +_nw {
> + clocks = <_ccc>, <_ccc>, <_ccc>,
> <_ccc>,
> + <_ccc>, <_ccc>;
> + clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0",
> "pll1_ref1",
> + "dll0_ref", "dll1_ref";
> + status = "okay";
> +};
> diff --git a/arch/riscv/dts/mpfs-icicle-kit.dts
> b/arch/riscv/dts/mpfs-icicle-kit.dts
> index 3c56400b92..8aa5fb17d6 100644
> --- a/arch/riscv/dts/mpfs-icicle-kit.dts
> +++ b/arch/riscv/dts/mpfs-icicle-kit.dts
> @@ -7,29 +7,63 @@
> /dts-v1/;
>
> #include "mpfs.dtsi"
> +#include "mpfs-icicle-kit-fabric.dtsi"
> +#include
> +#include
>
> /* Clock frequency (in Hz) of the rtcclk */
> #define RTCCLK_FREQ 100
>
> / {
> model = "Microchip PolarFire-SoC Icicle Kit";
> -
Re: [PATCH v1 1/3] riscv: dts: drop microchip from dts filenames
> On Wed, 2023-06-07 at 11:06 +0100, Conor Dooley wrote:
> The original names picked for the DT doesn't match Linux's naming
> scheme
> and it was renamed there a while ago. Rename it in U-Boot to allow
> easily syncing dts between the two projects.
>
> Signed-off-by: Conor Dooley
> ---
> arch/riscv/dts/Makefile | 2 +-
> ...s-icicle-kit-u-boot.dtsi => mpfs-icicle-kit-u-boot.dtsi} | 0
> .../{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 2 +-
> arch/riscv/dts/{microchip-mpfs.dtsi => mpfs.dtsi} | 0
> configs/microchip_mpfs_icicle_defconfig | 2 +-
> doc/board/microchip/mpfs_icicle.rst | 6 +++-
Reviewed-by: Padmarao Begari
> --
> 6 files changed, 6 insertions(+), 6 deletions(-)
> rename arch/riscv/dts/{microchip-mpfs-icicle-kit-u-boot.dtsi =>
> mpfs-icicle-kit-u-boot.dtsi} (100%)
> rename arch/riscv/dts/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-
> kit.dts} (98%)
> rename arch/riscv/dts/{microchip-mpfs.dtsi => mpfs.dtsi} (100%)
>
> diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> index 79a58694f5..1d61eb8020 100644
> --- a/arch/riscv/dts/Makefile
> +++ b/arch/riscv/dts/Makefile
> @@ -1,7 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0+
>
> dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb
> -dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-
> kit.dtb
> +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
> dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
> dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
> dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
> diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> b/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi
> similarity index 100%
> rename from arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> rename to arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi
> diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> b/arch/riscv/dts/mpfs-icicle-kit.dts
> similarity index 98%
> rename from arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> rename to arch/riscv/dts/mpfs-icicle-kit.dts
> index c3f58e2d56..3c56400b92 100644
> --- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> +++ b/arch/riscv/dts/mpfs-icicle-kit.dts
> @@ -6,7 +6,7 @@
>
> /dts-v1/;
>
> -#include "microchip-mpfs.dtsi"
> +#include "mpfs.dtsi"
>
> /* Clock frequency (in Hz) of the rtcclk */
> #define RTCCLK_FREQ 100
> diff --git a/arch/riscv/dts/microchip-mpfs.dtsi
> b/arch/riscv/dts/mpfs.dtsi
> similarity index 100%
> rename from arch/riscv/dts/microchip-mpfs.dtsi
> rename to arch/riscv/dts/mpfs.dtsi
> diff --git a/configs/microchip_mpfs_icicle_defconfig
> b/configs/microchip_mpfs_icicle_defconfig
> index c03c8ec6ec..fa49d3865f 100644
> --- a/configs/microchip_mpfs_icicle_defconfig
> +++ b/configs/microchip_mpfs_icicle_defconfig
> @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
> CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8020
> CONFIG_ENV_SIZE=0x2000
> -CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit"
> +CONFIG_DEFAULT_DEVICE_TREE="mpfs-icicle-kit"
> CONFIG_SYS_PROMPT="RISC-V # "
> CONFIG_SYS_MEM_TOP_HIDE=0x40
> CONFIG_SYS_LOAD_ADDR=0x8020
> diff --git a/doc/board/microchip/mpfs_icicle.rst
> b/doc/board/microchip/mpfs_icicle.rst
> index 09c2c6a9c1..1464e536e9 100644
> --- a/doc/board/microchip/mpfs_icicle.rst
> +++ b/doc/board/microchip/mpfs_icicle.rst
> @@ -134,7 +134,7 @@ Build OpenSBI
> .. code-block:: none
>
> make PLATFORM=generic FW_PAYLOAD_PATH=/u-
> boot.bin
> - FW_FDT_PATH=/arch/riscv/dts/microchip-mpfs-
> icicle-kit-.dtb
> + FW_FDT_PATH=/arch/riscv/dts/mpfs-icicle-kit-
> .dtb
>
> 3. Output "fw_payload.bin" file available at
> " directory>/build/platform/generic/firmware/fw_payload.bin"
> @@ -277,14 +277,14 @@ load uImage (with initramfs).
> done
> Bytes transferred = 14482480 (dcfc30 hex)
>
> - RISC-V # tftpboot ${fdt_addr_r} microchip-mpfs-icicle-kit.dtb
> + RISC-V # tftpboot ${fdt_addr_r} mpfs-icicle-kit.dtb
> ethernet@20112000: PHY present at 9
> ethernet@20112000: Starting autonegotiation...
> ethernet@20112000: Autonegotiation complete
> ethernet@20112000: link up, 1000Mbps full-duplex (lpa: 0x7800)
> Using ethernet@20112000 device
> TFTP from server 192.168.1.3; our IP address is 192.168.1.5
> - Filename 'microchip-mpfs-icicle-kit.dtb'.
> + Filename 'mpfs-icicle-kit.dtb'.
> Load address: 0x8220
> Loading: #
> 2.5 MiB/s
Re: [PATCH 1/1] doc: board: typo GIUD Microchip MPFS Icicle Kit doc
> On Wed, 2022-11-30 at 18:03 +0100, Heinrich Schuchardt wrote:
> %s/GIUD/GUID/
>
> Fixes: 9e550e18305f ("doc: board: Add Microchip MPFS Icicle Kit doc")
> Signed-off-by: Heinrich Schuchardt >
> ---
> doc/board/microchip/mpfs_icicle.rst | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Reviewed-by: Padmarao Begari
> diff --git a/doc/board/microchip/mpfs_icicle.rst
> b/doc/board/microchip/mpfs_icicle.rst
> index a4b10c6bd7..09c2c6a9c1 100644
> --- a/doc/board/microchip/mpfs_icicle.rst
> +++ b/doc/board/microchip/mpfs_icicle.rst
> @@ -209,7 +209,7 @@ GUID type
> ~
>
> The HSS always picks up HSS payload from a GPT partition with
> -GIUD type "21686148-6449-6E6F-744E-656564454649" or sector '0' of
> the eMMC if no
> +GUID type "21686148-6449-6E6F-744E-656564454649" or sector '0' of
> the eMMC if no
> GPT partition.
>
> Booting
> @@ -460,7 +460,7 @@ GUID type
> ~
>
> The HSS always picks up the HSS payload from a GPT partition with
> -GIUD type "21686148-6449-6E6F-744E-656564454649" or sector '0' of
> the eMMC if no
> +GUID type "21686148-6449-6E6F-744E-656564454649" or sector '0' of
> the eMMC if no
> GPT partition.
>
> Sample boot log from MPFS Icicle Kit
> --
> 2.37.2
>
Re: [PATCH v2] riscv: Fix detecting FPU support in standard extension
> On Sat, 2022-11-05 at 14:02 +0800, Yu Chien Peter Lin wrote:
>
> We should check the string until it hits underscore, in case it
> searches for the letters in the custom extension. For example,
> "rv64imac_xandes" will be treated as D extension support since
> there is a "d" in "andes", resulting illegal instruction caused
> by initializing FCSR.
>
> Signed-off-by: Yu Chien Peter Lin
> ---
> arch/riscv/cpu/cpu.c | 14 +++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> index 52ab02519f..d34c8efce0 100644
> --- a/arch/riscv/cpu/cpu.c
> +++ b/arch/riscv/cpu/cpu.c
> @@ -36,6 +36,7 @@ static inline bool supports_extension(char ext)
> #ifdef CONFIG_CPU
> struct udevice *dev;
> char desc[32];
> + int i;
>
> uclass_find_first_device(UCLASS_CPU, );
> if (!dev) {
> @@ -43,9 +44,16 @@ static inline bool supports_extension(char ext)
> return false;
> }
> if (!cpu_get_desc(dev, desc, sizeof(desc))) {
> - /* skip the first 4 characters (rv32|rv64) */
> - if (strchr(desc + 4, ext))
> - return true;
> + /*
> +* skip the first 4 characters (rv32|rv64) and
> +* check until underscore
> +*/
> + for (i = 4; i < sizeof(desc); i++) {
> + if (desc[i] == '_' || desc[i] == '\0')
> + break;
> + if (desc[i] == ext)
> + return true;
> + }
>
Reviewed-by: Padmarao Begari
> }
>
> return false;
> --
> 2.34.1
>
Re: [PATCH 1/1] riscv: enable reset via SBI on PolarFire Icicle Kit
> On Mon, 2022-11-07 at 10:55 +0100, Heinrich Schuchardt wrote: > > HSS 2022.10 provides support for resetting the board. > > Signed-off-by: Heinrich Schuchardt > > --- > configs/microchip_mpfs_icicle_defconfig | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/configs/microchip_mpfs_icicle_defconfig > b/configs/microchip_mpfs_icicle_defconfig > index c295b9bad3..65bd50db80 100644 > --- a/configs/microchip_mpfs_icicle_defconfig > +++ b/configs/microchip_mpfs_icicle_defconfig > @@ -21,3 +21,5 @@ CONFIG_SYS_MEM_TOP_HIDE=0x40 > CONFIG_SYS_RELOC_GD_ENV_ADDR=y > CONFIG_BOOTP_SEND_HOSTNAME=y > CONFIG_DM_MTD=y > +CONFIG_SYSRESET=y > +CONFIG_SYSRESET_SBI=y Reviewed-by: Padmarao Begari Tested-by: Padmarao Begari > -- > 2.37.2 >
Re: [PATCH v1 6/6] riscv: dts: fix the mpfs's reference clock frequency
> On Tue, 2022-10-25 at 08:58 +0100, Conor Dooley wrote:
> The initial devicetree for PolarFire SoC incorrectly created a fixed
> frequency clock in the devicetree to represent the msspll, but the
> msspll is not a fixed frequency clock. The actual reference clock on
> a
> board is either 125 or 100 MHz, 125 MHz in the case of the icicle
> kit.
> Swap the incorrect representation of the msspll out for the actual
> reference clock.
>
> Fixes: dd4ee416a6 ("riscv: dts: Add device tree for Microchip Icicle
> Kit")
> Signed-off-by: Conor Dooley
> ---
> arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 4
> arch/riscv/dts/microchip-mpfs.dtsi | 14 ++
> 2 files changed, 10 insertions(+), 8 deletions(-)
>
> diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> index e1fbedc507..7d87b181db 100644
> --- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> @@ -53,6 +53,10 @@
> };
> };
>
> + {
> + clock-frequency = <12500>;
> +};
> +
> {
> status = "okay";
> };
> diff --git a/arch/riscv/dts/microchip-mpfs.dtsi
> b/arch/riscv/dts/microchip-mpfs.dtsi
> index 4f449a3a93..891dd0918b 100644
> --- a/arch/riscv/dts/microchip-mpfs.dtsi
> +++ b/arch/riscv/dts/microchip-mpfs.dtsi
> @@ -170,6 +170,11 @@
> };
> };
>
> + refclk: refclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> soc {
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -225,16 +230,9 @@
> _intc HART_INT_M_EXT
> _intc HART_INT_S_EXT>;
> };
>
> - refclk: refclk {
> - compatible = "fixed-clock";
> - #clock-cells = <0>;
> - clock-frequency = <6>;
> - clock-output-names = "msspllclk";
> - };
> -
> clkcfg: clkcfg@20002000 {
> compatible = "microchip,mpfs-clkcfg";
> - reg = <0x0 0x20002000 0x0 0x1000>;
> + reg = <0x0 0x20002000 0x0 0x1000>, <0x0
> 0x3E001000 0x0 0x1000>;
> reg-names = "mss_sysreg";
> clocks = <>;
> #clock-cells = <1>;
Reviewed-by: Padmarao Begari
Re: [PATCH v1 5/6] clk: microchip: mpfs: fix criticality of peripheral clocks
> On Tue, 2022-10-25 at 08:58 +0100, Conor Dooley wrote:
> Sync the critical clocks in the U-Boot driver with those marked as
> critical in Linux. The Linux driver has an explanation of why each
> clock
> is considered to be critical, so import that too.
>
> Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
> Signed-off-by: Conor Dooley
> ---
> drivers/clk/microchip/mpfs_clk_periph.c | 28 ++-
> --
> 1 file changed, 21 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/microchip/mpfs_clk_periph.c
> b/drivers/clk/microchip/mpfs_clk_periph.c
> index e23eb552c3..ddeccb9145 100644
> --- a/drivers/clk/microchip/mpfs_clk_periph.c
> +++ b/drivers/clk/microchip/mpfs_clk_periph.c
> @@ -114,13 +114,27 @@ static ulong mpfs_periph_clk_recalc_rate(struct
> clk *hw)
> .periph.flags = _flags, \
> }
>
> +/*
> + * Critical clocks:
> + * - CLK_ENVM: reserved by hart software services (hss) superloop
> monitor/m mode interrupt
> + * trap handler
> + * - CLK_MMUART0: reserved by the hss
> + * - CLK_DDRC: provides clock to the ddr subsystem
> + * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running
> as the rtc will stop
> + * if the AHB interface clock is disabled
> + * - CLK_FICx: these provide the processor side clocks to the "FIC"
> (Fabric InterConnect)
> + * clock domain crossers which provide the interface to the FPGA
> fabric. Disabling them
> + * causes the FPGA fabric to go into reset.
> + * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the
> Athena TeraFire.
> + */
> +
> static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
> CLK_PERIPH(CLK_ENVM, "clk_periph_envm", CLK_AHB, 0,
> CLK_IS_CRITICAL),
> CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", CLK_AHB, 1, 0),
> CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", CLK_AHB, 2, 0),
> CLK_PERIPH(CLK_MMC, "clk_periph_mmc", CLK_AHB, 3, 0),
> CLK_PERIPH(CLK_TIMER, "clk_periph_timer", CLK_RTCREF, 4, 0),
> - CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", CLK_AHB, 5, 0),
> + CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", CLK_AHB, 5,
> CLK_IS_CRITICAL),
> CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", CLK_AHB, 6, 0),
> CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", CLK_AHB, 7, 0),
> CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", CLK_AHB, 8, 0),
> @@ -132,17 +146,17 @@ static struct mpfs_periph_hw_clock
> mpfs_periph_clks[] = {
> CLK_PERIPH(CLK_CAN0, "clk_periph_can0", CLK_AHB, 14, 0),
> CLK_PERIPH(CLK_CAN1, "clk_periph_can1", CLK_AHB, 15, 0),
> CLK_PERIPH(CLK_USB, "clk_periph_usb", CLK_AHB, 16, 0),
> - CLK_PERIPH(CLK_RTC, "clk_periph_rtc", CLK_AHB, 18, 0),
> + CLK_PERIPH(CLK_RTC, "clk_periph_rtc", CLK_AHB, 18,
> CLK_IS_CRITICAL),
> CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", CLK_AHB, 19, 0),
> CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", CLK_AHB, 20, 0),
> CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", CLK_AHB, 21, 0),
> CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", CLK_AHB, 22, 0),
> CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", CLK_AHB, 23,
> CLK_IS_CRITICAL),
> - CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", CLK_AXI, 24, 0),
> - CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", CLK_AXI, 25, 0),
> - CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", CLK_AXI, 26, 0),
> - CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", CLK_AXI, 27, 0),
> - CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", CLK_AXI, 28, 0),
> + CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", CLK_AXI, 24,
> CLK_IS_CRITICAL),
> + CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", CLK_AXI, 25,
> CLK_IS_CRITICAL),
> + CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", CLK_AXI, 26,
> CLK_IS_CRITICAL),
> + CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", CLK_AXI, 27,
> CLK_IS_CRITICAL),
> + CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", CLK_AXI, 28,
> CLK_IS_CRITICAL),
> CLK_PERIPH(CLK_CFM, "clk_periph_cfm", CLK_AHB, 29, 0),
> };
>
Reviewed-by: Padmarao Begari
Re: [PATCH v1 4/6] clk: microchip: mpfs: fix periph clk parentage
> On Tue, 2022-10-25 at 08:58 +0100, Conor Dooley wrote:
> Not all "periph" clocks are children of the AHB clock, some have the
> AXI
> clock as their parent & the mtimer clock is derived from the external
> reference clock directly. Stop assuming the AHB clock to be the
> parent
> of all "periph" clocks and define their correct parents instead.
>
> Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
> Signed-off-by: Conor Dooley
> ---
> drivers/clk/microchip/mpfs_clk.c| 4 +-
> drivers/clk/microchip/mpfs_clk.h| 4 +-
> drivers/clk/microchip/mpfs_clk_periph.c | 72 +
>
> 3 files changed, 42 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/clk/microchip/mpfs_clk.c
> b/drivers/clk/microchip/mpfs_clk.c
> index f16f716f00..08f8bfcecb 100644
> --- a/drivers/clk/microchip/mpfs_clk.c
> +++ b/drivers/clk/microchip/mpfs_clk.c
> @@ -19,7 +19,6 @@
> static int mpfs_clk_probe(struct udevice *dev)
> {
> struct clk *parent_clk = dev_get_priv(dev);
> - struct clk clk_ahb = { .id = CLK_AHB };
> struct clk clk_msspll = { .id = CLK_MSSPLL };
> void __iomem *base;
> void __iomem *msspll_base;
> @@ -56,8 +55,7 @@ static int mpfs_clk_probe(struct udevice *dev)
> if (ret)
> return ret;
>
> - clk_request(dev, _ahb);
> - ret = mpfs_clk_register_periphs(base, _ahb);
> + ret = mpfs_clk_register_periphs(base, dev);
>
> return ret;
> }
> diff --git a/drivers/clk/microchip/mpfs_clk.h
> b/drivers/clk/microchip/mpfs_clk.h
> index cb7d303e67..72288cc971 100644
> --- a/drivers/clk/microchip/mpfs_clk.h
> +++ b/drivers/clk/microchip/mpfs_clk.h
> @@ -27,10 +27,10 @@ int mpfs_clk_register_msspll(void __iomem *base,
> struct clk *parent);
> * mpfs_clk_register_periphs() - register peripheral clocks
> *
> * @base: base address of the mpfs system register.
> - * @parent: a pointer to parent clock.
> + * @dev: udevice representing the clock controller.
> * Return: zero on success, or a negative error code.
> */
> -int mpfs_clk_register_periphs(void __iomem *base, struct clk
> *parent);
> +int mpfs_clk_register_periphs(void __iomem *base, struct udevice
> *dev);
> /**
> * divider_get_val() - get the clock divider value
> *
> diff --git a/drivers/clk/microchip/mpfs_clk_periph.c
> b/drivers/clk/microchip/mpfs_clk_periph.c
> index 1488ef503e..e23eb552c3 100644
> --- a/drivers/clk/microchip/mpfs_clk_periph.c
> +++ b/drivers/clk/microchip/mpfs_clk_periph.c
> @@ -29,12 +29,14 @@
> /**
> * struct mpfs_periph_clock - per instance of peripheral clock
> * @id: index of a peripheral clock
> + * @parent_id: index of the parent clock
> * @name: name of a peripheral clock
> * @shift: shift to a peripheral clock bit field
> * @flags: common clock framework flags
> */
> struct mpfs_periph_clock {
> unsigned int id;
> + unsigned int parent_id;
> const char *name;
> u8 shift;
> unsigned long flags;
> @@ -104,46 +106,47 @@ static ulong mpfs_periph_clk_recalc_rate(struct
> clk *hw)
>
> }
>
> -#define CLK_PERIPH(_id, _name, _shift, _flags) { \
> +#define CLK_PERIPH(_id, _name, _parent_id, _shift, _flags) { \
> .periph.id = _id, \
> + .periph.parent_id = _parent_id, \
> .periph.name = _name, \
> .periph.shift = _shift, \
> .periph.flags = _flags, \
> }
>
> static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
> - CLK_PERIPH(CLK_ENVM, "clk_periph_envm", 0, CLK_IS_CRITICAL),
> - CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", 1, 0),
> - CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", 2, 0),
> - CLK_PERIPH(CLK_MMC, "clk_periph_mmc", 3, 0),
> - CLK_PERIPH(CLK_TIMER, "clk_periph_timer", 4, 0),
> - CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", 5, 0),
> - CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", 6, 0),
> - CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", 7, 0),
> - CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", 8, 0),
> - CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", 9, 0),
> - CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", 10, 0),
> - CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", 11, 0),
> - CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", 12, 0),
> - CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", 13, 0),
> - CLK_PERIPH(CLK_CAN0, "clk_periph_can0", 14, 0),
> - CLK_PERIPH(CLK_CAN1, "clk_periph_can1", 15, 0),
> - CLK_PERIPH(CLK_USB, "clk_periph_usb", 16, 0),
> - CLK_PERIPH(CLK_RTC, "clk_periph_rtc", 18, 0),
> - CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", 19, 0),
> - CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", 20, 0),
> - CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", 21, 0),
> - CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", 22, 0),
> - CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", 23, CLK_IS_CRITICAL),
> - CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", 24, 0),
> - CLK_PERIPH(CLK_FIC1,
Re: [PATCH v1 3/6] clk: microchip: mpfs: fix reference clock handling
> On Tue, 2022-10-25 at 08:58 +0100, Conor Dooley wrote:
> The original devicetrees for PolarFire SoC messed up & defined the
> msspll's output as a fixed-frequency, 600 MHz clock & used that as
> the
> input for the clock controller node. The msspll is not a fixed
> frequency clock and later devicetrees handled this properly. Check
> the
> devicetree & if it is one of the fixed ones, register the msspll.
> Otherwise, skip registering it & pass the reference clock directly to
> the cfg clock registration function so that existing devicetrees are
> not broken by this change.
>
> As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver
> for
> it, based on the one in Linux.
>
> Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
> Signed-off-by: Conor Dooley
> ---
> drivers/clk/microchip/mpfs_clk.c| 23 -
> drivers/clk/microchip/mpfs_clk.h| 8 ++
> drivers/clk/microchip/mpfs_clk_msspll.c | 119
>
> 3 files changed, 149 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/microchip/mpfs_clk_msspll.c
>
> diff --git a/drivers/clk/microchip/mpfs_clk.c
> b/drivers/clk/microchip/mpfs_clk.c
> index 7ba1218b56..f16f716f00 100644
> --- a/drivers/clk/microchip/mpfs_clk.c
> +++ b/drivers/clk/microchip/mpfs_clk.c
> @@ -20,10 +20,12 @@ static int mpfs_clk_probe(struct udevice *dev)
> {
> struct clk *parent_clk = dev_get_priv(dev);
> struct clk clk_ahb = { .id = CLK_AHB };
> + struct clk clk_msspll = { .id = CLK_MSSPLL };
> void __iomem *base;
> + void __iomem *msspll_base;
> int ret;
>
> - base = dev_read_addr_ptr(dev);
> + base = dev_read_addr_index_ptr(dev, 0);
> if (!base)
> return -EINVAL;
>
> @@ -31,6 +33,25 @@ static int mpfs_clk_probe(struct udevice *dev)
> if (ret)
> return ret;
>
> + /*
> + * The original devicetrees for mpfs messed up & defined the
> msspll's
> + * output as a fixed-frequency, 600 MHz clock & used that as
> the input
> + * for the clock controller node. The msspll is however not a
> fixed
> + * frequency clock and later devicetrees handled this properly.
> Check
> + * the devicetree & if it is one of the fixed ones, register
> the msspll.
> + * Otherwise, skip registering it & pass the reference clock
> directly
> + * to the cfg clock registration function.
> + */
> + msspll_base = dev_read_addr_index_ptr(dev, 1);
> + if (msspll_base) {
> + ret = mpfs_clk_register_msspll(msspll_base,
> parent_clk);
> + if (ret)
> + return ret;
> +
> + clk_request(dev, _msspll);
> + parent_clk = _msspll;
> + }
> +
> ret = mpfs_clk_register_cfgs(base, parent_clk);
> if (ret)
> return ret;
> diff --git a/drivers/clk/microchip/mpfs_clk.h
> b/drivers/clk/microchip/mpfs_clk.h
> index 35cfeac92e..cb7d303e67 100644
> --- a/drivers/clk/microchip/mpfs_clk.h
> +++ b/drivers/clk/microchip/mpfs_clk.h
> @@ -15,6 +15,14 @@
> * Return: zero on success, or a negative error code.
> */
> int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent);
> +/**
> + * mpfs_clk_register_msspll() - register the mss pll
> + *
> + * @base: base address of the mpfs system register.
> + * @parent: a pointer to parent clock.
> + * Return: zero on success, or a negative error code.
> + */
> +int mpfs_clk_register_msspll(void __iomem *base, struct clk
> *parent);
> /**
> * mpfs_clk_register_periphs() - register peripheral clocks
> *
> diff --git a/drivers/clk/microchip/mpfs_clk_msspll.c
> b/drivers/clk/microchip/mpfs_clk_msspll.c
> new file mode 100644
> index 00..f37c0d8604
> --- /dev/null
> +++ b/drivers/clk/microchip/mpfs_clk_msspll.c
> @@ -0,0 +1,119 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2022 Microchip Technology Inc.
> + */
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "mpfs_clk.h"
> +
> +#define MPFS_MSSPLL_CLOCK "mpfs_msspll_clock"
> +
> +/* address offset of control registers */
> +#define REG_MSSPLL_REF_CR0x08u
> +#define REG_MSSPLL_POSTDIV_CR0x10u
> +#define REG_MSSPLL_SSCG_2_CR 0x2Cu
> +
> +#define MSSPLL_FBDIV_SHIFT 0x00u
> +#define MSSPLL_FBDIV_WIDTH 0x0Cu
> +#define MSSPLL_REFDIV_SHIFT 0x08u
> +#define MSSPLL_REFDIV_WIDTH 0x06u
> +#define MSSPLL_POSTDIV_SHIFT 0x08u
> +#define MSSPLL_POSTDIV_WIDTH 0x07u
> +#define MSSPLL_FIXED_DIV 4u
> +
> +/**
> + * struct mpfs_msspll_hw_clock
> + * @id: index of the msspll clock
> + * @name: the msspll clocks name
> + * @reg_offset: offset to the core complex's output of the msspll
> + * @shift: shift to the divider bit field of a msspll clock output
> + * @width: width of the divider bit field of the msspll clock output
> + * @flags: common clock framework flags
> + * @prate: the reference clock rate
> + * @hw:
Re: [PATCH v1 2/6] clk: microchip: mpfs: convert parent rate acquistion to get_get_rate()
Hi Conor,
> On Tue, 2022-10-25 at 08:58 +0100, Conor Dooley wrote:
> Currently the clock driver for PolarFire SoC takes a very naive
> approach
> to the relationship between clocks. It reads the dt to get an input
> clock, assumes that that is fixed frequency, reads the "clock-
s/that that/that
> frequency"
> property & uses that to set up both the "cfg" and "periph" clocks.
>
> Simplifying for the sake of incremental fixes, the "correct"
> parentage for
> the clocks currently supported in U-Boot is that the "cfg" clocks
> should
> be children of the fixed frequency clock in the dt. The AHB clock is
> one
> of these "cfg" clocks and is the parent of the "periph" clocks.
>
> Instead of passing the clock rate of the fixed-frequency clock to the
> "cfg" and "periph" registration functions and the name of the
> parents,
> pass their actual parents & use clk_get_rate() to determine their
> parents
> rates.
>
> The "periph" clocks are purely gate clocks and should not be reading
> the
> AHB clocks registers to determine their rates, as they can simply
> report
> the output of clk_get_rate() on their parent.
>
> Signed-off-by: Conor Dooley
> ---
> drivers/clk/microchip/Makefile | 2 +-
> drivers/clk/microchip/mpfs_clk.c| 18 --
> drivers/clk/microchip/mpfs_clk.h| 12
> drivers/clk/microchip/mpfs_clk_cfg.c| 7 +++
> drivers/clk/microchip/mpfs_clk_periph.c | 16
> 5 files changed, 20 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/clk/microchip/Makefile
> b/drivers/clk/microchip/Makefile
> index 904b345d75..329b2c0c93 100644
> --- a/drivers/clk/microchip/Makefile
> +++ b/drivers/clk/microchip/Makefile
> @@ -1 +1 @@
> -obj-y += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o
> +obj-y += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o
> mpfs_clk_msspll.o
> diff --git a/drivers/clk/microchip/mpfs_clk.c
> b/drivers/clk/microchip/mpfs_clk.c
> index 67828c9bf4..7ba1218b56 100644
> --- a/drivers/clk/microchip/mpfs_clk.c
> +++ b/drivers/clk/microchip/mpfs_clk.c
> @@ -11,34 +11,32 @@
> #include
> #include
> #include
> +#include
> #include
>
> #include "mpfs_clk.h"
>
> static int mpfs_clk_probe(struct udevice *dev)
> {
> - int ret;
> + struct clk *parent_clk = dev_get_priv(dev);
> + struct clk clk_ahb = { .id = CLK_AHB };
The peripheral clock updated code added in this patch but removed it in
the patch 4, you can update only related code in this patch instead of
removing it later.
Other than that:
Reviewed-by: Padmarao Begari
> void __iomem *base;
> - u32 clk_rate;
> - const char *parent_clk_name;
> - struct clk *clk = dev_get_priv(dev);
> + int ret;
>
> base = dev_read_addr_ptr(dev);
> if (!base)
> return -EINVAL;
>
> - ret = clk_get_by_index(dev, 0, clk);
> + ret = clk_get_by_index(dev, 0, parent_clk);
> if (ret)
> return ret;
>
> - dev_read_u32(clk->dev, "clock-frequency", _rate);
> - parent_clk_name = clk->dev->name;
> -
> - ret = mpfs_clk_register_cfgs(base, clk_rate, parent_clk_name);
> + ret = mpfs_clk_register_cfgs(base, parent_clk);
> if (ret)
> return ret;
>
> - ret = mpfs_clk_register_periphs(base, clk_rate, "clk_ahb");
> + clk_request(dev, _ahb);
> + ret = mpfs_clk_register_periphs(base, _ahb);
>
> return ret;
> }
> diff --git a/drivers/clk/microchip/mpfs_clk.h
> b/drivers/clk/microchip/mpfs_clk.h
> index 442562a5e7..35cfeac92e 100644
> --- a/drivers/clk/microchip/mpfs_clk.h
> +++ b/drivers/clk/microchip/mpfs_clk.h
> @@ -11,22 +11,18 @@
> * mpfs_clk_register_cfgs() - register configuration clocks
> *
> * @base: base address of the mpfs system register.
> - * @clk_rate: the mpfs pll clock rate.
> - * @parent_name: a pointer to parent clock name.
> + * @parent: a pointer to parent clock.
> * Return: zero on success, or a negative error code.
> */
> -int mpfs_clk_register_cfgs(void __iomem *base, u32 clk_rate,
> -const char *parent_name);
> +int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent);
> /**
> * mpfs_clk_register_periphs() - register peripheral clocks
> *
> * @base: base address of the mpfs system register.
> - * @clk_rate: the mpfs pll clock rate.
> - * @parent_name: a pointer to parent clock name.
> + * @parent: a pointer to parent clock.
> * Return: zero on success, or a negative error code.
> */
> -int mpfs_clk_register_periphs(void __iomem *base, u32 clk_rate,
> - const char *parent_name);
> +int mpfs_clk_register_periphs(void __iomem *base, struct clk
> *parent);
> /**
> * divider_get_val() - get the clock divider value
> *
> diff --git a/drivers/clk/microchip/mpfs_clk_cfg.c
> b/drivers/clk/microchip/mpfs_clk_cfg.c
> index fefddd1413..5739fd66e8 100644
> --- a/drivers/clk/microchip/mpfs_clk_cfg.c
> +++ b/drivers/clk/microchip/mpfs_clk_cfg.c
> @@ -117,8
Re: [PATCH v1 1/6] dt-bindings: clk: add missing clk ids for microchip mpfs
> On Tue, 2022-10-25 at 08:58 +0100, Conor Dooley wrote: > When this binding header was initally upstreamed, the PLL clocking > the > microprocessor subsystem (MSS) and the RTC reference clocks were > omitted. Add them now, matching the IDs used in Linux. > > Signed-off-by: Conor Dooley > --- > include/dt-bindings/clock/microchip-mpfs-clock.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/include/dt-bindings/clock/microchip-mpfs-clock.h > b/include/dt-bindings/clock/microchip-mpfs-clock.h > index 55fe64693f..c7ed0a8db7 100644 > --- a/include/dt-bindings/clock/microchip-mpfs-clock.h > +++ b/include/dt-bindings/clock/microchip-mpfs-clock.h > @@ -42,4 +42,7 @@ > #define CLK_ATHENA 31 > #define CLK_CFM 32 > > +#define CLK_RTCREF 33 > +#define CLK_MSSPLL 34 > + > #endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */ Reviewed-by: Padmarao Begari
Re: [PATCH v1 2/2] i2c: microchip: fix erroneous late ack send
Hi Conor,
> On Wed, 2022-10-26 at 07:54 +, Conor Dooley - M52691 wrote:
> On 26/10/2022 08:49, Conor Dooley wrote:
> > A late ack is currently being sent at the end of a transfer due to
> > incorrect logic in mchp_corei2c_empty_rx(). Currently the Assert
> > Ack
> > bit is being written to the controller's control reg after the last
> > byte has been received, causing it to sent another byte with the
> > ack.
> > Instead, the AA flag should be written to the control register when
> > the penultimate byte is read so it is sent out for the last byte.
> >
> > Reported-by: Andreas Buerkler
> > Fixes: 0dc0d1e094 ("i2c: Add Microchip PolarFire SoC I2C driver")
> > Fixes: 0190d48488 ("i2c: microchip: fix ack sending logic")
>
> I had removed this fixes tag but I must have aborted the rebase
> in which I did. If nothing else needs changing, please drop it,
> otherwise I'll remove it if/when I send a v2.
>
Yes you can remove it because the patch check is showing warning for
this fixes tag
Regards
Padmarao
> Thanks,
> Conor.
>
> > Signed-off-by: Conor Dooley
> > ---
> > drivers/i2c/i2c-microchip.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/i2c/i2c-microchip.c b/drivers/i2c/i2c-
> > microchip.c
> > index 3a27459386..d82b80f535 100644
> > --- a/drivers/i2c/i2c-microchip.c
> > +++ b/drivers/i2c/i2c-microchip.c
> > @@ -224,7 +224,7 @@ static void mpfs_i2c_empty_rx(struct
> > mpfs_i2c_bus *bus)
> > bus->msg_len--;
> > }
> >
> > - if (bus->msg_len == 0) {
> > + if (bus->msg_len <= 1) {
> > ctrl = readl(bus->base + MPFS_I2C_CTRL);
> > ctrl &= ~CTRL_AA;
> > writel(ctrl, bus->base + MPFS_I2C_CTRL);
Re: [PATCH v1 1/2] i2c: microchip: fix ack sending logic
> On Wed, 2022-10-26 at 08:49 +0100, Conor Dooley wrote:
> "Master receive mode" was not correctly sending ACKs/NACKs in the
> interrupt handler. Bring the handling of M_SLAR_ACK, M_RX_DATA_ACKED
> &
> M_RX_DATA_NACKED in line with the Linux driver.
>
> Fixes: 0dc0d1e094 ("i2c: Add Microchip PolarFire SoC I2C driver")
> Reported-by: Shravan Chippa
> Signed-off-by: Conor Dooley
> ---
> drivers/i2c/i2c-microchip.c | 23 +--
> 1 file changed, 17 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/i2c/i2c-microchip.c b/drivers/i2c/i2c-
> microchip.c
> index 12f65d0af7..3a27459386 100644
> --- a/drivers/i2c/i2c-microchip.c
> +++ b/drivers/i2c/i2c-microchip.c
> @@ -2,8 +2,9 @@
> /*
> * Microchip I2C controller driver
> *
> - * Copyright (C) 2021 Microchip Technology Inc.
> + * Copyright (C) 2021-2022 Microchip Technology Inc.
> * Padmarao Begari
> + * Conor Dooley
> */
> #include
> #include
> @@ -265,16 +266,27 @@ static int mpfs_i2c_service_handler(struct
> mpfs_i2c_bus *bus)
> }
> break;
> case STATUS_M_SLAR_ACK:
> - ctrl = readl(bus->base + MPFS_I2C_CTRL);
> - ctrl |= CTRL_AA;
> - writel(ctrl, bus->base + MPFS_I2C_CTRL);
> - if (bus->msg_len == 0) {
> + if (bus->msg_len > 1u) {
> + ctrl = readl(bus->base + MPFS_I2C_CTRL);
> + ctrl |= CTRL_AA;
> + writel(ctrl, bus->base + MPFS_I2C_CTRL);
> + } else if (bus->msg_len == 1u) {
> + ctrl = readl(bus->base + MPFS_I2C_CTRL);
> + ctrl &= ~CTRL_AA;
> + writel(ctrl, bus->base + MPFS_I2C_CTRL);
> + } else {
> + ctrl = readl(bus->base + MPFS_I2C_CTRL);
> + ctrl |= CTRL_AA;
> + writel(ctrl, bus->base + MPFS_I2C_CTRL);
> /* On the last byte to be transmitted, send
> STOP */
> mpfs_i2c_stop(bus);
> finish = true;
> }
> break;
> case STATUS_M_RX_DATA_ACKED:
> + mpfs_i2c_empty_rx(bus);
> + break;
> + case STATUS_M_RX_DATA_NACKED:
> mpfs_i2c_empty_rx(bus);
> if (bus->msg_len == 0) {
> /* On the last byte to be transmitted, send
> STOP */
> @@ -283,7 +295,6 @@ static int mpfs_i2c_service_handler(struct
> mpfs_i2c_bus *bus)
> }
> break;
> case STATUS_M_TX_DATA_NACK:
> - case STATUS_M_RX_DATA_NACKED:
> case STATUS_M_SLAR_NACK:
> case STATUS_M_SLAW_NACK:
> bus->msg_err = -ENXIO;
Reviewed-by: Padmarao Begari
Re: [PATCH v1 2/2] i2c: microchip: fix erroneous late ack send
> On Wed, 2022-10-26 at 08:49 +0100, Conor Dooley wrote:
> A late ack is currently being sent at the end of a transfer due to
> incorrect logic in mchp_corei2c_empty_rx(). Currently the Assert Ack
> bit is being written to the controller's control reg after the last
> byte has been received, causing it to sent another byte with the ack.
> Instead, the AA flag should be written to the control register when
> the penultimate byte is read so it is sent out for the last byte.
>
> Reported-by: Andreas Buerkler
> Fixes: 0dc0d1e094 ("i2c: Add Microchip PolarFire SoC I2C driver")
> Fixes: 0190d48488 ("i2c: microchip: fix ack sending logic")
> Signed-off-by: Conor Dooley
> ---
> drivers/i2c/i2c-microchip.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/i2c/i2c-microchip.c b/drivers/i2c/i2c-
> microchip.c
> index 3a27459386..d82b80f535 100644
> --- a/drivers/i2c/i2c-microchip.c
> +++ b/drivers/i2c/i2c-microchip.c
> @@ -224,7 +224,7 @@ static void mpfs_i2c_empty_rx(struct mpfs_i2c_bus
> *bus)
> bus->msg_len--;
> }
>
> - if (bus->msg_len == 0) {
> + if (bus->msg_len <= 1) {
> ctrl = readl(bus->base + MPFS_I2C_CTRL);
> ctrl &= ~CTRL_AA;
> writel(ctrl, bus->base + MPFS_I2C_CTRL);
Reviewed-by: Padmarao Begari
Re: [PATCH v2 3/4] spi: Add Microchip PolarFire SoC QSPI driver
On Sat, 2022-10-22 at 12:46 +0100, Conor Dooley wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > On Fri, Oct 21, 2022 at 12:29:21PM +0530, Padmarao Begari wrote: > > Add QSPI driver code for the Microchip PolarFire SoC. > > This driver supports the QSPI standard, dual and quad > > mode interfaces. > > > > Co-developed-by: Naga Sureshkumar Relli < > > nagasuresh.re...@microchip.com> > > Signed-off-by: Naga Sureshkumar Relli < > > nagasuresh.re...@microchip.com> > > Signed-off-by: Padmarao Begari > > --- > > drivers/spi/Kconfig | 6 + > > drivers/spi/Makefile | 1 + > > drivers/spi/microchip_coreqspi.c | 505 > > +++ > > 3 files changed, 512 insertions(+) > > create mode 100644 drivers/spi/microchip_coreqspi.c > > > > +/* QSPI ready time out value */ > > +#define TIMEOUT_MS (1000 * 60) > > Hey Padmarao, just zipping through and cross referencing against the > linux driver.. Why's this a 60 * 1000 when linux times out after 500 > ms? Ok, will update as per Linux time out(500ms) Regards Padmarao > Other than that, things look identical modulo the required interrupt > and > clocking changes for U-Boot. > Reviewed-by: Conor Dooley > > Thanks, > Conor. >
Re: [PATCH v2 1/4] riscv: dts: Update memory configuration
Hi Conor,
> On Tue, 2022-10-25 at 19:50 +, Conor Dooley - M52691 wrote:
> On 22/10/2022 12:21, Conor Dooley wrote:
> >
> > On Fri, Oct 21, 2022 at 12:29:19PM +0530, Padmarao Begari wrote:
> > > In the v2022.10 Icicle reference design, the seg registers are
> > > going to be
> >
> > Hey Padmarao,
> > Since the release was done the other day I think that this should
> > be
> > s/are going to be/have been
> >
> > > changed, resulting in a required change to the memory map.
> > > A small 4MB reservation is made at the end of 32-bit DDR to
> > > provide some
> > > memory for the HSS to use, so that it can cache its payload
> > > between
> > > reboots of a specific context.
> > >
> > > Co-developed-by: Conor Dooley
> > > Signed-off-by: Conor Dooley
> > > Signed-off-by: Padmarao Begari
> > > Reviewed-by: Conor Dooley
> > > ---
> > > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 70
> > >
> > > 1 file changed, 14 insertions(+), 56 deletions(-)
> > >
> > > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > > b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > > index 287ef3d23b..876c475069 100644
> > > --- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > > @@ -1,6 +1,6 @@
> > > // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > /*
> > > - * Copyright (C) 2021 Microchip Technology Inc.
> > > + * Copyright (C) 2021-2022 Microchip Technology Inc.
> > > * Padmarao Begari
> > > */
> > >
> > > @@ -28,70 +28,28 @@
> > > timebase-frequency = ;
> > > };
> >
> > FWIW I think we should add the compatible that the linux dt has,
> > signifying that this memory layout is compatible with the v2022.10
> > release and later (w/ appropriate line-wrapping ofc):
> > compatible = "microchip,mpfs-icicle-reference-rtlv2210",
> > "microchip,mpfs-icicle-kit", "microchip,mpfs";
> >
> > Other than that:
> > Reviewed-by: Conor Dooley
> >
> > > - reserved-memory {
> > > - ranges;
> > > - #size-cells = <2>;
> > > - #address-cells = <2>;
> > > -
> > > - fabricbuf0: fabricbuf@0 {
> > > - compatible = "shared-dma-pool";
> > > - reg = <0x0 0xae00 0x0 0x200>;
> > > - label = "fabricbuf0-ddr-c";
> > > - };
> > > -
> > > - fabricbuf1: fabricbuf@1 {
> > > - compatible = "shared-dma-pool";
> > > - reg = <0x0 0xc000 0x0 0x800>;
> > > - label = "fabricbuf1-ddr-nc";
> > > - };
> > > -
> > > - fabricbuf2: fabricbuf@2 {
> > > - compatible = "shared-dma-pool";
> > > - reg = <0x0 0xd800 0x0 0x800>;
> > > - label = "fabricbuf2-ddr-nc-wcb";
> > > - };
> > > - };
> > > -
> > > - udmabuf0 {
> > > - compatible = "ikwzm,u-dma-buf";
> > > - device-name = "udmabuf-ddr-c0";
> > > - minor-number = <0>;
> > > - size = <0x0 0x200>;
> > > - memory-region = <>;
> > > - sync-mode = <3>;
> > > - };
> > > -
> > > - udmabuf1 {
> > > - compatible = "ikwzm,u-dma-buf";
> > > - device-name = "udmabuf-ddr-nc0";
> > > - minor-number = <1>;
> > > - size = <0x0 0x800>;
> > > - memory-region = <>;
> > > - sync-mode = <3>;
> > > - };
> > > -
> > > - udmabuf2 {
> > > - compatible = "ikwzm,u-dma-buf";
> > > - device-name = "udmabuf-ddr-nc-wcb0";
> > > - minor-number = <2>;
> > > - size = <0x0 0x800>;
> > > - memory-region = <>;
> > > - sync-mode = <3>;
> > > - };
> > > -
> > > ddrc_cache_lo: memory@8000 {
> > > device_type = "memory";
> > > - reg = <0x0 0x8000 0x0 0x2e00>;
> > > - clocks = < CLK_DDRC>;
> > > + reg = <0x0 0x8000 0x0 0x4000>;
> > > status = "okay";
> > > };
> > >
> > > ddrc_cache_hi: memory@10 {
>
> Sorry for not noticing prior, but this should bee changed too to
> match
> the reg property shouldn't it..
>
Yes, will update same.
Regards
Padmarao
> > > device_type = "memory";
> > > - reg = <0x10 0x0 0x0 0x4000>;
> > > - clocks = < CLK_DDRC>;
> > > + reg = <0x10 0x4000 0x0 0x4000>;
> > > status = "okay";
> > > };
> > > +
> > > + reserved-memory {
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > + ranges;
> > > +
> > > + hss_payload: region@BFC0 {
> > > + reg = <0x0 0xBFC0 0x0 0x40>;
> > > + no-map;
> > > + };
> > > + };
> > > };
> > >
> > > {
> > >
Re: [PATCH v2 1/4] riscv: dts: Update memory configuration
On Sat, 2022-10-22 at 12:21 +0100, Conor Dooley wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> On Fri, Oct 21, 2022 at 12:29:19PM +0530, Padmarao Begari wrote:
> > In the v2022.10 Icicle reference design, the seg registers are
> > going to be
>
> Hey Padmarao,
> Since the release was done the other day I think that this should be
> s/are going to be/have been
>
Ok, will update same.
> > changed, resulting in a required change to the memory map.
> > A small 4MB reservation is made at the end of 32-bit DDR to provide
> > some
> > memory for the HSS to use, so that it can cache its payload between
> > reboots of a specific context.
> >
> > Co-developed-by: Conor Dooley
> > Signed-off-by: Conor Dooley
> > Signed-off-by: Padmarao Begari
> > Reviewed-by: Conor Dooley
> > ---
> > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 70 --
> > --
> > 1 file changed, 14 insertions(+), 56 deletions(-)
> >
> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > index 287ef3d23b..876c475069 100644
> > --- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > @@ -1,6 +1,6 @@
> > // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > /*
> > - * Copyright (C) 2021 Microchip Technology Inc.
> > + * Copyright (C) 2021-2022 Microchip Technology Inc.
> > * Padmarao Begari
> > */
> >
> > @@ -28,70 +28,28 @@
> > timebase-frequency = ;
> > };
>
> FWIW I think we should add the compatible that the linux dt has,
> signifying that this memory layout is compatible with the v2022.10
> release and later (w/ appropriate line-wrapping ofc):
> compatible = "microchip,mpfs-icicle-reference-rtlv2210",
> "microchip,mpfs-icicle-kit", "microchip,mpfs";
>
Ok, will add compatible "microchip,mpfs-icicle-reference-rtlv2210"
Regards
Padmarao
> Other than that:
> Reviewed-by: Conor Dooley
>
> > - reserved-memory {
> > - ranges;
> > - #size-cells = <2>;
> > - #address-cells = <2>;
> > -
> > - fabricbuf0: fabricbuf@0 {
> > - compatible = "shared-dma-pool";
> > - reg = <0x0 0xae00 0x0 0x200>;
> > - label = "fabricbuf0-ddr-c";
> > - };
> > -
> > - fabricbuf1: fabricbuf@1 {
> > - compatible = "shared-dma-pool";
> > - reg = <0x0 0xc000 0x0 0x800>;
> > - label = "fabricbuf1-ddr-nc";
> > - };
> > -
> > - fabricbuf2: fabricbuf@2 {
> > - compatible = "shared-dma-pool";
> > - reg = <0x0 0xd800 0x0 0x800>;
> > - label = "fabricbuf2-ddr-nc-wcb";
> > - };
> > - };
> > -
> > - udmabuf0 {
> > - compatible = "ikwzm,u-dma-buf";
> > - device-name = "udmabuf-ddr-c0";
> > - minor-number = <0>;
> > - size = <0x0 0x200>;
> > - memory-region = <>;
> > - sync-mode = <3>;
> > - };
> > -
> > - udmabuf1 {
> > - compatible = "ikwzm,u-dma-buf";
> > - device-name = "udmabuf-ddr-nc0";
> > - minor-number = <1>;
> > - size = <0x0 0x800>;
> > - memory-region = <>;
> > - sync-mode = <3>;
> > - };
> > -
> > - udmabuf2 {
> > - compatible = "ikwzm,u-dma-buf";
> > - device-name = "udmabuf-ddr-nc-wcb0";
> > - minor-number = <2>;
> > - size = <0x0 0x800>;
> > - memory-region = <>;
> > - sync-mode = <3>;
> > - };
> > -
> > ddrc_cache_lo: memory@8000 {
> > device_type = "memory";
> > - reg = <0x0 0x8000 0x0 0x2e00>;
> > - clocks = < CLK_DDRC>;
> > + reg = <0x0 0x8000 0x0 0x4000>;
> > status = "okay";
> > };
> >
> > ddrc_cache_hi: memory@10 {
> > device_type = "memory";
> > - reg = <0x10 0x0 0x0 0x4000>;
> > - clocks = < CLK_DDRC>;
> > + reg = <0x10 0x4000 0x0 0x4000>;
> > status = "okay";
> > };
> > +
> > + reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + hss_payload: region@BFC0 {
> > + reg = <0x0 0xBFC0 0x0 0x40>;
> > + no-map;
> > + };
> > + };
> > };
> >
> > {
> > --
> > 2.25.1
> >
Re: [PATCH 4/4] spi: Add Microchip PolarFire SoC QSPI driver
Hi Conor,
> On Wed, 2022-10-19 at 17:20 +0100, Conor Dooley wrote:
>
> On Wed, Oct 19, 2022 at 08:23:22PM +0530, Padmarao Begari wrote:
> > Add QSPI driver code for the Microchip PolarFire SoC.
> > This driver supports the qspi standard, dual and quad
> > mode interfaces.
> >
> > Signed-off-by: Padmarao Begari
> > Signed-off-by: Naga Sureshkumar Relli <
> > nagasuresh.re...@microchip.com>
> > ---
> > drivers/spi/Kconfig | 6 +
> > drivers/spi/Makefile | 1 +
> > drivers/spi/microchip_qspi.c | 504
> > +++
> > 3 files changed, 511 insertions(+)
> > create mode 100644 drivers/spi/microchip_qspi.c
> >
> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> > index 2f12081f88..690306309a 100644
> > --- a/drivers/spi/Kconfig
> > +++ b/drivers/spi/Kconfig
> > @@ -237,6 +237,12 @@ config MESON_SPIFC
> > This driver can be used to access the SPI NOR flash chips
> > on
> > Amlogic Meson SoCs.
> >
> > +config MICROCHIP_QSPI
>
> Can this be MICROCHIP_COREQSPI to match my proposed name of the
> driver
> and the function/structure names in the driver?
>
Ok
> > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> > +
> > +static const struct udevice_id mchp_coreqspi_ids[] = {
> > + { .compatible = "microchip,mpfs-qspi" },
>
> Could we add microchip,coreqspi-rtl-v2 to the compatible list here
> please to match the linux driver? The linux driver works perfectly
> well
> with the fabric core and I assume that's the case for the the U-Boot
> driver too?
>
Ok
Regards
Padmarao
> Thanks,
> Conor.
>
> > + { }
> > +};
> > +
> > +U_BOOT_DRIVER(mchp_coreqspi) = {
> > + .name = "mchp_coreqspi",
> > + .id = UCLASS_SPI,
> > + .of_match = mchp_coreqspi_ids,
> > + .ops= _coreqspi_ops,
> > + .priv_auto = sizeof(struct mchp_coreqspi),
> > + .probe = mchp_coreqspi_probe,
> > +};
> > --
> > 2.25.1
> >
Re: [PATCH 4/4] spi: Add Microchip PolarFire SoC QSPI driver
Hi Conor, > On Wed, 2022-10-19 at 16:47 +0100, Conor Dooley wrote: > > On Wed, Oct 19, 2022 at 03:16:01PM +, tudor.amba...@microchip.com > wrote: > > Hi! > > > > On 10/19/22 17:53, Padmarao Begari wrote: > > > drivers/spi/microchip_qspi.c | 504 > > > +++ > > > > The name is too generic, there are multiple QSPI IPs inside mchp. > > I would suggest to create an mchp directory and rename your c file > > to > > maybe something like mpfs-qspi? > > The (linux) driver works for both the "hard" peripheral on mpfs & for > the core in FPGA fabric. I would wouldn't mind copying the linux > naming > and using "microchip-corespi" & "microchip-coreqspi" as the > underlying > IPs are called CoreSPI and CoreQSPI respectively. > Ok, will use "microchip-coreqspi" name. Regards Padmarao
Re: [PATCH 2/4] riscv: dts: Add QSPI NAND device node
Hi Conor,
> On Wed, 2022-10-19 at 16:59 +0100, Conor Dooley wrote:
>
> On Wed, Oct 19, 2022 at 08:23:20PM +0530, Padmarao Begari wrote:
>
> > riscv: dts: Add QSPI NAND device node
>
> I didn't notice this on 1/3, but I think we need to mention which
> board
> that this is being added for in the shortlog.
Ok, will board details.
Regards
Padmarao
> Thanks,
> Conor.
>
> > Add QSPI NAND device node to the Microchip PolarFire SoC
> > Icicle kit device tree
> >
> > Signed-off-by: Padmarao Begari
> > ---
> > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 15 +++
> > 1 file changed, 15 insertions(+)
> >
> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > index 876c475069..679221e13f 100644
> > --- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > @@ -18,6 +18,7 @@
> > aliases {
> > serial1 =
> > ethernet0 =
> > + spi0 =
> > };
> >
> > chosen {
> > @@ -113,3 +114,17 @@
> > ti,fifo-depth = <0x1>;
> > };
> > };
> > +
> > + {
> > + status = "okay";
> > + num-cs = <1>;
> > + flash0: spi-nand@0 {
> > + compatible = "spi-nand";
> > + reg = <0x0>;
> > + spi-tx-bus-width = <4>;
> > + spi-rx-bus-width = <4>;
> > + spi-max-frequency = <2000>;
> > + spi-cpol;
> > + spi-cpha;
> > + };
> > +};
> > --
> > 2.25.1
> >
Re: [PATCH 2/4] riscv: dts: Add QSPI NAND device node
Hi Tudor,
> On Wed, 2022-10-19 at 15:28 +, Tudor Ambarus - M18064 wrote:
> On 10/19/22 17:53, Padmarao Begari wrote:
> > + flash0: spi-nand@0 {
>
> the node should have generic name according to the dt specification,
> so please s/spi-nand/flash.
>
Ok, will use "flash"
Regards
Padmarao
> --
> Cheers,
> ta
>
Re: [PATCH 1/4] riscv: dts: update memory configuration
Hi Conor,
> On Wed, 2022-10-19 at 16:57 +0100, Conor Dooley wrote:
>
> On Wed, Oct 19, 2022 at 08:23:19PM +0530, Padmarao Begari wrote:
> > In the v2022.10 Icicle reference design, the seg registers are
> > going to be
> > changed, resulting in a required change to the memory map.
> > A small 4MB reservation is made at the end of 32-bit DDR to provide
> > some
> > memory for the HSS to use, so that it can cache its payload between
> > reboots of a specific context.
> >
> > Signed-off-by: Padmarao Begari
> > Signed-off-by: Conor Dooley
>
> Hmm, not sure that my SoB here is correct. If you took my patch
> directly, then you should change the patch so that I am the author or
> otherwise I think it should be:
> Co-developed-by: Conor Dooley
> Signed-off-by: Conor Dooley
> Signed-off-by: Padmarao Begari
>
Ok. will add you with "Co-developed-by"
Regards
Padmarao
> I assume that it is the same for the QSPI driver?
> Otherwise, LGTM:
> Reviewed-by: Conor Dooley
>
> Thanks,
> Conor.
> > ---
> > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 70 --
> > --
> > 1 file changed, 14 insertions(+), 56 deletions(-)
> >
> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > index 287ef3d23b..876c475069 100644
> > --- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > @@ -1,6 +1,6 @@
> > // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > /*
> > - * Copyright (C) 2021 Microchip Technology Inc.
> > + * Copyright (C) 2021-2022 Microchip Technology Inc.
> > * Padmarao Begari
> > */
> >
> > @@ -28,70 +28,28 @@
> > timebase-frequency = ;
> > };
> >
> > - reserved-memory {
> > - ranges;
> > - #size-cells = <2>;
> > - #address-cells = <2>;
> > -
> > - fabricbuf0: fabricbuf@0 {
> > - compatible = "shared-dma-pool";
> > - reg = <0x0 0xae00 0x0 0x200>;
> > - label = "fabricbuf0-ddr-c";
> > - };
> > -
> > - fabricbuf1: fabricbuf@1 {
> > - compatible = "shared-dma-pool";
> > - reg = <0x0 0xc000 0x0 0x800>;
> > - label = "fabricbuf1-ddr-nc";
> > - };
> > -
> > - fabricbuf2: fabricbuf@2 {
> > - compatible = "shared-dma-pool";
> > - reg = <0x0 0xd800 0x0 0x800>;
> > - label = "fabricbuf2-ddr-nc-wcb";
> > - };
> > - };
> > -
> > - udmabuf0 {
> > - compatible = "ikwzm,u-dma-buf";
> > - device-name = "udmabuf-ddr-c0";
> > - minor-number = <0>;
> > - size = <0x0 0x200>;
> > - memory-region = <>;
> > - sync-mode = <3>;
> > - };
> > -
> > - udmabuf1 {
> > - compatible = "ikwzm,u-dma-buf";
> > - device-name = "udmabuf-ddr-nc0";
> > - minor-number = <1>;
> > - size = <0x0 0x800>;
> > - memory-region = <>;
> > - sync-mode = <3>;
> > - };
> > -
> > - udmabuf2 {
> > - compatible = "ikwzm,u-dma-buf";
> > - device-name = "udmabuf-ddr-nc-wcb0";
> > - minor-number = <2>;
> > - size = <0x0 0x800>;
> > - memory-region = <>;
> > - sync-mode = <3>;
> > - };
> > -
> > ddrc_cache_lo: memory@8000 {
> > device_type = "memory";
> > - reg = <0x0 0x8000 0x0 0x2e00>;
> > - clocks = < CLK_DDRC>;
> > + reg = <0x0 0x8000 0x0 0x4000>;
> > status = "okay";
> > };
> >
> > ddrc_cache_hi: memory@10 {
> > device_type = "memory";
> > - reg = <0x10 0x0 0x0 0x4000>;
> > - clocks = < CLK_DDRC>;
> > + reg = <0x10 0x4000 0x0 0x4000>;
> > status = "okay";
> > };
> > +
> > + reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + hss_payload: region@BFC0 {
> > + reg = <0x0 0xBFC0 0x0 0x40>;
> > + no-map;
> > + };
> > + };
> > };
> >
> > {
> > --
> > 2.25.1
> >
Re: [PATCH 1/6] net: macb: use dummy descriptor for RBQP
Hi Eugen,
This series of patches break my side of work(patches) so you need to create
patches after my patches are going into master branch because my patches are
already reviewed and tested.
Regards
Padmarao
From: Eugen Hristev - M18282
Sent: Wednesday, December 16, 2020 12:24 PM
To: anup.pa...@wdc.com ; bin.m...@windriver.com
; Padmarao Begari - I30397
Cc: Claudiu Beznea - M18063 ;
joe.hershber...@ni.com ; u-boot@lists.denx.de
Subject: Re: [PATCH 1/6] net: macb: use dummy descriptor for RBQP
On 03.12.2020 11:25, Claudiu Beznea wrote:
> In case of multiple queues on RX side the queue scheduler
> will try to use all the available configured queues (with
> descriptors having TX_USED bit cleared). If at least one RBQP
> points to a descriptor with a valid used bit configuration then
> the reception may block as this may point to any memory. To avoid
> this scenario all the queues (except queue zero) were disabled by
> setting DMA descriptors with used bit set on proper RBQP. The driver
> anyway uses only queue 0 for TX/RX.
>
> Signed-off-by: Claudiu Beznea
> ---
Hi Anup, Bin, Padmarao,
I noticed on the mailing list that you have been actively working and
testing the Macb driver on various platforms, we have this series
outstanding and I want to make sure that it does not break anything on
your side, so it would be appreciated if you could have a look or test
it before it goes into master branch.
Thanks !
Eugen
> drivers/net/macb.c | 4 +++-
> drivers/net/macb.h | 2 ++
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> index b80a259ff757..836eb85ec96a 100644
> --- a/drivers/net/macb.c
> +++ b/drivers/net/macb.c
> @@ -732,8 +732,10 @@ static int gmac_init_multi_queues(struct macb_device
> *macb)
>flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
>ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
>
> - for (i = 1; i < num_queues; i++)
> + for (i = 1; i < num_queues; i++) {
>gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
> + gem_writel_queue_RBQP(macb, macb->dummy_desc_dma, i - 1);
> + }
>
>return 0;
> }
> diff --git a/drivers/net/macb.h b/drivers/net/macb.h
> index 9b16383eba46..28c7fe306883 100644
> --- a/drivers/net/macb.h
> +++ b/drivers/net/macb.h
> @@ -768,5 +768,7 @@
> #define GEM_RX_CSUM_CHECKED_MASK2
> #define gem_writel_queue_TBQP(port, value, queue_num) \
>writel((value), (port)->regs + GEM_TBQP(queue_num))
> +#define gem_writel_queue_RBQP(port, value, queue_num)\
> + writel((value), (port)->regs + GEM_RBQP(queue_num))
>
> #endif /* __DRIVERS_MACB_H__ */
>
[PATCH v1 8/8] doc: board: Add Microchip MPFS Icicle Kit doc
From: Padmarao Begari
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: Padmarao Begari
---
doc/board/index.rst | 1 +
doc/board/microchip/index.rst | 9 +
doc/board/microchip/mpfs_icicle.rst | 605
3 files changed, 615 insertions(+)
create mode 100644 doc/board/microchip/index.rst
create mode 100644 doc/board/microchip/mpfs_icicle.rst
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 63935abcd7..e50a78d752 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -15,6 +15,7 @@ Board-specific doc
freescale/index
google/index
intel/index
+ microchip/index
renesas/index
rockchip/index
sifive/index
diff --git a/doc/board/microchip/index.rst b/doc/board/microchip/index.rst
new file mode 100644
index 00..b09e6788af
--- /dev/null
+++ b/doc/board/microchip/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip
+==
+
+.. toctree::
+ :maxdepth: 2
+
+ mpfs_icicle
diff --git a/doc/board/microchip/mpfs_icicle.rst
b/doc/board/microchip/mpfs_icicle.rst
new file mode 100644
index 00..d1e6bd2077
--- /dev/null
+++ b/doc/board/microchip/mpfs_icicle.rst
@@ -0,0 +1,605 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip PolarFire SoC Icicle Kit
+==
+
+RISC-V PolarFire SoC
+-
+The PolarFire SoC is the 4+1 64-bit RISC-V SoC from Microchip.
+
+The Icicle Kit development platform is based on PolarFire SoC and capable
+of running Linux.
+
+Mainline support
+
+The support for following drivers are already enabled:
+
+1. NS16550 UART Driver.
+2. Microchip Clock Driver.
+3. Cadence MACB ethernet driver for networking support.
+4. Cadence MMC Driver for eMMC/SD support.
+
+Booting from eMMC using HSS
+---
+
+Building
+
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+ export CROSS_COMPILE=
+
+3. make microchip_mpfs_icicle_defconfig
+4. make
+
+Flashing
+
+
+The current U-Boot port is supported in S-mode only and loaded from DRAM.
+
+A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is required to
+boot the u-boot.bin in S-mode.
+
+Currently, the u-boot.bin is used as a payload of the HSS firmware.
+
+You will be creating a payload from `u-boot-dtb.bin`.
+Copy this file to the toplevel HSS (Hart Software Services) directory.
+
+Creating the HSS payload
+
+
+Please refer to HSS documenation to build the HSS firmware.
+(Note: HSS git repo is at
+https://github.com/polarfire-soc/hart-software-services/blob/master
+/tools/hss-payload-generator/README.md)
+
+Once the payload binary is generated, it should be copied to the eMMC.
+
+FPGA design with HSS programming file
+-
+https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards
+/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md
+
+The HSS firmware runs from the PolarFire SoC eNVM on reset.
+
+eMMC
+
+Program eMMC with payload binary is explained in the PolarFire SoC
documentation.
+
+(Note: PolarFire SoC Documentation git repo is at
+https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards
+/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md#eMMC
+
+Once the payload image is copied to the eMMC, press CTRL+C in the HSS command
+line interface, then type 'boot' and enter to boot the newly copied image.
+
+.. code-block:: none
+
+sudo dd if= of=/dev/sdX bs=512
+
+Booting
+---
+you should see the U-Boot prompt on UART1.
+
+Sample boot log from MPFS Icicle Kit
+---
+
+.. code-block:: none
+
+ U-Boot 2020.10-00544-g4f642dd804-dirty (Oct 16 2020 - 11:37:31 +0530)
+
+ CPU: rv64imafdc
+ Model: Microchip PolarFire-SoC
+ DRAM: 1 GiB
+ MMC: sdhc@20008000: 0
+ In:serial@2010
+ Out: serial@2010
+ Err: serial@2010
+ Net: eth0: ethernet@20112000
+ Hit any key to stop autoboot: 0
+
+Now you can configure your networking, tftp server and use tftp boot method to
+load uImage(with initramfs).
+
+.. code-block:: none
+
+ RISC-V # setenv kernel_addr_r 0x8020
+ RISC-V # setenv fdt_addr_r 0x8220
+
+ RISC-V # setenv ipaddr 192.168.1.5
+ RISC-V # setenv netmask 255.255.255.0
+ RISC-V # setenv serverip 192.168.1.3
+ RISC-V # setenv gateway 192.168.1.1
+
+ RISC-V # tftpboot ${kernel_addr_r} uImage
+ ethernet@20112000: PHY present at 9
+ ethernet@20112000: Starting autonegotiation...
+ ethernet@20112000: Autonegotiation complete
+ ethernet@20112000: link up, 1000Mbps full-duplex (lpa: 0x7800)
+ Using ethernet@20112000 device
+ TFTP from server 192.168.1.3; our IP address is 192.168.1.5
+ Filename
[PATCH v1 7/8] clk: Add Microchip PolarFire SoC clock driver
From: Padmarao Begari
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: Padmarao Begari
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/microchip/Kconfig| 5 +
drivers/clk/microchip/Makefile | 1 +
drivers/clk/microchip/clk_pfsoc.c| 120
drivers/clk/microchip/clk_pfsoc.h| 19 +++
drivers/clk/microchip/clk_pfsoc_cfg.c| 135 ++
drivers/clk/microchip/clk_pfsoc_periph.c | 171 +++
8 files changed, 453 insertions(+)
create mode 100644 drivers/clk/microchip/Kconfig
create mode 100644 drivers/clk/microchip/Makefile
create mode 100644 drivers/clk/microchip/clk_pfsoc.c
create mode 100644 drivers/clk/microchip/clk_pfsoc.h
create mode 100644 drivers/clk/microchip/clk_pfsoc_cfg.c
create mode 100644 drivers/clk/microchip/clk_pfsoc_periph.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4dfbad7986..1161fe7b5a 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -173,6 +173,7 @@ source "drivers/clk/exynos/Kconfig"
source "drivers/clk/imx/Kconfig"
source "drivers/clk/kendryte/Kconfig"
source "drivers/clk/meson/Kconfig"
+source "drivers/clk/microchip/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/owl/Kconfig"
source "drivers/clk/renesas/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d1e295ac7c..bd8a6eed88 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
obj-$(CONFIG_CLK_K210) += kendryte/
+obj-$(CONFIG_CLK_MPFS) += microchip/
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
obj-$(CONFIG_CLK_OWL) += owl/
diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig
new file mode 100644
index 00..b70241559d
--- /dev/null
+++ b/drivers/clk/microchip/Kconfig
@@ -0,0 +1,5 @@
+config CLK_MPFS
+ bool "Clock support for Microchip PolarFire SoC"
+ depends on CLK && CLK_CCF
+ help
+ This enables support clock driver for Microchip PolarFire SoC
platform.
diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile
new file mode 100644
index 00..c7f5ad21ae
--- /dev/null
+++ b/drivers/clk/microchip/Makefile
@@ -0,0 +1 @@
+obj-y += clk_pfsoc.o clk_pfsoc_cfg.o clk_pfsoc_periph.o
diff --git a/drivers/clk/microchip/clk_pfsoc.c
b/drivers/clk/microchip/clk_pfsoc.c
new file mode 100644
index 00..6c7f89f25c
--- /dev/null
+++ b/drivers/clk/microchip/clk_pfsoc.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Microchip Technology Inc.
+ * Padmarao Begari
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk_pfsoc.h"
+
+/* All methods are delegated to CCF clocks */
+
+static ulong pfsoc_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return clk_get_rate(c);
+}
+
+static ulong pfsoc_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return clk_set_rate(c, rate);
+}
+
+static int pfsoc_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *p;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+
+ err = clk_get_by_id(parent->id, );
+ if (err)
+ return err;
+
+ return clk_set_parent(c, p);
+}
+
+static int pfsoc_clk_endisable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return enable ? clk_enable(c) : clk_disable(c);
+}
+
+static int pfsoc_clk_enable(struct clk *clk)
+{
+ return pfsoc_clk_endisable(clk, true);
+}
+
+static int pfsoc_clk_disable(struct clk *clk)
+{
+ return pfsoc_clk_endisable(clk, false);
+}
+
+static int pfsoc_clk_probe(struct udevice *dev)
+{
+ int ret;
+ void __iomem *base;
+ u32 clk_rate;
+ struct clk *clk;
+ const char *parent_clk_name;
+
+ base = dev_read_addr_ptr(dev);
+ if (!base)
+ return -ENODEV;
+ clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+ if (!clk)
+ return -ENOMEM;
+
+ ret = clk_get_by_index(dev, 0, clk);
+ if (ret)
+ return ret;
+ dev_read_u32(clk->dev, "clock-frequency", _rate);
+ parent_clk_name = clk->dev->name;
+ ret = pfsoc_clk_register_cfgs(base, clk_rate, parent_clk_name);
+ ret = pfsoc_clk_register_periphs(base,
[PATCH v1 6/8] net: macb: Add phy address to read it from device tree
From: Padmarao Begari
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari
---
drivers/net/macb.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index e06d85d849..fda90f4e49 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -477,6 +477,12 @@ static int macb_phy_find(struct macb_device *macb, const
char *name)
int i;
u16 phy_id;
+ phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
+ if (phy_id != 0x) {
+ printf("%s: PHY present at %d\n", name, macb->phy_addr);
+ return 0;
+ }
+
/* Search for PHY... */
for (i = 0; i < 32; i++) {
macb->phy_addr = i;
@@ -1254,6 +1260,8 @@ static int macb_eth_probe(struct udevice *dev)
struct macb_device *macb = dev_get_priv(dev);
const char *phy_mode;
int ret;
+ u32 phy_addr;
+ ofnode node;
phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
NULL);
@@ -1264,6 +1272,13 @@ static int macb_eth_probe(struct udevice *dev)
return -EINVAL;
}
+ /* Look for a PHY node under the Ethernet node */
+ node = dev_read_subnode(dev, "ethernet-phy");
+ if (ofnode_valid(node)) {
+ ofnode_read_u32(node, "reg", _addr);
+ macb->phy_addr = phy_addr;
+ }
+
macb->regs = (void *)pdata->iobase;
macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
--
2.17.1
[PATCH v1 4/8] riscv: Add DMA 64-bit address support
From: Padmarao Begari dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit addresses, dma_addr_t need only be 32/64 bits wide. Signed-off-by: Padmarao Begari --- arch/riscv/Kconfig | 5 + arch/riscv/include/asm/types.h | 4 2 files changed, 9 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index aaa3b833a5..7ab1ccff40 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -152,6 +152,11 @@ config 32BIT config 64BIT bool +config DMA_ADDR_T_64BIT + bool + depends on 64BIT + default n + config SIFIVE_CLINT bool depends on RISCV_MMODE || SPL_RISCV_MMODE diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h index 403cf9a48f..b800b2d221 100644 --- a/arch/riscv/include/asm/types.h +++ b/arch/riscv/include/asm/types.h @@ -29,7 +29,11 @@ typedef unsigned short umode_t; #include +#ifdef CONFIG_DMA_ADDR_T_64BIT +typedef u64 dma_addr_t; +#else typedef u32 dma_addr_t; +#endif typedef unsigned long phys_addr_t; typedef unsigned long phys_size_t; -- 2.17.1
[PATCH v1 5/8] net: macb: Add DMA 64-bit address support for macb
From: Padmarao Begari
Enable 64-bit DMA support in the macb driver when CONFIG_DMA_ADDR_T_64BIT
is enabled. 32-bit DMA is enabled by default.
Signed-off-by: Padmarao Begari
---
drivers/net/macb.c | 42 +++---
drivers/net/macb.h | 6 ++
2 files changed, 41 insertions(+), 7 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index b80a259ff7..e06d85d849 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -81,6 +81,10 @@ DECLARE_GLOBAL_DATA_PTR;
struct macb_dma_desc {
u32 addr;
u32 ctrl;
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ u32 addrh;
+ u32 unused;
+#endif
};
#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
@@ -327,6 +331,9 @@ static int _macb_send(struct macb_device *macb, const char
*name, void *packet,
macb->tx_ring[tx_head].ctrl = ctrl;
macb->tx_ring[tx_head].addr = paddr;
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ macb->tx_ring[tx_head].addrh = upper_32_bits((dma_addr_t)packet);
+#endif
barrier();
macb_flush_ring_desc(macb, TX);
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
@@ -732,9 +739,18 @@ static int gmac_init_multi_queues(struct macb_device *macb)
flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
- for (i = 1; i < num_queues; i++)
+ for (i = 1; i < num_queues; i++) {
gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
-
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ gem_writel_queue_TBQPH(macb,
+ upper_32_bits(macb->dummy_desc_dma), i - 1);
+#endif
+ gem_writel_queue_RBQP(macb, macb->dummy_desc_dma, i - 1);
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ gem_writel_queue_RBQPH(macb,
+ upper_32_bits(macb->dummy_desc_dma), i - 1);
+#endif
+ }
return 0;
}
@@ -760,6 +776,9 @@ static void gmac_configure_dma(struct macb_device *macb)
dmacfg &= ~GEM_BIT(ENDIA_DESC);
dmacfg &= ~GEM_BIT(ADDR64);
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ dmacfg |= GEM_BIT(ADDR64);
+#endif
gem_writel(macb, DMACFG, dmacfg);
}
@@ -772,7 +791,7 @@ static int _macb_init(struct macb_device *macb, const char
*name)
#ifdef CONFIG_DM_ETH
struct macb_device *macb = dev_get_priv(dev);
#endif
- unsigned long paddr;
+ dma_addr_t paddr;
int ret;
int i;
@@ -786,8 +805,11 @@ static int _macb_init(struct macb_device *macb, const char
*name)
for (i = 0; i < MACB_RX_RING_SIZE; i++) {
if (i == (MACB_RX_RING_SIZE - 1))
paddr |= MACB_BIT(RX_WRAP);
- macb->rx_ring[i].addr = paddr;
+ macb->rx_ring[i].addr = lower_32_bits(paddr);
macb->rx_ring[i].ctrl = 0;
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ macb->rx_ring[i].addrh = upper_32_bits(paddr);
+#endif
paddr += macb->rx_buffer_size;
}
macb_flush_ring_desc(macb, RX);
@@ -800,6 +822,9 @@ static int _macb_init(struct macb_device *macb, const char
*name)
MACB_BIT(TX_WRAP);
else
macb->tx_ring[i].ctrl = MACB_BIT(TX_USED);
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ macb->tx_ring[i].addrh = 0x0;
+#endif
}
macb_flush_ring_desc(macb, TX);
@@ -812,9 +837,12 @@ static int _macb_init(struct macb_device *macb, const char
*name)
gem_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
#endif
- macb_writel(macb, RBQP, macb->rx_ring_dma);
- macb_writel(macb, TBQP, macb->tx_ring_dma);
-
+ macb_writel(macb, RBQP, lower_32_bits(macb->rx_ring_dma));
+ macb_writel(macb, TBQP, lower_32_bits(macb->tx_ring_dma));
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ macb_writel(macb, RBQPH, upper_32_bits(macb->rx_ring_dma));
+ macb_writel(macb, TBQPH, upper_32_bits(macb->tx_ring_dma));
+#endif
if (macb_is_gem(macb)) {
/* Initialize DMA properties */
gmac_configure_dma(macb);
diff --git a/drivers/net/macb.h b/drivers/net/macb.h
index 9b16383eba..72b84ae96e 100644
--- a/drivers/net/macb.h
+++ b/drivers/net/macb.h
@@ -768,5 +768,11 @@
#define GEM_RX_CSUM_CHECKED_MASK 2
#define gem_writel_queue_TBQP(port, value, queue_num) \
writel((value), (port)->regs + GEM_TBQP(queue_num))
+#define gem_writel_queue_TBQPH(port, value, queue_num) \
+ writel((value), (port)->regs + GEM_TBQPH(queue_num))
+#define gem_writel_queue_RBQP(port, value, queue_num) \
+ writel((value), (port)->regs + GEM_RBQP(queue_num))
+#define gem_writel_queue_RBQPH(port, value, queue_num) \
+ writel((value), (port)->regs + GEM_RBQPH(queue_num))
#endif /* __DRIVERS_MACB_H__ */
--
2.17.1
[PATCH v1 3/8] dt-bindings: clock: Add indexes for reset signals
From: Padmarao Begari Add indexes for reset and clock control signals within the system register module of the Microchip PolarFire SoC. Signed-off-by: Padmarao Begari --- .../dt-bindings/clock/microchip,pfsoc-clock.h | 45 +++ 1 file changed, 45 insertions(+) create mode 100644 include/dt-bindings/clock/microchip,pfsoc-clock.h diff --git a/include/dt-bindings/clock/microchip,pfsoc-clock.h b/include/dt-bindings/clock/microchip,pfsoc-clock.h new file mode 100644 index 00..527cff1a28 --- /dev/null +++ b/include/dt-bindings/clock/microchip,pfsoc-clock.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari + */ + +#ifndef _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_ +#define _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_ + +#define CLK_CPU0 +#define CLK_AXI1 +#define CLK_AHB2 + +#define CLK_ENVM 3 +#define CLK_MAC0 4 +#define CLK_MAC1 5 +#define CLK_MMC6 +#define CLK_TIMER 7 +#define CLK_MMUART08 +#define CLK_MMUART19 +#define CLK_MMUART210 +#define CLK_MMUART311 +#define CLK_MMUART412 +#define CLK_SPI0 13 +#define CLK_SPI1 14 +#define CLK_I2C0 15 +#define CLK_I2C1 16 +#define CLK_CAN0 17 +#define CLK_CAN1 18 +#define CLK_USB19 +#define CLK_RESERVED 20 +#define CLK_RTC21 +#define CLK_QSPI 22 +#define CLK_GPIO0 23 +#define CLK_GPIO1 24 +#define CLK_GPIO2 25 +#define CLK_DDRC 26 +#define CLK_FIC0 27 +#define CLK_FIC1 28 +#define CLK_FIC2 29 +#define CLK_FIC3 30 +#define CLK_ATHENA 31 +#define CLK_CFM32 + +#endif /* _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_ */ -- 2.17.1
[PATCH v1 2/8] riscv: dts: Add device tree for Microchip Icicle Kit
From: Padmarao Begari
Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: Padmarao Begari
---
arch/riscv/dts/Makefile | 1 +
arch/riscv/dts/microchip-icicle-kit-a000.dts | 419 +++
2 files changed, 420 insertions(+)
create mode 100644 arch/riscv/dts/microchip-icicle-kit-a000.dts
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 3a6f96c67d..48c43bd122 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -3,6 +3,7 @@
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
+dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-icicle-kit-a000.dtb
targets += $(dtb-y)
diff --git a/arch/riscv/dts/microchip-icicle-kit-a000.dts
b/arch/riscv/dts/microchip-icicle-kit-a000.dts
new file mode 100644
index 00..e7f0ec6926
--- /dev/null
+++ b/arch/riscv/dts/microchip-icicle-kit-a000.dts
@@ -0,0 +1,419 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+#include "dt-bindings/clock/microchip,pfsoc-clock.h"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip PolarFire-SoC";
+ compatible = "microchip,polarfire-soc";
+
+ aliases {
+ serial0 =
+ ethernet0 =
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpucomplex: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <100>;
+ cpu0: cpu@0 {
+ clocks = < CLK_CPU>;
+ compatible = "sifive,e51", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+ operating-points = <
+ /* kHz uV */
+ 60 110
+ 30 95
+ 15 75
+ >;
+ cpu0intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ clocks = < CLK_CPU>;
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+ operating-points = <
+ /* kHz uV */
+ 60 110
+ 30 95
+ 15 75
+ >;
+ cpu1intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu2: cpu@2 {
+ clocks = < CLK_CPU>;
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <2>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+ operating-points = <
+
[PATCH v1 0/8] Microchip PolarFire SoC support
From: Padmarao Begari This patch set adds Microchip PolarFire SoC Icicle Kit support to RISC-V U-Boot. The patches are based upon latest U-Boot tree (https://gitlab.denx.de/u-boot/u-boot.git) at commit id 9dc6aef8c963ae17e1263b89c692792fce0c7198 All drivers namely: NS16550 Serial, Microchip clock, Cadence eMMC and Cadence MACB Ethernet work fine on actual Microchip PolarFire SoC Icicle Kit. Padmarao Begari (8): riscv: Add Microchip MPFS Icicle Kit support riscv: dts: Add device tree for Microchip Icicle Kit dt-bindings: clock: Add indexes for reset signals riscv: Add DMA 64-bit address support net: macb: Add DMA 64-bit address support for macb net: macb: Add phy address to read it from device tree clk: Add Microchip PolarFire SoC clock driver doc: board: Add Microchip MPFS Icicle Kit doc arch/riscv/Kconfig| 5 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/microchip-icicle-kit-a000.dts | 419 arch/riscv/include/asm/types.h| 4 + board/microchip/mpfs_icicle/Kconfig | 26 + board/microchip/mpfs_icicle/mpfs_icicle.c | 96 ++- configs/microchip_mpfs_icicle_defconfig | 9 +- doc/board/index.rst | 1 + doc/board/microchip/index.rst | 9 + doc/board/microchip/mpfs_icicle.rst | 605 ++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/microchip/Kconfig | 5 + drivers/clk/microchip/Makefile| 1 + drivers/clk/microchip/clk_pfsoc.c | 120 drivers/clk/microchip/clk_pfsoc.h | 19 + drivers/clk/microchip/clk_pfsoc_cfg.c | 135 drivers/clk/microchip/clk_pfsoc_periph.c | 171 + drivers/net/macb.c| 57 +- drivers/net/macb.h| 6 + include/configs/microchip_mpfs_icicle.h | 60 +- .../dt-bindings/clock/microchip,pfsoc-clock.h | 45 ++ 22 files changed, 1744 insertions(+), 52 deletions(-) create mode 100644 arch/riscv/dts/microchip-icicle-kit-a000.dts create mode 100644 doc/board/microchip/index.rst create mode 100644 doc/board/microchip/mpfs_icicle.rst create mode 100644 drivers/clk/microchip/Kconfig create mode 100644 drivers/clk/microchip/Makefile create mode 100644 drivers/clk/microchip/clk_pfsoc.c create mode 100644 drivers/clk/microchip/clk_pfsoc.h create mode 100644 drivers/clk/microchip/clk_pfsoc_cfg.c create mode 100644 drivers/clk/microchip/clk_pfsoc_periph.c create mode 100644 include/dt-bindings/clock/microchip,pfsoc-clock.h -- 2.17.1
[PATCH v1 1/8] riscv: Add Microchip MPFS Icicle Kit support
From: Padmarao Begari
This patch adds Microchip MPFS Icicle Kit support. For now, only
NS16550 Serial, Microchip clock, Cadence eMMC and MACB drivers are
only enabled. The Microchip MPFS Icicle defconfig by default builds
U-Boot for S-Mode because U-Boot on Microchip PolarFire SoC will run
in S-Mode as payload of HSS + OpenSBI.
Signed-off-by: Padmarao Begari
---
board/microchip/mpfs_icicle/Kconfig | 26 ++
board/microchip/mpfs_icicle/mpfs_icicle.c | 96 ++-
configs/microchip_mpfs_icicle_defconfig | 9 ++-
include/configs/microchip_mpfs_icicle.h | 60 +-
4 files changed, 146 insertions(+), 45 deletions(-)
diff --git a/board/microchip/mpfs_icicle/Kconfig
b/board/microchip/mpfs_icicle/Kconfig
index bf8e1a13ec..4406d1a13f 100644
--- a/board/microchip/mpfs_icicle/Kconfig
+++ b/board/microchip/mpfs_icicle/Kconfig
@@ -20,7 +20,33 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
imply SMP
+ imply CLK
+ imply CLK_CCF
+ imply CLK_MPFS
imply SYS_NS16550
+ imply CMD_DHCP
+ imply CMD_EXT2
+ imply CMD_EXT4
+ imply CMD_FAT
+ imply CMD_FS_GENERIC
+ imply CMD_NET
+ imply CMD_PING
+ imply CMD_MMC
+ imply DOS_PARTITION
+ imply EFI_PARTITION
+ imply IP_DYN
+ imply ISO_PARTITION
+ imply MACB
+ imply MII
+ imply NET_RANDOM_ETHADDR
+ imply PHY_LIB
+ imply PHY_VITESSE
+ imply DMA_ADDR_T_64BIT
+ imply MMC
+ imply MMC_WRITE
+ imply MMC_SDHCI
+ imply MMC_SDHCI_CADENCE
endif
diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c
b/board/microchip/mpfs_icicle/mpfs_icicle.c
index 8381361ec3..64133aee59 100644
--- a/board/microchip/mpfs_icicle/mpfs_icicle.c
+++ b/board/microchip/mpfs_icicle/mpfs_icicle.c
@@ -5,11 +5,47 @@
*/
#include
+#include
#include
#include
#include
-#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
+#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
+#define MPFS_SYS_SERVICE_CR((unsigned int *)0x37020050)
+#define MPFS_SYS_SERVICE_SR((unsigned int *)0x37020054)
+#define MPFS_SYS_SERVICE_MAILBOX ((unsigned char *)0x37020800)
+
+#define PERIPH_RESET_VALUE 0x1e8u
+#define SERVICE_CR_REQ 0x1u
+#define SERVICE_SR_BUSY0x2u
+
+static void read_device_serial_number(u8 *response, u8 response_size)
+{
+ u8 idx;
+ u8 *response_buf;
+ unsigned int val;
+
+ response_buf = (u8 *)response;
+
+ writel(SERVICE_CR_REQ, MPFS_SYS_SERVICE_CR);
+
+ /* REQ bit will remain set till the system controller starts
+* processing.
+*/
+ do {
+ val = readl(MPFS_SYS_SERVICE_CR);
+ } while (SERVICE_CR_REQ == (val & SERVICE_CR_REQ));
+
+ /* Once system controller starts processing the busy bit will
+* go high and service is completed when busy bit is gone low
+*/
+ do {
+ val = readl(MPFS_SYS_SERVICE_SR);
+ } while (SERVICE_SR_BUSY == (val & SERVICE_SR_BUSY));
+
+ for (idx = 0; idx < response_size; idx++)
+ response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX + idx);
+}
int board_init(void)
{
@@ -22,10 +58,64 @@ int board_early_init_f(void)
{
unsigned int val;
- /* Reset uart peripheral */
+ /* Reset uart, mmc peripheral */
val = readl(MPFS_SYSREG_SOFT_RESET);
- val = (val & ~(1u << 5u));
+ val = (val & ~(PERIPH_RESET_VALUE));
writel(val, MPFS_SYSREG_SOFT_RESET);
return 0;
}
+
+int board_late_init(void)
+{
+ u32 ret;
+ u32 node;
+ u8 idx;
+ u8 device_serial_number[16] = { 0 };
+ unsigned char mac_addr[6];
+ char icicle_mac_addr[20];
+ void *blob = (void *)gd->fdt_blob;
+
+ node = fdt_path_offset(blob, "ethernet0");
+ if (node < 0) {
+ printf("No ethernet0 path offset\n");
+ return -ENODEV;
+ }
+
+ ret = fdtdec_get_byte_array(blob, node, "mac-address", mac_addr, 6);
+ if (ret) {
+ printf("No mac-address property\n");
+ return -EINVAL;
+ }
+
+ read_device_serial_number(device_serial_number, 16);
+
+ /* Update MAC address with device serial number */
+ mac_addr[0] = 0x00;
+ mac_addr[1] = 0x04;
+ mac_addr[2] = 0xA3;
+ mac_addr[3] = device_serial_number[2];
+ mac_addr[4] = device_serial_number[1];
+ mac_addr[5] = device_serial_number[0];
+
+ ret = fdt_setprop(blob, node, "mac-address", mac_addr, 6);
+ if (ret) {
+ printf("Error setting mac-address property\n");
+ return -ENODEV;
+ }
+
+ icicle_mac_addr[0] = '[';
+
+ sprintf(_mac_addr[1], "%pM", mac_addr);
+
+
