RE: [PATCH 1/1] cmd/riscv/sbi: support System Reset Extension

[Pragnesh Patel]

>-Original Message-
>From: Heinrich Schuchardt 
>Sent: 18 January 2021 02:57
>To: Rick Chen 
>Cc: Atish Patra ; Bin Meng ;
>Pragnesh Patel ; u-boot@lists.denx.de; Heinrich
>Schuchardt 
>Subject: [PATCH 1/1] cmd/riscv/sbi: support System Reset Extension
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Let the sbi command detect the 'System Reset Extension'
>(EID #0x53525354 "SRST").
>
>Cf. https://github.com/riscv/riscv-sbi-doc
>
>Signed-off-by: Heinrich Schuchardt 
>---
> cmd/riscv/sbi.c | 1 +
> 1 file changed, 1 insertion(+)

Reviewed-by: Pragnesh Patel 

[PATCH v4 2/2] riscv: timer: Add support for an early timer

[Pragnesh Patel]

Added support for timer_early_get_count() and timer_early_get_rate()
This is mostly useful in tracing.

Signed-off-by: Pragnesh Patel 
Reviewed-by: Rick Chen 
---

Changes in v4:
- Rebase on master

Changes in v3:
- Add IS_ENABLED(CONFIG_TIMER_EARLY) for timer_early_get_rate()
  and timer_early_get_count() functions.

Changes in v2:
- make u-boot compile for qemu (include/configs/qemu-riscv.h)

 drivers/timer/andes_plmt_timer.c   | 21 -
 drivers/timer/riscv_timer.c| 21 -
 drivers/timer/sifive_clint_timer.c | 21 -
 include/configs/ax25-ae350.h   |  5 +
 include/configs/qemu-riscv.h   |  5 +
 include/configs/sifive-fu540.h |  5 +
 6 files changed, 75 insertions(+), 3 deletions(-)

diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c
index db2cf86f63..a3797b22c7 100644
--- a/drivers/timer/andes_plmt_timer.c
+++ b/drivers/timer/andes_plmt_timer.c
@@ -18,11 +18,30 @@
 /* mtime register */
 #define MTIME_REG(base)((ulong)(base))
 
-static u64 andes_plmt_get_count(struct udevice *dev)
+static u64 notrace andes_plmt_get_count(struct udevice *dev)
 {
return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
 }
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ */
+unsigned long notrace timer_early_get_rate(void)
+{
+   return RISCV_MMODE_TIMER_FREQ;
+}
+
+/**
+ * timer_early_get_count() - Get the timer count before driver model
+ *
+ */
+u64 notrace timer_early_get_count(void)
+{
+   return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
+}
+#endif
+
 static const struct timer_ops andes_plmt_ops = {
.get_count = andes_plmt_get_count,
 };
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 21ae184057..3627ed79b8 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -16,7 +16,7 @@
 #include 
 #include 
 
-static u64 riscv_timer_get_count(struct udevice *dev)
+static u64 notrace riscv_timer_get_count(struct udevice *dev)
 {
__maybe_unused u32 hi, lo;
 
@@ -31,6 +31,25 @@ static u64 riscv_timer_get_count(struct udevice *dev)
return ((u64)hi << 32) | lo;
 }
 
+#if CONFIG_IS_ENABLED(RISCV_SMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ */
+unsigned long notrace timer_early_get_rate(void)
+{
+   return RISCV_SMODE_TIMER_FREQ;
+}
+
+/**
+ * timer_early_get_count() - Get the timer count before driver model
+ *
+ */
+u64 notrace timer_early_get_count(void)
+{
+   return riscv_timer_get_count(NULL);
+}
+#endif
+
 static int riscv_timer_probe(struct udevice *dev)
 {
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
diff --git a/drivers/timer/sifive_clint_timer.c 
b/drivers/timer/sifive_clint_timer.c
index de23b85404..de7b4b95c9 100644
--- a/drivers/timer/sifive_clint_timer.c
+++ b/drivers/timer/sifive_clint_timer.c
@@ -15,11 +15,30 @@
 /* mtime register */
 #define MTIME_REG(base)((ulong)(base) + 0xbff8)
 
-static u64 sifive_clint_get_count(struct udevice *dev)
+static u64 notrace sifive_clint_get_count(struct udevice *dev)
 {
return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
 }
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ */
+unsigned long notrace timer_early_get_rate(void)
+{
+   return RISCV_MMODE_TIMER_FREQ;
+}
+
+/**
+ * timer_early_get_count() - Get the timer count before driver model
+ *
+ */
+u64 notrace timer_early_get_count(void)
+{
+   return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
+}
+#endif
+
 static const struct timer_ops sifive_clint_ops = {
.get_count = sifive_clint_get_count,
 };
diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h
index b2606e794d..bd9c371f83 100644
--- a/include/configs/ax25-ae350.h
+++ b/include/configs/ax25-ae350.h
@@ -17,6 +17,11 @@
 #endif
 #endif
 
+#define RISCV_MMODE_TIMERBASE   0xe600
+#define RISCV_MMODE_TIMER_FREQ  6000
+
+#define RISCV_SMODE_TIMER_FREQ  6000
+
 /*
  * CPU and Board Configuration Options
  */
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index a2f33587c2..5291de83f8 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -29,6 +29,11 @@
 
 #define CONFIG_STANDALONE_LOAD_ADDR0x8020
 
+#define RISCV_MMODE_TIMERBASE  0x200
+#define RISCV_MMODE_TIMER_FREQ 100
+
+#define RISCV_SMODE_TIMER_FREQ 100
+
 /* Environment options */
 
 #ifndef CONFIG_SPL_BUILD
diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
index c1c79db147..0d69d1c548 100644
--- a/include/configs/sifive

[PATCH v4 1/2] trace: select TIMER_EARLY to avoid infinite recursion

[Pragnesh Patel]

When tracing functions is enabled this adds calls to
__cyg_profile_func_enter() and __cyg_profile_func_exit() to the traced
functions.

__cyg_profile_func_enter() and __cyg_profile_func_exit() invoke
timer_get_us() to record the entry and exit time.

initr_dm() will make gd->dm_root = NULL and gd->timer = NULL, so
timer_get_us() -> get_ticks() -> dm_timer_init() will lead to an
indefinite recursion.

So select TIMER_EARLY when tracing got enabled.

Signed-off-by: Pragnesh Patel 
Reviewed-by: Simon Glass 
Reviewed-by: Rick Chen 
---

Changes in v4:
- no change

Changes in v3:
- no change

Changes in v2:
- new patch

 lib/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/Kconfig b/lib/Kconfig
index a704568443..9b9177f2aa 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -210,6 +210,7 @@ config BITREVERSE
 config TRACE
bool "Support for tracing of function calls and timing"
imply CMD_TRACE
+   select TIMER_EARLY
help
  Enables function tracing within U-Boot. This allows recording of call
  traces including timing information. The command can write data to
-- 
2.17.1

Re: [PATCH v3 2/2] riscv: timer: Add support for an early timer

[Pragnesh Patel]

Hi Rick

On Tue, Jan 12, 2021 at 7:30 AM Rick Chen  wrote:
>
> Hi Pragnesh
>
> > > From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
> > > Sent: Sunday, January 10, 2021 8:43 PM
> > > To: u-boot@lists.denx.de
> > > Cc: atish.pa...@wdc.com; palmerdabb...@google.com; bmeng...@gmail.com; 
> > > paul.walms...@sifive.com; anup.pa...@wdc.com; sagar.ka...@sifive.com; 
> > > Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; Palmer Dabbelt; Sean Anderson; 
> > > Simon Glass
> > > Subject: [PATCH v3 2/2] riscv: timer: Add support for an early timer
> > >
> > > Added support for timer_early_get_count() and timer_early_get_rate()
> > > This is mostly useful in tracing.
> > >
> > > Signed-off-by: Pragnesh Patel 
> > > ---
> > >
> > > Changes in v3:
> > > - Add IS_ENABLED(CONFIG_TIMER_EARLY) for timer_early_get_rate()
> > >   and timer_early_get_count() functions.
> >
> > Reviewed-by: Rick Chen 
>
> I am trying to merge to mainline, but it conflict with master.
> Please rebase again,
>
> Applying: trace: select TIMER_EARLY to avoid infinite recursion
> Applying: riscv: timer: Add support for an early timer
> error: patch failed: drivers/timer/andes_plmt_timer.c:17
> error: drivers/timer/andes_plmt_timer.c: patch does not apply
> error: patch failed: drivers/timer/sifive_clint_timer.c:14
> error: drivers/timer/sifive_clint_timer.c: patch does not apply
> Patch failed at 0002 riscv: timer: Add support for an early timer
> The copy of the patch that failed is found in: .git/rebase-apply/patch
> When you have resolved this problem, run "git am --continue".
> If you prefer to skip this patch, run "git am --skip" instead.
> To restore the original branch and stop patching, run "git am --abort".

Will rebase and send again.

>
> Thanks,
> Rick

Re: [PATCH v4] cmd: Add a pwm command

[Pragnesh Patel]

Hi Tom,

Any comment on this ?

On Tue, Dec 22, 2020 at 11:30 AM Pragnesh Patel
 wrote:
>
> Add the command "pwm" for controlling the pwm channels. This
> command provides pwm invert/config/enable/disable functionalities
> via PWM uclass drivers
>
> Signed-off-by: Pragnesh Patel 
> Reviewed-by: Simon Glass 
> ---
>
> Changes in v4:
> - Add ut_assertok() for every run_command()
>
> Changes in v3:
> - Replace goto with return
> - Print return value for error
> - Change the assert condition for success
>
> Changes in v2:
> - Add test for pwm command
>
>  README|   1 +
>  cmd/Kconfig   |   6 ++
>  cmd/Makefile  |   1 +
>  cmd/pwm.c | 117 ++
>  configs/sandbox_defconfig |   1 +
>  test/cmd/Makefile |   1 +
>  test/cmd/pwm.c|  47 +++
>  7 files changed, 174 insertions(+)
>  create mode 100644 cmd/pwm.c
>  create mode 100644 test/cmd/pwm.c
>
> diff --git a/README b/README
> index cb49aa15da..dab291e0d0 100644
> --- a/README
> +++ b/README
> @@ -3160,6 +3160,7 @@ i2c   - I2C sub-system
>  sspi   - SPI utility commands
>  base   - print or set address offset
>  printenv- print environment variables
> +pwm- control pwm channels
>  setenv - set environment variables
>  saveenv - save environment variables to persistent storage
>  protect - enable or disable FLASH write protection
> diff --git a/cmd/Kconfig b/cmd/Kconfig
> index 1595de999b..0d085108f4 100644
> --- a/cmd/Kconfig
> +++ b/cmd/Kconfig
> @@ -918,6 +918,12 @@ config CMD_GPIO
> help
>   GPIO support.
>
> +config CMD_PWM
> +   bool "pwm"
> +   depends on DM_PWM
> +   help
> + Control PWM channels, this allows invert/config/enable/disable PWM 
> channels.
> +
>  config CMD_GPT
> bool "GPT (GUID Partition Table) command"
> select EFI_PARTITION
> diff --git a/cmd/Makefile b/cmd/Makefile
> index dd86675bf2..75df3c136c 100644
> --- a/cmd/Makefile
> +++ b/cmd/Makefile
> @@ -120,6 +120,7 @@ endif
>  obj-$(CONFIG_CMD_PINMUX) += pinmux.o
>  obj-$(CONFIG_CMD_PMC) += pmc.o
>  obj-$(CONFIG_CMD_PSTORE) += pstore.o
> +obj-$(CONFIG_CMD_PWM) += pwm.o
>  obj-$(CONFIG_CMD_PXE) += pxe.o pxe_utils.o
>  obj-$(CONFIG_CMD_WOL) += wol.o
>  obj-$(CONFIG_CMD_QFW) += qfw.o
> diff --git a/cmd/pwm.c b/cmd/pwm.c
> new file mode 100644
> index 00..5849fc57b6
> --- /dev/null
> +++ b/cmd/pwm.c
> @@ -0,0 +1,117 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Control PWM channels
> + *
> + * Copyright (c) 2020 SiFive, Inc
> + * author: Pragnesh Patel 
> + */
> +
> +#include 
> +#include 
> +#include 
> +
> +enum pwm_cmd {
> +   PWM_SET_INVERT,
> +   PWM_SET_CONFIG,
> +   PWM_SET_ENABLE,
> +   PWM_SET_DISABLE,
> +};
> +
> +static int do_pwm(struct cmd_tbl *cmdtp, int flag, int argc,
> + char *const argv[])
> +{
> +   const char *str_cmd, *str_channel = NULL, *str_enable = NULL;
> +   const char *str_pwm = NULL, *str_period = NULL, *str_duty = NULL;
> +   enum pwm_cmd sub_cmd;
> +   struct udevice *dev;
> +   u32 channel, pwm_enable, pwm_dev, period_ns = 0, duty_ns = 0;
> +   int ret;
> +
> +   if (argc < 4)
> +   return CMD_RET_USAGE;
> +
> +   str_cmd = argv[1];
> +   argc -= 2;
> +   argv += 2;
> +
> +   if (argc > 0) {
> +   str_pwm = *argv;
> +   argc--;
> +   argv++;
> +   }
> +
> +   if (!str_pwm)
> +   return CMD_RET_USAGE;
> +
> +   switch (*str_cmd) {
> +   case 'i':
> +   sub_cmd = PWM_SET_INVERT;
> +   break;
> +   case 'c':
> +   sub_cmd = PWM_SET_CONFIG;
> +   break;
> +   case 'e':
> +   sub_cmd = PWM_SET_ENABLE;
> +   break;
> +   case 'd':
> +   sub_cmd = PWM_SET_DISABLE;
> +   break;
> +   default:
> +   return CMD_RET_USAGE;
> +   }
> +
> +   pwm_dev = simple_strtoul(str_pwm, NULL, 10);
> +   ret = uclass_get_device(UCLASS_PWM, pwm_dev, );
> +   if (ret) {
> +   printf("pwm: '%s' not found\n", str_pwm);
> +   return cmd_process_error(cmdtp, ret);
> +   }
> +
> +   if (argc > 0) {
> +   str_channel = *argv;
> +   channel = simple_strtoul(str_channel, NULL, 10);
> +   argc--;
> +   argv++;
> +   

[PATCH v3 2/2] riscv: timer: Add support for an early timer

[Pragnesh Patel]

Added support for timer_early_get_count() and timer_early_get_rate()
This is mostly useful in tracing.

Signed-off-by: Pragnesh Patel 
---

Changes in v3:
- Add IS_ENABLED(CONFIG_TIMER_EARLY) for timer_early_get_rate()
  and timer_early_get_count() functions.

Changes in v2:
- make u-boot compile for qemu (include/configs/qemu-riscv.h)

 drivers/timer/andes_plmt_timer.c   | 21 -
 drivers/timer/riscv_timer.c| 21 -
 drivers/timer/sifive_clint_timer.c | 21 -
 include/configs/ax25-ae350.h   |  5 +
 include/configs/qemu-riscv.h   |  5 +
 include/configs/sifive-fu540.h |  5 +
 6 files changed, 75 insertions(+), 3 deletions(-)

diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c
index cec86718c7..ce4040d76d 100644
--- a/drivers/timer/andes_plmt_timer.c
+++ b/drivers/timer/andes_plmt_timer.c
@@ -17,11 +17,30 @@
 /* mtime register */
 #define MTIME_REG(base)((ulong)(base))
 
-static u64 andes_plmt_get_count(struct udevice *dev)
+static u64 notrace andes_plmt_get_count(struct udevice *dev)
 {
return readq((void __iomem *)MTIME_REG(dev->priv));
 }
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ */
+unsigned long notrace timer_early_get_rate(void)
+{
+   return RISCV_MMODE_TIMER_FREQ;
+}
+
+/**
+ * timer_early_get_count() - Get the timer count before driver model
+ *
+ */
+u64 notrace timer_early_get_count(void)
+{
+   return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
+}
+#endif
+
 static const struct timer_ops andes_plmt_ops = {
.get_count = andes_plmt_get_count,
 };
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 21ae184057..3627ed79b8 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -16,7 +16,7 @@
 #include 
 #include 
 
-static u64 riscv_timer_get_count(struct udevice *dev)
+static u64 notrace riscv_timer_get_count(struct udevice *dev)
 {
__maybe_unused u32 hi, lo;
 
@@ -31,6 +31,25 @@ static u64 riscv_timer_get_count(struct udevice *dev)
return ((u64)hi << 32) | lo;
 }
 
+#if CONFIG_IS_ENABLED(RISCV_SMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ */
+unsigned long notrace timer_early_get_rate(void)
+{
+   return RISCV_SMODE_TIMER_FREQ;
+}
+
+/**
+ * timer_early_get_count() - Get the timer count before driver model
+ *
+ */
+u64 notrace timer_early_get_count(void)
+{
+   return riscv_timer_get_count(NULL);
+}
+#endif
+
 static int riscv_timer_probe(struct udevice *dev)
 {
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
diff --git a/drivers/timer/sifive_clint_timer.c 
b/drivers/timer/sifive_clint_timer.c
index 00ce0f08d6..2e902feb61 100644
--- a/drivers/timer/sifive_clint_timer.c
+++ b/drivers/timer/sifive_clint_timer.c
@@ -14,11 +14,30 @@
 /* mtime register */
 #define MTIME_REG(base)((ulong)(base) + 0xbff8)
 
-static u64 sifive_clint_get_count(struct udevice *dev)
+static u64 notrace sifive_clint_get_count(struct udevice *dev)
 {
return readq((void __iomem *)MTIME_REG(dev->priv));
 }
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ */
+unsigned long notrace timer_early_get_rate(void)
+{
+   return RISCV_MMODE_TIMER_FREQ;
+}
+
+/**
+ * timer_early_get_count() - Get the timer count before driver model
+ *
+ */
+u64 notrace timer_early_get_count(void)
+{
+   return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
+}
+#endif
+
 static const struct timer_ops sifive_clint_ops = {
.get_count = sifive_clint_get_count,
 };
diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h
index b2606e794d..bd9c371f83 100644
--- a/include/configs/ax25-ae350.h
+++ b/include/configs/ax25-ae350.h
@@ -17,6 +17,11 @@
 #endif
 #endif
 
+#define RISCV_MMODE_TIMERBASE   0xe600
+#define RISCV_MMODE_TIMER_FREQ  6000
+
+#define RISCV_SMODE_TIMER_FREQ  6000
+
 /*
  * CPU and Board Configuration Options
  */
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index a2f33587c2..5291de83f8 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -29,6 +29,11 @@
 
 #define CONFIG_STANDALONE_LOAD_ADDR0x8020
 
+#define RISCV_MMODE_TIMERBASE  0x200
+#define RISCV_MMODE_TIMER_FREQ 100
+
+#define RISCV_SMODE_TIMER_FREQ 100
+
 /* Environment options */
 
 #ifndef CONFIG_SPL_BUILD
diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
index c1c79db147..0d69d1c548 100644
--- a/include/configs/sifive-fu540.h
+++ b/include/configs/sifive-fu540.h
@@ -36,6 +36,11 @@
 

[PATCH v3 1/2] trace: select TIMER_EARLY to avoid infinite recursion

[Pragnesh Patel]

When tracing functions is enabled this adds calls to
__cyg_profile_func_enter() and __cyg_profile_func_exit() to the traced
functions.

__cyg_profile_func_enter() and __cyg_profile_func_exit() invoke
timer_get_us() to record the entry and exit time.

initr_dm() will make gd->dm_root = NULL and gd->timer = NULL, so
timer_get_us() -> get_ticks() -> dm_timer_init() will lead to an
indefinite recursion.

So select TIMER_EARLY when tracing got enabled.

Signed-off-by: Pragnesh Patel 
Reviewed-by: Simon Glass 
Reviewed-by: Rick Chen 
---

Changes in v3:
- no change

Changes in v2:
- new patch

 lib/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/Kconfig b/lib/Kconfig
index 7673d2e4e0..671386963a 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -210,6 +210,7 @@ config BITREVERSE
 config TRACE
bool "Support for tracing of function calls and timing"
imply CMD_TRACE
+   select TIMER_EARLY
help
  Enables function tracing within U-Boot. This allows recording of call
  traces including timing information. The command can write data to
-- 
2.17.1

Re: [PATCH v2 2/2] riscv: timer: Add support for an early timer

[Pragnesh Patel]

Hi Rick,

On Wed, Jan 6, 2021 at 7:28 AM Rick Chen  wrote:
>
> Hi Pragnesh
>
> > On Tue, Jan 5, 2021 at 7:12 AM Sean Anderson  wrote:
> > >
> > > On 1/4/21 8:37 PM, Rick Chen wrote:
> > > > Hi Pragnesh
> > > >
> > > >>> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
> > > >>> Sent: Tuesday, December 22, 2020 2:23 PM
> > > >>> To: u-boot@lists.denx.de
> > > >>> Cc: atish.pa...@wdc.com; palmerdabb...@google.com; 
> > > >>> bmeng...@gmail.com; paul.walms...@sifive.com; anup.pa...@wdc.com; 
> > > >>> sagar.ka...@sifive.com; Rick Jian-Zhi Chen(陳建志); 
> > > >>> pragnesh.pa...@openfive.com; Pragnesh Patel; Palmer Dabbelt; Sean 
> > > >>> Anderson; Claudiu Beznea; Simon Glass
> > > >>> Subject: [PATCH v2 2/2] riscv: timer: Add support for an early timer
> > > >>>
> > > >>> Added support for timer_early_get_count() and timer_early_get_rate()
> > > >>> This is mostly useful in tracing.
> > > >>>
> > > >>> Signed-off-by: Pragnesh Patel 
> > > >>> ---
> > > >>>
> > > >>> Changes in v2:
> > > >>> - make u-boot compile for qemu (include/configs/qemu-riscv.h)
> > > >>>
> > > >>>   drivers/timer/andes_plmt_timer.c   | 21 -
> > > >>>   drivers/timer/riscv_timer.c| 21 -
> > > >>>   drivers/timer/sifive_clint_timer.c | 21 -
> > > >>>   include/configs/ax25-ae350.h   |  5 +
> > > >>>   include/configs/qemu-riscv.h   |  5 +
> > > >>>   include/configs/sifive-fu540.h |  5 +
> > > >>>   6 files changed, 75 insertions(+), 3 deletions(-)
> > > >>
> > > >> Reviewed-by: Rick Chen 
> > > >
> > > > Please check about the CI failure item:
> > > > https://gitlab.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/196578
> > >
> > > 404 for me (though I suspect it's really a 403).
> >
> > 404 for me also.
> >
>
> Followings are the errors from CI:
>
> ...
> ...
> +
> 562 riscv: + microchip_mpfs_icicle
> 563+drivers/timer/sifive_clint_timer.c: In function 'timer_early_get_rate':
> 564+drivers/timer/sifive_clint_timer.c:28:9: error:
> 'RISCV_MMODE_TIMER_FREQ' undeclared (first use in this function)
> 565+ 28 | return RISCV_MMODE_TIMER_FREQ;
> 566+ | ^~
> 567+drivers/timer/sifive_clint_timer.c:28:9: note: each undeclared
> identifier is reported only once for each function it appears in
> 568+drivers/timer/sifive_clint_timer.c: In function 'timer_early_get_count':
> 569+drivers/timer/sifive_clint_timer.c:37:41: error:
> 'RISCV_MMODE_TIMERBASE' undeclared (first use in this function)
> 570+ 37 | return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
> 571+ | ^
> 572+drivers/timer/sifive_clint_timer.c:15:36: note: in definition of
> macro 'MTIME_REG'
> 573+ 15 | #define MTIME_REG(base) ((ulong)(base) + 0xbff8)
> 574+ | ^~~~
> 575+drivers/timer/sifive_clint_timer.c:29:1: error: control reaches
> end of non-void function [-Werror=return-type]
> 576+ 29 | }
> 577+ | ^
> 578+drivers/timer/sifive_clint_timer.c:38:1: error: control reaches
> end of non-void function [-Werror=return-type]
> 579+ 38 | }
> 580+cc1: all warnings being treated as errors
> 581+make[3]: *** [drivers/timer/sifive_clint_timer.o] Error 1
> 582+make[2]: *** [drivers/timer] Error 2
> 583+make[1]: *** [drivers] Error 2
> 584+make: *** [sub-make] Error 2
> 585 riscv: + sipeed_maix_bitm
> 586+drivers/timer/sifive_clint_timer.c: In function 'timer_early_get_rate':
> 587+drivers/timer/sifive_clint_timer.c:28:9: error:
> 'RISCV_MMODE_TIMER_FREQ' undeclared (first use in this function)
> 588+ 28 | return RISCV_MMODE_TIMER_FREQ;
> 589+ | ^~
> 590+drivers/timer/sifive_clint_timer.c:28:9: note: each undeclared
> identifier is reported only once for each function it appears in
> 591+drivers/timer/sifive_clint_timer.c: In function 'timer_early_get_count':
> 592+drivers/timer/sifive_clint_timer.c:37:41: error:
> 'RISCV_MMODE_TIMERBASE' undeclared (first use in this function)
> 593+ 37 | return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
> 594+ | ^
> 595+drivers/timer/sifive_clint_timer.c:15:36: note: in definition of
> macro 'MTIME_REG'
> 596+ 15 | #define MTIME_REG(base)

Re: [PATCH v2 2/2] riscv: timer: Add support for an early timer

[Pragnesh Patel]

On Tue, Jan 5, 2021 at 7:12 AM Sean Anderson  wrote:
>
> On 1/4/21 8:37 PM, Rick Chen wrote:
> > Hi Pragnesh
> >
> >>> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
> >>> Sent: Tuesday, December 22, 2020 2:23 PM
> >>> To: u-boot@lists.denx.de
> >>> Cc: atish.pa...@wdc.com; palmerdabb...@google.com; bmeng...@gmail.com; 
> >>> paul.walms...@sifive.com; anup.pa...@wdc.com; sagar.ka...@sifive.com; 
> >>> Rick Jian-Zhi Chen(陳建志); pragnesh.pa...@openfive.com; Pragnesh Patel; 
> >>> Palmer Dabbelt; Sean Anderson; Claudiu Beznea; Simon Glass
> >>> Subject: [PATCH v2 2/2] riscv: timer: Add support for an early timer
> >>>
> >>> Added support for timer_early_get_count() and timer_early_get_rate()
> >>> This is mostly useful in tracing.
> >>>
> >>> Signed-off-by: Pragnesh Patel 
> >>> ---
> >>>
> >>> Changes in v2:
> >>> - make u-boot compile for qemu (include/configs/qemu-riscv.h)
> >>>
> >>>   drivers/timer/andes_plmt_timer.c   | 21 -
> >>>   drivers/timer/riscv_timer.c| 21 -
> >>>   drivers/timer/sifive_clint_timer.c | 21 -
> >>>   include/configs/ax25-ae350.h   |  5 +
> >>>   include/configs/qemu-riscv.h   |  5 +
> >>>   include/configs/sifive-fu540.h |  5 +
> >>>   6 files changed, 75 insertions(+), 3 deletions(-)
> >>
> >> Reviewed-by: Rick Chen 
> >
> > Please check about the CI failure item:
> > https://gitlab.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/196578
>
> 404 for me (though I suspect it's really a 403).

404 for me also.

>
> --Sean
>

[PATCH v2 2/2] riscv: timer: Add support for an early timer

[Pragnesh Patel]

Added support for timer_early_get_count() and timer_early_get_rate()
This is mostly useful in tracing.

Signed-off-by: Pragnesh Patel 
---

Changes in v2:
- make u-boot compile for qemu (include/configs/qemu-riscv.h)

 drivers/timer/andes_plmt_timer.c   | 21 -
 drivers/timer/riscv_timer.c| 21 -
 drivers/timer/sifive_clint_timer.c | 21 -
 include/configs/ax25-ae350.h   |  5 +
 include/configs/qemu-riscv.h   |  5 +
 include/configs/sifive-fu540.h |  5 +
 6 files changed, 75 insertions(+), 3 deletions(-)

diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c
index cec86718c7..74b795c97a 100644
--- a/drivers/timer/andes_plmt_timer.c
+++ b/drivers/timer/andes_plmt_timer.c
@@ -17,11 +17,30 @@
 /* mtime register */
 #define MTIME_REG(base)((ulong)(base))
 
-static u64 andes_plmt_get_count(struct udevice *dev)
+static u64 notrace andes_plmt_get_count(struct udevice *dev)
 {
return readq((void __iomem *)MTIME_REG(dev->priv));
 }
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ */
+unsigned long notrace timer_early_get_rate(void)
+{
+   return RISCV_MMODE_TIMER_FREQ;
+}
+
+/**
+ * timer_early_get_count() - Get the timer count before driver model
+ *
+ */
+u64 notrace timer_early_get_count(void)
+{
+   return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
+}
+#endif
+
 static const struct timer_ops andes_plmt_ops = {
.get_count = andes_plmt_get_count,
 };
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 21ae184057..a0f71ca897 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -16,7 +16,7 @@
 #include 
 #include 
 
-static u64 riscv_timer_get_count(struct udevice *dev)
+static u64 notrace riscv_timer_get_count(struct udevice *dev)
 {
__maybe_unused u32 hi, lo;
 
@@ -31,6 +31,25 @@ static u64 riscv_timer_get_count(struct udevice *dev)
return ((u64)hi << 32) | lo;
 }
 
+#if CONFIG_IS_ENABLED(RISCV_SMODE)
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ */
+unsigned long notrace timer_early_get_rate(void)
+{
+   return RISCV_SMODE_TIMER_FREQ;
+}
+
+/**
+ * timer_early_get_count() - Get the timer count before driver model
+ *
+ */
+u64 notrace timer_early_get_count(void)
+{
+   return riscv_timer_get_count(NULL);
+}
+#endif
+
 static int riscv_timer_probe(struct udevice *dev)
 {
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
diff --git a/drivers/timer/sifive_clint_timer.c 
b/drivers/timer/sifive_clint_timer.c
index 00ce0f08d6..9ae05a0e7e 100644
--- a/drivers/timer/sifive_clint_timer.c
+++ b/drivers/timer/sifive_clint_timer.c
@@ -14,11 +14,30 @@
 /* mtime register */
 #define MTIME_REG(base)((ulong)(base) + 0xbff8)
 
-static u64 sifive_clint_get_count(struct udevice *dev)
+static u64 notrace sifive_clint_get_count(struct udevice *dev)
 {
return readq((void __iomem *)MTIME_REG(dev->priv));
 }
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ */
+unsigned long notrace timer_early_get_rate(void)
+{
+   return RISCV_MMODE_TIMER_FREQ;
+}
+
+/**
+ * timer_early_get_count() - Get the timer count before driver model
+ *
+ */
+u64 notrace timer_early_get_count(void)
+{
+   return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
+}
+#endif
+
 static const struct timer_ops sifive_clint_ops = {
.get_count = sifive_clint_get_count,
 };
diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h
index b2606e794d..bd9c371f83 100644
--- a/include/configs/ax25-ae350.h
+++ b/include/configs/ax25-ae350.h
@@ -17,6 +17,11 @@
 #endif
 #endif
 
+#define RISCV_MMODE_TIMERBASE   0xe600
+#define RISCV_MMODE_TIMER_FREQ  6000
+
+#define RISCV_SMODE_TIMER_FREQ  6000
+
 /*
  * CPU and Board Configuration Options
  */
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index a2f33587c2..5291de83f8 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -29,6 +29,11 @@
 
 #define CONFIG_STANDALONE_LOAD_ADDR0x8020
 
+#define RISCV_MMODE_TIMERBASE  0x200
+#define RISCV_MMODE_TIMER_FREQ 100
+
+#define RISCV_SMODE_TIMER_FREQ 100
+
 /* Environment options */
 
 #ifndef CONFIG_SPL_BUILD
diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
index c1c79db147..0d69d1c548 100644
--- a/include/configs/sifive-fu540.h
+++ b/include/configs/sifive-fu540.h
@@ -36,6 +36,11 @@
 
 #define CONFIG_STANDALONE_LOAD_ADDR0x8020
 
+#define RISCV_MMODE_TIMERBASE  0x200
+#define RISCV_MMODE_TIMER_FREQ 100
+
+#define RISCV_SMODE_TIMER_FREQ 100
+
 /* Environment options */
 
 #ifndef CONF

[PATCH v2 1/2] trace: select TIMER_EARLY to avoid infinite recursion

[Pragnesh Patel]

When tracing functions is enabled this adds calls to
__cyg_profile_func_enter() and __cyg_profile_func_exit() to the traced
functions.

__cyg_profile_func_enter() and __cyg_profile_func_exit() invoke
timer_get_us() to record the entry and exit time.

initr_dm() will make gd->dm_root = NULL and gd->timer = NULL, so
timer_get_us() -> get_ticks() -> dm_timer_init() will lead to an
indefinite recursion.

So select TIMER_EARLY when tracing got enabled.

Signed-off-by: Pragnesh Patel 
---

Changes in v2:
- new patch

 lib/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/Kconfig b/lib/Kconfig
index 7673d2e4e0..671386963a 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -210,6 +210,7 @@ config BITREVERSE
 config TRACE
bool "Support for tracing of function calls and timing"
imply CMD_TRACE
+   select TIMER_EARLY
help
  Enables function tracing within U-Boot. This allows recording of call
  traces including timing information. The command can write data to
-- 
2.17.1

[PATCH v4] cmd: Add a pwm command

[Pragnesh Patel]

Add the command "pwm" for controlling the pwm channels. This
command provides pwm invert/config/enable/disable functionalities
via PWM uclass drivers

Signed-off-by: Pragnesh Patel 
Reviewed-by: Simon Glass 
---

Changes in v4:
- Add ut_assertok() for every run_command()

Changes in v3:
- Replace goto with return
- Print return value for error
- Change the assert condition for success

Changes in v2:
- Add test for pwm command

 README|   1 +
 cmd/Kconfig   |   6 ++
 cmd/Makefile  |   1 +
 cmd/pwm.c | 117 ++
 configs/sandbox_defconfig |   1 +
 test/cmd/Makefile |   1 +
 test/cmd/pwm.c|  47 +++
 7 files changed, 174 insertions(+)
 create mode 100644 cmd/pwm.c
 create mode 100644 test/cmd/pwm.c

diff --git a/README b/README
index cb49aa15da..dab291e0d0 100644
--- a/README
+++ b/README
@@ -3160,6 +3160,7 @@ i2c   - I2C sub-system
 sspi   - SPI utility commands
 base   - print or set address offset
 printenv- print environment variables
+pwm- control pwm channels
 setenv - set environment variables
 saveenv - save environment variables to persistent storage
 protect - enable or disable FLASH write protection
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 1595de999b..0d085108f4 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -918,6 +918,12 @@ config CMD_GPIO
help
  GPIO support.
 
+config CMD_PWM
+   bool "pwm"
+   depends on DM_PWM
+   help
+ Control PWM channels, this allows invert/config/enable/disable PWM 
channels.
+
 config CMD_GPT
bool "GPT (GUID Partition Table) command"
select EFI_PARTITION
diff --git a/cmd/Makefile b/cmd/Makefile
index dd86675bf2..75df3c136c 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -120,6 +120,7 @@ endif
 obj-$(CONFIG_CMD_PINMUX) += pinmux.o
 obj-$(CONFIG_CMD_PMC) += pmc.o
 obj-$(CONFIG_CMD_PSTORE) += pstore.o
+obj-$(CONFIG_CMD_PWM) += pwm.o
 obj-$(CONFIG_CMD_PXE) += pxe.o pxe_utils.o
 obj-$(CONFIG_CMD_WOL) += wol.o
 obj-$(CONFIG_CMD_QFW) += qfw.o
diff --git a/cmd/pwm.c b/cmd/pwm.c
new file mode 100644
index 00..5849fc57b6
--- /dev/null
+++ b/cmd/pwm.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Control PWM channels
+ *
+ * Copyright (c) 2020 SiFive, Inc
+ * author: Pragnesh Patel 
+ */
+
+#include 
+#include 
+#include 
+
+enum pwm_cmd {
+   PWM_SET_INVERT,
+   PWM_SET_CONFIG,
+   PWM_SET_ENABLE,
+   PWM_SET_DISABLE,
+};
+
+static int do_pwm(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+   const char *str_cmd, *str_channel = NULL, *str_enable = NULL;
+   const char *str_pwm = NULL, *str_period = NULL, *str_duty = NULL;
+   enum pwm_cmd sub_cmd;
+   struct udevice *dev;
+   u32 channel, pwm_enable, pwm_dev, period_ns = 0, duty_ns = 0;
+   int ret;
+
+   if (argc < 4)
+   return CMD_RET_USAGE;
+
+   str_cmd = argv[1];
+   argc -= 2;
+   argv += 2;
+
+   if (argc > 0) {
+   str_pwm = *argv;
+   argc--;
+   argv++;
+   }
+
+   if (!str_pwm)
+   return CMD_RET_USAGE;
+
+   switch (*str_cmd) {
+   case 'i':
+   sub_cmd = PWM_SET_INVERT;
+   break;
+   case 'c':
+   sub_cmd = PWM_SET_CONFIG;
+   break;
+   case 'e':
+   sub_cmd = PWM_SET_ENABLE;
+   break;
+   case 'd':
+   sub_cmd = PWM_SET_DISABLE;
+   break;
+   default:
+   return CMD_RET_USAGE;
+   }
+
+   pwm_dev = simple_strtoul(str_pwm, NULL, 10);
+   ret = uclass_get_device(UCLASS_PWM, pwm_dev, );
+   if (ret) {
+   printf("pwm: '%s' not found\n", str_pwm);
+   return cmd_process_error(cmdtp, ret);
+   }
+
+   if (argc > 0) {
+   str_channel = *argv;
+   channel = simple_strtoul(str_channel, NULL, 10);
+   argc--;
+   argv++;
+   } else {
+   return CMD_RET_USAGE;
+   }
+
+   if (sub_cmd == PWM_SET_INVERT && argc > 0) {
+   str_enable = *argv;
+   pwm_enable = simple_strtoul(str_enable, NULL, 10);
+   ret = pwm_set_invert(dev, channel, pwm_enable);
+   } else if (sub_cmd == PWM_SET_CONFIG && argc == 2) {
+   str_period = *argv;
+   argc--;
+   argv++;
+   period_ns = simple_strtoul(str_period, NULL, 10);
+
+   if (argc > 0) {
+   str_duty = *argv;
+   duty_ns = simple_strtoul(str_duty, NULL, 10);
+   }
+
+   ret = pwm_set_config(dev, channel, period_ns, duty_ns);
+   } else if (sub_cmd == PWM_SET_ENABLE) {
+   ret = pwm_set_enable(dev, channel, 1

RE: [PATCH] riscv: timer: Add support for an early timer

[Pragnesh Patel]

Hi Rick,

>-Original Message-
>From: Rick Chen 
>Sent: 10 December 2020 08:36
>To: Pragnesh Patel 
>Cc: Simon Glass ; U-Boot Mailing List b...@lists.denx.de>; Atish Patra ; Bin Meng
>; Paul Walmsley ( Sifive) ;
>Anup Patel ; Sagar Kadam
>; Palmer Dabbelt ; rick
>; Alan Kao ; Leo Liang
>
>Subject: Re: [PATCH] riscv: timer: Add support for an early timer
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh
>
>
>> Hi Rick,
>>
>> [...]
>> >>
>> >>Following are the configurations, steps and debug logs:
>> >>
>> >>+++ b/configs/ae350_rv64_defconfig
>> >>q+CONFIG_TRACE=y
>> >>+CONFIG_TRACE_BUFFER_SIZE=0x0100
>> >>+CONFIG_TRACE_CALL_DEPTH_LIMIT=15
>> >>+CONFIG_CMD_TRACE=y
>> >>+CONFIG_TIMER_EARLY=y
>> >>
>> >>+++ b/configs/ae350_rv64_spl_defconfig
>> >>+CONFIG_TRACE=y
>> >>+CONFIG_TRACE_BUFFER_SIZE=0x0100
>> >>+CONFIG_TRACE_CALL_DEPTH_LIMIT=15
>> >>+CONFIG_CMD_TRACE=y
>> >>+CONFIG_TIMER_EARLY=y
>> >>
>> >> case 1
>> >>///
>> >>ae350_rv64_defconfig with FTRACE=1, kernel booting is ok
>> >> case 1
>> >>///
>> >>make FTRACE=1 ae350_rv64_defconfig
>> >>make FTRACE=1
>> >>
>> >>///
>> [...]
>> >> case 2
>> >>///
>> >>ae350_rv64_spl_defconfig with FTRACE=1, kernel booting fail
>> >> case 2
>> >>///
>> >>make FTRACE=1 ae350_rv64_spl_defconfig make FTRACE=1
>> >>
>> >>///
>> >>///
>> >>/
>> [...]
>> >>(hang here)
>> >
>> >Thanks for the logs.
>> >
>> >From logs, I can't find where it got stuck. Can you please use gdb to
>> >see where it got stuck ?
>> >
>> >Meanwhile I will give it a try on HiFive Unleashed board.
>>
>> On HiFive Unleashed it works fine with tracing.
>>
>> U-Boot 2021.01-rc2-00049-gb2a38d1d0f (Dec 01 2020 - 15:04:41 +0530)
>> CPU:   rv64imafdc
>> Model: SiFive HiFive Unleashed A00
>> DRAM:  8 GiB
>> trace: enabled
>> MMC:   spi@1005:mmc@0: 0
>> Loading Environment from SPIFlash... SF: Detected is25wp256 with page
>> size 256 Bytes, erase size 4 KiB, total 32 MiB
>> *** Warning - bad CRC, using default environment
>> In:serial@1001
>> Out:   serial@1001
>> Err:   serial@1001
>> Net:   eth0: ethernet@1009
>> Hit any key to stop autoboot:  0
>> =>
>> => trace stats
>> 178,750 function sites
>>  25,359,991 function calls
>>   1 untracked function calls
>>   1,278,927 traced function calls (24358307 dropped due to overflow)
>>  19 maximum observed call depth
>>  15 call depth limit
>>  25,238,922 calls not traced due to depth => fatload mmc 0:3
>> 0x8600 hifive-unleashed-a00.dtb
>> 7199 bytes read in 27 ms (259.8 KiB/s) => fatload mmc 0:3 0x8400
>> uImage
>> 21421212 bytes read in 19496 ms (1 MiB/s) => bootm 0x8400 -
>> 0x8600 ## Booting kernel from Legacy Image at 8400 ...
>>Image Name:   Linux
>>Image Type:   RISC-V Linux Kernel Image (uncompressed)
>>Data Size:21421148 Bytes = 20.4 MiB
>>Load Address: 8020
>>Entry Point:  8020
>>Verifying Checksum ... OK
>> ## Flattened Device Tree blob at 8600
>>Booting using the fdt blob at 0x8600
>>Loading Kernel Image
>>Using Device Tree in place at 8600, end
>> 86004c1e Starting kernel ...(fake run for tracing) Starting
>> kernel ...
>> [0.00] OF: fdt: Ignoring memory range 0x8000 - 0x8020
>> [0.00] Linux version 5.8.0-rc3-16077-g9ebcfadb0610-dirty
>(pragneshp@sachinj2-OptiPlex-7010) (riscv64-unknown-linux-gnu-gcc (crosstool-
>NG 1.24.0.37-3f461da) 9.2.0,

RE: [RESEND,PATCH v3] cmd: Add a pwm command

[Pragnesh Patel]

Hi Simon,

>-Original Message-
>From: Simon Glass 
>Sent: 12 December 2020 21:05
>To: Pragnesh Patel 
>Cc: U-Boot Mailing List ; Atish Patra
>; Palmer Dabbelt ; Bin
>Meng ; Paul Walmsley ( Sifive)
>; Anup Patel ; Sagar Kadam
>; rick ; Naoki Hayama
>; Marek Vasut ;
>Patrick Delaunay ; Adam Ford
>; Thomas Hebb ; Ramon Fried
>; Heinrich Schuchardt ; Bin Meng
>; Sam Protsenko ; Miquel
>Raynal ; Frédéric Danis
>; Philippe Reynes
>; Patrice Chotard ;
>Baruch Siach ; Vladimir Olovyannikov
>
>Subject: Re: [RESEND,PATCH v3] cmd: Add a pwm command
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh,
>
>On Wed, 2 Dec 2020 at 21:59, Pragnesh Patel 
>wrote:
>>
>> Add the command "pwm" for controlling the pwm channels. This command
>> provides pwm invert/config/enable/disable functionalities via PWM
>> uclass drivers
>>
>> Signed-off-by: Pragnesh Patel 
>> Reviewed-by: Simon Glass 
>> ---
>>
>> Changes in v3:
>> - Replace goto with return
>> - Print return value for error
>> - Change the assert condition for success
>>
>> Changes in v2:
>> - Add test for pwm command
>>
>>  README|   1 +
>>  cmd/Kconfig   |   6 ++
>>  cmd/Makefile  |   1 +
>>  cmd/pwm.c | 117 ++
>>  configs/sandbox_defconfig |   1 +
>>  test/cmd/Makefile |   1 +
>>  test/cmd/pwm.c|  47 +++
>>  7 files changed, 174 insertions(+)
>>  create mode 100644 cmd/pwm.c
>>  create mode 100644 test/cmd/pwm.c
>>
>> diff --git a/README b/README
>> index cb49aa15da..dab291e0d0 100644
>> --- a/README
>> +++ b/README
>> @@ -3160,6 +3160,7 @@ i2c   - I2C sub-system
>>  sspi   - SPI utility commands
>>  base   - print or set address offset
>>  printenv- print environment variables
>> +pwm- control pwm channels
>>  setenv - set environment variables
>>  saveenv - save environment variables to persistent storage  protect -
>> enable or disable FLASH write protection diff --git a/cmd/Kconfig
>> b/cmd/Kconfig index 1595de999b..0d085108f4 100644
>> --- a/cmd/Kconfig
>> +++ b/cmd/Kconfig
>> @@ -918,6 +918,12 @@ config CMD_GPIO
>> help
>>   GPIO support.
>>
>> +config CMD_PWM
>> +   bool "pwm"
>> +   depends on DM_PWM
>> +   help
>> + Control PWM channels, this allows invert/config/enable/disable PWM
>channels.
>> +
>>  config CMD_GPT
>> bool "GPT (GUID Partition Table) command"
>> select EFI_PARTITION
>> diff --git a/cmd/Makefile b/cmd/Makefile index dd86675bf2..75df3c136c
>> 100644
>> --- a/cmd/Makefile
>> +++ b/cmd/Makefile
>> @@ -120,6 +120,7 @@ endif
>>  obj-$(CONFIG_CMD_PINMUX) += pinmux.o
>>  obj-$(CONFIG_CMD_PMC) += pmc.o
>>  obj-$(CONFIG_CMD_PSTORE) += pstore.o
>> +obj-$(CONFIG_CMD_PWM) += pwm.o
>>  obj-$(CONFIG_CMD_PXE) += pxe.o pxe_utils.o
>>  obj-$(CONFIG_CMD_WOL) += wol.o
>>  obj-$(CONFIG_CMD_QFW) += qfw.o
>> diff --git a/cmd/pwm.c b/cmd/pwm.c
>> new file mode 100644
>> index 00..5849fc57b6
>> --- /dev/null
>> +++ b/cmd/pwm.c
>> @@ -0,0 +1,117 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Control PWM channels
>> + *
>> + * Copyright (c) 2020 SiFive, Inc
>> + * author: Pragnesh Patel   */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +
>> +enum pwm_cmd {
>> +   PWM_SET_INVERT,
>> +   PWM_SET_CONFIG,
>> +   PWM_SET_ENABLE,
>> +   PWM_SET_DISABLE,
>> +};
>> +
>> +static int do_pwm(struct cmd_tbl *cmdtp, int flag, int argc,
>> + char *const argv[])
>> +{
>> +   const char *str_cmd, *str_channel = NULL, *str_enable = NULL;
>> +   const char *str_pwm = NULL, *str_period = NULL, *str_duty = NULL;
>> +   enum pwm_cmd sub_cmd;
>> +   struct udevice *dev;
>> +   u32 channel, pwm_enable, pwm_dev, period_ns = 0, duty_ns = 0;
>> +   int ret;
>> +
>> +   if (argc < 4)
>> +   return CMD_RET_USAGE;
>> +
>> +   str_cmd = argv[1];
>> +   argc -= 2;
>> +   argv += 2;
>> +
>> +   if (argc > 0) {
>> +   str_pwm = *argv;
>> +   argc--;
>> +   argv++;
>> +   }

[RESEND,PATCH v3] cmd: Add a pwm command

[Pragnesh Patel]

Add the command "pwm" for controlling the pwm channels. This
command provides pwm invert/config/enable/disable functionalities
via PWM uclass drivers

Signed-off-by: Pragnesh Patel 
Reviewed-by: Simon Glass 
---

Changes in v3:
- Replace goto with return
- Print return value for error
- Change the assert condition for success

Changes in v2:
- Add test for pwm command

 README|   1 +
 cmd/Kconfig   |   6 ++
 cmd/Makefile  |   1 +
 cmd/pwm.c | 117 ++
 configs/sandbox_defconfig |   1 +
 test/cmd/Makefile |   1 +
 test/cmd/pwm.c|  47 +++
 7 files changed, 174 insertions(+)
 create mode 100644 cmd/pwm.c
 create mode 100644 test/cmd/pwm.c

diff --git a/README b/README
index cb49aa15da..dab291e0d0 100644
--- a/README
+++ b/README
@@ -3160,6 +3160,7 @@ i2c   - I2C sub-system
 sspi   - SPI utility commands
 base   - print or set address offset
 printenv- print environment variables
+pwm- control pwm channels
 setenv - set environment variables
 saveenv - save environment variables to persistent storage
 protect - enable or disable FLASH write protection
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 1595de999b..0d085108f4 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -918,6 +918,12 @@ config CMD_GPIO
help
  GPIO support.
 
+config CMD_PWM
+   bool "pwm"
+   depends on DM_PWM
+   help
+ Control PWM channels, this allows invert/config/enable/disable PWM 
channels.
+
 config CMD_GPT
bool "GPT (GUID Partition Table) command"
select EFI_PARTITION
diff --git a/cmd/Makefile b/cmd/Makefile
index dd86675bf2..75df3c136c 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -120,6 +120,7 @@ endif
 obj-$(CONFIG_CMD_PINMUX) += pinmux.o
 obj-$(CONFIG_CMD_PMC) += pmc.o
 obj-$(CONFIG_CMD_PSTORE) += pstore.o
+obj-$(CONFIG_CMD_PWM) += pwm.o
 obj-$(CONFIG_CMD_PXE) += pxe.o pxe_utils.o
 obj-$(CONFIG_CMD_WOL) += wol.o
 obj-$(CONFIG_CMD_QFW) += qfw.o
diff --git a/cmd/pwm.c b/cmd/pwm.c
new file mode 100644
index 00..5849fc57b6
--- /dev/null
+++ b/cmd/pwm.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Control PWM channels
+ *
+ * Copyright (c) 2020 SiFive, Inc
+ * author: Pragnesh Patel 
+ */
+
+#include 
+#include 
+#include 
+
+enum pwm_cmd {
+   PWM_SET_INVERT,
+   PWM_SET_CONFIG,
+   PWM_SET_ENABLE,
+   PWM_SET_DISABLE,
+};
+
+static int do_pwm(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+   const char *str_cmd, *str_channel = NULL, *str_enable = NULL;
+   const char *str_pwm = NULL, *str_period = NULL, *str_duty = NULL;
+   enum pwm_cmd sub_cmd;
+   struct udevice *dev;
+   u32 channel, pwm_enable, pwm_dev, period_ns = 0, duty_ns = 0;
+   int ret;
+
+   if (argc < 4)
+   return CMD_RET_USAGE;
+
+   str_cmd = argv[1];
+   argc -= 2;
+   argv += 2;
+
+   if (argc > 0) {
+   str_pwm = *argv;
+   argc--;
+   argv++;
+   }
+
+   if (!str_pwm)
+   return CMD_RET_USAGE;
+
+   switch (*str_cmd) {
+   case 'i':
+   sub_cmd = PWM_SET_INVERT;
+   break;
+   case 'c':
+   sub_cmd = PWM_SET_CONFIG;
+   break;
+   case 'e':
+   sub_cmd = PWM_SET_ENABLE;
+   break;
+   case 'd':
+   sub_cmd = PWM_SET_DISABLE;
+   break;
+   default:
+   return CMD_RET_USAGE;
+   }
+
+   pwm_dev = simple_strtoul(str_pwm, NULL, 10);
+   ret = uclass_get_device(UCLASS_PWM, pwm_dev, );
+   if (ret) {
+   printf("pwm: '%s' not found\n", str_pwm);
+   return cmd_process_error(cmdtp, ret);
+   }
+
+   if (argc > 0) {
+   str_channel = *argv;
+   channel = simple_strtoul(str_channel, NULL, 10);
+   argc--;
+   argv++;
+   } else {
+   return CMD_RET_USAGE;
+   }
+
+   if (sub_cmd == PWM_SET_INVERT && argc > 0) {
+   str_enable = *argv;
+   pwm_enable = simple_strtoul(str_enable, NULL, 10);
+   ret = pwm_set_invert(dev, channel, pwm_enable);
+   } else if (sub_cmd == PWM_SET_CONFIG && argc == 2) {
+   str_period = *argv;
+   argc--;
+   argv++;
+   period_ns = simple_strtoul(str_period, NULL, 10);
+
+   if (argc > 0) {
+   str_duty = *argv;
+   duty_ns = simple_strtoul(str_duty, NULL, 10);
+   }
+
+   ret = pwm_set_config(dev, channel, period_ns, duty_ns);
+   } else if (sub_cmd == PWM_SET_ENABLE) {
+   ret = pwm_set_enable(dev, channel, 1);
+   } else if (sub_cmd == PWM_SET_DISABLE) 

RE: [PATCH v3] cmd: Add a pwm command

[Pragnesh Patel]

Forgot to add "Reviewed-by: Simon Glass " tag, will resend 
this patch.

>-Original Message-
>From: Pragnesh Patel 
>Sent: 03 December 2020 10:21
>To: u-boot@lists.denx.de
>Cc: atish.pa...@wdc.com; palmerdabb...@google.com; bmeng...@gmail.com;
>Paul Walmsley ( Sifive) ; anup.pa...@wdc.com;
>Sagar Kadam ; r...@andestech.com; Pragnesh
>Patel ; Simon Glass ; Naoki
>Hayama ; Marek Vasut
>; Patrick Delaunay
>; Adam Ford ; Thomas Hebb
>; Ramon Fried ; Heinrich
>Schuchardt ; Bin Meng ; Sam
>Protsenko ; Miquel Raynal ;
>Philippe Reynes ; Frédéric Danis
>; Patrice Chotard ;
>Baruch Siach 
>Subject: [PATCH v3] cmd: Add a pwm command
>
>Add the command "pwm" for controlling the pwm channels. This command
>provides pwm invert/config/enable/disable functionalities via PWM uclass
>drivers
>
>Signed-off-by: Pragnesh Patel 
>---
>
>Changes in v3:
>- Replace goto with return
>- Print return value for error
>- Change the assert condition for success
>
>Changes in v2:
>- Add test for pwm command
>
> README|   1 +
> cmd/Kconfig   |   6 ++
> cmd/Makefile  |   1 +
> cmd/pwm.c | 117 ++
> configs/sandbox_defconfig |   1 +
> test/cmd/Makefile |   1 +
> test/cmd/pwm.c|  47 +++
> 7 files changed, 174 insertions(+)
> create mode 100644 cmd/pwm.c
> create mode 100644 test/cmd/pwm.c
>
>diff --git a/README b/README
>index cb49aa15da..dab291e0d0 100644
>--- a/README
>+++ b/README
>@@ -3160,6 +3160,7 @@ i2c  - I2C sub-system
> sspi  - SPI utility commands
> base  - print or set address offset
> printenv- print environment variables
>+pwm   - control pwm channels
> setenv- set environment variables
> saveenv - save environment variables to persistent storage  protect - enable 
> or
>disable FLASH write protection diff --git a/cmd/Kconfig b/cmd/Kconfig index
>1595de999b..0d085108f4 100644
>--- a/cmd/Kconfig
>+++ b/cmd/Kconfig
>@@ -918,6 +918,12 @@ config CMD_GPIO
>   help
> GPIO support.
>
>+config CMD_PWM
>+  bool "pwm"
>+  depends on DM_PWM
>+  help
>+Control PWM channels, this allows invert/config/enable/disable PWM
>channels.
>+
> config CMD_GPT
>   bool "GPT (GUID Partition Table) command"
>   select EFI_PARTITION
>diff --git a/cmd/Makefile b/cmd/Makefile index dd86675bf2..75df3c136c
>100644
>--- a/cmd/Makefile
>+++ b/cmd/Makefile
>@@ -120,6 +120,7 @@ endif
> obj-$(CONFIG_CMD_PINMUX) += pinmux.o
> obj-$(CONFIG_CMD_PMC) += pmc.o
> obj-$(CONFIG_CMD_PSTORE) += pstore.o
>+obj-$(CONFIG_CMD_PWM) += pwm.o
> obj-$(CONFIG_CMD_PXE) += pxe.o pxe_utils.o
> obj-$(CONFIG_CMD_WOL) += wol.o
> obj-$(CONFIG_CMD_QFW) += qfw.o
>diff --git a/cmd/pwm.c b/cmd/pwm.c
>new file mode 100644
>index 00..5849fc57b6
>--- /dev/null
>+++ b/cmd/pwm.c
>@@ -0,0 +1,117 @@
>+// SPDX-License-Identifier: GPL-2.0+
>+/*
>+ * Control PWM channels
>+ *
>+ * Copyright (c) 2020 SiFive, Inc
>+ * author: Pragnesh Patel   */
>+
>+#include 
>+#include 
>+#include 
>+
>+enum pwm_cmd {
>+  PWM_SET_INVERT,
>+  PWM_SET_CONFIG,
>+  PWM_SET_ENABLE,
>+  PWM_SET_DISABLE,
>+};
>+
>+static int do_pwm(struct cmd_tbl *cmdtp, int flag, int argc,
>+char *const argv[])
>+{
>+  const char *str_cmd, *str_channel = NULL, *str_enable = NULL;
>+  const char *str_pwm = NULL, *str_period = NULL, *str_duty = NULL;
>+  enum pwm_cmd sub_cmd;
>+  struct udevice *dev;
>+  u32 channel, pwm_enable, pwm_dev, period_ns = 0, duty_ns = 0;
>+  int ret;
>+
>+  if (argc < 4)
>+  return CMD_RET_USAGE;
>+
>+  str_cmd = argv[1];
>+  argc -= 2;
>+  argv += 2;
>+
>+  if (argc > 0) {
>+  str_pwm = *argv;
>+  argc--;
>+  argv++;
>+  }
>+
>+  if (!str_pwm)
>+  return CMD_RET_USAGE;
>+
>+  switch (*str_cmd) {
>+  case 'i':
>+  sub_cmd = PWM_SET_INVERT;
>+  break;
>+  case 'c':
>+  sub_cmd = PWM_SET_CONFIG;
>+  break;
>+  case 'e':
>+  sub_cmd = PWM_SET_ENABLE;
>+  break;
>+  case 'd':
>+  sub_cmd = PWM_SET_DISABLE;
>+  break;
>+  default:
>+  return CMD_RET_USAGE;
>+  }
>+
>+  pwm_dev = simple_strtoul(str_pwm, NULL, 10);
>+  ret = uclass_get_device(UCLASS_PWM, pwm_dev, );
>+  if (ret) {
>+  printf("pwm: '%s' not found\n&q

[PATCH v3] cmd: Add a pwm command

[Pragnesh Patel]

Add the command "pwm" for controlling the pwm channels. This
command provides pwm invert/config/enable/disable functionalities
via PWM uclass drivers

Signed-off-by: Pragnesh Patel 
---

Changes in v3:
- Replace goto with return
- Print return value for error
- Change the assert condition for success

Changes in v2:
- Add test for pwm command

 README|   1 +
 cmd/Kconfig   |   6 ++
 cmd/Makefile  |   1 +
 cmd/pwm.c | 117 ++
 configs/sandbox_defconfig |   1 +
 test/cmd/Makefile |   1 +
 test/cmd/pwm.c|  47 +++
 7 files changed, 174 insertions(+)
 create mode 100644 cmd/pwm.c
 create mode 100644 test/cmd/pwm.c

diff --git a/README b/README
index cb49aa15da..dab291e0d0 100644
--- a/README
+++ b/README
@@ -3160,6 +3160,7 @@ i2c   - I2C sub-system
 sspi   - SPI utility commands
 base   - print or set address offset
 printenv- print environment variables
+pwm- control pwm channels
 setenv - set environment variables
 saveenv - save environment variables to persistent storage
 protect - enable or disable FLASH write protection
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 1595de999b..0d085108f4 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -918,6 +918,12 @@ config CMD_GPIO
help
  GPIO support.
 
+config CMD_PWM
+   bool "pwm"
+   depends on DM_PWM
+   help
+ Control PWM channels, this allows invert/config/enable/disable PWM 
channels.
+
 config CMD_GPT
bool "GPT (GUID Partition Table) command"
select EFI_PARTITION
diff --git a/cmd/Makefile b/cmd/Makefile
index dd86675bf2..75df3c136c 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -120,6 +120,7 @@ endif
 obj-$(CONFIG_CMD_PINMUX) += pinmux.o
 obj-$(CONFIG_CMD_PMC) += pmc.o
 obj-$(CONFIG_CMD_PSTORE) += pstore.o
+obj-$(CONFIG_CMD_PWM) += pwm.o
 obj-$(CONFIG_CMD_PXE) += pxe.o pxe_utils.o
 obj-$(CONFIG_CMD_WOL) += wol.o
 obj-$(CONFIG_CMD_QFW) += qfw.o
diff --git a/cmd/pwm.c b/cmd/pwm.c
new file mode 100644
index 00..5849fc57b6
--- /dev/null
+++ b/cmd/pwm.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Control PWM channels
+ *
+ * Copyright (c) 2020 SiFive, Inc
+ * author: Pragnesh Patel 
+ */
+
+#include 
+#include 
+#include 
+
+enum pwm_cmd {
+   PWM_SET_INVERT,
+   PWM_SET_CONFIG,
+   PWM_SET_ENABLE,
+   PWM_SET_DISABLE,
+};
+
+static int do_pwm(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+   const char *str_cmd, *str_channel = NULL, *str_enable = NULL;
+   const char *str_pwm = NULL, *str_period = NULL, *str_duty = NULL;
+   enum pwm_cmd sub_cmd;
+   struct udevice *dev;
+   u32 channel, pwm_enable, pwm_dev, period_ns = 0, duty_ns = 0;
+   int ret;
+
+   if (argc < 4)
+   return CMD_RET_USAGE;
+
+   str_cmd = argv[1];
+   argc -= 2;
+   argv += 2;
+
+   if (argc > 0) {
+   str_pwm = *argv;
+   argc--;
+   argv++;
+   }
+
+   if (!str_pwm)
+   return CMD_RET_USAGE;
+
+   switch (*str_cmd) {
+   case 'i':
+   sub_cmd = PWM_SET_INVERT;
+   break;
+   case 'c':
+   sub_cmd = PWM_SET_CONFIG;
+   break;
+   case 'e':
+   sub_cmd = PWM_SET_ENABLE;
+   break;
+   case 'd':
+   sub_cmd = PWM_SET_DISABLE;
+   break;
+   default:
+   return CMD_RET_USAGE;
+   }
+
+   pwm_dev = simple_strtoul(str_pwm, NULL, 10);
+   ret = uclass_get_device(UCLASS_PWM, pwm_dev, );
+   if (ret) {
+   printf("pwm: '%s' not found\n", str_pwm);
+   return cmd_process_error(cmdtp, ret);
+   }
+
+   if (argc > 0) {
+   str_channel = *argv;
+   channel = simple_strtoul(str_channel, NULL, 10);
+   argc--;
+   argv++;
+   } else {
+   return CMD_RET_USAGE;
+   }
+
+   if (sub_cmd == PWM_SET_INVERT && argc > 0) {
+   str_enable = *argv;
+   pwm_enable = simple_strtoul(str_enable, NULL, 10);
+   ret = pwm_set_invert(dev, channel, pwm_enable);
+   } else if (sub_cmd == PWM_SET_CONFIG && argc == 2) {
+   str_period = *argv;
+   argc--;
+   argv++;
+   period_ns = simple_strtoul(str_period, NULL, 10);
+
+   if (argc > 0) {
+   str_duty = *argv;
+   duty_ns = simple_strtoul(str_duty, NULL, 10);
+   }
+
+   ret = pwm_set_config(dev, channel, period_ns, duty_ns);
+   } else if (sub_cmd == PWM_SET_ENABLE) {
+   ret = pwm_set_enable(dev, channel, 1);
+   } else if (sub_cmd == PWM_SET_DISABLE) {
+   ret = pwm_set_enable(dev, chan

RE: [PATCH] riscv: timer: Add support for an early timer

[Pragnesh Patel]

Hi Rick,

[...]
>>
>>Following are the configurations, steps and debug logs:
>>
>>+++ b/configs/ae350_rv64_defconfig
>>q+CONFIG_TRACE=y
>>+CONFIG_TRACE_BUFFER_SIZE=0x0100
>>+CONFIG_TRACE_CALL_DEPTH_LIMIT=15
>>+CONFIG_CMD_TRACE=y
>>+CONFIG_TIMER_EARLY=y
>>
>>+++ b/configs/ae350_rv64_spl_defconfig
>>+CONFIG_TRACE=y
>>+CONFIG_TRACE_BUFFER_SIZE=0x0100
>>+CONFIG_TRACE_CALL_DEPTH_LIMIT=15
>>+CONFIG_CMD_TRACE=y
>>+CONFIG_TIMER_EARLY=y
>>
>> case 1
>>///
>>ae350_rv64_defconfig with FTRACE=1, kernel booting is ok
>> case 1
>>///
>>make FTRACE=1 ae350_rv64_defconfig
>>make FTRACE=1
>>///
[...]
>> case 2
>>///
>>ae350_rv64_spl_defconfig with FTRACE=1, kernel booting fail
>> case 2
>>///
>>make FTRACE=1 ae350_rv64_spl_defconfig
>>make FTRACE=1
>>///
>>///
>>/
[...]
>>(hang here)
>
>Thanks for the logs.
>
>From logs, I can't find where it got stuck. Can you please use gdb to see 
>where it
>got stuck ?
>
>Meanwhile I will give it a try on HiFive Unleashed board.

On HiFive Unleashed it works fine with tracing.

U-Boot 2021.01-rc2-00049-gb2a38d1d0f (Dec 01 2020 - 15:04:41 +0530)
CPU:   rv64imafdc
Model: SiFive HiFive Unleashed A00
DRAM:  8 GiB
trace: enabled
MMC:   spi@1005:mmc@0: 0
Loading Environment from SPIFlash... SF: Detected is25wp256 with page size 256 
Bytes, erase size 4 KiB, total 32 MiB
*** Warning - bad CRC, using default environment
In:serial@1001
Out:   serial@1001
Err:   serial@1001
Net:   eth0: ethernet@1009
Hit any key to stop autoboot:  0
=>
=> trace stats
178,750 function sites
 25,359,991 function calls
  1 untracked function calls
  1,278,927 traced function calls (24358307 dropped due to overflow)
 19 maximum observed call depth
 15 call depth limit
 25,238,922 calls not traced due to depth
=> fatload mmc 0:3 0x8600 hifive-unleashed-a00.dtb
7199 bytes read in 27 ms (259.8 KiB/s)
=> fatload mmc 0:3 0x8400 uImage
21421212 bytes read in 19496 ms (1 MiB/s)
=> bootm 0x8400 - 0x8600
## Booting kernel from Legacy Image at 8400 ...
   Image Name:   Linux
   Image Type:   RISC-V Linux Kernel Image (uncompressed)
   Data Size:21421148 Bytes = 20.4 MiB
   Load Address: 8020
   Entry Point:  8020
   Verifying Checksum ... OK
## Flattened Device Tree blob at 8600
   Booting using the fdt blob at 0x8600
   Loading Kernel Image
   Using Device Tree in place at 8600, end 86004c1e
Starting kernel ...(fake run for tracing)
Starting kernel ...
[0.00] OF: fdt: Ignoring memory range 0x8000 - 0x8020
[0.00] Linux version 5.8.0-rc3-16077-g9ebcfadb0610-dirty 
(pragneshp@sachinj2-OptiPlex-7010) (riscv64-unknown-linux-gnu-gcc (crosstool-NG 
1.24.0.37-3f461da) 9.2.0, GNU ld (crosstool-NG 1.24.0.37-3f461da) 2.32) #34 SMP 
Tue Jul 21 15:56:29 IST 2020
[0.00] initrd not found or empty - disabling initrd
[0.00] Zone ranges:
[0.00]   DMA32[mem 0x8020-0x]
[0.00]   Normal   [mem 0x0001-0x00027fff]
[0.00] Movable zone start for each node
[0.00] Early memory node ranges
[0.00]   node   0: [mem 0x8020-0x00027fff]
[0.00] Initmem setup node 0 [mem 0x8020-0x00027fff]

Welcome to Buildroot
buildroot login: root
Password:


>
>>
>> case 3
>>///
>>ae350_rv64_spl_defconfig without FTRACE=1, kernel booting ok
>> case 2
>>///
>>make ae350_rv64_spl_defconfig
>>make
>>///

RE: [PATCH v2] cmd: Add a pwm command

[Pragnesh Patel]

Hi Simon,

>-Original Message-
>From: U-Boot  On Behalf Of Pragnesh Patel
>Sent: 01 December 2020 11:17
>To: Simon Glass 
>Cc: U-Boot Mailing List ; Atish Patra
>; Palmer Dabbelt ; Bin
>Meng ; Paul Walmsley ( Sifive)
>; Anup Patel ; Sagar Kadam
>; rick ; Naoki Hayama
>; Marek Vasut ;
>Patrick Delaunay ; Adam Ford
>; Thomas Hebb ; Ramon Fried
>; Heinrich Schuchardt ; Bin Meng
>; Sam Protsenko ; Miquel
>Raynal ; Philippe Reynes
>; Frédéric Danis
>; Patrice Chotard ;
>Vladimir Olovyannikov 
>Subject: RE: [PATCH v2] cmd: Add a pwm command
>
>Hi Simon,
>
>>-Original Message-
>>From: Simon Glass 
>>Sent: 01 December 2020 01:42
>>To: Pragnesh Patel 
>>Cc: U-Boot Mailing List ; Atish Patra
>>; Palmer Dabbelt ; Bin
>>Meng ; Paul Walmsley ( Sifive)
>>; Anup Patel ; Sagar
>>Kadam ; rick ; Naoki
>>Hayama ; Marek Vasut
>>; Patrick Delaunay
>>; Adam Ford ; Thomas Hebb
>>; Ramon Fried ; Heinrich
>>Schuchardt ; Bin Meng ;
>Sam
>>Protsenko ; Miquel Raynal
>>; Philippe Reynes
>>; Frédéric Danis
>>; Patrice Chotard
>>; Vladimir Olovyannikov
>>
>>Subject: Re: [PATCH v2] cmd: Add a pwm command
>>
>>[External Email] Do not click links or attachments unless you recognize
>>the sender and know the content is safe
>>
>>Hi Pragnesh,
>>
>>On Thu, 26 Nov 2020 at 03:48, Pragnesh Patel
>>
>>wrote:
>>>
>>> Add the command "pwm" for controlling the pwm channels. This command
>>> provides pwm invert/config/enable/disable functionalities via PWM
>>> uclass drivers
>>>
>>> Signed-off-by: Pragnesh Patel 
>>> ---
>>>
>>> Changes in v2:
>>> - Add test for pwm command
>>>
>>>
>>>  README|   1 +
>>>  cmd/Kconfig   |   6 ++
>>>  cmd/Makefile  |   1 +
>>>  cmd/pwm.c | 120 ++
>>>  configs/sandbox_defconfig |   1 +
>>>  test/cmd/Makefile |   1 +
>>>  test/cmd/pwm.c|  54 +
>>>  7 files changed, 184 insertions(+)
>>>  create mode 100644 cmd/pwm.c
>>>  create mode 100644 test/cmd/pwm.c
>>
>>Reviewed-by: Simon Glass 
>>
>>Minor nits below
>>
>>>
>>> diff --git a/README b/README
>>> index cb49aa15da..dab291e0d0 100644
>>> --- a/README
>>> +++ b/README
>>> @@ -3160,6 +3160,7 @@ i2c   - I2C sub-system
>>>  sspi   - SPI utility commands
>>>  base   - print or set address offset
>>>  printenv- print environment variables
>>> +pwm- control pwm channels
>>>  setenv - set environment variables
>>>  saveenv - save environment variables to persistent storage  protect
>>> - enable or disable FLASH write protection diff --git a/cmd/Kconfig
>>> b/cmd/Kconfig index 1595de999b..0d085108f4 100644
>>> --- a/cmd/Kconfig
>>> +++ b/cmd/Kconfig
>>> @@ -918,6 +918,12 @@ config CMD_GPIO
>>> help
>>>   GPIO support.
>>>
>>> +config CMD_PWM
>>> +   bool "pwm"
>>> +   depends on DM_PWM
>>> +   help
>>> + Control PWM channels, this allows
>>> +invert/config/enable/disable PWM
>>channels.
>>> +
>>>  config CMD_GPT
>>> bool "GPT (GUID Partition Table) command"
>>> select EFI_PARTITION
>>> diff --git a/cmd/Makefile b/cmd/Makefile index dd86675bf2..75df3c136c
>>> 100644
>>> --- a/cmd/Makefile
>>> +++ b/cmd/Makefile
>>> @@ -120,6 +120,7 @@ endif
>>>  obj-$(CONFIG_CMD_PINMUX) += pinmux.o
>>>  obj-$(CONFIG_CMD_PMC) += pmc.o
>>>  obj-$(CONFIG_CMD_PSTORE) += pstore.o
>>> +obj-$(CONFIG_CMD_PWM) += pwm.o
>>>  obj-$(CONFIG_CMD_PXE) += pxe.o pxe_utils.o
>>>  obj-$(CONFIG_CMD_WOL) += wol.o
>>>  obj-$(CONFIG_CMD_QFW) += qfw.o
>>> diff --git a/cmd/pwm.c b/cmd/pwm.c
>>> new file mode 100644
>>> index 00..f704c7a755
>>> --- /dev/null
>>> +++ b/cmd/pwm.c
>>> @@ -0,0 +1,120 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/*
>>> + * Control PWM channels
>>> + *
>>> + * Copyright (c) 2020 SiFive, Inc
>>> + * author: Pragnesh Patel   */
>>> +
>>> +#include 
>>> +#include 
>>> +#include 
>>> +
>>> +enum pwm_cmd {
>>> +   PWM_SET_INVERT

RE: [PATCH v2] cmd: Add a pwm command

[Pragnesh Patel]

Hi Simon,

>-Original Message-
>From: Simon Glass 
>Sent: 01 December 2020 01:42
>To: Pragnesh Patel 
>Cc: U-Boot Mailing List ; Atish Patra
>; Palmer Dabbelt ; Bin
>Meng ; Paul Walmsley ( Sifive)
>; Anup Patel ; Sagar Kadam
>; rick ; Naoki Hayama
>; Marek Vasut ;
>Patrick Delaunay ; Adam Ford
>; Thomas Hebb ; Ramon Fried
>; Heinrich Schuchardt ; Bin Meng
>; Sam Protsenko ; Miquel
>Raynal ; Philippe Reynes
>; Frédéric Danis
>; Patrice Chotard ;
>Vladimir Olovyannikov 
>Subject: Re: [PATCH v2] cmd: Add a pwm command
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh,
>
>On Thu, 26 Nov 2020 at 03:48, Pragnesh Patel 
>wrote:
>>
>> Add the command "pwm" for controlling the pwm channels. This command
>> provides pwm invert/config/enable/disable functionalities via PWM
>> uclass drivers
>>
>> Signed-off-by: Pragnesh Patel 
>> ---
>>
>> Changes in v2:
>> - Add test for pwm command
>>
>>
>>  README|   1 +
>>  cmd/Kconfig   |   6 ++
>>  cmd/Makefile  |   1 +
>>  cmd/pwm.c | 120 ++
>>  configs/sandbox_defconfig |   1 +
>>  test/cmd/Makefile |   1 +
>>  test/cmd/pwm.c|  54 +
>>  7 files changed, 184 insertions(+)
>>  create mode 100644 cmd/pwm.c
>>  create mode 100644 test/cmd/pwm.c
>
>Reviewed-by: Simon Glass 
>
>Minor nits below
>
>>
>> diff --git a/README b/README
>> index cb49aa15da..dab291e0d0 100644
>> --- a/README
>> +++ b/README
>> @@ -3160,6 +3160,7 @@ i2c   - I2C sub-system
>>  sspi   - SPI utility commands
>>  base   - print or set address offset
>>  printenv- print environment variables
>> +pwm- control pwm channels
>>  setenv - set environment variables
>>  saveenv - save environment variables to persistent storage  protect -
>> enable or disable FLASH write protection diff --git a/cmd/Kconfig
>> b/cmd/Kconfig index 1595de999b..0d085108f4 100644
>> --- a/cmd/Kconfig
>> +++ b/cmd/Kconfig
>> @@ -918,6 +918,12 @@ config CMD_GPIO
>> help
>>   GPIO support.
>>
>> +config CMD_PWM
>> +   bool "pwm"
>> +   depends on DM_PWM
>> +   help
>> + Control PWM channels, this allows invert/config/enable/disable PWM
>channels.
>> +
>>  config CMD_GPT
>> bool "GPT (GUID Partition Table) command"
>> select EFI_PARTITION
>> diff --git a/cmd/Makefile b/cmd/Makefile index dd86675bf2..75df3c136c
>> 100644
>> --- a/cmd/Makefile
>> +++ b/cmd/Makefile
>> @@ -120,6 +120,7 @@ endif
>>  obj-$(CONFIG_CMD_PINMUX) += pinmux.o
>>  obj-$(CONFIG_CMD_PMC) += pmc.o
>>  obj-$(CONFIG_CMD_PSTORE) += pstore.o
>> +obj-$(CONFIG_CMD_PWM) += pwm.o
>>  obj-$(CONFIG_CMD_PXE) += pxe.o pxe_utils.o
>>  obj-$(CONFIG_CMD_WOL) += wol.o
>>  obj-$(CONFIG_CMD_QFW) += qfw.o
>> diff --git a/cmd/pwm.c b/cmd/pwm.c
>> new file mode 100644
>> index 00..f704c7a755
>> --- /dev/null
>> +++ b/cmd/pwm.c
>> @@ -0,0 +1,120 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Control PWM channels
>> + *
>> + * Copyright (c) 2020 SiFive, Inc
>> + * author: Pragnesh Patel   */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +
>> +enum pwm_cmd {
>> +   PWM_SET_INVERT,
>> +   PWM_SET_CONFIG,
>> +   PWM_SET_ENABLE,
>> +   PWM_SET_DISABLE,
>> +};
>> +
>> +static int do_pwm(struct cmd_tbl *cmdtp, int flag, int argc,
>> + char *const argv[])
>> +{
>> +   const char *str_cmd, *str_channel = NULL, *str_enable = NULL;
>> +   const char *str_pwm = NULL, *str_period = NULL, *str_duty = NULL;
>> +   enum pwm_cmd sub_cmd;
>> +   struct udevice *dev;
>> +   u32 channel, pwm_enable, pwm_dev, period_ns = 0, duty_ns = 0;
>> +   int ret;
>> +
>> +   if (argc < 4)
>> + show_usage:
>> +   return CMD_RET_USAGE;
>> +
>> +   str_cmd = argv[1];
>> +   argc -= 2;
>> +   argv += 2;
>> +
>> +   if (argc > 0) {
>> +   str_pwm = *argv;
>> +   argc--;
>> +   argv++;
>> +   }
>> +
>> +   if (!str_pwm)
>> +   goto show_usage;
>> +
>> +   switch (*str_cmd) {

RE: [PATCH] riscv: timer: Add support for an early timer

[Pragnesh Patel]

Hi Rick,
[]
>> >After add CONFIG_TIMER_EARLY, U-Boot boots ok.
>> >But When I try to booting kernel with FTRACE=1, following are the test 
>> >stats:
>> >
>> >ae350_rv64_spl_defconfig without FTRACE=1, kernel booting is ok.
>> >ae350_rv64_spl_defconfig with FTRACE=1, kernel booting fail.
>> >ae350_rv64_defconfig with FTRACE=1, kernel booting is ok
>> >
>> >The failure case seems not reasonable.
>> >Any suggestions ?

Can you please enable debug logs by adding below in ae350_rv64_spl_defconfig ?

CONFIG_LOG=y
CONFIG_LOG_MAX_LEVEL=9
CONFIG_LOG_DEFAULT_LEVEL=9
CONFIG_LOG_CONSOLE=y
CONFIG_SPL_LOG=y
CONFIG_SPL_LOG_MAX_LEVEL=9
CONFIG_SPL_LOG_CONSOLE=y

>>
>> Strange, Can you please tell me which steps you follow and also send some
>debug logs  if possible.
>>
>
>Following are the configurations, steps and debug logs:
>
>+++ b/configs/ae350_rv64_defconfig
>q+CONFIG_TRACE=y
>+CONFIG_TRACE_BUFFER_SIZE=0x0100
>+CONFIG_TRACE_CALL_DEPTH_LIMIT=15
>+CONFIG_CMD_TRACE=y
>+CONFIG_TIMER_EARLY=y
>
>+++ b/configs/ae350_rv64_spl_defconfig
>+CONFIG_TRACE=y
>+CONFIG_TRACE_BUFFER_SIZE=0x0100
>+CONFIG_TRACE_CALL_DEPTH_LIMIT=15
>+CONFIG_CMD_TRACE=y
>+CONFIG_TIMER_EARLY=y
>
> case 1
>///
>ae350_rv64_defconfig with FTRACE=1, kernel booting is ok
> case 1
>///
>make FTRACE=1 ae350_rv64_defconfig
>make FTRACE=1
>//
>/
>U-Boot 2021.01-rc2-00139-gb3d3d69-dirty (Nov 25 2020 - 11:14:28 +0800)
>
>DRAM:  1 GiB
>trace: enabled
>Flash: 64 MiB
>MMC:   mmc@f0e0: 0
>Loading Environment from SPIFlash... SF: Detected mx25u1635e with page
>size 256 Bytes, erase size 4 KiB, total 2 MiB
>OK
>In:serial@f030
>Out:   serial@f030
>Err:   serial@f030
>Net:   no alias for ethernet0
>Warning: mac@e010 (eth0) using random MAC address - de:fa:3e:1b:11:42
>eth0: mac@e010
>Hit any key to stop autoboot:  0
>RISC-V # fatload mmc 0:1 0x2000 ae350_rv64_smp_4_no_fd_coherent.dtb
>6455 bytes read in 67 ms (93.8 KiB/s)
>RISC-V # fatload mmc 0:1 0x0060 bootm_ae350_rv64_smp_bbl.bin
>22518836 bytes read in 11915 ms (1.8 MiB/s)
>RISC-V # bootm 0x0060 - 0x2000
>## Booting kernel from Legacy Image at 0060 ...
>   Image Name:
>   Image Type:   RISC-V Linux Kernel Image (uncompressed)
>   Data Size:22518772 Bytes = 21.5 MiB
>   Load Address: 
>   Entry Point:  
>   Verifying Checksum ... OK
>## Flattened Device Tree blob at 2000
>   Booting using the fdt blob at 0x2000
>   Loading Kernel Image
>   Loading Device Tree to 1effb000, end 1efff936 ... OK
>
>Starting kernel ...(fake run for tracing)
>
>Starting kernel ...
>
>OF: fdt: Ignoring memory range 0x0 - 0x20
>Linux version 4.17.0-00253-g49136e10bcb2 (sqa@atcsqa07) (gcc version
>7.3.0 (2019-04-06_nds64le-linux-glibc-v5_experimental)) #1 SMP PREEMPT
>Sat Apr 6 23:41:49 CST 2019
>bootconsole [early0] enabled
>Initial ramdisk at: 0x(ptrval) (13665712 bytes)
>Zone ranges:
>  DMA32[mem 0x0020-0x3fff]
>  Normal   empty
>Movable zone start for each node
>Early memory node ranges
>...
>...
>
> case 2
>///
>ae350_rv64_spl_defconfig with FTRACE=1, kernel booting fail
> case 2
>///
>make FTRACE=1 ae350_rv64_spl_defconfig
>make FTRACE=1
>//
>/
>U-Boot SPL 2020.10-rc2-00175-gfa50824 (Sep 15 2020 - 19:26:29 +0800)
>Trying to boot from MMC1
>U-Boot SPL 2021.01-rc2-00139-gb3d3d69-dirty (Nov 25 2020 - 13:48:05 +0800)
>Trying to boot from RAM
>U-Boot 2021.01-rc2-00139-gb3d3d69-dirty (Nov 25 2020 - 13:48:05 +0800)
>DRAM:  1 GiB
>trace: enabled
>Flash: 64 MiB
>MMC:   mmc@f0e0: 0
>Loading Environment from SPIFlash... SF: Detected mx25u1635e with page
>size 256 Bytes, erase size 4 KiB, total 2 MiB
>OK
>In:serial@f030
>Out:   serial@f030
>Err:   serial@f030
>Net:   no alias for ethernet0
>Warning: mac@e010 (eth0) using random MAC address - 36:86:da:0f:8e:8d
>eth0: mac@e010
>Hit any key to stop autoboot:  0
>27689996 bytes read in 15024 ms (1.8 MiB/s)
>6435 bytes read in 25 ms (251 KiB/s)
>## Booting kernel from Legacy Image at 0060 ...
>   Image Name:
>   Image Type:   RISC-V Linux Kernel Image (uncompressed)
>   Data Size:27689932 Bytes = 26.4 MiB
>   Load Address: 0020
>   Entry Point:  0020
>   Verifying Checksum ... OK
>## Flattened Device Tree blob at 2000
>   Booting using the fdt blob at 0x2000
>   Loading Kernel Image
>   Loading Device Tree to 

RE: [PATCH] riscv: timer: Add support for an early timer

[Pragnesh Patel]

Hi Rick,

>-Original Message-
[...]
>> >After add CONFIG_TIMER_EARLY, U-Boot boots ok.
>> >But When I try to booting kernel with FTRACE=1, following are the test 
>> >stats:
>> >
>> >ae350_rv64_spl_defconfig without FTRACE=1, kernel booting is ok.
>> >ae350_rv64_spl_defconfig with FTRACE=1, kernel booting fail.
>> >ae350_rv64_defconfig with FTRACE=1, kernel booting is ok
>> >
>> >The failure case seems not reasonable.
>> >Any suggestions ?
>>
>> Strange, Can you please tell me which steps you follow and also send some
>debug logs  if possible.
>>
>
>Following are the configurations, steps and debug logs:
>
>+++ b/configs/ae350_rv64_defconfig
>q+CONFIG_TRACE=y
>+CONFIG_TRACE_BUFFER_SIZE=0x0100
>+CONFIG_TRACE_CALL_DEPTH_LIMIT=15
>+CONFIG_CMD_TRACE=y
>+CONFIG_TIMER_EARLY=y
>
>+++ b/configs/ae350_rv64_spl_defconfig
>+CONFIG_TRACE=y
>+CONFIG_TRACE_BUFFER_SIZE=0x0100
>+CONFIG_TRACE_CALL_DEPTH_LIMIT=15
>+CONFIG_CMD_TRACE=y
>+CONFIG_TIMER_EARLY=y
>
> case 1
>///
>ae350_rv64_defconfig with FTRACE=1, kernel booting is ok
> case 1
>///
>make FTRACE=1 ae350_rv64_defconfig
>make FTRACE=1
>//
>/
>U-Boot 2021.01-rc2-00139-gb3d3d69-dirty (Nov 25 2020 - 11:14:28 +0800)
>
>DRAM:  1 GiB
>trace: enabled
>Flash: 64 MiB
>MMC:   mmc@f0e0: 0
>Loading Environment from SPIFlash... SF: Detected mx25u1635e with page
>size 256 Bytes, erase size 4 KiB, total 2 MiB
>OK
>In:serial@f030
>Out:   serial@f030
>Err:   serial@f030
>Net:   no alias for ethernet0
>Warning: mac@e010 (eth0) using random MAC address - de:fa:3e:1b:11:42
>eth0: mac@e010
>Hit any key to stop autoboot:  0
>RISC-V # fatload mmc 0:1 0x2000 ae350_rv64_smp_4_no_fd_coherent.dtb
>6455 bytes read in 67 ms (93.8 KiB/s)
>RISC-V # fatload mmc 0:1 0x0060 bootm_ae350_rv64_smp_bbl.bin
>22518836 bytes read in 11915 ms (1.8 MiB/s)
>RISC-V # bootm 0x0060 - 0x2000
>## Booting kernel from Legacy Image at 0060 ...
>   Image Name:
>   Image Type:   RISC-V Linux Kernel Image (uncompressed)
>   Data Size:22518772 Bytes = 21.5 MiB
>   Load Address: 
>   Entry Point:  
>   Verifying Checksum ... OK
>## Flattened Device Tree blob at 2000
>   Booting using the fdt blob at 0x2000
>   Loading Kernel Image
>   Loading Device Tree to 1effb000, end 1efff936 ... OK
>
>Starting kernel ...(fake run for tracing)
>
>Starting kernel ...
>
>OF: fdt: Ignoring memory range 0x0 - 0x20
>Linux version 4.17.0-00253-g49136e10bcb2 (sqa@atcsqa07) (gcc version
>7.3.0 (2019-04-06_nds64le-linux-glibc-v5_experimental)) #1 SMP PREEMPT
>Sat Apr 6 23:41:49 CST 2019
>bootconsole [early0] enabled
>Initial ramdisk at: 0x(ptrval) (13665712 bytes)
>Zone ranges:
>  DMA32[mem 0x0020-0x3fff]
>  Normal   empty
>Movable zone start for each node
>Early memory node ranges
>...
>...
>
> case 2
>///
>ae350_rv64_spl_defconfig with FTRACE=1, kernel booting fail
> case 2
>///
>make FTRACE=1 ae350_rv64_spl_defconfig
>make FTRACE=1
>//
>/
>U-Boot SPL 2020.10-rc2-00175-gfa50824 (Sep 15 2020 - 19:26:29 +0800)
>Trying to boot from MMC1
>U-Boot SPL 2021.01-rc2-00139-gb3d3d69-dirty (Nov 25 2020 - 13:48:05 +0800)
>Trying to boot from RAM
>U-Boot 2021.01-rc2-00139-gb3d3d69-dirty (Nov 25 2020 - 13:48:05 +0800)
>DRAM:  1 GiB
>trace: enabled
>Flash: 64 MiB
>MMC:   mmc@f0e0: 0
>Loading Environment from SPIFlash... SF: Detected mx25u1635e with page
>size 256 Bytes, erase size 4 KiB, total 2 MiB
>OK
>In:serial@f030
>Out:   serial@f030
>Err:   serial@f030
>Net:   no alias for ethernet0
>Warning: mac@e010 (eth0) using random MAC address - 36:86:da:0f:8e:8d
>eth0: mac@e010
>Hit any key to stop autoboot:  0
>27689996 bytes read in 15024 ms (1.8 MiB/s)
>6435 bytes read in 25 ms (251 KiB/s)
>## Booting kernel from Legacy Image at 0060 ...
>   Image Name:
>   Image Type:   RISC-V Linux Kernel Image (uncompressed)
>   Data Size:27689932 Bytes = 26.4 MiB
>   Load Address: 0020
>   Entry Point:  0020
>   Verifying Checksum ... OK
>## Flattened Device Tree blob at 2000
>   Booting using the fdt blob at 0x2000
>   Loading Kernel Image
>   Loading Device Tree to 1effb000, end 1efff922 ... OK
>
>Starting kernel ...(fake run for tracing)
>
>Starting kernel ...
>
>(hang here)

Thanks for the logs.

From logs, I can't find where it got stuck. Can you please use gdb to 

RE: [PATCH] riscv: timer: Add support for an early timer

[Pragnesh Patel]

Hi Rick,

>-Original Message-
>From: Rick Chen 
>Sent: 26 November 2020 14:44
>To: Pragnesh Patel 
>Cc: Simon Glass ; U-Boot Mailing List b...@lists.denx.de>; Atish Patra ; Bin Meng
>; Paul Walmsley ( Sifive) ;
>Anup Patel ; Sagar Kadam
>; Palmer Dabbelt ; rick
>; Alan Kao ; Leo Liang
>
>Subject: Re: [PATCH] riscv: timer: Add support for an early timer
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh
>
>> Hi Rick,
>>
>> >-Original Message-----
>> >From: Rick Chen 
>> >Sent: 24 November 2020 13:08
>> >To: Pragnesh Patel 
>> >Cc: U-Boot Mailing List ; Atish Patra
>> >; Bin Meng ; Paul Walmsley (
>> >Sifive) ; Anup Patel ;
>> >Sagar Kadam ; Palmer Dabbelt
>> >; Simon Glass ; rick
>> >; Alan Kao ; Leo Liang
>> >
>> >Subject: Re: [PATCH] riscv: timer: Add support for an early timer
>> >
>> >[External Email] Do not click links or attachments unless you
>> >recognize the sender and know the content is safe
>> >
>> >Hi Pragnesh,
>> >
>> >> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
>> >> Sent: Tuesday, November 17, 2020 7:05 PM
>> >> To: u-boot@lists.denx.de
>> >> Cc: atish.pa...@wdc.com; palmerdabb...@google.com;
>> >bmeng...@gmail.com;
>> >> paul.walms...@sifive.com; anup.pa...@wdc.com;
>> >> sagar.ka...@sifive.com; Rick Jian-Zhi Chen(陳建志); Pragnesh Patel;
>> >> Palmer Dabbelt; Sean Anderson; Simon Glass; Bin Meng
>> >> Subject: [PATCH] riscv: timer: Add support for an early timer
>> >>
>> >> Added support for timer_early_get_count() and
>> >> timer_early_get_rate() This is mostly useful in tracing.
>> >>
>> >> Signed-off-by: Pragnesh Patel 
>> >> ---
>> >>  drivers/timer/andes_plmt_timer.c   | 21 -
>> >>  drivers/timer/riscv_timer.c| 21 -
>> >>  drivers/timer/sifive_clint_timer.c | 21 -
>> >>  include/configs/ax25-ae350.h   |  5 +
>> >>  include/configs/sifive-fu540.h |  5 +
>> >>  5 files changed, 70 insertions(+), 3 deletions(-)
>> >>
>> >
>> >I verify with ae350_rv64_defconfig
>> >
>> >make FTRACE=1 ae350_rv64_defconfig
>> >make FTRACE=1
>> >
>> >and it boot fail as below:
>> >
>> >U-Boot 2021.01-rc2-00140-geb42715 (Nov 24 2020 - 15:02:18 +0800)
>> >
>> >DRAM:  1 GiB
>> >trace: enabled
>> >
>> >DO you have any suggestions ?
>>
>> Please enable CONFIG_TIMER_EARLY=y in ae350_rv64_defconfig
>>
>> Actually in v2, I will make TRACE to select TIMER_EARLY like below,
>>
>> --- a/lib/Kconfig
>> +++ b/lib/Kconfig
>> @@ -210,6 +210,7 @@ config BITREVERSE
>>  config TRACE
>> bool "Support for tracing of function calls and timing"
>> imply CMD_TRACE
>> +   select TIMER_EARLY
>>
>> Let me know if you have any suggestion.
>
>OK.
>
>After add CONFIG_TIMER_EARLY, U-Boot boots ok.
>But When I try to booting kernel with FTRACE=1, following are the test stats:
>
>ae350_rv64_spl_defconfig without FTRACE=1, kernel booting is ok.
>ae350_rv64_spl_defconfig with FTRACE=1, kernel booting fail.
>ae350_rv64_defconfig with FTRACE=1, kernel booting is ok
>
>The failure case seems not reasonable.
>Any suggestions ?

Strange, Can you please tell me which steps you follow and also send some debug 
logs  if possible.

>
>Thanks,
>Rick
>
>>
>> >
>> >Thanks,
>> >Rick
>> >
>> >> diff --git a/drivers/timer/andes_plmt_timer.c
>> >> b/drivers/timer/andes_plmt_timer.c
>> >> index cec86718c7..74b795c97a 100644
>> >> --- a/drivers/timer/andes_plmt_timer.c
>> >> +++ b/drivers/timer/andes_plmt_timer.c
>> >> @@ -17,11 +17,30 @@
>> >>  /* mtime register */
>> >>  #define MTIME_REG(base)((ulong)(base))
>> >>
>> >> -static u64 andes_plmt_get_count(struct udevice *dev)
>> >> +static u64 notrace andes_plmt_get_count(struct udevice *dev)
>> >>  {
>> >> return readq((void __iomem *)MTIME_REG(dev->priv));  }
>> >>
>> >> +#if CONFIG_IS_ENABLED(RISCV_MMODE)
>> >> +/**
>> >> + * timer_early_get_rate() - Get the timer rate bef

[PATCH v2] cmd: Add a pwm command

[Pragnesh Patel]

Add the command "pwm" for controlling the pwm channels. This
command provides pwm invert/config/enable/disable functionalities
via PWM uclass drivers

Signed-off-by: Pragnesh Patel 
---

Changes in v2:
- Add test for pwm command


 README|   1 +
 cmd/Kconfig   |   6 ++
 cmd/Makefile  |   1 +
 cmd/pwm.c | 120 ++
 configs/sandbox_defconfig |   1 +
 test/cmd/Makefile |   1 +
 test/cmd/pwm.c|  54 +
 7 files changed, 184 insertions(+)
 create mode 100644 cmd/pwm.c
 create mode 100644 test/cmd/pwm.c

diff --git a/README b/README
index cb49aa15da..dab291e0d0 100644
--- a/README
+++ b/README
@@ -3160,6 +3160,7 @@ i2c   - I2C sub-system
 sspi   - SPI utility commands
 base   - print or set address offset
 printenv- print environment variables
+pwm- control pwm channels
 setenv - set environment variables
 saveenv - save environment variables to persistent storage
 protect - enable or disable FLASH write protection
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 1595de999b..0d085108f4 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -918,6 +918,12 @@ config CMD_GPIO
help
  GPIO support.
 
+config CMD_PWM
+   bool "pwm"
+   depends on DM_PWM
+   help
+ Control PWM channels, this allows invert/config/enable/disable PWM 
channels.
+
 config CMD_GPT
bool "GPT (GUID Partition Table) command"
select EFI_PARTITION
diff --git a/cmd/Makefile b/cmd/Makefile
index dd86675bf2..75df3c136c 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -120,6 +120,7 @@ endif
 obj-$(CONFIG_CMD_PINMUX) += pinmux.o
 obj-$(CONFIG_CMD_PMC) += pmc.o
 obj-$(CONFIG_CMD_PSTORE) += pstore.o
+obj-$(CONFIG_CMD_PWM) += pwm.o
 obj-$(CONFIG_CMD_PXE) += pxe.o pxe_utils.o
 obj-$(CONFIG_CMD_WOL) += wol.o
 obj-$(CONFIG_CMD_QFW) += qfw.o
diff --git a/cmd/pwm.c b/cmd/pwm.c
new file mode 100644
index 00..f704c7a755
--- /dev/null
+++ b/cmd/pwm.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Control PWM channels
+ *
+ * Copyright (c) 2020 SiFive, Inc
+ * author: Pragnesh Patel 
+ */
+
+#include 
+#include 
+#include 
+
+enum pwm_cmd {
+   PWM_SET_INVERT,
+   PWM_SET_CONFIG,
+   PWM_SET_ENABLE,
+   PWM_SET_DISABLE,
+};
+
+static int do_pwm(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+   const char *str_cmd, *str_channel = NULL, *str_enable = NULL;
+   const char *str_pwm = NULL, *str_period = NULL, *str_duty = NULL;
+   enum pwm_cmd sub_cmd;
+   struct udevice *dev;
+   u32 channel, pwm_enable, pwm_dev, period_ns = 0, duty_ns = 0;
+   int ret;
+
+   if (argc < 4)
+ show_usage:
+   return CMD_RET_USAGE;
+
+   str_cmd = argv[1];
+   argc -= 2;
+   argv += 2;
+
+   if (argc > 0) {
+   str_pwm = *argv;
+   argc--;
+   argv++;
+   }
+
+   if (!str_pwm)
+   goto show_usage;
+
+   switch (*str_cmd) {
+   case 'i':
+   sub_cmd = PWM_SET_INVERT;
+   break;
+   case 'c':
+   sub_cmd = PWM_SET_CONFIG;
+   break;
+   case 'e':
+   sub_cmd = PWM_SET_ENABLE;
+   break;
+   case 'd':
+   sub_cmd = PWM_SET_DISABLE;
+   break;
+   default:
+   goto show_usage;
+   }
+
+   if (IS_ENABLED(CONFIG_DM_PWM)) {
+   pwm_dev = simple_strtoul(str_pwm, NULL, 10);
+   ret = uclass_get_device(UCLASS_PWM, pwm_dev, );
+   if (ret) {
+   printf("PWM: '%s' not found\n", str_pwm);
+   return cmd_process_error(cmdtp, ret);
+   }
+   }
+
+   if (argc > 0) {
+   str_channel = *argv;
+   channel = simple_strtoul(str_channel, NULL, 10);
+   argc--;
+   argv++;
+   } else {
+   goto show_usage;
+   }
+
+   if (sub_cmd == PWM_SET_INVERT && argc > 0) {
+   str_enable = *argv;
+   pwm_enable = simple_strtoul(str_enable, NULL, 10);
+   ret = pwm_set_invert(dev, channel, pwm_enable);
+   } else if (sub_cmd == PWM_SET_CONFIG && argc == 2) {
+   str_period = *argv;
+   argc--;
+   argv++;
+   period_ns = simple_strtoul(str_period, NULL, 10);
+
+   if (argc > 0) {
+   str_duty = *argv;
+   duty_ns = simple_strtoul(str_duty, NULL, 10);
+   }
+
+   ret = pwm_set_config(dev, channel, period_ns, duty_ns);
+   } else if (sub_cmd == PWM_SET_ENABLE) {
+   ret = pwm_set_enable(dev, channel, 1);
+   } else if (sub_cmd == PWM_SET_DISABLE) {
+   ret = pwm_set_enable(dev, channe

RE: [PATCH] cmd: Add a pwm command

[Pragnesh Patel]

>-Original Message-
>From: Tom Rini 
>Sent: 23 November 2020 21:22
>To: Pragnesh Patel 
>Cc: u-boot@lists.denx.de; atish.pa...@wdc.com; palmerdabb...@google.com;
>bmeng...@gmail.com; Paul Walmsley ( Sifive) ;
>anup.pa...@wdc.com; Sagar Kadam ;
>r...@andestech.com; Simon Glass ; Heinrich Schuchardt
>; Bin Meng ; Miquel Raynal
>; Patrick Delaunay ;
>Sam Protsenko ; Philippe Reynes
>; Frédéric Danis
>; Patrice Chotard ;
>Vladimir Olovyannikov ; Ramon Fried
>; Eugeniu Rosca 
>Subject: Re: [PATCH] cmd: Add a pwm command
>
>On Mon, Nov 23, 2020 at 01:38:41PM +0530, Pragnesh Patel wrote:
>
>> Add the command "pwm" for controlling the pwm channels. This command
>> provides pwm invert/config/enable/disable functionalities via PWM
>> uclass drivers
>>
>> Signed-off-by: Pragnesh Patel 
>> ---
>>  cmd/Kconfig  |   6 +++
>>  cmd/Makefile |   1 +
>>  cmd/pwm.c| 119
>+++
>>  3 files changed, 126 insertions(+)
>>  create mode 100644 cmd/pwm.c
>
>Can you please add some tests and dt fragments to sandbox for this?

There is already a "test/dm/pwm.c".

>Thanks.
>
>--
>Tom

RE: [PATCH] riscv: timer: Add support for an early timer

[Pragnesh Patel]

Hi Rick,

>-Original Message-
>From: Rick Chen 
>Sent: 24 November 2020 13:08
>To: Pragnesh Patel 
>Cc: U-Boot Mailing List ; Atish Patra
>; Bin Meng ; Paul Walmsley (
>Sifive) ; Anup Patel ; Sagar
>Kadam ; Palmer Dabbelt ;
>Simon Glass ; rick ; Alan Kao
>; Leo Liang 
>Subject: Re: [PATCH] riscv: timer: Add support for an early timer
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh,
>
>> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
>> Sent: Tuesday, November 17, 2020 7:05 PM
>> To: u-boot@lists.denx.de
>> Cc: atish.pa...@wdc.com; palmerdabb...@google.com;
>bmeng...@gmail.com;
>> paul.walms...@sifive.com; anup.pa...@wdc.com; sagar.ka...@sifive.com;
>> Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; Palmer Dabbelt; Sean
>> Anderson; Simon Glass; Bin Meng
>> Subject: [PATCH] riscv: timer: Add support for an early timer
>>
>> Added support for timer_early_get_count() and timer_early_get_rate()
>> This is mostly useful in tracing.
>>
>> Signed-off-by: Pragnesh Patel 
>> ---
>>  drivers/timer/andes_plmt_timer.c   | 21 -
>>  drivers/timer/riscv_timer.c| 21 -
>>  drivers/timer/sifive_clint_timer.c | 21 -
>>  include/configs/ax25-ae350.h   |  5 +
>>  include/configs/sifive-fu540.h |  5 +
>>  5 files changed, 70 insertions(+), 3 deletions(-)
>>
>
>I verify with ae350_rv64_defconfig
>
>make FTRACE=1 ae350_rv64_defconfig
>make FTRACE=1
>
>and it boot fail as below:
>
>U-Boot 2021.01-rc2-00140-geb42715 (Nov 24 2020 - 15:02:18 +0800)
>
>DRAM:  1 GiB
>trace: enabled
>
>DO you have any suggestions ?

Please enable CONFIG_TIMER_EARLY=y in ae350_rv64_defconfig

Actually in v2, I will make TRACE to select TIMER_EARLY like below,

--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -210,6 +210,7 @@ config BITREVERSE
 config TRACE
bool "Support for tracing of function calls and timing"
imply CMD_TRACE
+   select TIMER_EARLY

Let me know if you have any suggestion.

>
>Thanks,
>Rick
>
>> diff --git a/drivers/timer/andes_plmt_timer.c
>> b/drivers/timer/andes_plmt_timer.c
>> index cec86718c7..74b795c97a 100644
>> --- a/drivers/timer/andes_plmt_timer.c
>> +++ b/drivers/timer/andes_plmt_timer.c
>> @@ -17,11 +17,30 @@
>>  /* mtime register */
>>  #define MTIME_REG(base)((ulong)(base))
>>
>> -static u64 andes_plmt_get_count(struct udevice *dev)
>> +static u64 notrace andes_plmt_get_count(struct udevice *dev)
>>  {
>> return readq((void __iomem *)MTIME_REG(dev->priv));  }
>>
>> +#if CONFIG_IS_ENABLED(RISCV_MMODE)
>> +/**
>> + * timer_early_get_rate() - Get the timer rate before driver model
>> +*/ unsigned long notrace timer_early_get_rate(void) {
>> +   return RISCV_MMODE_TIMER_FREQ; }
>> +
>> +/**
>> + * timer_early_get_count() - Get the timer count before driver model
>> + *
>> + */
>> +u64 notrace timer_early_get_count(void) {
>> +   return readq((void __iomem
>> +*)MTIME_REG(RISCV_MMODE_TIMERBASE));
>> +}
>> +#endif
>> +
>>  static const struct timer_ops andes_plmt_ops = {
>> .get_count = andes_plmt_get_count,  }; diff --git
>> a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c index
>> 21ae184057..a0f71ca897 100644
>> --- a/drivers/timer/riscv_timer.c
>> +++ b/drivers/timer/riscv_timer.c
>> @@ -16,7 +16,7 @@
>>  #include 
>>  #include 
>>
>> -static u64 riscv_timer_get_count(struct udevice *dev)
>> +static u64 notrace riscv_timer_get_count(struct udevice *dev)
>>  {
>> __maybe_unused u32 hi, lo;
>>
>> @@ -31,6 +31,25 @@ static u64 riscv_timer_get_count(struct udevice *dev)
>> return ((u64)hi << 32) | lo;
>>  }
>>
>> +#if CONFIG_IS_ENABLED(RISCV_SMODE)
>> +/**
>> + * timer_early_get_rate() - Get the timer rate before driver model
>> +*/ unsigned long notrace timer_early_get_rate(void) {
>> +   return RISCV_SMODE_TIMER_FREQ; }
>> +
>> +/**
>> + * timer_early_get_count() - Get the timer count before driver model
>> + *
>> + */
>> +u64 notrace timer_early_get_count(void) {
>> +   return riscv_timer_get_count(NULL); } #endif
>> +
>>  static int riscv_timer_probe(struct udevice *dev)  {
>> struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
>> diff --git a/drivers/timer/sifive_clint_timer.c
>> b/drivers/timer

[PATCH] cmd: Add a pwm command

[Pragnesh Patel]

Add the command "pwm" for controlling the pwm channels. This
command provides pwm invert/config/enable/disable functionalities
via PWM uclass drivers

Signed-off-by: Pragnesh Patel 
---
 cmd/Kconfig  |   6 +++
 cmd/Makefile |   1 +
 cmd/pwm.c| 119 +++
 3 files changed, 126 insertions(+)
 create mode 100644 cmd/pwm.c

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 1595de999b..4f3a70b1d5 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -918,6 +918,12 @@ config CMD_GPIO
help
  GPIO support.
 
+config CMD_PWM
+   bool "pwm"
+   depends on DM_PWM
+   help
+ PWM support.
+
 config CMD_GPT
bool "GPT (GUID Partition Table) command"
select EFI_PARTITION
diff --git a/cmd/Makefile b/cmd/Makefile
index dd86675bf2..75df3c136c 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -120,6 +120,7 @@ endif
 obj-$(CONFIG_CMD_PINMUX) += pinmux.o
 obj-$(CONFIG_CMD_PMC) += pmc.o
 obj-$(CONFIG_CMD_PSTORE) += pstore.o
+obj-$(CONFIG_CMD_PWM) += pwm.o
 obj-$(CONFIG_CMD_PXE) += pxe.o pxe_utils.o
 obj-$(CONFIG_CMD_WOL) += wol.o
 obj-$(CONFIG_CMD_QFW) += qfw.o
diff --git a/cmd/pwm.c b/cmd/pwm.c
new file mode 100644
index 00..f82f7789cd
--- /dev/null
+++ b/cmd/pwm.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Control PWM channels
+ *
+ * Copyright (c) 2020 SiFive, Inc
+ * author: Pragnesh Patel 
+ */
+
+#include 
+#include 
+#include 
+
+enum pwm_cmd {
+   PWM_SET_INVERT,
+   PWM_SET_CONFIG,
+   PWM_SET_ENABLE,
+   PWM_SET_DISABLE,
+};
+
+static int do_pwm(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+   const char *str_cmd, *str_channel = NULL, *str_enable = NULL;
+   const char *str_pwm = NULL, *str_period = NULL, *str_duty = NULL;
+   enum pwm_cmd sub_cmd;
+   struct udevice *dev;
+   u32 channel, pwm_enable, period_ns = 0, duty_ns = 0;
+   int ret;
+
+   if (argc < 4)
+ show_usage:
+   return CMD_RET_USAGE;
+
+   str_cmd = argv[1];
+   argc -= 2;
+   argv += 2;
+
+   if (argc > 0) {
+   str_pwm = *argv;
+   argc--;
+   argv++;
+   }
+
+   if (!str_pwm)
+   goto show_usage;
+
+   switch (*str_cmd) {
+   case 'i':
+   sub_cmd = PWM_SET_INVERT;
+   break;
+   case 'c':
+   sub_cmd = PWM_SET_CONFIG;
+   break;
+   case 'e':
+   sub_cmd = PWM_SET_ENABLE;
+   break;
+   case 'd':
+   sub_cmd = PWM_SET_DISABLE;
+   break;
+   default:
+   goto show_usage;
+   }
+
+   if (IS_ENABLED(CONFIG_DM_PWM)) {
+   ret = uclass_get_device_by_name(UCLASS_PWM, str_pwm, );
+   if (ret) {
+   printf("PWM: '%s' not found\n", str_pwm);
+   return cmd_process_error(cmdtp, ret);
+   }
+   }
+
+   if (argc > 0) {
+   str_channel = *argv;
+   channel = simple_strtoul(str_channel, NULL, 10);
+   argc--;
+   argv++;
+   } else {
+   goto show_usage;
+   }
+
+   if (sub_cmd == PWM_SET_INVERT && argc > 0) {
+   str_enable = *argv;
+   pwm_enable = simple_strtoul(str_enable, NULL, 10);
+   ret = pwm_set_invert(dev, channel, pwm_enable);
+   } else if (sub_cmd == PWM_SET_CONFIG && argc == 2) {
+   str_period = *argv;
+   argc--;
+   argv++;
+   period_ns = simple_strtoul(str_period, NULL, 10);
+
+   if (argc > 0) {
+   str_duty = *argv;
+   duty_ns = simple_strtoul(str_duty, NULL, 10);
+   }
+
+   ret = pwm_set_config(dev, channel, period_ns, duty_ns);
+   } else if (sub_cmd == PWM_SET_ENABLE) {
+   ret = pwm_set_enable(dev, channel, 1);
+   } else if (sub_cmd == PWM_SET_DISABLE) {
+   ret = pwm_set_enable(dev, channel, 0);
+   } else {
+   printf("PWM arguments missing\n");
+   return CMD_RET_FAILURE;
+   }
+
+   if (ret) {
+   printf("error!\n");
+   return CMD_RET_FAILURE;
+   }
+
+   printf("success!\n");
+   return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(pwm, 6, 0, do_pwm,
+  "control pwm channels",
+  "pwm\n"
+  "pwm \n"
+  "pwm   ");
-- 
2.17.1

RE: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing

[Pragnesh Patel]

Hi Leo,

>-Original Message-
>From: Leo Liang 
>Sent: 23 November 2020 11:28
>To: Pragnesh Patel 
>Cc: Rick Chen ; U-Boot Mailing List b...@lists.denx.de>; Atish Patra ;
>palmerdabb...@google.com; Bin Meng ; Paul Walmsley
>( Sifive) ; Anup Patel ; Sagar
>Kadam ; Sean Anderson ;
>rick ; Alan Kao 
>Subject: Re: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On Tue, Nov 17, 2020 at 08:30:21AM +, Pragnesh Patel wrote:
>
>Hi Pragnesh,
>
>> Hi Rick,
>>
>> >-Original Message-
>> >From: Rick Chen 
>> >Sent: 13 November 2020 13:37
>> >To: Pragnesh Patel 
>> >Cc: U-Boot Mailing List ; Atish Patra
>> >; palmerdabb...@google.com; Bin Meng
>> >; Paul Walmsley ( Sifive)
>> >; Anup Patel ; Sagar
>> >Kadam ; Sean Anderson
>;
>> >rick ; Alan Kao ; Leo
>> >Liang 
>> >Subject: Re: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing
>> >
>> >[External Email] Do not click links or attachments unless you
>> >recognize the sender and know the content is safe
>> >
>> >Hi Pragnesh
>> >
>> >> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
>> >> Sent: Wednesday, November 11, 2020 6:15 PM
>> >> To: u-boot@lists.denx.de
>> >> Cc: atish.pa...@wdc.com; palmerdabb...@google.com;
>> >bmeng...@gmail.com;
>> >> paul.walms...@sifive.com; anup.pa...@wdc.com;
>> >> sagar.ka...@sifive.com; Rick Jian-Zhi Chen(陳建志); Pragnesh Patel;
>> >> Sean Anderson; Heinrich Schuchardt; Simon Glass
>> >> Subject: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing
>> >>
>> >> Add timer_get_us() which is useful for tracing.
>> >> For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide a timer
>> >> ticks and For M-mode U-Boot, mtime register will provide the same.
>> >>
>> >> Signed-off-by: Pragnesh Patel 
>> >> ---
>> >>
>> >> Changes in v3:
>> >> - Added gd->arch.plmt in global data
>> >> - For timer_get_us(), use readq() instead of andes_plmt_get_count()
>> >>   and sifive_clint_get_count()
>> >>
>> >> Changes in v2:
>> >> - Added timer_get_us() in riscv_timer.c, sifive_clint_timer.c
>> >>   and andes_plmt_timer.c.
>> >>
>> >>
>> >>  arch/riscv/include/asm/global_data.h |  3 +++
>> >>  drivers/timer/andes_plmt_timer.c | 19 ++-
>> >>  drivers/timer/riscv_timer.c  | 14 +-
>> >>  drivers/timer/sifive_clint_timer.c   | 19 ++-
>> >>  4 files changed, 52 insertions(+), 3 deletions(-)
>> >>
>> >> diff --git a/arch/riscv/include/asm/global_data.h
>> >> b/arch/riscv/include/asm/global_data.h
>> >> index d3a0b1d221..4e22ceb83f 100644
>> >> --- a/arch/riscv/include/asm/global_data.h
>> >> +++ b/arch/riscv/include/asm/global_data.h
>> >> @@ -24,6 +24,9 @@ struct arch_global_data {  #ifdef CONFIG_ANDES_PLIC
>> >> void __iomem *plic; /* plic base address */
>> >>  #endif
>> >> +#ifdef CONFIG_ANDES_PLMT
>> >
>> >It shall be CONFIG_ANDES_PLMT, or it will compile fail as below:
>> >
>> >drivers/timer/andes_plmt_timer.c: In function 'timer_get_us':
>> >drivers/timer/andes_plmt_timer.c:36:15: error: 'struct
>> >arch_global_data' has no member named 'plmt'; did you mean 'plic'?
>> >  if (gd->arch.plmt) {
>> >   ^~~~
>> >   plic
>> >drivers/timer/andes_plmt_timer.c:37:52: error: 'struct
>> >arch_global_data' has no member named 'plmt'; did you mean 'plic'?
>> >   ticks = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
>> >
>
>This patch will cause compile error with ae350 defconfig.
>
>${uboot}/drivers/timer/Makefile is articulated in this way,
>"obj-$(CONFIG_ANDES_PLMT_TIMER) += andes_plmt_timer.o", so the #ifdef
>indicator in ${uboot}/arch/riscv/include/asm/global_data.h should use
>CONFIG_ANDES_PLMT_TIMER.

Thanks Leo but Rick has already informed about this error.

I have discarded this series and added a new patch for Tracing which uses 
TIMER_EARLY
https://patchwork.ozlabs.org/project/uboot/patch/20201117110508.25819-1-pragnesh.pa...@sifive.com/

>
>Best regards,
>Leo
>
>> >And it is not proper to have dependency of data s

RE: [PATCH] common/board_r: make sure to call initr_dm() before initr_trace()

[Pragnesh Patel]

>-Original Message-
>From: Simon Glass 
>Sent: 18 November 2020 20:07
>To: Pragnesh Patel 
>Cc: Heinrich Schuchardt ; U-Boot Mailing List b...@lists.denx.de>
>Subject: Re: [PATCH] common/board_r: make sure to call initr_dm() before
>initr_trace()
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh,
>
>On Mon, 16 Nov 2020 at 22:23, Pragnesh Patel 
>wrote:
>>
>> Hi,
>>
>> >-Original Message-----
>> >From: Simon Glass 
>> >Sent: 17 November 2020 05:23
>> >To: Pragnesh Patel 
>> >Cc: Heinrich Schuchardt ; U-Boot Mailing List > >b...@lists.denx.de>
>> >Subject: Re: [PATCH] common/board_r: make sure to call initr_dm()
>> >before
>> >initr_trace()
>> >
>> >[External Email] Do not click links or attachments unless you
>> >recognize the sender and know the content is safe
>> >
>> >Hi,
>> >
>> >On Sun, 15 Nov 2020 at 05:16, Pragnesh Patel
>> >
>> >wrote:
>> >>
>> >> Hi Heinrich,
>> >>
>> >> >-Original Message-
>> >> >From: Heinrich Schuchardt 
>> >> >Sent: 12 November 2020 18:02
>> >> >To: Pragnesh Patel 
>> >> >Cc: U-Boot Mailing List ; Simon Glass
>> >> >
>> >> >Subject: Re: [PATCH] common/board_r: make sure to call initr_dm()
>> >> >before
>> >> >initr_trace()
>> >> >
>> >> >[External Email] Do not click links or attachments unless you
>> >> >recognize the sender and know the content is safe
>> >> >
>> >> >On 11/12/20 12:18 PM, Pragnesh Patel wrote:
>> >> >> Tracing need timer ticks and initr_dm() will make gd->timer and
>> >> >> gd->dm_root is equal to NULL, so make sure that initr_dm() to
>> >> >> call before tracing got enabled.
>> >> >>
>> >> >> Signed-off-by: Pragnesh Patel 
>> >> >> ---
>> >> >>  common/board_r.c | 6 +++---
>> >> >>  1 file changed, 3 insertions(+), 3 deletions(-)
>> >> >>
>> >> >> diff --git a/common/board_r.c b/common/board_r.c index
>> >> >> 29dd7d26d9..7140a39947 100644
>> >> >> --- a/common/board_r.c
>> >> >> +++ b/common/board_r.c
>> >> >> @@ -693,6 +693,9 @@ static int run_main_loop(void)
>> >> >>   * TODO: perhaps reset the watchdog in the initcall function after 
>> >> >> each
>call?
>> >> >>   */
>> >> >>  static init_fnc_t init_sequence_r[] = {
>> >> >> +#ifdef CONFIG_DM
>> >> >> + initr_dm,
>> >> >> +#endif
>> >> >>   initr_trace,
>> >> >>   initr_reloc,
>> >> >>   /* TODO: could x86/PPC have this also perhaps? */ @@
>> >> >> -718,9
>> >> >> +721,6 @@ static init_fnc_t init_sequence_r[] = {
>> >> >>   initr_noncached,
>> >> >>  #endif
>> >> >>   initr_of_live,
>> >> >> -#ifdef CONFIG_DM
>> >> >> - initr_dm,
>> >> >> -#endif
>> >> >
>> >> >You are moving initr_of_live before initr_of_live. I doubt this
>> >> >will work for boards that have CONFIG_OF_LIVE=y.
>> >>
>> >> yes you are right. It will not work for CONFIG_OF_LIVE.
>> >>
>> >> >
>> >> >Can't we move initr_trace down in the code to after both
>> >> >initr_of_live and initr_dm?
>> >> >
>> >> >@Simon:
>> >> >Please, advise.
>> >>
>> >> I am okay with this suggestion.
>> >
>> >Actually can we use the early timer for this case?
>> >
>> >DM init is a part of U-Boot and not being able to trace it would be
>unfortunate.
>>
>> Got it.
>>
>> If someone wants to use tracing without TIMER_EARLY then
>>
>> - initr_dm() will make gd->dm_root = NULL; and gd->timer = NULL; and
>> __cyg_profile_func_enter () will call timer_get_us() -> get_ticks() ->
>dm_timer_init().
>>
>> dm_timer_init() will not able to initialize timer and return an error.
>>
>> We need to find any solution for this.
>
>How about we make TRACE select or depend on TIMER_EARLY?

I am okay with this. Better to make TRACE select TIMER_EARLY.

>
>Regards,
>Simon

[PATCH] riscv: timer: Add support for an early timer

[Pragnesh Patel]

Added support for timer_early_get_count() and timer_early_get_rate()
This is mostly useful in tracing.

Signed-off-by: Pragnesh Patel 
---
 drivers/timer/andes_plmt_timer.c   | 21 -
 drivers/timer/riscv_timer.c| 21 -
 drivers/timer/sifive_clint_timer.c | 21 -
 include/configs/ax25-ae350.h   |  5 +
 include/configs/sifive-fu540.h |  5 +
 5 files changed, 70 insertions(+), 3 deletions(-)

diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c
index cec86718c7..74b795c97a 100644
--- a/drivers/timer/andes_plmt_timer.c
+++ b/drivers/timer/andes_plmt_timer.c
@@ -17,11 +17,30 @@
 /* mtime register */
 #define MTIME_REG(base)((ulong)(base))
 
-static u64 andes_plmt_get_count(struct udevice *dev)
+static u64 notrace andes_plmt_get_count(struct udevice *dev)
 {
return readq((void __iomem *)MTIME_REG(dev->priv));
 }
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ */
+unsigned long notrace timer_early_get_rate(void)
+{
+   return RISCV_MMODE_TIMER_FREQ;
+}
+
+/**
+ * timer_early_get_count() - Get the timer count before driver model
+ *
+ */
+u64 notrace timer_early_get_count(void)
+{
+   return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
+}
+#endif
+
 static const struct timer_ops andes_plmt_ops = {
.get_count = andes_plmt_get_count,
 };
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 21ae184057..a0f71ca897 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -16,7 +16,7 @@
 #include 
 #include 
 
-static u64 riscv_timer_get_count(struct udevice *dev)
+static u64 notrace riscv_timer_get_count(struct udevice *dev)
 {
__maybe_unused u32 hi, lo;
 
@@ -31,6 +31,25 @@ static u64 riscv_timer_get_count(struct udevice *dev)
return ((u64)hi << 32) | lo;
 }
 
+#if CONFIG_IS_ENABLED(RISCV_SMODE)
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ */
+unsigned long notrace timer_early_get_rate(void)
+{
+   return RISCV_SMODE_TIMER_FREQ;
+}
+
+/**
+ * timer_early_get_count() - Get the timer count before driver model
+ *
+ */
+u64 notrace timer_early_get_count(void)
+{
+   return riscv_timer_get_count(NULL);
+}
+#endif
+
 static int riscv_timer_probe(struct udevice *dev)
 {
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
diff --git a/drivers/timer/sifive_clint_timer.c 
b/drivers/timer/sifive_clint_timer.c
index 00ce0f08d6..9ae05a0e7e 100644
--- a/drivers/timer/sifive_clint_timer.c
+++ b/drivers/timer/sifive_clint_timer.c
@@ -14,11 +14,30 @@
 /* mtime register */
 #define MTIME_REG(base)((ulong)(base) + 0xbff8)
 
-static u64 sifive_clint_get_count(struct udevice *dev)
+static u64 notrace sifive_clint_get_count(struct udevice *dev)
 {
return readq((void __iomem *)MTIME_REG(dev->priv));
 }
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ */
+unsigned long notrace timer_early_get_rate(void)
+{
+   return RISCV_MMODE_TIMER_FREQ;
+}
+
+/**
+ * timer_early_get_count() - Get the timer count before driver model
+ *
+ */
+u64 notrace timer_early_get_count(void)
+{
+   return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
+}
+#endif
+
 static const struct timer_ops sifive_clint_ops = {
.get_count = sifive_clint_get_count,
 };
diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h
index b2606e794d..bd9c371f83 100644
--- a/include/configs/ax25-ae350.h
+++ b/include/configs/ax25-ae350.h
@@ -17,6 +17,11 @@
 #endif
 #endif
 
+#define RISCV_MMODE_TIMERBASE   0xe600
+#define RISCV_MMODE_TIMER_FREQ  6000
+
+#define RISCV_SMODE_TIMER_FREQ  6000
+
 /*
  * CPU and Board Configuration Options
  */
diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
index c1c79db147..0d69d1c548 100644
--- a/include/configs/sifive-fu540.h
+++ b/include/configs/sifive-fu540.h
@@ -36,6 +36,11 @@
 
 #define CONFIG_STANDALONE_LOAD_ADDR0x8020
 
+#define RISCV_MMODE_TIMERBASE  0x200
+#define RISCV_MMODE_TIMER_FREQ 100
+
+#define RISCV_SMODE_TIMER_FREQ 100
+
 /* Environment options */
 
 #ifndef CONFIG_SPL_BUILD
-- 
2.17.1

RE: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing

[Pragnesh Patel]

Hi Rick,

>-Original Message-
>From: Rick Chen 
>Sent: 13 November 2020 13:37
>To: Pragnesh Patel 
>Cc: U-Boot Mailing List ; Atish Patra
>; palmerdabb...@google.com; Bin Meng
>; Paul Walmsley ( Sifive) ;
>Anup Patel ; Sagar Kadam
>; Sean Anderson ; rick
>; Alan Kao ; Leo Liang
>
>Subject: Re: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh
>
>> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
>> Sent: Wednesday, November 11, 2020 6:15 PM
>> To: u-boot@lists.denx.de
>> Cc: atish.pa...@wdc.com; palmerdabb...@google.com;
>bmeng...@gmail.com;
>> paul.walms...@sifive.com; anup.pa...@wdc.com; sagar.ka...@sifive.com;
>> Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; Sean Anderson; Heinrich
>> Schuchardt; Simon Glass
>> Subject: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing
>>
>> Add timer_get_us() which is useful for tracing.
>> For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide a timer ticks
>> and For M-mode U-Boot, mtime register will provide the same.
>>
>> Signed-off-by: Pragnesh Patel 
>> ---
>>
>> Changes in v3:
>> - Added gd->arch.plmt in global data
>> - For timer_get_us(), use readq() instead of andes_plmt_get_count()
>>   and sifive_clint_get_count()
>>
>> Changes in v2:
>> - Added timer_get_us() in riscv_timer.c, sifive_clint_timer.c
>>   and andes_plmt_timer.c.
>>
>>
>>  arch/riscv/include/asm/global_data.h |  3 +++
>>  drivers/timer/andes_plmt_timer.c | 19 ++-
>>  drivers/timer/riscv_timer.c  | 14 +-
>>  drivers/timer/sifive_clint_timer.c   | 19 ++-
>>  4 files changed, 52 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/riscv/include/asm/global_data.h
>> b/arch/riscv/include/asm/global_data.h
>> index d3a0b1d221..4e22ceb83f 100644
>> --- a/arch/riscv/include/asm/global_data.h
>> +++ b/arch/riscv/include/asm/global_data.h
>> @@ -24,6 +24,9 @@ struct arch_global_data {  #ifdef CONFIG_ANDES_PLIC
>> void __iomem *plic; /* plic base address */
>>  #endif
>> +#ifdef CONFIG_ANDES_PLMT
>
>It shall be CONFIG_ANDES_PLMT, or it will compile fail as below:
>
>drivers/timer/andes_plmt_timer.c: In function 'timer_get_us':
>drivers/timer/andes_plmt_timer.c:36:15: error: 'struct arch_global_data' has no
>member named 'plmt'; did you mean 'plic'?
>  if (gd->arch.plmt) {
>   ^~~~
>   plic
>drivers/timer/andes_plmt_timer.c:37:52: error: 'struct arch_global_data' has no
>member named 'plmt'; did you mean 'plic'?
>   ticks = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
>
>And it is not proper to have dependency of data structure between
>/arch/riscv/include/asm/* and /drivers/timer/* Maybe enable TIMER_EARLY and
>use timer_get_us() of /lib/time.c will be better.

I am planning to use TIMER_EARLY for tracing.

With TIMER_EARLY, I need to implement timer_early_get_rate() and 
timer_early_get_count()

For timer_early_get_count(), I need PLMT or CLINT base address to read mtime 
register.
So I think it's better to save base address in gd->arch.clint or gd->arch.plmt.

Let me know if you have any other idea to save PLM or CLINT base address.

For timer_early_get_rate(), I will add new variable in global data (gd)
Like, gd->arch.clock_rate;   /* Clock rate of timer in Hz */
This will return Timer frequency in Hz.

Tracing is only useful in U-Boot not in U-Boot SPL so I am doing this for M 
mode U-boot and
S mode U-Boot.

>I also found that without dm_timer_init() in initf_dm(),
>andes_plmt_get_count() will be executed ahead of andes_plmt_probe().

If andes_plmt_get_count() executed before andes_plmt_probe() then how did it 
will get
PLMT base address ?

>
>Thanks,
>Rick
>
>
>> +   void __iomem *plmt; /* plmt base address */
>> +#endif
>>  #if CONFIG_IS_ENABLED(SMP)
>> struct ipi_data ipi[CONFIG_NR_CPUS];  #endif diff --git
>> a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c
>> index cec86718c7..7c50c46d9e 100644
>> --- a/drivers/timer/andes_plmt_timer.c
>> +++ b/drivers/timer/andes_plmt_timer.c
>> @@ -13,11 +13,12 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>
>>  /* mtime register */
>>  #define MTIME_REG(base)((ulong)(base))
>>
>> -static u64 andes_plmt_get_count(struct udevice *dev)
>> +static u64 notrace andes_plmt_get_count(struct udevice *dev)
>>  {
>> ret

RE: [PATCH] common/board_r: make sure to call initr_dm() before initr_trace()

[Pragnesh Patel]

Hi,

>-Original Message-
>From: Simon Glass 
>Sent: 17 November 2020 05:23
>To: Pragnesh Patel 
>Cc: Heinrich Schuchardt ; U-Boot Mailing List b...@lists.denx.de>
>Subject: Re: [PATCH] common/board_r: make sure to call initr_dm() before
>initr_trace()
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi,
>
>On Sun, 15 Nov 2020 at 05:16, Pragnesh Patel 
>wrote:
>>
>> Hi Heinrich,
>>
>> >-Original Message-----
>> >From: Heinrich Schuchardt 
>> >Sent: 12 November 2020 18:02
>> >To: Pragnesh Patel 
>> >Cc: U-Boot Mailing List ; Simon Glass
>> >
>> >Subject: Re: [PATCH] common/board_r: make sure to call initr_dm()
>> >before
>> >initr_trace()
>> >
>> >[External Email] Do not click links or attachments unless you
>> >recognize the sender and know the content is safe
>> >
>> >On 11/12/20 12:18 PM, Pragnesh Patel wrote:
>> >> Tracing need timer ticks and initr_dm() will make gd->timer and
>> >> gd->dm_root is equal to NULL, so make sure that initr_dm() to
>> >> call before tracing got enabled.
>> >>
>> >> Signed-off-by: Pragnesh Patel 
>> >> ---
>> >>  common/board_r.c | 6 +++---
>> >>  1 file changed, 3 insertions(+), 3 deletions(-)
>> >>
>> >> diff --git a/common/board_r.c b/common/board_r.c index
>> >> 29dd7d26d9..7140a39947 100644
>> >> --- a/common/board_r.c
>> >> +++ b/common/board_r.c
>> >> @@ -693,6 +693,9 @@ static int run_main_loop(void)
>> >>   * TODO: perhaps reset the watchdog in the initcall function after each 
>> >> call?
>> >>   */
>> >>  static init_fnc_t init_sequence_r[] = {
>> >> +#ifdef CONFIG_DM
>> >> + initr_dm,
>> >> +#endif
>> >>   initr_trace,
>> >>   initr_reloc,
>> >>   /* TODO: could x86/PPC have this also perhaps? */ @@ -718,9
>> >> +721,6 @@ static init_fnc_t init_sequence_r[] = {
>> >>   initr_noncached,
>> >>  #endif
>> >>   initr_of_live,
>> >> -#ifdef CONFIG_DM
>> >> - initr_dm,
>> >> -#endif
>> >
>> >You are moving initr_of_live before initr_of_live. I doubt this will
>> >work for boards that have CONFIG_OF_LIVE=y.
>>
>> yes you are right. It will not work for CONFIG_OF_LIVE.
>>
>> >
>> >Can't we move initr_trace down in the code to after both
>> >initr_of_live and initr_dm?
>> >
>> >@Simon:
>> >Please, advise.
>>
>> I am okay with this suggestion.
>
>Actually can we use the early timer for this case?
>
>DM init is a part of U-Boot and not being able to trace it would be 
>unfortunate.

Got it.

If someone wants to use tracing without TIMER_EARLY then

- initr_dm() will make gd->dm_root = NULL; and gd->timer = NULL; and
__cyg_profile_func_enter () will call timer_get_us() -> get_ticks() -> 
dm_timer_init().

dm_timer_init() will not able to initialize timer and return an error.

We need to find any solution for this.

>
>Regards,
>Simon

RE: [PATCH] common/board_r: make sure to call initr_dm() before initr_trace()

[Pragnesh Patel]

Hi Heinrich,

>-Original Message-
>From: Heinrich Schuchardt 
>Sent: 12 November 2020 18:02
>To: Pragnesh Patel 
>Cc: U-Boot Mailing List ; Simon Glass
>
>Subject: Re: [PATCH] common/board_r: make sure to call initr_dm() before
>initr_trace()
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On 11/12/20 12:18 PM, Pragnesh Patel wrote:
>> Tracing need timer ticks and initr_dm() will make gd->timer and
>> gd->dm_root is equal to NULL, so make sure that initr_dm() to
>> call before tracing got enabled.
>>
>> Signed-off-by: Pragnesh Patel 
>> ---
>>  common/board_r.c | 6 +++---
>>  1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/common/board_r.c b/common/board_r.c index
>> 29dd7d26d9..7140a39947 100644
>> --- a/common/board_r.c
>> +++ b/common/board_r.c
>> @@ -693,6 +693,9 @@ static int run_main_loop(void)
>>   * TODO: perhaps reset the watchdog in the initcall function after each 
>> call?
>>   */
>>  static init_fnc_t init_sequence_r[] = {
>> +#ifdef CONFIG_DM
>> + initr_dm,
>> +#endif
>>   initr_trace,
>>   initr_reloc,
>>   /* TODO: could x86/PPC have this also perhaps? */ @@ -718,9
>> +721,6 @@ static init_fnc_t init_sequence_r[] = {
>>   initr_noncached,
>>  #endif
>>   initr_of_live,
>> -#ifdef CONFIG_DM
>> - initr_dm,
>> -#endif
>
>You are moving initr_of_live before initr_of_live. I doubt this will work for 
>boards
>that have CONFIG_OF_LIVE=y.

yes you are right. It will not work for CONFIG_OF_LIVE.

>
>Can't we move initr_trace down in the code to after both initr_of_live and
>initr_dm?
>
>@Simon:
>Please, advise.

I am okay with this suggestion.

>
>Best regards
>
>Heinrich
>
>>  #if defined(CONFIG_ARM) || defined(CONFIG_NDS32) ||
>defined(CONFIG_RISCV) || \
>>   defined(CONFIG_SANDBOX)
>>   board_init, /* Setup chipselects */
>>

RE: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing

[Pragnesh Patel]

Hi Rick,

>-Original Message-
>From: Rick Chen 
>Sent: 13 November 2020 13:37
>To: Pragnesh Patel 
>Cc: U-Boot Mailing List ; Atish Patra
>; palmerdabb...@google.com; Bin Meng
>; Paul Walmsley ( Sifive) ;
>Anup Patel ; Sagar Kadam
>; Sean Anderson ; rick
>; Alan Kao ; Leo Liang
>
>Subject: Re: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh
>
>> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
>> Sent: Wednesday, November 11, 2020 6:15 PM
>> To: u-boot@lists.denx.de
>> Cc: atish.pa...@wdc.com; palmerdabb...@google.com;
>bmeng...@gmail.com;
>> paul.walms...@sifive.com; anup.pa...@wdc.com; sagar.ka...@sifive.com;
>> Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; Sean Anderson; Heinrich
>> Schuchardt; Simon Glass
>> Subject: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing
>>
>> Add timer_get_us() which is useful for tracing.
>> For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide a timer ticks
>> and For M-mode U-Boot, mtime register will provide the same.
>>
>> Signed-off-by: Pragnesh Patel 
>> ---
>>
>> Changes in v3:
>> - Added gd->arch.plmt in global data
>> - For timer_get_us(), use readq() instead of andes_plmt_get_count()
>>   and sifive_clint_get_count()
>>
>> Changes in v2:
>> - Added timer_get_us() in riscv_timer.c, sifive_clint_timer.c
>>   and andes_plmt_timer.c.
>>
>>
>>  arch/riscv/include/asm/global_data.h |  3 +++
>>  drivers/timer/andes_plmt_timer.c | 19 ++-
>>  drivers/timer/riscv_timer.c  | 14 +-
>>  drivers/timer/sifive_clint_timer.c   | 19 ++-
>>  4 files changed, 52 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/riscv/include/asm/global_data.h
>> b/arch/riscv/include/asm/global_data.h
>> index d3a0b1d221..4e22ceb83f 100644
>> --- a/arch/riscv/include/asm/global_data.h
>> +++ b/arch/riscv/include/asm/global_data.h
>> @@ -24,6 +24,9 @@ struct arch_global_data {  #ifdef CONFIG_ANDES_PLIC
>> void __iomem *plic; /* plic base address */
>>  #endif
>> +#ifdef CONFIG_ANDES_PLMT
>
>It shall be CONFIG_ANDES_PLMT, or it will compile fail as below:
>
>drivers/timer/andes_plmt_timer.c: In function 'timer_get_us':
>drivers/timer/andes_plmt_timer.c:36:15: error: 'struct arch_global_data' has no
>member named 'plmt'; did you mean 'plic'?
>  if (gd->arch.plmt) {
>   ^~~~
>   plic
>drivers/timer/andes_plmt_timer.c:37:52: error: 'struct arch_global_data' has no
>member named 'plmt'; did you mean 'plic'?
>   ticks = readq((void __iomem *)MTIME_REG(gd->arch.plmt));

No I did not get this. Why are you getting this error because plmt is already 
defined ?

>
>And it is not proper to have dependency of data structure between
>/arch/riscv/include/asm/* and /drivers/timer/* Maybe enable TIMER_EARLY and
>use timer_get_us() of /lib/time.c will be better.
>I also found that without dm_timer_init() in initf_dm(),
>andes_plmt_get_count() will be executed ahead of andes_plmt_probe().

Thanks Rick but me and Heinrich are working on different approach to use 
existing dm_timer_init() from lib/time.c

https://patchwork.ozlabs.org/project/uboot/patch/20201112071411.4202-1-xypron.g...@gmx.de/

>
>Thanks,
>Rick
>
>
>> +   void __iomem *plmt; /* plmt base address */
>> +#endif
>>  #if CONFIG_IS_ENABLED(SMP)
>> struct ipi_data ipi[CONFIG_NR_CPUS];  #endif diff --git
>> a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c
>> index cec86718c7..7c50c46d9e 100644
>> --- a/drivers/timer/andes_plmt_timer.c
>> +++ b/drivers/timer/andes_plmt_timer.c
>> @@ -13,11 +13,12 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>
>>  /* mtime register */
>>  #define MTIME_REG(base)((ulong)(base))
>>
>> -static u64 andes_plmt_get_count(struct udevice *dev)
>> +static u64 notrace andes_plmt_get_count(struct udevice *dev)
>>  {
>> return readq((void __iomem *)MTIME_REG(dev->priv));  } @@
>> -26,12 +27,28 @@ static const struct timer_ops andes_plmt_ops = {
>> .get_count = andes_plmt_get_count,  };
>>
>> +#if CONFIG_IS_ENABLED(RISCV_MMODE)
>> +unsigned long notrace timer_get_us(void) {
>> +   u64 ticks;
>> +
>> +   /* FIXME: gd->arch.plmt should contain valid base address */
>> +   if (gd->arch.plmt) {
>> +   ticks = readq((void _

[PATCH v3 2/2] riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller

[Pragnesh Patel]

Enable support for SiFive FU540 Opencores I2C master controller.

Signed-off-by: Pragnesh Patel 
Reviewed-by: Rick Chen 
---

(no changes since v1)

 arch/riscv/cpu/fu540/Kconfig | 2 ++
 board/sifive/fu540/Kconfig   | 1 +
 2 files changed, 3 insertions(+)

diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
index ac3f183342..61bd5c426e 100644
--- a/arch/riscv/cpu/fu540/Kconfig
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -35,6 +35,8 @@ config SIFIVE_FU540
imply SIFIVE_OTP
imply DM_PWM
imply PWM_SIFIVE
+   imply DM_I2C
+   imply SYS_I2C_OCORES
 
 if ENV_IS_IN_SPI_FLASH
 
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index e70d1e53f9..64fdbd44b4 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -47,5 +47,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply SPI_FLASH_ISSI
imply SYSRESET
imply SYSRESET_GPIO
+   imply CMD_I2C
 
 endif
-- 
2.17.1

[PATCH v3 1/2] i2c: ocores: add i2c driver for OpenCores I2C controller

[Pragnesh Patel]

Add support for the OpenCores I2C controller IP core
(See http://www.opencores.org/projects.cgi/web/i2c/overview).

This driver implementation is inspired from the Linux OpenCores
I2C driver available.

Thanks to Peter Korsgaard  for writing Linux
OpenCores I2C driver.

Signed-off-by: Pragnesh Patel 
Reviewed-by: Rick Chen 
---

Changes in v3:
- Rebase to master and add missing #include 

Changes in v2:
- Remove TYPE_SIFIVE_REV0 flag
- Update the Opencores I2C Controller Link

 drivers/i2c/Kconfig  |   7 +
 drivers/i2c/Makefile |   1 +
 drivers/i2c/ocores_i2c.c | 637 +++
 3 files changed, 645 insertions(+)
 create mode 100644 drivers/i2c/ocores_i2c.c

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 8ae54e1e93..37958083af 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -342,6 +342,13 @@ config SYS_I2C_NEXELL
  have several I2C ports and all are provided, controlled by the
  device tree.
 
+config SYS_I2C_OCORES
+   bool "ocores I2C driver"
+   depends on DM_I2C
+   help
+ Add support for ocores I2C controller. For details see
+ https://opencores.org/projects/i2c
+
 config SYS_I2C_OMAP24XX
bool "TI OMAP2+ I2C driver"
depends on ARCH_OMAP2PLUS || ARCH_K3
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index b37198036c..1aac5c481e 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o
 obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
 obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
 obj-$(CONFIG_SYS_I2C_NEXELL) += nx_i2c.o
+obj-$(CONFIG_SYS_I2C_OCORES) += ocores_i2c.o
 obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o
 obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
 obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o
diff --git a/drivers/i2c/ocores_i2c.c b/drivers/i2c/ocores_i2c.c
new file mode 100644
index 00..c4f2cc43f9
--- /dev/null
+++ b/drivers/i2c/ocores_i2c.c
@@ -0,0 +1,637 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ocores-i2c.c: I2C bus driver for OpenCores I2C controller
+ * (https://opencores.org/projects/i2c)
+ *
+ * (C) Copyright Peter Korsgaard 
+ *
+ * Copyright (C) 2020 SiFive, Inc.
+ * Pragnesh Patel 
+ *
+ * Support for the GRLIB port of the controller by
+ * Andreas Larsson 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* registers */
+#define OCI2C_PRELOW   0
+#define OCI2C_PREHIGH  1
+#define OCI2C_CONTROL  2
+#define OCI2C_DATA 3
+#define OCI2C_CMD  4 /* write only */
+#define OCI2C_STATUS   4 /* read only, same address as OCI2C_CMD */
+
+#define OCI2C_CTRL_IEN 0x40
+#define OCI2C_CTRL_EN  0x80
+
+#define OCI2C_CMD_START0x91
+#define OCI2C_CMD_STOP 0x41
+#define OCI2C_CMD_READ 0x21
+#define OCI2C_CMD_WRITE0x11
+#define OCI2C_CMD_READ_ACK 0x21
+#define OCI2C_CMD_READ_NACK0x29
+#define OCI2C_CMD_IACK 0x01
+
+#define OCI2C_STAT_IF  0x01
+#define OCI2C_STAT_TIP 0x02
+#define OCI2C_STAT_ARBLOST 0x20
+#define OCI2C_STAT_BUSY0x40
+#define OCI2C_STAT_NACK0x80
+
+#define STATE_DONE 0
+#define STATE_START1
+#define STATE_WRITE2
+#define STATE_READ 3
+#define STATE_ERROR4
+
+#define TYPE_OCORES0
+#define TYPE_GRLIB 1
+
+#define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */
+
+struct ocores_i2c_bus {
+   void __iomem *base;
+   u32 reg_shift;
+   u32 reg_io_width;
+   unsigned long flags;
+   struct i2c_msg *msg;
+   int pos;
+   int nmsgs;
+   int state; /* see STATE_ */
+   struct clk clk;
+   int ip_clk_khz;
+   int bus_clk_khz;
+   void (*setreg)(struct ocores_i2c_bus *i2c, int reg, u8 value);
+   u8 (*getreg)(struct ocores_i2c_bus *i2c, int reg);
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Boolean attribute values */
+enum {
+   FALSE = 0,
+   TRUE,
+};
+
+static void oc_setreg_8(struct ocores_i2c_bus *i2c, int reg, u8 value)
+{
+   writeb(value, i2c->base + (reg << i2c->reg_shift));
+}
+
+static void oc_setreg_16(struct ocores_i2c_bus *i2c, int reg, u8 value)
+{
+   writew(value, i2c->base + (reg << i2c->reg_shift));
+}
+
+static void oc_setreg_32(struct ocores_i2c_bus *i2c, int reg, u8 value)
+{
+   writel(value, i2c->base + (reg << i2c->reg_shift));
+}
+
+static void oc_setreg_16be(struct ocores_i2c_bus *i2c, int reg, u8 value)
+{
+   out_be16(i2c->base + (reg << i2c->reg_shift), value);
+}
+
+static void oc_setreg_32be(struct ocores_i2c_bus *i2c, int reg, u8 value)
+{
+   out_be32(i2c->base + (reg << i2c->reg_shift), value);
+}
+
+static inline u8 oc_getreg_8(struct ocores_i2c_bus *i2c, int

[PATCH v3 0/2] Add OpenCores I2C controller driver

[Pragnesh Patel]

This driver has been tested on HiFive Unleashed with a PMOD based
RTCC sensor connected to I2C pins J1 header of the board.

This series is available here [1] for testing
[1] https://github.com/pragnesh26992/u-boot/tree/i2c

Tested-by: Sagar Shrikant Kadam 

Changes in v3:
- Rebase to master and add missing #include 

Changes in v2:
- Remove TYPE_SIFIVE_REV0 flag
- Update the Opencores I2C Controller Link

U-Boot Logs for reference:

Hit any key to stop autoboot:  0
=> i2c dev 0
Setting bus to 0
=> i2c probe
Valid chip addresses: 57 6F
=> i2c md 0x57 0x0 1
: a5.
=> i2c mw 0x57 0x0 0x5a 1
=> i2c md 0x57 0x0 1
: 5aZ
=> i2c md 0x57 0x2 1
0002: 99.
=> i2c mw 0x57 0x2 0xa9 1
=> i2c md 0x57 0x2 1
0002: a9.
=> i2c md 0x6f 0x20 1
0020: 5aZ
=> i2c md 0x6f 0x5f 1
005f: a5.
=> i2c mw 0x6f 0x20 0xa9 1
=> i2c mw 0x6f 0x5f 0xa9 1
=> i2c md 0x6f 0x20 1
0020: a9.
=> i2c md 0x6f 0x5f 1
005f: a9.
=>

Pragnesh Patel (2):
  i2c: ocores: add i2c driver for OpenCores I2C controller
  riscv: sifive/fu540: kconfig: Enable support for Opencores I2C
controller

 arch/riscv/cpu/fu540/Kconfig |   2 +
 board/sifive/fu540/Kconfig   |   1 +
 drivers/i2c/Kconfig  |   7 +
 drivers/i2c/Makefile |   1 +
 drivers/i2c/ocores_i2c.c | 637 +++
 5 files changed, 648 insertions(+)
 create mode 100644 drivers/i2c/ocores_i2c.c

-- 
2.17.1

RE: [PATCH v2 1/2] i2c: ocores: add i2c driver for OpenCores I2C controller

[Pragnesh Patel]

Hi Rick,

>-Original Message-
>From: Rick Chen 
>Sent: 13 November 2020 12:47
>To: Pragnesh Patel 
>Cc: U-Boot Mailing List ; Atish Patra
>; palmerdabb...@google.com; Bin Meng
>; Paul Walmsley ( Sifive) ;
>Anup Patel ; Sagar Kadam
>; rick ; Alan Kao
>; Leo Liang 
>Subject: Re: [PATCH v2 1/2] i2c: ocores: add i2c driver for OpenCores I2C
>controller
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh
>
>> > From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
>> > Sent: Thursday, October 22, 2020 2:55 PM
>> > To: u-boot@lists.denx.de
>> > Cc: atish.pa...@wdc.com; palmerdabb...@google.com;
>> > bmeng...@gmail.com; paul.walms...@sifive.com; anup.pa...@wdc.com;
>> > sagar.ka...@sifive.com; Rick Jian-Zhi Chen(陳建志);
>> > pe...@korsgaard.com; Pragnesh Patel; Heiko Schocher
>> > Subject: [PATCH v2 1/2] i2c: ocores: add i2c driver for OpenCores
>> > I2C controller
>> >
>> > Add support for the OpenCores I2C controller IP core (See
>> > http://www.opencores.org/projects.cgi/web/i2c/overview).
>> >
>> > This driver implementation is inspired from the Linux OpenCores I2C
>> > driver available.
>> >
>> > Thanks to Peter Korsgaard  for writing Linux
>> > OpenCores I2C driver.
>> >
>> > Signed-off-by: Pragnesh Patel 
>> > ---
>> >
>> > Changes in v2:
>> > - Remove TYPE_SIFIVE_REV0 flag
>> > - Update the Opencores I2C Controller Link
>> >
>> >  drivers/i2c/Kconfig  |   7 +
>> >  drivers/i2c/Makefile |   1 +
>> >  drivers/i2c/ocores_i2c.c | 636
>> > +++
>> >  3 files changed, 644 insertions(+)
>> >  create mode 100644 drivers/i2c/ocores_i2c.c
>> >
>>
>> Reviewed-by: Rick Chen 
>
>Please check the CI failure item:
>https://travis-ci.org/github/rickchen36/u-boot-riscv/jobs/743114190
>
>+drivers/i2c/ocores_i2c.c: In function 'ocores_i2c_probe':
>1291+drivers/i2c/ocores_i2c.c:523:4: error: implicit declaration of
>function 'dev_err' [-Werror=implicit-function-declaration]
>1292+  523 |dev_err(dev,
>1293+  |^~~
>1294+drivers/i2c/ocores_i2c.c:528:4: error: implicit declaration of
>function 'dev_warn' [-Werror=implicit-function-declaration]
>1295+  528 |dev_warn(dev,
>1296+  |^~~~
>1297+cc1: all warnings being treated as errors
>
>Thanks,
>Rick

Will rebase and send it again.

RE: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing

[Pragnesh Patel]

>-Original Message-
>From: U-Boot  On Behalf Of Pragnesh Patel
>Sent: 12 November 2020 13:06
>To: Heinrich Schuchardt ; Simon Glass
>
>Cc: atish.pa...@wdc.com; palmerdabb...@google.com; u-boot@lists.denx.de;
>bmeng...@gmail.com; Paul Walmsley ( Sifive) ;
>anup.pa...@wdc.com; Sagar Kadam ;
>r...@andestech.com; Sean Anderson 
>Subject: RE: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing
>
>Hi Heinrich,
>
>>-Original Message-
>>From: Heinrich Schuchardt 
>>Sent: 12 November 2020 12:49
>>To: Pragnesh Patel ; Simon Glass
>>
>>Cc: atish.pa...@wdc.com; palmerdabb...@google.com;
>>u-boot@lists.denx.de; bmeng...@gmail.com; Paul Walmsley ( Sifive)
>>; anup.pa...@wdc.com; Sagar Kadam
>>; r...@andestech.com; Sean Anderson
>>
>>Subject: Re: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing
>>
>>[External Email] Do not click links or attachments unless you recognize
>>the sender and know the content is safe
>>
>>On 11/12/20 8:09 AM, Heinrich Schuchardt wrote:
>>> On 11/12/20 7:34 AM, Pragnesh Patel wrote:
>>>> Hi Heinrich,
>>>>
>>>>> -Original Message-
>>>>> From: Heinrich Schuchardt 
>>>>> Sent: 11 November 2020 19:18
>>>>> To: Pragnesh Patel 
>>>>> Cc: atish.pa...@wdc.com; palmerdabb...@google.com;
>>>>> u-boot@lists.denx.de; bmeng...@gmail.com; Paul Walmsley ( Sifive)
>>>>> ; anup.pa...@wdc.com; Sagar Kadam
>>>>> ; r...@andestech.com; Sean Anderson
>>>>> ; Simon Glass 
>>>>> Subject: Re: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing
>>>>>
>>>>> [External Email] Do not click links or attachments unless you
>>>>> recognize the sender and know the content is safe
>>>>>
>>>>> On 11/11/20 12:56 PM, Pragnesh Patel wrote:
>>>>>> Hi Heinrich,
>>>>>>
>>>>>>> -Original Message-
>>>>>>> From: Heinrich Schuchardt 
>>>>>>> Sent: 11 November 2020 16:51
>>>>>>> To: Pragnesh Patel ;
>>>>>>> u-boot@lists.denx.de
>>>>>>> Cc: atish.pa...@wdc.com; palmerdabb...@google.com;
>>>>>>> bmeng...@gmail.com; Paul Walmsley ( Sifive)
>>>>>>> ; anup.pa...@wdc.com; Sagar Kadam
>>>>>>> ; r...@andestech.com; Sean Anderson
>>>>>>> ; Simon Glass 
>>>>>>> Subject: Re: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing
>>>>>>>
>>>>>>> [External Email] Do not click links or attachments unless you
>>>>>>> recognize the sender and know the content is safe
>>>>>>>
>>>>>>> On 11.11.20 11:14, Pragnesh Patel wrote:
>>>>>>>> Add timer_get_us() which is useful for tracing.
>>>>>>>> For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide a timer
>>>>>>>> ticks and For M-mode U-Boot, mtime register will provide the same.
>>>>>>>>
>>>>>>>> Signed-off-by: Pragnesh Patel 
>>>>>>>
>>>>>>> The default implementation of get_timer_us() in lib/time.c calls
>>>>>>> get_ticks() which calls timer_get_count(). The get_count()
>>>>>>> operation is implemented in drivers/timer/andes_plmt_timer.c,
>>>>>>> drivers/timer/sifive_clint_timer.c, drivers/timer/riscv_timer.c.
>>>>>>>
>>>>>>> Why do you need special timer_get_us() implementations?
>>>>>>> Isn't it enough to supply the get_count() operation in the drivers?
>>>>>>
>>>>>> get_ticks() is depend on gd->timer and there are 2 cases
>>>>>>
>>>>>> 1) if gd->timer== NULL then dm_timer_init() gets called and it
>>>>>> will call functions which are not marked with "notrace" so tracing got
>stuck.
>>>>>
>>>>> Thanks for the background information.
>>>>>
>>>>> Please, identify the existing functions that lack "notrace" and fix
>>>>> them. This will give us a solution for all existing boards and not
>>>>> for a small
>>selection.
>>>>> Furthermore it will avoid code duplication.
>>>>
>>>> I tried but There are so many functions which need "notrace".
>>>
>>> Let's start with

RE: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing

[Pragnesh Patel]

Hi Heinrich,

>-Original Message-
>From: Heinrich Schuchardt 
>Sent: 12 November 2020 12:49
>To: Pragnesh Patel ; Simon Glass
>
>Cc: atish.pa...@wdc.com; palmerdabb...@google.com; u-boot@lists.denx.de;
>bmeng...@gmail.com; Paul Walmsley ( Sifive) ;
>anup.pa...@wdc.com; Sagar Kadam ;
>r...@andestech.com; Sean Anderson 
>Subject: Re: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On 11/12/20 8:09 AM, Heinrich Schuchardt wrote:
>> On 11/12/20 7:34 AM, Pragnesh Patel wrote:
>>> Hi Heinrich,
>>>
>>>> -Original Message-
>>>> From: Heinrich Schuchardt 
>>>> Sent: 11 November 2020 19:18
>>>> To: Pragnesh Patel 
>>>> Cc: atish.pa...@wdc.com; palmerdabb...@google.com;
>>>> u-boot@lists.denx.de; bmeng...@gmail.com; Paul Walmsley ( Sifive)
>>>> ; anup.pa...@wdc.com; Sagar Kadam
>>>> ; r...@andestech.com; Sean Anderson
>>>> ; Simon Glass 
>>>> Subject: Re: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing
>>>>
>>>> [External Email] Do not click links or attachments unless you
>>>> recognize the sender and know the content is safe
>>>>
>>>> On 11/11/20 12:56 PM, Pragnesh Patel wrote:
>>>>> Hi Heinrich,
>>>>>
>>>>>> -Original Message-
>>>>>> From: Heinrich Schuchardt 
>>>>>> Sent: 11 November 2020 16:51
>>>>>> To: Pragnesh Patel ;
>>>>>> u-boot@lists.denx.de
>>>>>> Cc: atish.pa...@wdc.com; palmerdabb...@google.com;
>>>>>> bmeng...@gmail.com; Paul Walmsley ( Sifive)
>>>>>> ; anup.pa...@wdc.com; Sagar Kadam
>>>>>> ; r...@andestech.com; Sean Anderson
>>>>>> ; Simon Glass 
>>>>>> Subject: Re: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing
>>>>>>
>>>>>> [External Email] Do not click links or attachments unless you
>>>>>> recognize the sender and know the content is safe
>>>>>>
>>>>>> On 11.11.20 11:14, Pragnesh Patel wrote:
>>>>>>> Add timer_get_us() which is useful for tracing.
>>>>>>> For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide a timer
>>>>>>> ticks and For M-mode U-Boot, mtime register will provide the same.
>>>>>>>
>>>>>>> Signed-off-by: Pragnesh Patel 
>>>>>>
>>>>>> The default implementation of get_timer_us() in lib/time.c calls
>>>>>> get_ticks() which calls timer_get_count(). The get_count()
>>>>>> operation is implemented in drivers/timer/andes_plmt_timer.c,
>>>>>> drivers/timer/sifive_clint_timer.c, drivers/timer/riscv_timer.c.
>>>>>>
>>>>>> Why do you need special timer_get_us() implementations?
>>>>>> Isn't it enough to supply the get_count() operation in the drivers?
>>>>>
>>>>> get_ticks() is depend on gd->timer and there are 2 cases
>>>>>
>>>>> 1) if gd->timer== NULL then dm_timer_init() gets called and it will
>>>>> call functions which are not marked with "notrace" so tracing got stuck.
>>>>
>>>> Thanks for the background information.
>>>>
>>>> Please, identify the existing functions that lack "notrace" and fix
>>>> them. This will give us a solution for all existing boards and not for a 
>>>> small
>selection.
>>>> Furthermore it will avoid code duplication.
>>>
>>> I tried but There are so many functions which need "notrace".
>>
>> Let's start with the problem statement:
>>
>> When tracing functions is enabled this adds calls to
>> __cyg_profile_func_enter() and __cyg_profile_func_exit() to the traced
>> functions.
>>
>> __cyg_profile_func_exit() and __cyg_profile_func_exit() invoke
>> timer_get_us() to record the entry and exit time.
>>
>> If timer_get_us() or any function used to implement does not carry
>> __attribute__((no_instrument_function)) this will lead to an
>> indefinite recursion.
>>
>> We have to change __cyg_profile_func_enter() and
>> __cyg_profile_func_exit() such that during their execution no function
>> is traced. We can do so by temporarily setting trace_enabled to false.
>>
>> Does this match

RE: [PATCH 1/1] trace: avoid infinite recursion

[Pragnesh Patel]

Hi Heinrich,

>-Original Message-
>From: Heinrich Schuchardt 
>Sent: 12 November 2020 12:44
>To: Simon Glass 
>Cc: Pragnesh Patel ; u-boot@lists.denx.de;
>Heinrich Schuchardt 
>Subject: [PATCH 1/1] trace: avoid infinite recursion
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>When tracing functions is enabled this adds calls to
>__cyg_profile_func_enter() and __cyg_profile_func_exit() to the traced 
>functions.
>
>__cyg_profile_func_exit() and __cyg_profile_func_exit() invoke

Replace one of __cyg_profile_func_exit() with __cyg_profile_func_enter()

>timer_get_us() to record the entry and exit time.
>
>If timer_get_us() or any function used to implement does not carry
>__attribute__((no_instrument_function)) this will lead to an indefinite 
>recursion.
>
>The patch changes __cyg_profile_func_enter() and
>__cyg_profile_func_exit() such that during their execution no function is 
>traced
>by temporarily setting trace_enabled to false.
>
>Reported-by: Pragnesh Patel 
>Signed-off-by: Heinrich Schuchardt 
>---
> lib/trace.c | 10 ++
> 1 file changed, 10 insertions(+)
>
>diff --git a/lib/trace.c b/lib/trace.c
>index defc9716d8..b84b9fbfef 100644
>--- a/lib/trace.c
>+++ b/lib/trace.c
>@@ -141,9 +141,12 @@ static void __attribute__((no_instrument_function))
>add_textbase(void)  void __attribute__((no_instrument_function))
>__cyg_profile_func_enter(
>void *func_ptr, void *caller)  {
>+


No need for new line

>if (trace_enabled) {
>int func;
>+   char trace_enabled_old = trace_enabled;
>
>+   trace_enabled = 0;
>trace_swap_gd();
>add_ftrace(func_ptr, caller, FUNCF_ENTRY);
>func = func_ptr_to_num(func_ptr); @@ -157,6 +160,7 @@ void
>__attribute__((no_instrument_function)) __cyg_profile_func_enter(
>if (hdr->depth > hdr->depth_limit)
>hdr->max_depth = hdr->depth;
>trace_swap_gd();
>+   trace_enabled = trace_enabled_old;
>}
> }
>
>@@ -169,11 +173,17 @@ void __attribute__((no_instrument_function))
>__cyg_profile_func_enter(  void __attribute__((no_instrument_function))
>__cyg_profile_func_exit(
>void *func_ptr, void *caller)  {
>+   trace_enabled

Is this necessary ?

>+
>if (trace_enabled) {
>+   char trace_enabled_old = trace_enabled;
>+
>+   trace_enabled = 0;
>trace_swap_gd();
>add_ftrace(func_ptr, caller, FUNCF_EXIT);
>hdr->depth--;
>trace_swap_gd();
>+   trace_enabled = trace_enabled_old;
>}
> }
>
>--
>2.28.0

RE: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing

[Pragnesh Patel]

Hi Heinrich,

>-Original Message-
>From: Heinrich Schuchardt 
>Sent: 11 November 2020 19:18
>To: Pragnesh Patel 
>Cc: atish.pa...@wdc.com; palmerdabb...@google.com; u-boot@lists.denx.de;
>bmeng...@gmail.com; Paul Walmsley ( Sifive) ;
>anup.pa...@wdc.com; Sagar Kadam ;
>r...@andestech.com; Sean Anderson ; Simon Glass
>
>Subject: Re: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On 11/11/20 12:56 PM, Pragnesh Patel wrote:
>> Hi Heinrich,
>>
>>> -Original Message-
>>> From: Heinrich Schuchardt 
>>> Sent: 11 November 2020 16:51
>>> To: Pragnesh Patel ;
>>> u-boot@lists.denx.de
>>> Cc: atish.pa...@wdc.com; palmerdabb...@google.com;
>>> bmeng...@gmail.com; Paul Walmsley ( Sifive)
>>> ; anup.pa...@wdc.com; Sagar Kadam
>>> ; r...@andestech.com; Sean Anderson
>>> ; Simon Glass 
>>> Subject: Re: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing
>>>
>>> [External Email] Do not click links or attachments unless you
>>> recognize the sender and know the content is safe
>>>
>>> On 11.11.20 11:14, Pragnesh Patel wrote:
>>>> Add timer_get_us() which is useful for tracing.
>>>> For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide a timer ticks
>>>> and For M-mode U-Boot, mtime register will provide the same.
>>>>
>>>> Signed-off-by: Pragnesh Patel 
>>>
>>> The default implementation of get_timer_us() in lib/time.c calls
>>> get_ticks() which calls timer_get_count(). The get_count() operation
>>> is implemented in drivers/timer/andes_plmt_timer.c,
>>> drivers/timer/sifive_clint_timer.c, drivers/timer/riscv_timer.c.
>>>
>>> Why do you need special timer_get_us() implementations?
>>> Isn't it enough to supply the get_count() operation in the drivers?
>>
>> get_ticks() is depend on gd->timer and there are 2 cases
>>
>> 1) if gd->timer== NULL then dm_timer_init() gets called and it will
>> call functions which are not marked with "notrace" so tracing got stuck.
>
>Thanks for the background information.
>
>Please, identify the existing functions that lack "notrace" and fix them. This 
>will
>give us a solution for all existing boards and not for a small selection.
>Furthermore it will avoid code duplication.

I tried but There are so many functions which need "notrace".

Why don’t we consider removing gd->timer=NULL in initr_dm()
initr_dm()
{
#ifdef CONFIG_TIMER
 gd->timer = NULL;
#endif
}

Or I can use TIMER_EARLY and return ticks and rate  by adding 
timer_early_get_count()
and timer_early_get_rate() repectively.

Suggestions are welcome

>
>In lib/trace.c consider replacing
>"__attribute__((no_instrument_function))" by "notrace".
>
>Best regards
>
>Heinrich
>
>>
>> 2) if gd->timer is already initialized then still initr_dm() will make
>> gd->timer = NULL;
>>
>> initr_dm()
>> {
>> #ifdef CONFIG_TIMER
>>  gd->timer = NULL;
>> #endif
>> }
>>
>> So again dm_timer_init() gets called and tracing got stuck.
>>
>> So I thought better to implement timer_get_us().
>>
>>>
>>> Best regards
>>>
>>> Heinrich
>>>
>>>> ---
>>>>
>>>> Changes in v3:
>>>> - Added gd->arch.plmt in global data
>>>> - For timer_get_us(), use readq() instead of andes_plmt_get_count()
>>>>and sifive_clint_get_count()
>>>>
>>>> Changes in v2:
>>>> - Added timer_get_us() in riscv_timer.c, sifive_clint_timer.c
>>>>and andes_plmt_timer.c.
>>>>
>>>>
>>>>   arch/riscv/include/asm/global_data.h |  3 +++
>>>>   drivers/timer/andes_plmt_timer.c | 19 ++-
>>>>   drivers/timer/riscv_timer.c  | 14 +-
>>>>   drivers/timer/sifive_clint_timer.c   | 19 ++-
>>>>   4 files changed, 52 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/arch/riscv/include/asm/global_data.h
>>>> b/arch/riscv/include/asm/global_data.h
>>>> index d3a0b1d221..4e22ceb83f 100644
>>>> --- a/arch/riscv/include/asm/global_data.h
>>>> +++ b/arch/riscv/include/asm/global_data.h
>>>> @@ -24,6 +24,9 @@ struct arch_global_data {  #ifdef CONFIG_ANDES_PLIC
>>>>void __iomem *plic

RE: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing

[Pragnesh Patel]

Hi Heinrich,

>-Original Message-
>From: Heinrich Schuchardt 
>Sent: 11 November 2020 16:51
>To: Pragnesh Patel ; u-boot@lists.denx.de
>Cc: atish.pa...@wdc.com; palmerdabb...@google.com; bmeng...@gmail.com;
>Paul Walmsley ( Sifive) ; anup.pa...@wdc.com;
>Sagar Kadam ; r...@andestech.com; Sean
>Anderson ; Simon Glass 
>Subject: Re: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On 11.11.20 11:14, Pragnesh Patel wrote:
>> Add timer_get_us() which is useful for tracing.
>> For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide a timer ticks
>> and For M-mode U-Boot, mtime register will provide the same.
>>
>> Signed-off-by: Pragnesh Patel 
>
>The default implementation of get_timer_us() in lib/time.c calls
>get_ticks() which calls timer_get_count(). The get_count() operation is
>implemented in drivers/timer/andes_plmt_timer.c,
>drivers/timer/sifive_clint_timer.c, drivers/timer/riscv_timer.c.
>
>Why do you need special timer_get_us() implementations?
>Isn't it enough to supply the get_count() operation in the drivers?

get_ticks() is depend on gd->timer and there are 2 cases

1) if gd->timer== NULL then dm_timer_init() gets called and it will call 
functions
which are not marked with "notrace" so tracing got stuck.

2) if gd->timer is already initialized then still initr_dm() will make 
gd->timer = NULL;

initr_dm()
{
#ifdef CONFIG_TIMER
gd->timer = NULL;
#endif
}

So again dm_timer_init() gets called and tracing got stuck.

So I thought better to implement timer_get_us().

>
>Best regards
>
>Heinrich
>
>> ---
>>
>> Changes in v3:
>> - Added gd->arch.plmt in global data
>> - For timer_get_us(), use readq() instead of andes_plmt_get_count()
>>   and sifive_clint_get_count()
>>
>> Changes in v2:
>> - Added timer_get_us() in riscv_timer.c, sifive_clint_timer.c
>>   and andes_plmt_timer.c.
>>
>>
>>  arch/riscv/include/asm/global_data.h |  3 +++
>>  drivers/timer/andes_plmt_timer.c | 19 ++-
>>  drivers/timer/riscv_timer.c  | 14 +-
>>  drivers/timer/sifive_clint_timer.c   | 19 ++-
>>  4 files changed, 52 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/riscv/include/asm/global_data.h
>> b/arch/riscv/include/asm/global_data.h
>> index d3a0b1d221..4e22ceb83f 100644
>> --- a/arch/riscv/include/asm/global_data.h
>> +++ b/arch/riscv/include/asm/global_data.h
>> @@ -24,6 +24,9 @@ struct arch_global_data {  #ifdef CONFIG_ANDES_PLIC
>>   void __iomem *plic; /* plic base address */
>>  #endif
>> +#ifdef CONFIG_ANDES_PLMT
>> + void __iomem *plmt; /* plmt base address */
>> +#endif
>>  #if CONFIG_IS_ENABLED(SMP)
>>   struct ipi_data ipi[CONFIG_NR_CPUS];  #endif diff --git
>> a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c
>> index cec86718c7..7c50c46d9e 100644
>> --- a/drivers/timer/andes_plmt_timer.c
>> +++ b/drivers/timer/andes_plmt_timer.c
>> @@ -13,11 +13,12 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>
>>  /* mtime register */
>>  #define MTIME_REG(base)  ((ulong)(base))
>>
>> -static u64 andes_plmt_get_count(struct udevice *dev)
>> +static u64 notrace andes_plmt_get_count(struct udevice *dev)
>>  {
>>   return readq((void __iomem *)MTIME_REG(dev->priv));  } @@ -26,12
>> +27,28 @@ static const struct timer_ops andes_plmt_ops = {
>>   .get_count = andes_plmt_get_count,  };
>>
>> +#if CONFIG_IS_ENABLED(RISCV_MMODE)
>> +unsigned long notrace timer_get_us(void) {
>> + u64 ticks;
>> +
>> + /* FIXME: gd->arch.plmt should contain valid base address */
>> + if (gd->arch.plmt) {
>> + ticks = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
>> + do_div(ticks, CONFIG_SYS_HZ);
>> + }
>> +
>> + return ticks;
>> +}
>> +#endif
>> +
>>  static int andes_plmt_probe(struct udevice *dev)  {
>>   dev->priv = dev_read_addr_ptr(dev);
>>   if (!dev->priv)
>>   return -EINVAL;
>>
>> + gd->arch.plmt = dev->priv;
>>   return timer_timebase_fallback(dev);  }
>>
>> diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
>> index 21ae184057..7fa8773da3 100644
>> --- a/drivers/timer/riscv_timer.c
>> +++ b/drivers/timer/riscv_timer.c
>> @@ -15,8 +15,9 @@
>>

[PATCH v3 1/1] riscv: Add timer_get_us() for tracing

[Pragnesh Patel]

Add timer_get_us() which is useful for tracing.
For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide
a timer ticks and For M-mode U-Boot, mtime register will
provide the same.

Signed-off-by: Pragnesh Patel 
---

Changes in v3:
- Added gd->arch.plmt in global data
- For timer_get_us(), use readq() instead of andes_plmt_get_count()
  and sifive_clint_get_count()

Changes in v2:
- Added timer_get_us() in riscv_timer.c, sifive_clint_timer.c
  and andes_plmt_timer.c.


 arch/riscv/include/asm/global_data.h |  3 +++
 drivers/timer/andes_plmt_timer.c | 19 ++-
 drivers/timer/riscv_timer.c  | 14 +-
 drivers/timer/sifive_clint_timer.c   | 19 ++-
 4 files changed, 52 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/include/asm/global_data.h 
b/arch/riscv/include/asm/global_data.h
index d3a0b1d221..4e22ceb83f 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -24,6 +24,9 @@ struct arch_global_data {
 #ifdef CONFIG_ANDES_PLIC
void __iomem *plic; /* plic base address */
 #endif
+#ifdef CONFIG_ANDES_PLMT
+   void __iomem *plmt; /* plmt base address */
+#endif
 #if CONFIG_IS_ENABLED(SMP)
struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif
diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c
index cec86718c7..7c50c46d9e 100644
--- a/drivers/timer/andes_plmt_timer.c
+++ b/drivers/timer/andes_plmt_timer.c
@@ -13,11 +13,12 @@
 #include 
 #include 
 #include 
+#include 
 
 /* mtime register */
 #define MTIME_REG(base)((ulong)(base))
 
-static u64 andes_plmt_get_count(struct udevice *dev)
+static u64 notrace andes_plmt_get_count(struct udevice *dev)
 {
return readq((void __iomem *)MTIME_REG(dev->priv));
 }
@@ -26,12 +27,28 @@ static const struct timer_ops andes_plmt_ops = {
.get_count = andes_plmt_get_count,
 };
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+unsigned long notrace timer_get_us(void)
+{
+   u64 ticks;
+
+   /* FIXME: gd->arch.plmt should contain valid base address */
+   if (gd->arch.plmt) {
+   ticks = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
+   do_div(ticks, CONFIG_SYS_HZ);
+   }
+
+   return ticks;
+}
+#endif
+
 static int andes_plmt_probe(struct udevice *dev)
 {
dev->priv = dev_read_addr_ptr(dev);
if (!dev->priv)
return -EINVAL;
 
+   gd->arch.plmt = dev->priv;
return timer_timebase_fallback(dev);
 }
 
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 21ae184057..7fa8773da3 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -15,8 +15,9 @@
 #include 
 #include 
 #include 
+#include 
 
-static u64 riscv_timer_get_count(struct udevice *dev)
+static u64 notrace riscv_timer_get_count(struct udevice *dev)
 {
__maybe_unused u32 hi, lo;
 
@@ -31,6 +32,17 @@ static u64 riscv_timer_get_count(struct udevice *dev)
return ((u64)hi << 32) | lo;
 }
 
+#if CONFIG_IS_ENABLED(RISCV_SMODE)
+unsigned long notrace timer_get_us(void)
+{
+   u64 ticks;
+
+   ticks = riscv_timer_get_count(NULL);
+   do_div(ticks, CONFIG_SYS_HZ);
+   return ticks;
+}
+#endif
+
 static int riscv_timer_probe(struct udevice *dev)
 {
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
diff --git a/drivers/timer/sifive_clint_timer.c 
b/drivers/timer/sifive_clint_timer.c
index 00ce0f08d6..c341f7789b 100644
--- a/drivers/timer/sifive_clint_timer.c
+++ b/drivers/timer/sifive_clint_timer.c
@@ -10,11 +10,12 @@
 #include 
 #include 
 #include 
+#include 
 
 /* mtime register */
 #define MTIME_REG(base)((ulong)(base) + 0xbff8)
 
-static u64 sifive_clint_get_count(struct udevice *dev)
+static u64 notrace sifive_clint_get_count(struct udevice *dev)
 {
return readq((void __iomem *)MTIME_REG(dev->priv));
 }
@@ -23,12 +24,28 @@ static const struct timer_ops sifive_clint_ops = {
.get_count = sifive_clint_get_count,
 };
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+unsigned long notrace timer_get_us(void)
+{
+   u64 ticks;
+
+   /* FIXME: gd->arch.clint should contain valid base address */
+   if (gd->arch.clint) {
+   ticks = readq((void __iomem *)MTIME_REG(gd->arch.clint));
+   do_div(ticks, CONFIG_SYS_HZ);
+   }
+
+   return ticks;
+}
+#endif
+
 static int sifive_clint_probe(struct udevice *dev)
 {
dev->priv = dev_read_addr_ptr(dev);
if (!dev->priv)
return -EINVAL;
 
+   gd->arch.clint = dev->priv;
return timer_timebase_fallback(dev);
 }
 
-- 
2.17.1

[PATCH v3 0/1] RISC-V tracing support

[Pragnesh Patel]

This series add a support of tracing for RISC-V arch.

This series is also available here [1] for testing.
[1] https://github.com/pragnesh26992/u-boot/tree/trace

How to test this patch:
1) Enable tracing in "configs/sifive_fu540_defconfig"
CONFIG_TRACE=y
CONFIG_TRACE_BUFFER_SIZE=0x0100
CONFIG_TRACE_CALL_DEPTH_LIMIT=15
CONFIG_CMD_TRACE=y

2) make FTRACE=1 sifive_fu540_defconfig
3) make FTRACE=1

Changes in v3:
- Added gd->arch.plmt in global data
- For timer_get_us(), use readq() instead of andes_plmt_get_count()
  and sifive_clint_get_count()

Changes in v2:
- Remove newly added timer file (arch/riscv/lib/timer.c)
- Added timer_get_us() in riscv_timer.c, sifive_clint_timer.c
  and andes_plmt_timer.c.


Following are the boot messages on FU540 five cores SMP platform:

U-Boot SPL 2021.01-rc1-00244-g88b5af756c-dirty (Nov 11 2020 - 14:57:25 +0530)
Trying to boot from MMC1


U-Boot 2021.01-rc1-00244-g88b5af756c-dirty (Nov 11 2020 - 14:57:25 +0530)

CPU:   rv64imafdc
Model: SiFive HiFive Unleashed A00
DRAM:  8 GiB
trace: enabled
MMC:   spi@1005:mmc@0: 0
*** Warning - bad CRC, using default environment

In:serial@1001
Out:   serial@1001
Err:   serial@1001
Board serial number should not be 0 !!
Net:
Error: ethernet@1009 address not set.
No ethernet found.

Hit any key to stop autoboot:  0
=> trace stats
178,556 function sites
 15,443,168 function calls
  1 untracked function calls
  1,279,056 traced function calls (14135744 dropped due to overflow)
 19 maximum observed call depth
 15 call depth limit
 15,633,052 calls not traced due to depth
=>


Pragnesh Patel (1):
  riscv: Add timer_get_us() for tracing

 arch/riscv/include/asm/global_data.h |  3 +++
 drivers/timer/andes_plmt_timer.c | 19 ++-
 drivers/timer/riscv_timer.c  | 14 +-
 drivers/timer/sifive_clint_timer.c   | 19 ++-
 4 files changed, 52 insertions(+), 3 deletions(-)

-- 
2.17.1

RE: [RESEND,PATCH v2 1/1] riscv: Add timer_get_us() for tracing

[Pragnesh Patel]

Hi Rick,

>-Original Message-
>From: Rick Chen 
>Sent: 10 November 2020 13:17
>To: Pragnesh Patel 
>Cc: U-Boot Mailing List ; Atish Patra
>; Bin Meng ; Paul Walmsley (
>Sifive) ; Anup Patel ; Sagar
>Kadam ; Simon Glass ; Sean
>Anderson ; palmerdabb...@google.com; rick
>; Alan Kao 
>Subject: Re: [RESEND,PATCH v2 1/1] riscv: Add timer_get_us() for tracing
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh
>
>> Hi Rick,
>>
>> >-Original Message-
>> >From: Rick Chen 
>> >Sent: 09 November 2020 13:44
>> >To: Pragnesh Patel 
>> >Cc: U-Boot Mailing List ; Atish Patra
>> >; Bin Meng ; Paul Walmsley (
>> >Sifive) ; Anup Patel ;
>> >Sagar Kadam ; Simon Glass
>> >; Sean Anderson ;
>> >palmerdabb...@google.com; rick ; Alan Kao
>> >
>> >Subject: Re: [RESEND,PATCH v2 1/1] riscv: Add timer_get_us() for
>> >tracing
>> >
>> >[External Email] Do not click links or attachments unless you
>> >recognize the sender and know the content is safe
>> >
>> >> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
>> >> Sent: Thursday, November 05, 2020 7:31 PM
>> >> To: u-boot@lists.denx.de
>> >> Cc: atish.pa...@wdc.com; palmerdabb...@google.com;
>> >bmeng...@gmail.com;
>> >> paul.walms...@sifive.com; anup.pa...@wdc.com;
>> >> sagar.ka...@sifive.com; Rick Jian-Zhi Chen(陳建志); Pragnesh Patel;
>> >> Sean Anderson; Claudiu Beznea; Simon Glass
>> >> Subject: [RESEND,PATCH v2 1/1] riscv: Add timer_get_us() for
>> >> tracing
>> >>
>> >> Add timer_get_us() which is useful for tracing.
>> >> For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide a timer
>> >> ticks and For M-mode U-Boot, mtime register will provide the same.
>> >>
>> >> Signed-off-by: Pragnesh Patel 
>> >> ---
>> >>  drivers/timer/andes_plmt_timer.c   | 16 +++-
>> >>  drivers/timer/riscv_timer.c| 14 +-
>> >>  drivers/timer/sifive_clint_timer.c | 16 +++-
>> >>  3 files changed, 43 insertions(+), 3 deletions(-)
>> >>
>> >
>> >I verify it fail as below:
>> >
>> >U-Boot 2020.10-20532-g0910882 (Nov 09 2020 - 15:51:31 +0800)
>> >
>> >DRAM:  1 GiB
>> >trace: enabled
>> >
>> >Do you have any suggestion ?
>>
>> On which platform ?
>>
>> Do you follow this
>https://patchwork.ozlabs.org/project/uboot/cover/20201105113032.26234-1-
>pragnesh.pa...@sifive.com/ ?
>>
>
>I verify on AE350 platform with the following configurations:
>
>CONFIG_TRACE=y
>CONFIG_TRACE_BUFFER_SIZE=0x0100
>CONFIG_TRACE_CALL_DEPTH_LIMIT=15
>CONFIG_CMD_TRACE=y
>
>make FTRACE=1 ae350_rv64_defconfig
>make FTRACE=1
>
>After dig in and I found the root cause.
>You can't use gd->arch.plic to record plmt base.
>It conflicts with andes plic.

O nice catch, will update in v3.

>
>Thanks,
>Rick
>
>> >
>> >Thanks,
>> >Rick
>> >
>> >
>> >> diff --git a/drivers/timer/andes_plmt_timer.c
>> >> b/drivers/timer/andes_plmt_timer.c
>> >> index cec86718c7..9d663e036e 100644
>> >> --- a/drivers/timer/andes_plmt_timer.c
>> >> +++ b/drivers/timer/andes_plmt_timer.c
>> >> @@ -13,11 +13,12 @@
>> >>  #include 
>> >>  #include 
>> >>  #include 
>> >> +#include 
>> >>
>> >>  /* mtime register */
>> >>  #define MTIME_REG(base)((ulong)(base))
>> >>
>> >> -static u64 andes_plmt_get_count(struct udevice *dev)
>> >> +static u64 notrace andes_plmt_get_count(struct udevice *dev)
>> >>  {
>> >> return readq((void __iomem *)MTIME_REG(dev->priv));  } @@
>> >> -26,12 +27,25 @@ static const struct timer_ops andes_plmt_ops = {
>> >> .get_count = andes_plmt_get_count,  };
>> >>
>> >> +#if CONFIG_IS_ENABLED(RISCV_MMODE) unsigned long notrace
>> >> +timer_get_us(void) {
>> >> +   u64 ticks;
>> >> +
>> >> +   /* FIXME: gd->arch.plic should contain valid base address */

Any comment here for FIXME ?

>> >> +   ticks = andes_plmt_get_count(gd->arch.plic);
>>
>> Here andes_plmt_get_count() should be replaced with MTIME_REG() macro.
>Will upd

RE: [RESEND,PATCH v2 1/1] riscv: Add timer_get_us() for tracing

[Pragnesh Patel]

Hi Rick,

>-Original Message-
>From: Rick Chen 
>Sent: 09 November 2020 13:44
>To: Pragnesh Patel 
>Cc: U-Boot Mailing List ; Atish Patra
>; Bin Meng ; Paul Walmsley (
>Sifive) ; Anup Patel ; Sagar
>Kadam ; Simon Glass ; Sean
>Anderson ; palmerdabb...@google.com; rick
>; Alan Kao 
>Subject: Re: [RESEND,PATCH v2 1/1] riscv: Add timer_get_us() for tracing
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
>> Sent: Thursday, November 05, 2020 7:31 PM
>> To: u-boot@lists.denx.de
>> Cc: atish.pa...@wdc.com; palmerdabb...@google.com;
>bmeng...@gmail.com;
>> paul.walms...@sifive.com; anup.pa...@wdc.com; sagar.ka...@sifive.com;
>> Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; Sean Anderson; Claudiu
>> Beznea; Simon Glass
>> Subject: [RESEND,PATCH v2 1/1] riscv: Add timer_get_us() for tracing
>>
>> Add timer_get_us() which is useful for tracing.
>> For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide a timer ticks
>> and For M-mode U-Boot, mtime register will provide the same.
>>
>> Signed-off-by: Pragnesh Patel 
>> ---
>>  drivers/timer/andes_plmt_timer.c   | 16 +++-
>>  drivers/timer/riscv_timer.c| 14 +-
>>  drivers/timer/sifive_clint_timer.c | 16 +++-
>>  3 files changed, 43 insertions(+), 3 deletions(-)
>>
>
>I verify it fail as below:
>
>U-Boot 2020.10-20532-g0910882 (Nov 09 2020 - 15:51:31 +0800)
>
>DRAM:  1 GiB
>trace: enabled
>
>Do you have any suggestion ?

On which platform ?

Do you follow this 
https://patchwork.ozlabs.org/project/uboot/cover/20201105113032.26234-1-pragnesh.pa...@sifive.com/
 ?

>
>Thanks,
>Rick
>
>
>> diff --git a/drivers/timer/andes_plmt_timer.c
>> b/drivers/timer/andes_plmt_timer.c
>> index cec86718c7..9d663e036e 100644
>> --- a/drivers/timer/andes_plmt_timer.c
>> +++ b/drivers/timer/andes_plmt_timer.c
>> @@ -13,11 +13,12 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>
>>  /* mtime register */
>>  #define MTIME_REG(base)((ulong)(base))
>>
>> -static u64 andes_plmt_get_count(struct udevice *dev)
>> +static u64 notrace andes_plmt_get_count(struct udevice *dev)
>>  {
>> return readq((void __iomem *)MTIME_REG(dev->priv));  } @@
>> -26,12 +27,25 @@ static const struct timer_ops andes_plmt_ops = {
>> .get_count = andes_plmt_get_count,  };
>>
>> +#if CONFIG_IS_ENABLED(RISCV_MMODE)
>> +unsigned long notrace timer_get_us(void) {
>> +   u64 ticks;
>> +
>> +   /* FIXME: gd->arch.plic should contain valid base address */
>> +   ticks = andes_plmt_get_count(gd->arch.plic);

Here andes_plmt_get_count() should be replaced with MTIME_REG() macro. Will 
update in v3.

>> +   do_div(ticks, CONFIG_SYS_HZ);
>> +   return ticks;
>> +}
>> +#endif
>> +
>>  static int andes_plmt_probe(struct udevice *dev)  {
>> dev->priv = dev_read_addr_ptr(dev);
>> if (!dev->priv)
>> return -EINVAL;
>>
>> +   gd->arch.plic = dev->priv;
>> return timer_timebase_fallback(dev);  }
>>
>> diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
>> index 21ae184057..7fa8773da3 100644
>> --- a/drivers/timer/riscv_timer.c
>> +++ b/drivers/timer/riscv_timer.c
>> @@ -15,8 +15,9 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>
>> -static u64 riscv_timer_get_count(struct udevice *dev)
>> +static u64 notrace riscv_timer_get_count(struct udevice *dev)
>>  {
>> __maybe_unused u32 hi, lo;
>>
>> @@ -31,6 +32,17 @@ static u64 riscv_timer_get_count(struct udevice *dev)
>> return ((u64)hi << 32) | lo;
>>  }
>>
>> +#if CONFIG_IS_ENABLED(RISCV_SMODE)
>> +unsigned long notrace timer_get_us(void) {
>> +   u64 ticks;
>> +
>> +   ticks = riscv_timer_get_count(NULL);
>> +   do_div(ticks, CONFIG_SYS_HZ);
>> +   return ticks;
>> +}
>> +#endif
>> +
>>  static int riscv_timer_probe(struct udevice *dev)  {
>> struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
>> diff --git a/drivers/timer/sifive_clint_timer.c
>> b/drivers/timer/sifive_clint_timer.c
>> index 00ce0f08d6..166655e99d 100644
>> --- a/drivers/timer/sifive_clint_timer.c
>> +++ b/drivers/timer/sifive_clint_timer.c
>> @@ -10,11 +10

[RESEND,PATCH v2 0/1] RISC-V tracing support

[Pragnesh Patel]

This series add a support of tracing for RISC-V arch.

This series is also available here [1] for testing.
[1] https://github.com/pragnesh26992/u-boot/tree/trace

How to test this patch:
1) Enable tracing in "configs/sifive_fu540_defconfig"
CONFIG_TRACE=y
CONFIG_TRACE_BUFFER_SIZE=0x0100
CONFIG_TRACE_CALL_DEPTH_LIMIT=15
CONFIG_CMD_TRACE=y

2) make FTRACE=1 sifive_fu540_defconfig
3) make FTRACE=1

Following are the boot messages on FU540 five cores SMP platform:

U-Boot SPL 2021.01-rc1-00244-gc0ac5b69ea-dirty (Nov 05 2020 - 15:21:06 +0530)
Trying to boot from MMC1


U-Boot 2021.01-rc1-00244-gc0ac5b69ea-dirty (Nov 05 2020 - 15:21:06 +0530)

CPU:   rv64imafdc
Model: SiFive HiFive Unleashed A00
DRAM:  8 GiB
trace: enabled
MMC:   spi@1005:mmc@0: 0
*** Warning - bad CRC, using default environment

In:serial@1001
Out:   serial@1001
Err:   serial@1001
Board serial number should not be 0 !!
Net:
Error: ethernet@1009 address not set.
No ethernet found.

Hit any key to stop autoboot:  0
=> trace stats
178,556 function sites
  9,378,800 function calls
  1 untracked function calls
  1,279,056 traced function calls (8070507 dropped due to overflow)
 19 maximum observed call depth
 15 call depth limit
  9,568,845 calls not traced due to depth
=> trace calls 0x8300 0xf0
Call list dumped to 8300, size 0xea33d0
=>


Pragnesh Patel (1):
  riscv: Add timer_get_us() for tracing

 drivers/timer/andes_plmt_timer.c   | 16 +++-
 drivers/timer/riscv_timer.c| 14 +-
 drivers/timer/sifive_clint_timer.c | 16 +++-
 3 files changed, 43 insertions(+), 3 deletions(-)

-- 
2.17.1

[RESEND,PATCH v2 1/1] riscv: Add timer_get_us() for tracing

[Pragnesh Patel]

Add timer_get_us() which is useful for tracing.
For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide
a timer ticks and For M-mode U-Boot, mtime register will
provide the same.

Signed-off-by: Pragnesh Patel 
---
 drivers/timer/andes_plmt_timer.c   | 16 +++-
 drivers/timer/riscv_timer.c| 14 +-
 drivers/timer/sifive_clint_timer.c | 16 +++-
 3 files changed, 43 insertions(+), 3 deletions(-)

diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c
index cec86718c7..9d663e036e 100644
--- a/drivers/timer/andes_plmt_timer.c
+++ b/drivers/timer/andes_plmt_timer.c
@@ -13,11 +13,12 @@
 #include 
 #include 
 #include 
+#include 
 
 /* mtime register */
 #define MTIME_REG(base)((ulong)(base))
 
-static u64 andes_plmt_get_count(struct udevice *dev)
+static u64 notrace andes_plmt_get_count(struct udevice *dev)
 {
return readq((void __iomem *)MTIME_REG(dev->priv));
 }
@@ -26,12 +27,25 @@ static const struct timer_ops andes_plmt_ops = {
.get_count = andes_plmt_get_count,
 };
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+unsigned long notrace timer_get_us(void)
+{
+   u64 ticks;
+
+   /* FIXME: gd->arch.plic should contain valid base address */
+   ticks = andes_plmt_get_count(gd->arch.plic);
+   do_div(ticks, CONFIG_SYS_HZ);
+   return ticks;
+}
+#endif
+
 static int andes_plmt_probe(struct udevice *dev)
 {
dev->priv = dev_read_addr_ptr(dev);
if (!dev->priv)
return -EINVAL;
 
+   gd->arch.plic = dev->priv;
return timer_timebase_fallback(dev);
 }
 
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 21ae184057..7fa8773da3 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -15,8 +15,9 @@
 #include 
 #include 
 #include 
+#include 
 
-static u64 riscv_timer_get_count(struct udevice *dev)
+static u64 notrace riscv_timer_get_count(struct udevice *dev)
 {
__maybe_unused u32 hi, lo;
 
@@ -31,6 +32,17 @@ static u64 riscv_timer_get_count(struct udevice *dev)
return ((u64)hi << 32) | lo;
 }
 
+#if CONFIG_IS_ENABLED(RISCV_SMODE)
+unsigned long notrace timer_get_us(void)
+{
+   u64 ticks;
+
+   ticks = riscv_timer_get_count(NULL);
+   do_div(ticks, CONFIG_SYS_HZ);
+   return ticks;
+}
+#endif
+
 static int riscv_timer_probe(struct udevice *dev)
 {
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
diff --git a/drivers/timer/sifive_clint_timer.c 
b/drivers/timer/sifive_clint_timer.c
index 00ce0f08d6..166655e99d 100644
--- a/drivers/timer/sifive_clint_timer.c
+++ b/drivers/timer/sifive_clint_timer.c
@@ -10,11 +10,12 @@
 #include 
 #include 
 #include 
+#include 
 
 /* mtime register */
 #define MTIME_REG(base)((ulong)(base) + 0xbff8)
 
-static u64 sifive_clint_get_count(struct udevice *dev)
+static u64 notrace sifive_clint_get_count(struct udevice *dev)
 {
return readq((void __iomem *)MTIME_REG(dev->priv));
 }
@@ -23,12 +24,25 @@ static const struct timer_ops sifive_clint_ops = {
.get_count = sifive_clint_get_count,
 };
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+unsigned long notrace timer_get_us(void)
+{
+   u64 ticks;
+
+   /* FIXME: gd->arch.clint should contain valid base address */
+   ticks = sifive_clint_get_count(gd->arch.clint);
+   do_div(ticks, CONFIG_SYS_HZ);
+   return ticks;
+}
+#endif
+
 static int sifive_clint_probe(struct udevice *dev)
 {
dev->priv = dev_read_addr_ptr(dev);
if (!dev->priv)
return -EINVAL;
 
+   gd->arch.clint = dev->priv;
return timer_timebase_fallback(dev);
 }
 
-- 
2.17.1

[PATCH v2 0/1] RISC-V tracing support

[Pragnesh Patel]

This series add a support of tracing for RISC-V arch.

This series is also available here [1] for testing.
[1] https://github.com/pragnesh26992/u-boot/tree/trace

How to test this patch:
1) Enable tracing in "configs/sifive_fu540_defconfig"
CONFIG_TRACE=y
CONFIG_TRACE_BUFFER_SIZE=0x0100
CONFIG_TRACE_CALL_DEPTH_LIMIT=15
CONFIG_CMD_TRACE=y

2) make FTRACE=1 sifive_fu540_defconfig
3) make FTRACE=1

Following are the boot messages on FU540 five cores SMP platform:

U-Boot SPL 2021.01-rc1-00244-gc0ac5b69ea-dirty (Nov 05 2020 - 15:21:06 +0530)
Trying to boot from MMC1


U-Boot 2021.01-rc1-00244-gc0ac5b69ea-dirty (Nov 05 2020 - 15:21:06 +0530)

CPU:   rv64imafdc
Model: SiFive HiFive Unleashed A00
DRAM:  8 GiB
trace: enabled
MMC:   spi@1005:mmc@0: 0
*** Warning - bad CRC, using default environment

In:serial@1001
Out:   serial@1001
Err:   serial@1001
Board serial number should not be 0 !!
Net:
Error: ethernet@1009 address not set.
No ethernet found.

Hit any key to stop autoboot:  0
=> trace stats
178,556 function sites
  9,378,800 function calls
  1 untracked function calls
  1,279,056 traced function calls (8070507 dropped due to overflow)
 19 maximum observed call depth
 15 call depth limit
  9,568,845 calls not traced due to depth
=> trace calls 0x8300 0xf0
Call list dumped to 8300, size 0xea33d0
=>


Pragnesh Patel (1):
  riscv: Add timer_get_us() for tracing

 drivers/timer/andes_plmt_timer.c   | 14 ++
 drivers/timer/riscv_timer.c| 14 +-
 drivers/timer/sifive_clint_timer.c | 16 +++-
 3 files changed, 42 insertions(+), 2 deletions(-)

-- 
2.17.1

[PATCH v2] riscv: Add timer_get_us() for tracing

[Pragnesh Patel]

Add timer_get_us() which is useful for tracing.
For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide
a timer ticks and For M-mode U-Boot, mtime register will
provide the same.

Signed-off-by: Pragnesh Patel 
---
 drivers/timer/andes_plmt_timer.c   | 16 +++-
 drivers/timer/riscv_timer.c| 14 +-
 drivers/timer/sifive_clint_timer.c | 16 +++-
 3 files changed, 43 insertions(+), 3 deletions(-)

diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c
index cec86718c7..9d663e036e 100644
--- a/drivers/timer/andes_plmt_timer.c
+++ b/drivers/timer/andes_plmt_timer.c
@@ -13,11 +13,12 @@
 #include 
 #include 
 #include 
+#include 
 
 /* mtime register */
 #define MTIME_REG(base)((ulong)(base))
 
-static u64 andes_plmt_get_count(struct udevice *dev)
+static u64 notrace andes_plmt_get_count(struct udevice *dev)
 {
return readq((void __iomem *)MTIME_REG(dev->priv));
 }
@@ -26,12 +27,25 @@ static const struct timer_ops andes_plmt_ops = {
.get_count = andes_plmt_get_count,
 };
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+unsigned long notrace timer_get_us(void)
+{
+   u64 ticks;
+
+   /* FIXME: gd->arch.plic should contain valid base address */
+   ticks = andes_plmt_get_count(gd->arch.plic);
+   do_div(ticks, CONFIG_SYS_HZ);
+   return ticks;
+}
+#endif
+
 static int andes_plmt_probe(struct udevice *dev)
 {
dev->priv = dev_read_addr_ptr(dev);
if (!dev->priv)
return -EINVAL;
 
+   gd->arch.plic = dev->priv;
return timer_timebase_fallback(dev);
 }
 
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 21ae184057..7fa8773da3 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -15,8 +15,9 @@
 #include 
 #include 
 #include 
+#include 
 
-static u64 riscv_timer_get_count(struct udevice *dev)
+static u64 notrace riscv_timer_get_count(struct udevice *dev)
 {
__maybe_unused u32 hi, lo;
 
@@ -31,6 +32,17 @@ static u64 riscv_timer_get_count(struct udevice *dev)
return ((u64)hi << 32) | lo;
 }
 
+#if CONFIG_IS_ENABLED(RISCV_SMODE)
+unsigned long notrace timer_get_us(void)
+{
+   u64 ticks;
+
+   ticks = riscv_timer_get_count(NULL);
+   do_div(ticks, CONFIG_SYS_HZ);
+   return ticks;
+}
+#endif
+
 static int riscv_timer_probe(struct udevice *dev)
 {
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
diff --git a/drivers/timer/sifive_clint_timer.c 
b/drivers/timer/sifive_clint_timer.c
index 00ce0f08d6..166655e99d 100644
--- a/drivers/timer/sifive_clint_timer.c
+++ b/drivers/timer/sifive_clint_timer.c
@@ -10,11 +10,12 @@
 #include 
 #include 
 #include 
+#include 
 
 /* mtime register */
 #define MTIME_REG(base)((ulong)(base) + 0xbff8)
 
-static u64 sifive_clint_get_count(struct udevice *dev)
+static u64 notrace sifive_clint_get_count(struct udevice *dev)
 {
return readq((void __iomem *)MTIME_REG(dev->priv));
 }
@@ -23,12 +24,25 @@ static const struct timer_ops sifive_clint_ops = {
.get_count = sifive_clint_get_count,
 };
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+unsigned long notrace timer_get_us(void)
+{
+   u64 ticks;
+
+   /* FIXME: gd->arch.clint should contain valid base address */
+   ticks = sifive_clint_get_count(gd->arch.clint);
+   do_div(ticks, CONFIG_SYS_HZ);
+   return ticks;
+}
+#endif
+
 static int sifive_clint_probe(struct udevice *dev)
 {
dev->priv = dev_read_addr_ptr(dev);
if (!dev->priv)
return -EINVAL;
 
+   gd->arch.clint = dev->priv;
return timer_timebase_fallback(dev);
 }
 
-- 
2.17.1

RE: [PATCH 1/3] riscv: Add timer_get_us() for tracing

[Pragnesh Patel]

Hi Bin,

>-Original Message-
>From: Rick Chen 
>Sent: 21 October 2020 08:58
>To: Pragnesh Patel 
>Cc: U-Boot Mailing List ; Atish Patra
>; Anup Patel ; Sagar Kadam
>; Bin Meng ; Lukas Auer
>; Sean Anderson ; rick
>; Alan Kao 
>Subject: Re: [PATCH 1/3] riscv: Add timer_get_us() for tracing
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh
>
>> From: Bin Meng [mailto:bmeng...@gmail.com]
>> Sent: Friday, September 11, 2020 2:48 PM
>> To: Pragnesh Patel
>> Cc: U-Boot Mailing List; Atish Patra; Anup Patel; Sagar Kadam; Rick
>> Jian-Zhi Chen(陳建志); Paul Walmsley; Bin Meng; Lukas Auer; Sean Anderson
>> Subject: Re: [PATCH 1/3] riscv: Add timer_get_us() for tracing
>>
>> Hi Pragnesh,
>>
>> On Mon, Aug 24, 2020 at 10:45 PM Pragnesh Patel
>>  wrote:
>> >
>> > timer_get_us() will use timer_ops->get_count() function for timer counter.
>> > For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide a timer
>> > counter and For M-mode U-Boot, mtime register will provide the same.
>> >
>> > Signed-off-by: Pragnesh Patel 
>> > ---
>> >  arch/riscv/lib/Makefile |  1 +
>> >  arch/riscv/lib/timer.c  | 50
>> > +
>> >  2 files changed, 51 insertions(+)
>> >  create mode 100644 arch/riscv/lib/timer.c
>> >
>> > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index
>> > 10ac5b06d3..fbb68e583b 100644
>> > --- a/arch/riscv/lib/Makefile
>> > +++ b/arch/riscv/lib/Makefile
>> > @@ -26,6 +26,7 @@ obj-y   += setjmp.o
>> >  obj-$(CONFIG_$(SPL_)SMP) += smp.o
>> >  obj-$(CONFIG_SPL_BUILD)+= spl.o
>> >  obj-y   += fdt_fixup.o
>> > +obj-$(CONFIG_TIMER) += timer.o
>> >
>> >  # For building EFI apps
>> >  CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI) diff --git
>> > a/arch/riscv/lib/timer.c b/arch/riscv/lib/timer.c new file mode
>> > 100644 index 00..3e423f2805
>> > --- /dev/null
>> > +++ b/arch/riscv/lib/timer.c
>> > @@ -0,0 +1,50 @@
>> > +// SPDX-License-Identifier: GPL-2.0+
>> > +/*
>> > + * Copyright (C) 2020 SiFive, Inc
>> > + *
>> > + * Authors:
>> > + *   Pragnesh Patel 
>> > + */
>> > +
>> > +#include 
>> > +#include 
>> > +#include 
>> > +
>> > +DECLARE_GLOBAL_DATA_PTR;
>> > +
>> > +static struct udevice *timer;
>> > +
>> > +ulong notrace timer_get_us(void)
>>
>> Does the weak one in lib/time.c not work on RISC-V?

No because if "gd->timer" is set early then also it will become NULL in 
initr_dm()

static int initr_dm(void) {
...
#ifdef CONFIG_TIMER
gd->timer = NULL;
#endif
...
}

So timer_get_us() again try to call dm_timer_init() to initialize "gd->timer" 
and it got stuck in tracing.

Not all the functins are marked with notrace in dm_timer_init().

>
>Do you have any comments about Bin's reply ?
>
>Thanks,
>Rick
>
>>
>> > +{
>> > +   u64 count;
>> > +   ulong rate;
>> > +   int ret;
>> > +
>> > +   /**
>> > +* gd->timer will become NULL in initr_dm(), so assign gd->timer
>> > +* to other static global timer, so that timer_get_us() can use it.
>> > +*/
>> > +   if (!timer && gd->timer)
>> > +   timer = (struct udevice *)gd->timer;
>> > +
>> > +   if (timer) {
>> > +   ret = timer_get_count(timer, );
>> > +   if (ret)
>> > +   return ret;
>> > +
>> > +   rate = timer_get_rate(timer);
>> > +   }
>> > +
>> > +   return (ulong)count / rate;
>> > +}
>> > +
>> > +int timer_init(void)
>>
>> Why is this function necessary?
>>
>> > +{
>> > +   int ret;
>> > +
>> > +   ret = dm_timer_init();
>>
>> Does enabling CONFIG_TIMER_EARLY help?

I need to implement timer_early_get_count() and timer_early_get_rate() for 
that. Will look into this

>>
>> > +   if (ret)
>> > +   return ret;
>> > +
>> > +   return 0;
>> > +}
>>
>> Regards,
>> Bin

[PATCH v2 1/2] i2c: ocores: add i2c driver for OpenCores I2C controller

[Pragnesh Patel]

Add support for the OpenCores I2C controller IP core
(See http://www.opencores.org/projects.cgi/web/i2c/overview).

This driver implementation is inspired from the Linux OpenCores
I2C driver available.

Thanks to Peter Korsgaard  for writing Linux
OpenCores I2C driver.

Signed-off-by: Pragnesh Patel 
---

Changes in v2:
- Remove TYPE_SIFIVE_REV0 flag
- Update the Opencores I2C Controller Link

 drivers/i2c/Kconfig  |   7 +
 drivers/i2c/Makefile |   1 +
 drivers/i2c/ocores_i2c.c | 636 +++
 3 files changed, 644 insertions(+)
 create mode 100644 drivers/i2c/ocores_i2c.c

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 8ae54e1e93..37958083af 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -342,6 +342,13 @@ config SYS_I2C_NEXELL
  have several I2C ports and all are provided, controlled by the
  device tree.
 
+config SYS_I2C_OCORES
+   bool "ocores I2C driver"
+   depends on DM_I2C
+   help
+ Add support for ocores I2C controller. For details see
+ https://opencores.org/projects/i2c
+
 config SYS_I2C_OMAP24XX
bool "TI OMAP2+ I2C driver"
depends on ARCH_OMAP2PLUS || ARCH_K3
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index bd248cbf52..37dc8ada6d 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o
 obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
 obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
 obj-$(CONFIG_SYS_I2C_NEXELL) += nx_i2c.o
+obj-$(CONFIG_SYS_I2C_OCORES) += ocores_i2c.o
 obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o
 obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
 obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o
diff --git a/drivers/i2c/ocores_i2c.c b/drivers/i2c/ocores_i2c.c
new file mode 100644
index 00..1e62e4dc5f
--- /dev/null
+++ b/drivers/i2c/ocores_i2c.c
@@ -0,0 +1,636 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ocores-i2c.c: I2C bus driver for OpenCores I2C controller
+ * (https://opencores.org/projects/i2c)
+ *
+ * (C) Copyright Peter Korsgaard 
+ *
+ * Copyright (C) 2020 SiFive, Inc.
+ * Pragnesh Patel 
+ *
+ * Support for the GRLIB port of the controller by
+ * Andreas Larsson 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* registers */
+#define OCI2C_PRELOW   0
+#define OCI2C_PREHIGH  1
+#define OCI2C_CONTROL  2
+#define OCI2C_DATA 3
+#define OCI2C_CMD  4 /* write only */
+#define OCI2C_STATUS   4 /* read only, same address as OCI2C_CMD */
+
+#define OCI2C_CTRL_IEN 0x40
+#define OCI2C_CTRL_EN  0x80
+
+#define OCI2C_CMD_START0x91
+#define OCI2C_CMD_STOP 0x41
+#define OCI2C_CMD_READ 0x21
+#define OCI2C_CMD_WRITE0x11
+#define OCI2C_CMD_READ_ACK 0x21
+#define OCI2C_CMD_READ_NACK0x29
+#define OCI2C_CMD_IACK 0x01
+
+#define OCI2C_STAT_IF  0x01
+#define OCI2C_STAT_TIP 0x02
+#define OCI2C_STAT_ARBLOST 0x20
+#define OCI2C_STAT_BUSY0x40
+#define OCI2C_STAT_NACK0x80
+
+#define STATE_DONE 0
+#define STATE_START1
+#define STATE_WRITE2
+#define STATE_READ 3
+#define STATE_ERROR4
+
+#define TYPE_OCORES0
+#define TYPE_GRLIB 1
+
+#define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */
+
+struct ocores_i2c_bus {
+   void __iomem *base;
+   u32 reg_shift;
+   u32 reg_io_width;
+   unsigned long flags;
+   struct i2c_msg *msg;
+   int pos;
+   int nmsgs;
+   int state; /* see STATE_ */
+   struct clk clk;
+   int ip_clk_khz;
+   int bus_clk_khz;
+   void (*setreg)(struct ocores_i2c_bus *i2c, int reg, u8 value);
+   u8 (*getreg)(struct ocores_i2c_bus *i2c, int reg);
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Boolean attribute values */
+enum {
+   FALSE = 0,
+   TRUE,
+};
+
+static void oc_setreg_8(struct ocores_i2c_bus *i2c, int reg, u8 value)
+{
+   writeb(value, i2c->base + (reg << i2c->reg_shift));
+}
+
+static void oc_setreg_16(struct ocores_i2c_bus *i2c, int reg, u8 value)
+{
+   writew(value, i2c->base + (reg << i2c->reg_shift));
+}
+
+static void oc_setreg_32(struct ocores_i2c_bus *i2c, int reg, u8 value)
+{
+   writel(value, i2c->base + (reg << i2c->reg_shift));
+}
+
+static void oc_setreg_16be(struct ocores_i2c_bus *i2c, int reg, u8 value)
+{
+   out_be16(i2c->base + (reg << i2c->reg_shift), value);
+}
+
+static void oc_setreg_32be(struct ocores_i2c_bus *i2c, int reg, u8 value)
+{
+   out_be32(i2c->base + (reg << i2c->reg_shift), value);
+}
+
+static inline u8 oc_getreg_8(struct ocores_i2c_bus *i2c, int reg)
+{
+   return readb(i2c->base + (reg << i2c->reg_shift));
+}
+
+static i

[PATCH v2 0/2] Add OpenCores I2C controller driver

[Pragnesh Patel]

This driver has been tested on HiFive Unleashed with a PMOD based
RTCC sensor connected to I2C pins J1 header of the board.

This series is available here [1] for testing
[1] https://github.com/pragnesh26992/u-boot/tree/i2c

Tested-by: Sagar Shrikant Kadam 

Changes in v2:
- Remove TYPE_SIFIVE_REV0 flag
- Update the Opencores I2C Controller Link

U-Boot Logs for reference:

Hit any key to stop autoboot:  0
=> i2c dev 0
Setting bus to 0
=> i2c probe
Valid chip addresses: 57 6F
=> i2c md 0x57 0x0 1
: a5.
=> i2c mw 0x57 0x0 0x5a 1
=> i2c md 0x57 0x0 1
: 5aZ
=> i2c md 0x57 0x2 1
0002: 99.
=> i2c mw 0x57 0x2 0xa9 1
=> i2c md 0x57 0x2 1
0002: a9.
=> i2c md 0x6f 0x20 1
0020: 5aZ
=> i2c md 0x6f 0x5f 1
005f: a5.
=> i2c mw 0x6f 0x20 0xa9 1
=> i2c mw 0x6f 0x5f 0xa9 1
=> i2c md 0x6f 0x20 1
0020: a9.
=> i2c md 0x6f 0x5f 1
005f: a9.
=>

Pragnesh Patel (2):
  i2c: ocores: add i2c driver for OpenCores I2C controller
  riscv: sifive/fu540: kconfig: Enable support for Opencores I2C
controller

 arch/riscv/cpu/fu540/Kconfig |   2 +
 board/sifive/fu540/Kconfig   |   1 +
 drivers/i2c/Kconfig  |   7 +
 drivers/i2c/Makefile |   1 +
 drivers/i2c/ocores_i2c.c | 636 +++
 5 files changed, 647 insertions(+)
 create mode 100644 drivers/i2c/ocores_i2c.c

-- 
2.17.1

[PATCH v2 2/2] riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller

[Pragnesh Patel]

Enable support for SiFive FU540 Opencores I2C master controller.

Signed-off-by: Pragnesh Patel 
---

(no changes since v1)

 arch/riscv/cpu/fu540/Kconfig | 2 ++
 board/sifive/fu540/Kconfig   | 1 +
 2 files changed, 3 insertions(+)

diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
index ac3f183342..61bd5c426e 100644
--- a/arch/riscv/cpu/fu540/Kconfig
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -35,6 +35,8 @@ config SIFIVE_FU540
imply SIFIVE_OTP
imply DM_PWM
imply PWM_SIFIVE
+   imply DM_I2C
+   imply SYS_I2C_OCORES
 
 if ENV_IS_IN_SPI_FLASH
 
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index e70d1e53f9..64fdbd44b4 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -47,5 +47,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply SPI_FLASH_ISSI
imply SYSRESET
imply SYSRESET_GPIO
+   imply CMD_I2C
 
 endif
-- 
2.17.1

[PATCH] riscv: fu540: dts: Correct reg size of clint node

[Pragnesh Patel]

Signed-off-by: Pragnesh Patel 
---
 arch/riscv/dts/fu540-c000-u-boot.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi 
b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index a06e1b11c6..b7cd600b8c 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -62,7 +62,7 @@
   _intc 3 _intc 7
   _intc 3 _intc 7
   _intc 3 _intc 7>;
-   reg = <0x0 0x200 0x0 0xc>;
+   reg = <0x0 0x200 0x0 0x1>;
u-boot,dm-spl;
};
prci: clock-controller@1000 {
-- 
2.17.1

RE: [PATCH 1/2] i2c: ocores: add i2c driver for OpenCores I2C controller

[Pragnesh Patel]

Hi Sean,

>-Original Message-
>From: Sean Anderson 
>Sent: 09 October 2020 17:58
>To: Pragnesh Patel ; u-boot@lists.denx.de
>Cc: atish.pa...@wdc.com; palmerdabb...@google.com; bmeng...@gmail.com;
>Paul Walmsley ( Sifive) ; anup.pa...@wdc.com;
>Sagar Kadam ; r...@andestech.com; Heiko
>Schocher 
>Subject: Re: [PATCH 1/2] i2c: ocores: add i2c driver for OpenCores I2C 
>controller
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On 10/9/20 1:46 AM, Pragnesh Patel wrote:
>> Add support for the OpenCores I2C controller IP core (See
>> http://www.opencores.org/projects.cgi/web/i2c/overview).
>>
>> This driver implementation is inspired from the Linux OpenCores I2C
>> driver available.
>>
>> Thanks to Peter Korsgaard  for writing Linux
>> OpenCores I2C driver.
>>
>> Signed-off-by: Pragnesh Patel 
>> ---
>>  drivers/i2c/Kconfig  |   7 +
>>  drivers/i2c/Makefile |   1 +
>>  drivers/i2c/ocores_i2c.c | 638
>> +++
>>  3 files changed, 646 insertions(+)
>>  create mode 100644 drivers/i2c/ocores_i2c.c
>>
>> diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index
>> 8ae54e1e93..adf37177c4 100644
>> --- a/drivers/i2c/Kconfig
>> +++ b/drivers/i2c/Kconfig
>> @@ -342,6 +342,13 @@ config SYS_I2C_NEXELL
>> have several I2C ports and all are provided, controlled by the
>> device tree.
>>
>> +config SYS_I2C_OCORES
>> + bool "ocores I2C driver"
>> + depends on DM_I2C
>> + help
>> +   Add support for ocores I2C controller. For details see
>> +   http://www.opencores.org/projects.cgi/web/i2c/overview
>
>This link 404s for me. https://opencores.org/projects/i2c works.

Ooops, This is copied from Linux I2C driver.
I will update in v2.

>
>> +
>>  config SYS_I2C_OMAP24XX
>>   bool "TI OMAP2+ I2C driver"
>>   depends on ARCH_OMAP2PLUS || ARCH_K3 diff --git
>> a/drivers/i2c/Makefile b/drivers/i2c/Makefile index
>> bd248cbf52..37dc8ada6d 100644
>> --- a/drivers/i2c/Makefile
>> +++ b/drivers/i2c/Makefile
>> @@ -32,6 +32,7 @@ obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o
>>  obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
>>  obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
>>  obj-$(CONFIG_SYS_I2C_NEXELL) += nx_i2c.o
>> +obj-$(CONFIG_SYS_I2C_OCORES) += ocores_i2c.o
>>  obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o
>>  obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
>>  obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o diff --git
>> a/drivers/i2c/ocores_i2c.c b/drivers/i2c/ocores_i2c.c new file mode
>> 100644 index 00..b42b55625f
>> --- /dev/null
>> +++ b/drivers/i2c/ocores_i2c.c
>> @@ -0,0 +1,638 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * ocores-i2c.c: I2C bus driver for OpenCores I2C controller
>> + * (https://opencores.org/project/i2c/overview)
>> + *
>> + * (C) Copyright Peter Korsgaard 
>> + *
>> + * Copyright (C) 2020 SiFive, Inc.
>> + * Pragnesh Patel 
>> + *
>> + * Support for the GRLIB port of the controller by
>> + * Andreas Larsson   */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +/* registers */
>> +#define OCI2C_PRELOW 0
>> +#define OCI2C_PREHIGH1
>> +#define OCI2C_CONTROL2
>> +#define OCI2C_DATA   3
>> +#define OCI2C_CMD4 /* write only */
>> +#define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
>> +
>> +#define OCI2C_CTRL_IEN   0x40
>> +#define OCI2C_CTRL_EN0x80
>> +
>> +#define OCI2C_CMD_START  0x91
>> +#define OCI2C_CMD_STOP   0x41
>> +#define OCI2C_CMD_READ   0x21
>> +#define OCI2C_CMD_WRITE  0x11
>> +#define OCI2C_CMD_READ_ACK   0x21
>> +#define OCI2C_CMD_READ_NACK  0x29
>> +#define OCI2C_CMD_IACK   0x01
>> +
>> +#define OCI2C_STAT_IF0x01
>> +#define OCI2C_STAT_TIP   0x02
>> +#define OCI2C_STAT_ARBLOST   0x20
>> +#define OCI2C_STAT_BUSY  0x40
>> +#define OCI2C_STAT_NACK  0x80
>> +
>> +#define STATE_DONE   0
>> +#define STATE_START  1
>> +#define STATE_WRITE  2
>> +#define STATE_READ   3
>> +#define S

[PATCH 1/2] i2c: ocores: add i2c driver for OpenCores I2C controller

[Pragnesh Patel]

Add support for the OpenCores I2C controller IP core
(See http://www.opencores.org/projects.cgi/web/i2c/overview).

This driver implementation is inspired from the Linux OpenCores
I2C driver available.

Thanks to Peter Korsgaard  for writing Linux
OpenCores I2C driver.

Signed-off-by: Pragnesh Patel 
---
 drivers/i2c/Kconfig  |   7 +
 drivers/i2c/Makefile |   1 +
 drivers/i2c/ocores_i2c.c | 638 +++
 3 files changed, 646 insertions(+)
 create mode 100644 drivers/i2c/ocores_i2c.c

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 8ae54e1e93..adf37177c4 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -342,6 +342,13 @@ config SYS_I2C_NEXELL
  have several I2C ports and all are provided, controlled by the
  device tree.
 
+config SYS_I2C_OCORES
+   bool "ocores I2C driver"
+   depends on DM_I2C
+   help
+ Add support for ocores I2C controller. For details see
+ http://www.opencores.org/projects.cgi/web/i2c/overview
+
 config SYS_I2C_OMAP24XX
bool "TI OMAP2+ I2C driver"
depends on ARCH_OMAP2PLUS || ARCH_K3
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index bd248cbf52..37dc8ada6d 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o
 obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
 obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
 obj-$(CONFIG_SYS_I2C_NEXELL) += nx_i2c.o
+obj-$(CONFIG_SYS_I2C_OCORES) += ocores_i2c.o
 obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o
 obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
 obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o
diff --git a/drivers/i2c/ocores_i2c.c b/drivers/i2c/ocores_i2c.c
new file mode 100644
index 00..b42b55625f
--- /dev/null
+++ b/drivers/i2c/ocores_i2c.c
@@ -0,0 +1,638 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ocores-i2c.c: I2C bus driver for OpenCores I2C controller
+ * (https://opencores.org/project/i2c/overview)
+ *
+ * (C) Copyright Peter Korsgaard 
+ *
+ * Copyright (C) 2020 SiFive, Inc.
+ * Pragnesh Patel 
+ *
+ * Support for the GRLIB port of the controller by
+ * Andreas Larsson 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* registers */
+#define OCI2C_PRELOW   0
+#define OCI2C_PREHIGH  1
+#define OCI2C_CONTROL  2
+#define OCI2C_DATA 3
+#define OCI2C_CMD  4 /* write only */
+#define OCI2C_STATUS   4 /* read only, same address as OCI2C_CMD */
+
+#define OCI2C_CTRL_IEN 0x40
+#define OCI2C_CTRL_EN  0x80
+
+#define OCI2C_CMD_START0x91
+#define OCI2C_CMD_STOP 0x41
+#define OCI2C_CMD_READ 0x21
+#define OCI2C_CMD_WRITE0x11
+#define OCI2C_CMD_READ_ACK 0x21
+#define OCI2C_CMD_READ_NACK0x29
+#define OCI2C_CMD_IACK 0x01
+
+#define OCI2C_STAT_IF  0x01
+#define OCI2C_STAT_TIP 0x02
+#define OCI2C_STAT_ARBLOST 0x20
+#define OCI2C_STAT_BUSY0x40
+#define OCI2C_STAT_NACK0x80
+
+#define STATE_DONE 0
+#define STATE_START1
+#define STATE_WRITE2
+#define STATE_READ 3
+#define STATE_ERROR4
+
+#define TYPE_OCORES0
+#define TYPE_GRLIB 1
+#define TYPE_SIFIVE_REV0   2
+
+#define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */
+
+struct ocores_i2c_bus {
+   void __iomem *base;
+   u32 reg_shift;
+   u32 reg_io_width;
+   unsigned long flags;
+   struct i2c_msg *msg;
+   int pos;
+   int nmsgs;
+   int state; /* see STATE_ */
+   struct clk clk;
+   int ip_clk_khz;
+   int bus_clk_khz;
+   void (*setreg)(struct ocores_i2c_bus *i2c, int reg, u8 value);
+   u8 (*getreg)(struct ocores_i2c_bus *i2c, int reg);
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Boolean attribute values */
+enum {
+   FALSE = 0,
+   TRUE,
+};
+
+static void oc_setreg_8(struct ocores_i2c_bus *i2c, int reg, u8 value)
+{
+   writeb(value, i2c->base + (reg << i2c->reg_shift));
+}
+
+static void oc_setreg_16(struct ocores_i2c_bus *i2c, int reg, u8 value)
+{
+   writew(value, i2c->base + (reg << i2c->reg_shift));
+}
+
+static void oc_setreg_32(struct ocores_i2c_bus *i2c, int reg, u8 value)
+{
+   writel(value, i2c->base + (reg << i2c->reg_shift));
+}
+
+static void oc_setreg_16be(struct ocores_i2c_bus *i2c, int reg, u8 value)
+{
+   out_be16(i2c->base + (reg << i2c->reg_shift), value);
+}
+
+static void oc_setreg_32be(struct ocores_i2c_bus *i2c, int reg, u8 value)
+{
+   out_be32(i2c->base + (reg << i2c->reg_shift), value);
+}
+
+static inline u8 oc_getreg_8(struct ocores_i2c_bus *i2c, int reg)
+{
+   return readb(i2c->base + (reg << i2c->reg_shift));
+}
+
+static inline u8 oc_getreg_16(str

[PATCH 2/2] riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller

[Pragnesh Patel]

Enable support for SiFive FU540 Opencores I2C master controller.

Signed-off-by: Pragnesh Patel 
---
 arch/riscv/cpu/fu540/Kconfig | 2 ++
 board/sifive/fu540/Kconfig   | 1 +
 2 files changed, 3 insertions(+)

diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
index ac3f183342..61bd5c426e 100644
--- a/arch/riscv/cpu/fu540/Kconfig
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -35,6 +35,8 @@ config SIFIVE_FU540
imply SIFIVE_OTP
imply DM_PWM
imply PWM_SIFIVE
+   imply DM_I2C
+   imply SYS_I2C_OCORES
 
 if ENV_IS_IN_SPI_FLASH
 
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index e70d1e53f9..64fdbd44b4 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -47,5 +47,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply SPI_FLASH_ISSI
imply SYSRESET
imply SYSRESET_GPIO
+   imply CMD_I2C
 
 endif
-- 
2.17.1

[PATCH 0/2] Add OpenCores I2C controller driver

[Pragnesh Patel]

This driver has been tested on HiFive Unleashed with a PMOD based
RTCC sensor connected to I2C pins J1 header of the board.

This series is available here [1] for testing
[1] https://github.com/pragnesh26992/u-boot/tree/i2c

Tested-by: Sagar Shrikant Kadam 

U-Boot Logs for reference:

Hit any key to stop autoboot:  0
=> i2c dev 0
Setting bus to 0
=> i2c probe
Valid chip addresses: 57 6F
=> i2c md 0x57 0x0 1
: ff
=> i2c mw 0x57 0x0 0xa5 1
=> i2c md 0x57 0x0 1
: a5
=> i2c md 0x6f 0x0 1
: 00
=> i2c md 0x6f 0x1 1
0001: 00
=> i2c md 0x6f 0x2 1
0002: 00
=> i2c md 0x6f 0x20 1
0020: 98
=> i2c md 0x6f 0x5f 1
005f: 55
=> i2c mw 0x6f 0x0 0x12 1
=> i2c mw 0x6f 0x1 0x34 1
=> i2c mw 0x6f 0x2 0x56 1
=> i2c md 0x6f 0x0 1
: 12
=> i2c md 0x6f 0x1 1
0001: 34
=> i2c md 0x6f 0x2 1
0002: 56
=> i2c mw 0x6f 0x20 0x78 1
=> i2c md 0x6f 0x20 1
0020: 78
=> i2c mw 0x6f 0x5f 0x5a 1
=> i2c md 0x6f 0x5f 1
005f: 5a
=> i2c mw 0x6f 0x5f 0xa5 1
=> i2c md 0x6f 0x5f 1
005f: a5


Pragnesh Patel (2):
  i2c: ocores: add i2c driver for OpenCores I2C controller
  riscv: sifive/fu540: kconfig: Enable support for Opencores I2C
controller

 arch/riscv/cpu/fu540/Kconfig |   2 +
 board/sifive/fu540/Kconfig   |   1 +
 drivers/i2c/Kconfig  |   7 +
 drivers/i2c/Makefile |   1 +
 drivers/i2c/ocores_i2c.c | 638 +++
 5 files changed, 649 insertions(+)
 create mode 100644 drivers/i2c/ocores_i2c.c

-- 
2.17.1

RE: [PATCH 07/10] ram: sifive: Default to y only if compiling for fu540

[Pragnesh Patel]

>-Original Message-
>From: Sean Anderson 
>Sent: 29 September 2020 19:49
>To: u-boot@lists.denx.de
>Cc: Bin Meng ; Rick Chen ;
>Heinrich Schuchardt ; Sean Anderson
>; Pragnesh Patel 
>Subject: [PATCH 07/10] ram: sifive: Default to y only if compiling for fu540
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Other RISC-V targets should not have RAM_SIFIVE enabled by default.
>
>Signed-off-by: Sean Anderson 
>---
>
> drivers/ram/sifive/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Pragnesh Patel 

RE: [PATCH v3 7/7] riscv: Update SiFive device tree for new CLINT driver

[Pragnesh Patel]

>-Original Message-
>From: Sean Anderson 
>Sent: 01 September 2020 16:02
>To: u-boot@lists.denx.de
>Cc: Rick Chen ; Bin Meng ;
>Pragnesh Patel ; Sean Anderson
>
>Subject: [PATCH v3 7/7] riscv: Update SiFive device tree for new CLINT driver
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>We may need to add a clock-frequency binding like for the K210.
>
>Signed-off-by: Sean Anderson 
>---
>This patch builds but has NOT been tested.
>
>Changes in v3:
>- Rebase
>
>Changes in v2:
>- Fix SiFive CLINT not getting tick-rate from rtcclk
>
> arch/riscv/dts/fu540-c000-u-boot.dtsi   | 8 ++--
> arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 4 ++++
> 2 files changed, 10 insertions(+), 2 deletions(-)

Reviewed-by: Pragnesh Patel 

RE: [PATCH v3 4/7] riscv: Rework Sifive CLINT as UCLASS_TIMER driver

[Pragnesh Patel]

>-Original Message-
>From: Sean Anderson 
>Sent: 01 September 2020 16:02
>To: u-boot@lists.denx.de
>Cc: Rick Chen ; Bin Meng ;
>Pragnesh Patel ; Sean Anderson
>
>Subject: [PATCH v3 4/7] riscv: Rework Sifive CLINT as UCLASS_TIMER driver
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>This converts the clint driver from the riscv-specific interface to be a 
>DM-based
>UCLASS_TIMER driver. We also need to re-add the initialization for IPI back 
>into
>the SPL code. This was previously implicitly done when the timer was 
>initialized.
>In addition, the SiFive DDR driver previously implicitly depended on the CLINT 
>to
>select REGMAP.
>
>Unlike Andes's PLMT/PLIC (which AFAIK never have anything pass it a dtb), the
>SiFive CLINT is part of the device tree passed in by qemu. This device tree 
>doesn't
>have a clocks or clock-frequency property on clint, so we need to fall back on 
>the
>timebase-frequency property. Perhaps in the future we can get a clock-frequency
>property added to the qemu dtb.
>
>Unlike with the Andes PLMT, the Sifive CLINT is also an IPI controller.
>RISCV_SYSCON_CLINT is retained for this purpose.
>
>Signed-off-by: Sean Anderson 
>---
>This patch builds but has only been tested on the K210 and QEMU. It has NOT
>been tested on a HiFive.
>
>Changes in v3:
>- Don't initialize the IPI in spl_invoke_opensbi. Further testing has
>  revealed it to be unnecessary.
>
> arch/riscv/Kconfig|  4 --
> arch/riscv/lib/sifive_clint.c | 87 +++----
> drivers/ram/sifive/Kconfig|  2 +
> 3 files changed, 59 insertions(+), 34 deletions(-)

Reviewed-by: Pragnesh Patel 

RE: [PATCH v3 1/7] riscv: Rework riscv timer driver to only support S-mode

[Pragnesh Patel]

Hi Sean,

>-Original Message-
>From: Sean Anderson 
>Sent: 01 September 2020 16:02
>To: u-boot@lists.denx.de
>Cc: Rick Chen ; Bin Meng ;
>Pragnesh Patel ; Sean Anderson
>; Bin Meng ; Anup Patel
>
>Subject: [PATCH v3 1/7] riscv: Rework riscv timer driver to only support S-mode
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>The riscv-timer driver currently serves as a shim for several riscv timer 
>drivers.
>This is not too desirable because it bypasses the usual timer selection via the
>driver model. There is no easy way to specify an alternate timing driver, or 
>have
>the tick rate depend on the cpu's configured frequency. The timer drivers also 
>do
>not have device structs, and so have to rely on storing parameters in gd_t. 
>Lastly,
>there is no initialization call, so driver init is done in the same function 
>which
>reads the time. This can result in confusing error messages. To a user, it 
>looks like
>the driver failed when trying to read the time, whereas it may have failed 
>while
>initializing.
>
>This patch removes the shim functionality from the riscv-timer driver, and has 
>it
>instead implement the former rdtime.c timer driver. This is because existing u-
>boot users who pass in a device tree (e.g. qemu) do not create a timer device 
>for
>S-mode u-boot. The existing behavior of creating the riscv-timer device in the
>riscv cpu driver must be kept. The actual reading of the CSRs has been redone 
>in
>the style of Linux's get_cycles64.
>
>Signed-off-by: Sean Anderson 
>Reviewed-by: Bin Meng 
>---
>
>(no changes since v2)
>
>Changes in v2:
>- Remove RISCV_RDTIME KConfig option
>
> arch/riscv/Kconfig  |  8 
> arch/riscv/lib/Makefile |  1 -
> arch/riscv/lib/rdtime.c | 38 
> drivers/timer/Kconfig   |  6 +++---
> drivers/timer/riscv_timer.c | 39 +++--
> 5 files changed, 23 insertions(+), 69 deletions(-)  delete mode 100644
>arch/riscv/lib/rdtime.c
>
>diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 
>009a545fcf..21e6690f4d
>100644
>--- a/arch/riscv/Kconfig
>+++ b/arch/riscv/Kconfig
>@@ -185,14 +185,6 @@ config ANDES_PLMT
>  The Andes PLMT block holds memory-mapped mtime register
>  associated with timer tick.
>
>-config RISCV_RDTIME
>-   bool
>-   default y if RISCV_SMODE || SPL_RISCV_SMODE
>-   help
>- The provides the riscv_get_time() API that is implemented using the
>- standard rdtime instruction. This is the case for S-mode U-Boot, and
>- is useful for processors that support rdtime in M-mode too.
>-
> config SYS_MALLOC_F_LEN
>default 0x1000
>
>diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index
>6c503ff2b2..10ac5b06d3 100644
>--- a/arch/riscv/lib/Makefile
>+++ b/arch/riscv/lib/Makefile
>@@ -15,7 +15,6 @@ obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
> obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
> obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o  else
>-obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
> obj-$(CONFIG_SBI) += sbi.o
> obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> endif
>diff --git a/arch/riscv/lib/rdtime.c b/arch/riscv/lib/rdtime.c deleted file 
>mode
>100644 index e128d7fce6..00
>--- a/arch/riscv/lib/rdtime.c
>+++ /dev/null
>@@ -1,38 +0,0 @@
>-// SPDX-License-Identifier: GPL-2.0+
>-/*
>- * Copyright (C) 2018, Anup Patel 
>- * Copyright (C) 2018, Bin Meng 
>- *
>- * The riscv_get_time() API implementation that is using the
>- * standard rdtime instruction.
>- */
>-
>-#include 
>-
>-/* Implement the API required by RISC-V timer driver */ -int 
>riscv_get_time(u64
>*time) -{ -#ifdef CONFIG_64BIT
>-   u64 n;
>-
>-   __asm__ __volatile__ (
>-   "rdtime %0"
>-   : "=r" (n));
>-
>-   *time = n;
>-#else
>-   u32 lo, hi, tmp;
>-
>-   __asm__ __volatile__ (
>-   "1:\n"
>-   "rdtimeh %0\n"
>-   "rdtime %1\n"
>-   "rdtimeh %2\n"
>-   "bne %0, %2, 1b"
>-   : "=" (hi), "=" (lo), "=" (tmp));
>-
>-   *time = ((u64)hi << 32) | lo;
>-#endif
>-
>-   return 0;
>-}
>diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index
>637024445c..b85fa33e47 100644
>--- a/drivers/timer/Kconfig
>+++ b/drivers/timer/Kconfig
>@@ -144,10 +144,10 @@ config OMAP_TIMER
>
> config RISCV_TIMER
>bool "RISC-V timer support&quo

[PATCH] cmd: irq: disable CMD_IRQ for riscv arch

[Pragnesh Patel]

For RISC-V arch, no need for CMD_IRQ so disable the same.

Signed-off-by: Pragnesh Patel 
---
 cmd/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 9ad511aa17..9709666261 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -2217,7 +2217,7 @@ config CMD_DIAG
 
 config CMD_IRQ
bool "irq - Show information about interrupts"
-   depends on !ARM && !MIPS && !SH
+   depends on !ARM && !MIPS && !RISCV && !SH
help
  This enables two commands:
 
-- 
2.17.1

[PATCH 3/3] riscv: Mark andes_plmt_get_count() with 'notrace'

[Pragnesh Patel]

For M-mode U-boot, andes_plmt_get_count() will provide timer counter.
Mark it as 'notrace' so that it doesn't cause infinite recursion.

Signed-off-by: Pragnesh Patel 
---
 arch/riscv/lib/andes_plmt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c
index b0245d0b52..488a98406b 100644
--- a/arch/riscv/lib/andes_plmt.c
+++ b/arch/riscv/lib/andes_plmt.c
@@ -17,7 +17,7 @@
 /* mtime register */
 #define MTIME_REG(base)((ulong)(base))
 
-static int andes_plmt_get_count(struct udevice *dev, u64 *count)
+static int notrace andes_plmt_get_count(struct udevice *dev, u64 *count)
 {
*count = readq((void __iomem *)MTIME_REG(dev->priv));
 
-- 
2.17.1

[PATCH 0/3] RISC-V tracing support

[Pragnesh Patel]

This series add a support of tracing for RISC-V arch.

This series is also available here [1] for testing.
Series depends on [2].

[1] https://github.com/pragnesh26992/u-boot/tree/trace
[2] 
https://patchwork.ozlabs.org/project/uboot/cover/20200729095636.1077054-1-sean...@gmail.com/

How to test this patch:
1) Enable tracing in "configs/sifive_fu540_defconfig"
CONFIG_TRACE=y
CONFIG_TRACE_BUFFER_SIZE=0x0100
CONFIG_TRACE_CALL_DEPTH_LIMIT=15
CONFIG_CMD_TRACE=y

2) make FTRACE=1 sifive_fu540_defconfig
3) make FTRACE=1

Following are the boot messages on FU540 five cores SMP platform:

U-Boot 2020.10-rc1-02837-g8613dc2e66 (Aug 24 2020 - 20:03:47 +0530)

CPU:   rv64imac
Model: SiFive HiFive Unleashed A00
DRAM:  8 GiB
trace: enabled
MMC:   spi@1005:mmc@0: 0
Loading Environment from SPIFlash... SF: Detected is25wp256 with page size 256 
Bytes, erase size 4 KiB, total 32 MiB
OK
In:serial@1001
Out:   serial@1001
Err:   serial@1001
Board serial number should not be 0 !!
Net:
Warning: ethernet@1009 (eth0) using random MAC address - 92:a1:a7:02:5a:14
eth0: ethernet@1009
Hit any key to stop autoboot:  0
=> trace stats
177,722 function sites
 37,057,350 function calls
  1 untracked function calls
  1,279,612 traced function calls (36015585 dropped due to overflow)
 19 maximum observed call depth
 15 call depth limit
 37,055,565 calls not traced due to depth
=>


Pragnesh Patel (3):
  riscv: Add timer_get_us() for tracing
  riscv: Mark riscv_timer_get_count() and sifive_clint_get_count() with
'notrace'
  riscv: Mark andes_plmt_get_count() with 'notrace'

 arch/riscv/lib/Makefile   |  1 +
 arch/riscv/lib/andes_plmt.c   |  2 +-
 arch/riscv/lib/sifive_clint.c |  2 +-
 arch/riscv/lib/timer.c| 50 +++
 drivers/timer/riscv_timer.c   |  2 +-
 5 files changed, 54 insertions(+), 3 deletions(-)
 create mode 100644 arch/riscv/lib/timer.c

-- 
2.17.1

[PATCH 2/3] riscv: Mark riscv_timer_get_count() and sifive_clint_get_count() with 'notrace'

[Pragnesh Patel]

Mark them as 'notrace' so that it doesn't cause infinite recursion.

Signed-off-by: Pragnesh Patel 
---
 arch/riscv/lib/sifive_clint.c | 2 +-
 drivers/timer/riscv_timer.c   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
index 3345a17ad2..1cf74a6cf4 100644
--- a/arch/riscv/lib/sifive_clint.c
+++ b/arch/riscv/lib/sifive_clint.c
@@ -62,7 +62,7 @@ int riscv_get_ipi(int hart, int *pending)
return 0;
 }
 
-static int sifive_clint_get_count(struct udevice *dev, u64 *count)
+static int notrace sifive_clint_get_count(struct udevice *dev, u64 *count)
 {
*count = readq((void __iomem *)MTIME_REG(dev->priv));
 
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 449fcfcfd5..342e0354dc 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -16,7 +16,7 @@
 #include 
 #include 
 
-static int riscv_timer_get_count(struct udevice *dev, u64 *count)
+static int notrace riscv_timer_get_count(struct udevice *dev, u64 *count)
 {
if (IS_ENABLED(CONFIG_64BIT)) {
*count = csr_read(CSR_TIME);
-- 
2.17.1

[PATCH 1/3] riscv: Add timer_get_us() for tracing

[Pragnesh Patel]

timer_get_us() will use timer_ops->get_count() function for timer counter.
For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide a timer counter and
For M-mode U-Boot, mtime register will provide the same.

Signed-off-by: Pragnesh Patel 
---
 arch/riscv/lib/Makefile |  1 +
 arch/riscv/lib/timer.c  | 50 +
 2 files changed, 51 insertions(+)
 create mode 100644 arch/riscv/lib/timer.c

diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 10ac5b06d3..fbb68e583b 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -26,6 +26,7 @@ obj-y   += setjmp.o
 obj-$(CONFIG_$(SPL_)SMP) += smp.o
 obj-$(CONFIG_SPL_BUILD)+= spl.o
 obj-y   += fdt_fixup.o
+obj-$(CONFIG_TIMER) += timer.o
 
 # For building EFI apps
 CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI)
diff --git a/arch/riscv/lib/timer.c b/arch/riscv/lib/timer.c
new file mode 100644
index 00..3e423f2805
--- /dev/null
+++ b/arch/riscv/lib/timer.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 SiFive, Inc
+ *
+ * Authors:
+ *   Pragnesh Patel 
+ */
+
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct udevice *timer;
+
+ulong notrace timer_get_us(void)
+{
+   u64 count;
+   ulong rate;
+   int ret;
+
+   /**
+* gd->timer will become NULL in initr_dm(), so assign gd->timer
+* to other static global timer, so that timer_get_us() can use it.
+*/
+   if (!timer && gd->timer)
+   timer = (struct udevice *)gd->timer;
+
+   if (timer) {
+   ret = timer_get_count(timer, );
+   if (ret)
+   return ret;
+
+   rate = timer_get_rate(timer);
+   }
+
+   return (ulong)count / rate;
+}
+
+int timer_init(void)
+{
+   int ret;
+
+   ret = dm_timer_init();
+   if (ret)
+   return ret;
+
+   return 0;
+}
-- 
2.17.1

RE: [PATCH] riscv: Add do_irqinfo() for CONFIG_CMD_IRQ

[Pragnesh Patel]

Hi Heinrich,

>-Original Message-
>From: Heinrich Schuchardt 
>Sent: 24 August 2020 19:01
>To: Pragnesh Patel ; u-boot@lists.denx.de;
>atish.pa...@wdc.com; bmeng...@gmail.com; anup.pa...@wdc.com; Sagar
>Kadam ; r...@andestech.com
>Cc: Paul Walmsley ( Sifive) ; Simon Glass
>; Sean Anderson ; Bin Meng
>
>Subject: Re: [PATCH] riscv: Add do_irqinfo() for CONFIG_CMD_IRQ
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On 24.08.20 13:00, Pragnesh Patel wrote:
>> Right now, do_irqinfo() done nothing and return 0 for
>
>Nits:
>
>%s/done/does/
>
>> CONFIG_CMD_IRQ
>>
>> Signed-off-by: Pragnesh Patel 
>> ---
>>  arch/riscv/lib/interrupts.c | 7 +++
>>  1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
>> index cd47e64487..d6273606b5 100644
>> --- a/arch/riscv/lib/interrupts.c
>> +++ b/arch/riscv/lib/interrupts.c
>> @@ -145,3 +145,10 @@ __attribute__((weak)) void
>> external_interrupt(struct pt_regs *regs)
>>  __attribute__((weak)) void timer_interrupt(struct pt_regs *regs)  {
>> }
>> +
>> +#if defined(CONFIG_CMD_IRQ)
>> +int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const
>> +argv[]) {
>> + return 0;
>> +}
>> +#endif
>
>Why do we allow CONFIG_CMD_IRQ for RISC-V if the command is not
>supported?
>
>How about:
>
>cmd/Kconfig:2224
>
> config CMD_IRQ
>bool "irq - Show information about interrupts"
>-   depends on !ARM && !MIPS && !SH
>+   depends on !ARM && !MIPS && !RISCV && !SH

Agreed, will send a new patch.

>
>Best regards
>
>Heinrich
>
>>

[PATCH] riscv: Add do_irqinfo() for CONFIG_CMD_IRQ

[Pragnesh Patel]

Right now, do_irqinfo() done nothing and return 0 for
CONFIG_CMD_IRQ

Signed-off-by: Pragnesh Patel 
---
 arch/riscv/lib/interrupts.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index cd47e64487..d6273606b5 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -145,3 +145,10 @@ __attribute__((weak)) void external_interrupt(struct 
pt_regs *regs)
 __attribute__((weak)) void timer_interrupt(struct pt_regs *regs)
 {
 }
+
+#if defined(CONFIG_CMD_IRQ)
+int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+   return 0;
+}
+#endif
-- 
2.17.1

RE: [PATCH v5 1/1] cmd: provide command sbi

[Pragnesh Patel]

>-Original Message-
>From: Heinrich Schuchardt 
>Sent: 20 August 2020 23:14
>To: Rick Chen 
>Cc: Bin Meng ; Pragnesh Patel
>; Lukas Auer ; Atish Patra
>; u-boot@lists.denx.de; Heinrich Schuchardt
>; Bin Meng 
>Subject: [PATCH v5 1/1] cmd: provide command sbi
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Provide a command to display information about the SBI implementation.
>
>The output might look like:
>
>=> sbi
>SBI 0.2
>OpenSBI
>Extensions:
>  sbi_set_timer
>  sbi_console_putchar
>  sbi_console_getchar
>  sbi_clear_ipi
>  sbi_send_ipi
>  sbi_remote_fence_i
>  sbi_remote_sfence_vma
>  sbi_remote_sfence_vma_asid
>  sbi_shutdown
>  SBI Base Functionality
>  Timer Extension
>  IPI Extension
>  RFENCE Extension
>  Hart State Management Extension
>
>The command can be used to construct a unit test checking that the
>communication with the SEE is working.
>
>Signed-off-by: Heinrich Schuchardt 
>Reviewed-by: Atish Patra 
>Reviewed-by: Bin Meng 
>Tested-by: Bin Meng 
>---
>v5:
>The sbi command takes no arguments. Set maxargs=1.
>v4:
>only show command name 'sbi' as short description in Kconfig menu
>as suggested by Bin
>v3:
>add dependency on CONFIG_SBI_V02
>use lower case for sbi in Kconfig
>v2:
>provide a non-blank long help text
>---
> arch/riscv/include/asm/sbi.h |  2 +
> arch/riscv/lib/sbi.c | 36 
> cmd/Kconfig  |  6 +++
> cmd/riscv/Makefile       |  1 +
> cmd/riscv/sbi.c      | 82 
> 5 files changed, 127 insertions(+)
> create mode 100644 cmd/riscv/sbi.c

Reviewed-by: Pragnesh Patel 
Tested-by:  Pragnesh Patel 

RE: [PATCH v2 1/1] riscv: fix building with CONFIG_SPL_SMP=n

[Pragnesh Patel]

>-Original Message-
>From: U-Boot  On Behalf Of Heinrich Schuchardt
>Sent: 15 August 2020 13:19
>To: Rick Chen 
>Cc: Simon Glass ; Bin Meng ;
>Anup Patel ; Lukas Auer
>; u-boot@lists.denx.de; Heinrich Schuchardt
>
>Subject: [PATCH v2 1/1] riscv: fix building with CONFIG_SPL_SMP=n
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Building with CONFIG_SPL_SMP=n results in:
>
>arch/riscv/lib/spl.c: In function ‘jump_to_image_no_args’:
>arch/riscv/lib/spl.c:33:6:
>error: unused variable ‘ret’ [-Werror=unused-variable]
>   33 |  int ret;
>  |  ^~~
>
>Define the variable ret as __maybe_unused.
>
>Fixes: 191636e44898 ("riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL")
>Fixes: 8c59f2023cc8 ("riscv: add SPL support")
>Signed-off-by: Heinrich Schuchardt 
>Reviewed-by: Bin Meng 
>Reviewed-by: Simon Glass 
>Reviewed-by: Rick Chen 
>---
>v2:
>Do not break Fixes line
>---
> arch/riscv/lib/spl.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Pragnesh Patel 

RE: [PATCH 2/2] ram: sifive: Fix compiler warnings for 32-bit

[Pragnesh Patel]

>-Original Message-
>From: Bin Meng 
>Sent: 18 August 2020 13:39
>To: Rick Chen ; Pragnesh Patel
>; U-Boot Mailing List 
>Cc: Bin Meng 
>Subject: [PATCH 2/2] ram: sifive: Fix compiler warnings for 32-bit
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>From: Bin Meng 
>
>priv->info.size is of type 'size_t' but the length modifier is l.
>Fix this by casting priv->info.size. Note 'z' cannot be used as the modifier 
>as SPL
>does not support that.
>
>Signed-off-by: Bin Meng 
>---
>
> drivers/ram/sifive/fu540_ddr.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Pragnesh Patel 

RE: [PATCH v4 1/1] cmd: provide command sbi

[Pragnesh Patel]

Hi Heinrich,

>-Original Message-
>From: Heinrich Schuchardt 
>Sent: 20 August 2020 17:25
>To: Pragnesh Patel 
>Cc: Bin Meng ; Lukas Auer ; Atish Patra
>; u-boot@lists.denx.de; Bin Meng
>; Rick Chen 
>Subject: Re: [PATCH v4 1/1] cmd: provide command sbi
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On 20.08.20 13:30, Pragnesh Patel wrote:
>> Hi Heinrich,
>>
>>> -Original Message-
>>> From: Heinrich Schuchardt 
>>> Sent: 20 August 2020 16:23
>>> To: Rick Chen 
>>> Cc: Bin Meng ; Pragnesh Patel
>>> ; Lukas Auer ; Atish
>>> Patra ; u-boot@lists.denx.de; Heinrich
>>> Schuchardt ; Bin Meng 
>>> Subject: [PATCH v4 1/1] cmd: provide command sbi
>>>
>>> [External Email] Do not click links or attachments unless you
>>> recognize the sender and know the content is safe
>>>
>>> Provide a command to display information about the SBI implementation.
>>>
>>> The output might look like:
>>>
>>> => sbi
>>> SBI 0.2
>>> OpenSBI
>>> Extensions:
>>>  sbi_set_timer
>>>  sbi_console_putchar
>>>  sbi_console_getchar
>>>  sbi_clear_ipi
>>>  sbi_send_ipi
>>>  sbi_remote_fence_i
>>>  sbi_remote_sfence_vma
>>>  sbi_remote_sfence_vma_asid
>>>  sbi_shutdown
>>>  SBI Base Functionality
>>>  Timer Extension
>>>  IPI Extension
>>>  RFENCE Extension
>>>  Hart State Management Extension
>>>
>>> The command can be used to construct a unit test checking that the
>>> communication with the SEE is working.
>>>
>>> Signed-off-by: Heinrich Schuchardt 
>>> Reviewed-by: Atish Patra 
>>> Reviewed-by: Bin Meng 
>>> Tested-by: Bin Meng 
>>> ---
>>> v4:
>>>only show command name 'sbi' as short description in Kconfig menu
>>>as suggested by Bin
>>> v3:
>>>add dependency on CONFIG_SBI_V02
>>>use lower case for sbi in Kconfig
>>> v2:
>>>provide a non-blank long help text
>>> ---
>>> arch/riscv/include/asm/sbi.h |  2 +
>>> arch/riscv/lib/sbi.c | 36 
>>> cmd/Kconfig  |  6 +++
>>> cmd/riscv/Makefile   |  1 +
>>> cmd/riscv/sbi.c  | 82 
>>> 5 files changed, 127 insertions(+)
>>> create mode 100644 cmd/riscv/sbi.c
>>>
>>> diff --git a/arch/riscv/include/asm/sbi.h
>>> b/arch/riscv/include/asm/sbi.h index
>>> 08e1ac0c0e..53ca316180 100644
>>> --- a/arch/riscv/include/asm/sbi.h
>>> +++ b/arch/riscv/include/asm/sbi.h
>>> @@ -115,6 +115,8 @@ void sbi_remote_sfence_vma_asid(const unsigned
>>> long *hart_mask,
>>>unsigned long asid);  #endif  void
>>> sbi_set_timer(uint64_t stime_value);
>>> +long sbi_get_spec_version(void);
>>> +int sbi_get_impl_id(void);
>>> int sbi_probe_extension(int ext);
>>>
>>> #endif
>>> diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c index
>>> 8fbc23839d..920889ed13 100644
>>> --- a/arch/riscv/lib/sbi.c
>>> +++ b/arch/riscv/lib/sbi.c
>>> @@ -53,6 +53,42 @@ void sbi_set_timer(uint64_t stime_value)  #endif
>>> }
>>>
>>> +/**
>>> + * sbi_get_spec_version() - get current SBI specification version
>>> + *
>>> + * Return: version id
>>> + */
>>> +long sbi_get_spec_version(void)
>>> +{
>>> +   struct sbiret ret;
>>> +
>>> +   ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION,
>>> +   0, 0, 0, 0, 0, 0);
>>> +   if (!ret.error)
>>> +   if (ret.value)
>>> +   return ret.value;
>>> +
>>> +   return -ENOTSUPP;
>>> +}
>>> +
>>> +/**
>>> + * sbi_get_impl_id() - get SBI implementation ID
>>> + *
>>> + * Return: implementation ID
>>> + */
>>> +int sbi_get_impl_id(void)
>>> +{
>>> +   struct sbiret ret;
>>> +
>>> +   ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID,
>>> +   0, 0, 0, 0, 0, 0);
>>> +   if (!ret.error)
>>> +   if (ret.value)
>>> +   return ret.value;
>>> +
>>

RE: [PATCH 1/2] riscv: fu540: Use correct API to get L2 cache controller base address

[Pragnesh Patel]

>-Original Message-
>From: Bin Meng 
>Sent: 18 August 2020 13:39
>To: Rick Chen ; Pragnesh Patel
>; U-Boot Mailing List 
>Cc: Bin Meng 
>Subject: [PATCH 1/2] riscv: fu540: Use correct API to get L2 cache controller 
>base
>address
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>From: Bin Meng 
>
>At present fdtdec_get_addr() is used to get L2 cache controller base address. 
>This
>only works for a fixed #address-cells and #size-cells.
>Change to use fdtdec_get_addr_size_auto_parent() instead.
>
>Signed-off-by: Bin Meng 
>---
>
> arch/riscv/cpu/fu540/cache.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Pragnesh Patel 

RE: [PATCH v4 1/1] cmd: provide command sbi

[Pragnesh Patel]

Hi Heinrich,

>-Original Message-
>From: Pragnesh Patel
>Sent: 20 August 2020 17:00
>To: 'Heinrich Schuchardt' 
>Cc: Bin Meng ; Lukas Auer ; Atish Patra
>; u-boot@lists.denx.de; Bin Meng
>; Rick Chen 
>Subject: RE: [PATCH v4 1/1] cmd: provide command sbi
>
>Hi Heinrich,
>
>>-Original Message-
>>From: Heinrich Schuchardt 
>>Sent: 20 August 2020 16:23
>>To: Rick Chen 
>>Cc: Bin Meng ; Pragnesh Patel
>>; Lukas Auer ; Atish Patra
>>; u-boot@lists.denx.de; Heinrich Schuchardt
>>; Bin Meng 
>>Subject: [PATCH v4 1/1] cmd: provide command sbi
>>
>>[External Email] Do not click links or attachments unless you recognize
>>the sender and know the content is safe
>>
>>Provide a command to display information about the SBI implementation.
>>
>>The output might look like:
>>
>>=> sbi
>>SBI 0.2
>>OpenSBI
>>Extensions:
>>  sbi_set_timer
>>  sbi_console_putchar
>>  sbi_console_getchar
>>  sbi_clear_ipi
>>  sbi_send_ipi
>>  sbi_remote_fence_i
>>  sbi_remote_sfence_vma
>>  sbi_remote_sfence_vma_asid
>>  sbi_shutdown
>>  SBI Base Functionality
>>  Timer Extension
>>  IPI Extension
>>  RFENCE Extension
>>  Hart State Management Extension
>>
>>The command can be used to construct a unit test checking that the
>>communication with the SEE is working.
>>
>>Signed-off-by: Heinrich Schuchardt 
>>Reviewed-by: Atish Patra 
>>Reviewed-by: Bin Meng 
>>Tested-by: Bin Meng 
>>---
>>v4:
>>only show command name 'sbi' as short description in Kconfig menu
>>as suggested by Bin
>>v3:
>>add dependency on CONFIG_SBI_V02
>>use lower case for sbi in Kconfig
>>v2:
>>provide a non-blank long help text
>>---
>> arch/riscv/include/asm/sbi.h |  2 +
>> arch/riscv/lib/sbi.c | 36 
>> cmd/Kconfig  |  6 +++
>> cmd/riscv/Makefile   |  1 +
>> cmd/riscv/sbi.c  | 82 
>> 5 files changed, 127 insertions(+)
>> create mode 100644 cmd/riscv/sbi.c
>>
>>diff --git a/arch/riscv/include/asm/sbi.h
>>b/arch/riscv/include/asm/sbi.h index
>>08e1ac0c0e..53ca316180 100644
>>--- a/arch/riscv/include/asm/sbi.h
>>+++ b/arch/riscv/include/asm/sbi.h
>>@@ -115,6 +115,8 @@ void sbi_remote_sfence_vma_asid(const unsigned long
>>*hart_mask,
>>unsigned long asid);  #endif  void
>>sbi_set_timer(uint64_t stime_value);
>>+long sbi_get_spec_version(void);
>>+int sbi_get_impl_id(void);
>> int sbi_probe_extension(int ext);
>>
>> #endif
>>diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c index
>>8fbc23839d..920889ed13 100644
>>--- a/arch/riscv/lib/sbi.c
>>+++ b/arch/riscv/lib/sbi.c
>>@@ -53,6 +53,42 @@ void sbi_set_timer(uint64_t stime_value)  #endif  }
>>
>>+/**
>>+ * sbi_get_spec_version() - get current SBI specification version
>>+ *
>>+ * Return: version id
>>+ */
>>+long sbi_get_spec_version(void)
>>+{
>>+   struct sbiret ret;
>>+
>>+   ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION,
>>+   0, 0, 0, 0, 0, 0);
>>+   if (!ret.error)
>>+   if (ret.value)
>>+   return ret.value;
>>+
>>+   return -ENOTSUPP;
>>+}
>>+
>>+/**
>>+ * sbi_get_impl_id() - get SBI implementation ID
>>+ *
>>+ * Return: implementation ID
>>+ */
>>+int sbi_get_impl_id(void)
>>+{
>>+   struct sbiret ret;
>>+
>>+   ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID,
>>+   0, 0, 0, 0, 0, 0);
>>+   if (!ret.error)
>>+   if (ret.value)
>>+   return ret.value;
>>+
>>+   return -ENOTSUPP;
>>+}
>>+
>> /**
>>  * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
>>  * @extid: The extension ID to be probed.
>>diff --git a/cmd/Kconfig b/cmd/Kconfig
>>index 9ad511aa17..8feeb0ddb0 100644
>>--- a/cmd/Kconfig
>>+++ b/cmd/Kconfig
>>@@ -270,6 +270,12 @@ config SPL_CMD_TLV_EEPROM
>>help
>>  Read system EEPROM data block in ONIE Tlvinfo format from SPL.
>>
>>+config CMD_SBI
>>+   bool "sbi"
>>+   depends on RISCV_SMODE && SBI_V02
>>+   help
>>+ Display information about the SBI implementation.
>>+

RE: [PATCH v4 1/1] cmd: provide command sbi

[Pragnesh Patel]

Hi Heinrich,

>-Original Message-
>From: Heinrich Schuchardt 
>Sent: 20 August 2020 16:23
>To: Rick Chen 
>Cc: Bin Meng ; Pragnesh Patel
>; Lukas Auer ; Atish Patra
>; u-boot@lists.denx.de; Heinrich Schuchardt
>; Bin Meng 
>Subject: [PATCH v4 1/1] cmd: provide command sbi
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Provide a command to display information about the SBI implementation.
>
>The output might look like:
>
>=> sbi
>SBI 0.2
>OpenSBI
>Extensions:
>  sbi_set_timer
>  sbi_console_putchar
>  sbi_console_getchar
>  sbi_clear_ipi
>  sbi_send_ipi
>  sbi_remote_fence_i
>  sbi_remote_sfence_vma
>  sbi_remote_sfence_vma_asid
>  sbi_shutdown
>  SBI Base Functionality
>  Timer Extension
>  IPI Extension
>  RFENCE Extension
>  Hart State Management Extension
>
>The command can be used to construct a unit test checking that the
>communication with the SEE is working.
>
>Signed-off-by: Heinrich Schuchardt 
>Reviewed-by: Atish Patra 
>Reviewed-by: Bin Meng 
>Tested-by: Bin Meng 
>---
>v4:
>only show command name 'sbi' as short description in Kconfig menu
>as suggested by Bin
>v3:
>add dependency on CONFIG_SBI_V02
>use lower case for sbi in Kconfig
>v2:
>provide a non-blank long help text
>---
> arch/riscv/include/asm/sbi.h |  2 +
> arch/riscv/lib/sbi.c | 36 
> cmd/Kconfig  |  6 +++
> cmd/riscv/Makefile   |  1 +
> cmd/riscv/sbi.c  | 82 
> 5 files changed, 127 insertions(+)
> create mode 100644 cmd/riscv/sbi.c
>
>diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index
>08e1ac0c0e..53ca316180 100644
>--- a/arch/riscv/include/asm/sbi.h
>+++ b/arch/riscv/include/asm/sbi.h
>@@ -115,6 +115,8 @@ void sbi_remote_sfence_vma_asid(const unsigned long
>*hart_mask,
>unsigned long asid);  #endif  void 
> sbi_set_timer(uint64_t
>stime_value);
>+long sbi_get_spec_version(void);
>+int sbi_get_impl_id(void);
> int sbi_probe_extension(int ext);
>
> #endif
>diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c index
>8fbc23839d..920889ed13 100644
>--- a/arch/riscv/lib/sbi.c
>+++ b/arch/riscv/lib/sbi.c
>@@ -53,6 +53,42 @@ void sbi_set_timer(uint64_t stime_value)  #endif  }
>
>+/**
>+ * sbi_get_spec_version() - get current SBI specification version
>+ *
>+ * Return: version id
>+ */
>+long sbi_get_spec_version(void)
>+{
>+   struct sbiret ret;
>+
>+   ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION,
>+   0, 0, 0, 0, 0, 0);
>+   if (!ret.error)
>+   if (ret.value)
>+   return ret.value;
>+
>+   return -ENOTSUPP;
>+}
>+
>+/**
>+ * sbi_get_impl_id() - get SBI implementation ID
>+ *
>+ * Return: implementation ID
>+ */
>+int sbi_get_impl_id(void)
>+{
>+   struct sbiret ret;
>+
>+   ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID,
>+   0, 0, 0, 0, 0, 0);
>+   if (!ret.error)
>+   if (ret.value)
>+   return ret.value;
>+
>+   return -ENOTSUPP;
>+}
>+
> /**
>  * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
>  * @extid: The extension ID to be probed.
>diff --git a/cmd/Kconfig b/cmd/Kconfig
>index 9ad511aa17..8feeb0ddb0 100644
>--- a/cmd/Kconfig
>+++ b/cmd/Kconfig
>@@ -270,6 +270,12 @@ config SPL_CMD_TLV_EEPROM
>help
>  Read system EEPROM data block in ONIE Tlvinfo format from SPL.
>
>+config CMD_SBI
>+   bool "sbi"
>+   depends on RISCV_SMODE && SBI_V02
>+   help
>+ Display information about the SBI implementation.
>+
> endmenu
>
> menu "Boot commands"
>diff --git a/cmd/riscv/Makefile b/cmd/riscv/Makefile index
>24df023ece..1e6ac364e3 100644
>--- a/cmd/riscv/Makefile
>+++ b/cmd/riscv/Makefile
>@@ -1,3 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0+
>
> obj-$(CONFIG_CMD_EXCEPTION) += exception.o
>+obj-$(CONFIG_CMD_SBI) += sbi.o
>diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c new file mode 100644 index
>00..7c9151f436
>--- /dev/null
>+++ b/cmd/riscv/sbi.c
>@@ -0,0 +1,82 @@
>+// SPDX-License-Identifier: GPL-2.0+
>+/*
>+ * The 'sbi' command displays information about the SBI implementation.
>+ *
>+ * Copyright (c) 2020, Heinrich Schuchardt   */
>+
>+#include 
>+#include 
>+#include 
>+
>+struct sbi_ext {
>+   const u32 id;
>+   cons

RE: [PATCH v4 1/1] cmd: provide command sbi

[Pragnesh Patel]

>-Original Message-
>From: Heinrich Schuchardt 
>Sent: 20 August 2020 16:23
>To: Rick Chen 
>Cc: Bin Meng ; Pragnesh Patel
>; Lukas Auer ; Atish Patra
>; u-boot@lists.denx.de; Heinrich Schuchardt
>; Bin Meng 
>Subject: [PATCH v4 1/1] cmd: provide command sbi
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Provide a command to display information about the SBI implementation.
>
>The output might look like:
>
>=> sbi
>SBI 0.2
>OpenSBI
>Extensions:
>  sbi_set_timer
>  sbi_console_putchar
>  sbi_console_getchar
>  sbi_clear_ipi
>  sbi_send_ipi
>  sbi_remote_fence_i
>  sbi_remote_sfence_vma
>  sbi_remote_sfence_vma_asid
>  sbi_shutdown
>  SBI Base Functionality
>  Timer Extension
>  IPI Extension
>  RFENCE Extension
>  Hart State Management Extension
>
>The command can be used to construct a unit test checking that the
>communication with the SEE is working.
>
>Signed-off-by: Heinrich Schuchardt 
>Reviewed-by: Atish Patra 
>Reviewed-by: Bin Meng 
>Tested-by: Bin Meng 
>---
>v4:
>only show command name 'sbi' as short description in Kconfig menu
>as suggested by Bin
>v3:
>add dependency on CONFIG_SBI_V02
>use lower case for sbi in Kconfig
>v2:
>provide a non-blank long help text
>---
> arch/riscv/include/asm/sbi.h |  2 +
> arch/riscv/lib/sbi.c | 36 
> cmd/Kconfig  |  6 +++
> cmd/riscv/Makefile   |  1 +
> cmd/riscv/sbi.c  | 82 
> 5 files changed, 127 insertions(+)
> create mode 100644 cmd/riscv/sbi.c
>
>diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index
>08e1ac0c0e..53ca316180 100644
>--- a/arch/riscv/include/asm/sbi.h
>+++ b/arch/riscv/include/asm/sbi.h
>@@ -115,6 +115,8 @@ void sbi_remote_sfence_vma_asid(const unsigned long
>*hart_mask,
>unsigned long asid);  #endif  void 
> sbi_set_timer(uint64_t
>stime_value);
>+long sbi_get_spec_version(void);
>+int sbi_get_impl_id(void);
> int sbi_probe_extension(int ext);
>
> #endif
>diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c index
>8fbc23839d..920889ed13 100644
>--- a/arch/riscv/lib/sbi.c
>+++ b/arch/riscv/lib/sbi.c
>@@ -53,6 +53,42 @@ void sbi_set_timer(uint64_t stime_value)  #endif  }
>
>+/**
>+ * sbi_get_spec_version() - get current SBI specification version
>+ *
>+ * Return: version id
>+ */
>+long sbi_get_spec_version(void)
>+{
>+   struct sbiret ret;
>+
>+   ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION,
>+   0, 0, 0, 0, 0, 0);
>+   if (!ret.error)
>+   if (ret.value)
>+   return ret.value;
>+
>+   return -ENOTSUPP;
>+}
>+
>+/**
>+ * sbi_get_impl_id() - get SBI implementation ID
>+ *
>+ * Return: implementation ID
>+ */
>+int sbi_get_impl_id(void)
>+{
>+   struct sbiret ret;
>+
>+   ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID,
>+   0, 0, 0, 0, 0, 0);
>+   if (!ret.error)
>+   if (ret.value)
>+   return ret.value;
>+
>+   return -ENOTSUPP;
>+}
>+
> /**
>  * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
>  * @extid: The extension ID to be probed.
>diff --git a/cmd/Kconfig b/cmd/Kconfig
>index 9ad511aa17..8feeb0ddb0 100644
>--- a/cmd/Kconfig
>+++ b/cmd/Kconfig
>@@ -270,6 +270,12 @@ config SPL_CMD_TLV_EEPROM
>help
>  Read system EEPROM data block in ONIE Tlvinfo format from SPL.
>
>+config CMD_SBI
>+   bool "sbi"
>+   depends on RISCV_SMODE && SBI_V02
>+   help
>+ Display information about the SBI implementation.
>+
> endmenu
>
> menu "Boot commands"
>diff --git a/cmd/riscv/Makefile b/cmd/riscv/Makefile index
>24df023ece..1e6ac364e3 100644
>--- a/cmd/riscv/Makefile
>+++ b/cmd/riscv/Makefile
>@@ -1,3 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0+
>
> obj-$(CONFIG_CMD_EXCEPTION) += exception.o
>+obj-$(CONFIG_CMD_SBI) += sbi.o
>diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c new file mode 100644 index
>00..7c9151f436
>--- /dev/null
>+++ b/cmd/riscv/sbi.c
>@@ -0,0 +1,82 @@
>+// SPDX-License-Identifier: GPL-2.0+
>+/*
>+ * The 'sbi' command displays information about the SBI implementation.
>+ *
>+ * Copyright (c) 2020, Heinrich Schuchardt   */
>+
>+#include 
>+#include 
>+#include 
>+
>+struct sbi_ext {
>+   const u32 id;
>+   cons

[PATCH v3] common/board_f: make sure to call fix_fdt() before reserve_fdt()

[Pragnesh Patel]

There may be a chance that board specific fix_fdt() will change the
size of FDT blob so it's safe to call reserve_fdt() after fix_fdt()
otherwise global data (gd) will overwrite with FDT blob values.

Fixes: a8492e25ac71 ("riscv: Expand the DT size before copy reserved memory 
node")

Signed-off-by: Pragnesh Patel 
Reviewed-by: Bin Meng 
Reviewed-by: Rick Chen 
Reviewed-by: Atish Patra 
---

Changes in v3:
- Rebase on master

Changes in v2:
- Add Fixes tag

 common/board_f.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/common/board_f.c b/common/board_f.c
index 79532f4365..3932e0c69d 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -919,6 +919,9 @@ static const init_fnc_t init_sequence_f[] = {
 *  - board info struct
 */
setup_dest_addr,
+#ifdef CONFIG_OF_BOARD_FIXUP
+   fix_fdt,
+#endif
 #ifdef CONFIG_PRAM
reserve_pram,
 #endif
@@ -941,9 +944,6 @@ static const init_fnc_t init_sequence_f[] = {
INIT_FUNC_WATCHDOG_RESET
setup_bdinfo,
display_new_sp,
-#ifdef CONFIG_OF_BOARD_FIXUP
-   fix_fdt,
-#endif
INIT_FUNC_WATCHDOG_RESET
reloc_fdt,
reloc_bootstage,
-- 
2.17.1

RE: [PATCH v2] common/board_f: make sure to call fix_fdt() before reserve_fdt()

[Pragnesh Patel]

Hi Rick,

>-Original Message-
>From: Rick Chen 
>Sent: 13 August 2020 08:59
>To: Pragnesh Patel 
>Cc: U-Boot Mailing List ; Atish Patra
>; Bin Meng ; Anup Patel
>; Sagar Kadam ; Paul
>Walmsley ( Sifive) ; Simon Glass
>; ovpan...@gmail.com; swar...@nvidia.com; rick
>; Alan Kao 
>Subject: Re: [PATCH v2] common/board_f: make sure to call fix_fdt() before
>reserve_fdt()
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh
>
>> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
>> Sent: Thursday, August 06, 2020 3:55 PM
>> To: atish.pa...@wdc.com; bmeng...@gmail.com; u-boot@lists.denx.de;
>> anup.pa...@wdc.com; sagar.ka...@sifive.com; Rick Jian-Zhi Chen(陳建志)
>> Cc: paul.walms...@sifive.com; Pragnesh Patel; Simon Glass; Ovidiu
>> Panait; Stephen Warren; Patrick Delaunay; Joe Hershberger; Vikas
>> Manocha; Masahiro Yamada; Ye Li
>> Subject: [PATCH v2] common/board_f: make sure to call fix_fdt() before
>> reserve_fdt()
>>
>> There may be a chance that board specific fix_fdt() will change the size of 
>> FDT
>blob so it's safe to call reserve_fdt() after fix_fdt() otherwise global data 
>(gd) will
>overwrite with FDT blob values.
>>
>> Fixes: a8492e25ac71 ("riscv: Expand the DT size before copy reserved
>> memory node")
>>
>> Signed-off-by: Pragnesh Patel 
>> Reviewed-by: Bin Meng 
>> Reviewed-by: Rick Chen 
>> ---
>>  common/board_f.c | 6 +++---
>>  1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/common/board_f.c b/common/board_f.c index
>> 88ff0424a7..7ae01e9fff 100644
>> --- a/common/board_f.c
>> +++ b/common/board_f.c
>> @@ -956,6 +956,9 @@ static const init_fnc_t init_sequence_f[] = {
>>  *  - board info struct
>>  */
>> setup_dest_addr,
>> +#ifdef CONFIG_OF_BOARD_FIXUP
>> +   fix_fdt,
>> +#endif
>>  #ifdef CONFIG_PRAM
>> reserve_pram,
>>  #endif
>> @@ -984,9 +987,6 @@ static const init_fnc_t init_sequence_f[] = {
>> setup_board_part2,
>>  #endif
>> display_new_sp,
>> -#ifdef CONFIG_OF_BOARD_FIXUP
>> -   fix_fdt,
>> -#endif
>> INIT_FUNC_WATCHDOG_RESET
>> reloc_fdt,
>> reloc_bootstage,
>> --
>> 2.17.1
>>
>
>Applying: common/board_f: make sure to call fix_fdt() before reserve_fdt()
>error: patch failed: common/board_f.c:984
>error: common/board_f.c: patch does not apply Patch failed at 0001
>common/board_f: make sure to call fix_fdt() before reserve_fdt()

Will rebase and send it again.

>
>Thanks,
>Rick

RE: [PATCH] common/board_f: make sure to call fix_fdt() before reserve_fdt()

[Pragnesh Patel]

Hi Atish,

>-Original Message-
>From: Atish Patra 
>Sent: 10 August 2020 01:51
>To: Pragnesh Patel 
>Cc: Atish Patra ; Bin Meng ; U-
>Boot Mailing List ; Anup Patel ;
>Sagar Kadam ; Rick Chen ;
>Paul Walmsley ( Sifive) ; Simon Glass
>; Ovidiu Panait ; Stephen Warren
>; Patrick Delaunay ; Vikas
>Manocha ; Masahiro Yamada
>; Ye Li 
>Subject: Re: [PATCH] common/board_f: make sure to call fix_fdt() before
>reserve_fdt()
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On Wed, Aug 5, 2020 at 2:01 AM Pragnesh Patel 
>wrote:
>>
>> There may be a chance that board specific fix_fdt() will change the
>> size of FDT blob so it's safe to call reserve_fdt() after fix_fdt()
>> otherwise global data (gd) will overwrite with FDT blob values.
>>
>> Signed-off-by: Pragnesh Patel 
>> ---
>>  common/board_f.c | 6 +++---
>>  1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/common/board_f.c b/common/board_f.c index
>> 88ff0424a7..7ae01e9fff 100644
>> --- a/common/board_f.c
>> +++ b/common/board_f.c
>> @@ -956,6 +956,9 @@ static const init_fnc_t init_sequence_f[] = {
>>  *  - board info struct
>>  */
>> setup_dest_addr,
>> +#ifdef CONFIG_OF_BOARD_FIXUP
>> +   fix_fdt,
>> +#endif
>>  #ifdef CONFIG_PRAM
>> reserve_pram,
>>  #endif
>> @@ -984,9 +987,6 @@ static const init_fnc_t init_sequence_f[] = {
>> setup_board_part2,
>>  #endif
>> display_new_sp,
>> -#ifdef CONFIG_OF_BOARD_FIXUP
>> -   fix_fdt,
>> -#endif
>> INIT_FUNC_WATCHDOG_RESET
>> reloc_fdt,
>> reloc_bootstage,
>> --
>> 2.17.1
>>
>
>
>Reviewed-by: Atish Patra 

Thanks for the review, can you please send your Reviewed-by tag in the v2 
version of this patch.

>--
>Regards,
>Atish

RE: [PATCH] common/board_f: make sure to call fix_fdt() before reserve_fdt()

[Pragnesh Patel]

Hi Bin,

>-Original Message-
>From: Bin Meng 
>Sent: 06 August 2020 13:43
>To: Pragnesh Patel 
>Cc: Rick Chen ; U-Boot Mailing List b...@lists.denx.de>; Atish Patra ; Anup Patel
>; Sagar Kadam ; Paul
>Walmsley ( Sifive) ; Simon Glass
>; ovpan...@gmail.com; swar...@nvidia.com;
>patrick.delau...@st.com; vikas.mano...@st.com; masahi...@kernel.org;
>ye...@nxp.com; rick ; Alan Kao
>
>Subject: Re: [PATCH] common/board_f: make sure to call fix_fdt() before
>reserve_fdt()
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On Thu, Aug 6, 2020 at 12:44 PM Pragnesh Patel 
>wrote:
>>
>> Hi Rick,
>>
>> >-Original Message-
>> >From: Rick Chen 
>> >Sent: 06 August 2020 08:22
>> >To: Pragnesh Patel 
>> >Cc: U-Boot Mailing List ; Atish Patra
>> >; Bin Meng ; Anup Patel
>> >; Sagar Kadam ; Paul
>> >Walmsley ( Sifive) ; Simon Glass
>> >; ovpan...@gmail.com; swar...@nvidia.com;
>> >patrick.delau...@st.com; vikas.mano...@st.com; masahi...@kernel.org;
>> >ye...@nxp.com; rick ; Alan Kao
>> >
>> >Subject: Re: [PATCH] common/board_f: make sure to call fix_fdt()
>> >before
>> >reserve_fdt()
>> >
>> >[External Email] Do not click links or attachments unless you
>> >recognize the sender and know the content is safe
>> >
>> >Hi Pragnesh
>> >
>> >> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
>> >> Sent: Wednesday, August 05, 2020 5:01 PM
>> >> To: atish.pa...@wdc.com; bmeng...@gmail.com; u-boot@lists.denx.de;
>> >> anup.pa...@wdc.com; sagar.ka...@sifive.com; Rick Jian-Zhi Chen(陳建志)
>> >> Cc: paul.walms...@sifive.com; Pragnesh Patel; Simon Glass; Ovidiu
>> >> Panait; Stephen Warren; Patrick Delaunay; Vikas Manocha; Masahiro
>> >> Yamada; Ye Li
>> >> Subject: [PATCH] common/board_f: make sure to call fix_fdt() before
>> >> reserve_fdt()
>> >>
>> >> There may be a chance that board specific fix_fdt() will change the
>> >> size of FDT
>> >blob so it's safe to call reserve_fdt() after fix_fdt() otherwise
>> >global data (gd) will overwrite with FDT blob values.
>> >>
>> >> Signed-off-by: Pragnesh Patel 
>> >> ---
>> >>  common/board_f.c | 6 +++---
>> >>  1 file changed, 3 insertions(+), 3 deletions(-)
>> >>
>> >
>> >Maybe you can add the fix tag if it is caused by this.
>> >Fixes: a8492e25ac71 ("riscv: Expand the DT size before copy reserved
>> >memory
>> >node")
>> >
>> >Reviewed-by: Rick Chen 
>>
>> Good suggestion, will update in v2. Thanks for the review.
>
>I tend to disagree. The ordering issue is there for a long time and not 
>introduced
>by a8492e25ac71 so "Fixes" tag is not accurate.
>
>It's just a8492e25ac71 triggered the bug, not introduced the bug.

I agreed with you that "a8492e25ac71 triggered the bug, not introduced the bug" 
but this patch obviously add a fix
for " a8492e25ac71 " so IMHO there is nothing wrong to add Fixes tag in this 
patch.

If I miss any other Fixes tag for this patch just let me know.

>
>>
>> >
>> >> diff --git a/common/board_f.c b/common/board_f.c index
>> >> 88ff0424a7..7ae01e9fff 100644
>> >> --- a/common/board_f.c
>> >> +++ b/common/board_f.c
>> >> @@ -956,6 +956,9 @@ static const init_fnc_t init_sequence_f[] = {
>> >>  *  - board info struct
>> >>  */
>> >> setup_dest_addr,
>> >> +#ifdef CONFIG_OF_BOARD_FIXUP
>> >> +   fix_fdt,
>> >> +#endif
>> >>  #ifdef CONFIG_PRAM
>> >> reserve_pram,
>> >>  #endif
>> >> @@ -984,9 +987,6 @@ static const init_fnc_t init_sequence_f[] = {
>> >> setup_board_part2,
>> >>  #endif
>> >> display_new_sp,
>> >> -#ifdef CONFIG_OF_BOARD_FIXUP
>> >> -   fix_fdt,
>> >> -#endif
>> >> INIT_FUNC_WATCHDOG_RESET
>> >> reloc_fdt,
>> >> reloc_bootstage,
>
>Regards,
>Bin

[PATCH v2] common/board_f: make sure to call fix_fdt() before reserve_fdt()

[Pragnesh Patel]

There may be a chance that board specific fix_fdt() will change the
size of FDT blob so it's safe to call reserve_fdt() after fix_fdt()
otherwise global data (gd) will overwrite with FDT blob values.

Fixes: a8492e25ac71 ("riscv: Expand the DT size before copy reserved memory 
node")

Signed-off-by: Pragnesh Patel 
Reviewed-by: Bin Meng 
Reviewed-by: Rick Chen 
---
 common/board_f.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/common/board_f.c b/common/board_f.c
index 88ff0424a7..7ae01e9fff 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -956,6 +956,9 @@ static const init_fnc_t init_sequence_f[] = {
 *  - board info struct
 */
setup_dest_addr,
+#ifdef CONFIG_OF_BOARD_FIXUP
+   fix_fdt,
+#endif
 #ifdef CONFIG_PRAM
reserve_pram,
 #endif
@@ -984,9 +987,6 @@ static const init_fnc_t init_sequence_f[] = {
setup_board_part2,
 #endif
display_new_sp,
-#ifdef CONFIG_OF_BOARD_FIXUP
-   fix_fdt,
-#endif
INIT_FUNC_WATCHDOG_RESET
reloc_fdt,
reloc_bootstage,
-- 
2.17.1

RE: [PATCH 6/6] riscv: sifive/fu540: Move SPL related functions to spl.c

[Pragnesh Patel]

>-Original Message-
>From: Bin Meng 
>Sent: 03 August 2020 11:39
>To: Rick Chen ; Pragnesh Patel
>; U-Boot Mailing List 
>Cc: Bin Meng 
>Subject: [PATCH 6/6] riscv: sifive/fu540: Move SPL related functions to spl.c
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>From: Bin Meng 
>
>It's better to keep all SPL related functions in the same spl.c.
>
>Signed-off-by: Bin Meng 
>---
>
> board/sifive/fu540/fu540.c | 33 -
> board/sifive/fu540/spl.c   | 33 -
> 2 files changed, 32 insertions(+), 34 deletions(-)
>

Reviewed-by: Pragnesh Patel 
Tested-by: Pragnesh Patel 

RE: [PATCH 5/6] riscv: sifive/fu540: Drop NET_RANDOM_ETHADDR

[Pragnesh Patel]

>-Original Message-
>From: Bin Meng 
>Sent: 03 August 2020 11:39
>To: Rick Chen ; Pragnesh Patel
>; U-Boot Mailing List 
>Cc: Bin Meng 
>Subject: [PATCH 5/6] riscv: sifive/fu540: Drop NET_RANDOM_ETHADDR
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>From: Bin Meng 
>
>This option was enabled during the earlier U-Boot porting time. Now we already
>have the OTP driver in place and the unique MAC address is read from the OTP,
>there is no need to turn on this option.
>
>Signed-off-by: Bin Meng 
>---
>
> board/sifive/fu540/Kconfig | 1 -
> 1 file changed, 1 deletion(-)
>

Reviewed-by: Pragnesh Patel 
Tested-by: Pragnesh Patel 

RE: [PATCH 4/6] riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level

[Pragnesh Patel]

>-Original Message-
>From: Bin Meng 
>Sent: 03 August 2020 11:39
>To: Rick Chen ; Pragnesh Patel
>; U-Boot Mailing List 
>Cc: Bin Meng 
>Subject: [PATCH 4/6] riscv: sifive/fu540: kconfig: Move FU540 driver related
>options to the SoC level
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>From: Bin Meng 
>
>All FU540 driver related options should be in the SoC level Kconfig.
>
>Signed-off-by: Bin Meng 
>---
>
> arch/riscv/cpu/fu540/Kconfig | 22 ++
> board/sifive/fu540/Kconfig   | 22 --
> 2 files changed, 22 insertions(+), 22 deletions(-)
>

Reviewed-by: Pragnesh Patel 
Tested-by: Pragnesh Patel 

RE: [PATCH 3/6] riscv: sifive/fu540: spl: Rename soc_spl_init()

[Pragnesh Patel]

>-Original Message-
>From: Bin Meng 
>Sent: 03 August 2020 11:39
>To: Rick Chen ; Pragnesh Patel
>; U-Boot Mailing List 
>Cc: Bin Meng 
>Subject: [PATCH 3/6] riscv: sifive/fu540: spl: Rename soc_spl_init()
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>From: Bin Meng 
>
>spl_soc_init() seems to be a better name, as all SPL functions names start from
>the spl_ prefix.
>
>Signed-off-by: Bin Meng 
>---
>
> arch/riscv/cpu/fu540/spl.c  | 2 +-
> arch/riscv/include/asm/arch-fu540/spl.h | 2 +-
> board/sifive/fu540/spl.c| 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>

Reviewed-by: Pragnesh Patel 
Tested-by: Pragnesh Patel 

RE: [PATCH 2/6] riscv: sifive/fu540: spl: Drop our own version of board_init_f()

[Pragnesh Patel]

>-Original Message-
>From: Bin Meng 
>Sent: 03 August 2020 11:39
>To: Rick Chen ; Pragnesh Patel
>; U-Boot Mailing List 
>Cc: Bin Meng 
>Subject: [PATCH 2/6] riscv: sifive/fu540: spl: Drop our own version of
>board_init_f()
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>From: Bin Meng 
>
>Use the generic board_init_f() provided by the RISC-V library codes.
>
>Signed-off-by: Bin Meng 
>---
>
> board/sifive/fu540/spl.c | 19 +--
> 1 file changed, 1 insertion(+), 18 deletions(-)
>

Reviewed-by: Pragnesh Patel 
Tested-by: Pragnesh Patel 

RE: [PATCH 1/6] riscv: Call spl_board_init_f() in the generic SPL board_init_f()

[Pragnesh Patel]

>-Original Message-
>From: Bin Meng 
>Sent: 03 August 2020 11:39
>To: Rick Chen ; Pragnesh Patel
>; U-Boot Mailing List 
>Cc: Bin Meng 
>Subject: [PATCH 1/6] riscv: Call spl_board_init_f() in the generic SPL
>board_init_f()
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>From: Bin Meng 
>
>The generic SPL version of board_init_f() should give a call to board specific
>codes to initialize board in the SPL phase.
>
>Signed-off-by: Bin Meng 
>---
>
> arch/riscv/include/asm/spl.h | 7 +++
> arch/riscv/lib/spl.c     | 9 +++++
> 2 files changed, 16 insertions(+)

Reviewed-by: Pragnesh Patel 
Tested-by: Pragnesh Patel 

RE: [PATCH] common/board_f: make sure to call fix_fdt() before reserve_fdt()

[Pragnesh Patel]

Hi Rick,

>-Original Message-
>From: Rick Chen 
>Sent: 06 August 2020 08:22
>To: Pragnesh Patel 
>Cc: U-Boot Mailing List ; Atish Patra
>; Bin Meng ; Anup Patel
>; Sagar Kadam ; Paul
>Walmsley ( Sifive) ; Simon Glass
>; ovpan...@gmail.com; swar...@nvidia.com;
>patrick.delau...@st.com; vikas.mano...@st.com; masahi...@kernel.org;
>ye...@nxp.com; rick ; Alan Kao
>
>Subject: Re: [PATCH] common/board_f: make sure to call fix_fdt() before
>reserve_fdt()
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh
>
>> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
>> Sent: Wednesday, August 05, 2020 5:01 PM
>> To: atish.pa...@wdc.com; bmeng...@gmail.com; u-boot@lists.denx.de;
>> anup.pa...@wdc.com; sagar.ka...@sifive.com; Rick Jian-Zhi Chen(陳建志)
>> Cc: paul.walms...@sifive.com; Pragnesh Patel; Simon Glass; Ovidiu
>> Panait; Stephen Warren; Patrick Delaunay; Vikas Manocha; Masahiro
>> Yamada; Ye Li
>> Subject: [PATCH] common/board_f: make sure to call fix_fdt() before
>> reserve_fdt()
>>
>> There may be a chance that board specific fix_fdt() will change the size of 
>> FDT
>blob so it's safe to call reserve_fdt() after fix_fdt() otherwise global data 
>(gd) will
>overwrite with FDT blob values.
>>
>> Signed-off-by: Pragnesh Patel 
>> ---
>>  common/board_f.c | 6 +++---
>>  1 file changed, 3 insertions(+), 3 deletions(-)
>>
>
>Maybe you can add the fix tag if it is caused by this.
>Fixes: a8492e25ac71 ("riscv: Expand the DT size before copy reserved memory
>node")
>
>Reviewed-by: Rick Chen 

Good suggestion, will update in v2. Thanks for the review.

>
>> diff --git a/common/board_f.c b/common/board_f.c index
>> 88ff0424a7..7ae01e9fff 100644
>> --- a/common/board_f.c
>> +++ b/common/board_f.c
>> @@ -956,6 +956,9 @@ static const init_fnc_t init_sequence_f[] = {
>>  *  - board info struct
>>  */
>> setup_dest_addr,
>> +#ifdef CONFIG_OF_BOARD_FIXUP
>> +   fix_fdt,
>> +#endif
>>  #ifdef CONFIG_PRAM
>> reserve_pram,
>>  #endif
>> @@ -984,9 +987,6 @@ static const init_fnc_t init_sequence_f[] = {
>> setup_board_part2,
>>  #endif
>> display_new_sp,
>> -#ifdef CONFIG_OF_BOARD_FIXUP
>> -   fix_fdt,
>> -#endif
>> INIT_FUNC_WATCHDOG_RESET
>> reloc_fdt,
>> reloc_bootstage,
>> --
>> 2.17.1

RE: master u-boot broken for HiFive Unleashed

[Pragnesh Patel]

Hi Atish,

I just sent a patch to solve this issue.
https://patchwork.ozlabs.org/project/uboot/patch/20200805090053.11805-1-pragnesh.pa...@sifive.com/


Thanks,
Pragnesh

>-Original Message-
>From: U-Boot  On Behalf Of Pragnesh Patel
>Sent: 04 August 2020 20:03
>To: Atish Patra ; Bin Meng ;
>Rick Chen 
>Cc: Anup Patel ; Lukas Auer
>; U-Boot Mailing List 
>Subject: RE: master u-boot broken for HiFive Unleashed
>
>Hi Atish,
>
>>-Original Message-
>>From: U-Boot  On Behalf Of Pragnesh Patel
>>Sent: 04 August 2020 19:55
>>To: Atish Patra ; Bin Meng ;
>>Rick Chen 
>>Cc: Anup Patel ; Lukas Auer
>>; U-Boot Mailing List
>>
>>Subject: RE: master u-boot broken for HiFive Unleashed
>>
>>Hi Atish,
>>
>>I tried to debug this and find something interesting.
>>
>>With FSBL,
>>I am able to reproduce the same and found that if I will disable
>>CONFIG_OF_BOARD_FIXUP and then print the bdinfo shows expected result.
>>
>>=> bdinfo
>>boot_params = 0x
>>DRAM bank   = 0x
>>-> start= 0x8000
>>-> size = 0x0002
>>memstart= 0x
>>memsize = 0x
>>flashstart  = 0x
>>flashsize   = 0x
>>flashoffset = 0x
>>baudrate= 115200 bps
>>relocaddr   = 0xfff83000
>>reloc off   = 0x7fd83000
>>Build   = 64-bit
>>current eth = ethernet@1009
>>ethaddr = (not set)
>>IP addr = 
>>fdt_blob= 0xff75e680
>>new_fdt = 0xff75e680
>>fdt_size= 0x47a0
>>=>
>>
>>With CONFIG_OF_BOARD_FIXUP, following functions gets called
>>fix_fdt() ("common/board_f.c") -> board_fix_fdt()
>>("arch/riscv/lib/fdt_fixup.c") and in this we will increase the
>>fdt_blob size for PMP regions
>>
>>/*
>> * Extend the FDT by the following estimated size:
>> *
>> * Each PMP memory region entry occupies 64 bytes.
>> * With 16 PMP memory regions we need 64 * 16 = 1024 bytes.
>> */
>>err = fdt_open_into(dst, dst, fdt_totalsize(dst) + 1024);
>>
>>I suspect this will overwrite the global data (gd) and that creates the 
>>problem.
>>
>>
>>Surprisingly With U-Boot SPL,
>>Latest U-Boot master branch works fine and shows expected results.
>
>With U-Boot SPL it works because in riscv_board_reserved_mem_fixup()
>("arch/riscv/lib/fdt_fixup.c")
>
>riscv_board_reserved_mem_fixup() {
>/* avoid the copy if we are using the same device tree */
>if (src_fdt_addr == fdt)
>return 0;
>
>   riscv_fdt_copy_resv_mem_node();
>}
>
>OpenSBI and U-Boot both are using the same device tree (U-Boot SPL sends U-
>Boot device tree address in a1 register to OpenSBI), so
>riscv_fdt_copy_resv_mem_node() never gets called.
>
>
>With FSBL, OpenSBI and U-Boot uses different device tree so
>riscv_board_reserved_mem_fixup() ("arch/riscv/lib/fdt_fixup.c"), so
>riscv_fdt_copy_resv_mem_node() getting called and tried to increase the
>fdt_blob size which will overwrite the global data (gd).
>
>
>
>>
>>>-Original Message-
>>>From: Atish Patra 
>>>Sent: 30 July 2020 03:13
>>>To: U-Boot Mailing List ; Bin Meng
>>>; Rick Chen 
>>>Cc: Anup Patel ; Lukas Auer
>>>; Pragnesh Patel
>>>
>>>Subject: master u-boot broken for HiFive Unleashed
>>>
>>>[External Email] Do not click links or attachments unless you recognize
>>>the sender and know the content is safe
>>>
>>>Hi,
>>>The latest master (423e08cb7701 (origin/master, origin/HEAD) Merge
>>>branch
>>>'2020-07-28-misc-soc-improvements') seems to be broken for HiFive
>>Unleashed.
>>>
>>>It already has Bin's fix for unleashed.
>>>
>>>a0018fc8209c riscv: Make SiFive HiFive Unleashed board boot again
>>>
>>>dram start and size is corrupted for some reason. I have verified that
>>>it was initialized properly during DT parsing. However, it shows random
>>>values in the U- Boot console.
>>>
>>>=> bdinfo
>>>boot_params = 0x
>>>memstart= 0x
>>>memsize = 0x
>>>flashstart  = 0x
>>>flashsize   = 0x
>>>flashoffset = 0x
>>>baudrate= 115200 bps
>>>relocaddr   = 0xfff84000
>>>reloc off   = 0x7fd84000
>>>Build   = 64-bit
>>>
>>>=> bdinfo
>>>boot_params = 0x9a26a361c16aa601
>>>DRAM bank   = 0x
>>>-> start= 0x974515c3bda965ef
>>>-> size = 0x79b6f0fb37923036
>>>memstart= 0x574587c7f00570f9
>>>memsize = 0xCFD8C0F4D42668AB
>>>flashstart  = 0x67f9fbb06586658b
>>>flashsize   = 0xf91aed913c99b9e1
>>>flashoffset = 0x9ddbf00d69e870fa
>>>baudrate= 115200 bps
>>>
>>>v2020.07 seems to work fine. I couldn't bisect between those two as the
>>>number of commits didn't compile.
>>>
>>>--
>>>Regards,
>>>Atish

[PATCH] common/board_f: make sure to call fix_fdt() before reserve_fdt()

[Pragnesh Patel]

There may be a chance that board specific fix_fdt() will change the
size of FDT blob so it's safe to call reserve_fdt() after fix_fdt()
otherwise global data (gd) will overwrite with FDT blob values.

Signed-off-by: Pragnesh Patel 
---
 common/board_f.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/common/board_f.c b/common/board_f.c
index 88ff0424a7..7ae01e9fff 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -956,6 +956,9 @@ static const init_fnc_t init_sequence_f[] = {
 *  - board info struct
 */
setup_dest_addr,
+#ifdef CONFIG_OF_BOARD_FIXUP
+   fix_fdt,
+#endif
 #ifdef CONFIG_PRAM
reserve_pram,
 #endif
@@ -984,9 +987,6 @@ static const init_fnc_t init_sequence_f[] = {
setup_board_part2,
 #endif
display_new_sp,
-#ifdef CONFIG_OF_BOARD_FIXUP
-   fix_fdt,
-#endif
INIT_FUNC_WATCHDOG_RESET
reloc_fdt,
reloc_bootstage,
-- 
2.17.1

RE: master u-boot broken for HiFive Unleashed

[Pragnesh Patel]

Hi Atish,

>-Original Message-
>From: U-Boot  On Behalf Of Pragnesh Patel
>Sent: 04 August 2020 19:55
>To: Atish Patra ; Bin Meng ;
>Rick Chen 
>Cc: Anup Patel ; Lukas Auer
>; U-Boot Mailing List 
>Subject: RE: master u-boot broken for HiFive Unleashed
>
>Hi Atish,
>
>I tried to debug this and find something interesting.
>
>With FSBL,
>I am able to reproduce the same and found that if I will disable
>CONFIG_OF_BOARD_FIXUP and then print the bdinfo shows expected result.
>
>=> bdinfo
>boot_params = 0x
>DRAM bank   = 0x
>-> start= 0x8000
>-> size = 0x0002
>memstart= 0x
>memsize = 0x
>flashstart  = 0x
>flashsize   = 0x
>flashoffset = 0x
>baudrate= 115200 bps
>relocaddr   = 0xfff83000
>reloc off   = 0x7fd83000
>Build   = 64-bit
>current eth = ethernet@1009
>ethaddr = (not set)
>IP addr = 
>fdt_blob= 0xff75e680
>new_fdt = 0xff75e680
>fdt_size= 0x47a0
>=>
>
>With CONFIG_OF_BOARD_FIXUP, following functions gets called
>fix_fdt() ("common/board_f.c") -> board_fix_fdt() 
>("arch/riscv/lib/fdt_fixup.c")
>and in this we will increase the fdt_blob size for PMP regions
>
>/*
> * Extend the FDT by the following estimated size:
> *
> * Each PMP memory region entry occupies 64 bytes.
> * With 16 PMP memory regions we need 64 * 16 = 1024 bytes.
> */
>err = fdt_open_into(dst, dst, fdt_totalsize(dst) + 1024);
>
>I suspect this will overwrite the global data (gd) and that creates the 
>problem.
>
>
>Surprisingly With U-Boot SPL,
>Latest U-Boot master branch works fine and shows expected results.

With U-Boot SPL it works because in riscv_board_reserved_mem_fixup() 
("arch/riscv/lib/fdt_fixup.c")

riscv_board_reserved_mem_fixup() {
/* avoid the copy if we are using the same device tree */
if (src_fdt_addr == fdt)
return 0;

riscv_fdt_copy_resv_mem_node();
}

OpenSBI and U-Boot both are using the same device tree (U-Boot SPL sends U-Boot 
device tree address in a1 register to OpenSBI), so 
riscv_fdt_copy_resv_mem_node() never gets called.


With FSBL, OpenSBI and U-Boot uses different device tree so 
riscv_board_reserved_mem_fixup() ("arch/riscv/lib/fdt_fixup.c"), so 
riscv_fdt_copy_resv_mem_node() getting called and tried to increase the 
fdt_blob size which will overwrite the global data (gd).



>
>>-Original Message-
>>From: Atish Patra 
>>Sent: 30 July 2020 03:13
>>To: U-Boot Mailing List ; Bin Meng
>>; Rick Chen 
>>Cc: Anup Patel ; Lukas Auer
>>; Pragnesh Patel
>>
>>Subject: master u-boot broken for HiFive Unleashed
>>
>>[External Email] Do not click links or attachments unless you recognize
>>the sender and know the content is safe
>>
>>Hi,
>>The latest master (423e08cb7701 (origin/master, origin/HEAD) Merge
>>branch
>>'2020-07-28-misc-soc-improvements') seems to be broken for HiFive
>Unleashed.
>>
>>It already has Bin's fix for unleashed.
>>
>>a0018fc8209c riscv: Make SiFive HiFive Unleashed board boot again
>>
>>dram start and size is corrupted for some reason. I have verified that
>>it was initialized properly during DT parsing. However, it shows random
>>values in the U- Boot console.
>>
>>=> bdinfo
>>boot_params = 0x
>>memstart= 0x
>>memsize = 0x
>>flashstart  = 0x
>>flashsize   = 0x
>>flashoffset = 0x
>>baudrate= 115200 bps
>>relocaddr   = 0xfff84000
>>reloc off   = 0x7fd84000
>>Build   = 64-bit
>>
>>=> bdinfo
>>boot_params = 0x9a26a361c16aa601
>>DRAM bank   = 0x
>>-> start= 0x974515c3bda965ef
>>-> size = 0x79b6f0fb37923036
>>memstart= 0x574587c7f00570f9
>>memsize = 0xCFD8C0F4D42668AB
>>flashstart  = 0x67f9fbb06586658b
>>flashsize   = 0xf91aed913c99b9e1
>>flashoffset = 0x9ddbf00d69e870fa
>>baudrate= 115200 bps
>>
>>v2020.07 seems to work fine. I couldn't bisect between those two as the
>>number of commits didn't compile.
>>
>>--
>>Regards,
>>Atish

RE: master u-boot broken for HiFive Unleashed

[Pragnesh Patel]

Hi Atish,

I tried to debug this and find something interesting.

With FSBL,
I am able to reproduce the same and found that if I will disable 
CONFIG_OF_BOARD_FIXUP and then print the bdinfo shows expected result.

=> bdinfo
boot_params = 0x
DRAM bank   = 0x
-> start= 0x8000
-> size = 0x0002
memstart= 0x
memsize = 0x
flashstart  = 0x
flashsize   = 0x
flashoffset = 0x
baudrate= 115200 bps
relocaddr   = 0xfff83000
reloc off   = 0x7fd83000
Build   = 64-bit
current eth = ethernet@1009
ethaddr = (not set)
IP addr = 
fdt_blob= 0xff75e680
new_fdt = 0xff75e680
fdt_size= 0x47a0
=>

With CONFIG_OF_BOARD_FIXUP, following functions gets called
fix_fdt() ("common/board_f.c") -> board_fix_fdt() 
("arch/riscv/lib/fdt_fixup.c") and in this we will increase the fdt_blob size 
for PMP regions

/*
 * Extend the FDT by the following estimated size:
 *
 * Each PMP memory region entry occupies 64 bytes.
 * With 16 PMP memory regions we need 64 * 16 = 1024 bytes.
 */
err = fdt_open_into(dst, dst, fdt_totalsize(dst) + 1024);

I suspect this will overwrite the global data (gd) and that creates the problem.


Surprisingly With U-Boot SPL,
Latest U-Boot master branch works fine and shows expected results.

>-Original Message-
>From: Atish Patra 
>Sent: 30 July 2020 03:13
>To: U-Boot Mailing List ; Bin Meng
>; Rick Chen 
>Cc: Anup Patel ; Lukas Auer
>; Pragnesh Patel 
>Subject: master u-boot broken for HiFive Unleashed
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi,
>The latest master (423e08cb7701 (origin/master, origin/HEAD) Merge branch
>'2020-07-28-misc-soc-improvements') seems to be broken for HiFive Unleashed.
>
>It already has Bin's fix for unleashed.
>
>a0018fc8209c riscv: Make SiFive HiFive Unleashed board boot again
>
>dram start and size is corrupted for some reason. I have verified that it was
>initialized properly during DT parsing. However, it shows random values in the 
>U-
>Boot console.
>
>=> bdinfo
>boot_params = 0x
>memstart= 0x
>memsize = 0x
>flashstart  = 0x
>flashsize   = 0x
>flashoffset = 0x
>baudrate= 115200 bps
>relocaddr   = 0xfff84000
>reloc off   = 0x7fd84000
>Build   = 64-bit
>
>=> bdinfo
>boot_params = 0x9a26a361c16aa601
>DRAM bank   = 0x
>-> start= 0x974515c3bda965ef
>-> size = 0x79b6f0fb37923036
>memstart= 0x574587c7f00570f9
>memsize = 0xCFD8C0F4D42668AB
>flashstart  = 0x67f9fbb06586658b
>flashsize   = 0xf91aed913c99b9e1
>flashoffset = 0x9ddbf00d69e870fa
>baudrate= 115200 bps
>
>v2020.07 seems to work fine. I couldn't bisect between those two as the number
>of commits didn't compile.
>
>--
>Regards,
>Atish

RE: [PATCH 1/1] riscv: sifive: fu540: redundant initialization

[Pragnesh Patel]

>-Original Message-
>From: Heinrich Schuchardt 
>Sent: 04 August 2020 02:40
>To: Rick Chen 
>Cc: Pragnesh Patel ; Bin Meng
>; u-boot@lists.denx.de; Heinrich Schuchardt
>
>Subject: [PATCH 1/1] riscv: sifive: fu540: redundant initialization
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>We should not initialize a variable if the value is overwritten before being 
>read.
>
>Signed-off-by: Heinrich Schuchardt 
>---
> arch/riscv/cpu/fu540/cache.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Pragnesh Patel 
Tested-by: Pragnesh Patel 

RE: [PATCH 6/6] riscv: Update SiFive device tree for new CLINT driver

[Pragnesh Patel]

Hi Sean,

>-Original Message-
>From: Sean Anderson 
>Sent: 23 July 2020 19:27
>To: Bin Meng ; Pragnesh Patel
>; Sagar Kadam 
>Cc: U-Boot Mailing List ; Rick Chen
>
>Subject: Re: [PATCH 6/6] riscv: Update SiFive device tree for new CLINT driver
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On 7/23/20 9:50 AM, Bin Meng wrote:
>> Hi Sean,
>>
>> On Wed, Jul 22, 2020 at 11:51 PM Sean Anderson 
>wrote:
>>>
>>> We may need to add a clock-frequency binding like for the K210.
>>>
>>> Signed-off-by: Sean Anderson 
>>> ---
>>> This patch builds but has NOT been tested.
>>>
>>>  arch/riscv/dts/fu540-c000-u-boot.dtsi | 7 ++-
>>>  1 file changed, 6 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi
>>> b/arch/riscv/dts/fu540-c000-u-boot.dtsi
>>> index afdb4f4402..e56bfc7595 100644
>>> --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
>>> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
>>> @@ -55,8 +55,13 @@
>>> };
>>> clint@200 {
>>> compatible = "riscv,clint0";
>>> -   interrupts-extended = <_intc 3 _intc 7 
>>> _intc
>3 _intc 7 _intc 3 _intc 7 _intc 3 _intc 7
>_intc 3 _intc 7>;
>>> +   interrupts-extended = <_intc 3 _intc 7
>>> +  _intc 3 _intc 7
>>> +  _intc 3 _intc 7
>>> +      _intc 3 _intc 7
>>> +  _intc 3
>>> + _intc 7>;
>>> reg = <0x0 0x200 0x0 0xc>;
>>> +   clocks = < PRCI_CLK_COREPLL>;
>>
>> This looks wrong to me. The CLINT timer frequency should come from the
>RTC node.
>>
>> +Pragnesh Patel
>>
>> +Sagar Kadam
>
>On further review, I think you are right that this should be RTCCLK_FREQ.
>
>Perhaps the clocks part should be moved into arch/riscv/dts/hifive-
>unleashed-a00-u-boot.dts and changed to something like
>
>clocks = <>;

I am okay with your suggestion, better to add in 
"hifive-unleashed-a00-u-boot.dtsi".

>
>--Sean

RE: [PATCH v3 1/5] dt-bindings: prci: add indexes for reset signals available in prci

[Pragnesh Patel]

>-Original Message-
>From: Sagar Kadam 
>Sent: 10 July 2020 14:08
>To: u-boot@lists.denx.de
>Cc: r...@andestech.com; Paul Walmsley ( Sifive)
>; pal...@dabbelt.com; anup.pa...@wdc.com;
>atish.pa...@wdc.com; lu...@denx.de; Pragnesh Patel
>; bin.m...@windriver.com;
>ja...@amarulasolutions.com; s...@chromium.org; twoer...@gmail.com;
>abrod...@synopsys.com; eugeniy.palt...@synopsys.com; patr...@blueri.se;
>weijie@mediatek.com; feste...@gmail.com; Sagar Kadam
>
>Subject: [PATCH v3 1/5] dt-bindings: prci: add indexes for reset signals
>available in prci
>
>Add bit indexes for reset signals within the PRCI module on FU540-C000 SoC.
>The DDR and ethernet sub-system's have reset signals indicated by these
>reset indexes.
>
>Signed-off-by: Sagar Shrikant Kadam 
>---
> include/dt-bindings/reset/sifive-fu540-prci.h | 19 +++
> 1 file changed, 19 insertions(+)
> create mode 100644 include/dt-bindings/reset/sifive-fu540-prci.h
>

Reviewed-by: Pragnesh Patel 

RE: [PATCH v3 2/5] fu540: prci: use common reset indexes defined in binding header

[Pragnesh Patel]

>-Original Message-
>From: Sagar Kadam 
>Sent: 10 July 2020 14:08
>To: u-boot@lists.denx.de
>Cc: r...@andestech.com; Paul Walmsley ( Sifive)
>; pal...@dabbelt.com; anup.pa...@wdc.com;
>atish.pa...@wdc.com; lu...@denx.de; Pragnesh Patel
>; bin.m...@windriver.com;
>ja...@amarulasolutions.com; s...@chromium.org; twoer...@gmail.com;
>abrod...@synopsys.com; eugeniy.palt...@synopsys.com; patr...@blueri.se;
>weijie@mediatek.com; feste...@gmail.com; Sagar Kadam
>
>Subject: [PATCH v3 2/5] fu540: prci: use common reset indexes defined in
>binding header
>
>Indexes of reset signals available in PRCI driver are also defined in 
>include/dt-
>bindings/reset/sifive-fu540-prci.h.
>So use those instead of defining new ones again within the fu540-prci driver.
>
>Signed-off-by: Sagar Shrikant Kadam 
>---
> drivers/clk/sifive/fu540-prci.c | 17 +++--
> 1 file changed, 7 insertions(+), 10 deletions(-)
>

Reviewed-by: Pragnesh Patel 

RE: [PATCH v3 3/5] fu540: dtsi: add reset producer and consumer entries

[Pragnesh Patel]

>-Original Message-
>From: Sagar Kadam 
>Sent: 10 July 2020 14:08
>To: u-boot@lists.denx.de
>Cc: r...@andestech.com; Paul Walmsley ( Sifive)
>; pal...@dabbelt.com; anup.pa...@wdc.com;
>atish.pa...@wdc.com; lu...@denx.de; Pragnesh Patel
>; bin.m...@windriver.com;
>ja...@amarulasolutions.com; s...@chromium.org; twoer...@gmail.com;
>abrod...@synopsys.com; eugeniy.palt...@synopsys.com; patr...@blueri.se;
>weijie@mediatek.com; feste...@gmail.com; Sagar Kadam
>
>Subject: [PATCH v3 3/5] fu540: dtsi: add reset producer and consumer entries
>
>The resets to DDR and ethernet sub-system are connected to PRCI device
>reset control register, these reset signals are active low and are held low at
>power-up. Add these reset producer and consumer details needed by the
>reset driver.
>
>Signed-off-by: Sagar Shrikant Kadam 
>---
> arch/riscv/dts/fu540-c000-u-boot.dtsi | 12 ++++
> 1 file changed, 12 insertions(+)
>

Reviewed-by: Pragnesh Patel