[U-Boot] [PATCH] MIPS: Kconfig: use decimal number for all i/d-cache line-size.

[Purna Chandra Mandal]

Instead of using mix of hex and decimal numbering for i/d-cache size
and line-size use unified decimal integer only.

Cc: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
Cc: Paul Burton <paul.bur...@imgtec.com>
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

 arch/mips/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 5c30ae9..21066f0 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -253,7 +253,7 @@ config SYS_DCACHE_SIZE
  The total size of the L1 Dcache, if known at compile time.
 
 config SYS_DCACHE_LINE_SIZE
-   hex
+   int
default 0
help
  The size of L1 Dcache lines, if known at compile time.
-- 
1.8.3.1

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[U-Boot] [PATCH] spi: pic32_spi: add SPI master driver for PIC32 SoC.

[Purna Chandra Mandal]

This driver implements SPI protocol in master mode to communicate
with the SPI device connected on SPI bus. It handles /CS explicitly
by controlling respective pin as gpio ('cs-gpios' property in dt node)
and uses PIO mode for SPI transaction. It is configurable based
on driver-model only.

Cc: Jagan Teki <jt...@openedev.com>
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

 drivers/spi/Kconfig |   8 +
 drivers/spi/Makefile|   1 +
 drivers/spi/pic32_spi.c | 448 
 3 files changed, 457 insertions(+)
 create mode 100644 drivers/spi/pic32_spi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index b7fd8e5..aca385d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -75,6 +75,14 @@ config ICH_SPI
  access the SPI NOR flash on platforms embedding this Intel
  ICH IP core.
 
+config PIC32_SPI
+   bool "Microchip PIC32 SPI driver"
+   depends on MACH_PIC32
+   help
+ Enable the Microchip PIC32 SPI driver. This driver can be used
+ to access the SPI NOR flash, MMC-over-SPI on platforms based on
+ Microchip PIC32 family devices.
+
 config ROCKCHIP_SPI
bool "Rockchip SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 7fb2926..b1d9e20 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
 obj-$(CONFIG_MXC_SPI) += mxc_spi.o
 obj-$(CONFIG_MXS_SPI) += mxs_spi.o
 obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
 obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
 obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
 obj-$(CONFIG_SH_SPI) += sh_spi.o
diff --git a/drivers/spi/pic32_spi.c b/drivers/spi/pic32_spi.c
new file mode 100644
index 000..25ca1f3
--- /dev/null
+++ b/drivers/spi/pic32_spi.c
@@ -0,0 +1,448 @@
+/*
+ * Microchip PIC32 SPI controller driver.
+ *
+ * Copyright (c) 2015, Microchip Technology Inc.
+ *  Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* PIC32 SPI controller registers */
+struct pic32_reg_spi {
+   struct pic32_reg_atomic ctrl;
+   struct pic32_reg_atomic status;
+   struct pic32_reg_atomic buf;
+   struct pic32_reg_atomic baud;
+   struct pic32_reg_atomic ctrl2;
+};
+
+/* Bit fields in SPI Control Register */
+#define PIC32_SPI_CTRL_MSTEN   BIT(5) /* Enable SPI Master */
+#define PIC32_SPI_CTRL_CKP BIT(6) /* active low */
+#define PIC32_SPI_CTRL_CKE BIT(8) /* Tx on falling edge */
+#define PIC32_SPI_CTRL_SMP BIT(9) /* Rx at middle or end of tx */
+#define PIC32_SPI_CTRL_BPW_MASK0x03   /* Bits per word */
+#define  PIC32_SPI_CTRL_BPW_8  0x0
+#define  PIC32_SPI_CTRL_BPW_16 0x1
+#define  PIC32_SPI_CTRL_BPW_32 0x2
+#define PIC32_SPI_CTRL_BPW_SHIFT   10
+#define PIC32_SPI_CTRL_ON  BIT(15) /* Macro enable */
+#define PIC32_SPI_CTRL_ENHBUF  BIT(16) /* Enable enhanced buffering */
+#define PIC32_SPI_CTRL_MCLKSEL BIT(23) /* Select SPI Clock src */
+#define PIC32_SPI_CTRL_MSSEN   BIT(28) /* SPI macro will drive SS */
+#define PIC32_SPI_CTRL_FRMEN   BIT(31) /* Enable framing mode */
+
+/* Bit fields in SPI Status Register */
+#define PIC32_SPI_STAT_RX_OV   BIT(6) /* err, s/w needs to clear */
+#define PIC32_SPI_STAT_TF_LVL_MASK 0x1f
+#define PIC32_SPI_STAT_TF_LVL_SHIFT16
+#define PIC32_SPI_STAT_RF_LVL_MASK 0x1f
+#define PIC32_SPI_STAT_RF_LVL_SHIFT24
+
+/* Bit fields in SPI Baud Register */
+#define PIC32_SPI_BAUD_MASK0x1ff
+
+struct pic32_spi_priv {
+   struct pic32_reg_spi*regs;
+   u32 fifo_depth; /* FIFO depth in bytes */
+   u32 fifo_n_word; /* FIFO depth in words */
+   struct gpio_desccs_gpio;
+
+   /* Current SPI slave specific */
+   ulong   clk_rate;
+   u32 speed_hz; /* spi-clk rate */
+   int mode;
+
+   /* Current message/transfer state */
+   const void  *tx;
+   const void  *tx_end;
+   const void  *rx;
+   const void  *rx_end;
+   u32 len;
+
+   /* SPI FiFo accessor */
+   void (*rx_fifo)(struct pic32_spi_priv *);
+   void (*tx_fifo)(struct pic32_spi_priv *);
+};
+
+static inline void pic32_spi_enable(struct pic32_spi_priv *priv)
+{
+   writel(PIC32_SPI_CTRL_ON, >regs->ctrl.set);
+}
+
+static inline void pic32_spi_disable(struct pic32_spi_priv *priv)
+{
+   writel(PIC32_SPI_CTRL_ON, >regs->ctrl.clr);
+}
+
+static inline u32 pic32_spi_rx_fifo_level(struct pic32_spi_priv *priv)
+{
+   u32 s

[U-Boot] [PATCH] MIPS: bootm: Add fixup of '/memory' node.

[Purna Chandra Mandal]

MIPS arch do not update 'reg' property of /memory node.
As a result Linux bootup will not work unless board.dts
file contains right /memory offset-size information or
board implements required memory fixup.
Fixing by renaming (unused) _arch_fixup_memory_node_ to 
_arch_fixup_fdt_ in arch/mips/lib/bootm.c inline with ARM arch.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Cc: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
---

 arch/mips/lib/bootm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index eed159c..aa0475a 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -252,10 +253,10 @@ static int boot_reloc_fdt(bootm_headers_t *images)
 #endif
 }
 
-int arch_fixup_memory_node(void *blob)
+int arch_fixup_fdt(void *blob)
 {
 #if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT)
-   u64 mem_start = 0;
+   u64 mem_start = virt_to_phys((void *)gd->bd->bi_memstart);
u64 mem_size = gd->ram_size;
 
return fdt_fixup_memory_banks(blob, _start, _size, 1);
-- 
1.8.3.1

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Re: [U-Boot] [PATCH] mips: fix DTC unit warnings

[Purna Chandra Mandal]

On 04/15/2016 08:53 PM, Andreas Färber wrote:

> Am 15.04.2016 um 12:59 schrieb Heiko Schocher:
>> Fix following warnings for all mips based boards:
>>  mips:  +   pic32mzdask
>> +Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, 
>> but no unit name
>> +Warning (unit_address_vs_reg): Node /cpus/cpu@0 has a unit name, but no reg 
>> property
>>
>> Signed-off-by: Heiko Schocher 
>> ---
>> This warnings pop up with the DTC compiler:
>> $ /tmp/dtc/dtc -v
>> Version: DTC 1.4.1-gbeef80b8
>>
>> This fixes the compile warnings for:
>> https://travis-ci.org/hsdenx/u-boot/jobs/123254184
>>
>> see:
>> https://travis-ci.org/hsdenx/u-boot/jobs/123281033
>>
>>
>>  arch/mips/dts/pic32mzda.dtsi | 2 +-
>>  arch/mips/dts/skeleton.dtsi  | 2 +-
>>  2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
>> index 8a554f9..791c364 100644
>> --- a/arch/mips/dts/pic32mzda.dtsi
>> +++ b/arch/mips/dts/pic32mzda.dtsi
>> @@ -27,7 +27,7 @@
>>  };
>>  
>>  cpus {
>> -cpu@0 {
>> +cpu {
>>  compatible = "mips,mips14kc";
>>  };
>>  };
>> diff --git a/arch/mips/dts/skeleton.dtsi b/arch/mips/dts/skeleton.dtsi
>> index 24ee6c3..643996c 100644
>> --- a/arch/mips/dts/skeleton.dtsi
>> +++ b/arch/mips/dts/skeleton.dtsi
>> @@ -16,7 +16,7 @@
>>  aliases {
>>  };
>>  
>> -memory {
>> +memory@0 {
> I have just been told on linux-rockchip mailing list that such a change
> should not be done as /memory is being special-cased in dtc warnings for
> the benefit of U-Boot. Supposedly U-Boot cannot handle updating memory
> size on /memory@0.
>
> If that is untrue, please someone object on the Linux mailing lists.

Interestingly MIPS arch does not update size on /memory node during bootm.
Either we can fix that in arch/mips/ or all boards have to implement board
specific ft_board_setup() to address this. Shortly you'll see a patch.

In PIC32 boards(may be in some other boards as well) embedded dts is used
for U-Boot and for Linux full dts is downloaded from external media. And
external version has updated memory reg=<> property so problem due to
'/memory@0' fix is not seen.

>
> Regards,
> Andreas
>
>>  device_type = "memory";
>>  reg = <0 0>;
>>  };
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Re: [U-Boot] [PATCH] mips: fix DTC unit warnings

[Purna Chandra Mandal]

On 04/15/2016 04:29 PM, Heiko Schocher wrote:

> Fix following warnings for all mips based boards:
>  mips:  +   pic32mzdask
> +Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, 
> but no unit name
> +Warning (unit_address_vs_reg): Node /cpus/cpu@0 has a unit name, but no reg 
> property
>
> Signed-off-by: Heiko Schocher <h...@denx.de>
> ---
> This warnings pop up with the DTC compiler:
> $ /tmp/dtc/dtc -v
> Version: DTC 1.4.1-gbeef80b8
>
> This fixes the compile warnings for:
> https://travis-ci.org/hsdenx/u-boot/jobs/123254184
>
> see:
> https://travis-ci.org/hsdenx/u-boot/jobs/123281033
>
>
>  arch/mips/dts/pic32mzda.dtsi | 2 +-
>  arch/mips/dts/skeleton.dtsi  | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
> index 8a554f9..791c364 100644
> --- a/arch/mips/dts/pic32mzda.dtsi
> +++ b/arch/mips/dts/pic32mzda.dtsi
> @@ -27,7 +27,7 @@
>   };
>  
>   cpus {
> - cpu@0 {
> + cpu {
>   compatible = "mips,mips14kc";
>   };
>   };
> diff --git a/arch/mips/dts/skeleton.dtsi b/arch/mips/dts/skeleton.dtsi
> index 24ee6c3..643996c 100644
> --- a/arch/mips/dts/skeleton.dtsi
> +++ b/arch/mips/dts/skeleton.dtsi
> @@ -16,7 +16,7 @@
>   aliases {
>   };
>  
> - memory {
> + memory@0 {
>   device_type = "memory";
>   reg = <0 0>;
>   };

Reviewed-by: Purna Chandra Mandal <purna.man...@microchip.com>

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Re: [U-Boot] [PATCH V3 1/6] dm: gpio: add a default gpio xlate routine

[Purna Chandra Mandal]

On 04/11/2016 11:01 PM, Eric Nelson wrote:

> Many drivers use a common form of offset + flags for device
> tree nodes. e.g.:
>   < 2 GPIO_ACTIVE_LOW>
>
> This patch adds a common implementation of this type of parsing
> and calls it when a gpio driver doesn't supply its' own xlate
> routine.
>
> This will allow removal of the driver-specific versions in a
> handful of drivers and simplify the addition of new drivers.
>
> Signed-off-by: Eric Nelson <e...@nelint.com>
> Acked-by: Stephen Warren <swar...@wwwdotorg.org>

Reviewed-by: Purna Chandra Mandal <purna.man...@microchip.com>

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Re: [U-Boot] [PATCH V2 4/6] gpio: pic32: remove gpio_xlate routine

[Purna Chandra Mandal]

On 04/11/2016 10:30 PM, Eric Nelson wrote:

> With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
> the pic32 gpio driver doesn't need a custom xlate routine.
>
> Signed-off-by: Eric Nelson <e...@nelint.com>
> Acked-by: Simon Glass <s...@chromium.org>

Reviewed-by: Purna Chandra Mandal <purna.man...@microchip.com>

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Re: [U-Boot] [PATCH v5 1/4] arm: add missing writes[bwql], reads[bwql].

[Purna Chandra Mandal]

On 03/21/2016 05:09 PM, Marek Vasut wrote:
> On 03/21/2016 12:19 PM, Purna Chandra Mandal wrote:
>> On 03/21/2016 04:49 PM, Marek Vasut wrote:
>>
>>> On 03/21/2016 08:35 AM, Purna Chandra Mandal wrote:
>>>> ARM defines __raw_writes[bwql], __raw_reads[bwql] in arch io.h
>>>> but not the writes[bwql], reads[bwql] needed by some drivers.
>>>>
>>>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>> Applied all four to u-boot-usb/master, thanks!
>>>
>> Thanks. :)
>>
> Thank you for persevering ;-)
>
> btw. have you worked with Olimex PIC32-EMZ64 (PIC32MZ2048EFH064) ?
> Can it be used for testing U-Boot on PIC32 and this musb stuff ?

Not exactly 'PIC32MZ2048EFH064' but on some other board having
PIC32MZ2048EFM144 (with additional SRAM connected on EBI).
Anyway MUSB stuff is same. And pin-mapping will be different
so need to update pinctrl. Otherwise it should be fine for U-Boot
testing.


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Re: [U-Boot] [PATCH v5 1/4] arm: add missing writes[bwql], reads[bwql].

[Purna Chandra Mandal]

On 03/21/2016 04:49 PM, Marek Vasut wrote:

> On 03/21/2016 08:35 AM, Purna Chandra Mandal wrote:
>> ARM defines __raw_writes[bwql], __raw_reads[bwql] in arch io.h
>> but not the writes[bwql], reads[bwql] needed by some drivers.
>>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
> Applied all four to u-boot-usb/master, thanks!
>
Thanks. :)

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[U-Boot] [PATCH v5 4/4] board: pic32mzda: enable USB-host, USB-storage support.

[Purna Chandra Mandal]

Enable MUSB host and USB storage support for Microchip
PIC32MZ[DA] Starter Kit.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---

Changes in v5: None
Changes in v4:
- dts: add USB clock to musb node
- add missing CONFIG_PIC32_USB in defconfig

Changes in v3:
- add arch specific reads{bwlq}, writes{bwlq} in respective arch io.h
- remove reads{bwlq}, writes{bwlq} in musb-new driver

Changes in v2:
- compilation fix in drivers/usb/musb-new/linux-compat.h seperated
- compilation fix in drivers/gadget/f_mass_storage.c seperated

 arch/mips/dts/pic32mzda.dtsi   | 12 
 arch/mips/dts/pic32mzda_sk.dts |  4 
 configs/pic32mzdask_defconfig  |  6 ++
 include/configs/pic32mzdask.h  |  7 +++
 4 files changed, 29 insertions(+)

diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
index 7d180d9..8a554f9 100644
--- a/arch/mips/dts/pic32mzda.dtsi
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -171,4 +171,16 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+   usb: musb@1f8e3000 {
+   compatible = "microchip,pic32mzda-usb";
+   reg = <0x1f8e3000 0x1000>,
+ <0x1f884000 0x1000>;
+   reg-names = "mc", "control";
+   interrupts = <132 IRQ_TYPE_EDGE_RISING>,
+<133 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < PB5CLK>;
+   clock-names = "usb_clk";
+   status = "disabled";
+   };
 };
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
index e5ce0bd..0a7847e 100644
--- a/arch/mips/dts/pic32mzda_sk.dts
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -52,4 +52,8 @@
ethernet_phy: lan8740_phy@0 {
reg = <0>;
};
+};
+
+ {
+   status = "okay";
 };
\ No newline at end of file
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 4017983..eba6cd5 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -14,6 +14,7 @@ CONFIG_LOOPW=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_RARP=y
@@ -30,5 +31,10 @@ CONFIG_PIC32_ETH=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_PIC32=y
+CONFIG_USB_STORAGE=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 3ea1194..78faaec 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -105,6 +105,12 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_MMC
 
+/*--
+ * USB Configuration
+ */
+#define CONFIG_USB_MUSB_PIO_ONLY
+#define CONFIG_SYS_CACHELINE_SIZE  16
+
 /*---
  * File System Configuration
  */
@@ -153,6 +159,7 @@
 
 #define BOOT_TARGET_DEVICES(func)  \
func(MMC, mmc, 0)   \
+   func(USB, usb, 0)   \
func(DHCP, dhcp, na)
 
 #include 
-- 
1.8.3.1

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[U-Boot] [PATCH v5 3/4] drivers: musb-new: Add USB DRC driver for Microchip PIC32 OTG controller.

[Purna Chandra Mandal]

This driver adds support of PIC32 MUSB OTG controller as dual role device.
It implements platform specific glue to reuse musb core.

Signed-off-by: Cristian Birsan <cristian.bir...@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

Changes in v5:
- drop OR'ing irqreturn_t in pic32_interrupt().

Changes in v4:
- add support to handle multiple MUSB controllers.
- remove unaligned buffer handling in musb_read_fifo
- update comment and error prints

Changes in v3: None
Changes in v2: None

 drivers/usb/musb-new/Kconfig |   7 +
 drivers/usb/musb-new/Makefile|   1 +
 drivers/usb/musb-new/musb_core.c |   2 +-
 drivers/usb/musb-new/pic32.c | 288 +++
 4 files changed, 297 insertions(+), 1 deletion(-)
 create mode 100644 drivers/usb/musb-new/pic32.c

diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index 6a6cb93..4e8a543 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -15,6 +15,13 @@ config USB_MUSB_GADGET
 
 if USB_MUSB_HOST || USB_MUSB_GADGET
 
+config USB_MUSB_PIC32
+   bool "Enable Microchip PIC32 DRC USB controller"
+   depends on DM_USB && MACH_PIC32
+   help
+ Say y to enable PIC32 USB DRC controller support
+ if it is available on your Microchip PIC32 platform.
+
 config USB_MUSB_SUNXI
bool "Enable sunxi OTG / DRC USB controller"
depends on ARCH_SUNXI
diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile
index 072d516..df1c3c8 100644
--- a/drivers/usb/musb-new/Makefile
+++ b/drivers/usb/musb-new/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_USB_MUSB_HOST) += musb_host.o musb_core.o 
musb_uboot.o
 obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o
 obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o
 obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
+obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o
 obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
 
 ccflags-y := $(call cc-option,-Wno-unused-variable) \
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index a6d6af6..dd0443c 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -259,7 +259,7 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, 
const u8 *src)
}
 }
 
-#if !defined(CONFIG_USB_MUSB_AM35X)
+#if !defined(CONFIG_USB_MUSB_AM35X) && !defined(CONFIG_USB_MUSB_PIC32)
 /*
  * Unload an endpoint's FIFO
  */
diff --git a/drivers/usb/musb-new/pic32.c b/drivers/usb/musb-new/pic32.c
new file mode 100644
index 000..c888c64
--- /dev/null
+++ b/drivers/usb/musb-new/pic32.c
@@ -0,0 +1,288 @@
+/*
+ * Microchip PIC32 MUSB "glue layer"
+ *
+ * Copyright (C) 2015, Microchip Technology Inc.
+ *  Cristian Birsan <cristian.bir...@microchip.com>
+ *  Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Based on the dsps "glue layer" code.
+ */
+
+#include 
+#include 
+#include "linux-compat.h"
+#include "musb_core.h"
+#include "musb_uboot.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PIC32_TX_EP_MASK   0x0f/* EP0 + 7 Tx EPs */
+#define PIC32_RX_EP_MASK   0x0e/* 7 Rx EPs */
+
+#define MUSB_SOFTRST   0x7f
+#define  MUSB_SOFTRST_NRST BIT(0)
+#define  MUSB_SOFTRST_NRSTXBIT(1)
+
+#define USBCRCON   0
+#define  USBCRCON_USBWKUPENBIT(0)  /* Enable Wakeup Interrupt */
+#define  USBCRCON_USBRIE   BIT(1)  /* Enable Remote resume Interrupt */
+#define  USBCRCON_USBIEBIT(2)  /* Enable USB General interrupt 
*/
+#define  USBCRCON_SENDMONENBIT(3)  /* Enable Session End VBUS monitoring */
+#define  USBCRCON_BSVALMONEN   BIT(4)  /* Enable B-Device VBUS monitoring */
+#define  USBCRCON_ASVALMONEN   BIT(5)  /* Enable A-Device VBUS monitoring */
+#define  USBCRCON_VBUSMONENBIT(6)  /* Enable VBUS monitoring */
+#define  USBCRCON_PHYIDEN  BIT(7)  /* PHY ID monitoring enable */
+#define  USBCRCON_USBIDVAL BIT(8)  /* USB ID value */
+#define  USBCRCON_USBIDOVENBIT(9)  /* USB ID override enable */
+#define  USBCRCON_USBWKBIT(24) /* USB Wakeup Status */
+#define  USBCRCON_USBRFBIT(25) /* USB Resume Status */
+#define  USBCRCON_USBIFBIT(26) /* USB General Interrupt Status 
*/
+
+/* PIC32 controller data */
+struct pic32_musb_data {
+   struct musb_host_data mdata;
+   struct device dev;
+   void __iomem *musb_glue;
+};
+
+#define to_pic32_musb_data(d)  \
+   container_of(d, struct pic32_musb_data, dev)
+
+static void pic32_musb_disable(struct musb *musb)
+{
+   /* no way to shut the controller */
+}
+
+static int pic32_musb_enable(struct musb *musb)
+{
+   /* soft reset by NRSTx */
+   musb_writeb(musb->mregs, MUSB_SOFTRST, MUSB_SOFTRST_NRSTX);
+   /* set mode */
+   musb_platform_set_mode(musb, musb->board_mode);

[U-Boot] [PATCH v5 2/4] drivers: remove writes{b, w, l, q} and reads{b, w, l, q}.

[Purna Chandra Mandal]

Definition of writes{bwlq}, reads{bwlq} are now added into arch specific
asm/io.h. So removing them from driver to fix re-definition error

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/mtd/nand/pxa3xx_nand.c  | 8 
 drivers/usb/musb-new/linux-compat.h | 7 ---
 2 files changed, 15 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 9392742..d529467 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -19,14 +19,6 @@
 
 #include "pxa3xx_nand.h"
 
-/* Some U-Boot compatibility macros */
-#define writesl(a, d, s)   __raw_writesl((unsigned long)a, d, s)
-#define readsl(a, d, s)__raw_readsl((unsigned long)a, d, s)
-#define writesw(a, d, s)   __raw_writesw((unsigned long)a, d, s)
-#define readsw(a, d, s)__raw_readsw((unsigned long)a, d, s)
-#define writesb(a, d, s)   __raw_writesb((unsigned long)a, d, s)
-#define readsb(a, d, s)__raw_readsb((unsigned long)a, d, s)
-
 #define TIMEOUT_DRAIN_FIFO 5   /* in ms */
 #defineCHIP_DELAY_TIMEOUT  200
 #define NAND_STOP_DELAY40
diff --git a/drivers/usb/musb-new/linux-compat.h 
b/drivers/usb/musb-new/linux-compat.h
index 1fc9391..9244977 100644
--- a/drivers/usb/musb-new/linux-compat.h
+++ b/drivers/usb/musb-new/linux-compat.h
@@ -13,13 +13,6 @@
printf(fmt, ##args);\
ret_warn; })
 
-#define writesl(a, d, s) __raw_writesl((unsigned long)a, d, s)
-#define readsl(a, d, s) __raw_readsl((unsigned long)a, d, s)
-#define writesw(a, d, s) __raw_writesw((unsigned long)a, d, s)
-#define readsw(a, d, s) __raw_readsw((unsigned long)a, d, s)
-#define writesb(a, d, s) __raw_writesb((unsigned long)a, d, s)
-#define readsb(a, d, s) __raw_readsb((unsigned long)a, d, s)
-
 #define device_init_wakeup(dev, a) do {} while (0)
 
 #define platform_data device_data
-- 
1.8.3.1

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[U-Boot] [PATCH v5 0/4] This series add MUSB support on PIC32MZDA Starter Kit.

[Purna Chandra Mandal]

It contains fix for core MUSB driver, platform specific
glue for PIC32 and board support.

Changes in v5:
- drop OR'ing irqreturn_t in pic32_interrupt().

Changes in v4:
- add support to handle multiple MUSB controllers.
- remove unaligned buffer handling in musb_read_fifo
- update comment and error prints
- dts: add USB clock to musb node
- add missing CONFIG_PIC32_USB in defconfig

Changes in v3:
- add arch specific reads{bwlq}, writes{bwlq} in respective arch io.h
- remove reads{bwlq}, writes{bwlq} in musb-new driver

Changes in v2:
- compilation fix in drivers/usb/musb-new/linux-compat.h seperated
- compilation fix in drivers/gadget/f_mass_storage.c seperated

Purna Chandra Mandal (4):
  arm: add missing writes[bwql], reads[bwql].
  drivers: remove writes{b,w,l,q} and reads{b,w,l,q}.
  drivers: musb-new: Add USB DRC driver for Microchip PIC32 OTG
controller.
  board: pic32mzda: enable USB-host, USB-storage support.

 arch/arm/include/asm/io.h   |   7 +
 arch/mips/dts/pic32mzda.dtsi|  12 ++
 arch/mips/dts/pic32mzda_sk.dts  |   4 +
 configs/pic32mzdask_defconfig   |   6 +
 drivers/mtd/nand/pxa3xx_nand.c  |   8 -
 drivers/usb/musb-new/Kconfig|   7 +
 drivers/usb/musb-new/Makefile   |   1 +
 drivers/usb/musb-new/linux-compat.h |   7 -
 drivers/usb/musb-new/musb_core.c|   2 +-
 drivers/usb/musb-new/pic32.c| 288 
 include/configs/pic32mzdask.h   |   7 +
 11 files changed, 333 insertions(+), 16 deletions(-)
 create mode 100644 drivers/usb/musb-new/pic32.c

-- 
1.8.3.1

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[U-Boot] [PATCH v5 1/4] arm: add missing writes[bwql], reads[bwql].

[Purna Chandra Mandal]

ARM defines __raw_writes[bwql], __raw_reads[bwql] in arch io.h
but not the writes[bwql], reads[bwql] needed by some drivers.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/include/asm/io.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 75773bd..9d185a6 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -284,6 +284,13 @@ static inline void __raw_readsl(unsigned long addr, void 
*data, int longlen)
 #define insw_p(port,to,len)insw(port,to,len)
 #define insl_p(port,to,len)insl(port,to,len)
 
+#define writesl(a, d, s)   __raw_writesl((unsigned long)a, d, s)
+#define readsl(a, d, s)__raw_readsl((unsigned long)a, d, s)
+#define writesw(a, d, s)   __raw_writesw((unsigned long)a, d, s)
+#define readsw(a, d, s)__raw_readsw((unsigned long)a, d, s)
+#define writesb(a, d, s)   __raw_writesb((unsigned long)a, d, s)
+#define readsb(a, d, s)__raw_readsb((unsigned long)a, d, s)
+
 /*
  * ioremap and friends.
  *
-- 
1.8.3.1

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Re: [U-Boot] [PATCH v3 3/4] drivers: musb-new: Add USB DRC driver for Microchip PIC32 OTG controller.

[Purna Chandra Mandal]

On 03/16/2016 09:18 PM, Marek Vasut wrote:

> On 03/16/2016 10:58 AM, Purna Chandra Mandal wrote:
>> On 03/15/2016 11:49 PM, Marek Vasut wrote:
>>
>>> On 03/15/2016 01:44 PM, Purna Chandra Mandal wrote:
>>>> This driver adds support of PIC32 MUSB OTG controller as dual role device.
>>>> It implements platform specific glue to reuse musb core.
>>>>
>>>> Signed-off-by: Cristian Birsan <cristian.bir...@microchip.com>
>>>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>> [...]
>>>
>>>> diff --git a/drivers/usb/musb-new/pic32.c b/drivers/usb/musb-new/pic32.c
>>>> new file mode 100644
>>>> index 000..980a971
>>>> --- /dev/null
>>>> +++ b/drivers/usb/musb-new/pic32.c
>>>> @@ -0,0 +1,294 @@
>>>> +/*
>>>> + * Microchip PIC32 MUSB "glue layer"
>>>> + *
>>>> + * Copyright (C) 2015, Microchip Technology Inc.
>>>> + *  Cristian Birsan <cristian.bir...@microchip.com>
>>>> + *  Purna Chandra Mandal <purna.man...@microchip.com>
>>>> + *
>>>> + * SPDX-License-Identifier: GPL-2.0+
>>>> + *
>>>> + * Based on the dsps "glue layer" code.
>>>> + */
>>>> +
>>>> +#include 
>>>> +#include 
>>>> +#include "linux-compat.h"
>>>> +#include "musb_core.h"
>>>> +#include "musb_uboot.h"
>>>> +
>>>> +DECLARE_GLOBAL_DATA_PTR;
>>>> +
>>>> +#define PIC32_TX_EP_MASK  0x0f/* EP0 + 7 Tx EPs */
>>>> +#define PIC32_RX_EP_MASK  0x0e/* 7 Rx EPs */
>>>> +
>>>> +#define MUSB_SOFTRST  0x7f
>>>> +#define  MUSB_SOFTRST_NRSTBIT(0)
>>>> +#define  MUSB_SOFTRST_NRSTX   BIT(1)
>>>> +
>>>> +#define USBCRCON  0
>>>> +#define  USBCRCON_USBWKUPEN   BIT(0)  /* Enable Wakeup Interrupt */
>>>> +#define  USBCRCON_USBRIE  BIT(1)  /* Enable Remote resume Interrupt */
>>>> +#define  USBCRCON_USBIE   BIT(2)  /* Enable USB General interrupt 
>>>> */
>>>> +#define  USBCRCON_SENDMONEN   BIT(3)  /* Enable Session End VBUS 
>>>> monitoring */
>>>> +#define  USBCRCON_BSVALMONEN  BIT(4)  /* Enable B-Device VBUS 
>>>> monitoring */
>>>> +#define  USBCRCON_ASVALMONEN  BIT(5)  /* Enable A-Device VBUS 
>>>> monitoring */
>>>> +#define  USBCRCON_VBUSMONEN   BIT(6)  /* Enable VBUS monitoring */
>>>> +#define  USBCRCON_PHYIDEN BIT(7)  /* PHY ID monitoring enable */
>>>> +#define  USBCRCON_USBIDVALBIT(8)  /* USB ID value */
>>>> +#define  USBCRCON_USBIDOVEN   BIT(9)  /* USB ID override enable */
>>>> +#define  USBCRCON_USBWK   BIT(24) /* USB Wakeup Status */
>>>> +#define  USBCRCON_USBRF   BIT(25) /* USB Resume Status */
>>>> +#define  USBCRCON_USBIF   BIT(26) /* USB General Interrupt Status 
>>>> */
>>>> +
>>>> +static void __iomem *musb_glue;
>>> What would happen once you make a chip with two MUSB controllers ?
>> Currently PIC32 has only one MUSB controller and only one glue reg-space.
>> Don't know how the reg-map will be in future when PIC32 will have multiple
>> MUSB controllers. Assuming that glue address map will be separate for
>> each controller we can add logic to support multiple MUSB controller.
>>
>> IMO, better if we don't assume something of the future and bloat logic.
> If you switch this to driver model, you will need to weed out all the
> static global variables anyway. Better do it now.

Thanks. Will do.

>>>> +/* pic32_musb_disable - disable HDRC */
>>>> +static void pic32_musb_disable(struct musb *musb)
>>>> +{
>>> Is there no way to shut down the MUSB on the PIC32 ?
>> There is no way to disable MUSB.
> Yet another broken chip design. Can't you put the controller into reset
> and gate the clock for it ?

USB clock can't be gated! USB controller clock is derived from peripheral bus
clock(PBCLK5) which is shared with other modules and USB Phy clock derived from
UPLL can;t be gated at all.

>>>> +}
>>>> +
>>>> +/* pic32_musb_enable - enable HDRC */
>>>> +static int pic32_musb_enable(struct musb *musb)
>>>> +{
>>>> +  /* soft reset by NRSTx */
>>>> +  musb_writeb(musb->mregs, MUSB_SOFTRST, MUSB_SOFTRST_NRSTX);
>>

[U-Boot] [PATCH v3 2/2] drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.

[Purna Chandra Mandal]

PIC32 internal flash devices are parallel NOR flash divided into
number of banks to allow erase-programming in one while fetch and
execution continues on other. As the flash banks are memory mapped
stored code can be executed directly from flash (XIP), also there
is additional hardware logic to prefetch and cache contents to
improve execution performance. These flash can also be used to
store user data (like environment).
Flash erase and programming are handled by on-chip NVM controller.

Driver implemented driver model but MTD is not really support.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

Changes in v3:
- add driver model support but MTD is not implemented

Changes in v2:
- kconfig: add CONFIG_FLASH_PIC32 dependent on MACH_PIC32
- fix single/multi-line comment style
- simplify byte-stream-to-word in little-endian format
- replace virt_to_phys() with CPHYSADDR()
- separate flash ID definition in different patch

 drivers/mtd/Kconfig   |   7 +
 drivers/mtd/Makefile  |   1 +
 drivers/mtd/pic32_flash.c | 444 ++
 3 files changed, 452 insertions(+)
 create mode 100644 drivers/mtd/pic32_flash.c

diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index c58841e..390e9e4 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -28,6 +28,13 @@ config ALTERA_QSPI
  NOR flash to parallel flash interface. Please find details on the
  "Embedded Peripherals IP User Guide" of Altera.
 
+config FLASH_PIC32
+   bool "Microchip PIC32 Flash driver"
+   depends on MACH_PIC32 && MTD
+   help
+ This enables access to Microchip PIC32 internal non-CFI flash
+ chips through PIC32 Non-Volatile-Memory Controller.
+
 endmenu
 
 source "drivers/mtd/nand/Kconfig"
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 7f018a4..9380085 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -19,4 +19,5 @@ obj-$(CONFIG_HAS_DATAFLASH) += dataflash.o
 obj-$(CONFIG_FTSMC020) += ftsmc020.o
 obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
 obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o
+obj-$(CONFIG_FLASH_PIC32) += pic32_flash.o
 obj-$(CONFIG_ST_SMI) += st_smi.o
diff --git a/drivers/mtd/pic32_flash.c b/drivers/mtd/pic32_flash.c
new file mode 100644
index 000..9166fcd
--- /dev/null
+++ b/drivers/mtd/pic32_flash.c
@@ -0,0 +1,444 @@
+/*
+ * Copyright (C) 2015
+ * Cristian Birsan <cristian.bir...@microchip.com>
+ * Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* NVM Controller registers */
+struct pic32_reg_nvm {
+   struct pic32_reg_atomic ctrl;
+   struct pic32_reg_atomic key;
+   struct pic32_reg_atomic addr;
+   struct pic32_reg_atomic data;
+};
+
+/* NVM operations */
+#define NVMOP_NOP  0
+#define NVMOP_WORD_WRITE   1
+#define NVMOP_PAGE_ERASE   4
+
+/* NVM control bits */
+#define NVM_WR BIT(15)
+#define NVM_WREN   BIT(14)
+#define NVM_WRERR  BIT(13)
+#define NVM_LVDERR BIT(12)
+
+/* NVM programming unlock register */
+#define LOCK_KEY   0x0
+#define UNLOCK_KEY10xaa996655
+#define UNLOCK_KEY20x556699aa
+
+/*
+ * PIC32 flash banks consist of number of pages, each page
+ * into number of rows and rows into number of words.
+ * Here we will maintain page information instead of sector.
+ */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+static struct pic32_reg_nvm *nvm_regs_p;
+
+static inline void flash_initiate_operation(u32 nvmop)
+{
+   /* set operation */
+   writel(nvmop, _regs_p->ctrl.raw);
+
+   /* enable flash write */
+   writel(NVM_WREN, _regs_p->ctrl.set);
+
+   /* unlock sequence */
+   writel(LOCK_KEY, _regs_p->key.raw);
+   writel(UNLOCK_KEY1, _regs_p->key.raw);
+   writel(UNLOCK_KEY2, _regs_p->key.raw);
+
+   /* initiate operation */
+   writel(NVM_WR, _regs_p->ctrl.set);
+}
+
+static int flash_wait_till_busy(const char *func, ulong timeout)
+{
+   int ret = wait_for_bit(__func__, _regs_p->ctrl.raw,
+  NVM_WR, false, timeout, false);
+
+   return ret ? ERR_TIMOUT : ERR_OK;
+}
+
+static inline int flash_complete_operation(void)
+{
+   u32 tmp;
+
+   tmp = readl(_regs_p->ctrl.raw);
+   if (tmp & NVM_WRERR) {
+   printf("Error in Block Erase - Lock Bit may be set!\n");
+   flash_initiate_operation(NVMOP_NOP);
+   return ERR_PROTECTED;
+   }
+
+   if (tmp & NVM_LVDERR) {
+   printf("Error in Block Erase - low-vol detected!\n");
+   flash_initiate_operation(NVMOP_NOP);
+   return ERR_NOT_ERASED;
+   }
+
+   /* di

[U-Boot] [PATCH v4 4/4] board: pic32mzda: enable USB-host, USB-storage support.

[Purna Chandra Mandal]

Enable MUSB host and USB storage support for Microchip
PIC32MZ[DA] Starter Kit.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---

Changes in v4:
- dts: add USB clock to musb node
- add missing CONFIG_PIC32_USB in defconfig

Changes in v3:
- add arch specific reads{bwlq}, writes{bwlq} in respective arch io.h
- remove reads{bwlq}, writes{bwlq} in musb-new driver

Changes in v2:
- compilation fix in drivers/usb/musb-new/linux-compat.h seperated
- compilation fix in drivers/gadget/f_mass_storage.c seperated

 arch/mips/dts/pic32mzda.dtsi   | 12 
 arch/mips/dts/pic32mzda_sk.dts |  4 
 configs/pic32mzdask_defconfig  |  7 ++-
 include/configs/pic32mzdask.h  |  7 +++
 4 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
index 5d8bc4b..8865154 100644
--- a/arch/mips/dts/pic32mzda.dtsi
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -179,4 +179,16 @@
  <0x1d10 0x10>;
reg-names = "nvm", "bank1","bank2";
};
+
+   usb: musb@1f8e3000 {
+   compatible = "microchip,pic32mzda-usb";
+   reg = <0x1f8e3000 0x1000>,
+ <0x1f884000 0x1000>;
+   reg-names = "mc", "control";
+   interrupts = <132 IRQ_TYPE_EDGE_RISING>,
+<133 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < PB5CLK>;
+   clock-names = "usb_clk";
+   status = "disabled";
+   };
 };
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
index e5ce0bd..0a7847e 100644
--- a/arch/mips/dts/pic32mzda_sk.dts
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -52,4 +52,8 @@
ethernet_phy: lan8740_phy@0 {
reg = <0>;
};
+};
+
+ {
+   status = "okay";
 };
\ No newline at end of file
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 2f3d463..33af04e 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -12,6 +12,7 @@ CONFIG_SYS_PROMPT="dask # "
 CONFIG_LOOPW=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_RARP=y
@@ -29,6 +30,10 @@ CONFIG_DM_ETH=y
 CONFIG_PIC32_ETH=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_FULL is not set
-CONFIG_SYS_VSNPRINTF=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_PIC32=y
+CONFIG_USB_STORAGE=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 92314e5..9296d26 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -110,6 +110,12 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_MMC
 
+/*--
+ * USB Configuration
+ */
+#define CONFIG_USB_MUSB_PIO_ONLY
+#define CONFIG_SYS_CACHELINE_SIZE  16
+
 /*---
  * File System Configuration
  */
@@ -160,6 +166,7 @@
 
 #define BOOT_TARGET_DEVICES(func)  \
func(MMC, mmc, 0)   \
+   func(USB, usb, 0)   \
func(DHCP, dhcp, na)
 
 #include 
-- 
1.8.3.1

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[U-Boot] [PATCH v4 1/4] arm: add missing writes[bwql], reads[bwql].

[Purna Chandra Mandal]

ARM defines __raw_writes[bwql], __raw_reads[bwql] in arch io.h
but not the writes[bwql], reads[bwql] needed by some drivers.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/include/asm/io.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 75773bd..9d185a6 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -284,6 +284,13 @@ static inline void __raw_readsl(unsigned long addr, void 
*data, int longlen)
 #define insw_p(port,to,len)insw(port,to,len)
 #define insl_p(port,to,len)insl(port,to,len)
 
+#define writesl(a, d, s)   __raw_writesl((unsigned long)a, d, s)
+#define readsl(a, d, s)__raw_readsl((unsigned long)a, d, s)
+#define writesw(a, d, s)   __raw_writesw((unsigned long)a, d, s)
+#define readsw(a, d, s)__raw_readsw((unsigned long)a, d, s)
+#define writesb(a, d, s)   __raw_writesb((unsigned long)a, d, s)
+#define readsb(a, d, s)__raw_readsb((unsigned long)a, d, s)
+
 /*
  * ioremap and friends.
  *
-- 
1.8.3.1

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[U-Boot] [PATCH v4 0/4] This series add MUSB support on PIC32MZDA Starter Kit.

[Purna Chandra Mandal]

It contains fix for MUSB driver compat, PIC32 platform specific glue
and board support.

Changes in v4:
- add support to handle multiple MUSB controllers.
- remove unaligned buffer handling in musb_read_fifo
- update comment and error prints
- dts: add USB clock to musb node
- add missing CONFIG_PIC32_USB in defconfig

Changes in v3:
- add arch specific reads{bwlq}, writes{bwlq} in respective arch io.h
- remove reads{bwlq}, writes{bwlq} in musb-new driver

Changes in v2:
- compilation fix in drivers/usb/musb-new/linux-compat.h seperated
- compilation fix in drivers/gadget/f_mass_storage.c seperated

Purna Chandra Mandal (4):
  arm: add missing writes[bwql], reads[bwql].
  drivers: remove writes{b,w,l,q} and reads{b,w,l,q}.
  drivers: musb-new: Add USB DRC driver for Microchip PIC32 OTG
controller.
  board: pic32mzda: enable USB-host, USB-storage support.

 arch/arm/include/asm/io.h   |   7 +
 arch/mips/dts/pic32mzda.dtsi|  12 ++
 arch/mips/dts/pic32mzda_sk.dts  |   4 +
 configs/pic32mzdask_defconfig   |   7 +-
 drivers/mtd/nand/pxa3xx_nand.c  |   8 -
 drivers/usb/musb-new/Kconfig|   7 +
 drivers/usb/musb-new/Makefile   |   1 +
 drivers/usb/musb-new/linux-compat.h |   7 -
 drivers/usb/musb-new/musb_core.c|   2 +-
 drivers/usb/musb-new/pic32.c| 288 
 include/configs/pic32mzdask.h   |   7 +
 11 files changed, 333 insertions(+), 17 deletions(-)
 create mode 100644 drivers/usb/musb-new/pic32.c

-- 
1.8.3.1

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[U-Boot] [PATCH v4 3/4] drivers: musb-new: Add USB DRC driver for Microchip PIC32 OTG controller.

[Purna Chandra Mandal]

This driver adds support of PIC32 MUSB OTG controller as dual role device.
It implements platform specific glue to reuse musb core.

Signed-off-by: Cristian Birsan <cristian.bir...@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

Changes in v4:
- add support to handle multiple MUSB controllers.
- remove unaligned buffer handling in musb_read_fifo
- update comment and error prints

Changes in v3: None
Changes in v2: None

 drivers/usb/musb-new/Kconfig |   7 +
 drivers/usb/musb-new/Makefile|   1 +
 drivers/usb/musb-new/musb_core.c |   2 +-
 drivers/usb/musb-new/pic32.c | 288 +++
 4 files changed, 297 insertions(+), 1 deletion(-)
 create mode 100644 drivers/usb/musb-new/pic32.c

diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index 6a6cb93..4e8a543 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -15,6 +15,13 @@ config USB_MUSB_GADGET
 
 if USB_MUSB_HOST || USB_MUSB_GADGET
 
+config USB_MUSB_PIC32
+   bool "Enable Microchip PIC32 DRC USB controller"
+   depends on DM_USB && MACH_PIC32
+   help
+ Say y to enable PIC32 USB DRC controller support
+ if it is available on your Microchip PIC32 platform.
+
 config USB_MUSB_SUNXI
bool "Enable sunxi OTG / DRC USB controller"
depends on ARCH_SUNXI
diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile
index 072d516..df1c3c8 100644
--- a/drivers/usb/musb-new/Makefile
+++ b/drivers/usb/musb-new/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_USB_MUSB_HOST) += musb_host.o musb_core.o 
musb_uboot.o
 obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o
 obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o
 obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
+obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o
 obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
 
 ccflags-y := $(call cc-option,-Wno-unused-variable) \
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index a6d6af6..dd0443c 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -259,7 +259,7 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, 
const u8 *src)
}
 }
 
-#if !defined(CONFIG_USB_MUSB_AM35X)
+#if !defined(CONFIG_USB_MUSB_AM35X) && !defined(CONFIG_USB_MUSB_PIC32)
 /*
  * Unload an endpoint's FIFO
  */
diff --git a/drivers/usb/musb-new/pic32.c b/drivers/usb/musb-new/pic32.c
new file mode 100644
index 000..71c9f44
--- /dev/null
+++ b/drivers/usb/musb-new/pic32.c
@@ -0,0 +1,288 @@
+/*
+ * Microchip PIC32 MUSB "glue layer"
+ *
+ * Copyright (C) 2015, Microchip Technology Inc.
+ *  Cristian Birsan <cristian.bir...@microchip.com>
+ *  Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Based on the dsps "glue layer" code.
+ */
+
+#include 
+#include 
+#include "linux-compat.h"
+#include "musb_core.h"
+#include "musb_uboot.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PIC32_TX_EP_MASK   0x0f/* EP0 + 7 Tx EPs */
+#define PIC32_RX_EP_MASK   0x0e/* 7 Rx EPs */
+
+#define MUSB_SOFTRST   0x7f
+#define  MUSB_SOFTRST_NRST BIT(0)
+#define  MUSB_SOFTRST_NRSTXBIT(1)
+
+#define USBCRCON   0
+#define  USBCRCON_USBWKUPENBIT(0)  /* Enable Wakeup Interrupt */
+#define  USBCRCON_USBRIE   BIT(1)  /* Enable Remote resume Interrupt */
+#define  USBCRCON_USBIEBIT(2)  /* Enable USB General interrupt 
*/
+#define  USBCRCON_SENDMONENBIT(3)  /* Enable Session End VBUS monitoring */
+#define  USBCRCON_BSVALMONEN   BIT(4)  /* Enable B-Device VBUS monitoring */
+#define  USBCRCON_ASVALMONEN   BIT(5)  /* Enable A-Device VBUS monitoring */
+#define  USBCRCON_VBUSMONENBIT(6)  /* Enable VBUS monitoring */
+#define  USBCRCON_PHYIDEN  BIT(7)  /* PHY ID monitoring enable */
+#define  USBCRCON_USBIDVAL BIT(8)  /* USB ID value */
+#define  USBCRCON_USBIDOVENBIT(9)  /* USB ID override enable */
+#define  USBCRCON_USBWKBIT(24) /* USB Wakeup Status */
+#define  USBCRCON_USBRFBIT(25) /* USB Resume Status */
+#define  USBCRCON_USBIFBIT(26) /* USB General Interrupt Status 
*/
+
+/* PIC32 controller data */
+struct pic32_musb_data {
+   struct musb_host_data mdata;
+   struct device dev;
+   void __iomem *musb_glue;
+};
+
+#define to_pic32_musb_data(d)  \
+   container_of(d, struct pic32_musb_data, dev)
+
+static void pic32_musb_disable(struct musb *musb)
+{
+   /* no way to shut the controller */
+}
+
+static int pic32_musb_enable(struct musb *musb)
+{
+   /* soft reset by NRSTx */
+   musb_writeb(musb->mregs, MUSB_SOFTRST, MUSB_SOFTRST_NRSTX);
+   /* set mode */
+   musb_platform_set_mode(musb, musb->board_mode);
+
+   return 0;
+}
+
+static irqreturn_t pic32_interrupt(int 

[U-Boot] [PATCH v4 2/4] drivers: remove writes{b, w, l, q} and reads{b, w, l, q}.

[Purna Chandra Mandal]

Definition of writes{bwlq}, reads{bwlq} are now added into arch specific
asm/io.h. So removing them from drivers to fix re-definition error

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/mtd/nand/pxa3xx_nand.c  | 8 
 drivers/usb/musb-new/linux-compat.h | 7 ---
 2 files changed, 15 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 9392742..d529467 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -19,14 +19,6 @@
 
 #include "pxa3xx_nand.h"
 
-/* Some U-Boot compatibility macros */
-#define writesl(a, d, s)   __raw_writesl((unsigned long)a, d, s)
-#define readsl(a, d, s)__raw_readsl((unsigned long)a, d, s)
-#define writesw(a, d, s)   __raw_writesw((unsigned long)a, d, s)
-#define readsw(a, d, s)__raw_readsw((unsigned long)a, d, s)
-#define writesb(a, d, s)   __raw_writesb((unsigned long)a, d, s)
-#define readsb(a, d, s)__raw_readsb((unsigned long)a, d, s)
-
 #define TIMEOUT_DRAIN_FIFO 5   /* in ms */
 #defineCHIP_DELAY_TIMEOUT  200
 #define NAND_STOP_DELAY40
diff --git a/drivers/usb/musb-new/linux-compat.h 
b/drivers/usb/musb-new/linux-compat.h
index 46f83d9..526f4f2 100644
--- a/drivers/usb/musb-new/linux-compat.h
+++ b/drivers/usb/musb-new/linux-compat.h
@@ -13,13 +13,6 @@
printf(fmt, ##args);\
ret_warn; })
 
-#define writesl(a, d, s) __raw_writesl((unsigned long)a, d, s)
-#define readsl(a, d, s) __raw_readsl((unsigned long)a, d, s)
-#define writesw(a, d, s) __raw_writesw((unsigned long)a, d, s)
-#define readsw(a, d, s) __raw_readsw((unsigned long)a, d, s)
-#define writesb(a, d, s) __raw_writesb((unsigned long)a, d, s)
-#define readsb(a, d, s) __raw_readsb((unsigned long)a, d, s)
-
 #define device_init_wakeup(dev, a) do {} while (0)
 
 #define platform_data device_data
-- 
1.8.3.1

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[U-Boot] [PATCH v3 1/2] flash: add device ID for Microchip PIC32 internal flash.

[Purna Chandra Mandal]

Microchip PIC32 has internal parallel flash (non-CFI compliant).
These flash devices do not support any identifier command so no
standard IDs. Added unique IDs to seperate these flash devices
from others supported by U-Boot.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---

Changes in v3: None
Changes in v2: None

 include/flash.h | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/include/flash.h b/include/flash.h
index f53ace7..c9aacd5 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -400,6 +400,9 @@ extern flash_info_t *flash_get_info(ulong base);
 #define FLASH_STM800DT 0x00D7  /* STM M29W800DT (1M = 64K x 16, top)   
*/
 #define FLASH_STM800DB 0x005B  /* STM M29W800DB (1M = 64K x 16, 
bottom)*/
 
+#define FLASH_MCHP100T 0x0060  /* MCHP internal (1M = 64K x 16) */
+#define FLASH_MCHP100B 0x0061  /* MCHP internal (1M = 64K x 16) */
+
 #define FLASH_28F400_T 0x0062  /* MT  28F400B3 ID (  4M = 256K x 16 )  
*/
 #define FLASH_28F400_B 0x0063  /* MT  28F400B3 ID (  4M = 256K x 16 )  
*/
 
@@ -486,7 +489,7 @@ extern flash_info_t *flash_get_info(ulong base);
 #define FLASH_MAN_SHARP 0x0050
 #define FLASH_MAN_ATM  0x0060
 #define FLASH_MAN_CFI  0x0100
-
+#define FLASH_MAN_MCHP 0x0200  /* Microchip Technology */
 
 #define FLASH_TYPEMASK 0x  /* extract FLASH type   information 
*/
 #define FLASH_VENDMASK 0x  /* extract FLASH vendor information 
*/
-- 
1.8.3.1

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Re: [U-Boot] [PATCH] drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.

[Purna Chandra Mandal]

On 03/15/2016 05:35 PM, Jagan Teki wrote:

> On 14 March 2016 at 19:37, Purna Chandra Mandal
> <purna.man...@microchip.com> wrote:
>> Jagan.
>>
>> On 03/14/2016 07:16 PM, Jagan Teki wrote:
>>
>>> On Monday 14 March 2016 07:00 PM, Purna Chandra Mandal wrote:
>>>> On 03/14/2016 06:13 PM, Daniel Schwierzeck wrote:
>>>>> 2016-03-10 14:12 GMT+01:00 Purna Chandra Mandal 
>>>>> <purna.man...@microchip.com>:
>>>>>> PIC32 embedded flash banks are memory mapped, directly read by CPU,
>>>>>> and programming (erase followed by write) operation on them are
>>>>>> handled by on-chip NVM controller.
>>>>>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>>>>> ---
>>>>>>   drivers/mtd/Kconfig   |   6 +
>>>>>>   drivers/mtd/Makefile  |   1 +
>>>>>>   drivers/mtd/pic32_flash.c | 377 
>>>>>> ++
>>> BTW: this driver need to be write in mtd driver mode, see for existing
>>> drivers and let me know for any help.
>> Will take up this activity [of supporting MTD] later on. For the time-being 
>> we are
>> not using mtd on embedded flash, mainly using for environment and bootcode 
>> which
>> are at well-known offset, size defined in include/configs/.
> I understand your concern, but It look very hard to maintain the new
> drivers with non-dm model.

If issue is only non-dm model I can add DM support with exception that it will 
not
implement MTD functionality.

> My suggestions are better to add this on existing mtd(cfi or
> something) I guess ie "not possible"  or move this driver to your soc
> or board code for time being till mtd uclass addition or write a fresh
> mtd dm driver.

PIC32 flash devices are non CFI/JEDEC compliant so no way we can separate one 
flash
chip from other. Even though flash devices are parallel erase and program on 
these
flash chips are performed through NVM controller (serial interface). So we can't
directly port the functionality on CFI driver.

I like the idea of adding this driver under arch/soc/ or board/. But that is 
where it was
initially added, but based on review comment it is moved to drivers/mtd/.

Please suggest me a way!

> thanks!

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Re: [U-Boot] [PATCH v3 3/4] drivers: musb-new: Add USB DRC driver for Microchip PIC32 OTG controller.

[Purna Chandra Mandal]

On 03/15/2016 11:49 PM, Marek Vasut wrote:

> On 03/15/2016 01:44 PM, Purna Chandra Mandal wrote:
>> This driver adds support of PIC32 MUSB OTG controller as dual role device.
>> It implements platform specific glue to reuse musb core.
>>
>> Signed-off-by: Cristian Birsan <cristian.bir...@microchip.com>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
> [...]
>
>> diff --git a/drivers/usb/musb-new/pic32.c b/drivers/usb/musb-new/pic32.c
>> new file mode 100644
>> index 000..980a971
>> --- /dev/null
>> +++ b/drivers/usb/musb-new/pic32.c
>> @@ -0,0 +1,294 @@
>> +/*
>> + * Microchip PIC32 MUSB "glue layer"
>> + *
>> + * Copyright (C) 2015, Microchip Technology Inc.
>> + *  Cristian Birsan <cristian.bir...@microchip.com>
>> + *  Purna Chandra Mandal <purna.man...@microchip.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + *
>> + * Based on the dsps "glue layer" code.
>> + */
>> +
>> +#include 
>> +#include 
>> +#include "linux-compat.h"
>> +#include "musb_core.h"
>> +#include "musb_uboot.h"
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#define PIC32_TX_EP_MASK0x0f/* EP0 + 7 Tx EPs */
>> +#define PIC32_RX_EP_MASK0x0e/* 7 Rx EPs */
>> +
>> +#define MUSB_SOFTRST0x7f
>> +#define  MUSB_SOFTRST_NRST  BIT(0)
>> +#define  MUSB_SOFTRST_NRSTX BIT(1)
>> +
>> +#define USBCRCON0
>> +#define  USBCRCON_USBWKUPEN BIT(0)  /* Enable Wakeup Interrupt */
>> +#define  USBCRCON_USBRIEBIT(1)  /* Enable Remote resume Interrupt */
>> +#define  USBCRCON_USBIE BIT(2)  /* Enable USB General interrupt 
>> */
>> +#define  USBCRCON_SENDMONEN BIT(3)  /* Enable Session End VBUS monitoring */
>> +#define  USBCRCON_BSVALMONENBIT(4)  /* Enable B-Device VBUS 
>> monitoring */
>> +#define  USBCRCON_ASVALMONENBIT(5)  /* Enable A-Device VBUS 
>> monitoring */
>> +#define  USBCRCON_VBUSMONEN BIT(6)  /* Enable VBUS monitoring */
>> +#define  USBCRCON_PHYIDEN   BIT(7)  /* PHY ID monitoring enable */
>> +#define  USBCRCON_USBIDVAL  BIT(8)  /* USB ID value */
>> +#define  USBCRCON_USBIDOVEN BIT(9)  /* USB ID override enable */
>> +#define  USBCRCON_USBWK BIT(24) /* USB Wakeup Status */
>> +#define  USBCRCON_USBRF BIT(25) /* USB Resume Status */
>> +#define  USBCRCON_USBIF BIT(26) /* USB General Interrupt Status 
>> */
>> +
>> +static void __iomem *musb_glue;
> What would happen once you make a chip with two MUSB controllers ?

Currently PIC32 has only one MUSB controller and only one glue reg-space.
Don't know how the reg-map will be in future when PIC32 will have multiple
MUSB controllers. Assuming that glue address map will be separate for
each controller we can add logic to support multiple MUSB controller.

IMO, better if we don't assume something of the future and bloat logic.

>> +/* pic32_musb_disable - disable HDRC */
>> +static void pic32_musb_disable(struct musb *musb)
>> +{
> Is there no way to shut down the MUSB on the PIC32 ?

There is no way to disable MUSB.

>> +}
>> +
>> +/* pic32_musb_enable - enable HDRC */
>> +static int pic32_musb_enable(struct musb *musb)
>> +{
>> +/* soft reset by NRSTx */
>> +musb_writeb(musb->mregs, MUSB_SOFTRST, MUSB_SOFTRST_NRSTX);
>> +/* set mode */
>> +musb_platform_set_mode(musb, musb->board_mode);
>> +
>> +return 0;
>> +}
>> +
>> +static irqreturn_t pic32_interrupt(int irq, void *hci)
>> +{
>> +struct musb  *musb = hci;
>> +irqreturn_t ret = IRQ_NONE;
>> +u32 epintr, usbintr;
>> +
>> +/* Get usb core interrupts */
> You mean "get" or "ack" here ?

I meant read-and-ack. Will update comment.

>> +musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
>> +if (musb->int_usb)
>> +musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
>> +
>> +/* Get endpoint interrupts */
> DTTO

I meant read-and-ack.

>> +musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX) & PIC32_RX_EP_MASK;
>> +if (musb->int_rx)
>> +musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
> Same here

ack. Will update comment.

>> +musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX) & PIC32_TX_EP_MASK;
>> +if (musb->int_tx)
>> +musb_writew(musb->mregs, MUSB_INTRTX, musb->

Re: [U-Boot] [PATCH v3 2/4] drivers: musb-new: remove writes{bwlq} and reads{bwlq}.

[Purna Chandra Mandal]

On 03/15/2016 11:40 PM, Marek Vasut wrote:

> On 03/15/2016 01:44 PM, Purna Chandra Mandal wrote:
>> Moved definition of writes{bwlq} and reads{bwlq} into arch.
>> There is no need of having arch specific wrapper in driver.
> And so the patch does ... what exactly ? I cannot figure it out just by
> reading the commit message, sorry.
>
> The patch itself is fine of course, but please fix the commit message.

I hope new commit message will do.
"Definition of writes{bwlq}, reads{bwlq} are now added into arch specific 
asm/io.h.
 So removing them from driver to fix re-definition error.
"

>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>> ---
>>
>> Changes in v3: None
>> Changes in v2: None
>>
>>  drivers/usb/musb-new/linux-compat.h | 7 ---
>>  1 file changed, 7 deletions(-)
>>
>> diff --git a/drivers/usb/musb-new/linux-compat.h 
>> b/drivers/usb/musb-new/linux-compat.h
>> index 46f83d9..526f4f2 100644
>> --- a/drivers/usb/musb-new/linux-compat.h
>> +++ b/drivers/usb/musb-new/linux-compat.h
>> @@ -13,13 +13,6 @@
>>  printf(fmt, ##args);\
>>  ret_warn; })
>>  
>> -#define writesl(a, d, s) __raw_writesl((unsigned long)a, d, s)
>> -#define readsl(a, d, s) __raw_readsl((unsigned long)a, d, s)
>> -#define writesw(a, d, s) __raw_writesw((unsigned long)a, d, s)
>> -#define readsw(a, d, s) __raw_readsw((unsigned long)a, d, s)
>> -#define writesb(a, d, s) __raw_writesb((unsigned long)a, d, s)
>> -#define readsb(a, d, s) __raw_readsb((unsigned long)a, d, s)
>> -
>>  #define device_init_wakeup(dev, a) do {} while (0)
>>  
>>  #define platform_data device_data
>>
>

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[U-Boot] [PATCH v3 4/4] board: pic32mzda: enable USB-host, USB-storage support.

[Purna Chandra Mandal]

Enable MUSB host and USB storage support for Microchip
PIC32MZ[DA] Starter Kit.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

Changes in v3:
- add arch specific reads{bwlq}, writes{bwlq} in respective arch io.h
- remove reads{bwlq}, writes{bwlq} in musb-new driver

Changes in v2:
- compilation fix in drivers/usb/musb-new/linux-compat.h seperated
- compilation fix in drivers/gadget/f_mass_storage.c seperated

 arch/mips/dts/pic32mzda.dtsi   | 10 ++
 arch/mips/dts/pic32mzda_sk.dts |  4 
 configs/pic32mzdask_defconfig  |  6 +-
 include/configs/pic32mzdask.h  |  7 +++
 4 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
index 7d180d9..57e4500 100644
--- a/arch/mips/dts/pic32mzda.dtsi
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -171,4 +171,14 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+   usb: musb@1f8e3000 {
+   compatible = "microchip,pic32mzda-usb";
+   reg = <0x1f8e3000 0x1000>,
+ <0x1f884000 0x1000>;
+   reg-names = "mc", "control";
+   interrupts = <132 IRQ_TYPE_EDGE_RISING>,
+<133 IRQ_TYPE_LEVEL_HIGH>;
+   status = "disabled";
+   };
 };
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
index e5ce0bd..0a7847e 100644
--- a/arch/mips/dts/pic32mzda_sk.dts
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -52,4 +52,8 @@
ethernet_phy: lan8740_phy@0 {
reg = <0>;
};
+};
+
+ {
+   status = "okay";
 };
\ No newline at end of file
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 1dbe1b5..544112f 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -12,6 +12,7 @@ CONFIG_SYS_PROMPT="dask # "
 CONFIG_LOOPW=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_RARP=y
@@ -28,6 +29,9 @@ CONFIG_DM_ETH=y
 CONFIG_PIC32_ETH=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_FULL is not set
-CONFIG_SYS_VSNPRINTF=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_STORAGE=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 2d35a0b..1d5be2b 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -117,6 +117,12 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_MMC
 
+/*--
+ * USB Configuration
+ */
+#define CONFIG_USB_MUSB_PIO_ONLY
+#define CONFIG_SYS_CACHELINE_SIZE  16
+
 /*---
  * File System Configuration
  */
@@ -167,6 +173,7 @@
 
 #define BOOT_TARGET_DEVICES(func)  \
func(MMC, mmc, 0)   \
+   func(USB, usb, 0)   \
func(DHCP, dhcp, na)
 
 #include 
-- 
1.8.3.1

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[U-Boot] [PATCH v3 3/4] drivers: musb-new: Add USB DRC driver for Microchip PIC32 OTG controller.

[Purna Chandra Mandal]

This driver adds support of PIC32 MUSB OTG controller as dual role device.
It implements platform specific glue to reuse musb core.

Signed-off-by: Cristian Birsan <cristian.bir...@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---

Changes in v3: None
Changes in v2: None

 drivers/usb/musb-new/Kconfig |   7 +
 drivers/usb/musb-new/Makefile|   1 +
 drivers/usb/musb-new/musb_core.c |   2 +-
 drivers/usb/musb-new/pic32.c | 294 +++
 4 files changed, 303 insertions(+), 1 deletion(-)
 create mode 100644 drivers/usb/musb-new/pic32.c

diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index 6a6cb93..4e8a543 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -15,6 +15,13 @@ config USB_MUSB_GADGET
 
 if USB_MUSB_HOST || USB_MUSB_GADGET
 
+config USB_MUSB_PIC32
+   bool "Enable Microchip PIC32 DRC USB controller"
+   depends on DM_USB && MACH_PIC32
+   help
+ Say y to enable PIC32 USB DRC controller support
+ if it is available on your Microchip PIC32 platform.
+
 config USB_MUSB_SUNXI
bool "Enable sunxi OTG / DRC USB controller"
depends on ARCH_SUNXI
diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile
index 072d516..df1c3c8 100644
--- a/drivers/usb/musb-new/Makefile
+++ b/drivers/usb/musb-new/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_USB_MUSB_HOST) += musb_host.o musb_core.o 
musb_uboot.o
 obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o
 obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o
 obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
+obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o
 obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
 
 ccflags-y := $(call cc-option,-Wno-unused-variable) \
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index a6d6af6..dd0443c 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -259,7 +259,7 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, 
const u8 *src)
}
 }
 
-#if !defined(CONFIG_USB_MUSB_AM35X)
+#if !defined(CONFIG_USB_MUSB_AM35X) && !defined(CONFIG_USB_MUSB_PIC32)
 /*
  * Unload an endpoint's FIFO
  */
diff --git a/drivers/usb/musb-new/pic32.c b/drivers/usb/musb-new/pic32.c
new file mode 100644
index 000..980a971
--- /dev/null
+++ b/drivers/usb/musb-new/pic32.c
@@ -0,0 +1,294 @@
+/*
+ * Microchip PIC32 MUSB "glue layer"
+ *
+ * Copyright (C) 2015, Microchip Technology Inc.
+ *  Cristian Birsan <cristian.bir...@microchip.com>
+ *  Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Based on the dsps "glue layer" code.
+ */
+
+#include 
+#include 
+#include "linux-compat.h"
+#include "musb_core.h"
+#include "musb_uboot.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PIC32_TX_EP_MASK   0x0f/* EP0 + 7 Tx EPs */
+#define PIC32_RX_EP_MASK   0x0e/* 7 Rx EPs */
+
+#define MUSB_SOFTRST   0x7f
+#define  MUSB_SOFTRST_NRST BIT(0)
+#define  MUSB_SOFTRST_NRSTXBIT(1)
+
+#define USBCRCON   0
+#define  USBCRCON_USBWKUPENBIT(0)  /* Enable Wakeup Interrupt */
+#define  USBCRCON_USBRIE   BIT(1)  /* Enable Remote resume Interrupt */
+#define  USBCRCON_USBIEBIT(2)  /* Enable USB General interrupt 
*/
+#define  USBCRCON_SENDMONENBIT(3)  /* Enable Session End VBUS monitoring */
+#define  USBCRCON_BSVALMONEN   BIT(4)  /* Enable B-Device VBUS monitoring */
+#define  USBCRCON_ASVALMONEN   BIT(5)  /* Enable A-Device VBUS monitoring */
+#define  USBCRCON_VBUSMONENBIT(6)  /* Enable VBUS monitoring */
+#define  USBCRCON_PHYIDEN  BIT(7)  /* PHY ID monitoring enable */
+#define  USBCRCON_USBIDVAL BIT(8)  /* USB ID value */
+#define  USBCRCON_USBIDOVENBIT(9)  /* USB ID override enable */
+#define  USBCRCON_USBWKBIT(24) /* USB Wakeup Status */
+#define  USBCRCON_USBRFBIT(25) /* USB Resume Status */
+#define  USBCRCON_USBIFBIT(26) /* USB General Interrupt Status 
*/
+
+static void __iomem *musb_glue;
+
+/* pic32_musb_disable - disable HDRC */
+static void pic32_musb_disable(struct musb *musb)
+{
+}
+
+/* pic32_musb_enable - enable HDRC */
+static int pic32_musb_enable(struct musb *musb)
+{
+   /* soft reset by NRSTx */
+   musb_writeb(musb->mregs, MUSB_SOFTRST, MUSB_SOFTRST_NRSTX);
+   /* set mode */
+   musb_platform_set_mode(musb, musb->board_mode);
+
+   return 0;
+}
+
+static irqreturn_t pic32_interrupt(int irq, void *hci)
+{
+   struct musb  *musb = hci;
+   irqreturn_t ret = IRQ_NONE;
+   u32 epintr, usbintr;
+
+   /* Get usb core interrupts */
+   musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
+   if (musb->int_usb)
+   musb_writeb(musb->mregs, MUSB_INTRUSB, musb-&

[U-Boot] [PATCH v3 1/4] arm: add missing writes{bwql}, reads{bwql}.

[Purna Chandra Mandal]

ARM arch defines __raw_writes[bwql], __raw_reads[bwql] in io.h
but not writes[bwql], reads[bwql] as required by some drivers.
Some of the drivers are defining writes{bwlq} or reads{bwlq} as
wrapper of their "__raw" version.
To avoid that lets add the wrapper in arch itself.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---

Changes in v3: None
Changes in v2: None

 arch/arm/include/asm/io.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 75773bd..9d185a6 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -284,6 +284,13 @@ static inline void __raw_readsl(unsigned long addr, void 
*data, int longlen)
 #define insw_p(port,to,len)insw(port,to,len)
 #define insl_p(port,to,len)insl(port,to,len)
 
+#define writesl(a, d, s)   __raw_writesl((unsigned long)a, d, s)
+#define readsl(a, d, s)__raw_readsl((unsigned long)a, d, s)
+#define writesw(a, d, s)   __raw_writesw((unsigned long)a, d, s)
+#define readsw(a, d, s)__raw_readsw((unsigned long)a, d, s)
+#define writesb(a, d, s)   __raw_writesb((unsigned long)a, d, s)
+#define readsb(a, d, s)__raw_readsb((unsigned long)a, d, s)
+
 /*
  * ioremap and friends.
  *
-- 
1.8.3.1

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[U-Boot] [PATCH v3 2/4] drivers: musb-new: remove writes{bwlq} and reads{bwlq}.

[Purna Chandra Mandal]

Moved definition of writes{bwlq} and reads{bwlq} into arch.
There is no need of having arch specific wrapper in driver.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---

Changes in v3: None
Changes in v2: None

 drivers/usb/musb-new/linux-compat.h | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/drivers/usb/musb-new/linux-compat.h 
b/drivers/usb/musb-new/linux-compat.h
index 46f83d9..526f4f2 100644
--- a/drivers/usb/musb-new/linux-compat.h
+++ b/drivers/usb/musb-new/linux-compat.h
@@ -13,13 +13,6 @@
printf(fmt, ##args);\
ret_warn; })
 
-#define writesl(a, d, s) __raw_writesl((unsigned long)a, d, s)
-#define readsl(a, d, s) __raw_readsl((unsigned long)a, d, s)
-#define writesw(a, d, s) __raw_writesw((unsigned long)a, d, s)
-#define readsw(a, d, s) __raw_readsw((unsigned long)a, d, s)
-#define writesb(a, d, s) __raw_writesb((unsigned long)a, d, s)
-#define readsb(a, d, s) __raw_readsb((unsigned long)a, d, s)
-
 #define device_init_wakeup(dev, a) do {} while (0)
 
 #define platform_data device_data
-- 
1.8.3.1

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[U-Boot] [PATCH v2 2/2] drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.

[Purna Chandra Mandal]

PIC32 internal flash devices are parallel NOR flash divided into
number of banks to allow erase-programming in one while fetch and
execution continues on other. As the flash banks are memory mapped
stored code can be executed directly from flash (XIP), also there
is additional hardware logic to prefetch and cache contents to
improve execution performance. These flash can also be used to
store user data (like environment).
Flash erase and programming are handled by on-chip NVM controller.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

Changes in v2:
- kconfig: add CONFIG_FLASH_PIC32 dependent on MACH_PIC32
- fix single/multi-line comment style
- simplify byte-stream-to-word in little-endian format
- replace virt_to_phys() with CPHYSADDR()
- separate flash ID definition in different patch

 drivers/mtd/Kconfig   |   7 +
 drivers/mtd/Makefile  |   1 +
 drivers/mtd/pic32_flash.c | 380 ++
 3 files changed, 388 insertions(+)
 create mode 100644 drivers/mtd/pic32_flash.c

diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index c58841e..5ed860d 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -30,6 +30,13 @@ config ALTERA_QSPI
 
 endmenu
 
+config FLASH_PIC32
+   bool "Microchip PIC32 Flash driver"
+   depends on MACH_PIC32
+   help
+ This enables access to Microchip PIC32 internal non-CFI flash
+ chips through PIC32 Non-Volatile-Memory Controller.
+
 source "drivers/mtd/nand/Kconfig"
 
 source "drivers/mtd/spi/Kconfig"
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 7f018a4..9380085 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -19,4 +19,5 @@ obj-$(CONFIG_HAS_DATAFLASH) += dataflash.o
 obj-$(CONFIG_FTSMC020) += ftsmc020.o
 obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
 obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o
+obj-$(CONFIG_FLASH_PIC32) += pic32_flash.o
 obj-$(CONFIG_ST_SMI) += st_smi.o
diff --git a/drivers/mtd/pic32_flash.c b/drivers/mtd/pic32_flash.c
new file mode 100644
index 000..59555ca
--- /dev/null
+++ b/drivers/mtd/pic32_flash.c
@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2015
+ * Cristian Birsan <cristian.bir...@microchip.com>
+ * Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+/* NVM Controller registers */
+struct pic32_reg_nvm {
+   struct pic32_reg_atomic ctrl;
+   struct pic32_reg_atomic key;
+   struct pic32_reg_atomic addr;
+   struct pic32_reg_atomic data;
+};
+
+/* NVM operations */
+#define NVMOP_NOP  0
+#define NVMOP_WORD_WRITE   1
+#define NVMOP_PAGE_ERASE   4
+
+/* NVM control bits */
+#define NVM_WR BIT(15)
+#define NVM_WREN   BIT(14)
+#define NVM_WRERR  BIT(13)
+#define NVM_LVDERR BIT(12)
+
+/* NVM programming unlock register */
+#define LOCK_KEY   0x0
+#define UNLOCK_KEY10xaa996655
+#define UNLOCK_KEY20x556699aa
+
+/*
+ * PIC32 flash banks consist of number of pages, each page
+ * into number of rows and rows into number of words.
+ * Here we will maintain page information instead of sector.
+ */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+static struct pic32_reg_nvm *nvm_regs_p;
+
+static inline void flash_initiate_operation(u32 nvmop)
+{
+   /* set operation */
+   writel(nvmop, _regs_p->ctrl.raw);
+
+   /* enable flash write */
+   writel(NVM_WREN, _regs_p->ctrl.set);
+
+   /* unlock sequence */
+   writel(LOCK_KEY, _regs_p->key.raw);
+   writel(UNLOCK_KEY1, _regs_p->key.raw);
+   writel(UNLOCK_KEY2, _regs_p->key.raw);
+
+   /* initiate operation */
+   writel(NVM_WR, _regs_p->ctrl.set);
+}
+
+static int flash_wait_till_busy(const char *func, ulong timeout)
+{
+   int ret = wait_for_bit(__func__, _regs_p->ctrl.raw,
+  NVM_WR, false, timeout, false);
+
+   return ret ? ERR_TIMOUT : ERR_OK;
+}
+
+static inline int flash_complete_operation(void)
+{
+   u32 tmp;
+
+   tmp = readl(_regs_p->ctrl.raw);
+   if (tmp & NVM_WRERR) {
+   printf("Error in Block Erase - Lock Bit may be set!\n");
+   flash_initiate_operation(NVMOP_NOP);
+   return ERR_PROTECTED;
+   }
+
+   if (tmp & NVM_LVDERR) {
+   printf("Error in Block Erase - low-vol detected!\n");
+   flash_initiate_operation(NVMOP_NOP);
+   return ERR_NOT_ERASED;
+   }
+
+   /* disable flash write or erase operation */
+   writel(NVM_WREN, _regs_p->ctrl.clr);
+
+   return ERR_OK;
+}
+
+/*
+ * Erase flash sectors, returns:
+ * ERR_OK - OK
+ * ERR_INVAL - invalid sector arguments
+ * ERR_TIMOUT - write timeout
+ * ERR_NOT_ERASED - Flash not erased
+ * ERR_UNKNOWN_FLASH_VENDO

[U-Boot] [PATCH v2 1/2] flash: add device ID for Microchip PIC32 internal flash.

[Purna Chandra Mandal]

Microchip PIC32 has internal parallel flash (non-CFI compliant).
These flash devices do not support any identifier command so no
standard IDs. Added unique IDs to seperate these flash devices
from others supported by U-Boot.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---

Changes in v2: None

 include/flash.h | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/include/flash.h b/include/flash.h
index f53ace7..c9aacd5 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -400,6 +400,9 @@ extern flash_info_t *flash_get_info(ulong base);
 #define FLASH_STM800DT 0x00D7  /* STM M29W800DT (1M = 64K x 16, top)   
*/
 #define FLASH_STM800DB 0x005B  /* STM M29W800DB (1M = 64K x 16, 
bottom)*/
 
+#define FLASH_MCHP100T 0x0060  /* MCHP internal (1M = 64K x 16) */
+#define FLASH_MCHP100B 0x0061  /* MCHP internal (1M = 64K x 16) */
+
 #define FLASH_28F400_T 0x0062  /* MT  28F400B3 ID (  4M = 256K x 16 )  
*/
 #define FLASH_28F400_B 0x0063  /* MT  28F400B3 ID (  4M = 256K x 16 )  
*/
 
@@ -486,7 +489,7 @@ extern flash_info_t *flash_get_info(ulong base);
 #define FLASH_MAN_SHARP 0x0050
 #define FLASH_MAN_ATM  0x0060
 #define FLASH_MAN_CFI  0x0100
-
+#define FLASH_MAN_MCHP 0x0200  /* Microchip Technology */
 
 #define FLASH_TYPEMASK 0x  /* extract FLASH type   information 
*/
 #define FLASH_VENDMASK 0x  /* extract FLASH vendor information 
*/
-- 
1.8.3.1

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Re: [U-Boot] [PATCH] drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.

[Purna Chandra Mandal]

Jagan.

On 03/14/2016 07:16 PM, Jagan Teki wrote:

> On Monday 14 March 2016 07:00 PM, Purna Chandra Mandal wrote:
>> On 03/14/2016 06:13 PM, Daniel Schwierzeck wrote:
>>> 2016-03-10 14:12 GMT+01:00 Purna Chandra Mandal 
>>> <purna.man...@microchip.com>:
>>>> PIC32 embedded flash banks are memory mapped, directly read by CPU,
>>>> and programming (erase followed by write) operation on them are
>>>> handled by on-chip NVM controller.
>>>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>>> ---
>>>>   drivers/mtd/Kconfig   |   6 +
>>>>   drivers/mtd/Makefile  |   1 +
>>>>   drivers/mtd/pic32_flash.c | 377 
>>>> ++
> BTW: this driver need to be write in mtd driver mode, see for existing 
> drivers and let me know for any help.

Will take up this activity [of supporting MTD] later on. For the time-being we 
are
not using mtd on embedded flash, mainly using for environment and bootcode which
are at well-known offset, size defined in include/configs/.

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Re: [U-Boot] [PATCH] drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.

[Purna Chandra Mandal]

On 03/14/2016 06:13 PM, Daniel Schwierzeck wrote:

> 2016-03-10 14:12 GMT+01:00 Purna Chandra Mandal <purna.man...@microchip.com>:
>> PIC32 embedded flash banks are memory mapped, directly read by CPU,
>> and programming (erase followed by write) operation on them are
>> handled by on-chip NVM controller.
>>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>
>> ---
>>
>>  drivers/mtd/Kconfig   |   6 +
>>  drivers/mtd/Makefile  |   1 +
>>  drivers/mtd/pic32_flash.c | 377 
>> ++
>>  include/flash.h   |   5 +-
>>  4 files changed, 388 insertions(+), 1 deletion(-)
>>  create mode 100644 drivers/mtd/pic32_flash.c
>>
>> diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
>> index c58841e..e3c6b9f 100644
>> --- a/drivers/mtd/Kconfig
>> +++ b/drivers/mtd/Kconfig
>> @@ -30,6 +30,12 @@ config ALTERA_QSPI
>>
>>  endmenu
>>
>> +config FLASH_PIC32
>> +   bool "Microchip PIC32 Flash driver"
> you should add: depends on MACH_PIC32

ack. Will add,

>> +   help
>> + This enables access to Microchip PIC32 internal non-CFI flash
>> + chips through PIC32 Non-Volatile-Memory Controller.
>> +
>>  source "drivers/mtd/nand/Kconfig"
>>
>>  source "drivers/mtd/spi/Kconfig"
>> diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
>> index 7f018a4..9380085 100644
>> --- a/drivers/mtd/Makefile
>> +++ b/drivers/mtd/Makefile
>> @@ -19,4 +19,5 @@ obj-$(CONFIG_HAS_DATAFLASH) += dataflash.o
>>  obj-$(CONFIG_FTSMC020) += ftsmc020.o
>>  obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
>>  obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o
>> +obj-$(CONFIG_FLASH_PIC32) += pic32_flash.o
>>  obj-$(CONFIG_ST_SMI) += st_smi.o
>> diff --git a/drivers/mtd/pic32_flash.c b/drivers/mtd/pic32_flash.c
>> new file mode 100644
>> index 000..9a226b1
>> --- /dev/null
>> +++ b/drivers/mtd/pic32_flash.c
>> @@ -0,0 +1,377 @@
>> +/*
>> + * Copyright (C) 2015
>> + * Cristian Birsan <cristian.bir...@microchip.com>
>> + * Purna Chandra Mandal <purna.man...@microchip.com>
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +/* NVM Controller registers */
>> +struct pic32_reg_nvm {
>> +   struct pic32_reg_atomic ctrl;
>> +   struct pic32_reg_atomic key;
>> +   struct pic32_reg_atomic addr;
>> +   struct pic32_reg_atomic data;
>> +};
>> +
>> +/* NVM operations */
>> +#define NVMOP_NOP  0
>> +#define NVMOP_WORD_WRITE   1
>> +#define NVMOP_PAGE_ERASE   4
>> +
>> +/* NVM control bits */
>> +#define NVM_WR BIT(15)
>> +#define NVM_WREN   BIT(14)
>> +#define NVM_WRERR  BIT(13)
>> +#define NVM_LVDERR BIT(12)
>> +
>> +/* NVM programming unlock register */
>> +#define LOCK_KEY   0x0
>> +#define UNLOCK_KEY10xaa996655
>> +#define UNLOCK_KEY20x556699aa
>> +
>> +/* PIC32 flash banks consist of number of pages, each page
>> + * into number of row and rows are into number of words.
>> + * Here we will maintain page information instead of sector.
>> + */
>> +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
>> +static struct pic32_reg_nvm *nvm_regs_p;
>> +
>> +static inline void flash_initiate_operation(u32 nvmop)
>> +{
>> +   /* set operation */
>> +   writel(nvmop, _regs_p->ctrl.raw);
>> +
>> +   /* enable flash write */
>> +   writel(NVM_WREN, _regs_p->ctrl.set);
>> +
>> +   /* unlock sequence */
>> +   writel(LOCK_KEY, _regs_p->key.raw);
>> +   writel(UNLOCK_KEY1, _regs_p->key.raw);
>> +   writel(UNLOCK_KEY2, _regs_p->key.raw);
>> +
>> +   /* initiate operation */
>> +   writel(NVM_WR, _regs_p->ctrl.set);
>> +}
>> +
>> +static int flash_wait_till_busy(const char *func, ulong timeout)
>> +{
>> +   int ret = wait_for_bit(__func__, _regs_p->ctrl.raw,
>> +  NVM_WR, false, timeout, false);
>> +
>> +   return ret ? ERR_TIMOUT : ERR_OK;
>> +}
>> +
>> +static inline int flash_complete_operation(void)
>> +{
>> +   u32 v;
>> +
>> +   v = readl(_regs_p->ctrl.raw);
>> +   if (v & NVM

Re: [U-Boot] [PATCH] drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.

[Purna Chandra Mandal]

On 03/10/2016 07:11 PM, Jagan Teki wrote:
> On Thursday 10 March 2016 06:42 PM, Purna Chandra Mandal wrote:
>> PIC32 embedded flash banks are memory mapped, directly read by CPU,
>> and programming (erase followed by write) operation on them are
>> handled by on-chip NVM controller.
>
> Can you please add some more description to understand bit more, which kind 
> of flash it is, parallel NOR?
>
Jagan,

These are parallel NOR flash divided into number of banks to allow
erase/programming in one while fetch/execution continues from other.
As the flash is memory-mapped code stored can be directly executed
from flash (XIP), also there is additional hardware logic to prefetch
and cache contents to improve code execution. These flash can also
be used to store user data.

In PIC32 there are two sets of embedded flash memory of same type -
boot flash, and program flash; early-boot-code executes from
boot-flash and one bank of program-flash is used for u-boot, other
bank for environment.

> thanks!
> -- 
> Jagan.

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[U-Boot] [PATCH] drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.

[Purna Chandra Mandal]

PIC32 embedded flash banks are memory mapped, directly read by CPU,
and programming (erase followed by write) operation on them are
handled by on-chip NVM controller.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

 drivers/mtd/Kconfig   |   6 +
 drivers/mtd/Makefile  |   1 +
 drivers/mtd/pic32_flash.c | 377 ++
 include/flash.h   |   5 +-
 4 files changed, 388 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mtd/pic32_flash.c

diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index c58841e..e3c6b9f 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -30,6 +30,12 @@ config ALTERA_QSPI
 
 endmenu
 
+config FLASH_PIC32
+   bool "Microchip PIC32 Flash driver"
+   help
+ This enables access to Microchip PIC32 internal non-CFI flash
+ chips through PIC32 Non-Volatile-Memory Controller.
+
 source "drivers/mtd/nand/Kconfig"
 
 source "drivers/mtd/spi/Kconfig"
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 7f018a4..9380085 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -19,4 +19,5 @@ obj-$(CONFIG_HAS_DATAFLASH) += dataflash.o
 obj-$(CONFIG_FTSMC020) += ftsmc020.o
 obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
 obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o
+obj-$(CONFIG_FLASH_PIC32) += pic32_flash.o
 obj-$(CONFIG_ST_SMI) += st_smi.o
diff --git a/drivers/mtd/pic32_flash.c b/drivers/mtd/pic32_flash.c
new file mode 100644
index 000..9a226b1
--- /dev/null
+++ b/drivers/mtd/pic32_flash.c
@@ -0,0 +1,377 @@
+/*
+ * Copyright (C) 2015
+ * Cristian Birsan <cristian.bir...@microchip.com>
+ * Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+/* NVM Controller registers */
+struct pic32_reg_nvm {
+   struct pic32_reg_atomic ctrl;
+   struct pic32_reg_atomic key;
+   struct pic32_reg_atomic addr;
+   struct pic32_reg_atomic data;
+};
+
+/* NVM operations */
+#define NVMOP_NOP  0
+#define NVMOP_WORD_WRITE   1
+#define NVMOP_PAGE_ERASE   4
+
+/* NVM control bits */
+#define NVM_WR BIT(15)
+#define NVM_WREN   BIT(14)
+#define NVM_WRERR  BIT(13)
+#define NVM_LVDERR BIT(12)
+
+/* NVM programming unlock register */
+#define LOCK_KEY   0x0
+#define UNLOCK_KEY10xaa996655
+#define UNLOCK_KEY20x556699aa
+
+/* PIC32 flash banks consist of number of pages, each page
+ * into number of row and rows are into number of words.
+ * Here we will maintain page information instead of sector.
+ */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+static struct pic32_reg_nvm *nvm_regs_p;
+
+static inline void flash_initiate_operation(u32 nvmop)
+{
+   /* set operation */
+   writel(nvmop, _regs_p->ctrl.raw);
+
+   /* enable flash write */
+   writel(NVM_WREN, _regs_p->ctrl.set);
+
+   /* unlock sequence */
+   writel(LOCK_KEY, _regs_p->key.raw);
+   writel(UNLOCK_KEY1, _regs_p->key.raw);
+   writel(UNLOCK_KEY2, _regs_p->key.raw);
+
+   /* initiate operation */
+   writel(NVM_WR, _regs_p->ctrl.set);
+}
+
+static int flash_wait_till_busy(const char *func, ulong timeout)
+{
+   int ret = wait_for_bit(__func__, _regs_p->ctrl.raw,
+  NVM_WR, false, timeout, false);
+
+   return ret ? ERR_TIMOUT : ERR_OK;
+}
+
+static inline int flash_complete_operation(void)
+{
+   u32 v;
+
+   v = readl(_regs_p->ctrl.raw);
+   if (v & NVM_WRERR) {
+   printf("Error in Block Erase - Lock Bit may be set!\n");
+   flash_initiate_operation(NVMOP_NOP);
+   return ERR_PROTECTED;
+   }
+
+   if (v & NVM_LVDERR) {
+   printf("Error in Block Erase - low-vol detected!\n");
+   flash_initiate_operation(NVMOP_NOP);
+   return ERR_NOT_ERASED;
+   }
+
+   /* disable flash write or erase operation */
+   writel(NVM_WREN, _regs_p->ctrl.clr);
+
+   return ERR_OK;
+}
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+   ulong sect_start, sect_end, flags;
+   int prot, sect;
+   int rc;
+
+   if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MCHP) {
+   printf("Can't erase unknown flash type %08lx - aborted\n",
+  info->flash_id);
+   return ERR_UNKNOWN_FLASH_VENDOR;
+   }
+
+   if ((s_first < 0) || (s_first > s_last)) {
+   printf("- no sectors to erase\n");
+   return ERR_INVAL;
+   }
+
+   prot = 0;
+   for (sect = s_first; sect <= s_last; ++sect) {
+   if (info->protect[sect])
+   prot++;
+   }
+
+   if (prot)
+   

Re: [U-Boot] [PATCH v2 1/4] drivers: musb-new: fix compilation error for MIPS.

[Purna Chandra Mandal]

On 03/07/2016 09:18 PM, Daniel Schwierzeck wrote:

> 2016-03-07 14:19 GMT+01:00 Purna Chandra Mandal <purna.man...@microchip.com>:
>> MIPS arch implements writes{b,w,l,q}, reads{b,w,l,q}
>> whereas other archs implement __raw version of them.
>> So defining macro writes{bwlq}() to __raw_writes{bwlq}()
>> (and similarly for reads{bwlq}) is not necessary for MIPS.
>>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>> ---
>>
>> Changes in v2: None
>>
>>  drivers/usb/musb-new/linux-compat.h | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/usb/musb-new/linux-compat.h 
>> b/drivers/usb/musb-new/linux-compat.h
>> index 46f83d9..9ac48c1 100644
>> --- a/drivers/usb/musb-new/linux-compat.h
>> +++ b/drivers/usb/musb-new/linux-compat.h
>> @@ -13,12 +13,14 @@
>> printf(fmt, ##args);\
>> ret_warn; })
>>
>> +#if !defined(CONFIG_MIPS)
>>  #define writesl(a, d, s) __raw_writesl((unsigned long)a, d, s)
>>  #define readsl(a, d, s) __raw_readsl((unsigned long)a, d, s)
>>  #define writesw(a, d, s) __raw_writesw((unsigned long)a, d, s)
>>  #define readsw(a, d, s) __raw_readsw((unsigned long)a, d, s)
>>  #define writesb(a, d, s) __raw_writesb((unsigned long)a, d, s)
>>  #define readsb(a, d, s) __raw_readsb((unsigned long)a, d, s)
>> +#endif
> I guess the current musb-new users are ARM boards only. Thus this
> should be moved to arch/arm/asm/io.h. Adding I/O primitives to a
> architecture-independent linux-compat.h was wrong from the beginning.

Makes sense! ARM Linux also defines readsl(or similar) to their __raw
version in arch/arm/include/asm/io.h file.

>>  #define device_init_wakeup(dev, a) do {} while (0)
>>
>> --
>> 1.8.3.1
>>
>

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Re: [U-Boot] [PATCH] MIPS: pic32mzdask: use CONFIG_USE_PRIVATE_LIBGCC=y

[Purna Chandra Mandal]

On 03/09/2016 04:00 PM, Daniel Schwierzeck wrote:

> MIPS EL boards should define CONFIG_USE_PRIVATE_LIBGCC=y to work
> with EB-only toolchains like the one from kernel.org. If one do
> not globally set CONFIG_USE_PRIVATE_LIBGCC=y, the build fails with:
>
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: 
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o):
>  compiled for a big endian system and target is little endian
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: 
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o):
>  endianness incompatible with that of the selected emulation
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: failed to merge 
> target specific data of file 
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o)
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: 
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o):
>  compiled for a big endian system and target is little endian
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: 
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o):
>  endianness incompatible with that of the selected emulation
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: failed to merge 
> target specific data of file 
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o)
> /work/git-trees/u-boot-mips/Makefile:1171: recipe for target 'u-boot' failed
>
> One example for a failing build is Travis CI.
>
> Signed-off-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com>

Reviewed-by: Purna Chandra Mandal <purna.man...@microchip.com>

> ---
>
>  configs/pic32mzdask_defconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
> index 169a2ac..4017983 100644
> --- a/configs/pic32mzdask_defconfig
> +++ b/configs/pic32mzdask_defconfig
> @@ -29,6 +29,6 @@ CONFIG_DM_ETH=y
>  CONFIG_PIC32_ETH=y
>  CONFIG_PINCTRL=y
>  # CONFIG_PINCTRL_FULL is not set
> -CONFIG_SYS_VSNPRINTF=y
> +CONFIG_USE_PRIVATE_LIBGCC=y
>  CONFIG_USE_TINY_PRINTF=y
>  CONFIG_CMD_DHRYSTONE=y

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[U-Boot] [PATCH v2 3/4] drivers: musb-new: Add USB DRC driver for Microchip PIC32 OTG controller.

[Purna Chandra Mandal]

This driver adds support of PIC32 MUSB OTG controller as dual role device.
It implements platform specific glue to reuse musb core.

Signed-off-by: Cristian Birsan <cristian.bir...@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---

Changes in v2: None

 drivers/usb/musb-new/Kconfig |   7 +
 drivers/usb/musb-new/Makefile|   1 +
 drivers/usb/musb-new/musb_core.c |   2 +-
 drivers/usb/musb-new/pic32.c | 294 +++
 4 files changed, 303 insertions(+), 1 deletion(-)
 create mode 100644 drivers/usb/musb-new/pic32.c

diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index 6a6cb93..4e8a543 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -15,6 +15,13 @@ config USB_MUSB_GADGET
 
 if USB_MUSB_HOST || USB_MUSB_GADGET
 
+config USB_MUSB_PIC32
+   bool "Enable Microchip PIC32 DRC USB controller"
+   depends on DM_USB && MACH_PIC32
+   help
+ Say y to enable PIC32 USB DRC controller support
+ if it is available on your Microchip PIC32 platform.
+
 config USB_MUSB_SUNXI
bool "Enable sunxi OTG / DRC USB controller"
depends on ARCH_SUNXI
diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile
index 072d516..df1c3c8 100644
--- a/drivers/usb/musb-new/Makefile
+++ b/drivers/usb/musb-new/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_USB_MUSB_HOST) += musb_host.o musb_core.o 
musb_uboot.o
 obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o
 obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o
 obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
+obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o
 obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
 
 ccflags-y := $(call cc-option,-Wno-unused-variable) \
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index a6d6af6..dd0443c 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -259,7 +259,7 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, 
const u8 *src)
}
 }
 
-#if !defined(CONFIG_USB_MUSB_AM35X)
+#if !defined(CONFIG_USB_MUSB_AM35X) && !defined(CONFIG_USB_MUSB_PIC32)
 /*
  * Unload an endpoint's FIFO
  */
diff --git a/drivers/usb/musb-new/pic32.c b/drivers/usb/musb-new/pic32.c
new file mode 100644
index 000..980a971
--- /dev/null
+++ b/drivers/usb/musb-new/pic32.c
@@ -0,0 +1,294 @@
+/*
+ * Microchip PIC32 MUSB "glue layer"
+ *
+ * Copyright (C) 2015, Microchip Technology Inc.
+ *  Cristian Birsan <cristian.bir...@microchip.com>
+ *  Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Based on the dsps "glue layer" code.
+ */
+
+#include 
+#include 
+#include "linux-compat.h"
+#include "musb_core.h"
+#include "musb_uboot.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PIC32_TX_EP_MASK   0x0f/* EP0 + 7 Tx EPs */
+#define PIC32_RX_EP_MASK   0x0e/* 7 Rx EPs */
+
+#define MUSB_SOFTRST   0x7f
+#define  MUSB_SOFTRST_NRST BIT(0)
+#define  MUSB_SOFTRST_NRSTXBIT(1)
+
+#define USBCRCON   0
+#define  USBCRCON_USBWKUPENBIT(0)  /* Enable Wakeup Interrupt */
+#define  USBCRCON_USBRIE   BIT(1)  /* Enable Remote resume Interrupt */
+#define  USBCRCON_USBIEBIT(2)  /* Enable USB General interrupt 
*/
+#define  USBCRCON_SENDMONENBIT(3)  /* Enable Session End VBUS monitoring */
+#define  USBCRCON_BSVALMONEN   BIT(4)  /* Enable B-Device VBUS monitoring */
+#define  USBCRCON_ASVALMONEN   BIT(5)  /* Enable A-Device VBUS monitoring */
+#define  USBCRCON_VBUSMONENBIT(6)  /* Enable VBUS monitoring */
+#define  USBCRCON_PHYIDEN  BIT(7)  /* PHY ID monitoring enable */
+#define  USBCRCON_USBIDVAL BIT(8)  /* USB ID value */
+#define  USBCRCON_USBIDOVENBIT(9)  /* USB ID override enable */
+#define  USBCRCON_USBWKBIT(24) /* USB Wakeup Status */
+#define  USBCRCON_USBRFBIT(25) /* USB Resume Status */
+#define  USBCRCON_USBIFBIT(26) /* USB General Interrupt Status 
*/
+
+static void __iomem *musb_glue;
+
+/* pic32_musb_disable - disable HDRC */
+static void pic32_musb_disable(struct musb *musb)
+{
+}
+
+/* pic32_musb_enable - enable HDRC */
+static int pic32_musb_enable(struct musb *musb)
+{
+   /* soft reset by NRSTx */
+   musb_writeb(musb->mregs, MUSB_SOFTRST, MUSB_SOFTRST_NRSTX);
+   /* set mode */
+   musb_platform_set_mode(musb, musb->board_mode);
+
+   return 0;
+}
+
+static irqreturn_t pic32_interrupt(int irq, void *hci)
+{
+   struct musb  *musb = hci;
+   irqreturn_t ret = IRQ_NONE;
+   u32 epintr, usbintr;
+
+   /* Get usb core interrupts */
+   musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
+   if (musb->int_usb)
+   musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
+
+   /* 

[U-Boot] [PATCH v2 4/4] board: pic32mzda: enable USB-host, USB-storage support.

[Purna Chandra Mandal]

Enable MUSB host and USB storage support for Microchip
PIC32MZ[DA] Starter Kit.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

Changes in v2:
- compilation fix in drivers/usb/musb-new/linux-compat.h seperated
- compilation fix in drivers/gadget/f_mass_storage.c seperated

 arch/mips/dts/pic32mzda.dtsi   | 10 ++
 arch/mips/dts/pic32mzda_sk.dts |  4 
 configs/pic32mzdask_defconfig  |  6 +-
 include/configs/pic32mzdask.h  |  7 +++
 4 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
index 7d180d9..57e4500 100644
--- a/arch/mips/dts/pic32mzda.dtsi
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -171,4 +171,14 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+   usb: musb@1f8e3000 {
+   compatible = "microchip,pic32mzda-usb";
+   reg = <0x1f8e3000 0x1000>,
+ <0x1f884000 0x1000>;
+   reg-names = "mc", "control";
+   interrupts = <132 IRQ_TYPE_EDGE_RISING>,
+<133 IRQ_TYPE_LEVEL_HIGH>;
+   status = "disabled";
+   };
 };
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
index e5ce0bd..0a7847e 100644
--- a/arch/mips/dts/pic32mzda_sk.dts
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -52,4 +52,8 @@
ethernet_phy: lan8740_phy@0 {
reg = <0>;
};
+};
+
+ {
+   status = "okay";
 };
\ No newline at end of file
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 1dbe1b5..544112f 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -12,6 +12,7 @@ CONFIG_SYS_PROMPT="dask # "
 CONFIG_LOOPW=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_RARP=y
@@ -28,6 +29,9 @@ CONFIG_DM_ETH=y
 CONFIG_PIC32_ETH=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_FULL is not set
-CONFIG_SYS_VSNPRINTF=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_STORAGE=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 2d35a0b..1d5be2b 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -117,6 +117,12 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_MMC
 
+/*--
+ * USB Configuration
+ */
+#define CONFIG_USB_MUSB_PIO_ONLY
+#define CONFIG_SYS_CACHELINE_SIZE  16
+
 /*---
  * File System Configuration
  */
@@ -167,6 +173,7 @@
 
 #define BOOT_TARGET_DEVICES(func)  \
func(MMC, mmc, 0)   \
+   func(USB, usb, 0)   \
func(DHCP, dhcp, na)
 
 #include 
-- 
1.8.3.1

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[U-Boot] [PATCH v2 2/4] gadget: f_mass_storge: fix compilation error for MIPS.

[Purna Chandra Mandal]

Compiling USB mass storage gadget for MIPS reports redefinition error.
--
drivers/usb/gadget/f_mass_storage.c:286:13: error: redefinition of 'set_bit'
 inline void set_bit(int nr, volatile void *addr)
 ^
In file included from include/linux/bitops.h:123:0,
 from include/common.h:20,
 from drivers/usb/gadget/f_mass_storage.c:245:
./arch/mips/include/asm/bitops.h:328:24: note: previous definition of 'set_bit' 
was here
 static __inline__ void set_bit(int nr, volatile void * addr)
^
drivers/usb/gadget/f_mass_storage.c:296:13: error: redefinition of 'clear_bit'
 inline void clear_bit(int nr, volatile void *addr)
 ^
In file included from include/linux/bitops.h:123:0,
 from include/common.h:20,
 from drivers/usb/gadget/f_mass_storage.c:245:
./arch/mips/include/asm/bitops.h:370:24: note: previous definition of 
'clear_bit' was here
 static __inline__ void clear_bit(int nr, volatile void * addr)
-
Fixed it by allowing default implementation of set_bit(), clear_bit()
for non MIPS.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---

Changes in v2: None

 drivers/usb/gadget/f_mass_storage.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/gadget/f_mass_storage.c 
b/drivers/usb/gadget/f_mass_storage.c
index 1ecb92a..8ca02f2 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -283,6 +283,7 @@ static const char fsg_string_interface[] = "Mass Storage";
 struct kref {int x; };
 struct completion {int x; };
 
+#if !defined(CONFIG_MIPS)
 inline void set_bit(int nr, volatile void *addr)
 {
int mask;
@@ -302,6 +303,7 @@ inline void clear_bit(int nr, volatile void *addr)
mask = 1 << (nr & 0x1f);
*a &= ~mask;
 }
+#endif
 
 struct fsg_dev;
 struct fsg_common;
-- 
1.8.3.1

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[U-Boot] [PATCH v2 1/4] drivers: musb-new: fix compilation error for MIPS.

[Purna Chandra Mandal]

MIPS arch implements writes{b,w,l,q}, reads{b,w,l,q}
whereas other archs implement __raw version of them.
So defining macro writes{bwlq}() to __raw_writes{bwlq}()
(and similarly for reads{bwlq}) is not necessary for MIPS.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---

Changes in v2: None

 drivers/usb/musb-new/linux-compat.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/musb-new/linux-compat.h 
b/drivers/usb/musb-new/linux-compat.h
index 46f83d9..9ac48c1 100644
--- a/drivers/usb/musb-new/linux-compat.h
+++ b/drivers/usb/musb-new/linux-compat.h
@@ -13,12 +13,14 @@
printf(fmt, ##args);\
ret_warn; })
 
+#if !defined(CONFIG_MIPS)
 #define writesl(a, d, s) __raw_writesl((unsigned long)a, d, s)
 #define readsl(a, d, s) __raw_readsl((unsigned long)a, d, s)
 #define writesw(a, d, s) __raw_writesw((unsigned long)a, d, s)
 #define readsw(a, d, s) __raw_readsw((unsigned long)a, d, s)
 #define writesb(a, d, s) __raw_writesb((unsigned long)a, d, s)
 #define readsb(a, d, s) __raw_readsb((unsigned long)a, d, s)
+#endif
 
 #define device_init_wakeup(dev, a) do {} while (0)
 
-- 
1.8.3.1

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[U-Boot] [PATCH v1 1/2] drivers: musb-new: Add USB DRC driver for Microchip PIC32 OTG controller.

[Purna Chandra Mandal]

From: Cristian Birsan <cristian.bir...@microchip.com>

This driver adds support of PIC32 MUSB OTG controller as dual role device.
It implements platform specific glue to reuse musb core.

Signed-off-by: Cristian Birsan <cristian.bir...@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---

 drivers/usb/gadget/f_mass_storage.c |   2 +
 drivers/usb/musb-new/Kconfig|   7 +
 drivers/usb/musb-new/Makefile   |   1 +
 drivers/usb/musb-new/linux-compat.h |   2 +
 drivers/usb/musb-new/musb_core.c|   2 +-
 drivers/usb/musb-new/pic32.c| 294 
 6 files changed, 307 insertions(+), 1 deletion(-)
 create mode 100644 drivers/usb/musb-new/pic32.c

diff --git a/drivers/usb/gadget/f_mass_storage.c 
b/drivers/usb/gadget/f_mass_storage.c
index 1ecb92a..8ca02f2 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -283,6 +283,7 @@ static const char fsg_string_interface[] = "Mass Storage";
 struct kref {int x; };
 struct completion {int x; };
 
+#if !defined(CONFIG_MIPS)
 inline void set_bit(int nr, volatile void *addr)
 {
int mask;
@@ -302,6 +303,7 @@ inline void clear_bit(int nr, volatile void *addr)
mask = 1 << (nr & 0x1f);
*a &= ~mask;
 }
+#endif
 
 struct fsg_dev;
 struct fsg_common;
diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index 6a6cb93..4e8a543 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -15,6 +15,13 @@ config USB_MUSB_GADGET
 
 if USB_MUSB_HOST || USB_MUSB_GADGET
 
+config USB_MUSB_PIC32
+   bool "Enable Microchip PIC32 DRC USB controller"
+   depends on DM_USB && MACH_PIC32
+   help
+ Say y to enable PIC32 USB DRC controller support
+ if it is available on your Microchip PIC32 platform.
+
 config USB_MUSB_SUNXI
bool "Enable sunxi OTG / DRC USB controller"
depends on ARCH_SUNXI
diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile
index 072d516..df1c3c8 100644
--- a/drivers/usb/musb-new/Makefile
+++ b/drivers/usb/musb-new/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_USB_MUSB_HOST) += musb_host.o musb_core.o 
musb_uboot.o
 obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o
 obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o
 obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
+obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o
 obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
 
 ccflags-y := $(call cc-option,-Wno-unused-variable) \
diff --git a/drivers/usb/musb-new/linux-compat.h 
b/drivers/usb/musb-new/linux-compat.h
index 46f83d9..9ac48c1 100644
--- a/drivers/usb/musb-new/linux-compat.h
+++ b/drivers/usb/musb-new/linux-compat.h
@@ -13,12 +13,14 @@
printf(fmt, ##args);\
ret_warn; })
 
+#if !defined(CONFIG_MIPS)
 #define writesl(a, d, s) __raw_writesl((unsigned long)a, d, s)
 #define readsl(a, d, s) __raw_readsl((unsigned long)a, d, s)
 #define writesw(a, d, s) __raw_writesw((unsigned long)a, d, s)
 #define readsw(a, d, s) __raw_readsw((unsigned long)a, d, s)
 #define writesb(a, d, s) __raw_writesb((unsigned long)a, d, s)
 #define readsb(a, d, s) __raw_readsb((unsigned long)a, d, s)
+#endif
 
 #define device_init_wakeup(dev, a) do {} while (0)
 
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index a6d6af6..dd0443c 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -259,7 +259,7 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, 
const u8 *src)
}
 }
 
-#if !defined(CONFIG_USB_MUSB_AM35X)
+#if !defined(CONFIG_USB_MUSB_AM35X) && !defined(CONFIG_USB_MUSB_PIC32)
 /*
  * Unload an endpoint's FIFO
  */
diff --git a/drivers/usb/musb-new/pic32.c b/drivers/usb/musb-new/pic32.c
new file mode 100644
index 000..980a971
--- /dev/null
+++ b/drivers/usb/musb-new/pic32.c
@@ -0,0 +1,294 @@
+/*
+ * Microchip PIC32 MUSB "glue layer"
+ *
+ * Copyright (C) 2015, Microchip Technology Inc.
+ *  Cristian Birsan <cristian.bir...@microchip.com>
+ *  Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Based on the dsps "glue layer" code.
+ */
+
+#include 
+#include 
+#include "linux-compat.h"
+#include "musb_core.h"
+#include "musb_uboot.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PIC32_TX_EP_MASK   0x0f/* EP0 + 7 Tx EPs */
+#define PIC32_RX_EP_MASK   0x0e/* 7 Rx EPs */
+
+#define MUSB_SOFTRST   0x7f
+#define  MUSB_SOFTRST_NRST BIT(0)
+#define  MUSB_SOFTRST_NRSTXBIT(1)
+
+#define USBCRCON   0
+#define  USBCRCON_USBWKUPENBIT(0)  /* Enable Wakeup Interrupt */
+#define  USBCRCON_USBRIE   BIT(1)  /* Enable Remote resume Interrupt */
+#define  USBCRCON_USBIEBIT(2)  /* Enable USB General interrupt 
*/
+#define  USBCR

[U-Boot] [PATCH v1 2/2] board: pic32mzda: enable USB-host, USB-storage support.

[Purna Chandra Mandal]

Enable MUSB host and USB storage support for Microchip
PIC32MZ[DA] Starter Kit.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

 arch/mips/dts/pic32mzda.dtsi   | 10 ++
 arch/mips/dts/pic32mzda_sk.dts |  4 
 configs/pic32mzdask_defconfig  |  6 +-
 include/configs/pic32mzdask.h  |  7 +++
 4 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
index 7d180d9..57e4500 100644
--- a/arch/mips/dts/pic32mzda.dtsi
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -171,4 +171,14 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+   usb: musb@1f8e3000 {
+   compatible = "microchip,pic32mzda-usb";
+   reg = <0x1f8e3000 0x1000>,
+ <0x1f884000 0x1000>;
+   reg-names = "mc", "control";
+   interrupts = <132 IRQ_TYPE_EDGE_RISING>,
+<133 IRQ_TYPE_LEVEL_HIGH>;
+   status = "disabled";
+   };
 };
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
index e5ce0bd..0a7847e 100644
--- a/arch/mips/dts/pic32mzda_sk.dts
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -52,4 +52,8 @@
ethernet_phy: lan8740_phy@0 {
reg = <0>;
};
+};
+
+ {
+   status = "okay";
 };
\ No newline at end of file
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 1dbe1b5..544112f 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -12,6 +12,7 @@ CONFIG_SYS_PROMPT="dask # "
 CONFIG_LOOPW=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_RARP=y
@@ -28,6 +29,9 @@ CONFIG_DM_ETH=y
 CONFIG_PIC32_ETH=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_FULL is not set
-CONFIG_SYS_VSNPRINTF=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_STORAGE=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 2d35a0b..1d5be2b 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -117,6 +117,12 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_MMC
 
+/*--
+ * USB Configuration
+ */
+#define CONFIG_USB_MUSB_PIO_ONLY
+#define CONFIG_SYS_CACHELINE_SIZE  16 /* usb gadget */
+
 /*---
  * File System Configuration
  */
@@ -167,6 +173,7 @@
 
 #define BOOT_TARGET_DEVICES(func)  \
func(MMC, mmc, 0)   \
+   func(USB, usb, 0)   \
func(DHCP, dhcp, na)
 
 #include 
-- 
1.8.3.1

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Re: [U-Boot] [PATCH v1 1/2] drivers: musb-new: Add USB DRC driver for Microchip PIC32 OTG controller.

[Purna Chandra Mandal]

On 02/09/2016 06:48 PM, Marek Vasut wrote:

> On Tuesday, February 09, 2016 at 01:02:49 PM, Purna Chandra Mandal wrote:
>> From: Cristian Birsan <cristian.bir...@microchip.com>
>>
>> This driver adds support of PIC32 MUSB OTG controller as dual role device.
>> It implements platform specific glue to reuse musb core.
>>
>> Signed-off-by: Cristian Birsan <cristian.bir...@microchip.com>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>> ---
>>
>>  drivers/usb/gadget/f_mass_storage.c |   2 +
>>  drivers/usb/musb-new/Kconfig|   7 +
>>  drivers/usb/musb-new/Makefile   |   1 +
>>  drivers/usb/musb-new/linux-compat.h |   2 +
>>  drivers/usb/musb-new/musb_core.c|   2 +-
>>  drivers/usb/musb-new/pic32.c| 294
>>  6 files changed, 307 insertions(+), 1
>> deletion(-)
>>  create mode 100644 drivers/usb/musb-new/pic32.c
>>
>> diff --git a/drivers/usb/gadget/f_mass_storage.c
>> b/drivers/usb/gadget/f_mass_storage.c index 1ecb92a..8ca02f2 100644
>> --- a/drivers/usb/gadget/f_mass_storage.c
>> +++ b/drivers/usb/gadget/f_mass_storage.c
>> @@ -283,6 +283,7 @@ static const char fsg_string_interface[] = "Mass
>> Storage"; struct kref {int x; };
>>  struct completion {int x; };
>>
>> +#if !defined(CONFIG_MIPS)
> Why is this change needed, endianness issues ?
>
> Also, you should put this into separate patch.

This is to fix compilation error with MIPS.
MIPS already implements these functions in "arch/mips/include/asm/bitops.h" 
(recently added).
I'll add this in separate patch.

>>  inline void set_bit(int nr, volatile void *addr)
>>  {
>>  int mask;
>> @@ -302,6 +303,7 @@ inline void clear_bit(int nr, volatile void *addr)
>>  mask = 1 << (nr & 0x1f);
>>  *a &= ~mask;
>>  }
>> +#endif
>>
>>  struct fsg_dev;
>>  struct fsg_common;
> [...]
>
>> diff --git a/drivers/usb/musb-new/linux-compat.h
>> b/drivers/usb/musb-new/linux-compat.h index 46f83d9..9ac48c1 100644
>> --- a/drivers/usb/musb-new/linux-compat.h
>> +++ b/drivers/usb/musb-new/linux-compat.h
>> @@ -13,12 +13,14 @@
>>  printf(fmt, ##args);\
>>  ret_warn; })
>>
>> +#if !defined(CONFIG_MIPS)
>>  #define writesl(a, d, s) __raw_writesl((unsigned long)a, d, s)
>>  #define readsl(a, d, s) __raw_readsl((unsigned long)a, d, s)
>>  #define writesw(a, d, s) __raw_writesw((unsigned long)a, d, s)
>>  #define readsw(a, d, s) __raw_readsw((unsigned long)a, d, s)
>>  #define writesb(a, d, s) __raw_writesb((unsigned long)a, d, s)
>>  #define readsb(a, d, s) __raw_readsb((unsigned long)a, d, s)
>> +#endif
> Why is this needed?

To fix compilation error with MIPS.
MIPS already implements these macros in "arch/mips/include/asm/io.h".

>>  #define device_init_wakeup(dev, a) do {} while (0)
>>
> [...]
>
>> +static int pic32_musb_set_mode(struct musb *musb, u8 mode)
>> +{
>> +struct device *dev = musb->controller;
>> +
>> +switch (mode) {
>> +case MUSB_HOST:
>> +clrsetbits_le32(musb_glue + USBCRCON,
>> +USBCRCON_USBIDVAL, USBCRCON_USBIDOVEN);
> Is pic32 mipsel ? Or is the core doing endian swapping ?
>
> I would expect _be32() stuff on mips.

In PIC32 MIPS is little-endian.

>> +break;
>> +case MUSB_PERIPHERAL:
>> +setbits_le32(musb_glue + USBCRCON,
>> + USBCRCON_USBIDVAL | USBCRCON_USBIDOVEN);
>> +break;
>> +case MUSB_OTG:
>> +dev_err(dev, "MUSB OTG mode enabled\n");
>> +break;
>> +default:
>> +dev_err(dev, "unsupported mode %d\n", mode);
>> +return -EINVAL;
>> +}
>> +
>> +return 0;
>> +}
> [...]
>
> Looks good otherwise.

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Re: [U-Boot] [PATCH v4 08/13] board: Add Microchip PIC32MZ[DA]-Starter-Kit board.

[Purna Chandra Mandal]

On 01/29/2016 08:42 PM, Daniel Schwierzeck wrote:

>
> Am 28.01.2016 um 11:00 schrieb Purna Chandra Mandal:
>> This adds support for Microchip PIC32MZ[DA] StarterKit board
>> based on a PIC32MZ[DA] family of microcontroller.
>>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
> Reviewed-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com>

Thanks Daniel.
Could you please apply these patches in your tree?

>>
>> ---
>>
>> Changes in v4:
>> - create defconfig by 'make savedefconfig'
>> - drop explicit SYS_BAUDRATE_TABLE in favor of default one
>>
>> Changes in v3:
>> - drop SKIP_LOWLEVEL_INIT, GBL_DATA_OFFSET from config header
>> - move CMD_MEMTEST, CMD_MEMINFO to defconfig
>> - increase SYS_MALLOC_F_LEN to 0x600
>> - use auto-generated defconfig - no hand edit
>>
>> Changes in v2:
>> - move CONFIG_SYS_TEXT_BASE (from board/*/config.mk) to 
>> include/configs/.h
>>
>>  arch/mips/dts/Makefile|  2 +-
>>  arch/mips/dts/pic32mzda_sk.dts| 38 ++
>>  arch/mips/mach-pic32/Kconfig  | 13 +
>>  board/microchip/pic32mzda/Kconfig | 13 +
>>  board/microchip/pic32mzda/MAINTAINERS |  6 +++
>>  board/microchip/pic32mzda/Makefile|  7 +++
>>  board/microchip/pic32mzda/README  | 22 +
>>  board/microchip/pic32mzda/pic32mzda.c | 31 
>>  configs/pic32mzdask_defconfig | 30 +++
>>  include/configs/pic32mzdask.h | 93 
>> +++
>>  10 files changed, 254 insertions(+), 1 deletion(-)
>>  create mode 100644 arch/mips/dts/pic32mzda_sk.dts
>>  create mode 100644 board/microchip/pic32mzda/Kconfig
>>  create mode 100644 board/microchip/pic32mzda/MAINTAINERS
>>  create mode 100644 board/microchip/pic32mzda/Makefile
>>  create mode 100644 board/microchip/pic32mzda/README
>>  create mode 100644 board/microchip/pic32mzda/pic32mzda.c
>>  create mode 100644 configs/pic32mzdask_defconfig
>>  create mode 100644 include/configs/pic32mzdask.h
>>
>> diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
>> index 47b6eb5..b513918 100644
>> --- a/arch/mips/dts/Makefile
>> +++ b/arch/mips/dts/Makefile
>> @@ -2,7 +2,7 @@
>>  # SPDX-License-Identifier:  GPL-2.0+
>>  #
>>  
>> -dtb-y +=
>> +dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
>>  
>>  targets += $(dtb-y)
>>  
>> diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
>> new file mode 100644
>> index 000..99e7f64
>> --- /dev/null
>> +++ b/arch/mips/dts/pic32mzda_sk.dts
>> @@ -0,0 +1,38 @@
>> +/*
>> + * Copyright (C) 2015 Purna Chandra Mandal, purna.man...@microchip.com
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "pic32mzda.dtsi"
>> +
>> +/ {
>> +model = "Microchip PIC32MZDASK";
>> +compatible = "microchip,pic32mzdask", "microchip,pic32mzda";
>> +
>> +aliases {
>> +console = 
>> +serial0 = 
>> +};
>> +
>> +chosen {
>> +stdout-path = "serial0:115200n8";
>> +};
>> +};
>> +
>> + {
>> +status = "okay";
>> +u-boot,dm-pre-reloc;
>> +};
>> +
>> + {
>> +status = "okay";
>> +u-boot,dm-pre-reloc;
>> +};
>> +
>> + {
>> +status = "okay";
>> +u-boot,dm-pre-reloc;
>> +};
>> diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig
>> index f636266..2e38bb7 100644
>> --- a/arch/mips/mach-pic32/Kconfig
>> +++ b/arch/mips/mach-pic32/Kconfig
>> @@ -19,4 +19,17 @@ config SOC_PIC32MZDA
>>  
>>  endchoice
>>  
>> +choice
>> +prompt "Board select"
>> +
>> +config TARGET_PIC32MZDASK
>> +bool "Microchip PIC32MZ[DA] Starter Kit"
>> +depends on SOC_PIC32MZDA
>> +help
>> +  This supports Microchip PIC32MZ[DA] Starter Kit.
>> +
>> +endchoice
>> +
>> +source "board/microchip/pic32mzda/Kconfig"
>> +
>>  endmenu
>> diff --git a/board/microchip/pic32mzda/Kconfig 
>> b/board/microchip/pic32mzda/Kconfig
>> new file mode 100644
>> index 000..8acb393
>> --- /dev/null
>> +++ b/board/microchip/pic32mzda/Kconfig
>> @@ -0,0 +1,13 @@
>> +
>> +if TARGET_PIC32MZDASK
>&g

[U-Boot] [PATCH v4 12/13] drivers: net: Add ethernet driver for Microchip PIC32.

[Purna Chandra Mandal]

This driver implements MAC and MII layer of the ethernet controller.
Network data transfer is handled by controller internal DMA engine.
Ethernet controller is configurable through device-tree file.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>


---

Changes in v4:
- drop ioremap() success check
- drop _dcache_flush/invalidate() helpers for flash/invalidate_dcache_range().

Changes in v3:
- merge wrappers with eth operation callbacks
- read phy address from device-tree
- rename functions (e.g. _eth_xyz() with pic32_eth_xyz())

Changes in v2: None

 drivers/net/Kconfig  |   8 +
 drivers/net/Makefile |   1 +
 drivers/net/pic32_eth.c  | 605 +++
 drivers/net/pic32_eth.h  | 164 +
 drivers/net/pic32_mdio.c | 121 ++
 5 files changed, 899 insertions(+)
 create mode 100644 drivers/net/pic32_eth.c
 create mode 100644 drivers/net/pic32_eth.h
 create mode 100644 drivers/net/pic32_mdio.c

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index de54ca8..1502f8e 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -109,4 +109,12 @@ config ZYNQ_GEM
help
  This MAC is present in Xilinx Zynq and ZynqMP SoCs.
 
+config PIC32_ETH
+   bool "Microchip PIC32 Ethernet Support"
+   depends on DM_ETH && MACH_PIC32
+   select PHYLIB
+   help
+ This driver implements 10/100 Mbps Ethernet and MAC layer for
+ Microchip PIC32 microcontrollers.
+
 endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 150470c..33a81ee 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -72,3 +72,4 @@ obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
 obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/
 obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
 obj-$(CONFIG_VSC9953) += vsc9953.o
+obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
diff --git a/drivers/net/pic32_eth.c b/drivers/net/pic32_eth.c
new file mode 100644
index 000..167af8b
--- /dev/null
+++ b/drivers/net/pic32_eth.c
@@ -0,0 +1,605 @@
+/*
+ * (c) 2015 Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pic32_eth.h"
+
+#define MAX_RX_BUF_SIZE1536
+#define MAX_RX_DESCR   PKTBUFSRX
+#define MAX_TX_DESCR   2
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pic32eth_dev {
+   struct eth_dma_desc rxd_ring[MAX_RX_DESCR];
+   struct eth_dma_desc txd_ring[MAX_TX_DESCR];
+   u32 rxd_idx; /* index of RX desc to read */
+   /* regs */
+   struct pic32_ectl_regs *ectl_regs;
+   struct pic32_emac_regs *emac_regs;
+   /* Phy */
+   struct phy_device *phydev;
+   phy_interface_t phyif;
+   u32 phy_addr;
+   struct gpio_desc rst_gpio;
+};
+
+void __weak board_netphy_reset(void *dev)
+{
+   struct pic32eth_dev *priv = dev;
+
+   if (!dm_gpio_is_valid(>rst_gpio))
+   return;
+
+   /* phy reset */
+   dm_gpio_set_value(>rst_gpio, 0);
+   udelay(300);
+   dm_gpio_set_value(>rst_gpio, 1);
+   udelay(300);
+}
+
+/* Initialize mii(MDIO) interface, discover which PHY is
+ * attached to the device, and configure it properly.
+ */
+static int pic32_mii_init(struct pic32eth_dev *priv)
+{
+   struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
+   struct pic32_emac_regs *emac_p = priv->emac_regs;
+
+   /* board phy reset */
+   board_netphy_reset(priv);
+
+   /* disable RX, TX & all transactions */
+   writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, _p->con1.clr);
+
+   /* wait till busy */
+   wait_for_bit(__func__, _p->stat.raw, ETHSTAT_BUSY, false,
+CONFIG_SYS_HZ, false);
+
+   /* turn controller ON to access PHY over MII */
+   writel(ETHCON_ON, _p->con1.set);
+
+   mdelay(10);
+
+   /* reset MAC */
+   writel(EMAC_SOFTRESET, _p->cfg1.set); /* reset assert */
+   mdelay(10);
+   writel(EMAC_SOFTRESET, _p->cfg1.clr); /* reset deassert */
+
+   /* initialize MDIO/MII */
+   if (priv->phyif == PHY_INTERFACE_MODE_RMII) {
+   writel(EMAC_RMII_RESET, _p->supp.set);
+   mdelay(10);
+   writel(EMAC_RMII_RESET, _p->supp.clr);
+   }
+
+   return pic32_mdio_init(PIC32_MDIO_NAME, (ulong)_p->mii);
+}
+
+static int pic32_phy_init(struct pic32eth_dev *priv, struct udevice *dev)
+{
+   struct mii_dev *mii;
+
+   mii = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
+
+   /* find & connect PHY */
+   priv->phydev = phy_connect(mii, priv->phy_addr,
+  dev, priv->phyif);
+   if (!priv->phydev) {
+   printf("%s: %s: Error, PHY connect\n", __FILE__, __func__);
+   return 0;
+   }
+
+   /* Wait for phy to

[U-Boot] [PATCH v4 13/13] board: Enable ethernet, tftpboot support to pic32mzdask board.

[Purna Chandra Mandal]

This adds ethernet, TFTP support for PIC32MZ[DA] Starter Kit. Also
custom environment variables/scripts are added to help boot from network.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

Changes in v4: None
Changes in v3: None
Changes in v2:
- replace unbounded loop with wait_for_bit()
- replace register access as readl/writel(base + offset)
- translate (dts provided) physical address to MIPS kseg1 address before use

 arch/mips/dts/pic32mzda.dtsi   | 10 ++
 arch/mips/dts/pic32mzda_sk.dts | 10 ++
 configs/pic32mzdask_defconfig  |  9 ++---
 include/configs/pic32mzdask.h  | 22 +-
 4 files changed, 47 insertions(+), 4 deletions(-)

diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
index f1894ec..7d180d9 100644
--- a/arch/mips/dts/pic32mzda.dtsi
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -161,4 +161,14 @@
bus-width = <4>;
status = "disabled";
};
+
+   ethernet: ethernet@1f882000 {
+   compatible = "microchip,pic32mzda-eth";
+   reg = <0x1f882000 0x1000>;
+   interrupts = <153 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < PB5CLK>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
 };
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
index f886a0f..e5ce0bd 100644
--- a/arch/mips/dts/pic32mzda_sk.dts
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -42,4 +42,14 @@
 
  {
status = "okay";
+};
+
+ {
+   reset-gpios = < 15 0>;
+   status = "okay";
+   phy-mode = "rmii";
+   phy-handle = <_phy>;
+   ethernet_phy: lan8740_phy@0 {
+   reg = <0>;
+   };
 };
\ No newline at end of file
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 55ba3f8..169a2ac 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -16,16 +16,19 @@ CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
+CONFIG_CMD_RARP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK=y
 CONFIG_DM_MMC=y
 CONFIG_PIC32_SDHCI=y
+CONFIG_DM_ETH=y
+CONFIG_PIC32_ETH=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_SYS_VSNPRINTF=y
 CONFIG_USE_TINY_PRINTF=y
-CONFIG_REGEX=y
 CONFIG_CMD_DHRYSTONE=y
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index b258038..3ea1194 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -73,6 +73,25 @@
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_CMDLINE_EDITING 1
 
+/*---
+ * Networking Configuration
+ */
+#define CONFIG_MII
+#define CONFIG_PHY_SMSC
+#define CONFIG_SYS_RX_ETH_BUFFER   8
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_ARP_TIMEOUT 500 /* millisec */
+
+#define CONFIG_CMD_MII
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
 /*
  * Handover flattened device tree (dtb file) to Linux kernel
  */
@@ -133,7 +152,8 @@
"fi; \0"
 
 #define BOOT_TARGET_DEVICES(func)  \
-   func(MMC, mmc, 0)
+   func(MMC, mmc, 0)   \
+   func(DHCP, dhcp, na)
 
 #include 
 
-- 
1.8.3.1

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[U-Boot] [PATCH v4 11/13] drivers: net: phy: add SMSC LAN8740 Phy support.

[Purna Chandra Mandal]

Add SMSC LAN8740 Phy support required for PIC32MZDA devices.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Reviewed-by: Tom Rini <tr...@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com>

---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/net/phy/smsc.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index bfd9815..34986a2 100644
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -69,11 +69,21 @@ static struct phy_driver lan8710_driver = {
.shutdown = _shutdown,
 };
 
+static struct phy_driver lan8740_driver = {
+   .name = "SMSC LAN8740",
+   .uid = 0x0007c110,
+   .mask = 0x0,
+   .features = PHY_BASIC_FEATURES,
+   .config = _config_aneg,
+   .startup = _startup,
+   .shutdown = _shutdown,
+};
 int phy_smsc_init(void)
 {
phy_register(_driver);
phy_register(_driver);
phy_register(_driver);
+   phy_register(_driver);
 
return 0;
 }
-- 
1.8.3.1

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[U-Boot] [PATCH v4 09/13] drivers: mmc: add driver for Microchip PIC32 SDHCI controller.

[Purna Chandra Mandal]

From: Andrei Pistirica <andrei.pistir...@microchip.com>

This driver implements platform specific glue and fixups for
PIC32 internal SDHCI controller.

Signed-off-by: Andrei Pistirica <andrei.pistir...@microchip.com>
Signed-off-by: Sandeep Sheriker Mallikarjun 
<sandeepsheriker.mallikar...@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Reviewed-by: Tom Rini <tr...@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com>

---

Changes in v4:
- update Kconfig help message
- add CD errata under SDHCI_QUIRK_NO_CD

Changes in v3:
- remove ofdata_to_platdata, and replace platdata with priv
- replace pic32_ioremap() with ioremap()

Changes in v2:
- drop sdhci shared bus configuration (for shared interrupt, clock pins)

 drivers/mmc/Kconfig   |  6 +
 drivers/mmc/Makefile  |  2 +-
 drivers/mmc/pic32_sdhci.c | 58 +++
 drivers/mmc/sdhci.c   |  7 ++
 4 files changed, 72 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mmc/pic32_sdhci.c

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index ceae7bc..9f4b766 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -31,4 +31,10 @@ config SH_SDHI
help
  Support for the on-chip SDHI host controller on SuperH/Renesas ARM 
SoCs platform
 
+config PIC32_SDHCI
+   bool "Microchip PIC32 on-chip SDHCI support"
+   depends on DM_MMC && MACH_PIC32
+   help
+ Support for Microchip PIC32 SDHCI controller.
+
 endmenu
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 5d35705..c9c3e3e 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -48,4 +48,4 @@ obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
 else
 obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
 endif
-
+obj-$(CONFIG_PIC32_SDHCI) += pic32_sdhci.o
diff --git a/drivers/mmc/pic32_sdhci.c b/drivers/mmc/pic32_sdhci.c
new file mode 100644
index 000..28da55d
--- /dev/null
+++ b/drivers/mmc/pic32_sdhci.c
@@ -0,0 +1,58 @@
+/*
+ * Support of SDHCI for Microchip PIC32 SoC.
+ *
+ * Copyright (C) 2015 Microchip Technology Inc.
+ * Andrei Pistirica <andrei.pistir...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int pic32_sdhci_probe(struct udevice *dev)
+{
+   struct sdhci_host *host = dev_get_priv(dev);
+   const void *fdt = gd->fdt_blob;
+   u32 f_min_max[2];
+   fdt_addr_t addr;
+   fdt_size_t size;
+   int ret;
+
+   addr = fdtdec_get_addr_size(fdt, dev->of_offset, "reg", );
+   if (addr == FDT_ADDR_T_NONE)
+   return -EINVAL;
+
+   host->ioaddr= ioremap(addr, size);
+   host->name  = (char *)dev->name;
+   host->quirks= SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_NO_CD;
+   host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+   "bus-width", 4);
+
+   ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+  "clock-freq-min-max", f_min_max, 2);
+   if (ret) {
+   printf("sdhci: clock-freq-min-max not found\n");
+   return ret;
+   }
+
+   return add_sdhci(host, f_min_max[1], f_min_max[0]);
+}
+
+static const struct udevice_id pic32_sdhci_ids[] = {
+   { .compatible = "microchip,pic32mzda-sdhci" },
+   { }
+};
+
+U_BOOT_DRIVER(pic32_sdhci_drv) = {
+   .name   = "pic32_sdhci",
+   .id = UCLASS_MMC,
+   .of_match   = pic32_sdhci_ids,
+   .probe  = pic32_sdhci_probe,
+   .priv_auto_alloc_size   = sizeof(struct sdhci_host),
+};
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 02d71b9..f77b707 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -443,6 +443,12 @@ static int sdhci_init(struct mmc *mmc)
sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 
if (host->quirks & SDHCI_QUIRK_NO_CD) {
+#if defined(CONFIG_PIC32_SDHCI)
+   /* PIC32 SDHCI CD errata:
+* - set CD_TEST and clear CD_TEST_INS bit
+*/
+   sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
+#else
unsigned int status;
 
sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
@@ -453,6 +459,7 @@ static int sdhci_init(struct mmc *mmc)
(!(status & SDHCI_CARD_STATE_STABLE)) ||
(!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
status = sdhci_readl(host, SDHCI_PRESENT_STATE);
+#endif
}
 
/* Enable only interrupts served by the SD controller */
-- 
1.8.3.1

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[U-Boot] [PATCH v4 06/13] drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.

[Purna Chandra Mandal]

This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy 
module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).

Signed-off-by: Paul Thacker <paul.thac...@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
Reviewed-by: Tom Rini <tr...@konsulko.com>
Reviewed-by: Simon Glass <s...@chromium.org>


---

Changes in v4: None
Changes in v3:
- annotating fixed table with const
- fix camel-case in ddr2 timing parameters
- fix cmd index parameter of host_load_cmd().
- fix compilation warning

Changes in v2:
- move ddr2 initialization from board/microchip/ to drivers/ddr/microchip

 arch/mips/mach-pic32/include/mach/ddr.h |  32 
 drivers/Makefile|   1 +
 drivers/ddr/microchip/Makefile  |   6 +
 drivers/ddr/microchip/ddr2.c| 278 
 drivers/ddr/microchip/ddr2_regs.h   | 148 +
 drivers/ddr/microchip/ddr2_timing.h |  65 
 6 files changed, 530 insertions(+)
 create mode 100644 arch/mips/mach-pic32/include/mach/ddr.h
 create mode 100644 drivers/ddr/microchip/Makefile
 create mode 100644 drivers/ddr/microchip/ddr2.c
 create mode 100644 drivers/ddr/microchip/ddr2_regs.h
 create mode 100644 drivers/ddr/microchip/ddr2_timing.h

diff --git a/arch/mips/mach-pic32/include/mach/ddr.h 
b/arch/mips/mach-pic32/include/mach/ddr.h
new file mode 100644
index 000..00abfa3
--- /dev/null
+++ b/arch/mips/mach-pic32/include/mach/ddr.h
@@ -0,0 +1,32 @@
+/*
+ * (c) 2015 Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#ifndef __MICROCHIP_PIC32_DDR_H
+#define __MICROCHIP_PIC32_DDR_H
+
+/* called by initdram() function */
+void ddr2_phy_init(void);
+void ddr2_ctrl_init(void);
+phys_size_t ddr2_calculate_size(void);
+
+/* Maximum number of agents */
+#define NUM_AGENTS 5
+
+/* Board can provide agent specific parameters for arbitration by
+ * filling struct ddr2_arbiter_params for all the agents and
+ * implementing board_get_ddr_arbiter_params() to return the filled
+ * structure.
+ */
+struct ddr2_arbiter_params {
+   u32 min_limit;  /* min bursts to execute per arbitration */
+   u32 req_period; /* request period threshold for accepted cmds */
+   u32 min_cmd_acpt; /* min number of accepted cmds */
+};
+
+const struct ddr2_arbiter_params *board_get_ddr_arbiter_params(void);
+
+#endif /* __MICROCHIP_PIC32_DDR_H */
diff --git a/drivers/Makefile b/drivers/Makefile
index 6294048..e7eab66 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -69,4 +69,5 @@ obj-y += soc/
 obj-$(CONFIG_REMOTEPROC) += remoteproc/
 obj-y += thermal/
 
+obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
 endif
diff --git a/drivers/ddr/microchip/Makefile b/drivers/ddr/microchip/Makefile
new file mode 100644
index 000..305c48b
--- /dev/null
+++ b/drivers/ddr/microchip/Makefile
@@ -0,0 +1,6 @@
+#
+# Copyright (C) 2015 Microchip Technology Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+obj-$(CONFIG_MACH_PIC32) += ddr2.o
diff --git a/drivers/ddr/microchip/ddr2.c b/drivers/ddr/microchip/ddr2.c
new file mode 100644
index 000..6056418
--- /dev/null
+++ b/drivers/ddr/microchip/ddr2.c
@@ -0,0 +1,278 @@
+/*
+ * (c) 2015 Paul Thacker <paul.thac...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "ddr2_regs.h"
+#include "ddr2_timing.h"
+
+/* init DDR2 Phy */
+void ddr2_phy_init(void)
+{
+   struct ddr2_phy_regs *ddr2_phy;
+   u32 pad_ctl;
+
+   ddr2_phy = ioremap(PIC32_DDR2P_BASE, sizeof(*ddr2_phy));
+
+   /* PHY_DLL_RECALIB */
+   writel(DELAY_START_VAL(3) | DISABLE_RECALIB(0) |
+  RECALIB_CNT(0x10), _phy->dll_recalib);
+
+   /* PHY_PAD_CTRL */
+   pad_ctl = ODT_SEL | ODT_EN | DRIVE_SEL(0) |
+ ODT_PULLDOWN(2) | ODT_PULLUP(3) |
+ EXTRA_OEN_CLK(0) | NOEXT_DLL |
+ DLR_DFT_WRCMD | HALF_RATE |
+ DRVSTR_PFET(0xe) | DRVSTR_NFET(0xe) |
+ RCVR_EN | PREAMBLE_DLY(2);
+   writel(pad_ctl, _phy->pad_ctrl);
+
+   /* SCL_CONFIG_0 */
+   writel(SCL_BURST8 | SCL_DDR_CONNECTED | SCL_RCAS_LAT(RL) |
+  SCL_ODTCSWW, _phy->scl_config_1);
+
+   /* SCL_CONFIG_1 */
+   writel(SCL_CSEN | SCL_WCAS_LAT(WL), _phy->scl_config_2);
+
+   /* SCL_LAT */
+   writel(SCL_CAPCLKDLY(3) | SCL_DDRCLKDLY(4), _phy->scl_latency);
+}
+
+/* start phy self calibration logic */
+static int ddr2_phy_calib_start(void)
+{
+   struct ddr2_phy_regs *ddr2_phy;
+
+   ddr2_phy = ioremap(PIC32_DDR2P_BASE, sizeof(*ddr2_phy));
+
+   /* DDR Phy SCL Start */
+   writel(SCL_START | SCL_EN, _phy->scl_start);
+
+   /* Wait for SCL for data by

[U-Boot] [PATCH v4 07/13] MIPS: Add support for Microchip PIC32MZ[DA] SoC family.

[Purna Chandra Mandal]

Add Microchip PIC32MZ[DA] SoC family support.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

Changes in v4:
- drop forcing DM_SERIAL, PIC32_SERIAL, PIC32_PINCTRL in mach-pic32/Kconfig
- drop extra include
- rename clock compatible to "pic32mzda-clk" from "pic32mzda_clk".
- fix typo 'clock-cells' to '#clock-cells'

Changes in v3:
- drop forcing CONFIG_MIPS_BOOT_* selection in mach-pic32/Kconfig
- indent assembly instructions in delay slot
- made GPIO-nodes child of pinctrl-node in devicetree
- replace pic32_ioremap() with ioremap()

Changes in v2:
- drop board_early_init_f
- use macro LEAF(), END() for lowlevel_init
- move initialization of board_init_f() argument to common start.S
- move initdram() from board/microchip/ to mach-pic32/cpu.c
- remove MIPS virtual address in favor physical one in dts file

 arch/mips/dts/pic32mzda.dtsi  | 153 ++
 arch/mips/mach-pic32/Kconfig  |  17 +++-
 arch/mips/mach-pic32/Makefile |   2 +-
 arch/mips/mach-pic32/cpu.c| 143 
 arch/mips/mach-pic32/include/mach/pic32.h |   3 +
 arch/mips/mach-pic32/lowlevel_init.S  |  27 ++
 arch/mips/mach-pic32/reset.c  |  36 +++
 7 files changed, 379 insertions(+), 2 deletions(-)
 create mode 100644 arch/mips/dts/pic32mzda.dtsi
 create mode 100644 arch/mips/mach-pic32/lowlevel_init.S
 create mode 100644 arch/mips/mach-pic32/reset.c

diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
new file mode 100644
index 000..c67cfa9
--- /dev/null
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2015 Microchip Technology, Inc.
+ * Purna Chandra Mandal, <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include "skeleton.dtsi"
+
+/ {
+   compatible = "microchip,pic32mzda", "microchip,pic32mz";
+
+   aliases {
+   gpio0 = 
+   gpio1 = 
+   gpio2 = 
+   gpio3 = 
+   gpio4 = 
+   gpio5 = 
+   gpio6 = 
+   gpio7 = 
+   gpio8 = 
+   gpio9 = 
+   };
+
+   cpus {
+   cpu@0 {
+   compatible = "mips,mips14kc";
+   };
+   };
+
+   clock: clk@1f801200 {
+   compatible = "microchip,pic32mzda-clk";
+   reg = <0x1f801200 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   uart1: serial@1f822000 {
+   compatible = "microchip,pic32mzda-uart";
+   reg = <0x1f822000 0x50>;
+   interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
+   status = "disabled";
+   clocks = < PB2CLK>;
+   };
+
+   uart2: serial@1f822200 {
+   compatible = "microchip,pic32mzda-uart";
+   reg = <0x1f822200 0x50>;
+   interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < PB2CLK>;
+   status = "disabled";
+   };
+
+   uart6: serial@1f822a00 {
+   compatible = "microchip,pic32mzda-uart";
+   reg = <0x1f822a00 0x50>;
+   interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < PB2CLK>;
+   status = "disabled";
+   };
+
+   evic: interrupt-controller@1f81 {
+   compatible = "microchip,pic32mzda-evic";
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   reg = <0x1f81 0x1000>;
+   };
+
+   pinctrl: pinctrl@1f801400 {
+   compatible = "microchip,pic32mzda-pinctrl";
+   reg = <0x1f801400 0x100>, /* in  */
+ <0x1f801500 0x200>, /* out */
+ <0x1f86 0xa00>; /* port */
+   reg-names = "ppsin","ppsout","port";
+   status = "disabled";
+
+   ranges = <0 0x1f86 0xa00>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   gpioA: gpio0@0 {
+   compatible = "microchip,pic32mzda-gpio";
+   reg = <0x000 0x48>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
+   gpioB: gpio1@100 {
+   compatible = "microchip,pic32mzda-gpio";
+   reg = <0x100 0x48>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
+   gpioC: gpio2@200 {
+   compatible = 

[U-Boot] [PATCH v4 08/13] board: Add Microchip PIC32MZ[DA]-Starter-Kit board.

[Purna Chandra Mandal]

This adds support for Microchip PIC32MZ[DA] StarterKit board
based on a PIC32MZ[DA] family of microcontroller.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>


---

Changes in v4:
- create defconfig by 'make savedefconfig'
- drop explicit SYS_BAUDRATE_TABLE in favor of default one

Changes in v3:
- drop SKIP_LOWLEVEL_INIT, GBL_DATA_OFFSET from config header
- move CMD_MEMTEST, CMD_MEMINFO to defconfig
- increase SYS_MALLOC_F_LEN to 0x600
- use auto-generated defconfig - no hand edit

Changes in v2:
- move CONFIG_SYS_TEXT_BASE (from board/*/config.mk) to 
include/configs/.h

 arch/mips/dts/Makefile|  2 +-
 arch/mips/dts/pic32mzda_sk.dts| 38 ++
 arch/mips/mach-pic32/Kconfig  | 13 +
 board/microchip/pic32mzda/Kconfig | 13 +
 board/microchip/pic32mzda/MAINTAINERS |  6 +++
 board/microchip/pic32mzda/Makefile|  7 +++
 board/microchip/pic32mzda/README  | 22 +
 board/microchip/pic32mzda/pic32mzda.c | 31 
 configs/pic32mzdask_defconfig | 30 +++
 include/configs/pic32mzdask.h | 93 +++
 10 files changed, 254 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/dts/pic32mzda_sk.dts
 create mode 100644 board/microchip/pic32mzda/Kconfig
 create mode 100644 board/microchip/pic32mzda/MAINTAINERS
 create mode 100644 board/microchip/pic32mzda/Makefile
 create mode 100644 board/microchip/pic32mzda/README
 create mode 100644 board/microchip/pic32mzda/pic32mzda.c
 create mode 100644 configs/pic32mzdask_defconfig
 create mode 100644 include/configs/pic32mzdask.h

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 47b6eb5..b513918 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-dtb-y +=
+dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
new file mode 100644
index 000..99e7f64
--- /dev/null
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2015 Purna Chandra Mandal, purna.man...@microchip.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "pic32mzda.dtsi"
+
+/ {
+   model = "Microchip PIC32MZDASK";
+   compatible = "microchip,pic32mzdask", "microchip,pic32mzda";
+
+   aliases {
+   console = 
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+ {
+   status = "okay";
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   status = "okay";
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   status = "okay";
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig
index f636266..2e38bb7 100644
--- a/arch/mips/mach-pic32/Kconfig
+++ b/arch/mips/mach-pic32/Kconfig
@@ -19,4 +19,17 @@ config SOC_PIC32MZDA
 
 endchoice
 
+choice
+   prompt "Board select"
+
+config TARGET_PIC32MZDASK
+   bool "Microchip PIC32MZ[DA] Starter Kit"
+   depends on SOC_PIC32MZDA
+   help
+ This supports Microchip PIC32MZ[DA] Starter Kit.
+
+endchoice
+
+source "board/microchip/pic32mzda/Kconfig"
+
 endmenu
diff --git a/board/microchip/pic32mzda/Kconfig 
b/board/microchip/pic32mzda/Kconfig
new file mode 100644
index 000..8acb393
--- /dev/null
+++ b/board/microchip/pic32mzda/Kconfig
@@ -0,0 +1,13 @@
+
+if TARGET_PIC32MZDASK
+
+config SYS_BOARD
+   default "pic32mzda"
+
+config SYS_VENDOR
+   default "microchip"
+
+config SYS_CONFIG_NAME
+   default "pic32mzdask"
+
+endif
diff --git a/board/microchip/pic32mzda/MAINTAINERS 
b/board/microchip/pic32mzda/MAINTAINERS
new file mode 100644
index 000..c934f1a
--- /dev/null
+++ b/board/microchip/pic32mzda/MAINTAINERS
@@ -0,0 +1,6 @@
+PIC32MZDASK BOARD
+M: Purna Chandra Mandal <purna.man...@microchip.com>
+S: Maintained
+F: board/microchip/pic32mzda/
+F: include/configs/pic32mzdask.h
+F: configs/pic32mzdask_defconfig
diff --git a/board/microchip/pic32mzda/Makefile 
b/board/microchip/pic32mzda/Makefile
new file mode 100644
index 000..3629530
--- /dev/null
+++ b/board/microchip/pic32mzda/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015
+# Purna Chandra Mandal, purna.man...@microchip.com.
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+obj-y := pic32mzda.o
diff --git a/board/microchip/pic32mzda/README b/board/microchip/pic32mzda/README
new file mode 100644
index 000..91d16ab
--- /dev/null
+++ b/board/microchip/pic32mzda/README
@@ -0,0 +1,22 @@
+/*
+ * (c) 2015 Purna Chandra Mandal <purna.man...@microchip.com>
+ */
+
+PIC32MZ[DA] Starter Kit
+
+PIC32MZ[DA] Starter Kit is based on PIC32MZ[DA] family of mic

[U-Boot] [PATCH v4 04/13] drivers: gpio: add driver for Microchip PIC32 GPIO controller.

[Purna Chandra Mandal]

In PIC32 GPIO controller is part of PIC32 pin controller.
PIC32 has ten independently programmable ports and each with multiple pins.
Each of these pins can be configured and used as GPIO, provided they
are not in use for other peripherals.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Reviewed-by: Tom Rini <tr...@konsulko.com>
Reviewed-by: Simon Glass <s...@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com>

---

Changes in v4:
- update kconfig dependency on DM && MACH_PIC32, and default y
- drop ioremap failure check
- return -EPERM if the pin is found in analog mode
- drop desc->offset setting in _gpio_xlate()

Changes in v3:
- add check on dev_get_addr()

Changes in v2: None

 drivers/gpio/Kconfig  |   7 ++
 drivers/gpio/Makefile |   2 +-
 drivers/gpio/pic32_gpio.c | 174 ++
 3 files changed, 182 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpio/pic32_gpio.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index e60e9fd..845dc72 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -83,4 +83,11 @@ config VYBRID_GPIO
help
  Say yes here to support Vybrid vf610 GPIOs.
 
+config PIC32_GPIO
+   bool "Microchip PIC32 GPIO driver"
+   depends on DM_GPIO && MACH_PIC32
+   default y
+   help
+ Say yes here to support Microchip PIC32 GPIOs.
+
 endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fb4fd25..845a6d4 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -46,4 +46,4 @@ obj-$(CONFIG_STM32_GPIO)  += stm32_gpio.o
 obj-$(CONFIG_ZYNQ_GPIO)+= zynq_gpio.o
 obj-$(CONFIG_VYBRID_GPIO)  += vybrid_gpio.o
 obj-$(CONFIG_HIKEY_GPIO)   += hi6220_gpio.o
-
+obj-$(CONFIG_PIC32_GPIO)   += pic32_gpio.o
diff --git a/drivers/gpio/pic32_gpio.c b/drivers/gpio/pic32_gpio.c
new file mode 100644
index 000..499b4fa
--- /dev/null
+++ b/drivers/gpio/pic32_gpio.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2015 Microchip Technology Inc
+ * Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Peripheral Pin Control */
+struct pic32_reg_port {
+   struct pic32_reg_atomic ansel;
+   struct pic32_reg_atomic tris;
+   struct pic32_reg_atomic port;
+   struct pic32_reg_atomic lat;
+   struct pic32_reg_atomic open_drain;
+   struct pic32_reg_atomic cnpu;
+   struct pic32_reg_atomic cnpd;
+   struct pic32_reg_atomic cncon;
+};
+
+enum {
+   MICROCHIP_GPIO_DIR_OUT,
+   MICROCHIP_GPIO_DIR_IN,
+   MICROCHIP_GPIOS_PER_BANK = 16,
+};
+
+struct pic32_gpio_priv {
+   struct pic32_reg_port *regs;
+   char name[2];
+};
+
+static int pic32_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+   struct pic32_gpio_priv *priv = dev_get_priv(dev);
+
+   return !!(readl(>regs->port.raw) & BIT(offset));
+}
+
+static int pic32_gpio_set_value(struct udevice *dev, unsigned offset,
+   int value)
+{
+   struct pic32_gpio_priv *priv = dev_get_priv(dev);
+   int mask = BIT(offset);
+
+   if (value)
+   writel(mask, >regs->port.set);
+   else
+   writel(mask, >regs->port.clr);
+
+   return 0;
+}
+
+static int pic32_gpio_direction(struct udevice *dev, unsigned offset)
+{
+   struct pic32_gpio_priv *priv = dev_get_priv(dev);
+
+   /* pin in analog mode ? */
+   if (readl(>regs->ansel.raw) & BIT(offset))
+   return -EPERM;
+
+   if (readl(>regs->tris.raw) & BIT(offset))
+   return MICROCHIP_GPIO_DIR_IN;
+   else
+   return MICROCHIP_GPIO_DIR_OUT;
+}
+
+static int pic32_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+   struct pic32_gpio_priv *priv = dev_get_priv(dev);
+   int mask = BIT(offset);
+
+   writel(mask, >regs->ansel.clr);
+   writel(mask, >regs->tris.set);
+
+   return 0;
+}
+
+static int pic32_gpio_direction_output(struct udevice *dev,
+  unsigned offset, int value)
+{
+   struct pic32_gpio_priv *priv = dev_get_priv(dev);
+   int mask = BIT(offset);
+
+   writel(mask, >regs->ansel.clr);
+   writel(mask, >regs->tris.clr);
+
+   pic32_gpio_set_value(dev, offset, value);
+   return 0;
+}
+
+static int pic32_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+   struct fdtdec_phandle_args *args)
+{
+   desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+   return 0;
+}
+
+static int pic32_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+   int ret = GPIOF

[U-Boot] [PATCH v4 10/13] board: add SDHCI support for PIC32MZDASK board.

[Purna Chandra Mandal]

Enable MMC, SDHCI, FAT_FS support for PIC32MZ[DA] StarterKit.
Also add custom scripts, rules to boot Linux from microSD card.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

Changes in v4: None
Changes in v3:
- use distro boot commands from config_distro_bootcmd.h
- separate old booting logic as legacy_bootcmd

Changes in v2:
- drop shared bus (shared pin selection) configuration.

 arch/mips/dts/pic32mzda.dtsi   | 11 
 arch/mips/dts/pic32mzda_sk.dts |  7 +
 configs/pic32mzdask_defconfig  |  3 ++-
 include/configs/pic32mzdask.h  | 59 --
 4 files changed, 77 insertions(+), 3 deletions(-)

diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
index c67cfa9..f1894ec 100644
--- a/arch/mips/dts/pic32mzda.dtsi
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -150,4 +150,15 @@
#gpio-cells = <2>;
};
};
+
+   sdhci: sdhci@1f8ec000 {
+   compatible = "microchip,pic32mzda-sdhci";
+   reg = <0x1f8ec000 0x100>;
+   interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < REF4CLK>, < PB5CLK>;
+   clock-names = "base_clk", "sys_clk";
+   clock-freq-min-max = <2500>,<2500>;
+   bus-width = <4>;
+   status = "disabled";
+   };
 };
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
index 99e7f64..f886a0f 100644
--- a/arch/mips/dts/pic32mzda_sk.dts
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -23,6 +23,9 @@
 };
 
  {
+   microchip,refo2-frequency = <5000>;
+   microchip,refo4-frequency = <2500>;
+   microchip,refo5-frequency = <4000>;
status = "okay";
u-boot,dm-pre-reloc;
 };
@@ -36,3 +39,7 @@
status = "okay";
u-boot,dm-pre-reloc;
 };
+
+ {
+   status = "okay";
+};
\ No newline at end of file
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 1c968fc..55ba3f8 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="dask # "
 # CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_SAVEENV is not set
 CONFIG_LOOPW=y
 CONFIG_CMD_MEMTEST=y
@@ -22,6 +21,8 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_TIME=y
 CONFIG_OF_EMBED=y
 CONFIG_CLK=y
+CONFIG_DM_MMC=y
+CONFIG_PIC32_SDHCI=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_SYS_VSNPRINTF=y
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 5ba2a19..b258038 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -46,6 +46,7 @@
 
 #define CONFIG_SYS_LOAD_ADDR   0x8850 /* default load address */
 #define CONFIG_SYS_ENV_ADDR0x8830
+#define CONFIG_SYS_FDT_ADDR0x89d0
 
 /* Memory Test */
 #define CONFIG_SYS_MEMTEST_START   0x8800
@@ -77,6 +78,33 @@
  */
 #define CONFIG_OF_LIBFDT   1
 
+/*---
+ * SDHC Configuration
+ */
+#define CONFIG_SDHCI
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_MMC
+
+/*---
+ * File System Configuration
+ */
+/* FAT FS */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_FS_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_PART
+#define CONFIG_CMD_FAT
+
+/* EXT4 FS */
+#define CONFIG_FS_EXT4
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+
 /* -
  * Environment
  */
@@ -87,7 +115,34 @@
  * Board boot configuration
  */
 #define CONFIG_TIMESTAMP   /* Print image info with timestamp */
-#define CONFIG_BOOTDELAY   5 /* autoboot after X seconds */
-#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTDELAY   5
+
+#define MEM_LAYOUT_ENV_SETTINGS\
+   "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0"   \
+   "fdt_addr_r="__stringify(CONFIG_SYS_FDT_ADDR)"\0"   \
+   "scriptaddr="__stringify(CONFIG_SYS_ENV_ADDR)"\0"
+
+#define CONFIG_LEGACY_BOOTCMD_ENV  \
+   "legacy_bootcmd= "  \
+   "if load mmc 0 ${scriptaddr} uEnv.txt; then "   \
+   "env import -tr ${scriptaddr} ${filesize}; "\
+   "if test -n \"${bootcmd_uenv}\" ; then "\
+   &qu

[U-Boot] [PATCH v4 00/13] Initial Microchip PIC32MZ[DA] Support

[Purna Chandra Mandal]

This patch series adds support for Microchip PIC32MZ[DA] MIPS microcontroller 
platform.
All drivers required to boot from MMC uSD card and network are included in it; 
clock,
pinctrl, gpio, DDR2, serial, SDHCI, ethernet.
This series been tested on PIC32MZ[DA] Starter Kit.

This series is generated on u-boot/master branch. A tree with these changes is 
available
at [1].

[1] https://github.com/purna-mandal/u-boot/tree/pic32-upstream-v4
[0] https://github.com/purna-mandal/u-boot/tree/pic32-upstream-v3

Changes in v4:
- update kconfig dependency and default selection
- drop ioremap failure check
- gpio: return -EPERM if the pin is found in analog mode
- gpio: drop desc->offset setting in _gpio_xlate()
- serial: update comment for _pending_input().
- serial: rename UART_RX_OERR to UART_RX_OVER.
- serial: DEBUG_UART_PIC32 now depends on PIC32_SERIAL
- serial: extract clock-id from device-tree
- drop forcing DM_SERIAL, PIC32_SERIAL, PIC32_PINCTRL in mach-pic32/Kconfig
- drop extra includes
- rename clock compatible to "pic32mzda-clk" from "pic32mzda_clk".
- fix typo 'clock-cells' to '#clock-cells'
- create defconfig by 'make savedefconfig'
- drop explicit SYS_BAUDRATE_TABLE in favor of default one
- add CD errata under SDHCI_QUIRK_NO_CD
- eth: drop _dcache_flush/invalidate() helpers for 
flush/invalidate_dcache_range().

Changes in v3:
- drop empty choice in mach-pic32/Kconfig
- add pic32_get_syscfg_base()
- rename clk-pic32.c to clk_pic32.c
- update clock binding documentation
- replace pic32_ioremap() with ioremap()
- separate MPLL initialization constants
- read register base from device-tree
- add/update comments to explain how pinctrl'r works.
- replace pic32_ioremap() with ioremap().
- add check on dev_get_addr()
- remove ofdata_to_platdata, and replace platdata with priv
- remove special handling of '\r' as being handled by serial-uclass
- remove loop to wait for space in tx buffer before pumping char
- annotating fixed table with const
- fix camel-case in ddr2 timing parameters
- fix cmd index parameter of host_load_cmd().
- fix compilation warning
- drop forcing CONFIG_MIPS_BOOT_* selection in mach-pic32/Kconfig
- indent assembly instructions in delay slot
- made GPIO-nodes child of pinctrl-node in devicetree
- replace pic32_ioremap() with ioremap()
- drop SKIP_LOWLEVEL_INIT, GBL_DATA_OFFSET from config header
- move CMD_MEMTEST, CMD_MEMINFO to defconfig
- increase SYS_MALLOC_F_LEN to 0x600
- use auto-generated defconfig - no hand edit
- remove ofdata_to_platdata, and replace platdata with priv
- replace pic32_ioremap() with ioremap()
- use distro boot commands from config_distro_bootcmd.h
- separate old booting logic as legacy_bootcmd
- merge wrappers with eth operation callbacks
- read phy address from device-tree
- rename functions (e.g. _eth_xyz() with pic32_eth_xyz())

Changes in v2:
- move PIC32 specific headers to arch/mips/mach-pic32/include/mach/
- define register-base as physical address
- drop CONFIG_PIC32_SUPPORTS_FDT_BOOT
- add mpll get clock rate
- add pinconf routine for configuring pin property
- fix missing/corrupted chars during baud rate change
- remove loop until any char is avaialbale in getc()
- move ddr2 initialization from board/microchip/ to drivers/ddr/microchip
- drop board_early_init_f
- use macro LEAF(), END() for lowlevel_init
- move initialization of board_init_f() argument to common start.S
- move initdram() from board/microchip/ to mach-pic32/cpu.c
- remove MIPS virtual address in favor physical one in dts file
- move CONFIG_SYS_TEXT_BASE (from board/*/config.mk) to 
include/configs/.h
- drop sdhci shared bus configuration (for shared interrupt, clock pins)
- drop shared bus (shared pin selection) configuration.
- replace unbounded loop with wait_for_bit()
- replace register access as readl/writel(base + offset)
- translate (dts provided) physical address to MIPS kseg1 address before use

Andrei Pistirica (1):
  drivers: mmc: add driver for Microchip PIC32 SDHCI controller.

Paul Thacker (1):
  drivers: serial: add driver for Microchip PIC32 UART controller.

Purna Chandra Mandal (11):
  MIPS: initial infrastructure for Microchip PIC32 architecture
  drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.
  drivers: pinctrl: Add pinctrl driver for Microchip PIC32.
  drivers: gpio: add driver for Microchip PIC32 GPIO controller.
  drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.
  MIPS: Add support for Microchip PIC32MZ[DA] SoC family.
  board: Add Microchip PIC32MZ[DA]-Starter-Kit board.
  board: add SDHCI support for PIC32MZDASK board.
  drivers: net: phy: add SMSC LAN8740 Phy support.
  drivers: net: Add ethernet driver for Microchip PIC32.
  board: Enable ethernet, tftpboot support to pic32mzdask board.

 arch/mips/Kconfig  |   6 +
 arch/mips/Makefile |   1 +
 arch/mips/dts/Makefile |   2 +-
 arch/

[U-Boot] [PATCH v4 01/13] MIPS: initial infrastructure for Microchip PIC32 architecture

[Purna Chandra Mandal]

Create initial directory, Kconfigs needed for PIC32 architecture
support. Also add PIC32 specific register definition required for drivers.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
Reviewed-by: Tom Rini <tr...@konsulko.com>

---

Changes in v4: None
Changes in v3:
- drop empty choice in mach-pic32/Kconfig
- add pic32_get_syscfg_base()

Changes in v2:
- move PIC32 specific headers to arch/mips/mach-pic32/include/mach/
- define register-base as physical address
- drop CONFIG_PIC32_SUPPORTS_FDT_BOOT

 arch/mips/Kconfig |  6 +++
 arch/mips/Makefile|  1 +
 arch/mips/mach-pic32/Kconfig  |  7 +++
 arch/mips/mach-pic32/Makefile |  7 +++
 arch/mips/mach-pic32/cpu.c| 13 ++
 arch/mips/mach-pic32/include/mach/pic32.h | 76 +++
 6 files changed, 110 insertions(+)
 create mode 100644 arch/mips/mach-pic32/Kconfig
 create mode 100644 arch/mips/mach-pic32/Makefile
 create mode 100644 arch/mips/mach-pic32/cpu.c
 create mode 100644 arch/mips/mach-pic32/include/mach/pic32.h

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1b39c4c..380ed81 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -54,6 +54,11 @@ config TARGET_PB1X00
select SYS_MIPS_CACHE_INIT_RAM_LOAD
select MIPS_TUNE_4KC
 
+config MACH_PIC32
+   bool "Support Microchip PIC32"
+   select OF_CONTROL
+   select DM
+
 endchoice
 
 source "board/dbau1x00/Kconfig"
@@ -61,6 +66,7 @@ source "board/imgtec/malta/Kconfig"
 source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
+source "arch/mips/mach-pic32/Kconfig"
 
 if MIPS
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 2133e7e..aec5a15 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/
 libs-y += arch/mips/lib/
 
 machine-$(CONFIG_SOC_AU1X00) += au1x00
+machine-$(CONFIG_MACH_PIC32) += pic32
 
 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
 libs-y += $(machdirs)
diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig
new file mode 100644
index 000..c1cc5e3
--- /dev/null
+++ b/arch/mips/mach-pic32/Kconfig
@@ -0,0 +1,7 @@
+menu "Microchip PIC32 platforms"
+   depends on MACH_PIC32
+
+config SYS_SOC
+   default "none"
+
+endmenu
diff --git a/arch/mips/mach-pic32/Makefile b/arch/mips/mach-pic32/Makefile
new file mode 100644
index 000..cb42607
--- /dev/null
+++ b/arch/mips/mach-pic32/Makefile
@@ -0,0 +1,7 @@
+# (C) Copyright 2015
+# Purna Chandra Mandal, purna.man...@microchip.com.
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+
+obj-y = cpu.o
diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c
new file mode 100644
index 000..58fd3ab
--- /dev/null
+++ b/arch/mips/mach-pic32/cpu.c
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2015
+ * Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+#include 
+
+phys_size_t initdram(int board_type)
+{
+   return 0;
+}
diff --git a/arch/mips/mach-pic32/include/mach/pic32.h 
b/arch/mips/mach-pic32/include/mach/pic32.h
new file mode 100644
index 000..7e41810
--- /dev/null
+++ b/arch/mips/mach-pic32/include/mach/pic32.h
@@ -0,0 +1,76 @@
+/*
+ * (c) 2015 Paul Thacker <paul.thac...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#ifndef __PIC32_REGS_H__
+#define __PIC32_REGS_H__
+
+#include 
+
+/* System Configuration */
+#define PIC32_CFG_BASE 0x1f80
+
+/* System config register offsets */
+#define CFGCON 0x
+#define DEVID  0x0020
+#define SYSKEY 0x0030
+#define PMD1   0x0040
+#define PMD7   0x00a0
+#define CFGEBIA0x00c0
+#define CFGEBIC0x00d0
+#define CFGPG  0x00e0
+#define CFGMPLL0x0100
+
+/* Non Volatile Memory (NOR flash) */
+#define PIC32_NVM_BASE (PIC32_CFG_BASE + 0x0600)
+/* Oscillator Configuration */
+#define PIC32_OSC_BASE (PIC32_CFG_BASE + 0x1200)
+/* Peripheral Pin Select Input */
+#define PPS_IN_BASE0x1f801400
+/* Peripheral Pin Select Output */
+#define PPS_OUT_BASE   0x1f801500
+/* Pin Config */
+#define PINCTRL_BASE   0x1f86
+
+/* USB Core */
+#define PIC32_USB_CORE_BASE0x1f8e3000
+#define PIC32_USB_CTRL_BASE0x1f884000
+
+/* SPI1-SPI6 */
+#define PIC32_SPI1_BASE0x1f821000
+
+/* Prefetch Module */
+#define PREFETCH_BASE  0x1f8e
+
+/* DDR2 Controller */
+#define PIC32_DDR2C_BASE   0x1f8e8000
+
+/* DDR2 PHY */
+#define PIC32_DDR2P_BASE   0x1f8e9100
+
+/* EBI */
+#define PIC32_EBI_BASE 0x1f8e1000
+
+/* SQI */
+#define PIC32_SQI_BASE 0x1f8e2000
+
+struct p

[U-Boot] [PATCH v4 03/13] drivers: pinctrl: Add pinctrl driver for Microchip PIC32.

[Purna Chandra Mandal]

In PIC32 pin-controller is a combined gpio-controller, pin-mux and
pin-config module. Remappable peripherals are assigned pins through
per-pin based muxing logic. And pin configuration are performed on
specific port registers which are shared along with gpio controller.
Note, non-remappable peripherals have default pins assigned thus
require no muxing.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Reviewed-by: Tom Rini <tr...@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
Reviewed-by: Simon Glass <s...@chromium.org>


---

Changes in v4:
- update commit message
- update kconfig dependency on (DM && MACH_PIC32) and default y

Changes in v3:
- read register base from device-tree
- add/update comments to explain how pinctrl'r works.
- replace pic32_ioremap() with ioremap().

Changes in v2:
- add pinconf routine for configuring pin property

 drivers/pinctrl/Kconfig |  10 ++
 drivers/pinctrl/Makefile|   1 +
 drivers/pinctrl/pinctrl_pic32.c | 363 
 3 files changed, 374 insertions(+)
 create mode 100644 drivers/pinctrl/pinctrl_pic32.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 57e6142..5dd2ddd 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -131,6 +131,16 @@ config PINCTRL_SANDBOX
  actually does nothing but print debug messages when pinctrl
  operations are invoked.
 
+config PIC32_PINCTRL
+   bool "Microchip PIC32 pin-control and pin-mux driver"
+   depends on DM && MACH_PIC32
+   default y
+   help
+ Supports individual pin selection and configuration for each 
remappable
+ peripheral available on Microchip PIC32 SoCs. This driver is 
controlled
+ by a device tree node which contains both GPIO defintion and pin 
control
+ functions.
+
 endif
 
 source "drivers/pinctrl/uniphier/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 70d25dc..b4f4650 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
 obj-$(CONFIG_PINCTRL_SANDBOX)  += pinctrl-sandbox.o
 
 obj-$(CONFIG_ARCH_UNIPHIER)+= uniphier/
+obj-$(CONFIG_PIC32_PINCTRL)+= pinctrl_pic32.o
diff --git a/drivers/pinctrl/pinctrl_pic32.c b/drivers/pinctrl/pinctrl_pic32.c
new file mode 100644
index 000..5cf97ec
--- /dev/null
+++ b/drivers/pinctrl/pinctrl_pic32.c
@@ -0,0 +1,363 @@
+/*
+ * Pinctrl driver for Microchip PIC32 SoCs
+ * Copyright (c) 2015 Microchip Technology Inc.
+ * Written by Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* PIC32 has 10 peripheral ports with 16 pins each.
+ * Ports are marked PORTA-PORTK or PORT0-PORT9.
+ */
+enum {
+   PIC32_PORT_A = 0,
+   PIC32_PORT_B = 1,
+   PIC32_PORT_C = 2,
+   PIC32_PORT_D = 3,
+   PIC32_PORT_E = 4,
+   PIC32_PORT_F = 5,
+   PIC32_PORT_G = 6,
+   PIC32_PORT_H = 7,
+   PIC32_PORT_J = 8, /* no PORT_I */
+   PIC32_PORT_K = 9,
+   PIC32_PINS_PER_PORT = 16,
+};
+
+#define PIN_CONFIG_PIC32_DIGITAL   (PIN_CONFIG_END + 1)
+#define PIN_CONFIG_PIC32_ANALOG(PIN_CONFIG_END + 2)
+
+/* pin configuration descriptor */
+struct pic32_pin_config {
+   u16 port;   /* port number */
+   u16 pin;/* pin number in the port */
+   u32 config; /* one of PIN_CONFIG_* */
+};
+#define PIN_CONFIG(_prt, _pin, _cfg) \
+   {.port = (_prt), .pin = (_pin), .config = (_cfg), }
+
+/* In PIC32 muxing is performed at pin-level through two
+ * different set of registers - one set for input functions,
+ * and other for output functions.
+ * Pin configuration is handled through port register.
+ */
+/* Port control registers */
+struct pic32_reg_port {
+   struct pic32_reg_atomic ansel;
+   struct pic32_reg_atomic tris;
+   struct pic32_reg_atomic port;
+   struct pic32_reg_atomic lat;
+   struct pic32_reg_atomic odc;
+   struct pic32_reg_atomic cnpu;
+   struct pic32_reg_atomic cnpd;
+   struct pic32_reg_atomic cncon;
+   struct pic32_reg_atomic unused[8];
+};
+
+/* Input function mux registers */
+struct pic32_reg_in_mux {
+   u32 unused0;
+   u32 int1[4];
+   u32 unused1;
+   u32 t2ck[8];
+   u32 ic1[9];
+   u32 unused2;
+   u32 ocfar;
+   u32 unused3;
+   u32 u1rx;
+   u32 u1cts;
+   u32 u2rx;
+   u32 u2cts;
+   u32 u3rx;
+   u32 u3cts;
+   u32 u4rx;
+   u32 u4cts;
+   u32 u5rx;
+   u32 u5cts;
+   u32 u6rx;
+   u32 u6cts;
+   u32 unused4;
+   u32 sdi1;
+   u32 ss1;
+   u32 unused5;
+   u32 sdi2;
+   u32 ss2;
+   u32 unused6;
+   u32 sdi3;
+   u32 ss3;
+

[U-Boot] [PATCH v4 02/13] drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.

[Purna Chandra Mandal]

PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers
and dividers capable of supplying clock to various controllers
on or off-chip.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Reviewed-by: Simon Glass <s...@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com>

---

Changes in v4: None
Changes in v3:
- rename clk-pic32.c to clk_pic32.c
- update clock binding documentation
- replace pic32_ioremap() with ioremap()
- separate MPLL initialization constants

Changes in v2:
- add mpll get clock rate

 .../clock/microchip,pic32-clock.txt|  33 ++
 drivers/clk/Makefile   |   1 +
 drivers/clk/clk_pic32.c| 433 +
 include/dt-bindings/clock/microchip,clock.h|  29 ++
 4 files changed, 496 insertions(+)
 create mode 100644 doc/device-tree-bindings/clock/microchip,pic32-clock.txt
 create mode 100644 drivers/clk/clk_pic32.c
 create mode 100644 include/dt-bindings/clock/microchip,clock.h

diff --git a/doc/device-tree-bindings/clock/microchip,pic32-clock.txt 
b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
new file mode 100644
index 000..f185ce0
--- /dev/null
+++ b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
@@ -0,0 +1,33 @@
+* Microchip PIC32 Clock and Oscillator
+
+Microchip PIC32 clock tree consists of few oscillators, PLLs,
+multiplexers and few divider modules capable of supplying clocks
+to various controllers within SoC and also to off-chip.
+
+PIC32 clock controller output is defined by indices as defined
+in [0]
+
+[0] include/dt-bindings/clock/microchip,clock.h
+
+Required Properties:
+- compatible: should be "microchip,pic32mzda_clk"
+- reg: physical base address of the controller and length of memory mapped
+   region.
+- #clock-cells: should be 1.
+
+Example: Clock controller node:
+
+   clock: clk@1f801200 {
+   compatible = "microchip,pic32mzda-clk";
+   reg = <0x1f801200 0x1000>;
+   };
+
+Example: UART controller node that consumes the clock generated by the clock
+controller:
+
+   uart1: serial@1f822000 {
+   compatible = "microchip,pic32mzda-uart";
+   reg = <0xbf822000 0x50>;
+   interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < PB2CLK>;
+   };
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 8aa81f4..c9144e3 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_CLK) += clk-uclass.o clk_fixed_rate.o
 obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
 obj-$(CONFIG_SANDBOX) += clk_sandbox.o
+obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
diff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c
new file mode 100644
index 000..5d88354
--- /dev/null
+++ b/drivers/clk/clk_pic32.c
@@ -0,0 +1,433 @@
+/*
+ * Copyright (C) 2015 Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Primary oscillator */
+#define SYS_POSC_CLK_HZ2400
+
+/* FRC clk rate */
+#define SYS_FRC_CLK_HZ 800
+
+/* Clock Registers */
+#define OSCCON 0x
+#define OSCTUNE0x0010
+#define SPLLCON0x0020
+#define REFO1CON   0x0080
+#define REFO1TRIM  0x0090
+#define PB1DIV 0x0140
+
+/* SPLL */
+#define ICLK_MASK  0x0080
+#define PLLIDIV_MASK   0x0007
+#define PLLODIV_MASK   0x0007
+#define CUROSC_MASK0x0007
+#define PLLMUL_MASK0x007F
+#define FRCDIV_MASK0x0007
+
+/* PBCLK */
+#define PBDIV_MASK 0x0007
+
+/* SYSCLK MUX */
+#define SCLK_SRC_FRC1  0
+#define SCLK_SRC_SPLL  1
+#define SCLK_SRC_POSC  2
+#define SCLK_SRC_FRC2  7
+
+/* Reference Oscillator Control Reg fields */
+#define REFO_SEL_MASK  0x0f
+#define REFO_SEL_SHIFT 0
+#define REFO_ACTIVEBIT(8)
+#define REFO_DIVSW_EN  BIT(9)
+#define REFO_OEBIT(12)
+#define REFO_ONBIT(15)
+#define REFO_DIV_SHIFT 16
+#define REFO_DIV_MASK  0x7fff
+
+/* Reference Oscillator Trim Register Fields */
+#define REFO_TRIM_REG  0x10
+#define REFO_TRIM_MASK 0x1ff
+#define REFO_TRIM_SHIFT23
+#define REFO_TRIM_MAX  511
+
+#define ROCLK_SRC_SCLK 0x0
+#define ROCLK_SRC_SPLL 0x7
+#define ROCLK_SRC_ROCLKI   0x8
+
+/* Memory PLL */
+#define MPLL_IDIV  0x3f
+#define MPLL_MULT  0xff
+#define MPLL_ODIV1 0x7
+#define MPLL_ODIV2 0x7
+#define MPLL_VREG_RDY  BIT(23)
+#define MPLL_RDY   BIT(31)
+#define MPLL_IDIV_SHIFT0
+#define MPLL_MULT_SHIFT8
+#define MPLL_ODIV1_SHIFT   24
+#define MPLL_ODIV2_SHIFT 

[U-Boot] [PATCH v4 05/13] drivers: serial: add driver for Microchip PIC32 UART controller.

[Purna Chandra Mandal]

From: Paul Thacker <paul.thac...@microchip.com>

This adds PIC32 UART controller support based on driver model.

Signed-off-by: Paul Thacker <paul.thac...@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
Reviewed-by: Tom Rini <tr...@konsulko.com>
Reviewed-by: Simon Glass <s...@chromium.org>


---

Changes in v4:
- update kconfig dependency (DM_SERIAL && MACH_PIC32)
- update comment for _pending_input().
- rename UART_RX_OERR to UART_RX_OVER.
- DEBUG_UART_PIC32 now depends on PIC32_SERIAL
- extract clk_id from device-tree

Changes in v3:
- remove ofdata_to_platdata, and replace platdata with priv
- remove special handling of '\r' as being handled by serial-uclass
- remove loop to wait for space in tx buffer before pumping char

Changes in v2:
- fix missing/corrupted chars during baud rate change
- remove loop until any char is avaialbale in getc()

 .../serial/microchip,pic32-uart.txt|   5 +
 drivers/serial/Kconfig |  15 ++
 drivers/serial/Makefile|   1 +
 drivers/serial/serial_pic32.c  | 198 +
 4 files changed, 219 insertions(+)
 create mode 100644 doc/device-tree-bindings/serial/microchip,pic32-uart.txt
 create mode 100644 drivers/serial/serial_pic32.c

diff --git a/doc/device-tree-bindings/serial/microchip,pic32-uart.txt 
b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt
new file mode 100644
index 000..f00e215
--- /dev/null
+++ b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt
@@ -0,0 +1,5 @@
+* Microchip PIC32 serial UART
+
+Required properties:
+- compatible: must be "microchip,pic32mzda-uart".
+- reg: exactly one register range.
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 83068cf..43b2ec3 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -143,6 +143,14 @@ config DEBUG_UART_PL011
  work. The driver will be available until the real driver model
  serial is running.
 
+config DEBUG_UART_PIC32
+   bool "Microchip PIC32"
+   depends on PIC32_SERIAL
+   help
+ Select this to enable a debug UART using the serial_pic32 driver. You
+ will need to provide parameters to make this work. The driver will
+ be available until the real driver model serial is running.
+
 endchoice
 
 config DEBUG_UART_BASE
@@ -234,6 +242,13 @@ config FSL_LPUART
  Select this to enable a Low Power UART for Freescale VF610 and
  QorIQ Layerscape devices.
 
+config PIC32_SERIAL
+   bool "Support for Microchip PIC32 on-chip UART"
+   depends on DM_SERIAL && MACH_PIC32
+   default y
+   help
+ Support for the UART found on Microchip PIC32 SoC's.
+
 config SYS_NS16550
bool "NS16550 UART or compatible"
help
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index dd87147..57cd38b 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_MXS_AUART) += mxs_auart.o
 obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
 obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
 obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
+obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c
new file mode 100644
index 000..af9fbbf
--- /dev/null
+++ b/drivers/serial/serial_pic32.c
@@ -0,0 +1,198 @@
+/*
+ * (c) 2015 Paul Thacker <paul.thac...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* UART Control Registers */
+#define U_MOD  0x00
+#define U_MODCLR   (U_MOD + _CLR_OFFSET)
+#define U_MODSET   (U_MOD + _SET_OFFSET)
+#define U_STA  0x10
+#define U_STACLR   (U_STA + _CLR_OFFSET)
+#define U_STASET   (U_STA + _SET_OFFSET)
+#define U_TXR  0x20
+#define U_RXR  0x30
+#define U_BRG  0x40
+
+/* U_MOD bits */
+#define UART_ENABLEBIT(15)
+
+/* U_STA bits */
+#define UART_RX_ENABLE BIT(12)
+#define UART_TX_BRKBIT(11)
+#define UART_TX_ENABLE BIT(10)
+#define UART_TX_FULL   BIT(9)
+#define UART_TX_EMPTY  BIT(8)
+#define UART_RX_OVER   BIT(1)
+#define UART_RX_DATA_AVAIL BIT(0)
+
+struct pic32_uart_priv {
+   void __iomem *base;
+   ulong uartclk;
+};
+
+/*
+ * Initialize the serial port with the given baudrate.
+ * The settings are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int pic32_serial_init(void __iomem *base, ulong clk, u32 baudrate)
+{
+   u32 div = DIV_ROUND_CLOSEST(clk, baudrate * 16);
+
+   /* wait for TX FIFO to empty */
+   w

[U-Boot] [PATCH v2] MIPS: initialize board_init_f() argument to zero.

[Purna Chandra Mandal]

Argument boot_flags of board_init_f() should be set to 0 as
$a0 may be utilized in lowlevel_init() or mips_cache_reset()
or previous stage boot-loader.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

Changes in v2:
- add comment in same line as of the asm instruction
- add commit message

 arch/mips/cpu/start.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index e95cdca..2aa2dcb 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -185,7 +185,7 @@ reset:
PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset
sw  sp, 0(t0)
 #endif
-
+   movea0, zero# a0 <-- boot_flags = 0
PTR_LA  t9, board_init_f
jr  t9
 move   ra, zero
-- 
1.8.3.1

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[U-Boot] [PATCH] bootm: fix size arg of flush_cache() in bootm_load_os().

[Purna Chandra Mandal]

Variable _load_end_ points to end address of uncompressed buffer
(*not* uncomress_buffer_end / sizeof(ulong)), so multipling uncompressed
size with sizeof(ulong) is grossly incorrect in flush_cache().
It might lead to access of address beyond valid memory range and hang the CPU.

Tested on MIPS architecture by using compressed(gzip, lzma)
and uncompressed uImage.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---

 common/bootm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/bootm.c b/common/bootm.c
index 58936ca..99d574d 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -435,7 +435,7 @@ static int bootm_load_os(bootm_headers_t *images, unsigned 
long *load_end,
bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
return err;
}
-   flush_cache(load, (*load_end - load) * sizeof(ulong));
+   flush_cache(load, *load_end - load);
 
debug("   kernel loaded at 0x%08lx, end = 0x%08lx\n", load, *load_end);
bootstage_mark(BOOTSTAGE_ID_KERNEL_LOADED);
-- 
1.8.3.1

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Re: [U-Boot] [PATCH v3 11/14] board: add SDHCI support for PIC32MZDASK board.

[Purna Chandra Mandal]

On 01/13/2016 08:26 PM, Tom Rini wrote:
> On Tue, Jan 12, 2016 at 03:48:26PM +0530, Purna Chandra Mandal wrote:
>
>> Enable MMC, SDHCI, FAT FS, EXT4 FS support for PIC32MZ[DA] StarterKit.
>> Also add custom scripts, rules to boot Linux from microSD card.
>>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
> [snip]
>> +#define CONFIG_EXTRA_ENV_SETTINGS   \
>> +"loadaddr="__stringify(CONFIG_SYS_LOAD_ADDR)"\0"\
>> +"uenvfile=uEnv.txt\0"   \
>> +"uenvaddr="__stringify(CONFIG_SYS_ENV_ADDR)"\0" \
>> +"scriptfile=boot.scr\0" \
>> +"ubootfile=u-boot.bin\0"\
>> +"importbootenv= "   \
>> +"env import -t -r ${uenvaddr} ${filesize};\0"   \
>> +\
>> +"mmcloadenv=fatload mmc 0 ${uenvaddr} ${uenvfile}\0"\
>> +"mmcloadscr=fatload mmc 0 ${uenvaddr} ${scriptfile}\0"  \
>> +"mmcloadub=fatload mmc 0 ${loadaddr} ${ubootfile}\0"\
>> +\
>> +"loadbootenv=run mmcloadenv\0"  \
>> +"loadbootscr=run mmcloadscr\0"  \
>> +"bootcmd_root= "\
>> +"if run loadbootenv; then " \
>> +"echo Loaded environment ${uenvfile}; " \
>> +"run importbootenv; "   \
>> +"fi; "  \
>> +"if test -n \"${bootcmd_uenv}\" ; then "\
>> +"echo Running bootcmd_uenv ...; "   \
>> +"run bootcmd_uenv; "\
>> +"fi; "  \
>> +"if run loadbootscr; then " \
>> +"echo Jumping to ${scriptfile}; "   \
>> +"source ${uenvaddr}; "  \
>> +"fi; "  \
>> +"echo Custom environment or script not found. " \
>> +"Aborting auto booting...; \0"  \
>> +""
>> +
>> +#define CONFIG_BOOTCOMMAND  "run bootcmd_root"
> I would like to see the env above done as a separate commit and then
> using config_distro_default / bootcmd :)

agreed. Will add in separate commit and using config_distro_default(/bootcmd).h.


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Re: [U-Boot] [PATCH v3 09/14] board: Add Microchip PIC32MZ[DA]-Starter-Kit board.

[Purna Chandra Mandal]

On 01/13/2016 08:33 PM, Daniel Schwierzeck wrote:

> Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:
>> This adds support for Microchip PIC32MZ[DA] StarterKit board
>> based on a PIC32MZ[DA] family of microcontroller.
>>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>
>>
>> ---
>>
>> Changes in v3:
>> - drop SKIP_LOWLEVEL_INIT, GBL_DATA_OFFSET from config header
>> - move CMD_MEMTEST, CMD_MEMINFO to defconfig
>> - increase SYS_MALLOC_F_LEN to 0x600
>> - use auto-generated defconfig - no hand edit
>>
>> Changes in v2:
>> - move CONFIG_SYS_TEXT_BASE (from board/*/config.mk) to
>> include/configs/.h
>>
>>  arch/mips/dts/Makefile|   2 +-
>>  arch/mips/dts/pic32mzda_sk.dts|  38 
>>  arch/mips/mach-pic32/Kconfig  |  13 ++
>>  board/microchip/pic32mzda/Kconfig |  13 ++
>>  board/microchip/pic32mzda/MAINTAINERS |   6 +
>>  board/microchip/pic32mzda/Makefile|   7 +
>>  board/microchip/pic32mzda/README  |  22 ++
>>  board/microchip/pic32mzda/pic32mzda.c |  31 +++
>>  configs/pic32mzdask_defconfig | 416
>> ++
>>  include/configs/pic32mzdask.h |  94 
>>  10 files changed, 641 insertions(+), 1 deletion(-)
>>  create mode 100644 arch/mips/dts/pic32mzda_sk.dts
>>  create mode 100644 board/microchip/pic32mzda/Kconfig
>>  create mode 100644 board/microchip/pic32mzda/MAINTAINERS
>>  create mode 100644 board/microchip/pic32mzda/Makefile
>>  create mode 100644 board/microchip/pic32mzda/README
>>  create mode 100644 board/microchip/pic32mzda/pic32mzda.c
>>  create mode 100644 configs/pic32mzdask_defconfig
>>  create mode 100644 include/configs/pic32mzdask.h
>>
>> diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
>> index 47b6eb5..b513918 100644
>> --- a/arch/mips/dts/Makefile
>> +++ b/arch/mips/dts/Makefile
>> @@ -2,7 +2,7 @@
>>  # SPDX-License-Identifier:  GPL-2.0+
>>  #
>>  
>> -dtb-y +=
>> +dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
>>  
>>  targets += $(dtb-y)
>>  
>> diff --git a/arch/mips/dts/pic32mzda_sk.dts
>> b/arch/mips/dts/pic32mzda_sk.dts
>> new file mode 100644
>> index 000..99e7f64
>> --- /dev/null
>> +++ b/arch/mips/dts/pic32mzda_sk.dts
>> @@ -0,0 +1,38 @@
>> +/*
>> + * Copyright (C) 2015 Purna Chandra Mandal, 
>> purna.man...@microchip.com
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "pic32mzda.dtsi"
>> +
>> +/ {
>> +model = "Microchip PIC32MZDASK";
>> +compatible = "microchip,pic32mzdask", "microchip,pic32mzda";
>> +
>> +aliases {
>> +console = 
>> +serial0 = 
>> +};
>> +
>> +chosen {
>> +stdout-path = "serial0:115200n8";
>> +};
>> +};
>> +
>> + {
>> +status = "okay";
>> +u-boot,dm-pre-reloc;
>> +};
>> +
>> + {
>> +status = "okay";
>> +u-boot,dm-pre-reloc;
>> +};
>> +
>> + {
>> +status = "okay";
>> +u-boot,dm-pre-reloc;
>> +};
>> diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach
>> -pic32/Kconfig
>> index 74be9fb..d665f63 100644
>> --- a/arch/mips/mach-pic32/Kconfig
>> +++ b/arch/mips/mach-pic32/Kconfig
>> @@ -22,4 +22,17 @@ config SOC_PIC32MZDA
>>  
>>  endchoice
>>  
>> +choice
>> +prompt "Board select"
>> +
>> +config TARGET_PIC32MZDASK
>> +bool "Microchip PIC32MZ[DA] Starter Kit"
>> +depends on SOC_PIC32MZDA
>> +help
>> +  This supports Microchip PIC32MZ[DA] Starter Kit.
>> +
>> +endchoice
>> +
>> +source "board/microchip/pic32mzda/Kconfig"
>> +
>>  endmenu
>> diff --git a/board/microchip/pic32mzda/Kconfig
>> b/board/microchip/pic32mzda/Kconfig
>> new file mode 100644
>> index 000..8acb393
>> --- /dev/null
>> +++ b/board/microchip/pic32mzda/Kconfig
>> @@ -0,0 +1,13 @@
>> +
>> +if TARGET_PIC32MZDASK
>> +
>> +config SYS_BOARD
>> +default "pic32mzda"
>> +
>> +config SYS_VENDOR
>> +default "microchip"
>> +
>> +config SYS_CONFIG_NAME
>> +default "pic32mzdask"
>> +
>> +endif
>> diff

Re: [U-Boot] [PATCH v3 05/14] drivers: gpio: add driver for Microchip PIC32 GPIO controller.

[Purna Chandra Mandal]

On 01/14/2016 01:40 AM, Simon Glass wrote:

> Hi Puma,
>
> On 12 January 2016 at 03:18, Purna Chandra Mandal
> <purna.man...@microchip.com> wrote:
>> In PIC32 GPIO controller is part of PIC32 pin controller.
>> PIC32 has ten independently programmable ports and each with multiple pins.
>> Each of these pins can be configured and used as GPIO, provided they
>> are not in use for other peripherals.
>>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>
>> ---
>>
>> Changes in v3:
>> - add check on dev_get_addr()
>>
>> Changes in v2: None
>>
>>  drivers/gpio/Kconfig  |   7 ++
>>  drivers/gpio/Makefile |   2 +-
>>  drivers/gpio/pic32_gpio.c | 175 
>> ++
>>  3 files changed, 183 insertions(+), 1 deletion(-)
>>  create mode 100644 drivers/gpio/pic32_gpio.c
>>
> Reviewed-by: Simon Glass <s...@chromium.org>
>
> Just a few nits.
>
>> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
>> index e60e9fd..13e9a6a 100644
>> --- a/drivers/gpio/Kconfig
>> +++ b/drivers/gpio/Kconfig
>> @@ -83,4 +83,11 @@ config VYBRID_GPIO
>> help
>>   Say yes here to support Vybrid vf610 GPIOs.
>>
>> +config PIC32_GPIO
>> +   bool "Microchip PIC32 GPIO driver"
>> +   depends on DM_GPIO
>> +   default y if MACH_PIC32
>> +   help
>> + Say yes here to support Microchip PIC32 GPIOs.
>> +
>>  endmenu
>> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
>> index fb4fd25..845a6d4 100644
>> --- a/drivers/gpio/Makefile
>> +++ b/drivers/gpio/Makefile
>> @@ -46,4 +46,4 @@ obj-$(CONFIG_STM32_GPIO)  += stm32_gpio.o
>>  obj-$(CONFIG_ZYNQ_GPIO)+= zynq_gpio.o
>>  obj-$(CONFIG_VYBRID_GPIO)  += vybrid_gpio.o
>>  obj-$(CONFIG_HIKEY_GPIO)   += hi6220_gpio.o
>> -
>> +obj-$(CONFIG_PIC32_GPIO)   += pic32_gpio.o
>> diff --git a/drivers/gpio/pic32_gpio.c b/drivers/gpio/pic32_gpio.c
>> new file mode 100644
>> index 000..5b23af4
>> --- /dev/null
>> +++ b/drivers/gpio/pic32_gpio.c
>> @@ -0,0 +1,175 @@
>> +/*
>> + * Copyright (c) 2015 Microchip Technology Inc
>> + * Purna Chandra Mandal <purna.man...@microchip.com>
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +/* Peripheral Pin Control */
>> +struct pic32_reg_port {
>> +   struct pic32_reg_atomic ansel;
>> +   struct pic32_reg_atomic tris;
>> +   struct pic32_reg_atomic port;
>> +   struct pic32_reg_atomic lat;
>> +   struct pic32_reg_atomic open_drain;
>> +   struct pic32_reg_atomic cnpu;
>> +   struct pic32_reg_atomic cnpd;
>> +   struct pic32_reg_atomic cncon;
>> +};
>> +
>> +enum {
>> +   MICROCHIP_GPIO_DIR_OUT,
>> +   MICROCHIP_GPIO_DIR_IN,
>> +   MICROCHIP_GPIOS_PER_BANK = 16,
>> +};
>> +
>> +struct pic32_gpio_priv {
>> +   struct pic32_reg_port *regs;
>> +   char name[2];
>> +};
>> +
>> +static int pic32_gpio_get_value(struct udevice *dev, unsigned offset)
>> +{
>> +   struct pic32_gpio_priv *priv = dev_get_priv(dev);
>> +
>> +   return !!(readl(>regs->port.raw) & BIT(offset));
>> +}
>> +
>> +static int pic32_gpio_set_value(struct udevice *dev, unsigned offset,
>> +   int value)
>> +{
>> +   struct pic32_gpio_priv *priv = dev_get_priv(dev);
>> +   int mask = BIT(offset);
>> +
>> +   if (value)
>> +   writel(mask, >regs->port.set);
>> +   else
>> +   writel(mask, >regs->port.clr);
>> +
>> +   return 0;
>> +}
>> +
>> +static int pic32_gpio_direction(struct udevice *dev, unsigned offset)
>> +{
>> +   struct pic32_gpio_priv *priv = dev_get_priv(dev);
>> +
>> +   if (readl(>regs->ansel.raw) & BIT(offset))
>> +   return -1;
> What does this error mean? Should it be -EPERM? Perhaps add a comment.

It checks whether the pin is still in ANALOG mode. Report error (-EPERM is 
better) in case of analog. For GPIO to work the pin has to be in DIGITAL mode 
which is configured in _direction_input(), _direction_output() cal

Re: [U-Boot] [PATCH v3 13/14] drivers: net: Add ethernet driver for Microchip PIC32.

[Purna Chandra Mandal]

On 01/13/2016 09:07 PM, Daniel Schwierzeck wrote:

> Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:
>> This driver implements MAC and MII layer of the ethernet controller.
>> Network data transfer is handled by controller internal DMA engine.
>> Ethernet controller is configurable through device-tree file.
>>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>
>>
>> ---
>>
>> Changes in v3:
>> - merge wrappers with eth operation callbacks
>> - read phy address from device-tree
>> - rename functions (e.g. _eth_xyz() with pic32_eth_xyz())
>>
>> Changes in v2: None
>>
>>  drivers/net/Kconfig  |   7 +
>>  drivers/net/Makefile |   1 +
>>  drivers/net/pic32_eth.c  | 606
>> +++
>>  drivers/net/pic32_eth.h  | 171 +
>>  drivers/net/pic32_mdio.c | 121 ++
>>  5 files changed, 906 insertions(+)
>>  create mode 100644 drivers/net/pic32_eth.c
>>  create mode 100644 drivers/net/pic32_eth.h
>>  create mode 100644 drivers/net/pic32_mdio.c
>>
>> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
>> index ae5e78d..dc49493 100644
>> --- a/drivers/net/Kconfig
>> +++ b/drivers/net/Kconfig
>> @@ -108,4 +108,11 @@ config ZYNQ_GEM
>>  help
>>This MAC is present in Xilinx Zynq and ZynqMP SoCs.
>>  
>> +config PIC32_ETH
>> +bool "Microchip PIC32 Ethernet Support"
>> +depends on MACH_PIC32
> should be
>
> depends on DM_ETH && MACH_PIC32
> select PHYLIB

ack.

>> +help
>> +  This driver implements 10/100 Mbps Ethernet and MAC layer
>> for
>> +  Microchip PIC32 microcontrollers.
>> +
>>  endif # NETDEVICES
>> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
>> index 150470c..33a81ee 100644
>> --- a/drivers/net/Makefile
>> +++ b/drivers/net/Makefile
>> @@ -72,3 +72,4 @@ obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
>>  obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/
>>  obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
>>  obj-$(CONFIG_VSC9953) += vsc9953.o
>> +obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
>> diff --git a/drivers/net/pic32_eth.c b/drivers/net/pic32_eth.c
>> new file mode 100644
>> index 000..1cef62e
>> --- /dev/null
>> +++ b/drivers/net/pic32_eth.c
>> @@ -0,0 +1,606 @@
>> +/*
>> + * (c) 2015 Purna Chandra Mandal <purna.man...@microchip.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + *
>> + */
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include "pic32_eth.h"
>> +
>> +#define MAX_RX_BUF_SIZE 1536
>> +#define MAX_RX_DESCRPKTBUFSRX
>> +#define MAX_TX_DESCR2
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +struct pic32eth_dev {
>> +struct eth_dma_desc rxd_ring[MAX_RX_DESCR];
>> +struct eth_dma_desc txd_ring[MAX_TX_DESCR];
>> +u32 rxd_idx; /* index of RX desc to read */
>> +/* regs */
>> +struct pic32_ectl_regs *ectl_regs;
>> +struct pic32_emac_regs *emac_regs;
>> +/* Phy */
>> +struct phy_device *phydev;
>> +phy_interface_t phyif;
>> +u32 phy_addr;
>> +struct gpio_desc rst_gpio;
>> +};
>> +
>> +void __weak board_netphy_reset(void *dev)
>> +{
>> +struct pic32eth_dev *priv = (struct pic32eth_dev *)dev;
> the cast is not necessary

ack. Will remove,

>> +
>> +if (!dm_gpio_is_valid(>rst_gpio))
>> +return;
>> +
>> +/* phy reset */
>> +dm_gpio_set_value(>rst_gpio, 0);
>> +udelay(300);
>> +dm_gpio_set_value(>rst_gpio, 1);
>> +udelay(300);
>> +}
>> +
>> +/* Initialize mii(MDIO) interface, discover which PHY is
>> + * attached to the device, and configure it properly.
>> + */
>> +static int pic32_mii_init(struct pic32eth_dev *priv)
>> +{
>> +struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
>> +struct pic32_emac_regs *emac_p = priv->emac_regs;
>> +
>> +/* board phy reset */
>> +board_netphy_reset(priv);
>> +
>> +/* disable RX, TX & all transactions */
>> +writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, _p
>> ->con1.clr);
>> +
>> +/* wait till busy */
>> +wait_for_bit(__func__, _p->stat.raw, ETHSTAT_BUSY,
>> false,
>&g

Re: [U-Boot] [PATCH v3 13/14] drivers: net: Add ethernet driver for Microchip PIC32.

[Purna Chandra Mandal]

On 01/13/2016 08:26 PM, Tom Rini wrote:

> On Tue, Jan 12, 2016 at 03:48:28PM +0530, Purna Chandra Mandal wrote:
>
>> This driver implements MAC and MII layer of the ethernet controller.
>> Network data transfer is handled by controller internal DMA engine.
>> Ethernet controller is configurable through device-tree file.
>>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
> [snip]
>> +/* cache operation helper */
>> +#define __dcache_flush(__a, __l) \
>> +flush_dcache_range((ulong)(__a),  ((__l) + (ulong)(__a)))
>> +
>> +#define __dcache_invalidate(__a, __l) \
>> +invalidate_dcache_range((ulong)(__a),  ((__l) + (ulong)(__a)))
> Why using these helper functions instead of directly?  Yes, we may be
> casting in some cases and if that's how it must be, so be it (it's how
> we're doing it in other drivers).  Thanks!

Thanks, Will drop these helpers/macros.


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Re: [U-Boot] [PATCH v3 10/14] drivers: mmc: add driver for Microchip PIC32 SDHCI controller.

[Purna Chandra Mandal]

On 01/13/2016 08:45 PM, Daniel Schwierzeck wrote:
> Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:
>> From: Andrei Pistirica <andrei.pistir...@microchip.com>
>>
>> This driver implements platform specific glue and fixups for
>> PIC32 internal SDHCI controller.
>>
>> Signed-off-by: Andrei Pistirica <andrei.pistir...@microchip.com>
>> Signed-off-by: Sandeep Sheriker Mallikarjun <
>> sandeepsheriker.mallikar...@microchip.com>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>
> Reviewed-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
>
> nits below
>
>> ---
>>
>> Changes in v3:
>> - remove ofdata_to_platdata, and replace platdata with priv
>> - replace pic32_ioremap() with ioremap()
>>
>> Changes in v2:
>> - drop sdhci shared bus configuration (for shared interrupt, clock
>> pins)
>>
>>  drivers/mmc/Kconfig   |  6 +
>>  drivers/mmc/Makefile  |  2 +-
>>  drivers/mmc/pic32_sdhci.c | 61
>> +++
>>  drivers/mmc/sdhci.c   | 12 ++
>>  4 files changed, 80 insertions(+), 1 deletion(-)
>>  create mode 100644 drivers/mmc/pic32_sdhci.c
>>
>> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
>> index ceae7bc..0b6f54b 100644
>> --- a/drivers/mmc/Kconfig
>> +++ b/drivers/mmc/Kconfig
>> @@ -31,4 +31,10 @@ config SH_SDHI
>>  help
>>Support for the on-chip SDHI host controller on
>> SuperH/Renesas ARM SoCs platform
>>  
>> +config PIC32_SDHCI
>> +bool "Microchip PIC32 on-chip SDHCI support"
>> +depends on DM_MMC && MACH_PIC32
>> +help
>> +  Support for the on-chip SDHCI support on Microchip PIC32
>> platforms.
>> +
>>  endmenu
>> diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
>> index 5d35705..c9c3e3e 100644
>> --- a/drivers/mmc/Makefile
>> +++ b/drivers/mmc/Makefile
>> @@ -48,4 +48,4 @@ obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
>>  else
>>  obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
>>  endif
>> -
>> +obj-$(CONFIG_PIC32_SDHCI) += pic32_sdhci.o
>> diff --git a/drivers/mmc/pic32_sdhci.c b/drivers/mmc/pic32_sdhci.c
>> new file mode 100644
>> index 000..f8a5a23
>> --- /dev/null
>> +++ b/drivers/mmc/pic32_sdhci.c
>> @@ -0,0 +1,61 @@
>> +/*
>> + * Support of SDHCI for Microchip PIC32 SoC.
>> + *
>> + * Copyright (C) 2015 Microchip Technology Inc.
>> + * Andrei Pistirica <andrei.pistir...@microchip.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +static int pic32_sdhci_probe(struct udevice *dev)
>> +{
>> +struct sdhci_host *host = dev_get_priv(dev);
>> +const void *fdt = gd->fdt_blob;
>> +u32 f_min_max[2];
>> +fdt_addr_t addr;
>> +fdt_size_t size;
>> +int ret;
>> +
>> +addr = fdtdec_get_addr_size(fdt, dev->of_offset, "reg",
>> );
>> +if (addr == FDT_ADDR_T_NONE)
>> +return -EINVAL;
>> +
>> +host->ioaddr = ioremap(addr, size);
>> +if (!host->ioaddr)
>> +return -EINVAL;
> this check can be dropped. ioremap() always returns a mapped address

Ack. Will drop.

>> +
>> +host->name  = (char *)dev->name;
>> +host->quirks= SDHCI_QUIRK_NO_HISPD_BIT;
>> +host->bus_width = fdtdec_get_int(gd->fdt_blob, dev
>> ->of_offset,
>> +"bus-width", 4);
>> +
>> +ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
>> +   "clock-freq-min-max", f_min_max,
>> 2);
>> +if (ret) {
>> +printf("sdhci: clock-freq-min-max not found\n");
>> +return ret;
>> +}
>> +
>> +return add_sdhci(host, f_min_max[1], f_min_max[0]);
>> +}
>> +
>> +static const struct udevice_id pic32_sdhci_ids[] = {
>> +{ .compatible = "microchip,pic32mzda-sdhci" },
>> +{ }
>> +};
>> +
>> +U_BOOT_DRIVER(pic32_sdhci_drv) = {
>> +.name   = "pic32_sdhci",
>> +.id = UCLASS_MMC,
>> +.of_match   = pic32_sdhci_ids,
>> +.probe  = pic32_sdhci_pr

Re: [U-Boot] [PATCH v3 03/14] drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.

[Purna Chandra Mandal]

On 01/13/2016 07:08 PM, Daniel Schwierzeck wrote:

> Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:
>> PIC32 clock module consists of multiple oscillators, PLLs,
>> mutiplexers
>> and dividers capable of supplying clock to various controllers
>> on or off-chip.
>>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>> Reviewed-by: Simon Glass <s...@chromium.org>
> Reviewed-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
>
> nits below
>
>> ---
>>
>> Changes in v3:
>> - rename clk-pic32.c to clk_pic32.c
>> - update clock binding documentation
>> - replace pic32_ioremap() with ioremap()
>> - separate MPLL initialization constants
>>
>> Changes in v2:
>> - add mpll get clock rate
>>
>>  .../clock/microchip,pic32-clock.txt|  33 ++
>>  drivers/clk/Makefile   |   1 +
>>  drivers/clk/clk_pic32.c| 433
>> +
>>  include/dt-bindings/clock/microchip,clock.h|  29 ++
>>  4 files changed, 496 insertions(+)
>>  create mode 100644 doc/device-tree-bindings/clock/microchip,pic32
>> -clock.txt
>>  create mode 100644 drivers/clk/clk_pic32.c
>>  create mode 100644 include/dt-bindings/clock/microchip,clock.h
>>
>> diff --git a/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
>> b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
>> new file mode 100644
>> index 000..02e5ce4
>> --- /dev/null
>> +++ b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
>> @@ -0,0 +1,33 @@
>> +* Microchip PIC32 Clock and Oscillator
>> +
>> +Microchip PIC32 clock tree consists of few oscillators, PLLs,
>> +multiplexers and few divider modules capable of supplying clocks
>> +to various controllers within SoC and also to off-chip.
>> +
>> +PIC32 clock controller output is defined by indices as defined
>> +in [0]
>> +
>> +[0] include/dt-bindings/clock/microchip,clock.h
>> +
>> +Required Properties:
>> +- compatible: should be "microchip,pic32mzda_clk"
>> +- reg: physical base address of the controller and length of memory
>> mapped
>> +   region.
>> +- #clock-cells: should be 1.
>> +
>> +Example: Clock controller node:
>> +
>> +clock: clk@1f801200 {
>> +compatible = "microchip,pic32mzda_clk";
>> +reg = <0x1f801200 0x1000>;
>> +};
>> +
>> +Example: UART controller node that consumes the clock generated by
>> the clock
>> +controller:
>> +
>> +uart1: serial@1f822000 {
>> +compatible = "microchip,pic32mzda-uart";
>> +reg = <0xbf822000 0x50>;
>> +interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
>> +clocks = < PB2CLK>;
>> +};
>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>> index 4a6a4a8..adda769 100644
>> --- a/drivers/clk/Makefile
>> +++ b/drivers/clk/Makefile
>> @@ -9,3 +9,4 @@ obj-$(CONFIG_CLK) += clk-uclass.o
>>  obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
>>  obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
>>  obj-$(CONFIG_SANDBOX) += clk_sandbox.o
>> +obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
>> diff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c
>> new file mode 100644
>> index 000..bb0a1cf
>> --- /dev/null
>> +++ b/drivers/clk/clk_pic32.c
>> @@ -0,0 +1,433 @@
>> +/*
>> + * Copyright (C) 2015 Purna Chandra Mandal <
>> purna.man...@microchip.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + *
>> + */
>> +
>> [...]
>> +
>> +static ulong pic32_set_periph_rate(struct udevice *dev, int periph,
>> ulong rate)
>> +{
>> +struct pic32_clk_priv *priv = dev_get_priv(dev);
>> +ulong pll_hz;
>> +
>> +switch (periph) {
>> +case REF1CLK ... REF5CLK:
>> +pll_hz = pic32_get_pll_rate(priv);
>> +pic32_set_refclk(priv, periph, pll_hz, rate,
>> ROCLK_SRC_SPLL);
>> +break;
>> +default:
>> +break;
>> +}
>> +
>> +return rate;
>> +}
>> +
>> +static struct clk_ops pic32_pic32_clk_ops = {
>> +.get_rate = pic32_clk_get_rate,
>> +.set_periph_rate = pic32_set_periph_rate,
>> +.get_periph_rate = pic32_get_periph_rate,
>> +};
>> +
>> +static int pic32_clk_probe(struct udevice *dev)
>>

Re: [U-Boot] [PATCH v3 03/14] drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.

[Purna Chandra Mandal]

On 01/13/2016 08:25 PM, Tom Rini wrote:

> On Tue, Jan 12, 2016 at 03:48:18PM +0530, Purna Chandra Mandal wrote:
>
>> PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers
>> and dividers capable of supplying clock to various controllers
>> on or off-chip.
> [snip]
>>  include/dt-bindings/clock/microchip,clock.h|  29 ++
> Has this been submitted for the kernel and reviewed there as well
> already?  Thanks!
>
Clock driver in kernel is under review.
[1] clock driver: https://lkml.org/lkml/2016/1/7/764
[0] clock binding: https://lkml.org/lkml/2016/1/7/762
 
Please note clock driver in Linux kernel is implemented in more 
elaborate/descriptive way - all the sub-modules are individually defined in 
device-tree (having "#clock-cells = <0>") and their phandles are directly
referred in clock clients so there was no need of having dt-binding header.


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Re: [U-Boot] [PATCH v3 01/14] MIPS: initialize board_init_f() argument to zero.

[Purna Chandra Mandal]

On 01/12/2016 05:59 PM, Daniel Schwierzeck wrote:

> 2016-01-12 11:18 GMT+01:00 Purna Chandra Mandal <purna.man...@microchip.com>:
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>> ---
>>
>> Changes in v3: None
>> Changes in v2: None
>>
>>  arch/mips/cpu/start.S | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
>> index e95cdca..35d9650 100644
>> --- a/arch/mips/cpu/start.S
>> +++ b/arch/mips/cpu/start.S
>> @@ -185,6 +185,8 @@ reset:
>> PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset
>> sw  sp, 0(t0)
>>  #endif
>> +   /* Initialize args to zero */
>> +   movea0, zero
> the comment should be on the same line and more precise. That is
> useful in disassemblies or when debugging. E.g.
>
> movea0, zero# a0 <-- boot_flags = 0
>
> Also add a commit message please explaining why the change is
> required. Something like that the boot_flags of board_init_f should be
> set to 0 because $a0 may be utilized in lowlevel_init or
> mips_cache_reset.

ack. Will add accordingly,

>> PTR_LA  t9, board_init_f
>> jr  t9
>> --
>> 1.8.3.1
>>
>
>

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Re: [U-Boot] [PATCH v3 08/14] MIPS: Add support for Microchip PIC32MZ[DA] SoC family.

[Purna Chandra Mandal]

On 01/13/2016 08:19 PM, Daniel Schwierzeck wrote:

> Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:
>> Add Microchip PIC32MZ[DA] SoC family support.
>>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>
>> ---
>>
>> Changes in v3:
>> - drop forcing CONFIG_MIPS_BOOT_* selection in mach-pic32/Kconfig
>> - indent assembly instructions in delay slot
>> - made GPIO-nodes child of pinctrl-node in devicetree
>> - replace pic32_ioremap() with ioremap()
>>
>> Changes in v2:
>> - drop board_early_init_f
>> - use macro LEAF(), END() for lowlevel_init assembly
>> - move initialization of board_init_f() argument to common start.S
>> - move initdram() from board/microchip/ to mach-pic32/cpu.c
>> - remove MIPS virtual address in favor physical one in dts file
>>
>>  arch/mips/dts/pic32mzda.dtsi  | 153
>> ++
>>  arch/mips/mach-pic32/Kconfig  |  20 +++-
>>  arch/mips/mach-pic32/Makefile |   2 +-
>>  arch/mips/mach-pic32/cpu.c| 147
>> 
>>  arch/mips/mach-pic32/include/mach/pic32.h |   3 +
>>  arch/mips/mach-pic32/lowlevel_init.S  |  27 ++
>>  arch/mips/mach-pic32/reset.c  |  36 +++
>>  7 files changed, 386 insertions(+), 2 deletions(-)
>>  create mode 100644 arch/mips/dts/pic32mzda.dtsi
>>  create mode 100644 arch/mips/mach-pic32/lowlevel_init.S
>>  create mode 100644 arch/mips/mach-pic32/reset.c
>>
>> diff --git a/arch/mips/dts/pic32mzda.dtsi
>> b/arch/mips/dts/pic32mzda.dtsi
>> new file mode 100644
>> index 000..fe8b13a
>> --- /dev/null
>> +++ b/arch/mips/dts/pic32mzda.dtsi
>> @@ -0,0 +1,153 @@
>> +/*
>> + * Copyright 2015 Microchip Technology, Inc.
>> + * Purna Chandra Mandal, <purna.man...@microchip.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include "skeleton.dtsi"
>> +
>> +/ {
>> +compatible = "microchip,pic32mzda", "microchip,pic32mz";
>> +
>> +aliases {
>> +gpio0 = 
>> +gpio1 = 
>> +gpio2 = 
>> +gpio3 = 
>> +gpio4 = 
>> +gpio5 = 
>> +gpio6 = 
>> +gpio7 = 
>> +gpio8 = 
>> +gpio9 = 
>> +};
>> +
>> +cpus {
>> +cpu@0 {
>> +compatible = "mips,mips14kc";
>> +};
>> +};
>> +
>> +clock: clk@1f801200 {
>> +compatible = "microchip,pic32mzda_clk";
>> +reg = <0x1f801200 0x1000>;
>> +clock-cells = <1>;
>> +};
>> +
>> +uart1: serial@1f822000 {
>> +compatible = "microchip,pic32mzda-uart";
>> +reg = <0x1f822000 0x50>;
>> +interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
>> +status = "disabled";
>> +clocks = < PB2CLK>;
>> +};
>> +
>> +uart2: serial@1f822200 {
>> +compatible = "microchip,pic32mzda-uart";
>> +reg = <0x1f822200 0x50>;
>> +interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
>> +clocks = < PB2CLK>;
>> +status = "disabled";
>> +};
>> +
>> +uart6: serial@1f822a00 {
>> +compatible = "microchip,pic32mzda-uart";
>> +reg = <0x1f822a00 0x50>;
>> +interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
>> +clocks = < PB2CLK>;
>> +status = "disabled";
>> +};
>> +
>> +evic: interrupt-controller@1f81 {
>> +compatible = "microchip,pic32mzda-evic";
>> +interrupt-controller;
>> +#interrupt-cells = <2>;
>> +reg = <0x1f81 0x1000>;
>> +};
>> +
>> +pinctrl: pinctrl@1f801400 {
>> +compatible = "microchip,pic32mzda-pinctrl";
>> +reg = <0x1f801400 0x100>, /* in  */
>> +  <0x1f801500 0x200>, /* out */
>> +  <0x1f86 0xa00>; /* port */
>> +reg-names = "ppsin","ppsout","port";
>> +status = "dis

Re: [U-Boot] [PATCH v3 06/14] drivers: serial: add driver for Microchip PIC32 UART controller.

[Purna Chandra Mandal]

On 01/14/2016 01:39 AM, Simon Glass wrote:

> Hi Purna,
>
> On 12 January 2016 at 03:18, Purna Chandra Mandal
> <purna.man...@microchip.com> wrote:
>> From: Paul Thacker <paul.thac...@microchip.com>
>>
>> This adds PIC32 UART controller support based on driver model.
>>
>> Signed-off-by: Paul Thacker <paul.thac...@microchip.com>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>
>>
>> ---
>>
>> Changes in v3:
>> - remove ofdata_to_platdata, and replace platdata with priv
>> - remove special handling of '\r' as being handled by serial-uclass
>> - remove loop to wait for space in tx buffer before pumping char
>>
>> Changes in v2:
>> - fix missing/corrupted chars during baud rate change
>> - remove loop until any char is avaialbale in getc()
>>
>>  .../serial/microchip,pic32-uart.txt|   5 +
>>  drivers/serial/Kconfig |  13 ++
>>  drivers/serial/Makefile|   1 +
>>  drivers/serial/serial_pic32.c  | 199 
>> +
>>  4 files changed, 218 insertions(+)
>>  create mode 100644 doc/device-tree-bindings/serial/microchip,pic32-uart.txt
>>  create mode 100644 drivers/serial/serial_pic32.c
>>
> Reviewed-by: Simon Glass <s...@chromium.org>
>
> One nit/question below.
>
>> diff --git a/doc/device-tree-bindings/serial/microchip,pic32-uart.txt 
>> b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt
>> new file mode 100644
>> index 000..f00e215
>> --- /dev/null
>> +++ b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt
>> @@ -0,0 +1,5 @@
>> +* Microchip PIC32 serial UART
>> +
>> +Required properties:
>> +- compatible: must be "microchip,pic32mzda-uart".
>> +- reg: exactly one register range.
>> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
>> index 1fc287e..9763ea1 100644
>> --- a/drivers/serial/Kconfig
>> +++ b/drivers/serial/Kconfig
>> @@ -107,6 +107,14 @@ config DEBUG_UART_APBUART
>>   will need to provide parameters to make this work. The driver will
>>   be available until the real driver model serial is running.
>>
>> +config DEBUG_UART_PIC32
>> +   bool "Microchip PIC32"
>> +   help
>> + Select this to enable a debug UART using the serial_pic32 driver. 
>> You
>> + will need to provide parameters to make this work. The driver will
>> + be available until the real driver model serial is running.
>> +
>> +
>>  endchoice
>>
>>  config DEBUG_UART_BASE
>> @@ -223,4 +231,9 @@ config UNIPHIER_SERIAL
>>   If you have a UniPhier based board and want to use the on-chip
>>   serial ports, say Y to this option. If unsure, say N.
>>
>> +config PIC32_SERIAL
>> +   bool "Support for Microchip PIC32 on-chip UART"
>> +   help
>> + Support for the UART found on Microchip PIC32 SoC's.
>> +
>>  endmenu
>> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
>> index dd87147..57cd38b 100644
>> --- a/drivers/serial/Makefile
>> +++ b/drivers/serial/Makefile
>> @@ -41,6 +41,7 @@ obj-$(CONFIG_MXS_AUART) += mxs_auart.o
>>  obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
>>  obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
>>  obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
>> +obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
>>
>>  ifndef CONFIG_SPL_BUILD
>>  obj-$(CONFIG_USB_TTY) += usbtty.o
>> diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c
>> new file mode 100644
>> index 000..ee9d056
>> --- /dev/null
>> +++ b/drivers/serial/serial_pic32.c
>> @@ -0,0 +1,199 @@
>> +/*
>> + * (c) 2015 Paul Thacker <paul.thac...@microchip.com>
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + *
>> + */
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +/* UART Control Registers */
>> +#define U_MOD  0x00
>> +#define U_MODCLR   (U_MOD + _CLR_OFFSET)
>> +#define U_MODSET   (U_MOD + _SET_OFFSET)
>> +#define U_STA  0x10
>> +#define U_STACLR   (U_STA + _CLR_OFFSET)
>> +#define U_STASET   (U_STA + _SET_OFFSET)
>> +#define U_TXR  0x20
>> +#define U_RXR  0x30
>> +#define U_BRG  0x40
>>

Re: [U-Boot] [PATCH v3 05/14] drivers: gpio: add driver for Microchip PIC32 GPIO controller.

[Purna Chandra Mandal]

On 01/13/2016 07:38 PM, Daniel Schwierzeck wrote:

> Am Mittwoch, den 13.01.2016, 14:46 +0100 schrieb Daniel Schwierzeck:
>> Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra
>> Mandal:
>>> In PIC32 GPIO controller is part of PIC32 pin controller.
>>> PIC32 has ten independently programmable ports and each with
>>> multiple
>>> pins.
>>> Each of these pins can be configured and used as GPIO, provided
>>> they
>>> are not in use for other peripherals.
>>>
>>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>> Reviewed-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
>>
>> nits below
>>
>>> ---
>>>
>>> Changes in v3:
>>> - add check on dev_get_addr()
>>>
>>> Changes in v2: None
>>>
>>>  drivers/gpio/Kconfig  |   7 ++
>>>  drivers/gpio/Makefile |   2 +-
>>>  drivers/gpio/pic32_gpio.c | 175
>>> ++
>>>  3 files changed, 183 insertions(+), 1 deletion(-)
>>>  create mode 100644 drivers/gpio/pic32_gpio.c
>>>
>>> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
>>> index e60e9fd..13e9a6a 100644
>>> --- a/drivers/gpio/Kconfig
>>> +++ b/drivers/gpio/Kconfig
>>> @@ -83,4 +83,11 @@ config VYBRID_GPIO
>>> help
>>>   Say yes here to support Vybrid vf610 GPIOs.
>>>  
>>> +config PIC32_GPIO
>>> +   bool "Microchip PIC32 GPIO driver"
>>> +   depends on DM_GPIO
>>> +   default y if MACH_PIC32
> this should be
>
> depends on DM_GPIO && MACH_PIC32

ack, will add.

>>> +   help
>>> + Say yes here to support Microchip PIC32 GPIOs.
>>> +
>>>  endmenu
>>> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
>>> index fb4fd25..845a6d4 100644
>>> --- a/drivers/gpio/Makefile
>>> +++ b/drivers/gpio/Makefile
>>> @@ -46,4 +46,4 @@ obj-$(CONFIG_STM32_GPIO)  += stm32_gpio.o
>>>  obj-$(CONFIG_ZYNQ_GPIO)+= zynq_gpio.o
>>>  obj-$(CONFIG_VYBRID_GPIO)  += vybrid_gpio.o
>>>  obj-$(CONFIG_HIKEY_GPIO)   += hi6220_gpio.o
>>> -
>>> +obj-$(CONFIG_PIC32_GPIO)   += pic32_gpio.o
>>> diff --git a/drivers/gpio/pic32_gpio.c b/drivers/gpio/pic32_gpio.c
>>> new file mode 100644
>>> index 000..5b23af4
>>> --- /dev/null
>>> +++ b/drivers/gpio/pic32_gpio.c
>>> @@ -0,0 +1,175 @@
>>> +/*
>>> + * Copyright (c) 2015 Microchip Technology Inc
>>> + * Purna Chandra Mandal <purna.man...@microchip.com>
>>> + *
>>> + * SPDX-License-Identifier:GPL-2.0+
>>> + */
>>> +
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +/* Peripheral Pin Control */
>>> +struct pic32_reg_port {
>>> +   struct pic32_reg_atomic ansel;
>>> +   struct pic32_reg_atomic tris;
>>> +   struct pic32_reg_atomic port;
>>> +   struct pic32_reg_atomic lat;
>>> +   struct pic32_reg_atomic open_drain;
>>> +   struct pic32_reg_atomic cnpu;
>>> +   struct pic32_reg_atomic cnpd;
>>> +   struct pic32_reg_atomic cncon;
>>> +};
>>> +
>>> +enum {
>>> +   MICROCHIP_GPIO_DIR_OUT,
>>> +   MICROCHIP_GPIO_DIR_IN,
>>> +   MICROCHIP_GPIOS_PER_BANK = 16,
>>> +};
>>> +
>>> +struct pic32_gpio_priv {
>>> +   struct pic32_reg_port *regs;
>>> +   char name[2];
>>> +};
>>> +
>>> +static int pic32_gpio_get_value(struct udevice *dev, unsigned
>>> offset)
>>> +{
>>> +   struct pic32_gpio_priv *priv = dev_get_priv(dev);
>>> +
>>> +   return !!(readl(>regs->port.raw) & BIT(offset));
>>> +}
>>> +
>>> +static int pic32_gpio_set_value(struct udevice *dev, unsigned
>>> offset,
>>> +   int value)
>>> +{
>>> +   struct pic32_gpio_priv *priv = dev_get_priv(dev);
>>> +   int mask = BIT(offset);
>>> +
>>> +   if (value)
>>> +   writel(mask, >regs->port.set);
>>> +   else
>>> +   writel(mask, >regs->port.clr);
>>> +
>>> +   return 0;
>>> +}
>>> +
>&g

Re: [U-Boot] [PATCH v3 06/14] drivers: serial: add driver for Microchip PIC32 UART controller.

[Purna Chandra Mandal]

On 01/13/2016 07:33 PM, Daniel Schwierzeck wrote:

> Am Mittwoch, den 13.01.2016, 14:49 +0100 schrieb Daniel Schwierzeck:
>> Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra
>> Mandal:
>>> From: Paul Thacker <paul.thac...@microchip.com>
>>>
>>> This adds PIC32 UART controller support based on driver model.
>>>
>>> Signed-off-by: Paul Thacker <paul.thac...@microchip.com>
>>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>>
>> Reviewed-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
>>
>> nits below
> I forgot one thing
>>> ---
>>>
>>> Changes in v3:
>>> - remove ofdata_to_platdata, and replace platdata with priv
>>> - remove special handling of '\r' as being handled by serial-uclass
>>> - remove loop to wait for space in tx buffer before pumping char
>>>
>>> Changes in v2:
>>> - fix missing/corrupted chars during baud rate change
>>> - remove loop until any char is avaialbale in getc()
>>>
>>>  .../serial/microchip,pic32-uart.txt|   5 +
>>>  drivers/serial/Kconfig |  13 ++
>>>  drivers/serial/Makefile|   1 +
>>>  drivers/serial/serial_pic32.c  | 199
>>> +
>>>  4 files changed, 218 insertions(+)
>>>  create mode 100644 doc/device-tree-bindings/serial/microchip,pic32
>>> -uart.txt
>>>  create mode 100644 drivers/serial/serial_pic32.c
>>>
>>> diff --git a/doc/device-tree-bindings/serial/microchip,pic32
>>> -uart.txt
>>> b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt
>>> new file mode 100644
>>> index 000..f00e215
>>> --- /dev/null
>>> +++ b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt
>>> @@ -0,0 +1,5 @@
>>> +* Microchip PIC32 serial UART
>>> +
>>> +Required properties:
>>> +- compatible: must be "microchip,pic32mzda-uart".
>>> +- reg: exactly one register range.
>>> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
>>> index 1fc287e..9763ea1 100644
>>> --- a/drivers/serial/Kconfig
>>> +++ b/drivers/serial/Kconfig
>>> @@ -107,6 +107,14 @@ config DEBUG_UART_APBUART
>>>   will need to provide parameters to make this work. The
>>> driver will
>>>   be available until the real driver model serial is
>>> running.
>>>  
>>> +config DEBUG_UART_PIC32
>>> +   bool "Microchip PIC32"
>>> +   help
>>> + Select this to enable a debug UART using the
>>> serial_pic32
>>> driver. You
>>> + will need to provide parameters to make this work. The
>>> driver will
>>> + be available until the real driver model serial is
>>> running.
>>> +
>>> +
>>>  endchoice
>>>  
>>>  config DEBUG_UART_BASE
>>> @@ -223,4 +231,9 @@ config UNIPHIER_SERIAL
>>>   If you have a UniPhier based board and want to use the
>>> on
>>> -chip
>>>   serial ports, say Y to this option. If unsure, say N.
>>>  
>>> +config PIC32_SERIAL
>>> +   bool "Support for Microchip PIC32 on-chip UART"
> you should add
>
> depends on DM_SERIAL && MACH_PIC32

ack. Will add.

>>> +   help
>>> + Support for the UART found on Microchip PIC32 SoC's.
>>> +
>>>  endmenu
>>> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
>>> index dd87147..57cd38b 100644
>>> --- a/drivers/serial/Makefile
>>> +++ b/drivers/serial/Makefile
>>> @@ -41,6 +41,7 @@ obj-$(CONFIG_MXS_AUART) += mxs_auart.o
>>>  obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
>>>  obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
>>>  obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
>>> +obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
>>>  
>>>  ifndef CONFIG_SPL_BUILD
>>>  obj-$(CONFIG_USB_TTY) += usbtty.o
>>> diff --git a/drivers/serial/serial_pic32.c
>>> b/drivers/serial/serial_pic32.c
>>> new file mode 100644
>>> index 000..ee9d056
>>> --- /dev/null
>>> +++ b/drivers/serial/serial_pic32.c
>>> @@ -0,0 +1,199 @@
>>> +/*
>>> + * (c) 2015 Paul Thacker <paul.thac...@microchip.com>
>>> + *
>>> + * SPDX-License-Identifier:GPL-2.0+
>>> + *
>>> + */
>>> +#include 

Re: [U-Boot] [PATCH v3 09/14] board: Add Microchip PIC32MZ[DA]-Starter-Kit board.

[Purna Chandra Mandal]

On 01/13/2016 08:26 PM, Tom Rini wrote:
> On Tue, Jan 12, 2016 at 03:48:24PM +0530, Purna Chandra Mandal wrote:
>
>> This adds support for Microchip PIC32MZ[DA] StarterKit board
>> based on a PIC32MZ[DA] family of microcontroller.
>>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
> [snip]
>> diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
>> new file mode 100644
>> index 000..3483eb0
>> --- /dev/null
>> +++ b/configs/pic32mzdask_defconfig
>> @@ -0,0 +1,416 @@
>> +#
>> +# Automatically generated file; DO NOT EDIT.
>> +# U-Boot 2016.01-rc3 Configuration
> Please use 'make savedefconfig' to generate this file instead, it will
> be much smaller (and this is also what you do with the linux kernel).

ack. Will do.

>> +++ b/include/configs/pic32mzdask.h
> [snip]
>> +#define CONFIG_SYS_BAUDRATE_TABLE   {9600, 19200, 38400, 57600, 115200}
> I think you can use the default here.

ack. Will drop this to use fallback one.


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[U-Boot] [PATCH v3 04/14] drivers: pinctrl: Add pinctrl driver for Microchip PIC32.

[Purna Chandra Mandal]

In PIC32 pin-controller is a combined gpio-controller, pin-mux and
pin-config module. Remappable peripherals are assigned pins through
per-pin based muxing logic. And pin configuration are performed on
specific port registers which are shared along with gpio controller.
Note, non-remappable peripherals have default pins assigned thus require
no muxing.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>


---

Changes in v3:
- read register base from device-tree
- add/update comments to explain how pinctrl'r works.
- replace pic32_ioremap() with ioremap().

Changes in v2:
- add pinconf routine for configuring pin property

 drivers/pinctrl/Kconfig |   9 +
 drivers/pinctrl/Makefile|   1 +
 drivers/pinctrl/pinctrl_pic32.c | 363 
 3 files changed, 373 insertions(+)
 create mode 100644 drivers/pinctrl/pinctrl_pic32.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 57e6142..292c4e2 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -131,6 +131,15 @@ config PINCTRL_SANDBOX
  actually does nothing but print debug messages when pinctrl
  operations are invoked.
 
+config PIC32_PINCTRL
+   bool "Microchip PIC32 pin-control and pin-mux driver"
+   depends on DM && MACH_PIC32
+   help
+ Supports individual pin selection and configuration for each 
remappable
+ peripheral available on Microchip PIC32 SoCs. This driver is 
controlled
+ by a device tree node which contains both GPIO defintion and pin 
control
+ functions.
+
 endif
 
 source "drivers/pinctrl/uniphier/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 70d25dc..b4f4650 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
 obj-$(CONFIG_PINCTRL_SANDBOX)  += pinctrl-sandbox.o
 
 obj-$(CONFIG_ARCH_UNIPHIER)+= uniphier/
+obj-$(CONFIG_PIC32_PINCTRL)+= pinctrl_pic32.o
diff --git a/drivers/pinctrl/pinctrl_pic32.c b/drivers/pinctrl/pinctrl_pic32.c
new file mode 100644
index 000..5cf97ec
--- /dev/null
+++ b/drivers/pinctrl/pinctrl_pic32.c
@@ -0,0 +1,363 @@
+/*
+ * Pinctrl driver for Microchip PIC32 SoCs
+ * Copyright (c) 2015 Microchip Technology Inc.
+ * Written by Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* PIC32 has 10 peripheral ports with 16 pins each.
+ * Ports are marked PORTA-PORTK or PORT0-PORT9.
+ */
+enum {
+   PIC32_PORT_A = 0,
+   PIC32_PORT_B = 1,
+   PIC32_PORT_C = 2,
+   PIC32_PORT_D = 3,
+   PIC32_PORT_E = 4,
+   PIC32_PORT_F = 5,
+   PIC32_PORT_G = 6,
+   PIC32_PORT_H = 7,
+   PIC32_PORT_J = 8, /* no PORT_I */
+   PIC32_PORT_K = 9,
+   PIC32_PINS_PER_PORT = 16,
+};
+
+#define PIN_CONFIG_PIC32_DIGITAL   (PIN_CONFIG_END + 1)
+#define PIN_CONFIG_PIC32_ANALOG(PIN_CONFIG_END + 2)
+
+/* pin configuration descriptor */
+struct pic32_pin_config {
+   u16 port;   /* port number */
+   u16 pin;/* pin number in the port */
+   u32 config; /* one of PIN_CONFIG_* */
+};
+#define PIN_CONFIG(_prt, _pin, _cfg) \
+   {.port = (_prt), .pin = (_pin), .config = (_cfg), }
+
+/* In PIC32 muxing is performed at pin-level through two
+ * different set of registers - one set for input functions,
+ * and other for output functions.
+ * Pin configuration is handled through port register.
+ */
+/* Port control registers */
+struct pic32_reg_port {
+   struct pic32_reg_atomic ansel;
+   struct pic32_reg_atomic tris;
+   struct pic32_reg_atomic port;
+   struct pic32_reg_atomic lat;
+   struct pic32_reg_atomic odc;
+   struct pic32_reg_atomic cnpu;
+   struct pic32_reg_atomic cnpd;
+   struct pic32_reg_atomic cncon;
+   struct pic32_reg_atomic unused[8];
+};
+
+/* Input function mux registers */
+struct pic32_reg_in_mux {
+   u32 unused0;
+   u32 int1[4];
+   u32 unused1;
+   u32 t2ck[8];
+   u32 ic1[9];
+   u32 unused2;
+   u32 ocfar;
+   u32 unused3;
+   u32 u1rx;
+   u32 u1cts;
+   u32 u2rx;
+   u32 u2cts;
+   u32 u3rx;
+   u32 u3cts;
+   u32 u4rx;
+   u32 u4cts;
+   u32 u5rx;
+   u32 u5cts;
+   u32 u6rx;
+   u32 u6cts;
+   u32 unused4;
+   u32 sdi1;
+   u32 ss1;
+   u32 unused5;
+   u32 sdi2;
+   u32 ss2;
+   u32 unused6;
+   u32 sdi3;
+   u32 ss3;
+   u32 unused7;
+   u32 sdi4;
+   u32 ss4;
+   u32 unused8;
+   u32 sdi5;
+   u32 ss5;
+   u32 unused9;
+   u32 sdi6;
+   u32 ss6;
+   u32 c1rx;
+   u32 c2rx;
+   u32 refclki1;
+   u32 refclki2;
+   u32 refclki3;
+   u32 refclki4;
+};
+
+/

[U-Boot] [PATCH v3 05/14] drivers: gpio: add driver for Microchip PIC32 GPIO controller.

[Purna Chandra Mandal]

In PIC32 GPIO controller is part of PIC32 pin controller.
PIC32 has ten independently programmable ports and each with multiple pins.
Each of these pins can be configured and used as GPIO, provided they
are not in use for other peripherals.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

Changes in v3:
- add check on dev_get_addr()

Changes in v2: None

 drivers/gpio/Kconfig  |   7 ++
 drivers/gpio/Makefile |   2 +-
 drivers/gpio/pic32_gpio.c | 175 ++
 3 files changed, 183 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpio/pic32_gpio.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index e60e9fd..13e9a6a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -83,4 +83,11 @@ config VYBRID_GPIO
help
  Say yes here to support Vybrid vf610 GPIOs.
 
+config PIC32_GPIO
+   bool "Microchip PIC32 GPIO driver"
+   depends on DM_GPIO
+   default y if MACH_PIC32
+   help
+ Say yes here to support Microchip PIC32 GPIOs.
+
 endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fb4fd25..845a6d4 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -46,4 +46,4 @@ obj-$(CONFIG_STM32_GPIO)  += stm32_gpio.o
 obj-$(CONFIG_ZYNQ_GPIO)+= zynq_gpio.o
 obj-$(CONFIG_VYBRID_GPIO)  += vybrid_gpio.o
 obj-$(CONFIG_HIKEY_GPIO)   += hi6220_gpio.o
-
+obj-$(CONFIG_PIC32_GPIO)   += pic32_gpio.o
diff --git a/drivers/gpio/pic32_gpio.c b/drivers/gpio/pic32_gpio.c
new file mode 100644
index 000..5b23af4
--- /dev/null
+++ b/drivers/gpio/pic32_gpio.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2015 Microchip Technology Inc
+ * Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Peripheral Pin Control */
+struct pic32_reg_port {
+   struct pic32_reg_atomic ansel;
+   struct pic32_reg_atomic tris;
+   struct pic32_reg_atomic port;
+   struct pic32_reg_atomic lat;
+   struct pic32_reg_atomic open_drain;
+   struct pic32_reg_atomic cnpu;
+   struct pic32_reg_atomic cnpd;
+   struct pic32_reg_atomic cncon;
+};
+
+enum {
+   MICROCHIP_GPIO_DIR_OUT,
+   MICROCHIP_GPIO_DIR_IN,
+   MICROCHIP_GPIOS_PER_BANK = 16,
+};
+
+struct pic32_gpio_priv {
+   struct pic32_reg_port *regs;
+   char name[2];
+};
+
+static int pic32_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+   struct pic32_gpio_priv *priv = dev_get_priv(dev);
+
+   return !!(readl(>regs->port.raw) & BIT(offset));
+}
+
+static int pic32_gpio_set_value(struct udevice *dev, unsigned offset,
+   int value)
+{
+   struct pic32_gpio_priv *priv = dev_get_priv(dev);
+   int mask = BIT(offset);
+
+   if (value)
+   writel(mask, >regs->port.set);
+   else
+   writel(mask, >regs->port.clr);
+
+   return 0;
+}
+
+static int pic32_gpio_direction(struct udevice *dev, unsigned offset)
+{
+   struct pic32_gpio_priv *priv = dev_get_priv(dev);
+
+   if (readl(>regs->ansel.raw) & BIT(offset))
+   return -1;
+
+   if (readl(>regs->tris.raw) & BIT(offset))
+   return MICROCHIP_GPIO_DIR_IN;
+   else
+   return MICROCHIP_GPIO_DIR_OUT;
+}
+
+static int pic32_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+   struct pic32_gpio_priv *priv = dev_get_priv(dev);
+   int mask = BIT(offset);
+
+   writel(mask, >regs->ansel.clr);
+   writel(mask, >regs->tris.set);
+
+   return 0;
+}
+
+static int pic32_gpio_direction_output(struct udevice *dev,
+  unsigned offset, int value)
+{
+   struct pic32_gpio_priv *priv = dev_get_priv(dev);
+   int mask = BIT(offset);
+
+   writel(mask, >regs->ansel.clr);
+   writel(mask, >regs->tris.clr);
+
+   pic32_gpio_set_value(dev, offset, value);
+   return 0;
+}
+
+static int pic32_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+   struct fdtdec_phandle_args *args)
+{
+   desc->offset = args->args[0];
+   desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+   return 0;
+}
+
+static int pic32_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+   int ret = GPIOF_UNUSED;
+
+   switch (pic32_gpio_direction(dev, offset)) {
+   case MICROCHIP_GPIO_DIR_OUT:
+   ret = GPIOF_OUTPUT;
+   break;
+   case MICROCHIP_GPIO_DIR_IN:
+   ret = GPIOF_INPUT;
+   break;
+   default:
+   ret = GPIOF_UNUSED;
+   break;
+   }
+   return ret;
+}
+
+static 

[U-Boot] [PATCH v3 07/14] drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.

[Purna Chandra Mandal]

This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy 
module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).

Signed-off-by: Paul Thacker <paul.thac...@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>


---

Changes in v3:
- annotating fixed table with const
- fix camel-case in ddr2 timing parameters
- fix cmd index parameter of host_load_cmd().
- fix compilation warning

Changes in v2:
- move ddr2 initialization from board/microchip/ to drivers/ddr/microchip

 arch/mips/mach-pic32/include/mach/ddr.h |  32 
 drivers/Makefile|   1 +
 drivers/ddr/microchip/Makefile  |   6 +
 drivers/ddr/microchip/ddr2.c| 278 
 drivers/ddr/microchip/ddr2_regs.h   | 148 +
 drivers/ddr/microchip/ddr2_timing.h |  65 
 6 files changed, 530 insertions(+)
 create mode 100644 arch/mips/mach-pic32/include/mach/ddr.h
 create mode 100644 drivers/ddr/microchip/Makefile
 create mode 100644 drivers/ddr/microchip/ddr2.c
 create mode 100644 drivers/ddr/microchip/ddr2_regs.h
 create mode 100644 drivers/ddr/microchip/ddr2_timing.h

diff --git a/arch/mips/mach-pic32/include/mach/ddr.h 
b/arch/mips/mach-pic32/include/mach/ddr.h
new file mode 100644
index 000..00abfa3
--- /dev/null
+++ b/arch/mips/mach-pic32/include/mach/ddr.h
@@ -0,0 +1,32 @@
+/*
+ * (c) 2015 Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#ifndef __MICROCHIP_PIC32_DDR_H
+#define __MICROCHIP_PIC32_DDR_H
+
+/* called by initdram() function */
+void ddr2_phy_init(void);
+void ddr2_ctrl_init(void);
+phys_size_t ddr2_calculate_size(void);
+
+/* Maximum number of agents */
+#define NUM_AGENTS 5
+
+/* Board can provide agent specific parameters for arbitration by
+ * filling struct ddr2_arbiter_params for all the agents and
+ * implementing board_get_ddr_arbiter_params() to return the filled
+ * structure.
+ */
+struct ddr2_arbiter_params {
+   u32 min_limit;  /* min bursts to execute per arbitration */
+   u32 req_period; /* request period threshold for accepted cmds */
+   u32 min_cmd_acpt; /* min number of accepted cmds */
+};
+
+const struct ddr2_arbiter_params *board_get_ddr_arbiter_params(void);
+
+#endif /* __MICROCHIP_PIC32_DDR_H */
diff --git a/drivers/Makefile b/drivers/Makefile
index c9031f2..0ab54d9 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -68,4 +68,5 @@ obj-y += soc/
 obj-$(CONFIG_REMOTEPROC) += remoteproc/
 obj-y += thermal/
 
+obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
 endif
diff --git a/drivers/ddr/microchip/Makefile b/drivers/ddr/microchip/Makefile
new file mode 100644
index 000..305c48b
--- /dev/null
+++ b/drivers/ddr/microchip/Makefile
@@ -0,0 +1,6 @@
+#
+# Copyright (C) 2015 Microchip Technology Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+obj-$(CONFIG_MACH_PIC32) += ddr2.o
diff --git a/drivers/ddr/microchip/ddr2.c b/drivers/ddr/microchip/ddr2.c
new file mode 100644
index 000..6056418
--- /dev/null
+++ b/drivers/ddr/microchip/ddr2.c
@@ -0,0 +1,278 @@
+/*
+ * (c) 2015 Paul Thacker <paul.thac...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "ddr2_regs.h"
+#include "ddr2_timing.h"
+
+/* init DDR2 Phy */
+void ddr2_phy_init(void)
+{
+   struct ddr2_phy_regs *ddr2_phy;
+   u32 pad_ctl;
+
+   ddr2_phy = ioremap(PIC32_DDR2P_BASE, sizeof(*ddr2_phy));
+
+   /* PHY_DLL_RECALIB */
+   writel(DELAY_START_VAL(3) | DISABLE_RECALIB(0) |
+  RECALIB_CNT(0x10), _phy->dll_recalib);
+
+   /* PHY_PAD_CTRL */
+   pad_ctl = ODT_SEL | ODT_EN | DRIVE_SEL(0) |
+ ODT_PULLDOWN(2) | ODT_PULLUP(3) |
+ EXTRA_OEN_CLK(0) | NOEXT_DLL |
+ DLR_DFT_WRCMD | HALF_RATE |
+ DRVSTR_PFET(0xe) | DRVSTR_NFET(0xe) |
+ RCVR_EN | PREAMBLE_DLY(2);
+   writel(pad_ctl, _phy->pad_ctrl);
+
+   /* SCL_CONFIG_0 */
+   writel(SCL_BURST8 | SCL_DDR_CONNECTED | SCL_RCAS_LAT(RL) |
+  SCL_ODTCSWW, _phy->scl_config_1);
+
+   /* SCL_CONFIG_1 */
+   writel(SCL_CSEN | SCL_WCAS_LAT(WL), _phy->scl_config_2);
+
+   /* SCL_LAT */
+   writel(SCL_CAPCLKDLY(3) | SCL_DDRCLKDLY(4), _phy->scl_latency);
+}
+
+/* start phy self calibration logic */
+static int ddr2_phy_calib_start(void)
+{
+   struct ddr2_phy_regs *ddr2_phy;
+
+   ddr2_phy = ioremap(PIC32_DDR2P_BASE, sizeof(*ddr2_phy));
+
+   /* DDR Phy SCL Start */
+   writel(SCL_START | SCL_EN, _phy->scl_start);
+
+   /* Wait for SCL for data byte to pass */
+   return wait_for_bit(__func__, _phy->scl_start, SCL_LUBPASS,
+   true, CONFIG_SYS_HZ, false);
+}
+
+/* DDR2 Controller initialization */
+
+/* Target Agent Ar

[U-Boot] [PATCH v3 03/14] drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.

[Purna Chandra Mandal]

PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers
and dividers capable of supplying clock to various controllers
on or off-chip.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Reviewed-by: Simon Glass <s...@chromium.org>

---

Changes in v3:
- rename clk-pic32.c to clk_pic32.c
- update clock binding documentation
- replace pic32_ioremap() with ioremap()
- separate MPLL initialization constants

Changes in v2:
- add mpll get clock rate

 .../clock/microchip,pic32-clock.txt|  33 ++
 drivers/clk/Makefile   |   1 +
 drivers/clk/clk_pic32.c| 433 +
 include/dt-bindings/clock/microchip,clock.h|  29 ++
 4 files changed, 496 insertions(+)
 create mode 100644 doc/device-tree-bindings/clock/microchip,pic32-clock.txt
 create mode 100644 drivers/clk/clk_pic32.c
 create mode 100644 include/dt-bindings/clock/microchip,clock.h

diff --git a/doc/device-tree-bindings/clock/microchip,pic32-clock.txt 
b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
new file mode 100644
index 000..02e5ce4
--- /dev/null
+++ b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
@@ -0,0 +1,33 @@
+* Microchip PIC32 Clock and Oscillator
+
+Microchip PIC32 clock tree consists of few oscillators, PLLs,
+multiplexers and few divider modules capable of supplying clocks
+to various controllers within SoC and also to off-chip.
+
+PIC32 clock controller output is defined by indices as defined
+in [0]
+
+[0] include/dt-bindings/clock/microchip,clock.h
+
+Required Properties:
+- compatible: should be "microchip,pic32mzda_clk"
+- reg: physical base address of the controller and length of memory mapped
+   region.
+- #clock-cells: should be 1.
+
+Example: Clock controller node:
+
+   clock: clk@1f801200 {
+   compatible = "microchip,pic32mzda_clk";
+   reg = <0x1f801200 0x1000>;
+   };
+
+Example: UART controller node that consumes the clock generated by the clock
+controller:
+
+   uart1: serial@1f822000 {
+   compatible = "microchip,pic32mzda-uart";
+   reg = <0xbf822000 0x50>;
+   interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < PB2CLK>;
+   };
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 4a6a4a8..adda769 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_CLK) += clk-uclass.o
 obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
 obj-$(CONFIG_SANDBOX) += clk_sandbox.o
+obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
diff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c
new file mode 100644
index 000..bb0a1cf
--- /dev/null
+++ b/drivers/clk/clk_pic32.c
@@ -0,0 +1,433 @@
+/*
+ * Copyright (C) 2015 Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Primary oscillator */
+#define SYS_POSC_CLK_HZ2400
+
+/* FRC clk rate */
+#define SYS_FRC_CLK_HZ 800
+
+/* Clock Registers */
+#define OSCCON 0x
+#define OSCTUNE0x0010
+#define SPLLCON0x0020
+#define REFO1CON   0x0080
+#define REFO1TRIM  0x0090
+#define PB1DIV 0x0140
+
+/* SPLL */
+#define ICLK_MASK  0x0080
+#define PLLIDIV_MASK   0x0007
+#define PLLODIV_MASK   0x0007
+#define CUROSC_MASK0x0007
+#define PLLMUL_MASK0x007F
+#define FRCDIV_MASK0x0007
+
+/* PBCLK */
+#define PBDIV_MASK 0x0007
+
+/* SYSCLK MUX */
+#define SCLK_SRC_FRC1  0
+#define SCLK_SRC_SPLL  1
+#define SCLK_SRC_POSC  2
+#define SCLK_SRC_FRC2  7
+
+/* Reference Oscillator Control Reg fields */
+#define REFO_SEL_MASK  0x0f
+#define REFO_SEL_SHIFT 0
+#define REFO_ACTIVEBIT(8)
+#define REFO_DIVSW_EN  BIT(9)
+#define REFO_OEBIT(12)
+#define REFO_ONBIT(15)
+#define REFO_DIV_SHIFT 16
+#define REFO_DIV_MASK  0x7fff
+
+/* Reference Oscillator Trim Register Fields */
+#define REFO_TRIM_REG  0x10
+#define REFO_TRIM_MASK 0x1ff
+#define REFO_TRIM_SHIFT23
+#define REFO_TRIM_MAX  511
+
+#define ROCLK_SRC_SCLK 0x0
+#define ROCLK_SRC_SPLL 0x7
+#define ROCLK_SRC_ROCLKI   0x8
+
+/* Memory PLL */
+#define MPLL_IDIV  0x3f
+#define MPLL_MULT  0xff
+#define MPLL_ODIV1 0x7
+#define MPLL_ODIV2 0x7
+#define MPLL_VREG_RDY  BIT(23)
+#define MPLL_RDY   BIT(31)
+#define MPLL_IDIV_SHIFT0
+#define MPLL_MULT_SHIFT8
+#define MPLL_ODIV1_SHIFT   24
+#define MPLL_ODIV2_SHIFT   27
+#define MPLL_IDIV_INIT 0x03
+#define MPLL_MULT_INIT 0x32
+#define MPLL_ODIV1_INIT   

[U-Boot] [PATCH v3 01/14] MIPS: initialize board_init_f() argument to zero.

[Purna Chandra Mandal]

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---

Changes in v3: None
Changes in v2: None

 arch/mips/cpu/start.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index e95cdca..35d9650 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -185,6 +185,8 @@ reset:
PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset
sw  sp, 0(t0)
 #endif
+   /* Initialize args to zero */
+   movea0, zero
 
PTR_LA  t9, board_init_f
jr  t9
-- 
1.8.3.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v3 06/14] drivers: serial: add driver for Microchip PIC32 UART controller.

[Purna Chandra Mandal]

From: Paul Thacker <paul.thac...@microchip.com>

This adds PIC32 UART controller support based on driver model.

Signed-off-by: Paul Thacker <paul.thac...@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>


---

Changes in v3:
- remove ofdata_to_platdata, and replace platdata with priv
- remove special handling of '\r' as being handled by serial-uclass
- remove loop to wait for space in tx buffer before pumping char

Changes in v2:
- fix missing/corrupted chars during baud rate change
- remove loop until any char is avaialbale in getc()

 .../serial/microchip,pic32-uart.txt|   5 +
 drivers/serial/Kconfig |  13 ++
 drivers/serial/Makefile|   1 +
 drivers/serial/serial_pic32.c  | 199 +
 4 files changed, 218 insertions(+)
 create mode 100644 doc/device-tree-bindings/serial/microchip,pic32-uart.txt
 create mode 100644 drivers/serial/serial_pic32.c

diff --git a/doc/device-tree-bindings/serial/microchip,pic32-uart.txt 
b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt
new file mode 100644
index 000..f00e215
--- /dev/null
+++ b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt
@@ -0,0 +1,5 @@
+* Microchip PIC32 serial UART
+
+Required properties:
+- compatible: must be "microchip,pic32mzda-uart".
+- reg: exactly one register range.
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 1fc287e..9763ea1 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -107,6 +107,14 @@ config DEBUG_UART_APBUART
  will need to provide parameters to make this work. The driver will
  be available until the real driver model serial is running.
 
+config DEBUG_UART_PIC32
+   bool "Microchip PIC32"
+   help
+ Select this to enable a debug UART using the serial_pic32 driver. You
+ will need to provide parameters to make this work. The driver will
+ be available until the real driver model serial is running.
+
+
 endchoice
 
 config DEBUG_UART_BASE
@@ -223,4 +231,9 @@ config UNIPHIER_SERIAL
  If you have a UniPhier based board and want to use the on-chip
  serial ports, say Y to this option. If unsure, say N.
 
+config PIC32_SERIAL
+   bool "Support for Microchip PIC32 on-chip UART"
+   help
+ Support for the UART found on Microchip PIC32 SoC's.
+
 endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index dd87147..57cd38b 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_MXS_AUART) += mxs_auart.o
 obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
 obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
 obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
+obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c
new file mode 100644
index 000..ee9d056
--- /dev/null
+++ b/drivers/serial/serial_pic32.c
@@ -0,0 +1,199 @@
+/*
+ * (c) 2015 Paul Thacker <paul.thac...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* UART Control Registers */
+#define U_MOD  0x00
+#define U_MODCLR   (U_MOD + _CLR_OFFSET)
+#define U_MODSET   (U_MOD + _SET_OFFSET)
+#define U_STA  0x10
+#define U_STACLR   (U_STA + _CLR_OFFSET)
+#define U_STASET   (U_STA + _SET_OFFSET)
+#define U_TXR  0x20
+#define U_RXR  0x30
+#define U_BRG  0x40
+
+/* U_MOD bits */
+#define UART_ENABLEBIT(15)
+
+/* U_STA bits */
+#define UART_RX_ENABLE BIT(12)
+#define UART_TX_BRKBIT(11)
+#define UART_TX_ENABLE BIT(10)
+#define UART_TX_FULL   BIT(9)
+#define UART_TX_EMPTY  BIT(8)
+#define UART_RX_OERR   BIT(1)
+#define UART_RX_DATA_AVAIL BIT(0)
+
+struct pic32_uart_priv {
+   void __iomem *base;
+   ulong uartclk;
+};
+
+/*
+ * Initialize the serial port with the given baudrate.
+ * The settings are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int pic32_serial_init(void __iomem *base, ulong clk, u32 baudrate)
+{
+   u32 div = DIV_ROUND_CLOSEST(clk, baudrate * 16);
+
+   /* wait for TX FIFO to empty */
+   wait_for_bit(__func__, base + U_STA, UART_TX_EMPTY,
+true, CONFIG_SYS_HZ, false);
+
+   /* send break */
+   writel(UART_TX_BRK, base + U_STASET);
+
+   /* disable and clear mode */
+   writel(0, base + U_MOD);
+   writel(0, base + U_STA);
+
+   /* set baud rate generator */
+   writel(div - 1, base + U_BRG);
+
+   /* enable the UART for TX and RX */
+   writel(UART_TX_ENABLE | UART_RX_ENABLE, base + U_STASET);
+
+   /* enable the UART */
+   

[U-Boot] [PATCH v3 02/14] MIPS: initial infrastructure for Microchip PIC32 architecture

[Purna Chandra Mandal]

Create initial directory, Kconfigs needed for PIC32 architecture
support. Also add PIC32 specific register definition required for drivers.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

Changes in v3:
- drop empty choices in mach-pic32/Kconfig
- add pic32_get_syscfg_base() for device-config registers

Changes in v2:
- move PIC32 specific headers to arch/mips/mach-pic32/include/mach/
- define register-base as physical address
- drop CONFIG_PIC32_SUPPORTS_FDT_BOOT

 arch/mips/Kconfig |  6 +++
 arch/mips/Makefile|  1 +
 arch/mips/mach-pic32/Kconfig  |  7 +++
 arch/mips/mach-pic32/Makefile |  7 +++
 arch/mips/mach-pic32/cpu.c| 13 ++
 arch/mips/mach-pic32/include/mach/pic32.h | 76 +++
 6 files changed, 110 insertions(+)
 create mode 100644 arch/mips/mach-pic32/Kconfig
 create mode 100644 arch/mips/mach-pic32/Makefile
 create mode 100644 arch/mips/mach-pic32/cpu.c
 create mode 100644 arch/mips/mach-pic32/include/mach/pic32.h

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1b39c4c..380ed81 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -54,6 +54,11 @@ config TARGET_PB1X00
select SYS_MIPS_CACHE_INIT_RAM_LOAD
select MIPS_TUNE_4KC
 
+config MACH_PIC32
+   bool "Support Microchip PIC32"
+   select OF_CONTROL
+   select DM
+
 endchoice
 
 source "board/dbau1x00/Kconfig"
@@ -61,6 +66,7 @@ source "board/imgtec/malta/Kconfig"
 source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
+source "arch/mips/mach-pic32/Kconfig"
 
 if MIPS
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 2133e7e..aec5a15 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/
 libs-y += arch/mips/lib/
 
 machine-$(CONFIG_SOC_AU1X00) += au1x00
+machine-$(CONFIG_MACH_PIC32) += pic32
 
 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
 libs-y += $(machdirs)
diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig
new file mode 100644
index 000..c1cc5e3
--- /dev/null
+++ b/arch/mips/mach-pic32/Kconfig
@@ -0,0 +1,7 @@
+menu "Microchip PIC32 platforms"
+   depends on MACH_PIC32
+
+config SYS_SOC
+   default "none"
+
+endmenu
diff --git a/arch/mips/mach-pic32/Makefile b/arch/mips/mach-pic32/Makefile
new file mode 100644
index 000..cb42607
--- /dev/null
+++ b/arch/mips/mach-pic32/Makefile
@@ -0,0 +1,7 @@
+# (C) Copyright 2015
+# Purna Chandra Mandal, purna.man...@microchip.com.
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+
+obj-y = cpu.o
diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c
new file mode 100644
index 000..58fd3ab
--- /dev/null
+++ b/arch/mips/mach-pic32/cpu.c
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2015
+ * Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+#include 
+
+phys_size_t initdram(int board_type)
+{
+   return 0;
+}
diff --git a/arch/mips/mach-pic32/include/mach/pic32.h 
b/arch/mips/mach-pic32/include/mach/pic32.h
new file mode 100644
index 000..7e41810
--- /dev/null
+++ b/arch/mips/mach-pic32/include/mach/pic32.h
@@ -0,0 +1,76 @@
+/*
+ * (c) 2015 Paul Thacker <paul.thac...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#ifndef __PIC32_REGS_H__
+#define __PIC32_REGS_H__
+
+#include 
+
+/* System Configuration */
+#define PIC32_CFG_BASE 0x1f80
+
+/* System config register offsets */
+#define CFGCON 0x
+#define DEVID  0x0020
+#define SYSKEY 0x0030
+#define PMD1   0x0040
+#define PMD7   0x00a0
+#define CFGEBIA0x00c0
+#define CFGEBIC0x00d0
+#define CFGPG  0x00e0
+#define CFGMPLL0x0100
+
+/* Non Volatile Memory (NOR flash) */
+#define PIC32_NVM_BASE (PIC32_CFG_BASE + 0x0600)
+/* Oscillator Configuration */
+#define PIC32_OSC_BASE (PIC32_CFG_BASE + 0x1200)
+/* Peripheral Pin Select Input */
+#define PPS_IN_BASE0x1f801400
+/* Peripheral Pin Select Output */
+#define PPS_OUT_BASE   0x1f801500
+/* Pin Config */
+#define PINCTRL_BASE   0x1f86
+
+/* USB Core */
+#define PIC32_USB_CORE_BASE0x1f8e3000
+#define PIC32_USB_CTRL_BASE0x1f884000
+
+/* SPI1-SPI6 */
+#define PIC32_SPI1_BASE0x1f821000
+
+/* Prefetch Module */
+#define PREFETCH_BASE  0x1f8e
+
+/* DDR2 Controller */
+#define PIC32_DDR2C_BASE   0x1f8e8000
+
+/* DDR2 PHY */
+#define PIC32_DDR2P_BASE   0x1f8e9100
+
+/* EBI */
+#define PIC32_EBI_BASE 0x1f8e1000
+
+/* SQI */
+#define PIC32_SQI_BASE 0x1f8e2000
+
+struct pic32_reg_atomic {
+   u32 raw;
+   u32 clr;
+   u32 set;
+   u32 inv;
+};
+
+#define

[U-Boot] [PATCH v3 00/14] Initial Microchip PIC32MZ[DA] Support

[Purna Chandra Mandal]

This patch series adds support for Microchip PIC32MZ[DA] MIPS microcontroller 
platform.
All drivers required to boot from MMC uSD card and network are included in it; 
clock,
pinctrl, gpio, DDR2, serial, SDHCI, ethernet.
This series is tested on PIC32MZ[DA] Starter Kit.

This series is generated on mips_io_v1 branch of u-boot-mips tree.
A tree with these changes are available at [2].

[2] https://github.com/purna-mandal/u-boot/tree/pic32-upstream-v3
[1] https://github.com/purna-mandal/u-boot/tree/pic32-upstream-v2
[0] https://github.com/purna-mandal/u-boot/tree/pic32-upstream-v1

Changes in v3:
- drop empty choices in mach-pic32/Kconfig
- add pic32_get_syscfg_base() for device-config regs base
- rename clk-pic32.c to clk_pic32.c
- update clock binding documentation
- replace pic32_ioremap() with ioremap()
- read register base from device-tree
- add/update comments to explain how pinctrl'r works.
- remove ofdata_to_platdata, and replace platdata with priv
- serial:remove special handling of '\r' as being handled by serial-uclass
- serial:remove loop to wait for space in tx buffer before pumping char
- pinctrl: annotating fixed table with const
- ddr: fix camel-case in ddr2 timing parameters
- ddr: fix cmd index parameter of host_load_cmd().
- drop forcing CONFIG_MIPS_BOOT_* selection in mach-pic32/Kconfig
- indent assembly instructions in delay slot
- made GPIO-nodes child of pinctrl-node in devicetree
- drop SKIP_LOWLEVEL_INIT, GBL_DATA_OFFSET from config header
- move CMD_MEMTEST, CMD_MEMINFO to defconfig
- increase SYS_MALLOC_F_LEN to 0x600
- use auto-generated defconfig - no hand edit
- net: merge internal wrappers functions with eth operation callbacks
- net: read ethernet-phy address from device-tree
- net: rename ethernet callback functions

Changes in v2:
- move PIC32 specific headers to arch/mips/mach-pic32/include/mach/
- define register-base as physical address
- drop CONFIG_PIC32_SUPPORTS_FDT_BOOT
- add mpll get clock rate
- add pinconf routine for configuring pin property
- fix missing/corrupted chars during baud rate change
- remove loop until any char is avaialbale in getc()
- move ddr2 initialization from board/microchip/ to drivers/ddr/microchip
- drop board_early_init_f
- use macro LEAF(), END() for lowlevel_init
- move initialization of board_init_f() argument to common start.S
- move initdram() from board/microchip/ to mach-pic32/cpu.c
- remove MIPS virtual address in favor physical one in dts file
- move CONFIG_SYS_TEXT_BASE (from board/*/config.mk) to 
include/configs/.h
- drop sdhci shared bus configuration (for shared interrupt, clock pins)
- drop shared bus (shared pin selection) configuration.
- replace unbounded loop with wait_for_bit()
- replace register access as readl/writel(base + offset)
- translate (dts provided) physical address to MIPS kseg1 address before use

Andrei Pistirica (1):
  drivers: mmc: add driver for Microchip PIC32 SDHCI controller.

Paul Thacker (1):
  drivers: serial: add driver for Microchip PIC32 UART controller.

Purna Chandra Mandal (12):
  MIPS: initialize board_init_f() argument to zero.
  MIPS: initial infrastructure for Microchip PIC32 architecture
  drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.
  drivers: pinctrl: Add pinctrl driver for Microchip PIC32.
  drivers: gpio: add driver for Microchip PIC32 GPIO controller.
  drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.
  MIPS: Add support for Microchip PIC32MZ[DA] SoC family.
  board: Add Microchip PIC32MZ[DA]-Starter-Kit board.
  board: add SDHCI support for PIC32MZDASK board.
  drivers: net: phy: add SMSC LAN8740 Phy support.
  drivers: net: Add ethernet driver for Microchip PIC32.
  board: Enable ethernet, tftpboot support to pic32mzdask board.

 arch/mips/Kconfig  |   6 +
 arch/mips/Makefile |   1 +
 arch/mips/cpu/start.S  |   2 +
 arch/mips/dts/Makefile |   2 +-
 arch/mips/dts/pic32mzda.dtsi   | 174 ++
 arch/mips/dts/pic32mzda_sk.dts |  55 ++
 arch/mips/mach-pic32/Kconfig   |  38 ++
 arch/mips/mach-pic32/Makefile  |   7 +
 arch/mips/mach-pic32/cpu.c | 160 ++
 arch/mips/mach-pic32/include/mach/ddr.h|  32 ++
 arch/mips/mach-pic32/include/mach/pic32.h  |  79 +++
 arch/mips/mach-pic32/lowlevel_init.S   |  27 +
 arch/mips/mach-pic32/reset.c   |  36 ++
 board/microchip/pic32mzda/Kconfig  |  13 +
 board/microchip/pic32mzda/MAINTAINERS  |   6 +
 board/microchip/pic32mzda/Makefile |   7 +
 board/microchip/pic32mzda/README   |  22 +
 board/microchip/pic32mzda/pic32mzda.c  |  31 ++
 configs/pic32mzdask_defconfig  | 426 +++
 .../clock/microchip,pic32-clock.txt|  33

[U-Boot] [PATCH v3 14/14] board: Enable ethernet, tftpboot support to pic32mzdask board.

[Purna Chandra Mandal]

This adds ethernet, TFTP support for PIC32MZ[DA] Starter Kit. Also
custom environment variables/scripts are added to help boot from network.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

Changes in v3: None
Changes in v2:
- replace unbounded loop with wait_for_bit()
- replace register access as readl/writel(base + offset)
- translate (dts provided) physical address to MIPS kseg1 address before use

 arch/mips/dts/pic32mzda.dtsi   | 10 ++
 arch/mips/dts/pic32mzda_sk.dts | 10 ++
 configs/pic32mzdask_defconfig  | 26 +-
 include/configs/pic32mzdask.h  | 27 +--
 4 files changed, 62 insertions(+), 11 deletions(-)

diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
index 3d62a17..57612bc 100644
--- a/arch/mips/dts/pic32mzda.dtsi
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -161,4 +161,14 @@
bus-width = <4>;
status = "disabled";
};
+
+   ethernet: ethernet@1f882000 {
+   compatible = "microchip,pic32mzda-eth";
+   reg = <0x1f882000 0x1000>;
+   interrupts = <153 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < PB5CLK>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
 };
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
index f886a0f..e5ce0bd 100644
--- a/arch/mips/dts/pic32mzda_sk.dts
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -42,4 +42,14 @@
 
  {
status = "okay";
+};
+
+ {
+   reset-gpios = < 15 0>;
+   status = "okay";
+   phy-mode = "rmii";
+   phy-handle = <_phy>;
+   ethernet_phy: lan8740_phy@0 {
+   reg = <0>;
+   };
 };
\ No newline at end of file
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 6981cf7..5e78e14 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -165,13 +165,13 @@ CONFIG_CMD_SETEXPR=y
 #
 # Network commands
 #
-# CONFIG_CMD_NET is not set
+CONFIG_CMD_NET=y
 # CONFIG_CMD_TFTPPUT is not set
 # CONFIG_CMD_TFTPSRV is not set
-# CONFIG_CMD_RARP is not set
-# CONFIG_CMD_DHCP is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_PING is not set
+CONFIG_CMD_RARP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_PING=y
 # CONFIG_CMD_CDP is not set
 # CONFIG_CMD_SNTP is not set
 # CONFIG_CMD_DNS is not set
@@ -208,7 +208,10 @@ CONFIG_SUPPORT_OF_CONTROL=y
 CONFIG_OF_CONTROL=y
 # CONFIG_OF_SEPARATE is not set
 CONFIG_OF_EMBED=y
-# CONFIG_NET is not set
+CONFIG_NET=y
+CONFIG_NET_RANDOM_ETHADDR=y
+# CONFIG_NETCONSOLE is not set
+CONFIG_NET_TFTP_VARS=y
 
 #
 # Device Drivers
@@ -308,8 +311,13 @@ CONFIG_PIC32_SDHCI=y
 # SPI Flash Support
 #
 # CONFIG_SPI_FLASH is not set
-# CONFIG_DM_ETH is not set
-# CONFIG_PHYLIB is not set
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+# CONFIG_ALTERA_TSE is not set
+# CONFIG_E1000 is not set
+# CONFIG_ETH_DESIGNWARE is not set
+CONFIG_PIC32_ETH=y
 
 #
 # PCI
@@ -398,7 +406,7 @@ CONFIG_SYS_HZ=1000
 CONFIG_SYS_VSNPRINTF=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_REGEX=y
-# CONFIG_LIB_RAND is not set
+CONFIG_LIB_RAND=y
 CONFIG_CMD_DHRYSTONE=y
 # CONFIG_RSA is not set
 # CONFIG_TPM is not set
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 224b21c..7339f0f 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -73,6 +73,25 @@
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_CMDLINE_EDITING 1
 
+/*---
+ * Networking Configuration
+ */
+#define CONFIG_MII
+#define CONFIG_PHY_SMSC
+#define CONFIG_SYS_RX_ETH_BUFFER   8
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_ARP_TIMEOUT 500 /* millisec */
+
+#define CONFIG_CMD_MII
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
 /*
  * Handover flattened device tree (dtb file) to Linux kernel
  */
@@ -127,12 +146,16 @@
"importbootenv= "   \
"env import -t -r ${uenvaddr} ${filesize};\0"   \
\
+   "tftploadenv=tftp ${uenvaddr} ${uenvfile} \0"   \
+   "tftploadscr=tftp ${uenvaddr} ${scriptfile} \0" \
+   "tftploadub=tftp ${loadaddr} ${ubootfile} \0"   \
+   \
"mmcloadenv=fatload mmc 0 ${uenvaddr} ${uenvfile}\0"\
"mmcloadscr=fatload mmc 0 ${uenvaddr} ${scriptfile}\0"  \
"mmcloadub=fatload mmc 0 ${loada

[U-Boot] [PATCH v3 13/14] drivers: net: Add ethernet driver for Microchip PIC32.

[Purna Chandra Mandal]

This driver implements MAC and MII layer of the ethernet controller.
Network data transfer is handled by controller internal DMA engine.
Ethernet controller is configurable through device-tree file.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>


---

Changes in v3:
- merge wrappers with eth operation callbacks
- read phy address from device-tree
- rename functions (e.g. _eth_xyz() with pic32_eth_xyz())

Changes in v2: None

 drivers/net/Kconfig  |   7 +
 drivers/net/Makefile |   1 +
 drivers/net/pic32_eth.c  | 606 +++
 drivers/net/pic32_eth.h  | 171 +
 drivers/net/pic32_mdio.c | 121 ++
 5 files changed, 906 insertions(+)
 create mode 100644 drivers/net/pic32_eth.c
 create mode 100644 drivers/net/pic32_eth.h
 create mode 100644 drivers/net/pic32_mdio.c

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index ae5e78d..dc49493 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -108,4 +108,11 @@ config ZYNQ_GEM
help
  This MAC is present in Xilinx Zynq and ZynqMP SoCs.
 
+config PIC32_ETH
+   bool "Microchip PIC32 Ethernet Support"
+   depends on MACH_PIC32
+   help
+ This driver implements 10/100 Mbps Ethernet and MAC layer for
+ Microchip PIC32 microcontrollers.
+
 endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 150470c..33a81ee 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -72,3 +72,4 @@ obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
 obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/
 obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
 obj-$(CONFIG_VSC9953) += vsc9953.o
+obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
diff --git a/drivers/net/pic32_eth.c b/drivers/net/pic32_eth.c
new file mode 100644
index 000..1cef62e
--- /dev/null
+++ b/drivers/net/pic32_eth.c
@@ -0,0 +1,606 @@
+/*
+ * (c) 2015 Purna Chandra Mandal <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pic32_eth.h"
+
+#define MAX_RX_BUF_SIZE1536
+#define MAX_RX_DESCR   PKTBUFSRX
+#define MAX_TX_DESCR   2
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pic32eth_dev {
+   struct eth_dma_desc rxd_ring[MAX_RX_DESCR];
+   struct eth_dma_desc txd_ring[MAX_TX_DESCR];
+   u32 rxd_idx; /* index of RX desc to read */
+   /* regs */
+   struct pic32_ectl_regs *ectl_regs;
+   struct pic32_emac_regs *emac_regs;
+   /* Phy */
+   struct phy_device *phydev;
+   phy_interface_t phyif;
+   u32 phy_addr;
+   struct gpio_desc rst_gpio;
+};
+
+void __weak board_netphy_reset(void *dev)
+{
+   struct pic32eth_dev *priv = (struct pic32eth_dev *)dev;
+
+   if (!dm_gpio_is_valid(>rst_gpio))
+   return;
+
+   /* phy reset */
+   dm_gpio_set_value(>rst_gpio, 0);
+   udelay(300);
+   dm_gpio_set_value(>rst_gpio, 1);
+   udelay(300);
+}
+
+/* Initialize mii(MDIO) interface, discover which PHY is
+ * attached to the device, and configure it properly.
+ */
+static int pic32_mii_init(struct pic32eth_dev *priv)
+{
+   struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
+   struct pic32_emac_regs *emac_p = priv->emac_regs;
+
+   /* board phy reset */
+   board_netphy_reset(priv);
+
+   /* disable RX, TX & all transactions */
+   writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, _p->con1.clr);
+
+   /* wait till busy */
+   wait_for_bit(__func__, _p->stat.raw, ETHSTAT_BUSY, false,
+CONFIG_SYS_HZ, false);
+
+   /* turn controller ON to access PHY over MII */
+   writel(ETHCON_ON, _p->con1.set);
+
+   mdelay(10);
+
+   /* reset MAC */
+   writel(EMAC_SOFTRESET, _p->cfg1.set); /* reset assert */
+   mdelay(10);
+   writel(EMAC_SOFTRESET, _p->cfg1.clr); /* reset deassert */
+
+   /* initialize MDIO/MII */
+   if (priv->phyif == PHY_INTERFACE_MODE_RMII) {
+   writel(EMAC_RMII_RESET, _p->supp.set);
+   mdelay(10);
+   writel(EMAC_RMII_RESET, _p->supp.clr);
+   }
+
+   return pic32_mdio_init(PIC32_MDIO_NAME, (ulong)_p->mii);
+}
+
+static int pic32_phy_init(struct pic32eth_dev *priv, struct udevice *dev)
+{
+   struct mii_dev *mii;
+
+   mii = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
+
+   /* find & connect PHY */
+   priv->phydev = phy_connect(mii, priv->phy_addr,
+  dev, priv->phyif);
+   if (!priv->phydev) {
+   printf("%s: %s: Error, PHY connect\n", __FILE__, __func__);
+   return 0;
+   }
+
+   /* Wait for phy to complete reset */
+   mdelay(10);
+
+   /* configure supported modes */
+   pri

[U-Boot] [PATCH v3 12/14] drivers: net: phy: add SMSC LAN8740 Phy support.

[Purna Chandra Mandal]

Add SMSC LAN8740 Phy support required for PIC32MZDA devices.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

Changes in v3: None
Changes in v2: None

 drivers/net/phy/smsc.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index bfd9815..34986a2 100644
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -69,11 +69,21 @@ static struct phy_driver lan8710_driver = {
.shutdown = _shutdown,
 };
 
+static struct phy_driver lan8740_driver = {
+   .name = "SMSC LAN8740",
+   .uid = 0x0007c110,
+   .mask = 0x0,
+   .features = PHY_BASIC_FEATURES,
+   .config = _config_aneg,
+   .startup = _startup,
+   .shutdown = _shutdown,
+};
 int phy_smsc_init(void)
 {
phy_register(_driver);
phy_register(_driver);
phy_register(_driver);
+   phy_register(_driver);
 
return 0;
 }
-- 
1.8.3.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v3 09/14] board: Add Microchip PIC32MZ[DA]-Starter-Kit board.

[Purna Chandra Mandal]

This adds support for Microchip PIC32MZ[DA] StarterKit board
based on a PIC32MZ[DA] family of microcontroller.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>


---

Changes in v3:
- drop SKIP_LOWLEVEL_INIT, GBL_DATA_OFFSET from config header
- move CMD_MEMTEST, CMD_MEMINFO to defconfig
- increase SYS_MALLOC_F_LEN to 0x600
- use auto-generated defconfig - no hand edit

Changes in v2:
- move CONFIG_SYS_TEXT_BASE (from board/*/config.mk) to 
include/configs/.h

 arch/mips/dts/Makefile|   2 +-
 arch/mips/dts/pic32mzda_sk.dts|  38 
 arch/mips/mach-pic32/Kconfig  |  13 ++
 board/microchip/pic32mzda/Kconfig |  13 ++
 board/microchip/pic32mzda/MAINTAINERS |   6 +
 board/microchip/pic32mzda/Makefile|   7 +
 board/microchip/pic32mzda/README  |  22 ++
 board/microchip/pic32mzda/pic32mzda.c |  31 +++
 configs/pic32mzdask_defconfig | 416 ++
 include/configs/pic32mzdask.h |  94 
 10 files changed, 641 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/dts/pic32mzda_sk.dts
 create mode 100644 board/microchip/pic32mzda/Kconfig
 create mode 100644 board/microchip/pic32mzda/MAINTAINERS
 create mode 100644 board/microchip/pic32mzda/Makefile
 create mode 100644 board/microchip/pic32mzda/README
 create mode 100644 board/microchip/pic32mzda/pic32mzda.c
 create mode 100644 configs/pic32mzdask_defconfig
 create mode 100644 include/configs/pic32mzdask.h

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 47b6eb5..b513918 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-dtb-y +=
+dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
new file mode 100644
index 000..99e7f64
--- /dev/null
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2015 Purna Chandra Mandal, purna.man...@microchip.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "pic32mzda.dtsi"
+
+/ {
+   model = "Microchip PIC32MZDASK";
+   compatible = "microchip,pic32mzdask", "microchip,pic32mzda";
+
+   aliases {
+   console = 
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+ {
+   status = "okay";
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   status = "okay";
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   status = "okay";
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig
index 74be9fb..d665f63 100644
--- a/arch/mips/mach-pic32/Kconfig
+++ b/arch/mips/mach-pic32/Kconfig
@@ -22,4 +22,17 @@ config SOC_PIC32MZDA
 
 endchoice
 
+choice
+   prompt "Board select"
+
+config TARGET_PIC32MZDASK
+   bool "Microchip PIC32MZ[DA] Starter Kit"
+   depends on SOC_PIC32MZDA
+   help
+ This supports Microchip PIC32MZ[DA] Starter Kit.
+
+endchoice
+
+source "board/microchip/pic32mzda/Kconfig"
+
 endmenu
diff --git a/board/microchip/pic32mzda/Kconfig 
b/board/microchip/pic32mzda/Kconfig
new file mode 100644
index 000..8acb393
--- /dev/null
+++ b/board/microchip/pic32mzda/Kconfig
@@ -0,0 +1,13 @@
+
+if TARGET_PIC32MZDASK
+
+config SYS_BOARD
+   default "pic32mzda"
+
+config SYS_VENDOR
+   default "microchip"
+
+config SYS_CONFIG_NAME
+   default "pic32mzdask"
+
+endif
diff --git a/board/microchip/pic32mzda/MAINTAINERS 
b/board/microchip/pic32mzda/MAINTAINERS
new file mode 100644
index 000..c934f1a
--- /dev/null
+++ b/board/microchip/pic32mzda/MAINTAINERS
@@ -0,0 +1,6 @@
+PIC32MZDASK BOARD
+M: Purna Chandra Mandal <purna.man...@microchip.com>
+S: Maintained
+F: board/microchip/pic32mzda/
+F: include/configs/pic32mzdask.h
+F: configs/pic32mzdask_defconfig
diff --git a/board/microchip/pic32mzda/Makefile 
b/board/microchip/pic32mzda/Makefile
new file mode 100644
index 000..3629530
--- /dev/null
+++ b/board/microchip/pic32mzda/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015
+# Purna Chandra Mandal, purna.man...@microchip.com.
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+obj-y := pic32mzda.o
diff --git a/board/microchip/pic32mzda/README b/board/microchip/pic32mzda/README
new file mode 100644
index 000..91d16ab
--- /dev/null
+++ b/board/microchip/pic32mzda/README
@@ -0,0 +1,22 @@
+/*
+ * (c) 2015 Purna Chandra Mandal <purna.man...@microchip.com>
+ */
+
+PIC32MZ[DA] Starter Kit
+
+PIC32MZ[DA] Starter Kit is based on PIC32MZ[DA] family of micro-controller.
+This family is powered by MIPS M14KEC 32bit general purpose core and has
+advanced microcontroller features and peripherals.

[U-Boot] [PATCH v3 10/14] drivers: mmc: add driver for Microchip PIC32 SDHCI controller.

[Purna Chandra Mandal]

From: Andrei Pistirica <andrei.pistir...@microchip.com>

This driver implements platform specific glue and fixups for
PIC32 internal SDHCI controller.

Signed-off-by: Andrei Pistirica <andrei.pistir...@microchip.com>
Signed-off-by: Sandeep Sheriker Mallikarjun 
<sandeepsheriker.mallikar...@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

Changes in v3:
- remove ofdata_to_platdata, and replace platdata with priv
- replace pic32_ioremap() with ioremap()

Changes in v2:
- drop sdhci shared bus configuration (for shared interrupt, clock pins)

 drivers/mmc/Kconfig   |  6 +
 drivers/mmc/Makefile  |  2 +-
 drivers/mmc/pic32_sdhci.c | 61 +++
 drivers/mmc/sdhci.c   | 12 ++
 4 files changed, 80 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mmc/pic32_sdhci.c

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index ceae7bc..0b6f54b 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -31,4 +31,10 @@ config SH_SDHI
help
  Support for the on-chip SDHI host controller on SuperH/Renesas ARM 
SoCs platform
 
+config PIC32_SDHCI
+   bool "Microchip PIC32 on-chip SDHCI support"
+   depends on DM_MMC && MACH_PIC32
+   help
+ Support for the on-chip SDHCI support on Microchip PIC32 platforms.
+
 endmenu
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 5d35705..c9c3e3e 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -48,4 +48,4 @@ obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
 else
 obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
 endif
-
+obj-$(CONFIG_PIC32_SDHCI) += pic32_sdhci.o
diff --git a/drivers/mmc/pic32_sdhci.c b/drivers/mmc/pic32_sdhci.c
new file mode 100644
index 000..f8a5a23
--- /dev/null
+++ b/drivers/mmc/pic32_sdhci.c
@@ -0,0 +1,61 @@
+/*
+ * Support of SDHCI for Microchip PIC32 SoC.
+ *
+ * Copyright (C) 2015 Microchip Technology Inc.
+ * Andrei Pistirica <andrei.pistir...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int pic32_sdhci_probe(struct udevice *dev)
+{
+   struct sdhci_host *host = dev_get_priv(dev);
+   const void *fdt = gd->fdt_blob;
+   u32 f_min_max[2];
+   fdt_addr_t addr;
+   fdt_size_t size;
+   int ret;
+
+   addr = fdtdec_get_addr_size(fdt, dev->of_offset, "reg", );
+   if (addr == FDT_ADDR_T_NONE)
+   return -EINVAL;
+
+   host->ioaddr = ioremap(addr, size);
+   if (!host->ioaddr)
+   return -EINVAL;
+
+   host->name  = (char *)dev->name;
+   host->quirks= SDHCI_QUIRK_NO_HISPD_BIT;
+   host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+   "bus-width", 4);
+
+   ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+  "clock-freq-min-max", f_min_max, 2);
+   if (ret) {
+   printf("sdhci: clock-freq-min-max not found\n");
+   return ret;
+   }
+
+   return add_sdhci(host, f_min_max[1], f_min_max[0]);
+}
+
+static const struct udevice_id pic32_sdhci_ids[] = {
+   { .compatible = "microchip,pic32mzda-sdhci" },
+   { }
+};
+
+U_BOOT_DRIVER(pic32_sdhci_drv) = {
+   .name   = "pic32_sdhci",
+   .id = UCLASS_MMC,
+   .of_match   = pic32_sdhci_ids,
+   .probe  = pic32_sdhci_probe,
+   .priv_auto_alloc_size   = sizeof(struct sdhci_host),
+};
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 02d71b9..f32fe67 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -424,6 +424,18 @@ static void sdhci_set_ios(struct mmc *mmc)
if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
ctrl &= ~SDHCI_CTRL_HISPD;
 
+#if defined(CONFIG_PIC32_SDHCI)
+   /*
+   * In PIC32MZ[DA] due to h/w bug SDHCI fails detecting card when JTAG
+   * is not connected.
+   * To work-around this problem:
+   *  - set Card_Detect_Signal_Selection bit in SDHCI_Host_Control register
+   *  - clear Card_Detect_Test_Level bit in SDHCI_Host_Control register
+   */
+   ctrl |= SDHCI_CTRL_CD_TEST;
+   ctrl &= ~SDHCI_CTRL_CD_TEST_INS;
+#endif
+
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 }
 
-- 
1.8.3.1

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[U-Boot] [PATCH v3 11/14] board: add SDHCI support for PIC32MZDASK board.

[Purna Chandra Mandal]

Enable MMC, SDHCI, FAT FS, EXT4 FS support for PIC32MZ[DA] StarterKit.
Also add custom scripts, rules to boot Linux from microSD card.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

Changes in v3: None
Changes in v2:
- drop shared bus (shared pin selection) configuration.

 arch/mips/dts/pic32mzda.dtsi   | 11 
 arch/mips/dts/pic32mzda_sk.dts |  7 +
 configs/pic32mzdask_defconfig  |  6 +++--
 include/configs/pic32mzdask.h  | 61 ++
 4 files changed, 83 insertions(+), 2 deletions(-)

diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
index fe8b13a..3d62a17 100644
--- a/arch/mips/dts/pic32mzda.dtsi
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -150,4 +150,15 @@
#gpio-cells = <2>;
};
};
+
+   sdhci: sdhci@1f8ec000 {
+   compatible = "microchip,pic32mzda-sdhci";
+   reg = <0x1f8ec000 0x100>;
+   interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < REF4CLK>, < PB5CLK>;
+   clock-names = "base_clk", "sys_clk";
+   clock-freq-min-max = <2500>,<2500>;
+   bus-width = <4>;
+   status = "disabled";
+   };
 };
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
index 99e7f64..f886a0f 100644
--- a/arch/mips/dts/pic32mzda_sk.dts
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -23,6 +23,9 @@
 };
 
  {
+   microchip,refo2-frequency = <5000>;
+   microchip,refo4-frequency = <2500>;
+   microchip,refo5-frequency = <4000>;
status = "okay";
u-boot,dm-pre-reloc;
 };
@@ -36,3 +39,7 @@
status = "okay";
u-boot,dm-pre-reloc;
 };
+
+ {
+   status = "okay";
+};
\ No newline at end of file
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 3483eb0..6981cf7 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -122,7 +122,7 @@ CONFIG_CMD_XIMG=y
 #
 # Environment commands
 #
-# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_EXPORTENV=y
 CONFIG_CMD_IMPORTENV=y
 CONFIG_CMD_EDITENV=y
 # CONFIG_CMD_SAVEENV is not set
@@ -284,7 +284,9 @@ CONFIG_PIC32_GPIO=y
 #
 # MMC Host controller Support
 #
-# CONFIG_DM_MMC is not set
+CONFIG_DM_MMC=y
+# CONFIG_ROCKCHIP_DWMMC is not set
+CONFIG_PIC32_SDHCI=y
 
 #
 # MTD Support
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 6552fa2..224b21c 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -78,6 +78,33 @@
  */
 #define CONFIG_OF_LIBFDT   1
 
+/*---
+ * SDHC Configuration
+ */
+#define CONFIG_SDHCI
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_MMC
+
+/*---
+ * File System Configuration
+ */
+/* FAT FS */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_FS_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_PART
+#define CONFIG_CMD_FAT
+
+/* EXT4 FS */
+#define CONFIG_FS_EXT4
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+
 /* -
  * Environment
  */
@@ -91,4 +118,38 @@
 #define CONFIG_BOOTDELAY   5 /* autoboot after X seconds */
 #undef CONFIG_BOOTARGS
 
+#define CONFIG_EXTRA_ENV_SETTINGS  \
+   "loadaddr="__stringify(CONFIG_SYS_LOAD_ADDR)"\0"\
+   "uenvfile=uEnv.txt\0"   \
+   "uenvaddr="__stringify(CONFIG_SYS_ENV_ADDR)"\0" \
+   "scriptfile=boot.scr\0" \
+   "ubootfile=u-boot.bin\0"\
+   "importbootenv= "   \
+   "env import -t -r ${uenvaddr} ${filesize};\0"   \
+   \
+   "mmcloadenv=fatload mmc 0 ${uenvaddr} ${uenvfile}\0"\
+   "mmcloadscr=fatload mmc 0 ${uenvaddr} ${scriptfile}\0"  \
+   "mmcloadub=fatload mmc 0 ${loadaddr} ${ubootfile}\0"\
+   \
+   "loadbootenv=run mmcloadenv\0"  \
+   "loadbootscr=run mmcloadscr\0"  \
+   "bootcmd_root= "\
+   "if run loadbootenv; then " \
+   "echo Loaded environment ${uenvfile}; &q

[U-Boot] [PATCH v3 08/14] MIPS: Add support for Microchip PIC32MZ[DA] SoC family.

[Purna Chandra Mandal]

Add Microchip PIC32MZ[DA] SoC family support.

Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>

---

Changes in v3:
- drop forcing CONFIG_MIPS_BOOT_* selection in mach-pic32/Kconfig
- indent assembly instructions in delay slot
- made GPIO-nodes child of pinctrl-node in devicetree
- replace pic32_ioremap() with ioremap()

Changes in v2:
- drop board_early_init_f
- use macro LEAF(), END() for lowlevel_init assembly
- move initialization of board_init_f() argument to common start.S
- move initdram() from board/microchip/ to mach-pic32/cpu.c
- remove MIPS virtual address in favor physical one in dts file

 arch/mips/dts/pic32mzda.dtsi  | 153 ++
 arch/mips/mach-pic32/Kconfig  |  20 +++-
 arch/mips/mach-pic32/Makefile |   2 +-
 arch/mips/mach-pic32/cpu.c| 147 
 arch/mips/mach-pic32/include/mach/pic32.h |   3 +
 arch/mips/mach-pic32/lowlevel_init.S  |  27 ++
 arch/mips/mach-pic32/reset.c  |  36 +++
 7 files changed, 386 insertions(+), 2 deletions(-)
 create mode 100644 arch/mips/dts/pic32mzda.dtsi
 create mode 100644 arch/mips/mach-pic32/lowlevel_init.S
 create mode 100644 arch/mips/mach-pic32/reset.c

diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
new file mode 100644
index 000..fe8b13a
--- /dev/null
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2015 Microchip Technology, Inc.
+ * Purna Chandra Mandal, <purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include "skeleton.dtsi"
+
+/ {
+   compatible = "microchip,pic32mzda", "microchip,pic32mz";
+
+   aliases {
+   gpio0 = 
+   gpio1 = 
+   gpio2 = 
+   gpio3 = 
+   gpio4 = 
+   gpio5 = 
+   gpio6 = 
+   gpio7 = 
+   gpio8 = 
+   gpio9 = 
+   };
+
+   cpus {
+   cpu@0 {
+   compatible = "mips,mips14kc";
+   };
+   };
+
+   clock: clk@1f801200 {
+   compatible = "microchip,pic32mzda_clk";
+   reg = <0x1f801200 0x1000>;
+   clock-cells = <1>;
+   };
+
+   uart1: serial@1f822000 {
+   compatible = "microchip,pic32mzda-uart";
+   reg = <0x1f822000 0x50>;
+   interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
+   status = "disabled";
+   clocks = < PB2CLK>;
+   };
+
+   uart2: serial@1f822200 {
+   compatible = "microchip,pic32mzda-uart";
+   reg = <0x1f822200 0x50>;
+   interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < PB2CLK>;
+   status = "disabled";
+   };
+
+   uart6: serial@1f822a00 {
+   compatible = "microchip,pic32mzda-uart";
+   reg = <0x1f822a00 0x50>;
+   interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < PB2CLK>;
+   status = "disabled";
+   };
+
+   evic: interrupt-controller@1f81 {
+   compatible = "microchip,pic32mzda-evic";
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   reg = <0x1f81 0x1000>;
+   };
+
+   pinctrl: pinctrl@1f801400 {
+   compatible = "microchip,pic32mzda-pinctrl";
+   reg = <0x1f801400 0x100>, /* in  */
+ <0x1f801500 0x200>, /* out */
+ <0x1f86 0xa00>; /* port */
+   reg-names = "ppsin","ppsout","port";
+   status = "disabled";
+
+   ranges = <0 0x1f86 0xa00>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   gpioA: gpio0@0 {
+   compatible = "microchip,pic32mzda-gpio";
+   reg = <0x000 0x48>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
+   gpioB: gpio1@100 {
+   compatible = "microchip,pic32mzda-gpio";
+   reg = <0x100 0x48>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
+   gpioC: gpio2@200 {
+   compatible = "microchip,pic32mzda-gpio";
+   reg = <0x200 0x48>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+
+   gpioD: gpio3

Re: [U-Boot] [PATCH v1 0/9] MIPS: sync asm header files with linux-4.4

[Purna Chandra Mandal]

On 01/09/2016 10:02 PM, Daniel Schwierzeck wrote:

> This patch series updates all MIPS asm header files containing
> I/O code as well as processor, register and assembly definitions.
> The source of the update are the MIPS asm header files of linux-4.4.
>
> The main goal is to get a complete set of I/O accessors on MIPS and
> to support platform-specific address spaces and mappings. Also a
> working ioremap() implementation will be added, which supports
> platform-specific callbacks. Furthermore support for bit manipulating
> I/O accessors (clrbits_X, setbits_X, clrsetbits_X) will be added.
>
> The patch series is also available on git://git.denx.de/u-boot-mips.git
> in branch mips_io_v1 and based on next branch.
>
> @Wills
> I changed map_physmem() and used the new and working ioremap() function.
> Thus you can discard your patch.
>
> @Wills, Purna
> You can use now ioremap() directly in your drivers. You can also use the
> new bit manipulating I/O accessors as requested by Marek. Please rebase
> and test your patch series against this series, thanks.

Thanks Daniel.
Rebased my PIC32 patches on 'mips_io_v1' branch and tested functionality to 
work fine.
Also updated drivers to use ioremap() (instead of pic32_ioremap()) and 
clrsetbits_le()
wherever applicable.

>
> Daniel Schwierzeck (9):
>   MIPS: malta: do not pull in target header files in config.h
>   MIPS: malta: fix IO accessor call
>   MIPS: vct: fix I/O accessor calls
>   MIPS: sync I/O related header files with linux-4.4
>   MIPS: sync processor and register definitions with linux-4.4
>   MIPS: fix SPDX license identifier in remaining arch header files
>   MIPS: kconfig: add option for MIPS_L1_CACHE_SHIFT
>   MIPS: implement bit manipulating I/O accessors
>   MIPS: DO NOT MERGE: test I/O accessors
>
>  arch/mips/Kconfig  |   21 +
>  arch/mips/Makefile |5 +-
>  arch/mips/include/asm/addrspace.h  |   10 +-
>  arch/mips/include/asm/asm.h|  126 +-
>  arch/mips/include/asm/bitops.h |6 +-
>  arch/mips/include/asm/byteorder.h  |6 +-
>  arch/mips/include/asm/cache.h  |   14 +-
>  arch/mips/include/asm/cachectl.h   |6 +-
>  arch/mips/include/asm/cacheops.h   |6 +-
>  arch/mips/include/asm/const.h  |   31 +
>  arch/mips/include/asm/cpu-features.h   |   30 +
>  arch/mips/include/asm/io.h |  817 ++-
>  arch/mips/include/asm/isadep.h |6 +-
>  .../asm/mach-generic/cpu-feature-overrides.h   |   11 +
>  arch/mips/include/asm/mach-generic/ioremap.h   |   32 +
>  arch/mips/include/asm/mach-generic/mangle-port.h   |   50 +
>  arch/mips/include/asm/mach-generic/spaces.h|  102 ++
>  arch/mips/include/asm/mipsregs.h   | 1495 
> ++--
>  arch/mips/include/asm/pgtable-bits.h   |  283 
>  arch/mips/include/asm/posix_types.h|9 +-
>  arch/mips/include/asm/processor.h  |6 +-
>  arch/mips/include/asm/ptrace.h |   99 +-
>  arch/mips/include/asm/reboot.h |6 +-
>  arch/mips/include/asm/reg.h|6 +-
>  arch/mips/include/asm/regdef.h |   12 +-
>  arch/mips/include/asm/sgidefs.h|6 +-
>  arch/mips/include/asm/string.h |6 +-
>  arch/mips/include/asm/system.h |6 +-
>  arch/mips/include/asm/types.h  |6 +-
>  arch/mips/include/asm/unaligned.h  |6 +-
>  arch/mips/lib/cache.c  |4 +-
>  arch/mips/lib/cache_init.S |   16 +-
>  arch/mips/lib/io.c |  183 +++
>  board/imgtec/malta/malta.c |3 +-
>  board/micronas/vct/vct.h   |6 +-
>  include/configs/malta.h|9 +-
>  36 files changed, 2457 insertions(+), 989 deletions(-)
>  create mode 100644 arch/mips/include/asm/const.h
>  create mode 100644 arch/mips/include/asm/cpu-features.h
>  create mode 100644 arch/mips/include/asm/mach-generic/cpu-feature-overrides.h
>  create mode 100644 arch/mips/include/asm/mach-generic/ioremap.h
>  create mode 100644 arch/mips/include/asm/mach-generic/mangle-port.h
>  create mode 100644 arch/mips/include/asm/mach-generic/spaces.h
>  create mode 100644 arch/mips/include/asm/pgtable-bits.h
>
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Re: [U-Boot] [PATCH v2 02/13] drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.

[Purna Chandra Mandal]

On 01/11/2016 10:27 PM, Simon Glass wrote:
> Hi,
>
> On 4 January 2016 at 07:00, Purna Chandra Mandal
> <purna.man...@microchip.com> wrote:
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>
> Commit message please.

Ack. Will add.

>> ---
>>
>> Changes in v2:
>> - add get clock rate for mpll clock
>>
>>  .../clock/microchip,pic32-clock.txt|  28 ++
>>  drivers/clk/Makefile   |   1 +
>>  drivers/clk/clk-pic32.c| 427 
>> +
>>  include/dt-bindings/clock/microchip,clock.h|  29 ++
>>  4 files changed, 485 insertions(+)
>>  create mode 100644 doc/device-tree-bindings/clock/microchip,pic32-clock.txt
>>  create mode 100644 drivers/clk/clk-pic32.c
>>  create mode 100644 include/dt-bindings/clock/microchip,clock.h
>>
> Reviewed-by: Simon Glass <s...@chromium.org>
>
> nits below
>
>> diff --git a/doc/device-tree-bindings/clock/microchip,pic32-clock.txt 
>> b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
>> new file mode 100644
>> index 000..d02b9d7
>> --- /dev/null
>> +++ b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
>> @@ -0,0 +1,28 @@
>> +* Microchip PIC32 Clock and Oscillator
>> +
>> +The PIC32 clock controller generates and supplies clock to various
>> +controllers within the SoC.
>> +
>> +Required Properties:
>> +
>> +- compatible: should be "microchip,pic32mzda_clk"
>> +- reg: physical base address of the controller and length of memory mapped
>> +  region.
>> +- #clock-cells: should be 1.
>> +
>> +Example: Clock controller node:
>> +
>> +   clock: clk@1f801200 {
>> +   compatible = "microchip,pic32mzda_clk";
>> +   reg = <0xbf801200 0x1000>;
>> +   };
>> +
>> +Example: UART controller node that consumes the clock generated by the clock
>> +  controller:
>> +
>> +   uart1: serial@1f822000 {
>> +   compatible = "microchip,pic32mzda-uart";
>> +   reg = <0xbf822000 0x50>;
>> +   interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
>> +   clocks = < PB2CLK>;
>> +   };
>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>> index 4a6a4a8..3c84e08 100644
>> --- a/drivers/clk/Makefile
>> +++ b/drivers/clk/Makefile
>> @@ -9,3 +9,4 @@ obj-$(CONFIG_CLK) += clk-uclass.o
>>  obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
>>  obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
>>  obj-$(CONFIG_SANDBOX) += clk_sandbox.o
>> +obj-$(CONFIG_MACH_PIC32) += clk-pic32.o
> As the other review mentions, should use underscore in filenames
> unless it is a uclass.

Agreed.

>> diff --git a/drivers/clk/clk-pic32.c b/drivers/clk/clk-pic32.c
>> new file mode 100644
>> index 000..70aac05
>> --- /dev/null
>> +++ b/drivers/clk/clk-pic32.c
>> @@ -0,0 +1,427 @@
>> +/*
>> + * Copyright (C) 2015 Purna Chandra Mandal <purna.man...@microchip.com>
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + *
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
> nit: clk.h should go above dm.h, below common.h

ack. If you could share *specific* reason behind this order (like dependencies)?

>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
> Regards,
> Simon

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Re: [U-Boot] [PATCH v2 05/13] drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.

[Purna Chandra Mandal]

On 01/11/2016 10:27 PM, Simon Glass wrote:

> Hi,
>
> On 4 January 2016 at 07:01, Purna Chandra Mandal
> <purna.man...@microchip.com> wrote:
>> Signed-off-by: Paul Thacker <paul.thac...@microchip.com>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
> Please add a commit message.

Agreed, Will add.

>> ---
>>
>> Changes in v2:
>> - move ddr2 initialization from board/microchip/ to drivers/ddr/microchip
>>
>>  arch/mips/mach-pic32/include/mach/ddr.h |  32 
>>  drivers/Makefile|   1 +
>>  drivers/ddr/microchip/Makefile  |   6 +
>>  drivers/ddr/microchip/ddr2.c| 277 
>> 
>>  drivers/ddr/microchip/ddr2_regs.h   | 151 +
>>  drivers/ddr/microchip/ddr2_timing.h |  65 
>>  6 files changed, 532 insertions(+)
>>  create mode 100644 arch/mips/mach-pic32/include/mach/ddr.h
>>  create mode 100644 drivers/ddr/microchip/Makefile
>>  create mode 100644 drivers/ddr/microchip/ddr2.c
>>  create mode 100644 drivers/ddr/microchip/ddr2_regs.h
>>  create mode 100644 drivers/ddr/microchip/ddr2_timing.h
>>
> Regards,
> Simon

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Re: [U-Boot] [PATCH v2 02/13] drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.

[Purna Chandra Mandal]

On 01/11/2016 09:46 PM, Daniel Schwierzeck wrote:

> Am Montag, den 04.01.2016, 19:30 +0530 schrieb Purna Chandra Mandal:
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>
>> ---
>>
>> Changes in v2:
>> - add get clock rate for mpll clock
>>
>>  .../clock/microchip,pic32-clock.txt|  28 ++
>>  drivers/clk/Makefile   |   1 +
>>  drivers/clk/clk-pic32.c| 427
>> +
>>  include/dt-bindings/clock/microchip,clock.h|  29 ++
>>  4 files changed, 485 insertions(+)
>>  create mode 100644 doc/device-tree-bindings/clock/microchip,pic32
>> -clock.txt
>>  create mode 100644 drivers/clk/clk-pic32.c
>>  create mode 100644 include/dt-bindings/clock/microchip,clock.h
>>
>> diff --git a/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
>> b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
>> new file mode 100644
>> index 000..d02b9d7
>> --- /dev/null
>> +++ b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
>> @@ -0,0 +1,28 @@
>> +* Microchip PIC32 Clock and Oscillator
>> +
>> +The PIC32 clock controller generates and supplies clock to various
>> +controllers within the SoC.
>> +
>> +Required Properties:
>> +
>> +- compatible: should be "microchip,pic32mzda_clk"
>> +- reg: physical base address of the controller and length of memory
>> mapped
>> +  region.
>> +- #clock-cells: should be 1.
>> +
>> +Example: Clock controller node:
>> +
>> +clock: clk@1f801200 {
>> +compatible = "microchip,pic32mzda_clk";
>> +reg = <0xbf801200 0x1000>;
>> +};
>> +
>> +Example: UART controller node that consumes the clock generated by
>> the clock
>> +  controller:
>> +
>> +uart1: serial@1f822000 {
>> +compatible = "microchip,pic32mzda-uart";
>> +reg = <0xbf822000 0x50>;
>> +interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
>> +clocks = < PB2CLK>;
>> +};
>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>> index 4a6a4a8..3c84e08 100644
>> --- a/drivers/clk/Makefile
>> +++ b/drivers/clk/Makefile
>> @@ -9,3 +9,4 @@ obj-$(CONFIG_CLK) += clk-uclass.o
>>  obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
>>  obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
>>  obj-$(CONFIG_SANDBOX) += clk_sandbox.o
>> +obj-$(CONFIG_MACH_PIC32) += clk-pic32.o
>> diff --git a/drivers/clk/clk-pic32.c b/drivers/clk/clk-pic32.c
>> new file mode 100644
>> index 000..70aac05
>> --- /dev/null
>> +++ b/drivers/clk/clk-pic32.c
>> @@ -0,0 +1,427 @@
>> +/*
>> + * Copyright (C) 2015 Purna Chandra Mandal <
>> purna.man...@microchip.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + *
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
> I can't find wait_bit.h in mainline. Is there an unmerged patch which
> adds this file and you depend on? Could you point me to it? Thanks.

Yes, this is not on mainline. Based on review (from Marek Vesut)
to use wait_for_bit() for unbounded loops I have pulled the
under-review patch from [1].

[1] http://patchwork.ozlabs.org/patch/561185/

>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +/* Primary oscillator */
>> +#define SYS_POSC_CLK_HZ 2400
>> +
>> +/* FRC clk rate */
>> +#define SYS_FRC_CLK_HZ  800
>> +
>> +/* Clock registers */
>> +#define OSCCON  0x
>> +#define OSCTUNE 0x0010
>> +#define SPLLCON 0x0020
>> +#define REFO1CON0x0080
>> +#define REFO1TRIM   0x0090
>> +#define PB1DIV  0x0140
>> +
>> +/* PLL */
>> +#define ICLK_MASK   0x0080
>> +#define PLLIDIV_MASK0x0007
>> +#define PLLODIV_MASK0x0007
>> +#define CUROSC_MASK 0x0007
>> +#define PLLMUL_MASK 0x007F
>> +#define FRCDIV_MASK 0x0007
>> +
>> +/* PBCLK */
>> +#define PBDIV_MASK  0x0007
>> +
>> +/* SYSCLK MUX */
>> +#define SCLK_SRC_FRC1   0
>> +#define SCLK_SRC_SPLL   1
>> +#define SCLK_SRC_POSC   2
>> +#define SCLK_SRC_FRC2   7
>> +
>> +/* Reference Oscillator Control Reg fields */
>> +#define REFO_SEL_MASK   0x0f
>> +#define R

Re: [U-Boot] [PATCH v2 03/13] drivers: pinctrl: Add pinctrl driver for Microchip PIC32 microcontroller

[Purna Chandra Mandal]

On 01/11/2016 10:28 PM, Simon Glass wrote:

> Hi,
>
> On 7 January 2016 at 23:46, Purna Chandra Mandal
> <purna.man...@microchip.com> wrote:
>> On 01/08/2016 09:04 AM, Simon Glass wrote:
>>
>>> Hi Purna,
>>>
>>> On 4 January 2016 at 07:00, Purna Chandra Mandal
>>> <purna.man...@microchip.com> wrote:
>>>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>>>
>>> Please add a commit message.
>> Ack. will add.
>>
>>>> ---
>>>>
>>>> Changes in v2:
>>>> - add routine to configure pin properties
>>>>
>>>>  drivers/pinctrl/Kconfig |   6 +
>>>>  drivers/pinctrl/Makefile|   1 +
>>>>  drivers/pinctrl/pinctrl_pic32.c | 284 
>>>> 
>>>>  3 files changed, 291 insertions(+)
>>>>  create mode 100644 drivers/pinctrl/pinctrl_pic32.c
>>>>
>>>> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
>>>> index 57e6142..a4acaf3 100644
>>>> --- a/drivers/pinctrl/Kconfig
>>>> +++ b/drivers/pinctrl/Kconfig
>>>> @@ -131,6 +131,12 @@ config PINCTRL_SANDBOX
>>>>   actually does nothing but print debug messages when pinctrl
>>>>   operations are invoked.
>>>>
>>>> +config PIC32_PINCTRL
>>>> +   bool "Microchip PIC32 pin-control driver"
>>>> +   depends on DM && MACH_PIC32
>>>> +   help
>>>> + Support pin multiplexing control on Microchip PIC32 SoCs.
>>> Please add a bit more detail here. What type of functions use pinmux?
>>> Does the pinmux work on a per-pin or per-function basis, or use
>>> groups? Try to add some useful info.
>> Ack. Will add more information here.
>> In PIC32 pin controller is combination of gpio-controller, pin mux and pin 
>> config.
>> Remappable peripherals are assigned pins through per-pin based muxing logic.
>> And pin configuration are performed through port registers which are
>> shared along with gpio controller.
>>
>>>> +
>>>>  endif
>>>>
>>>>  source "drivers/pinctrl/uniphier/Kconfig"
>>>> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
>>>> index 70d25dc..b4f4650 100644
>>>> --- a/drivers/pinctrl/Makefile
>>>> +++ b/drivers/pinctrl/Makefile
>>>> @@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
>>>>  obj-$(CONFIG_PINCTRL_SANDBOX)  += pinctrl-sandbox.o
>>>>
>>>>  obj-$(CONFIG_ARCH_UNIPHIER)+= uniphier/
>>>> +obj-$(CONFIG_PIC32_PINCTRL)+= pinctrl_pic32.o
>>>> diff --git a/drivers/pinctrl/pinctrl_pic32.c 
>>>> b/drivers/pinctrl/pinctrl_pic32.c
>>>> new file mode 100644
>>>> index 000..043f589
>>>> --- /dev/null
>>>> +++ b/drivers/pinctrl/pinctrl_pic32.c
>>>> @@ -0,0 +1,284 @@
>>>> +/*
>>>> + * Pinctrl driver for Microchip PIC32 SoCs
>>>> + * Copyright (c) 2015 Microchip Technology Inc.
>>>> + * Written by Purna Chandra Mandal <purna.man...@microchip.com>
>>>> + *
>>>> + * SPDX-License-Identifier:GPL-2.0+
>>>> + */
>>>> +#include 
>>>> +#include 
>>>> +#include 
>>>> +#include 
>>>> +#include 
>>>> +#include 
>>>> +#include 
>>>> +
>>>> +DECLARE_GLOBAL_DATA_PTR;
>>>> +
>>>> +/* Peripheral PORTA-PORTK / PORT0-PORT9 */
>>>> +enum {
>>>> +   PIC32_PORT_A = 0,
>>>> +   PIC32_PORT_B = 1,
>>>> +   PIC32_PORT_C = 2,
>>>> +   PIC32_PORT_D = 3,
>>>> +   PIC32_PORT_E = 4,
>>>> +   PIC32_PORT_F = 5,
>>>> +   PIC32_PORT_G = 6,
>>>> +   PIC32_PORT_H = 7,
>>>> +   PIC32_PORT_J = 8, /* no PORT_I */
>>>> +   PIC32_PORT_K = 9,
>>>> +   PIC32_PORT_MAX
>>>> +};
>>>> +
>>>> +/* Input pinmux reg offset */
>>>> +#define U1RXR  0x0068
>>>> +#define U2RXR  0x0070
>>>> +#define SDI1R  0x009c
>>>> +#define SDI2R  0x00a8
>>>> +
>>>> +/* Output pinmux reg offset */
>>>> +#define PPS_OUT(__port, __pin) (((__port) * 16 + (__pin)) << 2)
>>>> +
>>

Re: [U-Boot] [PATCH v2 4/5] MIPS: add initial infrastructure for device-tree files

[Purna Chandra Mandal]

On 12/20/2015 04:13 AM, Daniel Schwierzeck wrote:
> Prepare sub-folder for device-tree files. Make support for
> device-tree on MIPS available in Kbuild/Kconfig.
>
> Signed-off-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>
>
> ---
>
> Changes in v2:
> - add arch/mips/dts to clean list in dts/Makefile
> - keep section .dtb during link in case of CONFIG_OF_EMBED
>
>  arch/Kconfig|  1 +
>  arch/mips/config.mk |  2 +-
>  arch/mips/dts/.gitignore|  1 +
>  arch/mips/dts/Makefile  | 16 
>  arch/mips/dts/skeleton.dtsi | 23 +++
>  dts/Makefile|  2 +-
>  6 files changed, 43 insertions(+), 2 deletions(-)
>  create mode 100644 arch/mips/dts/.gitignore
>  create mode 100644 arch/mips/dts/Makefile
>  create mode 100644 arch/mips/dts/skeleton.dtsi
>
> diff --git a/arch/Kconfig b/arch/Kconfig
> index 1709d40..ec12013 100644
> --- a/arch/Kconfig
> +++ b/arch/Kconfig
> @@ -55,6 +55,7 @@ config MIPS
>   select HAVE_PRIVATE_LIBGCC
>   select HAVE_GENERIC_BOARD
>   select SYS_GENERIC_BOARD
> + select SUPPORT_OF_CONTROL
>  
>  config NDS32
>   bool "NDS32 architecture"
> diff --git a/arch/mips/config.mk b/arch/mips/config.mk
> index 415ec8a..3ebc202 100644
> --- a/arch/mips/config.mk
> +++ b/arch/mips/config.mk
> @@ -71,7 +71,7 @@ else
>  PF_ABICALLS  := -mabicalls
>  PF_PIC   := -fpic
>  PF_PIE   := -pie
> -PF_OBJCOPY   := -j .got -j .u_boot_list -j .rel.dyn -j 
> .padding
> +PF_OBJCOPY   := -j .got -j .u_boot_list -j .rel.dyn -j 
> .padding -j .dtb
>  endif
>  

There is no section called '.dtb' in U-boot linker script, instead one 
generated by build script is named '.dtb.init.rodata'.
Unless we add '-j .dtb.init.rodata' device-tree blob will not be copied to 
binary.

>  PLATFORM_CPPFLAGS+= -G 0 $(PF_ABICALLS) $(PF_PIC)
> diff --git a/arch/mips/dts/.gitignore b/arch/mips/dts/.gitignore
> new file mode 100644
> index 000..b60ed20
> --- /dev/null
> +++ b/arch/mips/dts/.gitignore
> @@ -0,0 +1 @@
> +*.dtb
> diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
> new file mode 100644
> index 000..47b6eb5
> --- /dev/null
> +++ b/arch/mips/dts/Makefile
> @@ -0,0 +1,16 @@
> +#
> +# SPDX-License-Identifier:   GPL-2.0+
> +#
> +
> +dtb-y +=
> +
> +targets += $(dtb-y)
> +
> +# Add any required device tree compiler flags here
> +DTC_FLAGS +=
> +
> +PHONY += dtbs
> +dtbs: $(addprefix $(obj)/, $(dtb-y))
> + @:
> +
> +clean-files := *.dtb
> diff --git a/arch/mips/dts/skeleton.dtsi b/arch/mips/dts/skeleton.dtsi
> new file mode 100644
> index 000..24ee6c3
> --- /dev/null
> +++ b/arch/mips/dts/skeleton.dtsi
> @@ -0,0 +1,23 @@
> +/*
> + * Skeleton device tree; the bare minimum needed to boot; just include and
> + * add a compatible value.  The bootloader will typically populate the memory
> + * node.
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + chosen {
> + };
> +
> + aliases {
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0 0>;
> + };
> +};
> diff --git a/dts/Makefile b/dts/Makefile
> index d3122aa..c4ac153 100644
> --- a/dts/Makefile
> +++ b/dts/Makefile
> @@ -45,4 +45,4 @@ dtbs: $(obj)/dt.dtb
>  clean-files := dt.dtb.S
>  
>  # Let clean descend into dts directories
> -subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/sandbox/dts 
> ../arch/x86/dts
> +subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts 
> ../arch/sandbox/dts ../arch/x86/dts

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Re: [U-Boot] [PATCH v1 08/18] MIPS: pic32: Add driver for Microchip PIC32 flash controller.

[Purna Chandra Mandal]

On 12/21/2015 08:50 PM, Stefan Roese wrote:
> On 21.12.2015 15:58, Daniel Schwierzeck wrote:
>>
>>
>> Am 17.12.2015 um 18:30 schrieb Purna Chandra Mandal:
>>> From: Cristian Birsan <cristi.bir...@microchip.com>
>>>
>>> Signed-off-by: Cristian Birsan <cristi.bir...@microchip.com>
>>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>> ---
>>>
>>>   arch/mips/mach-pic32/Makefile |   5 +-
>>>   arch/mips/mach-pic32/flash.c  | 471 
>>> ++
>>>   include/flash.h   |   5 +-
>>>   3 files changed, 479 insertions(+), 2 deletions(-)
>>>   create mode 100644 arch/mips/mach-pic32/flash.c
>>>
>>
>> +cc Stefan Roese
>>
>> have you tried to use drivers/mtd/cfi_flash.c? You are duplicating some
>> common code. If you need additional logic for your flash controller,
>> then you can try to overwrite the weak flash_readX/flash_writeX
>> accessors. You have to enable CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS to be
>> able to do this.
>
> Yes, this really looks like it could use the common CFI flash driver.
> You might need to add support for the new flash devices with the
> commands, if its not already supported. But this should be better
> than duplicating some of the code already available.
>
Thanks Stefan.

Tried to understand and map PIC32 flash driver on cfi_flash.c. It is not 
straight
forward and resultant code becomes clumsy, full of if-else.

Please note PIC32 flash is not CFI complaint. Specific operations
(like erase, and program) on the flash panel are handled by PIC32 nvm 
controller.
NVM controller documentation: 
http://ww1.microchip.com/downloads/en/DeviceDoc/60001193B.pdf

Instead I'll propose to improve current pic32_flash driver and move it to 
drivers/mtd/
(like st_smi.c).

NVM controller: 

Thanks,
Purna

> So please take a deeper look at cfi_flash.c and try to integrate
> your flash support there.
>
> Thanks,
> Stefan
>
>>> diff --git a/arch/mips/mach-pic32/Makefile b/arch/mips/mach-pic32/Makefile
>>> index 03d5f27..3a621c3 100644
>>> --- a/arch/mips/mach-pic32/Makefile
>>> +++ b/arch/mips/mach-pic32/Makefile
>>> @@ -4,4 +4,7 @@
>>>   # SPDX-License-Identifier:  GPL-2.0+
>>>   #
>>>
>>> -obj-y = cpu.o reset.o lowlevel_init.o
>>> \ No newline at end of file
>>> +obj-y = cpu.o reset.o lowlevel_init.o
>>> +ifndef CONFIG_SYS_NO_FLASH
>>> +obj-y += flash.o
>>> +endif
>>> \ No newline at end of file
>>> diff --git a/arch/mips/mach-pic32/flash.c b/arch/mips/mach-pic32/flash.c
>>> new file mode 100644
>>> index 000..b3c1e0a
>>> --- /dev/null
>>> +++ b/arch/mips/mach-pic32/flash.c
>>> @@ -0,0 +1,471 @@
>>> +/*
>>> + * Copyright (C) 2015
>>> + * Cristian Birsan <cristian.bir...@microchip.com>
>>> + *
>>> + * SPDX-License-Identifier:GPL-2.0+
>>> + *
>>> + */
>>> +
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +
>>> +#if defined(CONFIG_ENV_IS_IN_FLASH)
>>> +#ifndef CONFIG_ENV_ADDR
>>> +#define CONFIG_ENV_ADDR(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
>>> +#endif
>>> +
>>> +#ifndef CONFIG_ENV_SIZE
>>> +#define CONFIG_ENV_SIZECONFIG_ENV_SECT_SIZE
>>> +#endif
>>> +
>>> +#ifndef CONFIG_ENV_SECT_SIZE
>>> +#define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
>>> +#endif
>>> +#endif
>>> +
>>> +/* NVM Controller registers */
>>> +#define NVMCON(PIC32_NVM_BASE + 0x00)
>>> +#define NVMCONCLR(NVMCON + _CLR_OFFSET)
>>> +#define NVMCONSET(NVMCON + _SET_OFFSET)
>>> +#define NVMKEY(PIC32_NVM_BASE + 0x10)
>>> +#define NVMADDR(PIC32_NVM_BASE + 0x20)
>>> +#define NVMDATA0(PIC32_NVM_BASE + 0x30)
>>> +
>>> +/* NVM Operations */
>>> +#define NVMOP_NOP0x
>>> +#define NVMOP_WORD_WRITE0x0001
>>> +#define NVMOP_PAGE_ERASE0x0004
>>> +
>>> +/* NVM Programming Control Register*/
>>> +#define NVMCON_WREN0x4000
>>> +#define NVMCON_WR0x8000
>>> +#define NVMCON_WRERR0x2000
>>> +#define NVMCON_LVDERR0x1000
>>> +
>>> +/*---
>>> + */
>>> +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS

Re: [U-Boot] [PATCH v2 03/13] drivers: pinctrl: Add pinctrl driver for Microchip PIC32 microcontroller

[Purna Chandra Mandal]

On 01/08/2016 09:04 AM, Simon Glass wrote:

> Hi Purna,
>
> On 4 January 2016 at 07:00, Purna Chandra Mandal
> <purna.man...@microchip.com> wrote:
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>
> Please add a commit message.

Ack. will add.

>> ---
>>
>> Changes in v2:
>> - add routine to configure pin properties
>>
>>  drivers/pinctrl/Kconfig |   6 +
>>  drivers/pinctrl/Makefile|   1 +
>>  drivers/pinctrl/pinctrl_pic32.c | 284 
>> 
>>  3 files changed, 291 insertions(+)
>>  create mode 100644 drivers/pinctrl/pinctrl_pic32.c
>>
>> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
>> index 57e6142..a4acaf3 100644
>> --- a/drivers/pinctrl/Kconfig
>> +++ b/drivers/pinctrl/Kconfig
>> @@ -131,6 +131,12 @@ config PINCTRL_SANDBOX
>>   actually does nothing but print debug messages when pinctrl
>>   operations are invoked.
>>
>> +config PIC32_PINCTRL
>> +   bool "Microchip PIC32 pin-control driver"
>> +   depends on DM && MACH_PIC32
>> +   help
>> + Support pin multiplexing control on Microchip PIC32 SoCs.
> Please add a bit more detail here. What type of functions use pinmux?
> Does the pinmux work on a per-pin or per-function basis, or use
> groups? Try to add some useful info.

Ack. Will add more information here.
In PIC32 pin controller is combination of gpio-controller, pin mux and pin 
config.
Remappable peripherals are assigned pins through per-pin based muxing logic.
And pin configuration are performed through port registers which are
shared along with gpio controller.

>> +
>>  endif
>>
>>  source "drivers/pinctrl/uniphier/Kconfig"
>> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
>> index 70d25dc..b4f4650 100644
>> --- a/drivers/pinctrl/Makefile
>> +++ b/drivers/pinctrl/Makefile
>> @@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
>>  obj-$(CONFIG_PINCTRL_SANDBOX)  += pinctrl-sandbox.o
>>
>>  obj-$(CONFIG_ARCH_UNIPHIER)+= uniphier/
>> +obj-$(CONFIG_PIC32_PINCTRL)+= pinctrl_pic32.o
>> diff --git a/drivers/pinctrl/pinctrl_pic32.c 
>> b/drivers/pinctrl/pinctrl_pic32.c
>> new file mode 100644
>> index 000..043f589
>> --- /dev/null
>> +++ b/drivers/pinctrl/pinctrl_pic32.c
>> @@ -0,0 +1,284 @@
>> +/*
>> + * Pinctrl driver for Microchip PIC32 SoCs
>> + * Copyright (c) 2015 Microchip Technology Inc.
>> + * Written by Purna Chandra Mandal <purna.man...@microchip.com>
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +/* Peripheral PORTA-PORTK / PORT0-PORT9 */
>> +enum {
>> +   PIC32_PORT_A = 0,
>> +   PIC32_PORT_B = 1,
>> +   PIC32_PORT_C = 2,
>> +   PIC32_PORT_D = 3,
>> +   PIC32_PORT_E = 4,
>> +   PIC32_PORT_F = 5,
>> +   PIC32_PORT_G = 6,
>> +   PIC32_PORT_H = 7,
>> +   PIC32_PORT_J = 8, /* no PORT_I */
>> +   PIC32_PORT_K = 9,
>> +   PIC32_PORT_MAX
>> +};
>> +
>> +/* Input pinmux reg offset */
>> +#define U1RXR  0x0068
>> +#define U2RXR  0x0070
>> +#define SDI1R  0x009c
>> +#define SDI2R  0x00a8
>> +
>> +/* Output pinmux reg offset */
>> +#define PPS_OUT(__port, __pin) (((__port) * 16 + (__pin)) << 2)
>> +
>> +/* Port config/control registers */
>> +struct pic32_reg_port {
>> +   struct pic32_reg_atomic ansel;
> What is pic32_reg_atomic? Can we use u32 instead?

For fast and atomic manipulation of registers h/w designers provided a
set of interfaces/registers {raw, clear, set, invert} for some of target 
register.
'struct pic32_reg_atomic' refers to this set as defined in [patch 01/13].

>> +   struct pic32_reg_atomic tris;
>> +   struct pic32_reg_atomic port;
>> +   struct pic32_reg_atomic lat;
>> +   struct pic32_reg_atomic odc;
>> +   struct pic32_reg_atomic cnpu;
>> +   struct pic32_reg_atomic cnpd;
>> +   struct pic32_reg_atomic cncon;
>> +};
>> +
>> +#define PIN_CONFIG_PIC32_DIGITAL   (PIN_CONFIG_END + 1)
>> +#define PIN_CONFIG_PIC32_ANALOG(PIN_CONFIG_END + 2)
>> +
>> +struct pic32_pin_config {
>> +   u16 port;
>> +   u16 pin;
>> +   u32 flags;
&g

Re: [U-Boot] [PATCH v2 06/13] MIPS: Add support for Microchip PIC32MZ[DA] family.

[Purna Chandra Mandal]

On 01/06/2016 01:53 AM, Daniel Schwierzeck wrote:
> 2016-01-04 15:01 GMT+01:00 Purna Chandra Mandal <purna.man...@microchip.com>:
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>
>> ---
>>
>> Changes in v2:
>> - drop unnecessary board_early_init_f()
>> - use LEAF(), END() macros for lowlevel_init
>> - move initialization of board_init_f() argument to common start.S
>> - move initdram() from board/microchip/ to mach-pic32/cpu.c
>> - remove MIPS virtual address in favor of physical address in dts file
>>
>>  arch/mips/cpu/start.S |   2 +
>>  arch/mips/dts/pic32mzda.dtsi  |  64 +
>>  arch/mips/mach-pic32/Kconfig  |  16 +++-
>>  arch/mips/mach-pic32/Makefile |   2 +-
>>  arch/mips/mach-pic32/cpu.c| 146 
>> ++
>>  arch/mips/mach-pic32/include/mach/pic32.h |   3 +
>>  arch/mips/mach-pic32/lowlevel_init.S  |  27 ++
>>  arch/mips/mach-pic32/reset.c  |  36 
>>  8 files changed, 294 insertions(+), 2 deletions(-)
>>  create mode 100644 arch/mips/dts/pic32mzda.dtsi
>>  create mode 100644 arch/mips/mach-pic32/lowlevel_init.S
>>  create mode 100644 arch/mips/mach-pic32/reset.c
>>
>> diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
>> index e95cdca..a7e6722 100644
>> --- a/arch/mips/cpu/start.S
>> +++ b/arch/mips/cpu/start.S
>> @@ -185,6 +185,8 @@ reset:
>> PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset
>> sw  sp, 0(t0)
>>  #endif
>> +   /* Initialize args to zero. */
>> +   li  a0, 0x0
> please create a separate patch for this change. Also the code must be
> compatible with MIPS64 now, so please do:
>
> PTR_LI  a0, 0

ack.

>> PTR_LA  t9, board_init_f
>> jr  t9
>> diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
>> new file mode 100644
>> index 000..f518ba8
>> --- /dev/null
>> +++ b/arch/mips/dts/pic32mzda.dtsi
>> @@ -0,0 +1,64 @@
>> +/*
>> + * Copyright 2015 Microchip Technology, Inc.
>> + * Purna Chandra Mandal, <purna.man...@microchip.com>
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include "skeleton.dtsi"
>> +
>> +/ {
>> +   compatible = "microchip,pic32mzda", "microchip,pic32mz";
>> +
>> +   cpus {
>> +   cpu@0 {
>> +   compatible = "mips,mips14kc";
>> +   };
>> +   };
>> +
>> +   clock: clk@1f801200 {
>> +   compatible = "microchip,pic32mzda_clk";
>> +   reg = <0x1f801200 0x1000>;
>> +   clock-cells = <1>;
>> +   };
>> +
>> +   uart1: serial@1f822000 {
>> +   compatible = "microchip,pic32mzda-uart";
>> +   reg = <0x1f822000 0x50>;
>> +   interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
>> +   status = "disabled";
>> +   clocks = < PB2CLK>;
>> +   };
>> +
>> +   uart2: serial@1f822200 {
>> +   compatible = "microchip,pic32mzda-uart";
>> +   reg = <0x1f822200 0x50>;
>> +   interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
>> +   clocks = < PB2CLK>;
>> +   status = "disabled";
>> +   };
>> +
>> +   uart6: serial@1f822a00 {
>> +   compatible = "microchip,pic32mzda-uart";
>> +   reg = <0x1f822a00 0x50>;
>> +   interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
>> +   clocks = < PB2CLK>;
>> +   status = "disabled";
>> +   };
>> +
>> +   evic: interrupt-controller@1f81 {
>> +   compatible = "microchip,pic32mzda-evic";
>> +   interrupt-controller;
>> +   #interrupt-cells = <2>;
>> +   reg = <0x1f81 0x1000>;
>> +   };
>> +
>> +   pinctrl: pinctrl@1f801400 {
>> +   compatible = "microchip,pic32mzda-pinctrl";
>> +   reg = <0x1f801400 0x100>, /* in  */
>> + <0x1f801500 0x200>; /* out */
>> +   status = "disabled";
>> +   }

Re: [U-Boot] [PATCH v2 08/13] drivers: mmc: add driver for Microchip PIC32 SDHCI controller.

[Purna Chandra Mandal]

On 01/06/2016 02:08 AM, Daniel Schwierzeck wrote:

> 2016-01-04 15:01 GMT+01:00 Purna Chandra Mandal <purna.man...@microchip.com>:
>> PIC32 architecture has in-built SDHCI controller. This driver implements
>> platform specific glue to use common SDHCI functionality.
>>
>> Signed-off-by: Andrei Pistirica <andrei.pistir...@microchip.com>
>> Signed-off-by: Sandeep Sheriker Mallikarjun 
>> <sandeepsheriker.mallikar...@microchip.com>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>
>> ---
>>
>> Changes in v2:
>> - drop SDHCI shared bus configuration (for shared interrupt-and-clock pins)
>>
>>  drivers/mmc/Kconfig   |  6 +
>>  drivers/mmc/Makefile  |  2 +-
>>  drivers/mmc/pic32_sdhci.c | 63 
>> +++
>>  drivers/mmc/sdhci.c   | 12 +
>>  4 files changed, 82 insertions(+), 1 deletion(-)
>>  create mode 100644 drivers/mmc/pic32_sdhci.c
>>
>> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
>> index ceae7bc..0b6f54b 100644
>> --- a/drivers/mmc/Kconfig
>> +++ b/drivers/mmc/Kconfig
>> @@ -31,4 +31,10 @@ config SH_SDHI
>> help
>>   Support for the on-chip SDHI host controller on SuperH/Renesas ARM 
>> SoCs platform
>>
>> +config PIC32_SDHCI
>> +   bool "Microchip PIC32 on-chip SDHCI support"
>> +   depends on DM_MMC && MACH_PIC32
>> +   help
>> + Support for the on-chip SDHCI support on Microchip PIC32 platforms.
>> +
>>  endmenu
>> diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
>> index 5d35705..c9c3e3e 100644
>> --- a/drivers/mmc/Makefile
>> +++ b/drivers/mmc/Makefile
>> @@ -48,4 +48,4 @@ obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
>>  else
>>  obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
>>  endif
>> -
>> +obj-$(CONFIG_PIC32_SDHCI) += pic32_sdhci.o
>> diff --git a/drivers/mmc/pic32_sdhci.c b/drivers/mmc/pic32_sdhci.c
>> new file mode 100644
>> index 000..9eb603e
>> --- /dev/null
>> +++ b/drivers/mmc/pic32_sdhci.c
>> @@ -0,0 +1,63 @@
>> +/*
>> + * Support of SDHCI for Microchip PIC32 SoC.
>> + *
>> + * Copyright (C) 2015 Microchip Technology Inc.
>> + * Andrei Pistirica <andrei.pistir...@microchip.com>
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +static int pic32_sdhci_probe(struct udevice *dev)
>> +{
>> +   struct sdhci_host *host = dev_get_priv(dev);
>> +   u32 f_min_max[2];
>> +   int ret;
>> +
>> +   ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
>> +  "clock-freq-min-max", f_min_max, 2);
>> +   if (ret) {
>> +   printf("sdhci: clock-freq-min-max not found\n");
>> +   return ret;
>> +   }
>> +
>> +   return add_sdhci(host, f_min_max[1], f_min_max[0]);
>> +}
>> +
>> +static int pic32_sdhci_ofdata_to_platdata(struct udevice *dev)
>> +{
>> +   struct sdhci_host *host = dev_get_priv(dev);
>> +   fdt_addr_t addr;
>> +
>> +   addr = dev_get_addr(dev);
>> +   if (addr == FDT_ADDR_T_NONE)
>> +   return -EINVAL;
>> +
>> +   host->name  = (char *)dev->name;
>> +   host->ioaddr= pic32_ioremap(addr);
>> +   host->quirks= SDHCI_QUIRK_NO_HISPD_BIT;
>> +   host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
>> +   "bus-width", 4);
>> +   return 0;
> all that code could be moved to pic32_sdhci_probe()

ack.

>> +}
>> +
>> +static const struct udevice_id pic32_sdhci_ids[] = {
>> +   { .compatible = "microchip,pic32mzda-sdhci" },
>> +   { }
>> +};
>> +
>> +U_BOOT_DRIVER(pic32_sdhci_drv) = {
>> +   .name   = "pic32_sdhci",
>> +   .id = UCLASS_MMC,
>> +   .of_match   = pic32_sdhci_ids,
>> +   .probe  = pic32_sdhci_probe,
>> +   .ofdata_to_platdata = pic32_sdhci_ofdata_to_platdata,
>> +   .priv_auto_alloc_size   = sizeof(struct sdhci_host),
>> +};
>> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhc