[PATCH] spl: riscv: opensbi: fix check of PAYLOAD_ARGS_ADDR
When Falcon Mode is enabled on RISC-V, use CONFIG_VAL to check PAYLOAD_ARGS_ADDR, not CONFIG_IS_ENABLED. Signed-off-by: Randolph --- common/spl/spl_opensbi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c index 8127ebc946..ec62aab929 100644 --- a/common/spl/spl_opensbi.c +++ b/common/spl/spl_opensbi.c @@ -66,7 +66,7 @@ void __noreturn spl_invoke_opensbi(struct spl_image_info *spl_image) * Moving DTB in front of the kernel can avoid the error. */ #if CONFIG_IS_ENABLED(LOAD_FIT_OPENSBI_OS_BOOT) && \ -CONFIG_IS_ENABLED(PAYLOAD_ARGS_ADDR) +CONFIG_VAL(PAYLOAD_ARGS_ADDR) memcpy((void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR, spl_image->fdt_addr, fdt_totalsize(spl_image->fdt_addr)); spl_image->fdt_addr = map_sysmem(CONFIG_SPL_PAYLOAD_ARGS_ADDR, 0); -- 2.34.1
Re: [PATCH V4 2/2] configs: andes: add watchdog support fot andes ae350
On Wed, Jan 24, 2024 at 09:37:41AM +0100, Stefan Roese wrote: Hi Stefan, Thank you for testing and reviewing. I have checked the error message and the relationship to my patch. The reason for the failure has nothing to do with my patch. Could you kindly help me run the CI test again? Randolph Sincerely > Hi Randolph, > > On 1/24/24 07:21, Randolph wrote: > > It adds the ATCWDT200 support for Andes AE350 platform. > > It also enables wdt command support. > > > > Signed-off-by: CL Wang > > Signed-off-by: Randolph > > Reviewed-by: Leo Yu-Chi Liang > > This fails in world CI build in "test.py for sandbox": > > https://dev.azure.com/sr0718/0cded7c3-6e6a-4b57-8d0f-65c99496c42f/_apis/build/builds/338/logs/181 > > Not sure how this is related. Could you please take a look? > > Thanks, > Stefan > > > --- > > configs/ae350_rv32_defconfig | 4 > > configs/ae350_rv32_spl_defconfig | 4 > > configs/ae350_rv32_spl_xip_defconfig | 4 > > configs/ae350_rv32_xip_defconfig | 4 > > configs/ae350_rv64_defconfig | 4 > > configs/ae350_rv64_spl_defconfig | 4 > > configs/ae350_rv64_spl_xip_defconfig | 4 > > configs/ae350_rv64_xip_defconfig | 4 > > 8 files changed, 32 insertions(+) > > > > diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig > > index 3bfa3e9f8e..35ad62c845 100644 > > --- a/configs/ae350_rv32_defconfig > > +++ b/configs/ae350_rv32_defconfig > > @@ -23,6 +23,7 @@ CONFIG_SYS_PROMPT="RISC-V # " > > CONFIG_CMD_IMLS=y > > CONFIG_CMD_MMC=y > > CONFIG_CMD_SF_TEST=y > > +CONFIG_CMD_WDT=y > > # CONFIG_CMD_SETEXPR is not set > > CONFIG_BOOTP_PREFER_SERVERIP=y > > CONFIG_CMD_CACHE=y > > @@ -49,3 +50,6 @@ CONFIG_BAUDRATE=38400 > > CONFIG_SYS_NS16550=y > > CONFIG_SPI=y > > CONFIG_ATCSPI200_SPI=y > > +# CONFIG_WATCHDOG_AUTOSTART is not set > > +CONFIG_WDT=y > > +CONFIG_WDT_ATCWDT200=y > > diff --git a/configs/ae350_rv32_spl_defconfig > > b/configs/ae350_rv32_spl_defconfig > > index aeb50206d2..41cd457bc3 100644 > > --- a/configs/ae350_rv32_spl_defconfig > > +++ b/configs/ae350_rv32_spl_defconfig > > @@ -33,6 +33,7 @@ CONFIG_SYS_PROMPT="RISC-V # " > > CONFIG_CMD_IMLS=y > > CONFIG_CMD_MMC=y > > CONFIG_CMD_SF_TEST=y > > +CONFIG_CMD_WDT=y > > # CONFIG_CMD_SETEXPR is not set > > CONFIG_BOOTP_PREFER_SERVERIP=y > > CONFIG_CMD_CACHE=y > > @@ -58,3 +59,6 @@ CONFIG_SYS_NS16550=y > > CONFIG_SPI=y > > CONFIG_ATCSPI200_SPI=y > > # CONFIG_BINMAN_FDT is not set > > +# CONFIG_WATCHDOG_AUTOSTART is not set > > +CONFIG_WDT=y > > +CONFIG_WDT_ATCWDT200=y > > diff --git a/configs/ae350_rv32_spl_xip_defconfig > > b/configs/ae350_rv32_spl_xip_defconfig > > index f15ec301ce..954e2f2de7 100644 > > --- a/configs/ae350_rv32_spl_xip_defconfig > > +++ b/configs/ae350_rv32_spl_xip_defconfig > > @@ -34,6 +34,7 @@ CONFIG_SYS_PROMPT="RISC-V # " > > CONFIG_CMD_IMLS=y > > CONFIG_CMD_MMC=y > > CONFIG_CMD_SF_TEST=y > > +CONFIG_CMD_WDT=y > > # CONFIG_CMD_SETEXPR is not set > > CONFIG_BOOTP_PREFER_SERVERIP=y > > CONFIG_CMD_CACHE=y > > @@ -59,3 +60,6 @@ CONFIG_SYS_NS16550=y > > CONFIG_SPI=y > > CONFIG_ATCSPI200_SPI=y > > # CONFIG_BINMAN_FDT is not set > > +# CONFIG_WATCHDOG_AUTOSTART is not set > > +CONFIG_WDT=y > > +CONFIG_WDT_ATCWDT200=y > > diff --git a/configs/ae350_rv32_xip_defconfig > > b/configs/ae350_rv32_xip_defconfig > > index c40eb043c5..95863595d2 100644 > > --- a/configs/ae350_rv32_xip_defconfig > > +++ b/configs/ae350_rv32_xip_defconfig > > @@ -24,6 +24,7 @@ CONFIG_SYS_PROMPT="RISC-V # " > > CONFIG_CMD_IMLS=y > > CONFIG_CMD_MMC=y > > CONFIG_CMD_SF_TEST=y > > +CONFIG_CMD_WDT=y > > # CONFIG_CMD_SETEXPR is not set > > CONFIG_BOOTP_PREFER_SERVERIP=y > > CONFIG_CMD_CACHE=y > > @@ -50,3 +51,6 @@ CONFIG_BAUDRATE=38400 > > CONFIG_SYS_NS16550=y > > CONFIG_SPI=y > > CONFIG_ATCSPI200_SPI=y > > +# CONFIG_WATCHDOG_AUTOSTART is not set > > +CONFIG_WDT=y > > +CONFIG_WDT_ATCWDT200=y > > diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig > > index 7ae938aeb2..988214285a 100644 > > --- a/configs/ae350_rv64_defconfig > > +++ b/configs/ae350_rv64_defconfig > > @@ -23,6 +23,7 @@ CONFIG_SYS_PROMPT="RISC-V # " > > CONFIG_CMD_IMLS=y > > CONFIG_CMD_MMC=y &g
[PATCH V4 2/2] configs: andes: add watchdog support fot andes ae350
It adds the ATCWDT200 support for Andes AE350 platform. It also enables wdt command support. Signed-off-by: CL Wang Signed-off-by: Randolph Reviewed-by: Leo Yu-Chi Liang --- configs/ae350_rv32_defconfig | 4 configs/ae350_rv32_spl_defconfig | 4 configs/ae350_rv32_spl_xip_defconfig | 4 configs/ae350_rv32_xip_defconfig | 4 configs/ae350_rv64_defconfig | 4 configs/ae350_rv64_spl_defconfig | 4 configs/ae350_rv64_spl_xip_defconfig | 4 configs/ae350_rv64_xip_defconfig | 4 8 files changed, 32 insertions(+) diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 3bfa3e9f8e..35ad62c845 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -49,3 +50,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index aeb50206d2..41cd457bc3 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -58,3 +59,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index f15ec301ce..954e2f2de7 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -34,6 +34,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -59,3 +60,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index c40eb043c5..95863595d2 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -24,6 +24,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -50,3 +51,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 7ae938aeb2..988214285a 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -49,3 +50,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 68ac4325ab..e929320433 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -58,3 +59,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 839ca335d4..3f92643b07 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -34,6 +34,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -59,3 +60,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index 5432b6d6d7..835f020990 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -24,6 +24,7
[PATCH V4 1/2] drivers: watchdog: add andes atcwdt200 support
This patch adds an implementation of the Andes watchdog ATCWDT200 driver.
Signed-off-by: CL Wang
Signed-off-by: Randolph
Reviewed-by: Leo Yu-Chi Liang
---
drivers/watchdog/Kconfig | 6 +
drivers/watchdog/Makefile| 1 +
drivers/watchdog/atcwdt200_wdt.c | 220 +++
3 files changed, 227 insertions(+)
create mode 100644 drivers/watchdog/atcwdt200_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 569726119c..8318fd77a3 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -130,6 +130,12 @@ config WDT_AT91
Select this to enable Microchip watchdog timer, which can be found on
some AT91 devices.
+config WDT_ATCWDT200
+ bool "Andes watchdog timer support"
+ depends on WDT
+ help
+ Select this to enable Andes ATCWDT200 watchdog timer
+
config WDT_BCM6345
bool "BCM6345 watchdog timer support"
depends on WDT && (ARCH_BMIPS || BCM6856 || \
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 5520d3d9ae..7b39adcf0f 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_WDT_ARM_SMC) += arm_smc_wdt.o
obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o
+obj-$(CONFIG_WDT_ATCWDT200) += atcwdt200_wdt.o
obj-$(CONFIG_WDT_BCM2835) += bcm2835_wdt.o
obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o
diff --git a/drivers/watchdog/atcwdt200_wdt.c b/drivers/watchdog/atcwdt200_wdt.c
new file mode 100644
index 00..a29b42d607
--- /dev/null
+++ b/drivers/watchdog/atcwdt200_wdt.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Andes Technology Corporation.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define NODE_NOT_FOUND 0x
+
+#define WDT_WP_MAGIC 0x5aa5
+#define WDT_RESTART_MAGIC 0xcafe
+
+/* Control Register */
+#define REG_WDT_ID 0x00
+#define REG_WDT_CFG0x10
+#define REG_WDT_RS 0x14
+#define REG_WDT_WE 0x18
+#define REG_WDT_STA0x1C
+
+#define RST_TIME_OFF 8
+#define RST_TIME_MSK (0x7 << RST_TIME_OFF)
+#define RST_CLK_128(0 << RST_TIME_OFF)
+#define RST_CLK_256(1 << RST_TIME_OFF)
+#define RST_CLK_512(2 << RST_TIME_OFF)
+#define RST_CLK_1024 (3 << RST_TIME_OFF)
+#define INT_TIME_OFF 4
+#define INT_TIME_MSK (0xf << INT_TIME_OFF)
+#define INT_CLK_2_6(0 << INT_TIME_OFF) /* clk period*2^6 */
+#define INT_CLK_2_8(1 << INT_TIME_OFF) /* clk period*2^8 */
+#define INT_CLK_2_10 (2 << INT_TIME_OFF) /* clk period*2^10 */
+#define INT_CLK_2_11 (3 << INT_TIME_OFF) /* clk period*2^11 */
+#define INT_CLK_2_12 (4 << INT_TIME_OFF) /* clk period*2^12 */
+#define INT_CLK_2_13 (5 << INT_TIME_OFF) /* clk period*2^13 */
+#define INT_CLK_2_14 (6 << INT_TIME_OFF) /* clk period*2^14 */
+#define INT_CLK_2_15 (7 << INT_TIME_OFF) /* clk period*2^15 */
+#define INT_CLK_2_17 (8 << INT_TIME_OFF) /* clk period*2^17 */
+#define INT_CLK_2_19 (9 << INT_TIME_OFF) /* clk period*2^19 */
+#define INT_CLK_2_21 (10 << INT_TIME_OFF) /* clk period*2^21 */
+#define INT_CLK_2_23 (11 << INT_TIME_OFF) /* clk period*2^23 */
+#define INT_CLK_2_25 (12 << INT_TIME_OFF) /* clk period*2^25 */
+#define INT_CLK_2_27 (13 << INT_TIME_OFF) /* clk period*2^27 */
+#define INT_CLK_2_29 (14 << INT_TIME_OFF) /* clk period*2^29 */
+#define INT_CLK_2_31 (15 << INT_TIME_OFF) /* clk period*2^31 */
+#define INT_CLK_MIN0x0
+#define INT_CLK_MAX_16B0x7
+#define INT_CLK_MAX_32B0xF
+#define RST_EN BIT(3)
+#define INT_EN BIT(2)
+#define CLK_PCLK BIT(1)
+#define WDT_EN BIT(0)
+#define INT_EXPIREDBIT(0)
+
+#define INT_TIME_ARRAY 16
+#define RST_TIME_ARRAY 8
+
+struct wdt_priv {
+ void __iomem *base;
+ u32 wdt_clk_src;
+ u32 clk_freq;
+ u8 max_clk;
+};
+
+static inline u8 atcwdt_get_2_power_of_n(u8 index, u8 type)
+{
+ const u8 div_int[INT_TIME_ARRAY] = {6, 8, 10, 11, 12, 13, 14, 15,
+ 17, 19, 21, 23, 25, 27, 29, 31};
+ const u8 div_rst[RST_TIME_ARRAY] = {7, 8, 9, 10, 11, 12, 13, 14};
+ const u8 *pdiv;
+
+ if (type == RST_TIME_ARRAY)
+ pdiv = div_rst;
+ else
+ pdiv = div_int;
+
+ if (index >= type)
+ index = type - 1;
+
+ return pdiv[index];
+}
+
+static u8 atcwdt_search_msb(u64 freq_ms, u8 type)
+{
+ u64 result;
+ u64 freq_sec;
+ u8 index;
+
+ freq_sec = freq_ms /
[PATCH V4 3/3] configs: andes: add the fdt blob copy address for SPL
Add the address to which the FDT blob is to be moved. Signed-off-by: Randolph --- configs/ae350_rv32_falcon_defconfig | 1 + configs/ae350_rv32_falcon_xip_defconfig | 1 + configs/ae350_rv64_falcon_defconfig | 1 + configs/ae350_rv64_falcon_xip_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/ae350_rv32_falcon_defconfig b/configs/ae350_rv32_falcon_defconfig index 3f2993e371..c0837322bb 100644 --- a/configs/ae350_rv32_falcon_defconfig +++ b/configs/ae350_rv32_falcon_defconfig @@ -14,6 +14,7 @@ CONFIG_TARGET_ANDES_AE350=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y +CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x0170 CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x1000 diff --git a/configs/ae350_rv32_falcon_xip_defconfig b/configs/ae350_rv32_falcon_xip_defconfig index e4f4c7807c..d401e4963b 100644 --- a/configs/ae350_rv32_falcon_xip_defconfig +++ b/configs/ae350_rv32_falcon_xip_defconfig @@ -15,6 +15,7 @@ CONFIG_TARGET_ANDES_AE350=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y +CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x0170 CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x8001 diff --git a/configs/ae350_rv64_falcon_defconfig b/configs/ae350_rv64_falcon_defconfig index 4fb83d8240..b4ae5f9848 100644 --- a/configs/ae350_rv64_falcon_defconfig +++ b/configs/ae350_rv64_falcon_defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y +CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x0170 CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x1000 diff --git a/configs/ae350_rv64_falcon_xip_defconfig b/configs/ae350_rv64_falcon_xip_defconfig index 45464260ee..c7c8324d30 100644 --- a/configs/ae350_rv64_falcon_xip_defconfig +++ b/configs/ae350_rv64_falcon_xip_defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y +CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x0170 CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x8001 -- 2.34.1
[PATCH V4 2/3] spl: riscv: falcon: move fdt blob to specified address
In Falcon Boot mode, the fdt blob should be move to the RAM from
kernel BSS section. To avoid being cleared by BSS initialisation.
SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies.
Signed-off-by: Randolph
---
board/AndesTech/ae350/ae350.c | 25 -
common/spl/Kconfig| 2 +-
common/spl/spl_opensbi.c | 15 +++
3 files changed, 16 insertions(+), 26 deletions(-)
diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
index 772c6bf1ee..36375d9def 100644
--- a/board/AndesTech/ae350/ae350.c
+++ b/board/AndesTech/ae350/ae350.c
@@ -19,8 +19,6 @@
#include
#include
#include
-#include
-#include
DECLARE_GLOBAL_DATA_PTR;
@@ -28,29 +26,6 @@ DECLARE_GLOBAL_DATA_PTR;
* Miscellaneous platform dependent initializations
*/
-#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
-#define ANDES_SPL_FDT_ADDR (CONFIG_TEXT_BASE - 0x10)
-void spl_perform_fixups(struct spl_image_info *spl_image)
-{
- /*
-* Originally, u-boot-spl will place DTB directly after the kernel,
-* but the size of the kernel did not include the BSS section, which
-* means u-boot-spl will place the DTB in the kernel BSS section
-* causing the DTB to be cleared by kernel BSS initializtion.
-* Moving DTB in front of the kernel can avoid the error.
-*/
- if (ANDES_SPL_FDT_ADDR < 0) {
- printf("%s: CONFIG_TEXT_BASE needs to be larger than
0x10\n",
- __func__);
- hang();
- }
-
- memcpy((void *)ANDES_SPL_FDT_ADDR, spl_image->fdt_addr,
- fdt_totalsize(spl_image->fdt_addr));
- spl_image->fdt_addr = map_sysmem(ANDES_SPL_FDT_ADDR, 0);
-}
-#endif
-
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index c521b02f4a..bb283d823e 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -1081,7 +1081,7 @@ config SPL_OS_BOOT
config SPL_PAYLOAD_ARGS_ADDR
hex "Address in memory to load 'args' file for Falcon Mode to"
- depends on SPL_OS_BOOT
+ depends on SPL_OS_BOOT || SPL_LOAD_FIT_OPENSBI_OS_BOOT
default 0x8800 if ARCH_OMAP2PLUS
help
Address in memory where the 'args' file, typically a device tree
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index 9801d38c0b..8127ebc946 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -57,6 +58,20 @@ void __noreturn spl_invoke_opensbi(struct spl_image_info
*spl_image)
hang();
}
+ /*
+* Originally, u-boot-spl will place DTB directly after the kernel,
+* but the size of the kernel did not include the BSS section, which
+* means u-boot-spl will place the DTB in the kernel BSS section
+* causing the DTB to be cleared by kernel BSS initializtion.
+* Moving DTB in front of the kernel can avoid the error.
+*/
+#if CONFIG_IS_ENABLED(LOAD_FIT_OPENSBI_OS_BOOT) && \
+CONFIG_IS_ENABLED(PAYLOAD_ARGS_ADDR)
+ memcpy((void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR, spl_image->fdt_addr,
+ fdt_totalsize(spl_image->fdt_addr));
+ spl_image->fdt_addr = map_sysmem(CONFIG_SPL_PAYLOAD_ARGS_ADDR, 0);
+#endif
+
/*
* Find next os image in /fit-images
* The next os image default is u-boot proper, once enable
--
2.34.1
[PATCH V4 1/3] doc: falcon: riscv: Falcon Mode boot on RISC-V
Add documentation to introduce the Falcon Mode on RISC-V. In this mode, the boot sequence is SPL -> OpenSBI -> Linux kernel. Signed-off-by: Randolph --- doc/develop/falcon.rst | 158 + 1 file changed, 158 insertions(+) diff --git a/doc/develop/falcon.rst b/doc/develop/falcon.rst index 8a46c0efa1..244b4ccb5c 100644 --- a/doc/develop/falcon.rst +++ b/doc/develop/falcon.rst @@ -256,3 +256,161 @@ the following command: Falcon Mode was presented at the RMLL 2012. Slides are available at: http://schedule2012.rmll.info/IMG/pdf/LSM2012_UbootFalconMode_Babic.pdf + +Falcon Mode Boot on RISC-V +-- + +Introduction + + +In the RISC-V environment, OpenSBI is required to enable a supervisor mode +binary to execute certain privileged operations. The typical boot sequence on +RISC-V is SPL -> OpenSBI -> U-Boot -> Linux kernel. SPL will load and start +the OpenSBI initializations, then OpenSBI will bring up the next image, U-Boot +proper. The OpenSBI binary must be prepared in advance of the U-Boot build +process and it will be packed together with U-Boot into a file called +u-boot.itb. + +The Falcon Mode on RISC-V platforms is a distinct boot sequence. Borrowing +ideas from the U-Boot Falcon Mode on ARM, it skips the U-Boot proper phase +in the normal boot process and allows OpenSBI to load and start the Linux +kernel. Its boot sequence is SPL -> OpenSBI -> Linux kernel. The OpenSBI +binary and Linux kernel binary must be prepared prior to the U-Boot build +process and they will be packed together as a FIT image named linux.itb in +this process. + +CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT enables the Falcon Mode boot on RISC-V. +This configuration setting tells OpenSBI that Linux kernel is its next OS +image and makes it load and start the kernel afterwards. + +Note that the Falcon Mode boot bypasses a lot of initializations by U-Boot. +If the Linux kernel expects hardware initializations by U-Boot, make sure to +port the relevant code to the SPL build process. + +Configuration +~ + +CONFIG_SPL_LOAD_FIT_ADDRESS +Specifies the address to load u-boot.itb in a normal boot. When the Falcon +Mode boot is enabled, it specifies the load address of linux.itb. + +CONFIG_SYS_TEXT_BASE +Specifies the address of the text section for a u-boot proper in a normal +boot. When the Falcon Mode boot is enabled, it specifies the text section +address for the Linux kernel image. + +CONFIG_SPL_PAYLOAD_ARGS_ADDR +The address in the RAM to which the FDT blob is to be moved by the SPL. +SPL places the FDT blob right after the kernel. As the kernel does not +include the BSS section in its size calculation, SPL ends up placing +the FDT blob within the BSS section of the kernel. This may cause the +FDT blob to be cleared during kernel BSS initialization. To avoid the +issue, be sure to move the FDT blob out of the kernel first. + +CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT +Activates the Falcon Mode boot on RISC-V. + +Example for Andes AE350 Board +~ + +A FDT blob is required to boot the Linux kernel from the SPL. Andes AE350 +platforms generally come with a builtin dtb. To load a custom DTB, follow +these steps: + +1. Load the custom DTB to SDRAM:: + +=> fatload mmc 0:1 0x2000 user_custom.dtb + +2. Set the SPI speed:: + +=> sf probe 0:0 5000 0 + +3. Erase sectors from the SPI Flash:: + +=> sf erase 0xf 0x1 + +4. Write the FDT blob to the erased sectors of the Flash:: + +=> sf write 0x2000 0xf 0x1 + +Console Log of AE350 Falcon Mode Boot +~ + +:: + +U-Boot SPL 2023.01-00031-g777ecdea66 (Oct 31 2023 - 18:41:36 +0800) +Trying to boot from RAM + +OpenSBI v1.2-51-g7304e42 + _ _ + / __ \ / | _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |) | |_) || |_ + \/| .__/ \___|_| |_|_/|/_| +| | +|_| + +Platform Name : andestech,ax25 +Platform Features : medeleg +Platform HART Count : 1 +Platform IPI Device : andes_plicsw +Platform Timer Device : andes_plmt @ 6000Hz +Platform Console Device : uart8250 +Platform HSM Device : andes_smu +Platform PMU Device : andes_pmu +Platform Reboot Device: atcwdt200 +Platform Shutdown Device : --- +Firmware Base : 0x0 +Firmware Size : 196 KB +Runtime SBI Version : 1.0 + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs
[PATCH V4 0/3] doc: falcon: riscv: Falcon Mode boot on RISC-V
Changes in v4: - remove "Function that a board must implement" section in falcon.rst - fix compile error when config LOAD_FIT_OPENSBI_OS_BOOT not enabled. Changes in v3: - Change by suggestions in falcon.rst - Move the board-related code to arch-specific code, its the issue when enabling LOAD_FIT_OPENSBI_OS_BOOT - Add SPL_PAYLOAD_ARGS_ADDR to defconfig. This is the address that SPL copies into defconfig. Randolph (3): doc: falcon: riscv: Falcon Mode boot on RISC-V spl: riscv: falcon: move fdt blob to specified address configs: andes: add the fdt blob copy address for SPL board/AndesTech/ae350/ae350.c | 25 common/spl/Kconfig | 2 +- common/spl/spl_opensbi.c| 15 +++ configs/ae350_rv32_falcon_defconfig | 1 + configs/ae350_rv32_falcon_xip_defconfig | 1 + configs/ae350_rv64_falcon_defconfig | 1 + configs/ae350_rv64_falcon_xip_defconfig | 1 + doc/develop/falcon.rst | 158 8 files changed, 178 insertions(+), 26 deletions(-) -- 2.34.1
[PATCH V3 2/2] configs: andes: add watchdog support fot andes ae350
It adds the ATCWDT200 support for Andes AE350 platform. It also enables wdt command support. Signed-off-by: CL Wang Signed-off-by: Randolph Reviewed-by: Leo Yu-Chi Liang --- configs/ae350_rv32_defconfig | 4 configs/ae350_rv32_spl_defconfig | 4 configs/ae350_rv32_spl_xip_defconfig | 4 configs/ae350_rv32_xip_defconfig | 4 configs/ae350_rv64_defconfig | 4 configs/ae350_rv64_spl_defconfig | 4 configs/ae350_rv64_spl_xip_defconfig | 4 configs/ae350_rv64_xip_defconfig | 4 8 files changed, 32 insertions(+) diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 06cd972a0d..eb4dd90311 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -48,3 +49,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index f469d5bb2b..e09f878329 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -57,3 +58,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 9672a19c23..850e67a0d9 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -58,3 +59,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index b90200a97e..fa0b52f686 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -49,3 +50,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index a4b9ad6162..e67c9cbf93 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -48,3 +49,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 834a0fbbdd..1a3c294b16 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -57,3 +58,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index b52b8d78d7..f8db0a1a85 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -58,3 +59,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index cc5e751c9b..51509e76c5 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y
[PATCH V3 1/2] drivers: watchdog: add andes atcwdt200 support
This patch adds an implementation of the Andes watchdog ATCWDT200 driver.
Signed-off-by: CL Wang
Signed-off-by: Randolph
Reviewed-by: Leo Yu-Chi Liang
---
drivers/watchdog/Kconfig | 6 +
drivers/watchdog/Makefile| 1 +
drivers/watchdog/atcwdt200_wdt.c | 220 +++
3 files changed, 227 insertions(+)
create mode 100644 drivers/watchdog/atcwdt200_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 569726119c..8318fd77a3 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -130,6 +130,12 @@ config WDT_AT91
Select this to enable Microchip watchdog timer, which can be found on
some AT91 devices.
+config WDT_ATCWDT200
+ bool "Andes watchdog timer support"
+ depends on WDT
+ help
+ Select this to enable Andes ATCWDT200 watchdog timer
+
config WDT_BCM6345
bool "BCM6345 watchdog timer support"
depends on WDT && (ARCH_BMIPS || BCM6856 || \
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 5520d3d9ae..7b39adcf0f 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_WDT_ARM_SMC) += arm_smc_wdt.o
obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o
+obj-$(CONFIG_WDT_ATCWDT200) += atcwdt200_wdt.o
obj-$(CONFIG_WDT_BCM2835) += bcm2835_wdt.o
obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o
diff --git a/drivers/watchdog/atcwdt200_wdt.c b/drivers/watchdog/atcwdt200_wdt.c
new file mode 100644
index 00..c6a8e4e054
--- /dev/null
+++ b/drivers/watchdog/atcwdt200_wdt.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Andes Technology Corporation.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define NODE_NOT_FOUND 0x
+
+#define WDT_WP_MAGIC 0x5aa5
+#define WDT_RESTART_MAGIC 0xcafe
+
+/* Control Register */
+#define REG_WDT_ID 0x00
+#define REG_WDT_CFG0x10
+#define REG_WDT_RS 0x14
+#define REG_WDT_WE 0x18
+#define REG_WDT_STA0x1C
+
+#define RST_TIME_OFF 8
+#define RST_TIME_MSK (0x7 << RST_TIME_OFF)
+#define RST_CLK_128(0 << RST_TIME_OFF)
+#define RST_CLK_256(1 << RST_TIME_OFF)
+#define RST_CLK_512(2 << RST_TIME_OFF)
+#define RST_CLK_1024 (3 << RST_TIME_OFF)
+#define INT_TIME_OFF 4
+#define INT_TIME_MSK (0xf << INT_TIME_OFF)
+#define INT_CLK_2_6(0 << INT_TIME_OFF) /* clk period*2^6 */
+#define INT_CLK_2_8(1 << INT_TIME_OFF) /* clk period*2^8 */
+#define INT_CLK_2_10 (2 << INT_TIME_OFF) /* clk period*2^10 */
+#define INT_CLK_2_11 (3 << INT_TIME_OFF) /* clk period*2^11 */
+#define INT_CLK_2_12 (4 << INT_TIME_OFF) /* clk period*2^12 */
+#define INT_CLK_2_13 (5 << INT_TIME_OFF) /* clk period*2^13 */
+#define INT_CLK_2_14 (6 << INT_TIME_OFF) /* clk period*2^14 */
+#define INT_CLK_2_15 (7 << INT_TIME_OFF) /* clk period*2^15 */
+#define INT_CLK_2_17 (8 << INT_TIME_OFF) /* clk period*2^17 */
+#define INT_CLK_2_19 (9 << INT_TIME_OFF) /* clk period*2^19 */
+#define INT_CLK_2_21 (10 << INT_TIME_OFF) /* clk period*2^21 */
+#define INT_CLK_2_23 (11 << INT_TIME_OFF) /* clk period*2^23 */
+#define INT_CLK_2_25 (12 << INT_TIME_OFF) /* clk period*2^25 */
+#define INT_CLK_2_27 (13 << INT_TIME_OFF) /* clk period*2^27 */
+#define INT_CLK_2_29 (14 << INT_TIME_OFF) /* clk period*2^29 */
+#define INT_CLK_2_31 (15 << INT_TIME_OFF) /* clk period*2^31 */
+#define INT_CLK_MIN0x0
+#define INT_CLK_MAX_16B0x7
+#define INT_CLK_MAX_32B0xF
+#define RST_EN BIT(3)
+#define INT_EN BIT(2)
+#define CLK_PCLK BIT(1)
+#define WDT_EN BIT(0)
+#define INT_EXPIREDBIT(0)
+
+#define INT_TIME_ARRAY 16
+#define RST_TIME_ARRAY 8
+
+struct wdt_priv {
+ void __iomem *base;
+ u32 wdt_clk_src;
+ u32 clk_freq;
+ u8 max_clk;
+};
+
+static inline u8 atcwdt_get_2_power_of_n(u8 index, u8 type)
+{
+ const u8 div_int[INT_TIME_ARRAY] = {6, 8, 10, 11, 12, 13, 14, 15,
+ 17, 19, 21, 23, 25, 27, 29, 31};
+ const u8 div_rst[RST_TIME_ARRAY] = {7, 8, 9, 10, 11, 12, 13, 14};
+ u8 *pdiv;
+
+ if (type == RST_TIME_ARRAY)
+ pdiv = div_rst;
+ else
+ pdiv = div_int;
+
+ if (index >= type)
+ index = type - 1;
+
+ return pdiv[index];
+}
+
+static u8 atcwdt_search_msb(u64 freq_ms, u8 type)
+{
+ u64 result;
+ u64 freq_sec;
+ u8 index;
+
+ freq_sec = freq_ms /
[PATCH V2 2/2] configs: andes: add watchdog support fot andes ae350
It adds the ATCWDT200 support for Andes AE350 platform. It also enables wdt command support. Signed-off-by: CL Wang Signed-off-by: Randolph --- configs/ae350_rv32_defconfig | 4 configs/ae350_rv32_spl_defconfig | 4 configs/ae350_rv32_spl_xip_defconfig | 4 configs/ae350_rv32_xip_defconfig | 4 configs/ae350_rv64_defconfig | 4 configs/ae350_rv64_spl_defconfig | 4 configs/ae350_rv64_spl_xip_defconfig | 4 configs/ae350_rv64_xip_defconfig | 4 8 files changed, 32 insertions(+) diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 06cd972a0d..eb4dd90311 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -48,3 +49,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index f469d5bb2b..e09f878329 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -57,3 +58,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 9672a19c23..850e67a0d9 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -58,3 +59,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index b90200a97e..fa0b52f686 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -49,3 +50,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index a4b9ad6162..e67c9cbf93 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -48,3 +49,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 834a0fbbdd..1a3c294b16 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -57,3 +58,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index b52b8d78d7..f8db0a1a85 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -58,3 +59,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index cc5e751c9b..51509e76c5 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y
[PATCH V2 1/2] drivers: watchdog: add andes atcwdt200 support
This patch adds an implementation of the Andes watchdog ATCWDT200 driver.
Signed-off-by: CL Wang
Signed-off-by: Randolph
---
drivers/watchdog/Kconfig | 6 +
drivers/watchdog/Makefile| 1 +
drivers/watchdog/atcwdt200_wdt.c | 220 +++
3 files changed, 227 insertions(+)
create mode 100644 drivers/watchdog/atcwdt200_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 07fc4940e9..6b0f77dd3f 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -130,6 +130,12 @@ config WDT_AT91
Select this to enable Microchip watchdog timer, which can be found on
some AT91 devices.
+config WDT_ATCWDT200
+ bool "Andes watchdog timer support"
+ depends on WDT
+ help
+ Select this to enable Andes ATCWDT200 watchdog timer
+
config WDT_BCM6345
bool "BCM6345 watchdog timer support"
depends on WDT && (ARCH_BMIPS || BCM6856 || \
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index eef786f5e7..1750ebbb1f 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_WDT_ARM_SMC) += arm_smc_wdt.o
obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o
+obj-$(CONFIG_WDT_ATCWDT200) += atcwdt200_wdt.o
obj-$(CONFIG_WDT_BCM2835) += bcm2835_wdt.o
obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o
diff --git a/drivers/watchdog/atcwdt200_wdt.c b/drivers/watchdog/atcwdt200_wdt.c
new file mode 100644
index 00..2a456d7a46
--- /dev/null
+++ b/drivers/watchdog/atcwdt200_wdt.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Andes Technology Corporation.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define NODE_NOT_FOUND 0x
+
+#define WDT_WP_MAGIC 0x5aa5
+#define WDT_RESTART_MAGIC 0xcafe
+
+/* Control Register */
+#define REG_WDT_ID 0x00
+#define REG_WDT_CFG0x10
+#define REG_WDT_RS 0x14
+#define REG_WDT_WE 0x18
+#define REG_WDT_STA0x1C
+
+#define RST_TIME_OFF 8
+#define RST_TIME_MSK (0x7 << RST_TIME_OFF)
+#define RST_CLK_128(0 << RST_TIME_OFF)
+#define RST_CLK_256(1 << RST_TIME_OFF)
+#define RST_CLK_512(2 << RST_TIME_OFF)
+#define RST_CLK_1024 (3 << RST_TIME_OFF)
+#define INT_TIME_OFF 4
+#define INT_TIME_MSK (0xf << INT_TIME_OFF)
+#define INT_CLK_2_6(0 << INT_TIME_OFF) /* clk period*2^6 */
+#define INT_CLK_2_8(1 << INT_TIME_OFF) /* clk period*2^8 */
+#define INT_CLK_2_10 (2 << INT_TIME_OFF) /* clk period*2^10 */
+#define INT_CLK_2_11 (3 << INT_TIME_OFF) /* clk period*2^11 */
+#define INT_CLK_2_12 (4 << INT_TIME_OFF) /* clk period*2^12 */
+#define INT_CLK_2_13 (5 << INT_TIME_OFF) /* clk period*2^13 */
+#define INT_CLK_2_14 (6 << INT_TIME_OFF) /* clk period*2^14 */
+#define INT_CLK_2_15 (7 << INT_TIME_OFF) /* clk period*2^15 */
+#define INT_CLK_2_17 (8 << INT_TIME_OFF) /* clk period*2^17 */
+#define INT_CLK_2_19 (9 << INT_TIME_OFF) /* clk period*2^19 */
+#define INT_CLK_2_21 (10 << INT_TIME_OFF) /* clk period*2^21 */
+#define INT_CLK_2_23 (11 << INT_TIME_OFF) /* clk period*2^23 */
+#define INT_CLK_2_25 (12 << INT_TIME_OFF) /* clk period*2^25 */
+#define INT_CLK_2_27 (13 << INT_TIME_OFF) /* clk period*2^27 */
+#define INT_CLK_2_29 (14 << INT_TIME_OFF) /* clk period*2^29 */
+#define INT_CLK_2_31 (15 << INT_TIME_OFF) /* clk period*2^31 */
+#define INT_CLK_MIN0x0
+#define INT_CLK_MAX_16B0x7
+#define INT_CLK_MAX_32B0xF
+#define RST_EN BIT(3)
+#define INT_EN BIT(2)
+#define CLK_PCLK BIT(1)
+#define WDT_EN BIT(0)
+#define INT_EXPIREDBIT(0)
+
+#define INT_TIME_ARRAY 16
+#define RST_TIME_ARRAY 8
+
+struct wdt_priv {
+ void __iomem *base;
+ u32 wdt_clk_src;
+ u32 clk_freq;
+ u8 max_clk;
+};
+
+static inline u8 atcwdt_get_2_power_of_n(u8 index, u8 type)
+{
+ const u8 div_int[INT_TIME_ARRAY] = {6, 8, 10, 11, 12, 13, 14, 15,
+ 17, 19, 21, 23, 25, 27, 29, 31};
+ const u8 div_rst[RST_TIME_ARRAY] = {7, 8, 9, 10, 11, 12, 13, 14};
+ u8 *pdiv;
+
+ if (type == RST_TIME_ARRAY)
+ pdiv = div_rst;
+ else
+ pdiv = div_int;
+
+ if (index >= type)
+ index = type - 1;
+
+ return pdiv[index];
+}
+
+static u8 atwdt_search_msb(u64 freq_ms, u8 type)
+{
+ u64 result;
+ u64 freq_sec;
+ u8 index;
+
+ freq_sec = freq_ms / 1000;
+ for (index = 0; i
[PATCH RESEND 2/2] configs: andes: add watchdog support fot andes ae350
It adds the ATCWDT200 support for Andes AE350 platform. It also enables wdt command support. Signed-off-by: CL Wang Signed-off-by: Randolph --- configs/ae350_rv32_defconfig | 4 configs/ae350_rv32_spl_defconfig | 4 configs/ae350_rv32_spl_xip_defconfig | 4 configs/ae350_rv32_xip_defconfig | 4 configs/ae350_rv64_defconfig | 4 configs/ae350_rv64_spl_defconfig | 4 configs/ae350_rv64_spl_xip_defconfig | 4 configs/ae350_rv64_xip_defconfig | 4 8 files changed, 32 insertions(+) diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 06cd972a0d..a32672f8ed 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -48,3 +49,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y \ No newline at end of file diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index f469d5bb2b..e09f878329 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -57,3 +58,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 9672a19c23..850e67a0d9 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -58,3 +59,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index b90200a97e..8745ac4c07 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -49,3 +50,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y \ No newline at end of file diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index a4b9ad6162..4aa0b1a29d 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -48,3 +49,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y \ No newline at end of file diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 834a0fbbdd..1a3c294b16 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -57,3 +58,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index b52b8d78d7..f8db0a1a85 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -58,3 +59,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index cc5e751c9b..70119f154a 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -23,6 +23,7
[PATCH RESEND 1/2] drivers: watchdog: add andes atcwdt200 support
This patch adds an implementation of the Andes watchdog ATCWDT200 driver.
Signed-off-by: CL Wang
Signed-off-by: Randolph
---
drivers/watchdog/Kconfig | 6 +
drivers/watchdog/Makefile| 1 +
drivers/watchdog/atcwdt200_wdt.c | 219 +++
3 files changed, 226 insertions(+)
create mode 100644 drivers/watchdog/atcwdt200_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 07fc4940e9..6b0f77dd3f 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -130,6 +130,12 @@ config WDT_AT91
Select this to enable Microchip watchdog timer, which can be found on
some AT91 devices.
+config WDT_ATCWDT200
+ bool "Andes watchdog timer support"
+ depends on WDT
+ help
+ Select this to enable Andes ATCWDT200 watchdog timer
+
config WDT_BCM6345
bool "BCM6345 watchdog timer support"
depends on WDT && (ARCH_BMIPS || BCM6856 || \
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index eef786f5e7..1750ebbb1f 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_WDT_ARM_SMC) += arm_smc_wdt.o
obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o
+obj-$(CONFIG_WDT_ATCWDT200) += atcwdt200_wdt.o
obj-$(CONFIG_WDT_BCM2835) += bcm2835_wdt.o
obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o
diff --git a/drivers/watchdog/atcwdt200_wdt.c b/drivers/watchdog/atcwdt200_wdt.c
new file mode 100644
index 00..dc34013473
--- /dev/null
+++ b/drivers/watchdog/atcwdt200_wdt.c
@@ -0,0 +1,219 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Andes Technology Corporation.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define NODE_NOT_FOUND 0x
+
+#define WDT_WP_MAGIC 0x5aa5
+#define WDT_RESTART_MAGIC 0xcafe
+
+/* Control Register */
+#define REG_WDT_ID 0x00
+#define REG_WDT_CFG0x10
+#define REG_WDT_RS 0x14
+#define REG_WDT_WE 0x18
+#define REG_WDT_STA0x1C
+
+#define RST_TIME_OFF 8
+#define RST_TIME_MSK (0x7 << RST_TIME_OFF)
+#define RST_CLK_128(0 << RST_TIME_OFF)
+#define RST_CLK_256(1 << RST_TIME_OFF)
+#define RST_CLK_512(2 << RST_TIME_OFF)
+#define RST_CLK_1024 (3 << RST_TIME_OFF)
+#define INT_TIME_OFF 4
+#define INT_TIME_MSK (0xf << INT_TIME_OFF)
+#define INT_CLK_2_6(0 << INT_TIME_OFF) /* clk period*2^6 */
+#define INT_CLK_2_8(1 << INT_TIME_OFF) /* clk period*2^8 */
+#define INT_CLK_2_10 (2 << INT_TIME_OFF) /* clk period*2^10 */
+#define INT_CLK_2_11 (3 << INT_TIME_OFF) /* clk period*2^11 */
+#define INT_CLK_2_12 (4 << INT_TIME_OFF) /* clk period*2^12 */
+#define INT_CLK_2_13 (5 << INT_TIME_OFF) /* clk period*2^13 */
+#define INT_CLK_2_14 (6 << INT_TIME_OFF) /* clk period*2^14 */
+#define INT_CLK_2_15 (7 << INT_TIME_OFF) /* clk period*2^15 */
+#define INT_CLK_2_17 (8 << INT_TIME_OFF) /* clk period*2^17 */
+#define INT_CLK_2_19 (9 << INT_TIME_OFF) /* clk period*2^19 */
+#define INT_CLK_2_21 (10 << INT_TIME_OFF) /* clk period*2^21 */
+#define INT_CLK_2_23 (11 << INT_TIME_OFF) /* clk period*2^23 */
+#define INT_CLK_2_25 (12 << INT_TIME_OFF) /* clk period*2^25 */
+#define INT_CLK_2_27 (13 << INT_TIME_OFF) /* clk period*2^27 */
+#define INT_CLK_2_29 (14 << INT_TIME_OFF) /* clk period*2^29 */
+#define INT_CLK_2_31 (15 << INT_TIME_OFF) /* clk period*2^31 */
+#define INT_CLK_MIN0x0
+#define INT_CLK_MAX_16B0x7
+#define INT_CLK_MAX_32B0xF
+#define RST_EN BIT(3)
+#define INT_EN BIT(2)
+#define CLK_PCLK BIT(1)
+#define WDT_EN BIT(0)
+#define INT_EXPIREDBIT(0)
+
+#define INT_TIME_ARRAY 16
+#define RST_TIME_ARRAY 8
+
+struct wdt_priv {
+ void __iomem *base;
+ u32 wdt_clk_src;
+ u32 clk_freq;
+ u8 max_clk;
+};
+
+static inline u8 atcwdt_get_2_power_of_n(u8 index, u8 type)
+{
+ u8 div_int[INT_TIME_ARRAY] = {6, 8, 10, 11, 12, 13, 14, 15, 17, 19, 21,
23, 25, 27, 29, 31};
+ u8 div_rst[RST_TIME_ARRAY] = {7, 8, 9, 10, 11, 12, 13, 14};
+ u8 *pdiv;
+
+ if (type == RST_TIME_ARRAY)
+ pdiv = div_rst;
+ else
+ pdiv = div_int;
+
+ if (index >= type)
+ index = type - 1;
+
+ return pdiv[index];
+}
+
+static u8 atwdt_search_msb(u64 freq_ms, u8 type)
+{
+ u64 result;
+ u64 freq_sec;
+ u8 index;
+
+ freq_sec = freq_ms / 1000;
+ for (index = 0; index < type; index++) {
+ result = freq_sec >>
[PATCH V3] riscv: binman: fix the load field format
Using /bits/ 64 prefix for 64 bits address
Signed-off-by: Randolph
Reviewed-by: Simon Glass
---
arch/riscv/dts/binman.dtsi | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index 6b4eb8dc7b..9271de0ddf 100644
--- a/arch/riscv/dts/binman.dtsi
+++ b/arch/riscv/dts/binman.dtsi
@@ -5,9 +5,6 @@
#include
-#define U64_TO_U32_H(addr) (((addr) >> 32) & 0x)
-#define U64_TO_U32_L(addr) ((addr) & 0x)
-
/ {
binman: binman {
multiple-images;
@@ -36,8 +33,7 @@
os = "U-Boot";
arch = "riscv";
compression = "none";
- load = ;
+ load = /bits/ 64 ;
uboot_blob: blob-ext {
filename = "u-boot-nodtb.bin";
@@ -50,7 +46,7 @@
os = "Linux";
arch = "riscv";
compression = "none";
- load = ;
+ load = /bits/ 64 ;
linux_blob: blob-ext {
filename = "Image";
@@ -64,10 +60,8 @@
os = "opensbi";
arch = "riscv";
compression = "none";
- load =
;
- entry =
;
+ load = /bits/ 64
;
+ entry = /bits/ 64
;
opensbi_blob: opensbi {
filename = "fw_dynamic.bin";
--
2.34.1
[PATCH V3 2/3] spl: riscv: falcon: move fdt blob to specified address
In Falcon Boot mode, the fdt blob should be move to the RAM from
kernel BSS section. To avoid being cleared by BSS initialisation.
SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies.
Signed-off-by: Randolph
---
board/AndesTech/ae350/ae350.c | 25 -
common/spl/Kconfig| 2 +-
common/spl/spl_opensbi.c | 16
3 files changed, 17 insertions(+), 26 deletions(-)
diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
index 772c6bf1ee..36375d9def 100644
--- a/board/AndesTech/ae350/ae350.c
+++ b/board/AndesTech/ae350/ae350.c
@@ -19,8 +19,6 @@
#include
#include
#include
-#include
-#include
DECLARE_GLOBAL_DATA_PTR;
@@ -28,29 +26,6 @@ DECLARE_GLOBAL_DATA_PTR;
* Miscellaneous platform dependent initializations
*/
-#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
-#define ANDES_SPL_FDT_ADDR (CONFIG_TEXT_BASE - 0x10)
-void spl_perform_fixups(struct spl_image_info *spl_image)
-{
- /*
-* Originally, u-boot-spl will place DTB directly after the kernel,
-* but the size of the kernel did not include the BSS section, which
-* means u-boot-spl will place the DTB in the kernel BSS section
-* causing the DTB to be cleared by kernel BSS initializtion.
-* Moving DTB in front of the kernel can avoid the error.
-*/
- if (ANDES_SPL_FDT_ADDR < 0) {
- printf("%s: CONFIG_TEXT_BASE needs to be larger than
0x10\n",
- __func__);
- hang();
- }
-
- memcpy((void *)ANDES_SPL_FDT_ADDR, spl_image->fdt_addr,
- fdt_totalsize(spl_image->fdt_addr));
- spl_image->fdt_addr = map_sysmem(ANDES_SPL_FDT_ADDR, 0);
-}
-#endif
-
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 25cd18afda..db279a588a 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -1081,7 +1081,7 @@ config SPL_OS_BOOT
config SPL_PAYLOAD_ARGS_ADDR
hex "Address in memory to load 'args' file for Falcon Mode to"
- depends on SPL_OS_BOOT
+ depends on SPL_OS_BOOT || SPL_LOAD_FIT_OPENSBI_OS_BOOT
default 0x8800 if ARCH_OMAP2PLUS
help
Address in memory where the 'args' file, typically a device tree
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index 9801d38c0b..0a8ee9a7fc 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -57,6 +58,21 @@ void __noreturn spl_invoke_opensbi(struct spl_image_info
*spl_image)
hang();
}
+ /*
+* Originally, u-boot-spl will place DTB directly after the kernel,
+* but the size of the kernel did not include the BSS section, which
+* means u-boot-spl will place the DTB in the kernel BSS section
+* causing the DTB to be cleared by kernel BSS initializtion.
+* Moving DTB in front of the kernel can avoid the error.
+*/
+ if (CONFIG_IS_ENABLED(LOAD_FIT_OPENSBI_OS_BOOT)) {
+ memcpy((void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR,
+ spl_image->fdt_addr,
+ fdt_totalsize(spl_image->fdt_addr));
+ spl_image->fdt_addr =
+ map_sysmem(CONFIG_SPL_PAYLOAD_ARGS_ADDR, 0);
+ }
+
/*
* Find next os image in /fit-images
* The next os image default is u-boot proper, once enable
--
2.34.1
[PATCH V3 3/3] configs: andes: add the fdt blob address for SPL copy to
Add the address where the FDT blob should be moved. Signed-off-by: Randolph --- configs/ae350_rv32_falcon_defconfig | 1 + configs/ae350_rv32_falcon_xip_defconfig | 1 + configs/ae350_rv64_falcon_defconfig | 1 + configs/ae350_rv64_falcon_xip_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/ae350_rv32_falcon_defconfig b/configs/ae350_rv32_falcon_defconfig index 3f2993e371..c0837322bb 100644 --- a/configs/ae350_rv32_falcon_defconfig +++ b/configs/ae350_rv32_falcon_defconfig @@ -14,6 +14,7 @@ CONFIG_TARGET_ANDES_AE350=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y +CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x0170 CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x1000 diff --git a/configs/ae350_rv32_falcon_xip_defconfig b/configs/ae350_rv32_falcon_xip_defconfig index e4f4c7807c..d401e4963b 100644 --- a/configs/ae350_rv32_falcon_xip_defconfig +++ b/configs/ae350_rv32_falcon_xip_defconfig @@ -15,6 +15,7 @@ CONFIG_TARGET_ANDES_AE350=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y +CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x0170 CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x8001 diff --git a/configs/ae350_rv64_falcon_defconfig b/configs/ae350_rv64_falcon_defconfig index 4fb83d8240..b4ae5f9848 100644 --- a/configs/ae350_rv64_falcon_defconfig +++ b/configs/ae350_rv64_falcon_defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y +CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x0170 CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x1000 diff --git a/configs/ae350_rv64_falcon_xip_defconfig b/configs/ae350_rv64_falcon_xip_defconfig index 45464260ee..c7c8324d30 100644 --- a/configs/ae350_rv64_falcon_xip_defconfig +++ b/configs/ae350_rv64_falcon_xip_defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y +CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x0170 CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x8001 -- 2.34.1
[PATCH V3 1/3] doc: falcon: riscv: Falcon Mode boot on RISC-V
Add documentation to introduce the Falcon Mode on RISC-V. In this mode, the boot sequence is SPL -> OpenSBI -> Linux kernel. Signed-off-by: Randolph --- doc/develop/falcon.rst | 171 + 1 file changed, 171 insertions(+) diff --git a/doc/develop/falcon.rst b/doc/develop/falcon.rst index 2f25fc8532..65644d1c57 100644 --- a/doc/develop/falcon.rst +++ b/doc/develop/falcon.rst @@ -256,3 +256,174 @@ the following command: Falcon Mode was presented at the RMLL 2012. Slides are available at: http://schedule2012.rmll.info/IMG/pdf/LSM2012_UbootFalconMode_Babic.pdf + +Falcon Mode Boot on RISC-V +-- + +Introduction + + +In the RISC-V environment, OpenSBI is required to enable a supervisor mode +binary to execute certain privileged operations. The typical boot sequence on +RISC-V is SPL -> OpenSBI -> U-Boot -> Linux kernel. SPL will load and start +the OpenSBI initializations, then OpenSBI will bring up the next image, U-Boot +proper. The OpenSBI binary must be prepared in advance of the U-Boot build +process and it will be packed together with U-Boot into a file called +u-boot.itb. + +The Falcon Mode on RISC-V platforms is a distinct boot sequence. Borrowing +ideas from the U-Boot Falcon Mode on ARM, it skips the U-Boot proper phase +in the normal boot process and allows OpenSBI to load and start the Linux +kernel. Its boot sequence is SPL -> OpenSBI -> Linux kernel. The OpenSBI +binary and Linux kernel binary must be prepared prior to the U-Boot build +process and they will be packed together as a FIT image named linux.itb in +this process. + +CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT enables the Falcon Mode boot on RISC-V. +This configuration setting tells OpenSBI that Linux kernel is its next OS +image and makes it load and start the kernel afterwards. + +Note that the Falcon Mode boot bypasses a lot of initializations by U-Boot. +If the Linux kernel expects hardware initializations by U-Boot, make sure to +port the relevant code to the SPL build process. + +Configuration +~ + +CONFIG_SPL_LOAD_FIT_ADDRESS +Specifies the address to load u-boot.itb in a normal boot. When the Falcon +Mode boot is enabled, it specifies the load address of linux.itb. + +CONFIG_SYS_TEXT_BASE +Specifies the address of the text section for a u-boot proper in a normal +boot. When the Falcon Mode boot is enabled, it specifies the text section +address for the Linux kernel image. + +CONFIG_SPL_PAYLOAD_ARGS_ADDR +The address in the RAM to which the FDT blob is to be moved by the SPL. + SPL places the FDT blob right after the kernel. As the kernel does not +include the BSS section in its size calculation, SPL ends up placing +the FDT blob within the BSS section of the kernel. This may cause the +FDT blob to be cleared during kernel BSS initialization. To avoid the +issue, be sure to move the FDT blob out of the kernel first. + +CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT +Activates the Falcon Mode boot on RISC-V. + +Function that a board must implement + + +Initially, SPL places the FDT blob right after the kernel. As the kernel does +not include the BSS section in its size calculation, SPL ends up placing the +FDT blob within the BSS section of the kernel. This may cause the FDT blob to +be cleared during kernel BSS initialization. To avoid the issue, be sure to +move the FDT blob out of the kernel first. + +void spl_perform_fixups(struct spl_image_info *spl_image) +required, necessary action to move the FDT blob out of the Linux kernel BSS +section + +Example for Andes AE350 Board +~ + +A FDT blob is required to boot the Linux kernel from the SPL. Andes AE350 +platforms generally come with a builtin dtb. If you want to load a custom DTB, +follow the steps below: + +1. Load the custom DTB to SDRAM:: + +=> fatload mmc 0:1 0x2000 user_custom.dtb + +2. Set the SPI speed:: + +=> sf probe 0:0 5000 0 + +3. Erase sectors from the SPI Flash:: + +=> sf erase 0xf 0x1 + +4. Write the FDT blob to the erased sectors of the Flash:: + +=> sf write 0x2000 0xf 0x1 + +Console Log of AE350 Falcon Mode Boot +~ + +:: + +U-Boot SPL 2023.01-00031-g777ecdea66 (Oct 31 2023 - 18:41:36 +0800) +Trying to boot from RAM + +OpenSBI v1.2-51-g7304e42 + _ _ + / __ \ / | _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |) | |_) || |_ + \/| .__/ \___|_| |_|_/|/_| +| | +|_| + +Platform Name : andestech,ax25 +Platform Features : medeleg +Platform HA
[PATCH V3 0/3] doc: falcon: riscv: Falcon Mode boot on RISC-V
Changes in v3: - Change by suggestions in falcon.rst - Move the board-related code to arch-specific code, its the issue when enabling LOAD_FIT_OPENSBI_OS_BOOT - Add SPL_PAYLOAD_ARGS_ADDR to defconfig. This is the address that SPL copies into defconfig. Randolph (3): doc: falcon: riscv: Falcon Mode boot on RISC-V spl: riscv: falcon: move fdt blob to specified address configs: andes: add the fdt blob address for SPL copy to board/AndesTech/ae350/ae350.c | 25 common/spl/Kconfig | 2 +- common/spl/spl_opensbi.c| 16 +++ configs/ae350_rv32_falcon_defconfig | 1 + configs/ae350_rv32_falcon_xip_defconfig | 1 + configs/ae350_rv64_falcon_defconfig | 1 + configs/ae350_rv64_falcon_xip_defconfig | 1 + doc/develop/falcon.rst | 171 8 files changed, 192 insertions(+), 26 deletions(-) -- 2.34.1
[PATCH V2] riscv: binman: fix the load field format
Using /bits/64 prefix for 64bits address
Signed-off-by: Randolph
---
arch/riscv/dts/binman.dtsi | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index 6b4eb8dc7b..777b1309d0 100644
--- a/arch/riscv/dts/binman.dtsi
+++ b/arch/riscv/dts/binman.dtsi
@@ -5,9 +5,6 @@
#include
-#define U64_TO_U32_H(addr) (((addr) >> 32) & 0x)
-#define U64_TO_U32_L(addr) ((addr) & 0x)
-
/ {
binman: binman {
multiple-images;
@@ -36,8 +33,7 @@
os = "U-Boot";
arch = "riscv";
compression = "none";
- load = ;
+ load = /bits/64 ;
uboot_blob: blob-ext {
filename = "u-boot-nodtb.bin";
@@ -50,7 +46,7 @@
os = "Linux";
arch = "riscv";
compression = "none";
- load = ;
+ load = /bits/64 ;
linux_blob: blob-ext {
filename = "Image";
@@ -64,10 +60,8 @@
os = "opensbi";
arch = "riscv";
compression = "none";
- load =
;
- entry =
;
+ load = /bits/64
;
+ entry = /bits/64
;
opensbi_blob: opensbi {
filename = "fw_dynamic.bin";
--
2.34.1
Re: [PATCH] riscv: binman: fix the load field format
Hi Simon,
Thanks a lot.
On Fri, Nov 10, 2023 at 04:50:24AM -0700, Simon Glass wrote:
> Hi Randolph,
>
> On Wed, Nov 8, 2023, 20:15 Randolph wrote:
> >
> > The #address-cells is now equal to 2. The format of the load field for
> > the Linux kernel doesn't match.
> >
> > Signed-off-by: Randolph
> > ---
> > arch/riscv/dts/binman.dtsi | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
> > index 6b4eb8dc7b..5117d7c8c9 100644
> > --- a/arch/riscv/dts/binman.dtsi
> > +++ b/arch/riscv/dts/binman.dtsi
> > @@ -50,7 +50,8 @@
> > os = "Linux";
> > arch = "riscv";
> > compression = "none";
> > - load = ;
> > + load =
> > > +
> > U64_TO_U32_L(CONFIG_TEXT_BASE)>;
>
I just see the #address-cells changed from 1 to 2 in commit id: 5a348ccf0257.
In my last commit for binman.dtsi (commit id: d311df8b3169), it is based on
the value of #address-cells being 1. That's the reason for my patch submission.
> Does this work?
>
> load = /bits 64/
>
Yes, it works. We use this way for the DDR memory start address above 4G
platform. We find the example for 64bit address in the document
tools/binman/binman.rst and use it.
What is the method that we should continue to use in the binman.dtsi?
1. #address-cells = 2
2. append /bits/64
> >
> > linux_blob: blob-ext {
> > filename = "Image";
> > --
> > 2.34.1
> >
>
> Regards,
> Simon
[PATCH 1/2] drivers: watchdog: add andes atcwdt200 support
This patch adds an implementation of the Andes watchdog ATCWDT200 driver.
Signed-off-by: CL Wang
Signed-off-by: Randolph
---
drivers/watchdog/Kconfig | 6 +
drivers/watchdog/Makefile| 1 +
drivers/watchdog/atcwdt200_wdt.c | 219 +++
3 files changed, 226 insertions(+)
create mode 100644 drivers/watchdog/atcwdt200_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 07fc4940e9..6b0f77dd3f 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -130,6 +130,12 @@ config WDT_AT91
Select this to enable Microchip watchdog timer, which can be found on
some AT91 devices.
+config WDT_ATCWDT200
+ bool "Andes watchdog timer support"
+ depends on WDT
+ help
+ Select this to enable Andes ATCWDT200 watchdog timer
+
config WDT_BCM6345
bool "BCM6345 watchdog timer support"
depends on WDT && (ARCH_BMIPS || BCM6856 || \
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index eef786f5e7..1750ebbb1f 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_WDT_ARM_SMC) += arm_smc_wdt.o
obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o
+obj-$(CONFIG_WDT_ATCWDT200) += atcwdt200_wdt.o
obj-$(CONFIG_WDT_BCM2835) += bcm2835_wdt.o
obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o
diff --git a/drivers/watchdog/atcwdt200_wdt.c b/drivers/watchdog/atcwdt200_wdt.c
new file mode 100644
index 00..dc34013473
--- /dev/null
+++ b/drivers/watchdog/atcwdt200_wdt.c
@@ -0,0 +1,219 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Andes Technology Corporation.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define NODE_NOT_FOUND 0x
+
+#define WDT_WP_MAGIC 0x5aa5
+#define WDT_RESTART_MAGIC 0xcafe
+
+/* Control Register */
+#define REG_WDT_ID 0x00
+#define REG_WDT_CFG0x10
+#define REG_WDT_RS 0x14
+#define REG_WDT_WE 0x18
+#define REG_WDT_STA0x1C
+
+#define RST_TIME_OFF 8
+#define RST_TIME_MSK (0x7 << RST_TIME_OFF)
+#define RST_CLK_128(0 << RST_TIME_OFF)
+#define RST_CLK_256(1 << RST_TIME_OFF)
+#define RST_CLK_512(2 << RST_TIME_OFF)
+#define RST_CLK_1024 (3 << RST_TIME_OFF)
+#define INT_TIME_OFF 4
+#define INT_TIME_MSK (0xf << INT_TIME_OFF)
+#define INT_CLK_2_6(0 << INT_TIME_OFF) /* clk period*2^6 */
+#define INT_CLK_2_8(1 << INT_TIME_OFF) /* clk period*2^8 */
+#define INT_CLK_2_10 (2 << INT_TIME_OFF) /* clk period*2^10 */
+#define INT_CLK_2_11 (3 << INT_TIME_OFF) /* clk period*2^11 */
+#define INT_CLK_2_12 (4 << INT_TIME_OFF) /* clk period*2^12 */
+#define INT_CLK_2_13 (5 << INT_TIME_OFF) /* clk period*2^13 */
+#define INT_CLK_2_14 (6 << INT_TIME_OFF) /* clk period*2^14 */
+#define INT_CLK_2_15 (7 << INT_TIME_OFF) /* clk period*2^15 */
+#define INT_CLK_2_17 (8 << INT_TIME_OFF) /* clk period*2^17 */
+#define INT_CLK_2_19 (9 << INT_TIME_OFF) /* clk period*2^19 */
+#define INT_CLK_2_21 (10 << INT_TIME_OFF) /* clk period*2^21 */
+#define INT_CLK_2_23 (11 << INT_TIME_OFF) /* clk period*2^23 */
+#define INT_CLK_2_25 (12 << INT_TIME_OFF) /* clk period*2^25 */
+#define INT_CLK_2_27 (13 << INT_TIME_OFF) /* clk period*2^27 */
+#define INT_CLK_2_29 (14 << INT_TIME_OFF) /* clk period*2^29 */
+#define INT_CLK_2_31 (15 << INT_TIME_OFF) /* clk period*2^31 */
+#define INT_CLK_MIN0x0
+#define INT_CLK_MAX_16B0x7
+#define INT_CLK_MAX_32B0xF
+#define RST_EN BIT(3)
+#define INT_EN BIT(2)
+#define CLK_PCLK BIT(1)
+#define WDT_EN BIT(0)
+#define INT_EXPIREDBIT(0)
+
+#define INT_TIME_ARRAY 16
+#define RST_TIME_ARRAY 8
+
+struct wdt_priv {
+ void __iomem *base;
+ u32 wdt_clk_src;
+ u32 clk_freq;
+ u8 max_clk;
+};
+
+static inline u8 atcwdt_get_2_power_of_n(u8 index, u8 type)
+{
+ u8 div_int[INT_TIME_ARRAY] = {6, 8, 10, 11, 12, 13, 14, 15, 17, 19, 21,
23, 25, 27, 29, 31};
+ u8 div_rst[RST_TIME_ARRAY] = {7, 8, 9, 10, 11, 12, 13, 14};
+ u8 *pdiv;
+
+ if (type == RST_TIME_ARRAY)
+ pdiv = div_rst;
+ else
+ pdiv = div_int;
+
+ if (index >= type)
+ index = type - 1;
+
+ return pdiv[index];
+}
+
+static u8 atwdt_search_msb(u64 freq_ms, u8 type)
+{
+ u64 result;
+ u64 freq_sec;
+ u8 index;
+
+ freq_sec = freq_ms / 1000;
+ for (index = 0; index < type; index++) {
+ result = freq_sec >>
[PATCH 2/2] configs: andes: add watchdog support fot andes ae350
It adds the ATCWDT200 support for Andes AE350 platform. It also enables wdt command support. Signed-off-by: CL Wang Signed-off-by: Randolph --- configs/ae350_rv32_defconfig | 4 configs/ae350_rv32_spl_defconfig | 4 configs/ae350_rv32_spl_xip_defconfig | 4 configs/ae350_rv32_xip_defconfig | 4 configs/ae350_rv64_defconfig | 4 configs/ae350_rv64_spl_defconfig | 4 configs/ae350_rv64_spl_xip_defconfig | 4 configs/ae350_rv64_xip_defconfig | 4 8 files changed, 32 insertions(+) diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 06cd972a0d..a32672f8ed 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -48,3 +49,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y \ No newline at end of file diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index f469d5bb2b..e09f878329 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -57,3 +58,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 9672a19c23..850e67a0d9 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -58,3 +59,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index b90200a97e..8745ac4c07 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -49,3 +50,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y \ No newline at end of file diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index a4b9ad6162..4aa0b1a29d 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -48,3 +49,6 @@ CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y \ No newline at end of file diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 834a0fbbdd..1a3c294b16 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -57,3 +58,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index b52b8d78d7..f8db0a1a85 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y @@ -58,3 +59,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index cc5e751c9b..70119f154a 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -23,6 +23,7
[PATCH] riscv: binman: fix the load field format
The #address-cells is now equal to 2. The format of the load field for
the Linux kernel doesn't match.
Signed-off-by: Randolph
---
arch/riscv/dts/binman.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index 6b4eb8dc7b..5117d7c8c9 100644
--- a/arch/riscv/dts/binman.dtsi
+++ b/arch/riscv/dts/binman.dtsi
@@ -50,7 +50,8 @@
os = "Linux";
arch = "riscv";
compression = "none";
- load = ;
+ load = ;
linux_blob: blob-ext {
filename = "Image";
--
2.34.1
[PATCH V2] doc: falcon: riscv: Falcon Mode boot on RISC-V
Add documentation to introduce the Falcon Mode on RISC-V. In this mode, the boot sequence is SPL -> OpenSBI -> Linux kernel. Signed-off-by: Randolph --- doc/develop/falcon.rst | 159 + 1 file changed, 159 insertions(+) diff --git a/doc/develop/falcon.rst b/doc/develop/falcon.rst index 2f25fc8532..b553f0d0ea 100644 --- a/doc/develop/falcon.rst +++ b/doc/develop/falcon.rst @@ -256,3 +256,162 @@ the following command: Falcon Mode was presented at the RMLL 2012. Slides are available at: http://schedule2012.rmll.info/IMG/pdf/LSM2012_UbootFalconMode_Babic.pdf + +Falcon Mode Boot on RISC-V +-- + +Introduction + + +In the RISC-V environment, OpenSBI is required to enable a supervisor mode +to execute certain privileged operations. The typical boot sequence on +RISC-V is SPL -> OpenSBI -> U-Boot -> Linux kernel. SPL will load and start +the OpenSBI initializations, then OpenSBI will bring up the next image, U-Boot. +The OpenSBI binary must be prepared in advance of the U-Boot build process +and it will be packed together with U-Boot into a file called u-boot.itb. + +The Falcon Mode on RISC-V platforms is a distinct boot process. Borrowing +ideas from the U-Boot Falcon Mode on ARM, it skips the U-Boot proper phase +in the normal boot process and allows OpenSBI to load and start the Linux +kernel. Its boot sequence is SPL -> OpenSBI -> Linux kernel. The OpenSBI +binary and Linux kernel binary must be prepared prior to the U-Boot build +process and they will be packed together as linux.itb in this process. + +CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT enables the Falcon Mode boot on RISC-V. +This configuration tells OpenSBI that Linux kernel is its next OS image and +makes it load and start the kernel afterwards. + +Note that the Falcon Mode boot bypasses a lot of initializations by U-Boot. +If the Linux kernel expects hardware initializations by U-Boot, make sure to +port the relevant code to the SPL build process. + +Configurations +-- + +CONFIG_SPL_LOAD_FIT_ADDRESS +Specifies the address to load u-boot.itb in a normal boot. When the Falcon +Mode boot is enabled, it specifies the load address of linux.itb. + +CONFIG_SYS_TEXT_BASE +Specifies the address of the text section for a u-boot proper in a normal +boot. When the Falcon Mode boot is enabled, it specifies the text section +address for the Linux kernel image. + +CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT +Activates the Falcon Mode boot on RISC-V. + +Function that a board must implement + + +Initially, SPL places the FDT blob right after the kernel. As the kernel does +not include the BSS section in its size calculation, SPL ends up placing the +FDT blob within the BSS section of the kernel. This may cause the FDT blob to +be cleared during kernel BSS initialization. To avoid the issue, be sure to +move the FDT blob out of the kernel first. + +void spl_perform_fixups(struct spl_image_info *spl_image) +required, necessary action to move the FDT blob out of the Linux kernel BSS +section + +Example for Andes AE350 Board +- + +A FDT blob is required to boot the Linux kernel from the SPL. Andes AE350 +platforms generally come with a builtin dtb. If you want to load a custom DTB, +follow the steps below: + +1. Load the custom DTB to SDRAM:: + +=> fatload mmc 0:1 0x2000 user_custom.dtb + +2. Set the SPI speed:: + +=> sf probe 0:0 5000 0 + +3. Erase sectors from the SPI Flash:: + +=> sf erase 0xf 0x1 + +4. Write the FDT blob to the erased sectors of the Flash:: + +=> sf write 0x2000 0xf 0x1 + +Console Log of AE350 Falcon Mode Boot +- + +U-Boot SPL 2023.01-00031-g777ecdea66 (Oct 31 2023 - 18:41:36 +0800) +Trying to boot from RAM + +OpenSBI v1.2-51-g7304e42 + _ _ + / __ \ / | _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |) | |_) || |_ + \/| .__/ \___|_| |_|_/|/_| +| | +|_| + +Platform Name : andestech,ax25 +Platform Features : medeleg +Platform HART Count : 1 +Platform IPI Device : andes_plicsw +Platform Timer Device : andes_plmt @ 6000Hz +Platform Console Device : uart8250 +Platform HSM Device : andes_smu +Platform PMU Device : andes_pmu +Platform Reboot Device: atcwdt200 +Platform Shutdown Device : --- +Firmware Base : 0x0 +Firmware Size : 196 KB +Runtime SBI Version : 1.0 + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs : 0* +Domain0 Region00 : 0x-0x0003 () +Domain0 Region01 : 0xe600-0x
[PATCH] doc: falcon: riscv: Falcon Mode boot on RISC-V
Add documentation to introduce the Falcon Mode on RISC-V In this mode, boot sequence is SPL -> OpenSBI -> Linux kernel. Signed-off-by: Randolph --- doc/develop/falcon.rst | 159 + 1 file changed, 159 insertions(+) diff --git a/doc/develop/falcon.rst b/doc/develop/falcon.rst index 2f25fc8532..75648c76d7 100644 --- a/doc/develop/falcon.rst +++ b/doc/develop/falcon.rst @@ -256,3 +256,162 @@ the following command: Falcon Mode was presented at the RMLL 2012. Slides are available at: http://schedule2012.rmll.info/IMG/pdf/LSM2012_UbootFalconMode_Babic.pdf + +Falcon Mode Boot on RISC-V +-- + +Introduction + + +In the RISC-V environment, OpenSBI is required to enable a supervisor to +execute certain privileged operations. The typical boot sequence on +RISC-V is SPL -> OpenSBI -> u-boot proper -> Linux kernel. SPL will load +and start the OpenSBI initializations, then OpenSBI will bring up the next +image, U-Boot proper. The OpenSBI binary must be prepared in advance of the +u-boot build process and it will be packed together with u-boot proper into +a file called u-boot.itb. + +The Falcon Mode is a distinct boot process for RISC-V platforms. Borrowing +ideas from the U-Boot Falcon Mode, it skips the U-Boot proper phase in the +normal boot process and allows OpenSBI to load and start the Linux kernel. +Its boot sequence is SPL -> OpenSBI -> Linux kernel. The OpenSBI binary and +Linux kernel binary must be prepared prior to the u-boot build process and +they will be packed together as linux.itb in this process. + +To enable the Falcon boot on RISC-V, CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT +is set. This configuration tells OpenSBI that Linux kernel is its next +OS image and makes it load and start the kernel afterwards. + +Note that the Falcon boot bypasses a lot of initializations by U-Boot. If the +Linux kernel expects hardware initializations by U-Boot, make sure to port the +relevant code to the SPL build process. + +Configurations +-- + +CONFIG_SPL_LOAD_FIT_ADDRESS +Specifies the address to load u-boot.itb in a normal boot. When the Falcon +boot is enabled, it specifies the load address of linux.itb. + +CONFIG_SYS_TEXT_BASE +Specifies the address of the text section for a u-boot proper in a normal +boot. When the falcon boot is enabled, it specifies the text section address +for the Linux kernel image. + +CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT +Activates the Falcon boot on RISC-V. + +Function that a board must implement + + +Initially, SPL places the FDT blob right after the kernel. As the kernel does +not include the BSS section in its size calculation, SPL ends up placing the +FDT blob within the BSS section of the kernel. This may cause the FDT blob to +be cleared during kernel BSS initialization. To avoid the issue, be sure to +move the FDT blob out of the kernel first. + +void spl_perform_fixups(struct spl_image_info *spl_image) +required, necessary action to move the FDT blob out of the Linux kernel BSS section + +Example for Andes AE350 Board +- + +A FDT blob is required to boot the Linux kernel from the SPL. Andes AE350 +platforms generally come with a builtin dtb. If you want to load a custom FDT +blob, follow the steps below: + +1. Load the custom FDT blob to SDRAM:: + +=> fatload mmc 0:1 0x2000 user_custom.dtb + +2. Set the SPI speed:: + +=> sf probe 0:0 5000 0 + +3. Erase sectors from the SPI Flash:: + +=> sf erase 0xf 0x1 + +4. Write the FDT blob to the erased sectors of the Flash:: + +=> sf write 0x2000 0xf 0x1 + +Console Log of AE350 Falcon Boot + + +U-Boot SPL 2023.01-00031-g777ecdea66 (Oct 31 2023 - 18:41:36 +0800) +Trying to boot from RAM + +OpenSBI v1.2-51-g7304e42 + _ _ + / __ \ / | _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |) | |_) || |_ + \/| .__/ \___|_| |_|_/|/_| +| | +|_| + +Platform Name : andestech,ax25 +Platform Features : medeleg +Platform HART Count : 1 +Platform IPI Device : andes_plicsw +Platform Timer Device : andes_plmt @ 6000Hz +Platform Console Device : uart8250 +Platform HSM Device : andes_smu +Platform PMU Device : andes_pmu +Platform Reboot Device: atcwdt200 +Platform Shutdown Device : --- +Firmware Base : 0x0 +Firmware Size : 196 KB +Runtime SBI Version : 1.0 + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs : 0* +Domain0 Region00 : 0x-0x0003 () +Domain0 Region01 : 0xe600-0x
Re: Falcon mode on RISC-V
On Thu, Oct 19, 2023 at 10:49:56PM +0200, Heinrich Schuchardt wrote: Hi Heinrich > Hello Randolph, > > I just saw your patches merged to enable Falcon mode on RISC-V using > CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT. I did not see any documentation update. > > Should information about your development be added to > doc/develop/falcon.rst? Would you be willing to provide a patch? > > Best regards > > Heinrich Thanks a lot, I will update it ASAP. Randolph Sincerely
[PATCH V2 7/7] riscv: spl: andes: Move the DTB in front of kernel
Originally, u-boot SPL will place the DTB directly after the kernel,
but the size of the kernel does not include the BSS section, This
means that u-boot SPL places the DTB in the kernel BSS section causing
the DTB to be cleared by the kernel BSS initialisation.
Moving the DTB in front of the kernel can avoid this error.
Signed-off-by: Randolph
---
board/AndesTech/ae350/ae350.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
index 1c2288b6ce..d78ee403e6 100644
--- a/board/AndesTech/ae350/ae350.c
+++ b/board/AndesTech/ae350/ae350.c
@@ -19,6 +19,8 @@
#include
#include
#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -26,6 +28,29 @@ DECLARE_GLOBAL_DATA_PTR;
* Miscellaneous platform dependent initializations
*/
+#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
+#define ANDES_SPL_FDT_ADDR (CONFIG_TEXT_BASE - 0x10)
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+ /*
+* Originally, u-boot-spl will place DTB directly after the kernel,
+* but the size of the kernel did not include the BSS section, which
+* means u-boot-spl will place the DTB in the kernel BSS section
+* causing the DTB to be cleared by kernel BSS initializtion.
+* Moving DTB in front of the kernel can avoid the error.
+*/
+ if (ANDES_SPL_FDT_ADDR < 0) {
+ printf("%s: CONFIG_TEXT_BASE needs to be larger than
0x10\n",
+ __func__);
+ hang();
+ }
+
+ memcpy((void *)ANDES_SPL_FDT_ADDR, spl_image->fdt_addr,
+ fdt_totalsize(spl_image->fdt_addr));
+ spl_image->fdt_addr = map_sysmem(ANDES_SPL_FDT_ADDR, 0);
+}
+#endif
+
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
--
2.34.1
[PATCH V2 6/7] andes: config: add riscv falcon mode for ae350 platform
Fork from ae350_rv[32/64]_spl_[xip]_defconfig and append CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y Signed-off-by: Randolph --- configs/ae350_rv32_falcon_defconfig | 60 configs/ae350_rv32_falcon_xip_defconfig | 61 + configs/ae350_rv64_falcon_defconfig | 60 configs/ae350_rv64_falcon_xip_defconfig | 61 + 4 files changed, 242 insertions(+) create mode 100644 configs/ae350_rv32_falcon_defconfig create mode 100644 configs/ae350_rv32_falcon_xip_defconfig create mode 100644 configs/ae350_rv64_falcon_defconfig create mode 100644 configs/ae350_rv64_falcon_xip_defconfig diff --git a/configs/ae350_rv32_falcon_defconfig b/configs/ae350_rv32_falcon_defconfig new file mode 100644 index 00..8f796d88e3 --- /dev/null +++ b/configs/ae350_rv32_falcon_defconfig @@ -0,0 +1,60 @@ +CONFIG_RISCV=y +CONFIG_TEXT_BASE=0x0180 +CONFIG_SYS_MALLOC_LEN=0x8 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DEFAULT_DEVICE_TREE="ae350_32" +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SYS_MONITOR_LEN=786432 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x200 +CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x10 +CONFIG_TARGET_ANDES_AE350=y +CONFIG_RISCV_SMODE=y +# CONFIG_AVAILABLE_HARTS is not set +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x1000 +CONFIG_SYS_MONITOR_BASE=0x8800 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x10 +CONFIG_SPL_BSS_START_ADDR=0x40 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x400 +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 +CONFIG_SYS_CFI_FLASH_STATUS_POLL=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y +# CONFIG_BINMAN_FDT is not set +CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y \ No newline at end of file diff --git a/configs/ae350_rv32_falcon_xip_defconfig b/configs/ae350_rv32_falcon_xip_defconfig new file mode 100644 index 00..e01dd6fc51 --- /dev/null +++ b/configs/ae350_rv32_falcon_xip_defconfig @@ -0,0 +1,61 @@ +CONFIG_RISCV=y +CONFIG_TEXT_BASE=0x0180 +CONFIG_SYS_MALLOC_LEN=0x8 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DEFAULT_DEVICE_TREE="ae350_32" +CONFIG_SPL_TEXT_BASE=0x8000 +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SYS_MONITOR_LEN=786432 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x200 +CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x10 +CONFIG_TARGET_ANDES_AE350=y +CONFIG_RISCV_SMODE=y +CONFIG_SPL_XIP=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x8001 +CONFIG_SYS_MONITOR_BASE=0x8800 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x10 +CONFIG_SPL_BSS_START_ADDR=0x40 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x400 +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 +CONFIG_SYS_CFI_FLASH_STATUS_POLL=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y +# CONFIG_BINMAN_FDT is not set +CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y \ No newline at end of file diff --git a/configs/ae350_rv64_falcon_defconfig b/configs/ae350_rv64_falcon_defconfig new file mode 100644 index 00..d11be976de --- /dev/null +++ b/configs/ae350_rv64_falcon_defconfig @@ -0,0 +1,60 @@ +CONFIG_RISCV=y +CONFIG_TEXT_BASE=0x0180 +CONFIG_SYS_MALLOC_LEN=0x8 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DEFAULT_D
[PATCH V2 4/7] Makefile: delete file *.itb when make clean
Delete the output file *.itb Signed-off-by: Randolph --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 9d2e31e494..a7aa8c02a0 100644 --- a/Makefile +++ b/Makefile @@ -2165,7 +2165,7 @@ CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \ mkimage-out.spl.mkimage mkimage.spl.mkimage imx-boot.map \ itb.fit.fit itb.fit.itb itb.map spl.map mkimage-out.rom.mkimage \ mkimage.rom.mkimage rom.map simple-bin.map simple-bin-spi.map \ - idbloader-spi.img lib/efi_loader/helloworld_efi.S + idbloader-spi.img lib/efi_loader/helloworld_efi.S *.itb # Directories & files removed with 'make mrproper' MRPROPER_DIRS += include/config include/generated spl tpl vpl \ -- 2.34.1
[PATCH V2 5/7] spl: riscv: add os type for next booting stage
If SPL_LOAD_FIT_OPENSBI_OS_BOOT is enabled, the function
spl_invoke_opensbi should change the target OS type to IH_OS_LINUX.
OpenSBI will load the Linux image as the next boot stage.
The os_takes_devicetree function returns a value of true or false
depending on whether or not SPL_LOAD_FIT_OPENSBI_OS_BOOT is enabled.
Signed-off-by: Randolph
---
common/spl/spl_fit.c | 3 ++-
common/spl/spl_opensbi.c | 9 +++--
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index ce6b8aa370..e9126f07f7 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -366,7 +366,8 @@ static bool os_takes_devicetree(uint8_t os)
case IH_OS_U_BOOT:
return true;
case IH_OS_LINUX:
- return IS_ENABLED(CONFIG_SPL_OS_BOOT);
+ return IS_ENABLED(CONFIG_SPL_OS_BOOT) ||
+ IS_ENABLED(CONFIG_SPL_OPENSBI);
default:
return false;
}
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index 6583b31953..9801d38c0b 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -59,9 +59,14 @@ void __noreturn spl_invoke_opensbi(struct spl_image_info
*spl_image)
/*
* Find next os image in /fit-images
-* The next os image default is u-boot proper
+* The next os image default is u-boot proper, once enable
+* OpenSBI OS boot mode, the OS image should be linux.
*/
- os_type = IH_OS_U_BOOT;
+ if (CONFIG_IS_ENABLED(LOAD_FIT_OPENSBI_OS_BOOT))
+ os_type = IH_OS_LINUX;
+ else
+ os_type = IH_OS_U_BOOT;
+
ret = spl_opensbi_find_os_node(spl_image->fdt_addr, _node, os_type);
if (ret) {
pr_err("Can't find %s node for opensbi, %d\n",
--
2.34.1
[PATCH V2 1/7] spl: riscv: opensbi: change the default os_type as varible
In order to introduce the Opensbi OS boot mode, the next stage boot
image of OpenSBI should be configurable.
Signed-off-by: Randolph
Reviewed-by: Simon Glass
---
common/spl/spl_opensbi.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index 0df611623a..6583b31953 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -21,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR;
struct fw_dynamic_info opensbi_info;
-static int spl_opensbi_find_uboot_node(void *blob, int *uboot_node)
+static int spl_opensbi_find_os_node(void *blob, int *uboot_node, int os_type)
{
int fit_images_node, node;
const char *fit_os;
@@ -35,7 +35,7 @@ static int spl_opensbi_find_uboot_node(void *blob, int
*uboot_node)
if (!fit_os)
continue;
- if (genimg_get_os_id(fit_os) == IH_OS_U_BOOT) {
+ if (genimg_get_os_id(fit_os) == os_type) {
*uboot_node = node;
return 0;
}
@@ -46,8 +46,9 @@ static int spl_opensbi_find_uboot_node(void *blob, int
*uboot_node)
void __noreturn spl_invoke_opensbi(struct spl_image_info *spl_image)
{
- int ret, uboot_node;
- ulong uboot_entry;
+ int ret, os_node;
+ ulong os_entry;
+ int os_type;
typedef void __noreturn (*opensbi_entry_t)(ulong hartid, ulong dtb,
ulong info);
opensbi_entry_t opensbi_entry;
@@ -56,22 +57,27 @@ void __noreturn spl_invoke_opensbi(struct spl_image_info
*spl_image)
hang();
}
- /* Find U-Boot image in /fit-images */
- ret = spl_opensbi_find_uboot_node(spl_image->fdt_addr, _node);
+ /*
+* Find next os image in /fit-images
+* The next os image default is u-boot proper
+*/
+ os_type = IH_OS_U_BOOT;
+ ret = spl_opensbi_find_os_node(spl_image->fdt_addr, _node, os_type);
if (ret) {
- pr_err("Can't find U-Boot node, %d\n", ret);
+ pr_err("Can't find %s node for opensbi, %d\n",
+ genimg_get_os_name(os_type), ret);
hang();
}
/* Get U-Boot entry point */
- ret = fit_image_get_entry(spl_image->fdt_addr, uboot_node,
_entry);
+ ret = fit_image_get_entry(spl_image->fdt_addr, os_node, _entry);
if (ret)
- ret = fit_image_get_load(spl_image->fdt_addr, uboot_node,
_entry);
+ ret = fit_image_get_load(spl_image->fdt_addr, os_node,
_entry);
/* Prepare opensbi_info object */
opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE;
opensbi_info.version = FW_DYNAMIC_INFO_VERSION;
- opensbi_info.next_addr = uboot_entry;
+ opensbi_info.next_addr = os_entry;
opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
opensbi_info.options = CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS;
opensbi_info.boot_hart = gd->arch.boot_hart;
--
2.34.1
[PATCH V2 3/7] riscv: dts: binman: add condition for opensbi os boot
Add condition for OpenSBI OS boot mode, by default it is not enabled.
By default, binman creates the output file u-boot.itb.
If SPL_OPENSBI_OS_BOOT is enabled, linux.itb will be created
after compilation instead of the default u-boot.itb.
Signed-off-by: Randolph
---
arch/riscv/dts/binman.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index 156cb00971..1a55097d71 100644
--- a/arch/riscv/dts/binman.dtsi
+++ b/arch/riscv/dts/binman.dtsi
@@ -13,7 +13,12 @@
{
itb {
+
+#ifndef CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT
filename = "u-boot.itb";
+#else
+ filename = "linux.itb";
+#endif
fit {
description = "Configuration to load OpenSBI before
U-Boot";
@@ -21,6 +26,7 @@
fit,fdt-list = "of-list";
images {
+#ifndef CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT
uboot {
description = "U-Boot";
type = "standalone";
@@ -33,6 +39,20 @@
filename = "u-boot-nodtb.bin";
};
};
+#else
+ linux {
+ description = "Linux";
+ type = "standalone";
+ os = "Linux";
+ arch = "riscv";
+ compression = "none";
+ load = ;
+
+ linux_blob: blob-ext {
+ filename = "Image";
+ };
+ };
+#endif
opensbi {
description = "OpenSBI fw_dynamic
Firmware";
@@ -68,7 +88,11 @@
#endif
description = "NAME";
firmware = "opensbi";
+#ifndef CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT
loadables = "uboot";
+#else
+ loadables = "linux";
+#endif
#ifndef CONFIG_OF_BOARD
fdt = "fdt-SEQ";
#endif
--
2.34.1
[PATCH V2 2/7] riscv: kconfig: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbol
Introduce common Kconfig symbol for riscv architecture. This symbol SPL_LOAD_FIT_OPENSBI_OS_BOOT is like falcon mode on ARM, the Falcon boot is a shortcut boot method for SD/eMMC targets. It skips the loading the RAM version U-Boot. Instead, it will loads the FIT image and boots directly to Linux. When SPL_OPENSBI_OS_BOOT is enabled, linux.itb is created after compilation instead of the default u-boot.itb. It initialises memory with the U-Boot SPL at the first stage, just as a normal boot process does at the beginning. Instead of jumping to the U-Boot proper from OpenSBI before booting the Linux kernel, the RISC-V falcon mode process jumps directly to the Linux kernel to gain shorter booting time. Signed-off-by: Randolph --- arch/riscv/Kconfig | 8 1 file changed, 8 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 183885ebe7..49b6e1a4d6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -424,4 +424,12 @@ config TPL_USE_ARCH_MEMSET endmenu +config SPL_LOAD_FIT_OPENSBI_OS_BOOT + bool "Enable SPL (OpenSBI OS boot mode) applying linux from FIT" + depends on SPL_LOAD_FIT + help + Use fw_dynamic from the FIT image, and u-boot SPL will invoke it directly. + This is a shortcut boot flow, from u-boot SPL -> OpenSBI -> u-boot proper + -> linux to u-boot SPL -> OpenSBI -> linux. + endmenu -- 2.34.1
[PATCH V2 0/7] riscv: spl: OpenSBI OS boot mode
Introduce a shortcut boot mode for RISC-V. As we know, in ARM architecture has the Falcon mode to do the shortcut boot to the Linux kernel. (by enabling CONFIG_SPL_OS_BOOT) ARM Falcon mode boot flow would be as follows: u-boot SPL -> Linux kernel But for RISC-V, OpenSBI is required to allows the supervisor to execute some privileged operations. The RISC-V Normal boot flow as follows: u-boot SPL -> OpenSBI -> u-boot proper -> Linux kernel Quoting the same ideas as ARM's Falcon mode, OpenSBI OS boot flow as follows: u-boot SPL -> OpenSBI -> Linux kernel An important part of OpenSBI OS boot mode is to prepare the device tree. A normal U-Boot does FDT fixups when booting Linux. For OpenSBI OS boot mode, Linux boots directly from SPL, skipping the normal U-Boot. The device tree has to be prepared in advance. The device tree in memory is the one needed for OpenSBI OS boot mode. The Linux kernel image will also need to be provided for the generation of the FIT file. Changes in v2: - change the order from Patch 3/7 in V1 to Patch 1/7 in V2 - merge the OPENSBI_OS_BOOT related logic into binman.dtsi - change by suggestions - add a new patch to delete the output file when make clean. Randolph (7): spl: riscv: opensbi: change the default os_type as varible riscv: kconfig: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbol riscv: dts: binman: add condition for opensbi os boot Makefile: delete file *.itb when make clean spl: riscv: add os type for next booting stage andes: config: add riscv falcon mode for ae350 platform riscv: spl: andes: Move the DTB in front of kernel Makefile| 2 +- arch/riscv/Kconfig | 8 arch/riscv/dts/binman.dtsi | 24 ++ board/AndesTech/ae350/ae350.c | 25 ++ common/spl/spl_fit.c| 3 +- common/spl/spl_opensbi.c| 31 + configs/ae350_rv32_falcon_defconfig | 60 configs/ae350_rv32_falcon_xip_defconfig | 61 + configs/ae350_rv64_falcon_defconfig | 60 configs/ae350_rv64_falcon_xip_defconfig | 61 + 10 files changed, 323 insertions(+), 12 deletions(-) create mode 100644 configs/ae350_rv32_falcon_defconfig create mode 100644 configs/ae350_rv32_falcon_xip_defconfig create mode 100644 configs/ae350_rv64_falcon_defconfig create mode 100644 configs/ae350_rv64_falcon_xip_defconfig -- 2.34.1
[PATCH] riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy
Source hart information is not necessary in IPI, so we could
use single-bit-per-hart strategy to rearrange PLICSW mapping.
Bit 0 of Interrupt Pending Bits is hardwired to 0.
Therefore, we use bit 1 to send IPI to hart 0,
bit 2 to hart 1, ..., and so on.
Signed-off-by: Randolph
---
arch/riscv/lib/andes_plicsw.c | 24 +++-
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/arch/riscv/lib/andes_plicsw.c b/arch/riscv/lib/andes_plicsw.c
index 7518408089..6fd49e873b 100644
--- a/arch/riscv/lib/andes_plicsw.c
+++ b/arch/riscv/lib/andes_plicsw.c
@@ -22,7 +22,7 @@
#include
/* pending register */
-#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 + ((hart) / 4)
* 4)
+#define PENDING_REG(base) ((ulong)(base) + 0x1000)
/* enable register */
#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
/* claim register */
@@ -30,10 +30,11 @@
/* priority register */
#define PRIORITY_REG(base) ((ulong)(base) + PLICSW_PRIORITY_BASE)
-#define ENABLE_HART_IPI (0x01010101)
-#define SEND_IPI_TO_HART(hart) (0x1 << (hart))
+/* Bit 0 of PLIC-SW pending array is hardwired to zero, so we start from bit 1
*/
+#define FIRST_AVAILABLE_BIT0x2
+#define SEND_IPI_TO_HART(hart) (FIRST_AVAILABLE_BIT << (hart))
#define PLICSW_PRIORITY_BASE0x4
-#define PLICSW_INTERRUPT_PER_HART 0x8
+#define PLICSW_INTERRUPT_PER_HART 0x1
DECLARE_GLOBAL_DATA_PTR;
@@ -41,9 +42,8 @@ static int enable_ipi(int hart)
{
unsigned int en;
- en = ENABLE_HART_IPI << hart;
+ en = FIRST_AVAILABLE_BIT << hart;
writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart));
- writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw + 0x4, hart));
return 0;
}
@@ -75,7 +75,7 @@ int riscv_init_ipi(void)
ret = uclass_find_first_device(UCLASS_CPU, );
if (ret)
return ret;
- else if (!dev)
+ if (!dev)
return -ENODEV;
ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
@@ -105,10 +105,9 @@ int riscv_init_ipi(void)
int riscv_send_ipi(int hart)
{
- unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
+ unsigned int ipi = SEND_IPI_TO_HART(hart);
- writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw,
- gd->arch.boot_hart));
+ writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw));
return 0;
}
@@ -125,10 +124,9 @@ int riscv_clear_ipi(int hart)
int riscv_get_ipi(int hart, int *pending)
{
- unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
+ unsigned int ipi = SEND_IPI_TO_HART(hart);
- *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw,
-gd->arch.boot_hart));
+ *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw));
*pending = !!(*pending & ipi);
return 0;
--
2.34.1
[PATCH RESEND 7/7] riscv: spl: andes: Move the DTB in front of kernel
Originally, u-boot SPL will place the DTB directly after the kernel,
but the size of the kernel does not include the BSS section, This
means that u-boot SPL places the DTB in the kernel BSS section causing
the DTB to be cleared by the kernel BSS initialisation.
Moving the DTB in front of the kernel can avoid this error.
Signed-off-by: Randolph
---
board/AndesTech/ae350/ae350.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
index 1c2288b6ce..d78ee403e6 100644
--- a/board/AndesTech/ae350/ae350.c
+++ b/board/AndesTech/ae350/ae350.c
@@ -19,6 +19,8 @@
#include
#include
#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -26,6 +28,29 @@ DECLARE_GLOBAL_DATA_PTR;
* Miscellaneous platform dependent initializations
*/
+#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
+#define ANDES_SPL_FDT_ADDR (CONFIG_TEXT_BASE - 0x10)
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+ /*
+* Originally, u-boot-spl will place DTB directly after the kernel,
+* but the size of the kernel did not include the BSS section, which
+* means u-boot-spl will place the DTB in the kernel BSS section
+* causing the DTB to be cleared by kernel BSS initializtion.
+* Moving DTB in front of the kernel can avoid the error.
+*/
+ if (ANDES_SPL_FDT_ADDR < 0) {
+ printf("%s: CONFIG_TEXT_BASE needs to be larger than
0x10\n",
+ __func__);
+ hang();
+ }
+
+ memcpy((void *)ANDES_SPL_FDT_ADDR, spl_image->fdt_addr,
+ fdt_totalsize(spl_image->fdt_addr));
+ spl_image->fdt_addr = map_sysmem(ANDES_SPL_FDT_ADDR, 0);
+}
+#endif
+
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
--
2.34.1
[PATCH RESEND 6/7] andes: config: add riscv falcon mode for ae350 platform
Fork from ae350_rv[32/64]_spl_[xip]_defconfig and append CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y Signed-off-by: Randolph --- configs/ae350_rv32_falcon_defconfig | 60 configs/ae350_rv32_falcon_xip_defconfig | 61 + configs/ae350_rv64_falcon_defconfig | 60 configs/ae350_rv64_falcon_xip_defconfig | 61 + 4 files changed, 242 insertions(+) create mode 100644 configs/ae350_rv32_falcon_defconfig create mode 100644 configs/ae350_rv32_falcon_xip_defconfig create mode 100644 configs/ae350_rv64_falcon_defconfig create mode 100644 configs/ae350_rv64_falcon_xip_defconfig diff --git a/configs/ae350_rv32_falcon_defconfig b/configs/ae350_rv32_falcon_defconfig new file mode 100644 index 00..8f796d88e3 --- /dev/null +++ b/configs/ae350_rv32_falcon_defconfig @@ -0,0 +1,60 @@ +CONFIG_RISCV=y +CONFIG_TEXT_BASE=0x0180 +CONFIG_SYS_MALLOC_LEN=0x8 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DEFAULT_DEVICE_TREE="ae350_32" +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SYS_MONITOR_LEN=786432 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x200 +CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x10 +CONFIG_TARGET_ANDES_AE350=y +CONFIG_RISCV_SMODE=y +# CONFIG_AVAILABLE_HARTS is not set +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x1000 +CONFIG_SYS_MONITOR_BASE=0x8800 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x10 +CONFIG_SPL_BSS_START_ADDR=0x40 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x400 +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 +CONFIG_SYS_CFI_FLASH_STATUS_POLL=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y +# CONFIG_BINMAN_FDT is not set +CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y \ No newline at end of file diff --git a/configs/ae350_rv32_falcon_xip_defconfig b/configs/ae350_rv32_falcon_xip_defconfig new file mode 100644 index 00..e01dd6fc51 --- /dev/null +++ b/configs/ae350_rv32_falcon_xip_defconfig @@ -0,0 +1,61 @@ +CONFIG_RISCV=y +CONFIG_TEXT_BASE=0x0180 +CONFIG_SYS_MALLOC_LEN=0x8 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DEFAULT_DEVICE_TREE="ae350_32" +CONFIG_SPL_TEXT_BASE=0x8000 +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SYS_MONITOR_LEN=786432 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x200 +CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x10 +CONFIG_TARGET_ANDES_AE350=y +CONFIG_RISCV_SMODE=y +CONFIG_SPL_XIP=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x8001 +CONFIG_SYS_MONITOR_BASE=0x8800 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x10 +CONFIG_SPL_BSS_START_ADDR=0x40 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x400 +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 +CONFIG_SYS_CFI_FLASH_STATUS_POLL=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y +# CONFIG_BINMAN_FDT is not set +CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y \ No newline at end of file diff --git a/configs/ae350_rv64_falcon_defconfig b/configs/ae350_rv64_falcon_defconfig new file mode 100644 index 00..d11be976de --- /dev/null +++ b/configs/ae350_rv64_falcon_defconfig @@ -0,0 +1,60 @@ +CONFIG_RISCV=y +CONFIG_TEXT_BASE=0x0180 +CONFIG_SYS_MALLOC_LEN=0x8 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DEFAULT_D
[PATCH RESEND 5/7] spl: riscv: add os type for next booting stage
If SPL_LOAD_FIT_OPENSBI_OS_BOOT is enabled, the function
spl_invoke_opensbi should change the target OS type to IH_OS_LINUX.
OpenSBI will load the Linux image as the next boot stage.
The os_takes_devicetree function returns a value of true or false
depending on whether or not SPL_LOAD_FIT_OPENSBI_OS_BOOT is enabled.
Signed-off-by: Randolph
---
common/spl/spl_fit.c | 4
common/spl/spl_opensbi.c | 7 ++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 730639f756..750562721a 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -351,7 +351,11 @@ static bool os_takes_devicetree(uint8_t os)
case IH_OS_U_BOOT:
return true;
case IH_OS_LINUX:
+#ifdef CONFIG_RISCV
+ return IS_ENABLED(CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT);
+#else
return IS_ENABLED(CONFIG_SPL_OS_BOOT);
+#endif
default:
return false;
}
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index a0c5f35dab..708869ad48 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -58,9 +58,14 @@ void __noreturn spl_invoke_opensbi(struct spl_image_info
*spl_image)
/*
* Find next os image in /fit-images
-* The next os image default is u-boot proper
+* The next os image default is u-boot proper, once enable
+* OpenSBI OS boot mode, the OS image should be linux.
*/
+#if CONFIG_IS_ENABLED(LOAD_FIT_OPENSBI_OS_BOOT)
+ os_type = IH_OS_LINUX;
+#else
os_type = IH_OS_U_BOOT;
+#endif
ret = spl_opensbi_find_os_node(spl_image->fdt_addr, _node, os_type);
if (ret) {
pr_err("Can't find %s node for opensbi, %d\n",
--
2.34.1
[PATCH RESEND 4/7] riscv: dts: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbol
Introduce common Kconfig symbol for riscv architecture. This symbol SPL_LOAD_FIT_OPENSBI_OS_BOOT is like falcon mode on ARM, the Falcon boot is a shortcut boot method for SD/eMMC targets. It skips the loading the RAM version U-Boot. Instead, it will loads the FIT image and boots directly to Linux. When SPL_OPENSBI_OS_BOOT is enabled, linux.itb is created after compilation instead of the default u-boot.itb. It initialises memory with the U-Boot SPL at the first stage, just as a normal boot process does at the beginning. Instead of jumping to the U-Boot proper from OpenSBI before booting the Linux kernel, the RISC-V falcon mode process jumps directly to the Linux kernel to gain shorter booting time. When SPL_OPENSBI_OS_BOOT is enabled, it will change the default FIT configure file "binman.dtsi" to "binman_linux.dtsi" Default is not enabled. Signed-off-by: Randolph --- arch/riscv/Kconfig | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ec1cfcaaa7..4f104789a7 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -422,8 +422,17 @@ config TPL_USE_ARCH_MEMSET endmenu +config SPL_LOAD_FIT_OPENSBI_OS_BOOT + bool "Enable SPL (OpenSBI OS boot mode) applying linux from FIT" + depends on SPL_LOAD_FIT + help + Use fw_dynamic from the FIT image, and u-boot SPL will invoke it directly. + This is a shortcut boot flow, from u-boot SPL -> OpenSBI -> u-boot proper + -> linux to u-boot SPL -> OpenSBI -> linux. + config SPL_LOAD_FIT_CONFIG string "Default FIT configuration for SPL" + default "binman_linux.dtsi" if SPL_LOAD_FIT_OPENSBI_OS_BOOT default "binman.dtsi" depends on SPL_LOAD_FIT help -- 2.34.1
[PATCH RESEND 3/7] spl: riscv: opensbi: change the default os_type as varible
In order to introduce the Opensbi OS boot mode, the next stage boot
image of OpenSBI should be configurable.
Signed-off-by: Randolph
---
common/spl/spl_opensbi.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index e2aaa46046..a0c5f35dab 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
struct fw_dynamic_info opensbi_info;
-static int spl_opensbi_find_uboot_node(void *blob, int *uboot_node)
+static int spl_opensbi_find_os_node(void *blob, int *uboot_node, int os_type)
{
int fit_images_node, node;
const char *fit_os;
@@ -34,7 +34,7 @@ static int spl_opensbi_find_uboot_node(void *blob, int
*uboot_node)
if (!fit_os)
continue;
- if (genimg_get_os_id(fit_os) == IH_OS_U_BOOT) {
+ if (genimg_get_os_id(fit_os) == os_type) {
*uboot_node = node;
return 0;
}
@@ -45,8 +45,9 @@ static int spl_opensbi_find_uboot_node(void *blob, int
*uboot_node)
void __noreturn spl_invoke_opensbi(struct spl_image_info *spl_image)
{
- int ret, uboot_node;
- ulong uboot_entry;
+ int ret, os_node;
+ ulong os_entry;
+ int os_type;
typedef void __noreturn (*opensbi_entry_t)(ulong hartid, ulong dtb,
ulong info);
opensbi_entry_t opensbi_entry;
@@ -55,22 +56,27 @@ void __noreturn spl_invoke_opensbi(struct spl_image_info
*spl_image)
hang();
}
- /* Find U-Boot image in /fit-images */
- ret = spl_opensbi_find_uboot_node(spl_image->fdt_addr, _node);
+ /*
+* Find next os image in /fit-images
+* The next os image default is u-boot proper
+*/
+ os_type = IH_OS_U_BOOT;
+ ret = spl_opensbi_find_os_node(spl_image->fdt_addr, _node, os_type);
if (ret) {
- pr_err("Can't find U-Boot node, %d\n", ret);
+ pr_err("Can't find %s node for opensbi, %d\n",
+ genimg_get_os_name(os_type), ret);
hang();
}
/* Get U-Boot entry point */
- ret = fit_image_get_entry(spl_image->fdt_addr, uboot_node,
_entry);
+ ret = fit_image_get_entry(spl_image->fdt_addr, os_node, _entry);
if (ret)
- ret = fit_image_get_load(spl_image->fdt_addr, uboot_node,
_entry);
+ ret = fit_image_get_load(spl_image->fdt_addr, os_node,
_entry);
/* Prepare opensbi_info object */
opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE;
opensbi_info.version = FW_DYNAMIC_INFO_VERSION;
- opensbi_info.next_addr = uboot_entry;
+ opensbi_info.next_addr = os_entry;
opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
opensbi_info.options = CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS;
opensbi_info.boot_hart = gd->arch.boot_hart;
--
2.34.1
[PATCH RESEND 2/7] riscv: dts: add binman_linux.dtsi for opensbi os boot mode
The binman_linux.dtsi is a fork of binman.dtsi, just change the first
section image from the "u-boot" to "linux". Note that the filename
is also changed. In binman.dtsi, the filename of u-boot section filename
is called "u-boot-nodtb.bin". In binman_linux.dtsi, the filename should
be called "Image", which is located in linux/arch/riscv/boot.
Signed-off-by: Randolph
---
arch/riscv/dts/binman_linux.dtsi | 79
1 file changed, 79 insertions(+)
create mode 100644 arch/riscv/dts/binman_linux.dtsi
diff --git a/arch/riscv/dts/binman_linux.dtsi b/arch/riscv/dts/binman_linux.dtsi
new file mode 100644
index 00..334d64bc40
--- /dev/null
+++ b/arch/riscv/dts/binman_linux.dtsi
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021, Bin Meng
+ */
+
+#include
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+ {
+ itb {
+ filename = "linux.itb";
+
+ fit {
+ description = "Configuration to load OpenSBI before
Linux";
+ #address-cells = <1>;
+ fit,fdt-list = "of-list";
+
+ images {
+ linux {
+ description = "Linux";
+ type = "standalone";
+ os = "Linux";
+ arch = "riscv";
+ compression = "none";
+ load = ;
+
+ linux_blob: blob-ext {
+ filename = "Image";
+ };
+ };
+
+ opensbi {
+ description = "OpenSBI fw_dynamic
Firmware";
+ type = "firmware";
+ os = "opensbi";
+ arch = "riscv";
+ compression = "none";
+ load = ;
+ entry = ;
+
+ opensbi_blob: opensbi {
+ filename = "fw_dynamic.bin";
+ missing-msg = "opensbi";
+ };
+ };
+
+#ifndef CONFIG_OF_BOARD
+ @fdt-SEQ {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+ };
+#endif
+ };
+
+ configurations {
+ default = "conf-1";
+
+#ifndef CONFIG_OF_BOARD
+ @conf-SEQ {
+#else
+ conf-1 {
+#endif
+ description = "NAME";
+ firmware = "opensbi";
+ loadables = "linux";
+#ifndef CONFIG_OF_BOARD
+ fdt = "fdt-SEQ";
+#endif
+ };
+ };
+ };
+ };
+};
--
2.34.1
[PATCH RESEND 1/7] riscv: dts: Introduce SPL_LOAD_FIT_CONFIG symbol
Introduce common Kconfig symbol for riscv architecture
This symbol SPL_LOAD_FIT_CONFIG for binman itb layout selection
Default is using binman.dtsi
Signed-off-by: Randolph
---
arch/riscv/Kconfig | 7 +++
arch/riscv/dts/ae350-u-boot.dtsi | 1 +
arch/riscv/dts/ae350_32.dts | 1 -
arch/riscv/dts/ae350_64.dts | 1 -
4 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index aff1f33665..ec1cfcaaa7 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -422,4 +422,11 @@ config TPL_USE_ARCH_MEMSET
endmenu
+config SPL_LOAD_FIT_CONFIG
+ string "Default FIT configuration for SPL"
+ default "binman.dtsi"
+ depends on SPL_LOAD_FIT
+ help
+ Specify corresponding FIT configuration for SPL modes.
+
endmenu
diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-boot.dtsi
index aef9159b7a..ff5725501f 100644
--- a/arch/riscv/dts/ae350-u-boot.dtsi
+++ b/arch/riscv/dts/ae350-u-boot.dtsi
@@ -1,4 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+#include CONFIG_SPL_LOAD_FIT_CONFIG
/ {
cpus {
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 61af6d5465..2caabad888 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -2,7 +2,6 @@
/dts-v1/;
-#include "binman.dtsi"
#include "ae350-u-boot.dtsi"
/ {
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 8c7db29b4f..9d5f6c743c 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -2,7 +2,6 @@
/dts-v1/;
-#include "binman.dtsi"
#include "ae350-u-boot.dtsi"
/ {
--
2.34.1
[PATCH RESEND 0/7] riscv: spl: OpenSBI OS boot mode
Introduce a shortcut boot mode for RISC-V. As we know, in ARM architecture has the Falcon mode to do the shortcut boot to the Linux kernel. (by enabling CONFIG_SPL_OS_BOOT) ARM Falcon mode boot flow would be as follows: u-boot SPL -> Linux kernel But for RISC-V, OpenSBI is required to allows the supervisor to execute some privileged operations. The RISC-V Normal boot flow as follows: u-boot SPL -> OpenSBI -> u-boot proper -> Linux kernel Quoting the same ideas as ARM's Falcon mode, OpenSBI OS boot flow as follows: u-boot SPL -> OpenSBI -> Linux kernel An important part of OpenSBI OS boot mode is to prepare the device tree. A normal U-Boot does FDT fixups when booting Linux. For OpenSBI OS boot mode, Linux boots directly from SPL, skipping the normal U-Boot. The device tree has to be prepared in advance. The device tree in memory is the one needed for OpenSBI OS boot mode. The Linux kernel image will also need to be provided for the generation of the FIT file. Randolph (7): riscv: dts: Introduce SPL_LOAD_FIT_CONFIG symbol riscv: dts: add binman_linux.dtsi for opensbi os boot mode spl: riscv: opensbi: change the default os_type as varible riscv: dts: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbol spl: riscv: add os type for next booting stage andes: config: add riscv falcon mode for ae350 platform riscv: spl: andes: Move the DTB in front of kernel arch/riscv/Kconfig | 16 + arch/riscv/dts/ae350-u-boot.dtsi| 1 + arch/riscv/dts/ae350_32.dts | 1 - arch/riscv/dts/ae350_64.dts | 1 - arch/riscv/dts/binman_linux.dtsi| 79 + board/AndesTech/ae350/ae350.c | 25 common/spl/spl_fit.c| 4 ++ common/spl/spl_opensbi.c| 31 ++ configs/ae350_rv32_falcon_defconfig | 60 +++ configs/ae350_rv32_falcon_xip_defconfig | 61 +++ configs/ae350_rv64_falcon_defconfig | 60 +++ configs/ae350_rv64_falcon_xip_defconfig | 61 +++ 12 files changed, 388 insertions(+), 12 deletions(-) create mode 100644 arch/riscv/dts/binman_linux.dtsi create mode 100644 configs/ae350_rv32_falcon_defconfig create mode 100644 configs/ae350_rv32_falcon_xip_defconfig create mode 100644 configs/ae350_rv64_falcon_defconfig create mode 100644 configs/ae350_rv64_falcon_xip_defconfig -- 2.34.1
[PATCH 7/7] riscv: spl: andes: Move the DTB in front of kernel
Originally, u-boot SPL will place the DTB directly after the kernel,
but the size of the kernel does not include the BSS section, This
means that u-boot SPL places the DTB in the kernel BSS section causing
the DTB to be cleared by the kernel BSS initialisation.
Moving the DTB in front of the kernel can avoid this error.
Signed-off-by: Randolph
---
board/AndesTech/ae350/ae350.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
index 1c2288b6ce..d78ee403e6 100644
--- a/board/AndesTech/ae350/ae350.c
+++ b/board/AndesTech/ae350/ae350.c
@@ -19,6 +19,8 @@
#include
#include
#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -26,6 +28,29 @@ DECLARE_GLOBAL_DATA_PTR;
* Miscellaneous platform dependent initializations
*/
+#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
+#define ANDES_SPL_FDT_ADDR (CONFIG_TEXT_BASE - 0x10)
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+ /*
+* Originally, u-boot-spl will place DTB directly after the kernel,
+* but the size of the kernel did not include the BSS section, which
+* means u-boot-spl will place the DTB in the kernel BSS section
+* causing the DTB to be cleared by kernel BSS initializtion.
+* Moving DTB in front of the kernel can avoid the error.
+*/
+ if (ANDES_SPL_FDT_ADDR < 0) {
+ printf("%s: CONFIG_TEXT_BASE needs to be larger than
0x10\n",
+ __func__);
+ hang();
+ }
+
+ memcpy((void *)ANDES_SPL_FDT_ADDR, spl_image->fdt_addr,
+ fdt_totalsize(spl_image->fdt_addr));
+ spl_image->fdt_addr = map_sysmem(ANDES_SPL_FDT_ADDR, 0);
+}
+#endif
+
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
--
2.34.1
[PATCH 6/7] andes: config: add riscv falcon mode for ae350 platform
Fork from ae350_rv[32/64]_spl_[xip]_defconfig and append CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y Signed-off-by: Randolph --- configs/ae350_rv32_falcon_defconfig | 60 configs/ae350_rv32_falcon_xip_defconfig | 61 + configs/ae350_rv64_falcon_defconfig | 60 configs/ae350_rv64_falcon_xip_defconfig | 61 + 4 files changed, 242 insertions(+) create mode 100644 configs/ae350_rv32_falcon_defconfig create mode 100644 configs/ae350_rv32_falcon_xip_defconfig create mode 100644 configs/ae350_rv64_falcon_defconfig create mode 100644 configs/ae350_rv64_falcon_xip_defconfig diff --git a/configs/ae350_rv32_falcon_defconfig b/configs/ae350_rv32_falcon_defconfig new file mode 100644 index 00..8f796d88e3 --- /dev/null +++ b/configs/ae350_rv32_falcon_defconfig @@ -0,0 +1,60 @@ +CONFIG_RISCV=y +CONFIG_TEXT_BASE=0x0180 +CONFIG_SYS_MALLOC_LEN=0x8 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DEFAULT_DEVICE_TREE="ae350_32" +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SYS_MONITOR_LEN=786432 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x200 +CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x10 +CONFIG_TARGET_ANDES_AE350=y +CONFIG_RISCV_SMODE=y +# CONFIG_AVAILABLE_HARTS is not set +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x1000 +CONFIG_SYS_MONITOR_BASE=0x8800 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x10 +CONFIG_SPL_BSS_START_ADDR=0x40 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x400 +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 +CONFIG_SYS_CFI_FLASH_STATUS_POLL=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y +# CONFIG_BINMAN_FDT is not set +CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y \ No newline at end of file diff --git a/configs/ae350_rv32_falcon_xip_defconfig b/configs/ae350_rv32_falcon_xip_defconfig new file mode 100644 index 00..e01dd6fc51 --- /dev/null +++ b/configs/ae350_rv32_falcon_xip_defconfig @@ -0,0 +1,61 @@ +CONFIG_RISCV=y +CONFIG_TEXT_BASE=0x0180 +CONFIG_SYS_MALLOC_LEN=0x8 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DEFAULT_DEVICE_TREE="ae350_32" +CONFIG_SPL_TEXT_BASE=0x8000 +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SYS_MONITOR_LEN=786432 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x200 +CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x10 +CONFIG_TARGET_ANDES_AE350=y +CONFIG_RISCV_SMODE=y +CONFIG_SPL_XIP=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x8001 +CONFIG_SYS_MONITOR_BASE=0x8800 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x10 +CONFIG_SPL_BSS_START_ADDR=0x40 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x400 +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 +CONFIG_SYS_CFI_FLASH_STATUS_POLL=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y +# CONFIG_BINMAN_FDT is not set +CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y \ No newline at end of file diff --git a/configs/ae350_rv64_falcon_defconfig b/configs/ae350_rv64_falcon_defconfig new file mode 100644 index 00..d11be976de --- /dev/null +++ b/configs/ae350_rv64_falcon_defconfig @@ -0,0 +1,60 @@ +CONFIG_RISCV=y +CONFIG_TEXT_BASE=0x0180 +CONFIG_SYS_MALLOC_LEN=0x8 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DEFAULT_D
[PATCH 5/7] spl: riscv: add os type for next booting stage
If SPL_LOAD_FIT_OPENSBI_OS_BOOT is enabled, the function
spl_invoke_opensbi should change the target OS type to IH_OS_LINUX.
OpenSBI will load the Linux image as the next boot stage.
The os_takes_devicetree function returns a value of true or false
depending on whether or not SPL_LOAD_FIT_OPENSBI_OS_BOOT is enabled.
Signed-off-by: Randolph
---
common/spl/spl_fit.c | 4
common/spl/spl_opensbi.c | 7 ++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 730639f756..750562721a 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -351,7 +351,11 @@ static bool os_takes_devicetree(uint8_t os)
case IH_OS_U_BOOT:
return true;
case IH_OS_LINUX:
+#ifdef CONFIG_RISCV
+ return IS_ENABLED(CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT);
+#else
return IS_ENABLED(CONFIG_SPL_OS_BOOT);
+#endif
default:
return false;
}
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index a0c5f35dab..708869ad48 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -58,9 +58,14 @@ void __noreturn spl_invoke_opensbi(struct spl_image_info
*spl_image)
/*
* Find next os image in /fit-images
-* The next os image default is u-boot proper
+* The next os image default is u-boot proper, once enable
+* OpenSBI OS boot mode, the OS image should be linux.
*/
+#if CONFIG_IS_ENABLED(LOAD_FIT_OPENSBI_OS_BOOT)
+ os_type = IH_OS_LINUX;
+#else
os_type = IH_OS_U_BOOT;
+#endif
ret = spl_opensbi_find_os_node(spl_image->fdt_addr, _node, os_type);
if (ret) {
pr_err("Can't find %s node for opensbi, %d\n",
--
2.34.1
[PATCH 4/7] riscv: dts: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbol
Introduce common Kconfig symbol for riscv architecture. This symbol SPL_LOAD_FIT_OPENSBI_OS_BOOT is like falcon mode on ARM, the Falcon boot is a shortcut boot method for SD/eMMC targets. It skips the loading the RAM version U-Boot. Instead, it will loads the FIT image and boots directly to Linux. When SPL_OPENSBI_OS_BOOT is enabled, linux.itb is created after compilation instead of the default u-boot.itb. It initialises memory with the U-Boot SPL at the first stage, just as a normal boot process does at the beginning. Instead of jumping to the U-Boot proper from OpenSBI before booting the Linux kernel, the RISC-V falcon mode process jumps directly to the Linux kernel to gain shorter booting time. When SPL_OPENSBI_OS_BOOT is enabled, it will change the default FIT configure file "binman.dtsi" to "binman_linux.dtsi" Default is not enabled. Signed-off-by: Randolph --- arch/riscv/Kconfig | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ec1cfcaaa7..4f104789a7 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -422,8 +422,17 @@ config TPL_USE_ARCH_MEMSET endmenu +config SPL_LOAD_FIT_OPENSBI_OS_BOOT + bool "Enable SPL (OpenSBI OS boot mode) applying linux from FIT" + depends on SPL_LOAD_FIT + help + Use fw_dynamic from the FIT image, and u-boot SPL will invoke it directly. + This is a shortcut boot flow, from u-boot SPL -> OpenSBI -> u-boot proper + -> linux to u-boot SPL -> OpenSBI -> linux. + config SPL_LOAD_FIT_CONFIG string "Default FIT configuration for SPL" + default "binman_linux.dtsi" if SPL_LOAD_FIT_OPENSBI_OS_BOOT default "binman.dtsi" depends on SPL_LOAD_FIT help -- 2.34.1
[PATCH 3/7] spl: riscv: opensbi: change the default os_type as varible
In order to introduce the Opensbi OS boot mode, the next stage boot
image of OpenSBI should be configurable.
Signed-off-by: Randolph
---
common/spl/spl_opensbi.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index e2aaa46046..a0c5f35dab 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
struct fw_dynamic_info opensbi_info;
-static int spl_opensbi_find_uboot_node(void *blob, int *uboot_node)
+static int spl_opensbi_find_os_node(void *blob, int *uboot_node, int os_type)
{
int fit_images_node, node;
const char *fit_os;
@@ -34,7 +34,7 @@ static int spl_opensbi_find_uboot_node(void *blob, int
*uboot_node)
if (!fit_os)
continue;
- if (genimg_get_os_id(fit_os) == IH_OS_U_BOOT) {
+ if (genimg_get_os_id(fit_os) == os_type) {
*uboot_node = node;
return 0;
}
@@ -45,8 +45,9 @@ static int spl_opensbi_find_uboot_node(void *blob, int
*uboot_node)
void __noreturn spl_invoke_opensbi(struct spl_image_info *spl_image)
{
- int ret, uboot_node;
- ulong uboot_entry;
+ int ret, os_node;
+ ulong os_entry;
+ int os_type;
typedef void __noreturn (*opensbi_entry_t)(ulong hartid, ulong dtb,
ulong info);
opensbi_entry_t opensbi_entry;
@@ -55,22 +56,27 @@ void __noreturn spl_invoke_opensbi(struct spl_image_info
*spl_image)
hang();
}
- /* Find U-Boot image in /fit-images */
- ret = spl_opensbi_find_uboot_node(spl_image->fdt_addr, _node);
+ /*
+* Find next os image in /fit-images
+* The next os image default is u-boot proper
+*/
+ os_type = IH_OS_U_BOOT;
+ ret = spl_opensbi_find_os_node(spl_image->fdt_addr, _node, os_type);
if (ret) {
- pr_err("Can't find U-Boot node, %d\n", ret);
+ pr_err("Can't find %s node for opensbi, %d\n",
+ genimg_get_os_name(os_type), ret);
hang();
}
/* Get U-Boot entry point */
- ret = fit_image_get_entry(spl_image->fdt_addr, uboot_node,
_entry);
+ ret = fit_image_get_entry(spl_image->fdt_addr, os_node, _entry);
if (ret)
- ret = fit_image_get_load(spl_image->fdt_addr, uboot_node,
_entry);
+ ret = fit_image_get_load(spl_image->fdt_addr, os_node,
_entry);
/* Prepare opensbi_info object */
opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE;
opensbi_info.version = FW_DYNAMIC_INFO_VERSION;
- opensbi_info.next_addr = uboot_entry;
+ opensbi_info.next_addr = os_entry;
opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
opensbi_info.options = CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS;
opensbi_info.boot_hart = gd->arch.boot_hart;
--
2.34.1
[PATCH 2/7] riscv: dts: add binman_linux.dtsi for opensbi os boot mode
The binman_linux.dtsi is a fork of binman.dtsi, just change the first
section image from the "u-boot" to "linux". Note that the filename
is also changed. In binman.dtsi, the filename of u-boot section filename
is called "u-boot-nodtb.bin". In binman_linux.dtsi, the filename should
be called "Image", which is located in linux/arch/riscv/boot.
Signed-off-by: Randolph
---
arch/riscv/dts/binman_linux.dtsi | 79
1 file changed, 79 insertions(+)
create mode 100644 arch/riscv/dts/binman_linux.dtsi
diff --git a/arch/riscv/dts/binman_linux.dtsi b/arch/riscv/dts/binman_linux.dtsi
new file mode 100644
index 00..334d64bc40
--- /dev/null
+++ b/arch/riscv/dts/binman_linux.dtsi
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021, Bin Meng
+ */
+
+#include
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+ {
+ itb {
+ filename = "linux.itb";
+
+ fit {
+ description = "Configuration to load OpenSBI before
Linux";
+ #address-cells = <1>;
+ fit,fdt-list = "of-list";
+
+ images {
+ linux {
+ description = "Linux";
+ type = "standalone";
+ os = "Linux";
+ arch = "riscv";
+ compression = "none";
+ load = ;
+
+ linux_blob: blob-ext {
+ filename = "Image";
+ };
+ };
+
+ opensbi {
+ description = "OpenSBI fw_dynamic
Firmware";
+ type = "firmware";
+ os = "opensbi";
+ arch = "riscv";
+ compression = "none";
+ load = ;
+ entry = ;
+
+ opensbi_blob: opensbi {
+ filename = "fw_dynamic.bin";
+ missing-msg = "opensbi";
+ };
+ };
+
+#ifndef CONFIG_OF_BOARD
+ @fdt-SEQ {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+ };
+#endif
+ };
+
+ configurations {
+ default = "conf-1";
+
+#ifndef CONFIG_OF_BOARD
+ @conf-SEQ {
+#else
+ conf-1 {
+#endif
+ description = "NAME";
+ firmware = "opensbi";
+ loadables = "linux";
+#ifndef CONFIG_OF_BOARD
+ fdt = "fdt-SEQ";
+#endif
+ };
+ };
+ };
+ };
+};
--
2.34.1
[PATCH 1/7] riscv: dts: Introduce SPL_LOAD_FIT_CONFIG symbol
Introduce common Kconfig symbol for riscv architecture
This symbol SPL_LOAD_FIT_CONFIG for binman itb layout selection
Default is using binman.dtsi
Signed-off-by: Randolph
---
arch/riscv/Kconfig | 7 +++
arch/riscv/dts/ae350-u-boot.dtsi | 1 +
arch/riscv/dts/ae350_32.dts | 1 -
arch/riscv/dts/ae350_64.dts | 1 -
4 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index aff1f33665..ec1cfcaaa7 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -422,4 +422,11 @@ config TPL_USE_ARCH_MEMSET
endmenu
+config SPL_LOAD_FIT_CONFIG
+ string "Default FIT configuration for SPL"
+ default "binman.dtsi"
+ depends on SPL_LOAD_FIT
+ help
+ Specify corresponding FIT configuration for SPL modes.
+
endmenu
diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-boot.dtsi
index aef9159b7a..ff5725501f 100644
--- a/arch/riscv/dts/ae350-u-boot.dtsi
+++ b/arch/riscv/dts/ae350-u-boot.dtsi
@@ -1,4 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+#include CONFIG_SPL_LOAD_FIT_CONFIG
/ {
cpus {
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 61af6d5465..2caabad888 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -2,7 +2,6 @@
/dts-v1/;
-#include "binman.dtsi"
#include "ae350-u-boot.dtsi"
/ {
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 8c7db29b4f..9d5f6c743c 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -2,7 +2,6 @@
/dts-v1/;
-#include "binman.dtsi"
#include "ae350-u-boot.dtsi"
/ {
--
2.34.1
[PATCH 0/7] riscv: spl: OpenSBI OS boot mode
Introduce a shortcut boot mode for RISC-V. As we know, in ARM architecture has the Falcon mode to do the shortcut boot to the Linux kernel. (by enabling CONFIG_SPL_OS_BOOT) ARM Falcon mode boot flow would be as follows: u-boot SPL -> Linux kernel But for RISC-V, OpenSBI is required to allows the supervisor to execute some privileged operations. The RISC-V Normal boot flow as follows: u-boot SPL -> OpenSBI -> u-boot proper -> Linux kernel Quoting the same ideas as ARM's Falcon mode, OpenSBI OS boot flow as follows: u-boot SPL -> OpenSBI -> Linux kernel An important part of OpenSBI OS boot mode is to prepare the device tree. A normal U-Boot does FDT fixups when booting Linux. For OpenSBI OS boot mode, Linux boots directly from SPL, skipping the normal U-Boot. The device tree has to be prepared in advance. The device tree in memory is the one needed for OpenSBI OS boot mode. The Linux kernel image will also need to be provided for the generation of the FIT file. Randolph (7): riscv: dts: Introduce SPL_LOAD_FIT_CONFIG symbol riscv: dts: add binman_linux.dtsi for opensbi os boot mode spl: riscv: opensbi: change the default os_type as varible riscv: dts: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbol spl: riscv: add os type for next booting stage andes: config: add riscv falcon mode for ae350 platform riscv: spl: andes: Move the DTB in front of kernel arch/riscv/Kconfig | 16 + arch/riscv/dts/ae350-u-boot.dtsi| 1 + arch/riscv/dts/ae350_32.dts | 1 - arch/riscv/dts/ae350_64.dts | 1 - arch/riscv/dts/binman_linux.dtsi| 79 + board/AndesTech/ae350/ae350.c | 25 common/spl/spl_fit.c| 4 ++ common/spl/spl_opensbi.c| 31 ++ configs/ae350_rv32_falcon_defconfig | 60 +++ configs/ae350_rv32_falcon_xip_defconfig | 61 +++ configs/ae350_rv64_falcon_defconfig | 60 +++ configs/ae350_rv64_falcon_xip_defconfig | 61 +++ 12 files changed, 388 insertions(+), 12 deletions(-) create mode 100644 arch/riscv/dts/binman_linux.dtsi create mode 100644 configs/ae350_rv32_falcon_defconfig create mode 100644 configs/ae350_rv32_falcon_xip_defconfig create mode 100644 configs/ae350_rv64_falcon_defconfig create mode 100644 configs/ae350_rv64_falcon_xip_defconfig -- 2.34.1
[PATCH V3 2/2] configs: andes: rearrange SPL mode memory layout
Unify the memory layout for u-boot SPL mode Add "CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS" Signed-off-by: Randolph --- configs/ae350_rv32_spl_defconfig | 7 --- configs/ae350_rv32_spl_xip_defconfig | 5 +++-- configs/ae350_rv64_spl_defconfig | 7 --- configs/ae350_rv64_spl_xip_defconfig | 5 +++-- 4 files changed, 14 insertions(+), 10 deletions(-) diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 4adc1134ba..b28a0a84fb 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -8,14 +8,14 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_MONITOR_LEN=786432 -CONFIG_SPL_SYS_MALLOC_F_LEN=0x10 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x200 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x10 CONFIG_TARGET_ANDES_AE350=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x0020 +CONFIG_SPL_LOAD_FIT_ADDRESS=0x1000 CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 @@ -23,9 +23,10 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x10 -CONFIG_SPL_BSS_START_ADDR=0x400 +CONFIG_SPL_BSS_START_ADDR=0x40 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index e19eb546a6..5e8f1b3631 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -9,7 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SPL_TEXT_BASE=0x8000 CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_MONITOR_LEN=786432 -CONFIG_SPL_SYS_MALLOC_F_LEN=0x10 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x200 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x10 CONFIG_TARGET_ANDES_AE350=y @@ -24,9 +24,10 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x10 -CONFIG_SPL_BSS_START_ADDR=0x400 +CONFIG_SPL_BSS_START_ADDR=0x40 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 629c5bab77..1592ec811a 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -7,7 +7,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SPL_SYS_MALLOC_F_LEN=0x10 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x200 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x10 CONFIG_TARGET_ANDES_AE350=y @@ -15,7 +15,7 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x0020 +CONFIG_SPL_LOAD_FIT_ADDRESS=0x1000 CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 @@ -23,9 +23,10 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x10 -CONFIG_SPL_BSS_START_ADDR=0x400 +CONFIG_SPL_BSS_START_ADDR=0x40 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 4557e05445..97f961b6c9 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -8,7 +8,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_TEXT_BASE=0x8000 CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SPL_SYS_MALLOC_F_LEN=0x10 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x200 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x10 CONFIG_TARGET_ANDES_AE350=y @@ -24,9 +24,10 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x10 -CONFIG_SPL_BSS_START_ADDR=0x400 +CONFIG_SPL_BSS_START_ADDR=0x40 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y -- 2.34.1
[PATCH V3 1/2] configs: andes: add vender prefix for target name
Modify "CONFIG_TARGET_AE350" to "CONFIG_TARGET_ANDES_AE350" Signed-off-by: Randolph Reviewed-by: Tom Rini --- arch/riscv/Kconfig | 4 ++-- arch/riscv/dts/Makefile | 2 +- board/AndesTech/ae350/Kconfig| 2 +- configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv32_spl_defconfig | 2 +- configs/ae350_rv32_spl_xip_defconfig | 2 +- configs/ae350_rv32_xip_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- configs/ae350_rv64_spl_defconfig | 2 +- configs/ae350_rv64_spl_xip_defconfig | 2 +- configs/ae350_rv64_xip_defconfig | 2 +- 11 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6771d8d919..aff1f33665 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -8,8 +8,8 @@ choice prompt "Target select" optional -config TARGET_AE350 - bool "Support ae350" +config TARGET_ANDES_AE350 + bool "Support Andes ae350" config TARGET_MICROCHIP_ICICLE bool "Support Microchip PolarFire-SoC Icicle Board" diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index f1525cb668..be6c8a4227 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb diff --git a/board/AndesTech/ae350/Kconfig b/board/AndesTech/ae350/Kconfig index 75815bf99a..a85e7d6351 100644 --- a/board/AndesTech/ae350/Kconfig +++ b/board/AndesTech/ae350/Kconfig @@ -1,4 +1,4 @@ -if TARGET_AE350 +if TARGET_ANDES_AE350 config SYS_CPU default "andesv5" diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 06a683d986..2fbb87a9b3 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -9,7 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SYS_LOAD_ADDR=0x10 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 75e55ba724..4adc1134ba 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -11,7 +11,7 @@ CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x10 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x10 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_FIT=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index c2221b891e..e19eb546a6 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -12,7 +12,7 @@ CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x10 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x10 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y CONFIG_FIT=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index 6d19400c2d..f1c1e5bc00 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -9,7 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SYS_LOAD_ADDR=0x10 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_XIP=y CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x8800 diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 0d7f0a552e..3f30842a8e 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -8,7 +8,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_LOAD_ADDR=0x10 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x8800 diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 6a72b5a047..629c5bab77 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -10,7 +10,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SPL_SYS_MALLOC_F_LEN=0x10 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x10 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 43581c79b1..4557e05445 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -11,7 +11,
[PATCH V3 0/2] andes: rearrange defconfig and dts
Changes in v3: - Drop the "SPL config option for itb layout" patch Changes in v2: - Split the original patch into three smaller ones Randolph (2): configs: andes: add vender prefix for target name configs: andes: rearrange SPL mode memory layout arch/riscv/Kconfig | 4 ++-- arch/riscv/dts/Makefile | 2 +- board/AndesTech/ae350/Kconfig| 2 +- configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv32_spl_defconfig | 9 + configs/ae350_rv32_spl_xip_defconfig | 7 --- configs/ae350_rv32_xip_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- configs/ae350_rv64_spl_defconfig | 9 + configs/ae350_rv64_spl_xip_defconfig | 7 --- configs/ae350_rv64_xip_defconfig | 2 +- 11 files changed, 26 insertions(+), 22 deletions(-) -- 2.34.1
Re: [PATCH V2 3/3] dts: andes: add SPL config option for itb layout
Hi Tom, Tom Rini 於 2023年9月18日 週一 下午11:04寫道： > > On Mon, Sep 18, 2023 at 08:11:36PM +0800, Randolph wrote: > > > Add SPL_LOAD_FIT_CONFIG for binman itb layout selection > > > > Signed-off-by: Randolph > > --- > > arch/riscv/dts/ae350-u-boot.dtsi | 1 + > > arch/riscv/dts/ae350_32.dts | 1 - > > arch/riscv/dts/ae350_64.dts | 1 - > > board/AndesTech/ae350/Kconfig| 6 ++ > > configs/ae350_rv32_defconfig | 1 + > > configs/ae350_rv32_spl_defconfig | 1 + > > configs/ae350_rv32_spl_xip_defconfig | 1 + > > configs/ae350_rv32_xip_defconfig | 1 + > > configs/ae350_rv64_defconfig | 1 + > > configs/ae350_rv64_spl_defconfig | 1 + > > configs/ae350_rv64_spl_xip_defconfig | 1 + > > configs/ae350_rv64_xip_defconfig | 1 + > > 12 files changed, 15 insertions(+), 2 deletions(-) > > So this is where I have a problem. It's not clear why you need to > change anything here, as there's no example given for doing something > other than what you do today, and there's no documentation about it > either. From other contexts, it seems like you're trying to re-implement > CONFIG_SPL_OS_BOOT but not explaining why you can't use the existing > framework. > > -- > Tom We want to add our binman.dtsi (very similar to SPL_OS_BOOT) in the future, but this may affect other vendors' code under arch/riscv. To take a step back and reduce the gap, we just want to rearrange our code now (in this patch). We are not re-implementing SPL_OS_BOOT, the goal (skip loading u-boot proper) is the same, the method is different. For example, in ARM architecture, the Falcon mode (by enabling SPL_OS_BOOT), the boot flow is u-boot SPL jump to Linux kernel. In RISC-V architecture, most SOCs require OpenSBI, the boot flow should be u-boot SPL -> OpenSBI -> Linux kernel. Apart from the boot flow, the code flow is also different, "jump_to_image_linux" is not necessary and the names are not quite right in the RISC-V architecture. The CONFIG_SPL_ARGS_ADDR macro is also not required when building RISC-V u-boot. That's why we need to create another way for OpenSBI to do the actions like CONFIG_SPL_OS_BOOT. Randolph Sincerely
[PATCH V2 3/3] dts: andes: add SPL config option for itb layout
Add SPL_LOAD_FIT_CONFIG for binman itb layout selection
Signed-off-by: Randolph
---
arch/riscv/dts/ae350-u-boot.dtsi | 1 +
arch/riscv/dts/ae350_32.dts | 1 -
arch/riscv/dts/ae350_64.dts | 1 -
board/AndesTech/ae350/Kconfig| 6 ++
configs/ae350_rv32_defconfig | 1 +
configs/ae350_rv32_spl_defconfig | 1 +
configs/ae350_rv32_spl_xip_defconfig | 1 +
configs/ae350_rv32_xip_defconfig | 1 +
configs/ae350_rv64_defconfig | 1 +
configs/ae350_rv64_spl_defconfig | 1 +
configs/ae350_rv64_spl_xip_defconfig | 1 +
configs/ae350_rv64_xip_defconfig | 1 +
12 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-boot.dtsi
index aef9159b7a..ff5725501f 100644
--- a/arch/riscv/dts/ae350-u-boot.dtsi
+++ b/arch/riscv/dts/ae350-u-boot.dtsi
@@ -1,4 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+#include CONFIG_SPL_LOAD_FIT_CONFIG
/ {
cpus {
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 61af6d5465..2caabad888 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -2,7 +2,6 @@
/dts-v1/;
-#include "binman.dtsi"
#include "ae350-u-boot.dtsi"
/ {
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 8c7db29b4f..9d5f6c743c 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -2,7 +2,6 @@
/dts-v1/;
-#include "binman.dtsi"
#include "ae350-u-boot.dtsi"
/ {
diff --git a/board/AndesTech/ae350/Kconfig b/board/AndesTech/ae350/Kconfig
index a85e7d6351..49a2f8ec23 100644
--- a/board/AndesTech/ae350/Kconfig
+++ b/board/AndesTech/ae350/Kconfig
@@ -41,4 +41,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply SPL_RAM_DEVICE
imply OF_HAS_PRIOR_STAGE
+config SPL_LOAD_FIT_CONFIG
+ string "Default FIT configuration for SPL"
+ depends on SPL_LOAD_FIT
+ help
+ Specify corresponding FIT configuration for SPL modes.
+
endif
diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index 2fbb87a9b3..eea919249d 100644
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -10,6 +10,7 @@ CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SYS_LOAD_ADDR=0x10
CONFIG_TARGET_ANDES_AE350=y
+CONFIG_SPL_LOAD_FIT_CONFIG="binman.dtsi"
CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0x8800
CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
index b28a0a84fb..0d100bdbb1 100644
--- a/configs/ae350_rv32_spl_defconfig
+++ b/configs/ae350_rv32_spl_defconfig
@@ -13,6 +13,7 @@ CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x10
CONFIG_TARGET_ANDES_AE350=y
CONFIG_RISCV_SMODE=y
+CONFIG_SPL_LOAD_FIT_CONFIG="binman.dtsi"
# CONFIG_AVAILABLE_HARTS is not set
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x1000
diff --git a/configs/ae350_rv32_spl_xip_defconfig
b/configs/ae350_rv32_spl_xip_defconfig
index 5e8f1b3631..0284d18e58 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -14,6 +14,7 @@ CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x10
CONFIG_TARGET_ANDES_AE350=y
CONFIG_RISCV_SMODE=y
+CONFIG_SPL_LOAD_FIT_CONFIG="binman.dtsi"
CONFIG_SPL_XIP=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8001
diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig
index f1c1e5bc00..1b01b881ed 100644
--- a/configs/ae350_rv32_xip_defconfig
+++ b/configs/ae350_rv32_xip_defconfig
@@ -10,6 +10,7 @@ CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SYS_LOAD_ADDR=0x10
CONFIG_TARGET_ANDES_AE350=y
+CONFIG_SPL_LOAD_FIT_CONFIG="binman.dtsi"
CONFIG_XIP=y
CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0x8800
diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
index 3f30842a8e..cd13fc58a5 100644
--- a/configs/ae350_rv64_defconfig
+++ b/configs/ae350_rv64_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_LOAD_ADDR=0x10
CONFIG_TARGET_ANDES_AE350=y
+CONFIG_SPL_LOAD_FIT_CONFIG="binman.dtsi"
CONFIG_ARCH_RV64I=y
CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0x8800
diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig
index 1592ec811a..2d32aea041 100644
--- a/configs/ae350_rv64_spl_defconfig
+++ b/configs/ae350_rv64_spl_defconfig
@@ -13,6 +13,7 @@ CONFIG_SYS_LOAD_ADDR=0x10
CONFIG_TARGET_ANDES_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
+CONFIG_SPL_LOAD_FIT_CONFIG="binman.dtsi"
# CONFIG_AVAILABLE_HARTS is not set
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x1000
diff --git a/configs/ae350_rv64_spl_xip_defconfig
b/configs/ae350_rv64_spl_xip_defconfig
index 97f961b6c9..f2fea9d28e 100644
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/config
[PATCH V2 2/3] configs: andes: rearrange SPL mode memory layout
Unify the memory layout for u-boot SPL mode Add "CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS" Signed-off-by: Randolph --- configs/ae350_rv32_spl_defconfig | 7 --- configs/ae350_rv32_spl_xip_defconfig | 5 +++-- configs/ae350_rv64_spl_defconfig | 7 --- configs/ae350_rv64_spl_xip_defconfig | 5 +++-- 4 files changed, 14 insertions(+), 10 deletions(-) diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 4adc1134ba..b28a0a84fb 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -8,14 +8,14 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_MONITOR_LEN=786432 -CONFIG_SPL_SYS_MALLOC_F_LEN=0x10 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x200 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x10 CONFIG_TARGET_ANDES_AE350=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x0020 +CONFIG_SPL_LOAD_FIT_ADDRESS=0x1000 CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 @@ -23,9 +23,10 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x10 -CONFIG_SPL_BSS_START_ADDR=0x400 +CONFIG_SPL_BSS_START_ADDR=0x40 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index e19eb546a6..5e8f1b3631 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -9,7 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SPL_TEXT_BASE=0x8000 CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_MONITOR_LEN=786432 -CONFIG_SPL_SYS_MALLOC_F_LEN=0x10 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x200 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x10 CONFIG_TARGET_ANDES_AE350=y @@ -24,9 +24,10 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x10 -CONFIG_SPL_BSS_START_ADDR=0x400 +CONFIG_SPL_BSS_START_ADDR=0x40 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 629c5bab77..1592ec811a 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -7,7 +7,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SPL_SYS_MALLOC_F_LEN=0x10 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x200 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x10 CONFIG_TARGET_ANDES_AE350=y @@ -15,7 +15,7 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x0020 +CONFIG_SPL_LOAD_FIT_ADDRESS=0x1000 CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 @@ -23,9 +23,10 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x10 -CONFIG_SPL_BSS_START_ADDR=0x400 +CONFIG_SPL_BSS_START_ADDR=0x40 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 4557e05445..97f961b6c9 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -8,7 +8,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_TEXT_BASE=0x8000 CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SPL_SYS_MALLOC_F_LEN=0x10 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x200 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x10 CONFIG_TARGET_ANDES_AE350=y @@ -24,9 +24,10 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x10 -CONFIG_SPL_BSS_START_ADDR=0x400 +CONFIG_SPL_BSS_START_ADDR=0x40 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y -- 2.34.1
[PATCH V2 1/3] configs: andes: add vender prefix for target name
Modify "CONFIG_TARGET_AE350" to "CONFIG_TARGET_ANDES_AE350" Signed-off-by: Randolph --- arch/riscv/Kconfig | 4 ++-- arch/riscv/dts/Makefile | 2 +- board/AndesTech/ae350/Kconfig| 2 +- configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv32_spl_defconfig | 2 +- configs/ae350_rv32_spl_xip_defconfig | 2 +- configs/ae350_rv32_xip_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- configs/ae350_rv64_spl_defconfig | 2 +- configs/ae350_rv64_spl_xip_defconfig | 2 +- configs/ae350_rv64_xip_defconfig | 2 +- 11 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6771d8d919..aff1f33665 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -8,8 +8,8 @@ choice prompt "Target select" optional -config TARGET_AE350 - bool "Support ae350" +config TARGET_ANDES_AE350 + bool "Support Andes ae350" config TARGET_MICROCHIP_ICICLE bool "Support Microchip PolarFire-SoC Icicle Board" diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index f1525cb668..be6c8a4227 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb diff --git a/board/AndesTech/ae350/Kconfig b/board/AndesTech/ae350/Kconfig index 75815bf99a..a85e7d6351 100644 --- a/board/AndesTech/ae350/Kconfig +++ b/board/AndesTech/ae350/Kconfig @@ -1,4 +1,4 @@ -if TARGET_AE350 +if TARGET_ANDES_AE350 config SYS_CPU default "andesv5" diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 06a683d986..2fbb87a9b3 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -9,7 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SYS_LOAD_ADDR=0x10 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 75e55ba724..4adc1134ba 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -11,7 +11,7 @@ CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x10 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x10 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_FIT=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index c2221b891e..e19eb546a6 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -12,7 +12,7 @@ CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x10 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x10 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y CONFIG_FIT=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index 6d19400c2d..f1c1e5bc00 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -9,7 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SYS_LOAD_ADDR=0x10 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_XIP=y CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x8800 diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 0d7f0a552e..3f30842a8e 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -8,7 +8,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_LOAD_ADDR=0x10 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x8800 diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 6a72b5a047..629c5bab77 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -10,7 +10,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SPL_SYS_MALLOC_F_LEN=0x10 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x10 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 43581c79b1..4557e05445 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -11,7 +11,7 @@ CONFIG_SYS_PROMPT="
[PATCH V2 0/3] andes: rearrange defconfig and dts
Changes in v2: - Split the original patch into three smaller ones Randolph (3): configs: andes: add vender prefix for target name configs: andes: rearrange SPL mode memory layout dts: andes: add SPL config option for itb layout arch/riscv/Kconfig | 4 ++-- arch/riscv/dts/Makefile | 2 +- arch/riscv/dts/ae350-u-boot.dtsi | 1 + arch/riscv/dts/ae350_32.dts | 1 - arch/riscv/dts/ae350_64.dts | 1 - board/AndesTech/ae350/Kconfig| 8 +++- configs/ae350_rv32_defconfig | 3 ++- configs/ae350_rv32_spl_defconfig | 10 ++ configs/ae350_rv32_spl_xip_defconfig | 8 +--- configs/ae350_rv32_xip_defconfig | 3 ++- configs/ae350_rv64_defconfig | 3 ++- configs/ae350_rv64_spl_defconfig | 10 ++ configs/ae350_rv64_spl_xip_defconfig | 8 +--- configs/ae350_rv64_xip_defconfig | 3 ++- 14 files changed, 41 insertions(+), 24 deletions(-) -- 2.34.1
[PATCH] andes: rearrange defconfig and dts and memory layout for SPL.
Modify "CONFIG_AE350" to "CONFIG_ANDES_AE350"
Unify the memory layout for u-boot SPL.
Signed-off-by: Randolph
---
arch/riscv/Kconfig | 4 +-
arch/riscv/dts/Makefile | 2 +-
arch/riscv/dts/ae350-u-boot.dtsi | 1 +
arch/riscv/dts/ae350_32.dts | 61 ++--
arch/riscv/dts/ae350_64.dts | 1 -
board/AndesTech/ae350/Kconfig| 28 -
configs/ae350_rv32_defconfig | 3 +-
configs/ae350_rv32_spl_defconfig | 21 --
configs/ae350_rv32_spl_xip_defconfig | 18
configs/ae350_rv32_xip_defconfig | 3 +-
configs/ae350_rv64_defconfig | 3 +-
configs/ae350_rv64_spl_defconfig | 19 -
configs/ae350_rv64_spl_xip_defconfig | 16
configs/ae350_rv64_xip_defconfig | 3 +-
14 files changed, 101 insertions(+), 82 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6771d8d919..aff1f33665 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -8,8 +8,8 @@ choice
prompt "Target select"
optional
-config TARGET_AE350
- bool "Support ae350"
+config TARGET_ANDES_AE350
+ bool "Support Andes ae350"
config TARGET_MICROCHIP_ICICLE
bool "Support Microchip PolarFire-SoC Icicle Board"
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index f1525cb668..be6c8a4227 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
-dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb
+dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-boot.dtsi
index aef9159b7a..ff5725501f 100644
--- a/arch/riscv/dts/ae350-u-boot.dtsi
+++ b/arch/riscv/dts/ae350-u-boot.dtsi
@@ -1,4 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+#include CONFIG_SPL_LOAD_FIT_CONFIG
/ {
cpus {
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 61af6d5465..3dde0e1dfa 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -2,12 +2,11 @@
/dts-v1/;
-#include "binman.dtsi"
#include "ae350-u-boot.dtsi"
/ {
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
compatible = "andestech,a25";
model = "andestech,a25";
@@ -115,7 +114,7 @@
compatible = "cache";
cache-level = <2>;
cache-size = <0x4>;
- reg = <0xe050 0x4>;
+ reg = <0x0 0xe050 0x0 0x4>;
andes,inst-prefetch = <3>;
andes,data-prefetch = <3>;
/* The value format is */
@@ -125,12 +124,12 @@
memory@0 {
device_type = "memory";
- reg = <0x 0x4000>;
+ reg = <0x0 0x 0x0 0x4000>;
};
soc {
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
compatible = "simple-bus";
ranges;
@@ -138,7 +137,7 @@
compatible = "riscv,plic0";
#interrupt-cells = <2>;
interrupt-controller;
- reg = <0xe400 0x200>;
+ reg = <0x0 0xe400 0x0 0x200>;
riscv,ndev=<71>;
interrupts-extended = <_intc 11 _intc 9
_intc 11 _intc 9
@@ -148,9 +147,9 @@
plicsw: interrupt-controller@e640 {
compatible = "andestech,plicsw";
- #interrupt-cells = <1>;
+ #interrupt-cells = <2>;
interrupt-controller;
- reg = <0xe640 0x40>;
+ reg = <0x0 0xe640 0x0 0x40>;
riscv,ndev=<2>;
interrupts-extended = <_intc 3
_intc 3
@@ -164,7 +163,7 @@
_intc 7
_intc 7
_intc 7>;
- reg = <0xe600 0x10>;
+ reg = <0x0 0xe600 0x0 0x10>;
};
};
@@ -176,7 +175,7 @@
timer0: timer@f0
