Re: [U-Boot] ARM: sunxi: Experiences NAND flash
Hello, Reply in-line Op 17-08-15 om 08:34 schreef Boris Brezillon: Hi Oliver, Sorry for the late reply (I was in vacation for the last 2 weeks) On Tue, 11 Aug 2015 14:16:52 +0200 Olliver Schinagl oliver+l...@schinagl.nl wrote: Hello everybody, We are working with Boris and Roy's patch series on getting the NAND flash chip working on Olimex OLinuXino Lime2 boards. Initially, everything looks fine, but we noticed that occasionally (after power/cycle or power cut) ubi fails to mount the partition. It is not something easily enough to reproduce, but it has failed on 5 boards out of 30 we have. I remember warning you about that problem before: MLC NANDs are not as reliable as SLC ones (please read my presentation about MLC support in Linux [1]). I also remember recommending using an SLC chip if you were tight on time to avoid dealing with all these MLC related problems, but you decided to go for the MLC solution. Back to your problem now, what you're seeing here is probably caused by interrupted PROGRAM operations on paired pages (page 17, 18 and 26 to 32 of my presentation for more information). In his defence; we looked at it, and from what we could tell it is not possible to find an affordable SLC chip that the Allwinner A10/A20 BootROM would even boot from. In general, chips below 8K page size require 64-bit EEC strength to operate, which in turn required more OOB area than any chip would provide. This limitation is in my opinion a design fault from AllWinners side and I hope that their future SoCs can boot with more relaxed EEC settings to facilitate for cheap SLC chips, but right now there is nothing we can do to change that situation. U-boot reports the following: UBI: default fastmap pool size: 100 UBI: default fastmap WL pool size: 25 UBI: attaching mtd1 to ubi0 UBI: scanning is finished UBI init error 22 Error reading superblock on volume 'ubi:boot' errno=-19! ubifsmount - mount UBIFS volume whereas the linux kernel booted from sd card gives: ubiattach /dev/ubi_ctrl -m 0 [ 100.560704] ubi0: default fastmap pool size: 8 [ 100.565186] ubi0: default fastmap WL pool size: 4 [ 100.570100] ubi0: attaching mtd0 [ 100.590469] ubi0: scanning is finished [ 100.594732] ubi0 error: ubi_read_volume_table: the layout volume was not found [ 100.602675] ubi0 error: ubi_attach_mtd_dev: failed to attach mtd0, error -22 ubiattach: error!: cannot attach mtd0 error 22 (Invalid argument) The u-boot version we are using is a few months out of date U-Boot 2015.07-rc2-g2540c39 (Aug 04 2015 - 16:09:02 +0200) Allwinner Technology arm-none-eabi-gcc (4.8.4-1+11-1) 4.8.4 20141219 (release) GNU ld (2.25-5+5+b1) 2.25 but the kernel is fairly up to date: 4.2.0-rc4-opinicus-g8ec3671 Now I know that the mtd stuff is all very new and all very untested, what I am curious about is a) have other people actually tried the mtd stuff on Allwinner hardware, and b) has anybody encountered this issue as well? Yes we did. So far we're using the NAND in SLC mode to address this problem. It seems to work, but you also loose half the NAND capacity. So as requested by someone else: how exactly does that work? Can we just give your NAND driver a mapping between shared pages and instruct it to ignore half, or does the driver require some serious patchery? Cheers, Roy It's not something very easily reproducible (toggling a machine on/off repeatedly did not trigger it yet) but it does happen. I managed to reproduce it by faking a power cut directly in the NAND core code (by sending a RESET command to the NAND chip in the middle of a program operation), and I can confirm SLC mode address the problem. Anyway, remember that MLC NANDs have other sources of unreliability (e.g the unstable bits problem). Best Regards, Boris [1]http://events.linuxfoundation.org/sites/events/files/slides/brezillon-mlc-nand_0.pdf ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC 09/11] sunxi/nand: Enable UBI and NAND commands
Oh yes, thanks for pointing this one out. I increased the malloc pool during debugging as google hinted towards UBI being rather memory-hungry, but forgot to double-check whether it was required. I just did, and as it turns out it really only needs to be increased to 8MiB for UBI to work in my set-up. As we have plenty of memory anyway, should I allocate some extra headroom for set-ups I haven't tested (e.g. many partitions, large bad-block tables etc.) and go for 16MiB instead? Roy Op 06-06-15 om 17:36 schreef Ian Campbell: On Sat, 2015-06-06 at 17:13 +0200, Hans de Goede wrote: @@ -113,7 +113,7 @@ #endif /* 4MB of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 20)) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 20)) /* * Miscellaneous configurable options Please update the comment about malloc_pool size to match :) ...and explain in the commit log why this needs increasing as part of this change. Ian. -- IMAGINE IT MAKE IT Meet us online at Twitter http://twitter.com/ultimaker, Facebook http://facebook.com/ultimaker, Google+ http://google.com/+Ultimaker www.ultimaker.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC 02/11] mtd/nand: add ONFI timing mode to nand_timings converter
Hello Scott et al., Op 06-06-15 om 00:02 schreef Scott Wood: On Fri, 2015-06-05 at 13:52 +0200, Roy Spliet wrote: From: yassin yassinjaf...@gmail.com Signed-off-by: Roy Spliet r.spl...@ultimaker.com --- drivers/mtd/nand/Makefile | 2 +- drivers/mtd/nand/nand_timings.c | 252 include/linux/mtd/nand.h| 3 + 3 files changed, 256 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/nand/nand_timings.c This code comes from Linux and yet I see no acknowledgement of that, much less a statement of which version of Linux this was pulled from. Correct, my apologies as I should have clarified that work by Boris Brezillon does not mean upsteam work. The code comes from Boris' github tree[1] and contains work that was not yet brought upstream, yet is required for NAND on sunxi to work. It would probably be better to handle this as part of a general sync with the Linux mtd code. Ideally yes, but. In upstream Linux MTD we have a few issues to address as shown by Boris' patch-set, most importantly: - NAND chip timings (patch 1 to 3) - Randomisation support (patch 6) - Per-partition settings for ECC and randomisation (left out of my RFC, highly desirable but not strictly required for U-boot booting) - OF definition of all the above U-Boot has the additional challenge - Partitioning is not done the upstream way, but rather in/around cmd_mtdparts We started discussion on these topics in the #mtd IRC channel (OFTC), and several ideas have come up. The way I see it these issues can currently either be addressed by bolting/duct-taping/tie-wrapping more layers of indirection on top of upstream MTD framework, but really I feel that it might require a bit more of a structural approach that may or may not break existing drivers. The code I posted as RFC is functional. If you wish to steer towards an MTD sync-up, I highly suggest first getting these issues tackled, and then making sure that we extend the U-boot side of MTD with OF support for everything. This trajectory should include deprecating the current implementation of cmd_mtdparts and hook that command up to the new upstream way. In other words: now is probably not the right moment. I'm afraid that as much as I'd like to, I will not have time to address every single one of these issues (not to mention I am hardly the expert in MTD/NAND). I'm happy to think along with designing a sustainable solution, but I will need someone to chime in when it comes to carrying solutions upstream. Roy -Scott [1] https://github.com/bbrezillon/linux-sunxi/commits/sunxi-nand -- IMAGINE IT MAKE IT Meet us online at Twitter http://twitter.com/ultimaker, Facebook http://facebook.com/ultimaker, Google+ http://google.com/+Ultimaker www.ultimaker.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [linux-sunxi] Re: [RFC 02/11] mtd/nand: add ONFI timing mode to nand_timings converter
Hello Michal, Op 08-06-15 om 10:34 schreef Michal Suchanek: On 8 June 2015 at 10:11, Roy Spliet r.spl...@ultimaker.com wrote: Hello Scott et al., Op 06-06-15 om 00:02 schreef Scott Wood: On Fri, 2015-06-05 at 13:52 +0200, Roy Spliet wrote: From: yassin yassinjaf...@gmail.com Signed-off-by: Roy Spliet r.spl...@ultimaker.com --- drivers/mtd/nand/Makefile | 2 +- drivers/mtd/nand/nand_timings.c | 252 include/linux/mtd/nand.h| 3 + 3 files changed, 256 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/nand/nand_timings.c This code comes from Linux and yet I see no acknowledgement of that, much less a statement of which version of Linux this was pulled from. Correct, my apologies as I should have clarified that work by Boris Brezillon does not mean upsteam work. The code comes from Boris' github tree[1] and contains work that was not yet brought upstream, yet is required for NAND on sunxi to work. It would probably be better to handle this as part of a general sync with the Linux mtd code. Ideally yes, but. In upstream Linux MTD we have a few issues to address as shown by Boris' patch-set, most importantly: - NAND chip timings (patch 1 to 3) - Randomisation support (patch 6) - Per-partition settings for ECC and randomisation (left out of my RFC, highly desirable but not strictly required for U-boot booting) Hello, as I understand it the ECC and randomisation settings for the bootloader part of the nand are suboptimal or unusable for ubifs so if u-boot SPL is to read the u-boot binary and later u-boot the kernel from an ubifs volume it has to support non-uniform settings. Alternatively the bootloader part can be extended to contain partitions for u-boot binary and kernel image written to raw partition without filesystem much like what Andriod usually does. SPL does not read U-boot from UBI. The SPL driver is separate, much smaller and only reads in the same way BROM does. U-boot itself is not bound by the limitations imposed by BROM, which means proper randomisation and ECC settings can be used for the UBI partition. Yours, Roy Thanks Michal -- IMAGINE IT MAKE IT Meet us online at Twitter http://twitter.com/ultimaker, Facebook http://facebook.com/ultimaker, Google+ http://google.com/+Ultimaker www.ultimaker.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [linux-sunxi] [RFC 11/11] mtd/nand: Sunxi NAND boot partition definitions
Hello Michal, Op 07-06-15 om 18:48 schreef Michal Suchanek: Hello, On 5 June 2015 at 13:52, Roy Spliet r.spl...@ultimaker.com wrote: Based on the default layout of the android image used at least on Olimex Lime Signed-off-by: Roy Spliet r.spl...@ultimaker.com --- include/configs/sunxi-common.h | 9 + 1 file changed, 9 insertions(+) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index ec28c40..b38f2f5 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -404,8 +404,15 @@ extern int soft_i2c_gpio_scl; #define BOOT_TARGET_DEVICES_USB(func) #endif +#ifdef CONFIG_NAND +#define BOOT_TARGET_DEVICES_NAND(func) func(NAND, nand , 0) +#else +#define BOOT_TARGET_DEVICES_NAND(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_NAND(func) \ BOOT_TARGET_DEVICES_SCSI(func) \ BOOT_TARGET_DEVICES_USB(func) \ func(PXE, pxe, na) \ @@ -441,6 +448,8 @@ extern int soft_i2c_gpio_scl; MEM_LAYOUT_ENV_SETTINGS \ fdtfile= CONFIG_DEFAULT_DEVICE_TREE .dtb\0 \ console=ttyS0,115200\0 \ + mtdids=nand0=mtd2\0 \ + mtdparts=mtdparts=mtd2:0xffc0@0x40(nand0_main)\0 \ BOOTENV From what I heard the nand boot partition size should be specified in nand pages rather than bytes because the boot rom loads a fixed number of pages and just uses the start of each page regardless of page size. Although I believe you have the facts mostly right, they do not apply in this situation. What you are looking for is the partition definition for U-boot. At this point the boot rom (BROM) is no longer active and thus it's inner workings are mostly irrelevant. The NAND partition lay-out for the boards I have seen (various Olimex + Cubietruck..) are as follows: 0-2MB U-Boot-SPL + U-Boot 2-4MB U-Boot SPL + U-Boot (for recovery) 4MB+ Main file system The mtdparts env variable defines only the main file system because that's the only place with relevant files for U-Boot. This said: I have replaced the default file system with a custom UBI FS containing just a boot and a rootfs partition. I am unsure whether these defaults apply for the Android image that ships with the Olimex boards. But then again: that image also ships with a boot-loader, so do we care? I did not find any document regarding the nand boot partition layout so I would like to see some input from somebody familiar with the driver. While it is fine for testing to hand-edit the environment the final nand support should have 1) way to express the boot partition size in nand pages 2) way to make the main partition start at the end of boot partition and extend to the end of the flash This should probably also go to Linux. Linux can define partitions in the device tree. I'd prefer to carry this approach to U-boot, but current U-Boot has the partitioning part of the MTD code hacked away and replaced by custom mtdparts code without OF support. Doing this proper requires getting rid of the latter, which will likely break a lot of legacy. So as far as I agree, I have to warn that is a longer-term project, extended further by the ongoing (justified) discussion we are having regarding the MTD partitioning code in upstream Linux that may or may not lead to parts of the framework being re-architected. Roy Thanks Michal -- IMAGINE IT MAKE IT Meet us online at Twitter http://twitter.com/ultimaker, Facebook http://facebook.com/ultimaker, Google+ http://google.com/+Ultimaker www.ultimaker.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [linux-sunxi] [RFC 11/11] mtd/nand: Sunxi NAND boot partition definitions
Dear Michal, Op 08-06-15 om 10:54 schreef Michal Suchanek: On 8 June 2015 at 10:38, Roy Spliet r.spl...@ultimaker.com wrote: Hello Michal, Op 07-06-15 om 18:48 schreef Michal Suchanek: Hello, On 5 June 2015 at 13:52, Roy Spliet r.spl...@ultimaker.com wrote: Based on the default layout of the android image used at least on Olimex Lime Signed-off-by: Roy Spliet r.spl...@ultimaker.com --- include/configs/sunxi-common.h | 9 + 1 file changed, 9 insertions(+) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index ec28c40..b38f2f5 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -404,8 +404,15 @@ extern int soft_i2c_gpio_scl; #define BOOT_TARGET_DEVICES_USB(func) #endif +#ifdef CONFIG_NAND +#define BOOT_TARGET_DEVICES_NAND(func) func(NAND, nand , 0) +#else +#define BOOT_TARGET_DEVICES_NAND(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_NAND(func) \ BOOT_TARGET_DEVICES_SCSI(func) \ BOOT_TARGET_DEVICES_USB(func) \ func(PXE, pxe, na) \ @@ -441,6 +448,8 @@ extern int soft_i2c_gpio_scl; MEM_LAYOUT_ENV_SETTINGS \ fdtfile= CONFIG_DEFAULT_DEVICE_TREE .dtb\0 \ console=ttyS0,115200\0 \ + mtdids=nand0=mtd2\0 \ + mtdparts=mtdparts=mtd2:0xffc0@0x40(nand0_main)\0 \ BOOTENV From what I heard the nand boot partition size should be specified in nand pages rather than bytes because the boot rom loads a fixed number of pages and just uses the start of each page regardless of page size. Although I believe you have the facts mostly right, they do not apply in this situation. What you are looking for is the partition definition for U-boot. At this point the boot rom (BROM) is no longer active and thus it's inner workings are mostly irrelevant. The NAND partition lay-out for the boards I have seen (various Olimex + Cubietruck..) are as follows: 0-2MB U-Boot-SPL + U-Boot OK, so 0-2 MB has to be read (at least in part) by brom to load the SPL so it must be in the format brom understands. The part containing the SPL which is read by brom has certain number of pages. The u-boot part can contain whatever we define. 2-4MB U-Boot SPL + U-Boot (for recovery) 4MB+ Main file system The main filesystem has to be in format suitable for UBIFS. It has to follow u-boot part possibly with some space in between. If support for non-uniform flash format is not available then there are basically two options: 1) SPL supports brom format and u-boot binary is part of boot partition. SPL can read/write itself and u-boot and u-boot can read/write the main partition 2) SPL and u-boot support the main partition format. While u-boot is written to the boot partition its pages are written in the format suitable for ubifs. This will get hairy when you want to actually write u-boot and SPL. The problem with counting the partition sizes in bytes is obvious - whatever you do the brom reads predefined number of pages from the start of the nand to load the SPL and unless you know maximum page size of every nand ever made that is compatible with Allwinner brom you cannot tell what is even the maximum size of this part in bytes.] The solution already implemented now and carried to Hans' tree is 1) with the size of SPL aligned to 8KB blocks (the largest of the page sizes attempted). The modes tried by BROM are listed in [1]. SPL currently tries only a single mode whose params are defined in sunxi-common.h, but this is likely to change to a brute-force approach to resemble BROM in the near future. Yours, Roy Thanks Michal [1] https://linux-sunxi.org/NAND -- IMAGINE IT MAKE IT Meet us online at Twitter http://twitter.com/ultimaker, Facebook http://facebook.com/ultimaker, Google+ http://google.com/+Ultimaker www.ultimaker.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [linux-sunxi] [RFC 11/11] mtd/nand: Sunxi NAND boot partition definitions
Hello Hans, Op 08-06-15 om 15:16 schreef Hans de Goede: Hi Roy, On 08-06-15 10:38, Roy Spliet wrote: Hello Michal, Op 07-06-15 om 18:48 schreef Michal Suchanek: Hello, On 5 June 2015 at 13:52, Roy Spliet r.spl...@ultimaker.com wrote: Based on the default layout of the android image used at least on Olimex Lime Signed-off-by: Roy Spliet r.spl...@ultimaker.com --- include/configs/sunxi-common.h | 9 + 1 file changed, 9 insertions(+) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index ec28c40..b38f2f5 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -404,8 +404,15 @@ extern int soft_i2c_gpio_scl; #define BOOT_TARGET_DEVICES_USB(func) #endif +#ifdef CONFIG_NAND +#define BOOT_TARGET_DEVICES_NAND(func) func(NAND, nand , 0) +#else +#define BOOT_TARGET_DEVICES_NAND(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_NAND(func) \ BOOT_TARGET_DEVICES_SCSI(func) \ BOOT_TARGET_DEVICES_USB(func) \ func(PXE, pxe, na) \ @@ -441,6 +448,8 @@ extern int soft_i2c_gpio_scl; MEM_LAYOUT_ENV_SETTINGS \ fdtfile= CONFIG_DEFAULT_DEVICE_TREE .dtb\0 \ console=ttyS0,115200\0 \ + mtdids=nand0=mtd2\0 \ + mtdparts=mtdparts=mtd2:0xffc0@0x40(nand0_main)\0 \ BOOTENV From what I heard the nand boot partition size should be specified in nand pages rather than bytes because the boot rom loads a fixed number of pages and just uses the start of each page regardless of page size. Although I believe you have the facts mostly right, they do not apply in this situation. What you are looking for is the partition definition for U-boot. At this point the boot rom (BROM) is no longer active and thus it's inner workings are mostly irrelevant. The NAND partition lay-out for the boards I have seen (various Olimex + Cubietruck..) are as follows: 0-2MB U-Boot-SPL + U-Boot 2-4MB U-Boot SPL + U-Boot (for recovery) 4MB+ Main file system The mtdparts env variable defines only the main file system because that's the only place with relevant files for U-Boot. This said: I have replaced the default file system with a custom UBI FS containing just a boot and a rootfs partition. I am unsure whether these defaults apply for the Android image that ships with the Olimex boards. But then again: that image also ships with a boot-loader, so do we care? I did not find any document regarding the nand boot partition layout so I would like to see some input from somebody familiar with the driver. While it is fine for testing to hand-edit the environment the final nand support should have 1) way to express the boot partition size in nand pages 2) way to make the main partition start at the end of boot partition and extend to the end of the flash This should probably also go to Linux. Linux can define partitions in the device tree. I'd prefer to carry this approach to U-boot, but current U-Boot has the partitioning part of the MTD code hacked away and replaced by custom mtdparts code without OF support. Doing this proper requires getting rid of the latter, which will likely break a lot of legacy. So as far as I agree, I have to warn that is a longer-term project, extended further by the ongoing (justified) discussion we are having regarding the MTD partitioning code in upstream Linux that may or may not lead to parts of the framework being re-architected. Last time I discussed this with some kernel people, they pointed me to the fact that the kernel actually parses partition info provided by u-boot through the u-boot mtdparts command, and that that is the preferred way to pass partition info to the kernel, so rather then adding dts partition info to u-boot we would need to teach the existing kernel mtdpart code to deal with separate ecc / random setting and maybe use a list of hardcoded partitition names for which to use the brom compatible settings. These are all things which we need to figure out on the kernel side, it would be good to get a discussion started on this with the kernel mtd people. I am unaware of the kernel developers' preferences, but [1] shows that the kernel gained OF (DTS) partition parsing in 2008. We do need to teach the kernel (and U-Boot) the trick of parsing mtd partitions, but with ARM/Linaro pushing DTS as the preferred way to describe hardware we might have to consider this a separate discussion point. Note that we will also need to have a u-boot env partition somewhare either at the nandpart level, or as a ubi volume, assuming the u-boot env code can deal with ubi volumes (we are in the full u-boot environment when reading the env.) Thanks, this is a relevant addition and something that needs investigation. Unfortunately I can probably not pull this wagon too much further, given I am about to continue my career in academics starting next month. I'd be happy
Re: [U-Boot] [linux-sunxi] [RFC 11/11] mtd/nand: Sunxi NAND boot partition definitions
Hello Yassin, Op 08-06-15 om 12:48 schreef Yassin: Hi Roy Thank you for working on this, I would like to suggest if you could implement separate control commands to switch ECC and Randomisation modes per partitions. I know this is not the best approach but it will provide more controls. Thanks for the suggestion. However, for now I do not see the immediate need for this in U-boot. U-boot should really only care about one thing: load Linux. Therefore, the only partition it needs to be able to read is whatever partition is used for storing boot data on. And if we only care about one NAND partition, we don't need per-partition settings. I agree that it would be nice to have eventually, but I think this problem first needs to be solved in Linux properly. Then in U-boot we can sync MTD up with Linux and we get the support we need for free. I'd personally recommend to take this approach over now first hacking up all sorts of new commands in U-boot, as the latter will create more problems with syncing up MTD and doing the right thing on the longer run. Yours, Roy On 8 Jun 2015, at 7:11 pm, Roy Spliet r.spl...@ultimaker.com wrote: Dear Michal, Op 08-06-15 om 10:54 schreef Michal Suchanek: On 8 June 2015 at 10:38, Roy Spliet r.spl...@ultimaker.com wrote: Hello Michal, Op 07-06-15 om 18:48 schreef Michal Suchanek: Hello, On 5 June 2015 at 13:52, Roy Spliet r.spl...@ultimaker.com wrote: Based on the default layout of the android image used at least on Olimex Lime Signed-off-by: Roy Spliet r.spl...@ultimaker.com --- include/configs/sunxi-common.h | 9 + 1 file changed, 9 insertions(+) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index ec28c40..b38f2f5 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -404,8 +404,15 @@ extern int soft_i2c_gpio_scl; #define BOOT_TARGET_DEVICES_USB(func) #endif +#ifdef CONFIG_NAND +#define BOOT_TARGET_DEVICES_NAND(func) func(NAND, nand , 0) +#else +#define BOOT_TARGET_DEVICES_NAND(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_NAND(func) \ BOOT_TARGET_DEVICES_SCSI(func) \ BOOT_TARGET_DEVICES_USB(func) \ func(PXE, pxe, na) \ @@ -441,6 +448,8 @@ extern int soft_i2c_gpio_scl; MEM_LAYOUT_ENV_SETTINGS \ fdtfile= CONFIG_DEFAULT_DEVICE_TREE .dtb\0 \ console=ttyS0,115200\0 \ + mtdids=nand0=mtd2\0 \ + mtdparts=mtdparts=mtd2:0xffc0@0x40(nand0_main)\0 \ BOOTENV From what I heard the nand boot partition size should be specified in nand pages rather than bytes because the boot rom loads a fixed number of pages and just uses the start of each page regardless of page size. Although I believe you have the facts mostly right, they do not apply in this situation. What you are looking for is the partition definition for U-boot. At this point the boot rom (BROM) is no longer active and thus it's inner workings are mostly irrelevant. The NAND partition lay-out for the boards I have seen (various Olimex + Cubietruck..) are as follows: 0-2MB U-Boot-SPL + U-Boot OK, so 0-2 MB has to be read (at least in part) by brom to load the SPL so it must be in the format brom understands. The part containing the SPL which is read by brom has certain number of pages. The u-boot part can contain whatever we define. 2-4MB U-Boot SPL + U-Boot (for recovery) 4MB+ Main file system The main filesystem has to be in format suitable for UBIFS. It has to follow u-boot part possibly with some space in between. If support for non-uniform flash format is not available then there are basically two options: 1) SPL supports brom format and u-boot binary is part of boot partition. SPL can read/write itself and u-boot and u-boot can read/write the main partition 2) SPL and u-boot support the main partition format. While u-boot is written to the boot partition its pages are written in the format suitable for ubifs. This will get hairy when you want to actually write u-boot and SPL. The problem with counting the partition sizes in bytes is obvious - whatever you do the brom reads predefined number of pages from the start of the nand to load the SPL and unless you know maximum page size of every nand ever made that is compatible with Allwinner brom you cannot tell what is even the maximum size of this part in bytes.] The solution already implemented now and carried to Hans' tree is 1) with the size of SPL aligned to 8KB blocks (the largest of the page sizes attempted). The modes tried by BROM are listed in [1]. SPL currently tries only a single mode whose params are defined in sunxi-common.h, but this is likely to change to a brute-force approach to resemble BROM in the near future. Yours, Roy Thanks Michal [1] https://linux-sunxi.org/NAND -- IMAGINE IT MAKE IT Meet us online at Twitter http://twitter.com/ultimaker, Facebook http://facebook.com/ultimaker
[U-Boot] [RFC 01/11] mtd/nand: define struct nand_timings
From: yassin yassinjaf...@gmail.com
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
include/linux/mtd/nand.h | 49
1 file changed, 49 insertions(+)
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index bc927ec..b026110 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -1008,6 +1008,55 @@ static inline int jedec_feature(struct nand_chip *chip)
: 0;
}
+/**
+ * struct nand_sdr_timings - SDR NAND chip timings
+ *
+ * This struct defines the timing requirements of a SDR NAND chip.
+ * These informations can be found in every NAND datasheets and the timings
+ * meaning are described in the ONFI specifications:
+ * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
+ * Parameters)
+ *
+ * All these timings are expressed in picoseconds.
+ */
+
+struct nand_sdr_timings {
+ u32 tALH_min;
+ u32 tADL_min;
+ u32 tALS_min;
+ u32 tAR_min;
+ u32 tCEA_max;
+ u32 tCEH_min;
+ u32 tCH_min;
+ u32 tCHZ_max;
+ u32 tCLH_min;
+ u32 tCLR_min;
+ u32 tCLS_min;
+ u32 tCOH_min;
+ u32 tCS_min;
+ u32 tDH_min;
+ u32 tDS_min;
+ u32 tFEAT_max;
+ u32 tIR_min;
+ u32 tITC_max;
+ u32 tRC_min;
+ u32 tREA_max;
+ u32 tREH_min;
+ u32 tRHOH_min;
+ u32 tRHW_min;
+ u32 tRHZ_max;
+ u32 tRLOH_min;
+ u32 tRP_min;
+ u32 tRR_min;
+ u64 tRST_max;
+ u32 tWB_max;
+ u32 tWC_min;
+ u32 tWH_min;
+ u32 tWHR_min;
+ u32 tWP_min;
+ u32 tWW_min;
+};
+
#ifdef __UBOOT__
/* Standard NAND functions from nand_base.c */
void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
--
2.4.2
--
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[U-Boot] [RFC] Sunxi NAND support for U-Boot
Following up on earlier SPL patches, here a series based on Yassin Jaffer's work to bring NAND support to U-boot. RFC because I know that the sunxi nand configuration options are dependent on a work-in-progress by Daniel - trying to deliver a single SPL for both MMC and NAND boot. Given I have spent the past few weeks learning how Boris' original driver works, I have probably grown a bit blind for potentially existing issues. Please provide plenty of feedback so I can bring this in good shape. Patches tested on an Olimex Lime with 4GB Hynix nand. Has a partition as defined in sunxi-common.h with two UBIFS partitions (boot, rootfs) set up in Linux. To me it feels self-explanatory how to set this up, but I've spent the last few weeks full-time on this, implying my view of the world and how it revolves around MTD is rather distorted. Feel free to ask directed questions if you desire assistance in setting up and/or testing. Thanks! Roy -- IMAGINE IT MAKE IT Meet us online at Twitter http://twitter.com/ultimaker, Facebook http://facebook.com/ultimaker, Google+ http://google.com/+Ultimaker www.ultimaker.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC 02/11] mtd/nand: add ONFI timing mode to nand_timings converter
From: yassin yassinjaf...@gmail.com
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
drivers/mtd/nand/Makefile | 2 +-
drivers/mtd/nand/nand_timings.c | 252
include/linux/mtd/nand.h| 3 +
3 files changed, 256 insertions(+), 1 deletion(-)
create mode 100644 drivers/mtd/nand/nand_timings.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index a0cf4d5..f194493 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -32,7 +32,7 @@ obj-y += nand_bbt.o
obj-y += nand_ids.o
obj-y += nand_util.o
obj-y += nand_ecc.o
-obj-y += nand_base.o
+obj-y += nand_base.o nand_timings.o
endif # not spl
diff --git a/drivers/mtd/nand/nand_timings.c b/drivers/mtd/nand/nand_timings.c
new file mode 100644
index 000..9e8b0a5
--- /dev/null
+++ b/drivers/mtd/nand/nand_timings.c
@@ -0,0 +1,252 @@
+/*
+ * Copyright (C) 2014 Free Electrons
+ *
+ * Author: Boris BREZILLON boris.brezil...@free-electrons.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include common.h
+#include linux/err.h
+#include linux/mtd/nand.h
+
+static const struct nand_sdr_timings onfi_sdr_timings[] = {
+ /* Mode 0 */
+ {
+ .tADL_min = 20,
+ .tALH_min = 2,
+ .tALS_min = 5,
+ .tAR_min = 25000,
+ .tCEA_max = 10,
+ .tCEH_min = 2,
+ .tCH_min = 2,
+ .tCHZ_max = 10,
+ .tCLH_min = 2,
+ .tCLR_min = 2,
+ .tCLS_min = 5,
+ .tCOH_min = 0,
+ .tCS_min = 7,
+ .tDH_min = 2,
+ .tDS_min = 4,
+ .tFEAT_max = 100,
+ .tIR_min = 1,
+ .tITC_max = 100,
+ .tRC_min = 10,
+ .tREA_max = 4,
+ .tREH_min = 3,
+ .tRHOH_min = 0,
+ .tRHW_min = 20,
+ .tRHZ_max = 20,
+ .tRLOH_min = 0,
+ .tRP_min = 5,
+ .tRST_max = 2500ULL,
+ .tWB_max = 20,
+ .tRR_min = 4,
+ .tWC_min = 10,
+ .tWH_min = 3,
+ .tWHR_min = 12,
+ .tWP_min = 5,
+ .tWW_min = 10,
+ },
+ /* Mode 1 */
+ {
+ .tADL_min = 10,
+ .tALH_min = 1,
+ .tALS_min = 25000,
+ .tAR_min = 1,
+ .tCEA_max = 45000,
+ .tCEH_min = 2,
+ .tCH_min = 1,
+ .tCHZ_max = 5,
+ .tCLH_min = 1,
+ .tCLR_min = 1,
+ .tCLS_min = 25000,
+ .tCOH_min = 15000,
+ .tCS_min = 35000,
+ .tDH_min = 1,
+ .tDS_min = 2,
+ .tFEAT_max = 100,
+ .tIR_min = 0,
+ .tITC_max = 100,
+ .tRC_min = 5,
+ .tREA_max = 3,
+ .tREH_min = 15000,
+ .tRHOH_min = 15000,
+ .tRHW_min = 10,
+ .tRHZ_max = 10,
+ .tRLOH_min = 0,
+ .tRP_min = 25000,
+ .tRR_min = 2,
+ .tRST_max = 5,
+ .tWB_max = 10,
+ .tWC_min = 45000,
+ .tWH_min = 15000,
+ .tWHR_min = 8,
+ .tWP_min = 25000,
+ .tWW_min = 10,
+ },
+ /* Mode 2 */
+ {
+ .tADL_min = 10,
+ .tALH_min = 1,
+ .tALS_min = 15000,
+ .tAR_min = 1,
+ .tCEA_max = 3,
+ .tCEH_min = 2,
+ .tCH_min = 1,
+ .tCHZ_max = 5,
+ .tCLH_min = 1,
+ .tCLR_min = 1,
+ .tCLS_min = 15000,
+ .tCOH_min = 15000,
+ .tCS_min = 25000,
+ .tDH_min = 5000,
+ .tDS_min = 15000,
+ .tFEAT_max = 100,
+ .tIR_min = 0,
+ .tITC_max = 100,
+ .tRC_min = 35000,
+ .tREA_max = 25000,
+ .tREH_min = 15000,
+ .tRHOH_min = 15000,
+ .tRHW_min = 10,
+ .tRHZ_max = 10,
+ .tRLOH_min = 0,
+ .tRR_min = 2,
+ .tRST_max = 5,
+ .tWB_max = 10,
+ .tRP_min = 17000,
+ .tWC_min = 35000,
+ .tWH_min = 15000,
+ .tWHR_min = 8,
+ .tWP_min = 17000
[U-Boot] [RFC 03/11] mtd/nand: support ONFI timing mode retrieval for non-ONFI
From: yassin yassinjaf...@gmail.com
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
drivers/mtd/nand/nand_base.c | 1 +
include/linux/mtd/nand.h | 7 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index c0e381a..dbeb092 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -3709,6 +3709,7 @@ static bool find_full_id_nand(struct mtd_info *mtd,
struct nand_chip *chip,
chip-options |= type-options;
chip-ecc_strength_ds = NAND_ECC_STRENGTH(type);
chip-ecc_step_ds = NAND_ECC_STEP(type);
+ chip-onfi_timing_mode_ds = type-onfi_timing_mode_ds;
*busw = type-options NAND_BUSWIDTH_16;
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index abda5c3..0cdb3b9 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -634,6 +634,7 @@ struct nand_buffers {
* @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
* also from the datasheet. It is the recommended ECC step
* size, if known; if unknown, set to zero.
+ * @onfi_timing_mode_ds:[INTERN] ONFI timing mode deduced from datasheet.
* @numchips: [INTERN] number of physical chips
* @chipsize: [INTERN] the size of one chip for multichip arrays
* @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
@@ -718,6 +719,7 @@ struct nand_chip {
uint8_t bits_per_cell;
uint16_t ecc_strength_ds;
uint16_t ecc_step_ds;
+ int onfi_timing_mode_ds;
int badblockpos;
int badblockbits;
@@ -822,6 +824,10 @@ struct nand_chip {
* @ecc_step_ds in nand_chip{}, also from the datasheet.
* For example, the 4bit ECC for each 512Byte can be set with
* NAND_ECC_INFO(4, 512).
+ * @onfi_timing_mode_ds: the ONFI timing mode supported by this NAND chip. This
+ * should be deduced from timings described in the
+ * datasheet.
+ *
*/
struct nand_flash_dev {
char *name;
@@ -842,6 +848,7 @@ struct nand_flash_dev {
uint16_t strength_ds;
uint16_t step_ds;
} ecc;
+ int onfi_timing_mode_ds;
};
/**
--
2.4.2
--
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[U-Boot] [RFC 11/11] mtd/nand: Sunxi NAND boot partition definitions
Based on the default layout of the android image used at least on Olimex Lime Signed-off-by: Roy Spliet r.spl...@ultimaker.com --- include/configs/sunxi-common.h | 9 + 1 file changed, 9 insertions(+) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index ec28c40..b38f2f5 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -404,8 +404,15 @@ extern int soft_i2c_gpio_scl; #define BOOT_TARGET_DEVICES_USB(func) #endif +#ifdef CONFIG_NAND +#define BOOT_TARGET_DEVICES_NAND(func) func(NAND, nand , 0) +#else +#define BOOT_TARGET_DEVICES_NAND(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_NAND(func) \ BOOT_TARGET_DEVICES_SCSI(func) \ BOOT_TARGET_DEVICES_USB(func) \ func(PXE, pxe, na) \ @@ -441,6 +448,8 @@ extern int soft_i2c_gpio_scl; MEM_LAYOUT_ENV_SETTINGS \ fdtfile= CONFIG_DEFAULT_DEVICE_TREE .dtb\0 \ console=ttyS0,115200\0 \ + mtdids=nand0=mtd2\0 \ + mtdparts=mtdparts=mtd2:0xffc0@0x40(nand0_main)\0 \ BOOTENV #else /* ifndef CONFIG_SPL_BUILD */ -- 2.4.2 -- IMAGINE IT MAKE IT Meet us online at Twitter http://twitter.com/ultimaker, Facebook http://facebook.com/ultimaker, Google+ http://google.com/+Ultimaker www.ultimaker.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC 07/11] mtd/nand Add Sunxi NAND driver
Heavily based on BBrezillon's (downstream) driver. Most noticable differences - No per-partition ECC settings. Partitions in U-boot are quite different from Linux - U-boot register definitions, shared with sunxi_nand_spl - FDT parsing in-line, there's no framework method yet Signed-off-by: Roy Spliet r.spl...@ultimaker.com --- arch/arm/include/asm/arch-sunxi/nand.h | 46 +- board/sunxi/board.c|5 + drivers/mtd/nand/Makefile |1 + drivers/mtd/nand/sunxi_nand.c | 1887 include/fdtdec.h | 13 + lib/fdtdec.c | 17 + 6 files changed, 1966 insertions(+), 3 deletions(-) create mode 100644 drivers/mtd/nand/sunxi_nand.c diff --git a/arch/arm/include/asm/arch-sunxi/nand.h b/arch/arm/include/asm/arch-sunxi/nand.h index 22844d8..d0fae80 100644 --- a/arch/arm/include/asm/arch-sunxi/nand.h +++ b/arch/arm/include/asm/arch-sunxi/nand.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2015 Roy Spliet rspl...@ultimaker.com + * (C) Copyright 2015 Roy Spliet r.spl...@ultimaker.com * * SPDX-License-Identifier:GPL-2.0+ */ @@ -27,8 +27,7 @@ struct sunxi_nand u32 ecc_ctl;/* 0x034 ECC configure and control */ u32 ecc_st; /* 0x038 ECC status and operation info */ u32 efr;/* 0x03C Enhanced feature */ - u32 err_cnt0; /* 0x040 Corrected error bit counter 0 */ - u32 err_cnt1; /* 0x044 Corrected error bit counter 1 */ + u32 err_cnt[4]; /* 0x040[4] Corrected error bit counter 0 */ u32 user_data[16]; /* 0x050[16] User data field */ u32 efnand_st; /* 0x090 EFNAND status */ u32 res0[3]; @@ -40,28 +39,69 @@ struct sunxi_nand u32 res1[3]; u32 mdma_addr; /* 0x0C0 MBUS DMA Address */ u32 mdma_cnt; /* 0x0C4 MBUS DMA data counter */ + u32 res2[206]; + u32 ram0_base; }; #define SUNXI_NAND_CTL_EN (1 0) #define SUNXI_NAND_CTL_RST (1 1) +#define SUNXI_NAND_BUS_WIDTH (1 2) +#define SUNXI_NAND_CTL_RB_SEL_MASK (0x3 3) +#define SUNXI_NAND_CTL_RB_SEL(a) ((a) 3) +#define SUNXI_NAND_CTL_CE_ACT (1 6) +#define SUNXI_NAND_CTL_PAGE_SIZE_MASK (0xf 8) #define SUNXI_NAND_CTL_PAGE_SIZE(a)((fls(a) - 11) 8) #define SUNXI_NAND_CTL_RAM_METHOD_DMA (1 14) +#define SUNXI_NAND_CTL_CE_SEL_MASK (0xf 24) +#define SUNXI_NAND_CTL_CE_SEL(a) (a 24) +#define SUNXI_NAND_CTL_DEBUG (1 31) +#define SUNXI_NAND_ST_RB_B2R (1 0) #define SUNXI_NAND_ST_CMD_INT (1 1) #define SUNXI_NAND_ST_DMA_INT (1 2) #define SUNXI_NAND_ST_FIFO_FULL(1 3) +#define SUNXI_NAND_ST_BUSY (1 4) +#define SUNXI_NAND_ST_RB_STATE0(1 8) +#define SUNXI_NAND_ST_RB_STATE1(1 9) +#define SUNXI_NAND_ST_RB_STATE2(1 10) +#define SUNXI_NAND_ST_RB_STATE3(1 11) + +#define SUNXI_NAND_INT_B2R_ENABLE (1 0) +#define SUNXI_NAND_INT_CMD_ENABLE (1 1) +#define SUNXI_NAND_INT_DMA_ENABLE (1 2) +#define SUNXI_NAND_INT_MASK(SUNXI_NAND_INT_B2R_ENABLE | \ +SUNXI_NAND_INT_CMD_ENABLE | \ +SUNXI_NAND_INT_DMA_ENABLE) + +#define SUNXI_NAND_CMD_LOW_BYTE(a) (a 0xff) +#define SUNXI_NAND_CMD_HIGH_BYTE(a)((a 0xff) 8) #define SUNXI_NAND_CMD_ADDR_CYCLES(a) ((a - 1) 16); +#define SUNXI_NAND_CMD_SEND_ADR(1 19) +#define SUNXI_NAND_CMD_ACCESS_RD 0 +#define SUNXI_NAND_CMD_ACCESS_WR (1 20) +#define SUNXI_NAND_CMD_DATA_TRANS (1 21) #define SUNXI_NAND_CMD_SEND_CMD1 (1 22) #define SUNXI_NAND_CMD_WAIT_FLAG (1 23) +#define SUNXI_NAND_CMD_SEND_CMD2 (1 24) #define SUNXI_NAND_CMD_ORDER_INTERLEAVE0 #define SUNXI_NAND_CMD_ORDER_SEQ (1 25) +#define SUNXI_NAND_CMD_DATA_SWAP_METHOD(1 26) +#define SUNXI_NAND_CMD_ROW_AUTO_INC(1 27) +#define SUNXI_NAND_CMD_SEND_CMD3 (1 28) +#define SUNXI_NAND_CMD_SEND_CMD4 (1 29) #define SUNXI_NAND_ECC_CTL_ECC_EN (1 0) #define SUNXI_NAND_ECC_CTL_PIPELINE(1 3) +#define SUNXI_NAND_ECC_CTL_EXCEPTION (1 4) #define SUNXI_NAND_ECC_CTL_BS_512B (1 5) #define SUNXI_NAND_ECC_CTL_RND_EN (1 9) +#define SUNXI_NAND_ECC_CTL_RND_DIRECTION (1 10) +#define SUNXI_NAND_ECC_CTL_MODE_MASK (0xf 12) #define SUNXI_NAND_ECC_CTL_MODE(a) ((a) 12) +#define
[U-Boot] [RFC 04/11] mtd/nand: add page status table (pst)
From: yassin yassinjaf...@gmail.com
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
drivers/mtd/nand/nand_base.c | 154 +++
include/linux/mtd/nand.h | 21 ++
2 files changed, 175 insertions(+)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index dbeb092..1c514a0 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1185,6 +1185,138 @@ EXPORT_SYMBOL(nand_lock);
#endif
/**
+ * nand_page_is_empty - check wether a NAND page contains only FFs
+ * @mtd: mtd info
+ * @data: data buffer
+ * @oob: oob buffer
+ *
+ * Reads the data stored in the databuf buffer and check if it contains only
+ * FFs.
+ *
+ * Return true if it does else return false.
+ */
+bool nand_page_is_empty(struct mtd_info *mtd, void *data, void *oob)
+{
+ u8 *buf;
+ int length;
+ u32 pattern = 0x;
+ int bitflips = 0;
+ int cnt;
+
+ buf = data;
+ length = mtd-writesize;
+ while (length) {
+ cnt = length sizeof(pattern) ? length : sizeof(pattern);
+ if (memcmp(pattern, buf, cnt)) {
+ int i;
+ for (i = 0; i cnt * 8; i++) {
+ if (!(buf[i / 8]
+ (1 (i % 8 {
+ bitflips++;
+ if (bitflips mtd-ecc_strength)
+ return false;
+ }
+ }
+ }
+
+ buf += sizeof(pattern);
+ length -= sizeof(pattern);
+ }
+
+ buf = oob;
+ length = mtd-oobsize;
+ while (length) {
+ cnt = length sizeof(pattern) ? length : sizeof(pattern);
+ if (memcmp(pattern, buf, cnt)) {
+ int i;
+ for (i = 0; i cnt * 8; i++) {
+ if (!(buf[i / 8]
+ (1 (i % 8 {
+ bitflips++;
+ if (bitflips mtd-ecc_strength)
+ return false;
+ }
+ }
+ }
+
+ buf += sizeof(pattern);
+ length -= sizeof(pattern);
+ }
+
+ return true;
+}
+EXPORT_SYMBOL(nand_page_is_empty);
+
+/**
+ * nand_page_get_status - retrieve page status from the page status table (pst)
+ * @mtd: mtd info
+ * @page: page you want to get status on
+ *
+ * Return the page status.
+ */
+int nand_page_get_status(struct mtd_info *mtd, int page)
+{
+ struct nand_chip *chip = mtd-priv;
+ u8 shift = (page % 4) * 2;
+ uint64_t offset = page / 4;
+ int ret = NAND_PAGE_STATUS_UNKNOWN;
+
+ if (chip-pst)
+ ret = (chip-pst[offset] shift) 0x3;
+
+ return ret;
+}
+EXPORT_SYMBOL(nand_page_get_status);
+
+/**
+ * nand_page_set_status - assign page status from in the page status table
+ * @mtd: mtd info
+ * @page: page you want to get status on
+ * @status:new status to assign
+ */
+void nand_page_set_status(struct mtd_info *mtd, int page,
+ enum nand_page_status status)
+{
+ struct nand_chip *chip = mtd-priv;
+ u8 shift;
+ uint64_t offset;
+
+ if (!chip-pst)
+ return;
+
+ shift = (page % 4) * 2;
+ offset = page / 4;
+ chip-pst[offset] = ~(0x3 shift);
+ chip-pst[offset] |= (status 0x3) shift;
+}
+EXPORT_SYMBOL(nand_page_set_status);
+
+/**
+ * nand_pst_create - create a page status table
+ * @mtd: mtd info
+ *
+ * Allocate a page status table and assign it to the mtd device.
+ *
+ * Returns 0 in case of success or -ERRNO in case of error.
+ */
+int nand_pst_create(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd-priv;
+
+ if (chip-pst)
+ return 0;
+
+ chip-pst = kzalloc(mtd-size
+ (chip-page_shift + mtd-subpage_sft + 2),
+ GFP_KERNEL);
+ if (!chip-pst)
+ return -ENOMEM;
+
+ return 0;
+}
+EXPORT_SYMBOL(nand_pst_create);
+
+/**
* nand_read_page_raw - [INTERN] read raw page data without ecc
* @mtd: mtd info structure
* @chip: nand chip info structure
@@ -2521,6 +2653,7 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t
to,
int bytes = mtd-writesize;
int cached = writelen bytes page != blockmask;
uint8_t *wbuf = buf;
+ int subpage;
WATCHDOG_RESET();
/* Partial page write? */
@@ -2547,6 +2680,14 @@ static int nand_do_write_ops(struct mtd_info *mtd,
loff_t to,
if (ret)
break
[U-Boot] [RFC 05/11] mtd/nand: take nand_ecc_ctrl initialization out of nand_scan_tail
From: yassin yassinjaf...@gmail.com
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
drivers/mtd/nand/nand_base.c | 101 ++-
1 file changed, 61 insertions(+), 40 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 1c514a0..83586cc 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -4114,47 +4114,15 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips,
}
EXPORT_SYMBOL(nand_scan_ident);
-
-/**
- * nand_scan_tail - [NAND Interface] Scan for the NAND device
- * @mtd: MTD device structure
- *
- * This is the second phase of the normal nand_scan() function. It fills out
- * all the uninitialized function pointers with the defaults and scans for a
- * bad block table if appropriate.
+/*
+ * Initialize ECC struct:
+ * - fill ECC struct with default function/values when these ones are
undefined
+ * - fill ECC infos based on MTD device
*/
-int nand_scan_tail(struct mtd_info *mtd)
+static int nand_ecc_ctrl_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc)
{
int i;
- struct nand_chip *chip = mtd-priv;
- struct nand_ecc_ctrl *ecc = chip-ecc;
- struct nand_buffers *nbuf;
- /* New bad blocks should be marked in OOB, flash-based BBT, or both */
- BUG_ON((chip-bbt_options NAND_BBT_NO_OOB_BBM)
- !(chip-bbt_options NAND_BBT_USE_FLASH));
-
- if (!(chip-options NAND_OWN_BUFFERS)) {
-#ifndef __UBOOT__
- nbuf = kzalloc(sizeof(*nbuf) + mtd-writesize
- + mtd-oobsize * 3, GFP_KERNEL);
- if (!nbuf)
- return -ENOMEM;
- nbuf-ecccalc = (uint8_t *)(nbuf + 1);
- nbuf-ecccode = nbuf-ecccalc + mtd-oobsize;
- nbuf-databuf = nbuf-ecccode + mtd-oobsize;
-#else
- nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
-#endif
-
- chip-buffers = nbuf;
- } else {
- if (!chip-buffers)
- return -ENOMEM;
- }
-
- /* Set the internal oob buffer location, just after the page data */
- chip-oob_poi = chip-buffers-databuf + mtd-writesize;
/*
* If no default placement scheme is given, select an appropriate one.
@@ -4180,9 +4148,6 @@ int nand_scan_tail(struct mtd_info *mtd)
}
}
- if (!chip-write_page)
- chip-write_page = nand_write_page;
-
/*
* Check ECC mode, default to software if 3byte/512byte hardware ECC is
* selected and we have 256 byte pagesize fallback to software ECC
@@ -4349,6 +4314,62 @@ int nand_scan_tail(struct mtd_info *mtd)
}
ecc-total = ecc-steps * ecc-bytes;
+ return 0;
+}
+
+/**
+ * nand_scan_tail - [NAND Interface] Scan for the NAND device
+ * @mtd: MTD device structure
+ *
+ * This is the second phase of the normal nand_scan() function. It fills out
+ * all the uninitialized function pointers with the defaults and scans for a
+ * bad block table if appropriate.
+ */
+int nand_scan_tail(struct mtd_info *mtd)
+{
+ int ret;
+ struct nand_chip *chip = mtd-priv;
+ struct nand_ecc_ctrl *ecc = chip-ecc;
+ struct nand_buffers *nbuf;
+
+ /* New bad blocks should be marked in OOB, flash-based BBT, or both */
+ BUG_ON((chip-bbt_options NAND_BBT_NO_OOB_BBM)
+ !(chip-bbt_options NAND_BBT_USE_FLASH));
+
+ if (!(chip-options NAND_OWN_BUFFERS)) {
+#ifndef __UBOOT__
+ nbuf = kzalloc(sizeof(*nbuf) + mtd-writesize
+ + mtd-oobsize * 3, GFP_KERNEL);
+ if (!nbuf)
+ return -ENOMEM;
+ nbuf-ecccalc = (uint8_t *)(nbuf + 1);
+ nbuf-ecccode = nbuf-ecccalc + mtd-oobsize;
+ nbuf-databuf = nbuf-ecccode + mtd-oobsize;
+#else
+ nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
+#endif
+
+ chip-buffers = nbuf;
+ } else {
+ if (!chip-buffers)
+ return -ENOMEM;
+ }
+
+ /* Set the internal oob buffer location, just after the page data */
+ chip-oob_poi = chip-buffers-databuf + mtd-writesize;
+
+ if (!chip-write_page)
+ chip-write_page = nand_write_page;
+
+ /* Initialize ECC struct */
+ ret = nand_ecc_ctrl_init(mtd, ecc);
+ if (ret) {
+ if (!(chip-options NAND_OWN_BUFFERS))
+ kfree(chip-buffers);
+
+ return ret;
+ }
+
/* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
if (!(chip-options NAND_NO_SUBPAGE_WRITE) nand_is_slc(chip)) {
switch (ecc-steps) {
--
2.4.2
--
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[U-Boot] [RFC 06/11] mtd/nand: Add randomisation layer
Based on BBrezillons work, minus per-partition support. Changes to support
that would be quite invasive while it hasn't been solved yet for Linux.
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
drivers/mtd/nand/nand_base.c | 255 ++-
include/linux/mtd/nand.h | 96
2 files changed, 299 insertions(+), 52 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 83586cc..5196c0c 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1185,6 +1185,62 @@ EXPORT_SYMBOL(nand_lock);
#endif
/**
+ * nand_rnd_is_activ - check wether a region of a NAND page requires NAND
+ *randomizer to be disabled
+ * @mtd: mtd info
+ * @page: NAND page
+ * @column:offset within the page
+ * @len: len of the region
+ *
+ * Returns 1 if the randomizer should be enabled, 0 if not, or -ERR in case of
+ * error.
+ *
+ * In case of success len will contain the size of the region:
+ * - if the requested region fits in a NAND random region len will not change
+ * - else len will be replaced by the available length within the NAND random
+ *region
+ */
+int nand_rnd_is_activ(struct mtd_info *mtd, int page, int column, int *len)
+{
+ struct nand_chip *chip = mtd-priv;
+ struct nand_rnd_layout *layout = chip-rnd.layout;
+ struct nand_rndfree *range;
+ int ret = 1;
+ int tmp;
+ int i;
+
+ if (!len || *len 0 || column 0 ||
+ column + *len mtd-writesize + mtd-oobsize)
+ return -EINVAL;
+
+ if (layout) {
+ for (i = 0; i layout-nranges; i++) {
+ range = layout-ranges[i];
+ if (column + *len = range-offset) {
+ break;
+ } else if (column = range-offset + range-length) {
+ continue;
+ } else if (column range-offset) {
+ tmp = range-offset - column;
+ if (*len tmp)
+ *len = tmp;
+ break;
+ } else {
+ tmp = range-offset + range-length - column;
+ if (*len tmp)
+ *len = tmp;
+ ret = 0;
+ break;
+ }
+
+ }
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL(nand_rnd_is_activ);
+
+/**
* nand_page_is_empty - check wether a NAND page contains only FFs
* @mtd: mtd info
* @data: data buffer
@@ -1329,9 +1385,13 @@ EXPORT_SYMBOL(nand_pst_create);
static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
uint8_t *buf, int oob_required, int page)
{
- chip-read_buf(mtd, buf, mtd-writesize);
- if (oob_required)
- chip-read_buf(mtd, chip-oob_poi, mtd-oobsize);
+ nand_rnd_config(mtd, page, 0, NAND_RND_READ);
+ nand_rnd_read_buf(mtd, buf, mtd-writesize);
+ if (oob_required){
+ nand_rnd_config(mtd, page, mtd-writesize, NAND_RND_READ);
+ nand_rnd_read_buf(mtd, chip-oob_poi, mtd-oobsize);
+ }
+ nand_rnd_config(mtd, -1, -1, NAND_RND_READ);
return 0;
}
@@ -1352,29 +1412,40 @@ static int nand_read_page_raw_syndrome(struct mtd_info
*mtd,
int eccsize = chip-ecc.size;
int eccbytes = chip-ecc.bytes;
uint8_t *oob = chip-oob_poi;
- int steps, size;
+ int steps, size, column = 0;
for (steps = chip-ecc.steps; steps 0; steps--) {
- chip-read_buf(mtd, buf, eccsize);
+ nand_rnd_config(mtd, page, column, NAND_RND_READ);
+ nand_rnd_read_buf(mtd, buf, eccsize);
buf += eccsize;
+ column += eccsize;
if (chip-ecc.prepad) {
- chip-read_buf(mtd, oob, chip-ecc.prepad);
+ nand_rnd_config(mtd, page, column, NAND_RND_READ);
+ nand_rnd_read_buf(mtd, oob, chip-ecc.prepad);
oob += chip-ecc.prepad;
+ column += chip-ecc.prepad;
}
- chip-read_buf(mtd, oob, eccbytes);
+ nand_rnd_config(mtd, page, column, NAND_RND_READ);
+ nand_rnd_read_buf(mtd, oob, eccbytes);
oob += eccbytes;
+ column += eccbytes;
if (chip-ecc.postpad) {
- chip-read_buf(mtd, oob, chip-ecc.postpad);
+ nand_rnd_config(mtd, page, column, NAND_RND_READ);
+ nand_rnd_read_buf(mtd, oob, chip-ecc.postpad);
oob += chip-ecc.postpad;
+ column += chip-ecc.postpad
[U-Boot] [RFC 09/11] sunxi/nand: Enable UBI and NAND commands
Signed-off-by: Roy Spliet r.spl...@ultimaker.com --- board/sunxi/Kconfig| 8 +++- drivers/mtd/Makefile | 1 + include/configs/sunxi-common.h | 33 + 3 files changed, 29 insertions(+), 13 deletions(-) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index cf58d73..37bbd0f 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -269,17 +269,15 @@ config MMC_SUNXI_SLOT_EXTRA slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable support for this. -config SPL_NAND_SUPPORT - bool SPL/NAND mode support +config NAND_SUNXI + bool NAND support depends on SPL default n ---help--- This enables support for booting from NAND internal memory. U-Boot SPL doesn't detect where is it load from, therefore this option is needed to properly load image from - flash. Option also disables MMC functionality on U-Boot due to - initialization errors encountered, when both controllers are - enabled. + flash. config USB0_VBUS_PIN string Vbus enable pin for usb0 (otg) diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 5467a95..124b0f9 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -18,3 +18,4 @@ obj-$(CONFIG_FTSMC020) += ftsmc020.o obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o obj-$(CONFIG_ST_SMI) += st_smi.o +obj-$(CONFIG_MTD_UBI) += ubi/ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index cce0441..ec28c40 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -113,7 +113,7 @@ #endif /* 4MB of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 20)) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 20)) /* * Miscellaneous configurable options @@ -326,10 +326,31 @@ extern int soft_i2c_gpio_scl; #define CONFIG_ENV_IS_NOWHERE #endif -#ifdef CONFIG_SPL_NAND_SUPPORT +#ifdef CONFIG_NAND_SUNXI +#ifndef CONFIG_NAND_SUNXI_GPC_PORTS +#error No NAND GPC ports defined, NAND unsupported +#endif /* CONFIG_NAND_SUNXI_GPC_PORTS */ #define CONFIG_NAND #define CONFIG_SYS_NAND_SELF_INIT -#define CONFIG_NAND_SUNXI +#define CONFIG_SYS_MAX_NAND_DEVICE 8 + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* Requirements for UBI */ +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_MTD_DEVICE + +#define CONFIG_SPL_NAND_SUPPORT + +#define CONFIG_MTD_PARTITIONS +/* +#define CONFIG_MTD_DEBUG +#define CONFIG_MTD_DEBUG_VERBOSE MTD_DEBUG_LEVEL3 +*/ #define CONFIG_CMD_SPL_WRITE_SIZE 0x000400 #define CONFIG_SYS_NAND_U_BOOT_OFFS0x008000 @@ -338,11 +359,7 @@ extern int soft_i2c_gpio_scl; #define CONFIG_NAND_SUNXI_ECC_STEP 1024 #define CONFIG_NAND_SUNXI_ECC_STRENGTH 40 #define CONFIG_NAND_SUNXI_ADDR_CYCLES 5 - -#ifndef CONFIG_NAND_SUNXI_GPC_PORTS -#error No NAND GPC ports defined, NAND unsupported -#endif -#endif /* CONFIG_SPL_NAND_SUPPORT */ +#endif /* CONFIG_NAND_SUNXI */ #define CONFIG_MISC_INIT_R #define CONFIG_SYS_CONSOLE_IS_IN_ENV -- 2.4.2 -- IMAGINE IT MAKE IT Meet us online at Twitter http://twitter.com/ultimaker, Facebook http://facebook.com/ultimaker, Google+ http://google.com/+Ultimaker www.ultimaker.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC 08/11] mtd/nand: Add DT definitions for Olimex Lime
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
arch/arm/dts/sun7i-a20-olinuxino-lime.dts | 41 ++
arch/arm/dts/sun7i-a20.dtsi | 90 +++
2 files changed, 131 insertions(+)
diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
index 6592cb2..cc5e65d 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
@@ -181,3 +181,44 @@
usb2_vbus-supply = reg_usb2_vbus;
status = okay;
};
+
+nfc {
+ pinctrl-names = default;
+ pinctrl-0 = nand_pins_a nand_cs0_pins_a nand_rb0_pins_a;
+ status = okay;
+
+ nand@0 {
+ #address-cells = 2;
+ #size-cells = 2;
+ reg = 0;
+ allwinner,rb = 0;
+ nand-ecc-mode = hw;
+ nand-ecc-strength = 40;
+ nand-ecc-step-size = 1024;
+ nand-rnd-mode = hw;
+ nand-randomizer-seeds = /bits/ 16
+ 0x2b75 0x0bd0 0x5ca3 0x62d1 0x1c93 0x07e9 0x2162 0x3a72
+ 0x0d67 0x67f9 0x1be7 0x077d 0x032f 0x0dac 0x2716 0x2436
+ 0x7922 0x1510 0x3860 0x5287 0x480f 0x4252 0x1789 0x5a2d
+ 0x2a49 0x5e10 0x437f 0x4b4e 0x2f45 0x216e 0x5cb7 0x7130
+ 0x2a3f 0x60e4 0x4dc9 0x0ef0 0x0f52 0x1bb9 0x6211 0x7a56
+ 0x226d 0x4ea7 0x6f36 0x3692 0x38bf 0x0c62 0x05eb 0x4c55
+ 0x60f4 0x728c 0x3b6f 0x2037 0x7f69 0x0936 0x651a 0x4ceb
+ 0x6218 0x79f3 0x383f 0x18d9 0x4f05 0x5c82 0x2912 0x6f17
+ 0x6856 0x5938 0x1007 0x61ab 0x3e7f 0x57c2 0x542f 0x4f62
+ 0x7454 0x2eac 0x7739 0x42d4 0x2f90 0x435a 0x2e52 0x2064
+ 0x637c 0x66ad 0x2c90 0x0bad 0x759c 0x0029 0x0986 0x7126
+ 0x1ca7 0x1605 0x386a 0x27f5 0x1380 0x6d75 0x24c3 0x0f8e
+ 0x2b7a 0x1418 0x1fd1 0x7dc1 0x2d8e 0x43af 0x2267 0x7da3
+ 0x4e3d 0x1338 0x50db 0x454d 0x764d 0x40a3 0x42e6 0x262b
+ 0x2d2e 0x1aea 0x2e17 0x173d 0x3a6e 0x71bf 0x25f9 0x0a5d
+ 0x7c57 0x0fbe 0x46ce 0x4939 0x6b17 0x37bb 0x3e91
0x76db;
+ onfi,nand-timing-mode = 0x1f;
+/*
+ main@40 {
+ label = main;
+ reg = /bits/ 64 0x40 0xffc0;
+ };
+*/
+ };
+};
diff --git a/arch/arm/dts/sun7i-a20.dtsi b/arch/arm/dts/sun7i-a20.dtsi
index d4ba772..af89575 100644
--- a/arch/arm/dts/sun7i-a20.dtsi
+++ b/arch/arm/dts/sun7i-a20.dtsi
@@ -612,6 +612,17 @@
clocks = ahb_gates 17;
status = disabled;
};
+
+ nfc: nand@01c03000 {
+ compatible = allwinner,sun4i-nand;
+ reg = 0x01c03000 0x1000;
+ interrupts = 0 37 4;
+ clocks = ahb_gates 13, nand_clk;
+ clock-names = ahb, mod;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ };
mdio: mdio@01c0b080 {
compatible = allwinner,sun4i-a10-mdio;
@@ -1020,6 +1031,85 @@
allwinner,drive = SUN4I_PINCTRL_10_MA;
allwinner,pull = SUN4I_PINCTRL_NO_PULL;
};
+ nand_pins_a: nand_base0@0 {
+ allwinner,pins = PC0, PC1, PC2,
+ PC5, PC8, PC9, PC10,
+ PC11, PC12, PC13, PC14,
+ PC15, PC16;
+ allwinner,function = nand0;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
+
+ nand_cs0_pins_a: nand_cs@0 {
+ allwinner,pins = PC4;
+ allwinner,function = nand0;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
+
+ nand_cs1_pins_a: nand_cs@1 {
+ allwinner,pins = PC3;
+ allwinner,function = nand0;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
+
+ nand_cs2_pins_a: nand_cs@2 {
+ allwinner,pins = PC17;
+ allwinner,function = nand0;
+ allwinner,drive = 0;
+ allwinner,pull = 0
[U-Boot] [RFC 10/11] mtd/nand: Define bootcmd for nand
Assumes a UBI partition called boot
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
include/config_distro_bootcmd.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 3a360ca4..361b914 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -72,6 +72,21 @@
BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC
#endif
+#ifdef CONFIG_CMD_NAND
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+ bootcmd_nand= \
+ ubi part #devtypel #instance _main; \
+ ubifsmount ubi:boot;\
+ run scan_ubifs_for_script\0
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance)#devtypel
+#else
+#define BOOTENV_SHARED_NAND
+#define BOOTENV_DEV_NAND \
+ BOOT_TARGET_DEVICES_references_NAND_without_CONFIG_CMD_NAND
+#define BOOTENV_DEV_NAME_NAND \
+ BOOT_TARGET_DEVICES_references_NAND_without_CONFIG_CMD_NAND
+#endif
+
#ifdef CONFIG_CMD_SATA
#define BOOTENV_SHARED_SATABOOTENV_SHARED_BLKDEV(sata)
#define BOOTENV_DEV_SATA BOOTENV_DEV_BLKDEV
@@ -202,6 +217,17 @@
echo SCRIPT FAILED: continuing...; \
fi\0\
\
+ scan_ubifs_for_script= \
+ for script in ${boot_scripts}; do \
+ for prefix in ${boot_prefixes}; do \
+ if ubifsload ${scriptaddr} \
+ ${prefix}${script}; then\
+ echo Found U-Boot script\
+ ${prefix}${script}; \
+ source ${scriptaddr}; \
+ fi; \
+ done; \
+ done\0 \
boot_a_script= \
load ${devtype} ${devnum}:${bootpart} \
${scriptaddr} ${prefix}${script}; \
--
2.4.2
--
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Re: [U-Boot] [PATCH 2/2] nand: sunxi: Add support for booting from internal NAND memory
Dear Scott,
Thank you for taking your time to feedback. However, it seems to be
about a week and two versions of the patchset too late. Most of your
issues have been addressed in the meanwhile, as you can see in Hans de
Goede's sunxi branch.
Yours,
Roy
Op 02-06-15 om 00:14 schreef Scott Wood:
On Thu, 2015-05-21 at 15:59 +0200, Roy Spliet wrote:
+#ifdef CONFIG_NAND_SUNXI
+#include nand.h
+#endif
Why do you need the ifdef?
+#include common.h
+#include config.h
+#include asm/io.h
+#include nand.h
+
+/* DMAC */
+#define DMAC_BASE0x01c02000
+#define DMAC_REG(a) (DMAC_BASE + a)
+
+#define DMAC_INT DMAC_REG(0x000)
+#define DMAC_DDMA_CFGDMAC_REG(0x300)
+#define DMAC_DDMA_SRCDMAC_REG(0x304)
+#define DMAC_DDMA_DSTDMAC_REG(0x308)
+#define DMAC_DDMA_BYTE_COUNT DMAC_REG(0x30C)
+#define DMAC_DDMA_PARAM DMAC_REG(0x318)
+
+/* NAND controller */
+#define NANDFLASHC_BASE 0x01c03000
+#define NREG(a) (0x01c03000 + a)
+
+#define NANDFLASHC_CTL NREG(0x00)
+#define NANDFLASHC_CTL_EN0x0001
+#define NANDFLASHC_CTL_RST 0x0002
+#define NANDFLASHC_CTL_RAM_METHOD0x4000
+
+#define NANDFLASHC_STNREG(0x004)
+#define NANDFLASHC_INT NREG(0x008)
+#define NANDFLASHC_TIMING_CTLNREG(0x00C)
+#define NANDFLASHC_TIMING_CFGNREG(0x010)
+#define NANDFLASHC_ADDR_LOW NREG(0x014)
+#define NANDFLASHC_ADDR_HIGH NREG(0x018)
+#define NANDFLASHC_SECTOR_NUMNREG(0x01C)
+#define NANDFLASHC_CNT NREG(0x020)
+
+#define NANDFLASHC_CMD NREG(0x024)
+#define NANDFLASHC_SEND_CMD1 (1 22)
+#define NANDFLASHC_WAIT_FLAG (1 23)
+
+#define NANDFLASHC_RCMD_SET NREG(0x028)
+#define NANDFLASHC_WCMD_SET NREG(0x02C)
+#define NANDFLASHC_IO_DATA NREG(0x030)
+#define NANDFLASHC_ECC_CTL NREG(0x034)
+#define NANDFLASHC_ECC_STNREG(0x038)
+#define NANDFLASHC_DEBUG NREG(0x03c)
+#define NANDFLASHC_ECC_CNT0 NREG(0x040)
+#define NANDFLASHC_ECC_CNT1 NREG(0x044)
+#define NANDFLASHC_ECC_CNT2 NREG(0x048)
+#define NANDFLASHC_ECC_CNT3 NREG(0x04c)
+#define NANDFLASHC_USER_DATA_BASENREG(0x050)
+#define NANDFLASHC_EFNAND_STATUS NREG(0x090)
+#define NANDFLASHC_SPARE_AREANREG(0x0A0)
+#define NANDFLASHC_PATTERN_IDNREG(0x0A4)
+#define NANDFLASHC_RAM0_BASE NREG(0x400)
+#define NANDFLASHC_RAM1_BASE NREG(0x800)
Shouldn't these be in a header file so they can be shared with a non-
SPL driver?
+void
+nand_init(void)
+{
Don't put a newline after the return type.
+ uint32_t val;
+
+ board_nand_init();
+ val = readl(NANDFLASHC_CTL);
+ val |= NANDFLASHC_CTL_RST;
+ writel(val, NANDFLASHC_CTL);
+
+ /* Wait until reset pin is deasserted */
+ do {
+ val = readl(NANDFLASHC_CTL);
+ if (!(val NANDFLASHC_CTL_RST))
+ break;
+ } while (1);
Add a timeout to delay loops.
+
+ /** \todo Chip select, currently kind of static */
+ val = readl(NANDFLASHC_CTL);
+ val = 0xf0fff0f2;
Don't put magic numbers in the code -- use symbolic constants taht
describe what the fields mean.
+/* random seed */
+static const uint16_t random_seed[128] = {
+ 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
+ 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
+ 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
+ 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
+ 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
+ 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
+ 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
+ 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
+ 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
+ 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
+ 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
+ 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
+ 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
+ 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
+ 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
+ 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
+};
Why is randomness needed?
+uint32_t ecc_errors = 0;
Why is this global?
+int
+nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
+{
+ dma_addr_t dst_block;
+ dma_addr_t dst_end;
+ phys_addr_t addr = offs;
+
+ dst_end = ((dma_addr_t) dest) + size
Re: [U-Boot] [PATCH] sunxi/spl: Detect at runtime where SPL was read from
Hey Daniel,
The approach seems good. Some comments inline
2015-05-28 10:43 GMT+02:00 Daniel Kochmański
dkochman...@turtle-solutions.eu:
This patch makes possible using single `u-boot-sunxi-with-spl.bin` binary
for both NAND memory and SD card. Detection where SPL was read from is
implemented in `spl_boot_device`.
Detection is performed only if `CONFIG_SPL_NAND_SUPPORT` is defined. Unless
SD card contains valid signature we assume, that SPL was read from NAND.
Signed-off-by: Daniel Kochmański dkochman...@turtle-solutions.eu
CC: Roy Spliet r.spl...@ultimaker.com
Cc: Ian Campbell i...@hellion.org.uk
Cc: Hans De Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/board.c | 53
++--
include/configs/sunxi-common.h | 2 --
2 files changed, 35 insertions(+), 20 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c
b/arch/arm/cpu/armv7/sunxi/board.c
index 70f413f..5e441ba 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -11,6 +11,7 @@
*/
#include common.h
+#include mmc.h
#include i2c.h
#include serial.h
#ifdef CONFIG_SPL_BUILD
@@ -109,12 +110,10 @@ void s_init(void)
}
#ifdef CONFIG_SPL_BUILD
+DECLARE_GLOBAL_DATA_PTR;
+
/* The sunxi internal brom will try to loader external bootloader
* from mmc0, nand flash, mmc2.
- *
- * Unfortunately we can't check how SPL was loaded so assume it's
- * always the first SD/MMC controller, unless it was explicitly
- * stated that SPL is on nand flash.
*/
u32 spl_boot_device(void)
{
@@ -124,17 +123,13 @@ u32 spl_boot_device(void)
* enabled build. It has many restrictions and can only boot over
USB.
*/
return BOOT_DEVICE_BOARD;
-#elif defined(CONFIG_SPL_NAND_SUPPORT)
- /*
-* This is compile time configuration informing SPL, that it
-* was loaded from nand flash.
-*/
- return BOOT_DEVICE_NAND;
#else
+ __maybe_unused struct mmc *mmc0;
+ __maybe_unused char buf[512];
Maybe_unused? Either reserve it or don't. If you only need them for
CONFIG_SPL_NAND_SUPPORT, then ifdef around it. Also, why are you
reserving half a K if you are only going to use 12 bytes? And if you need
to round up, can't you just malloc it from SDRAM instead of reserving this
space in SRAM like this?
/*
-* When booting from the SD card, the eGON.BT0 signature is
expected
-* to be found in memory at the address 0x0004 (see the
mksunxiboot
-* tool, which generates this header).
+* When booting from the SD card or NAND memory, the eGON.BT0
+* signature is expected to be found in memory at the address
0x0004
+* (see the mksunxiboot tool, which generates this header).
*
* When booting in the FEL mode over USB, this signature is
patched in
* memory and replaced with something else by the 'fel' tool. This
other
@@ -142,13 +137,35 @@ u32 spl_boot_device(void)
* valid bootable SD card image (because the BROM would refuse to
* execute the SPL in this case).
*
-* This branch is just making a decision at runtime whether to load
-* the main u-boot binary from the SD card (if the eGON.BT0
signature
-* is found) or return to the FEL code in the BROM to wait and
receive
-* the main u-boot binary over USB.
+* This branch is just making a decision at runtime whether to
load the
+* main u-boot binary from the SD card or NAND memory (if the
eGON.BT0
+* signature is found) or return to the FEL code in the BROM to
wait and
+* receive the main u-boot binary over USB. If signature is
present,
+* decision where to boot from (SD card or NAND memory) depends on
+* compile options (if SPL_NAND_SUPPORT isn't defined, we assume
we boot
+* from SD card), and runtime check - if SD card doesn't contain
valid
+* signature we assume that SPL was loaded from NAND.
*/
- if (readl(4) == 0x4E4F4765 readl(8) == 0x3054422E) /* eGON.BT0
*/
+ if (readl(4) == 0x4E4F4765 readl(8) == 0x3054422E) { /*
eGON.BT0 */
+#if !defined(
CONFIG_SPL_NAND_SUPPORT)
return BOOT_DEVICE_MMC1;
+#else
+ mmc_initialize(gd-bd);
+
mmc0 = find_mmc_device(0);
Is this not supposed to be mmc0 =
find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
? I'm not entirely sure, Hans, how should this constant be interpreted?
+ /*
+* Figure out where we're booting from. Try mmc0 first,
just
+* like the brom does. If it doesn't contain valid
signature,
+* assume SPL was loaded from NAND memory.
+*/
+ if (mmc0 mmc_getcd(mmc0) mmc_init(mmc0) == 0
+ mmc0-block_dev.block_read(0, 16, 1, buf) == 1) {
+ buf[12
Re: [U-Boot] Proposal to add NAND-boot support for Sunxi SPL
Hello Hans, Re-sent to everybody instead of just you. Reply inline. Op 25-05-15 om 22:39 schreef Hans de Goede: Hi, On 25-05-15 20:35, Hans de Goede wrote: Hi, On 22-05-15 09:04, Roy Spliet wrote: Hello, For my set-up I made use of Boris Brezillon's sunxi-nand tree[1], or actually I rebased his patches on top of 4.0rc7. This basically adds support for NAND-chip partitioning, ECC and randomisation. Docs for the DT specification in Documentation/devicetree/bindings/mtd/sunxi-nand.txt , and an example can be found in arch/arm/boot/dts/sun7i-a20-cubietruck.dts . [2] lists the acceptable configuration options for the boot and boot_rescue partitions, make sure to pick one of these (which should be no problem for MLC-type nand). The ECC mode for these boot partitions is called hw_syndrome. Assuming you now have a Linux set-up kernel based on this tree with NAND support on an MMC, for U-boot what you should currently do is: 1) in include/configs/sunxi-common.h, adjust the parameters CONFIG_NAND_SUNXI_PAGE_SIZE, ECC_STEP, ECC_STRENGTH to match your NAND chip and DT configuration. 2) Build 3) Use your MMC to flash u-boot-sunxi-with-spl.bin onto NAND: # flash_erase /dev/mtd0 # nandwrite -p /dev/mtd0 u-boot-sunxi-with-spl.bin 4) Reboot without the MMC card and see U-boot load Ok, it took me way longer then I wanted (see below) but I've this working now. It is cool to see u-boot load from nand :) That should be all. @Alex: To answer your question specifically: It's likely that the parameters in sunxi-common.h mentioned above might not match your NAND-chip configuration in the Linux kernel. I can't tell you precisely how to fetch these details from the 3.4 kernel, sorry. I recall Daniel using 24-bit strength ECC with otherwise equal parameters, but perhaps he can help you with this better than I can. Alex, could it be that you are writing the nand using a (rebased) version of bbrezillon's sunxi-nand-next branch ? I started with that too because it is much newer and contains various bug fixes, but it seems that it also contains a new bug causing it to write the NAND in such a way that the BROM and u-boot SPL code will not read it. I've just pushed a rebased version of the sunxi-nand branch of Boris here: https://github.com/jwrdegoede/linux-sunxi/commits/sunxi-nand-experiment And that works for me, where as before I got the exact same errors trying to fel load a nand enabled spl. I'm working on merging over all the changes from the sunxi-nand-next branch onto my working sunxi-nand-experiment branch 1 by 1 until I find the one which causes the breakage... Ok, so quick update the breakage was caused by this commit: https://github.com/bbrezillon/linux-sunxi/commit/7f7324bc6170a45742352070fb45170779a3611c When it was rebased someone (Boris I guess) forgot to remove the chip-read_buf(mtd, NULL, ecc-size); line at line 1075 (after the patch) and likewise the chip-write_buf(mtd, buf + (i * ecc-size), ecc-size); line at line 1161. With these 2 lines removed the sunxi-nand-next branch from Boris, rebased on 4.1-rc1 can write the nand boot parts and the brom / spl can load the spl / resp. u-boot.bin from there (on a cubieboard2). You're right... I did spot this, but assumed this was my own mistake in merging these patches with our 4.0RC7 tree. Sorry, could have saved you some trouble if I were sharper. I've also tried to get this code running on a cubieboard (non 2 so A10 rather then A20), the SPL loads fine there (indicating that the kernel bits work), but then I get: U-Boot SPL 2015.07-rc1-00287-g050de86-dirty (May 25 2015 - 22:28:19) DRAM: 1024 MiB CPU: 100800Hz, AXI/AHB/APB: 3/2/2 Nand initialised NAND timeout reading data NAND timeout reading data NAND timeout reading data NAND timeout reading data NAND timeout reading data NAND timeout reading data ... Thanks for testing this. I don't own an A10 myself, so I haven't observed this behaviour. First thing I would verify personally is whether all the clocks are properly configured. Could you make U-boot print ccm-ahb_gate0 and ccm-nand0_clk_cfg? For the first, bits 6 (DMA) and 13 (NAND) must be set, the second must have bit 31 set, bits 24 and 25 cleared (and otherwise, the accompanying PLL must be configured too... probably easier to use the OSC24M), and the divide ratios set to 0 (although a small divider, like 1, shouldn't be a problem either). I am assuming these values should be correct, but only because BROM initialised part of it. I am aware of the fact that the SPL driver doesn't control the DMA gating reg and the NAND post-dividers. It might be a good idea to do so for as long as we don't have a full DMA driver, so I'll patch that up today. Roy Which seems to indicate a problem with the SPL nand code on the A10. I'll investigate this further tomorrow evening. A cleaned up version of my kernel work on this is available in my sunxi-wip branch. Regards, Hans -- IMAGINE IT MAKE
[U-Boot] [PATCH V4 1/4] sunxi/nand: change BLOCK_SIZE in mksunxiboot to match NAND block size
From: Daniel Kochmański dkochman...@turtle-solutions.eu
This change is necessary to calculate correct checksum for NAND
boot. Works both for MMC and NAND. Without it BROM rejects boot image
as invalid (bad checksum). (Changes block size from 0x200 to 0x2000).
V2: Document decision in source too
Signed-off-by: Daniel Kochmański dkochman...@turtle-solutions.eu
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
Cc: Ian Campbell i...@hellion.org.uk
Cc: Hans De Goede hdego...@redhat.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
tools/mksunxiboot.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c
index 0035f6e..3361251 100644
--- a/tools/mksunxiboot.c
+++ b/tools/mksunxiboot.c
@@ -65,7 +65,13 @@ int gen_check_sum(struct boot_file_head *head_p)
#define SUN4I_SRAM_SIZE 0x7600 /* 0x7748+ is used by BROM */
#define SRAM_LOAD_MAX_SIZE (SUN4I_SRAM_SIZE - sizeof(struct boot_file_head))
-#define BLOCK_SIZE 512
+
+/*
+ * BROM (at least on A10 and A20) requires NAND-images to be explicitly aligned
+ * to a multiple of 8K, and rejects the image otherwise. MMC-images are fine
+ * with 512B blocks. To cater for both, align to the largest of the two.
+ */
+#define BLOCK_SIZE 0x2000
struct boot_img {
struct boot_file_head header;
--
2.1.0
--
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[U-Boot] [PATCH V4 2/4] sunxi: Add DMA definitions
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
arch/arm/include/asm/arch-sunxi/dma.h | 16 +++
arch/arm/include/asm/arch-sunxi/dma_sun4i.h | 68 +
2 files changed, 84 insertions(+)
create mode 100644 arch/arm/include/asm/arch-sunxi/dma.h
create mode 100644 arch/arm/include/asm/arch-sunxi/dma_sun4i.h
diff --git a/arch/arm/include/asm/arch-sunxi/dma.h
b/arch/arm/include/asm/arch-sunxi/dma.h
new file mode 100644
index 000..e288f36
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dma.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2015 Roy Spliet rspl...@ultimaker.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_DMA_H
+#define _SUNXI_DMA_H
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+#include asm/arch/dma_sun4i.h
+#else
+#error DMA definition not available for this architecture
+#endif
+
+#endif /* _SUNXI_DMA_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dma_sun4i.h
b/arch/arm/include/asm/arch-sunxi/dma_sun4i.h
new file mode 100644
index 000..778a04b
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dma_sun4i.h
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2015 Roy Spliet rspl...@ultimaker.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_DMA_SUN4I_H
+#define _SUNXI_DMA_SUN4I_H
+
+struct sunxi_dma_cfg
+{
+ u32 ctl;/* 0x00 Control */
+ u32 src_addr; /* 0x04 Source address */
+ u32 dst_addr; /* 0x08 Destination address */
+ u32 bc; /* 0x0C Byte counter */
+ u32 res0[2];
+ u32 ddma_para; /* 0x18 extra parameter (dedicated DMA only) */
+ u32 res1;
+};
+
+struct sunxi_dma
+{
+ u32 irq_en; /* 0x000 IRQ enable */
+ u32 irq_pend; /* 0x004 IRQ pending */
+ u32 auto_gate; /* 0x008 auto gating */
+ u32 res0[61];
+ struct sunxi_dma_cfg ndma[8]; /* 0x100 Normal DMA */
+ u32 res1[64];
+ struct sunxi_dma_cfg ddma[8]; /* 0x300 Dedicated DMA */
+};
+
+enum ddma_drq_type {
+ DDMA_DST_DRQ_SRAM = 0,
+ DDMA_SRC_DRQ_SRAM = 0,
+ DDMA_DST_DRQ_SDRAM = 1,
+ DDMA_SRC_DRQ_SDRAM = 1,
+ DDMA_DST_DRQ_PATA = 2,
+ DDMA_SRC_DRQ_PATA = 2,
+ DDMA_DST_DRQ_NAND = 3,
+ DDMA_SRC_DRQ_NAND = 3,
+ DDMA_DST_DRQ_USB0 = 4,
+ DDMA_SRC_DRQ_USB0 = 4,
+ DDMA_DST_DRQ_ETHERNET_MAC_TX = 6,
+ DDMA_SRC_DRQ_ETHERNET_MAC_RX = 7,
+ DDMA_DST_DRQ_SPI1_TX = 8,
+ DDMA_SRC_DRQ_SPI1_RX = 9,
+ DDMA_DST_DRQ_SECURITY_SYS_TX = 10,
+ DDMA_SRC_DRQ_SECURITY_SYS_RX = 11,
+ DDMA_DST_DRQ_TCON0 = 14,
+ DDMA_DST_DRQ_TCON1 = 15,
+ DDMA_DST_DRQ_MSC = 23,
+ DDMA_SRC_DRQ_MSC = 23,
+ DDMA_DST_DRQ_SPI0_TX = 26,
+ DDMA_SRC_DRQ_SPI0_RX = 27,
+ DDMA_DST_DRQ_SPI2_TX = 28,
+ DDMA_SRC_DRQ_SPI2_RX = 29,
+ DDMA_DST_DRQ_SPI3_TX = 30,
+ DDMA_SRC_DRQ_SPI3_RX = 31,
+};
+
+#define SUNXI_DMA_CTL_SRC_DRQ(a) ((a) 0x1f)
+#define SUNXI_DMA_CTL_MODE_IO (1 5)
+#define SUNXI_DMA_CTL_SRC_DATA_WIDTH_32(2 9)
+#define SUNXI_DMA_CTL_DST_DRQ(a) (((a) 0x1f) 16)
+#define SUNXI_DMA_CTL_DST_DATA_WIDTH_32(2 25)
+#define SUNXI_DMA_CTL_TRIGGER (1 31)
+
+#endif /* _SUNXI_DMA_SUN4I_H */
--
2.1.0
--
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[U-Boot] [PATCH V4 4/4] sunxi/nand: Add support for booting from internal NAND memory
From: Daniel Kochmański dkochman...@turtle-solutions.eu
V2:
- Rename config option
- Move to separate driver
- fix DMA directly into RAM
- Many readability upgrades
- Drop R32 and W32 macros in favour of readl/writel respectively
- Use standard port controller methods for pinctl
- Make many NAND options semi-configurable
V3:
- Use proper structs and definitions for DMA and NAND
- Fix bug wrt. page size selection
- Add time-out to waits
V4:
- nand_init(): enable DMA
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
arch/arm/cpu/armv7/sunxi/board.c | 12 +-
arch/arm/include/asm/arch-sunxi/gpio.h | 2 +
arch/arm/include/asm/arch-sunxi/nand.h | 67
board/sunxi/Kconfig| 12 ++
board/sunxi/board.c| 16 ++
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/sunxi_nand_spl.c | 273 +
include/configs/sun4i.h| 1 +
include/configs/sun5i.h| 3 +
include/configs/sun7i.h| 2 +
include/configs/sun8i.h| 6 +
include/configs/sunxi-common.h | 20 +++
12 files changed, 413 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/include/asm/arch-sunxi/nand.h
create mode 100644 drivers/mtd/nand/sunxi_nand_spl.c
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 6718ae2..70f413f 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -111,8 +111,10 @@ void s_init(void)
#ifdef CONFIG_SPL_BUILD
/* The sunxi internal brom will try to loader external bootloader
* from mmc0, nand flash, mmc2.
- * Unfortunately we can't check how SPL was loaded so assume
- * it's always the first SD/MMC controller
+ *
+ * Unfortunately we can't check how SPL was loaded so assume it's
+ * always the first SD/MMC controller, unless it was explicitly
+ * stated that SPL is on nand flash.
*/
u32 spl_boot_device(void)
{
@@ -122,6 +124,12 @@ u32 spl_boot_device(void)
* enabled build. It has many restrictions and can only boot over USB.
*/
return BOOT_DEVICE_BOARD;
+#elif defined(CONFIG_SPL_NAND_SUPPORT)
+ /*
+* This is compile time configuration informing SPL, that it
+* was loaded from nand flash.
+*/
+ return BOOT_DEVICE_NAND;
#else
/*
* When booting from the SD card, the eGON.BT0 signature is expected
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 59d8210..2b49616 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -156,6 +156,8 @@ enum sunxi_gpio_number {
#define SUN4I_GPB_UART02
#define SUN5I_GPB_UART02
+#define SUNXI_GPC_NAND 2
+
#define SUNXI_GPC_SDC2 3
#define SUN6I_GPC_SDC3 4
diff --git a/arch/arm/include/asm/arch-sunxi/nand.h
b/arch/arm/include/asm/arch-sunxi/nand.h
new file mode 100644
index 000..22844d8
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/nand.h
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2015 Roy Spliet rspl...@ultimaker.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_NAND_H
+#define _SUNXI_NAND_H
+
+#include linux/types.h
+
+struct sunxi_nand
+{
+ u32 ctl;/* 0x000 Configure and control */
+ u32 st; /* 0x004 Status information */
+ u32 intr; /* 0x008 Interrupt control */
+ u32 timing_ctl; /* 0x00C Timing control */
+ u32 timing_cfg; /* 0x010 Timing configure */
+ u32 addr_low; /* 0x014 Low word address */
+ u32 addr_high; /* 0x018 High word address */
+ u32 block_num; /* 0x01C Data block number */
+ u32 data_cnt; /* 0x020 Data counter for transfer */
+ u32 cmd;/* 0x024 NDFC commands */
+ u32 rcmd_set; /* 0x028 Read command set for vendor NAND mem */
+ u32 wcmd_set; /* 0x02C Write command set */
+ u32 io_data;/* 0x030 IO data */
+ u32 ecc_ctl;/* 0x034 ECC configure and control */
+ u32 ecc_st; /* 0x038 ECC status and operation info */
+ u32 efr;/* 0x03C Enhanced feature */
+ u32 err_cnt0; /* 0x040 Corrected error bit counter 0 */
+ u32 err_cnt1; /* 0x044 Corrected error bit counter 1 */
+ u32 user_data[16]; /* 0x050[16] User data field */
+ u32 efnand_st; /* 0x090 EFNAND status */
+ u32 res0[3];
+ u32 spare_area; /* 0x0A0 Spare area configure */
+ u32 pat_id; /* 0x0A4 Pattern ID register */
+ u32 rdata_sta_ctl; /* 0x0A8 Read data status control */
+ u32 rdata_sta_0;/* 0x0AC Read data status 0 */
+ u32 rdata_sta_1;/* 0x0B0 Read data status 1 */
+ u32 res1[3];
+ u32
[U-Boot] [PATCH V4 3/4] sunxi: Match sun4i, sun6i, sun9i CCI definitions for NAND and DMA
V4:
- Match clock_sun9i too
- Make sure definitions for DMA gate bits are available across boards
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 4 ++--
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 3 +++
arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 6 +-
3 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index c28ee05..e40d368 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -39,7 +39,7 @@ struct sunxi_ccm_reg {
u32 apb0_gate; /* 0x68 apb0 module clock gating */
u32 apb1_gate; /* 0x6c apb1 module clock gating */
u8 res4[0x10];
- u32 nand_sclk_cfg; /* 0x80 nand sub clock control */
+ u32 nand0_clk_cfg; /* 0x80 nand sub clock control */
u32 ms_sclk_cfg;/* 0x84 memory stick sub clock control */
u32 sd0_clk_cfg;/* 0x88 sd0 clock control */
u32 sd1_clk_cfg;/* 0x8c sd1 clock control */
@@ -177,7 +177,7 @@ struct sunxi_ccm_reg {
#define AHB_GATE_OFFSET_ACE16
#define AHB_GATE_OFFSET_DLL15
#define AHB_GATE_OFFSET_SDRAM 14
-#define AHB_GATE_OFFSET_NAND 13
+#define AHB_GATE_OFFSET_NAND0 13
#define AHB_GATE_OFFSET_MS 12
#define AHB_GATE_OFFSET_MMC3 11
#define AHB_GATE_OFFSET_MMC2 10
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 04c6d58..7ba818f 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -215,11 +215,14 @@ struct sunxi_ccm_reg {
#define AHB_GATE_OFFSET_USB0 24
#define AHB_GATE_OFFSET_MCTL 14
#define AHB_GATE_OFFSET_GMAC 17
+#define AHB_GATE_OFFSET_NAND0 13
+#define AHB_GATE_OFFSET_NAND1 12
#define AHB_GATE_OFFSET_MMC3 11
#define AHB_GATE_OFFSET_MMC2 10
#define AHB_GATE_OFFSET_MMC1 9
#define AHB_GATE_OFFSET_MMC0 8
#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
+#define AHB_GATE_OFFSET_DMA6
#define AHB_GATE_OFFSET_SS 5
/* ahb_gate1 offsets */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
index c506b0a..a61934f 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -42,7 +42,7 @@ struct sunxi_ccm_reg {
u32 clk_output_b; /* 0x184 clk_output_a */
u8 reserved5[0x278];/* 0x188 */
- u32 nand0_clk_cfg0; /* 0x400 nand0 clock configuration0 */
+ u32 nand0_clk_cfg; /* 0x400 nand0 clock configuration0 */
u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */
u8 reserved6[0x08]; /* 0x408 */
u32 sd0_clk_cfg;/* 0x410 sd0 clock configuration */
@@ -113,8 +113,12 @@ struct sunxi_ccm_reg {
/* ahb_gate0 fields */
/* On sun9i all sdc-s share their ahb gate, so ignore (x) */
+#define AHB_GATE_OFFSET_NAND0 13
#define AHB_GATE_OFFSET_MMC(x) 8
+/* ahb gate1 field */
+#define AHB_GATE_OFFSET_DMA24
+
/* apb1_gate fields */
#define APB1_GATE_UART_SHIFT 16
#define APB1_GATE_UART_MASK(0xff APB1_GATE_UART_SHIFT)
--
2.1.0
--
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[U-Boot] [PATCH V4] Add Sunxi NAND support to SPL
V4 slightly clarifies the gating code and is a bit more precise with definitions for other boards. As far as I'm concerned they can be merged now. Happy testing, Roy -- IMAGINE IT MAKE IT Meet us online at Twitter http://twitter.com/ultimaker, Facebook http://facebook.com/ultimaker, Google+ http://google.com/+Ultimaker www.ultimaker.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Proposal to add NAND-boot support for Sunxi SPL
Hello, For my set-up I made use of Boris Brezillon's sunxi-nand tree[1], or actually I rebased his patches on top of 4.0rc7. This basically adds support for NAND-chip partitioning, ECC and randomisation. Docs for the DT specification in Documentation/devicetree/bindings/mtd/sunxi-nand.txt , and an example can be found in arch/arm/boot/dts/sun7i-a20-cubietruck.dts . [2] lists the acceptable configuration options for the boot and boot_rescue partitions, make sure to pick one of these (which should be no problem for MLC-type nand). The ECC mode for these boot partitions is called hw_syndrome. Assuming you now have a Linux set-up kernel based on this tree with NAND support on an MMC, for U-boot what you should currently do is: 1) in include/configs/sunxi-common.h, adjust the parameters CONFIG_NAND_SUNXI_PAGE_SIZE, ECC_STEP, ECC_STRENGTH to match your NAND chip and DT configuration. 2) Build 3) Use your MMC to flash u-boot-sunxi-with-spl.bin onto NAND: # flash_erase /dev/mtd0 # nandwrite -p /dev/mtd0 u-boot-sunxi-with-spl.bin 4) Reboot without the MMC card and see U-boot load That should be all. @Alex: To answer your question specifically: It's likely that the parameters in sunxi-common.h mentioned above might not match your NAND-chip configuration in the Linux kernel. I can't tell you precisely how to fetch these details from the 3.4 kernel, sorry. I recall Daniel using 24-bit strength ECC with otherwise equal parameters, but perhaps he can help you with this better than I can. Cheers, Roy [1] https://github.com/bbrezillon/linux-sunxi/commits/sunxi-nand [2] https://linux-sunxi.org/NAND#More_information_on_BROM_NAND Op 22-05-15 om 04:23 schreef kaplan2...@gmail.com: Hi Roy, I could definitely use such a howto. I have applied the patches to the current mainline u-boot head and try to boot my A13-OlinXino Wifi board in FEL mode. I can compile and boot into u-boot via FEL. However, I get these errors when I have CONFIG_SPL_NAND_SUPPORT defined: U-Boot SPL 2015.07-rc1-00276-g77792f9-dirty (May 21 2015 - 19:15:54) DRAM: 512 MiB Failed to set core voltage! Can't set CPU frequency sunxi board_nand_init() Nand initialised Error: 1 ECC failures detected Error: 512 ECC failures detected This is my configs/A13-OLinuXino_defconfig looks like this: CONFIG_SYS_EXTRA_OPTIONS=CONS_INDEX=2,AXP209_POWER,USB_EHCI,SYS_MAX_NAND_DEVICE=1,SYS_NAND_BASE=0x00 CONFIG_NAND=y CONFIG_SUNXI_NAND=y CONFIG_SUNXI_DMA=y CONFIG_CMD_NAND=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL=y CONFIG_FDTFILE=sun5i-a13-olinuxino.dtb CONFIG_USB1_VBUS_PIN=PG11 CONFIG_VIDEO_HDMI=n CONFIG_VIDEO_VGA_VIA_LCD=y CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y # For use with the Olimex 7 LCD module, adjust timings for other displays # Set video-mode=sunxi:800x600-24@60,monitor=lcd in the env. to enable CONFIG_VIDEO_LCD_MODE=x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0 CONFIG_VIDEO_LCD_POWER=AXP0-0 CONFIG_VIDEO_LCD_BL_PWM=PB2 CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 CONFIG_DRAM_ZQ=123 CONFIG_DRAM_EMR1=0 CONFIG_DEFAULT_DEVICE_TREE=sun5i-a13-olinuxino I just found out in the sun5i-a13-olinuxino.dts file are no nand settings. I guess I can find the information in the linux-sunxi 3.4 kernels fex file for the olinuxio and need to convert to dts, correct? I am happy about any hints / comments. Thanks Alex On Thursday, May 21, 2015 at 11:08:24 AM UTC-7, Hans de Goede wrote: Hi Roy, On 21-05-15 15:59, Roy Spliet wrote: The following patches take the work by Daniel Kochmánski, and make some heavy modifications for readability and functionality, based on Boris Brezillon's Linux driver. Tested on an Olimex Lime w/ A20. Patches are sent as RFC. Open questions: - Config options added are partially NAND-chip specific. Some options can be autodetected based on the NAND ID, others require either brute-forcing or config options like these. Do they belong in sunxi-common? Should we make a Kconfig option for this? If bikeshedding is desired, are defines in sunxi-common.h good enough for now? - Style is mostly kernel-like. Satisfied? - Daniel: do you think we can work from here? Please comment away! Cool stuff. Overall this looks good I'll reply with more detailed feedback to your individual patches, 2 questions: 1) Can you provide a quick howto (at developer level) on how to actually get the spl and u-boot into the nand, what I'm looking for is unstructions like this: a) Take this git repo + branch, build a kernel from it b) Look at this dts file for a nand settings example, adjust it for your board c) Once booted into the kernel using an updated dts you should have these block devices, dd spl to this one, and u-boot to this one. No more to go more detailed then that :) 2) What is the plan to add support
Re: [U-Boot] Proposal to add NAND-boot support for Sunxi SPL
Hello Hans, Sorry for ignoring the second half of your question so far. Here's what's on my mind. Op 21-05-15 om 20:08 schreef Hans de Goede: Hi Roy, 2) What is the plan to add support for loading files from nand in u-boot proper, so that we can get (e.g.) extlinux.conf + kernel +dtb from a /boot on nand ? For the full U-boot I agree we want both MMC and NAND support, regardless of where it was loaded from. From what I can tell U-boot already has UBI support. It sounds like a logical step to try and construct a proper NAND driver for U-boot that either co-exists with this SPL driver or, even better, shares code. That way, I only assume that the UBI and UBIFS layers will take care of all the rest. The NAND framework in u-boot resembles Linux in many ways. I'm currently in doubt whether we should take Boris' driver as a starting point, or rather use something heavily reduced that re-uses this SPL code. Either way, in U-boot we can perform a clean NAND-chip detection, preferably based on DT definitions as we also use on Linux, and take care of everything proper like PLL settings and a bunch of parameters which are now hard-coded or a configuration option in sunxi-common.h. SPL is a different story. I don't know the exact size restriction, but for A10 I've heard it might be as little as 30KB. Current SPL with my patches and without MMC is already 23KiB. I personally think we can reduce it slightly by taking out support for reading everything other than the bootloader partition from SPL (so remove non-syndrome mode, remove the random seeds table...), but it certainly doesn't leave any room for the full NAND framework to do ID-based NAND chip detection. I personally think it's acceptable if NAND-SPL does not have MMC support and vice-versa. For NAND, SPL is only loaded when there is no first-level bootloader found on the MMC, so I safely dare to assume U-boot isn't there. MMCs are generally not so tiny that SPL fits but U-boot doesn't. Questions, comments? Cheers, Roy Regards, Hans -- IMAGINE IT MAKE IT Meet us online at Twitter http://twitter.com/ultimaker, Facebook http://facebook.com/ultimaker, Google+ http://google.com/+Ultimaker www.ultimaker.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 (RFC) 4/4] sunxi/nand: Add support for booting from internal NAND memory
From: Daniel Kochmański dkochman...@turtle-solutions.eu
V2:
- Rename config option
- Move to separate driver
- fix DMA directly into RAM
- Many readability upgrades
- Drop R32 and W32 macros in favour of readl/writel respectively
- Use standard port controller methods for pinctl
- Make many NAND options semi-configurable
V3:
- Use proper structs and definitions for DMA and NAND
- Fix bug wrt. page size selection
- Add time-out to waits
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
arch/arm/cpu/armv7/sunxi/board.c | 12 +-
arch/arm/include/asm/arch-sunxi/gpio.h | 2 +
arch/arm/include/asm/arch-sunxi/nand.h | 67 +
board/sunxi/Kconfig| 12 ++
board/sunxi/board.c| 16 ++
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/sunxi_nand_spl.c | 268 +
include/configs/sun4i.h| 1 +
include/configs/sun5i.h| 3 +
include/configs/sun7i.h| 2 +
include/configs/sun8i.h| 6 +
include/configs/sunxi-common.h | 20 +++
12 files changed, 408 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/include/asm/arch-sunxi/nand.h
create mode 100644 drivers/mtd/nand/sunxi_nand_spl.c
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 6718ae2..70f413f 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -111,8 +111,10 @@ void s_init(void)
#ifdef CONFIG_SPL_BUILD
/* The sunxi internal brom will try to loader external bootloader
* from mmc0, nand flash, mmc2.
- * Unfortunately we can't check how SPL was loaded so assume
- * it's always the first SD/MMC controller
+ *
+ * Unfortunately we can't check how SPL was loaded so assume it's
+ * always the first SD/MMC controller, unless it was explicitly
+ * stated that SPL is on nand flash.
*/
u32 spl_boot_device(void)
{
@@ -122,6 +124,12 @@ u32 spl_boot_device(void)
* enabled build. It has many restrictions and can only boot over USB.
*/
return BOOT_DEVICE_BOARD;
+#elif defined(CONFIG_SPL_NAND_SUPPORT)
+ /*
+* This is compile time configuration informing SPL, that it
+* was loaded from nand flash.
+*/
+ return BOOT_DEVICE_NAND;
#else
/*
* When booting from the SD card, the eGON.BT0 signature is expected
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 59d8210..2b49616 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -156,6 +156,8 @@ enum sunxi_gpio_number {
#define SUN4I_GPB_UART02
#define SUN5I_GPB_UART02
+#define SUNXI_GPC_NAND 2
+
#define SUNXI_GPC_SDC2 3
#define SUN6I_GPC_SDC3 4
diff --git a/arch/arm/include/asm/arch-sunxi/nand.h
b/arch/arm/include/asm/arch-sunxi/nand.h
new file mode 100644
index 000..22844d8
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/nand.h
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2015 Roy Spliet rspl...@ultimaker.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_NAND_H
+#define _SUNXI_NAND_H
+
+#include linux/types.h
+
+struct sunxi_nand
+{
+ u32 ctl;/* 0x000 Configure and control */
+ u32 st; /* 0x004 Status information */
+ u32 intr; /* 0x008 Interrupt control */
+ u32 timing_ctl; /* 0x00C Timing control */
+ u32 timing_cfg; /* 0x010 Timing configure */
+ u32 addr_low; /* 0x014 Low word address */
+ u32 addr_high; /* 0x018 High word address */
+ u32 block_num; /* 0x01C Data block number */
+ u32 data_cnt; /* 0x020 Data counter for transfer */
+ u32 cmd;/* 0x024 NDFC commands */
+ u32 rcmd_set; /* 0x028 Read command set for vendor NAND mem */
+ u32 wcmd_set; /* 0x02C Write command set */
+ u32 io_data;/* 0x030 IO data */
+ u32 ecc_ctl;/* 0x034 ECC configure and control */
+ u32 ecc_st; /* 0x038 ECC status and operation info */
+ u32 efr;/* 0x03C Enhanced feature */
+ u32 err_cnt0; /* 0x040 Corrected error bit counter 0 */
+ u32 err_cnt1; /* 0x044 Corrected error bit counter 1 */
+ u32 user_data[16]; /* 0x050[16] User data field */
+ u32 efnand_st; /* 0x090 EFNAND status */
+ u32 res0[3];
+ u32 spare_area; /* 0x0A0 Spare area configure */
+ u32 pat_id; /* 0x0A4 Pattern ID register */
+ u32 rdata_sta_ctl; /* 0x0A8 Read data status control */
+ u32 rdata_sta_0;/* 0x0AC Read data status 0 */
+ u32 rdata_sta_1;/* 0x0B0 Read data status 1 */
+ u32 res1[3];
+ u32 mdma_addr; /* 0x0C0
[U-Boot] [PATCH v3 (RFC) 3/4] sunxi: Match sun4i nand clock name with sun6i
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index c28ee05..fe3e92f 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -39,7 +39,7 @@ struct sunxi_ccm_reg {
u32 apb0_gate; /* 0x68 apb0 module clock gating */
u32 apb1_gate; /* 0x6c apb1 module clock gating */
u8 res4[0x10];
- u32 nand_sclk_cfg; /* 0x80 nand sub clock control */
+ u32 nand0_clk_cfg; /* 0x80 nand sub clock control */
u32 ms_sclk_cfg;/* 0x84 memory stick sub clock control */
u32 sd0_clk_cfg;/* 0x88 sd0 clock control */
u32 sd1_clk_cfg;/* 0x8c sd1 clock control */
--
2.1.0
--
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[U-Boot] [PATCH v3 (RFC) 1/4] sunxi/nand: change BLOCK_SIZE in mksunxiboot to match NAND block size
From: Daniel Kochmański dkochman...@turtle-solutions.eu
This change is necessary to calculate correct checksum for NAND
boot. Works both for MMC and NAND. Without it BROM rejects boot image
as invalid (bad checksum). (Changes block size from 0x200 to 0x2000).
V2: Document decision in source too
Signed-off-by: Daniel Kochmański dkochman...@turtle-solutions.eu
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
Cc: Ian Campbell i...@hellion.org.uk
Cc: Hans De Goede hdego...@redhat.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
tools/mksunxiboot.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c
index 0035f6e..3361251 100644
--- a/tools/mksunxiboot.c
+++ b/tools/mksunxiboot.c
@@ -65,7 +65,13 @@ int gen_check_sum(struct boot_file_head *head_p)
#define SUN4I_SRAM_SIZE 0x7600 /* 0x7748+ is used by BROM */
#define SRAM_LOAD_MAX_SIZE (SUN4I_SRAM_SIZE - sizeof(struct boot_file_head))
-#define BLOCK_SIZE 512
+
+/*
+ * BROM (at least on A10 and A20) requires NAND-images to be explicitly aligned
+ * to a multiple of 8K, and rejects the image otherwise. MMC-images are fine
+ * with 512B blocks. To cater for both, align to the largest of the two.
+ */
+#define BLOCK_SIZE 0x2000
struct boot_img {
struct boot_file_head header;
--
2.1.0
--
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[U-Boot] [v3 (RFC)] Proposal to add NAND-boot support for Sunxi SPL
Hereby a v3 of the patches adding NAND support to SPL. Most noticably all the feedback has been addressed: tidy structs for NAND and DMA, timeouts on wait operations and more proper use of the CCU. Patches are marked RFC mostly because I'm still contemplating the implementation of a proper full NAND driver to be used with the existing UBI subsystem. This could mean some slight changes in structure to better accomodate code sharing between sunxi-nand for SPL and U-boot. If you wish you can merge the first three patches though, I expect them not to change any further. Thanks for earlier feedback, and don't hesitate to let me know if anything else could be improved. Cheers, Roy -- IMAGINE IT MAKE IT Meet us online at Twitter http://twitter.com/ultimaker, Facebook http://facebook.com/ultimaker, Google+ http://google.com/+Ultimaker www.ultimaker.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 (RFC) 2/4] sunxi: Add DMA definitions
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
arch/arm/include/asm/arch-sunxi/dma.h | 16 +++
arch/arm/include/asm/arch-sunxi/dma_sun4i.h | 68 +
2 files changed, 84 insertions(+)
create mode 100644 arch/arm/include/asm/arch-sunxi/dma.h
create mode 100644 arch/arm/include/asm/arch-sunxi/dma_sun4i.h
diff --git a/arch/arm/include/asm/arch-sunxi/dma.h
b/arch/arm/include/asm/arch-sunxi/dma.h
new file mode 100644
index 000..e288f36
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dma.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2015 Roy Spliet rspl...@ultimaker.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_DMA_H
+#define _SUNXI_DMA_H
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+#include asm/arch/dma_sun4i.h
+#else
+#error DMA definition not available for this architecture
+#endif
+
+#endif /* _SUNXI_DMA_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dma_sun4i.h
b/arch/arm/include/asm/arch-sunxi/dma_sun4i.h
new file mode 100644
index 000..778a04b
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dma_sun4i.h
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2015 Roy Spliet rspl...@ultimaker.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_DMA_SUN4I_H
+#define _SUNXI_DMA_SUN4I_H
+
+struct sunxi_dma_cfg
+{
+ u32 ctl;/* 0x00 Control */
+ u32 src_addr; /* 0x04 Source address */
+ u32 dst_addr; /* 0x08 Destination address */
+ u32 bc; /* 0x0C Byte counter */
+ u32 res0[2];
+ u32 ddma_para; /* 0x18 extra parameter (dedicated DMA only) */
+ u32 res1;
+};
+
+struct sunxi_dma
+{
+ u32 irq_en; /* 0x000 IRQ enable */
+ u32 irq_pend; /* 0x004 IRQ pending */
+ u32 auto_gate; /* 0x008 auto gating */
+ u32 res0[61];
+ struct sunxi_dma_cfg ndma[8]; /* 0x100 Normal DMA */
+ u32 res1[64];
+ struct sunxi_dma_cfg ddma[8]; /* 0x300 Dedicated DMA */
+};
+
+enum ddma_drq_type {
+ DDMA_DST_DRQ_SRAM = 0,
+ DDMA_SRC_DRQ_SRAM = 0,
+ DDMA_DST_DRQ_SDRAM = 1,
+ DDMA_SRC_DRQ_SDRAM = 1,
+ DDMA_DST_DRQ_PATA = 2,
+ DDMA_SRC_DRQ_PATA = 2,
+ DDMA_DST_DRQ_NAND = 3,
+ DDMA_SRC_DRQ_NAND = 3,
+ DDMA_DST_DRQ_USB0 = 4,
+ DDMA_SRC_DRQ_USB0 = 4,
+ DDMA_DST_DRQ_ETHERNET_MAC_TX = 6,
+ DDMA_SRC_DRQ_ETHERNET_MAC_RX = 7,
+ DDMA_DST_DRQ_SPI1_TX = 8,
+ DDMA_SRC_DRQ_SPI1_RX = 9,
+ DDMA_DST_DRQ_SECURITY_SYS_TX = 10,
+ DDMA_SRC_DRQ_SECURITY_SYS_RX = 11,
+ DDMA_DST_DRQ_TCON0 = 14,
+ DDMA_DST_DRQ_TCON1 = 15,
+ DDMA_DST_DRQ_MSC = 23,
+ DDMA_SRC_DRQ_MSC = 23,
+ DDMA_DST_DRQ_SPI0_TX = 26,
+ DDMA_SRC_DRQ_SPI0_RX = 27,
+ DDMA_DST_DRQ_SPI2_TX = 28,
+ DDMA_SRC_DRQ_SPI2_RX = 29,
+ DDMA_DST_DRQ_SPI3_TX = 30,
+ DDMA_SRC_DRQ_SPI3_RX = 31,
+};
+
+#define SUNXI_DMA_CTL_SRC_DRQ(a) ((a) 0x1f)
+#define SUNXI_DMA_CTL_MODE_IO (1 5)
+#define SUNXI_DMA_CTL_SRC_DATA_WIDTH_32(2 9)
+#define SUNXI_DMA_CTL_DST_DRQ(a) (((a) 0x1f) 16)
+#define SUNXI_DMA_CTL_DST_DATA_WIDTH_32(2 25)
+#define SUNXI_DMA_CTL_TRIGGER (1 31)
+
+#endif /* _SUNXI_DMA_SUN4I_H */
--
2.1.0
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[U-Boot] [PATCH 1/2] nand: sunxi: change BLOCK_SIZE in mksunxiboot to match NAND block size
From: Daniel Kochmański dkochman...@turtle-solutions.eu
This change is necessary to calculate correct checksum for NAND
boot. Works both for MMC and NAND. Without it BROM rejects boot image
as invalid (bad checksum). (Changes block size from 0x200 to 0x2000).
V2: Document decision in source too
Signed-off-by: Daniel Kochmański dkochman...@turtle-solutions.eu
Cc: Ian Campbell i...@hellion.org.uk
Cc: Hans De Goede hdego...@redhat.com
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
tools/mksunxiboot.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c
index 0035f6e..3361251 100644
--- a/tools/mksunxiboot.c
+++ b/tools/mksunxiboot.c
@@ -65,7 +65,13 @@ int gen_check_sum(struct boot_file_head *head_p)
#define SUN4I_SRAM_SIZE 0x7600 /* 0x7748+ is used by BROM */
#define SRAM_LOAD_MAX_SIZE (SUN4I_SRAM_SIZE - sizeof(struct boot_file_head))
-#define BLOCK_SIZE 512
+
+/*
+ * BROM (at least on A10 and A20) requires NAND-images to be explicitly aligned
+ * to a multiple of 8K, and rejects the image otherwise. MMC-images are fine
+ * with 512B blocks. To cater for both, align to the largest of the two.
+ */
+#define BLOCK_SIZE 0x2000
struct boot_img {
struct boot_file_head header;
--
2.1.0
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[U-Boot] [PATCH 2/2] nand: sunxi: Add support for booting from internal NAND memory
From: Daniel Kochmański dkochman...@turtle-solutions.eu
V2:
- Rename config option
- Move to separate driver
- fix DMA directly into RAM
- Many readability upgrades
- Drop R32 and W32 macros in favour of readl/writel respectively
- Use standard port controller methods for pinctl
- Make many NAND options semi-configurable
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
arch/arm/cpu/armv7/sunxi/board.c | 12 +-
arch/arm/include/asm/arch-sunxi/gpio.h | 2 +
board/sunxi/Kconfig| 12 ++
board/sunxi/board.c| 27 +++
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/sunxi_nand_spl.c | 290 +
include/configs/sun4i.h| 1 +
include/configs/sun5i.h| 3 +
include/configs/sun7i.h| 2 +
include/configs/sun8i.h| 6 +
include/configs/sunxi-common.h | 20 +++
11 files changed, 374 insertions(+), 2 deletions(-)
create mode 100644 drivers/mtd/nand/sunxi_nand_spl.c
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 6718ae2..70f413f 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -111,8 +111,10 @@ void s_init(void)
#ifdef CONFIG_SPL_BUILD
/* The sunxi internal brom will try to loader external bootloader
* from mmc0, nand flash, mmc2.
- * Unfortunately we can't check how SPL was loaded so assume
- * it's always the first SD/MMC controller
+ *
+ * Unfortunately we can't check how SPL was loaded so assume it's
+ * always the first SD/MMC controller, unless it was explicitly
+ * stated that SPL is on nand flash.
*/
u32 spl_boot_device(void)
{
@@ -122,6 +124,12 @@ u32 spl_boot_device(void)
* enabled build. It has many restrictions and can only boot over USB.
*/
return BOOT_DEVICE_BOARD;
+#elif defined(CONFIG_SPL_NAND_SUPPORT)
+ /*
+* This is compile time configuration informing SPL, that it
+* was loaded from nand flash.
+*/
+ return BOOT_DEVICE_NAND;
#else
/*
* When booting from the SD card, the eGON.BT0 signature is expected
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 59d8210..2b49616 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -156,6 +156,8 @@ enum sunxi_gpio_number {
#define SUN4I_GPB_UART02
#define SUN5I_GPB_UART02
+#define SUNXI_GPC_NAND 2
+
#define SUNXI_GPC_SDC2 3
#define SUN6I_GPC_SDC3 4
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index a60d028..cf58d73 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -269,6 +269,18 @@ config MMC_SUNXI_SLOT_EXTRA
slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
support for this.
+config SPL_NAND_SUPPORT
+ bool SPL/NAND mode support
+ depends on SPL
+ default n
+ ---help---
+ This enables support for booting from NAND internal
+ memory. U-Boot SPL doesn't detect where is it load from,
+ therefore this option is needed to properly load image from
+ flash. Option also disables MMC functionality on U-Boot due to
+ initialization errors encountered, when both controllers are
+ enabled.
+
config USB0_VBUS_PIN
string Vbus enable pin for usb0 (otg)
default
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index d9f7691..121e655 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -22,6 +22,9 @@
#ifdef CONFIG_AXP221_POWER
#include axp221.h
#endif
+#ifdef CONFIG_NAND_SUNXI
+#include nand.h
+#endif
#include asm/arch/clock.h
#include asm/arch/cpu.h
#include asm/arch/display.h
@@ -34,6 +37,8 @@
#include linux/usb/musb.h
#include net.h
+#define CCMU_BASE 0x01c2
+
#if defined CONFIG_VIDEO_LCD_PANEL_I2C !(defined CONFIG_SPL_BUILD)
/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
int soft_i2c_gpio_sda;
@@ -315,6 +320,28 @@ int board_mmc_init(bd_t *bis)
}
#endif
+void board_nand_init(void)
+{
+ uint32_t val;
+ unsigned int pin;
+ static u8 ports[] = CONFIG_NAND_SUNXI_GPC_PORTS;
+
+ /* Configure AHB muxes to connect output pins with NAND controller */
+ for (pin = 0; pin 16; pin++)
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(pin), SUNXI_GPC_NAND);
+
+ for (pin = 0; pin ARRAY_SIZE(ports); pin++)
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(ports[pin]), SUNXI_GPC_NAND);
+
+ /* un-gate NAND clock and clock source
+* This assumes that the clock was already correctly configured by
+* BootROM */
+ val = readl(CCMU_BASE + 0x60);
+ writel((val | 0x2000), CCMU_BASE + 0x60);
+ val = readl(CCMU_BASE + 0x80);
+ writel((val | 0x8000), CCMU_BASE + 0x80);
+}
+
void
[U-Boot] Proposal to add NAND-boot support for Sunxi SPL
The following patches take the work by Daniel Kochmánski, and make some heavy modifications for readability and functionality, based on Boris Brezillon's Linux driver. Tested on an Olimex Lime w/ A20. Patches are sent as RFC. Open questions: - Config options added are partially NAND-chip specific. Some options can be autodetected based on the NAND ID, others require either brute-forcing or config options like these. Do they belong in sunxi-common? Should we make a Kconfig option for this? If bikeshedding is desired, are defines in sunxi-common.h good enough for now? - Style is mostly kernel-like. Satisfied? - Daniel: do you think we can work from here? Please comment away! Roy -- IMAGINE IT MAKE IT Meet us online at Twitter http://twitter.com/ultimaker, Facebook http://facebook.com/ultimaker, Google+ http://google.com/+Ultimaker www.ultimaker.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] board/snowball: Add support for network boot
Signed-off-by: Roy Spliet rspl...@eclipso.eu
---
board/st-ericsson/snowball/snowball.c | 11 +++
include/configs/snowball.h| 14 ++
2 files changed, 25 insertions(+)
diff --git a/board/st-ericsson/snowball/snowball.c
b/board/st-ericsson/snowball/snowball.c
index c3061e2..c9ab71f 100644
--- a/board/st-ericsson/snowball/snowball.c
+++ b/board/st-ericsson/snowball/snowball.c
@@ -245,6 +245,8 @@ int board_late_init(void)
while (tstc())
(void) getc();
+ mdelay(25);
+
return 0;
}
@@ -338,3 +340,12 @@ int board_mmc_init(bd_t *bis)
return 0;
}
#endif /* CONFIG_MMC */
+
+int board_eth_init(bd_t *bis)
+{
+ int error = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+ if (error)
+ return error;
+
+ return cpu_eth_init(bis);
+}
diff --git a/include/configs/snowball.h b/include/configs/snowball.h
index 9a069f3..6201b3f 100644
--- a/include/configs/snowball.h
+++ b/include/configs/snowball.h
@@ -95,6 +95,10 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
#ifndef CONFIG_BOOTDELAY
#define CONFIG_BOOTDELAY 1
@@ -245,4 +249,14 @@
#define CFG_FSMC_BASE 0x8000 /* FSMC Controller */
+/*
+ * Networking
+ */
+#define CONFIG_NET
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_SMC911X_SHIFT 1
+#define CONFIG_SMC911X_BASE0x5000
+
#endif /* __CONFIG_H */
--
1.8.1.2
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[U-Boot] [PATCH 1/3] drivers/smc911x: Add support for shifted register read/write
Required for (but potentially not limited to) the snowball board. Implementation
is inspired by the linux smsc911x implementation, but by using a (pre-compiler)
constant, things should be optimised by the compiler for a shift of 0.
Signed-off-by: Roy Spliet rspl...@eclipso.eu
---
drivers/net/smc911x.h | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index acae0cf..7144722 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -19,6 +19,12 @@
CONFIG_SMC911X_16_BIT shall be set
#endif
+#ifndef CONFIG_SMC911X_SHIFT
+#define CONFIG_SMC911X_SHIFT 0
+#endif
+
+#define smc911x_shift(i) ((i) CONFIG_SMC911X_SHIFT)
+
#if defined (CONFIG_SMC911X_32_BIT)
static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset)
{
@@ -37,14 +43,14 @@ void smc911x_reg_write(struct eth_device *dev, u32 offset,
u32 val)
#elif defined (CONFIG_SMC911X_16_BIT)
static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
{
- volatile u16 *addr_16 = (u16 *)(dev-iobase + offset);
- return ((*addr_16 0x) | (*(addr_16 + 1) 16));
+ volatile u16 *addr_16 = (u16 *)(dev-iobase + smc911x_shift(offset));
+ return (*addr_16 0x) | (*(addr_16 + smc911x_shift(1)) 16);
}
static inline void smc911x_reg_write(struct eth_device *dev,
u32 offset, u32 val)
{
- *(volatile u16 *)(dev-iobase + offset) = (u16)val;
- *(volatile u16 *)(dev-iobase + offset + 2) = (u16)(val 16);
+ *(volatile u16 *)(dev-iobase + smc911x_shift(offset)) = (u16)val;
+ *(volatile u16 *)(dev-iobase + smc911x_shift(offset + 2)) = (u16)val;
}
#else
#error SMC911X: undefined bus width
--
1.8.1.2
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[U-Boot] [PATCH 3/3] board/snowball: Enable FDT
Signed-off-by: Roy Spliet rspl...@eclipso.eu Acked-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com --- include/configs/snowball.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/configs/snowball.h b/include/configs/snowball.h index 6201b3f..4a19d2c 100644 --- a/include/configs/snowball.h +++ b/include/configs/snowball.h @@ -259,4 +259,9 @@ #define CONFIG_SMC911X_SHIFT 1 #define CONFIG_SMC911X_BASE0x5000 +/* + * Device tree + */ +#define CONFIG_OF_LIBFDT + #endif /* __CONFIG_H */ -- 1.8.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Improve upstream support for Snowball board (v2)
Patches are loosely based on the tree maintained by Calao. FDT confirmed working, LAN is successfully detected by u-boot (but lacking a proper tftp setup this is untested). Upstream U-Boot still has one bug that prevents booting from eMMC. Easiest workaround is to revert e95504497ecac46907204b0ee3460b708a2981ac mmc: Split device init to decouple OCR-polling delay until I (or someone else) has time to device a proper fix. This doesn't prevent anyone from pushing these two patches though. v2: Split up networking patch into one for driver and one for board. Fix checkpatch errors. Three warnings are still reported by checkstyle.pl, related to the use of the volatile keyword. These warning are not justified or relevant for MMIO register reads as far as I know, so could be ignored. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] snowball: Add networking support
Dear Jagan,
Thanks for the feedback. I will check the patch and split it up in two. This
fix is derived from the igloocommunity github u-boot repository, but their
implementation was a bit too ad-hoc for my taste, using #ifdef CONFIG_SNOWBALL
to override the alignment of the smc911x driver. I added the delay based on
trial-and-error, and without the delay the device would not be detected
correctly. Perhaps 25ms is a little bit too long, but since I have no
documentation to back the exact value up I guess this will just do. If you
please I can experiment with shorter periods, but I personally feel it's not
worth the effort and risks having a u-boot that doesn't work based on physical
properties of the device (and thus appears to fail randomly).
Yours,
Roy
--- Ursprüngliche Nachricht ---
Von: Jagan Teki jagannadh.t...@gmail.com
Datum: 18:07:30 14-12-2013
An: Roy Spliet rspl...@eclipso.eu
Betreff: Re: [U-Boot] [PATCH 1/2] snowball: Add networking support
Try to fix - checkpatch.pl issues.
total: 2 errors, 4 warnings, 0 checks, 74 lines checked
On Sat, Dec 14, 2013 at 10:09 PM, Roy Spliet rspl...@eclipso.eu wrote:
Signed-off-by: Roy Spliet rspl...@eclipso.eu
---
board/st-ericsson/snowball/snowball.c | 11 +++
drivers/net/smc911x.h | 14 ++
include/configs/snowball.h| 14 ++
3 files changed, 35 insertions(+), 4 deletions(-)
diff --git a/board/st-ericsson/snowball/snowball.c
b/board/st-ericsson/snowball/snowball.c
index c3061e2..356beb1 100644
--- a/board/st-ericsson/snowball/snowball.c
+++ b/board/st-ericsson/snowball/snowball.c
@@ -245,6 +245,8 @@ int board_late_init(void)
while (tstc())
(void) getc();
+ mdelay(25);
+
return 0;
}
@@ -338,3 +340,12 @@ int board_mmc_init(bd_t *bis)
return 0;
}
#endif /* CONFIG_MMC */
+
+int board_eth_init(bd_t *bis)
+{
+ int error = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+ if(error)
+ return error;
+
+ return cpu_eth_init(bis);
+}
TAG++
diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index acae0cf..7fe55f1 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -19,6 +19,12 @@
CONFIG_SMC911X_16_BIT shall be set
#endif
+#ifndef CONFIG_SMC911X_SHIFT
+#define CONFIG_SMC911X_SHIFT 0
+#endif
+
+#define smc911x_shift(i) ((i) CONFIG_SMC911X_SHIFT)
+
#if defined (CONFIG_SMC911X_32_BIT)
static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset)
{
@@ -37,14 +43,14 @@ void smc911x_reg_write(struct eth_device *dev, u32
offset, u32 val)
#elif defined (CONFIG_SMC911X_16_BIT)
static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
{
- volatile u16 *addr_16 = (u16 *)(dev-iobase + offset);
- return ((*addr_16 0x) | (*(addr_16 + 1)
16));
+ volatile u16 *addr_16 = (u16 *)(dev-iobase +
smc911x_shift(offset));
+ return ((*addr_16 0x) | (*(addr_16 + smc911x_shift(1))
16));
}
static inline void smc911x_reg_write(struct eth_device *dev,
u32 offset, u32 val)
{
- *(volatile u16 *)(dev-iobase + offset) = (u16)val;
- *(volatile u16 *)(dev-iobase + offset + 2) = (u16)(val
16);
+ *(volatile u16 *)(dev-iobase + smc911x_shift(offset)) =
(u16)val;
+ *(volatile u16 *)(dev-iobase + smc911x_shift(offset + 2))
= (u16)val;
}
TAG--
TAG++ ..TAG-- as this area of code is part of smc911x driver, better to create
another patch for it.
By the way does this change comes from bcz of snowball or a generic one?
--
Thanks,
Jagan.
Jagannadha Sutradharudu Teki,
E: jagannadh.t...@gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki
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[U-Boot] Improve upstream support for Snowball board
Patches are loosely based on the tree maintained by Calao. FDT confirmed working, LAN is successfully detected by u-boot (but lacking a proper tftp setup this is untested). Upstream U-Boot still has one bug that prevents booting from eMMC. Easiest workaround is to revert e95504497ecac46907204b0ee3460b708a2981ac mmc: Split device init to decouple OCR-polling delay until I (or someone else) has time to device a proper fix. This doesn't prevent anyone from pushing these two patches though. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] snowball: Enable FDT
Signed-off-by: Roy Spliet rspl...@eclipso.eu --- include/configs/snowball.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/configs/snowball.h b/include/configs/snowball.h index 6201b3f..4a19d2c 100644 --- a/include/configs/snowball.h +++ b/include/configs/snowball.h @@ -259,4 +259,9 @@ #define CONFIG_SMC911X_SHIFT 1 #define CONFIG_SMC911X_BASE0x5000 +/* + * Device tree + */ +#define CONFIG_OF_LIBFDT + #endif /* __CONFIG_H */ -- 1.8.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] snowball: Add networking support
Signed-off-by: Roy Spliet rspl...@eclipso.eu
---
board/st-ericsson/snowball/snowball.c | 11 +++
drivers/net/smc911x.h | 14 ++
include/configs/snowball.h| 14 ++
3 files changed, 35 insertions(+), 4 deletions(-)
diff --git a/board/st-ericsson/snowball/snowball.c
b/board/st-ericsson/snowball/snowball.c
index c3061e2..356beb1 100644
--- a/board/st-ericsson/snowball/snowball.c
+++ b/board/st-ericsson/snowball/snowball.c
@@ -245,6 +245,8 @@ int board_late_init(void)
while (tstc())
(void) getc();
+ mdelay(25);
+
return 0;
}
@@ -338,3 +340,12 @@ int board_mmc_init(bd_t *bis)
return 0;
}
#endif /* CONFIG_MMC */
+
+int board_eth_init(bd_t *bis)
+{
+ int error = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+ if(error)
+ return error;
+
+ return cpu_eth_init(bis);
+}
diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index acae0cf..7fe55f1 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -19,6 +19,12 @@
CONFIG_SMC911X_16_BIT shall be set
#endif
+#ifndef CONFIG_SMC911X_SHIFT
+#define CONFIG_SMC911X_SHIFT 0
+#endif
+
+#define smc911x_shift(i) ((i) CONFIG_SMC911X_SHIFT)
+
#if defined (CONFIG_SMC911X_32_BIT)
static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset)
{
@@ -37,14 +43,14 @@ void smc911x_reg_write(struct eth_device *dev, u32 offset,
u32 val)
#elif defined (CONFIG_SMC911X_16_BIT)
static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
{
- volatile u16 *addr_16 = (u16 *)(dev-iobase + offset);
- return ((*addr_16 0x) | (*(addr_16 + 1) 16));
+ volatile u16 *addr_16 = (u16 *)(dev-iobase + smc911x_shift(offset));
+ return ((*addr_16 0x) | (*(addr_16 + smc911x_shift(1))
16));
}
static inline void smc911x_reg_write(struct eth_device *dev,
u32 offset, u32 val)
{
- *(volatile u16 *)(dev-iobase + offset) = (u16)val;
- *(volatile u16 *)(dev-iobase + offset + 2) = (u16)(val 16);
+ *(volatile u16 *)(dev-iobase + smc911x_shift(offset)) = (u16)val;
+ *(volatile u16 *)(dev-iobase + smc911x_shift(offset + 2)) = (u16)val;
}
#else
#error SMC911X: undefined bus width
diff --git a/include/configs/snowball.h b/include/configs/snowball.h
index 9a069f3..6201b3f 100644
--- a/include/configs/snowball.h
+++ b/include/configs/snowball.h
@@ -95,6 +95,10 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
#ifndef CONFIG_BOOTDELAY
#define CONFIG_BOOTDELAY 1
@@ -245,4 +249,14 @@
#define CFG_FSMC_BASE 0x8000 /* FSMC Controller */
+/*
+ * Networking
+ */
+#define CONFIG_NET
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_SMC911X_SHIFT 1
+#define CONFIG_SMC911X_BASE0x5000
+
#endif /* __CONFIG_H */
--
1.8.1.2
___
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