[U-Boot] [PATCH v3 6/6] board: toradex: colibri_vf: Add DCU support for Colibri Vybrid
From: Stefan Agner <stefan.ag...@toradex.com>
The Vybrid SoC family has the same display controller unit (DCU)
like the LS1021A SoC. This patch adds platform data, pinmux defines
and clock control to enable the driver for Toradex Colibri Vybrid
module.
Signed-off-by: Stefan Agner <stefan.ag...@toradex.com>
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
arch/arm/include/asm/arch-vf610/crm_regs.h| 14 +
arch/arm/include/asm/arch-vf610/imx-regs.h| 2 +
arch/arm/include/asm/arch-vf610/iomux-vf610.h | 31 +++
arch/arm/include/asm/imx-common/iomux-v3.h| 3 ++
board/toradex/colibri_vf/Makefile | 1 +
board/toradex/colibri_vf/colibri_vf.c | 76 +--
board/toradex/colibri_vf/dcu.c| 38 ++
configs/colibri_vf_defconfig | 4 ++
include/configs/colibri_vf.h | 13 +
9 files changed, 166 insertions(+), 16 deletions(-)
create mode 100644 board/toradex/colibri_vf/dcu.c
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h
b/arch/arm/include/asm/arch-vf610/crm_regs.h
index a46e396f1d..73b1dd2f14 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -9,6 +9,8 @@
#ifndef __ASSEMBLY__
+#include
+
/* Clock Controller Module (CCM) */
struct ccm_reg {
u32 ccr;
@@ -150,6 +152,9 @@ struct anadig_reg {
#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7)
+#define CCM_CSCMR1_DCU1_CLK_SEL(1 << 29)
+#define CCM_CSCMR1_DCU0_CLK_SEL(1 << 28)
+
#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET22
#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22)
#define CCM_CSCMR1_QSPI0_CLK_SEL(v)(((v) & 0x3) << 22)
@@ -174,6 +179,13 @@ struct anadig_reg {
#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20)
+#define CCM_CSCDR3_DCU1_EN (1 << 23)
+#define CCM_CSCDR3_DCU1_DIV_MASK (0x7 << 20)
+#define CCM_CSCDR3_DCU1_DIV(v) (((v) & 0x7) << 20)
+#define CCM_CSCDR3_DCU0_EN (1 << 19)
+#define CCM_CSCDR3_DCU0_DIV_MASK (0x7 << 16)
+#define CCM_CSCDR3_DCU0_DIV(v) (((v) & 0x7) << 16)
+
#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET 13
#define CCM_CSCDR3_NFC_PRE_DIV_MASK(0x7 << 13)
#define CCM_CSCDR3_NFC_PRE_DIV(v) (((v) & 0x7) << 13)
@@ -193,6 +205,7 @@ struct anadig_reg {
#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26)
#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8)
#define CCM_CCGR1_PIT_CTRL_MASK(0x3 << 14)
+#define CCM_CCGR1_TCON0_CTRL_MASK (0x3 << 26)
#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8)
#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16)
@@ -203,6 +216,7 @@ struct anadig_reg {
#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26)
#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
#define CCM_CCGR3_SCSC_CTRL_MASK(0x3 << 4)
+#define CCM_CCGR3_DCU0_CTRL_MASK (0x3 << 16)
#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20)
#define CCM_CCGR4_CCM_CTRL_MASK(0x3 << 22)
#define CCM_CCGR4_GPC_CTRL_MASK(0x3 << 24)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index cac68efde2..ca97462c35 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -69,6 +69,7 @@
#define USB_PHY0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050800)
#define USB_PHY1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050C00)
#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
+#define DCU0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00058000)
#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006)
#define SPDIF_BASE_ADDR(AIPS0_BASE_ADDR + 0x00061000)
#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
@@ -98,6 +99,7 @@
#define USBC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00034000)
#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x0005)
#define ENET1_BASE_ADDR(AIPS1_BASE_ADDR + 0x00051000)
+#define DCU1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00058000)
#define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x0006)
#define QSPI0_AMBA_BASE0x2000
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
index a140be05f1..5af071a4db 100644
--- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
[U-Boot] [PATCH v3 3/6] video: fsl_dcu_fb: Enable pixel clock after initialization
From: Stefan Agner <stefan.ag...@toradex.com> When enabling the DCU and pixel clock, the test mode is activated since this is the reset configuration. The test mode immediately shows a red screen on a LCD. A moment later, the DCU gets initialized properly. This patch enables the pixel clock after initialization of the DCU control register. This avoids this initial flicker on LCD screens. While at it change the polarity of pixel clock to display samples data on the rising edge. Signed-off-by: Stefan Agner <stefan.ag...@toradex.com> Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com> --- drivers/video/fsl_dcu_fb.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c index 801bf3db95..a922a91fb2 100644 --- a/drivers/video/fsl_dcu_fb.c +++ b/drivers/video/fsl_dcu_fb.c @@ -41,7 +41,7 @@ #define DCU_VSYN_PARA_BP(x)((x) << 22) #define DCU_VSYN_PARA_PW(x)((x) << 11) #define DCU_VSYN_PARA_FP(x)(x) -#define DCU_SYN_POL_INV_PXCK_FALL (0 << 6) +#define DCU_SYN_POL_INV_PXCK_FALL (1 << 6) #define DCU_SYN_POL_NEG_REMAIN (0 << 5) #define DCU_SYN_POL_INV_VS_LOW (1 << 1) #define DCU_SYN_POL_INV_HS_LOW (1) @@ -191,8 +191,6 @@ static void reset_total_layers(void) dcu_write32(>ctrldescl[i][9], 0); dcu_write32(>ctrldescl[i][10], 0); } - - dcu_write32(>update_mode, DCU_UPDATE_MODE_READREG); } static int layer_ctrldesc_init(int index, u32 pixel_format) @@ -246,8 +244,6 @@ static int layer_ctrldesc_init(int index, u32 pixel_format) dcu_write32(>ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0)); dcu_write32(>ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0)); - dcu_write32(>update_mode, DCU_UPDATE_MODE_READREG); - return 0; } @@ -273,8 +269,6 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres, memset(info.screen_base, 0, info.screen_size); reset_total_layers(); - div = dcu_set_pixel_clock(info.var.pixclock); - dcu_write32(>div_ratio, (div - 1)); dcu_write32(>disp_size, DCU_DISP_SIZE_DELTA_Y(info.var.yres) | @@ -313,6 +307,11 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres, layer_ctrldesc_init(0, pixel_format); + div = dcu_set_pixel_clock(info.var.pixclock); + dcu_write32(>div_ratio, (div - 1)); + + dcu_write32(>update_mode, DCU_UPDATE_MODE_READREG); + return 0; } -- 2.12.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 5/6] video: fsl_dcu_fb: add additional modes for DCU
From: Stefan Agner <stefan.ag...@toradex.com>
Add common widescreen modes 800x480 and 1024x600.
Signed-off-by: Stefan Agner <stefan.ag...@toradex.com>
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
drivers/video/fsl_dcu_fb.c | 61 --
1 file changed, 59 insertions(+), 2 deletions(-)
diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c
index 6e65d84903..85f98dc73c 100644
--- a/drivers/video/fsl_dcu_fb.c
+++ b/drivers/video/fsl_dcu_fb.c
@@ -104,7 +104,7 @@ static struct fb_videomode fsl_dcu_mode_480_272 = {
/*
* This setting is used for Siliconimage SiI9022A HDMI
*/
-static struct fb_videomode fsl_dcu_mode_640_480 = {
+static struct fb_videomode fsl_dcu_cea_mode_640_480 = {
.name = "640x480-60",
.refresh= 60,
.xres = 640,
@@ -120,6 +120,54 @@ static struct fb_videomode fsl_dcu_mode_640_480 = {
.vmode = FB_VMODE_NONINTERLACED,
};
+static struct fb_videomode fsl_dcu_mode_640_480 = {
+ .name = "640x480-60",
+ .refresh= 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = 25175,
+ .left_margin= 40,
+ .right_margin = 24,
+ .upper_margin = 32,
+ .lower_margin = 11,
+ .hsync_len = 96,
+ .vsync_len = 2,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_videomode fsl_dcu_mode_800_480 = {
+ .name = "800x480-60",
+ .refresh= 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 33260,
+ .left_margin= 216,
+ .right_margin = 40,
+ .upper_margin = 35,
+ .lower_margin = 10,
+ .hsync_len = 128,
+ .vsync_len = 2,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_videomode fsl_dcu_mode_1024_600 = {
+ .name = "1024x600-60",
+ .refresh= 60,
+ .xres = 1024,
+ .yres = 600,
+ .pixclock = 48000,
+ .left_margin= 104,
+ .right_margin = 43,
+ .upper_margin = 24,
+ .lower_margin = 20,
+ .hsync_len = 5,
+ .vsync_len = 5,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
/*
* DCU register map
*/
@@ -342,7 +390,16 @@ void *video_hw_init(void)
fsl_dcu_mode_db = _dcu_mode_480_272;
break;
case RESOLUTION(640, 480):
- fsl_dcu_mode_db = _dcu_mode_640_480;
+ if (!strncmp(options, "monitor=hdmi", 12))
+ fsl_dcu_mode_db = _dcu_cea_mode_640_480;
+ else
+ fsl_dcu_mode_db = _dcu_mode_640_480;
+ break;
+ case RESOLUTION(800, 480):
+ fsl_dcu_mode_db = _dcu_mode_800_480;
+ break;
+ case RESOLUTION(1024, 600):
+ fsl_dcu_mode_db = _dcu_mode_1024_600;
break;
default:
printf("unsupported resolution %ux%u\n",
--
2.12.2
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[U-Boot] [PATCH v3 4/6] video: fsl_dcu_fb: Fix DCU_MODE_BLEND_ITER setting
From: Stefan Agner <stefan.ag...@toradex.com> DCU_LAYER_MAX_NUM is currently used for DCU_MODE_BLEND_ITER and it actually overflows the maximum value of BLEND_ITER for Vybrid and LS102XA. Fix this by using a default value of 2. Signed-off-by: Stefan Agner <stefan.ag...@toradex.com> Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com> --- drivers/video/fsl_dcu_fb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c index a922a91fb2..6e65d84903 100644 --- a/drivers/video/fsl_dcu_fb.c +++ b/drivers/video/fsl_dcu_fb.c @@ -294,7 +294,7 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres, DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0)); dcu_write32(>mode, - DCU_MODE_BLEND_ITER(DCU_LAYER_MAX_NUM) | + DCU_MODE_BLEND_ITER(2) | DCU_MODE_RASTER_EN); dcu_write32(>threshold, -- 2.12.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 1/6] Convert CONFIG_FSL_DCU_FB to Kconfig
Rename CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB and convert it to Kconfig. Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com> --- arch/arm/cpu/armv7/ls102xa/soc.c| 2 +- board/freescale/ls1021aiot/Makefile | 2 +- board/freescale/ls1021aqds/Makefile | 2 +- board/freescale/ls1021atwr/Makefile | 2 +- configs/ls1021aqds_ddr4_nor_defconfig | 1 + configs/ls1021aqds_ddr4_nor_lpuart_defconfig| 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig| 1 + configs/ls1021aqds_nor_defconfig| 1 + configs/ls1021aqds_nor_lpuart_defconfig | 1 + configs/ls1021aqds_qspi_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig | 1 + configs/ls1021aqds_sdcard_qspi_defconfig| 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig| 1 + configs/ls1021atwr_nor_defconfig| 1 + configs/ls1021atwr_nor_lpuart_defconfig | 1 + configs/ls1021atwr_qspi_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig| 1 + drivers/video/Kconfig | 7 +++ drivers/video/Makefile | 2 +- include/configs/ls1021aqds.h| 4 +--- include/configs/ls1021atwr.h| 4 +--- scripts/config_whitelist.txt| 1 - 25 files changed, 30 insertions(+), 12 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 52fb6f8d51..b84a1a686a 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -91,7 +91,7 @@ int arch_soc_init(void) out_be32(>qspi_cfg, SCFG_QSPI_CLKSEL); #endif -#ifdef CONFIG_FSL_DCU_FB +#ifdef CONFIG_VIDEO_FSL_DCU_FB out_be32(>pixclkcr, SCFG_PIXCLKCR_PXCKEN); #endif diff --git a/board/freescale/ls1021aiot/Makefile b/board/freescale/ls1021aiot/Makefile index 05709e685c..6b960aa61c 100644 --- a/board/freescale/ls1021aiot/Makefile +++ b/board/freescale/ls1021aiot/Makefile @@ -5,5 +5,5 @@ # obj-y += ls1021aiot.o -obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile index f0390c129f..1e50e468a3 100644 --- a/board/freescale/ls1021aqds/Makefile +++ b/board/freescale/ls1021aqds/Makefile @@ -7,5 +7,5 @@ obj-y += ls1021aqds.o obj-y += ddr.o obj-y += eth.o -obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile index 5238b158d7..d9a2f52f2b 100644 --- a/board/freescale/ls1021atwr/Makefile +++ b/board/freescale/ls1021atwr/Makefile @@ -5,5 +5,5 @@ # obj-y += ls1021atwr.o -obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 8434870af3..5566053ae9 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -43,3 +43,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_VIDEO_FSL_DCU_FB=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index ece220bf94..9582662e53 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -44,3 +44,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_VIDEO_FSL_DCU_FB=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index dc547b5e0d..73f2fb070d 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -57,3 +57,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_VIDEO_FSL_DCU_FB=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index d1760ed742..74e1241974 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -43,5 +43,6 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_RSA=y CONFIG_SPL_RSA=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index 8de90b0757..14a2b7f562 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -44,3 +44,4 @@ CONFIG_US
[U-Boot] [PATCH v3 2/6] video: fsl_dcu_fb: fix framebuffer to the end of memory
From: Stefan Agner <stefan.ag...@toradex.com>
Fix the framebuffer location to the very end of the available memory.
This allows to remove the area from available memory for the kernel,
which in turn allows to display the splash screen through the while
Linux kernel boot process.
Ideas has been taken from the sunxi display driver, e.g.
20779ec3a5 ("sunxi: video: Dynamically reserve framebuffer memory")
Signed-off-by: Stefan Agner <stefan.ag...@toradex.com>
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
drivers/video/Kconfig | 8
drivers/video/fsl_dcu_fb.c | 45 ++---
include/fsl_dcu_fb.h | 1 +
3 files changed, 51 insertions(+), 3 deletions(-)
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 6aab8af1b3..d1b017cfad 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -402,6 +402,14 @@ config VIDEO_FSL_DCU_FB
This enables support for Freescale Display Control Unit (DCU4)
module found on Freescale Vybrid and QorIQ family of SoCs.
+config VIDEO_FSL_DCU_MAX_FB_SIZE_MB
+ int "Freescale DCU framebuffer size"
+ depends on VIDEO_FSL_DCU_FB
+ default 4194304
+ help
+Set maximum framebuffer size to be used for Freescale Display
+Controller Unit (DCU4).
+
config VIDEO_ROCKCHIP
bool "Enable Rockchip video support"
depends on DM_VIDEO
diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c
index d4cd382776..801bf3db95 100644
--- a/drivers/video/fsl_dcu_fb.c
+++ b/drivers/video/fsl_dcu_fb.c
@@ -8,6 +8,7 @@
#include
#include
+#include
#include
#include
#include
@@ -79,6 +80,8 @@
#define BPP_24_RGB888 5
#define BPP_32_ARGB6
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* This setting is used for the TWR_LCD_RGB card
*/
@@ -254,11 +257,19 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres,
struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
unsigned int div, mode;
- /* Memory allocation for framebuffer */
info.screen_size =
info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8);
- info.screen_base = (char *)memalign(ARCH_DMA_MINALIGN,
- roundup(info.screen_size, ARCH_DMA_MINALIGN));
+
+ if (info.screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) {
+ info.screen_size = 0;
+ return -ENOMEM;
+ }
+
+ /* Resever framebuffer at the end of memory */
+ gd->fb_base = gd->bd->bi_dram[0].start +
+ gd->bd->bi_dram[0].size - info.screen_size;
+ info.screen_base = (char *)gd->fb_base;
+
memset(info.screen_base, 0, info.screen_size);
reset_total_layers();
@@ -305,6 +316,11 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres,
return 0;
}
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB;
+}
+
void *video_hw_init(void)
{
static GraphicDevice ctfb;
@@ -363,3 +379,26 @@ void *video_hw_init(void)
return
}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int fsl_dcu_fixedfb_setup(void *blob)
+{
+ u64 start, size;
+ int ret;
+
+ start = gd->bd->bi_dram[0].start;
+ size = gd->bd->bi_dram[0].size - info.screen_size;
+
+ /*
+* Align size on section size (1 MiB).
+*/
+ size &= 0xfff0;
+ ret = fdt_fixup_memory_banks(blob, , , 1);
+ if (ret) {
+ eprintf("Cannot setup fb: Error reserving memory\n");
+ return ret;
+ }
+
+ return 0;
+}
+#endif
diff --git a/include/fsl_dcu_fb.h b/include/fsl_dcu_fb.h
index 42632984d3..67e29e74e6 100644
--- a/include/fsl_dcu_fb.h
+++ b/include/fsl_dcu_fb.h
@@ -9,6 +9,7 @@
int fsl_dcu_init(unsigned int xres, unsigned int yres,
unsigned int pixel_format);
+int fsl_dcu_fixedfb_setup(void *blob);
/* Prototypes for external board-specific functions */
int platform_dcu_init(unsigned int xres, unsigned int yres,
--
2.12.2
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[U-Boot] [PATCH v3 0/6] Introduce DCU support for Vybrid
Hello, This patchset adds support for the Freescale/NXP Display Controller Unit (DCU4) for Vybrid which is found on the LS1021A and Vybrid SoC. Patch series is based on top of latest u-boot master. First patch in the series renames existing CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB and then converts it to Kconfig. All board defconfigs affected by this patch have been compile tested. Patch 2-5 introduce incremental changes for supporting DCU on Vybrid. Patch 6 in the series adds DCU support to Vybrid and has been tested on Toradex Colibri VF61 module. Will appreciate it if the maintainers or users of LS1021 SoC can test this to check and report regressions if any. Changes since v2: 1. Rebase on top of latest u-boot master 2. Drop the fourth patch in earlier series and replace it with a fix for DCU_MODE_BLEND_ITER and use the existing DCU_LAYER_MAX_NUM instead of introducing DCU_TOTAL_LAYER_NUM as earlier incoporating Stefan's feedback. Changes since v1: 1. Rebase of top of latest u-boot master 2. Fix a bug present in v1 patch series which resulted in noisy screen when switching from u-boot to Linux. Patch fixed is second in this series. v1: https://lists.denx.de/pipermail/u-boot/2017-February/280281.html v2: https://www.mail-archive.com/u-boot@lists.denx.de/msg243132.html Thanks & Regards, Sanchayan. Sanchayan Maity (1): Convert CONFIG_FSL_DCU_FB to Kconfig Stefan Agner (5): video: fsl_dcu_fb: fix framebuffer to the end of memory video: fsl_dcu_fb: Enable pixel clock after initialization video: fsl_dcu_fb: Fix DCU_MODE_BLEND_ITER setting video: fsl_dcu_fb: add additional modes for DCU board: toradex: colibri_vf: Add DCU support for Colibri Vybrid arch/arm/cpu/armv7/ls102xa/soc.c | 2 +- arch/arm/include/asm/arch-vf610/crm_regs.h | 14 +++ arch/arm/include/asm/arch-vf610/imx-regs.h | 2 + arch/arm/include/asm/arch-vf610/iomux-vf610.h | 31 ++ arch/arm/include/asm/imx-common/iomux-v3.h | 3 + board/freescale/ls1021aiot/Makefile| 2 +- board/freescale/ls1021aqds/Makefile| 2 +- board/freescale/ls1021atwr/Makefile| 2 +- board/toradex/colibri_vf/Makefile | 1 + board/toradex/colibri_vf/colibri_vf.c | 76 ++--- board/toradex/colibri_vf/dcu.c | 38 +++ configs/colibri_vf_defconfig | 4 + configs/ls1021aqds_ddr4_nor_defconfig | 1 + configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021aqds_nor_defconfig | 1 + configs/ls1021aqds_nor_lpuart_defconfig| 1 + configs/ls1021aqds_qspi_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig| 1 + configs/ls1021aqds_sdcard_qspi_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_nor_defconfig | 1 + configs/ls1021atwr_nor_lpuart_defconfig| 1 + configs/ls1021atwr_qspi_defconfig | 1 + .../ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig| 1 + configs/ls1021atwr_sdcard_ifc_defconfig| 1 + configs/ls1021atwr_sdcard_qspi_defconfig | 1 + drivers/video/Kconfig | 15 +++ drivers/video/Makefile | 2 +- drivers/video/fsl_dcu_fb.c | 121 ++--- include/configs/colibri_vf.h | 13 +++ include/configs/ls1021aqds.h | 4 +- include/configs/ls1021atwr.h | 4 +- include/fsl_dcu_fb.h | 1 + scripts/config_whitelist.txt | 1 - 36 files changed, 313 insertions(+), 41 deletions(-) create mode 100644 board/toradex/colibri_vf/dcu.c -- 2.12.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 4/6] video: fsl_dcu_fb: Update DCU layers for Vybrid
From: Stefan Agner <stefan.ag...@toradex.com>
Users control the graphical content of the panel by manipulating
configuration of elements in DCU4 called layers. The number of
layers is different for Vybrid and LS102XA SoC's. Update this
to reflect for LS102XA accordingly and for use with Vybrid.
Signed-off-by: Stefan Agner <stefan.ag...@toradex.com>
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
arch/arm/include/asm/arch-ls102xa/config.h | 1 +
drivers/video/fsl_dcu_fb.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
b/arch/arm/include/asm/arch-ls102xa/config.h
index 2f7233f2fe..7a909c88af 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -107,6 +107,7 @@
#define CONFIG_SYS_FSL_SRK_LE
#define DCU_LAYER_MAX_NUM 16
+#define DCU_TOTAL_LAYER_NUM16
#ifdef CONFIG_LS102XA
#define CONFIG_USB_MAX_CONTROLLER_COUNT1
diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c
index a922a91fb2..35550afd63 100644
--- a/drivers/video/fsl_dcu_fb.c
+++ b/drivers/video/fsl_dcu_fb.c
@@ -178,7 +178,7 @@ static void reset_total_layers(void)
struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
int i;
- for (i = 0; i < DCU_LAYER_MAX_NUM; i++) {
+ for (i = 0; i < DCU_TOTAL_LAYER_NUM; i++) {
dcu_write32(>ctrldescl[i][0], 0);
dcu_write32(>ctrldescl[i][1], 0);
dcu_write32(>ctrldescl[i][2], 0);
@@ -188,8 +188,10 @@ static void reset_total_layers(void)
dcu_write32(>ctrldescl[i][6], 0);
dcu_write32(>ctrldescl[i][7], 0);
dcu_write32(>ctrldescl[i][8], 0);
+#ifdef CONFIG_LS102XA
dcu_write32(>ctrldescl[i][9], 0);
dcu_write32(>ctrldescl[i][10], 0);
+#endif
}
}
--
2.12.1
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[U-Boot] [PATCH v2 6/6] board: toradex: colibri_vf: Add DCU support for Colibri Vybrid
From: Stefan Agner <stefan.ag...@toradex.com>
The Vybrid SoC family has the same display controller unit (DCU)
like the LS1021A SoC. This patch adds platform data, pinmux defines
and clock control to enable the driver for Toradex Colibri Vybrid
module.
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
arch/arm/include/asm/arch-vf610/crm_regs.h| 14 +
arch/arm/include/asm/arch-vf610/imx-regs.h| 2 +
arch/arm/include/asm/arch-vf610/iomux-vf610.h | 31 +++
arch/arm/include/asm/imx-common/iomux-v3.h| 3 ++
board/toradex/colibri_vf/Makefile | 1 +
board/toradex/colibri_vf/colibri_vf.c | 76 +--
board/toradex/colibri_vf/dcu.c| 38 ++
configs/colibri_vf_defconfig | 4 ++
include/configs/colibri_vf.h | 18 ++-
9 files changed, 169 insertions(+), 18 deletions(-)
create mode 100644 board/toradex/colibri_vf/dcu.c
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h
b/arch/arm/include/asm/arch-vf610/crm_regs.h
index a46e396f1d..73b1dd2f14 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -9,6 +9,8 @@
#ifndef __ASSEMBLY__
+#include
+
/* Clock Controller Module (CCM) */
struct ccm_reg {
u32 ccr;
@@ -150,6 +152,9 @@ struct anadig_reg {
#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7)
+#define CCM_CSCMR1_DCU1_CLK_SEL(1 << 29)
+#define CCM_CSCMR1_DCU0_CLK_SEL(1 << 28)
+
#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET22
#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22)
#define CCM_CSCMR1_QSPI0_CLK_SEL(v)(((v) & 0x3) << 22)
@@ -174,6 +179,13 @@ struct anadig_reg {
#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20)
+#define CCM_CSCDR3_DCU1_EN (1 << 23)
+#define CCM_CSCDR3_DCU1_DIV_MASK (0x7 << 20)
+#define CCM_CSCDR3_DCU1_DIV(v) (((v) & 0x7) << 20)
+#define CCM_CSCDR3_DCU0_EN (1 << 19)
+#define CCM_CSCDR3_DCU0_DIV_MASK (0x7 << 16)
+#define CCM_CSCDR3_DCU0_DIV(v) (((v) & 0x7) << 16)
+
#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET 13
#define CCM_CSCDR3_NFC_PRE_DIV_MASK(0x7 << 13)
#define CCM_CSCDR3_NFC_PRE_DIV(v) (((v) & 0x7) << 13)
@@ -193,6 +205,7 @@ struct anadig_reg {
#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26)
#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8)
#define CCM_CCGR1_PIT_CTRL_MASK(0x3 << 14)
+#define CCM_CCGR1_TCON0_CTRL_MASK (0x3 << 26)
#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8)
#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16)
@@ -203,6 +216,7 @@ struct anadig_reg {
#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26)
#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
#define CCM_CCGR3_SCSC_CTRL_MASK(0x3 << 4)
+#define CCM_CCGR3_DCU0_CTRL_MASK (0x3 << 16)
#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20)
#define CCM_CCGR4_CCM_CTRL_MASK(0x3 << 22)
#define CCM_CCGR4_GPC_CTRL_MASK(0x3 << 24)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index cac68efde2..ca97462c35 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -69,6 +69,7 @@
#define USB_PHY0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050800)
#define USB_PHY1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050C00)
#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
+#define DCU0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00058000)
#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006)
#define SPDIF_BASE_ADDR(AIPS0_BASE_ADDR + 0x00061000)
#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
@@ -98,6 +99,7 @@
#define USBC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00034000)
#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x0005)
#define ENET1_BASE_ADDR(AIPS1_BASE_ADDR + 0x00051000)
+#define DCU1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00058000)
#define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x0006)
#define QSPI0_AMBA_BASE0x2000
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
index a140be05f1..5af071a4db 100644
--- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
+++ b/arch/arm/include/as
[U-Boot] [PATCH v2 1/6] Convert CONFIG_FSL_DCU_FB to Kconfig
Rename CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB and convert it to Kconfig. Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com> --- arch/arm/cpu/armv7/ls102xa/soc.c| 2 +- board/freescale/ls1021aiot/Makefile | 2 +- board/freescale/ls1021aqds/Makefile | 2 +- board/freescale/ls1021atwr/Makefile | 2 +- configs/ls1021aqds_ddr4_nor_defconfig | 1 + configs/ls1021aqds_ddr4_nor_lpuart_defconfig| 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig| 1 + configs/ls1021aqds_nor_defconfig| 1 + configs/ls1021aqds_nor_lpuart_defconfig | 1 + configs/ls1021aqds_qspi_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig | 1 + configs/ls1021aqds_sdcard_qspi_defconfig| 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig| 1 + configs/ls1021atwr_nor_defconfig| 1 + configs/ls1021atwr_nor_lpuart_defconfig | 1 + configs/ls1021atwr_qspi_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig| 1 + drivers/video/Kconfig | 7 +++ drivers/video/Makefile | 2 +- include/configs/ls1021aqds.h| 4 +--- include/configs/ls1021atwr.h| 4 +--- scripts/config_whitelist.txt| 1 - 25 files changed, 30 insertions(+), 12 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 52fb6f8d51..b84a1a686a 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -91,7 +91,7 @@ int arch_soc_init(void) out_be32(>qspi_cfg, SCFG_QSPI_CLKSEL); #endif -#ifdef CONFIG_FSL_DCU_FB +#ifdef CONFIG_VIDEO_FSL_DCU_FB out_be32(>pixclkcr, SCFG_PIXCLKCR_PXCKEN); #endif diff --git a/board/freescale/ls1021aiot/Makefile b/board/freescale/ls1021aiot/Makefile index 05709e685c..6b960aa61c 100644 --- a/board/freescale/ls1021aiot/Makefile +++ b/board/freescale/ls1021aiot/Makefile @@ -5,5 +5,5 @@ # obj-y += ls1021aiot.o -obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile index f0390c129f..1e50e468a3 100644 --- a/board/freescale/ls1021aqds/Makefile +++ b/board/freescale/ls1021aqds/Makefile @@ -7,5 +7,5 @@ obj-y += ls1021aqds.o obj-y += ddr.o obj-y += eth.o -obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile index 5238b158d7..d9a2f52f2b 100644 --- a/board/freescale/ls1021atwr/Makefile +++ b/board/freescale/ls1021atwr/Makefile @@ -5,5 +5,5 @@ # obj-y += ls1021atwr.o -obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 8434870af3..5566053ae9 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -43,3 +43,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_VIDEO_FSL_DCU_FB=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index ece220bf94..9582662e53 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -44,3 +44,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_VIDEO_FSL_DCU_FB=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index dc547b5e0d..73f2fb070d 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -57,3 +57,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_VIDEO_FSL_DCU_FB=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index d1760ed742..74e1241974 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -43,5 +43,6 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_RSA=y CONFIG_SPL_RSA=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index 8de90b0757..14a2b7f562 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -44,3 +44,4 @@ CONFIG_US
[U-Boot] [PATCH v2 5/6] video: fsl_dcu_fb: add additional modes for DCU
From: Stefan Agner <stefan.ag...@toradex.com>
Add common widescreen modes 800x480 and 1024x600.
Signed-off-by: Stefan Agner <stefan.ag...@toradex.com>
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
drivers/video/fsl_dcu_fb.c | 61 --
1 file changed, 59 insertions(+), 2 deletions(-)
diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c
index 35550afd63..a7b7378759 100644
--- a/drivers/video/fsl_dcu_fb.c
+++ b/drivers/video/fsl_dcu_fb.c
@@ -104,7 +104,7 @@ static struct fb_videomode fsl_dcu_mode_480_272 = {
/*
* This setting is used for Siliconimage SiI9022A HDMI
*/
-static struct fb_videomode fsl_dcu_mode_640_480 = {
+static struct fb_videomode fsl_dcu_cea_mode_640_480 = {
.name = "640x480-60",
.refresh= 60,
.xres = 640,
@@ -120,6 +120,54 @@ static struct fb_videomode fsl_dcu_mode_640_480 = {
.vmode = FB_VMODE_NONINTERLACED,
};
+static struct fb_videomode fsl_dcu_mode_640_480 = {
+ .name = "640x480-60",
+ .refresh= 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = 25175,
+ .left_margin= 40,
+ .right_margin = 24,
+ .upper_margin = 32,
+ .lower_margin = 11,
+ .hsync_len = 96,
+ .vsync_len = 2,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_videomode fsl_dcu_mode_800_480 = {
+ .name = "800x480-60",
+ .refresh= 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 33260,
+ .left_margin= 216,
+ .right_margin = 40,
+ .upper_margin = 35,
+ .lower_margin = 10,
+ .hsync_len = 128,
+ .vsync_len = 2,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_videomode fsl_dcu_mode_1024_600 = {
+ .name = "1024x600-60",
+ .refresh= 60,
+ .xres = 1024,
+ .yres = 600,
+ .pixclock = 48000,
+ .left_margin= 104,
+ .right_margin = 43,
+ .upper_margin = 24,
+ .lower_margin = 20,
+ .hsync_len = 5,
+ .vsync_len = 5,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
/*
* DCU register map
*/
@@ -344,7 +392,16 @@ void *video_hw_init(void)
fsl_dcu_mode_db = _dcu_mode_480_272;
break;
case RESOLUTION(640, 480):
- fsl_dcu_mode_db = _dcu_mode_640_480;
+ if (!strncmp(options, "monitor=hdmi", 12))
+ fsl_dcu_mode_db = _dcu_cea_mode_640_480;
+ else
+ fsl_dcu_mode_db = _dcu_mode_640_480;
+ break;
+ case RESOLUTION(800, 480):
+ fsl_dcu_mode_db = _dcu_mode_800_480;
+ break;
+ case RESOLUTION(1024, 600):
+ fsl_dcu_mode_db = _dcu_mode_1024_600;
break;
default:
printf("unsupported resolution %ux%u\n",
--
2.12.1
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[U-Boot] [PATCH v2 3/6] video: fsl_dcu_fb: Enable pixel clock after initialization
From: Stefan Agner <stefan.ag...@toradex.com> When enabling the DCU and pixel clock, the test mode is activated since this is the reset configuration. The test mode immediately shows a red screen on a LCD. A moment later, the DCU gets initialized properly. This patch enables the pixel clock after initialization of the DCU control register. This avoids this initial flicker on LCD screens. While at it change the polarity of pixel clock to display samples data on the rising edge. Signed-off-by: Stefan Agner <stefan.ag...@toradex.com> Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com> --- drivers/video/fsl_dcu_fb.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c index 801bf3db95..a922a91fb2 100644 --- a/drivers/video/fsl_dcu_fb.c +++ b/drivers/video/fsl_dcu_fb.c @@ -41,7 +41,7 @@ #define DCU_VSYN_PARA_BP(x)((x) << 22) #define DCU_VSYN_PARA_PW(x)((x) << 11) #define DCU_VSYN_PARA_FP(x)(x) -#define DCU_SYN_POL_INV_PXCK_FALL (0 << 6) +#define DCU_SYN_POL_INV_PXCK_FALL (1 << 6) #define DCU_SYN_POL_NEG_REMAIN (0 << 5) #define DCU_SYN_POL_INV_VS_LOW (1 << 1) #define DCU_SYN_POL_INV_HS_LOW (1) @@ -191,8 +191,6 @@ static void reset_total_layers(void) dcu_write32(>ctrldescl[i][9], 0); dcu_write32(>ctrldescl[i][10], 0); } - - dcu_write32(>update_mode, DCU_UPDATE_MODE_READREG); } static int layer_ctrldesc_init(int index, u32 pixel_format) @@ -246,8 +244,6 @@ static int layer_ctrldesc_init(int index, u32 pixel_format) dcu_write32(>ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0)); dcu_write32(>ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0)); - dcu_write32(>update_mode, DCU_UPDATE_MODE_READREG); - return 0; } @@ -273,8 +269,6 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres, memset(info.screen_base, 0, info.screen_size); reset_total_layers(); - div = dcu_set_pixel_clock(info.var.pixclock); - dcu_write32(>div_ratio, (div - 1)); dcu_write32(>disp_size, DCU_DISP_SIZE_DELTA_Y(info.var.yres) | @@ -313,6 +307,11 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres, layer_ctrldesc_init(0, pixel_format); + div = dcu_set_pixel_clock(info.var.pixclock); + dcu_write32(>div_ratio, (div - 1)); + + dcu_write32(>update_mode, DCU_UPDATE_MODE_READREG); + return 0; } -- 2.12.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 0/6] Introduce DCU support for Vybrid
Hello, This patchset adds support for the Freescale/NXP Display Controller Unit (DCU4) for Vybrid which is found on the LS1021A and Vybrid SoC. Patch series is based on top of latest u-boot master. First patch in the series renames existing CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB and then converts it to Kconfig. All board defconfigs affected by this patch have been compile tested. Patch 2-5 introduce incremental changes for supporting DCU on Vybrid. Patch 6 in the series adds DCU support to Vybrid and has been tested on Toradex Colibri VF61 module. Will appreciate it if the maintainers or users of LS1021 SoC can test this to check and report regressions if any. Changes since v1: 1. Rebase of top of latest u-boot master 2. Fix a bug present in v1 patch series which resulted in noisy screen when switching from u-boot to Linux. Patch fixed is second in this series. v1: https://lists.denx.de/pipermail/u-boot/2017-February/280281.html Thanks & Regards, Sanchayan. Sanchayan Maity (1): Convert CONFIG_FSL_DCU_FB to Kconfig Stefan Agner (5): video: fsl_dcu_fb: fix framebuffer to the end of memory video: fsl_dcu_fb: Enable pixel clock after initialization video: fsl_dcu_fb: Update DCU layers for Vybrid video: fsl_dcu_fb: add additional modes for DCU board: toradex: colibri_vf: Add DCU support for Colibri Vybrid arch/arm/cpu/armv7/ls102xa/soc.c | 2 +- arch/arm/include/asm/arch-ls102xa/config.h | 1 + arch/arm/include/asm/arch-vf610/crm_regs.h | 14 +++ arch/arm/include/asm/arch-vf610/imx-regs.h | 2 + arch/arm/include/asm/arch-vf610/iomux-vf610.h | 31 ++ arch/arm/include/asm/imx-common/iomux-v3.h | 3 + board/freescale/ls1021aiot/Makefile| 2 +- board/freescale/ls1021aqds/Makefile| 2 +- board/freescale/ls1021atwr/Makefile| 2 +- board/toradex/colibri_vf/Makefile | 1 + board/toradex/colibri_vf/colibri_vf.c | 76 ++--- board/toradex/colibri_vf/dcu.c | 38 +++ configs/colibri_vf_defconfig | 4 + configs/ls1021aqds_ddr4_nor_defconfig | 1 + configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021aqds_nor_defconfig | 1 + configs/ls1021aqds_nor_lpuart_defconfig| 1 + configs/ls1021aqds_qspi_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig| 1 + configs/ls1021aqds_sdcard_qspi_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_nor_defconfig | 1 + configs/ls1021atwr_nor_lpuart_defconfig| 1 + configs/ls1021atwr_qspi_defconfig | 1 + .../ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig| 1 + configs/ls1021atwr_sdcard_ifc_defconfig| 1 + configs/ls1021atwr_sdcard_qspi_defconfig | 1 + drivers/video/Kconfig | 15 +++ drivers/video/Makefile | 2 +- drivers/video/fsl_dcu_fb.c | 123 ++--- include/configs/colibri_vf.h | 18 ++- include/configs/ls1021aqds.h | 4 +- include/configs/ls1021atwr.h | 4 +- include/fsl_dcu_fb.h | 1 + scripts/config_whitelist.txt | 1 - 37 files changed, 319 insertions(+), 43 deletions(-) create mode 100644 board/toradex/colibri_vf/dcu.c -- 2.12.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/6] video: fsl_dcu_fb: fix framebuffer to the end of memory
From: Stefan Agner <stefan.ag...@toradex.com>
Fix the framebuffer location to the very end of the available memory.
This allows to remove the area from available memory for the kernel,
which in turn allows to display the splash screen through the while
Linux kernel boot process.
Ideas has been taken from the sunxi display driver, e.g.
20779ec3a5 ("sunxi: video: Dynamically reserve framebuffer memory")
Signed-off-by: Stefan Agner <stefan.ag...@toradex.com>
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
drivers/video/Kconfig | 8
drivers/video/fsl_dcu_fb.c | 45 ++---
include/fsl_dcu_fb.h | 1 +
3 files changed, 51 insertions(+), 3 deletions(-)
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 6aab8af1b3..d1b017cfad 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -402,6 +402,14 @@ config VIDEO_FSL_DCU_FB
This enables support for Freescale Display Control Unit (DCU4)
module found on Freescale Vybrid and QorIQ family of SoCs.
+config VIDEO_FSL_DCU_MAX_FB_SIZE_MB
+ int "Freescale DCU framebuffer size"
+ depends on VIDEO_FSL_DCU_FB
+ default 4194304
+ help
+Set maximum framebuffer size to be used for Freescale Display
+Controller Unit (DCU4).
+
config VIDEO_ROCKCHIP
bool "Enable Rockchip video support"
depends on DM_VIDEO
diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c
index d4cd382776..801bf3db95 100644
--- a/drivers/video/fsl_dcu_fb.c
+++ b/drivers/video/fsl_dcu_fb.c
@@ -8,6 +8,7 @@
#include
#include
+#include
#include
#include
#include
@@ -79,6 +80,8 @@
#define BPP_24_RGB888 5
#define BPP_32_ARGB6
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* This setting is used for the TWR_LCD_RGB card
*/
@@ -254,11 +257,19 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres,
struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
unsigned int div, mode;
- /* Memory allocation for framebuffer */
info.screen_size =
info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8);
- info.screen_base = (char *)memalign(ARCH_DMA_MINALIGN,
- roundup(info.screen_size, ARCH_DMA_MINALIGN));
+
+ if (info.screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) {
+ info.screen_size = 0;
+ return -ENOMEM;
+ }
+
+ /* Resever framebuffer at the end of memory */
+ gd->fb_base = gd->bd->bi_dram[0].start +
+ gd->bd->bi_dram[0].size - info.screen_size;
+ info.screen_base = (char *)gd->fb_base;
+
memset(info.screen_base, 0, info.screen_size);
reset_total_layers();
@@ -305,6 +316,11 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres,
return 0;
}
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB;
+}
+
void *video_hw_init(void)
{
static GraphicDevice ctfb;
@@ -363,3 +379,26 @@ void *video_hw_init(void)
return
}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int fsl_dcu_fixedfb_setup(void *blob)
+{
+ u64 start, size;
+ int ret;
+
+ start = gd->bd->bi_dram[0].start;
+ size = gd->bd->bi_dram[0].size - info.screen_size;
+
+ /*
+* Align size on section size (1 MiB).
+*/
+ size &= 0xfff0;
+ ret = fdt_fixup_memory_banks(blob, , , 1);
+ if (ret) {
+ eprintf("Cannot setup fb: Error reserving memory\n");
+ return ret;
+ }
+
+ return 0;
+}
+#endif
diff --git a/include/fsl_dcu_fb.h b/include/fsl_dcu_fb.h
index 42632984d3..67e29e74e6 100644
--- a/include/fsl_dcu_fb.h
+++ b/include/fsl_dcu_fb.h
@@ -9,6 +9,7 @@
int fsl_dcu_init(unsigned int xres, unsigned int yres,
unsigned int pixel_format);
+int fsl_dcu_fixedfb_setup(void *blob);
/* Prototypes for external board-specific functions */
int platform_dcu_init(unsigned int xres, unsigned int yres,
--
2.12.1
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[U-Boot] [PATCH v1 4/6] video: fsl_dcu_fb: Update DCU layers for Vybrid
From: Stefan Agner <stefan.ag...@toradex.com>
Users control the graphical content of the panel by manipulating
configuration of elements in DCU4 called layers. The number of
layers is different for Vybrid and LS102XA SoC's. Update this
to reflect for LS102XA accordingly and for use with Vybrid.
Signed-off-by: Stefan Agner <stefan.ag...@toradex.com>
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
arch/arm/include/asm/arch-ls102xa/config.h | 1 +
drivers/video/fsl_dcu_fb.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
b/arch/arm/include/asm/arch-ls102xa/config.h
index 2f7233f2fe..7a909c88af 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -107,6 +107,7 @@
#define CONFIG_SYS_FSL_SRK_LE
#define DCU_LAYER_MAX_NUM 16
+#define DCU_TOTAL_LAYER_NUM16
#ifdef CONFIG_LS102XA
#define CONFIG_USB_MAX_CONTROLLER_COUNT1
diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c
index c6fdedb5cf..22aba7ef48 100644
--- a/drivers/video/fsl_dcu_fb.c
+++ b/drivers/video/fsl_dcu_fb.c
@@ -178,7 +178,7 @@ static void reset_total_layers(void)
struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
int i;
- for (i = 0; i < DCU_LAYER_MAX_NUM; i++) {
+ for (i = 0; i < DCU_TOTAL_LAYER_NUM; i++) {
dcu_write32(>ctrldescl[i][0], 0);
dcu_write32(>ctrldescl[i][1], 0);
dcu_write32(>ctrldescl[i][2], 0);
@@ -188,8 +188,10 @@ static void reset_total_layers(void)
dcu_write32(>ctrldescl[i][6], 0);
dcu_write32(>ctrldescl[i][7], 0);
dcu_write32(>ctrldescl[i][8], 0);
+#ifdef CONFIG_LS102XA
dcu_write32(>ctrldescl[i][9], 0);
dcu_write32(>ctrldescl[i][10], 0);
+#endif
}
}
--
2.11.1
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[U-Boot] [PATCH v1 6/6] board: toradex: colibri_vf: Add DCU support for Colibri Vybrid
From: Stefan Agner <stefan.ag...@toradex.com>
The Vybrid SoC family has the same display controller unit (DCU)
like the LS1021A SoC. This patch adds platform data, pinmux defines
and clock control to enable the driver for Toradex Colibri Vybrid
module.
Signed-off-by: Stefan Agner <stefan.ag...@toradex.com>
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
arch/arm/include/asm/arch-vf610/crm_regs.h| 14 +
arch/arm/include/asm/arch-vf610/imx-regs.h| 2 +
arch/arm/include/asm/arch-vf610/iomux-vf610.h | 31 +++
arch/arm/include/asm/imx-common/iomux-v3.h| 3 ++
board/toradex/colibri_vf/Makefile | 1 +
board/toradex/colibri_vf/colibri_vf.c | 76 +--
board/toradex/colibri_vf/dcu.c| 38 ++
configs/colibri_vf_defconfig | 4 ++
include/configs/colibri_vf.h | 18 ++-
9 files changed, 169 insertions(+), 18 deletions(-)
create mode 100644 board/toradex/colibri_vf/dcu.c
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h
b/arch/arm/include/asm/arch-vf610/crm_regs.h
index a46e396f1d..73b1dd2f14 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -9,6 +9,8 @@
#ifndef __ASSEMBLY__
+#include
+
/* Clock Controller Module (CCM) */
struct ccm_reg {
u32 ccr;
@@ -150,6 +152,9 @@ struct anadig_reg {
#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7)
+#define CCM_CSCMR1_DCU1_CLK_SEL(1 << 29)
+#define CCM_CSCMR1_DCU0_CLK_SEL(1 << 28)
+
#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET22
#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22)
#define CCM_CSCMR1_QSPI0_CLK_SEL(v)(((v) & 0x3) << 22)
@@ -174,6 +179,13 @@ struct anadig_reg {
#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20)
+#define CCM_CSCDR3_DCU1_EN (1 << 23)
+#define CCM_CSCDR3_DCU1_DIV_MASK (0x7 << 20)
+#define CCM_CSCDR3_DCU1_DIV(v) (((v) & 0x7) << 20)
+#define CCM_CSCDR3_DCU0_EN (1 << 19)
+#define CCM_CSCDR3_DCU0_DIV_MASK (0x7 << 16)
+#define CCM_CSCDR3_DCU0_DIV(v) (((v) & 0x7) << 16)
+
#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET 13
#define CCM_CSCDR3_NFC_PRE_DIV_MASK(0x7 << 13)
#define CCM_CSCDR3_NFC_PRE_DIV(v) (((v) & 0x7) << 13)
@@ -193,6 +205,7 @@ struct anadig_reg {
#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26)
#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8)
#define CCM_CCGR1_PIT_CTRL_MASK(0x3 << 14)
+#define CCM_CCGR1_TCON0_CTRL_MASK (0x3 << 26)
#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8)
#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16)
@@ -203,6 +216,7 @@ struct anadig_reg {
#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26)
#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
#define CCM_CCGR3_SCSC_CTRL_MASK(0x3 << 4)
+#define CCM_CCGR3_DCU0_CTRL_MASK (0x3 << 16)
#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20)
#define CCM_CCGR4_CCM_CTRL_MASK(0x3 << 22)
#define CCM_CCGR4_GPC_CTRL_MASK(0x3 << 24)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 9758323433..c080b2f76b 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -69,6 +69,7 @@
#define USB_PHY0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050800)
#define USB_PHY1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050C00)
#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
+#define DCU0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00058000)
#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006)
#define SPDIF_BASE_ADDR(AIPS0_BASE_ADDR + 0x00061000)
#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
@@ -98,6 +99,7 @@
#define USBC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00034000)
#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x0005)
#define ENET1_BASE_ADDR(AIPS1_BASE_ADDR + 0x00051000)
+#define DCU1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00058000)
#define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x0006)
#define QSPI0_AMBA_BASE0x2000
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
index a140be05f1..5af071a4db 100644
--- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
[U-Boot] [PATCH v1 3/6] video: fsl_dcu_fb: Enable pixel clock after initialization
From: Stefan Agner <stefan.ag...@toradex.com> When enabling the DCU and pixel clock, the test mode is activated since this is the reset configuration. The test mode immediately shows a red screen on a LCD. A moment later, the DCU gets initialized properly. This patch enables the pixel clock after initialization of the DCU control register. This avoids this initial flicker on LCD screens. While at it change the polarity of pixel clock to display samples data on the rising edge. Signed-off-by: Stefan Agner <stefan.ag...@toradex.com> Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com> --- drivers/video/fsl_dcu_fb.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c index a456bd17da..c6fdedb5cf 100644 --- a/drivers/video/fsl_dcu_fb.c +++ b/drivers/video/fsl_dcu_fb.c @@ -41,7 +41,7 @@ #define DCU_VSYN_PARA_BP(x)((x) << 22) #define DCU_VSYN_PARA_PW(x)((x) << 11) #define DCU_VSYN_PARA_FP(x)(x) -#define DCU_SYN_POL_INV_PXCK_FALL (0 << 6) +#define DCU_SYN_POL_INV_PXCK_FALL (1 << 6) #define DCU_SYN_POL_NEG_REMAIN (0 << 5) #define DCU_SYN_POL_INV_VS_LOW (1 << 1) #define DCU_SYN_POL_INV_HS_LOW (1) @@ -191,8 +191,6 @@ static void reset_total_layers(void) dcu_write32(>ctrldescl[i][9], 0); dcu_write32(>ctrldescl[i][10], 0); } - - dcu_write32(>update_mode, DCU_UPDATE_MODE_READREG); } static int layer_ctrldesc_init(int index, u32 pixel_format) @@ -246,8 +244,6 @@ static int layer_ctrldesc_init(int index, u32 pixel_format) dcu_write32(>ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0)); dcu_write32(>ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0)); - dcu_write32(>update_mode, DCU_UPDATE_MODE_READREG); - return 0; } @@ -270,8 +266,6 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres, memset(info.screen_base, 0, info.screen_size); reset_total_layers(); - div = dcu_set_pixel_clock(info.var.pixclock); - dcu_write32(>div_ratio, (div - 1)); dcu_write32(>disp_size, DCU_DISP_SIZE_DELTA_Y(info.var.yres) | @@ -310,6 +304,11 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres, layer_ctrldesc_init(0, pixel_format); + div = dcu_set_pixel_clock(info.var.pixclock); + dcu_write32(>div_ratio, (div - 1)); + + dcu_write32(>update_mode, DCU_UPDATE_MODE_READREG); + return 0; } -- 2.11.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 5/6] video: fsl_dcu_fb: add additional modes for DCU
From: Stefan Agner <stefan.ag...@toradex.com>
Add common widescreen modes 800x480 and 1024x600.
Signed-off-by: Stefan Agner <stefan.ag...@toradex.com>
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
drivers/video/fsl_dcu_fb.c | 61 --
1 file changed, 59 insertions(+), 2 deletions(-)
diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c
index 22aba7ef48..6a66e788e0 100644
--- a/drivers/video/fsl_dcu_fb.c
+++ b/drivers/video/fsl_dcu_fb.c
@@ -104,7 +104,7 @@ static struct fb_videomode fsl_dcu_mode_480_272 = {
/*
* This setting is used for Siliconimage SiI9022A HDMI
*/
-static struct fb_videomode fsl_dcu_mode_640_480 = {
+static struct fb_videomode fsl_dcu_cea_mode_640_480 = {
.name = "640x480-60",
.refresh= 60,
.xres = 640,
@@ -120,6 +120,54 @@ static struct fb_videomode fsl_dcu_mode_640_480 = {
.vmode = FB_VMODE_NONINTERLACED,
};
+static struct fb_videomode fsl_dcu_mode_640_480 = {
+ .name = "640x480-60",
+ .refresh= 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = 25175,
+ .left_margin= 40,
+ .right_margin = 24,
+ .upper_margin = 32,
+ .lower_margin = 11,
+ .hsync_len = 96,
+ .vsync_len = 2,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_videomode fsl_dcu_mode_800_480 = {
+ .name = "800x480-60",
+ .refresh= 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 33260,
+ .left_margin= 216,
+ .right_margin = 40,
+ .upper_margin = 35,
+ .lower_margin = 10,
+ .hsync_len = 128,
+ .vsync_len = 2,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_videomode fsl_dcu_mode_1024_600 = {
+ .name = "1024x600-60",
+ .refresh= 60,
+ .xres = 1024,
+ .yres = 600,
+ .pixclock = 48000,
+ .left_margin= 104,
+ .right_margin = 43,
+ .upper_margin = 24,
+ .lower_margin = 20,
+ .hsync_len = 5,
+ .vsync_len = 5,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
/*
* DCU register map
*/
@@ -341,7 +389,16 @@ void *video_hw_init(void)
fsl_dcu_mode_db = _dcu_mode_480_272;
break;
case RESOLUTION(640, 480):
- fsl_dcu_mode_db = _dcu_mode_640_480;
+ if (!strncmp(options, "monitor=hdmi", 12))
+ fsl_dcu_mode_db = _dcu_cea_mode_640_480;
+ else
+ fsl_dcu_mode_db = _dcu_mode_640_480;
+ break;
+ case RESOLUTION(800, 480):
+ fsl_dcu_mode_db = _dcu_mode_800_480;
+ break;
+ case RESOLUTION(1024, 600):
+ fsl_dcu_mode_db = _dcu_mode_1024_600;
break;
default:
printf("unsupported resolution %ux%u\n",
--
2.11.1
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[U-Boot] [PATCH v1 2/6] video: fsl_dcu_fb: fix framebuffer to the end of memory
From: Stefan Agner <stefan.ag...@toradex.com>
Fix the framebuffer location to the very end of the available memory.
This allows to remove the area from available memory for the kernel,
which in turn allows to display the splash screen through the while
Linux kernel boot process.
Ideas has been taken from the sunxi display driver, e.g.
20779ec3a5 ("sunxi: video: Dynamically reserve framebuffer memory")
Signed-off-by: Stefan Agner <stefan.ag...@toradex.com>
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
drivers/video/Kconfig | 8
drivers/video/fsl_dcu_fb.c | 46 +-
include/fsl_dcu_fb.h | 1 +
3 files changed, 50 insertions(+), 5 deletions(-)
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 7097cfa59f..9fea167d0f 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -402,6 +402,14 @@ config VIDEO_FSL_DCU_FB
This enables support for Freescale Display Controller Unit (DCU4)
module found on Freescale Vybrid and QorIQ family of SoC's.
+config VIDEO_FSL_DCU_MAX_FB_SIZE_MB
+ int "Freescale DCU framebuffer size"
+ depends on VIDEO_FSL_DCU_FB
+ default 4194304
+ help
+Set maximum framebuffer size to be used for Freescale Display
+Controller Unit (DCU4).
+
config VIDEO_ROCKCHIP
bool "Enable Rockchip video support"
depends on DM_VIDEO
diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c
index d4cd382776..a456bd17da 100644
--- a/drivers/video/fsl_dcu_fb.c
+++ b/drivers/video/fsl_dcu_fb.c
@@ -8,6 +8,7 @@
#include
#include
+#include
#include
#include
#include
@@ -79,6 +80,8 @@
#define BPP_24_RGB888 5
#define BPP_32_ARGB6
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* This setting is used for the TWR_LCD_RGB card
*/
@@ -254,11 +257,16 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres,
struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
unsigned int div, mode;
- /* Memory allocation for framebuffer */
- info.screen_size =
- info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8);
- info.screen_base = (char *)memalign(ARCH_DMA_MINALIGN,
- roundup(info.screen_size, ARCH_DMA_MINALIGN));
+ if (info.screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) {
+ info.screen_size = 0;
+ return -ENOMEM;
+ }
+
+ /* Resever framebuffer at the end of memory */
+ gd->fb_base = gd->bd->bi_dram[0].start +
+ gd->bd->bi_dram[0].size - info.screen_size;
+ info.screen_base = (char *)gd->fb_base;
+
memset(info.screen_base, 0, info.screen_size);
reset_total_layers();
@@ -305,6 +313,11 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres,
return 0;
}
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB;
+}
+
void *video_hw_init(void)
{
static GraphicDevice ctfb;
@@ -363,3 +376,26 @@ void *video_hw_init(void)
return
}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int fsl_dcu_fixedfb_setup(void *blob)
+{
+ u64 start, size;
+ int ret;
+
+ start = gd->bd->bi_dram[0].start;
+ size = gd->bd->bi_dram[0].size - info.screen_size;
+
+ /*
+* Align size on section size (1 MiB).
+*/
+ size &= 0xfff0;
+ ret = fdt_fixup_memory_banks(blob, , , 1);
+ if (ret) {
+ eprintf("Cannot setup fb: Error reserving memory\n");
+ return ret;
+ }
+
+ return 0;
+}
+#endif
diff --git a/include/fsl_dcu_fb.h b/include/fsl_dcu_fb.h
index 42632984d3..67e29e74e6 100644
--- a/include/fsl_dcu_fb.h
+++ b/include/fsl_dcu_fb.h
@@ -9,6 +9,7 @@
int fsl_dcu_init(unsigned int xres, unsigned int yres,
unsigned int pixel_format);
+int fsl_dcu_fixedfb_setup(void *blob);
/* Prototypes for external board-specific functions */
int platform_dcu_init(unsigned int xres, unsigned int yres,
--
2.11.1
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[U-Boot] [PATCH v1 1/6] Convert CONFIG_FSL_DCU_FB to Kconfig
Rename CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB and convert it to Kconfig. Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com> --- arch/arm/cpu/armv7/ls102xa/soc.c| 2 +- board/freescale/ls1021aiot/Makefile | 2 +- board/freescale/ls1021aqds/Makefile | 2 +- board/freescale/ls1021atwr/Makefile | 2 +- configs/ls1021aqds_ddr4_nor_defconfig | 1 + configs/ls1021aqds_ddr4_nor_lpuart_defconfig| 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig| 1 + configs/ls1021aqds_nor_defconfig| 1 + configs/ls1021aqds_nor_lpuart_defconfig | 1 + configs/ls1021aqds_qspi_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig | 1 + configs/ls1021aqds_sdcard_qspi_defconfig| 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig| 1 + configs/ls1021atwr_nor_defconfig| 1 + configs/ls1021atwr_nor_lpuart_defconfig | 1 + configs/ls1021atwr_qspi_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig| 1 + drivers/video/Kconfig | 7 +++ drivers/video/Makefile | 2 +- include/configs/ls1021aqds.h| 4 +--- include/configs/ls1021atwr.h| 4 +--- scripts/config_whitelist.txt| 1 - 25 files changed, 30 insertions(+), 12 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 52fb6f8d51..b84a1a686a 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -91,7 +91,7 @@ int arch_soc_init(void) out_be32(>qspi_cfg, SCFG_QSPI_CLKSEL); #endif -#ifdef CONFIG_FSL_DCU_FB +#ifdef CONFIG_VIDEO_FSL_DCU_FB out_be32(>pixclkcr, SCFG_PIXCLKCR_PXCKEN); #endif diff --git a/board/freescale/ls1021aiot/Makefile b/board/freescale/ls1021aiot/Makefile index 05709e685c..6b960aa61c 100644 --- a/board/freescale/ls1021aiot/Makefile +++ b/board/freescale/ls1021aiot/Makefile @@ -5,5 +5,5 @@ # obj-y += ls1021aiot.o -obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile index f0390c129f..1e50e468a3 100644 --- a/board/freescale/ls1021aqds/Makefile +++ b/board/freescale/ls1021aqds/Makefile @@ -7,5 +7,5 @@ obj-y += ls1021aqds.o obj-y += ddr.o obj-y += eth.o -obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile index 5238b158d7..d9a2f52f2b 100644 --- a/board/freescale/ls1021atwr/Makefile +++ b/board/freescale/ls1021atwr/Makefile @@ -5,5 +5,5 @@ # obj-y += ls1021atwr.o -obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index ae09ea4992..3e50785d3a 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -41,3 +41,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_VIDEO_FSL_DCU_FB=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index bc6328d5bd..f67d80be5a 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -42,3 +42,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_VIDEO_FSL_DCU_FB=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 31ace140c9..d8f8867ae1 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -51,6 +51,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_OF_LIBFDT=y CONFIG_PCI=y CONFIG_DM_PCI=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 01e1e7304f..7087405dfc 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -38,6 +38,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_OF_LIBFDT=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index 9132482bf9..38230ebcbe 100644 --- a/configs/ls1021aqds_nor_defconfig +
[U-Boot] [PATCH v1 0/6] Introduce DCU support for Vybrid
Hello, This patchset adds support for the Freescale/NXP Display Controller Unit (DCU4) found on the LS1021A and Vybrid SoC. Patch series is based on top of latest u-boot master. First patch in the series renames existing CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB and then converts it to Kconfig. All board defconfigs affected by this patch have been compile tested. Patch 2-5 introduce incremental changes for supporting DCU on Vybrid. Patch 6 in the series adds DCU support to Vybrid and has been tested on Toradex Colibri VF61 module. Will appreciate it if the maintainers or users of LS1021 SoC can test this to check and report regressions if any. Thanks & Regards, Sanchayan. Sanchayan Maity (1): Convert CONFIG_FSL_DCU_FB to Kconfig Stefan Agner (5): video: fsl_dcu_fb: fix framebuffer to the end of memory video: fsl_dcu_fb: Enable pixel clock after initialization video: fsl_dcu_fb: Update DCU layers for Vybrid video: fsl_dcu_fb: add additional modes for DCU board: toradex: colibri_vf: Add DCU support for Colibri Vybrid arch/arm/cpu/armv7/ls102xa/soc.c | 2 +- arch/arm/include/asm/arch-ls102xa/config.h | 1 + arch/arm/include/asm/arch-vf610/crm_regs.h | 14 +++ arch/arm/include/asm/arch-vf610/imx-regs.h | 2 + arch/arm/include/asm/arch-vf610/iomux-vf610.h | 31 ++ arch/arm/include/asm/imx-common/iomux-v3.h | 3 + board/freescale/ls1021aiot/Makefile| 2 +- board/freescale/ls1021aqds/Makefile| 2 +- board/freescale/ls1021atwr/Makefile| 2 +- board/toradex/colibri_vf/Makefile | 1 + board/toradex/colibri_vf/colibri_vf.c | 76 ++--- board/toradex/colibri_vf/dcu.c | 38 +++ configs/colibri_vf_defconfig | 4 + configs/ls1021aqds_ddr4_nor_defconfig | 1 + configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021aqds_nor_defconfig | 1 + configs/ls1021aqds_nor_lpuart_defconfig| 1 + configs/ls1021aqds_qspi_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig| 1 + configs/ls1021aqds_sdcard_qspi_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_nor_defconfig | 1 + configs/ls1021atwr_nor_lpuart_defconfig| 1 + configs/ls1021atwr_qspi_defconfig | 1 + .../ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig| 1 + configs/ls1021atwr_sdcard_ifc_defconfig| 1 + configs/ls1021atwr_sdcard_qspi_defconfig | 1 + drivers/video/Kconfig | 15 +++ drivers/video/Makefile | 2 +- drivers/video/fsl_dcu_fb.c | 124 ++--- include/configs/colibri_vf.h | 18 ++- include/configs/ls1021aqds.h | 4 +- include/configs/ls1021atwr.h | 4 +- include/fsl_dcu_fb.h | 1 + scripts/config_whitelist.txt | 1 - 37 files changed, 318 insertions(+), 45 deletions(-) create mode 100644 board/toradex/colibri_vf/dcu.c -- 2.11.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] configs: colibri_vf: Add fdt_fixup environment variable
u-boot allows modifying a device tree after it is loaded into
memory. Add fdt_fixup hook in u-boot environment which can
facilitate such modifications.
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
include/configs/colibri_vf.h | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index d58145e..be28324 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -99,7 +99,7 @@
"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
"load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \
"load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
- "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define NFS_BOOTCMD \
"nfsargs=ip=:eth0: root=/dev/nfs\0" \
@@ -108,7 +108,7 @@
"${setupargs} ${vidargs}; echo Booting from NFS...;" \
"dhcp ${kernel_addr_r} && " \
"tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
- "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define UBI_BOOTCMD\
"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
@@ -119,7 +119,7 @@
"ubi part ubi && " \
"ubi read ${kernel_addr_r} kernel && " \
"ubi read ${fdt_addr_r} dtb && " \
- "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot"
@@ -131,6 +131,7 @@
"kernel_file=zImage\0" \
"fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \
"fdt_board=eval-v3\0" \
+ "fdt_fixup=;\0" \
"defargs=\0" \
"console=ttyLP0\0" \
"setup=setenv setupargs " \
--
2.10.2
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[U-Boot] [PATCH] colibri_vf: Read kernel and device tree from static UBI volumes
Our update scripts write the kernel and device tree in seperate
UBI volumes. This allows to use a lot less UBI/UBIFS support in
U-Boot, which should lower the risk of hitting bugs in this area.
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
include/configs/colibri_vf.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index be773a3..4c82fed 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -114,9 +114,9 @@
"ubiboot=run setup; " \
"setenv bootargs ${defargs} ${ubiargs} ${mtdparts} " \
"${setupargs} ${vidargs}; echo Booting from NAND...; " \
- "ubi part ubi && ubifsmount ubi0:rootfs && " \
- "ubifsload ${kernel_addr_r} /boot/${kernel_file} && " \
- "ubifsload ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
+ "ubi part ubi && " \
+ "ubi read ${kernel_addr_r} kernel && " \
+ "ubi read ${fdt_addr_r} dtb && " \
"bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot"
--
2.10.2
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[U-Boot] [PATCH v2 3/4] ARM: dts: vf-colibri: Enable USB device tree node for Colibri Vybrid
Enable USB device tree node for Toradex Colibri Vybrid module.
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
arch/arm/dts/vf-colibri.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/dts/vf-colibri.dtsi b/arch/arm/dts/vf-colibri.dtsi
index dc52748..c2f104a 100644
--- a/arch/arm/dts/vf-colibri.dtsi
+++ b/arch/arm/dts/vf-colibri.dtsi
@@ -21,6 +21,17 @@
};
};
+ {
+ dr_mode = "otg";
+ fsl,cdet-gpio = < 6 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+ {
+ dr_mode = "host";
+ status = "okay";
+};
+
{
status = "okay";
};
--
2.9.2
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[U-Boot] [PATCH v2 4/4] configs: colibri_vf_defconfig: Enable USB driver model for Colibri Vybrid
Enable USB driver model for Toradex Colibri Vybrid modules. Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com> --- configs/colibri_vf_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index 986cec4..5017c7d 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y CONFIG_FSL_LPUART=y CONFIG_FSL_DSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y -- 2.9.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/4] ARM: dts: vf: Add device tree node for USB on Vybrid
Add device tree node for USB peripheral on Vybrid.
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
arch/arm/dts/vf.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi
index 1530d2f..d7d21a3 100644
--- a/arch/arm/dts/vf.dtsi
+++ b/arch/arm/dts/vf.dtsi
@@ -4,6 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+ or X11
*/
/include/ "skeleton.dtsi"
+#include
/ {
aliases {
@@ -20,6 +21,8 @@
serial5 =
spi0 =
spi1 =
+ ehci0 =
+ ehci1 =
};
soc {
@@ -113,6 +116,12 @@
reg = <0x400ff100 0x40>;
#gpio-cells = <2>;
};
+
+ ehci0: ehci@40034000 {
+ compatible = "fsl,vf610-usb";
+ reg = <0x40034000 0x800>;
+ status = "disabled";
+ };
};
aips1: aips-bus@4008 {
@@ -133,6 +142,11 @@
status = "disabled";
};
+ ehci1: ehci@400b4000 {
+ compatible = "fsl,vf610-usb";
+ reg = <0x400b4000 0x800>;
+ status = "disabled";
+ };
};
};
};
--
2.9.2
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[U-Boot] [PATCH v2 0/4] Migrate Vybrid USB driver to driver model
Hello, This is the second version of the patchset for migrating Vybrid USB driver to driver model. Compare to the first version, this version takes care of dr_mode property and correctly handles OTG as well when gpio is specified for use as ID detection pin. This is an essential requirement for OTG as Vybrid USB controller is not a true OTG though it can be configured as either host or device. The ID pin which is unique for OTG operation is not present on Vybrid. The problem with client that I was observing was related to sequence numbers. While trying to implement the OTG functionality I observed that if during probe of USB0 if it returns ENODEV, the probe of USB1 provides a sequence number of 0 while we expect 1. The code relies on sequence numbers for initialising the appropriate peripherals. I use the bind operation to force a sequence number. This also seems to solve the problems I was having with USB client and mentioned in the previous version of the patchset. Host and client functionality are both functional with this patch. Patch series is based on top of latest u-boot master at the moment of this writing. Tested on Toradex Colibri Vybrid VF61 module. Thanks to Lukasz and Stefan for their comments. V1 Patches: [1]. https://patchwork.ozlabs.org/patch/655370/ [2]. https://patchwork.ozlabs.org/patch/655371/ [3]. https://patchwork.ozlabs.org/patch/655372/ [4]. https://patchwork.ozlabs.org/patch/655373/ Sanchayan Maity (4): usb: host: ehci-vf: Migrate Vybrid USB to driver model ARM: dts: vf: Add device tree node for USB on Vybrid ARM: dts: vf-colibri: Enable USB device tree node for Colibri Vybrid configs: colibri_vf_defconfig: Enable USB driver model for Colibri Vybrid arch/arm/dts/vf-colibri.dtsi | 11 +++ arch/arm/dts/vf.dtsi | 14 +++ configs/colibri_vf_defconfig | 1 + drivers/usb/host/ehci-vf.c | 208 +-- 4 files changed, 227 insertions(+), 7 deletions(-) -- 2.9.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/4] usb: host: ehci-vf: Migrate Vybrid USB to driver model
Add driver model support for Vybrid USB driver.
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
drivers/usb/host/ehci-vf.c | 208 +++--
1 file changed, 201 insertions(+), 7 deletions(-)
diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c
index 61789dd..f6f9efb 100644
--- a/drivers/usb/host/ehci-vf.c
+++ b/drivers/usb/host/ehci-vf.c
@@ -8,16 +8,20 @@
*/
#include
+#include
#include
#include
#include
#include
+#include
#include
#include
#include
#include
#include
#include
+#include
+#include
#include "ehci.h"
@@ -32,6 +36,8 @@
#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
#define UCMD_RESET (1 << 1) /* controller reset */
+DECLARE_GLOBAL_DATA_PTR;
+
static const unsigned phy_bases[] = {
USB_PHY0_BASE_ADDR,
USB_PHY1_BASE_ADDR,
@@ -131,24 +137,39 @@ int __weak board_ehci_hcd_init(int port)
return 0;
}
+int ehci_vf_common_init(struct usb_ehci *ehci, int index)
+{
+ int ret;
+
+ /* Do board specific initialisation */
+ ret = board_ehci_hcd_init(index);
+ if (ret)
+ return ret;
+
+ usb_power_config(index);
+ usb_oc_config(index);
+ usb_internal_phy_clock_gate(index);
+ usb_phy_enable(index, ehci);
+
+ return 0;
+}
+
+#ifndef CONFIG_DM_USB
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
enum usb_init_type type;
+ int ret;
if (index >= ARRAY_SIZE(nc_reg_bases))
return -EINVAL;
ehci = (struct usb_ehci *)nc_reg_bases[index];
- /* Do board specific initialisation */
- board_ehci_hcd_init(index);
-
- usb_power_config(index);
- usb_oc_config(index);
- usb_internal_phy_clock_gate(index);
- usb_phy_enable(index, ehci);
+ ret = ehci_vf_common_init(index);
+ if (ret)
+ return ret;
*hccr = (struct ehci_hccr *)((uint32_t)>caplength);
*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
@@ -175,3 +196,176 @@ int ehci_hcd_stop(int index)
{
return 0;
}
+#else
+/* Possible port types (dual role mode) */
+enum dr_mode {
+ DR_MODE_NONE = 0,
+ DR_MODE_HOST, /* supports host operation */
+ DR_MODE_DEVICE, /* supports device operation */
+ DR_MODE_OTG,/* supports both */
+};
+
+struct ehci_vf_priv_data {
+ struct ehci_ctrl ctrl;
+ struct usb_ehci *ehci;
+ struct gpio_desc cdet_gpio;
+ enum usb_init_type init_type;
+ enum dr_mode dr_mode;
+ u32 portnr;
+};
+
+static int vf_usb_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ehci_vf_priv_data *priv = dev_get_priv(dev);
+ const void *dt_blob = gd->fdt_blob;
+ int node = dev->of_offset;
+ const char *mode;
+
+ priv->portnr = dev->seq;
+
+ priv->ehci = (struct usb_ehci *)dev_get_addr(dev);
+ mode = fdt_getprop(dt_blob, node, "dr_mode", NULL);
+ if (mode) {
+ if (0 == strcmp(mode, "host")) {
+ priv->dr_mode = DR_MODE_HOST;
+ priv->init_type = USB_INIT_HOST;
+ } else if (0 == strcmp(mode, "peripheral")) {
+ priv->dr_mode = DR_MODE_DEVICE;
+ priv->init_type = USB_INIT_DEVICE;
+ } else if (0 == strcmp(mode, "otg")) {
+ priv->dr_mode = DR_MODE_OTG;
+ /*
+* We set init_type to device by default when OTG
+* mode is requested. If a valid gpio is provided
+* we will switch the init_type based on the state
+* of the gpio pin.
+*/
+ priv->init_type = USB_INIT_DEVICE;
+ } else {
+ debug("%s: Cannot decode dr_mode '%s'\n",
+ __func__, mode);
+ return -EINVAL;
+ }
+ } else {
+ priv->dr_mode = DR_MODE_HOST;
+ priv->init_type = USB_INIT_HOST;
+ }
+
+ if (priv->dr_mode == DR_MODE_OTG) {
+ gpio_request_by_name_nodev(dt_blob, node, "fsl,cdet-gpio", 0,
+ >cdet_gpio, GPIOD_IS_IN);
+ if (dm_gpio_is_valid(>cdet_gpio)) {
+ if (dm_gpio_get_value(>cdet_gpio))
+ priv->init_type = USB_INIT_DEVICE;
+ else
+ priv->init_type = USB_INIT_HOST;
+ }
+ }
+
+ return 0;
+}
+
+static int vf_init_after_reset(s
[U-Boot] [PATCH] cmd: dfu: Add error handling for failed registration
Without this, if g_dnl_register() fails, DFU code continues on
blindly and crashes. This fix makes it simply print an error
message instead.
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
cmd/dfu.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/cmd/dfu.c b/cmd/dfu.c
index d8aae26..e19d69c 100644
--- a/cmd/dfu.c
+++ b/cmd/dfu.c
@@ -54,7 +54,12 @@ static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, char
* const argv[])
int controller_index = simple_strtoul(usb_controller, NULL, 0);
board_usb_init(controller_index, USB_INIT_DEVICE);
g_dnl_clear_detach();
- g_dnl_register("usb_dnl_dfu");
+ ret = g_dnl_register("usb_dnl_dfu");
+ if (ret) {
+ error("g_dnl_register failed");
+ return CMD_RET_FAILURE;
+ }
+
while (1) {
if (g_dnl_detach()) {
/*
--
2.9.2
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[U-Boot] [PATCH v1 2/4] ARM: dts: vf: Add device tree node for USB on Vybrid
Add device tree node for USB peripheral on Vybrid.
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
arch/arm/dts/vf.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi
index 1530d2f..951d321 100644
--- a/arch/arm/dts/vf.dtsi
+++ b/arch/arm/dts/vf.dtsi
@@ -20,6 +20,8 @@
serial5 =
spi0 =
spi1 =
+ ehci0 =
+ ehci1 =
};
soc {
@@ -113,6 +115,12 @@
reg = <0x400ff100 0x40>;
#gpio-cells = <2>;
};
+
+ ehci0: ehci0@40034000 {
+ compatible = "fsl,vf610-usb";
+ reg = <0x40034000 0x800>;
+ status = "disabled";
+ };
};
aips1: aips-bus@4008 {
@@ -133,6 +141,11 @@
status = "disabled";
};
+ ehci1: ehci1@400b4000 {
+ compatible = "fsl,vf610-usb";
+ reg = <0x400b4000 0x800>;
+ status = "disabled";
+ };
};
};
};
--
2.9.2
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[U-Boot] [PATCH v1 4/4] configs: colibri_vf_defconfig: Enable USB driver model for Colibri Vybrid
Enable USB driver model for Toradex Colibri Vybrid modules. Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com> --- configs/colibri_vf_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index 986cec4..5017c7d 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y CONFIG_FSL_LPUART=y CONFIG_FSL_DSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y -- 2.9.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 3/4] ARM: dts: vf-colibri: Enable USB device tree node for Colibri Vybrid
Enable USB device tree node for Toradex Colibri Vybrid module.
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
arch/arm/dts/vf-colibri.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/vf-colibri.dtsi b/arch/arm/dts/vf-colibri.dtsi
index dc52748..e7d4c01 100644
--- a/arch/arm/dts/vf-colibri.dtsi
+++ b/arch/arm/dts/vf-colibri.dtsi
@@ -21,6 +21,16 @@
};
};
+ {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+ {
+ dr_mode = "host";
+ status = "okay";
+};
+
{
status = "okay";
};
--
2.9.2
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[U-Boot] [PATCH v1 1/4] usb: host: ehci-vf: Migrate Vybrid USB to driver model
Add driver model support for Vybrid USB driver.
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
Hello,
I am trying to migrate the Vybrid USB driver to driver model.
Patches are based on top of uboot master branch. With this
implementation, host works perfectly fine on both USB ports
but I have problems using it in client mode.
I tried DFU to test client mode and I get the following
Colibri VFxx # version
U-Boot 2016.09-rc1-00235-g4e8c122 (Aug 03 2016 - 17:07:48 +0530)
arm-linux-gnueabihf-gcc (Linaro GCC 5.2-2015.11-2) 5.2.1 20151005
GNU ld (GNU Binutils) 2.25.0 Linaro 2015_10
Colibri VFxx # dfu 0 nand 4
using id 'nand0,0'
using id 'nand0,1'
using id 'nand0,3'
g_dnl_register: failed!, error: -19
data abort
pc : [<8ff80f18>] lr : [<8ff612a9>]
reloc pc : [<3f431f18>]lr : [<3f4122a9>]
sp : 8fd15000 ip : fp : 2710
r10: 8ffb50cc r9 : 8fd16ee8 r8 : 8ffbc574
r7 : r6 : r5 : r4 :
r3 : f4b9 r2 : 8000 r1 : 0001 r0 :
Flags: nZCv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
resetting ...
It seems to return ENODEV from usb_setup_ehci_gadget after calling
uclass_find_device_by_seq. I am not sure what I am missing in the
current implementation. Can someone point me in the correct direction?
Since host works on both ports I would assume the device tree nodes
are correct.
Tried to look in documentation and usb-info.txt mentions that gadget
framework does not use driver model. Does this imply I cannot use
any usb gadget functionality if I am using USB DM? However the function
usb_gadget_register_driver in ci_udc.c does have a CONFIG_DM_USB and
calls into usb_setup_ehci_gadget which is in usb-uclass.c.
Regards,
Sanchayan.
---
drivers/usb/host/ehci-vf.c | 123 ++---
1 file changed, 117 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c
index 61789dd..8c5c593 100644
--- a/drivers/usb/host/ehci-vf.c
+++ b/drivers/usb/host/ehci-vf.c
@@ -8,6 +8,7 @@
*/
#include
+#include
#include
#include
#include
@@ -131,6 +132,24 @@ int __weak board_ehci_hcd_init(int port)
return 0;
}
+int ehci_vf_common_init(struct usb_ehci *ehci, int index)
+{
+ int ret;
+
+ /* Do board specific initialisation */
+ ret = board_ehci_hcd_init(index);
+ if (ret)
+ return ret;
+
+ usb_power_config(index);
+ usb_oc_config(index);
+ usb_internal_phy_clock_gate(index);
+ usb_phy_enable(index, ehci);
+
+ return 0;
+}
+
+#ifndef CONFIG_DM_USB
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
@@ -143,12 +162,9 @@ int ehci_hcd_init(int index, enum usb_init_type init,
ehci = (struct usb_ehci *)nc_reg_bases[index];
/* Do board specific initialisation */
- board_ehci_hcd_init(index);
-
- usb_power_config(index);
- usb_oc_config(index);
- usb_internal_phy_clock_gate(index);
- usb_phy_enable(index, ehci);
+ ret = ehci_vf_common_init(index);
+ if (ret)
+ return ret;
*hccr = (struct ehci_hccr *)((uint32_t)>caplength);
*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
@@ -175,3 +191,98 @@ int ehci_hcd_stop(int index)
{
return 0;
}
+#else
+struct ehci_vf_priv_data {
+ struct ehci_ctrl ctrl;
+ struct usb_ehci *ehci;
+ enum usb_init_type init_type;
+ int portnr;
+};
+
+static int vf_init_after_reset(struct ehci_ctrl *dev)
+{
+ struct ehci_vf_priv_data *priv = dev->priv;
+ enum usb_init_type type = priv->init_type;
+ struct usb_ehci *ehci = priv->ehci;
+ int ret;
+
+ ret = ehci_vf_common_init(priv->ehci, priv->portnr);
+ if (ret)
+ return ret;
+
+ if (type == USB_INIT_DEVICE)
+ return 0;
+
+ setbits_le32(>usbmode, CM_HOST);
+ writel((PORT_PTS_UTMI | PORT_PTS_PTW), >portsc);
+ setbits_le32(>portsc, USB_EN);
+
+ mdelay(10);
+
+ return 0;
+}
+
+static const struct ehci_ops vf_ehci_ops = {
+ .init_after_reset = vf_init_after_reset
+};
+
+static int ehci_usb_probe(struct udevice *dev)
+{
+ struct usb_platdata *plat = dev_get_platdata(dev);
+ struct usb_ehci *ehci = (struct usb_ehci *)dev_get_addr(dev);
+ struct ehci_vf_priv_data *priv = dev_get_priv(dev);
+ struct ehci_hccr *hccr;
+ struct ehci_hcor *hcor;
+ int ret;
+
+ priv->ehci = ehci;
+ priv->portnr = dev->seq;
+ priv->init_type = plat->init_type;
+
+ ret = ehci_vf_common_init(ehci, priv->portnr);
+ if (ret)
+ return ret;
+
+ if (priv->init_type == USB_INIT_HOST) {
+ setbits_le32(>usbmode, CM_HOST);
+ writel((PORT
[U-Boot] [PATCH v5] colibri_vf: Add board_usb_phy_mode function
Add board_usb_phy_mode function for detecting whether a port is
being used as host or client using a GPIO. On Colibri Vybrid we
provide GPIO 102 for this very same purpose.
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
Changes since v4:
No need to break after return.
Changes since v3:
Return USB_INIT_DEVICE or USB_INIT_HOST after checking for
the GPIO state to account for the fact that the previous
logic breaks in case if the enum for USB mode were to ever
be changed.
Add comments based on Stefan's feedback.
Changes since v2:
Instead of returning 0 from board_usb_phy_mode return it as
USB_INIT_HOST.
Changes since v1:
Move the GPIO request call to the board_init function as all
further calls to board_usb_phy_mode will actually result in the
gpio_request failing.
---
board/toradex/colibri_vf/colibri_vf.c | 33 -
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/board/toradex/colibri_vf/colibri_vf.c
b/board/toradex/colibri_vf/colibri_vf.c
index a6d1c5b..c65ccb3 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -34,6 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
#define USB_PEN_GPIO 83
+#define USB_CDET_GPIO 102
static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
/* levelling */
@@ -92,6 +94,7 @@ static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
static const iomux_v3_cfg_t usb_pads[] = {
VF610_PAD_PTD4__GPIO_83,
+ VF610_PAD_PTC29__GPIO_102,
};
int dram_init(void)
@@ -280,7 +283,6 @@ static void setup_iomux_gpio(void)
VF610_PAD_PTB23__GPIO_93,
VF610_PAD_PTB26__GPIO_96,
VF610_PAD_PTB28__GPIO_98,
- VF610_PAD_PTC29__GPIO_102,
VF610_PAD_PTC30__GPIO_103,
VF610_PAD_PTA7__GPIO_134,
};
@@ -509,6 +511,10 @@ int board_init(void)
setbits_le32(>sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
+#ifdef CONFIG_USB_EHCI_VF
+ gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
+#endif
+
return 0;
}
@@ -554,4 +560,29 @@ int board_ehci_hcd_init(int port)
}
return 0;
}
+
+int board_usb_phy_mode(int port)
+{
+ switch (port) {
+ case 0:
+ /*
+* Port 0 is used only in client mode on Colibri Vybrid modules
+* Check for state of USB client gpio pin and accordingly return
+* USB_INIT_DEVICE or USB_INIT_HOST.
+*/
+ if (gpio_get_value(USB_CDET_GPIO))
+ return USB_INIT_DEVICE;
+ else
+ return USB_INIT_HOST;
+ case 1:
+ /* Port 1 is used only in host mode on Colibri Vybrid modules */
+ return USB_INIT_HOST;
+ default:
+ /*
+* There are only two USB controllers on Vybrid. Ideally we will
+* not reach here. However return USB_INIT_HOST if we do.
+*/
+ return USB_INIT_HOST;
+ }
+}
#endif
--
2.6.2
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[U-Boot] [PATCH v4] colibri_vf: Add board_usb_phy_mode function
Add board_usb_phy_mode function for detecting whether a port is
being used as host or client using a GPIO. On Colibri Vybrid we
provide GPIO 102 for this very same purpose.
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
Changes since v3:
Return USB_INIT_DEVICE or USB_INIT_HOST after checking for
the GPIO state to account for the fact that the previous
logic breaks in case if the enum for USB mode were to ever
be changed.
Add comments based on Stefan's feedback.
Changes since v2:
Instead of returning 0 from board_usb_phy_mode return it as
USB_INIT_HOST.
Changes since v1:
Move the GPIO request call to the board_init function as all
further calls to board_usb_phy_mode will actually result in the
gpio_request failing.
---
board/toradex/colibri_vf/colibri_vf.c | 36 ++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/board/toradex/colibri_vf/colibri_vf.c
b/board/toradex/colibri_vf/colibri_vf.c
index a6d1c5b..b1a3375 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -34,6 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
#define USB_PEN_GPIO 83
+#define USB_CDET_GPIO 102
static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
/* levelling */
@@ -92,6 +94,7 @@ static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
static const iomux_v3_cfg_t usb_pads[] = {
VF610_PAD_PTD4__GPIO_83,
+ VF610_PAD_PTC29__GPIO_102,
};
int dram_init(void)
@@ -280,7 +283,6 @@ static void setup_iomux_gpio(void)
VF610_PAD_PTB23__GPIO_93,
VF610_PAD_PTB26__GPIO_96,
VF610_PAD_PTB28__GPIO_98,
- VF610_PAD_PTC29__GPIO_102,
VF610_PAD_PTC30__GPIO_103,
VF610_PAD_PTA7__GPIO_134,
};
@@ -509,6 +511,10 @@ int board_init(void)
setbits_le32(>sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
+#ifdef CONFIG_USB_EHCI_VF
+ gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
+#endif
+
return 0;
}
@@ -554,4 +560,32 @@ int board_ehci_hcd_init(int port)
}
return 0;
}
+
+int board_usb_phy_mode(int port)
+{
+ switch (port) {
+ case 0:
+ /*
+* Port 0 is used only in client mode on Colibri Vybrid modules
+* Check for state of USB client gpio pin and accordingly return
+* USB_INIT_DEVICE or USB_INIT_HOST.
+*/
+ if (gpio_get_value(USB_CDET_GPIO))
+ return USB_INIT_DEVICE;
+ else
+ return USB_INIT_HOST;
+ break;
+ case 1:
+ /* Port 1 is used only in host mode on Colibri Vybrid modules */
+ return USB_INIT_HOST;
+ break;
+ default:
+ /*
+* There are only two USB controllers on Vybrid. Ideally we will
+* not reach here. However return USB_INIT_HOST if we do.
+*/
+ return USB_INIT_HOST;
+ break;
+ }
+}
#endif
--
2.6.2
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[U-Boot] [PATCH v3] colibri_vf: Add board_usb_phy_mode function
Add board_usb_phy_mode function for detecting whether a port is
being used as host or client using a GPIO. On Colibri Vybrid we
provide the GPIO 102 for this very same purpose.
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
Changes since v1:
Move the GPIO request call to the board_init function as all
further calls to board_usb_phy_mode will actually result in the
gpio_request failing.
Changes since v2:
Instead of returning 0 from board_usb_phy_mode return it as
USB_INIT_HOST.
---
board/toradex/colibri_vf/colibri_vf.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/board/toradex/colibri_vf/colibri_vf.c
b/board/toradex/colibri_vf/colibri_vf.c
index a6d1c5b..9878671 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -34,6 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
#define USB_PEN_GPIO 83
+#define USB_CDET_GPIO 102
static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
/* levelling */
@@ -92,6 +94,7 @@ static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
static const iomux_v3_cfg_t usb_pads[] = {
VF610_PAD_PTD4__GPIO_83,
+ VF610_PAD_PTC29__GPIO_102,
};
int dram_init(void)
@@ -280,7 +283,6 @@ static void setup_iomux_gpio(void)
VF610_PAD_PTB23__GPIO_93,
VF610_PAD_PTB26__GPIO_96,
VF610_PAD_PTB28__GPIO_98,
- VF610_PAD_PTC29__GPIO_102,
VF610_PAD_PTC30__GPIO_103,
VF610_PAD_PTA7__GPIO_134,
};
@@ -509,6 +511,10 @@ int board_init(void)
setbits_le32(>sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
+#ifdef CONFIG_USB_EHCI_VF
+ gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
+#endif
+
return 0;
}
@@ -554,4 +560,19 @@ int board_ehci_hcd_init(int port)
}
return 0;
}
+
+int board_usb_phy_mode(int port)
+{
+ switch (port) {
+ case 0:
+ return gpio_get_value(USB_CDET_GPIO);
+ break;
+ case 1:
+ return USB_INIT_HOST;
+ break;
+ default:
+ return USB_INIT_HOST;
+ break;
+ }
+}
#endif
--
2.6.2
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[U-Boot] [PATCH v2] colibri_vf: Add board_usb_phy_mode function
Add board_usb_phy_mode function for detecting whether a port is
being used as host or client using a GPIO. On Colibri Vybrid we
provide the GPIO 102 for this very same purpose.
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
Changes since v1:
Move the GPIO request call to the board_init function as all
further calls to board_usb_phy_mode will actually result in the
gpio_request failing.
---
board/toradex/colibri_vf/colibri_vf.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/board/toradex/colibri_vf/colibri_vf.c
b/board/toradex/colibri_vf/colibri_vf.c
index a6d1c5b..69274e5 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -34,6 +34,7 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
#define USB_PEN_GPIO 83
+#define USB_CDET_GPIO 102
static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
/* levelling */
@@ -92,6 +93,7 @@ static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
static const iomux_v3_cfg_t usb_pads[] = {
VF610_PAD_PTD4__GPIO_83,
+ VF610_PAD_PTC29__GPIO_102,
};
int dram_init(void)
@@ -280,7 +282,6 @@ static void setup_iomux_gpio(void)
VF610_PAD_PTB23__GPIO_93,
VF610_PAD_PTB26__GPIO_96,
VF610_PAD_PTB28__GPIO_98,
- VF610_PAD_PTC29__GPIO_102,
VF610_PAD_PTC30__GPIO_103,
VF610_PAD_PTA7__GPIO_134,
};
@@ -509,6 +510,10 @@ int board_init(void)
setbits_le32(>sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
+#ifdef CONFIG_USB_EHCI_VF
+ gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
+#endif
+
return 0;
}
@@ -554,4 +559,19 @@ int board_ehci_hcd_init(int port)
}
return 0;
}
+
+int board_usb_phy_mode(int port)
+{
+ switch (port) {
+ case 0:
+ return gpio_get_value(USB_CDET_GPIO);
+ break;
+ case 1:
+ return 0;
+ break;
+ default:
+ return 0;
+ break;
+ }
+}
#endif
--
2.6.2
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[U-Boot] [PATCH 3/3] colibri_vf: Add board_usb_phy_mode function
Add board_usb_phy_mode function for detecting whether a port is
being used as host or client using a GPIO. On Colibri Vybrid we
provide the GPIO 102 for the very same purpose.
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
board/toradex/colibri_vf/colibri_vf.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/board/toradex/colibri_vf/colibri_vf.c
b/board/toradex/colibri_vf/colibri_vf.c
index a6d1c5b..fd90ef2 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -34,6 +34,7 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
#define USB_PEN_GPIO 83
+#define USB_CDET_GPIO 102
static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
/* levelling */
@@ -92,6 +93,7 @@ static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
static const iomux_v3_cfg_t usb_pads[] = {
VF610_PAD_PTD4__GPIO_83,
+ VF610_PAD_PTC29__GPIO_102,
};
int dram_init(void)
@@ -280,7 +282,6 @@ static void setup_iomux_gpio(void)
VF610_PAD_PTB23__GPIO_93,
VF610_PAD_PTB26__GPIO_96,
VF610_PAD_PTB28__GPIO_98,
- VF610_PAD_PTC29__GPIO_102,
VF610_PAD_PTC30__GPIO_103,
VF610_PAD_PTA7__GPIO_134,
};
@@ -554,4 +555,20 @@ int board_ehci_hcd_init(int port)
}
return 0;
}
+
+int board_usb_phy_mode(int port)
+{
+ switch (port) {
+ case 0:
+ gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
+ return gpio_get_value(USB_CDET_GPIO);
+ break;
+ case 1:
+ return 0;
+ break;
+ default:
+ return 0;
+ break;
+ }
+}
#endif
--
2.6.2
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[U-Boot] [PATCH 1/3] usb: host: ehci-vf: Remove hardcoded USB host client configuration
The current ehci-vf USB driver for Vybrid hardcodes the USB host and client functionality. Remove this. Reported-by: Santhosh Kumar Janardhanam <santhosh...@hcl.com> Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com> --- drivers/usb/host/ehci-vf.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c index 98e0fc6..351e0fb 100644 --- a/drivers/usb/host/ehci-vf.c +++ b/drivers/usb/host/ehci-vf.c @@ -134,11 +134,6 @@ int ehci_hcd_init(int index, enum usb_init_type init, if (index >= ARRAY_SIZE(nc_reg_bases)) return -EINVAL; - if (init == USB_INIT_DEVICE && index == 1) - return -ENODEV; - if (init == USB_INIT_HOST && index == 0) - return -ENODEV; - ehci = (struct usb_ehci *)nc_reg_bases[index]; /* Do board specific initialisation */ -- 2.6.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] usb: host: ehci-vf: Implement board_usb_phy_mode weak function
Add board_usb_phy_mode weak function on similar lines to ehci-mx6.
However since Vybrid USB does not have a true OTG, make this weak
functon just return 0. The function is supposed to be implemented
by the individual boards using a GPIO for providing the OTG pin
functionality.
Signed-off-by: Sanchayan Maity <maitysancha...@gmail.com>
---
There seems to be a problem here. As per DFU's help note,
the first argument to dfu is the USB controller.
So if dfu 1 nand 2 is run, I would expect the ehci_hcd_init
function's first index argument to recieve 1. However this
does not seem to be the case. Not sure if I am understanding
something wrongly here. Is this expected?
Currently because of this even though I did like dfu 1 nand 2
to bail out, it does not. I tried tracing the code from do_dfu
but I have yet to get from where ehci_hcd_init is getting called
in the call chain.
All seems to be well when using usb start.
---
drivers/usb/host/ehci-vf.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c
index 351e0fb..335e303 100644
--- a/drivers/usb/host/ehci-vf.c
+++ b/drivers/usb/host/ehci-vf.c
@@ -121,6 +121,11 @@ static void usb_oc_config(int index)
setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
}
+int __weak board_usb_phy_mode(int port)
+{
+ return 0;
+}
+
int __weak board_ehci_hcd_init(int port)
{
return 0;
@@ -130,6 +135,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
+ enum usb_init_type type;
if (index >= ARRAY_SIZE(nc_reg_bases))
return -EINVAL;
@@ -148,6 +154,10 @@ int ehci_hcd_init(int index, enum usb_init_type init,
*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+ type = board_usb_phy_mode(index);
+ if (type != init)
+ return -ENODEV;
+
if (init == USB_INIT_DEVICE) {
setbits_le32(>usbmode, CM_DEVICE);
writel((PORT_PTS_UTMI | PORT_PTS_PTW), >portsc);
--
2.6.2
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[U-Boot] [PATCH] colibri_vf: Increase console IO buffer size to 1024
Increase console IO buffer size to 1024 from the previous value of 256. The previous value was too short for editing environment variables like ubiboot from the console. Signed-off-by: Sanchayan Maity maitysancha...@gmail.com --- include/configs/colibri_vf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index ace31a5..17418c6 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -183,7 +183,7 @@ #define CONFIG_SYS_PROMPT_HUSH_PS2 #define CONFIG_SYS_PROMPT Colibri VFxx # #undef CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE \ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -- 2.4.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 7/7] colibri_vf: Enable USB support for Colibri Vybrid
Enable USB support on Toradex Colibri Vybrid Modules.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
board/toradex/colibri_vf/colibri_vf.c | 24 +++
include/configs/colibri_vf.h | 37 +++
2 files changed, 61 insertions(+)
diff --git a/board/toradex/colibri_vf/colibri_vf.c
b/board/toradex/colibri_vf/colibri_vf.c
index e7bc6c1..31ebb19 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -216,6 +216,14 @@ static void clock_init(void)
clrsetbits_le32(ccm-ccgr10, CCM_REG_CTRL_MASK,
CCM_CCGR10_NFC_CTRL_MASK);
+#ifdef CONFIG_CI_UDC
+ setbits_le32(ccm-ccgr1, CCM_CCGR1_USBC0_CTRL_MASK);
+#endif
+
+#ifdef CONFIG_USB_EHCI
+ setbits_le32(ccm-ccgr7, CCM_CCGR7_USBC1_CTRL_MASK);
+#endif
+
clrsetbits_le32(anadig-pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE |
ANADIG_PLL5_CTRL_DIV_SELECT);
@@ -359,3 +367,19 @@ int checkboard(void)
return 0;
}
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+ unsigned short usb_pid;
+
+ put_unaligned(CONFIG_TRDX_VID, dev-idVendor);
+
+ if (is_colibri_vf61())
+ usb_pid = CONFIG_TRDX_PID_COLIBRI_VF61IT;
+ else
+ usb_pid = CONFIG_TRDX_PID_COLIBRI_VF50IT;
+
+ put_unaligned(usb_pid, dev-idProduct);
+
+ return 0;
+}
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 84ffbe8..414600a 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -146,6 +146,8 @@
#define CONFIG_BOOTCOMMAND run ubiboot; run sdboot; run nfsboot
+#define DFU_ALT_NAND_INFO vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4
+
#define CONFIG_EXTRA_ENV_SETTINGS \
kernel_addr_r=0x8200\0 \
fdt_addr_r=0x8400\0 \
@@ -165,6 +167,7 @@
source ${loadaddr}\0 \
setupdate=run setsdupdate || run setusbupdate\0 \
mtdparts= MTDPARTS_DEFAULT \0 \
+ dfu_alt_info= DFU_ALT_NAND_INFO \0 \
SD_BOOTCMD \
NFS_BOOTCMD \
UBI_BOOTCMD
@@ -231,4 +234,38 @@
#define CONFIG_SYS_CACHELINE_SIZE 32
+/* USB Host Support */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_VF
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+/* USB Client Support */
+#define CONFIG_USB_GADGET
+#define CONFIG_CI_UDC
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_TRDX_VID 0x1B67
+#define CONFIG_TRDX_PID_COLIBRI_VF50 0x0016
+#define CONFIG_TRDX_PID_COLIBRI_VF61 0x0017
+#define CONFIG_TRDX_PID_COLIBRI_VF61IT 0x0018
+#define CONFIG_TRDX_PID_COLIBRI_VF50IT 0x0019
+#define CONFIG_G_DNL_MANUFACTURERToradex
+#define CONFIG_G_DNL_VENDOR_NUM CONFIG_TRDX_VID
+#define CONFIG_G_DNL_PRODUCT_NUM CONFIG_TRDX_PID_COLIBRI_VF50
+
+/* USB DFU */
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_CMD_DFU
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_NAND
+#define CONFIG_DFU_MMC
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024 * 1024)
+
+/* USB Storage */
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_CMD_USB_MASS_STORAGE
+
#endif /* __CONFIG_H */
--
2.3.5
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[U-Boot] [PATCH v3 0/7] Add support for Colibri Vybrid Modules
Hello,
This is the third version of the patchset which adds support for the
Toradex Colibri Vybrid VF50 and VF61 modules. Boot up has been tested
using the serial loader over UART. Compile tested for vf610twr_defconfig
and vf610twr_nand_defconfig as well.
First patch in the series refactors the DDR related code for use by both
the tower board and colibri modules. It also introduces a DDR3 based
JEDEC timing structure.
Second third and fourth patch in this series are improvement patches
related to RTC, SoC/CPU detection and caches.
Fifth patch introduces USB support for Vybrid modules. Much of the code
is similar to the ehci-mx6 driver. Both host and client modes are working
and DFU has also been tested with client. Currently, we restrict the
ports to be in one of host and client mode.
Sixth patch adds the actual support for the Colibri modules.
Comments and feedback are most welcome. Thanks for the feedback till
now.
The patchset is based and tested on the latest master branch as of
this writing.
Discussion on the version 2 of the patchset can be found at the below
link:
https://www.mail-archive.com/u-boot@lists.denx.de/msg168727.html
Discussion on the version 1 of the patchset can be found at the below
link:
https://www.mail-archive.com/u-boot@lists.denx.de/msg168136.html
Changes since v2:
- Rework the USB driver to use register + offset method in light of
discussion which Fabio Estevam pointed out instead of the regular
struct{} method which v2 used. The discussion is at the below link:
https://www.marc.info/?l=u-bootm=142609602127309w=2
- Reorder the patchset, putting the USB support in the end and add an
additional patch for adding USB support to Colibri modules. By chance
if more discussions happen on the USB support, this allows picking up
of atleast the first patches on which no issues have been reported so
far.
- The register definitions have been moved under arch/arm/include/asm/
imx-common in the regs-usbphy.h file. This was agreed on after
discussion with Marek and some input from Peter Chen. Since it is not
clear if SoC's other than Freescale's use the Sigmatel Phy's which seem
to be use in iMX/VF/MXS, put the USH PHY register definitions in
imx-common rather than include/usb in a chipidea specific file.
- Remove setting of a PLL divisor select which was added for USB but is
actually not required considering default value. It also seems to break
USB after my latest rebase. The file in question concerning the change
is colibri_vf.c. PLL divisor selects the PLL Multiplication factor which
by default is 0, setting Fout = Fref * 20 giving 480MHz. The earlier
patch set this to 1 giving Fout = Fref * 22 where Fref = 24MHz.
- Rebased on the latest master branch.
Changes since v1:
- Rework the USB driver to use register offsets using the regular
struct {} method
- Some cleanups and fixes in the sixth patch for the colibri_vf.h file
which takes care of environment variables in uboot
- Purge some useless defines in the fifth and sixth patch which were
related to USB.
- Sanchayan.
Sanchayan Maity (5):
ARM: vf610: Move DDR3 initialization to imx-common
ARM: vf610: Add SoC and CPU type detection
ARM: vf610: Initial integration for Colibri VF50/VF61
usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
colibri_vf: Enable USB support for Colibri Vybrid
Stefan Agner (2):
ARM: vf610: Enable external 32KHz oscillator
ARM: vf610: Enable caches
arch/arm/Kconfig | 5 +
arch/arm/cpu/armv7/vf610/generic.c| 45 ++-
arch/arm/imx-common/Makefile | 3 +
arch/arm/imx-common/ddrmc-vf610.c | 278 +++
arch/arm/include/asm/arch-vf610/crm_regs.h| 11 +
arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 72 +
arch/arm/include/asm/arch-vf610/imx-regs.h| 36 ++-
arch/arm/include/asm/imx-common/regs-usbphy.h | 26 ++
board/freescale/vf610twr/vf610twr.c | 295 +---
board/toradex/colibri_vf/Kconfig | 18 ++
board/toradex/colibri_vf/MAINTAINERS | 6 +
board/toradex/colibri_vf/Makefile | 7 +
board/toradex/colibri_vf/colibri_vf.c | 382 ++
board/toradex/colibri_vf/imximage.cfg | 17 ++
configs/colibri_vf_defconfig | 3 +
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ehci-vf.c| 164 +++
include/configs/colibri_vf.h | 271 ++
18 files changed, 1405 insertions(+), 235 deletions(-)
create mode 100644 arch/arm/imx-common/ddrmc-vf610.c
create mode 100644 arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
create mode 100644 arch/arm/include/asm/imx-common/regs-usbphy.h
create mode 100644 board/toradex/colibri_vf/Kconfig
create mode 100644 board/toradex/colibri_vf/MAINTAINERS
create mode 100644 board/toradex/colibri_vf/Makefile
create mode 100644 board/toradex/colibri_vf
[U-Boot] [PATCH v3 5/7] ARM: vf610: Initial integration for Colibri VF50/VF61
This adds initial support for Colibri VF50/VF61 based on Freescale Vybrid SoC. - CPU clocked at 396/500 MHz - DDR3 at 396MHz - for VF50, use PLL2 as memory clock (synchronous mode) - for VF61, use PLL1 as memory clock (asynchronous mode) - Console on UART0 (Colibri UART_A) - Ethernet on FEC1 - PLL5 based RMII clocking (E.g. No external crystal) - UART_A and UART_C I/O muxing - Boot from NAND by default Tested on Colibri VF50/VF61 booting using serial loader over UART. Signed-off-by: Sanchayan Maity maitysancha...@gmail.com --- arch/arm/Kconfig | 5 + arch/arm/include/asm/arch-vf610/imx-regs.h | 5 + board/toradex/colibri_vf/Kconfig | 18 ++ board/toradex/colibri_vf/MAINTAINERS | 6 + board/toradex/colibri_vf/Makefile | 7 + board/toradex/colibri_vf/colibri_vf.c | 361 + board/toradex/colibri_vf/imximage.cfg | 17 ++ configs/colibri_vf_defconfig | 3 + include/configs/colibri_vf.h | 234 +++ 9 files changed, 656 insertions(+) create mode 100644 board/toradex/colibri_vf/Kconfig create mode 100644 board/toradex/colibri_vf/MAINTAINERS create mode 100644 board/toradex/colibri_vf/Makefile create mode 100644 board/toradex/colibri_vf/colibri_vf.c create mode 100644 board/toradex/colibri_vf/imximage.cfg create mode 100644 configs/colibri_vf_defconfig create mode 100644 include/configs/colibri_vf.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7ed0e20..fb41f53 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -617,6 +617,10 @@ config TARGET_VF610TWR bool Support vf610twr select CPU_V7 +config TARGET_COLIBRI_VF + bool Support Colibri VF50/61 + select CPU_V7 + config ZYNQ bool Xilinx Zynq Platform select CPU_V7 @@ -875,6 +879,7 @@ source board/ti/ti814x/Kconfig source board/ti/ti816x/Kconfig source board/timll/devkit3250/Kconfig source board/toradex/colibri_pxa270/Kconfig +source board/toradex/colibri_vf/Kconfig source board/tqc/tqma6/Kconfig source board/trizepsiv/Kconfig source board/ttcontrol/vision2/Kconfig diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index a5908ca..bf41971 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -263,6 +263,11 @@ #define SRC_SRSR_WDOG_M4 (0x1 4) #define SRC_SRSR_WDOG_A5 (0x1 3) #define SRC_SRSR_POR_RST (0x1 0) +#define SRC_SBMR2_BMOD_MASK (0x3 24) +#define SRC_SBMR2_BMOD_SHIFT24 +#define SRC_SBMR2_BMOD_FUSES0x0 +#define SRC_SBMR2_BMOD_SERIAL 0x1 +#define SRC_SBMR2_BMOD_RCON 0x2 /* Slow Clock Source Controller Module (SCSC) */ #define SCSC_SOSC_CTR_SOSC_EN0x1 diff --git a/board/toradex/colibri_vf/Kconfig b/board/toradex/colibri_vf/Kconfig new file mode 100644 index 000..2c3cb30 --- /dev/null +++ b/board/toradex/colibri_vf/Kconfig @@ -0,0 +1,18 @@ +if TARGET_COLIBRI_VF + +config SYS_CPU + default armv7 + +config SYS_BOARD + default colibri_vf + +config SYS_VENDOR + default toradex + +config SYS_SOC + default vf610 + +config SYS_CONFIG_NAME + default colibri_vf + +endif diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS new file mode 100644 index 000..551c575 --- /dev/null +++ b/board/toradex/colibri_vf/MAINTAINERS @@ -0,0 +1,6 @@ +Colibri VFxx +M: Stefan Agner stefan.ag...@toradex.com +S: Maintained +F: board/toradex/colibri_vf/ +F: include/configs/colibri_vf.h +F: configs/colibri_vf_defconfig diff --git a/board/toradex/colibri_vf/Makefile b/board/toradex/colibri_vf/Makefile new file mode 100644 index 000..c7e5134 --- /dev/null +++ b/board/toradex/colibri_vf/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := colibri_vf.o diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c new file mode 100644 index 000..e7bc6c1 --- /dev/null +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -0,0 +1,361 @@ +/* + * Copyright 2015 Toradex, Inc. + * + * Based on vf610twr.c: + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include common.h +#include asm/io.h +#include asm/arch/imx-regs.h +#include asm/arch/iomux-vf610.h +#include asm/arch/ddrmc-vf610.h +#include asm/arch/crm_regs.h +#include asm/arch/clock.h +#include mmc.h +#include fsl_esdhc.h +#include miiphy.h +#include netdev.h +#include i2c.h +#include g_dnl.h + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE) + +#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP
[U-Boot] [PATCH v3 1/7] ARM: vf610: Move DDR3 initialization to imx-common
In order to avoid code duplication, move the DDR3 initialization to the
common place under imx-common. Currently ROW_DIFF and COL_DIFF can be
chosen from the board file. The JEDEC timings are specified using a
common ddr3_jedec_timings structure.
Signed-off-by: Stefan Agner ste...@agner.ch
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/imx-common/Makefile | 3 +
arch/arm/imx-common/ddrmc-vf610.c | 278 +
arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 72 +++
arch/arm/include/asm/arch-vf610/imx-regs.h| 4 +-
board/freescale/vf610twr/vf610twr.c | 282 +-
5 files changed, 408 insertions(+), 231 deletions(-)
create mode 100644 arch/arm/imx-common/ddrmc-vf610.c
create mode 100644 arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 606482f..b9f1ca4 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -22,6 +22,9 @@ ifeq ($(SOC),$(filter $(SOC),mx6))
obj-$(CONFIG_CMD_SATA) += sata.o
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
endif
+ifeq ($(SOC),$(filter $(SOC),vf610))
+obj-y += ddrmc-vf610.o
+endif
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
diff --git a/arch/arm/imx-common/ddrmc-vf610.c
b/arch/arm/imx-common/ddrmc-vf610.c
new file mode 100644
index 000..e462631
--- /dev/null
+++ b/arch/arm/imx-common/ddrmc-vf610.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright 2015 Toradex, Inc.
+ *
+ * Based on vf610twr:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm/io.h
+#include asm/arch/imx-regs.h
+#include asm/arch/iomux-vf610.h
+#include asm/arch/ddrmc-vf610.h
+
+void ddrmc_setup_iomux(void)
+{
+ static const iomux_v3_cfg_t ddr_pads[] = {
+ VF610_PAD_DDR_A15__DDR_A_15,
+ VF610_PAD_DDR_A14__DDR_A_14,
+ VF610_PAD_DDR_A13__DDR_A_13,
+ VF610_PAD_DDR_A12__DDR_A_12,
+ VF610_PAD_DDR_A11__DDR_A_11,
+ VF610_PAD_DDR_A10__DDR_A_10,
+ VF610_PAD_DDR_A9__DDR_A_9,
+ VF610_PAD_DDR_A8__DDR_A_8,
+ VF610_PAD_DDR_A7__DDR_A_7,
+ VF610_PAD_DDR_A6__DDR_A_6,
+ VF610_PAD_DDR_A5__DDR_A_5,
+ VF610_PAD_DDR_A4__DDR_A_4,
+ VF610_PAD_DDR_A3__DDR_A_3,
+ VF610_PAD_DDR_A2__DDR_A_2,
+ VF610_PAD_DDR_A1__DDR_A_1,
+ VF610_PAD_DDR_A0__DDR_A_0,
+ VF610_PAD_DDR_BA2__DDR_BA_2,
+ VF610_PAD_DDR_BA1__DDR_BA_1,
+ VF610_PAD_DDR_BA0__DDR_BA_0,
+ VF610_PAD_DDR_CAS__DDR_CAS_B,
+ VF610_PAD_DDR_CKE__DDR_CKE_0,
+ VF610_PAD_DDR_CLK__DDR_CLK_0,
+ VF610_PAD_DDR_CS__DDR_CS_B_0,
+ VF610_PAD_DDR_D15__DDR_D_15,
+ VF610_PAD_DDR_D14__DDR_D_14,
+ VF610_PAD_DDR_D13__DDR_D_13,
+ VF610_PAD_DDR_D12__DDR_D_12,
+ VF610_PAD_DDR_D11__DDR_D_11,
+ VF610_PAD_DDR_D10__DDR_D_10,
+ VF610_PAD_DDR_D9__DDR_D_9,
+ VF610_PAD_DDR_D8__DDR_D_8,
+ VF610_PAD_DDR_D7__DDR_D_7,
+ VF610_PAD_DDR_D6__DDR_D_6,
+ VF610_PAD_DDR_D5__DDR_D_5,
+ VF610_PAD_DDR_D4__DDR_D_4,
+ VF610_PAD_DDR_D3__DDR_D_3,
+ VF610_PAD_DDR_D2__DDR_D_2,
+ VF610_PAD_DDR_D1__DDR_D_1,
+ VF610_PAD_DDR_D0__DDR_D_0,
+ VF610_PAD_DDR_DQM1__DDR_DQM_1,
+ VF610_PAD_DDR_DQM0__DDR_DQM_0,
+ VF610_PAD_DDR_DQS1__DDR_DQS_1,
+ VF610_PAD_DDR_DQS0__DDR_DQS_0,
+ VF610_PAD_DDR_RAS__DDR_RAS_B,
+ VF610_PAD_DDR_WE__DDR_WE_B,
+ VF610_PAD_DDR_ODT1__DDR_ODT_0,
+ VF610_PAD_DDR_ODT0__DDR_ODT_1,
+ VF610_PAD_DDR_RESETB,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
+}
+
+void ddrmc_phy_init(void)
+{
+ struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+ writel(DDRMC_PHY_DQ_TIMING, ddrmr-phy[0]);
+ writel(DDRMC_PHY_DQ_TIMING, ddrmr-phy[16]);
+ writel(DDRMC_PHY_DQ_TIMING, ddrmr-phy[32]);
+
+ writel(DDRMC_PHY_DQS_TIMING, ddrmr-phy[1]);
+ writel(DDRMC_PHY_DQS_TIMING, ddrmr-phy[17]);
+
+ writel(DDRMC_PHY_CTRL, ddrmr-phy[2]);
+ writel(DDRMC_PHY_CTRL, ddrmr-phy[18]);
+ writel(DDRMC_PHY_CTRL, ddrmr-phy[34]);
+
+ writel(DDRMC_PHY_MASTER_CTRL, ddrmr-phy[3]);
+ writel(DDRMC_PHY_MASTER_CTRL, ddrmr-phy[19]);
+ writel(DDRMC_PHY_MASTER_CTRL, ddrmr-phy[35]);
+
+ writel(DDRMC_PHY_SLAVE_CTRL, ddrmr-phy[4]);
+ writel(DDRMC_PHY_SLAVE_CTRL, ddrmr-phy[20]);
+ writel(DDRMC_PHY_SLAVE_CTRL, ddrmr-phy[36]);
+
+ /* LPDDR2
[U-Boot] [PATCH v3 4/7] ARM: vf610: Enable caches
From: Stefan Agner ste...@agner.ch
Enables caches which provides a rather huge speedup of the boot loader.
Also mark the on-chip RAM as cachable since this is the area U-Boot runs
from.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/cpu/armv7/vf610/generic.c | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/cpu/armv7/vf610/generic.c
b/arch/arm/cpu/armv7/vf610/generic.c
index 3bdc221..1bb9b8e 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -342,3 +342,19 @@ int get_clocks(void)
#endif
return 0;
}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ enum dcache_option option = DCACHE_WRITETHROUGH;
+#else
+ enum dcache_option option = DCACHE_WRITEBACK;
+#endif
+ dcache_enable();
+ icache_enable();
+
+/* Enable caching on OCRAM */
+ mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
+}
+#endif
--
2.3.5
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[U-Boot] [PATCH v3 2/7] ARM: vf610: Enable external 32KHz oscillator
From: Stefan Agner ste...@agner.ch
Enable the SCSC (Slow Clock Source Controller) and select the external
32KHz oscillator. This improves the accuracy of the RTC.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/include/asm/arch-vf610/crm_regs.h | 1 +
arch/arm/include/asm/arch-vf610/imx-regs.h | 11 ++-
board/freescale/vf610twr/vf610twr.c| 13 -
3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h
b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 724682c..78708e2 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -199,6 +199,7 @@ struct anadig_reg {
#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 24)
#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 26)
#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
+#define CCM_CCGR3_SCSC_CTRL_MASK(0x3 4)
#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 20)
#define CCM_CCGR4_CCM_CTRL_MASK(0x3 22)
#define CCM_CCGR4_GPC_CTRL_MASK(0x3 24)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 866b303..aa60031 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -65,7 +65,7 @@
#define QSPI0_BASE_ADDR(AIPS0_BASE_ADDR + 0x00044000)
#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005)
-#define SCSCM_BASE_ADDR(AIPS0_BASE_ADDR + 0x00052000)
+#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006)
#define SPDIF_BASE_ADDR(AIPS0_BASE_ADDR + 0x00061000)
#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
@@ -264,6 +264,9 @@
#define SRC_SRSR_WDOG_A5 (0x1 3)
#define SRC_SRSR_POR_RST (0x1 0)
+/* Slow Clock Source Controller Module (SCSC) */
+#define SCSC_SOSC_CTR_SOSC_EN0x1
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include asm/types.h
@@ -448,6 +451,12 @@ struct mscm_ir {
u16 rsvd3[848];
};
+/* SCSC */
+struct scsc_reg {
+ u32 sirc_ctr;
+ u32 sosc_ctr;
+};
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/board/freescale/vf610twr/vf610twr.c
b/board/freescale/vf610twr/vf610twr.c
index eb27542..4160acd 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -227,7 +227,7 @@ static void clock_init(void)
CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
CCM_CCGR2_QSPI0_CTRL_MASK);
clrsetbits_le32(ccm-ccgr3, CCM_REG_CTRL_MASK,
- CCM_CCGR3_ANADIG_CTRL_MASK);
+ CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
clrsetbits_le32(ccm-ccgr4, CCM_REG_CTRL_MASK,
CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
@@ -308,9 +308,20 @@ int board_early_init_f(void)
int board_init(void)
{
+ struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
+
/* address of boot parameters */
gd-bd-bi_boot_params = PHYS_SDRAM + 0x100;
+ /*
+* Enable external 32K Oscillator
+*
+* The internal clock experiences significant drift
+* so we must use the external oscillator in order
+* to maintain correct time in the hwclock
+*/
+ setbits_le32(scsc-sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
+
return 0;
}
--
2.3.5
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[U-Boot] [PATCH v3 3/7] ARM: vf610: Add SoC and CPU type detection
Vybrid product family consists of several rather similar SoC which
can be determined by softare during boot time. This allows use of
variable ${soc} for Linux device tree files. Detect VF5xx CPU's by
reading the CPU count register. We can determine the second number
of the CPU type (VF6x0) which indicates the presence of a L2 cache.
Signed-off-by: Stefan Agner ste...@agner.ch
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/cpu/armv7/vf610/generic.c | 29 +++--
arch/arm/include/asm/arch-vf610/imx-regs.h | 12
2 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/vf610/generic.c
b/arch/arm/cpu/armv7/vf610/generic.c
index 92aaad9..3bdc221 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -18,6 +18,8 @@
DECLARE_GLOBAL_DATA_PTR;
#endif
+static char soc_type[] = xx0;
+
#ifdef CONFIG_MXC_OCOTP
void enable_ocotp_clk(unsigned char enable)
{
@@ -284,14 +286,37 @@ static char *get_reset_cause(void)
int print_cpuinfo(void)
{
- printf(CPU: Freescale Vybrid VF610 at %d MHz\n,
- mxc_get_clock(MXC_ARM_CLK) / 100);
+ printf(CPU: Freescale Vybrid VF%s at %d MHz\n,
+ soc_type, mxc_get_clock(MXC_ARM_CLK) / 100);
printf(Reset cause: %s\n, get_reset_cause());
return 0;
}
#endif
+int arch_cpu_init(void)
+{
+ struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
+
+ soc_type[0] = mscm-cpxcount ? '6' : '5'; /*Dual Core = VF6x0 */
+ soc_type[1] = mscm-cpxcfg1 ? '1' : '0'; /* L2 Cache = VFx10 */
+
+ return 0;
+}
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ char soc[6];
+
+ strcat(soc, vf);
+ strcat(soc, soc_type);
+ setenv(soc, soc);
+
+ return 0;
+}
+#endif
+
int cpu_eth_init(bd_t *bis)
{
int rc = -ENODEV;
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index aa60031..a5908ca 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -457,6 +457,18 @@ struct scsc_reg {
u32 sosc_ctr;
};
+/* MSCM */
+struct mscm {
+ u32 cpxtype;
+ u32 cpxnum;
+ u32 cpxmaster;
+ u32 cpxcount;
+ u32 cpxcfg0;
+ u32 cpxcfg1;
+ u32 cpxcfg2;
+ u32 cpxcfg3;
+};
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_IMX_REGS_H__ */
--
2.3.5
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[U-Boot] [PATCH v3 7/7] colibri_vf: Enable USB support for Colibri Vybrid
Enable USB support on Toradex Colibri Vybrid Modules.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
board/toradex/colibri_vf/colibri_vf.c | 25 +--
include/configs/colibri_vf.h | 37 +++
2 files changed, 60 insertions(+), 2 deletions(-)
diff --git a/board/toradex/colibri_vf/colibri_vf.c
b/board/toradex/colibri_vf/colibri_vf.c
index e7bc6c1..054e6f9 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -197,7 +197,8 @@ static void clock_init(void)
clrsetbits_le32(ccm-ccgr0, CCM_REG_CTRL_MASK,
CCM_CCGR0_UART0_CTRL_MASK);
clrsetbits_le32(ccm-ccgr1, CCM_REG_CTRL_MASK,
- CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
+ CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK |
+ CCM_CCGR1_USBC0_CTRL_MASK);
clrsetbits_le32(ccm-ccgr2, CCM_REG_CTRL_MASK,
CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
@@ -210,15 +211,19 @@ static void clock_init(void)
clrsetbits_le32(ccm-ccgr6, CCM_REG_CTRL_MASK,
CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
clrsetbits_le32(ccm-ccgr7, CCM_REG_CTRL_MASK,
- CCM_CCGR7_SDHC1_CTRL_MASK);
+ CCM_CCGR7_SDHC1_CTRL_MASK | CCM_CCGR7_USBC1_CTRL_MASK);
clrsetbits_le32(ccm-ccgr9, CCM_REG_CTRL_MASK,
CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
clrsetbits_le32(ccm-ccgr10, CCM_REG_CTRL_MASK,
CCM_CCGR10_NFC_CTRL_MASK);
+ clrsetbits_le32(anadig-pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS |
+ ANADIG_PLL7_CTRL_POWERDOWN, ANADIG_PLL7_CTRL_ENABLE);
clrsetbits_le32(anadig-pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE |
ANADIG_PLL5_CTRL_DIV_SELECT);
+ clrsetbits_le32(anadig-pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS |
+ ANADIG_PLL3_CTRL_POWERDOWN, ANADIG_PLL3_CTRL_ENABLE);
if (is_colibri_vf61()) {
clrsetbits_le32(anadig-pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS |
@@ -359,3 +364,19 @@ int checkboard(void)
return 0;
}
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+ unsigned short usb_pid;
+
+ put_unaligned(CONFIG_TRDX_VID, dev-idVendor);
+
+ if (is_colibri_vf61())
+ usb_pid = CONFIG_TRDX_PID_COLIBRI_VF61IT;
+ else
+ usb_pid = CONFIG_TRDX_PID_COLIBRI_VF50IT;
+
+ put_unaligned(usb_pid, dev-idProduct);
+
+ return 0;
+}
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 84ffbe8..414600a 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -146,6 +146,8 @@
#define CONFIG_BOOTCOMMAND run ubiboot; run sdboot; run nfsboot
+#define DFU_ALT_NAND_INFO vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4
+
#define CONFIG_EXTRA_ENV_SETTINGS \
kernel_addr_r=0x8200\0 \
fdt_addr_r=0x8400\0 \
@@ -165,6 +167,7 @@
source ${loadaddr}\0 \
setupdate=run setsdupdate || run setusbupdate\0 \
mtdparts= MTDPARTS_DEFAULT \0 \
+ dfu_alt_info= DFU_ALT_NAND_INFO \0 \
SD_BOOTCMD \
NFS_BOOTCMD \
UBI_BOOTCMD
@@ -231,4 +234,38 @@
#define CONFIG_SYS_CACHELINE_SIZE 32
+/* USB Host Support */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_VF
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+/* USB Client Support */
+#define CONFIG_USB_GADGET
+#define CONFIG_CI_UDC
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_TRDX_VID 0x1B67
+#define CONFIG_TRDX_PID_COLIBRI_VF50 0x0016
+#define CONFIG_TRDX_PID_COLIBRI_VF61 0x0017
+#define CONFIG_TRDX_PID_COLIBRI_VF61IT 0x0018
+#define CONFIG_TRDX_PID_COLIBRI_VF50IT 0x0019
+#define CONFIG_G_DNL_MANUFACTURERToradex
+#define CONFIG_G_DNL_VENDOR_NUM CONFIG_TRDX_VID
+#define CONFIG_G_DNL_PRODUCT_NUM CONFIG_TRDX_PID_COLIBRI_VF50
+
+/* USB DFU */
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_CMD_DFU
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_NAND
+#define CONFIG_DFU_MMC
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024 * 1024)
+
+/* USB Storage */
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_CMD_USB_MASS_STORAGE
+
#endif /* __CONFIG_H */
--
2.3.5
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[U-Boot] [PATCH v3 6/7] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
This driver adds support for the USB peripheral on Freescale Vybrid
SoC's.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/include/asm/arch-vf610/crm_regs.h| 10 ++
arch/arm/include/asm/arch-vf610/imx-regs.h| 4 +
arch/arm/include/asm/imx-common/regs-usbphy.h | 26
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ehci-vf.c| 164 ++
5 files changed, 205 insertions(+)
create mode 100644 arch/arm/include/asm/imx-common/regs-usbphy.h
create mode 100644 drivers/usb/host/ehci-vf.c
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h
b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 78708e2..bc6db2a 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -189,6 +189,7 @@ struct anadig_reg {
#define CCM_REG_CTRL_MASK 0x
#define CCM_CCGR0_UART0_CTRL_MASK (0x3 14)
#define CCM_CCGR0_UART1_CTRL_MASK (0x3 16)
+#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 8)
#define CCM_CCGR1_PIT_CTRL_MASK(0x3 14)
#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 28)
#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 8)
@@ -207,14 +208,23 @@ struct anadig_reg {
#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 10)
#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 28)
#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 4)
+#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 8)
#define CCM_CCGR9_FEC0_CTRL_MASK 0x3
#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 2)
#define CCM_CCGR10_NFC_CTRL_MASK 0x3
+#define ANADIG_PLL7_CTRL_BYPASS (1 16)
+#define ANADIG_PLL7_CTRL_ENABLE (1 13)
+#define ANADIG_PLL7_CTRL_POWERDOWN (1 12)
+#define ANADIG_PLL7_CTRL_DIV_SELECT (1 1)
#define ANADIG_PLL5_CTRL_BYPASS (1 16)
#define ANADIG_PLL5_CTRL_ENABLE (1 13)
#define ANADIG_PLL5_CTRL_POWERDOWN (1 12)
#define ANADIG_PLL5_CTRL_DIV_SELECT1
+#define ANADIG_PLL3_CTRL_BYPASS (1 16)
+#define ANADIG_PLL3_CTRL_ENABLE (1 13)
+#define ANADIG_PLL3_CTRL_POWERDOWN (1 12)
+#define ANADIG_PLL3_CTRL_DIV_SELECT (1 1)
#define ANADIG_PLL2_CTRL_ENABLE(1 13)
#define ANADIG_PLL2_CTRL_POWERDOWN (1 12)
#define ANADIG_PLL2_CTRL_DIV_SELECT1
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index bf41971..a7d765a 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -52,6 +52,7 @@
#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000)
+#define USBC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000)
#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
@@ -65,6 +66,8 @@
#define QSPI0_BASE_ADDR(AIPS0_BASE_ADDR + 0x00044000)
#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005)
+#define USB_PHY0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050800)
+#define USB_PHY1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050C00)
#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006)
#define SPDIF_BASE_ADDR(AIPS0_BASE_ADDR + 0x00061000)
@@ -84,6 +87,7 @@
#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000)
#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000)
#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
+#define USBC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00034000)
#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x0005)
#define ENET1_BASE_ADDR(AIPS1_BASE_ADDR + 0x00051000)
#define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x0006)
diff --git a/arch/arm/include/asm/imx-common/regs-usbphy.h
b/arch/arm/include/asm/imx-common/regs-usbphy.h
new file mode 100644
index 000..220e45f
--- /dev/null
+++ b/arch/arm/include/asm/imx-common/regs-usbphy.h
@@ -0,0 +1,26 @@
+/*
+ * Freescale USB PHY Register Definitions
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __REGS_USBPHY_H__
+#define __REGS_USBPHY_H__
+
+#define USBPHY_CTRL0x0030
+#define USBPHY_CTRL_SET0x0034
+#define USBPHY_CTRL_CLR0x0038
+#define USBPHY_CTRL_TOG0x003C
+#define USBPHY_PWD 0x
+#define USBPHY_TX 0x0010
[U-Boot] [PATCH v2 3/6] ARM: vf610: Add SoC and CPU type detection
Vybrid product family consists of several rather similar SoC which
can be determined by softare during boot time. This allows use of
variable ${soc} for Linux device tree files. Detect VF5xx CPU's by
reading the CPU count register. We can determine the second number
of the CPU type (VF6x0) which indicates the presence of a L2 cache.
Signed-off-by: Stefan Agner ste...@agner.ch
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/cpu/armv7/vf610/generic.c | 29 +++--
arch/arm/include/asm/arch-vf610/imx-regs.h | 12
2 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/vf610/generic.c
b/arch/arm/cpu/armv7/vf610/generic.c
index 92aaad9..3bdc221 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -18,6 +18,8 @@
DECLARE_GLOBAL_DATA_PTR;
#endif
+static char soc_type[] = xx0;
+
#ifdef CONFIG_MXC_OCOTP
void enable_ocotp_clk(unsigned char enable)
{
@@ -284,14 +286,37 @@ static char *get_reset_cause(void)
int print_cpuinfo(void)
{
- printf(CPU: Freescale Vybrid VF610 at %d MHz\n,
- mxc_get_clock(MXC_ARM_CLK) / 100);
+ printf(CPU: Freescale Vybrid VF%s at %d MHz\n,
+ soc_type, mxc_get_clock(MXC_ARM_CLK) / 100);
printf(Reset cause: %s\n, get_reset_cause());
return 0;
}
#endif
+int arch_cpu_init(void)
+{
+ struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
+
+ soc_type[0] = mscm-cpxcount ? '6' : '5'; /*Dual Core = VF6x0 */
+ soc_type[1] = mscm-cpxcfg1 ? '1' : '0'; /* L2 Cache = VFx10 */
+
+ return 0;
+}
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ char soc[6];
+
+ strcat(soc, vf);
+ strcat(soc, soc_type);
+ setenv(soc, soc);
+
+ return 0;
+}
+#endif
+
int cpu_eth_init(bd_t *bis)
{
int rc = -ENODEV;
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index aa60031..a5908ca 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -457,6 +457,18 @@ struct scsc_reg {
u32 sosc_ctr;
};
+/* MSCM */
+struct mscm {
+ u32 cpxtype;
+ u32 cpxnum;
+ u32 cpxmaster;
+ u32 cpxcount;
+ u32 cpxcfg0;
+ u32 cpxcfg1;
+ u32 cpxcfg2;
+ u32 cpxcfg3;
+};
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_IMX_REGS_H__ */
--
2.3.5
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[U-Boot] [PATCH v2 6/6] ARM: vf610: Initial integration for Colibri VF50/VF61
This adds initial support for Colibri VF50/VF61 based on Freescale Vybrid SoC. - CPU clocked at 396/500 MHz - DDR3 at 396MHz - for VF50, use PLL2 as memory clock (synchronous mode) - for VF61, use PLL1 as memory clock (asynchronous mode) - Console on UART0 (Colibri UART_A) - Ethernet on FEC1 - PLL5 based RMII clocking (E.g. No external crystal) - UART_A and UART_C I/O muxing - Boot from NAND by default - USB host and client support Tested on Colibri VF50/VF61 booting using serial loader over UART. Signed-off-by: Stefan Agner ste...@agner.ch Signed-off-by: Sanchayan Maity maitysancha...@gmail.com --- arch/arm/Kconfig | 5 + arch/arm/include/asm/arch-vf610/imx-regs.h | 5 + board/toradex/colibri_vf/Kconfig | 18 ++ board/toradex/colibri_vf/MAINTAINERS | 6 + board/toradex/colibri_vf/Makefile | 7 + board/toradex/colibri_vf/colibri_vf.c | 387 + board/toradex/colibri_vf/imximage.cfg | 17 ++ configs/colibri_vf_defconfig | 3 + include/configs/colibri_vf.h | 271 9 files changed, 719 insertions(+) create mode 100644 board/toradex/colibri_vf/Kconfig create mode 100644 board/toradex/colibri_vf/MAINTAINERS create mode 100644 board/toradex/colibri_vf/Makefile create mode 100644 board/toradex/colibri_vf/colibri_vf.c create mode 100644 board/toradex/colibri_vf/imximage.cfg create mode 100644 configs/colibri_vf_defconfig create mode 100644 include/configs/colibri_vf.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 80b0d34..e32a942 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -608,6 +608,10 @@ config TARGET_VF610TWR bool Support vf610twr select CPU_V7 +config TARGET_COLIBRI_VF + bool Support Colibri VF50/61 + select CPU_V7 + config ZYNQ bool Xilinx Zynq Platform select CPU_V7 @@ -864,6 +868,7 @@ source board/ti/ti814x/Kconfig source board/ti/ti816x/Kconfig source board/timll/devkit3250/Kconfig source board/toradex/colibri_pxa270/Kconfig +source board/toradex/colibri_vf/Kconfig source board/tqc/tqma6/Kconfig source board/trizepsiv/Kconfig source board/ttcontrol/vision2/Kconfig diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 26057fe..a7d765a 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -267,6 +267,11 @@ #define SRC_SRSR_WDOG_M4 (0x1 4) #define SRC_SRSR_WDOG_A5 (0x1 3) #define SRC_SRSR_POR_RST (0x1 0) +#define SRC_SBMR2_BMOD_MASK (0x3 24) +#define SRC_SBMR2_BMOD_SHIFT24 +#define SRC_SBMR2_BMOD_FUSES0x0 +#define SRC_SBMR2_BMOD_SERIAL 0x1 +#define SRC_SBMR2_BMOD_RCON 0x2 /* Slow Clock Source Controller Module (SCSC) */ #define SCSC_SOSC_CTR_SOSC_EN0x1 diff --git a/board/toradex/colibri_vf/Kconfig b/board/toradex/colibri_vf/Kconfig new file mode 100644 index 000..2c3cb30 --- /dev/null +++ b/board/toradex/colibri_vf/Kconfig @@ -0,0 +1,18 @@ +if TARGET_COLIBRI_VF + +config SYS_CPU + default armv7 + +config SYS_BOARD + default colibri_vf + +config SYS_VENDOR + default toradex + +config SYS_SOC + default vf610 + +config SYS_CONFIG_NAME + default colibri_vf + +endif diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS new file mode 100644 index 000..551c575 --- /dev/null +++ b/board/toradex/colibri_vf/MAINTAINERS @@ -0,0 +1,6 @@ +Colibri VFxx +M: Stefan Agner stefan.ag...@toradex.com +S: Maintained +F: board/toradex/colibri_vf/ +F: include/configs/colibri_vf.h +F: configs/colibri_vf_defconfig diff --git a/board/toradex/colibri_vf/Makefile b/board/toradex/colibri_vf/Makefile new file mode 100644 index 000..c7e5134 --- /dev/null +++ b/board/toradex/colibri_vf/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := colibri_vf.o diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c new file mode 100644 index 000..3667779 --- /dev/null +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -0,0 +1,387 @@ +/* + * Copyright 2015 Toradex, Inc. + * + * Based on vf610twr.c: + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include common.h +#include asm/io.h +#include asm/arch/imx-regs.h +#include asm/arch/iomux-vf610.h +#include asm/arch/ddrmc-vf610.h +#include asm/arch/crm_regs.h +#include asm/arch/clock.h +#include mmc.h +#include fsl_esdhc.h +#include miiphy.h +#include netdev.h +#include i2c.h +#include g_dnl.h + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_25ohm
[U-Boot] [PATCH v2 1/6] ARM: vf610: Move DDR3 initialization to imx-common
In order to avoid code duplication, move the DDR3 initialization to the
common place under imx-common. Currently ROW_DIFF and COL_DIFF can be
chosen from the board file. The JEDEC timings are specified using a
common ddr3_jedec_timings structure.
Signed-off-by: Stefan Agner ste...@agner.ch
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/imx-common/Makefile | 3 +
arch/arm/imx-common/ddrmc-vf610.c | 278 +
arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 72 +++
arch/arm/include/asm/arch-vf610/imx-regs.h| 4 +-
board/freescale/vf610twr/vf610twr.c | 282 +-
5 files changed, 408 insertions(+), 231 deletions(-)
create mode 100644 arch/arm/imx-common/ddrmc-vf610.c
create mode 100644 arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 606482f..b9f1ca4 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -22,6 +22,9 @@ ifeq ($(SOC),$(filter $(SOC),mx6))
obj-$(CONFIG_CMD_SATA) += sata.o
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
endif
+ifeq ($(SOC),$(filter $(SOC),vf610))
+obj-y += ddrmc-vf610.o
+endif
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
diff --git a/arch/arm/imx-common/ddrmc-vf610.c
b/arch/arm/imx-common/ddrmc-vf610.c
new file mode 100644
index 000..e462631
--- /dev/null
+++ b/arch/arm/imx-common/ddrmc-vf610.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright 2015 Toradex, Inc.
+ *
+ * Based on vf610twr:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm/io.h
+#include asm/arch/imx-regs.h
+#include asm/arch/iomux-vf610.h
+#include asm/arch/ddrmc-vf610.h
+
+void ddrmc_setup_iomux(void)
+{
+ static const iomux_v3_cfg_t ddr_pads[] = {
+ VF610_PAD_DDR_A15__DDR_A_15,
+ VF610_PAD_DDR_A14__DDR_A_14,
+ VF610_PAD_DDR_A13__DDR_A_13,
+ VF610_PAD_DDR_A12__DDR_A_12,
+ VF610_PAD_DDR_A11__DDR_A_11,
+ VF610_PAD_DDR_A10__DDR_A_10,
+ VF610_PAD_DDR_A9__DDR_A_9,
+ VF610_PAD_DDR_A8__DDR_A_8,
+ VF610_PAD_DDR_A7__DDR_A_7,
+ VF610_PAD_DDR_A6__DDR_A_6,
+ VF610_PAD_DDR_A5__DDR_A_5,
+ VF610_PAD_DDR_A4__DDR_A_4,
+ VF610_PAD_DDR_A3__DDR_A_3,
+ VF610_PAD_DDR_A2__DDR_A_2,
+ VF610_PAD_DDR_A1__DDR_A_1,
+ VF610_PAD_DDR_A0__DDR_A_0,
+ VF610_PAD_DDR_BA2__DDR_BA_2,
+ VF610_PAD_DDR_BA1__DDR_BA_1,
+ VF610_PAD_DDR_BA0__DDR_BA_0,
+ VF610_PAD_DDR_CAS__DDR_CAS_B,
+ VF610_PAD_DDR_CKE__DDR_CKE_0,
+ VF610_PAD_DDR_CLK__DDR_CLK_0,
+ VF610_PAD_DDR_CS__DDR_CS_B_0,
+ VF610_PAD_DDR_D15__DDR_D_15,
+ VF610_PAD_DDR_D14__DDR_D_14,
+ VF610_PAD_DDR_D13__DDR_D_13,
+ VF610_PAD_DDR_D12__DDR_D_12,
+ VF610_PAD_DDR_D11__DDR_D_11,
+ VF610_PAD_DDR_D10__DDR_D_10,
+ VF610_PAD_DDR_D9__DDR_D_9,
+ VF610_PAD_DDR_D8__DDR_D_8,
+ VF610_PAD_DDR_D7__DDR_D_7,
+ VF610_PAD_DDR_D6__DDR_D_6,
+ VF610_PAD_DDR_D5__DDR_D_5,
+ VF610_PAD_DDR_D4__DDR_D_4,
+ VF610_PAD_DDR_D3__DDR_D_3,
+ VF610_PAD_DDR_D2__DDR_D_2,
+ VF610_PAD_DDR_D1__DDR_D_1,
+ VF610_PAD_DDR_D0__DDR_D_0,
+ VF610_PAD_DDR_DQM1__DDR_DQM_1,
+ VF610_PAD_DDR_DQM0__DDR_DQM_0,
+ VF610_PAD_DDR_DQS1__DDR_DQS_1,
+ VF610_PAD_DDR_DQS0__DDR_DQS_0,
+ VF610_PAD_DDR_RAS__DDR_RAS_B,
+ VF610_PAD_DDR_WE__DDR_WE_B,
+ VF610_PAD_DDR_ODT1__DDR_ODT_0,
+ VF610_PAD_DDR_ODT0__DDR_ODT_1,
+ VF610_PAD_DDR_RESETB,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
+}
+
+void ddrmc_phy_init(void)
+{
+ struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+ writel(DDRMC_PHY_DQ_TIMING, ddrmr-phy[0]);
+ writel(DDRMC_PHY_DQ_TIMING, ddrmr-phy[16]);
+ writel(DDRMC_PHY_DQ_TIMING, ddrmr-phy[32]);
+
+ writel(DDRMC_PHY_DQS_TIMING, ddrmr-phy[1]);
+ writel(DDRMC_PHY_DQS_TIMING, ddrmr-phy[17]);
+
+ writel(DDRMC_PHY_CTRL, ddrmr-phy[2]);
+ writel(DDRMC_PHY_CTRL, ddrmr-phy[18]);
+ writel(DDRMC_PHY_CTRL, ddrmr-phy[34]);
+
+ writel(DDRMC_PHY_MASTER_CTRL, ddrmr-phy[3]);
+ writel(DDRMC_PHY_MASTER_CTRL, ddrmr-phy[19]);
+ writel(DDRMC_PHY_MASTER_CTRL, ddrmr-phy[35]);
+
+ writel(DDRMC_PHY_SLAVE_CTRL, ddrmr-phy[4]);
+ writel(DDRMC_PHY_SLAVE_CTRL, ddrmr-phy[20]);
+ writel(DDRMC_PHY_SLAVE_CTRL, ddrmr-phy[36]);
+
+ /* LPDDR2
[U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules
Hello,
This is the second version of the patchset which adds support for the
Toradex Colibri Vybrid VF50 and VF61 modules. Boot up has been tested
using the serial loader over UART.
First patch in the series refactors the DDR related code for use by both
the tower board and colibri modules. It also introduces a DDR3 based
JEDEC timing structure.
Second third and fourth patch in this series are improvement patches
related to RTC, SoC/CPU detection and caches.
Fifth patch introduces USB support for Vybrid modules. Much of the code
is similar to the ehci-mx6 driver. One open question here would be is
there a better way to take care of this similarity and perhaps share the
code base among the two drivers? Both host and client modes are working
and DFU has also been tested. Currently, we restrict the ports to be in
one of host and client mode.
Sixth patch adds the actual support for the Colibri modules.
Comments and feedback are most welcome.
The patchset is based and tested on the latest master branch as of
this writing.
Discussion on the version 1 of the patchset can be found at the below
link:
https://www.mail-archive.com/u-boot@lists.denx.de/msg168136.html
Changes since v1:
- Rework the USB driver to use register offsets using the regular
struct {} method
- Some cleanups and fixes in the sixth patch for the colibri_vf.h file
which takes care of environment variables in uboot
- Purge some useless defines in the fifth and sixth patch which were
related to USB.
- Sanchayan.
Sanchayan Maity (4):
ARM: vf610: Move DDR3 initialization to imx-common
ARM: vf610: Add SoC and CPU type detection
usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
ARM: vf610: Initial integration for Colibri VF50/VF61
Stefan Agner (2):
ARM: vf610: Enable external 32KHz oscillator
ARM: vf610: Enable caches
arch/arm/Kconfig | 5 +
arch/arm/cpu/armv7/vf610/generic.c| 45 ++-
arch/arm/imx-common/Makefile | 3 +
arch/arm/imx-common/ddrmc-vf610.c | 278 ++
arch/arm/include/asm/arch-vf610/crm_regs.h| 11 +
arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 72 +
arch/arm/include/asm/arch-vf610/imx-regs.h| 36 ++-
arch/arm/include/asm/arch-vf610/regs-usbphy.h | 31 +++
board/freescale/vf610twr/vf610twr.c | 295 +---
board/toradex/colibri_vf/Kconfig | 18 ++
board/toradex/colibri_vf/MAINTAINERS | 6 +
board/toradex/colibri_vf/Makefile | 7 +
board/toradex/colibri_vf/colibri_vf.c | 387 ++
board/toradex/colibri_vf/imximage.cfg | 17 ++
configs/colibri_vf_defconfig | 3 +
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ehci-vf.c| 196 +
include/configs/colibri_vf.h | 271 ++
18 files changed, 1447 insertions(+), 235 deletions(-)
create mode 100644 arch/arm/imx-common/ddrmc-vf610.c
create mode 100644 arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
create mode 100644 arch/arm/include/asm/arch-vf610/regs-usbphy.h
create mode 100644 board/toradex/colibri_vf/Kconfig
create mode 100644 board/toradex/colibri_vf/MAINTAINERS
create mode 100644 board/toradex/colibri_vf/Makefile
create mode 100644 board/toradex/colibri_vf/colibri_vf.c
create mode 100644 board/toradex/colibri_vf/imximage.cfg
create mode 100644 configs/colibri_vf_defconfig
create mode 100644 drivers/usb/host/ehci-vf.c
create mode 100644 include/configs/colibri_vf.h
--
2.3.5
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[U-Boot] [PATCH v2 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
This driver adds support for the USB peripheral on Freescale Vybrid
SoC's.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/include/asm/arch-vf610/crm_regs.h| 10 ++
arch/arm/include/asm/arch-vf610/imx-regs.h| 4 +
arch/arm/include/asm/arch-vf610/regs-usbphy.h | 31
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ehci-vf.c| 196 ++
5 files changed, 242 insertions(+)
create mode 100644 arch/arm/include/asm/arch-vf610/regs-usbphy.h
create mode 100644 drivers/usb/host/ehci-vf.c
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h
b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 78708e2..bc6db2a 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -189,6 +189,7 @@ struct anadig_reg {
#define CCM_REG_CTRL_MASK 0x
#define CCM_CCGR0_UART0_CTRL_MASK (0x3 14)
#define CCM_CCGR0_UART1_CTRL_MASK (0x3 16)
+#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 8)
#define CCM_CCGR1_PIT_CTRL_MASK(0x3 14)
#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 28)
#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 8)
@@ -207,14 +208,23 @@ struct anadig_reg {
#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 10)
#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 28)
#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 4)
+#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 8)
#define CCM_CCGR9_FEC0_CTRL_MASK 0x3
#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 2)
#define CCM_CCGR10_NFC_CTRL_MASK 0x3
+#define ANADIG_PLL7_CTRL_BYPASS (1 16)
+#define ANADIG_PLL7_CTRL_ENABLE (1 13)
+#define ANADIG_PLL7_CTRL_POWERDOWN (1 12)
+#define ANADIG_PLL7_CTRL_DIV_SELECT (1 1)
#define ANADIG_PLL5_CTRL_BYPASS (1 16)
#define ANADIG_PLL5_CTRL_ENABLE (1 13)
#define ANADIG_PLL5_CTRL_POWERDOWN (1 12)
#define ANADIG_PLL5_CTRL_DIV_SELECT1
+#define ANADIG_PLL3_CTRL_BYPASS (1 16)
+#define ANADIG_PLL3_CTRL_ENABLE (1 13)
+#define ANADIG_PLL3_CTRL_POWERDOWN (1 12)
+#define ANADIG_PLL3_CTRL_DIV_SELECT (1 1)
#define ANADIG_PLL2_CTRL_ENABLE(1 13)
#define ANADIG_PLL2_CTRL_POWERDOWN (1 12)
#define ANADIG_PLL2_CTRL_DIV_SELECT1
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index a5908ca..26057fe 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -52,6 +52,7 @@
#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000)
+#define USBC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000)
#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
@@ -65,6 +66,8 @@
#define QSPI0_BASE_ADDR(AIPS0_BASE_ADDR + 0x00044000)
#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005)
+#define USB_PHY0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050800)
+#define USB_PHY1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050C00)
#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006)
#define SPDIF_BASE_ADDR(AIPS0_BASE_ADDR + 0x00061000)
@@ -84,6 +87,7 @@
#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000)
#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000)
#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
+#define USBC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00034000)
#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x0005)
#define ENET1_BASE_ADDR(AIPS1_BASE_ADDR + 0x00051000)
#define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x0006)
diff --git a/arch/arm/include/asm/arch-vf610/regs-usbphy.h
b/arch/arm/include/asm/arch-vf610/regs-usbphy.h
new file mode 100644
index 000..b1b8876
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/regs-usbphy.h
@@ -0,0 +1,31 @@
+/*
+ * Freescale Vybrid USB PHY Register Definitions
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __REGS_USBPHY_H__
+#define __REGS_USBPHY_H__
+
+#include asm/imx-common/regs-common.h
+
+struct vf_usbphy_regs {
+ mxs_reg_32(hw_usbphy_pwd)
+ mxs_reg_32(hw_usbphy_tx)
+ mxs_reg_32(hw_usbphy_rx)
+ mxs_reg_32(hw_usbphy_ctrl)
+ mxs_reg_32(hw_usbphy_status)
+ mxs_reg_32(hw_usbphy_debug)
+ mxs_reg_32(hw_usbphy_debug0_status)
+ mxs_reg_32(hw_usbphy_debug1)
+ mxs_reg_32(hw_usbphy_version)
+ mxs_reg_32(hw_usbphy_ip)
+};
+
+#define
[U-Boot] [PATCH v2 2/6] ARM: vf610: Enable external 32KHz oscillator
From: Stefan Agner ste...@agner.ch
Enable the SCSC (Slow Clock Source Controller) and select the external
32KHz oscillator. This improves the accuracy of the RTC.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/include/asm/arch-vf610/crm_regs.h | 1 +
arch/arm/include/asm/arch-vf610/imx-regs.h | 11 ++-
board/freescale/vf610twr/vf610twr.c| 13 -
3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h
b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 724682c..78708e2 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -199,6 +199,7 @@ struct anadig_reg {
#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 24)
#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 26)
#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
+#define CCM_CCGR3_SCSC_CTRL_MASK(0x3 4)
#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 20)
#define CCM_CCGR4_CCM_CTRL_MASK(0x3 22)
#define CCM_CCGR4_GPC_CTRL_MASK(0x3 24)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 866b303..aa60031 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -65,7 +65,7 @@
#define QSPI0_BASE_ADDR(AIPS0_BASE_ADDR + 0x00044000)
#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005)
-#define SCSCM_BASE_ADDR(AIPS0_BASE_ADDR + 0x00052000)
+#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006)
#define SPDIF_BASE_ADDR(AIPS0_BASE_ADDR + 0x00061000)
#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
@@ -264,6 +264,9 @@
#define SRC_SRSR_WDOG_A5 (0x1 3)
#define SRC_SRSR_POR_RST (0x1 0)
+/* Slow Clock Source Controller Module (SCSC) */
+#define SCSC_SOSC_CTR_SOSC_EN0x1
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include asm/types.h
@@ -448,6 +451,12 @@ struct mscm_ir {
u16 rsvd3[848];
};
+/* SCSC */
+struct scsc_reg {
+ u32 sirc_ctr;
+ u32 sosc_ctr;
+};
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/board/freescale/vf610twr/vf610twr.c
b/board/freescale/vf610twr/vf610twr.c
index eb27542..4160acd 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -227,7 +227,7 @@ static void clock_init(void)
CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
CCM_CCGR2_QSPI0_CTRL_MASK);
clrsetbits_le32(ccm-ccgr3, CCM_REG_CTRL_MASK,
- CCM_CCGR3_ANADIG_CTRL_MASK);
+ CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
clrsetbits_le32(ccm-ccgr4, CCM_REG_CTRL_MASK,
CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
@@ -308,9 +308,20 @@ int board_early_init_f(void)
int board_init(void)
{
+ struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
+
/* address of boot parameters */
gd-bd-bi_boot_params = PHYS_SDRAM + 0x100;
+ /*
+* Enable external 32K Oscillator
+*
+* The internal clock experiences significant drift
+* so we must use the external oscillator in order
+* to maintain correct time in the hwclock
+*/
+ setbits_le32(scsc-sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
+
return 0;
}
--
2.3.5
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[U-Boot] [PATCH v2 4/6] ARM: vf610: Enable caches
From: Stefan Agner ste...@agner.ch
Enables caches which provides a rather huge speedup of the boot loader.
Also mark the on-chip RAM as cachable since this is the area U-Boot runs
from.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/cpu/armv7/vf610/generic.c | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/cpu/armv7/vf610/generic.c
b/arch/arm/cpu/armv7/vf610/generic.c
index 3bdc221..1bb9b8e 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -342,3 +342,19 @@ int get_clocks(void)
#endif
return 0;
}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ enum dcache_option option = DCACHE_WRITETHROUGH;
+#else
+ enum dcache_option option = DCACHE_WRITEBACK;
+#endif
+ dcache_enable();
+ icache_enable();
+
+/* Enable caching on OCRAM */
+ mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
+}
+#endif
--
2.3.5
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[U-Boot] [RESEND PATCH 1/6] ARM: vf610: Move DDR3 initialization to imx-common
In order to avoid code duplication, move the DDR3 initialization to the
common place under imx-common. Currently ROW_DIFF and COL_DIFF can be
chosen from the board file. The JEDEC timings are specified using a
common ddr3_jedec_timings structure.
Signed-off-by: Stefan Agner ste...@agner.ch
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/imx-common/Makefile | 3 +
arch/arm/imx-common/ddrmc-vf610.c | 278 +
arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 72 +++
arch/arm/include/asm/arch-vf610/imx-regs.h| 4 +-
board/freescale/vf610twr/vf610twr.c | 282 +-
5 files changed, 408 insertions(+), 231 deletions(-)
create mode 100644 arch/arm/imx-common/ddrmc-vf610.c
create mode 100644 arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 606482f..b9f1ca4 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -22,6 +22,9 @@ ifeq ($(SOC),$(filter $(SOC),mx6))
obj-$(CONFIG_CMD_SATA) += sata.o
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
endif
+ifeq ($(SOC),$(filter $(SOC),vf610))
+obj-y += ddrmc-vf610.o
+endif
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
diff --git a/arch/arm/imx-common/ddrmc-vf610.c
b/arch/arm/imx-common/ddrmc-vf610.c
new file mode 100644
index 000..e462631
--- /dev/null
+++ b/arch/arm/imx-common/ddrmc-vf610.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright 2015 Toradex, Inc.
+ *
+ * Based on vf610twr:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm/io.h
+#include asm/arch/imx-regs.h
+#include asm/arch/iomux-vf610.h
+#include asm/arch/ddrmc-vf610.h
+
+void ddrmc_setup_iomux(void)
+{
+ static const iomux_v3_cfg_t ddr_pads[] = {
+ VF610_PAD_DDR_A15__DDR_A_15,
+ VF610_PAD_DDR_A14__DDR_A_14,
+ VF610_PAD_DDR_A13__DDR_A_13,
+ VF610_PAD_DDR_A12__DDR_A_12,
+ VF610_PAD_DDR_A11__DDR_A_11,
+ VF610_PAD_DDR_A10__DDR_A_10,
+ VF610_PAD_DDR_A9__DDR_A_9,
+ VF610_PAD_DDR_A8__DDR_A_8,
+ VF610_PAD_DDR_A7__DDR_A_7,
+ VF610_PAD_DDR_A6__DDR_A_6,
+ VF610_PAD_DDR_A5__DDR_A_5,
+ VF610_PAD_DDR_A4__DDR_A_4,
+ VF610_PAD_DDR_A3__DDR_A_3,
+ VF610_PAD_DDR_A2__DDR_A_2,
+ VF610_PAD_DDR_A1__DDR_A_1,
+ VF610_PAD_DDR_A0__DDR_A_0,
+ VF610_PAD_DDR_BA2__DDR_BA_2,
+ VF610_PAD_DDR_BA1__DDR_BA_1,
+ VF610_PAD_DDR_BA0__DDR_BA_0,
+ VF610_PAD_DDR_CAS__DDR_CAS_B,
+ VF610_PAD_DDR_CKE__DDR_CKE_0,
+ VF610_PAD_DDR_CLK__DDR_CLK_0,
+ VF610_PAD_DDR_CS__DDR_CS_B_0,
+ VF610_PAD_DDR_D15__DDR_D_15,
+ VF610_PAD_DDR_D14__DDR_D_14,
+ VF610_PAD_DDR_D13__DDR_D_13,
+ VF610_PAD_DDR_D12__DDR_D_12,
+ VF610_PAD_DDR_D11__DDR_D_11,
+ VF610_PAD_DDR_D10__DDR_D_10,
+ VF610_PAD_DDR_D9__DDR_D_9,
+ VF610_PAD_DDR_D8__DDR_D_8,
+ VF610_PAD_DDR_D7__DDR_D_7,
+ VF610_PAD_DDR_D6__DDR_D_6,
+ VF610_PAD_DDR_D5__DDR_D_5,
+ VF610_PAD_DDR_D4__DDR_D_4,
+ VF610_PAD_DDR_D3__DDR_D_3,
+ VF610_PAD_DDR_D2__DDR_D_2,
+ VF610_PAD_DDR_D1__DDR_D_1,
+ VF610_PAD_DDR_D0__DDR_D_0,
+ VF610_PAD_DDR_DQM1__DDR_DQM_1,
+ VF610_PAD_DDR_DQM0__DDR_DQM_0,
+ VF610_PAD_DDR_DQS1__DDR_DQS_1,
+ VF610_PAD_DDR_DQS0__DDR_DQS_0,
+ VF610_PAD_DDR_RAS__DDR_RAS_B,
+ VF610_PAD_DDR_WE__DDR_WE_B,
+ VF610_PAD_DDR_ODT1__DDR_ODT_0,
+ VF610_PAD_DDR_ODT0__DDR_ODT_1,
+ VF610_PAD_DDR_RESETB,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
+}
+
+void ddrmc_phy_init(void)
+{
+ struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+ writel(DDRMC_PHY_DQ_TIMING, ddrmr-phy[0]);
+ writel(DDRMC_PHY_DQ_TIMING, ddrmr-phy[16]);
+ writel(DDRMC_PHY_DQ_TIMING, ddrmr-phy[32]);
+
+ writel(DDRMC_PHY_DQS_TIMING, ddrmr-phy[1]);
+ writel(DDRMC_PHY_DQS_TIMING, ddrmr-phy[17]);
+
+ writel(DDRMC_PHY_CTRL, ddrmr-phy[2]);
+ writel(DDRMC_PHY_CTRL, ddrmr-phy[18]);
+ writel(DDRMC_PHY_CTRL, ddrmr-phy[34]);
+
+ writel(DDRMC_PHY_MASTER_CTRL, ddrmr-phy[3]);
+ writel(DDRMC_PHY_MASTER_CTRL, ddrmr-phy[19]);
+ writel(DDRMC_PHY_MASTER_CTRL, ddrmr-phy[35]);
+
+ writel(DDRMC_PHY_SLAVE_CTRL, ddrmr-phy[4]);
+ writel(DDRMC_PHY_SLAVE_CTRL, ddrmr-phy[20]);
+ writel(DDRMC_PHY_SLAVE_CTRL, ddrmr-phy[36]);
+
+ /* LPDDR2
[U-Boot] [RESEND PATCH 2/6] ARM: vf610: Enable external 32KHz oscillator
From: Stefan Agner ste...@agner.ch
Enable the SCSC (Slow Clock Source Controller) and select the external
32KHz oscillator. This improves the accuracy of the RTC.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/include/asm/arch-vf610/crm_regs.h | 1 +
arch/arm/include/asm/arch-vf610/imx-regs.h | 11 ++-
board/freescale/vf610twr/vf610twr.c| 13 -
3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h
b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 724682c..78708e2 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -199,6 +199,7 @@ struct anadig_reg {
#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 24)
#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 26)
#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
+#define CCM_CCGR3_SCSC_CTRL_MASK(0x3 4)
#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 20)
#define CCM_CCGR4_CCM_CTRL_MASK(0x3 22)
#define CCM_CCGR4_GPC_CTRL_MASK(0x3 24)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 866b303..aa60031 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -65,7 +65,7 @@
#define QSPI0_BASE_ADDR(AIPS0_BASE_ADDR + 0x00044000)
#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005)
-#define SCSCM_BASE_ADDR(AIPS0_BASE_ADDR + 0x00052000)
+#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006)
#define SPDIF_BASE_ADDR(AIPS0_BASE_ADDR + 0x00061000)
#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
@@ -264,6 +264,9 @@
#define SRC_SRSR_WDOG_A5 (0x1 3)
#define SRC_SRSR_POR_RST (0x1 0)
+/* Slow Clock Source Controller Module (SCSC) */
+#define SCSC_SOSC_CTR_SOSC_EN0x1
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include asm/types.h
@@ -448,6 +451,12 @@ struct mscm_ir {
u16 rsvd3[848];
};
+/* SCSC */
+struct scsc_reg {
+ u32 sirc_ctr;
+ u32 sosc_ctr;
+};
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/board/freescale/vf610twr/vf610twr.c
b/board/freescale/vf610twr/vf610twr.c
index eb27542..4160acd 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -227,7 +227,7 @@ static void clock_init(void)
CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
CCM_CCGR2_QSPI0_CTRL_MASK);
clrsetbits_le32(ccm-ccgr3, CCM_REG_CTRL_MASK,
- CCM_CCGR3_ANADIG_CTRL_MASK);
+ CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
clrsetbits_le32(ccm-ccgr4, CCM_REG_CTRL_MASK,
CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
@@ -308,9 +308,20 @@ int board_early_init_f(void)
int board_init(void)
{
+ struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
+
/* address of boot parameters */
gd-bd-bi_boot_params = PHYS_SDRAM + 0x100;
+ /*
+* Enable external 32K Oscillator
+*
+* The internal clock experiences significant drift
+* so we must use the external oscillator in order
+* to maintain correct time in the hwclock
+*/
+ setbits_le32(scsc-sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
+
return 0;
}
--
2.3.4
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[U-Boot] [RESEND PATCH 4/6] ARM: vf610: Enable caches
From: Stefan Agner ste...@agner.ch
Enables caches which provides a rather huge speedup of the boot loader.
Also mark the on-chip RAM as cachable since this is the area U-Boot runs
from.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/cpu/armv7/vf610/generic.c | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/cpu/armv7/vf610/generic.c
b/arch/arm/cpu/armv7/vf610/generic.c
index 3bdc221..1bb9b8e 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -342,3 +342,19 @@ int get_clocks(void)
#endif
return 0;
}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ enum dcache_option option = DCACHE_WRITETHROUGH;
+#else
+ enum dcache_option option = DCACHE_WRITEBACK;
+#endif
+ dcache_enable();
+ icache_enable();
+
+/* Enable caching on OCRAM */
+ mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
+}
+#endif
--
2.3.4
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[U-Boot] [RESEND PATCH 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/include/asm/arch-vf610/crm_regs.h | 14 ++
arch/arm/include/asm/arch-vf610/imx-regs.h | 4 +
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ehci-vf.c | 204 +
4 files changed, 223 insertions(+)
create mode 100644 drivers/usb/host/ehci-vf.c
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h
b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 78708e2..851c3b9 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -124,6 +124,10 @@ struct anadig_reg {
#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 16)
#define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) 0x7) 16)
+#define CCM_CCSR_PLL3_PFD4_EN (1 31)
+#define CCM_CCSR_PLL3_PFD3_EN (1 30)
+#define CCM_CCSR_PLL3_PFD2_EN (1 29)
+#define CCM_CCSR_PLL3_PFD1_EN (1 28)
#define CCM_CCSR_PLL2_PFD4_EN (1 15)
#define CCM_CCSR_PLL2_PFD3_EN (1 14)
#define CCM_CCSR_PLL2_PFD2_EN (1 13)
@@ -189,6 +193,7 @@ struct anadig_reg {
#define CCM_REG_CTRL_MASK 0x
#define CCM_CCGR0_UART0_CTRL_MASK (0x3 14)
#define CCM_CCGR0_UART1_CTRL_MASK (0x3 16)
+#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 8)
#define CCM_CCGR1_PIT_CTRL_MASK(0x3 14)
#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 28)
#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 8)
@@ -207,14 +212,23 @@ struct anadig_reg {
#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 10)
#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 28)
#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 4)
+#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 8)
#define CCM_CCGR9_FEC0_CTRL_MASK 0x3
#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 2)
#define CCM_CCGR10_NFC_CTRL_MASK 0x3
+#define ANADIG_PLL7_CTRL_BYPASS (1 16)
+#define ANADIG_PLL7_CTRL_ENABLE (1 13)
+#define ANADIG_PLL7_CTRL_POWERDOWN (1 12)
+#define ANADIG_PLL7_CTRL_DIV_SELECT (1 1)
#define ANADIG_PLL5_CTRL_BYPASS (1 16)
#define ANADIG_PLL5_CTRL_ENABLE (1 13)
#define ANADIG_PLL5_CTRL_POWERDOWN (1 12)
#define ANADIG_PLL5_CTRL_DIV_SELECT1
+#define ANADIG_PLL3_CTRL_BYPASS (1 16)
+#define ANADIG_PLL3_CTRL_ENABLE (1 13)
+#define ANADIG_PLL3_CTRL_POWERDOWN (1 12)
+#define ANADIG_PLL3_CTRL_DIV_SELECT (1 1)
#define ANADIG_PLL2_CTRL_ENABLE(1 13)
#define ANADIG_PLL2_CTRL_POWERDOWN (1 12)
#define ANADIG_PLL2_CTRL_DIV_SELECT1
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index a5908ca..26057fe 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -52,6 +52,7 @@
#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000)
+#define USBC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000)
#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
@@ -65,6 +66,8 @@
#define QSPI0_BASE_ADDR(AIPS0_BASE_ADDR + 0x00044000)
#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005)
+#define USB_PHY0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050800)
+#define USB_PHY1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050C00)
#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006)
#define SPDIF_BASE_ADDR(AIPS0_BASE_ADDR + 0x00061000)
@@ -84,6 +87,7 @@
#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000)
#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000)
#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
+#define USBC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00034000)
#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x0005)
#define ENET1_BASE_ADDR(AIPS1_BASE_ADDR + 0x00051000)
#define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x0006)
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index eb6f34b..4bd9321 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
obj-$(CONFIG_USB_EHCI_UNIPHIER) += ehci-uniphier.o
obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
+obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o
obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
diff --git
[U-Boot] [RESEND PATCH 0/6] Add support for Colibri Vybrid Modules
Hello, This patchset adds support for the Toradex Colibri Vybrid VF50 and VF61 modules. Boot up has been tested using the serial loader over UART. First patch in the series refactors the DDR related code for use by both the tower board and colibri modules. It also introduces a DDR3 based JEDEC timing structure. Second third and fourth patch in this series are improvement patches related to RTC, SoC/CPU detection and caches. Fifth patch introduces USB support for Vybrid modules. Much of the code is similar to the ehci-mx6 driver. One open question here would be is there a better way to take care of this similarity and perhaps share the code base among the two drivers? Both host and client modes are working and DFU has also been tested. Currently, we restrict the ports to be in one of host and client mode. Sixth patch adds the actual support for the Colibri modules. Comments and feedback are most welcome. The patchset is based and tested on the latest master branch as of this writing which is 2015.04-rc5. - Sanchayan. Sanchayan Maity (4): ARM: vf610: Move DDR3 initialization to imx-common ARM: vf610: Add SoC and CPU type detection usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's ARM: vf610: Initial integration for Colibri VF50/VF61 Stefan Agner (2): ARM: vf610: Enable external 32KHz oscillator ARM: vf610: Enable caches arch/arm/Kconfig | 5 + arch/arm/cpu/armv7/vf610/generic.c| 45 ++- arch/arm/imx-common/Makefile | 3 + arch/arm/imx-common/ddrmc-vf610.c | 278 ++ arch/arm/include/asm/arch-vf610/crm_regs.h| 15 + arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 72 + arch/arm/include/asm/arch-vf610/imx-regs.h| 36 ++- board/freescale/vf610twr/vf610twr.c | 295 +-- board/toradex/colibri_vf/Kconfig | 18 ++ board/toradex/colibri_vf/MAINTAINERS | 6 + board/toradex/colibri_vf/Makefile | 7 + board/toradex/colibri_vf/colibri_vf.c | 389 ++ board/toradex/colibri_vf/imximage.cfg | 17 ++ configs/colibri_vf_defconfig | 3 + drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-vf.c| 204 ++ include/configs/colibri_vf.h | 266 ++ 17 files changed, 1425 insertions(+), 235 deletions(-) create mode 100644 arch/arm/imx-common/ddrmc-vf610.c create mode 100644 arch/arm/include/asm/arch-vf610/ddrmc-vf610.h create mode 100644 board/toradex/colibri_vf/Kconfig create mode 100644 board/toradex/colibri_vf/MAINTAINERS create mode 100644 board/toradex/colibri_vf/Makefile create mode 100644 board/toradex/colibri_vf/colibri_vf.c create mode 100644 board/toradex/colibri_vf/imximage.cfg create mode 100644 configs/colibri_vf_defconfig create mode 100644 drivers/usb/host/ehci-vf.c create mode 100644 include/configs/colibri_vf.h -- 2.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RESEND PATCH 3/6] ARM: vf610: Add SoC and CPU type detection
Vybrid product family consists of several rather similar SoC which
can be determined by softare during boot time. This allows use of
variable ${soc} for Linux device tree files. Detect VF5xx CPU's by
reading the CPU count register. We can determine the second number
of the CPU type (VF6x0) which indicates the presence of a L2 cache.
Signed-off-by: Stefan Agner ste...@agner.ch
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/cpu/armv7/vf610/generic.c | 29 +++--
arch/arm/include/asm/arch-vf610/imx-regs.h | 12
2 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/vf610/generic.c
b/arch/arm/cpu/armv7/vf610/generic.c
index 92aaad9..3bdc221 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -18,6 +18,8 @@
DECLARE_GLOBAL_DATA_PTR;
#endif
+static char soc_type[] = xx0;
+
#ifdef CONFIG_MXC_OCOTP
void enable_ocotp_clk(unsigned char enable)
{
@@ -284,14 +286,37 @@ static char *get_reset_cause(void)
int print_cpuinfo(void)
{
- printf(CPU: Freescale Vybrid VF610 at %d MHz\n,
- mxc_get_clock(MXC_ARM_CLK) / 100);
+ printf(CPU: Freescale Vybrid VF%s at %d MHz\n,
+ soc_type, mxc_get_clock(MXC_ARM_CLK) / 100);
printf(Reset cause: %s\n, get_reset_cause());
return 0;
}
#endif
+int arch_cpu_init(void)
+{
+ struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
+
+ soc_type[0] = mscm-cpxcount ? '6' : '5'; /*Dual Core = VF6x0 */
+ soc_type[1] = mscm-cpxcfg1 ? '1' : '0'; /* L2 Cache = VFx10 */
+
+ return 0;
+}
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ char soc[6];
+
+ strcat(soc, vf);
+ strcat(soc, soc_type);
+ setenv(soc, soc);
+
+ return 0;
+}
+#endif
+
int cpu_eth_init(bd_t *bis)
{
int rc = -ENODEV;
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index aa60031..a5908ca 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -457,6 +457,18 @@ struct scsc_reg {
u32 sosc_ctr;
};
+/* MSCM */
+struct mscm {
+ u32 cpxtype;
+ u32 cpxnum;
+ u32 cpxmaster;
+ u32 cpxcount;
+ u32 cpxcfg0;
+ u32 cpxcfg1;
+ u32 cpxcfg2;
+ u32 cpxcfg3;
+};
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_IMX_REGS_H__ */
--
2.3.4
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[U-Boot] [RESEND PATCH 6/6] ARM: vf610: Initial integration for Colibri VF50/VF61
This adds initial support for Colibri VF50/VF61 based on Freescale Vybrid SoC. - CPU clocked at 396/500 MHz - DDR3 at 396MHz - for VF50, use PLL2 as memory clock (synchronous mode) - for VF61, use PLL1 as memory clock (asynchronous mode) - Console on UART0 (Colibri UART_A) - Ethernet on FEC1 - PLL5 based RMII clocking (E.g. No external crystal) - UART_A and UART_C I/O muxing - Boot from NAND by default - USB host and client support Tested on Colibri VF50/VF61 booting using serial loader over UART. Signed-off-by: Stefan Agner ste...@agner.ch Signed-off-by: Sanchayan Maity maitysancha...@gmail.com --- arch/arm/Kconfig | 5 + arch/arm/include/asm/arch-vf610/imx-regs.h | 5 + board/toradex/colibri_vf/Kconfig | 18 ++ board/toradex/colibri_vf/MAINTAINERS | 6 + board/toradex/colibri_vf/Makefile | 7 + board/toradex/colibri_vf/colibri_vf.c | 389 + board/toradex/colibri_vf/imximage.cfg | 17 ++ configs/colibri_vf_defconfig | 3 + include/configs/colibri_vf.h | 266 9 files changed, 716 insertions(+) create mode 100644 board/toradex/colibri_vf/Kconfig create mode 100644 board/toradex/colibri_vf/MAINTAINERS create mode 100644 board/toradex/colibri_vf/Makefile create mode 100644 board/toradex/colibri_vf/colibri_vf.c create mode 100644 board/toradex/colibri_vf/imximage.cfg create mode 100644 configs/colibri_vf_defconfig create mode 100644 include/configs/colibri_vf.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 80b0d34..e32a942 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -608,6 +608,10 @@ config TARGET_VF610TWR bool Support vf610twr select CPU_V7 +config TARGET_COLIBRI_VF + bool Support Colibri VF50/61 + select CPU_V7 + config ZYNQ bool Xilinx Zynq Platform select CPU_V7 @@ -864,6 +868,7 @@ source board/ti/ti814x/Kconfig source board/ti/ti816x/Kconfig source board/timll/devkit3250/Kconfig source board/toradex/colibri_pxa270/Kconfig +source board/toradex/colibri_vf/Kconfig source board/tqc/tqma6/Kconfig source board/trizepsiv/Kconfig source board/ttcontrol/vision2/Kconfig diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 26057fe..a7d765a 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -267,6 +267,11 @@ #define SRC_SRSR_WDOG_M4 (0x1 4) #define SRC_SRSR_WDOG_A5 (0x1 3) #define SRC_SRSR_POR_RST (0x1 0) +#define SRC_SBMR2_BMOD_MASK (0x3 24) +#define SRC_SBMR2_BMOD_SHIFT24 +#define SRC_SBMR2_BMOD_FUSES0x0 +#define SRC_SBMR2_BMOD_SERIAL 0x1 +#define SRC_SBMR2_BMOD_RCON 0x2 /* Slow Clock Source Controller Module (SCSC) */ #define SCSC_SOSC_CTR_SOSC_EN0x1 diff --git a/board/toradex/colibri_vf/Kconfig b/board/toradex/colibri_vf/Kconfig new file mode 100644 index 000..2c3cb30 --- /dev/null +++ b/board/toradex/colibri_vf/Kconfig @@ -0,0 +1,18 @@ +if TARGET_COLIBRI_VF + +config SYS_CPU + default armv7 + +config SYS_BOARD + default colibri_vf + +config SYS_VENDOR + default toradex + +config SYS_SOC + default vf610 + +config SYS_CONFIG_NAME + default colibri_vf + +endif diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS new file mode 100644 index 000..551c575 --- /dev/null +++ b/board/toradex/colibri_vf/MAINTAINERS @@ -0,0 +1,6 @@ +Colibri VFxx +M: Stefan Agner stefan.ag...@toradex.com +S: Maintained +F: board/toradex/colibri_vf/ +F: include/configs/colibri_vf.h +F: configs/colibri_vf_defconfig diff --git a/board/toradex/colibri_vf/Makefile b/board/toradex/colibri_vf/Makefile new file mode 100644 index 000..c7e5134 --- /dev/null +++ b/board/toradex/colibri_vf/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := colibri_vf.o diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c new file mode 100644 index 000..62f3013 --- /dev/null +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -0,0 +1,389 @@ +/* + * Copyright 2015 Toradex, Inc. + * + * Based on vf610twr.c: + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include common.h +#include asm/io.h +#include asm/arch/imx-regs.h +#include asm/arch/iomux-vf610.h +#include asm/arch/ddrmc-vf610.h +#include asm/arch/crm_regs.h +#include asm/arch/clock.h +#include mmc.h +#include fsl_esdhc.h +#include miiphy.h +#include netdev.h +#include i2c.h +#include g_dnl.h + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_25ohm
[U-Boot] [PATCH 6/6] ARM: vf610: Initial integration for Colibri VF50/VF61
This adds initial support for Colibri VF50/VF61 based on Freescale Vybrid SoC. - CPU clocked at 396/500 MHz - DDR3 at 396MHz - for VF50, use PLL2 as memory clock (synchronous mode) - for VF61, use PLL1 as memory clock (asynchronous mode) - Console on UART0 (Colibri UART_A) - Ethernet on FEC1 - PLL5 based RMII clocking (E.g. No external crystal) - UART_A and UART_C I/O muxing - Boot from NAND by default - USB host and client support Tested on Colibri VF50/VF61 booting using serial loader over UART. Signed-off-by: Stefan Agner ste...@agner.ch Signed-off-by: Sanchayan Maity maitysancha...@gmail.com --- arch/arm/Kconfig | 5 + arch/arm/include/asm/arch-vf610/imx-regs.h | 5 + board/toradex/colibri_vf/Kconfig | 18 ++ board/toradex/colibri_vf/MAINTAINERS | 6 + board/toradex/colibri_vf/Makefile | 7 + board/toradex/colibri_vf/colibri_vf.c | 389 + board/toradex/colibri_vf/imximage.cfg | 17 ++ configs/colibri_vf_defconfig | 3 + include/configs/colibri_vf.h | 266 9 files changed, 716 insertions(+) create mode 100644 board/toradex/colibri_vf/Kconfig create mode 100644 board/toradex/colibri_vf/MAINTAINERS create mode 100644 board/toradex/colibri_vf/Makefile create mode 100644 board/toradex/colibri_vf/colibri_vf.c create mode 100644 board/toradex/colibri_vf/imximage.cfg create mode 100644 configs/colibri_vf_defconfig create mode 100644 include/configs/colibri_vf.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b9ebee1..96316d0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -609,6 +609,10 @@ config TARGET_VF610TWR bool Support vf610twr select CPU_V7 +config TARGET_COLIBRI_VF + bool Support Colibri VF50/61 + select CPU_V7 + config ZYNQ bool Xilinx Zynq Platform select CPU_V7 @@ -863,6 +867,7 @@ source board/ti/ti814x/Kconfig source board/ti/ti816x/Kconfig source board/timll/devkit3250/Kconfig source board/toradex/colibri_pxa270/Kconfig +source board/toradex/colibri_vf/Kconfig source board/tqc/tqma6/Kconfig source board/trizepsiv/Kconfig source board/ttcontrol/vision2/Kconfig diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 26057fe..a7d765a 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -267,6 +267,11 @@ #define SRC_SRSR_WDOG_M4 (0x1 4) #define SRC_SRSR_WDOG_A5 (0x1 3) #define SRC_SRSR_POR_RST (0x1 0) +#define SRC_SBMR2_BMOD_MASK (0x3 24) +#define SRC_SBMR2_BMOD_SHIFT24 +#define SRC_SBMR2_BMOD_FUSES0x0 +#define SRC_SBMR2_BMOD_SERIAL 0x1 +#define SRC_SBMR2_BMOD_RCON 0x2 /* Slow Clock Source Controller Module (SCSC) */ #define SCSC_SOSC_CTR_SOSC_EN0x1 diff --git a/board/toradex/colibri_vf/Kconfig b/board/toradex/colibri_vf/Kconfig new file mode 100644 index 000..2c3cb30 --- /dev/null +++ b/board/toradex/colibri_vf/Kconfig @@ -0,0 +1,18 @@ +if TARGET_COLIBRI_VF + +config SYS_CPU + default armv7 + +config SYS_BOARD + default colibri_vf + +config SYS_VENDOR + default toradex + +config SYS_SOC + default vf610 + +config SYS_CONFIG_NAME + default colibri_vf + +endif diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS new file mode 100644 index 000..551c575 --- /dev/null +++ b/board/toradex/colibri_vf/MAINTAINERS @@ -0,0 +1,6 @@ +Colibri VFxx +M: Stefan Agner stefan.ag...@toradex.com +S: Maintained +F: board/toradex/colibri_vf/ +F: include/configs/colibri_vf.h +F: configs/colibri_vf_defconfig diff --git a/board/toradex/colibri_vf/Makefile b/board/toradex/colibri_vf/Makefile new file mode 100644 index 000..c7e5134 --- /dev/null +++ b/board/toradex/colibri_vf/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := colibri_vf.o diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c new file mode 100644 index 000..62f3013 --- /dev/null +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -0,0 +1,389 @@ +/* + * Copyright 2015 Toradex, Inc. + * + * Based on vf610twr.c: + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include common.h +#include asm/io.h +#include asm/arch/imx-regs.h +#include asm/arch/iomux-vf610.h +#include asm/arch/ddrmc-vf610.h +#include asm/arch/crm_regs.h +#include asm/arch/clock.h +#include mmc.h +#include fsl_esdhc.h +#include miiphy.h +#include netdev.h +#include i2c.h +#include g_dnl.h + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_25ohm
[U-Boot] [PATCH 2/6] ARM: vf610: Enable external 32KHz oscillator
From: Stefan Agner ste...@agner.ch
Enable the SCSC (Slow Clock Source Controller) and select the external
32KHz oscillator. This improves the accuracy of the RTC.
Signed-off-by: Stefan Agner ste...@agner.ch
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/include/asm/arch-vf610/crm_regs.h | 1 +
arch/arm/include/asm/arch-vf610/imx-regs.h | 11 ++-
board/freescale/vf610twr/vf610twr.c| 13 -
3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h
b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 724682c..78708e2 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -199,6 +199,7 @@ struct anadig_reg {
#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 24)
#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 26)
#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
+#define CCM_CCGR3_SCSC_CTRL_MASK(0x3 4)
#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 20)
#define CCM_CCGR4_CCM_CTRL_MASK(0x3 22)
#define CCM_CCGR4_GPC_CTRL_MASK(0x3 24)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 866b303..aa60031 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -65,7 +65,7 @@
#define QSPI0_BASE_ADDR(AIPS0_BASE_ADDR + 0x00044000)
#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005)
-#define SCSCM_BASE_ADDR(AIPS0_BASE_ADDR + 0x00052000)
+#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006)
#define SPDIF_BASE_ADDR(AIPS0_BASE_ADDR + 0x00061000)
#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
@@ -264,6 +264,9 @@
#define SRC_SRSR_WDOG_A5 (0x1 3)
#define SRC_SRSR_POR_RST (0x1 0)
+/* Slow Clock Source Controller Module (SCSC) */
+#define SCSC_SOSC_CTR_SOSC_EN0x1
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include asm/types.h
@@ -448,6 +451,12 @@ struct mscm_ir {
u16 rsvd3[848];
};
+/* SCSC */
+struct scsc_reg {
+ u32 sirc_ctr;
+ u32 sosc_ctr;
+};
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/board/freescale/vf610twr/vf610twr.c
b/board/freescale/vf610twr/vf610twr.c
index eb27542..4160acd 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -227,7 +227,7 @@ static void clock_init(void)
CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
CCM_CCGR2_QSPI0_CTRL_MASK);
clrsetbits_le32(ccm-ccgr3, CCM_REG_CTRL_MASK,
- CCM_CCGR3_ANADIG_CTRL_MASK);
+ CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
clrsetbits_le32(ccm-ccgr4, CCM_REG_CTRL_MASK,
CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
@@ -308,9 +308,20 @@ int board_early_init_f(void)
int board_init(void)
{
+ struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
+
/* address of boot parameters */
gd-bd-bi_boot_params = PHYS_SDRAM + 0x100;
+ /*
+* Enable external 32K Oscillator
+*
+* The internal clock experiences significant drift
+* so we must use the external oscillator in order
+* to maintain correct time in the hwclock
+*/
+ setbits_le32(scsc-sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
+
return 0;
}
--
2.3.3
___
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[U-Boot] [PATCH 1/6] ARM: vf610: Move DDR3 initialization to imx-common
In order to avoid code duplication, move the DDR3 initialization to the
common place under imx-common. Currently ROW_DIFF and COL_DIFF can be
chosen from the board file. The JEDEC timings are specified using a
common ddr3_jedec_timings structure.
Signed-off-by: Stefan Agner ste...@agner.ch
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/imx-common/Makefile | 3 +
arch/arm/imx-common/ddrmc-vf610.c | 278 +
arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 72 +++
arch/arm/include/asm/arch-vf610/imx-regs.h| 4 +-
board/freescale/vf610twr/vf610twr.c | 282 +-
5 files changed, 408 insertions(+), 231 deletions(-)
create mode 100644 arch/arm/imx-common/ddrmc-vf610.c
create mode 100644 arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 606482f..b9f1ca4 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -22,6 +22,9 @@ ifeq ($(SOC),$(filter $(SOC),mx6))
obj-$(CONFIG_CMD_SATA) += sata.o
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
endif
+ifeq ($(SOC),$(filter $(SOC),vf610))
+obj-y += ddrmc-vf610.o
+endif
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
diff --git a/arch/arm/imx-common/ddrmc-vf610.c
b/arch/arm/imx-common/ddrmc-vf610.c
new file mode 100644
index 000..e462631
--- /dev/null
+++ b/arch/arm/imx-common/ddrmc-vf610.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright 2015 Toradex, Inc.
+ *
+ * Based on vf610twr:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm/io.h
+#include asm/arch/imx-regs.h
+#include asm/arch/iomux-vf610.h
+#include asm/arch/ddrmc-vf610.h
+
+void ddrmc_setup_iomux(void)
+{
+ static const iomux_v3_cfg_t ddr_pads[] = {
+ VF610_PAD_DDR_A15__DDR_A_15,
+ VF610_PAD_DDR_A14__DDR_A_14,
+ VF610_PAD_DDR_A13__DDR_A_13,
+ VF610_PAD_DDR_A12__DDR_A_12,
+ VF610_PAD_DDR_A11__DDR_A_11,
+ VF610_PAD_DDR_A10__DDR_A_10,
+ VF610_PAD_DDR_A9__DDR_A_9,
+ VF610_PAD_DDR_A8__DDR_A_8,
+ VF610_PAD_DDR_A7__DDR_A_7,
+ VF610_PAD_DDR_A6__DDR_A_6,
+ VF610_PAD_DDR_A5__DDR_A_5,
+ VF610_PAD_DDR_A4__DDR_A_4,
+ VF610_PAD_DDR_A3__DDR_A_3,
+ VF610_PAD_DDR_A2__DDR_A_2,
+ VF610_PAD_DDR_A1__DDR_A_1,
+ VF610_PAD_DDR_A0__DDR_A_0,
+ VF610_PAD_DDR_BA2__DDR_BA_2,
+ VF610_PAD_DDR_BA1__DDR_BA_1,
+ VF610_PAD_DDR_BA0__DDR_BA_0,
+ VF610_PAD_DDR_CAS__DDR_CAS_B,
+ VF610_PAD_DDR_CKE__DDR_CKE_0,
+ VF610_PAD_DDR_CLK__DDR_CLK_0,
+ VF610_PAD_DDR_CS__DDR_CS_B_0,
+ VF610_PAD_DDR_D15__DDR_D_15,
+ VF610_PAD_DDR_D14__DDR_D_14,
+ VF610_PAD_DDR_D13__DDR_D_13,
+ VF610_PAD_DDR_D12__DDR_D_12,
+ VF610_PAD_DDR_D11__DDR_D_11,
+ VF610_PAD_DDR_D10__DDR_D_10,
+ VF610_PAD_DDR_D9__DDR_D_9,
+ VF610_PAD_DDR_D8__DDR_D_8,
+ VF610_PAD_DDR_D7__DDR_D_7,
+ VF610_PAD_DDR_D6__DDR_D_6,
+ VF610_PAD_DDR_D5__DDR_D_5,
+ VF610_PAD_DDR_D4__DDR_D_4,
+ VF610_PAD_DDR_D3__DDR_D_3,
+ VF610_PAD_DDR_D2__DDR_D_2,
+ VF610_PAD_DDR_D1__DDR_D_1,
+ VF610_PAD_DDR_D0__DDR_D_0,
+ VF610_PAD_DDR_DQM1__DDR_DQM_1,
+ VF610_PAD_DDR_DQM0__DDR_DQM_0,
+ VF610_PAD_DDR_DQS1__DDR_DQS_1,
+ VF610_PAD_DDR_DQS0__DDR_DQS_0,
+ VF610_PAD_DDR_RAS__DDR_RAS_B,
+ VF610_PAD_DDR_WE__DDR_WE_B,
+ VF610_PAD_DDR_ODT1__DDR_ODT_0,
+ VF610_PAD_DDR_ODT0__DDR_ODT_1,
+ VF610_PAD_DDR_RESETB,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
+}
+
+void ddrmc_phy_init(void)
+{
+ struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+ writel(DDRMC_PHY_DQ_TIMING, ddrmr-phy[0]);
+ writel(DDRMC_PHY_DQ_TIMING, ddrmr-phy[16]);
+ writel(DDRMC_PHY_DQ_TIMING, ddrmr-phy[32]);
+
+ writel(DDRMC_PHY_DQS_TIMING, ddrmr-phy[1]);
+ writel(DDRMC_PHY_DQS_TIMING, ddrmr-phy[17]);
+
+ writel(DDRMC_PHY_CTRL, ddrmr-phy[2]);
+ writel(DDRMC_PHY_CTRL, ddrmr-phy[18]);
+ writel(DDRMC_PHY_CTRL, ddrmr-phy[34]);
+
+ writel(DDRMC_PHY_MASTER_CTRL, ddrmr-phy[3]);
+ writel(DDRMC_PHY_MASTER_CTRL, ddrmr-phy[19]);
+ writel(DDRMC_PHY_MASTER_CTRL, ddrmr-phy[35]);
+
+ writel(DDRMC_PHY_SLAVE_CTRL, ddrmr-phy[4]);
+ writel(DDRMC_PHY_SLAVE_CTRL, ddrmr-phy[20]);
+ writel(DDRMC_PHY_SLAVE_CTRL, ddrmr-phy[36]);
+
+ /* LPDDR2
[U-Boot] [PATCH 0/6] Add support for Colibri Vybrid Modules
Hello, This patchset adds support for the Toradex Colibri Vybrid VF50 and VF61 modules. Boot up has been tested using the serial loader over UART. First patch in the series refactors the DDR related code for use by both the tower board and colibri modules. It also introduces a DDR3 based JEDEC timing structure. Second third and fourth patch in this series are improvement patches related to RTC, SoC/CPU detection and caches. Fifth patch introduces USB support for Vybrid modules. Much of the code is similar to the ehci-mx6 driver. One open question here would be is there a better way to take care of this similarity and perhaps share the code base among the two drivers? Both host and client modes are working and DFU has also been tested. Currently, we restrict the ports to be in one of host and client mode. Sixth patch adds the actual support for the Colibri modules. Comments and feedback are most welcome. The patchset has been based and tested on the latest master branch as of this writing. - Sanchayan. Sanchayan Maity (4): ARM: vf610: Move DDR3 initialization to imx-common ARM: vf610: Add SoC and CPU type detection usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's ARM: vf610: Initial integration for Colibri VF50/VF61 Stefan Agner (2): ARM: vf610: Enable external 32KHz oscillator ARM: vf610: Enable caches arch/arm/Kconfig | 5 + arch/arm/cpu/armv7/vf610/generic.c| 45 ++- arch/arm/imx-common/Makefile | 3 + arch/arm/imx-common/ddrmc-vf610.c | 278 ++ arch/arm/include/asm/arch-vf610/crm_regs.h| 15 + arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 72 + arch/arm/include/asm/arch-vf610/imx-regs.h| 36 ++- board/freescale/vf610twr/vf610twr.c | 295 +-- board/toradex/colibri_vf/Kconfig | 18 ++ board/toradex/colibri_vf/MAINTAINERS | 6 + board/toradex/colibri_vf/Makefile | 7 + board/toradex/colibri_vf/colibri_vf.c | 389 ++ board/toradex/colibri_vf/imximage.cfg | 17 ++ configs/colibri_vf_defconfig | 3 + drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-vf.c| 204 ++ include/configs/colibri_vf.h | 266 ++ 17 files changed, 1425 insertions(+), 235 deletions(-) create mode 100644 arch/arm/imx-common/ddrmc-vf610.c create mode 100644 arch/arm/include/asm/arch-vf610/ddrmc-vf610.h create mode 100644 board/toradex/colibri_vf/Kconfig create mode 100644 board/toradex/colibri_vf/MAINTAINERS create mode 100644 board/toradex/colibri_vf/Makefile create mode 100644 board/toradex/colibri_vf/colibri_vf.c create mode 100644 board/toradex/colibri_vf/imximage.cfg create mode 100644 configs/colibri_vf_defconfig create mode 100644 drivers/usb/host/ehci-vf.c create mode 100644 include/configs/colibri_vf.h -- 2.3.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/include/asm/arch-vf610/crm_regs.h | 14 ++
arch/arm/include/asm/arch-vf610/imx-regs.h | 4 +
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ehci-vf.c | 204 +
4 files changed, 223 insertions(+)
create mode 100644 drivers/usb/host/ehci-vf.c
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h
b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 78708e2..851c3b9 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -124,6 +124,10 @@ struct anadig_reg {
#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 16)
#define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) 0x7) 16)
+#define CCM_CCSR_PLL3_PFD4_EN (1 31)
+#define CCM_CCSR_PLL3_PFD3_EN (1 30)
+#define CCM_CCSR_PLL3_PFD2_EN (1 29)
+#define CCM_CCSR_PLL3_PFD1_EN (1 28)
#define CCM_CCSR_PLL2_PFD4_EN (1 15)
#define CCM_CCSR_PLL2_PFD3_EN (1 14)
#define CCM_CCSR_PLL2_PFD2_EN (1 13)
@@ -189,6 +193,7 @@ struct anadig_reg {
#define CCM_REG_CTRL_MASK 0x
#define CCM_CCGR0_UART0_CTRL_MASK (0x3 14)
#define CCM_CCGR0_UART1_CTRL_MASK (0x3 16)
+#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 8)
#define CCM_CCGR1_PIT_CTRL_MASK(0x3 14)
#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 28)
#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 8)
@@ -207,14 +212,23 @@ struct anadig_reg {
#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 10)
#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 28)
#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 4)
+#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 8)
#define CCM_CCGR9_FEC0_CTRL_MASK 0x3
#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 2)
#define CCM_CCGR10_NFC_CTRL_MASK 0x3
+#define ANADIG_PLL7_CTRL_BYPASS (1 16)
+#define ANADIG_PLL7_CTRL_ENABLE (1 13)
+#define ANADIG_PLL7_CTRL_POWERDOWN (1 12)
+#define ANADIG_PLL7_CTRL_DIV_SELECT (1 1)
#define ANADIG_PLL5_CTRL_BYPASS (1 16)
#define ANADIG_PLL5_CTRL_ENABLE (1 13)
#define ANADIG_PLL5_CTRL_POWERDOWN (1 12)
#define ANADIG_PLL5_CTRL_DIV_SELECT1
+#define ANADIG_PLL3_CTRL_BYPASS (1 16)
+#define ANADIG_PLL3_CTRL_ENABLE (1 13)
+#define ANADIG_PLL3_CTRL_POWERDOWN (1 12)
+#define ANADIG_PLL3_CTRL_DIV_SELECT (1 1)
#define ANADIG_PLL2_CTRL_ENABLE(1 13)
#define ANADIG_PLL2_CTRL_POWERDOWN (1 12)
#define ANADIG_PLL2_CTRL_DIV_SELECT1
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index a5908ca..26057fe 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -52,6 +52,7 @@
#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000)
+#define USBC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000)
#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
@@ -65,6 +66,8 @@
#define QSPI0_BASE_ADDR(AIPS0_BASE_ADDR + 0x00044000)
#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005)
+#define USB_PHY0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050800)
+#define USB_PHY1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050C00)
#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006)
#define SPDIF_BASE_ADDR(AIPS0_BASE_ADDR + 0x00061000)
@@ -84,6 +87,7 @@
#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000)
#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000)
#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
+#define USBC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00034000)
#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x0005)
#define ENET1_BASE_ADDR(AIPS1_BASE_ADDR + 0x00051000)
#define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x0006)
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index eb6f34b..4bd9321 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
obj-$(CONFIG_USB_EHCI_UNIPHIER) += ehci-uniphier.o
obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
+obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o
obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
diff --git
[U-Boot] [PATCH 3/6] ARM: vf610: Add SoC and CPU type detection
Vybrid product family consists of several rather similar SoC which
can be determined by softare during boot time. This allows use of
variable ${soc} for Linux device tree files. Detect VF5xx CPU's by
reading the CPU count register. We can determine the second number
of the CPU type (VF6x0) which indicates the presence of a L2 cache.
Signed-off-by: Stefan Agner ste...@agner.ch
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/cpu/armv7/vf610/generic.c | 29 +++--
arch/arm/include/asm/arch-vf610/imx-regs.h | 12
2 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/vf610/generic.c
b/arch/arm/cpu/armv7/vf610/generic.c
index 92aaad9..3bdc221 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -18,6 +18,8 @@
DECLARE_GLOBAL_DATA_PTR;
#endif
+static char soc_type[] = xx0;
+
#ifdef CONFIG_MXC_OCOTP
void enable_ocotp_clk(unsigned char enable)
{
@@ -284,14 +286,37 @@ static char *get_reset_cause(void)
int print_cpuinfo(void)
{
- printf(CPU: Freescale Vybrid VF610 at %d MHz\n,
- mxc_get_clock(MXC_ARM_CLK) / 100);
+ printf(CPU: Freescale Vybrid VF%s at %d MHz\n,
+ soc_type, mxc_get_clock(MXC_ARM_CLK) / 100);
printf(Reset cause: %s\n, get_reset_cause());
return 0;
}
#endif
+int arch_cpu_init(void)
+{
+ struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
+
+ soc_type[0] = mscm-cpxcount ? '6' : '5'; /*Dual Core = VF6x0 */
+ soc_type[1] = mscm-cpxcfg1 ? '1' : '0'; /* L2 Cache = VFx10 */
+
+ return 0;
+}
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ char soc[6];
+
+ strcat(soc, vf);
+ strcat(soc, soc_type);
+ setenv(soc, soc);
+
+ return 0;
+}
+#endif
+
int cpu_eth_init(bd_t *bis)
{
int rc = -ENODEV;
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index aa60031..a5908ca 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -457,6 +457,18 @@ struct scsc_reg {
u32 sosc_ctr;
};
+/* MSCM */
+struct mscm {
+ u32 cpxtype;
+ u32 cpxnum;
+ u32 cpxmaster;
+ u32 cpxcount;
+ u32 cpxcfg0;
+ u32 cpxcfg1;
+ u32 cpxcfg2;
+ u32 cpxcfg3;
+};
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_IMX_REGS_H__ */
--
2.3.3
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[U-Boot] [PATCH 4/6] ARM: vf610: Enable caches
From: Stefan Agner ste...@agner.ch
Enables caches which provides a rather huge speedup of the boot loader.
Also mark the on-chip RAM as cachable since this is the area U-Boot runs
from.
Signed-off-by: Stefan Agner ste...@agner.ch
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/cpu/armv7/vf610/generic.c | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/cpu/armv7/vf610/generic.c
b/arch/arm/cpu/armv7/vf610/generic.c
index 3bdc221..1bb9b8e 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -342,3 +342,19 @@ int get_clocks(void)
#endif
return 0;
}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ enum dcache_option option = DCACHE_WRITETHROUGH;
+#else
+ enum dcache_option option = DCACHE_WRITEBACK;
+#endif
+ dcache_enable();
+ icache_enable();
+
+/* Enable caching on OCRAM */
+ mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
+}
+#endif
--
2.3.3
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Re: [U-Boot] [PATCH] mtd/nand/vf610_nfc: Disable subpage writes
On Monday 24 November 2014 11:03 AM, Sanchayan Maity wrote: This patch disables subpage writes for vf610_nfc nand driver. This is required, as without this fix, writing unaligned u-boot images with DFU results in a hang. Trying to write unalgined binary images also results in a hang, without disabling subpage writes. Patch has been tested on a Colibri VF61 module. Signed-off-by: Sanchayan Maity maitysancha...@gmail.com --- drivers/mtd/nand/vf610_nfc.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c index 7feb3a7..928d58b 100644 --- a/drivers/mtd/nand/vf610_nfc.c +++ b/drivers/mtd/nand/vf610_nfc.c @@ -611,6 +611,9 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr) vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT); } + /* Disable subpage writes as we do not provide ecc-hwctl */ + chip-options |= NAND_NO_SUBPAGE_WRITE; + chip-dev_ready = vf610_nfc_dev_ready; chip-cmdfunc = vf610_nfc_command; chip-read_byte = vf610_nfc_read_byte; Ping? -Regards, Sanchayan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] mtd/nand/vf610_nfc: Disable subpage writes
This patch disables subpage writes for vf610_nfc nand driver. This is required, as without this fix, writing unaligned u-boot images with DFU results in a hang. Trying to write unalgined binary images also results in a hang, without disabling subpage writes. Patch has been tested on a Colibri VF61 module. Signed-off-by: Sanchayan Maity maitysancha...@gmail.com --- drivers/mtd/nand/vf610_nfc.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c index 7feb3a7..928d58b 100644 --- a/drivers/mtd/nand/vf610_nfc.c +++ b/drivers/mtd/nand/vf610_nfc.c @@ -611,6 +611,9 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr) vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT); } + /* Disable subpage writes as we do not provide ecc-hwctl */ + chip-options |= NAND_NO_SUBPAGE_WRITE; + chip-dev_ready = vf610_nfc_dev_ready; chip-cmdfunc = vf610_nfc_command; chip-read_byte = vf610_nfc_read_byte; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Query on the ci_udc driver for USB client implementation
On Tuesday 04 November 2014 09:58 PM, Lukasz Majewski wrote: Hi Sanchayan, On Tuesday 04 November 2014 10:25 AM, Marek Vasut wrote: On Monday, November 03, 2014 at 04:46:48 PM, Fabio Estevam wrote: On Mon, Nov 3, 2014 at 3:33 AM, Sanchayan Maity maitysancha...@gmail.com wrote: Hello, Any pointers? Adding Marek and Stefan on Cc in case they can provide some help. Regards, Fabio Estevam Thanks Regards, Sanchayan Maity. On Thursday 30 October 2014 11:14 AM, Sanchayan Maity wrote: Hello, I am currently implementing USB Host and client support for Freescale Vybrid platform in u-boot. I managed to get the host implementation working. For the host side, usb start calls usb_init(), which in turns call, usb_lowlevel_init(), from there into the ehic_hcd_init() of my implementation. So, setting up the necessary clocks and plls for USB in my implementation and then setting up the usb_ehci, ehci_hccr and echi_hcor structures was all. The flow and setup required i was able to trace. The USB client part is not clear to me. I was thinking i can use the ci_udc driver somehow to implement the client part. How can i use the ci_udc driver to implement client functionality?. From what i could see, the usb_gadget_driver_register() is suppose to be the first call. But, i couldn't trace from where this gets called or the flow and setup is suppose to be. OR Is a separate client driver required and nothing generic can be used akin to how it could be done for host? See include/configs/sansa_fuze_plus.h , you need the gadget driver for the function you want to implement , in this case it's ethernet for example (selected via CONFIG_USB_ETH_CDC ). An example of DFU/UMS can be found in include/configs/exynos4-common.h and to activate those, you need to use the 'dfu' or 'ums' commands. Thank you Marek. I had enabled usb ether options already and was trying to test USB client functionality with RNDIS. For some reason it was not working and i was not able to trace the issue and subsequently was not sure about the client part. Your inputs cleared my doubts. I tried UMS and DFU. UMS is working just fine and i can download the respective images through DFU. Though this DFU is not working full proof, but, i can figure that out now i feel. I'm very happy that UMS is working seamlessly. What kind of trouble do you have with DFU? Hello, I have a memory alignment problem with DFU as of now. mtdparts is as below device nand0 fsl_nfc, # parts = 4 #: namesizeoffset mask_flags 0: vf-bcb 0x0002 0x 1 1: u-boot 0x0016 0x0002 1 2: u-boot-env 0x0008 0x0018 0 3: ubi 0x3fe0 0x0020 0 active partition: nand0,0 - (vf-bcb) 0x0002 @ 0x defaults: mtdids : nand0=fsl_nfc mtdparts: mtdparts=fsl_nfc:128k(vf-bcb)ro,1408k(u-boot)ro,512k(u-boot-env),-(ubi) As per the above, setenv dfu_alt_info vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4 and CONFIG_SYS_CACHELINE_SIZE is 32. I have a ubifs image and i was trying to write it by running dfu 0 nand 4 in u-boot and sudo dfu-util -D ubifs.img -a ubi on the host. I got the error as below. dfu_get_buf: Could not memalign 0x80 bytes Setting CONFIG_SYS_DFU_DATA_BUF_SIZE to (1024*1024) resolved this. After this, trying an update as above, did not give me an updated ubi (which i check by booting to user space) and doing a nand erase.part on ubi partition and then repeating the procedure results in Bad Linux ARM zImage magic!. After looking a bit online, at the below two links http://lists.denx.de/pipermail/u-boot/2013-May/155089.html http://www.linux-mtd.infradead.org/faq/ubifs.html#L_mkfubifs I started trying ubinize. Getting the memory alignment issues again now :). I have tried 1, 2, 4 and 8Mb for the dfu data buffer size. So i am trying to figure this out at the moment. I am probably missing something. :) --Best Regards, Sanchayan. Thanks again for your inputs. Cheers! Best Regards, Sanchayan. Sorry if i am asking this question in the wrong place. I couldn't find anyone in the u-boot IRC channel nor find something similar to the kernel-newbies mailing list. There isn't any, so ask away ;-) Hope i am asking the right questions. [...] Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Query on the ci_udc driver for USB client implementation
On Tuesday 04 November 2014 10:25 AM, Marek Vasut wrote: On Monday, November 03, 2014 at 04:46:48 PM, Fabio Estevam wrote: On Mon, Nov 3, 2014 at 3:33 AM, Sanchayan Maity maitysancha...@gmail.com wrote: Hello, Any pointers? Adding Marek and Stefan on Cc in case they can provide some help. Regards, Fabio Estevam Thanks Regards, Sanchayan Maity. On Thursday 30 October 2014 11:14 AM, Sanchayan Maity wrote: Hello, I am currently implementing USB Host and client support for Freescale Vybrid platform in u-boot. I managed to get the host implementation working. For the host side, usb start calls usb_init(), which in turns call, usb_lowlevel_init(), from there into the ehic_hcd_init() of my implementation. So, setting up the necessary clocks and plls for USB in my implementation and then setting up the usb_ehci, ehci_hccr and echi_hcor structures was all. The flow and setup required i was able to trace. The USB client part is not clear to me. I was thinking i can use the ci_udc driver somehow to implement the client part. How can i use the ci_udc driver to implement client functionality?. From what i could see, the usb_gadget_driver_register() is suppose to be the first call. But, i couldn't trace from where this gets called or the flow and setup is suppose to be. OR Is a separate client driver required and nothing generic can be used akin to how it could be done for host? See include/configs/sansa_fuze_plus.h , you need the gadget driver for the function you want to implement , in this case it's ethernet for example (selected via CONFIG_USB_ETH_CDC ). An example of DFU/UMS can be found in include/configs/exynos4-common.h and to activate those, you need to use the 'dfu' or 'ums' commands. Thank you Marek. I had enabled usb ether options already and was trying to test USB client functionality with RNDIS. For some reason it was not working and i was not able to trace the issue and subsequently was not sure about the client part. Your inputs cleared my doubts. I tried UMS and DFU. UMS is working just fine and i can download the respective images through DFU. Though this DFU is not working full proof, but, i can figure that out now i feel. Thanks again for your inputs. Cheers! Best Regards, Sanchayan. Sorry if i am asking this question in the wrong place. I couldn't find anyone in the u-boot IRC channel nor find something similar to the kernel-newbies mailing list. There isn't any, so ask away ;-) Hope i am asking the right questions. [...] Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Query on the ci_udc driver for USB client implementation
Hello, Any pointers? Thanks Regards, Sanchayan Maity. On Thursday 30 October 2014 11:14 AM, Sanchayan Maity wrote: Hello, I am currently implementing USB Host and client support for Freescale Vybrid platform in u-boot. I managed to get the host implementation working. For the host side, usb start calls usb_init(), which in turns call, usb_lowlevel_init(), from there into the ehic_hcd_init() of my implementation. So, setting up the necessary clocks and plls for USB in my implementation and then setting up the usb_ehci, ehci_hccr and echi_hcor structures was all. The flow and setup required i was able to trace. The USB client part is not clear to me. I was thinking i can use the ci_udc driver somehow to implement the client part. How can i use the ci_udc driver to implement client functionality?. From what i could see, the usb_gadget_driver_register() is suppose to be the first call. But, i couldn't trace from where this gets called or the flow and setup is suppose to be. OR Is a separate client driver required and nothing generic can be used akin to how it could be done for host? Sorry if i am asking this question in the wrong place. I couldn't find anyone in the u-boot IRC channel nor find something similar to the kernel-newbies mailing list. Hope i am asking the right questions. Thanks Regards, Sanchayan Maity. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Query on the ci_udc driver for USB client implementation
Hello, I am currently implementing USB Host and client support for Freescale Vybrid platform in u-boot. I managed to get the host implementation working. For the host side, usb start calls usb_init(), which in turns call, usb_lowlevel_init(), from there into the ehic_hcd_init() of my implementation. So, setting up the necessary clocks and plls for USB in my implementation and then setting up the usb_ehci, ehci_hccr and echi_hcor structures was all. The flow and setup required i was able to trace. The USB client part is not clear to me. I was thinking i can use the ci_udc driver somehow to implement the client part. How can i use the ci_udc driver to implement client functionality?. From what i could see, the usb_gadget_driver_register() is suppose to be the first call. But, i couldn't trace from where this gets called or the flow and setup is suppose to be. OR Is a separate client driver required and nothing generic can be used akin to how it could be done for host? Sorry if i am asking this question in the wrong place. I couldn't find anyone in the u-boot IRC channel nor find something similar to the kernel-newbies mailing list. Hope i am asking the right questions. Thanks Regards, Sanchayan Maity. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
