[U-Boot] [RESEND PATCH v2] i.MX28: bug fixes in PMU configuration code
Signed-off-by: Stathis Voukelatos stathis.voukela...@linn.co.uk
Cc: Stefano Babic sba...@denx.de
Cc: Marek Vasut marek.va...@gmail.com
---
Changes for v2:
- White space cleanup
arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
index 4b09b0c..cc71af8 100644
--- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
@@ -716,7 +716,7 @@ int mx28_get_vddio_power_source_off(void)
tmp = readl(power_regs-hw_power_vddioctrl);
if (tmp POWER_VDDIOCTRL_DISABLE_FET) {
if ((tmp POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
- POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+ POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
return 1;
}
}
@@ -724,7 +724,7 @@ int mx28_get_vddio_power_source_off(void)
if (!(readl(power_regs-hw_power_5vctrl)
POWER_5VCTRL_ENABLE_DCDC)) {
if ((tmp POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
- POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+ POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
return 1;
}
}
@@ -772,7 +772,7 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t
new_brownout)
uint32_t cur_target, diff, bo_int = 0;
uint32_t powered_by_linreg = 0;
- new_brownout = new_target - new_brownout;
+ new_brownout = (new_target - new_brownout + 25) / 50;
cur_target = readl(power_regs-hw_power_vddioctrl);
cur_target = POWER_VDDIOCTRL_TRG_MASK;
@@ -858,8 +858,8 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t
new_brownout)
}
clrsetbits_le32(power_regs-hw_power_vddioctrl,
- POWER_VDDDCTRL_BO_OFFSET_MASK,
- new_brownout POWER_VDDDCTRL_BO_OFFSET_OFFSET);
+ POWER_VDDIOCTRL_BO_OFFSET_MASK,
+ new_brownout POWER_VDDIOCTRL_BO_OFFSET_OFFSET);
}
void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
@@ -869,7 +869,7 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t
new_brownout)
uint32_t cur_target, diff, bo_int = 0;
uint32_t powered_by_linreg = 0;
- new_brownout = new_target - new_brownout;
+ new_brownout = (new_target - new_brownout + 12) / 25;
cur_target = readl(power_regs-hw_power_vdddctrl);
cur_target = POWER_VDDDCTRL_TRG_MASK;
--
1.7.2.5
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[U-Boot] [PATCH v2] i.MX28: bug fixes in PMU configuration code
Fixed some typos in the i.MX28 PMU code that sets up the VDDD and VDDIO power
rails. In addition the VDDD and VDDIO brownout offset values should be divided
by a step size before being programmed to the corresponding registers.
Signed-off-by: Stathis Voukelatos stathis.voukela...@linn.co.uk
Cc: Stefano Babic sba...@denx.de
Cc: Marek Vasut marek.va...@gmail.com
---
Changes for v2:
- White space cleanup
arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
index 4b09b0c..cc71af8 100644
--- arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
+++ arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
@@ -716,7 +716,7 @@ int mx28_get_vddio_power_source_off(void)
tmp = readl(power_regs-hw_power_vddioctrl);
if (tmp POWER_VDDIOCTRL_DISABLE_FET) {
if ((tmp POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
- POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+ POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
return 1;
}
}
@@ -724,7 +724,7 @@ int mx28_get_vddio_power_source_off(void)
if (!(readl(power_regs-hw_power_5vctrl)
POWER_5VCTRL_ENABLE_DCDC)) {
if ((tmp POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
- POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+ POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
return 1;
}
}
@@ -772,7 +772,7 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t
new_brownout)
uint32_t cur_target, diff, bo_int = 0;
uint32_t powered_by_linreg = 0;
- new_brownout = new_target - new_brownout;
+ new_brownout = (new_target - new_brownout + 25) / 50;
cur_target = readl(power_regs-hw_power_vddioctrl);
cur_target = POWER_VDDIOCTRL_TRG_MASK; @@ -858,8 +858,8 @@ void
mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
}
clrsetbits_le32(power_regs-hw_power_vddioctrl,
- POWER_VDDDCTRL_BO_OFFSET_MASK,
- new_brownout POWER_VDDDCTRL_BO_OFFSET_OFFSET);
+ POWER_VDDIOCTRL_BO_OFFSET_MASK,
+ new_brownout POWER_VDDIOCTRL_BO_OFFSET_OFFSET);
}
void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) @@ -869,7
+869,7 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
uint32_t cur_target, diff, bo_int = 0;
uint32_t powered_by_linreg = 0;
- new_brownout = new_target - new_brownout;
+ new_brownout = (new_target - new_brownout + 12) / 25;
cur_target = readl(power_regs-hw_power_vdddctrl);
cur_target = POWER_VDDDCTRL_TRG_MASK;
--
1.7.2.5
Stathis Voukelatos
Senior Software Engineer
Linn Products Ltd.
Glasgow Road
Eaglesham, Glasgow
G76 0EQ, UK
Tel: +44 (0)141 3035191
Email: stathis.voukela...@linn.co.uk
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[U-Boot] [PATCH] i.MX28: bug fixes in PMU configuration code
Fixed some typos in the i.MX28 PMU code that sets up the VDDD
and VDDIO power rails. In addition the VDDD and VDDIO brownout
offset values should be divided by a step size before being
programmed to the corresponding registers.
Signed-off-by: Stathis Voukelatos stathis.voukela...@linn.co.uk
Cc: Stefano Babic sba...@denx.de
Cc: Marek Vasut marek.va...@gmail.com
---
arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
index 4b09b0c..cc71af8 100644
--- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
@@ -716,7 +716,7 @@ int mx28_get_vddio_power_source_off(void)
tmp = readl(power_regs-hw_power_vddioctrl);
if (tmp POWER_VDDIOCTRL_DISABLE_FET) {
if ((tmp POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
- POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+ POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
return 1;
}
}
@@ -724,7 +724,7 @@ int mx28_get_vddio_power_source_off(void)
if (!(readl(power_regs-hw_power_5vctrl)
POWER_5VCTRL_ENABLE_DCDC)) {
if ((tmp POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
- POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+ POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
return 1;
}
}
@@ -772,7 +772,7 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t
new_brownout)
uint32_t cur_target, diff, bo_int = 0;
uint32_t powered_by_linreg = 0;
- new_brownout = new_target - new_brownout;
+ new_brownout = (new_target - new_brownout + 25) / 50;
cur_target = readl(power_regs-hw_power_vddioctrl);
cur_target = POWER_VDDIOCTRL_TRG_MASK;
@@ -858,8 +858,8 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t
new_brownout)
}
clrsetbits_le32(power_regs-hw_power_vddioctrl,
- POWER_VDDDCTRL_BO_OFFSET_MASK,
- new_brownout POWER_VDDDCTRL_BO_OFFSET_OFFSET);
+ POWER_VDDIOCTRL_BO_OFFSET_MASK,
+ new_brownout POWER_VDDIOCTRL_BO_OFFSET_OFFSET);
}
void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
@@ -869,7 +869,7 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t
new_brownout)
uint32_t cur_target, diff, bo_int = 0;
uint32_t powered_by_linreg = 0;
- new_brownout = new_target - new_brownout;
+ new_brownout = (new_target - new_brownout + 12) / 25;
cur_target = readl(power_regs-hw_power_vdddctrl);
cur_target = POWER_VDDDCTRL_TRG_MASK;
--
1.7.2.5
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[U-Boot] [PATCH] Sheevaplug: Add Kirkwood watchdog support
Signed-off-by: Stathis Voukelatos stathis.voukela...@linn.co.uk
Cc: Prafulla Wadaskar prafu...@marvell.com
---
arch/arm/cpu/arm926ejs/kirkwood/timer.c | 47
+++--
arch/arm/include/asm/arch-kirkwood/cpu.h |1 +
board/Marvell/sheevaplug/sheevaplug.c| 23 ++-
include/configs/sheevaplug.h |3 ++
4 files changed, 69 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/timer.c
b/arch/arm/cpu/arm926ejs/kirkwood/timer.c
index f5d0160..79994e7 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/timer.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/timer.c
@@ -23,9 +23,11 @@
#include common.h
#include asm/io.h
+#include asm/arch/cpu.h
#include asm/arch/kirkwood.h
-#define UBOOT_CNTR 0 /* counter to use for uboot timer */
+#define UBOOT_CNTR 0 /* counter to use for uboot timer */
+#define WDT_CNTR 2 /* watchdog timer */
/* Timer reload and current value registers */
struct kwtmr_val {
@@ -37,9 +39,7 @@ struct kwtmr_val {
struct kwtmr_registers {
u32 ctrl; /* Timer control reg */
u32 pad[3];
- struct kwtmr_val tmr[2];
- u32 wdt_reload;
- u32 wdt_val;
+ struct kwtmr_val tmr[3];
};
struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers
*)KW_TIMER_BASE;
@@ -89,6 +89,45 @@ DECLARE_GLOBAL_DATA_PTR;
#define timestamp gd-tbl
#define lastdec gd-lastinc
+
+#ifdef CONFIG_WATCHDOG
+
+#define WDT_TIMEOUT 20
+
+void watchdog_reset(void)
+{
+ writel(WDT_TIMEOUT * CONFIG_SYS_TCLK, CNTMR_VAL_REG(WDT_CNTR));
+}
+
+
+void kw_watchdog_enable(void)
+{
+ struct kwcpu_registers *cpureg =
+ (struct kwcpu_registers
*)KW_CPU_REG_BASE;
+ unsigned int reg;
+
+ /* Set WDT timeout */
+ watchdog_reset();
+
+ /* Clear WDT IRQ */
+ reg = readl(cpureg-ahb_mbus_cause_irq);
+ reg = ~(1 3);
+ writel(reg, cpureg-ahb_mbus_cause_irq);
+
+ /* Enable watchdog timer */
+ reg = readl(CNTMR_CTRL_REG);
+ reg |= CTCR_ARM_TIMER_EN(WDT_CNTR);
+ writel(reg, CNTMR_CTRL_REG);
+
+ /* Enable reset on watchdog */
+ reg = readl(cpureg-rstoutn_mask);
+ reg |= 1 1;
+ writel(reg, cpureg-rstoutn_mask);
+}
+
+#endif
+
+
ulong get_timer_masked(void)
{
ulong now = READ_TIMER;
diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h
b/arch/arm/include/asm/arch-kirkwood/cpu.h
index d28c51a..3397126 100644
--- a/arch/arm/include/asm/arch-kirkwood/cpu.h
+++ b/arch/arm/include/asm/arch-kirkwood/cpu.h
@@ -167,5 +167,6 @@ int kw_config_mpp(unsigned int mpp0_7, unsigned int
mpp8_15,
unsigned int mpp32_39, unsigned int mpp40_47,
unsigned int mpp48_55);
unsigned int kw_winctrl_calcsize(unsigned int sizeval);
+void kw_watchdog_enable(void);
#endif /* __ASSEMBLY__ */
#endif /* _KWCPU_H */
diff --git a/board/Marvell/sheevaplug/sheevaplug.c
b/board/Marvell/sheevaplug/sheevaplug.c
index 71e6793..cea1661 100644
--- a/board/Marvell/sheevaplug/sheevaplug.c
+++ b/board/Marvell/sheevaplug/sheevaplug.c
@@ -107,12 +107,33 @@ int board_init(void)
*/
gd-bd-bi_arch_number = MACH_TYPE_SHEEVAPLUG;
- /* adress of boot parameters */
+ /* address of boot parameters */
gd-bd-bi_boot_params = kw_sdram_bar(0) + 0x100;
return 0;
}
+#ifdef CONFIG_BOARD_LATE_INIT
+
+int board_late_init(void)
+{
+#ifdef CONFIG_WATCHDOG
+ {
+ char *s = getenv(watchdog);
+ if (s != NULL) {
+ if (strcmp(s, on) == 0) {
+ kw_watchdog_enable();
+ printf(Kirkwood watchdog enabled\n);
+ }
+ }
+ }
+#endif
+ return 0;
+}
+
+#endif
+
+
#ifdef CONFIG_RESET_PHY_R
/* Configure and enable MV88E1116 PHY */
void reset_phy(void)
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index 83dd8ff..c2bc864 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -56,6 +56,9 @@
*/
#include mv-common.h
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_WATCHDOG
+
/*
* Environment variables configurations
*/
--
1.7.2.5
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