RE: [PATCH 3/4] Revert "lpc32xx: cpu: add support for soft reset"
Hi Harald,
Yes, we have board code that will call this function with a different value to
generate a soft reset (i.e. no pulse on "RESOUT_N"). We have a need to be able
to reset the processor (soft or hard) based on the need to generate or not a
pulse on RESOUT_N signal.
We will be able to keep this patch local until somebody in the team look at a
sysreset driver implementation.
Regards,
Sylvain Lemieux
-Original Message-
From: Harald Seiler
Sent: Thursday, December 17, 2020 5:09 AM
To: Sylvain Lemieux ; u-boot@lists.denx.de
Cc: Tom Rini ; Simon Glass
Subject: Re: [PATCH 3/4] Revert "lpc32xx: cpu: add support for soft reset"
Hello Sylvain,
On Tue, 2020-12-15 at 17:29 +0000, Sylvain Lemieux wrote:
> Hi,
>
> This functionality (soft vs hard reset) is used in multiple LPC32xx
> products with our custom hardware.
>
> If this support is remove from upstream, we will have to maintain this
> patch locally (out of tree).
My intention with this series is of course not to break existing and useful
functionality. Can you elaborate how you are making use of this
differentiation in its current form? Does some board code call
reset_cpu() directly, with different parameter values?
I would argue that at this time, the proper way to support both soft-reset and
hard-reset is via a sysreset driver, see `drivers/sysreset/sysreset_psci.c` for
a simple example. As I laid out in the cover letter of this series, the `addr`
parameter to reset_cpu() does not really fit this purpose.
Regards,
--
Harald
> Sylvain Lemieux
>
> -Original Message-
> From: Harald Seiler
> Sent: Tuesday, December 15, 2020 10:48 AM
> To: u-boot@lists.denx.de
> Cc: Harald Seiler ; Tom Rini ; Simon
> Glass ; Sylvain Lemieux
> Subject: [PATCH 3/4] Revert "lpc32xx: cpu: add support for soft reset"
>
> This reverts commit 576007aec9a4a5f4f3dd1f690fb26a8c05ceb75f.
>
> The paramter passed to reset_cpu() no longer holds a meaning as all
> call-sites now pass the value 0. Thus, branching on it is essentially
> dead code and will just confuse future readers.
>
> Revert soft-reset support and just always perform a hard-reset for now.
> This is a preparation for removal of the reset_cpu() parameter across
> the entire tree in a later patch.
>
> Fixes: 576007aec9a4 ("lpc32xx: cpu: add support for soft reset")
> Cc: Sylvain Lemieux
> Signed-off-by: Harald Seiler
> ---
> arch/arm/mach-lpc32xx/cpu.c | 21 +
> 1 file changed, 5 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm/mach-lpc32xx/cpu.c b/arch/arm/mach-lpc32xx/cpu.c
> index 32af6206056b..7378192a33c2 100644
> --- a/arch/arm/mach-lpc32xx/cpu.c
> +++ b/arch/arm/mach-lpc32xx/cpu.c
> @@ -22,23 +22,12 @@ void reset_cpu(ulong addr)
> /* Enable watchdog clock */
> setbits_le32(>timclk_ctrl, CLK_TIMCLK_WATCHDOG);
>
> - /* To be compatible with the original U-Boot code:
> - * addr: - 0: perform hard reset.
> - * - !=0: perform a soft reset; i.e. "RESOUT_N" not
> asserted). */
> - if (addr == 0) {
> - /* Reset pulse length is 13005 peripheral clock frames
> */
> - writel(13000, >pulse);
> + /* Reset pulse length is 13005 peripheral clock frames */
> + writel(13000, >pulse);
>
> - /* Force WDOG_RESET2 and RESOUT_N signal active */
> - writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1
> - | WDTIM_MCTRL_M_RES2, >mctrl);
> - } else {
> - /* Force match output active */
> - writel(0x01, >emr);
> -
> - /* Internal reset on match output (no pulse on
> "RESOUT_N") */
> - writel(WDTIM_MCTRL_M_RES1, >mctrl);
> - }
> + /* Force WDOG_RESET2 and RESOUT_N signal active */
> + writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 |
> +WDTIM_MCTRL_M_RES2,
> + >mctrl);
>
> while (1)
> /* NOP */;
> --
> 2.26.2
>
--
Harald
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB
165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-62 Fax: +49-8142-66989-80 Email: h...@denx.de
RE: [PATCH 3/4] Revert "lpc32xx: cpu: add support for soft reset"
Hi,
This functionality (soft vs hard reset) is used in multiple LPC32xx products
with our custom hardware.
If this support is remove from upstream, we will have to maintain this patch
locally (out of tree).
Sylvain Lemieux
-Original Message-
From: Harald Seiler
Sent: Tuesday, December 15, 2020 10:48 AM
To: u-boot@lists.denx.de
Cc: Harald Seiler ; Tom Rini ; Simon Glass
; Sylvain Lemieux
Subject: [PATCH 3/4] Revert "lpc32xx: cpu: add support for soft reset"
This reverts commit 576007aec9a4a5f4f3dd1f690fb26a8c05ceb75f.
The paramter passed to reset_cpu() no longer holds a meaning as all call-sites
now pass the value 0. Thus, branching on it is essentially dead code and will
just confuse future readers.
Revert soft-reset support and just always perform a hard-reset for now.
This is a preparation for removal of the reset_cpu() parameter across the
entire tree in a later patch.
Fixes: 576007aec9a4 ("lpc32xx: cpu: add support for soft reset")
Cc: Sylvain Lemieux
Signed-off-by: Harald Seiler
---
arch/arm/mach-lpc32xx/cpu.c | 21 +
1 file changed, 5 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-lpc32xx/cpu.c b/arch/arm/mach-lpc32xx/cpu.c index
32af6206056b..7378192a33c2 100644
--- a/arch/arm/mach-lpc32xx/cpu.c
+++ b/arch/arm/mach-lpc32xx/cpu.c
@@ -22,23 +22,12 @@ void reset_cpu(ulong addr)
/* Enable watchdog clock */
setbits_le32(>timclk_ctrl, CLK_TIMCLK_WATCHDOG);
- /* To be compatible with the original U-Boot code:
-* addr: - 0: perform hard reset.
-* - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */
- if (addr == 0) {
- /* Reset pulse length is 13005 peripheral clock frames */
- writel(13000, >pulse);
+ /* Reset pulse length is 13005 peripheral clock frames */
+ writel(13000, >pulse);
- /* Force WDOG_RESET2 and RESOUT_N signal active */
- writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1
- | WDTIM_MCTRL_M_RES2, >mctrl);
- } else {
- /* Force match output active */
- writel(0x01, >emr);
-
- /* Internal reset on match output (no pulse on "RESOUT_N") */
- writel(WDTIM_MCTRL_M_RES1, >mctrl);
- }
+ /* Force WDOG_RESET2 and RESOUT_N signal active */
+ writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,
+ >mctrl);
while (1)
/* NOP */;
--
2.26.2
Re: [U-Boot] [PATCH 8/8] spi: Kconfig: Mark LPC32XX_SSP has BROKEN
Acked-by: Sylvain Lemieux On Tue, Apr 30, 2019 at 4:48 PM Vladimir Zapolskiy wrote: > > Hi Jagan, > > On 04/28/2019 11:48 PM, Jagan Teki wrote: > > Mark LPC32XX_SSP has BROKEN, this so the resulting build shows > > warning for broken configuration enabled and associated code > > will remove in v2019.07 release. > > > > Cc: Vladimir Zapolskiy > > Cc: Albert ARIBAUD > > Signed-off-by: Jagan Teki > > --- > > drivers/spi/Kconfig | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > > index 55f0d6cf2b..5fbe17bb20 100644 > > --- a/drivers/spi/Kconfig > > +++ b/drivers/spi/Kconfig > > @@ -369,6 +369,7 @@ config KIRKWOOD_SPI > > > > config LPC32XX_SSP > > bool "LPC32XX SPI Driver" > > + select BROKEN > > help > > Enable support for SPI on LPC32xx > > > > > > Acked-by: Vladimir Zapolskiy > > Thank you for the change, as we've discussed earlier I won't have > objections against the driver removal when time is up. > > Thus you can locally prepare a removal change in advance, the one > which you've sent earlier needs a minor update, please also remove > lpc32xx_ssp_init() function and its usage in the board files. > > -- > Best wishes, > Vladimir ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4] usb: lpc32xx: add i2c DM support
From: Liam Beguin <lbeg...@tycoint.com>
Add DM support for i2c functions.
Signed-off-by: Liam Beguin <lbeg...@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemi...@tycoint.com>
Reviewed-by: Marek Vasut <ma...@denx.de>
---
Changes from v3 to v4:
* Moved "dm.h" to the proper location in include list.
* Added Reviewed-by from Marek (taken from v3)
Changes from v2 to v3:
* Code clean-up to remove conditional compile else section (CONFIG_DM_I2C).
* As suggested by Marek, added Simon Glass to the list of cc for the patch.
Changes from v1 to v2:
* Do not request udevice on each single i2c write.
Note:
* This patch is require as part of the DM support of the LPC32xx I2C driver.
All I2C drivers should be converted, to DM, by the end of June 2017.
* The USB driver is supporting the DM and non-DM API.
* Once the ustream LPC32xx boards (devkit3250 & work_92105) are migrated
to DM (I2C), the non-DM API support can be remove from this driver.
drivers/usb/host/ohci-lpc32xx.c | 64 +
1 file changed, 46 insertions(+), 18 deletions(-)
diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c
index 9245126ed6..2f2b4b90de 100644
--- a/drivers/usb/host/ohci-lpc32xx.c
+++ b/drivers/usb/host/ohci-lpc32xx.c
@@ -9,11 +9,13 @@
*/
#include
+#include
#include
#include
#include
#include
#include
+#include
#include
#include
@@ -81,14 +83,20 @@ struct otg_regs {
static struct otg_regs *otg = (struct otg_regs *)USB_BASE;
static struct clk_pm_regs *clk_pwr = (struct clk_pm_regs *)CLK_PM_BASE;
-static int isp1301_set_value(int reg, u8 value)
+static int isp1301_set_value(struct udevice *dev, int reg, u8 value)
{
+#ifndef CONFIG_DM_I2C
return i2c_write(ISP1301_I2C_ADDR, reg, 1, , 1);
+#else
+ return dm_i2c_write(dev, reg, , 1);
+#endif
}
-static void isp1301_configure(void)
+static void isp1301_configure(struct udevice *dev)
{
+#ifndef CONFIG_DM_I2C
i2c_set_bus_num(I2C_2);
+#endif
/*
* LPC32XX only supports DAT_SE0 USB mode
@@ -96,23 +104,23 @@ static void isp1301_configure(void)
*/
/* Disable transparent UART mode first */
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_CLR, ~MC1_SPEED_REG);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_SET, MC1_SPEED_REG);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_2_CLR, ~0);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_2_SET,
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, ~MC1_SPEED_REG);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_SPEED_REG);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_SET,
MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL);
- isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_CLR, ~0);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0);
- isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET,
+ isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0);
+ isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET,
OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
- isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_CLR,
+ isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR,
OTG1_DM_PULLUP | OTG1_DP_PULLUP);
- isp1301_set_value(ISP1301_I2C_INTERRUPT_LATCH_CLR, ~0);
- isp1301_set_value(ISP1301_I2C_INTERRUPT_FALLING_CLR, ~0);
- isp1301_set_value(ISP1301_I2C_INTERRUPT_RISING_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_LATCH_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_FALLING_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_RISING_CLR, ~0);
/* Enable usb_need_clk clock after transceiver is initialized */
setbits_le32(_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN);
@@ -149,6 +157,15 @@ static int usbpll_setup(void)
int usb_cpu_init(void)
{
u32 ret;
+ struct udevice *dev = NULL;
+
+#ifdef CONFIG_DM_I2C
+ ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, 1, );
+ if (ret) {
+ debug("%s: No bus %d\n", __func__, I2C_2);
+ return ret;
+ }
+#endif
/*
* USB pins routing setup is done by "lpc32xx_usb_init()" and should
@@ -167,7 +184,7 @@ int usb_cpu_init(void)
return ret;
/* Configure ISP1301 */
- isp1301_configure();
+ isp1301_configure(dev);
/* setup USB clocks and PLL */
ret = usbpll_setup();
@@ -188,21 +205,32 @@ int usb_cpu_init(void)
return ret;
setbit
Re: [U-Boot] [PATCH v3] usb: lpc32xx: add i2c DM support
Hi,
On Fri, 2017-04-28 at 18:28 -0600, Simon Glass wrote:
> Hi,
>
> On 26 April 2017 at 05:57, Sylvain Lemieux <slemieux.t...@gmail.com> wrote:
> > From: Liam Beguin <lbeg...@tycoint.com>
> >
> > Add DM support for i2c functions.
> >
> > Signed-off-by: Liam Beguin <lbeg...@tycoint.com>
> > Signed-off-by: Sylvain Lemieux <slemi...@tycoint.com>
> > ---
> > Changes from v2 to v3:
> > * Code clean-up to remove conditional compile else section (CONFIG_DM_I2C).
> > * As suggested by Marek, added Simon Glass to the list of cc for the patch.
> >
> > Changes from v1 to v2:
> > * Do not request udevice on each single i2c write.
> >
> > Note:
> > * This patch is require as part of the DM support of the LPC32xx I2C driver.
> > All I2C drivers should be converted, to DM, by the end of June 2017.
> >
> > * The USB driver is supporting the DM and non-DM API.
> >
> > * Once the ustream LPC32xx boards (devkit3250 & work_92105) are migrated
> > to DM (I2C), the non-DM API support can be remove from this driver.
> >
> > drivers/usb/host/ohci-lpc32xx.c | 64
> > +
> > 1 file changed, 46 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/usb/host/ohci-lpc32xx.c
> > b/drivers/usb/host/ohci-lpc32xx.c
> > index 9245126ed6..c0c423b994 100644
> > --- a/drivers/usb/host/ohci-lpc32xx.c
> > +++ b/drivers/usb/host/ohci-lpc32xx.c
> > @@ -14,8 +14,10 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> > +#include
>
> Please check header file order.
>
> http://www.denx.de/wiki/U-Boot/CodingStyle
>
I will submit a revision 4.
> >
> > /* OTG I2C controller module register structures */
> > struct otgi2c_regs {
> > @@ -81,14 +83,20 @@ struct otg_regs {
> > static struct otg_regs *otg = (struct otg_regs *)USB_BASE;
> > static struct clk_pm_regs *clk_pwr = (struct clk_pm_regs *)CLK_PM_BASE;
> >
> > -static int isp1301_set_value(int reg, u8 value)
> > +static int isp1301_set_value(struct udevice *dev, int reg, u8 value)
> > {
> > +#ifndef CONFIG_DM_I2C
> > return i2c_write(ISP1301_I2C_ADDR, reg, 1, , 1);
> > +#else
> > + return dm_i2c_write(dev, reg, , 1);
> > +#endif
> > }
> >
> > -static void isp1301_configure(void)
> > +static void isp1301_configure(struct udevice *dev)
> > {
> > +#ifndef CONFIG_DM_I2C
> > i2c_set_bus_num(I2C_2);
> > +#endif
> >
> > /*
> > * LPC32XX only supports DAT_SE0 USB mode
> > @@ -96,23 +104,23 @@ static void isp1301_configure(void)
> > */
> >
> > /* Disable transparent UART mode first */
> > - isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN);
> > + isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN);
> >
> > - isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_CLR, ~MC1_SPEED_REG);
> > - isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_SET, MC1_SPEED_REG);
> > - isp1301_set_value(ISP1301_I2C_MODE_CONTROL_2_CLR, ~0);
> > - isp1301_set_value(ISP1301_I2C_MODE_CONTROL_2_SET,
> > + isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR,
> > ~MC1_SPEED_REG);
> > + isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET,
> > MC1_SPEED_REG);
> > + isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_CLR, ~0);
> > + isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_SET,
> > MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL);
> >
> > - isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_CLR, ~0);
> > - isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0);
> > - isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET,
> > + isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR, ~0);
> > + isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0);
> > + isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET,
> > OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
> > - isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_CLR,
> > + isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR,
> > OTG1_DM_PULLUP | OTG1_DP_PULLUP);
> > - isp1301_set_value(ISP1301_I2C_INTERRUPT_LATCH_CLR, ~0);
> > - isp1301_set_value(ISP1301_I2C_INTERRUPT_FALLING_CLR, ~0);
> > - isp1301_set_value(ISP1301_I2C_INTERRUPT_RISING_CLR, ~0);
> > + isp1301_set_v
[U-Boot] [PATCH v3] usb: lpc32xx: add i2c DM support
From: Liam Beguin <lbeg...@tycoint.com>
Add DM support for i2c functions.
Signed-off-by: Liam Beguin <lbeg...@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemi...@tycoint.com>
---
Changes from v2 to v3:
* Code clean-up to remove conditional compile else section (CONFIG_DM_I2C).
* As suggested by Marek, added Simon Glass to the list of cc for the patch.
Changes from v1 to v2:
* Do not request udevice on each single i2c write.
Note:
* This patch is require as part of the DM support of the LPC32xx I2C driver.
All I2C drivers should be converted, to DM, by the end of June 2017.
* The USB driver is supporting the DM and non-DM API.
* Once the ustream LPC32xx boards (devkit3250 & work_92105) are migrated
to DM (I2C), the non-DM API support can be remove from this driver.
drivers/usb/host/ohci-lpc32xx.c | 64 +
1 file changed, 46 insertions(+), 18 deletions(-)
diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c
index 9245126ed6..c0c423b994 100644
--- a/drivers/usb/host/ohci-lpc32xx.c
+++ b/drivers/usb/host/ohci-lpc32xx.c
@@ -14,8 +14,10 @@
#include
#include
#include
+#include
#include
#include
+#include
/* OTG I2C controller module register structures */
struct otgi2c_regs {
@@ -81,14 +83,20 @@ struct otg_regs {
static struct otg_regs *otg = (struct otg_regs *)USB_BASE;
static struct clk_pm_regs *clk_pwr = (struct clk_pm_regs *)CLK_PM_BASE;
-static int isp1301_set_value(int reg, u8 value)
+static int isp1301_set_value(struct udevice *dev, int reg, u8 value)
{
+#ifndef CONFIG_DM_I2C
return i2c_write(ISP1301_I2C_ADDR, reg, 1, , 1);
+#else
+ return dm_i2c_write(dev, reg, , 1);
+#endif
}
-static void isp1301_configure(void)
+static void isp1301_configure(struct udevice *dev)
{
+#ifndef CONFIG_DM_I2C
i2c_set_bus_num(I2C_2);
+#endif
/*
* LPC32XX only supports DAT_SE0 USB mode
@@ -96,23 +104,23 @@ static void isp1301_configure(void)
*/
/* Disable transparent UART mode first */
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_CLR, ~MC1_SPEED_REG);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_SET, MC1_SPEED_REG);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_2_CLR, ~0);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_2_SET,
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, ~MC1_SPEED_REG);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_SPEED_REG);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_SET,
MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL);
- isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_CLR, ~0);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0);
- isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET,
+ isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0);
+ isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET,
OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
- isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_CLR,
+ isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR,
OTG1_DM_PULLUP | OTG1_DP_PULLUP);
- isp1301_set_value(ISP1301_I2C_INTERRUPT_LATCH_CLR, ~0);
- isp1301_set_value(ISP1301_I2C_INTERRUPT_FALLING_CLR, ~0);
- isp1301_set_value(ISP1301_I2C_INTERRUPT_RISING_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_LATCH_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_FALLING_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_RISING_CLR, ~0);
/* Enable usb_need_clk clock after transceiver is initialized */
setbits_le32(_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN);
@@ -149,6 +157,15 @@ static int usbpll_setup(void)
int usb_cpu_init(void)
{
u32 ret;
+ struct udevice *dev = NULL;
+
+#ifdef CONFIG_DM_I2C
+ ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, 1, );
+ if (ret) {
+ debug("%s: No bus %d\n", __func__, I2C_2);
+ return ret;
+ }
+#endif
/*
* USB pins routing setup is done by "lpc32xx_usb_init()" and should
@@ -167,7 +184,7 @@ int usb_cpu_init(void)
return ret;
/* Configure ISP1301 */
- isp1301_configure();
+ isp1301_configure(dev);
/* setup USB clocks and PLL */
ret = usbpll_setup();
@@ -188,21 +205,32 @@ int usb_cpu_init(void)
return ret;
setbits_le32(>otg_sts_ctrl, OTG_HOST_EN);
- isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV);
+ isp1301_set_value(dev, ISP1301_I2C_OTG_C
[U-Boot] [PATCH v2] usb: lpc32xx: add i2c DM support
From: Liam Beguin <lbeg...@tycoint.com>
Add DM support for i2c functions.
Signed-off-by: Liam Beguin <lbeg...@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemi...@tycoint.com>
---
Changes from v1 to v2:
* Do not request udevice on each single i2c write.
Note:
* This patch is require as part of the DM support of the LPC32xx I2C driver.
All I2C drivers should be converted, to DM, by the end of June 2017.
* The USB driver is supporting the DM and non-DM API.
* Once the ustream LPC32xx boards (devkit3250 & work_92105) are migrated
to DM (I2C), the non-DM API support can be remove from this driver.
drivers/usb/host/ohci-lpc32xx.c | 68 ++---
1 file changed, 51 insertions(+), 17 deletions(-)
diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c
index 9245126ed6..fe4826b23d 100644
--- a/drivers/usb/host/ohci-lpc32xx.c
+++ b/drivers/usb/host/ohci-lpc32xx.c
@@ -14,8 +14,10 @@
#include
#include
#include
+#include
#include
#include
+#include
/* OTG I2C controller module register structures */
struct otgi2c_regs {
@@ -81,14 +83,23 @@ struct otg_regs {
static struct otg_regs *otg = (struct otg_regs *)USB_BASE;
static struct clk_pm_regs *clk_pwr = (struct clk_pm_regs *)CLK_PM_BASE;
-static int isp1301_set_value(int reg, u8 value)
+#ifndef CONFIG_DM_I2C
+static int isp1301_set_value(void *dev, int reg, u8 value)
{
return i2c_write(ISP1301_I2C_ADDR, reg, 1, , 1);
}
+#else
+static int isp1301_set_value(struct udevice *dev, int reg, u8 value)
+{
+ return dm_i2c_write(dev, reg, , 1);
+}
+#endif
-static void isp1301_configure(void)
+static void isp1301_configure(struct udevice *dev)
{
+#ifndef CONFIG_DM_I2C
i2c_set_bus_num(I2C_2);
+#endif
/*
* LPC32XX only supports DAT_SE0 USB mode
@@ -96,23 +107,23 @@ static void isp1301_configure(void)
*/
/* Disable transparent UART mode first */
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_CLR, ~MC1_SPEED_REG);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_SET, MC1_SPEED_REG);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_2_CLR, ~0);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_2_SET,
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, ~MC1_SPEED_REG);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_SPEED_REG);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_SET,
MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL);
- isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_CLR, ~0);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0);
- isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET,
+ isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0);
+ isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET,
OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
- isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_CLR,
+ isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR,
OTG1_DM_PULLUP | OTG1_DP_PULLUP);
- isp1301_set_value(ISP1301_I2C_INTERRUPT_LATCH_CLR, ~0);
- isp1301_set_value(ISP1301_I2C_INTERRUPT_FALLING_CLR, ~0);
- isp1301_set_value(ISP1301_I2C_INTERRUPT_RISING_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_LATCH_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_FALLING_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_RISING_CLR, ~0);
/* Enable usb_need_clk clock after transceiver is initialized */
setbits_le32(_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN);
@@ -149,6 +160,17 @@ static int usbpll_setup(void)
int usb_cpu_init(void)
{
u32 ret;
+#ifndef CONFIG_DM_I2C
+ void *dev = NULL;
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, 1, );
+ if (ret) {
+ debug("%s: No bus %d\n", __func__, I2C_2);
+ return ret;
+ }
+#endif
/*
* USB pins routing setup is done by "lpc32xx_usb_init()" and should
@@ -167,7 +189,7 @@ int usb_cpu_init(void)
return ret;
/* Configure ISP1301 */
- isp1301_configure();
+ isp1301_configure(dev);
/* setup USB clocks and PLL */
ret = usbpll_setup();
@@ -188,15 +210,27 @@ int usb_cpu_init(void)
return ret;
setbits_le32(>otg_sts_ctrl, OTG_HOST_EN);
- isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV);
+ isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV);
return 0;
}
int usb_cpu_stop(void)
{
Re: [U-Boot] [PATCH] usb: lpc32xx: Add i2c DM support
On Fri, 2017-04-14 at 16:01 +0200, Marek Vasut wrote:
> On 03/14/2017 04:28 PM, Sylvain Lemieux wrote:
> > From: Liam Beguin <lbeg...@tycoint.com>
> >
> > Add DM support for i2c functions.
> >
> > Signed-off-by: Liam Beguin <lbeg...@tycoint.com>
> > Signed-off-by: Sylvain Lemieux <slemi...@tycoint.com>
> > ---
> > Note:
> > * This patch is require as part of the DM support of the LPC32xx I2C driver.
> > All I2C drivers should be converted, to DM, by the end of June 2017.
> >
> > * The USB driver is supporting the DM and non-DM API.
> >
> > * This patch depend on the following patchset:
> > https://lists.denx.de/pipermail/u-boot/2017-March/283672.html
> >
> > drivers/usb/host/ohci-lpc32xx.c | 33 +++--
> > 1 file changed, 31 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/usb/host/ohci-lpc32xx.c
> > b/drivers/usb/host/ohci-lpc32xx.c
> > index 9245126ed6..51be4c90c7 100644
> > --- a/drivers/usb/host/ohci-lpc32xx.c
> > +++ b/drivers/usb/host/ohci-lpc32xx.c
> > @@ -14,8 +14,10 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> > +#include
> >
> > /* OTG I2C controller module register structures */
> > struct otgi2c_regs {
> > @@ -83,12 +85,35 @@ static struct clk_pm_regs *clk_pwr = (struct
> > clk_pm_regs *)CLK_PM_BASE;
> >
> > static int isp1301_set_value(int reg, u8 value)
> > {
> > +#ifndef CONFIG_DM_I2C
> > return i2c_write(ISP1301_I2C_ADDR, reg, 1, , 1);
> > +#else
> > + struct udevice *dev;
> > + int ret;
> > +
> > + ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR,
> > + 1, );
>
> I'd rather see you passing udevice around than requesting it on each
> single i2c write.
>
Will do the change and submit a version 2.
> > + if (ret)
> > + return ret;
> > +
> > + return dm_i2c_write(dev, reg, , 1);
> > +#endif
> > }
> >
> > -static void isp1301_configure(void)
> > +static int isp1301_configure(void)
> > {
> > +#ifndef CONFIG_DM_I2C
> > i2c_set_bus_num(I2C_2);
> > +#else
> > + int ret;
> > + struct udevice *bus;
> > +
> > + ret = uclass_get_device_by_seq(UCLASS_I2C, I2C_2, );
> > + if (ret) {
> > + debug("%s: No bus %d\n", __func__, I2C_2);
> > + return ret;
> > + }
> > +#endif
> >
> > /*
> > * LPC32XX only supports DAT_SE0 USB mode
> > @@ -116,6 +141,8 @@ static void isp1301_configure(void)
> >
> > /* Enable usb_need_clk clock after transceiver is initialized */
> > setbits_le32(_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN);
> > +
> > + return 0;
> > }
> >
> > static int usbpll_setup(void)
> > @@ -167,7 +194,9 @@ int usb_cpu_init(void)
> > return ret;
> >
> > /* Configure ISP1301 */
> > - isp1301_configure();
> > + ret = isp1301_configure();
> > + if (ret)
> > + return ret;
>
> Don't we need some sort of failpath now, to undo the changes ?
>
With the rework of the patch, this change is no longer needed.
> > /* setup USB clocks and PLL */
> > ret = usbpll_setup();
> >
>
>
Sylvain
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[U-Boot] [PATCH v2 4/7] i2c: lpc32xx: Add DM for lpc32xx I2C
From: Liam Beguin <lbeg...@tycoint.com>
Adding DM specific wrapper functions and definitions.
Signed-off-by: Liam Beguin <lbeg...@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemi...@tycoint.com>
---
Changes from v1 to v2:
* Fixed checkpatch issue.
drivers/i2c/lpc32xx_i2c.c | 91 +++
1 file changed, 91 insertions(+)
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
index 62d2d7eee5..17e8b744e5 100644
--- a/drivers/i2c/lpc32xx_i2c.c
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -15,6 +15,8 @@
#include
#include
#include
+#include
+#include
/*
* Provide default speed and slave if target did not
@@ -47,6 +49,14 @@ struct lpc32xx_i2c_base {
u32 stxfl;
};
+#ifdef CONFIG_DM_I2C
+struct lpc32xx_i2c_dev {
+ struct lpc32xx_i2c_base *base;
+ int index;
+ uint speed;
+};
+#endif /* CONFIG_DM_I2C */
+
/* TX register fields */
#define LPC32XX_I2C_TX_START 0x0100
#define LPC32XX_I2C_TX_STOP0x0200
@@ -61,11 +71,13 @@ struct lpc32xx_i2c_base {
#define LPC32XX_I2C_STAT_NAI 0x0004
#define LPC32XX_I2C_STAT_TDI 0x0001
+#ifndef CONFIG_DM_I2C
static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
(struct lpc32xx_i2c_base *)I2C1_BASE,
(struct lpc32xx_i2c_base *)I2C2_BASE,
(struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
};
+#endif
/* Set I2C bus speed */
static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
@@ -241,6 +253,7 @@ static int __i2c_write(struct lpc32xx_i2c_base *base, u8
dev, uint addr,
return 0;
}
+#ifndef CONFIG_DM_I2C
static void lpc32xx_i2c_init(struct i2c_adapter *adap,
int requested_speed, int slaveadd)
{
@@ -294,3 +307,80 @@ U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
10,
0,
2)
+#else /* CONFIG_DM_I2C */
+static int lpc32xx_i2c_probe(struct udevice *bus)
+{
+ struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+
+ __i2c_init(dev->base, dev->speed, 0, dev->index);
+ return 0;
+}
+
+static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
+ u32 chip_flags)
+{
+ struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+ return __i2c_probe_chip(dev->base, chip_addr);
+}
+
+static int lpc32xx_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
+ int nmsgs)
+{
+ struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+ struct i2c_msg *dmsg, *omsg, dummy;
+ uint i = 0, address = 0;
+
+ memset(, 0, sizeof(struct i2c_msg));
+
+ /* We expect either two messages (one with an offset and one with the
+* actual data) or one message (just data)
+*/
+ if (nmsgs > 2 || nmsgs == 0) {
+ debug("%s: Only one or two messages are supported.", __func__);
+ return -1;
+ }
+
+ omsg = nmsgs == 1 ? : msg;
+ dmsg = nmsgs == 1 ? msg : msg + 1;
+
+ /* the address is expected to be a uint, not a array. */
+ address = omsg->buf[0];
+ for (i = 1; i < omsg->len; i++)
+ address = (address << 8) + omsg->buf[i];
+
+ if (dmsg->flags & I2C_M_RD)
+ return __i2c_read(dev->base, dmsg->addr, address,
+ omsg->len, dmsg->buf, dmsg->len);
+ else
+ return __i2c_write(dev->base, dmsg->addr, address,
+ omsg->len, dmsg->buf, dmsg->len);
+}
+
+static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+ struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+ return __i2c_set_bus_speed(dev->base, speed, dev->index);
+}
+
+static int lpc32xx_i2c_reset(struct udevice *bus)
+{
+ struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+
+ __i2c_init(dev->base, dev->speed, 0, dev->index);
+ return 0;
+}
+
+static const struct dm_i2c_ops lpc32xx_i2c_ops = {
+ .xfer = lpc32xx_i2c_xfer,
+ .probe_chip= lpc32xx_i2c_probe_chip,
+ .deblock = lpc32xx_i2c_reset,
+ .set_bus_speed = lpc32xx_i2c_set_bus_speed,
+};
+
+U_BOOT_DRIVER(i2c_lpc32xx) = {
+ .id = UCLASS_I2C,
+ .name = "i2c_lpc32xx",
+ .probe= lpc32xx_i2c_probe,
+ .ops = _i2c_ops,
+};
+#endif /* CONFIG_DM_I2C */
--
2.11.0
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[U-Boot] [PATCH v2 3/7] i2c: lpc32xx: Factor out i2c_adapter parameter
From: Liam Beguin <lbeg...@tycoint.com>
This is part of the prep work for the migration to the driver model.
It will enable the driver to support DM and non-DM configurations
using the same functions.
Signed-off-by: Liam Beguin <lbeg...@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemi...@tycoint.com>
---
Changes from v1 to v2:
* Fixed checkpatch issue.
drivers/i2c/lpc32xx_i2c.c | 107 +++---
1 file changed, 53 insertions(+), 54 deletions(-)
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
index e5dfdfe1df..62d2d7eee5 100644
--- a/drivers/i2c/lpc32xx_i2c.c
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -29,7 +29,7 @@
#endif
/* i2c register set */
-struct lpc32xx_i2c_registers {
+struct lpc32xx_i2c_base {
union {
u32 rx;
u32 tx;
@@ -61,15 +61,15 @@ struct lpc32xx_i2c_registers {
#define LPC32XX_I2C_STAT_NAI 0x0004
#define LPC32XX_I2C_STAT_TDI 0x0001
-static struct lpc32xx_i2c_registers *lpc32xx_i2c[] = {
- (struct lpc32xx_i2c_registers *)I2C1_BASE,
- (struct lpc32xx_i2c_registers *)I2C2_BASE,
- (struct lpc32xx_i2c_registers *)(USB_BASE + 0x300)
+static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
+ (struct lpc32xx_i2c_base *)I2C1_BASE,
+ (struct lpc32xx_i2c_base *)I2C2_BASE,
+ (struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
};
/* Set I2C bus speed */
-static unsigned int __i2c_set_bus_speed(struct i2c_adapter *adap,
- unsigned int speed)
+static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
+ unsigned int speed, unsigned int chip)
{
int half_period;
@@ -77,7 +77,7 @@ static unsigned int __i2c_set_bus_speed(struct i2c_adapter
*adap,
return -EINVAL;
/* OTG I2C clock source and CLK registers are different */
- if (adap->hwadapnr == 2) {
+ if (chip == 2) {
half_period = (get_periph_clk_rate() / speed) / 2;
if (half_period > 0xFF)
return -EINVAL;
@@ -87,38 +87,35 @@ static unsigned int __i2c_set_bus_speed(struct i2c_adapter
*adap,
return -EINVAL;
}
- writel(half_period, _i2c[adap->hwadapnr]->clk_hi);
- writel(half_period, _i2c[adap->hwadapnr]->clk_lo);
+ writel(half_period, >clk_hi);
+ writel(half_period, >clk_lo);
return 0;
}
/* I2C init called by cmd_i2c when doing 'i2c reset'. */
-static void __i2c_init(struct i2c_adapter *adap,
- int requested_speed, int slaveadd)
+static void __i2c_init(struct lpc32xx_i2c_base *base,
+ int requested_speed, int slaveadd, unsigned int chip)
{
- struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
-
/* soft reset (auto-clears) */
- writel(LPC32XX_I2C_SOFT_RESET, >ctrl);
+ writel(LPC32XX_I2C_SOFT_RESET, >ctrl);
/* set HI and LO periods for half of the default speed */
- __i2c_set_bus_speed(adap, requested_speed);
+ __i2c_set_bus_speed(base, requested_speed, chip);
}
/* I2C probe called by cmd_i2c when doing 'i2c probe'. */
-static int __i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
+static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev)
{
- struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
int stat;
/* Soft-reset the controller */
- writel(LPC32XX_I2C_SOFT_RESET, >ctrl);
- while (readl(>ctrl) & LPC32XX_I2C_SOFT_RESET)
+ writel(LPC32XX_I2C_SOFT_RESET, >ctrl);
+ while (readl(>ctrl) & LPC32XX_I2C_SOFT_RESET)
;
/* Addre slave for write with start before and stop after */
writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
- >tx);
+ >tx);
/* wait for end of transation */
- while (!((stat = readl(>stat)) & LPC32XX_I2C_STAT_TDI))
+ while (!((stat = readl(>stat)) & LPC32XX_I2C_STAT_TDI))
;
/* was there no acknowledge? */
return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
@@ -128,20 +125,19 @@ static int __i2c_probe_chip(struct i2c_adapter *adap, u8
dev)
* I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
* Begin write, send address byte(s), begin read, receive data bytes, end.
*/
-static int __i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
-int alen, u8 *data, int length)
+static int __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
+ int alen, u8 *data, int length)
{
- struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
int stat, wlen;
/* Soft-reset the controller */
- writel(LPC32XX_I2C_SOFT_RESET, >ctrl);
- while (readl(>ctrl) & LPC32X
[U-Boot] [PATCH] net: link_local: Fix netmask endianness bug
From: Alexandre Messier <amess...@tycoint.com> The network mask must be stored in network order when in a 'struct in_addr'. This fix removes the "gatewayip needed but not set" message on the console when using a link-local IP setup. Signed-off-by: Alexandre Messier <amess...@tycoint.com> Signed-off-by: Sylvain Lemieux <slemi...@tycoint.com> --- net/link_local.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/link_local.c b/net/link_local.c index 27851b6b81..dfd240dfbc 100644 --- a/net/link_local.c +++ b/net/link_local.c @@ -111,7 +111,7 @@ void link_local_start(void) net_set_state(NETLOOP_FAIL); return; } - net_netmask.s_addr = IN_CLASSB_NET; + net_netmask.s_addr = htonl(IN_CLASSB_NET); seed = seed_mac(); if (ip.s_addr == 0) -- 2.11.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] arm: lpc32xx: Add i2c DM support
From: Liam Beguin <lbeg...@tycoint.com>
Since the driver does not yet support devicetree bindings,
the i2c buses need to be defined and probed when the bus
is initialized.
Signed-off-by: Liam Beguin <lbeg...@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemi...@tycoint.com>
---
Note:
* In the init functions, we can only display a warning
and not return an error because the board would reset.
* This patch is require as part of the DM support of the LPC32xx I2C driver.
All I2C drivers should be converted, to DM, by the end of June 2017.
* This patch depend on the following patchset & patch:
https://lists.denx.de/pipermail/u-boot/2017-March/283672.html (I2C)
https://lists.denx.de/pipermail/u-boot/2017-March/283680.html (USB)
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 55
1 file changed, 55 insertions(+)
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index f744398ca7..740ed774ba 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -12,12 +12,38 @@
#include
#include
#include
+#include
#include
static struct clk_pm_regs*clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
+#ifdef CONFIG_DM_I2C
+static const struct lpc32xx_i2c_dev lpc32xx_i2cs[] = {
+ {
+ .base = (struct lpc32xx_i2c_base *)I2C1_BASE,
+ .speed= CONFIG_SYS_I2C_LPC32XX_SPEED,
+ .index= I2C_0,
+ },
+ {
+ .base = (struct lpc32xx_i2c_base *)I2C2_BASE,
+ .speed= CONFIG_SYS_I2C_LPC32XX_SPEED,
+ .index= I2C_1,
+ },
+ {
+ .base = (struct lpc32xx_i2c_base *)(USB_BASE + 0x300),
+ .speed= 10,
+ .index= I2C_2,
+ },
+};
+U_BOOT_DEVICES(lpc32xx_i2cs) = {
+ { "i2c_lpc32xx", _i2cs[0] },
+ { "i2c_lpc32xx", _i2cs[1] },
+ { "i2c_lpc32xx", _i2cs[2] },
+};
+#endif /* CONFIG_DM_I2C */
+
void lpc32xx_uart_init(unsigned int uart_id)
{
if (uart_id < 1 || uart_id > 7)
@@ -110,19 +136,48 @@ void lpc32xx_slc_nand_init(void)
void lpc32xx_usb_init(void)
{
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+ int ret;
+#endif /* CONFIG_DM_I2C */
+
/* Do not route the UART 5 Tx/Rx pins to the USB D+ and USB D- pins. */
clrbits_le32(>ctrl, UART_CTRL_UART5_USB_MODE);
+
+#ifdef CONFIG_DM_I2C
+ ret = uclass_get_device(UCLASS_I2C, I2C_2, );
+ if (ret)
+ debug("I2C_2 init failed: %d\n", ret);
+#endif /* CONFIG_DM_I2C */
}
void lpc32xx_i2c_init(unsigned int devnum)
{
/* Enable I2C interface */
uint32_t ctrl = readl(>i2cclk_ctrl);
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+ int ret;
+#endif /* CONFIG_DM_I2C */
+
if (devnum == 1)
ctrl |= CLK_I2C1_ENABLE;
if (devnum == 2)
ctrl |= CLK_I2C2_ENABLE;
writel(ctrl, >i2cclk_ctrl);
+
+#ifdef CONFIG_DM_I2C
+ if (devnum == 1) {
+ ret = uclass_get_device(UCLASS_I2C, I2C_0, );
+ if (ret)
+ debug("I2C_1 init failed: %d\n", ret);
+ }
+ if (devnum == 2) {
+ ret = uclass_get_device(UCLASS_I2C, I2C_1, );
+ if (ret)
+ debug("I2C_2 init failed: %d\n", ret);
+ }
+#endif /* CONFIG_DM_I2C */
}
U_BOOT_DEVICE(lpc32xx_gpios) = {
--
2.11.0
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[U-Boot] [PATCH] usb: lpc32xx: Add i2c DM support
From: Liam Beguin <lbeg...@tycoint.com>
Add DM support for i2c functions.
Signed-off-by: Liam Beguin <lbeg...@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemi...@tycoint.com>
---
Note:
* This patch is require as part of the DM support of the LPC32xx I2C driver.
All I2C drivers should be converted, to DM, by the end of June 2017.
* The USB driver is supporting the DM and non-DM API.
* This patch depend on the following patchset:
https://lists.denx.de/pipermail/u-boot/2017-March/283672.html
drivers/usb/host/ohci-lpc32xx.c | 33 +++--
1 file changed, 31 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c
index 9245126ed6..51be4c90c7 100644
--- a/drivers/usb/host/ohci-lpc32xx.c
+++ b/drivers/usb/host/ohci-lpc32xx.c
@@ -14,8 +14,10 @@
#include
#include
#include
+#include
#include
#include
+#include
/* OTG I2C controller module register structures */
struct otgi2c_regs {
@@ -83,12 +85,35 @@ static struct clk_pm_regs *clk_pwr = (struct clk_pm_regs
*)CLK_PM_BASE;
static int isp1301_set_value(int reg, u8 value)
{
+#ifndef CONFIG_DM_I2C
return i2c_write(ISP1301_I2C_ADDR, reg, 1, , 1);
+#else
+ struct udevice *dev;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR,
+ 1, );
+ if (ret)
+ return ret;
+
+ return dm_i2c_write(dev, reg, , 1);
+#endif
}
-static void isp1301_configure(void)
+static int isp1301_configure(void)
{
+#ifndef CONFIG_DM_I2C
i2c_set_bus_num(I2C_2);
+#else
+ int ret;
+ struct udevice *bus;
+
+ ret = uclass_get_device_by_seq(UCLASS_I2C, I2C_2, );
+ if (ret) {
+ debug("%s: No bus %d\n", __func__, I2C_2);
+ return ret;
+ }
+#endif
/*
* LPC32XX only supports DAT_SE0 USB mode
@@ -116,6 +141,8 @@ static void isp1301_configure(void)
/* Enable usb_need_clk clock after transceiver is initialized */
setbits_le32(_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN);
+
+ return 0;
}
static int usbpll_setup(void)
@@ -167,7 +194,9 @@ int usb_cpu_init(void)
return ret;
/* Configure ISP1301 */
- isp1301_configure();
+ ret = isp1301_configure();
+ if (ret)
+ return ret;
/* setup USB clocks and PLL */
ret = usbpll_setup();
--
2.11.0
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[U-Boot] [PATCH 6/7] i2c: lpc32xx: Move definitions to header file
From: Liam Beguin <lbeg...@tycoint.com>
Since the lpc32xx i2c driver does not yet support the devicetree bindings,
this structure is also needed by the board file as the hardware description
is done there.
Signed-off-by: Liam Beguin <lbeg...@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemi...@tycoint.com>
---
arch/arm/include/asm/arch-lpc32xx/i2c.h | 37 +
drivers/i2c/lpc32xx_i2c.c | 28 +
2 files changed, 38 insertions(+), 27 deletions(-)
create mode 100644 arch/arm/include/asm/arch-lpc32xx/i2c.h
diff --git a/arch/arm/include/asm/arch-lpc32xx/i2c.h
b/arch/arm/include/asm/arch-lpc32xx/i2c.h
new file mode 100644
index 00..5301d4c1b0
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/i2c.h
@@ -0,0 +1,37 @@
+#ifndef _LPC32XX_I2C_H
+#define _LPC32XX_I2C_H
+
+#include
+#include
+
+/* i2c register set */
+struct lpc32xx_i2c_base {
+ union {
+ u32 rx;
+ u32 tx;
+ };
+ u32 stat;
+ u32 ctrl;
+ u32 clk_hi;
+ u32 clk_lo;
+ u32 adr;
+ u32 rxfl;
+ u32 txfl;
+ u32 rxb;
+ u32 txb;
+ u32 stx;
+ u32 stxfl;
+};
+
+#ifdef CONFIG_DM_I2C
+enum {
+ I2C_0, I2C_1, I2C_2,
+};
+
+struct lpc32xx_i2c_dev {
+ struct lpc32xx_i2c_base *base;
+ int index;
+ uint speed;
+};
+#endif /* CONFIG_DM_I2C */
+#endif /* _LPC32XX_I2C_H */
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
index e00a7a0fa2..8dc568d0e5 100644
--- a/drivers/i2c/lpc32xx_i2c.c
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
@@ -27,33 +28,6 @@
#define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
#endif
-/* i2c register set */
-struct lpc32xx_i2c_base {
- union {
- u32 rx;
- u32 tx;
- };
- u32 stat;
- u32 ctrl;
- u32 clk_hi;
- u32 clk_lo;
- u32 adr;
- u32 rxfl;
- u32 txfl;
- u32 rxb;
- u32 txb;
- u32 stx;
- u32 stxfl;
-};
-
-#ifdef CONFIG_DM_I2C
-struct lpc32xx_i2c_dev {
- struct lpc32xx_i2c_base *base;
- int index;
- uint speed;
-};
-#endif /* CONFIG_DM_I2C */
-
/* TX register fields */
#define LPC32XX_I2C_TX_START 0x0100
#define LPC32XX_I2C_TX_STOP0x0200
--
2.11.0
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[U-Boot] [PATCH 3/7] i2c: lpc32xx: Factor out i2c_adapter parameter
From: Liam Beguin <lbeg...@tycoint.com>
This is part of the prep work for the migration to the driver model.
It will enable the driver to support DM and non-DM configurations
using the same functions.
Signed-off-by: Liam Beguin <lbeg...@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemi...@tycoint.com>
---
drivers/i2c/lpc32xx_i2c.c | 107 +++---
1 file changed, 53 insertions(+), 54 deletions(-)
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
index e5dfdfe1df..62d2d7eee5 100644
--- a/drivers/i2c/lpc32xx_i2c.c
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -29,7 +29,7 @@
#endif
/* i2c register set */
-struct lpc32xx_i2c_registers {
+struct lpc32xx_i2c_base {
union {
u32 rx;
u32 tx;
@@ -61,15 +61,15 @@ struct lpc32xx_i2c_registers {
#define LPC32XX_I2C_STAT_NAI 0x0004
#define LPC32XX_I2C_STAT_TDI 0x0001
-static struct lpc32xx_i2c_registers *lpc32xx_i2c[] = {
- (struct lpc32xx_i2c_registers *)I2C1_BASE,
- (struct lpc32xx_i2c_registers *)I2C2_BASE,
- (struct lpc32xx_i2c_registers *)(USB_BASE + 0x300)
+static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
+ (struct lpc32xx_i2c_base *)I2C1_BASE,
+ (struct lpc32xx_i2c_base *)I2C2_BASE,
+ (struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
};
/* Set I2C bus speed */
-static unsigned int __i2c_set_bus_speed(struct i2c_adapter *adap,
- unsigned int speed)
+static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
+ unsigned int speed, unsigned int chip)
{
int half_period;
@@ -77,7 +77,7 @@ static unsigned int __i2c_set_bus_speed(struct i2c_adapter
*adap,
return -EINVAL;
/* OTG I2C clock source and CLK registers are different */
- if (adap->hwadapnr == 2) {
+ if (chip == 2) {
half_period = (get_periph_clk_rate() / speed) / 2;
if (half_period > 0xFF)
return -EINVAL;
@@ -87,38 +87,35 @@ static unsigned int __i2c_set_bus_speed(struct i2c_adapter
*adap,
return -EINVAL;
}
- writel(half_period, _i2c[adap->hwadapnr]->clk_hi);
- writel(half_period, _i2c[adap->hwadapnr]->clk_lo);
+ writel(half_period, >clk_hi);
+ writel(half_period, >clk_lo);
return 0;
}
/* I2C init called by cmd_i2c when doing 'i2c reset'. */
-static void __i2c_init(struct i2c_adapter *adap,
- int requested_speed, int slaveadd)
+static void __i2c_init(struct lpc32xx_i2c_base *base,
+ int requested_speed, int slaveadd, unsigned int chip)
{
- struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
-
/* soft reset (auto-clears) */
- writel(LPC32XX_I2C_SOFT_RESET, >ctrl);
+ writel(LPC32XX_I2C_SOFT_RESET, >ctrl);
/* set HI and LO periods for half of the default speed */
- __i2c_set_bus_speed(adap, requested_speed);
+ __i2c_set_bus_speed(base, requested_speed, chip);
}
/* I2C probe called by cmd_i2c when doing 'i2c probe'. */
-static int __i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
+static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev)
{
- struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
int stat;
/* Soft-reset the controller */
- writel(LPC32XX_I2C_SOFT_RESET, >ctrl);
- while (readl(>ctrl) & LPC32XX_I2C_SOFT_RESET)
+ writel(LPC32XX_I2C_SOFT_RESET, >ctrl);
+ while (readl(>ctrl) & LPC32XX_I2C_SOFT_RESET)
;
/* Addre slave for write with start before and stop after */
writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
- >tx);
+ >tx);
/* wait for end of transation */
- while (!((stat = readl(>stat)) & LPC32XX_I2C_STAT_TDI))
+ while (!((stat = readl(>stat)) & LPC32XX_I2C_STAT_TDI))
;
/* was there no acknowledge? */
return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
@@ -128,20 +125,19 @@ static int __i2c_probe_chip(struct i2c_adapter *adap, u8
dev)
* I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
* Begin write, send address byte(s), begin read, receive data bytes, end.
*/
-static int __i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
-int alen, u8 *data, int length)
+static int __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
+ int alen, u8 *data, int length)
{
- struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
int stat, wlen;
/* Soft-reset the controller */
- writel(LPC32XX_I2C_SOFT_RESET, >ctrl);
- while (readl(>ctrl) & LPC32XX_I2C_SOFT_RESET)
+ writel(LPC32XX_I2C_SOFT_
[U-Boot] [PATCH 4/7] i2c: lpc32xx: Add DM for lpc32xx I2C
From: Liam Beguin <lbeg...@tycoint.com>
Adding DM specific wrapper functions and definitions.
Signed-off-by: Liam Beguin <lbeg...@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemi...@tycoint.com>
---
drivers/i2c/lpc32xx_i2c.c | 91 +++
1 file changed, 91 insertions(+)
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
index 62d2d7eee5..17e8b744e5 100644
--- a/drivers/i2c/lpc32xx_i2c.c
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -15,6 +15,8 @@
#include
#include
#include
+#include
+#include
/*
* Provide default speed and slave if target did not
@@ -47,6 +49,14 @@ struct lpc32xx_i2c_base {
u32 stxfl;
};
+#ifdef CONFIG_DM_I2C
+struct lpc32xx_i2c_dev {
+ struct lpc32xx_i2c_base *base;
+ int index;
+ uint speed;
+};
+#endif /* CONFIG_DM_I2C */
+
/* TX register fields */
#define LPC32XX_I2C_TX_START 0x0100
#define LPC32XX_I2C_TX_STOP0x0200
@@ -61,11 +71,13 @@ struct lpc32xx_i2c_base {
#define LPC32XX_I2C_STAT_NAI 0x0004
#define LPC32XX_I2C_STAT_TDI 0x0001
+#ifndef CONFIG_DM_I2C
static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
(struct lpc32xx_i2c_base *)I2C1_BASE,
(struct lpc32xx_i2c_base *)I2C2_BASE,
(struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
};
+#endif
/* Set I2C bus speed */
static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
@@ -241,6 +253,7 @@ static int __i2c_write(struct lpc32xx_i2c_base *base, u8
dev, uint addr,
return 0;
}
+#ifndef CONFIG_DM_I2C
static void lpc32xx_i2c_init(struct i2c_adapter *adap,
int requested_speed, int slaveadd)
{
@@ -294,3 +307,80 @@ U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
10,
0,
2)
+#else /* CONFIG_DM_I2C */
+static int lpc32xx_i2c_probe(struct udevice *bus)
+{
+ struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+
+ __i2c_init(dev->base, dev->speed, 0, dev->index);
+ return 0;
+}
+
+static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
+ u32 chip_flags)
+{
+ struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+ return __i2c_probe_chip(dev->base, chip_addr);
+}
+
+static int lpc32xx_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
+ int nmsgs)
+{
+ struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+ struct i2c_msg *dmsg, *omsg, dummy;
+ uint i = 0, address = 0;
+
+ memset(, 0, sizeof(struct i2c_msg));
+
+ /* We expect either two messages (one with an offset and one with the
+* actual data) or one message (just data)
+*/
+ if (nmsgs > 2 || nmsgs == 0) {
+ debug("%s: Only one or two messages are supported.", __func__);
+ return -1;
+ }
+
+ omsg = nmsgs == 1 ? : msg;
+ dmsg = nmsgs == 1 ? msg : msg + 1;
+
+ /* the address is expected to be a uint, not a array. */
+ address = omsg->buf[0];
+ for (i = 1; i < omsg->len; i++)
+ address = (address << 8) + omsg->buf[i];
+
+ if (dmsg->flags & I2C_M_RD)
+ return __i2c_read(dev->base, dmsg->addr, address,
+ omsg->len, dmsg->buf, dmsg->len);
+ else
+ return __i2c_write(dev->base, dmsg->addr, address,
+ omsg->len, dmsg->buf, dmsg->len);
+}
+
+static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+ struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+ return __i2c_set_bus_speed(dev->base, speed, dev->index);
+}
+
+static int lpc32xx_i2c_reset(struct udevice *bus)
+{
+ struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+
+ __i2c_init(dev->base, dev->speed, 0, dev->index);
+ return 0;
+}
+
+static const struct dm_i2c_ops lpc32xx_i2c_ops = {
+ .xfer = lpc32xx_i2c_xfer,
+ .probe_chip= lpc32xx_i2c_probe_chip,
+ .deblock = lpc32xx_i2c_reset,
+ .set_bus_speed = lpc32xx_i2c_set_bus_speed,
+};
+
+U_BOOT_DRIVER(i2c_lpc32xx) = {
+ .id = UCLASS_I2C,
+ .name = "i2c_lpc32xx",
+ .probe= lpc32xx_i2c_probe,
+ .ops = _i2c_ops,
+};
+#endif /* CONFIG_DM_I2C */
--
2.11.0
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[U-Boot] [PATCH 5/7] i2c: lpc32xx: Remove note for DM conversation
From: Sylvain Lemieux <slemi...@tycoint.com> Removed note in the LPC32xx I2C driver for DM conversation. Signed-off-by: Sylvain Lemieux <slemi...@tycoint.com> --- drivers/i2c/lpc32xx_i2c.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c index 17e8b744e5..e00a7a0fa2 100644 --- a/drivers/i2c/lpc32xx_i2c.c +++ b/drivers/i2c/lpc32xx_i2c.c @@ -5,9 +5,6 @@ * Written-by: Albert ARIBAUD - 3ADEV <albert.arib...@3adev.fr> * * SPDX-License-Identifier:GPL-2.0+ - * - * NOTE: This driver should be converted to driver model before June 2017. - * Please see doc/driver-model/i2c-howto.txt for instructions. */ #include -- 2.11.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 7/7] i2c: lpc32xx: Force consistent bus numbering
From: Liam Beguin <lbeg...@tycoint.com>
Normally, this would probably be done by adding devicetree aliases
to the main dtsi file for the lpc32xx and using bus->req_seq instead.
Since we want to have consistent i2c numbering, we cannot force the
bus->req_seq because. If for instance we have 3 buses numbered
from 0 to 2 with i2c0 enabled, i2c1 disabled and i2c2 enabled;
i2c2 can be selected using 'i2c dev 1' and 'i2c dev 2' commands
because a bus can be probed using req_seq or seq interchangeably.
Signed-off-by: Liam Beguin <lbeg...@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemi...@tycoint.com>
---
drivers/i2c/lpc32xx_i2c.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
index 8dc568d0e5..e78b74625e 100644
--- a/drivers/i2c/lpc32xx_i2c.c
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -282,6 +282,7 @@ U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
static int lpc32xx_i2c_probe(struct udevice *bus)
{
struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+ bus->seq = dev->index;
__i2c_init(dev->base, dev->speed, 0, dev->index);
return 0;
--
2.11.0
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[U-Boot] [PATCH 2/7] i2c: lpc32xx: Prepare compatibility functions
From: Liam Beguin <lbeg...@tycoint.com>
This is part of the prep work for the migration to the driver model.
Signed-off-by: Liam Beguin <lbeg...@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemi...@tycoint.com>
---
drivers/i2c/lpc32xx_i2c.c | 47 ++-
1 file changed, 38 insertions(+), 9 deletions(-)
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
index 404fd53f53..e5dfdfe1df 100644
--- a/drivers/i2c/lpc32xx_i2c.c
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -68,7 +68,7 @@ static struct lpc32xx_i2c_registers *lpc32xx_i2c[] = {
};
/* Set I2C bus speed */
-static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
+static unsigned int __i2c_set_bus_speed(struct i2c_adapter *adap,
unsigned int speed)
{
int half_period;
@@ -93,7 +93,7 @@ static unsigned int lpc32xx_i2c_set_bus_speed(struct
i2c_adapter *adap,
}
/* I2C init called by cmd_i2c when doing 'i2c reset'. */
-static void _i2c_init(struct i2c_adapter *adap,
+static void __i2c_init(struct i2c_adapter *adap,
int requested_speed, int slaveadd)
{
struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
@@ -101,11 +101,11 @@ static void _i2c_init(struct i2c_adapter *adap,
/* soft reset (auto-clears) */
writel(LPC32XX_I2C_SOFT_RESET, >ctrl);
/* set HI and LO periods for half of the default speed */
- lpc32xx_i2c_set_bus_speed(adap, requested_speed);
+ __i2c_set_bus_speed(adap, requested_speed);
}
/* I2C probe called by cmd_i2c when doing 'i2c probe'. */
-static int lpc32xx_i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
+static int __i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
{
struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
int stat;
@@ -128,7 +128,7 @@ static int lpc32xx_i2c_probe_chip(struct i2c_adapter *adap,
u8 dev)
* I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
* Begin write, send address byte(s), begin read, receive data bytes, end.
*/
-static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
+static int __i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
int alen, u8 *data, int length)
{
struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
@@ -196,7 +196,7 @@ static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8
dev, uint addr,
* I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
* Begin write, send address byte(s), send data bytes, end.
*/
-static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
+static int __i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
int alen, u8 *data, int length)
{
struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
@@ -246,21 +246,50 @@ static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8
dev, uint addr,
return 0;
}
-U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, _i2c_init, lpc32xx_i2c_probe_chip,
+static void lpc32xx_i2c_init(struct i2c_adapter *adap,
+int requested_speed, int slaveadd)
+{
+ __i2c_init(adap, requested_speed, slaveadd);
+}
+
+static int lpc32xx_i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
+{
+ return __i2c_probe_chip(adap, dev);
+}
+
+static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
+ int alen, u8 *data, int length)
+{
+ return __i2c_read(adap, dev, addr, alen, data, length);
+}
+
+static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
+int alen, u8 *data, int length)
+{
+ return __i2c_write(adap, dev, addr, alen, data, length);
+}
+
+static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int speed)
+{
+ return __i2c_set_bus_speed(adap, speed);
+}
+
+U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
lpc32xx_i2c_read, lpc32xx_i2c_write,
lpc32xx_i2c_set_bus_speed,
CONFIG_SYS_I2C_LPC32XX_SPEED,
CONFIG_SYS_I2C_LPC32XX_SLAVE,
0)
-U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, _i2c_init, lpc32xx_i2c_probe_chip,
+U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
lpc32xx_i2c_read, lpc32xx_i2c_write,
lpc32xx_i2c_set_bus_speed,
CONFIG_SYS_I2C_LPC32XX_SPEED,
CONFIG_SYS_I2C_LPC32XX_SLAVE,
1)
-U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, _i2c_init, NULL,
+U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
lpc32xx_i2c_read, lpc32xx_i2c_write,
lpc32xx_i2c_set_bus_speed,
[U-Boot] [PATCH 1/7] i2c: lpc32xx: Rename probe function
From: Liam Beguin <lbeg...@tycoint.com>
This is part of the prep work for the migration to the driver model.
What used to be the probe function is now called probe_chip.
Signed-off-by: Liam Beguin <lbeg...@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemi...@tycoint.com>
---
drivers/i2c/lpc32xx_i2c.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
index b0167ab3dc..404fd53f53 100644
--- a/drivers/i2c/lpc32xx_i2c.c
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -105,7 +105,7 @@ static void _i2c_init(struct i2c_adapter *adap,
}
/* I2C probe called by cmd_i2c when doing 'i2c probe'. */
-static int lpc32xx_i2c_probe(struct i2c_adapter *adap, u8 dev)
+static int lpc32xx_i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
{
struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
int stat;
@@ -246,14 +246,14 @@ static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8
dev, uint addr,
return 0;
}
-U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, _i2c_init, lpc32xx_i2c_probe,
+U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, _i2c_init, lpc32xx_i2c_probe_chip,
lpc32xx_i2c_read, lpc32xx_i2c_write,
lpc32xx_i2c_set_bus_speed,
CONFIG_SYS_I2C_LPC32XX_SPEED,
CONFIG_SYS_I2C_LPC32XX_SLAVE,
0)
-U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, _i2c_init, lpc32xx_i2c_probe,
+U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, _i2c_init, lpc32xx_i2c_probe_chip,
lpc32xx_i2c_read, lpc32xx_i2c_write,
lpc32xx_i2c_set_bus_speed,
CONFIG_SYS_I2C_LPC32XX_SPEED,
--
2.11.0
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[U-Boot] [PATCH 0/7] i2c: lpc32xx: add DM support
From: Sylvain Lemieux <slemi...@tycoint.com> This patchset add DM support to the I2C LPC32xx platform. All I2C drivers should be converted, to DM, by the end of June 2017. The I2C driver is supporting the DM and non-DM setup. Since the mainline LPC32xx boards are not supporting the devicetree bindings, patch #6 and #7 are required to ensure the LPC32xx I2C driver is working properly in DM in a non-device tree environment. Refer to the individual patch for details. A separate patch will update the LPC32xx USB driver to support the DM i2C API (depend on this patchset). Another patch will add the support to the LPC32xx platform for I2C DM in a non-device tree environment (depend on this patchset and the LPC32xx USB patch). This patchset, and the other 2 patch (USB & platform) were tested on a two different custom LPC32xx board. To enable the mainline LPC32xx board (devkit3250 & work_92105), the following should be done: * Remove "#define CONFIG_SYS_I2C" from board header file and add "CONFIG_DM_I2C=y" to the board defconfig file. Liam Beguin (6): i2c: lpc32xx: Rename probe function i2c: lpc32xx: Prepare compatibility functions i2c: lpc32xx: Factor out i2c_adapter parameter i2c: lpc32xx: Add DM for lpc32xx I2C i2c: lpc32xx: Move definitions to header file i2c: lpc32xx: Force consistent bus numbering Sylvain Lemieux (1): i2c: lpc32xx: Remove note for DM conversation arch/arm/include/asm/arch-lpc32xx/i2c.h | 37 + drivers/i2c/lpc32xx_i2c.c | 237 ++-- 2 files changed, 201 insertions(+), 73 deletions(-) create mode 100644 arch/arm/include/asm/arch-lpc32xx/i2c.h -- 2.11.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
