Re: [PATCH v2 2/2] clk: cdce9xxx: Add maintainer

[Tero Kristo]

On 16/12/2021 15:57, Sean Anderson wrote:


On 12/16/21 8:17 AM, Tero Kristo wrote:

On 15/12/2021 18:47, Sean Anderson wrote:
This adds an entry in MAINTAINERS for the cdce9xx driver, since it 
was not

added when the driver was submitted. This will help future submitters
figure out who to CC.

Signed-off-by: Sean Anderson 
---
Tero, if you don't want to maintain this I'll resubmit this patch 
with the
orphaned status. Alternatively, perhaps Tom wants to maintain this 
driver since

it is used exclusively by boards he maintains.


Well, I am not actively maintaining this, as I am not employed by TI 
anymore. :)


That said, I don't see how much work there is needed for this driver 
anyways, it is very simple, and it can be considered "completed". 
That's the reason I didn't initially put any maintainer on it. Marking 
it "orphaned" would be a bit too harsh status for it imho, as it is 
still used by TI platforms, and it gets actively tested by them.


Well, the issue that I would like to resolve is that in order to CC you
I had to look up who did the initial commit, and even then the email was
wrong (since it had your TI email). So for the benefit of future
hackers, I would like to record your current email. I suppose your
Reviewed-By on the first patch will do.


Yes, I understand your point, however adding a maintainer entry for 
every tiny driver is a bit of an overkill. And well, it would also need 
an ack from the subsystem maintainer itself, whether he/she wants to 
share the workload on it or not.


U-boot contains a script called get_maintainer, that can be used to 
fetch the valid maintainer entry for a file. In this case, it reports 
Lukasz, which, imho, is just fine. cdce9xxx is not going to face many 
changes, and if any, those are just generic framework changes/fixes 
which can be handled just fine by the subsystem maintainers.


-Tero

Re: [PATCH v2 2/2] clk: cdce9xxx: Add maintainer

[Tero Kristo]

On 15/12/2021 18:47, Sean Anderson wrote:

This adds an entry in MAINTAINERS for the cdce9xx driver, since it was not
added when the driver was submitted. This will help future submitters
figure out who to CC.

Signed-off-by: Sean Anderson 
---
Tero, if you don't want to maintain this I'll resubmit this patch with the
orphaned status. Alternatively, perhaps Tom wants to maintain this driver since
it is used exclusively by boards he maintains.


Well, I am not actively maintaining this, as I am not employed by TI 
anymore. :)


That said, I don't see how much work there is needed for this driver 
anyways, it is very simple, and it can be considered "completed". That's 
the reason I didn't initially put any maintainer on it. Marking it 
"orphaned" would be a bit too harsh status for it imho, as it is still 
used by TI platforms, and it gets actively tested by them.


-Tero



(no changes since v1)

  MAINTAINERS | 6 ++
  1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 6db5354322..44f4b846e0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -658,6 +658,12 @@ M: Simon Glass 
  S:Maintained
  F:tools/buildman/
  
+CDCE9XX CLOCK:

+M: Tero Kristo 
+S: Maintained
+F: doc/device-tree-bindings/clock/ti,cdce9xx.txt
+F: drivers/clk/clk-cdce9xx.c
+
  CFI FLASH
  M:Stefan Roese 
  S:Maintained

Re: [PATCH v2 1/2] clk: cdce9xx: Convert .of_xlate to .request

[Tero Kristo]

On 15/12/2021 18:47, Sean Anderson wrote:

This xlate function just performs some checking. We can do this in
request() instead and use the default xlate.

Signed-off-by: Sean Anderson 


Looks good to me now.

Reviewed-by: Tero Kristo 


---

Changes in v2:
- Fix build error caused by mismatched function name

  drivers/clk/clk-cdce9xx.c | 12 +++-
  1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/clk-cdce9xx.c b/drivers/clk/clk-cdce9xx.c
index 6634b7b799..f23465d7e1 100644
--- a/drivers/clk/clk-cdce9xx.c
+++ b/drivers/clk/clk-cdce9xx.c
@@ -86,19 +86,13 @@ static int cdce9xx_reg_write(struct udevice *dev, u8 addr, 
u8 val)
return ret;
  }
  
-static int cdce9xx_clk_of_xlate(struct clk *clk,

-   struct ofnode_phandle_args *args)
+static int cdce9xx_clk_request(struct clk *clk)
  {
struct cdce9xx_clk_data *data = dev_get_priv(clk->dev);
  
-	if (args->args_count != 1)

+   if (clk->id > data->chip->num_outputs)
return -EINVAL;
  
-	if (args->args[0] > data->chip->num_outputs)

-   return -EINVAL;
-
-   clk->id = args->args[0];
-
return 0;
  }
  
@@ -241,7 +235,7 @@ static const struct udevice_id cdce9xx_clk_of_match[] = {

  };
  
  static const struct clk_ops cdce9xx_clk_ops = {

-   .of_xlate = cdce9xx_clk_of_xlate,
+   .request = cdce9xx_clk_request,
.get_rate = cdce9xx_clk_get_rate,
.set_rate = cdce9xx_clk_set_rate,
  };

Re: [PATCH 1/2] clk: cdce9xx: Convert .of_xlate to .request

[Tero Kristo]

On 01/12/2021 22:10, Sean Anderson wrote:

On 12/1/21 3:08 PM, Tom Rini wrote:

On Wed, Dec 01, 2021 at 02:44:02PM -0500, Sean Anderson wrote:


This xlate function just performs some checking. We can do this in
request() instead and use the default xlate.

Signed-off-by: Sean Anderson 


Hi Sean,

Did you compile this? I see...


---

  drivers/clk/clk-cdce9xx.c | 12 +++-
  1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/clk-cdce9xx.c b/drivers/clk/clk-cdce9xx.c
index 6634b7b799..c15e9f210e 100644
--- a/drivers/clk/clk-cdce9xx.c
+++ b/drivers/clk/clk-cdce9xx.c
@@ -86,19 +86,13 @@ static int cdce9xx_reg_write(struct udevice *dev, 
u8 addr, u8 val)

  return ret;
  }
-static int cdce9xx_clk_of_xlate(struct clk *clk,
-    struct ofnode_phandle_args *args)
+static int cdce9xx_clk_of_request(struct clk *clk)


cdce9xx_clk_of_request here...


  {
  struct cdce9xx_clk_data *data = dev_get_priv(clk->dev);
-    if (args->args_count != 1)
+    if (clk->id > data->chip->num_outputs)
  return -EINVAL;
-    if (args->args[0] > data->chip->num_outputs)
-    return -EINVAL;
-
-    clk->id = args->args[0];
-
  return 0;
  }
@@ -241,7 +235,7 @@ static const struct udevice_id 
cdce9xx_clk_of_match[] = {

  };
  static const struct clk_ops cdce9xx_clk_ops = {
-    .of_xlate = cdce9xx_clk_of_xlate,
+    .request = cdce9xx_clk_request,


but cdce9xx_clk_request here.

Other than that, looks fine to me.

-Tero


  .get_rate = cdce9xx_clk_get_rate,
  .set_rate = cdce9xx_clk_set_rate,
  };


Adding Tero...



Thanks. Perhaps .mailmap should be updated?

--Sean

Re: [GIT PULL v2] TI changes for v2021.10 next

[Tero Kristo]

On 13/06/2021 19:49, Tom Rini wrote:

On Fri, Jun 11, 2021 at 09:40:14PM +0530, Lokesh Vutla wrote:


Hi Tom,
Please find the PR for master branch targeted for v2021.10-next branch
with checkpatch warnings fixed. Details about the PR are updated in the tag 
message.

Gitlab CI report: 
https://source.denx.de/u-boot/custodians/u-boot-ti/-/pipelines/7817

The following changes since commit e8f720ee1707b43a0e14ade87b40a1f84baeb2f3:

   Merge branch '2021-06-08-kconfig-migrations' into next (2021-06-09 08:19:13 
-0400)

are available in the Git repository at:

   https://source.denx.de/u-boot/custodians/u-boot-ti.git 
tags/ti-v2021.10-next-v2

for you to fetch changes up to 5abb694d6016eaf497c3d9a3ec79382e217e7508:

   dma: ti: k3-udma: Add support for native configuration of chan/flow 
(2021-06-11 19:18:52 +0530)



I've applied this to u-boot/next now.  But please follow up to fix:
w+(j7200_evm_a72 j721e_evm_a72 j721e_hs_evm_a72 j7200_evm_r5
j721e_evm_r5 j721e_hs_evm_r5)
arch/arm/dts/k3-j7200-common-proc-board.dtb: Warning (reg_format):
/bus@10/bus@2838/mcu-navss/ringacc@2b80:reg: property has
invalid length (80 bytes) (#address-cells == 2, #size-cells == 1)

and all of the other dtc warnings.  Thanks!



Thanks a lot Tom!

I think those DTC warnings are coming out of the DMA support series from 
Vignesh. Vignesh, any comments?


-Tero

Re: [PATCHv6 00/26] HSM rearch series for TI K3 devices

[Tero Kristo]

On 11/06/2021 14:08, Lokesh Vutla wrote:

Hi Tero,

On 11/06/21 2:15 pm, Tero Kristo wrote:

Hello,

One more post, this time with the #ifdef hackery converted to use the
IS_ENABLED / CONFIG_IS_ENABLED macros, and also removed the "common.h"
include from k3-clk.h header. This version also contains fixes to any
build issues reported by Lokesh, and these are squashed in to relevant
patches.


Can you see if the below warnings can be fixed?

hsm/0018-arm-mach-k3-add-support-for-detecting-firmware-image.patch
---
WARNING: Use 'if (IS_ENABLED(CONFIG...))' instead of '#if or #ifdef' where 
possible
#26: FILE: arch/arm/mach-k3/common.c:31:
+#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)


This is static data, can't be fixed. Unless we want to compile it in always?



WARNING: Use 'if (IS_ENABLED(CONFIG...))' instead of '#if or #ifdef' where 
possible
#35: FILE: arch/arm/mach-k3/common.c:40:
+#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)


Same, static data.



WARNING: Use 'if (IS_ENABLED(CONFIG...))' instead of '#if or #ifdef' where 
possible
#55: FILE: arch/arm/mach-k3/common.c:131:
+#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)


This is actually just an old macro I changed from #ifdef to IS_ENABLED. 
Fixing the whole file from the existing #ifdef:s should be outside the 
scope of this series.




WARNING: Use 'if (IS_ENABLED(CONFIG...))' instead of '#if or #ifdef' where 
possible
#124: FILE: arch/arm/mach-k3/common.c:264:
+#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)


This code addresses the static data defined before, changing this will 
break compilation; unless we compile the data always in.




WARNING: Use 'if (IS_ENABLED(CONFIG...))' instead of '#if or #ifdef' where 
possible
#128: FILE: arch/arm/mach-k3/common.c:268:
+#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)


Same as above.


WARNING: Use 'if (IS_ENABLED(CONFIG...))' instead of '#if or #ifdef' where 
possible
#150: FILE: arch/arm/mach-k3/common.c:290:
+#if IS_ENABLED(CONFIG_TI_SECURE_DEVICE)


This can't be changed, the code it addresses is only linked in with the 
config, causing a linker time failure if this is fixed.


Imho, I am not too convinced about the checkpatch tool complaining about 
these issues. :)


-Tero



total: 0 errors, 6 warnings, 0 checks, 144 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
   mechanically convert to the typical style using --fix or --fix-inplace.

hsm/0018-arm-mach-k3-add-support-for-detecting-firmware-image.patch has style
problems, please review.
---
hsm/0019-arm-mach-k3-do-board-config-for-PM-only-if-supported.patch
---
WARNING: Use 'if (IS_ENABLED(CONFIG...))' instead of '#if or #ifdef' where 
possible
#24: FILE: arch/arm/mach-k3/sysfw-loader.c:162:
+#if !CONFIG_IS_ENABLED(K3_DM_FW)

total: 0 errors, 1 warnings, 0 checks, 13 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
   mechanically convert to the typical style using --fix or --fix-inplace.


Thanks and regards,
Lokesh

[PATCHv6 23/26] configs: j721e_evm_r5: Enable raw access power management features

[Tero Kristo]

From: Tero Kristo 

Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 configs/j721e_evm_r5_defconfig | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 8ebbe7348f..8a9b20141b 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -72,7 +72,7 @@ CONFIG_SPL_REGMAP=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
+# CONFIG_CLK_TI_SCI is not set
 CONFIG_DMA_CHANNELS=y
 CONFIG_TI_K3_NAVSS_UDMA=y
 CONFIG_TI_SCI_PROTOCOL=y
@@ -102,7 +102,7 @@ CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_GENERIC is not set
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
+# CONFIG_TI_SCI_POWER_DOMAIN is not set
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_TPS65941=y
 CONFIG_DM_REGULATOR=y
@@ -140,3 +140,11 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x6163
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_K3_DM_FW=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
-- 
2.17.1

[PATCHv6 25/26] board: ti: j72xx: README: update build instructions and image formats

[Tero Kristo]

From: Tero Kristo 

Update build instructions and image formats based on HSM rearch. A new
DM image is added into the build, which gets executed right after R5
SPL finishes its job.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 board/ti/j721e/README | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/board/ti/j721e/README b/board/ti/j721e/README
index c33afa496e..b1c9145c92 100644
--- a/board/ti/j721e/README
+++ b/board/ti/j721e/README
@@ -73,12 +73,12 @@ support. Below is the pictorial representation of boot flow:
 || | |   +-+ |   | 
  |
 || |<|---| Start A72   | |   | 
  |
 || | |   | and jump to | |   | 
  |
-|| | |   | next image  | |   | 
  |
+|| | |   | DM fw image | |   | 
  |
 || | |   +-+ |   | 
  |
 || | |   | +---+ | 
  |
 || |-|---|>| Reset rls | | 
  |
 || | |   | +---+ | 
  |
-||  DMSC   | |   |  :| 
  |
+||  TIFS   | |   |  :| 
  |
 ||Services | |   | +---+ | 
  |
 || |<|---|>|*ATF/OPTEE*| | 
  |
 || | |   | +---+ | 
  |
@@ -154,7 +154,7 @@ $ make CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5
 
 4.2. A72:
 $ make CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=/tmp/a72
-$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin O=/tmp/a72
+$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin DM= 
O=/tmp/a72
 
 Target Images
 --
@@ -197,6 +197,9 @@ Image formats:
 | | A72 OPTEE | |
 | +---+ |
 | |   | |
+| |  R5 DM FW | |
+| +---+ |
+| |   | |
 | |  A72 SPL  | |
 | +---+ |
 | |   | |
-- 
2.17.1

[PATCHv6 26/26] arm: dts: k3-j72xx: correct MCU timer1 frequency

[Tero Kristo]

MCU timer1 is used as the tick timer for MCU R5 SPL, and the
clock-frequency defined in DT appears to be incorrect at the moment.
Actual clock source for the timer is MCU_SYSCLK0 / 4 which is 250MHz.

Earlier setup of 25MHz went unnoticed, as there was a separate issue
with omap-timer, which caused an error to the clock by a factor of 8
with j7 devices. This problem surfaced once the omap-timer was fixed.

Signed-off-by: Tero Kristo 
---
 arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 2 +-
 arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi 
b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index bd037be350..c3aae65b39 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -33,7 +33,7 @@
compatible = "ti,omap5430-timer";
reg = <0x0 0x4040 0x0 0x80>;
ti,timer-alwon;
-   clock-frequency = <2500>;
+   clock-frequency = <25000>;
u-boot,dm-spl;
};
 
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi 
b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index fe095a6153..951331831e 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -46,7 +46,7 @@
compatible = "ti,omap5430-timer";
reg = <0x0 0x4040 0x0 0x80>;
ti,timer-alwon;
-   clock-frequency = <2500>;
+   clock-frequency = <25000>;
u-boot,dm-spl;
};
 
-- 
2.17.1

[PATCHv6 24/26] configs: j7200_evm_r5: Enable raw access power management features

[Tero Kristo]

From: Dave Gerlach 

Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.

Signed-off-by: Dave Gerlach 
Signed-off-by: Tero Kristo 
---
 configs/j7200_evm_r5_defconfig | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index 08fad3e04b..5c51bd5ae7 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -75,7 +75,7 @@ CONFIG_SPL_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
+# CONFIG_CLK_TI_SCI is not set
 CONFIG_DMA_CHANNELS=y
 CONFIG_TI_K3_NAVSS_UDMA=y
 CONFIG_TI_SCI_PROTOCOL=y
@@ -110,7 +110,7 @@ CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_GENERIC is not set
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
+# CONFIG_TI_SCI_POWER_DOMAIN is not set
 CONFIG_K3_SYSTEM_CONTROLLER=y
 CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_DM_RESET=y
@@ -142,3 +142,13 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x6164
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_K3_DM_FW=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
-- 
2.17.1

[PATCHv6 17/26] arm: mach-k3: Add platform data for j721e and j7200

[Tero Kristo]

From: Dave Gerlach 

Add platform clock and powerdomain data for J721e and J7200. This data
is used by the corresponding drivers to register all the required device
clocks and powerdomains.

Signed-off-by: Dave Gerlach 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/Makefile |   2 +-
 arch/arm/mach-k3/j7200/Makefile   |   5 +
 arch/arm/mach-k3/j7200/clk-data.c | 547 +
 arch/arm/mach-k3/j7200/dev-data.c |  77 +++
 arch/arm/mach-k3/j721e/Makefile   |   5 +
 arch/arm/mach-k3/j721e/clk-data.c | 781 ++
 arch/arm/mach-k3/j721e/dev-data.c |  75 +++
 7 files changed, 1491 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-k3/j7200/Makefile
 create mode 100644 arch/arm/mach-k3/j7200/clk-data.c
 create mode 100644 arch/arm/mach-k3/j7200/dev-data.c
 create mode 100644 arch/arm/mach-k3/j721e/Makefile
 create mode 100644 arch/arm/mach-k3/j721e/clk-data.c
 create mode 100644 arch/arm/mach-k3/j721e/dev-data.c

diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 890d1498d0..47cf7b6d17 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -4,7 +4,7 @@
 #  Lokesh Vutla 
 
 obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
-obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
+obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
 obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
 obj-$(CONFIG_ARM64) += arm64-mmu.o
 obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
diff --git a/arch/arm/mach-k3/j7200/Makefile b/arch/arm/mach-k3/j7200/Makefile
new file mode 100644
index 00..ff9abd78ea
--- /dev/null
+++ b/arch/arm/mach-k3/j7200/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/j7200/clk-data.c 
b/arch/arm/mach-k3/j7200/clk-data.c
new file mode 100644
index 00..93c067079a
--- /dev/null
+++ b/arch/arm/mach-k3/j7200/clk-data.c
@@ -0,0 +1,547 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J7200 specific clock platform data
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+   "osc_19_2_mhz",
+   "osc_20_mhz",
+   "osc_24_mhz",
+   "osc_25_mhz",
+   "osc_26_mhz",
+   "osc_27_mhz",
+};
+
+static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
+   "board_0_mcu_ospi0_dqs_out",
+   "fss_mcu_0_ospi_0_ospi_oclk_clk",
+};
+
+static const char * const wkup_fref_clksel_out0_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const main_pll_hfosc_sel_out1_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "board_0_hfosc1_clk_out",
+};
+
+static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
+   "wkup_fref_clksel_out0",
+   "hsdiv1_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
+   "hsdiv4_16fft_mcu_1_hsdivout4_clk",
+   "hsdiv4_16fft_mcu_2_hsdivout4_clk",
+};
+
+static const char * const mcuusart_clk_sel_out0_parents[] = {
+   "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+   "postdiv2_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_gpio0_clksel_out0_parents[] = {
+   "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+   "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+   "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
+   "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = {
+   "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+   "gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out0_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out12_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out14_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out2_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out3_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out4_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "b

[PATCHv6 22/26] arm: mach-k3: j721e_init: Force early probe of clk-k3 driver

[Tero Kristo]

From: Dave Gerlach 

Force the clk-k3 driver to probe early during R5 SPL boot to ensure the
default system clock configuration is completed. Many other drivers
assume a default state of the clock tree and it is currently possible
for them to probe before clk-k3 depending on the exact system
configuration.

Signed-off-by: Dave Gerlach 
Reported-by: Keerthy 
Tested-by: Keerthy 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/j721e_init.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 76a04a9035..e9e076c9e7 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -180,6 +180,18 @@ void board_init_f(ulong dummy)
k3_sysfw_loader(is_rom_loaded_sysfw(),
k3_mmc_stop_clock, k3_mmc_restart_clock);
 
+   /*
+* Force probe of clk_k3 driver here to ensure basic default clock
+* configuration is always done.
+*/
+   if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
+   ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(ti_clk),
+ );
+   if (ret)
+   panic("Failed to initialize clk-k3!\n");
+   }
+
/* Prepare console output */
preloader_console_init();
 
-- 
2.17.1

[PATCHv6 21/26] arm: mach-k3: sysfw-loader: pass boardcfg to sciserver

[Tero Kristo]

From: Tero Kristo 

Copy the contents of the board config loaded from sysfw.itb into an
EXTBOOT shared memory buffer that gets passed to sciserver. This only
needs to be done if EXTBOOT area has not been populated by ROM code yet.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/sysfw-loader.c | 113 ++--
 1 file changed, 106 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 41449db89d..d213e06afb 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -40,6 +40,46 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 #define K3_SYSTEM_CONTROLLER_RPROC_ID  0
 
+#define COMMON_HEADER_ADDRESS  0x41cffb00
+#define BOARDCFG_ADDRESS   0x41c8
+
+#define COMP_TYPE_SBL_DATA 0x11
+#define DESC_TYPE_BOARDCFG_PM_INDEX0x2
+#define DESC_TYPE_BOARDCFG_RM_INDEX0x3
+
+#define BOARD_CONFIG_RM_DESC_TYPE  0x000c
+#define BOARD_CONFIG_PM_DESC_TYPE  0x000e
+
+struct extboot_comp {
+   u32 comp_type;
+   u32 boot_core;
+   u32 comp_opts;
+   u64 dest_addr;
+   u32 comp_size;
+};
+
+struct extboot_header {
+   u8 magic[8];
+   u32 num_comps;
+   struct extboot_comp comps[5];
+   u32 reserved;
+};
+
+struct bcfg_desc {
+   u16 type;
+   u16 offset;
+   u16 size;
+   u8 devgrp;
+   u8 reserved;
+} __packed;
+
+struct bcfg_header {
+   u8 num_elems;
+   u8 sw_rev;
+   struct bcfg_desc descs[4];
+   u16 reserved;
+} __packed;
+
 static bool sysfw_loaded;
 static void *sysfw_load_address;
 
@@ -131,6 +171,13 @@ static void k3_sysfw_configure_using_fit(void *fit,
const void *cfg_fragment_addr;
size_t cfg_fragment_size;
int ret;
+   u8 *buf;
+   struct extboot_header *common_header;
+   struct bcfg_header *bcfg_header;
+   struct extboot_comp *comp;
+   struct bcfg_desc *desc;
+   u32 addr;
+   bool copy_bcfg = false;
 
/* Find the node holding the images information */
images = fdt_path_offset(fit, FIT_IMAGES_PATH);
@@ -159,13 +206,53 @@ static void k3_sysfw_configure_using_fit(void *fit,
  ret);
 
/* Apply power/clock (PM) specific configuration to SYSFW */
-#if !CONFIG_IS_ENABLED(K3_DM_FW)
-   ret = board_ops->board_config_pm(ti_sci,
-(u64)(u32)cfg_fragment_addr,
-(u32)cfg_fragment_size);
-   if (ret)
-   panic("Failed to set board PM configuration (%d)\n", ret);
-#endif
+   if (!IS_ENABLED(CONFIG_K3_DM_FW)) {
+   ret = board_ops->board_config_pm(ti_sci,
+(u64)(u32)cfg_fragment_addr,
+(u32)cfg_fragment_size);
+   if (ret)
+   panic("Failed to set board PM configuration (%d)\n", 
ret);
+   } else {
+   /* Initialize shared memory boardconfig buffer */
+   buf = (u8 *)COMMON_HEADER_ADDRESS;
+   common_header = (struct extboot_header *)buf;
+
+   /* Check if we have a struct populated by ROM in memory already 
*/
+   if (strcmp((char *)common_header->magic, "EXTBOOT"))
+   copy_bcfg = true;
+
+   if (copy_bcfg) {
+   strcpy((char *)common_header->magic, "EXTBOOT");
+   common_header->num_comps = 1;
+
+   comp = _header->comps[0];
+
+   comp->comp_type = COMP_TYPE_SBL_DATA;
+   comp->boot_core = 0x10;
+   comp->comp_opts = 0;
+   addr = (u32)BOARDCFG_ADDRESS;
+   comp->dest_addr = addr;
+   comp->comp_size = sizeof(*bcfg_header);
+
+   bcfg_header = (struct bcfg_header *)addr;
+
+   bcfg_header->num_elems = 2;
+   bcfg_header->sw_rev = 0;
+
+   desc = _header->descs[0];
+
+   desc->type = BOARD_CONFIG_PM_DESC_TYPE;
+   desc->offset = sizeof(*bcfg_header);
+   desc->size = cfg_fragment_size;
+   comp->comp_size += desc->size;
+   desc->devgrp = 0;
+   desc->reserved = 0;
+   memcpy((u8 *)bcfg_header + desc->offset,
+  cfg_fragment_addr, cfg_fragment_size);
+
+   bcfg_header->descs[1].offset = desc->offset + 
desc->size;
+   }
+   }
 
/* Extract resource management (RM) specific configuration from FIT */
ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM,
@@ -174,6 +261,

[PATCHv6 20/26] arm: mach-k3: common: Drop main r5 start

[Tero Kristo]

From: Dave Gerlach 

Only start-up the non-linux remote cores if we are running in legacy
boot mode. HSM rearch is not yet supporting this.

Signed-off-by: Dave Gerlach 
Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/common.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 0a1638ee04..ab6d9bd3d0 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -212,11 +212,12 @@ void __noreturn jump_to_image_no_args(struct 
spl_image_info *spl_image)
panic("rproc failed to be initialized (%d)\n", ret);
 
init_env();
-   start_non_linux_remote_cores();
-   if (!fit_image_info[IMAGE_ID_DM_FW].image_start)
+
+   if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
+   start_non_linux_remote_cores();
size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
 );
-
+   }
 
/*
 * It is assumed that remoteproc device 1 is the corresponding
-- 
2.17.1

[PATCHv6 19/26] arm: mach-k3: do board config for PM only if supported

[Tero Kristo]

From: Tero Kristo 

If the raw PM support is built in, we are operating in the split
firmware approach mode where PM support is not available. In this
case, skip the board config for this.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/sysfw-loader.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 0bacfc4d07..41449db89d 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -159,11 +159,13 @@ static void k3_sysfw_configure_using_fit(void *fit,
  ret);
 
/* Apply power/clock (PM) specific configuration to SYSFW */
+#if !CONFIG_IS_ENABLED(K3_DM_FW)
ret = board_ops->board_config_pm(ti_sci,
 (u64)(u32)cfg_fragment_addr,
 (u32)cfg_fragment_size);
if (ret)
panic("Failed to set board PM configuration (%d)\n", ret);
+#endif
 
/* Extract resource management (RM) specific configuration from FIT */
ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM,
-- 
2.17.1

[PATCHv6 18/26] arm: mach-k3: add support for detecting firmware images from FIT

[Tero Kristo]

From: Tero Kristo 

Add callback routines for parsing the firmware info from FIT image, and
use the data to boot up ATF and the MCU R5 firmware.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/common.c   | 84 +
 arch/arm/mach-k3/common.h   |  1 +
 arch/arm/mach-k3/security.c |  3 +-
 3 files changed, 78 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 9191f686f0..0a1638ee04 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -28,6 +28,27 @@
 #include 
 #include 
 
+#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
+enum {
+   IMAGE_ID_ATF,
+   IMAGE_ID_OPTEE,
+   IMAGE_ID_SPL,
+   IMAGE_ID_DM_FW,
+   IMAGE_AMT,
+};
+
+#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
+static const char *image_os_match[IMAGE_AMT] = {
+   "arm-trusted-firmware",
+   "tee",
+   "U-Boot",
+   "DM",
+};
+#endif
+
+static struct image_info fit_image_info[IMAGE_AMT];
+#endif
+
 struct ti_sci_handle *get_ti_sci_handle(void)
 {
struct udevice *dev;
@@ -107,7 +128,7 @@ int early_console_init(void)
 }
 #endif
 
-#ifdef CONFIG_SYS_K3_SPL_ATF
+#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
 
 void init_env(void)
 {
@@ -181,7 +202,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info 
*spl_image)
typedef void __noreturn (*image_entry_noargs_t)(void);
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
u32 loadaddr = 0;
-   int ret, size;
+   int ret, size = 0;
 
/* Release all the exclusive devices held by SPL before starting ATF */
ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
@@ -192,15 +213,20 @@ void __noreturn jump_to_image_no_args(struct 
spl_image_info *spl_image)
 
init_env();
start_non_linux_remote_cores();
-   size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
-);
+   if (!fit_image_info[IMAGE_ID_DM_FW].image_start)
+   size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
+);
 
 
/*
 * It is assumed that remoteproc device 1 is the corresponding
 * Cortex-A core which runs ATF. Make sure DT reflects the same.
 */
-   ret = rproc_load(1, spl_image->entry_point, 0x200);
+   if (!fit_image_info[IMAGE_ID_ATF].image_start)
+   fit_image_info[IMAGE_ID_ATF].image_start =
+   spl_image->entry_point;
+
+   ret = rproc_load(1, fit_image_info[IMAGE_ID_ATF].image_start, 0x200);
if (ret)
panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
 
@@ -210,7 +236,8 @@ void __noreturn jump_to_image_no_args(struct spl_image_info 
*spl_image)
ret = rproc_start(1);
if (ret)
panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
-   if (!(size > 0 && valid_elf_image(loadaddr))) {
+   if (!fit_image_info[IMAGE_ID_DM_FW].image_len &&
+   !(size > 0 && valid_elf_image(loadaddr))) {
debug("Shutting down...\n");
release_resources_for_core_shutdown();
 
@@ -218,13 +245,54 @@ void __noreturn jump_to_image_no_args(struct 
spl_image_info *spl_image)
asm volatile("wfe");
}
 
-   image_entry_noargs_t image_entry =
-   (image_entry_noargs_t)load_elf_image_phdr(loadaddr);
+   if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
+   loadaddr = load_elf_image_phdr(loadaddr);
+   } else {
+   loadaddr = fit_image_info[IMAGE_ID_DM_FW].image_start;
+   if (valid_elf_image(loadaddr))
+   loadaddr = load_elf_image_phdr(loadaddr);
+   }
+
+   debug("%s: jumping to address %x\n", __func__, loadaddr);
+
+   image_entry_noargs_t image_entry = (image_entry_noargs_t)loadaddr;
 
image_entry();
 }
 #endif
 
+#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
+{
+#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
+   int len;
+   int i;
+   const char *os;
+   u32 addr;
+
+   os = fdt_getprop(fit, node, "os", );
+   addr = fdt_getprop_u32_default_node(fit, node, 0, "entry", -1);
+
+   debug("%s: processing image: addr=%x, size=%d, os=%s\n", __func__,
+ addr, *p_size, os);
+
+   for (i = 0; i < IMAGE_AMT; i++) {
+   if (!strcmp(os, image_os_match[i])) {
+   fit_image_info[i].image_start = addr;
+   fit_image_info[i].image_len = *p_size;
+   debug("%s: matched image for ID %d\n", 

[PATCHv6 15/26] cmd: ti: pd: Add debug command for K3 power domains

[Tero Kristo]

From: Tero Kristo 

Add support command for debugging K3 power domains. This is useful with
the HSM rearch setup, where power domains are directly controlled by SPL
instead of going through the TI SCI layer. The debugging support is only
available in the u-boot codebase though, so the raw register access
power domain layer must be enabled on u-boot side for this to work. By
default, u-boot side uses the TI SCI layer, and R5 SPL only uses the
direct access methods.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
Reviewed-by: Jaehoon Chung 
---
 cmd/ti/Kconfig |   8 ++
 cmd/ti/Makefile|   1 +
 cmd/ti/pd.c| 185 +
 drivers/power/domain/ti-power-domain.c |   6 +-
 include/k3-dev.h   |   9 ++
 5 files changed, 206 insertions(+), 3 deletions(-)
 create mode 100644 cmd/ti/pd.c

diff --git a/cmd/ti/Kconfig b/cmd/ti/Kconfig
index efeff0d482..db557445a8 100644
--- a/cmd/ti/Kconfig
+++ b/cmd/ti/Kconfig
@@ -7,4 +7,12 @@ config CMD_DDR3
   supports memory verification, memory comapre and ecc
   verification if supported.
 
+config CMD_PD
+   bool "command for verifying power domains"
+   depends on TI_POWER_DOMAIN
+   help
+  Debug command for K3 power domains. For this to work, the
+  K3 power domain driver must be enabled for the u-boot; by
+  default it is only enabled for SPL.
+
 endmenu
diff --git a/cmd/ti/Makefile b/cmd/ti/Makefile
index 16fbade9ed..045593396b 100644
--- a/cmd/ti/Makefile
+++ b/cmd/ti/Makefile
@@ -5,4 +5,5 @@ obj- += dummy.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_CMD_DDR3) += ddr3.o
+obj-$(CONFIG_CMD_PD) += pd.o
 endif
diff --git a/cmd/ti/pd.c b/cmd/ti/pd.c
new file mode 100644
index 00..9e820b84ca
--- /dev/null
+++ b/cmd/ti/pd.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Power Domain test commands
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated, 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static const struct udevice_id ti_pd_of_match[] = {
+   { .compatible = "ti,sci-pm-domain" },
+   { /* sentinel */ }
+};
+
+static struct ti_k3_pd_platdata *ti_pd_find_data(void)
+{
+   struct udevice *dev;
+   int i = 0;
+
+   while (1) {
+   uclass_get_device(UCLASS_POWER_DOMAIN, i++, );
+   if (!dev)
+   return NULL;
+
+   if (device_is_compatible(dev,
+ti_pd_of_match[0].compatible))
+   return  dev_get_priv(dev);
+   }
+
+   return NULL;
+}
+
+static void dump_lpsc(struct ti_k3_pd_platdata *data, struct ti_pd *pd)
+{
+   int i;
+   struct ti_lpsc *lpsc;
+   u8 state;
+   static const char * const lpsc_states[] = {
+   "swrstdis", "syncrst", "disable", "enable", "autosleep",
+   "autowake", "unknown",
+   };
+
+   for (i = 0; i < data->num_lpsc; i++) {
+   lpsc = >lpsc[i];
+   if (lpsc->pd != pd)
+   continue;
+   state = lpsc_get_state(lpsc);
+   if (state > ARRAY_SIZE(lpsc_states))
+   state = ARRAY_SIZE(lpsc_states) - 1;
+   printf("LPSC%d: state=%s, usecount=%d\n",
+  lpsc->id, lpsc_states[state], lpsc->usecount);
+   }
+}
+
+static void dump_pd(struct ti_k3_pd_platdata *data, struct ti_psc *psc)
+{
+   int i;
+   struct ti_pd *pd;
+   u8 state;
+   static const char * const pd_states[] = {
+   "off", "on", "unknown"
+   };
+
+   for (i = 0; i < data->num_pd; i++) {
+   pd = >pd[i];
+   if (pd->psc != psc)
+   continue;
+   state = ti_pd_state(pd);
+   if (state > ARRAY_SIZE(pd_states))
+   state = ARRAY_SIZE(pd_states) - 1;
+   printf("  PD%d: state=%s, usecount=%d:\n",
+  pd->id, pd_states[state], pd->usecount);
+   dump_lpsc(data, pd);
+   }
+}
+
+static void dump_psc(struct ti_k3_pd_platdata *data)
+{
+   int i;
+   struct ti_psc *psc;
+
+   for (i = 0; i < data->num_psc; i++) {
+   psc = >psc[i];
+   printf("PSC%d [%p]:\n", psc->id, psc->base);
+   dump_pd(data, psc);
+   }
+}
+
+static int do_pd_dump(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+   struct ti_k3_pd_platdata *data;
+
+   data = ti_pd_find_data();
+   if (!data)
+   return CMD_RET_FAILURE;
+
+   dump_psc(data);
+
+   return 0;
+}
+
+static int do_pd_endis(int argc, char *const argv[], u8 state)
+

[PATCHv6 16/26] tools: k3_fit_atf: add DM binary to the FIT image

[Tero Kristo]

From: Tero Kristo 

Add DM (device manager) firmware image to the fit image that is loaded by
R5 SPL. This is needed with the HSM rearch where the firmware allocation
has been changed slightly.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/config.mk |  4 
 tools/k3_fit_atf.sh| 19 ++-
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk
index 6744890682..da458bcfb2 100644
--- a/arch/arm/mach-k3/config.mk
+++ b/arch/arm/mach-k3/config.mk
@@ -49,6 +49,10 @@ endif
 
 ifdef CONFIG_ARM64
 
+ifeq ($(CONFIG_SOC_K3_J721E),)
+export DM := /dev/null
+endif
+
 ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
 SPL_ITS := u-boot-spl-k3_HS.its
 $(SPL_ITS): export IS_HS=1
diff --git a/tools/k3_fit_atf.sh b/tools/k3_fit_atf.sh
index 2c0287a633..3a476ced98 100755
--- a/tools/k3_fit_atf.sh
+++ b/tools/k3_fit_atf.sh
@@ -21,6 +21,13 @@ if [ ! -f $TEE ]; then
TEE=/dev/null
 fi
 
+[ -z "$DM" ] && DM="dm.bin"
+
+if [ ! -e $DM ]; then
+   echo "WARNING DM file $DM NOT found, resulting might be non-functional" 
>&2
+   DM=/dev/null
+fi
+
 if [ ! -z "$IS_HS" ]; then
HS_APPEND=_HS
 fi
@@ -53,6 +60,16 @@ cat << __HEADER_EOF
load = <0x9e80>;
entry = <0x9e80>;
};
+   dm {
+   description = "DM binary";
+   data = /incbin/("$DM");
+   type = "firmware";
+   arch = "arm32";
+   compression = "none";
+   os = "DM";
+   load = <0xa000>;
+   entry = <0xa000>;
+   };
spl {
description = "SPL (64-bit)";
data = /incbin/("spl/u-boot-spl-nodtb.bin$HS_APPEND");
@@ -94,7 +111,7 @@ do
$(basename $dtname) {
description = "$(basename $dtname .dtb)";
firmware = "atf";
-   loadables = "tee", "spl";
+   loadables = "tee", "dm", "spl";
fdt = "$(basename $dtname)";
};
 __CONF_SECTION_EOF
-- 
2.17.1

[PATCHv6 13/26] clk: add support for TI K3 SoC clocks

[Tero Kristo]

From: Tero Kristo 

Add driver to support TI K3 generation SoC clocks. This driver registers
the clocks provided via platform data, and adds support for controlling
the clocks via DT handles.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/ti/Kconfig  |  12 ++
 drivers/clk/ti/Makefile |   1 +
 drivers/clk/ti/clk-k3.c | 374 
 include/k3-clk.h| 162 +
 4 files changed, 549 insertions(+)
 create mode 100644 drivers/clk/ti/clk-k3.c

diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index a8ec4f541a..fbcdefd889 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -53,3 +53,15 @@ config SPL_CLK_K3_PLL
depends on CLK && LIB_RATIONAL && SPL
help
  Enables PLL clock support for K3 SoC family of devices.
+
+config CLK_K3
+   bool "Clock support for K3 SoC family of devices"
+   depends on CLK
+   help
+ Enables the clock translation layer from DT to device clocks.
+
+config SPL_CLK_K3
+   bool "Clock support for K3 SoC family of devices"
+   depends on CLK && SPL
+   help
+ Enables the clock translation layer from DT to device clocks.
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 47839213e5..07aa9a53e0 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o
 obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
 obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o
 obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_K3) += clk-k3.o
diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
new file mode 100644
index 00..e921894e7a
--- /dev/null
+++ b/drivers/clk/ti/clk-k3.c
@@ -0,0 +1,374 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 clock driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "k3-clk.h"
+
+#define PLL_MIN_FREQ   8
+#define PLL_MAX_FREQ   32UL
+#define PLL_MAX_DIV127
+
+/**
+ * struct clk_map - mapping from dev/clk id tuples towards physical clocks
+ * @dev_id: device ID for the clock
+ * @clk_id: clock ID for the clock
+ * @clk: pointer to the registered clock entry for the mapping
+ */
+struct clk_map {
+   u16 dev_id;
+   u32 clk_id;
+   struct clk *clk;
+};
+
+/**
+ * struct ti_clk_data - clock controller information structure
+ * @map: mapping from dev/clk id tuples to physical clock entries
+ * @size: number of entries in the map
+ */
+struct ti_clk_data {
+   struct clk_map *map;
+   int size;
+};
+
+static ulong osc_freq;
+
+static void clk_add_map(struct ti_clk_data *data, struct clk *clk,
+   u32 dev_id, u32 clk_id)
+{
+   struct clk_map *map;
+
+   debug("%s: added clk=%p, data=%p, dev=%d, clk=%d\n", __func__,
+ clk, data, dev_id, clk_id);
+   if (!clk)
+   return;
+
+   map = data->map + data->size++;
+
+   map->dev_id = dev_id;
+   map->clk_id = clk_id;
+   map->clk = clk;
+}
+
+static const struct soc_attr ti_k3_soc_clk_data[] = {
+#if IS_ENABLED(CONFIG_SOC_K3_J721E)
+   {
+   .family = "J721E",
+   .data = _clk_platdata,
+   },
+   {
+   .family = "J7200",
+   .data = _clk_platdata,
+   },
+#endif
+   { /* sentinel */ }
+};
+
+static int ti_clk_probe(struct udevice *dev)
+{
+   struct ti_clk_data *data = dev_get_priv(dev);
+   struct clk *clk;
+   const char *name;
+   const struct clk_data *ti_clk_data;
+   int i, j;
+   const struct soc_attr *soc_match_data;
+   const struct ti_k3_clk_platdata *pdata;
+
+   debug("%s(dev=%p)\n", __func__, dev);
+
+   soc_match_data = soc_device_match(ti_k3_soc_clk_data);
+   if (!soc_match_data)
+   return -ENODEV;
+
+   pdata = (const struct ti_k3_clk_platdata *)soc_match_data->data;
+
+   data->map = kcalloc(pdata->soc_dev_clk_data_cnt, sizeof(*data->map),
+   GFP_KERNEL);
+   data->size = 0;
+
+   for (i = 0; i < pdata->clk_list_cnt; i++) {
+   ti_clk_data = >clk_list[i];
+
+   switch (ti_clk_data->type) {
+   case CLK_TYPE_FIXED_RATE:
+   name = ti_clk_data->clk.fixed_rate.name;
+   clk = clk_register_fixed_rate(NULL,
+ name,
+ 
ti_clk_data->clk.fixed_rate.rate);
+   break;
+   case CLK_TYPE_DIV:
+   name = ti_clk_data->clk.div.na

[PATCHv6 14/26] power: domain: Introduce driver for raw TI K3 PDs

[Tero Kristo]

From: Tero Kristo 

Normally, power domains are handled via TI-SCI in K3 SoCs. However,
SPL is not going to have access to sysfw resources, so it must control
them directly. Add driver for supporting this.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
Reviewed-by: Jaehoon Chung 
---
 drivers/power/domain/Kconfig   |   7 +
 drivers/power/domain/Makefile  |   1 +
 drivers/power/domain/ti-power-domain.c | 368 +
 include/k3-dev.h   |  76 +
 4 files changed, 452 insertions(+)
 create mode 100644 drivers/power/domain/ti-power-domain.c
 create mode 100644 include/k3-dev.h

diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index a0fd980752..99b3f9ae71 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -72,4 +72,11 @@ config TI_SCI_POWER_DOMAIN
help
  Generic power domain implementation for TI devices implementing the
  TI SCI protocol.
+
+config TI_POWER_DOMAIN
+   bool "Enable the TI K3 Power domain driver"
+   depends on POWER_DOMAIN && ARCH_K3
+   help
+ Generic power domain implementation for TI K3 devices.
+
 endmenu
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 45bf9f6383..3d1e5f073c 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
 obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
 obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o
 obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o
+obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o
diff --git a/drivers/power/domain/ti-power-domain.c 
b/drivers/power/domain/ti-power-domain.c
new file mode 100644
index 00..56bc6fc31c
--- /dev/null
+++ b/drivers/power/domain/ti-power-domain.c
@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments power domain driver
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PSC_PTCMD  0x120
+#define PSC_PTSTAT 0x128
+#define PSC_PDSTAT 0x200
+#define PSC_PDCTL  0x300
+#define PSC_MDSTAT 0x800
+#define PSC_MDCTL  0xa00
+
+#define PDCTL_STATE_MASK   0x1
+#define PDCTL_STATE_OFF0x0
+#define PDCTL_STATE_ON 0x1
+
+#define MDSTAT_STATE_MASK  0x3f
+#define MDSTAT_BUSY_MASK   0x30
+#define MDSTAT_STATE_SWRSTDISABLE  0x0
+#define MDSTAT_STATE_ENABLE0x3
+
+#define LPSC_TIMEOUT   1000
+#define PD_TIMEOUT 1000
+
+static u32 psc_read(struct ti_psc *psc, u32 reg)
+{
+   u32 val;
+
+   val = readl(psc->base + reg);
+   debug("%s: 0x%x from %p\n", __func__, val, psc->base + reg);
+   return val;
+}
+
+static void psc_write(u32 val, struct ti_psc *psc, u32 reg)
+{
+   debug("%s: 0x%x to %p\n", __func__, val, psc->base + reg);
+   writel(val, psc->base + reg);
+}
+
+static u32 pd_read(struct ti_pd *pd, u32 reg)
+{
+   return psc_read(pd->psc, reg + 4 * pd->id);
+}
+
+static void pd_write(u32 val, struct ti_pd *pd, u32 reg)
+{
+   psc_write(val, pd->psc, reg + 4 * pd->id);
+}
+
+static u32 lpsc_read(struct ti_lpsc *lpsc, u32 reg)
+{
+   return psc_read(lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static void lpsc_write(u32 val, struct ti_lpsc *lpsc, u32 reg)
+{
+   psc_write(val, lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static const struct soc_attr ti_k3_soc_pd_data[] = {
+#if IS_ENABLED(CONFIG_SOC_K3_J721E)
+   {
+   .family = "J721E",
+   .data = _pd_platdata,
+   },
+   {
+   .family = "J7200",
+   .data = _pd_platdata,
+   },
+#endif
+   { /* sentinel */ }
+};
+
+static int ti_power_domain_probe(struct udevice *dev)
+{
+   struct ti_k3_pd_platdata *data = dev_get_priv(dev);
+   const struct soc_attr *soc_match_data;
+   const struct ti_k3_pd_platdata *pdata;
+
+   printf("%s(dev=%p)\n", __func__, dev);
+
+   if (!data)
+   return -ENOMEM;
+
+   soc_match_data = soc_device_match(ti_k3_soc_pd_data);
+   if (!soc_match_data)
+   return -ENODEV;
+
+   pdata = (const struct ti_k3_pd_platdata *)soc_match_data->data;
+
+   data->psc = pdata->psc;
+   data->pd = pdata->pd;
+   data->lpsc = pdata->lpsc;
+   data->devs = pdata->devs;
+   data->num_psc = pdata->num_psc;
+   data->num_pd = pdata->num_pd;
+   data->num_lpsc = pdata->num_lpsc;
+   data->num_devs = pdata->num_devs;
+
+   return 0;

[PATCHv6 12/26] clk: add support for TI K3 SoC PLL

[Tero Kristo]

From: Tero Kristo 

Add support for TI K3 SoC PLLs. This clock type supports
enabling/disabling/setting and querying the clock rate for the PLL. The
euclidean library routine is used to calculate divider/multiplier rates
for the PLLs.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/ti/Kconfig  |  12 ++
 drivers/clk/ti/Makefile |   1 +
 drivers/clk/ti/clk-k3-pll.c | 283 
 include/k3-clk.h|  15 ++
 4 files changed, 311 insertions(+)
 create mode 100644 drivers/clk/ti/clk-k3-pll.c
 create mode 100644 include/k3-clk.h

diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index 2dc86d44a9..a8ec4f541a 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -41,3 +41,15 @@ config CLK_TI_SCI
  This enables the clock driver support over TI System Control Interface
  available on some new TI's SoCs. If you wish to use clock resources
  managed by the TI System Controller, say Y here. Otherwise, say N.
+
+config CLK_K3_PLL
+   bool "PLL clock support for K3 SoC family of devices"
+   depends on CLK && LIB_RATIONAL
+   help
+ Enables PLL clock support for K3 SoC family of devices.
+
+config SPL_CLK_K3_PLL
+   bool "PLL clock support for K3 SoC family of devices"
+   depends on CLK && LIB_RATIONAL && SPL
+   help
+ Enables PLL clock support for K3 SoC family of devices.
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 9f56b47736..47839213e5 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o
 obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o
 obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
 obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o
diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c
new file mode 100644
index 00..bf2407a020
--- /dev/null
+++ b/drivers/clk/ti/clk-k3-pll.c
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 SoC PLL clock driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "k3-clk.h"
+#include 
+
+/* 16FFT register offsets */
+#define PLL_16FFT_CFG  0x08
+#define PLL_KICK0  0x10
+#define PLL_KICK1  0x14
+#define PLL_16FFT_CTRL 0x20
+#define PLL_16FFT_STAT 0x24
+#define PLL_16FFT_FREQ_CTRL0   0x30
+#define PLL_16FFT_FREQ_CTRL1   0x34
+#define PLL_16FFT_DIV_CTRL 0x38
+
+/* CTRL register bits */
+#define PLL_16FFT_CTRL_BYPASS_EN   BIT(31)
+#define PLL_16FFT_CTRL_PLL_EN  BIT(15)
+#define PLL_16FFT_CTRL_DSM_EN  BIT(1)
+
+/* STAT register bits */
+#define PLL_16FFT_STAT_LOCKBIT(0)
+
+/* FREQ_CTRL0 bits */
+#define PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK   0xfff
+
+/* DIV CTRL register bits */
+#define PLL_16FFT_DIV_CTRL_REF_DIV_MASK0x3f
+
+#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS  24
+#define PLL_16FFT_HSDIV_CTRL_CLKOUT_EN  BIT(15)
+
+/* KICK register magic values */
+#define PLL_KICK0_VALUE0x68ef3490
+#define PLL_KICK1_VALUE0xd172bc5a
+
+/**
+ * struct ti_pll_clk - TI PLL clock data info structure
+ * @clk: core clock structure
+ * @reg: memory address of the PLL controller
+ */
+struct ti_pll_clk {
+   struct clk  clk;
+   void __iomem*reg;
+};
+
+#define to_clk_pll(_clk) container_of(_clk, struct ti_pll_clk, clk)
+
+static int ti_pll_wait_for_lock(struct clk *clk)
+{
+   struct ti_pll_clk *pll = to_clk_pll(clk);
+   u32 stat;
+   int i;
+
+   for (i = 0; i < 10; i++) {
+   stat = readl(pll->reg + PLL_16FFT_STAT);
+   if (stat & PLL_16FFT_STAT_LOCK)
+   return 0;
+   }
+
+   printf("%s: pll (%s) failed to lock\n", __func__,
+  clk->dev->name);
+
+   return -EBUSY;
+}
+
+static ulong ti_pll_clk_get_rate(struct clk *clk)
+{
+   struct ti_pll_clk *pll = to_clk_pll(clk);
+   u64 current_freq;
+   u64 parent_freq = clk_get_parent_rate(clk);
+   u32 pllm;
+   u32 plld;
+   u32 pllfm;
+   u32 ctrl;
+
+   /* Check if we are in bypass */
+   ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+   if (ctrl & PLL_16FFT_CTRL_BYPASS_EN)
+   return parent_freq;
+
+   pllm = readl(pll->reg + PLL_16FFT_FREQ_CTRL0);
+   pllfm = readl(pll->reg + PLL_16FFT_FREQ_CTRL1);
+
+   plld = readl(pll->reg + PLL_16FFT_DIV_CTRL) &
+   PLL_16FFT_DIV_CTRL_REF_DIV_MASK;
+
+   current_freq = parent_freq * pllm / plld;
+
+   if (pllfm) {
+ 

[PATCHv6 11/26] clk: fix set_rate to clean up cached rates for the hierarchy

[Tero Kristo]

From: Tero Kristo 

Clock rates are cached within the individual clock nodes, and right now
if one changes a clock rate somewhere in the middle of the tree, none
of its child clocks notice the change. To fix this, clear up all the
cached rates for us and our child clocks.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/clk-uclass.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 815f7bfe98..3d2344f009 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -568,6 +568,22 @@ ulong clk_round_rate(struct clk *clk, ulong rate)
return ops->round_rate(clk, rate);
 }
 
+static void clk_clean_rate_cache(struct clk *clk)
+{
+   struct udevice *child_dev;
+   struct clk *clkp;
+
+   if (!clk)
+   return;
+
+   clk->rate = 0;
+
+   list_for_each_entry(child_dev, >dev->child_head, sibling_node) {
+   clkp = dev_get_clk_ptr(child_dev);
+   clk_clean_rate_cache(clkp);
+   }
+}
+
 ulong clk_set_rate(struct clk *clk, ulong rate)
 {
const struct clk_ops *ops;
@@ -580,6 +596,9 @@ ulong clk_set_rate(struct clk *clk, ulong rate)
if (!ops->set_rate)
return -ENOSYS;
 
+   /* Clean up cached rates for us and all child clocks */
+   clk_clean_rate_cache(clk);
+
return ops->set_rate(clk, rate);
 }
 
-- 
2.17.1

[PATCHv6 10/26] clk: fix assigned-clocks to pass with deferring provider

[Tero Kristo]

From: Tero Kristo 

If a clock provider is not ready for assigning default rates/parents
during its probe, it may return -EPROBE_DEFER directly from xlate.
Handle this special case properly by skipping the entry and adjusting the
return value to pass. The defaults will be handled properly in post probe
phase then.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/clk-uclass.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 451d7da001..815f7bfe98 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -241,6 +241,15 @@ static int clk_set_default_parents(struct udevice *dev, 
int stage)
 
ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  index, );
+   /*
+* If the clock provider is not ready yet, let it handle
+* the re-programming later.
+*/
+   if (ret == -EPROBE_DEFER) {
+   ret = 0;
+   continue;
+   }
+
if (ret) {
debug("%s: could not get assigned clock %d for %s\n",
  __func__, index, dev_read_name(dev));
@@ -309,6 +318,15 @@ static int clk_set_default_rates(struct udevice *dev, int 
stage)
 
ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  index, );
+   /*
+* If the clock provider is not ready yet, let it handle
+* the re-programming later.
+*/
+   if (ret == -EPROBE_DEFER) {
+   ret = 0;
+   continue;
+   }
+
if (ret) {
dev_dbg(dev,
"could not get assigned clock %d (err = %d)\n",
-- 
2.17.1

[PATCHv6 09/26] clk: sci-clk: fix return value of set_rate

[Tero Kristo]

From: Tero Kristo 

Set rate should return the new clock rate on success, and negative error
value on failure. Fix this, as currently set_rate returns 0 on success.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/ti/clk-sci.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/ti/clk-sci.c b/drivers/clk/ti/clk-sci.c
index 6f0fdaa111..acb9eadf03 100644
--- a/drivers/clk/ti/clk-sci.c
+++ b/drivers/clk/ti/clk-sci.c
@@ -111,10 +111,12 @@ static ulong ti_sci_clk_set_rate(struct clk *clk, ulong 
rate)
 #endif
 
ret = cops->set_freq(sci, clk->id, clk->data, 0, rate, ULONG_MAX);
-   if (ret)
+   if (ret) {
dev_err(clk->dev, "%s: set_freq failed (%d)\n", __func__, ret);
+   return ret;
+   }
 
-   return ret;
+   return rate;
 }
 
 static int ti_sci_clk_set_parent(struct clk *clk, struct clk *parent)
-- 
2.17.1

[PATCHv6 08/26] clk: add support for setting clk rate from cmdline

[Tero Kristo]

From: Tero Kristo 

Add new clk subcommand "clk setfreq", for setting up a clock rate
directly from u-boot cmdline. This is handy for any debugging purposes
towards clocks.

Acked-by: Lukasz Majewski 
Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 cmd/clk.c | 53 +++--
 1 file changed, 51 insertions(+), 2 deletions(-)

diff --git a/cmd/clk.c b/cmd/clk.c
index 0245b97136..7ece2454e0 100644
--- a/cmd/clk.c
+++ b/cmd/clk.c
@@ -98,8 +98,56 @@ static int do_clk_dump(struct cmd_tbl *cmdtp, int flag, int 
argc,
return ret;
 }
 
+#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(CLK)
+struct udevice *clk_lookup(const char *name)
+{
+   int i = 0;
+   struct udevice *dev;
+
+   do {
+   uclass_get_device(UCLASS_CLK, i++, );
+   if (!strcmp(name, dev->name))
+   return dev;
+   } while (dev);
+
+   return NULL;
+}
+
+static int do_clk_setfreq(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+   struct clk *clk = NULL;
+   s32 freq;
+   struct udevice *dev;
+
+   freq = simple_strtoul(argv[2], NULL, 10);
+
+   dev = clk_lookup(argv[1]);
+
+   if (dev)
+   clk = dev_get_clk_ptr(dev);
+
+   if (!clk) {
+   printf("clock '%s' not found.\n", argv[1]);
+   return -EINVAL;
+   }
+
+   freq = clk_set_rate(clk, freq);
+   if (freq < 0) {
+   printf("set_rate failed: %d\n", freq);
+   return CMD_RET_FAILURE;
+   }
+
+   printf("set_rate returns %u\n", freq);
+   return 0;
+}
+#endif
+
 static struct cmd_tbl cmd_clk_sub[] = {
U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""),
+#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(CLK)
+   U_BOOT_CMD_MKENT(setfreq, 3, 1, do_clk_setfreq, "", ""),
+#endif
 };
 
 static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc,
@@ -124,7 +172,8 @@ static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc,
 
 #ifdef CONFIG_SYS_LONGHELP
 static char clk_help_text[] =
-   "dump - Print clock frequencies";
+   "dump - Print clock frequencies\n"
+   "setfreq [clk] [freq] - Set clock frequency";
 #endif
 
-U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text);
+U_BOOT_CMD(clk, 4, 1, do_clk, "CLK sub-system", clk_help_text);
-- 
2.17.1

[PATCHv6 07/26] clk: do not attempt to fetch clock pointer with null device

[Tero Kristo]

From: Tero Kristo 

Bail out early if device returned for the parent clock is null.
This avoids warning prints like this when doing clk dump:

  dev_get_uclass_priv: null device

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/clk-uclass.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 53e7be764d..451d7da001 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -502,6 +502,8 @@ struct clk *clk_get_parent(struct clk *clk)
return NULL;
 
pdev = dev_get_parent(clk->dev);
+   if (!pdev)
+   return ERR_PTR(-ENODEV);
pclk = dev_get_clk_ptr(pdev);
if (!pclk)
return ERR_PTR(-ENODEV);
-- 
2.17.1

[PATCHv6 05/26] clk: fixed_rate: add API for directly registering fixed rate clocks

[Tero Kristo]

From: Tero Kristo 

Current driver only supports registering fixed rate clocks from DT. Add
new API which makes it possible to register fixed rate clocks directly
from e.g. platform specific clock drivers.

Reviewed-by: Peng Fan 
Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/clk_fixed_rate.c | 45 
 include/linux/clk-provider.h |  3 +++
 2 files changed, 48 insertions(+)

diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 09f9ef26a4..325a9b2dcf 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -9,6 +9,9 @@
 #include 
 #include 
 
+#define UBOOT_DM_CLK_FIXED_RATE "fixed_rate_clock"
+#define UBOOT_DM_CLK_FIXED_RATE_RAW "fixed_rate_raw_clock"
+
 static ulong clk_fixed_rate_get_rate(struct clk *clk)
 {
return to_clk_fixed_rate(clk->dev)->fixed_rate;
@@ -40,6 +43,15 @@ void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev,
clk->enable_count = 0;
 }
 
+static ulong clk_fixed_rate_raw_get_rate(struct clk *clk)
+{
+   return container_of(clk, struct clk_fixed_rate, clk)->fixed_rate;
+}
+
+const struct clk_ops clk_fixed_rate_raw_ops = {
+   .get_rate = clk_fixed_rate_raw_get_rate,
+};
+
 static int clk_fixed_rate_of_to_plat(struct udevice *dev)
 {
clk_fixed_rate_ofdata_to_plat_(dev, to_clk_fixed_rate(dev));
@@ -47,6 +59,32 @@ static int clk_fixed_rate_of_to_plat(struct udevice *dev)
return 0;
 }
 
+#if CONFIG_IS_ENABLED(CLK_CCF)
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+   ulong rate)
+{
+   struct clk *clk;
+   struct clk_fixed_rate *fixed;
+   int ret;
+
+   fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
+   if (!fixed)
+   return ERR_PTR(-ENOMEM);
+
+   fixed->fixed_rate = rate;
+
+   clk = >clk;
+
+   ret = clk_register(clk, UBOOT_DM_CLK_FIXED_RATE_RAW, name, NULL);
+   if (ret) {
+   kfree(fixed);
+   return ERR_PTR(ret);
+   }
+
+   return clk;
+}
+#endif
+
 static const struct udevice_id clk_fixed_rate_match[] = {
{
.compatible = "fixed-clock",
@@ -63,3 +101,10 @@ U_BOOT_DRIVER(fixed_clock) = {
.ops = _fixed_rate_ops,
.flags = DM_FLAG_PRE_RELOC,
 };
+
+U_BOOT_DRIVER(clk_fixed_rate_raw) = {
+   .name = UBOOT_DM_CLK_FIXED_RATE_RAW,
+   .id = UCLASS_CLK,
+   .ops = _fixed_rate_raw_ops,
+   .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 6fda14f5fe..9d296f240a 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -247,6 +247,9 @@ struct clk *clk_register_mux(struct device *dev, const char 
*name,
void __iomem *reg, u8 shift, u8 width,
u8 clk_mux_flags);
 
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+   ulong rate);
+
 const char *clk_hw_get_name(const struct clk *hw);
 ulong clk_generic_get_rate(struct clk *clk);
 
-- 
2.17.1

[PATCHv6 06/26] clk: fix clock tree dump to properly dump out every registered clock

[Tero Kristo]

From: Tero Kristo 

Some clocks are not associated to a DM node, so just parsing the DM is not
enough. This is especially true for root clocks, which typically don't have
any parents. Instead, fetch every registered UCLASS_CLK instance, and dump
these out.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 cmd/clk.c | 27 +++
 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/cmd/clk.c b/cmd/clk.c
index e3c3d2f9bb..0245b97136 100644
--- a/cmd/clk.c
+++ b/cmd/clk.c
@@ -18,11 +18,14 @@ static void show_clks(struct udevice *dev, int depth, int 
last_flag)
 {
int i, is_last;
struct udevice *child;
-   struct clk *clkp;
+   struct clk *clkp, *parent;
u32 rate;
 
clkp = dev_get_clk_ptr(dev);
if (device_get_uclass_id(dev) == UCLASS_CLK && clkp) {
+   parent = clk_get_parent(clkp);
+   if (!IS_ERR(parent) && depth == -1)
+   return;
depth++;
rate = clk_get_rate(clkp);
 
@@ -47,6 +50,9 @@ static void show_clks(struct udevice *dev, int depth, int 
last_flag)
}
 
list_for_each_entry(child, >child_head, sibling_node) {
+   if (child == dev)
+   continue;
+
is_last = list_is_last(>sibling_node, >child_head);
show_clks(child, depth, (last_flag << 1) | is_last);
}
@@ -54,14 +60,19 @@ static void show_clks(struct udevice *dev, int depth, int 
last_flag)
 
 int __weak soc_clk_dump(void)
 {
-   struct udevice *root;
+   struct udevice *dev;
+   struct uclass *uc;
+   int ret;
 
-   root = dm_root();
-   if (root) {
-   printf(" Rate   Usecnt  Name\n");
-   printf("--\n");
-   show_clks(root, -1, 0);
-   }
+   ret = uclass_get(UCLASS_CLK, );
+   if (ret)
+   return ret;
+
+   printf(" Rate   Usecnt  Name\n");
+   printf("--\n");
+
+   uclass_foreach_dev(dev, uc)
+   show_clks(dev, -1, 0);
 
return 0;
 }
-- 
2.17.1

[PATCHv6 04/26] common: fit: Update board_fit_image_post_process() to pass fit and node_offset

[Tero Kristo]

From: Lokesh Vutla 

board_fit_image_post_process() passes only start and size of the image,
but type of the image is not passed. So pass fit and node_offset, to
derive information about image to be processed.

Signed-off-by: Lokesh Vutla 
Reviewed-by: Tom Rini 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/security.c   | 3 ++-
 arch/arm/mach-keystone/mon.c  | 3 ++-
 arch/arm/mach-socfpga/board.c | 3 ++-
 board/ti/am335x/board.c   | 3 ++-
 board/ti/am43xx/board.c   | 3 ++-
 board/ti/am57xx/board.c   | 3 ++-
 board/ti/dra7xx/evm.c | 3 ++-
 common/image-fit.c| 2 +-
 common/spl/spl_fit.c  | 2 +-
 include/image.h   | 5 -
 10 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c
index 66f90a5a34..5b5ff9ba7b 100644
--- a/arch/arm/mach-k3/security.c
+++ b/arch/arm/mach-k3/security.c
@@ -18,7 +18,8 @@
 #include 
 #include 
 
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
 {
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
struct ti_sci_proc_ops *proc_ops = _sci->ops.proc_ops;
diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c
index 58995d73ac..b863bab196 100644
--- a/arch/arm/mach-keystone/mon.c
+++ b/arch/arm/mach-keystone/mon.c
@@ -103,7 +103,8 @@ static int k2_hs_bm_auth(int cmd, void *arg1)
return  result;
 }
 
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
 {
int result = 0;
void *image = *p_image;
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 650122fcd4..36eecdc057 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -103,7 +103,8 @@ __weak int board_fit_config_name_match(const char *name)
 #endif
 
 #if IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS)
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
 {
if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH)) {
if (socfpga_vendor_authentication(p_image, p_size))
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 5959ff73dc..5c156a5d1d 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -960,7 +960,8 @@ int board_fit_config_name_match(const char *name)
 #endif
 
 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
 {
secure_boot_verify_image(p_image, p_size);
 }
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index e9febb9592..a71b588efc 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -896,7 +896,8 @@ int embedded_dtb_select(void)
 #endif
 
 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
 {
secure_boot_verify_image(p_image, p_size);
 }
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 05c26c74d9..399a2e5d91 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -1199,7 +1199,8 @@ static int board_bootmode_has_emmc(void)
 #endif
 
 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
 {
secure_boot_verify_image(p_image, p_size);
 }
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 05f251f778..23e8005991 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -1065,7 +1065,8 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason 
reason)
 #endif
 
 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
 {
secure_boot_verify_image(p_image, p_size);
 }
diff --git a/common/image-fit.c b/common/image-fit.c
index e614643fe3..0c5a05948d 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -2143,7 +2143,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
 
/* perform any post-processing on the image data */
if (!host_build() && IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS))
-   board_fit_image_post_process(, );
+   board_fit_image_post_process(f

[PATCHv6 03/26] remoteproc: k3-r5: remove sysfw PM calls if not supported

[Tero Kristo]

From: Tero Kristo 

With the sysfw rearch, sysfw PM calls are no longer available from SPL
level. To properly support this, remove the is_on checks and the reset
assertion from the R5 remoteproc driver as these are not supported.
Attempting to access unavailable services will cause the device to hang.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/remoteproc/ti_k3_r5f_rproc.c | 30 ++--
 1 file changed, 19 insertions(+), 11 deletions(-)

diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c 
b/drivers/remoteproc/ti_k3_r5f_rproc.c
index 3c569a3b7b..6f3e12d915 100644
--- a/drivers/remoteproc/ti_k3_r5f_rproc.c
+++ b/drivers/remoteproc/ti_k3_r5f_rproc.c
@@ -804,19 +804,27 @@ static int k3_r5f_probe(struct udevice *dev)
return ret;
}
 
-   ret = core->tsp.sci->ops.dev_ops.is_on(core->tsp.sci, core->tsp.dev_id,
-  _state, >in_use);
-   if (ret)
-   return ret;
+   /*
+* The PM functionality is not supported by the firmware during
+* SPL execution with the separated DM firmware image. The following
+* piece of code is not compiled in that case.
+*/
+   if (!IS_ENABLED(CONFIG_K3_DM_FW)) {
+   ret = core->tsp.sci->ops.dev_ops.is_on(core->tsp.sci,
+  core->tsp.dev_id,
+  _state, >in_use);
+   if (ret)
+   return ret;
 
-   if (core->in_use) {
-   dev_info(dev, "Core %d is already in use. No rproc commands 
work\n",
-core->tsp.proc_id);
-   return 0;
-   }
+   if (core->in_use) {
+   dev_info(dev, "Core %d is already in use. No rproc 
commands work\n",
+core->tsp.proc_id);
+   return 0;
+   }
 
-   /* Make sure Local reset is asserted. Redundant? */
-   reset_assert(>reset);
+   /* Make sure Local reset is asserted. Redundant? */
+   reset_assert(>reset);
+   }
 
ret = k3_r5f_rproc_configure(core);
if (ret) {
-- 
2.17.1

[PATCHv6 02/26] arm: mach-k3: introduce new config option for sysfw split

[Tero Kristo]

From: Tero Kristo 

On J7 family of SoCs (J721E and J7200), sysfw is being split to be run
under two cores, TIFS portion on DMSC core, and DM firmware under MCU
R5. As MCU R5 is also used to run one phase of the bootloader, we must
prevent access from here towards sysfw services. To support this, add
new config option which can be used to detect presence of RM/PM sysfw
services.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/Kconfig | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 21b2fc2230..fa8d134b42 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -154,6 +154,17 @@ config K3_ATF_LOAD_ADDR
  The load address for the ATF image. This value defaults to 0x7000
  if not provided in the board defconfig file.
 
+config K3_DM_FW
+   bool "Separate DM firmware image"
+   depends on SPL && CPU_V7R && SOC_K3_J721E && !CLK_TI_SCI && 
!TI_SCI_POWER_DOMAIN
+   default y
+   help
+ Enabling this will indicate that the system has separate DM
+ and TIFS firmware images in place, instead of a single SYSFW
+ firmware. Due to DM being executed on the same core as R5 SPL
+ bootloader, it makes RM and PM services not being available
+ during R5 SPL execution time.
+
 source "board/ti/am65x/Kconfig"
 source "board/ti/am64x/Kconfig"
 source "board/ti/j721e/Kconfig"
-- 
2.17.1

[PATCHv6 01/26] lib: rational: copy the rational fraction lib routines from Linux

[Tero Kristo]

From: Tero Kristo 

Copy the best rational approximation calculation routines from Linux.
Typical usecase for these routines is to calculate the M/N divider
values for PLLs to reach a specific clock rate.

This is based on linux kernel commit:
"lib/math/rational.c: fix possible incorrect result from rational
fractions helper"
(sha1: 323dd2c3ed0641f49e89b4e420f9eef5d3d5a881)

Signed-off-by: Tero Kristo 
Reviewed-by: Tom Rini 
Signed-off-by: Tero Kristo 
---
 include/linux/rational.h | 20 
 lib/Kconfig  |  7 +++
 lib/Makefile |  2 +
 lib/rational.c   | 99 
 4 files changed, 128 insertions(+)
 create mode 100644 include/linux/rational.h
 create mode 100644 lib/rational.c

diff --git a/include/linux/rational.h b/include/linux/rational.h
new file mode 100644
index 00..33f5f5fc3e
--- /dev/null
+++ b/include/linux/rational.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * rational fractions
+ *
+ * Copyright (C) 2009 emlix GmbH, Oskar Schirmer 
+ *
+ * helper functions when coping with rational numbers,
+ * e.g. when calculating optimum numerator/denominator pairs for
+ * pll configuration taking into account restricted register size
+ */
+
+#ifndef _LINUX_RATIONAL_H
+#define _LINUX_RATIONAL_H
+
+void rational_best_approximation(
+   unsigned long given_numerator, unsigned long given_denominator,
+   unsigned long max_numerator, unsigned long max_denominator,
+   unsigned long *best_numerator, unsigned long *best_denominator);
+
+#endif /* _LINUX_RATIONAL_H */
diff --git a/lib/Kconfig b/lib/Kconfig
index 15019d2c65..ad0cd52edd 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -674,6 +674,13 @@ config GENERATE_SMBIOS_TABLE
  See also SMBIOS_SYSINFO which allows SMBIOS values to be provided in
  the devicetree.
 
+config LIB_RATIONAL
+   bool "enable continued fraction calculation routines"
+
+config SPL_LIB_RATIONAL
+   bool "enable continued fraction calculation routines for SPL"
+   depends on SPL
+
 endmenu
 
 config ASN1_COMPILER
diff --git a/lib/Makefile b/lib/Makefile
index b4795a62a0..881034f4ae 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -73,6 +73,8 @@ obj-$(CONFIG_$(SPL_)LZO) += lzo/
 obj-$(CONFIG_$(SPL_)LZMA) += lzma/
 obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o
 
+obj-$(CONFIG_$(SPL_)LIB_RATIONAL) += rational.o
+
 obj-$(CONFIG_LIBAVB) += libavb/
 
 obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/
diff --git a/lib/rational.c b/lib/rational.c
new file mode 100644
index 00..316db3b590
--- /dev/null
+++ b/lib/rational.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * rational fractions
+ *
+ * Copyright (C) 2009 emlix GmbH, Oskar Schirmer 
+ * Copyright (C) 2019 Trent Piepho 
+ *
+ * helper functions when coping with rational numbers
+ */
+
+#include 
+#include 
+#include 
+
+/*
+ * calculate best rational approximation for a given fraction
+ * taking into account restricted register size, e.g. to find
+ * appropriate values for a pll with 5 bit denominator and
+ * 8 bit numerator register fields, trying to set up with a
+ * frequency ratio of 3.1415, one would say:
+ *
+ * rational_best_approximation(31415, 1,
+ * (1 << 8) - 1, (1 << 5) - 1, , );
+ *
+ * you may look at given_numerator as a fixed point number,
+ * with the fractional part size described in given_denominator.
+ *
+ * for theoretical background, see:
+ * http://en.wikipedia.org/wiki/Continued_fraction
+ */
+
+void rational_best_approximation(
+   unsigned long given_numerator, unsigned long given_denominator,
+   unsigned long max_numerator, unsigned long max_denominator,
+   unsigned long *best_numerator, unsigned long *best_denominator)
+{
+   /* n/d is the starting rational, which is continually
+* decreased each iteration using the Euclidean algorithm.
+*
+* dp is the value of d from the prior iteration.
+*
+* n2/d2, n1/d1, and n0/d0 are our successively more accurate
+* approximations of the rational.  They are, respectively,
+* the current, previous, and two prior iterations of it.
+*
+* a is current term of the continued fraction.
+*/
+   unsigned long n, d, n0, d0, n1, d1, n2, d2;
+   n = given_numerator;
+   d = given_denominator;
+   n0 = d1 = 0;
+   n1 = d0 = 1;
+
+   for (;;) {
+   unsigned long dp, a;
+
+   if (d == 0)
+   break;
+   /* Find next term in continued fraction, 'a', via
+* Euclidean algorithm.
+*/
+   dp = d;
+   a = n / d;
+   d = n % d;
+   n = dp;
+
+   /* Calculate the current rational approximation (aka
+* convergent), n2/d2, using the term just found and
+* the two prior approximations.
+ 

[PATCHv6 00/26] HSM rearch series for TI K3 devices

[Tero Kristo]

Hello,

One more post, this time with the #ifdef hackery converted to use the
IS_ENABLED / CONFIG_IS_ENABLED macros, and also removed the "common.h"
include from k3-clk.h header. This version also contains fixes to any
build issues reported by Lokesh, and these are squashed in to relevant
patches.

-Tero

Re: [GIT PULL] TI changes for v2021.10 next

[Tero Kristo]

On 10/06/2021 18:33, Lokesh Vutla wrote:

+Tero,

On 10/06/21 8:55 pm, Tom Rini wrote:

On Thu, Jun 10, 2021 at 12:16:50PM +0530, Lokesh Vutla wrote:


Hi Tom,
Please find the PR for master branch targeted for v2021.10-next branch.
Details about the PR are updated in the tag message.

Gitlab CI report: 
https://source.denx.de/u-boot/custodians/u-boot-ti/-/pipelines/7780


The following changes since commit e8f720ee1707b43a0e14ade87b40a1f84baeb2f3:

   Merge branch '2021-06-08-kconfig-migrations' into next (2021-06-09 08:19:13 
-0400)

are available in the Git repository at:

   https://source.denx.de/u-boot/custodians/u-boot-ti.git tags/ti-v2021.10-next

for you to fetch changes up to 47a10af8f8a90b3d9e83fafb51372800171344a9:

   dma: ti: k3-udma: Add support for native configuration of chan/flow 
(2021-06-09 22:23:45 +0530)



NAK:
ERROR: Avoid including common.h and dm.h in header files
#437: FILE: include/k3-clk.h:10:
+#include 


Interesting, I could not see this issue



And while you're in there, there's a number of:
WARNING: Use 'if (IS_ENABLED(CONFIG...))' instead of '#if or #ifdef' where 
possible
#53: FILE: drivers/clk/clk_fixed_rate.c:62:
+#if defined(CONFIG_CLK_CCF) || defined(CONFIG_SPL_CLK_CCF)

Where checkpatch is warning about the wrong thing, that should be
CONFIG_IS_ENABLED(CLK_CCF) at minimum and then see if we can use
if (...) instead.



Tero,
Can you fix it and re-post?


Yeah, I can take a look at these tomorrow.

-Tero



Thanks and regards,
Lokesh

Re: [PATCHv5 04/26] common: fit: Update board_fit_image_post_process() to pass fit and node_offset

[Tero Kristo]

Hi,

There is apparently a build failure with ARM socfpga board, the change 
below fixes it and should be squashed to the original patch:


diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 650122fcd4..36eecdc057 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -103,7 +103,8 @@ __weak int board_fit_config_name_match(const char *name)
 #endif

 #if IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS)
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void 
**p_image,

+ size_t *p_size)
 {
if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH)) {
if (socfpga_vendor_authentication(p_image, p_size))
--


-Tero

On 03/06/2021 09:32, Tero Kristo wrote:

From: Lokesh Vutla 

board_fit_image_post_process() passes only start and size of the image,
but type of the image is not passed. So pass fit and node_offset, to
derive information about image to be processed.

Signed-off-by: Lokesh Vutla 
Reviewed-by: Tom Rini 
Signed-off-by: Tero Kristo 
---
  arch/arm/mach-k3/security.c  | 3 ++-
  arch/arm/mach-keystone/mon.c | 3 ++-
  board/ti/am335x/board.c  | 3 ++-
  board/ti/am43xx/board.c  | 3 ++-
  board/ti/am57xx/board.c  | 3 ++-
  board/ti/dra7xx/evm.c| 3 ++-
  common/image-fit.c   | 2 +-
  common/spl/spl_fit.c | 2 +-
  include/image.h  | 5 -
  9 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c
index 66f90a5a34..5b5ff9ba7b 100644
--- a/arch/arm/mach-k3/security.c
+++ b/arch/arm/mach-k3/security.c
@@ -18,7 +18,8 @@
  #include 
  #include 
  
-void board_fit_image_post_process(void **p_image, size_t *p_size)

+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
  {
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
struct ti_sci_proc_ops *proc_ops = _sci->ops.proc_ops;
diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c
index 58995d73ac..b863bab196 100644
--- a/arch/arm/mach-keystone/mon.c
+++ b/arch/arm/mach-keystone/mon.c
@@ -103,7 +103,8 @@ static int k2_hs_bm_auth(int cmd, void *arg1)
return  result;
  }
  
-void board_fit_image_post_process(void **p_image, size_t *p_size)

+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
  {
int result = 0;
void *image = *p_image;
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 5959ff73dc..5c156a5d1d 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -960,7 +960,8 @@ int board_fit_config_name_match(const char *name)
  #endif
  
  #ifdef CONFIG_TI_SECURE_DEVICE

-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
  {
secure_boot_verify_image(p_image, p_size);
  }
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index e9febb9592..a71b588efc 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -896,7 +896,8 @@ int embedded_dtb_select(void)
  #endif
  
  #ifdef CONFIG_TI_SECURE_DEVICE

-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
  {
secure_boot_verify_image(p_image, p_size);
  }
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 05c26c74d9..399a2e5d91 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -1199,7 +1199,8 @@ static int board_bootmode_has_emmc(void)
  #endif
  
  #ifdef CONFIG_TI_SECURE_DEVICE

-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
  {
secure_boot_verify_image(p_image, p_size);
  }
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 05f251f778..23e8005991 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -1065,7 +1065,8 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason 
reason)
  #endif
  
  #ifdef CONFIG_TI_SECURE_DEVICE

-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
  {
secure_boot_verify_image(p_image, p_size);
  }
diff --git a/common/image-fit.c b/common/image-fit.c
index e614643fe3..0c5a05948d 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -2143,7 +2143,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
  
  	/* perform any post-processing on the image d

Re: [PATCHv5 00/26] Re-base / re-post of TI-K3 HSM rearch series

[Tero Kristo]

On 08/06/2021 09:32, Lokesh Vutla wrote:



On 08/06/21 11:57 am, Tero Kristo wrote:

On 07/06/2021 14:22, Lokesh Vutla wrote:



On 03/06/21 12:02 pm, Tero Kristo wrote:

Hi,

As requested, this is just a rebase to the latest u-boot tip.

Boot tested on j721e to make sure nothing got broken.


There are some build errors. Can you take a look?
https://source.denx.de/u-boot/custodians/u-boot-ti/-/jobs/275511


Hmm yeah, HS boards fail building. Attached fix, do you want me to re-post or do
you want to squash this in?


Can you point me to the patch no to squash this patch?


Goes on top of patch #18. Rest apply cleanly.

-Tero

Re: [PATCHv5 00/26] Re-base / re-post of TI-K3 HSM rearch series

[Tero Kristo]

On 07/06/2021 14:22, Lokesh Vutla wrote:



On 03/06/21 12:02 pm, Tero Kristo wrote:

Hi,

As requested, this is just a rebase to the latest u-boot tip.

Boot tested on j721e to make sure nothing got broken.


There are some build errors. Can you take a look?
https://source.denx.de/u-boot/custodians/u-boot-ti/-/jobs/275511


Hmm yeah, HS boards fail building. Attached fix, do you want me to 
re-post or do you want to squash this in?


-Tero
>From 037fcddc5ee6581988cc70e84395bc5f1b279724 Mon Sep 17 00:00:00 2001
From: Tero Kristo 
Date: Tue, 8 Jun 2021 09:05:59 +0300
Subject: [PATCH] arm: mach-k3: compile fix for HS boards

Fix compile error introduced by HSM rearch for HS boards.

Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/common.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 2b8c09a650..5079b390ba 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -266,6 +266,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 void board_fit_image_post_process(const void *fit, int node, void **p_image,
   size_t *p_size)
 {
+#ifdef CONFIG_SYS_K3_SPL_ATF
 	int len;
 	int i;
 	const char *os;
@@ -285,6 +286,7 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image,
 			break;
 		}
 	}
+#endif
 
 #ifdef CONFIG_TI_SECURE_DEVICE
 	ti_secure_image_post_process(p_image, p_size);
-- 
2.17.1

[PATCHv5 17/26] arm: mach-k3: Add platform data for j721e and j7200

[Tero Kristo]

From: Dave Gerlach 

Add platform clock and powerdomain data for J721e and J7200. This data
is used by the corresponding drivers to register all the required device
clocks and powerdomains.

Signed-off-by: Dave Gerlach 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/Makefile |   2 +-
 arch/arm/mach-k3/j7200/Makefile   |   5 +
 arch/arm/mach-k3/j7200/clk-data.c | 547 +
 arch/arm/mach-k3/j7200/dev-data.c |  77 +++
 arch/arm/mach-k3/j721e/Makefile   |   5 +
 arch/arm/mach-k3/j721e/clk-data.c | 781 ++
 arch/arm/mach-k3/j721e/dev-data.c |  75 +++
 7 files changed, 1491 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-k3/j7200/Makefile
 create mode 100644 arch/arm/mach-k3/j7200/clk-data.c
 create mode 100644 arch/arm/mach-k3/j7200/dev-data.c
 create mode 100644 arch/arm/mach-k3/j721e/Makefile
 create mode 100644 arch/arm/mach-k3/j721e/clk-data.c
 create mode 100644 arch/arm/mach-k3/j721e/dev-data.c

diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 890d1498d0..47cf7b6d17 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -4,7 +4,7 @@
 #  Lokesh Vutla 
 
 obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
-obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
+obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
 obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
 obj-$(CONFIG_ARM64) += arm64-mmu.o
 obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
diff --git a/arch/arm/mach-k3/j7200/Makefile b/arch/arm/mach-k3/j7200/Makefile
new file mode 100644
index 00..ff9abd78ea
--- /dev/null
+++ b/arch/arm/mach-k3/j7200/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/j7200/clk-data.c 
b/arch/arm/mach-k3/j7200/clk-data.c
new file mode 100644
index 00..93c067079a
--- /dev/null
+++ b/arch/arm/mach-k3/j7200/clk-data.c
@@ -0,0 +1,547 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J7200 specific clock platform data
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+   "osc_19_2_mhz",
+   "osc_20_mhz",
+   "osc_24_mhz",
+   "osc_25_mhz",
+   "osc_26_mhz",
+   "osc_27_mhz",
+};
+
+static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
+   "board_0_mcu_ospi0_dqs_out",
+   "fss_mcu_0_ospi_0_ospi_oclk_clk",
+};
+
+static const char * const wkup_fref_clksel_out0_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const main_pll_hfosc_sel_out1_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "board_0_hfosc1_clk_out",
+};
+
+static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
+   "wkup_fref_clksel_out0",
+   "hsdiv1_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
+   "hsdiv4_16fft_mcu_1_hsdivout4_clk",
+   "hsdiv4_16fft_mcu_2_hsdivout4_clk",
+};
+
+static const char * const mcuusart_clk_sel_out0_parents[] = {
+   "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+   "postdiv2_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_gpio0_clksel_out0_parents[] = {
+   "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+   "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+   "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
+   "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = {
+   "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+   "gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out0_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out12_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out14_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out2_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out3_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out4_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "b

[PATCHv5 25/26] board: ti: j72xx: README: update build instructions and image formats

[Tero Kristo]

From: Tero Kristo 

Update build instructions and image formats based on HSM rearch. A new
DM image is added into the build, which gets executed right after R5
SPL finishes its job.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 board/ti/j721e/README | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/board/ti/j721e/README b/board/ti/j721e/README
index c33afa496e..b1c9145c92 100644
--- a/board/ti/j721e/README
+++ b/board/ti/j721e/README
@@ -73,12 +73,12 @@ support. Below is the pictorial representation of boot flow:
 || | |   +-+ |   | 
  |
 || |<|---| Start A72   | |   | 
  |
 || | |   | and jump to | |   | 
  |
-|| | |   | next image  | |   | 
  |
+|| | |   | DM fw image | |   | 
  |
 || | |   +-+ |   | 
  |
 || | |   | +---+ | 
  |
 || |-|---|>| Reset rls | | 
  |
 || | |   | +---+ | 
  |
-||  DMSC   | |   |  :| 
  |
+||  TIFS   | |   |  :| 
  |
 ||Services | |   | +---+ | 
  |
 || |<|---|>|*ATF/OPTEE*| | 
  |
 || | |   | +---+ | 
  |
@@ -154,7 +154,7 @@ $ make CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5
 
 4.2. A72:
 $ make CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=/tmp/a72
-$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin O=/tmp/a72
+$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin DM= 
O=/tmp/a72
 
 Target Images
 --
@@ -197,6 +197,9 @@ Image formats:
 | | A72 OPTEE | |
 | +---+ |
 | |   | |
+| |  R5 DM FW | |
+| +---+ |
+| |   | |
 | |  A72 SPL  | |
 | +---+ |
 | |   | |
-- 
2.17.1

[PATCHv5 26/26] arm: dts: k3-j72xx: correct MCU timer1 frequency

[Tero Kristo]

MCU timer1 is used as the tick timer for MCU R5 SPL, and the
clock-frequency defined in DT appears to be incorrect at the moment.
Actual clock source for the timer is MCU_SYSCLK0 / 4 which is 250MHz.

Earlier setup of 25MHz went unnoticed, as there was a separate issue
with omap-timer, which caused an error to the clock by a factor of 8
with j7 devices. This problem surfaced once the omap-timer was fixed.

Signed-off-by: Tero Kristo 
---
 arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 2 +-
 arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi 
b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index bd037be350..c3aae65b39 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -33,7 +33,7 @@
compatible = "ti,omap5430-timer";
reg = <0x0 0x4040 0x0 0x80>;
ti,timer-alwon;
-   clock-frequency = <2500>;
+   clock-frequency = <25000>;
u-boot,dm-spl;
};
 
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi 
b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index fe095a6153..951331831e 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -46,7 +46,7 @@
compatible = "ti,omap5430-timer";
reg = <0x0 0x4040 0x0 0x80>;
ti,timer-alwon;
-   clock-frequency = <2500>;
+   clock-frequency = <25000>;
u-boot,dm-spl;
};
 
-- 
2.17.1

[PATCHv5 24/26] configs: j7200_evm_r5: Enable raw access power management features

[Tero Kristo]

From: Dave Gerlach 

Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.

Signed-off-by: Dave Gerlach 
Signed-off-by: Tero Kristo 
---
 configs/j7200_evm_r5_defconfig | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index 08fad3e04b..5c51bd5ae7 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -75,7 +75,7 @@ CONFIG_SPL_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
+# CONFIG_CLK_TI_SCI is not set
 CONFIG_DMA_CHANNELS=y
 CONFIG_TI_K3_NAVSS_UDMA=y
 CONFIG_TI_SCI_PROTOCOL=y
@@ -110,7 +110,7 @@ CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_GENERIC is not set
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
+# CONFIG_TI_SCI_POWER_DOMAIN is not set
 CONFIG_K3_SYSTEM_CONTROLLER=y
 CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_DM_RESET=y
@@ -142,3 +142,13 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x6164
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_K3_DM_FW=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
-- 
2.17.1

[PATCHv5 22/26] arm: mach-k3: j721e_init: Force early probe of clk-k3 driver

[Tero Kristo]

From: Dave Gerlach 

Force the clk-k3 driver to probe early during R5 SPL boot to ensure the
default system clock configuration is completed. Many other drivers
assume a default state of the clock tree and it is currently possible
for them to probe before clk-k3 depending on the exact system
configuration.

Signed-off-by: Dave Gerlach 
Reported-by: Keerthy 
Tested-by: Keerthy 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/j721e_init.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 76a04a9035..833568d4b8 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -180,6 +180,18 @@ void board_init_f(ulong dummy)
k3_sysfw_loader(is_rom_loaded_sysfw(),
k3_mmc_stop_clock, k3_mmc_restart_clock);
 
+#ifdef CONFIG_SPL_CLK_K3
+   /*
+* Force probe of clk_k3 driver here to ensure basic default clock
+* configuration is always done.
+*/
+   ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(ti_clk),
+ );
+   if (ret)
+   panic("Failed to initialize clk-k3!\n");
+#endif
+
/* Prepare console output */
preloader_console_init();
 
-- 
2.17.1

[PATCHv5 23/26] configs: j721e_evm_r5: Enable raw access power management features

[Tero Kristo]

From: Tero Kristo 

Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 configs/j721e_evm_r5_defconfig | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 8ebbe7348f..8a9b20141b 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -72,7 +72,7 @@ CONFIG_SPL_REGMAP=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
+# CONFIG_CLK_TI_SCI is not set
 CONFIG_DMA_CHANNELS=y
 CONFIG_TI_K3_NAVSS_UDMA=y
 CONFIG_TI_SCI_PROTOCOL=y
@@ -102,7 +102,7 @@ CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_GENERIC is not set
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
+# CONFIG_TI_SCI_POWER_DOMAIN is not set
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_TPS65941=y
 CONFIG_DM_REGULATOR=y
@@ -140,3 +140,11 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x6163
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_K3_DM_FW=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
-- 
2.17.1

[PATCHv5 21/26] arm: mach-k3: sysfw-loader: pass boardcfg to sciserver

[Tero Kristo]

From: Tero Kristo 

Copy the contents of the board config loaded from sysfw.itb into an
EXTBOOT shared memory buffer that gets passed to sciserver. This only
needs to be done if EXTBOOT area has not been populated by ROM code yet.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/sysfw-loader.c | 103 
 1 file changed, 103 insertions(+)

diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index c6af205163..ac719cd46f 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -40,6 +40,46 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 #define K3_SYSTEM_CONTROLLER_RPROC_ID  0
 
+#define COMMON_HEADER_ADDRESS  0x41cffb00
+#define BOARDCFG_ADDRESS   0x41c8
+
+#define COMP_TYPE_SBL_DATA 0x11
+#define DESC_TYPE_BOARDCFG_PM_INDEX0x2
+#define DESC_TYPE_BOARDCFG_RM_INDEX0x3
+
+#define BOARD_CONFIG_RM_DESC_TYPE  0x000c
+#define BOARD_CONFIG_PM_DESC_TYPE  0x000e
+
+struct extboot_comp {
+   u32 comp_type;
+   u32 boot_core;
+   u32 comp_opts;
+   u64 dest_addr;
+   u32 comp_size;
+};
+
+struct extboot_header {
+   u8 magic[8];
+   u32 num_comps;
+   struct extboot_comp comps[5];
+   u32 reserved;
+};
+
+struct bcfg_desc {
+   u16 type;
+   u16 offset;
+   u16 size;
+   u8 devgrp;
+   u8 reserved;
+} __packed;
+
+struct bcfg_header {
+   u8 num_elems;
+   u8 sw_rev;
+   struct bcfg_desc descs[4];
+   u16 reserved;
+} __packed;
+
 static bool sysfw_loaded;
 static void *sysfw_load_address;
 
@@ -131,6 +171,15 @@ static void k3_sysfw_configure_using_fit(void *fit,
const void *cfg_fragment_addr;
size_t cfg_fragment_size;
int ret;
+#ifdef CONFIG_K3_DM_FW
+   u8 *buf;
+   struct extboot_header *common_header;
+   struct bcfg_header *bcfg_header;
+   struct extboot_comp *comp;
+   struct bcfg_desc *desc;
+   u32 addr;
+   bool copy_bcfg = false;
+#endif
 
/* Find the node holding the images information */
images = fdt_path_offset(fit, FIT_IMAGES_PATH);
@@ -165,6 +214,46 @@ static void k3_sysfw_configure_using_fit(void *fit,
 (u32)cfg_fragment_size);
if (ret)
panic("Failed to set board PM configuration (%d)\n", ret);
+#else
+   /* Initialize shared memory boardconfig buffer */
+   buf = (u8 *)COMMON_HEADER_ADDRESS;
+   common_header = (struct extboot_header *)buf;
+
+   /* Check if we have a struct populated by ROM in memory already */
+   if (strcmp((char *)common_header->magic, "EXTBOOT"))
+   copy_bcfg = true;
+
+   if (copy_bcfg) {
+   strcpy((char *)common_header->magic, "EXTBOOT");
+   common_header->num_comps = 1;
+
+   comp = _header->comps[0];
+
+   comp->comp_type = COMP_TYPE_SBL_DATA;
+   comp->boot_core = 0x10;
+   comp->comp_opts = 0;
+   addr = (u32)BOARDCFG_ADDRESS;
+   comp->dest_addr = addr;
+   comp->comp_size = sizeof(*bcfg_header);
+
+   bcfg_header = (struct bcfg_header *)addr;
+
+   bcfg_header->num_elems = 2;
+   bcfg_header->sw_rev = 0;
+
+   desc = _header->descs[0];
+
+   desc->type = BOARD_CONFIG_PM_DESC_TYPE;
+   desc->offset = sizeof(*bcfg_header);
+   desc->size = cfg_fragment_size;
+   comp->comp_size += desc->size;
+   desc->devgrp = 0;
+   desc->reserved = 0;
+   memcpy((u8 *)bcfg_header + desc->offset, cfg_fragment_addr,
+  cfg_fragment_size);
+
+   bcfg_header->descs[1].offset = desc->offset + desc->size;
+   }
 #endif
 
/* Extract resource management (RM) specific configuration from FIT */
@@ -174,6 +263,20 @@ static void k3_sysfw_configure_using_fit(void *fit,
panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_RM,
  ret);
 
+#ifdef CONFIG_K3_DM_FW
+   if (copy_bcfg) {
+   desc = _header->descs[1];
+
+   desc->type = BOARD_CONFIG_RM_DESC_TYPE;
+   desc->size = cfg_fragment_size;
+   comp->comp_size += desc->size;
+   desc->devgrp = 0;
+   desc->reserved = 0;
+   memcpy((u8 *)bcfg_header + desc->offset, cfg_fragment_addr,
+  cfg_fragment_size);
+   }
+#endif
+
/* Apply resource management (RM) configuration to SYSFW */
ret = board_ops->board_config_rm(ti_sci,
 (u64)(u32)cfg_fragment_addr,
-- 
2.17.1

[PATCHv5 19/26] arm: mach-k3: do board config for PM only if supported

[Tero Kristo]

From: Tero Kristo 

If the raw PM support is built in, we are operating in the split
firmware approach mode where PM support is not available. In this
case, skip the board config for this.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/sysfw-loader.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 0bacfc4d07..c6af205163 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -159,11 +159,13 @@ static void k3_sysfw_configure_using_fit(void *fit,
  ret);
 
/* Apply power/clock (PM) specific configuration to SYSFW */
+#ifndef CONFIG_K3_DM_FW
ret = board_ops->board_config_pm(ti_sci,
 (u64)(u32)cfg_fragment_addr,
 (u32)cfg_fragment_size);
if (ret)
panic("Failed to set board PM configuration (%d)\n", ret);
+#endif
 
/* Extract resource management (RM) specific configuration from FIT */
ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM,
-- 
2.17.1

[PATCHv5 20/26] arm: mach-k3: common: Drop main r5 start

[Tero Kristo]

From: Dave Gerlach 

Only start-up the non-linux remote cores if we are running in legacy
boot mode. HSM rearch is not yet supporting this.

Signed-off-by: Dave Gerlach 
Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/common.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index a5d6a10dc7..2b8c09a650 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -212,11 +212,12 @@ void __noreturn jump_to_image_no_args(struct 
spl_image_info *spl_image)
panic("rproc failed to be initialized (%d)\n", ret);
 
init_env();
-   start_non_linux_remote_cores();
-   if (!fit_image_info[IMAGE_ID_DM_FW].image_start)
+
+   if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
+   start_non_linux_remote_cores();
size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
 );
-
+   }
 
/*
 * It is assumed that remoteproc device 1 is the corresponding
-- 
2.17.1

[PATCHv5 18/26] arm: mach-k3: add support for detecting firmware images from FIT

[Tero Kristo]

From: Tero Kristo 

Add callback routines for parsing the firmware info from FIT image, and
use the data to boot up ATF and the MCU R5 firmware.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/common.c   | 80 +
 arch/arm/mach-k3/common.h   |  1 +
 arch/arm/mach-k3/security.c |  3 +-
 3 files changed, 75 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 9191f686f0..a5d6a10dc7 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -28,6 +28,27 @@
 #include 
 #include 
 
+#ifdef CONFIG_SYS_K3_SPL_ATF
+enum {
+   IMAGE_ID_ATF,
+   IMAGE_ID_OPTEE,
+   IMAGE_ID_SPL,
+   IMAGE_ID_DM_FW,
+   IMAGE_AMT,
+};
+
+#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
+static const char *image_os_match[IMAGE_AMT] = {
+   "arm-trusted-firmware",
+   "tee",
+   "U-Boot",
+   "DM",
+};
+#endif
+
+static struct image_info fit_image_info[IMAGE_AMT];
+#endif
+
 struct ti_sci_handle *get_ti_sci_handle(void)
 {
struct udevice *dev;
@@ -181,7 +202,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info 
*spl_image)
typedef void __noreturn (*image_entry_noargs_t)(void);
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
u32 loadaddr = 0;
-   int ret, size;
+   int ret, size = 0;
 
/* Release all the exclusive devices held by SPL before starting ATF */
ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
@@ -192,15 +213,20 @@ void __noreturn jump_to_image_no_args(struct 
spl_image_info *spl_image)
 
init_env();
start_non_linux_remote_cores();
-   size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
-);
+   if (!fit_image_info[IMAGE_ID_DM_FW].image_start)
+   size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
+);
 
 
/*
 * It is assumed that remoteproc device 1 is the corresponding
 * Cortex-A core which runs ATF. Make sure DT reflects the same.
 */
-   ret = rproc_load(1, spl_image->entry_point, 0x200);
+   if (!fit_image_info[IMAGE_ID_ATF].image_start)
+   fit_image_info[IMAGE_ID_ATF].image_start =
+   spl_image->entry_point;
+
+   ret = rproc_load(1, fit_image_info[IMAGE_ID_ATF].image_start, 0x200);
if (ret)
panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
 
@@ -210,7 +236,8 @@ void __noreturn jump_to_image_no_args(struct spl_image_info 
*spl_image)
ret = rproc_start(1);
if (ret)
panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
-   if (!(size > 0 && valid_elf_image(loadaddr))) {
+   if (!fit_image_info[IMAGE_ID_DM_FW].image_len &&
+   !(size > 0 && valid_elf_image(loadaddr))) {
debug("Shutting down...\n");
release_resources_for_core_shutdown();
 
@@ -218,13 +245,52 @@ void __noreturn jump_to_image_no_args(struct 
spl_image_info *spl_image)
asm volatile("wfe");
}
 
-   image_entry_noargs_t image_entry =
-   (image_entry_noargs_t)load_elf_image_phdr(loadaddr);
+   if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
+   loadaddr = load_elf_image_phdr(loadaddr);
+   } else {
+   loadaddr = fit_image_info[IMAGE_ID_DM_FW].image_start;
+   if (valid_elf_image(loadaddr))
+   loadaddr = load_elf_image_phdr(loadaddr);
+   }
+
+   debug("%s: jumping to address %x\n", __func__, loadaddr);
+
+   image_entry_noargs_t image_entry = (image_entry_noargs_t)loadaddr;
 
image_entry();
 }
 #endif
 
+#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
+{
+   int len;
+   int i;
+   const char *os;
+   u32 addr;
+
+   os = fdt_getprop(fit, node, "os", );
+   addr = fdt_getprop_u32_default_node(fit, node, 0, "entry", -1);
+
+   debug("%s: processing image: addr=%x, size=%d, os=%s\n", __func__,
+ addr, *p_size, os);
+
+   for (i = 0; i < IMAGE_AMT; i++) {
+   if (!strcmp(os, image_os_match[i])) {
+   fit_image_info[i].image_start = addr;
+   fit_image_info[i].image_len = *p_size;
+   debug("%s: matched image for ID %d\n", __func__, i);
+   break;
+   }
+   }
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+   ti_secure_image_post_process(p_image, p_size);
+#endif
+}
+#endif
+
 #if defined(CONFIG_OF_LIBFD

[PATCHv5 16/26] tools: k3_fit_atf: add DM binary to the FIT image

[Tero Kristo]

From: Tero Kristo 

Add DM (device manager) firmware image to the fit image that is loaded by
R5 SPL. This is needed with the HSM rearch where the firmware allocation
has been changed slightly.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/config.mk |  4 
 tools/k3_fit_atf.sh| 19 ++-
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk
index 41fee2b5a1..503ece4520 100644
--- a/arch/arm/mach-k3/config.mk
+++ b/arch/arm/mach-k3/config.mk
@@ -49,6 +49,10 @@ endif
 
 ifdef CONFIG_ARM64
 
+ifeq ($(CONFIG_SOC_K3_J721E),)
+export DM := /dev/null
+endif
+
 ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
 SPL_ITS := u-boot-spl-k3_HS.its
 $(SPL_ITS): export IS_HS=1
diff --git a/tools/k3_fit_atf.sh b/tools/k3_fit_atf.sh
index 4e9f69c087..c0940a2fcc 100755
--- a/tools/k3_fit_atf.sh
+++ b/tools/k3_fit_atf.sh
@@ -21,6 +21,13 @@ if [ ! -f $TEE ]; then
TEE=/dev/null
 fi
 
+[ -z "$DM" ] && DM="dm.bin"
+
+if [ ! -e $DM ]; then
+   echo "WARNING DM file $DM NOT found, resulting might be non-functional" 
>&2
+   DM=/dev/null
+fi
+
 if [ ! -z "$IS_HS" ]; then
HS_APPEND=_HS
 fi
@@ -53,6 +60,16 @@ cat << __HEADER_EOF
load = <0x9e80>;
entry = <0x9e80>;
};
+   dm {
+   description = "DM binary";
+   data = /incbin/("$DM");
+   type = "firmware";
+   arch = "arm32";
+   compression = "none";
+   os = "DM";
+   load = <0xa000>;
+   entry = <0xa000>;
+   };
spl {
description = "SPL (64-bit)";
data = /incbin/("spl/u-boot-spl-nodtb.bin$HS_APPEND");
@@ -91,7 +108,7 @@ do
$(basename $dtname) {
description = "$(basename $dtname .dtb)";
firmware = "atf";
-   loadables = "tee", "spl";
+   loadables = "tee", "dm", "spl";
fdt = "$(basename $dtname)";
};
 __CONF_SECTION_EOF
-- 
2.17.1

[PATCHv5 15/26] cmd: ti: pd: Add debug command for K3 power domains

[Tero Kristo]

From: Tero Kristo 

Add support command for debugging K3 power domains. This is useful with
the HSM rearch setup, where power domains are directly controlled by SPL
instead of going through the TI SCI layer. The debugging support is only
available in the u-boot codebase though, so the raw register access
power domain layer must be enabled on u-boot side for this to work. By
default, u-boot side uses the TI SCI layer, and R5 SPL only uses the
direct access methods.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
Reviewed-by: Jaehoon Chung 
---
 cmd/ti/Kconfig |   8 ++
 cmd/ti/Makefile|   1 +
 cmd/ti/pd.c| 185 +
 drivers/power/domain/ti-power-domain.c |   6 +-
 include/k3-dev.h   |   9 ++
 5 files changed, 206 insertions(+), 3 deletions(-)
 create mode 100644 cmd/ti/pd.c

diff --git a/cmd/ti/Kconfig b/cmd/ti/Kconfig
index efeff0d482..db557445a8 100644
--- a/cmd/ti/Kconfig
+++ b/cmd/ti/Kconfig
@@ -7,4 +7,12 @@ config CMD_DDR3
   supports memory verification, memory comapre and ecc
   verification if supported.
 
+config CMD_PD
+   bool "command for verifying power domains"
+   depends on TI_POWER_DOMAIN
+   help
+  Debug command for K3 power domains. For this to work, the
+  K3 power domain driver must be enabled for the u-boot; by
+  default it is only enabled for SPL.
+
 endmenu
diff --git a/cmd/ti/Makefile b/cmd/ti/Makefile
index 16fbade9ed..045593396b 100644
--- a/cmd/ti/Makefile
+++ b/cmd/ti/Makefile
@@ -5,4 +5,5 @@ obj- += dummy.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_CMD_DDR3) += ddr3.o
+obj-$(CONFIG_CMD_PD) += pd.o
 endif
diff --git a/cmd/ti/pd.c b/cmd/ti/pd.c
new file mode 100644
index 00..a53ccdcc40
--- /dev/null
+++ b/cmd/ti/pd.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Power Domain test commands
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated, 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static const struct udevice_id ti_pd_of_match[] = {
+   { .compatible = "ti,sci-pm-domain" },
+   { /* sentinel */ }
+};
+
+static struct ti_k3_pd_platdata *ti_pd_find_data(void)
+{
+   struct udevice *dev;
+   int i = 0;
+
+   while (1) {
+   uclass_get_device(UCLASS_POWER_DOMAIN, i++, );
+   if (!dev)
+   return NULL;
+
+   if (device_is_compatible(dev,
+ti_pd_of_match[0].compatible))
+   return  dev_get_priv(dev);
+   }
+
+   return NULL;
+}
+
+static void dump_lpsc(struct ti_k3_pd_platdata *data, struct ti_pd *pd)
+{
+   int i;
+   struct ti_lpsc *lpsc;
+   u8 state;
+   static const char * const lpsc_states[] = {
+   "swrstdis", "syncrst", "disable", "enable", "autosleep",
+   "autowake", "unknown",
+   };
+
+   for (i = 0; i < data->num_lpsc; i++) {
+   lpsc = >lpsc[i];
+   if (lpsc->pd != pd)
+   continue;
+   state = lpsc_get_state(lpsc);
+   if (state > ARRAY_SIZE(lpsc_states))
+   state = ARRAY_SIZE(lpsc_states) - 1;
+   printf("LPSC%d: state=%s, usecount=%d\n",
+  lpsc->id, lpsc_states[state], lpsc->usecount);
+   }
+}
+
+static void dump_pd(struct ti_k3_pd_platdata *data, struct ti_psc *psc)
+{
+   int i;
+   struct ti_pd *pd;
+   u8 state;
+   static const char * const pd_states[] = {
+   "off", "on", "unknown"
+   };
+
+   for (i = 0; i < data->num_pd; i++) {
+   pd = >pd[i];
+   if (pd->psc != psc)
+   continue;
+   state = ti_pd_state(pd);
+   if (state > ARRAY_SIZE(pd_states))
+   state = ARRAY_SIZE(pd_states) - 1;
+   printf("  PD%d: state=%s, usecount=%d:\n",
+  pd->id, pd_states[state], pd->usecount);
+   dump_lpsc(data, pd);
+   }
+}
+
+static void dump_psc(struct ti_k3_pd_platdata *data)
+{
+   int i;
+   struct ti_psc *psc;
+
+   for (i = 0; i < data->num_psc; i++) {
+   psc = >psc[i];
+   printf("PSC%d [%p]:\n", psc->id, psc->base);
+   dump_pd(data, psc);
+   }
+}
+
+static int do_pd_dump(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+   struct ti_k3_pd_platdata *data;
+
+   data = ti_pd_find_data();
+   if (!data)
+   return CMD_RET_FAILURE;
+
+   dump_psc(data);
+
+   return 0;
+}
+
+static int do_pd_endis(int argc, char *const argv[], u8 state)
+

[PATCHv5 13/26] clk: add support for TI K3 SoC clocks

[Tero Kristo]

From: Tero Kristo 

Add driver to support TI K3 generation SoC clocks. This driver registers
the clocks provided via platform data, and adds support for controlling
the clocks via DT handles.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/ti/Kconfig  |  12 ++
 drivers/clk/ti/Makefile |   1 +
 drivers/clk/ti/clk-k3.c | 374 
 include/k3-clk.h| 162 +
 4 files changed, 549 insertions(+)
 create mode 100644 drivers/clk/ti/clk-k3.c

diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index a8ec4f541a..fbcdefd889 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -53,3 +53,15 @@ config SPL_CLK_K3_PLL
depends on CLK && LIB_RATIONAL && SPL
help
  Enables PLL clock support for K3 SoC family of devices.
+
+config CLK_K3
+   bool "Clock support for K3 SoC family of devices"
+   depends on CLK
+   help
+ Enables the clock translation layer from DT to device clocks.
+
+config SPL_CLK_K3
+   bool "Clock support for K3 SoC family of devices"
+   depends on CLK && SPL
+   help
+ Enables the clock translation layer from DT to device clocks.
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 47839213e5..07aa9a53e0 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o
 obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
 obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o
 obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_K3) += clk-k3.o
diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
new file mode 100644
index 00..ec262d5c21
--- /dev/null
+++ b/drivers/clk/ti/clk-k3.c
@@ -0,0 +1,374 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 clock driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "k3-clk.h"
+
+#define PLL_MIN_FREQ   8
+#define PLL_MAX_FREQ   32UL
+#define PLL_MAX_DIV127
+
+/**
+ * struct clk_map - mapping from dev/clk id tuples towards physical clocks
+ * @dev_id: device ID for the clock
+ * @clk_id: clock ID for the clock
+ * @clk: pointer to the registered clock entry for the mapping
+ */
+struct clk_map {
+   u16 dev_id;
+   u32 clk_id;
+   struct clk *clk;
+};
+
+/**
+ * struct ti_clk_data - clock controller information structure
+ * @map: mapping from dev/clk id tuples to physical clock entries
+ * @size: number of entries in the map
+ */
+struct ti_clk_data {
+   struct clk_map *map;
+   int size;
+};
+
+static ulong osc_freq;
+
+static void clk_add_map(struct ti_clk_data *data, struct clk *clk,
+   u32 dev_id, u32 clk_id)
+{
+   struct clk_map *map;
+
+   debug("%s: added clk=%p, data=%p, dev=%d, clk=%d\n", __func__,
+ clk, data, dev_id, clk_id);
+   if (!clk)
+   return;
+
+   map = data->map + data->size++;
+
+   map->dev_id = dev_id;
+   map->clk_id = clk_id;
+   map->clk = clk;
+}
+
+static const struct soc_attr ti_k3_soc_clk_data[] = {
+#ifdef CONFIG_SOC_K3_J721E
+   {
+   .family = "J721E",
+   .data = _clk_platdata,
+   },
+   {
+   .family = "J7200",
+   .data = _clk_platdata,
+   },
+#endif
+   { /* sentinel */ }
+};
+
+static int ti_clk_probe(struct udevice *dev)
+{
+   struct ti_clk_data *data = dev_get_priv(dev);
+   struct clk *clk;
+   const char *name;
+   const struct clk_data *ti_clk_data;
+   int i, j;
+   const struct soc_attr *soc_match_data;
+   const struct ti_k3_clk_platdata *pdata;
+
+   debug("%s(dev=%p)\n", __func__, dev);
+
+   soc_match_data = soc_device_match(ti_k3_soc_clk_data);
+   if (!soc_match_data)
+   return -ENODEV;
+
+   pdata = (const struct ti_k3_clk_platdata *)soc_match_data->data;
+
+   data->map = kcalloc(pdata->soc_dev_clk_data_cnt, sizeof(*data->map),
+   GFP_KERNEL);
+   data->size = 0;
+
+   for (i = 0; i < pdata->clk_list_cnt; i++) {
+   ti_clk_data = >clk_list[i];
+
+   switch (ti_clk_data->type) {
+   case CLK_TYPE_FIXED_RATE:
+   name = ti_clk_data->clk.fixed_rate.name;
+   clk = clk_register_fixed_rate(NULL,
+ name,
+ 
ti_clk_data->clk.fixed_rate.rate);
+   break;
+   case CLK_TYPE_DIV:
+   name = ti_clk_data->clk.div.name;
+   clk = clk_register_divider(NULL, nam

[PATCHv5 14/26] power: domain: Introduce driver for raw TI K3 PDs

[Tero Kristo]

From: Tero Kristo 

Normally, power domains are handled via TI-SCI in K3 SoCs. However,
SPL is not going to have access to sysfw resources, so it must control
them directly. Add driver for supporting this.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
Reviewed-by: Jaehoon Chung 
---
 drivers/power/domain/Kconfig   |   7 +
 drivers/power/domain/Makefile  |   1 +
 drivers/power/domain/ti-power-domain.c | 368 +
 include/k3-dev.h   |  76 +
 4 files changed, 452 insertions(+)
 create mode 100644 drivers/power/domain/ti-power-domain.c
 create mode 100644 include/k3-dev.h

diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index a0fd980752..99b3f9ae71 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -72,4 +72,11 @@ config TI_SCI_POWER_DOMAIN
help
  Generic power domain implementation for TI devices implementing the
  TI SCI protocol.
+
+config TI_POWER_DOMAIN
+   bool "Enable the TI K3 Power domain driver"
+   depends on POWER_DOMAIN && ARCH_K3
+   help
+ Generic power domain implementation for TI K3 devices.
+
 endmenu
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 45bf9f6383..3d1e5f073c 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
 obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
 obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o
 obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o
+obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o
diff --git a/drivers/power/domain/ti-power-domain.c 
b/drivers/power/domain/ti-power-domain.c
new file mode 100644
index 00..5d089f8e19
--- /dev/null
+++ b/drivers/power/domain/ti-power-domain.c
@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments power domain driver
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PSC_PTCMD  0x120
+#define PSC_PTSTAT 0x128
+#define PSC_PDSTAT 0x200
+#define PSC_PDCTL  0x300
+#define PSC_MDSTAT 0x800
+#define PSC_MDCTL  0xa00
+
+#define PDCTL_STATE_MASK   0x1
+#define PDCTL_STATE_OFF0x0
+#define PDCTL_STATE_ON 0x1
+
+#define MDSTAT_STATE_MASK  0x3f
+#define MDSTAT_BUSY_MASK   0x30
+#define MDSTAT_STATE_SWRSTDISABLE  0x0
+#define MDSTAT_STATE_ENABLE0x3
+
+#define LPSC_TIMEOUT   1000
+#define PD_TIMEOUT 1000
+
+static u32 psc_read(struct ti_psc *psc, u32 reg)
+{
+   u32 val;
+
+   val = readl(psc->base + reg);
+   debug("%s: 0x%x from %p\n", __func__, val, psc->base + reg);
+   return val;
+}
+
+static void psc_write(u32 val, struct ti_psc *psc, u32 reg)
+{
+   debug("%s: 0x%x to %p\n", __func__, val, psc->base + reg);
+   writel(val, psc->base + reg);
+}
+
+static u32 pd_read(struct ti_pd *pd, u32 reg)
+{
+   return psc_read(pd->psc, reg + 4 * pd->id);
+}
+
+static void pd_write(u32 val, struct ti_pd *pd, u32 reg)
+{
+   psc_write(val, pd->psc, reg + 4 * pd->id);
+}
+
+static u32 lpsc_read(struct ti_lpsc *lpsc, u32 reg)
+{
+   return psc_read(lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static void lpsc_write(u32 val, struct ti_lpsc *lpsc, u32 reg)
+{
+   psc_write(val, lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static const struct soc_attr ti_k3_soc_pd_data[] = {
+#ifdef CONFIG_SOC_K3_J721E
+   {
+   .family = "J721E",
+   .data = _pd_platdata,
+   },
+   {
+   .family = "J7200",
+   .data = _pd_platdata,
+   },
+#endif
+   { /* sentinel */ }
+};
+
+static int ti_power_domain_probe(struct udevice *dev)
+{
+   struct ti_k3_pd_platdata *data = dev_get_priv(dev);
+   const struct soc_attr *soc_match_data;
+   const struct ti_k3_pd_platdata *pdata;
+
+   printf("%s(dev=%p)\n", __func__, dev);
+
+   if (!data)
+   return -ENOMEM;
+
+   soc_match_data = soc_device_match(ti_k3_soc_pd_data);
+   if (!soc_match_data)
+   return -ENODEV;
+
+   pdata = (const struct ti_k3_pd_platdata *)soc_match_data->data;
+
+   data->psc = pdata->psc;
+   data->pd = pdata->pd;
+   data->lpsc = pdata->lpsc;
+   data->devs = pdata->devs;
+   data->num_psc = pdata->num_psc;
+   data->num_pd = pdata->num_pd;
+   data->num_lpsc = pdata->num_lpsc;
+   data->num_devs = pdata->num_devs;
+
+   return 0;

[PATCHv5 12/26] clk: add support for TI K3 SoC PLL

[Tero Kristo]

From: Tero Kristo 

Add support for TI K3 SoC PLLs. This clock type supports
enabling/disabling/setting and querying the clock rate for the PLL. The
euclidean library routine is used to calculate divider/multiplier rates
for the PLLs.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/ti/Kconfig  |  12 ++
 drivers/clk/ti/Makefile |   1 +
 drivers/clk/ti/clk-k3-pll.c | 283 
 include/k3-clk.h|  15 ++
 4 files changed, 311 insertions(+)
 create mode 100644 drivers/clk/ti/clk-k3-pll.c
 create mode 100644 include/k3-clk.h

diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index 2dc86d44a9..a8ec4f541a 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -41,3 +41,15 @@ config CLK_TI_SCI
  This enables the clock driver support over TI System Control Interface
  available on some new TI's SoCs. If you wish to use clock resources
  managed by the TI System Controller, say Y here. Otherwise, say N.
+
+config CLK_K3_PLL
+   bool "PLL clock support for K3 SoC family of devices"
+   depends on CLK && LIB_RATIONAL
+   help
+ Enables PLL clock support for K3 SoC family of devices.
+
+config SPL_CLK_K3_PLL
+   bool "PLL clock support for K3 SoC family of devices"
+   depends on CLK && LIB_RATIONAL && SPL
+   help
+ Enables PLL clock support for K3 SoC family of devices.
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 9f56b47736..47839213e5 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o
 obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o
 obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
 obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o
diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c
new file mode 100644
index 00..bf2407a020
--- /dev/null
+++ b/drivers/clk/ti/clk-k3-pll.c
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 SoC PLL clock driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "k3-clk.h"
+#include 
+
+/* 16FFT register offsets */
+#define PLL_16FFT_CFG  0x08
+#define PLL_KICK0  0x10
+#define PLL_KICK1  0x14
+#define PLL_16FFT_CTRL 0x20
+#define PLL_16FFT_STAT 0x24
+#define PLL_16FFT_FREQ_CTRL0   0x30
+#define PLL_16FFT_FREQ_CTRL1   0x34
+#define PLL_16FFT_DIV_CTRL 0x38
+
+/* CTRL register bits */
+#define PLL_16FFT_CTRL_BYPASS_EN   BIT(31)
+#define PLL_16FFT_CTRL_PLL_EN  BIT(15)
+#define PLL_16FFT_CTRL_DSM_EN  BIT(1)
+
+/* STAT register bits */
+#define PLL_16FFT_STAT_LOCKBIT(0)
+
+/* FREQ_CTRL0 bits */
+#define PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK   0xfff
+
+/* DIV CTRL register bits */
+#define PLL_16FFT_DIV_CTRL_REF_DIV_MASK0x3f
+
+#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS  24
+#define PLL_16FFT_HSDIV_CTRL_CLKOUT_EN  BIT(15)
+
+/* KICK register magic values */
+#define PLL_KICK0_VALUE0x68ef3490
+#define PLL_KICK1_VALUE0xd172bc5a
+
+/**
+ * struct ti_pll_clk - TI PLL clock data info structure
+ * @clk: core clock structure
+ * @reg: memory address of the PLL controller
+ */
+struct ti_pll_clk {
+   struct clk  clk;
+   void __iomem*reg;
+};
+
+#define to_clk_pll(_clk) container_of(_clk, struct ti_pll_clk, clk)
+
+static int ti_pll_wait_for_lock(struct clk *clk)
+{
+   struct ti_pll_clk *pll = to_clk_pll(clk);
+   u32 stat;
+   int i;
+
+   for (i = 0; i < 10; i++) {
+   stat = readl(pll->reg + PLL_16FFT_STAT);
+   if (stat & PLL_16FFT_STAT_LOCK)
+   return 0;
+   }
+
+   printf("%s: pll (%s) failed to lock\n", __func__,
+  clk->dev->name);
+
+   return -EBUSY;
+}
+
+static ulong ti_pll_clk_get_rate(struct clk *clk)
+{
+   struct ti_pll_clk *pll = to_clk_pll(clk);
+   u64 current_freq;
+   u64 parent_freq = clk_get_parent_rate(clk);
+   u32 pllm;
+   u32 plld;
+   u32 pllfm;
+   u32 ctrl;
+
+   /* Check if we are in bypass */
+   ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+   if (ctrl & PLL_16FFT_CTRL_BYPASS_EN)
+   return parent_freq;
+
+   pllm = readl(pll->reg + PLL_16FFT_FREQ_CTRL0);
+   pllfm = readl(pll->reg + PLL_16FFT_FREQ_CTRL1);
+
+   plld = readl(pll->reg + PLL_16FFT_DIV_CTRL) &
+   PLL_16FFT_DIV_CTRL_REF_DIV_MASK;
+
+   current_freq = parent_freq * pllm / plld;
+
+   if (pllfm) {
+ 

[PATCHv5 11/26] clk: fix set_rate to clean up cached rates for the hierarchy

[Tero Kristo]

From: Tero Kristo 

Clock rates are cached within the individual clock nodes, and right now
if one changes a clock rate somewhere in the middle of the tree, none
of its child clocks notice the change. To fix this, clear up all the
cached rates for us and our child clocks.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/clk-uclass.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 815f7bfe98..3d2344f009 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -568,6 +568,22 @@ ulong clk_round_rate(struct clk *clk, ulong rate)
return ops->round_rate(clk, rate);
 }
 
+static void clk_clean_rate_cache(struct clk *clk)
+{
+   struct udevice *child_dev;
+   struct clk *clkp;
+
+   if (!clk)
+   return;
+
+   clk->rate = 0;
+
+   list_for_each_entry(child_dev, >dev->child_head, sibling_node) {
+   clkp = dev_get_clk_ptr(child_dev);
+   clk_clean_rate_cache(clkp);
+   }
+}
+
 ulong clk_set_rate(struct clk *clk, ulong rate)
 {
const struct clk_ops *ops;
@@ -580,6 +596,9 @@ ulong clk_set_rate(struct clk *clk, ulong rate)
if (!ops->set_rate)
return -ENOSYS;
 
+   /* Clean up cached rates for us and all child clocks */
+   clk_clean_rate_cache(clk);
+
return ops->set_rate(clk, rate);
 }
 
-- 
2.17.1

[PATCHv5 10/26] clk: fix assigned-clocks to pass with deferring provider

[Tero Kristo]

From: Tero Kristo 

If a clock provider is not ready for assigning default rates/parents
during its probe, it may return -EPROBE_DEFER directly from xlate.
Handle this special case properly by skipping the entry and adjusting the
return value to pass. The defaults will be handled properly in post probe
phase then.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/clk-uclass.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 451d7da001..815f7bfe98 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -241,6 +241,15 @@ static int clk_set_default_parents(struct udevice *dev, 
int stage)
 
ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  index, );
+   /*
+* If the clock provider is not ready yet, let it handle
+* the re-programming later.
+*/
+   if (ret == -EPROBE_DEFER) {
+   ret = 0;
+   continue;
+   }
+
if (ret) {
debug("%s: could not get assigned clock %d for %s\n",
  __func__, index, dev_read_name(dev));
@@ -309,6 +318,15 @@ static int clk_set_default_rates(struct udevice *dev, int 
stage)
 
ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  index, );
+   /*
+* If the clock provider is not ready yet, let it handle
+* the re-programming later.
+*/
+   if (ret == -EPROBE_DEFER) {
+   ret = 0;
+   continue;
+   }
+
if (ret) {
dev_dbg(dev,
"could not get assigned clock %d (err = %d)\n",
-- 
2.17.1

[PATCHv5 09/26] clk: sci-clk: fix return value of set_rate

[Tero Kristo]

From: Tero Kristo 

Set rate should return the new clock rate on success, and negative error
value on failure. Fix this, as currently set_rate returns 0 on success.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/ti/clk-sci.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/ti/clk-sci.c b/drivers/clk/ti/clk-sci.c
index 6f0fdaa111..acb9eadf03 100644
--- a/drivers/clk/ti/clk-sci.c
+++ b/drivers/clk/ti/clk-sci.c
@@ -111,10 +111,12 @@ static ulong ti_sci_clk_set_rate(struct clk *clk, ulong 
rate)
 #endif
 
ret = cops->set_freq(sci, clk->id, clk->data, 0, rate, ULONG_MAX);
-   if (ret)
+   if (ret) {
dev_err(clk->dev, "%s: set_freq failed (%d)\n", __func__, ret);
+   return ret;
+   }
 
-   return ret;
+   return rate;
 }
 
 static int ti_sci_clk_set_parent(struct clk *clk, struct clk *parent)
-- 
2.17.1

[PATCHv5 08/26] clk: add support for setting clk rate from cmdline

[Tero Kristo]

From: Tero Kristo 

Add new clk subcommand "clk setfreq", for setting up a clock rate
directly from u-boot cmdline. This is handy for any debugging purposes
towards clocks.

Acked-by: Lukasz Majewski 
Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 cmd/clk.c | 49 +++--
 1 file changed, 47 insertions(+), 2 deletions(-)

diff --git a/cmd/clk.c b/cmd/clk.c
index 0245b97136..fd7944c02e 100644
--- a/cmd/clk.c
+++ b/cmd/clk.c
@@ -98,8 +98,52 @@ static int do_clk_dump(struct cmd_tbl *cmdtp, int flag, int 
argc,
return ret;
 }
 
+struct udevice *clk_lookup(const char *name)
+{
+   int i = 0;
+   struct udevice *dev;
+
+   do {
+   uclass_get_device(UCLASS_CLK, i++, );
+   if (!strcmp(name, dev->name))
+   return dev;
+   } while (dev);
+
+   return NULL;
+}
+
+static int do_clk_setfreq(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+   struct clk *clk = NULL;
+   s32 freq;
+   struct udevice *dev;
+
+   freq = simple_strtoul(argv[2], NULL, 10);
+
+   dev = clk_lookup(argv[1]);
+
+   if (dev)
+   clk = dev_get_clk_ptr(dev);
+
+   if (!clk) {
+   printf("clock '%s' not found.\n", argv[1]);
+   return -EINVAL;
+   }
+
+   freq = clk_set_rate(clk, freq);
+   if (freq < 0) {
+   printf("set_rate failed: %d\n", freq);
+   return CMD_RET_FAILURE;
+   }
+
+   printf("set_rate returns %u\n", freq);
+   return 0;
+}
+
 static struct cmd_tbl cmd_clk_sub[] = {
U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""),
+   U_BOOT_CMD_MKENT(setfreq, 3, 1, do_clk_setfreq, "", ""),
 };
 
 static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc,
@@ -124,7 +168,8 @@ static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc,
 
 #ifdef CONFIG_SYS_LONGHELP
 static char clk_help_text[] =
-   "dump - Print clock frequencies";
+   "dump - Print clock frequencies\n"
+   "setfreq [clk] [freq] - Set clock frequency";
 #endif
 
-U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text);
+U_BOOT_CMD(clk, 4, 1, do_clk, "CLK sub-system", clk_help_text);
-- 
2.17.1

[PATCHv5 07/26] clk: do not attempt to fetch clock pointer with null device

[Tero Kristo]

From: Tero Kristo 

Bail out early if device returned for the parent clock is null.
This avoids warning prints like this when doing clk dump:

  dev_get_uclass_priv: null device

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/clk-uclass.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 53e7be764d..451d7da001 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -502,6 +502,8 @@ struct clk *clk_get_parent(struct clk *clk)
return NULL;
 
pdev = dev_get_parent(clk->dev);
+   if (!pdev)
+   return ERR_PTR(-ENODEV);
pclk = dev_get_clk_ptr(pdev);
if (!pclk)
return ERR_PTR(-ENODEV);
-- 
2.17.1

[PATCHv5 06/26] clk: fix clock tree dump to properly dump out every registered clock

[Tero Kristo]

From: Tero Kristo 

Some clocks are not associated to a DM node, so just parsing the DM is not
enough. This is especially true for root clocks, which typically don't have
any parents. Instead, fetch every registered UCLASS_CLK instance, and dump
these out.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 cmd/clk.c | 27 +++
 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/cmd/clk.c b/cmd/clk.c
index e3c3d2f9bb..0245b97136 100644
--- a/cmd/clk.c
+++ b/cmd/clk.c
@@ -18,11 +18,14 @@ static void show_clks(struct udevice *dev, int depth, int 
last_flag)
 {
int i, is_last;
struct udevice *child;
-   struct clk *clkp;
+   struct clk *clkp, *parent;
u32 rate;
 
clkp = dev_get_clk_ptr(dev);
if (device_get_uclass_id(dev) == UCLASS_CLK && clkp) {
+   parent = clk_get_parent(clkp);
+   if (!IS_ERR(parent) && depth == -1)
+   return;
depth++;
rate = clk_get_rate(clkp);
 
@@ -47,6 +50,9 @@ static void show_clks(struct udevice *dev, int depth, int 
last_flag)
}
 
list_for_each_entry(child, >child_head, sibling_node) {
+   if (child == dev)
+   continue;
+
is_last = list_is_last(>sibling_node, >child_head);
show_clks(child, depth, (last_flag << 1) | is_last);
}
@@ -54,14 +60,19 @@ static void show_clks(struct udevice *dev, int depth, int 
last_flag)
 
 int __weak soc_clk_dump(void)
 {
-   struct udevice *root;
+   struct udevice *dev;
+   struct uclass *uc;
+   int ret;
 
-   root = dm_root();
-   if (root) {
-   printf(" Rate   Usecnt  Name\n");
-   printf("--\n");
-   show_clks(root, -1, 0);
-   }
+   ret = uclass_get(UCLASS_CLK, );
+   if (ret)
+   return ret;
+
+   printf(" Rate   Usecnt  Name\n");
+   printf("--\n");
+
+   uclass_foreach_dev(dev, uc)
+   show_clks(dev, -1, 0);
 
return 0;
 }
-- 
2.17.1

[PATCHv5 05/26] clk: fixed_rate: add API for directly registering fixed rate clocks

[Tero Kristo]

From: Tero Kristo 

Current driver only supports registering fixed rate clocks from DT. Add
new API which makes it possible to register fixed rate clocks directly
from e.g. platform specific clock drivers.

Reviewed-by: Peng Fan 
Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/clk_fixed_rate.c | 43 
 include/linux/clk-provider.h |  3 +++
 2 files changed, 46 insertions(+)

diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 09f9ef26a4..c591abf685 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -9,6 +9,9 @@
 #include 
 #include 
 
+#define UBOOT_DM_CLK_FIXED_RATE "fixed_rate_clock"
+#define UBOOT_DM_CLK_FIXED_RATE_RAW "fixed_rate_raw_clock"
+
 static ulong clk_fixed_rate_get_rate(struct clk *clk)
 {
return to_clk_fixed_rate(clk->dev)->fixed_rate;
@@ -40,6 +43,15 @@ void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev,
clk->enable_count = 0;
 }
 
+static ulong clk_fixed_rate_raw_get_rate(struct clk *clk)
+{
+   return container_of(clk, struct clk_fixed_rate, clk)->fixed_rate;
+}
+
+const struct clk_ops clk_fixed_rate_raw_ops = {
+   .get_rate = clk_fixed_rate_raw_get_rate,
+};
+
 static int clk_fixed_rate_of_to_plat(struct udevice *dev)
 {
clk_fixed_rate_ofdata_to_plat_(dev, to_clk_fixed_rate(dev));
@@ -47,6 +59,30 @@ static int clk_fixed_rate_of_to_plat(struct udevice *dev)
return 0;
 }
 
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+   ulong rate)
+{
+   struct clk *clk;
+   struct clk_fixed_rate *fixed;
+   int ret;
+
+   fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
+   if (!fixed)
+   return ERR_PTR(-ENOMEM);
+
+   fixed->fixed_rate = rate;
+
+   clk = >clk;
+
+   ret = clk_register(clk, UBOOT_DM_CLK_FIXED_RATE_RAW, name, NULL);
+   if (ret) {
+   kfree(fixed);
+   return ERR_PTR(ret);
+   }
+
+   return clk;
+}
+
 static const struct udevice_id clk_fixed_rate_match[] = {
{
.compatible = "fixed-clock",
@@ -63,3 +99,10 @@ U_BOOT_DRIVER(fixed_clock) = {
.ops = _fixed_rate_ops,
.flags = DM_FLAG_PRE_RELOC,
 };
+
+U_BOOT_DRIVER(clk_fixed_rate_raw) = {
+   .name = UBOOT_DM_CLK_FIXED_RATE_RAW,
+   .id = UCLASS_CLK,
+   .ops = _fixed_rate_raw_ops,
+   .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 6fda14f5fe..9d296f240a 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -247,6 +247,9 @@ struct clk *clk_register_mux(struct device *dev, const char 
*name,
void __iomem *reg, u8 shift, u8 width,
u8 clk_mux_flags);
 
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+   ulong rate);
+
 const char *clk_hw_get_name(const struct clk *hw);
 ulong clk_generic_get_rate(struct clk *clk);
 
-- 
2.17.1

[PATCHv5 04/26] common: fit: Update board_fit_image_post_process() to pass fit and node_offset

[Tero Kristo]

From: Lokesh Vutla 

board_fit_image_post_process() passes only start and size of the image,
but type of the image is not passed. So pass fit and node_offset, to
derive information about image to be processed.

Signed-off-by: Lokesh Vutla 
Reviewed-by: Tom Rini 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/security.c  | 3 ++-
 arch/arm/mach-keystone/mon.c | 3 ++-
 board/ti/am335x/board.c  | 3 ++-
 board/ti/am43xx/board.c  | 3 ++-
 board/ti/am57xx/board.c  | 3 ++-
 board/ti/dra7xx/evm.c| 3 ++-
 common/image-fit.c   | 2 +-
 common/spl/spl_fit.c | 2 +-
 include/image.h  | 5 -
 9 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c
index 66f90a5a34..5b5ff9ba7b 100644
--- a/arch/arm/mach-k3/security.c
+++ b/arch/arm/mach-k3/security.c
@@ -18,7 +18,8 @@
 #include 
 #include 
 
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
 {
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
struct ti_sci_proc_ops *proc_ops = _sci->ops.proc_ops;
diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c
index 58995d73ac..b863bab196 100644
--- a/arch/arm/mach-keystone/mon.c
+++ b/arch/arm/mach-keystone/mon.c
@@ -103,7 +103,8 @@ static int k2_hs_bm_auth(int cmd, void *arg1)
return  result;
 }
 
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
 {
int result = 0;
void *image = *p_image;
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 5959ff73dc..5c156a5d1d 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -960,7 +960,8 @@ int board_fit_config_name_match(const char *name)
 #endif
 
 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
 {
secure_boot_verify_image(p_image, p_size);
 }
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index e9febb9592..a71b588efc 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -896,7 +896,8 @@ int embedded_dtb_select(void)
 #endif
 
 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
 {
secure_boot_verify_image(p_image, p_size);
 }
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 05c26c74d9..399a2e5d91 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -1199,7 +1199,8 @@ static int board_bootmode_has_emmc(void)
 #endif
 
 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
 {
secure_boot_verify_image(p_image, p_size);
 }
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 05f251f778..23e8005991 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -1065,7 +1065,8 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason 
reason)
 #endif
 
 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
 {
secure_boot_verify_image(p_image, p_size);
 }
diff --git a/common/image-fit.c b/common/image-fit.c
index e614643fe3..0c5a05948d 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -2143,7 +2143,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
 
/* perform any post-processing on the image data */
if (!host_build() && IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS))
-   board_fit_image_post_process(, );
+   board_fit_image_post_process(fit, noffset, , );
 
len = (ulong)size;
 
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index caddf51196..57d621d5b3 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -320,7 +320,7 @@ static int spl_load_fit_image(struct spl_load_info *info, 
ulong sector,
}
 
if (CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS))
-   board_fit_image_post_process(, );
+   board_fit_image_post_process(fit, node, , );
 
load_ptr = map_sysmem(load_addr, length);
if (IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP) {
diff --git a/include/image.h b/include/image.h
index 459685d4d4..0c24bf6f35 100644
--- a/include/image.h
++

[PATCHv5 03/26] remoteproc: k3-r5: remove sysfw PM calls if not supported

[Tero Kristo]

From: Tero Kristo 

With the sysfw rearch, sysfw PM calls are no longer available from SPL
level. To properly support this, remove the is_on checks and the reset
assertion from the R5 remoteproc driver as these are not supported.
Attempting to access unavailable services will cause the device to hang.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/remoteproc/ti_k3_r5f_rproc.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c 
b/drivers/remoteproc/ti_k3_r5f_rproc.c
index 3c569a3b7b..c8c30b9020 100644
--- a/drivers/remoteproc/ti_k3_r5f_rproc.c
+++ b/drivers/remoteproc/ti_k3_r5f_rproc.c
@@ -781,7 +781,9 @@ static int k3_r5f_probe(struct udevice *dev)
 {
struct k3_r5f_cluster *cluster = dev_get_priv(dev->parent);
struct k3_r5f_core *core = dev_get_priv(dev);
+#ifndef CONFIG_K3_DM_FW
bool r_state;
+#endif
int ret;
 
dev_dbg(dev, "%s\n", __func__);
@@ -804,6 +806,12 @@ static int k3_r5f_probe(struct udevice *dev)
return ret;
}
 
+   /*
+* The PM functionality is not supported by the firmware during
+* SPL execution with the separated DM firmware image. The following
+* piece of code is not compiled in that case.
+*/
+#ifndef CONFIG_K3_DM_FW
ret = core->tsp.sci->ops.dev_ops.is_on(core->tsp.sci, core->tsp.dev_id,
   _state, >in_use);
if (ret)
@@ -817,6 +825,7 @@ static int k3_r5f_probe(struct udevice *dev)
 
/* Make sure Local reset is asserted. Redundant? */
reset_assert(>reset);
+#endif
 
ret = k3_r5f_rproc_configure(core);
if (ret) {
-- 
2.17.1

[PATCHv5 02/26] arm: mach-k3: introduce new config option for sysfw split

[Tero Kristo]

From: Tero Kristo 

On J7 family of SoCs (J721E and J7200), sysfw is being split to be run
under two cores, TIFS portion on DMSC core, and DM firmware under MCU
R5. As MCU R5 is also used to run one phase of the bootloader, we must
prevent access from here towards sysfw services. To support this, add
new config option which can be used to detect presence of RM/PM sysfw
services.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/Kconfig | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index bfbce44bfa..069786ed0e 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -147,6 +147,17 @@ config SYS_K3_SPL_ATF
  Enabling this will try to start Cortex-A (typically with ATF)
  after SPL from R5.
 
+config K3_DM_FW
+   bool "Separate DM firmware image"
+   depends on SPL && CPU_V7R && SOC_K3_J721E && !CLK_TI_SCI && 
!TI_SCI_POWER_DOMAIN
+   default y
+   help
+ Enabling this will indicate that the system has separate DM
+ and TIFS firmware images in place, instead of a single SYSFW
+ firmware. Due to DM being executed on the same core as R5 SPL
+ bootloader, it makes RM and PM services not being available
+ during R5 SPL execution time.
+
 source "board/ti/am65x/Kconfig"
 source "board/ti/am64x/Kconfig"
 source "board/ti/j721e/Kconfig"
-- 
2.17.1

[PATCHv5 01/26] lib: rational: copy the rational fraction lib routines from Linux

[Tero Kristo]

From: Tero Kristo 

Copy the best rational approximation calculation routines from Linux.
Typical usecase for these routines is to calculate the M/N divider
values for PLLs to reach a specific clock rate.

This is based on linux kernel commit:
"lib/math/rational.c: fix possible incorrect result from rational
fractions helper"
(sha1: 323dd2c3ed0641f49e89b4e420f9eef5d3d5a881)

Signed-off-by: Tero Kristo 
Reviewed-by: Tom Rini 
Signed-off-by: Tero Kristo 
---
 include/linux/rational.h | 20 
 lib/Kconfig  |  7 +++
 lib/Makefile |  2 +
 lib/rational.c   | 99 
 4 files changed, 128 insertions(+)
 create mode 100644 include/linux/rational.h
 create mode 100644 lib/rational.c

diff --git a/include/linux/rational.h b/include/linux/rational.h
new file mode 100644
index 00..33f5f5fc3e
--- /dev/null
+++ b/include/linux/rational.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * rational fractions
+ *
+ * Copyright (C) 2009 emlix GmbH, Oskar Schirmer 
+ *
+ * helper functions when coping with rational numbers,
+ * e.g. when calculating optimum numerator/denominator pairs for
+ * pll configuration taking into account restricted register size
+ */
+
+#ifndef _LINUX_RATIONAL_H
+#define _LINUX_RATIONAL_H
+
+void rational_best_approximation(
+   unsigned long given_numerator, unsigned long given_denominator,
+   unsigned long max_numerator, unsigned long max_denominator,
+   unsigned long *best_numerator, unsigned long *best_denominator);
+
+#endif /* _LINUX_RATIONAL_H */
diff --git a/lib/Kconfig b/lib/Kconfig
index 15019d2c65..ad0cd52edd 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -674,6 +674,13 @@ config GENERATE_SMBIOS_TABLE
  See also SMBIOS_SYSINFO which allows SMBIOS values to be provided in
  the devicetree.
 
+config LIB_RATIONAL
+   bool "enable continued fraction calculation routines"
+
+config SPL_LIB_RATIONAL
+   bool "enable continued fraction calculation routines for SPL"
+   depends on SPL
+
 endmenu
 
 config ASN1_COMPILER
diff --git a/lib/Makefile b/lib/Makefile
index b4795a62a0..881034f4ae 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -73,6 +73,8 @@ obj-$(CONFIG_$(SPL_)LZO) += lzo/
 obj-$(CONFIG_$(SPL_)LZMA) += lzma/
 obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o
 
+obj-$(CONFIG_$(SPL_)LIB_RATIONAL) += rational.o
+
 obj-$(CONFIG_LIBAVB) += libavb/
 
 obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/
diff --git a/lib/rational.c b/lib/rational.c
new file mode 100644
index 00..316db3b590
--- /dev/null
+++ b/lib/rational.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * rational fractions
+ *
+ * Copyright (C) 2009 emlix GmbH, Oskar Schirmer 
+ * Copyright (C) 2019 Trent Piepho 
+ *
+ * helper functions when coping with rational numbers
+ */
+
+#include 
+#include 
+#include 
+
+/*
+ * calculate best rational approximation for a given fraction
+ * taking into account restricted register size, e.g. to find
+ * appropriate values for a pll with 5 bit denominator and
+ * 8 bit numerator register fields, trying to set up with a
+ * frequency ratio of 3.1415, one would say:
+ *
+ * rational_best_approximation(31415, 1,
+ * (1 << 8) - 1, (1 << 5) - 1, , );
+ *
+ * you may look at given_numerator as a fixed point number,
+ * with the fractional part size described in given_denominator.
+ *
+ * for theoretical background, see:
+ * http://en.wikipedia.org/wiki/Continued_fraction
+ */
+
+void rational_best_approximation(
+   unsigned long given_numerator, unsigned long given_denominator,
+   unsigned long max_numerator, unsigned long max_denominator,
+   unsigned long *best_numerator, unsigned long *best_denominator)
+{
+   /* n/d is the starting rational, which is continually
+* decreased each iteration using the Euclidean algorithm.
+*
+* dp is the value of d from the prior iteration.
+*
+* n2/d2, n1/d1, and n0/d0 are our successively more accurate
+* approximations of the rational.  They are, respectively,
+* the current, previous, and two prior iterations of it.
+*
+* a is current term of the continued fraction.
+*/
+   unsigned long n, d, n0, d0, n1, d1, n2, d2;
+   n = given_numerator;
+   d = given_denominator;
+   n0 = d1 = 0;
+   n1 = d0 = 1;
+
+   for (;;) {
+   unsigned long dp, a;
+
+   if (d == 0)
+   break;
+   /* Find next term in continued fraction, 'a', via
+* Euclidean algorithm.
+*/
+   dp = d;
+   a = n / d;
+   d = n % d;
+   n = dp;
+
+   /* Calculate the current rational approximation (aka
+* convergent), n2/d2, using the term just found and
+* the two prior approximations.
+ 

[PATCHv5 00/26] Re-base / re-post of TI-K3 HSM rearch series

[Tero Kristo]

Hi,

As requested, this is just a rebase to the latest u-boot tip.

Boot tested on j721e to make sure nothing got broken.

-Tero

[PATCHv2] net: convert TFTP_TSIZE to proper Kconfig option

[Tero Kristo]

TFTP transfer size can be used to re-size the TFTP progress bar on
single line based on the server reported file size. The support for
this has been around from 2019, but it was never converted to proper
Kconfig.

While adding this new Kconfig, enable it by default for OMAP2+ and K3
devices also.

Signed-off-by: Tero Kristo 
---
v2: convert to proper Kconfig and add defaults for TI platforms

 net/Kconfig | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/net/Kconfig b/net/Kconfig
index c4b4dae064..ba0ca813ce 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -74,6 +74,17 @@ config TFTP_WINDOWSIZE
  before an ack response is required.
  The default TFTP implementation implies a window size of 1.
 
+config TFTP_TSIZE
+   bool "Track TFTP transfers based on file size option"
+   depends on CMD_TFTPBOOT
+   default y if (ARCH_OMAP2PLUS || ARCH_K3)
+   help
+ By default, TFTP progress bar is increased for each received UDP
+ frame, which can lead into long time being spent for sending
+ data over the UART. Enabling this option, TFTP queries the file
+ size from server, and if supported, limits the progress bar to
+ 50 characters total which fits on single line.
+
 config SERVERIP_FROM_PROXYDHCP
bool "Get serverip value from Proxy DHCP response"
help
-- 
2.17.1

Re: [PATCH v2 00/15] ram: k3-ddrss: Convert k3-j721e to common driver with k3-am64 support

[Tero Kristo]

On 11/05/2021 18:21, Dave Gerlach wrote:

This is v2 of the series to update the existing k3-j721e driver to a
common driver to support both j721e and the new am642 SoC. It renames
drivers/ram/k3-j721e to drivers/ram/k3-ddrss and then introduces a
refactored common driver with the existing j721e support moved to files
named with 32bit and am64 support introduced in files named with 16bit.

Changes since v1:
* Drop unnecessary error macro re-definitions and use normal errno header
* Drop other unnecessary headers that wrap standard kernel headers
* Fixed a few camelCase functions that slipped through
* Fixed clock initialization sequence based on comment from Vignesh

v1: https://lists.denx.de/pipermail/u-boot/2021-May/448716.html

Regards,
Dave


Hi Dave,

Thanks for the changes, did a diff between v1 and v2 of these patches 
and they look good. There is one thing that should maybe fixed sometime 
in future still, but I am not holding my review based on that. The 
function prototypes that return error codes should be changed to be int 
instead of u32, and change all the error return values to be negatives. 
Right now the driver is using positive values so some piece of code 
might get confused by that.


Just keep it in mind for future improvements.

For the whole series (did a quick test run with the latest v4 HSM rearch 
series also):


Reviewed-by: Tero Kristo 
Tested-by: Tero Kristo 



Dave Gerlach (14):
   dt-bindings: memory-controller: Add K3 AM64 DDRSS compatible
   ram: k3-j721e: lpddr4_address_slice_0_macros: Fix indentation issues
   ram: k3-j721e: lpddr4_data_slice_0_macros: Fix indentation issues
   ram: k3-j721e: lpddr4_data_slice_1_macros: Fix indentation issues
   ram: k3-j721e: lpddr4_data_slice_2_macros: Fix indentation issues
   ram: k3-j721e: lpddr4_data_slice_3_macros: Fix indentation issues
   ram: k3-j721e: lpddr4_ddr_controller_macros: Fix indentation issues
   ram: k3-j721e: lpddr4_phy_core_macros: Fix indentation issues
   ram: k3-j721e: lpddr4_pi_macros: Fix indentation issues
   ram: k3-j721e: lpddr4_ctl_regs: Fix checkpatch issue for types
   ram: k3-j721e: Rename to k3-ddrss
   ram: k3-ddrss: Introduce top-level CONFIG_K3_DDRSS
   ram: k3-ddrss: Introduce common driver with J7 SoC support
   ram: k3-ddrss: Introduce support for AM642 SoCs

Lokesh Vutla (1):
   ram: k3-ddrss: Enable vtt regulator if present

  board/ti/j721e/Kconfig|4 +-
  .../memory-controller/k3-j721e-ddrss.txt  |3 +-
  drivers/ram/Kconfig   |   24 +-
  drivers/ram/Makefile  |2 +-
  drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h  |  108 +
  .../ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h  |   14 +
  .../k3-ddrss/16bit/lpddr4_16bit_structs_if.h  |   15 +
  .../16bit/lpddr4_address_slice_0_macros.h |  624 ++
  .../16bit/lpddr4_address_slice_1_macros.h |  624 ++
  .../16bit/lpddr4_address_slice_2_macros.h |  624 ++
  drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h  | 1306 +++
  .../k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h |   23 +
  .../16bit/lpddr4_data_slice_0_macros.h| 2036 +
  .../16bit/lpddr4_data_slice_1_macros.h| 2036 +
  .../16bit/lpddr4_ddr_controller_macros.h  | 6436 ++
  .../k3-ddrss/16bit/lpddr4_phy_core_macros.h   | 1838 
  drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h | 5784 
  drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h  |   91 +
  .../ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h  |   14 +
  .../k3-ddrss/32bit/lpddr4_32bit_structs_if.h  |   15 +
  .../32bit}/lpddr4_address_slice_0_macros.h|  343 +-
  drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h  | 1545 
  .../k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h |   23 +
  .../32bit}/lpddr4_data_slice_0_macros.h   | 1443 ++-
  .../32bit}/lpddr4_data_slice_1_macros.h   | 1363 ++-
  .../32bit}/lpddr4_data_slice_2_macros.h   | 1363 ++-
  .../32bit}/lpddr4_data_slice_3_macros.h   | 1363 ++-
  .../32bit/lpddr4_ddr_controller_macros.h  | 7792 
  .../32bit}/lpddr4_phy_core_macros.h   | 1397 ++-
  drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h | 5396 
  drivers/ram/k3-ddrss/Makefile |   17 +
  drivers/ram/k3-ddrss/cps_drv_lpddr4.h |  102 +
  .../k3-j721e-ddrss.c => k3-ddrss/k3-ddrss.c}  |  289 +-
  drivers/ram/k3-ddrss/lpddr4.c | 1079 +++
  drivers/ram/k3-ddrss/lpddr4.h |   73 +
  drivers/ram/k3-ddrss/lpddr4_16bit.c   |  396 +
  drivers/ram/k3-ddrss/lpddr4_16bit.h   |   33 +
  .../k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c | 1309 +++
  drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h|  257 +
  drivers/ram/k3-ddrss/lpddr4_32bit.c   |  302 +
  drivers/ram/k3-ddrss/lpddr4_32bit.h   |   30 +
  .../k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c | 1548 
  drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h|  223 +
  drivers/ram/k3-ddrss/lpddr4_if.h  |  144 +
  drivers/ram

Re: [PATCH] configs: ti: enable TFTP_SIZE

[Tero Kristo]

On 11/05/2021 15:07, Tom Rini wrote:

On Tue, May 11, 2021 at 10:40:15AM +0300, Tero Kristo wrote:


This fits the TFTP progress bar on single line based on the size of the
file being downloaded, reducing unnecessary spam and also making it
easier to track the download progress.

Signed-off-by: Tero Kristo 
---
  include/configs/ti_armv7_common.h | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/include/configs/ti_armv7_common.h 
b/include/configs/ti_armv7_common.h
index f13e9e5264..f40089a3fd 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -205,6 +205,8 @@
"run netloadfdt; " \
"run netargs; " \
"bootz ${loadaddr} - ${fdtaddr}\0"
+
+#define CONFIG_TFTP_TSIZE
  #else
  #define NETARGS ""
  #endif


That's pretty handy.  Can you please convert it to Kconfig (it should go
in net/Kconfig) and default y if ARCH_OMAP2PLUS should be fine.  Thanks.



Yea, I can take a shot at that.

-Tero

[PATCHv4 24/26] configs: j7200_evm_r5: Enable raw access power management features

[Tero Kristo]

From: Dave Gerlach 

Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.

Signed-off-by: Dave Gerlach 
Signed-off-by: Tero Kristo 
---
 configs/j7200_evm_r5_defconfig | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index b20698fd0e..97eb1b3c9a 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -75,7 +75,7 @@ CONFIG_SPL_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
+# CONFIG_CLK_TI_SCI is not set
 CONFIG_DMA_CHANNELS=y
 CONFIG_TI_K3_NAVSS_UDMA=y
 CONFIG_TI_SCI_PROTOCOL=y
@@ -111,7 +111,7 @@ CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_GENERIC is not set
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
+# CONFIG_TI_SCI_POWER_DOMAIN is not set
 CONFIG_K3_SYSTEM_CONTROLLER=y
 CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_DM_RESET=y
@@ -143,3 +143,13 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x6164
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_K3_DM_FW=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
-- 
2.17.1

[PATCHv4 26/26] arm: dts: k3-j72xx: correct MCU timer1 frequency

[Tero Kristo]

MCU timer1 is used as the tick timer for MCU R5 SPL, and the
clock-frequency defined in DT appears to be incorrect at the moment.
Actual clock source for the timer is MCU_SYSCLK0 / 4 which is 250MHz.

Earlier setup of 25MHz went unnoticed, as there was a separate issue
with omap-timer, which caused an error to the clock by a factor of 8
with j7 devices. This problem surfaced once the omap-timer was fixed.

Signed-off-by: Tero Kristo 
---
 arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 2 +-
 arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi 
b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index bd037be350..c3aae65b39 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -33,7 +33,7 @@
compatible = "ti,omap5430-timer";
reg = <0x0 0x4040 0x0 0x80>;
ti,timer-alwon;
-   clock-frequency = <2500>;
+   clock-frequency = <25000>;
u-boot,dm-spl;
};
 
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi 
b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 3384ed9f3a..1135de5a92 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -46,7 +46,7 @@
compatible = "ti,omap5430-timer";
reg = <0x0 0x4040 0x0 0x80>;
ti,timer-alwon;
-   clock-frequency = <2500>;
+   clock-frequency = <25000>;
u-boot,dm-spl;
};
 
-- 
2.17.1

[PATCHv4 25/26] board: ti: j72xx: README: update build instructions and image formats

[Tero Kristo]

From: Tero Kristo 

Update build instructions and image formats based on HSM rearch. A new
DM image is added into the build, which gets executed right after R5
SPL finishes its job.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 board/ti/j721e/README | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/board/ti/j721e/README b/board/ti/j721e/README
index c33afa496e..b1c9145c92 100644
--- a/board/ti/j721e/README
+++ b/board/ti/j721e/README
@@ -73,12 +73,12 @@ support. Below is the pictorial representation of boot flow:
 || | |   +-+ |   | 
  |
 || |<|---| Start A72   | |   | 
  |
 || | |   | and jump to | |   | 
  |
-|| | |   | next image  | |   | 
  |
+|| | |   | DM fw image | |   | 
  |
 || | |   +-+ |   | 
  |
 || | |   | +---+ | 
  |
 || |-|---|>| Reset rls | | 
  |
 || | |   | +---+ | 
  |
-||  DMSC   | |   |  :| 
  |
+||  TIFS   | |   |  :| 
  |
 ||Services | |   | +---+ | 
  |
 || |<|---|>|*ATF/OPTEE*| | 
  |
 || | |   | +---+ | 
  |
@@ -154,7 +154,7 @@ $ make CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5
 
 4.2. A72:
 $ make CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=/tmp/a72
-$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin O=/tmp/a72
+$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin DM= 
O=/tmp/a72
 
 Target Images
 --
@@ -197,6 +197,9 @@ Image formats:
 | | A72 OPTEE | |
 | +---+ |
 | |   | |
+| |  R5 DM FW | |
+| +---+ |
+| |   | |
 | |  A72 SPL  | |
 | +---+ |
 | |   | |
-- 
2.17.1

[PATCHv4 22/26] arm: mach-k3: j721e_init: Force early probe of clk-k3 driver

[Tero Kristo]

From: Dave Gerlach 

Force the clk-k3 driver to probe early during R5 SPL boot to ensure the
default system clock configuration is completed. Many other drivers
assume a default state of the clock tree and it is currently possible
for them to probe before clk-k3 depending on the exact system
configuration.

Signed-off-by: Dave Gerlach 
Reported-by: Keerthy 
Tested-by: Keerthy 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/j721e_init.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 1a4f796e5e..b5268372dd 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -180,6 +180,18 @@ void board_init_f(ulong dummy)
k3_sysfw_loader(is_rom_loaded_sysfw(),
k3_mmc_stop_clock, k3_mmc_restart_clock);
 
+#ifdef CONFIG_SPL_CLK_K3
+   /*
+* Force probe of clk_k3 driver here to ensure basic default clock
+* configuration is always done.
+*/
+   ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(ti_clk),
+ );
+   if (ret)
+   panic("Failed to initialize clk-k3!\n");
+#endif
+
/* Prepare console output */
preloader_console_init();
 
-- 
2.17.1

[PATCHv4 21/26] arm: mach-k3: sysfw-loader: pass boardcfg to sciserver

[Tero Kristo]

From: Tero Kristo 

Copy the contents of the board config loaded from sysfw.itb into an
EXTBOOT shared memory buffer that gets passed to sciserver. This only
needs to be done if EXTBOOT area has not been populated by ROM code yet.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/sysfw-loader.c | 103 
 1 file changed, 103 insertions(+)

diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index c6af205163..ac719cd46f 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -40,6 +40,46 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 #define K3_SYSTEM_CONTROLLER_RPROC_ID  0
 
+#define COMMON_HEADER_ADDRESS  0x41cffb00
+#define BOARDCFG_ADDRESS   0x41c8
+
+#define COMP_TYPE_SBL_DATA 0x11
+#define DESC_TYPE_BOARDCFG_PM_INDEX0x2
+#define DESC_TYPE_BOARDCFG_RM_INDEX0x3
+
+#define BOARD_CONFIG_RM_DESC_TYPE  0x000c
+#define BOARD_CONFIG_PM_DESC_TYPE  0x000e
+
+struct extboot_comp {
+   u32 comp_type;
+   u32 boot_core;
+   u32 comp_opts;
+   u64 dest_addr;
+   u32 comp_size;
+};
+
+struct extboot_header {
+   u8 magic[8];
+   u32 num_comps;
+   struct extboot_comp comps[5];
+   u32 reserved;
+};
+
+struct bcfg_desc {
+   u16 type;
+   u16 offset;
+   u16 size;
+   u8 devgrp;
+   u8 reserved;
+} __packed;
+
+struct bcfg_header {
+   u8 num_elems;
+   u8 sw_rev;
+   struct bcfg_desc descs[4];
+   u16 reserved;
+} __packed;
+
 static bool sysfw_loaded;
 static void *sysfw_load_address;
 
@@ -131,6 +171,15 @@ static void k3_sysfw_configure_using_fit(void *fit,
const void *cfg_fragment_addr;
size_t cfg_fragment_size;
int ret;
+#ifdef CONFIG_K3_DM_FW
+   u8 *buf;
+   struct extboot_header *common_header;
+   struct bcfg_header *bcfg_header;
+   struct extboot_comp *comp;
+   struct bcfg_desc *desc;
+   u32 addr;
+   bool copy_bcfg = false;
+#endif
 
/* Find the node holding the images information */
images = fdt_path_offset(fit, FIT_IMAGES_PATH);
@@ -165,6 +214,46 @@ static void k3_sysfw_configure_using_fit(void *fit,
 (u32)cfg_fragment_size);
if (ret)
panic("Failed to set board PM configuration (%d)\n", ret);
+#else
+   /* Initialize shared memory boardconfig buffer */
+   buf = (u8 *)COMMON_HEADER_ADDRESS;
+   common_header = (struct extboot_header *)buf;
+
+   /* Check if we have a struct populated by ROM in memory already */
+   if (strcmp((char *)common_header->magic, "EXTBOOT"))
+   copy_bcfg = true;
+
+   if (copy_bcfg) {
+   strcpy((char *)common_header->magic, "EXTBOOT");
+   common_header->num_comps = 1;
+
+   comp = _header->comps[0];
+
+   comp->comp_type = COMP_TYPE_SBL_DATA;
+   comp->boot_core = 0x10;
+   comp->comp_opts = 0;
+   addr = (u32)BOARDCFG_ADDRESS;
+   comp->dest_addr = addr;
+   comp->comp_size = sizeof(*bcfg_header);
+
+   bcfg_header = (struct bcfg_header *)addr;
+
+   bcfg_header->num_elems = 2;
+   bcfg_header->sw_rev = 0;
+
+   desc = _header->descs[0];
+
+   desc->type = BOARD_CONFIG_PM_DESC_TYPE;
+   desc->offset = sizeof(*bcfg_header);
+   desc->size = cfg_fragment_size;
+   comp->comp_size += desc->size;
+   desc->devgrp = 0;
+   desc->reserved = 0;
+   memcpy((u8 *)bcfg_header + desc->offset, cfg_fragment_addr,
+  cfg_fragment_size);
+
+   bcfg_header->descs[1].offset = desc->offset + desc->size;
+   }
 #endif
 
/* Extract resource management (RM) specific configuration from FIT */
@@ -174,6 +263,20 @@ static void k3_sysfw_configure_using_fit(void *fit,
panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_RM,
  ret);
 
+#ifdef CONFIG_K3_DM_FW
+   if (copy_bcfg) {
+   desc = _header->descs[1];
+
+   desc->type = BOARD_CONFIG_RM_DESC_TYPE;
+   desc->size = cfg_fragment_size;
+   comp->comp_size += desc->size;
+   desc->devgrp = 0;
+   desc->reserved = 0;
+   memcpy((u8 *)bcfg_header + desc->offset, cfg_fragment_addr,
+  cfg_fragment_size);
+   }
+#endif
+
/* Apply resource management (RM) configuration to SYSFW */
ret = board_ops->board_config_rm(ti_sci,
 (u64)(u32)cfg_fragment_addr,
-- 
2.17.1

[PATCHv4 23/26] configs: j721e_evm_r5: Enable raw access power management features

[Tero Kristo]

From: Tero Kristo 

Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 configs/j721e_evm_r5_defconfig | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 7b4f0afce6..0d21904a00 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -72,7 +72,7 @@ CONFIG_SPL_REGMAP=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
+# CONFIG_CLK_TI_SCI is not set
 CONFIG_DMA_CHANNELS=y
 CONFIG_TI_K3_NAVSS_UDMA=y
 CONFIG_TI_SCI_PROTOCOL=y
@@ -103,7 +103,7 @@ CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_GENERIC is not set
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
+# CONFIG_TI_SCI_POWER_DOMAIN is not set
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_TPS65941=y
 CONFIG_DM_REGULATOR=y
@@ -141,3 +141,11 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x6163
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_K3_DM_FW=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
-- 
2.17.1

[PATCHv4 17/26] arm: mach-k3: Add platform data for j721e and j7200

[Tero Kristo]

From: Dave Gerlach 

Add platform clock and powerdomain data for J721e and J7200. This data
is used by the corresponding drivers to register all the required device
clocks and powerdomains.

Signed-off-by: Dave Gerlach 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/Makefile |   2 +-
 arch/arm/mach-k3/j7200/Makefile   |   5 +
 arch/arm/mach-k3/j7200/clk-data.c | 547 +
 arch/arm/mach-k3/j7200/dev-data.c |  77 +++
 arch/arm/mach-k3/j721e/Makefile   |   5 +
 arch/arm/mach-k3/j721e/clk-data.c | 781 ++
 arch/arm/mach-k3/j721e/dev-data.c |  75 +++
 7 files changed, 1491 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-k3/j7200/Makefile
 create mode 100644 arch/arm/mach-k3/j7200/clk-data.c
 create mode 100644 arch/arm/mach-k3/j7200/dev-data.c
 create mode 100644 arch/arm/mach-k3/j721e/Makefile
 create mode 100644 arch/arm/mach-k3/j721e/clk-data.c
 create mode 100644 arch/arm/mach-k3/j721e/dev-data.c

diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 7572f56925..534ddfcd49 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -4,7 +4,7 @@
 #  Lokesh Vutla 
 
 obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
-obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
+obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
 obj-$(CONFIG_ARM64) += arm64-mmu.o
 obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
 obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
diff --git a/arch/arm/mach-k3/j7200/Makefile b/arch/arm/mach-k3/j7200/Makefile
new file mode 100644
index 00..ff9abd78ea
--- /dev/null
+++ b/arch/arm/mach-k3/j7200/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/j7200/clk-data.c 
b/arch/arm/mach-k3/j7200/clk-data.c
new file mode 100644
index 00..93c067079a
--- /dev/null
+++ b/arch/arm/mach-k3/j7200/clk-data.c
@@ -0,0 +1,547 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J7200 specific clock platform data
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+   "osc_19_2_mhz",
+   "osc_20_mhz",
+   "osc_24_mhz",
+   "osc_25_mhz",
+   "osc_26_mhz",
+   "osc_27_mhz",
+};
+
+static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
+   "board_0_mcu_ospi0_dqs_out",
+   "fss_mcu_0_ospi_0_ospi_oclk_clk",
+};
+
+static const char * const wkup_fref_clksel_out0_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const main_pll_hfosc_sel_out1_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "board_0_hfosc1_clk_out",
+};
+
+static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
+   "wkup_fref_clksel_out0",
+   "hsdiv1_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
+   "hsdiv4_16fft_mcu_1_hsdivout4_clk",
+   "hsdiv4_16fft_mcu_2_hsdivout4_clk",
+};
+
+static const char * const mcuusart_clk_sel_out0_parents[] = {
+   "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+   "postdiv2_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_gpio0_clksel_out0_parents[] = {
+   "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+   "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+   "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
+   "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = {
+   "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+   "gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out0_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out12_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out14_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out2_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out3_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out4_parents[] = {
+   "gluelogic_hfosc0_clkout",
+   "b

[PATCHv4 20/26] arm: mach-k3: common: Drop main r5 start

[Tero Kristo]

From: Dave Gerlach 

Only start-up the non-linux remote cores if we are running in legacy
boot mode. HSM rearch is not yet supporting this.

Signed-off-by: Dave Gerlach 
Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/common.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index a5d6a10dc7..2b8c09a650 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -212,11 +212,12 @@ void __noreturn jump_to_image_no_args(struct 
spl_image_info *spl_image)
panic("rproc failed to be initialized (%d)\n", ret);
 
init_env();
-   start_non_linux_remote_cores();
-   if (!fit_image_info[IMAGE_ID_DM_FW].image_start)
+
+   if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
+   start_non_linux_remote_cores();
size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
 );
-
+   }
 
/*
 * It is assumed that remoteproc device 1 is the corresponding
-- 
2.17.1

[PATCHv4 19/26] arm: mach-k3: do board config for PM only if supported

[Tero Kristo]

From: Tero Kristo 

If the raw PM support is built in, we are operating in the split
firmware approach mode where PM support is not available. In this
case, skip the board config for this.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/sysfw-loader.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 0bacfc4d07..c6af205163 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -159,11 +159,13 @@ static void k3_sysfw_configure_using_fit(void *fit,
  ret);
 
/* Apply power/clock (PM) specific configuration to SYSFW */
+#ifndef CONFIG_K3_DM_FW
ret = board_ops->board_config_pm(ti_sci,
 (u64)(u32)cfg_fragment_addr,
 (u32)cfg_fragment_size);
if (ret)
panic("Failed to set board PM configuration (%d)\n", ret);
+#endif
 
/* Extract resource management (RM) specific configuration from FIT */
ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM,
-- 
2.17.1

[PATCHv4 16/26] tools: k3_fit_atf: add DM binary to the FIT image

[Tero Kristo]

From: Tero Kristo 

Add DM (device manager) firmware image to the fit image that is loaded by
R5 SPL. This is needed with the HSM rearch where the firmware allocation
has been changed slightly.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/config.mk |  4 
 tools/k3_fit_atf.sh| 19 ++-
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk
index 41fee2b5a1..503ece4520 100644
--- a/arch/arm/mach-k3/config.mk
+++ b/arch/arm/mach-k3/config.mk
@@ -49,6 +49,10 @@ endif
 
 ifdef CONFIG_ARM64
 
+ifeq ($(CONFIG_SOC_K3_J721E),)
+export DM := /dev/null
+endif
+
 ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
 SPL_ITS := u-boot-spl-k3_HS.its
 $(SPL_ITS): export IS_HS=1
diff --git a/tools/k3_fit_atf.sh b/tools/k3_fit_atf.sh
index 4e9f69c087..c0940a2fcc 100755
--- a/tools/k3_fit_atf.sh
+++ b/tools/k3_fit_atf.sh
@@ -21,6 +21,13 @@ if [ ! -f $TEE ]; then
TEE=/dev/null
 fi
 
+[ -z "$DM" ] && DM="dm.bin"
+
+if [ ! -e $DM ]; then
+   echo "WARNING DM file $DM NOT found, resulting might be non-functional" 
>&2
+   DM=/dev/null
+fi
+
 if [ ! -z "$IS_HS" ]; then
HS_APPEND=_HS
 fi
@@ -53,6 +60,16 @@ cat << __HEADER_EOF
load = <0x9e80>;
entry = <0x9e80>;
};
+   dm {
+   description = "DM binary";
+   data = /incbin/("$DM");
+   type = "firmware";
+   arch = "arm32";
+   compression = "none";
+   os = "DM";
+   load = <0xa000>;
+   entry = <0xa000>;
+   };
spl {
description = "SPL (64-bit)";
data = /incbin/("spl/u-boot-spl-nodtb.bin$HS_APPEND");
@@ -91,7 +108,7 @@ do
$(basename $dtname) {
description = "$(basename $dtname .dtb)";
firmware = "atf";
-   loadables = "tee", "spl";
+   loadables = "tee", "dm", "spl";
fdt = "$(basename $dtname)";
};
 __CONF_SECTION_EOF
-- 
2.17.1

[PATCHv4 18/26] arm: mach-k3: add support for detecting firmware images from FIT

[Tero Kristo]

From: Tero Kristo 

Add callback routines for parsing the firmware info from FIT image, and
use the data to boot up ATF and the MCU R5 firmware.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/common.c   | 80 +
 arch/arm/mach-k3/common.h   |  1 +
 arch/arm/mach-k3/security.c |  3 +-
 3 files changed, 75 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 9191f686f0..a5d6a10dc7 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -28,6 +28,27 @@
 #include 
 #include 
 
+#ifdef CONFIG_SYS_K3_SPL_ATF
+enum {
+   IMAGE_ID_ATF,
+   IMAGE_ID_OPTEE,
+   IMAGE_ID_SPL,
+   IMAGE_ID_DM_FW,
+   IMAGE_AMT,
+};
+
+#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
+static const char *image_os_match[IMAGE_AMT] = {
+   "arm-trusted-firmware",
+   "tee",
+   "U-Boot",
+   "DM",
+};
+#endif
+
+static struct image_info fit_image_info[IMAGE_AMT];
+#endif
+
 struct ti_sci_handle *get_ti_sci_handle(void)
 {
struct udevice *dev;
@@ -181,7 +202,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info 
*spl_image)
typedef void __noreturn (*image_entry_noargs_t)(void);
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
u32 loadaddr = 0;
-   int ret, size;
+   int ret, size = 0;
 
/* Release all the exclusive devices held by SPL before starting ATF */
ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
@@ -192,15 +213,20 @@ void __noreturn jump_to_image_no_args(struct 
spl_image_info *spl_image)
 
init_env();
start_non_linux_remote_cores();
-   size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
-);
+   if (!fit_image_info[IMAGE_ID_DM_FW].image_start)
+   size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
+);
 
 
/*
 * It is assumed that remoteproc device 1 is the corresponding
 * Cortex-A core which runs ATF. Make sure DT reflects the same.
 */
-   ret = rproc_load(1, spl_image->entry_point, 0x200);
+   if (!fit_image_info[IMAGE_ID_ATF].image_start)
+   fit_image_info[IMAGE_ID_ATF].image_start =
+   spl_image->entry_point;
+
+   ret = rproc_load(1, fit_image_info[IMAGE_ID_ATF].image_start, 0x200);
if (ret)
panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
 
@@ -210,7 +236,8 @@ void __noreturn jump_to_image_no_args(struct spl_image_info 
*spl_image)
ret = rproc_start(1);
if (ret)
panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
-   if (!(size > 0 && valid_elf_image(loadaddr))) {
+   if (!fit_image_info[IMAGE_ID_DM_FW].image_len &&
+   !(size > 0 && valid_elf_image(loadaddr))) {
debug("Shutting down...\n");
release_resources_for_core_shutdown();
 
@@ -218,13 +245,52 @@ void __noreturn jump_to_image_no_args(struct 
spl_image_info *spl_image)
asm volatile("wfe");
}
 
-   image_entry_noargs_t image_entry =
-   (image_entry_noargs_t)load_elf_image_phdr(loadaddr);
+   if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
+   loadaddr = load_elf_image_phdr(loadaddr);
+   } else {
+   loadaddr = fit_image_info[IMAGE_ID_DM_FW].image_start;
+   if (valid_elf_image(loadaddr))
+   loadaddr = load_elf_image_phdr(loadaddr);
+   }
+
+   debug("%s: jumping to address %x\n", __func__, loadaddr);
+
+   image_entry_noargs_t image_entry = (image_entry_noargs_t)loadaddr;
 
image_entry();
 }
 #endif
 
+#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
+{
+   int len;
+   int i;
+   const char *os;
+   u32 addr;
+
+   os = fdt_getprop(fit, node, "os", );
+   addr = fdt_getprop_u32_default_node(fit, node, 0, "entry", -1);
+
+   debug("%s: processing image: addr=%x, size=%d, os=%s\n", __func__,
+ addr, *p_size, os);
+
+   for (i = 0; i < IMAGE_AMT; i++) {
+   if (!strcmp(os, image_os_match[i])) {
+   fit_image_info[i].image_start = addr;
+   fit_image_info[i].image_len = *p_size;
+   debug("%s: matched image for ID %d\n", __func__, i);
+   break;
+   }
+   }
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+   ti_secure_image_post_process(p_image, p_size);
+#endif
+}
+#endif
+
 #if defined(CONFIG_OF_LIBFD

[PATCHv4 13/26] clk: add support for TI K3 SoC clocks

[Tero Kristo]

From: Tero Kristo 

Add driver to support TI K3 generation SoC clocks. This driver registers
the clocks provided via platform data, and adds support for controlling
the clocks via DT handles.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/ti/Kconfig  |  12 ++
 drivers/clk/ti/Makefile |   1 +
 drivers/clk/ti/clk-k3.c | 374 
 include/k3-clk.h| 162 +
 4 files changed, 549 insertions(+)
 create mode 100644 drivers/clk/ti/clk-k3.c

diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index a8ec4f541a..fbcdefd889 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -53,3 +53,15 @@ config SPL_CLK_K3_PLL
depends on CLK && LIB_RATIONAL && SPL
help
  Enables PLL clock support for K3 SoC family of devices.
+
+config CLK_K3
+   bool "Clock support for K3 SoC family of devices"
+   depends on CLK
+   help
+ Enables the clock translation layer from DT to device clocks.
+
+config SPL_CLK_K3
+   bool "Clock support for K3 SoC family of devices"
+   depends on CLK && SPL
+   help
+ Enables the clock translation layer from DT to device clocks.
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 47839213e5..07aa9a53e0 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o
 obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
 obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o
 obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_K3) += clk-k3.o
diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
new file mode 100644
index 00..ec262d5c21
--- /dev/null
+++ b/drivers/clk/ti/clk-k3.c
@@ -0,0 +1,374 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 clock driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "k3-clk.h"
+
+#define PLL_MIN_FREQ   8
+#define PLL_MAX_FREQ   32UL
+#define PLL_MAX_DIV127
+
+/**
+ * struct clk_map - mapping from dev/clk id tuples towards physical clocks
+ * @dev_id: device ID for the clock
+ * @clk_id: clock ID for the clock
+ * @clk: pointer to the registered clock entry for the mapping
+ */
+struct clk_map {
+   u16 dev_id;
+   u32 clk_id;
+   struct clk *clk;
+};
+
+/**
+ * struct ti_clk_data - clock controller information structure
+ * @map: mapping from dev/clk id tuples to physical clock entries
+ * @size: number of entries in the map
+ */
+struct ti_clk_data {
+   struct clk_map *map;
+   int size;
+};
+
+static ulong osc_freq;
+
+static void clk_add_map(struct ti_clk_data *data, struct clk *clk,
+   u32 dev_id, u32 clk_id)
+{
+   struct clk_map *map;
+
+   debug("%s: added clk=%p, data=%p, dev=%d, clk=%d\n", __func__,
+ clk, data, dev_id, clk_id);
+   if (!clk)
+   return;
+
+   map = data->map + data->size++;
+
+   map->dev_id = dev_id;
+   map->clk_id = clk_id;
+   map->clk = clk;
+}
+
+static const struct soc_attr ti_k3_soc_clk_data[] = {
+#ifdef CONFIG_SOC_K3_J721E
+   {
+   .family = "J721E",
+   .data = _clk_platdata,
+   },
+   {
+   .family = "J7200",
+   .data = _clk_platdata,
+   },
+#endif
+   { /* sentinel */ }
+};
+
+static int ti_clk_probe(struct udevice *dev)
+{
+   struct ti_clk_data *data = dev_get_priv(dev);
+   struct clk *clk;
+   const char *name;
+   const struct clk_data *ti_clk_data;
+   int i, j;
+   const struct soc_attr *soc_match_data;
+   const struct ti_k3_clk_platdata *pdata;
+
+   debug("%s(dev=%p)\n", __func__, dev);
+
+   soc_match_data = soc_device_match(ti_k3_soc_clk_data);
+   if (!soc_match_data)
+   return -ENODEV;
+
+   pdata = (const struct ti_k3_clk_platdata *)soc_match_data->data;
+
+   data->map = kcalloc(pdata->soc_dev_clk_data_cnt, sizeof(*data->map),
+   GFP_KERNEL);
+   data->size = 0;
+
+   for (i = 0; i < pdata->clk_list_cnt; i++) {
+   ti_clk_data = >clk_list[i];
+
+   switch (ti_clk_data->type) {
+   case CLK_TYPE_FIXED_RATE:
+   name = ti_clk_data->clk.fixed_rate.name;
+   clk = clk_register_fixed_rate(NULL,
+ name,
+ 
ti_clk_data->clk.fixed_rate.rate);
+   break;
+   case CLK_TYPE_DIV:
+   name = ti_clk_data->clk.div.name;
+   clk = clk_register_divider(NULL, nam

[PATCHv4 15/26] cmd: ti: pd: Add debug command for K3 power domains

[Tero Kristo]

From: Tero Kristo 

Add support command for debugging K3 power domains. This is useful with
the HSM rearch setup, where power domains are directly controlled by SPL
instead of going through the TI SCI layer. The debugging support is only
available in the u-boot codebase though, so the raw register access
power domain layer must be enabled on u-boot side for this to work. By
default, u-boot side uses the TI SCI layer, and R5 SPL only uses the
direct access methods.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 cmd/ti/Kconfig |   8 ++
 cmd/ti/Makefile|   1 +
 cmd/ti/pd.c| 185 +
 drivers/power/domain/ti-power-domain.c |   6 +-
 include/k3-dev.h   |   9 ++
 5 files changed, 206 insertions(+), 3 deletions(-)
 create mode 100644 cmd/ti/pd.c

diff --git a/cmd/ti/Kconfig b/cmd/ti/Kconfig
index efeff0d482..db557445a8 100644
--- a/cmd/ti/Kconfig
+++ b/cmd/ti/Kconfig
@@ -7,4 +7,12 @@ config CMD_DDR3
   supports memory verification, memory comapre and ecc
   verification if supported.
 
+config CMD_PD
+   bool "command for verifying power domains"
+   depends on TI_POWER_DOMAIN
+   help
+  Debug command for K3 power domains. For this to work, the
+  K3 power domain driver must be enabled for the u-boot; by
+  default it is only enabled for SPL.
+
 endmenu
diff --git a/cmd/ti/Makefile b/cmd/ti/Makefile
index 16fbade9ed..045593396b 100644
--- a/cmd/ti/Makefile
+++ b/cmd/ti/Makefile
@@ -5,4 +5,5 @@ obj- += dummy.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_CMD_DDR3) += ddr3.o
+obj-$(CONFIG_CMD_PD) += pd.o
 endif
diff --git a/cmd/ti/pd.c b/cmd/ti/pd.c
new file mode 100644
index 00..a53ccdcc40
--- /dev/null
+++ b/cmd/ti/pd.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Power Domain test commands
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated, 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static const struct udevice_id ti_pd_of_match[] = {
+   { .compatible = "ti,sci-pm-domain" },
+   { /* sentinel */ }
+};
+
+static struct ti_k3_pd_platdata *ti_pd_find_data(void)
+{
+   struct udevice *dev;
+   int i = 0;
+
+   while (1) {
+   uclass_get_device(UCLASS_POWER_DOMAIN, i++, );
+   if (!dev)
+   return NULL;
+
+   if (device_is_compatible(dev,
+ti_pd_of_match[0].compatible))
+   return  dev_get_priv(dev);
+   }
+
+   return NULL;
+}
+
+static void dump_lpsc(struct ti_k3_pd_platdata *data, struct ti_pd *pd)
+{
+   int i;
+   struct ti_lpsc *lpsc;
+   u8 state;
+   static const char * const lpsc_states[] = {
+   "swrstdis", "syncrst", "disable", "enable", "autosleep",
+   "autowake", "unknown",
+   };
+
+   for (i = 0; i < data->num_lpsc; i++) {
+   lpsc = >lpsc[i];
+   if (lpsc->pd != pd)
+   continue;
+   state = lpsc_get_state(lpsc);
+   if (state > ARRAY_SIZE(lpsc_states))
+   state = ARRAY_SIZE(lpsc_states) - 1;
+   printf("LPSC%d: state=%s, usecount=%d\n",
+  lpsc->id, lpsc_states[state], lpsc->usecount);
+   }
+}
+
+static void dump_pd(struct ti_k3_pd_platdata *data, struct ti_psc *psc)
+{
+   int i;
+   struct ti_pd *pd;
+   u8 state;
+   static const char * const pd_states[] = {
+   "off", "on", "unknown"
+   };
+
+   for (i = 0; i < data->num_pd; i++) {
+   pd = >pd[i];
+   if (pd->psc != psc)
+   continue;
+   state = ti_pd_state(pd);
+   if (state > ARRAY_SIZE(pd_states))
+   state = ARRAY_SIZE(pd_states) - 1;
+   printf("  PD%d: state=%s, usecount=%d:\n",
+  pd->id, pd_states[state], pd->usecount);
+   dump_lpsc(data, pd);
+   }
+}
+
+static void dump_psc(struct ti_k3_pd_platdata *data)
+{
+   int i;
+   struct ti_psc *psc;
+
+   for (i = 0; i < data->num_psc; i++) {
+   psc = >psc[i];
+   printf("PSC%d [%p]:\n", psc->id, psc->base);
+   dump_pd(data, psc);
+   }
+}
+
+static int do_pd_dump(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+   struct ti_k3_pd_platdata *data;
+
+   data = ti_pd_find_data();
+   if (!data)
+   return CMD_RET_FAILURE;
+
+   dump_psc(data);
+
+   return 0;
+}
+
+static int do_pd_endis(int argc, char *const argv[], u8 state)
+{
+   u32 ps

[PATCHv4 14/26] power: domain: Introduce driver for raw TI K3 PDs

[Tero Kristo]

From: Tero Kristo 

Normally, power domains are handled via TI-SCI in K3 SoCs. However,
SPL is not going to have access to sysfw resources, so it must control
them directly. Add driver for supporting this.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/power/domain/Kconfig   |   7 +
 drivers/power/domain/Makefile  |   1 +
 drivers/power/domain/ti-power-domain.c | 368 +
 include/k3-dev.h   |  76 +
 4 files changed, 452 insertions(+)
 create mode 100644 drivers/power/domain/ti-power-domain.c
 create mode 100644 include/k3-dev.h

diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index a0fd980752..99b3f9ae71 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -72,4 +72,11 @@ config TI_SCI_POWER_DOMAIN
help
  Generic power domain implementation for TI devices implementing the
  TI SCI protocol.
+
+config TI_POWER_DOMAIN
+   bool "Enable the TI K3 Power domain driver"
+   depends on POWER_DOMAIN && ARCH_K3
+   help
+ Generic power domain implementation for TI K3 devices.
+
 endmenu
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 45bf9f6383..3d1e5f073c 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
 obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
 obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o
 obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o
+obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o
diff --git a/drivers/power/domain/ti-power-domain.c 
b/drivers/power/domain/ti-power-domain.c
new file mode 100644
index 00..e418a7b996
--- /dev/null
+++ b/drivers/power/domain/ti-power-domain.c
@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments power domain driver
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PSC_PTCMD  0x120
+#define PSC_PTSTAT 0x128
+#define PSC_PDSTAT 0x200
+#define PSC_PDCTL  0x300
+#define PSC_MDSTAT 0x800
+#define PSC_MDCTL  0xa00
+
+#define PDCTL_STATE_MASK   0x1
+#define PDCTL_STATE_OFF0x0
+#define PDCTL_STATE_ON 0x1
+
+#define MDSTAT_STATE_MASK  0x3f
+#define MDSTAT_BUSY_MASK   0x30
+#define MDSTAT_STATE_SWRSTDISABLE  0x0
+#define MDSTAT_STATE_ENABLE0x3
+
+#define LPSC_TIMEOUT   1000
+#define PD_TIMEOUT 1000
+
+static u32 psc_read(struct ti_psc *psc, u32 reg)
+{
+   u32 val;
+
+   val = readl(psc->base + reg);
+   debug("%s: 0x%x from %p\n", __func__, val, psc->base + reg);
+   return val;
+}
+
+static void psc_write(u32 val, struct ti_psc *psc, u32 reg)
+{
+   debug("%s: 0x%x to %p\n", __func__, val, psc->base + reg);
+   writel(val, psc->base + reg);
+}
+
+static u32 pd_read(struct ti_pd *pd, u32 reg)
+{
+   return psc_read(pd->psc, reg + 4 * pd->id);
+}
+
+static void pd_write(u32 val, struct ti_pd *pd, u32 reg)
+{
+   psc_write(val, pd->psc, reg + 4 * pd->id);
+}
+
+static u32 lpsc_read(struct ti_lpsc *lpsc, u32 reg)
+{
+   return psc_read(lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static void lpsc_write(u32 val, struct ti_lpsc *lpsc, u32 reg)
+{
+   psc_write(val, lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static const struct soc_attr ti_k3_soc_pd_data[] = {
+#ifdef CONFIG_SOC_K3_J721E
+   {
+   .family = "J721E",
+   .data = _pd_platdata,
+   },
+   {
+   .family = "J7200",
+   .data = _pd_platdata,
+   },
+#endif
+   { /* sentinel */ }
+};
+
+static int ti_power_domain_probe(struct udevice *dev)
+{
+   struct ti_k3_pd_platdata *data = dev_get_priv(dev);
+   const struct soc_attr *soc_match_data;
+   const struct ti_k3_pd_platdata *pdata;
+
+   printf("%s(dev=%p)\n", __func__, dev);
+
+   if (!data)
+   return -ENOMEM;
+
+   soc_match_data = soc_device_match(ti_k3_soc_pd_data);
+   if (!soc_match_data)
+   return -ENODEV;
+
+   pdata = (const struct ti_k3_pd_platdata *)soc_match_data->data;
+
+   data->psc = pdata->psc;
+   data->pd = pdata->pd;
+   data->lpsc = pdata->lpsc;
+   data->devs = pdata->devs;
+   data->num_psc = pdata->num_psc;
+   data->num_pd = pdata->num_pd;
+   data->num_lpsc = pdata->num_lpsc;
+   data->num_devs = pdata->num_devs;
+
+   return 0;
+}
+
+static int ti_pd_wait(struct ti_pd *p

[PATCHv4 12/26] clk: add support for TI K3 SoC PLL

[Tero Kristo]

From: Tero Kristo 

Add support for TI K3 SoC PLLs. This clock type supports
enabling/disabling/setting and querying the clock rate for the PLL. The
euclidean library routine is used to calculate divider/multiplier rates
for the PLLs.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/ti/Kconfig  |  12 ++
 drivers/clk/ti/Makefile |   1 +
 drivers/clk/ti/clk-k3-pll.c | 283 
 include/k3-clk.h|  15 ++
 4 files changed, 311 insertions(+)
 create mode 100644 drivers/clk/ti/clk-k3-pll.c
 create mode 100644 include/k3-clk.h

diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index 2dc86d44a9..a8ec4f541a 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -41,3 +41,15 @@ config CLK_TI_SCI
  This enables the clock driver support over TI System Control Interface
  available on some new TI's SoCs. If you wish to use clock resources
  managed by the TI System Controller, say Y here. Otherwise, say N.
+
+config CLK_K3_PLL
+   bool "PLL clock support for K3 SoC family of devices"
+   depends on CLK && LIB_RATIONAL
+   help
+ Enables PLL clock support for K3 SoC family of devices.
+
+config SPL_CLK_K3_PLL
+   bool "PLL clock support for K3 SoC family of devices"
+   depends on CLK && LIB_RATIONAL && SPL
+   help
+ Enables PLL clock support for K3 SoC family of devices.
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 9f56b47736..47839213e5 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o
 obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o
 obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
 obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o
diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c
new file mode 100644
index 00..bf2407a020
--- /dev/null
+++ b/drivers/clk/ti/clk-k3-pll.c
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 SoC PLL clock driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "k3-clk.h"
+#include 
+
+/* 16FFT register offsets */
+#define PLL_16FFT_CFG  0x08
+#define PLL_KICK0  0x10
+#define PLL_KICK1  0x14
+#define PLL_16FFT_CTRL 0x20
+#define PLL_16FFT_STAT 0x24
+#define PLL_16FFT_FREQ_CTRL0   0x30
+#define PLL_16FFT_FREQ_CTRL1   0x34
+#define PLL_16FFT_DIV_CTRL 0x38
+
+/* CTRL register bits */
+#define PLL_16FFT_CTRL_BYPASS_EN   BIT(31)
+#define PLL_16FFT_CTRL_PLL_EN  BIT(15)
+#define PLL_16FFT_CTRL_DSM_EN  BIT(1)
+
+/* STAT register bits */
+#define PLL_16FFT_STAT_LOCKBIT(0)
+
+/* FREQ_CTRL0 bits */
+#define PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK   0xfff
+
+/* DIV CTRL register bits */
+#define PLL_16FFT_DIV_CTRL_REF_DIV_MASK0x3f
+
+#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS  24
+#define PLL_16FFT_HSDIV_CTRL_CLKOUT_EN  BIT(15)
+
+/* KICK register magic values */
+#define PLL_KICK0_VALUE0x68ef3490
+#define PLL_KICK1_VALUE0xd172bc5a
+
+/**
+ * struct ti_pll_clk - TI PLL clock data info structure
+ * @clk: core clock structure
+ * @reg: memory address of the PLL controller
+ */
+struct ti_pll_clk {
+   struct clk  clk;
+   void __iomem*reg;
+};
+
+#define to_clk_pll(_clk) container_of(_clk, struct ti_pll_clk, clk)
+
+static int ti_pll_wait_for_lock(struct clk *clk)
+{
+   struct ti_pll_clk *pll = to_clk_pll(clk);
+   u32 stat;
+   int i;
+
+   for (i = 0; i < 10; i++) {
+   stat = readl(pll->reg + PLL_16FFT_STAT);
+   if (stat & PLL_16FFT_STAT_LOCK)
+   return 0;
+   }
+
+   printf("%s: pll (%s) failed to lock\n", __func__,
+  clk->dev->name);
+
+   return -EBUSY;
+}
+
+static ulong ti_pll_clk_get_rate(struct clk *clk)
+{
+   struct ti_pll_clk *pll = to_clk_pll(clk);
+   u64 current_freq;
+   u64 parent_freq = clk_get_parent_rate(clk);
+   u32 pllm;
+   u32 plld;
+   u32 pllfm;
+   u32 ctrl;
+
+   /* Check if we are in bypass */
+   ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+   if (ctrl & PLL_16FFT_CTRL_BYPASS_EN)
+   return parent_freq;
+
+   pllm = readl(pll->reg + PLL_16FFT_FREQ_CTRL0);
+   pllfm = readl(pll->reg + PLL_16FFT_FREQ_CTRL1);
+
+   plld = readl(pll->reg + PLL_16FFT_DIV_CTRL) &
+   PLL_16FFT_DIV_CTRL_REF_DIV_MASK;
+
+   current_freq = parent_freq * pllm / plld;
+
+   if (pllfm) {
+ 

[PATCHv4 11/26] clk: fix set_rate to clean up cached rates for the hierarchy

[Tero Kristo]

From: Tero Kristo 

Clock rates are cached within the individual clock nodes, and right now
if one changes a clock rate somewhere in the middle of the tree, none
of its child clocks notice the change. To fix this, clear up all the
cached rates for us and our child clocks.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/clk-uclass.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 5ebf7a33cb..0e495a6a2e 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -565,6 +565,22 @@ ulong clk_round_rate(struct clk *clk, ulong rate)
return ops->round_rate(clk, rate);
 }
 
+static void clk_clean_rate_cache(struct clk *clk)
+{
+   struct udevice *child_dev;
+   struct clk *clkp;
+
+   if (!clk)
+   return;
+
+   clk->rate = 0;
+
+   list_for_each_entry(child_dev, >dev->child_head, sibling_node) {
+   clkp = dev_get_clk_ptr(child_dev);
+   clk_clean_rate_cache(clkp);
+   }
+}
+
 ulong clk_set_rate(struct clk *clk, ulong rate)
 {
const struct clk_ops *ops;
@@ -577,6 +593,9 @@ ulong clk_set_rate(struct clk *clk, ulong rate)
if (!ops->set_rate)
return -ENOSYS;
 
+   /* Clean up cached rates for us and all child clocks */
+   clk_clean_rate_cache(clk);
+
return ops->set_rate(clk, rate);
 }
 
-- 
2.17.1

[PATCHv4 09/26] clk: sci-clk: fix return value of set_rate

[Tero Kristo]

From: Tero Kristo 

Set rate should return the new clock rate on success, and negative error
value on failure. Fix this, as currently set_rate returns 0 on success.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/ti/clk-sci.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/ti/clk-sci.c b/drivers/clk/ti/clk-sci.c
index 6f0fdaa111..acb9eadf03 100644
--- a/drivers/clk/ti/clk-sci.c
+++ b/drivers/clk/ti/clk-sci.c
@@ -111,10 +111,12 @@ static ulong ti_sci_clk_set_rate(struct clk *clk, ulong 
rate)
 #endif
 
ret = cops->set_freq(sci, clk->id, clk->data, 0, rate, ULONG_MAX);
-   if (ret)
+   if (ret) {
dev_err(clk->dev, "%s: set_freq failed (%d)\n", __func__, ret);
+   return ret;
+   }
 
-   return ret;
+   return rate;
 }
 
 static int ti_sci_clk_set_parent(struct clk *clk, struct clk *parent)
-- 
2.17.1

[PATCHv4 10/26] clk: fix assigned-clocks to pass with deferring provider

[Tero Kristo]

From: Tero Kristo 

If a clock provider is not ready for assigning default rates/parents
during its probe, it may return -EPROBE_DEFER directly from xlate.
Handle this special case properly by skipping the entry and adjusting the
return value to pass. The defaults will be handled properly in post probe
phase then.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/clk-uclass.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index ac2b7ae84e..5ebf7a33cb 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -240,6 +240,15 @@ static int clk_set_default_parents(struct udevice *dev, 
int stage)
 
ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  index, );
+   /*
+* If the clock provider is not ready yet, let it handle
+* the re-programming later.
+*/
+   if (ret == -EPROBE_DEFER) {
+   ret = 0;
+   continue;
+   }
+
if (ret) {
debug("%s: could not get assigned clock %d for %s\n",
  __func__, index, dev_read_name(dev));
@@ -308,6 +317,15 @@ static int clk_set_default_rates(struct udevice *dev, int 
stage)
 
ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  index, );
+   /*
+* If the clock provider is not ready yet, let it handle
+* the re-programming later.
+*/
+   if (ret == -EPROBE_DEFER) {
+   ret = 0;
+   continue;
+   }
+
if (ret) {
debug("%s: could not get assigned clock %d for %s\n",
  __func__, index, dev_read_name(dev));
-- 
2.17.1

[PATCHv4 08/26] clk: add support for setting clk rate from cmdline

[Tero Kristo]

From: Tero Kristo 

Add new clk subcommand "clk setfreq", for setting up a clock rate
directly from u-boot cmdline. This is handy for any debugging purposes
towards clocks.

Acked-by: Lukasz Majewski 
Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 cmd/clk.c | 49 +++--
 1 file changed, 47 insertions(+), 2 deletions(-)

diff --git a/cmd/clk.c b/cmd/clk.c
index 0245b97136..fd7944c02e 100644
--- a/cmd/clk.c
+++ b/cmd/clk.c
@@ -98,8 +98,52 @@ static int do_clk_dump(struct cmd_tbl *cmdtp, int flag, int 
argc,
return ret;
 }
 
+struct udevice *clk_lookup(const char *name)
+{
+   int i = 0;
+   struct udevice *dev;
+
+   do {
+   uclass_get_device(UCLASS_CLK, i++, );
+   if (!strcmp(name, dev->name))
+   return dev;
+   } while (dev);
+
+   return NULL;
+}
+
+static int do_clk_setfreq(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+   struct clk *clk = NULL;
+   s32 freq;
+   struct udevice *dev;
+
+   freq = simple_strtoul(argv[2], NULL, 10);
+
+   dev = clk_lookup(argv[1]);
+
+   if (dev)
+   clk = dev_get_clk_ptr(dev);
+
+   if (!clk) {
+   printf("clock '%s' not found.\n", argv[1]);
+   return -EINVAL;
+   }
+
+   freq = clk_set_rate(clk, freq);
+   if (freq < 0) {
+   printf("set_rate failed: %d\n", freq);
+   return CMD_RET_FAILURE;
+   }
+
+   printf("set_rate returns %u\n", freq);
+   return 0;
+}
+
 static struct cmd_tbl cmd_clk_sub[] = {
U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""),
+   U_BOOT_CMD_MKENT(setfreq, 3, 1, do_clk_setfreq, "", ""),
 };
 
 static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc,
@@ -124,7 +168,8 @@ static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc,
 
 #ifdef CONFIG_SYS_LONGHELP
 static char clk_help_text[] =
-   "dump - Print clock frequencies";
+   "dump - Print clock frequencies\n"
+   "setfreq [clk] [freq] - Set clock frequency";
 #endif
 
-U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text);
+U_BOOT_CMD(clk, 4, 1, do_clk, "CLK sub-system", clk_help_text);
-- 
2.17.1

[PATCHv4 06/26] clk: fix clock tree dump to properly dump out every registered clock

[Tero Kristo]

From: Tero Kristo 

Some clocks are not associated to a DM node, so just parsing the DM is not
enough. This is especially true for root clocks, which typically don't have
any parents. Instead, fetch every registered UCLASS_CLK instance, and dump
these out.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 cmd/clk.c | 27 +++
 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/cmd/clk.c b/cmd/clk.c
index e3c3d2f9bb..0245b97136 100644
--- a/cmd/clk.c
+++ b/cmd/clk.c
@@ -18,11 +18,14 @@ static void show_clks(struct udevice *dev, int depth, int 
last_flag)
 {
int i, is_last;
struct udevice *child;
-   struct clk *clkp;
+   struct clk *clkp, *parent;
u32 rate;
 
clkp = dev_get_clk_ptr(dev);
if (device_get_uclass_id(dev) == UCLASS_CLK && clkp) {
+   parent = clk_get_parent(clkp);
+   if (!IS_ERR(parent) && depth == -1)
+   return;
depth++;
rate = clk_get_rate(clkp);
 
@@ -47,6 +50,9 @@ static void show_clks(struct udevice *dev, int depth, int 
last_flag)
}
 
list_for_each_entry(child, >child_head, sibling_node) {
+   if (child == dev)
+   continue;
+
is_last = list_is_last(>sibling_node, >child_head);
show_clks(child, depth, (last_flag << 1) | is_last);
}
@@ -54,14 +60,19 @@ static void show_clks(struct udevice *dev, int depth, int 
last_flag)
 
 int __weak soc_clk_dump(void)
 {
-   struct udevice *root;
+   struct udevice *dev;
+   struct uclass *uc;
+   int ret;
 
-   root = dm_root();
-   if (root) {
-   printf(" Rate   Usecnt  Name\n");
-   printf("--\n");
-   show_clks(root, -1, 0);
-   }
+   ret = uclass_get(UCLASS_CLK, );
+   if (ret)
+   return ret;
+
+   printf(" Rate   Usecnt  Name\n");
+   printf("--\n");
+
+   uclass_foreach_dev(dev, uc)
+   show_clks(dev, -1, 0);
 
return 0;
 }
-- 
2.17.1

[PATCHv4 07/26] clk: do not attempt to fetch clock pointer with null device

[Tero Kristo]

From: Tero Kristo 

Bail out early if device returned for the parent clock is null.
This avoids warning prints like this when doing clk dump:

  dev_get_uclass_priv: null device

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/clk-uclass.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 4ab3c402ed..ac2b7ae84e 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -499,6 +499,8 @@ struct clk *clk_get_parent(struct clk *clk)
return NULL;
 
pdev = dev_get_parent(clk->dev);
+   if (!pdev)
+   return ERR_PTR(-ENODEV);
pclk = dev_get_clk_ptr(pdev);
if (!pclk)
return ERR_PTR(-ENODEV);
-- 
2.17.1

[PATCHv4 04/26] common: fit: Update board_fit_image_post_process() to pass fit and node_offset

[Tero Kristo]

From: Lokesh Vutla 

board_fit_image_post_process() passes only start and size of the image,
but type of the image is not passed. So pass fit and node_offset, to
derive information about image to be processed.

Signed-off-by: Lokesh Vutla 
Reviewed-by: Tom Rini 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/security.c  | 3 ++-
 arch/arm/mach-keystone/mon.c | 3 ++-
 board/ti/am335x/board.c  | 3 ++-
 board/ti/am43xx/board.c  | 3 ++-
 board/ti/am57xx/board.c  | 3 ++-
 board/ti/dra7xx/evm.c| 3 ++-
 common/image-fit.c   | 2 +-
 common/spl/spl_fit.c | 2 +-
 include/image.h  | 5 -
 9 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c
index 66f90a5a34..5b5ff9ba7b 100644
--- a/arch/arm/mach-k3/security.c
+++ b/arch/arm/mach-k3/security.c
@@ -18,7 +18,8 @@
 #include 
 #include 
 
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
 {
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
struct ti_sci_proc_ops *proc_ops = _sci->ops.proc_ops;
diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c
index 58995d73ac..b863bab196 100644
--- a/arch/arm/mach-keystone/mon.c
+++ b/arch/arm/mach-keystone/mon.c
@@ -103,7 +103,8 @@ static int k2_hs_bm_auth(int cmd, void *arg1)
return  result;
 }
 
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
 {
int result = 0;
void *image = *p_image;
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index bc1657e88f..6952484d01 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -957,7 +957,8 @@ int board_fit_config_name_match(const char *name)
 #endif
 
 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
 {
secure_boot_verify_image(p_image, p_size);
 }
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index e9febb9592..a71b588efc 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -896,7 +896,8 @@ int embedded_dtb_select(void)
 #endif
 
 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
 {
secure_boot_verify_image(p_image, p_size);
 }
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 73063faee6..99d1ad3215 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -1198,7 +1198,8 @@ static int board_bootmode_has_emmc(void)
 #endif
 
 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
 {
secure_boot_verify_image(p_image, p_size);
 }
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 05f251f778..23e8005991 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -1065,7 +1065,8 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason 
reason)
 #endif
 
 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
 {
secure_boot_verify_image(p_image, p_size);
 }
diff --git a/common/image-fit.c b/common/image-fit.c
index e614643fe3..0c5a05948d 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -2143,7 +2143,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
 
/* perform any post-processing on the image data */
if (!host_build() && IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS))
-   board_fit_image_post_process(, );
+   board_fit_image_post_process(fit, noffset, , );
 
len = (ulong)size;
 
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 4288f571fc..9f17146f78 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -316,7 +316,7 @@ static int spl_load_fit_image(struct spl_load_info *info, 
ulong sector,
}
 
if (CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS))
-   board_fit_image_post_process(, );
+   board_fit_image_post_process(fit, node, , );
 
load_ptr = map_sysmem(load_addr, length);
if (IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP) {
diff --git a/include/image.h b/include/image.h
index 459685d4d4..0c24bf6f35 100644
--- a/include/image.h
++

[PATCHv4 05/26] clk: fixed_rate: add API for directly registering fixed rate clocks

[Tero Kristo]

From: Tero Kristo 

Current driver only supports registering fixed rate clocks from DT. Add
new API which makes it possible to register fixed rate clocks directly
from e.g. platform specific clock drivers.

Reviewed-by: Peng Fan 
Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/clk/clk_fixed_rate.c | 43 
 include/linux/clk-provider.h |  3 +++
 2 files changed, 46 insertions(+)

diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 09f9ef26a4..c591abf685 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -9,6 +9,9 @@
 #include 
 #include 
 
+#define UBOOT_DM_CLK_FIXED_RATE "fixed_rate_clock"
+#define UBOOT_DM_CLK_FIXED_RATE_RAW "fixed_rate_raw_clock"
+
 static ulong clk_fixed_rate_get_rate(struct clk *clk)
 {
return to_clk_fixed_rate(clk->dev)->fixed_rate;
@@ -40,6 +43,15 @@ void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev,
clk->enable_count = 0;
 }
 
+static ulong clk_fixed_rate_raw_get_rate(struct clk *clk)
+{
+   return container_of(clk, struct clk_fixed_rate, clk)->fixed_rate;
+}
+
+const struct clk_ops clk_fixed_rate_raw_ops = {
+   .get_rate = clk_fixed_rate_raw_get_rate,
+};
+
 static int clk_fixed_rate_of_to_plat(struct udevice *dev)
 {
clk_fixed_rate_ofdata_to_plat_(dev, to_clk_fixed_rate(dev));
@@ -47,6 +59,30 @@ static int clk_fixed_rate_of_to_plat(struct udevice *dev)
return 0;
 }
 
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+   ulong rate)
+{
+   struct clk *clk;
+   struct clk_fixed_rate *fixed;
+   int ret;
+
+   fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
+   if (!fixed)
+   return ERR_PTR(-ENOMEM);
+
+   fixed->fixed_rate = rate;
+
+   clk = >clk;
+
+   ret = clk_register(clk, UBOOT_DM_CLK_FIXED_RATE_RAW, name, NULL);
+   if (ret) {
+   kfree(fixed);
+   return ERR_PTR(ret);
+   }
+
+   return clk;
+}
+
 static const struct udevice_id clk_fixed_rate_match[] = {
{
.compatible = "fixed-clock",
@@ -63,3 +99,10 @@ U_BOOT_DRIVER(fixed_clock) = {
.ops = _fixed_rate_ops,
.flags = DM_FLAG_PRE_RELOC,
 };
+
+U_BOOT_DRIVER(clk_fixed_rate_raw) = {
+   .name = UBOOT_DM_CLK_FIXED_RATE_RAW,
+   .id = UCLASS_CLK,
+   .ops = _fixed_rate_raw_ops,
+   .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 6fda14f5fe..9d296f240a 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -247,6 +247,9 @@ struct clk *clk_register_mux(struct device *dev, const char 
*name,
void __iomem *reg, u8 shift, u8 width,
u8 clk_mux_flags);
 
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+   ulong rate);
+
 const char *clk_hw_get_name(const struct clk *hw);
 ulong clk_generic_get_rate(struct clk *clk);
 
-- 
2.17.1

[PATCHv4 03/26] remoteproc: k3-r5: remove sysfw PM calls if not supported

[Tero Kristo]

From: Tero Kristo 

With the sysfw rearch, sysfw PM calls are no longer available from SPL
level. To properly support this, remove the is_on checks and the reset
assertion from the R5 remoteproc driver as these are not supported.
Attempting to access unavailable services will cause the device to hang.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 drivers/remoteproc/ti_k3_r5f_rproc.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c 
b/drivers/remoteproc/ti_k3_r5f_rproc.c
index 3c569a3b7b..c8c30b9020 100644
--- a/drivers/remoteproc/ti_k3_r5f_rproc.c
+++ b/drivers/remoteproc/ti_k3_r5f_rproc.c
@@ -781,7 +781,9 @@ static int k3_r5f_probe(struct udevice *dev)
 {
struct k3_r5f_cluster *cluster = dev_get_priv(dev->parent);
struct k3_r5f_core *core = dev_get_priv(dev);
+#ifndef CONFIG_K3_DM_FW
bool r_state;
+#endif
int ret;
 
dev_dbg(dev, "%s\n", __func__);
@@ -804,6 +806,12 @@ static int k3_r5f_probe(struct udevice *dev)
return ret;
}
 
+   /*
+* The PM functionality is not supported by the firmware during
+* SPL execution with the separated DM firmware image. The following
+* piece of code is not compiled in that case.
+*/
+#ifndef CONFIG_K3_DM_FW
ret = core->tsp.sci->ops.dev_ops.is_on(core->tsp.sci, core->tsp.dev_id,
   _state, >in_use);
if (ret)
@@ -817,6 +825,7 @@ static int k3_r5f_probe(struct udevice *dev)
 
/* Make sure Local reset is asserted. Redundant? */
reset_assert(>reset);
+#endif
 
ret = k3_r5f_rproc_configure(core);
if (ret) {
-- 
2.17.1

[PATCHv4 02/26] arm: mach-k3: introduce new config option for sysfw split

[Tero Kristo]

From: Tero Kristo 

On J7 family of SoCs (J721E and J7200), sysfw is being split to be run
under two cores, TIFS portion on DMSC core, and DM firmware under MCU
R5. As MCU R5 is also used to run one phase of the bootloader, we must
prevent access from here towards sysfw services. To support this, add
new config option which can be used to detect presence of RM/PM sysfw
services.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 arch/arm/mach-k3/Kconfig | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index c7d186149b..c92722eab6 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -141,6 +141,17 @@ config SYS_K3_SPL_ATF
  Enabling this will try to start Cortex-A (typically with ATF)
  after SPL from R5.
 
+config K3_DM_FW
+   bool "Separate DM firmware image"
+   depends on SPL && CPU_V7R && SOC_K3_J721E && !CLK_TI_SCI && 
!TI_SCI_POWER_DOMAIN
+   default y
+   help
+ Enabling this will indicate that the system has separate DM
+ and TIFS firmware images in place, instead of a single SYSFW
+ firmware. Due to DM being executed on the same core as R5 SPL
+ bootloader, it makes RM and PM services not being available
+ during R5 SPL execution time.
+
 source "board/ti/am65x/Kconfig"
 source "board/ti/j721e/Kconfig"
 endif
-- 
2.17.1

[PATCHv4 00/26] J72xx: HSM rearch support series

[Tero Kristo]

Hello,

Couple of small changes in v4:
- re-worked patch #14 to include review comments from Jaehoon Chung
  * changed code to use iopoll version instead of hand crafted loops
for timeout handling
  * other mostly cosmetic changes
- patch #19/#21 changed to allow RM init to happen based on comment
  from Vignesh

-Tero

[PATCHv4 01/26] lib: rational: copy the rational fraction lib routines from Linux

[Tero Kristo]

From: Tero Kristo 

Copy the best rational approximation calculation routines from Linux.
Typical usecase for these routines is to calculate the M/N divider
values for PLLs to reach a specific clock rate.

This is based on linux kernel commit:
"lib/math/rational.c: fix possible incorrect result from rational
fractions helper"
(sha1: 323dd2c3ed0641f49e89b4e420f9eef5d3d5a881)

Signed-off-by: Tero Kristo 
Reviewed-by: Tom Rini 
Signed-off-by: Tero Kristo 
---
 include/linux/rational.h | 20 
 lib/Kconfig  |  7 +++
 lib/Makefile |  2 +
 lib/rational.c   | 99 
 4 files changed, 128 insertions(+)
 create mode 100644 include/linux/rational.h
 create mode 100644 lib/rational.c

diff --git a/include/linux/rational.h b/include/linux/rational.h
new file mode 100644
index 00..33f5f5fc3e
--- /dev/null
+++ b/include/linux/rational.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * rational fractions
+ *
+ * Copyright (C) 2009 emlix GmbH, Oskar Schirmer 
+ *
+ * helper functions when coping with rational numbers,
+ * e.g. when calculating optimum numerator/denominator pairs for
+ * pll configuration taking into account restricted register size
+ */
+
+#ifndef _LINUX_RATIONAL_H
+#define _LINUX_RATIONAL_H
+
+void rational_best_approximation(
+   unsigned long given_numerator, unsigned long given_denominator,
+   unsigned long max_numerator, unsigned long max_denominator,
+   unsigned long *best_numerator, unsigned long *best_denominator);
+
+#endif /* _LINUX_RATIONAL_H */
diff --git a/lib/Kconfig b/lib/Kconfig
index 6d2d41de30..68d58aa90d 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -663,6 +663,13 @@ config GENERATE_SMBIOS_TABLE
  See also SMBIOS_SYSINFO which allows SMBIOS values to be provided in
  the devicetree.
 
+config LIB_RATIONAL
+   bool "enable continued fraction calculation routines"
+
+config SPL_LIB_RATIONAL
+   bool "enable continued fraction calculation routines for SPL"
+   depends on SPL
+
 endmenu
 
 config ASN1_COMPILER
diff --git a/lib/Makefile b/lib/Makefile
index 6825671955..ea6bd0cb55 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -73,6 +73,8 @@ obj-$(CONFIG_$(SPL_)LZO) += lzo/
 obj-$(CONFIG_$(SPL_)LZMA) += lzma/
 obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o
 
+obj-$(CONFIG_$(SPL_)LIB_RATIONAL) += rational.o
+
 obj-$(CONFIG_LIBAVB) += libavb/
 
 obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/
diff --git a/lib/rational.c b/lib/rational.c
new file mode 100644
index 00..316db3b590
--- /dev/null
+++ b/lib/rational.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * rational fractions
+ *
+ * Copyright (C) 2009 emlix GmbH, Oskar Schirmer 
+ * Copyright (C) 2019 Trent Piepho 
+ *
+ * helper functions when coping with rational numbers
+ */
+
+#include 
+#include 
+#include 
+
+/*
+ * calculate best rational approximation for a given fraction
+ * taking into account restricted register size, e.g. to find
+ * appropriate values for a pll with 5 bit denominator and
+ * 8 bit numerator register fields, trying to set up with a
+ * frequency ratio of 3.1415, one would say:
+ *
+ * rational_best_approximation(31415, 1,
+ * (1 << 8) - 1, (1 << 5) - 1, , );
+ *
+ * you may look at given_numerator as a fixed point number,
+ * with the fractional part size described in given_denominator.
+ *
+ * for theoretical background, see:
+ * http://en.wikipedia.org/wiki/Continued_fraction
+ */
+
+void rational_best_approximation(
+   unsigned long given_numerator, unsigned long given_denominator,
+   unsigned long max_numerator, unsigned long max_denominator,
+   unsigned long *best_numerator, unsigned long *best_denominator)
+{
+   /* n/d is the starting rational, which is continually
+* decreased each iteration using the Euclidean algorithm.
+*
+* dp is the value of d from the prior iteration.
+*
+* n2/d2, n1/d1, and n0/d0 are our successively more accurate
+* approximations of the rational.  They are, respectively,
+* the current, previous, and two prior iterations of it.
+*
+* a is current term of the continued fraction.
+*/
+   unsigned long n, d, n0, d0, n1, d1, n2, d2;
+   n = given_numerator;
+   d = given_denominator;
+   n0 = d1 = 0;
+   n1 = d0 = 1;
+
+   for (;;) {
+   unsigned long dp, a;
+
+   if (d == 0)
+   break;
+   /* Find next term in continued fraction, 'a', via
+* Euclidean algorithm.
+*/
+   dp = d;
+   a = n / d;
+   d = n % d;
+   n = dp;
+
+   /* Calculate the current rational approximation (aka
+* convergent), n2/d2, using the term just found and
+* the two prior approximations.
+ 

[PATCH] configs: ti: enable TFTP_SIZE

[Tero Kristo]

This fits the TFTP progress bar on single line based on the size of the
file being downloaded, reducing unnecessary spam and also making it
easier to track the download progress.

Signed-off-by: Tero Kristo 
---
 include/configs/ti_armv7_common.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/ti_armv7_common.h 
b/include/configs/ti_armv7_common.h
index f13e9e5264..f40089a3fd 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -205,6 +205,8 @@
"run netloadfdt; " \
"run netargs; " \
"bootz ${loadaddr} - ${fdtaddr}\0"
+
+#define CONFIG_TFTP_TSIZE
 #else
 #define NETARGS ""
 #endif
-- 
2.17.1

Re: [PATCHv3 19/26] arm: mach-k3: do board config for PM and RM only if supported

[Tero Kristo]

On 09/05/2021 08:54, Vignesh Raghavendra wrote:



On 5/5/21 11:25 PM, Tero Kristo wrote:

From: Tero Kristo 

If the raw PM support is built in, we are operating in the split
firmware approach mode where RM and PM support is not available. In this
case, skip the board config for these two.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
  arch/arm/mach-k3/sysfw-loader.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 0bacfc4d07..64472353c4 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -159,11 +159,13 @@ static void k3_sysfw_configure_using_fit(void *fit,
  ret);
  
  	/* Apply power/clock (PM) specific configuration to SYSFW */

+#ifndef CONFIG_K3_DM_FW
ret = board_ops->board_config_pm(ti_sci,
 (u64)(u32)cfg_fragment_addr,
 (u32)cfg_fragment_size);
if (ret)
panic("Failed to set board PM configuration (%d)\n", ret);
+#endif
  
  	/* Extract resource management (RM) specific configuration from FIT */

ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM,
@@ -172,12 +174,14 @@ static void k3_sysfw_configure_using_fit(void *fit,
panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_RM,
  ret);
  
+#ifndef CONFIG_K3_DM_FW

/* Apply resource management (RM) configuration to SYSFW */
ret = board_ops->board_config_rm(ti_sci,
 (u64)(u32)cfg_fragment_addr,
 (u32)cfg_fragment_size);
if (ret)
panic("Failed to set board RM configuration (%d)\n", ret);
+#endif
  
  	/* Extract security specific configuration from FIT */

ret = fit_get_data_by_name(fit, images, SYSFW_CFG_SEC,




We still need to send RM CFG to TIFS in case of J721e in order for DMA
to work at R5 SPL. TIFS needs RM CFG to disable firewalls when R5 SPL
sends  DMA channel cfg requests.

Could you squash the following diff for next version:


Yes, I can squash that in. I believe you have tested this change and it 
works? (I will obviously double check at my end though.)


-Tero



diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index b95137fbdd..ac719cd46f 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -263,14 +263,7 @@ static void k3_sysfw_configure_using_fit(void *fit,
 panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_RM,
   ret);
  
-#ifndef CONFIG_K3_DM_FW

-   /* Apply resource management (RM) configuration to SYSFW */
-   ret = board_ops->board_config_rm(ti_sci,
-(u64)(u32)cfg_fragment_addr,
-(u32)cfg_fragment_size);
-   if (ret)
-   panic("Failed to set board RM configuration (%d)\n", ret);
-#else
+#ifdef CONFIG_K3_DM_FW
 if (copy_bcfg) {
 desc = _header->descs[1];
  
@@ -284,6 +277,13 @@ static void k3_sysfw_configure_using_fit(void *fit,

 }
  #endif
  
+   /* Apply resource management (RM) configuration to SYSFW */

+   ret = board_ops->board_config_rm(ti_sci,
+(u64)(u32)cfg_fragment_addr,
+(u32)cfg_fragment_size);
+   if (ret)
+   panic("Failed to set board RM configuration (%d)\n", ret);
+
 /* Extract security specific configuration from FIT */
 ret = fit_get_data_by_name(fit, images, SYSFW_CFG_SEC,
_fragment_addr, _fragment_size);


Regards
Vignesh

Re: [PATCHv3 14/26] power: domain: Introduce driver for raw TI K3 PDs

[Tero Kristo]

On 07/05/2021 03:03, Jaehoon Chung wrote:

Hi Tero,

On 5/6/21 2:55 AM, Tero Kristo wrote:

From: Tero Kristo 

Normally, power domains are handled via TI-SCI in K3 SoCs. However,
SPL is not going to have access to sysfw resources, so it must control
them directly. Add driver for supporting this.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
  drivers/power/domain/Kconfig   |   7 +
  drivers/power/domain/Makefile  |   1 +
  drivers/power/domain/ti-power-domain.c | 377 +
  include/k3-dev.h   |  76 +
  4 files changed, 461 insertions(+)
  create mode 100644 drivers/power/domain/ti-power-domain.c
  create mode 100644 include/k3-dev.h

diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index a0fd980752..b03a82d82c 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -72,4 +72,11 @@ config TI_SCI_POWER_DOMAIN
help
  Generic power domain implementation for TI devices implementing the
  TI SCI protocol.
+
+config TI_POWER_DOMAIN
+   bool "Enable the TI K3 Power domain driver"
+   depends on POWER_DOMAIN


Add your ARCH config as "depends on". This is TI specific thing.


Right, will do that.




+   help
+ Generic power domain implementation for TI K3 devices.
+
  endmenu
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 45bf9f6383..3d1e5f073c 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
  obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
  obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o
  obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o
+obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o
diff --git a/drivers/power/domain/ti-power-domain.c 
b/drivers/power/domain/ti-power-domain.c
new file mode 100644
index 00..ee2dc698ae
--- /dev/null
+++ b/drivers/power/domain/ti-power-domain.c
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments power domain driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/


2021?


Will change to 2020-2021.




+ * Tero Kristo 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PSC_PTCMD  0x120
+#define PSC_PTSTAT 0x128
+#define PSC_PDSTAT 0x200
+#define PSC_PDCTL  0x300
+#define PSC_MDSTAT 0x800
+#define PSC_MDCTL  0xa00
+
+#define PDCTL_STATE_MASK   0x1
+#define PDCTL_STATE_OFF0x0
+#define PDCTL_STATE_ON 0x1
+
+#define MDSTAT_STATE_MASK  0x3f
+#define MDSTAT_BUSY_MASK   0x30
+#define MDSTAT_STATE_SWRSTDISABLE  0x0
+#define MDSTAT_STATE_ENABLE0x3
+
+#define LPSC_TIMEOUT   10
+#define PD_TIMEOUT 10
+
+static u32 psc_read(struct ti_psc *psc, u32 reg)
+{
+   u32 val;
+
+   val = readl(psc->base + reg);
+   debug("%s: 0x%x from %p\n", __func__, val, psc->base + reg);
+   return val;
+}
+
+static void psc_write(u32 val, struct ti_psc *psc, u32 reg)
+{
+   debug("%s: 0x%x to %p\n", __func__, val, psc->base + reg);
+   writel(val, psc->base + reg);
+}
+
+static u32 pd_read(struct ti_pd *pd, u32 reg)
+{
+   return psc_read(pd->psc, reg + 4 * pd->id);
+}
+
+static void pd_write(u32 val, struct ti_pd *pd, u32 reg)
+{
+   psc_write(val, pd->psc, reg + 4 * pd->id);
+}
+
+static u32 lpsc_read(struct ti_lpsc *lpsc, u32 reg)
+{
+   return psc_read(lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static void lpsc_write(u32 val, struct ti_lpsc *lpsc, u32 reg)
+{
+   psc_write(val, lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static const struct soc_attr ti_k3_soc_pd_data[] = {
+#ifdef CONFIG_SOC_K3_J721E
+   {
+   .family = "J721E",
+   .data = _pd_platdata,
+   },
+   {
+   .family = "J7200",
+   .data = _pd_platdata,
+   },
+#endif
+   { /* sentinel */ }
+};
+
+static int ti_power_domain_probe(struct udevice *dev)
+{
+   struct ti_k3_pd_platdata *data = dev_get_priv(dev);
+   const struct soc_attr *soc_match_data;
+   const struct ti_k3_pd_platdata *pdata;
+
+   printf("%s(dev=%p)\n", __func__, dev);
+
+   if (!data)
+   return -ENOMEM;
+
+   soc_match_data = soc_device_match(ti_k3_soc_pd_data);
+   if (!soc_match_data)
+   return -ENODEV;
+
+   pdata = (const struct ti_k3_pd_platdata *)soc_match_data->data;
+
+   data->psc = pdata->psc;
+   data->pd = pdata->pd;
+   data->lpsc = pdata->lpsc;
+   data->devs = pdata->devs;
+   data->num_psc = 

Re: [PATCHv3 00/26] J72xx: HSM rearch support series

[Tero Kristo]

Uhm,

Sorry for CC:ing a stale email address with the patches, t-kri...@ti.com 
is no longer functional. Please drop that from any of the replies if you 
don't fancy spam replies from server.


-Tero

On 05/05/2021 20:55, Tero Kristo wrote:

Hello,

Resurrecting this series; v2 [1] was sort of put on hold due to some org
changes at TI. Sorry about the delay caused by this.

Anyways, v3 is mostly just a rebase of this series on top of
2021.07-rc1, and addition of some new data to support new boot modes for
j721e and j7200. This series has been tested on top of Dave's DDR driver
series [2]; on both J721e and J7200 boards.

Here are the details of changes compared to v2:

old-patch #2: removed (incorporated to Dave's DDR series now)
patch #12 & #13: squashed in some fixes for clock rate handling
patch #17: data additions
patch #21: squashed in a fix handle the boot headers properly
patch #22: new patch
patch #26: new patch to address the timer issues uncovered by Dario's
fix to omap timer code (commit 11326f379329: omap: timer: fix
the rate setting)

Rest of the changes are basically just rebases.

-Tero

[1] https://www.mail-archive.com/u-boot@lists.denx.de/msg390172.html
[2] https://www.mail-archive.com/u-boot@lists.denx.de/msg405657.html

[PATCHv3 26/26] arm: dts: k3-j72xx: correct MCU timer1 frequency

[Tero Kristo]

MCU timer1 is used as the tick timer for MCU R5 SPL, and the
clock-frequency defined in DT appears to be incorrect at the moment.
Actual clock source for the timer is MCU_SYSCLK0 / 4 which is 250MHz.

Earlier setup of 25MHz went unnoticed, as there was a separate issue
with omap-timer, which caused an error to the clock by a factor of 8
with j7 devices. This problem surfaced once the omap-timer was fixed.

Signed-off-by: Tero Kristo 
---
 arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 2 +-
 arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi 
b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index bd037be350..c3aae65b39 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -33,7 +33,7 @@
compatible = "ti,omap5430-timer";
reg = <0x0 0x4040 0x0 0x80>;
ti,timer-alwon;
-   clock-frequency = <2500>;
+   clock-frequency = <25000>;
u-boot,dm-spl;
};
 
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi 
b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 3384ed9f3a..1135de5a92 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -46,7 +46,7 @@
compatible = "ti,omap5430-timer";
reg = <0x0 0x4040 0x0 0x80>;
ti,timer-alwon;
-   clock-frequency = <2500>;
+   clock-frequency = <25000>;
u-boot,dm-spl;
};
 
-- 
2.17.1

[PATCHv3 25/26] board: ti: j72xx: README: update build instructions and image formats

[Tero Kristo]

From: Tero Kristo 

Update build instructions and image formats based on HSM rearch. A new
DM image is added into the build, which gets executed right after R5
SPL finishes its job.

Signed-off-by: Tero Kristo 
Signed-off-by: Tero Kristo 
---
 board/ti/j721e/README | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/board/ti/j721e/README b/board/ti/j721e/README
index c33afa496e..b1c9145c92 100644
--- a/board/ti/j721e/README
+++ b/board/ti/j721e/README
@@ -73,12 +73,12 @@ support. Below is the pictorial representation of boot flow:
 || | |   +-+ |   | 
  |
 || |<|---| Start A72   | |   | 
  |
 || | |   | and jump to | |   | 
  |
-|| | |   | next image  | |   | 
  |
+|| | |   | DM fw image | |   | 
  |
 || | |   +-+ |   | 
  |
 || | |   | +---+ | 
  |
 || |-|---|>| Reset rls | | 
  |
 || | |   | +---+ | 
  |
-||  DMSC   | |   |  :| 
  |
+||  TIFS   | |   |  :| 
  |
 ||Services | |   | +---+ | 
  |
 || |<|---|>|*ATF/OPTEE*| | 
  |
 || | |   | +---+ | 
  |
@@ -154,7 +154,7 @@ $ make CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5
 
 4.2. A72:
 $ make CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=/tmp/a72
-$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin O=/tmp/a72
+$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin DM= 
O=/tmp/a72
 
 Target Images
 --
@@ -197,6 +197,9 @@ Image formats:
 | | A72 OPTEE | |
 | +---+ |
 | |   | |
+| |  R5 DM FW | |
+| +---+ |
+| |   | |
 | |  A72 SPL  | |
 | +---+ |
 | |   | |
-- 
2.17.1