Re: [U-Boot] Pull request, u-boot-tegra/master
Thanks!
-Original Message-
From: Tom Rini [mailto:tr...@konsulko.com]
Sent: Tuesday, August 11, 2015 11:04 AM
To: Tom Warren
Cc: u-boot@lists.denx.de; Stephen Warren; Alex Courbot;
'tomcwarren3...@gmail.com'
Subject: Re: Pull request, u-boot-tegra/master
* PGP Signed by an unknown key
On Tue, Aug 11, 2015 at 05:44:13PM +, Tom Warren wrote:
Tom,
Don’t want to nag, but has this gone in yet?
So I saw this again this morning and double checked myself:
$ git pull git://git.denx.de/u-boot-tegra.git
From git://git.denx.de/u-boot-tegra
* branchHEAD - FETCH_HEAD
Already up-to-date.
$
I think this got folded in with the other PR you sent as I hadn't gotten to
it by
then? Or I applied it but somehow forgot to send the email, sorry! But it
is in.
Thanks!
--
nvpublic
From: Tom Warren [mailto:tomcwarren3...@gmail.com]
Sent: Thursday, August 06, 2015 1:40 PM
To: Tom Rini; u-boot@lists.denx.de
Cc: Stephen Warren; Tom Warren; Alex Courbot
Subject: Pull request, u-boot-tegra/master
Tom,
Please pull u-boot-tegra/master into U-Boot/master. Thanks!
./MAKEALL -s tegra is OK (all 32-bit builds), and ./MAKEALL -a aarch64 is OK
(includes p2571, P2371 and E220).
The following changes since commit
a5325cd5e91f77a2214e80198ae31c1d8b7e7c3c:
configs: Remove CONFIG_SERIAL_MULTI (2015-08-05 14:12:42 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-tegra.githttp://git.denx.de/u-boot-tegra.git
master
for you to fetch changes up to f05fa6781ae1122f348e66b5b26acbfe552f6602:
ARM: tegra: Add p2371- board (2015-08-06 10:50:04 -0700)
Alexandre Courbot (2):
ARM: tegra: move VPR configuration to a later stage
ARM: tegra: enable GPU DT node when appropriate
Stephen Warren (5):
ARM: tegra: restrict usable RAM size further
ARM: tegra: add comment re: autogeneration to pinmux headers
ARM: tegra: p2571: remove another unused define
ARM: tegra: Add e2220-1170 board
ARM: tegra: Add p2371- board
Tom Warren (7):
T210: P2571: Enable SD-card power via PMIC LDO2
T210: P2571: Restore USB gadget mode (ums)
T210: P2571: Turn CPU fan on
Tegra: clocks: Add 38.4MHz OSC support for T210 use
Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Tegra: spi: Move TEGRA114_SPI switch to defconfigs
Tegra: P2571: Clean up config file
arch/arm/dts/Makefile | 2 +
arch/arm/dts/tegra210-e2220-1170.dts | 58 +
arch/arm/dts/tegra210-p2371-.dts | 59 +
arch/arm/include/asm/arch-tegra/ap.h | 9 -
arch/arm/include/asm/arch-tegra/clk_rst.h | 32 +--
arch/arm/include/asm/arch-tegra/clock.h| 23 ++
arch/arm/include/asm/arch-tegra/gpu.h | 42
arch/arm/include/asm/arch-tegra210/clock-tables.h | 1 +
arch/arm/mach-tegra/Makefile | 4 +-
arch/arm/mach-tegra/ap.c | 3 -
arch/arm/mach-tegra/board2.c | 19 +-
arch/arm/mach-tegra/clock.c| 121 -
arch/arm/mach-tegra/cpu.c | 30 ++-
arch/arm/mach-tegra/{vpr.c = gpu.c} | 37 ++-
arch/arm/mach-tegra/tegra114/clock.c | 57 +++--
arch/arm/mach-tegra/tegra114/cpu.c | 39 ++-
arch/arm/mach-tegra/tegra124/clock.c | 44 +++-
arch/arm/mach-tegra/tegra124/cpu.c | 31 ++-
arch/arm/mach-tegra/tegra20/clock.c| 32 +++
arch/arm/mach-tegra/tegra210/Kconfig | 17 ++
arch/arm/mach-tegra/tegra210/clock.c | 39 ++-
arch/arm/mach-tegra/tegra30/clock.c| 45 +++-
board/nvidia/e2220-1170/Kconfig| 12 +
board/nvidia/e2220-1170/MAINTAINERS| 6 +
board/nvidia/e2220-1170/Makefile | 8 +
board/nvidia/e2220-1170/e2220-1170.c | 51
board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 277
+
board/nvidia/jetson-tk1/jetson-tk1.c | 8 +
board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h | 8 +
board/nvidia/nyan-big/pinmux-config-nyan-big.h | 8 +
board/nvidia/p2371-/Kconfig| 12 +
board/nvidia/p2371-/MAINTAINERS| 6 +
board/nvidia/p2371-/Makefile | 8 +
board/nvidia/p2371-/p2371-.c | 51
board/nvidia/p2371-/pinmux-config-p2371-.h | 268
board/nvidia/p2571/Makefile| 1 -
board/nvidia/p2571/max77620_init.c | 85 ---
board/nvidia/p2571
Re: [U-Boot] [PATCH v2 5/6] Tidy up some defconfig files
Simon, -Original Message- From: Simon Glass [mailto:s...@google.com] On Behalf Of Simon Glass Sent: Tuesday, August 11, 2015 6:39 AM To: U-Boot Mailing List Cc: Bin Meng; Joe Hershberger; Simon Glass; Akshay Saraswat; Vikas Manocha; VishnuPatekar; Stefano Babic; Marek Vasut; Siarhei Siamashka; Nikita Kiryanov; Michal Simek; Chander Kashyap; Tom Warren; Chin-Liang See; Hans de Goede; Priyanka Jain; Pavel Machek; Codrin Ciubotariu; Michal Suchanek; Nitin Garg; Markus Niebel; Stephen Warren; Paul Kocialkowski; Przemyslaw Marczak; Lokesh Vutla; Aneesh Bansal; Tom Rini; Peng Fan; Allen Martin; Stefan Roese; Jens Lucius; Dinh Nguyen; Masahiro Yamada; York Sun; Otavio Salvador; Alison Wang; Chen-Yu Tsai; Wang Dongsheng Subject: [PATCH v2 5/6] Tidy up some defconfig files Several files are out of order. This means that when the moveconfig tool moves CONFIG options to Kconfig it generates a large diff. To avoid this, reorder the files first. It appears (for P2571, at least) that you are not only reordering options (you moved CONFIG_TEGRA114_SPI), but removing some (CONFIG_SPL_DM and CONFIG_USE_PRIVATE_LIBGCC). If that's the intention, and removing those two options (because they're declared somewhere else?) doesn't affect the build/functionality, then perhaps two different patches are warranted - a cleanup patch (remove unused/unneeded config options) and then a reorder patch? Tom -- nvpublic -CONFIG_SPL_DM=y -CONFIG_TEGRA114_SPI=y CONFIG_SPI_FLASH=y +CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_USE_PRIVATE_LIBGCC=y Signed-off-by: Simon Glass s...@chromium.org --- Changes in v2: - Add new patch to tidy up some defconfig files configs/Ainol_AW1_defconfig | 2 +- configs/Ampe_A76_defconfig | 2 +- configs/Chuwi_V7_CW0825_defconfig| 2 +- configs/Et_q8_v1_6_defconfig | 2 +- configs/Hyundai_A7HD_defconfig | 2 +- configs/Ippo_q8h_v1_2_a33_1024x600_defconfig | 2 +- configs/Ippo_q8h_v1_2_defconfig | 2 +- configs/Ippo_q8h_v5_defconfig| 2 +- configs/MSI_Primo73_defconfig| 1 - configs/MSI_Primo81_defconfig| 3 +- configs/Merrii_A80_Optimus_defconfig | 1 - configs/Mini-X_defconfig | 2 +- configs/P3041DS_NAND_SECURE_BOOT_defconfig | 2 +- configs/P5020DS_NAND_SECURE_BOOT_defconfig | 2 +- configs/P5040DS_NAND_SECURE_BOOT_defconfig | 2 +- configs/T1040D4RDB_NAND_defconfig| 4 +-- configs/T1040D4RDB_SDCARD_defconfig | 4 +-- configs/T1040D4RDB_SECURE_BOOT_defconfig | 2 +- configs/T1040D4RDB_SPIFLASH_defconfig| 4 +-- configs/T1040D4RDB_defconfig | 2 +- configs/T1042D4RDB_NAND_defconfig| 4 +-- configs/T1042D4RDB_SDCARD_defconfig | 4 +-- configs/T1042D4RDB_SECURE_BOOT_defconfig | 2 +- configs/T1042D4RDB_SPIFLASH_defconfig| 4 +-- configs/T1042D4RDB_defconfig | 2 +- configs/TZX-Q8-713B7_defconfig | 2 +- configs/UTOO_P66_defconfig | 3 +- configs/Yones_Toptech_BD1078_defconfig | 2 +- configs/am43xx_evm_defconfig | 2 +- configs/arndale_defconfig| 4 +-- configs/ba10_tv_box_defconfig| 2 +- configs/cgtqmx6qeval_defconfig | 5 ++-- configs/cm_fx6_defconfig | 7 ++--- configs/dalmore_defconfig| 2 +- configs/db-88f6820-gp_defconfig | 2 +- configs/e2220-1170_defconfig | 5 +--- configs/efi-x86_defconfig| 9 +++--- configs/forfun_q88db_defconfig | 2 +- configs/ga10h_v1_1_defconfig | 2 +- configs/iNet_3F_defconfig| 2 +- configs/iNet_3W_defconfig| 2 +- configs/iNet_86VS_defconfig | 2 +- configs/jetson-tk1_defconfig | 2 +- configs/ls1021aqds_qspi_defconfig| 4 +-- configs/ls1021atwr_qspi_defconfig| 4 +-- configs/minnowmax_defconfig | 7 ++--- configs/mx6ul_14x14_evk_defconfig| 2 +- configs/nyan-big_defconfig | 2 +- configs/odroid-xu3_defconfig | 5 ++-- configs/p2371-_defconfig | 4 +-- configs/p2571_defconfig | 4 +-- configs/peach-pi_defconfig | 28 +-- configs/peach-pit_defconfig | 28 +-- configs/sandbox_defconfig| 22 +++ configs/smdk5250_defconfig | 18 ++-- configs/smdk5420_defconfig | 5 ++-- configs/snow_defconfig | 42 ++-- configs/socfpga_arria5_defconfig
Re: [U-Boot] [PATCH] tegra: Correct logic for reading pll_misc in clock_start_pll()
Simon,
-Original Message-
From: Simon Glass [mailto:s...@google.com] On Behalf Of Simon Glass
Sent: Monday, August 10, 2015 6:15 AM
To: U-Boot Mailing List
Cc: Simon Glass; Tom Warren; Thierry Reding; Masahiro Yamada; Stephen
Warren; Tom Rini; Albert Aribaud; Marcel Ziswiler; Stephen Warren
Subject: [PATCH] tegra: Correct logic for reading pll_misc in
clock_start_pll()
The logic for simple PLLs on T124 was broken by this commit:
722e000c Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Correct it by reading from the same pll_misc register that it writes to and
adding an entry for the DP PLL.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/arm/mach-tegra/clock.c | 33 +
arch/arm/mach-tegra/tegra124/clock.c | 2 ++
2 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index
3b2b4ff..f014434 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -126,19 +126,34 @@ unsigned long clock_start_pll(enum clock_id clkid, u32
divm, u32 divn, {
struct clk_pll *pll = NULL;
struct clk_pll_info *pllinfo = tegra_pll_info_table[clkid];
+ struct clk_pll_simple *simple_pll = NULL;
u32 misc_data, data;
- if (clkid (enum clock_id)TEGRA_CLK_PLLS)
+ if (clkid (enum clock_id)TEGRA_CLK_PLLS) {
pll = get_pll(clkid);
+ } else {
+ simple_pll = clock_get_simple_pll(clkid);
+ if (!simple_pll) {
+ debug(%s: Uknown simple PLL %d\n, __func__,
clkid);
+ return 0;
+ }
+ }
/*
* pllinfo has the m/n/p and kcp/kvco mask and shift
* values for all of the PLLs used in U-Boot, with any
* SoC differences accounted for.
+ *
+ * Preserve EN_LOCKDET, etc.
*/
- misc_data = readl(pll-pll_misc); /* preserve EN_LOCKDET, etc.
*/
- misc_data = ~(pllinfo-kcp_mask pllinfo-kcp_shift) | (cpcon
pllinfo-kcp_shift);
- misc_data = ~(pllinfo-kvco_mask pllinfo-kvco_shift) | (lfcon
pllinfo-kvco_shift);
+ if (pll)
+ misc_data = readl(pll-pll_misc);
+ else
+ misc_data = readl(simple_pll-pll_misc);
+ misc_data = ~(pllinfo-kcp_mask pllinfo-kcp_shift);
+ misc_data |= cpcon pllinfo-kcp_shift;
+ misc_data = ~(pllinfo-kvco_mask pllinfo-kvco_shift);
+ misc_data |= lfcon pllinfo-kvco_shift;
data = (divm pllinfo-m_shift) | (divn pllinfo-n_shift);
data |= divp pllinfo-p_shift;
@@ -148,14 +163,8 @@ unsigned long clock_start_pll(enum clock_id clkid, u32
divm, u32 divn,
writel(misc_data, pll-pll_misc);
writel(data, pll-pll_base);
} else {
- struct clk_pll_simple *pll = clock_get_simple_pll(clkid);
-
- if (!pll) {
- debug(%s: Uknown simple PLL %d\n, __func__,
clkid);
- return 0;
- }
- writel(misc_data, pll-pll_misc);
- writel(data, pll-pll_base);
+ writel(misc_data, simple_pll-pll_misc);
+ writel(data, simple_pll-pll_base);
}
/* calculate the stable time */
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-
tegra/tegra124/clock.c
index 9126218..42000ae 100644
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -593,6 +593,8 @@ struct clk_pll_info
tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
.lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3,
.kvco_shift = 0, .kvco_mask = 1 },/* PLLE */
{ .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift
=
20, .p_mask = 0x07,
.lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF,
.kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
+ { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift
= 20, .p_mask = 7,
+ .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF,
.kvco_shift = 4, .kvco_mask = 0xF }, /* PLLDP */
};
I was looking at adding a PLLDP table entry for T210 based on your T124 table,
and your settings don't match what I have in my T124 TRM.
PLLDP_MDIV is 8 bits wide, starting at bit 0, so .m_shift = 0 but .m_mask s/b
0xFF.
PLLDP_NDIV is 8 bits wide, starting at bit 8, so .n_shift = 8, but .n_mask s/b
0xFF.
.lock_det is OK at bit 27, but .lock_ena s/b bit 30 (PLLDP_LOCK_ENABLE).
PLLDP_KCP is 2 bits wide, starting at bit 25 with a mask of 0x3, so .kcp_shift
s/b 25 and .kcp_mask s/b 3.
PLLDP_KVCO is 1 bit wide, starting at bit 24 with a mask of 1, so .kvco_shift
s/b 24 and .kvco_mask s/b 1.
Not sure where your values came from - maybe a cutpaste error?
Please take a look. I've got this patch in u-boot-tegra/next right now, but I
can update it when you've confirmed
Re: [U-Boot] Pull request, u-boot-tegra/master
Tom,
Don’t want to nag, but has this gone in yet?
Thanks!
--
nvpublic
From: Tom Warren [mailto:tomcwarren3...@gmail.com]
Sent: Thursday, August 06, 2015 1:40 PM
To: Tom Rini; u-boot@lists.denx.de
Cc: Stephen Warren; Tom Warren; Alex Courbot
Subject: Pull request, u-boot-tegra/master
Tom,
Please pull u-boot-tegra/master into U-Boot/master. Thanks!
./MAKEALL -s tegra is OK (all 32-bit builds), and ./MAKEALL -a aarch64 is OK
(includes p2571, P2371 and E220).
The following changes since commit a5325cd5e91f77a2214e80198ae31c1d8b7e7c3c:
configs: Remove CONFIG_SERIAL_MULTI (2015-08-05 14:12:42 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-tegra.githttp://git.denx.de/u-boot-tegra.git master
for you to fetch changes up to f05fa6781ae1122f348e66b5b26acbfe552f6602:
ARM: tegra: Add p2371- board (2015-08-06 10:50:04 -0700)
Alexandre Courbot (2):
ARM: tegra: move VPR configuration to a later stage
ARM: tegra: enable GPU DT node when appropriate
Stephen Warren (5):
ARM: tegra: restrict usable RAM size further
ARM: tegra: add comment re: autogeneration to pinmux headers
ARM: tegra: p2571: remove another unused define
ARM: tegra: Add e2220-1170 board
ARM: tegra: Add p2371- board
Tom Warren (7):
T210: P2571: Enable SD-card power via PMIC LDO2
T210: P2571: Restore USB gadget mode (ums)
T210: P2571: Turn CPU fan on
Tegra: clocks: Add 38.4MHz OSC support for T210 use
Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Tegra: spi: Move TEGRA114_SPI switch to defconfigs
Tegra: P2571: Clean up config file
arch/arm/dts/Makefile | 2 +
arch/arm/dts/tegra210-e2220-1170.dts | 58 +
arch/arm/dts/tegra210-p2371-.dts | 59 +
arch/arm/include/asm/arch-tegra/ap.h | 9 -
arch/arm/include/asm/arch-tegra/clk_rst.h | 32 +--
arch/arm/include/asm/arch-tegra/clock.h| 23 ++
arch/arm/include/asm/arch-tegra/gpu.h | 42
arch/arm/include/asm/arch-tegra210/clock-tables.h | 1 +
arch/arm/mach-tegra/Makefile | 4 +-
arch/arm/mach-tegra/ap.c | 3 -
arch/arm/mach-tegra/board2.c | 19 +-
arch/arm/mach-tegra/clock.c| 121 -
arch/arm/mach-tegra/cpu.c | 30 ++-
arch/arm/mach-tegra/{vpr.c = gpu.c} | 37 ++-
arch/arm/mach-tegra/tegra114/clock.c | 57 +++--
arch/arm/mach-tegra/tegra114/cpu.c | 39 ++-
arch/arm/mach-tegra/tegra124/clock.c | 44 +++-
arch/arm/mach-tegra/tegra124/cpu.c | 31 ++-
arch/arm/mach-tegra/tegra20/clock.c| 32 +++
arch/arm/mach-tegra/tegra210/Kconfig | 17 ++
arch/arm/mach-tegra/tegra210/clock.c | 39 ++-
arch/arm/mach-tegra/tegra30/clock.c| 45 +++-
board/nvidia/e2220-1170/Kconfig| 12 +
board/nvidia/e2220-1170/MAINTAINERS| 6 +
board/nvidia/e2220-1170/Makefile | 8 +
board/nvidia/e2220-1170/e2220-1170.c | 51
board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 277 +
board/nvidia/jetson-tk1/jetson-tk1.c | 8 +
board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h | 8 +
board/nvidia/nyan-big/pinmux-config-nyan-big.h | 8 +
board/nvidia/p2371-/Kconfig| 12 +
board/nvidia/p2371-/MAINTAINERS| 6 +
board/nvidia/p2371-/Makefile | 8 +
board/nvidia/p2371-/p2371-.c | 51
board/nvidia/p2371-/pinmux-config-p2371-.h | 268
board/nvidia/p2571/Makefile| 1 -
board/nvidia/p2571/max77620_init.c | 85 ---
board/nvidia/p2571/max77620_init.h | 3 +-
board/nvidia/p2571/p2571.c | 41 +++
board/nvidia/p2571/pinmux-config-p2571.h | 8 +
board/nvidia/venice2/pinmux-config-venice2.h | 8 +
board/nvidia/venice2/venice2.c | 8 +
configs/dalmore_defconfig | 1 +
configs/e2220-1170_defconfig | 17 ++
configs/jetson-tk1_defconfig | 1 +
configs/nyan-big_defconfig | 1 +
configs/p2371-_defconfig | 17 ++
configs/p2571_defconfig| 1 +
configs/venice2_defconfig | 1 +
drivers/usb/host/ehci-tegra.c | 18 +-
include/configs/dalmore.h | 2 -
include/configs/e2220-1170.h | 65 +
include/configs/jetson-tk1.h
Re: [U-Boot] [PATCH] tegra: Correct logic for reading pll_misc in clock_start_pll()
Simon,
-Original Message-
From: Simon Glass [mailto:s...@google.com] On Behalf Of Simon Glass
Sent: Monday, August 10, 2015 6:15 AM
To: U-Boot Mailing List
Cc: Simon Glass; Tom Warren; Thierry Reding; Masahiro Yamada; Stephen
Warren; Tom Rini; Albert Aribaud; Marcel Ziswiler; Stephen Warren
Subject: [PATCH] tegra: Correct logic for reading pll_misc in
clock_start_pll()
The logic for simple PLLs on T124 was broken by this commit:
722e000c Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Correct it by reading from the same pll_misc register that it writes to and
adding an entry for the DP PLL.
Signed-off-by: Simon Glass s...@chromium.org
Thanks for finding this. I need to get my Nyan Chromebook back from my daughter
so I can use it for U-Boot testing (or buy another).
Marcel - can you test this on Colibri T20/T30? I'll check it out on my T210
p2571 (it'll need PLLDP support, too).
Tom
--
nvpublic
---
arch/arm/mach-tegra/clock.c | 33 +
arch/arm/mach-tegra/tegra124/clock.c | 2 ++
2 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index
3b2b4ff..f014434 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -126,19 +126,34 @@ unsigned long clock_start_pll(enum clock_id clkid, u32
divm, u32 divn, {
struct clk_pll *pll = NULL;
struct clk_pll_info *pllinfo = tegra_pll_info_table[clkid];
+ struct clk_pll_simple *simple_pll = NULL;
u32 misc_data, data;
- if (clkid (enum clock_id)TEGRA_CLK_PLLS)
+ if (clkid (enum clock_id)TEGRA_CLK_PLLS) {
pll = get_pll(clkid);
+ } else {
+ simple_pll = clock_get_simple_pll(clkid);
+ if (!simple_pll) {
+ debug(%s: Uknown simple PLL %d\n, __func__,
clkid);
+ return 0;
+ }
+ }
/*
* pllinfo has the m/n/p and kcp/kvco mask and shift
* values for all of the PLLs used in U-Boot, with any
* SoC differences accounted for.
+ *
+ * Preserve EN_LOCKDET, etc.
*/
- misc_data = readl(pll-pll_misc); /* preserve EN_LOCKDET, etc.
*/
- misc_data = ~(pllinfo-kcp_mask pllinfo-kcp_shift) | (cpcon
pllinfo-kcp_shift);
- misc_data = ~(pllinfo-kvco_mask pllinfo-kvco_shift) | (lfcon
pllinfo-kvco_shift);
+ if (pll)
+ misc_data = readl(pll-pll_misc);
+ else
+ misc_data = readl(simple_pll-pll_misc);
+ misc_data = ~(pllinfo-kcp_mask pllinfo-kcp_shift);
+ misc_data |= cpcon pllinfo-kcp_shift;
+ misc_data = ~(pllinfo-kvco_mask pllinfo-kvco_shift);
+ misc_data |= lfcon pllinfo-kvco_shift;
data = (divm pllinfo-m_shift) | (divn pllinfo-n_shift);
data |= divp pllinfo-p_shift;
@@ -148,14 +163,8 @@ unsigned long clock_start_pll(enum clock_id clkid, u32
divm, u32 divn,
writel(misc_data, pll-pll_misc);
writel(data, pll-pll_base);
} else {
- struct clk_pll_simple *pll = clock_get_simple_pll(clkid);
-
- if (!pll) {
- debug(%s: Uknown simple PLL %d\n, __func__,
clkid);
- return 0;
- }
- writel(misc_data, pll-pll_misc);
- writel(data, pll-pll_base);
+ writel(misc_data, simple_pll-pll_misc);
+ writel(data, simple_pll-pll_base);
}
/* calculate the stable time */
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-
tegra/tegra124/clock.c
index 9126218..42000ae 100644
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -593,6 +593,8 @@ struct clk_pll_info
tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
.lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3,
.kvco_shift = 0, .kvco_mask = 1 },/* PLLE */
{ .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift
=
20, .p_mask = 0x07,
.lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF,
.kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
+ { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift
= 20, .p_mask = 7,
+ .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF,
.kvco_shift = 4, .kvco_mask = 0xF }, /* PLLDP */
};
/*
--
2.5.0.rc2.392.g76e840b
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[U-Boot] Pull request, u-boot-tegra/master
Tom,
Please pull u-boot-tegra/master into U-Boot/master. Thanks!
./MAKEALL -s tegra is OK (all 32-bit builds), and ./MAKEALL -a aarch64 is
OK (includes p2571, P2371 and E220).
The following changes since commit a5325cd5e91f77a2214e80198ae31c1d8b7e7c3c:
configs: Remove CONFIG_SERIAL_MULTI (2015-08-05 14:12:42 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-tegra.git master
for you to fetch changes up to f05fa6781ae1122f348e66b5b26acbfe552f6602:
ARM: tegra: Add p2371- board (2015-08-06 10:50:04 -0700)
Alexandre Courbot (2):
ARM: tegra: move VPR configuration to a later stage
ARM: tegra: enable GPU DT node when appropriate
Stephen Warren (5):
ARM: tegra: restrict usable RAM size further
ARM: tegra: add comment re: autogeneration to pinmux headers
ARM: tegra: p2571: remove another unused define
ARM: tegra: Add e2220-1170 board
ARM: tegra: Add p2371- board
Tom Warren (7):
T210: P2571: Enable SD-card power via PMIC LDO2
T210: P2571: Restore USB gadget mode (ums)
T210: P2571: Turn CPU fan on
Tegra: clocks: Add 38.4MHz OSC support for T210 use
Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Tegra: spi: Move TEGRA114_SPI switch to defconfigs
Tegra: P2571: Clean up config file
arch/arm/dts/Makefile | 2 +
arch/arm/dts/tegra210-e2220-1170.dts | 58 +
arch/arm/dts/tegra210-p2371-.dts | 59 +
arch/arm/include/asm/arch-tegra/ap.h | 9 -
arch/arm/include/asm/arch-tegra/clk_rst.h | 32 +--
arch/arm/include/asm/arch-tegra/clock.h| 23 ++
arch/arm/include/asm/arch-tegra/gpu.h | 42
arch/arm/include/asm/arch-tegra210/clock-tables.h | 1 +
arch/arm/mach-tegra/Makefile | 4 +-
arch/arm/mach-tegra/ap.c | 3 -
arch/arm/mach-tegra/board2.c | 19 +-
arch/arm/mach-tegra/clock.c| 121 -
arch/arm/mach-tegra/cpu.c | 30 ++-
arch/arm/mach-tegra/{vpr.c = gpu.c} | 37 ++-
arch/arm/mach-tegra/tegra114/clock.c | 57 +++--
arch/arm/mach-tegra/tegra114/cpu.c | 39 ++-
arch/arm/mach-tegra/tegra124/clock.c | 44 +++-
arch/arm/mach-tegra/tegra124/cpu.c | 31 ++-
arch/arm/mach-tegra/tegra20/clock.c| 32 +++
arch/arm/mach-tegra/tegra210/Kconfig | 17 ++
arch/arm/mach-tegra/tegra210/clock.c | 39 ++-
arch/arm/mach-tegra/tegra30/clock.c| 45 +++-
board/nvidia/e2220-1170/Kconfig| 12 +
board/nvidia/e2220-1170/MAINTAINERS| 6 +
board/nvidia/e2220-1170/Makefile | 8 +
board/nvidia/e2220-1170/e2220-1170.c | 51
board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 277
+
board/nvidia/jetson-tk1/jetson-tk1.c | 8 +
board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h | 8 +
board/nvidia/nyan-big/pinmux-config-nyan-big.h | 8 +
board/nvidia/p2371-/Kconfig| 12 +
board/nvidia/p2371-/MAINTAINERS| 6 +
board/nvidia/p2371-/Makefile | 8 +
board/nvidia/p2371-/p2371-.c | 51
board/nvidia/p2371-/pinmux-config-p2371-.h | 268
board/nvidia/p2571/Makefile| 1 -
board/nvidia/p2571/max77620_init.c | 85 ---
board/nvidia/p2571/max77620_init.h | 3 +-
board/nvidia/p2571/p2571.c | 41 +++
board/nvidia/p2571/pinmux-config-p2571.h | 8 +
board/nvidia/venice2/pinmux-config-venice2.h | 8 +
board/nvidia/venice2/venice2.c | 8 +
configs/dalmore_defconfig | 1 +
configs/e2220-1170_defconfig | 17 ++
configs/jetson-tk1_defconfig | 1 +
configs/nyan-big_defconfig | 1 +
configs/p2371-_defconfig | 17 ++
configs/p2571_defconfig| 1 +
configs/venice2_defconfig | 1 +
drivers/usb/host/ehci-tegra.c | 18 +-
include/configs/dalmore.h | 2 -
include/configs/e2220-1170.h | 65 +
include/configs/jetson-tk1.h | 4 +-
include/configs/nyan-big.h | 2 -
include/configs/p2371-.h | 65 +
include/configs/p2571.h| 14 +-
include/configs/tegra124-common.h | 3 +
include/configs/tegra210-common.h | 3
Re: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node
-Original Message- From: Alex Courbot Sent: Thursday, August 06, 2015 12:58 AM To: Tom Warren; Andreas Färber; u-boot@lists.denx.de Cc: linux-te...@vger.kernel.org; gnu...@gmail.com; Stephen Warren; Guillaume Gardet Subject: Re: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node On 08/05/2015 08:24 AM, Tom Warren wrote: Alex/Andreas, -Original Message- From: Tom Warren Sent: Tuesday, August 04, 2015 8:41 AM To: 'Andreas Färber'; u-boot@lists.denx.de Cc: Alex Courbot; linux-te...@vger.kernel.org; gnu...@gmail.com; Stephen Warren; Guillaume Gardet Subject: RE: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node Andreas, -Original Message- From: Andreas Färber [mailto:afaer...@suse.de] Sent: Tuesday, August 04, 2015 6:56 AM To: u-boot@lists.denx.de Cc: Alex Courbot; linux-te...@vger.kernel.org; gnu...@gmail.com; Stephen Warren; Tom Warren; Guillaume Gardet Subject: Re: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node Am 23.07.2015 um 13:46 schrieb Andreas Färber: Am 09.07.2015 um 09:32 schrieb Alexandre Courbot: Tegra124 requires the bootloader to perform VPR initialization, otherwise the GPU cannot be used by the system. Since using the GPU without that initialization results in a hang, the GPU DT node is left disabled, and it is the task of the bootloader to enable it after ensuring it is safe to use the GPU. VPR init is already performed since patch df3443dfa449, but the device tree was left untouched. This patch series performs this last step and prepares the GPU intialization code to receive more code for newer chips. Tested-by: Andreas Färber afaer...@suse.de I've tested this patchset on v2015.07 with 4.2.0-rc3-00115-gc5dfd65 - with these two patches I get a console login on HDMI again. Ping! Independent of the Linux and X11 discussions this thread has drifted off into, these two patches are still missing in v2015.10-rc1 and don't apply any more (as reported by Guillaume). Can you please rebase and merge them? Is that request for me? Sorry, lost track of these patches since it appeared that there was an on-going discussion. If you're sure they're OK within the context of Tegra U-Boot, I'll apply them and send them with the next PR. Tom Applied to u-boot-tegra/next (along with some other pending Tegra patches for clocks/PLL/SPI/ums/etc.). I added T210/P2571 support to this patchset. PTAL. Also, there doesn't appear to be a 'gpu@0,5700' property in any t124/t210 DT file. Is that coming in another patch or one I missed? Thanks Tom! I have tried your branch and can confirm it is booting Jetson TK1 as expected (i.e. the GPU is in a usable state). The GPU node is not needed in U-boot's DT files (if that's what you meant). It is present in the kernel though, and that's the DT my patches will modify. Alex. Thanks, Alex. I'll send a PR with your changes later today. Tom -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Tegra: spi: Move TEGRA114_SPI switch to defconfigs
Jagan, -Original Message- From: Jagan Teki [mailto:jt...@openedev.com] Sent: Wednesday, August 05, 2015 1:35 AM To: Simon Glass Cc: Tom Warren; U-Boot Mailing List; Stephen Warren; Tom Warren Subject: Re: [U-Boot] [PATCH] Tegra: spi: Move TEGRA114_SPI switch to defconfigs On 31 July 2015 at 03:03, Simon Glass s...@chromium.org wrote: On 30 July 2015 at 14:57, Tom Warren twar...@nvidia.com wrote: All T114+ Tegra boards should be using the Kconfig TEGRA114_SPI switch. Remove it from include/config and put it into defconfig. Also removed unused TEGRA114_SPI_CTRLS from T114+ configs. All Tegra SoCs build OK with this change. Signed-off-by: Tom Warren twar...@nvidia.com --- configs/dalmore_defconfig| 1 + configs/jetson-tk1_defconfig | 1 + configs/nyan-big_defconfig | 1 + configs/p2571_defconfig | 1 + configs/venice2_defconfig| 1 + include/configs/dalmore.h| 2 -- include/configs/jetson-tk1.h | 2 -- include/configs/nyan-big.h | 2 -- include/configs/p2571.h | 2 -- include/configs/venice2.h| 2 -- 10 files changed, 5 insertions(+), 10 deletions(-) Reviewed-by: Simon Glass s...@chromium.org Reviewed-by: Jagan Teki jt...@openedev.com I couldn't find this patch on patchwork, pls- provide the link? I don't see it in patchworks, either (nor do I see my P2571 cleanup patch that was sent the same day/time). Maybe patchwork was down/busy that day and dropped it? Are you OK with my taking this in via u-boot-tegra, or do you want to take it in via u-boot-spi? Tom -- nvpublic thanks! -- Jagan | openedev. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] tegra: pll: fix pllx cpcon in pllinfo table for t20/t30
Marcel,
-Original Message-
From: Marcel Ziswiler [mailto:mar...@ziswiler.com]
Sent: Wednesday, August 05, 2015 7:37 AM
To: u-boot@lists.denx.de
Cc: Tom Warren; Tom Warren; Albert Aribaud; Tom Rini; Thierry Reding; Simon
Glass; Stephen Warren; Masahiro Yamada; Marcel Ziswiler
Subject: [PATCH] tegra: pll: fix pllx cpcon in pllinfo table for t20/t30
From: Marcel Ziswiler marcel.ziswi...@toradex.com
Fix CPCON mask and shift of PLLX for T20 as well as T30. While the former's
PLLX
did not even lock any more resulting is super slow operation the later seemed
to still lock OK. Nonetheless I this patch fixes it for both.
Signed-off-by: Marcel Ziswiler marcel.ziswi...@toradex.com
---
Note: This patch requires Tom's two Tegra PLL patches being applied first.
Do you mind if I just roll this into my pllinfo patch when I apply it to
u-boot-tegra/master and send the PR? I'll be sure to credit your work!
Tom
--
nvpublic
arch/arm/mach-tegra/tegra20/clock.c | 2 +- arch/arm/mach-
tegra/tegra30/clock.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-
tegra/tegra20/clock.c
index df9f412..dea459b 100644
--- a/arch/arm/mach-tegra/tegra20/clock.c
+++ b/arch/arm/mach-tegra/tegra20/clock.c
@@ -379,7 +379,7 @@ struct clk_pll_info
tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift
=
20, .p_mask = 0x07,
.lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF,
.kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift
= 20, .p_mask = 0x0F,
- .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0,
.kvco_shift = 0, .kvco_mask = 0 },/* PLLX */
+ .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF,
.kvco_shift = 0, .kvco_mask = 0 },/* PLLX */
{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift
=
0, .p_mask = 0,
.lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3,
.kvco_shift = 0, .kvco_mask = 1 },/* PLLE */
{ .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift
=
20, .p_mask = 0x07, diff --git a/arch/arm/mach-tegra/tegra30/clock.c
b/arch/arm/mach-tegra/tegra30/clock.c
index 4267bb2..3ce508b 100644
--- a/arch/arm/mach-tegra/tegra30/clock.c
+++ b/arch/arm/mach-tegra/tegra30/clock.c
@@ -428,7 +428,7 @@ struct clk_pll_info
tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift
=
20, .p_mask = 0x07,
.lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF,
.kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift
=
20, .p_mask = 0x0F,
- .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0,
.kvco_shift = 0, .kvco_mask = 0 },/* PLLX */
+ .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF,
.kvco_shift = 0, .kvco_mask = 0 },/* PLLX */
{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift
=
0, .p_mask = 0,
.lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3,
.kvco_shift = 0, .kvco_mask = 1 },/* PLLE */
{ .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift
=
20, .p_mask = 0x07,
--
2.4.3
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Re: [U-Boot] [PATCH] tegra: pll: fix pllx cpcon in pllinfo table for t20/t30
-Original Message- From: Marcel Ziswiler [mailto:marcel.ziswi...@toradex.com] Sent: Wednesday, August 05, 2015 8:33 AM To: u-boot@lists.denx.de; Tom Warren Cc: s...@chromium.org; tr...@konsulko.com; tomcwarren3...@gmail.com; Thierry Reding; albert.u.b...@aribaud.net; Stephen Warren; yamad...@jp.panasonic.com Subject: Re: [PATCH] tegra: pll: fix pllx cpcon in pllinfo table for t20/t30 On Wed, 2015-08-05 at 15:23 +, Tom Warren wrote: Do you mind if I just roll this into my pllinfo patch when I apply it to u-boot-tegra/master and send the PR? I'll be sure to credit your work! Fine with me and no need for any further credits. Thanks Tom. BTW: We are currently planning our ELCE trip to Dublin. Will any of you NVIDIA open-source maintainers make it there as well (e.g. to the U -Boot Summit)? I won't be able to make it - maybe Stephen? -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: tegra: restrict usable RAM size further
-Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Wednesday, August 05, 2015 11:33 AM To: Tom Warren Cc: u-boot@lists.denx.de; Simon Glass; Stephen Warren; Thierry Reding Subject: Re: [U-Boot] [PATCH] ARM: tegra: restrict usable RAM size further On 07/29/2015 01:47 PM, Stephen Warren wrote: From: Stephen Warren swar...@nvidia.com Additionally, ARM64 devices typically run a secure monitor in EL3 and U-Boot in EL2, and set up some secure RAM carve-outs to contain the EL3 code and data. These carve-outs are located at the top of 32-bit address space. Restrict U-Boot's RAM usage to well below the location of those carve-outs. Ideally, we would the secure monitor would inform U-Boot of exactly which RAM it could use at run-time. However, I'm not sure how to do that at present (and even if such a mechanism does exist, it would likely not be generic across all forms of secure monitor). TomW, what are your thoughts on applying this given the discussion thread? Thanks. I think this patch is fine. I have not set up any TZ/other carveouts (NVDEC,VPR,GPU,TSEC, etc.) yet in U-Boot, but I have in coreboot, and right now we're using approx. 153MB (0xf66c - 0x1). So 512MB here seems large but OK, given that we'll still have tons of SDRAM left on most any modern board. I can take this in on the next pass, if no one objects. Adding Marcel for Colibri T20/T30, since this'll affect those boards, too. Tom -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: tegra: restrict usable RAM size further
-Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Wednesday, August 05, 2015 12:27 PM To: Tom Warren Cc: u-boot@lists.denx.de; Simon Glass; Stephen Warren; Thierry Reding; Marcel Ziswiler Subject: Re: [U-Boot] [PATCH] ARM: tegra: restrict usable RAM size further On 08/05/2015 01:22 PM, Tom Warren wrote: -Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Wednesday, August 05, 2015 11:33 AM To: Tom Warren Cc: u-boot@lists.denx.de; Simon Glass; Stephen Warren; Thierry Reding Subject: Re: [U-Boot] [PATCH] ARM: tegra: restrict usable RAM size further On 07/29/2015 01:47 PM, Stephen Warren wrote: From: Stephen Warren swar...@nvidia.com Additionally, ARM64 devices typically run a secure monitor in EL3 and U-Boot in EL2, and set up some secure RAM carve-outs to contain the EL3 code and data. These carve-outs are located at the top of 32-bit address space. Restrict U-Boot's RAM usage to well below the location of those carve-outs. Ideally, we would the secure monitor would inform U-Boot of exactly which RAM it could use at run-time. However, I'm not sure how to do that at present (and even if such a mechanism does exist, it would likely not be generic across all forms of secure monitor). TomW, what are your thoughts on applying this given the discussion thread? Thanks. I think this patch is fine. I have not set up any TZ/other carveouts (NVDEC,VPR,GPU,TSEC, etc.) yet in U-Boot, but I have in coreboot, and right now we're using approx. 153MB (0xf66c - 0x1). So 512MB here seems large but OK, given that we'll still have tons of SDRAM left on most any modern board. I can take this in on the next pass, if no one objects. Adding Marcel for Colibri T20/T30, since this'll affect those boards, too. Thanks. This should only affect Tegra210 boards, since the function I modified is under #ifdef CONFIG_ARM64. Ah, yes. Missed that. -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Tegra: Allow TZ writes to VPR aperature regs
Stephen, -Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Wednesday, August 05, 2015 12:52 PM To: Tom Warren Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren; tomcwarren3...@gmail.com Subject: Re: [U-Boot] [PATCH] Tegra: Allow TZ writes to VPR aperature regs On 07/29/2015 10:24 AM, Tom Warren wrote: VPR (Video Protect Region) may be reconfigured from secure code in the kernel/OS. Set the ALLOW_TZ_WRITE_ACCESS bit in REG_CTRL to allow this. Also used common CONFIG option (CONFIG_LOCK_VPR) in T124/T210 builds to enable VPR setup. Acked-by: Stephen Warren swar...@nvidia.com I haven't investigated this much, but it seems fine. Thanks, but I'm dropping this patch. I've added Alex's 2 GPU/VPR patches, so this isn't needed (and enabling TZ writes is only done for dynamic VPR, which I've learned isn't needed/used). Tom -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V4 1/2] ARM: tegra: Add e2220-1170 board
Both of these applied to u-boot-tegra/next. PTAL. I'll issue a PR for this
(and the other 11 outstanding Tegra patches from you, me and Alex) when I get a
green light.
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Wednesday, August 05, 2015 10:52 AM
To: u-boot@lists.denx.de; Simon Glass; Tom Warren; Stephen Warren
Subject: [PATCH V4 1/2] ARM: tegra: Add e2220-1170 board
From: Stephen Warren swar...@nvidia.com
E2220-1170 is a Tegra210 bringup board with onboard SoC, DRAM, eMMC, SD
card slot, HDMI, USB micro-B port, and sockets for various expansion modules.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
v4: Remove a couple unused #defines from config header.
v3:
* More descriptions.
* Add auto-generation notice to pinmux header.
* Incorporate equivalent cleanups to those made to p2571.
v2: Use named constants for PMIC I2C and register addresses.
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/tegra210-e2220-1170.dts | 58 +
arch/arm/mach-tegra/tegra210/Kconfig | 8 +
board/nvidia/e2220-1170/Kconfig| 12 +
board/nvidia/e2220-1170/MAINTAINERS| 6 +
board/nvidia/e2220-1170/Makefile | 8 +
board/nvidia/e2220-1170/e2220-1170.c | 51
board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 277
+
configs/e2220-1170_defconfig | 17 ++
include/configs/e2220-1170.h | 65 +
10 files changed, 503 insertions(+)
create mode 100644 arch/arm/dts/tegra210-e2220-1170.dts
create mode 100644 board/nvidia/e2220-1170/Kconfig create mode 100644
board/nvidia/e2220-1170/MAINTAINERS
create mode 100644 board/nvidia/e2220-1170/Makefile create mode 100644
board/nvidia/e2220-1170/e2220-1170.c
create mode 100644 board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
create mode 100644 configs/e2220-1170_defconfig create mode 100644
include/configs/e2220-1170.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
ba6355379cba..d8e1841eb4d8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -33,6 +33,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-venice2.dtb \
+ tegra210-e2220-1170.dtb \
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
diff --git a/arch/arm/dts/tegra210-e2220-1170.dts b/arch/arm/dts/tegra210-
e2220-1170.dts
new file mode 100644
index ..75efbba1061e
--- /dev/null
+++ b/arch/arm/dts/tegra210-e2220-1170.dts
@@ -0,0 +1,58 @@
+/dts-v1/;
+
+#include tegra210.dtsi
+
+/ {
+ model = NVIDIA E2220-1170;
+ compatible = nvidia,e2220-1170, nvidia,tegra210;
+
+ chosen {
+ stdout-path = uarta;
+ };
+
+ aliases {
+ i2c0 = /i2c@0,7000d000;
+ sdhci0 = /sdhci@0,700b0600;
+ sdhci1 = /sdhci@0,700b;
+ usb0 = /usb@0,7d00;
+ };
+
+ memory {
+ reg = 0x0 0x8000 0x0 0xc000;
+ };
+
+ sdhci@0,700b {
+ status = okay;
+ cd-gpios = gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW;
+ power-gpios = gpio TEGRA_GPIO(Z, 4)
GPIO_ACTIVE_HIGH;
+ bus-width = 4;
+ };
+
+ sdhci@0,700b0600 {
+ status = okay;
+ bus-width = 8;
+ };
+
+ i2c@0,7000d000 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ usb@0,7d00 {
+ status = okay;
+ dr_mode = peripheral;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ clk32k_in: clock@0 {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 32768;
+ };
+ };
+};
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-
tegra/tegra210/Kconfig
index 147e6a83d722..a33fc5ce76b7 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -3,6 +3,13 @@ if TEGRA210
choice
prompt Tegra210 board select
+config TARGET_E2220_1170
+ bool NVIDIA Tegra210 E2220-1170 board
+ help
+ E2220-1170 is a Tegra210 bringup board with onboard SoC, DRAM,
+ eMMC, SD card slot, HDMI, USB micro-B port, and sockets for various
+ expansion modules.
+
config TARGET_P2571
bool NVIDIA Tegra210 P2571 base board
help
@@ -13,6 +20,7 @@ endchoice
config SYS_SOC
default tegra210
+source board/nvidia/e2220-1170/Kconfig
source board/nvidia/p2571/Kconfig
endif
diff --git a/board/nvidia/e2220-1170/Kconfig b/board/nvidia/e2220
Re: [U-Boot] [PATCH v3 00/16] assortment of tegra fixes/enhancements
Looks like almost all of these have been Acked-by StephenW and/or Reviewed-by SimonG. Only a couple are missing those tags - the NAND one and one other (can't think of it now). I'll apply them to u-boot-tegra/next. I've got u-boot-tegra/master in pretty good shape for a PR. Do you object if I send my master PR to TomR, then move -next to -master and send another by EOW? Just to keep the T210/P2x71 board stuff separate from all the Colibri T20/T30 fixes. Tom -- nvpublic -Original Message- From: Marcel Ziswiler [mailto:mar...@ziswiler.com] Sent: Wednesday, August 05, 2015 3:47 PM To: u-boot@lists.denx.de Cc: Albert Aribaud; Tom Rini; Tom Warren; Marcel Ziswiler; Lucas Stach; Stefan Agner; Scott Wood; Simon Glass; Stephen Warren; Paul Kocialkowski; Marcel Ziswiler Subject: [PATCH v3 00/16] assortment of tegra fixes/enhancements From: Marcel Ziswiler marcel.ziswi...@toradex.com This patch set is an assortment of tegra fixes/enhancements distilled straight from our downstream integration work. Changes in v3: - dropped apalis/colibri_t20/t30 specific raw initrd support enablement (formerly 12) - drop unrelated subpage writes disabling in (8) to be done as part of a separate patch (16) Changes in v2: - dropped Colibri T20 specific ONFI detection enablement patch (formerly 9) as I noticed this already being done globally as part of tegra20-common.h - enable UBI/UBIFS support (11) - limit TFTP block size (13) on Colibri T20 to 1536 due to issues observed otherwise - drop unrelated clean-up in (3) to be done as part of a separate patch (14) - new patch (15) fixing nRESET_OUT - new patch (16) fixing USB DM regression on Apalis/Colibri T30 Marcel Ziswiler (15): ARM: tegra: allow custom usb manufacturer/product/vendor ids/strings ARM: tegra: allow reading recovery mode boot type apalis/colibri_t20/t30: integrate recovery mode detection colibri_t20: fix device-tree compatible node colibri_t20: add lcd display support colibri_t20: add i2c support colibri_t20: disable PMIC sleep mode on low supply voltage tegra: nand: fix read_byte required for proper onfi detection mtd/nand/tegra: alignment workaround colibri_t20: enable mtdparts support colibri_t20: enable ubi/ubifs support apalis/colibri_t20/30: clean-up colibri_t20: fix reset out pin apalis/colibri_t30: fix usb dm regression tegra: nand: disable subpage writes Max Krummenacher (1): apalis/colibri_t20/t30: increase tftp blocksize arch/arm/dts/tegra20-colibri.dts | 63 ++- arch/arm/dts/tegra30-apalis.dts | 2 +- arch/arm/dts/tegra30-colibri.dts | 4 +- arch/arm/include/asm/arch-tegra/tegra.h | 2 + board/toradex/apalis_t30/apalis_t30.c | 15 +++- board/toradex/colibri_t20/colibri_t20.c | 68 board/toradex/colibri_t30/colibri_t30.c | 18 - drivers/mtd/nand/tegra_nand.c | 128 +++--- include/configs/apalis_t30.h | 13 ++- include/configs/colibri_t20.h | 53 +++-- include/configs/colibri_t30.h | 13 ++- include/configs/tegra-common-usb-gadget.h | 6 ++ 12 files changed, 283 insertions(+), 102 deletions(-) -- 2.4.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node
Andreas, -Original Message- From: Andreas Färber [mailto:afaer...@suse.de] Sent: Tuesday, August 04, 2015 6:56 AM To: u-boot@lists.denx.de Cc: Alex Courbot; linux-te...@vger.kernel.org; gnu...@gmail.com; Stephen Warren; Tom Warren; Guillaume Gardet Subject: Re: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node Am 23.07.2015 um 13:46 schrieb Andreas Färber: Am 09.07.2015 um 09:32 schrieb Alexandre Courbot: Tegra124 requires the bootloader to perform VPR initialization, otherwise the GPU cannot be used by the system. Since using the GPU without that initialization results in a hang, the GPU DT node is left disabled, and it is the task of the bootloader to enable it after ensuring it is safe to use the GPU. VPR init is already performed since patch df3443dfa449, but the device tree was left untouched. This patch series performs this last step and prepares the GPU intialization code to receive more code for newer chips. Tested-by: Andreas Färber afaer...@suse.de I've tested this patchset on v2015.07 with 4.2.0-rc3-00115-gc5dfd65 - with these two patches I get a console login on HDMI again. Ping! Independent of the Linux and X11 discussions this thread has drifted off into, these two patches are still missing in v2015.10-rc1 and don't apply any more (as reported by Guillaume). Can you please rebase and merge them? Is that request for me? Sorry, lost track of these patches since it appeared that there was an on-going discussion. If you're sure they're OK within the context of Tegra U-Boot, I'll apply them and send them with the next PR. Tom Thanks, Andreas -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer, Jane Smithard, Dilip Upmanyu, Graham Norton; HRB 21284 (AG Nürnberg) -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Marcel, -Original Message- From: Marcel Ziswiler [mailto:mar...@ziswiler.com] Sent: Tuesday, August 04, 2015 1:33 AM To: Tom Warren; u-boot@lists.denx.de Cc: tomcwarren3...@gmail.com; Stephen Warren; Thierry Reding; s...@chromium.org Subject: Re: [PATCH 2/2] Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. On Wed, 2015-07-29 at 13:13 -0700, Tom Warren wrote: Added PLL variables (dividers mask/shift, lock enable/detect, etc.) to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X. Used pllinfo struct in all clock functions, validated on T210. Should be equivalent to prior code on T124/114/30/20 but needs test. Corrections to divm mask vs shift and T20/30 divN masks thanks to Marcel Ziswiler. Signed-off-by: Tom Warren twar...@nvidia.com While this boots on Colibri T20/T30 as well as Apalis T30 there is still something askew on T20 as e.g. USB Ethernet is more than 6 times slower than before. T30 on the other hand seems to work fine. I will try to find some time to investigate further. Thanks. My T20/T30 boards are moth-balled, so I don't test on them. T210 USB is fine. If you can provide CAR register dumps (0x60006000 - 0x60006FFF) on T20 I can take a look. Appreciate any testing you can do. This won't go in to u-boot-tegra until you are satisified. Tom -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node
Alex/Andreas, -Original Message- From: Tom Warren Sent: Tuesday, August 04, 2015 8:41 AM To: 'Andreas Färber'; u-boot@lists.denx.de Cc: Alex Courbot; linux-te...@vger.kernel.org; gnu...@gmail.com; Stephen Warren; Guillaume Gardet Subject: RE: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node Andreas, -Original Message- From: Andreas Färber [mailto:afaer...@suse.de] Sent: Tuesday, August 04, 2015 6:56 AM To: u-boot@lists.denx.de Cc: Alex Courbot; linux-te...@vger.kernel.org; gnu...@gmail.com; Stephen Warren; Tom Warren; Guillaume Gardet Subject: Re: [U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node Am 23.07.2015 um 13:46 schrieb Andreas Färber: Am 09.07.2015 um 09:32 schrieb Alexandre Courbot: Tegra124 requires the bootloader to perform VPR initialization, otherwise the GPU cannot be used by the system. Since using the GPU without that initialization results in a hang, the GPU DT node is left disabled, and it is the task of the bootloader to enable it after ensuring it is safe to use the GPU. VPR init is already performed since patch df3443dfa449, but the device tree was left untouched. This patch series performs this last step and prepares the GPU intialization code to receive more code for newer chips. Tested-by: Andreas Färber afaer...@suse.de I've tested this patchset on v2015.07 with 4.2.0-rc3-00115-gc5dfd65 - with these two patches I get a console login on HDMI again. Ping! Independent of the Linux and X11 discussions this thread has drifted off into, these two patches are still missing in v2015.10-rc1 and don't apply any more (as reported by Guillaume). Can you please rebase and merge them? Is that request for me? Sorry, lost track of these patches since it appeared that there was an on-going discussion. If you're sure they're OK within the context of Tegra U-Boot, I'll apply them and send them with the next PR. Tom Applied to u-boot-tegra/next (along with some other pending Tegra patches for clocks/PLL/SPI/ums/etc.). I added T210/P2571 support to this patchset. PTAL. Also, there doesn't appear to be a 'gpu@0,5700' property in any t124/t210 DT file. Is that coming in another patch or one I missed? Thanks, Tom Thanks, Andreas -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer, Jane Smithard, Dilip Upmanyu, Graham Norton; HRB 21284 (AG Nürnberg) -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Tegra: P2571: Clean up config file
Removed NS16550_COM1 #define, not used since there's no SPL for T210 Also changed the number of USB controllers to 1 as only USBD is used. Signed-off-by: Tom Warren twar...@nvidia.com --- include/configs/p2571.h | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/include/configs/p2571.h b/include/configs/p2571.h index 5df7d2f..b22117b 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -22,7 +22,6 @@ /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1NV_PA_APB_UARTA_BASE /* I2C */ #define CONFIG_SYS_I2C_TEGRA @@ -51,7 +50,7 @@ /* USB2.0 Host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA -#define CONFIG_USB_MAX_CONTROLLER_COUNT2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT1 #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB @@ -62,10 +61,6 @@ /* General networking support */ #define CONFIG_CMD_DHCP -/* - * TODO(twar...@nvidia.com) - add tegra-common-usb-gadget.h back - * breaks 64-bit build in ci_udc.c - */ #include tegra-common-usb-gadget.h #include tegra-common-post.h -- 1.8.2.1.610.g562af5b ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Tegra: spi: Move TEGRA114_SPI switch to defconfigs
All T114+ Tegra boards should be using the Kconfig TEGRA114_SPI switch. Remove it from include/config and put it into defconfig. Also removed unused TEGRA114_SPI_CTRLS from T114+ configs. All Tegra SoCs build OK with this change. Signed-off-by: Tom Warren twar...@nvidia.com --- configs/dalmore_defconfig| 1 + configs/jetson-tk1_defconfig | 1 + configs/nyan-big_defconfig | 1 + configs/p2571_defconfig | 1 + configs/venice2_defconfig| 1 + include/configs/dalmore.h| 2 -- include/configs/jetson-tk1.h | 2 -- include/configs/nyan-big.h | 2 -- include/configs/p2571.h | 2 -- include/configs/venice2.h| 2 -- 10 files changed, 5 insertions(+), 10 deletions(-) diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig index e7443f8..2d80247 100644 --- a/configs/dalmore_defconfig +++ b/configs/dalmore_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE=tegra114-dalmore # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPL_DM=y +CONFIG_TEGRA114_SPI=y CONFIG_SPI_FLASH=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index 7085469..44c7a8e 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE=tegra124-jetson-tk1 # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPL_DM=y +CONFIG_TEGRA114_SPI=y CONFIG_SPI_FLASH=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index 79b74a7..ccf656b 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE=tegra124-nyan-big # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPL_DM=y +CONFIG_TEGRA114_SPI=y CONFIG_SPI_FLASH=y CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index 8494bb5..5fd2a54 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE=tegra210-p2571 # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPL_DM=y +CONFIG_TEGRA114_SPI=y CONFIG_SPI_FLASH=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig index 9ccd739..a4735f6 100644 --- a/configs/venice2_defconfig +++ b/configs/venice2_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE=tegra124-venice2 # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPL_DM=y +CONFIG_TEGRA114_SPI=y CONFIG_SPI_FLASH=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 89b6f23..32fe9e8 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -51,8 +51,6 @@ #define MACH_TYPE_DALMORE 4304/* not yet in mach-types.h */ /* SPI */ -#define CONFIG_TEGRA114_SPI -#define CONFIG_TEGRA114_SPI_CTRLS 6 #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED2400 diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 3bbff28..5999504 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -41,8 +41,6 @@ #define CONFIG_SYS_MMC_ENV_PART2 /* SPI */ -#define CONFIG_TEGRA114_SPI/* Compatible w/ Tegra114 SPI */ -#define CONFIG_TEGRA114_SPI_CTRLS 6 #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED2400 diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index dd549aa..4858dea 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -53,8 +53,6 @@ #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE /* SPI */ -#define CONFIG_TEGRA114_SPI/* Compatible w/ Tegra114 SPI */ -#define CONFIG_TEGRA114_SPI_CTRLS 6 #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED2400 diff --git a/include/configs/p2571.h b/include/configs/p2571.h index d39fa2a..5df7d2f 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -41,8 +41,6 @@ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) /* SPI */ -#define CONFIG_TEGRA114_SPI/* Compatible w/ Tegra114 SPI */ -#define CONFIG_TEGRA114_SPI_CTRLS 6 #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED2400 diff --git a/include/configs/venice2.h b/include/configs/venice2.h index 1d9d053..0535a6b 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -38,8 +38,6 @@ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) /* SPI */ -#define CONFIG_TEGRA114_SPI/* Compatible w/ Tegra114 SPI */ -#define CONFIG_TEGRA114_SPI_CTRLS 6 #define CONFIG_SPI_FLASH_WINBOND #define
Re: [U-Boot] [PATCH] Tegra: P2571: Clean up config file
Simon, -Original Message- From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass Sent: Thursday, July 30, 2015 2:33 PM To: Tom Warren Cc: U-Boot Mailing List; Tom Warren; Stephen Warren Subject: Re: [PATCH] Tegra: P2571: Clean up config file Hi Tom, On 30 July 2015 at 15:09, Tom Warren twar...@nvidia.com wrote: Removed NS16550_COM1 #define, not used since there's no SPL for T210 Also changed the number of USB controllers to 1 as only USBD is used. Signed-off-by: Tom Warren twar...@nvidia.com --- include/configs/p2571.h | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/include/configs/p2571.h b/include/configs/p2571.h index 5df7d2f..b22117b 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -22,7 +22,6 @@ /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1NV_PA_APB_UARTA_BASE /* I2C */ #define CONFIG_SYS_I2C_TEGRA @@ -51,7 +50,7 @@ /* USB2.0 Host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA -#define CONFIG_USB_MAX_CONTROLLER_COUNT2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT1 You should be able to drop this now that Tegra uses driver model for USB. Doesn't seem to work on P2571. If I drop MAX_CONTROLLER_COUNT, it builds, but I get EHCI failed to shut down host controller errors on usb start/reset, and I don't see any of my periphs (mouse, USB stick, network dongle). With it in there as I have it above, everything works. #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB @@ -62,10 +61,6 @@ /* General networking support */ #define CONFIG_CMD_DHCP -/* - * TODO(twar...@nvidia.com) - add tegra-common-usb-gadget.h back - * breaks 64-bit build in ci_udc.c - */ #include tegra-common-usb-gadget.h #include tegra-common-post.h -- 1.8.2.1.610.g562af5b Regards, Simon -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] ARM: tegra: Add e2220-1170 board
-Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Thursday, July 30, 2015 11:03 AM To: Tom Warren; Simon Glass Cc: U-Boot Mailing List; Stephen Warren; Thierry Reding Subject: Re: [PATCH 1/2] ARM: tegra: Add e2220-1170 board (It'd be nice if all the irrelevant context could be trimmed so it was possible to quickly find the responses within the patch. As it is, there are about 5 lines of response in hundreds of lines of quoted patch, which makes it very easy to miss things and wastes time). On 07/29/2015 08:42 PM, Tom Warren wrote: Simon, I can respond to your Kconfig questions below. -Original Message- From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass Sent: Wednesday, July 29, 2015 4:02 PM To: Stephen Warren Cc: U-Boot Mailing List; Tom Warren; Stephen Warren; Thierry Reding Subject: Re: [PATCH 1/2] ARM: tegra: Add e2220-1170 board Hi Stephen, On 29 July 2015 at 13:48, Stephen Warren swar...@wwwdotorg.org wrote: diff --git a/include/configs/e2220-1170.h +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE Do we need this still? 32-bit builds (i.e. w/SPL) still need this. I've removed it in a future patch for P2571. Is that a patch you've sent upstream; if so, which one was it? If it's been sent already, or even just pushed into a git server somewhere in a final form, I can apply it locally and align these new boards so they're consistent with the latest version of p2571.h etc. The same response applies to the other Kconfig-related questions. Nope, not sent yet. Later today, I hope. I'll send you a copy after lunch. Tom -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Tegra: Allow TZ writes to VPR aperature regs
VPR (Video Protect Region) may be reconfigured
from secure code in the kernel/OS. Set the
ALLOW_TZ_WRITE_ACCESS bit in REG_CTRL to allow
this. Also used common CONFIG option (CONFIG_LOCK_VPR)
in T124/T210 builds to enable VPR setup.
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/include/asm/arch-tegra124/mc.h | 2 ++
arch/arm/include/asm/arch-tegra210/mc.h | 2 ++
arch/arm/mach-tegra/Makefile| 4 +---
arch/arm/mach-tegra/vpr.c | 9 +++--
include/configs/tegra124-common.h | 3 +++
include/configs/tegra210-common.h | 3 +++
6 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra124/mc.h
b/arch/arm/include/asm/arch-tegra124/mc.h
index 37998a4..851e3df 100644
--- a/arch/arm/include/asm/arch-tegra124/mc.h
+++ b/arch/arm/include/asm/arch-tegra124/mc.h
@@ -78,5 +78,7 @@ struct mc_ctlr {
#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED(0 0)
#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 0)
+#define TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_DISABLED (0 1)
+#define TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_ENABLED (1 1)
#endif /* _TEGRA124_MC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/mc.h
b/arch/arm/include/asm/arch-tegra210/mc.h
index 77e9aa5..2a20b47 100644
--- a/arch/arm/include/asm/arch-tegra210/mc.h
+++ b/arch/arm/include/asm/arch-tegra210/mc.h
@@ -68,5 +68,7 @@ struct mc_ctlr {
#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED(0 0)
#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 0)
+#define TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_DISABLED (0 1)
+#define TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_ENABLED (1 1)
#endif /* _TEGRA210_MC_H_ */
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 0db8ee0..8a42216 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -24,9 +24,7 @@ obj-y += pinmux-common.o
obj-y += powergate.o
obj-y += xusb-padctl.o
obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
-#TCW Fix this to use a common config switch (CONFIG_LOCK_VPR?)
-obj-$(CONFIG_TEGRA124) += vpr.o
-obj-$(CONFIG_TEGRA210) += vpr.o
+obj-$(CONFIG_LOCK_VPR) += vpr.o
obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
ifndef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-tegra/vpr.c b/arch/arm/mach-tegra/vpr.c
index f695811..091163e 100644
--- a/arch/arm/mach-tegra/vpr.c
+++ b/arch/arm/mach-tegra/vpr.c
@@ -21,14 +21,19 @@
#include asm/arch/tegra.h
#include asm/arch/mc.h
-/* Configures VPR. Right now, all we do is turn it off. */
+/*
+ * Configures VPR. Right now, all we do is turn it off.
+ * But we set ALLOW_TZ_WRITE_ACCESS so secure code
+ * in the kernel/OS can reconfig it later if needed.
+ */
void config_vpr(void)
{
struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
/* Turn VPR off */
writel(0, mc-mc_video_protect_size_mb);
- writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
+ writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED |
+ TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_ENABLED,
mc-mc_video_protect_reg_ctrl);
/* read back to ensure the write went through */
readl(mc-mc_video_protect_reg_ctrl);
diff --git a/include/configs/tegra124-common.h
b/include/configs/tegra124-common.h
index af7698d..e850a75 100644
--- a/include/configs/tegra124-common.h
+++ b/include/configs/tegra124-common.h
@@ -70,4 +70,7 @@
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+/* Set up VPR (Video Protect Region) */
+#define CONFIG_LOCK_VPR
+
#endif /* _TEGRA124_COMMON_H_ */
diff --git a/include/configs/tegra210-common.h
b/include/configs/tegra210-common.h
index 0348d47..267beab 100644
--- a/include/configs/tegra210-common.h
+++ b/include/configs/tegra210-common.h
@@ -73,4 +73,7 @@
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+/* Set up VPR (Video Protect Region) */
+#define CONFIG_LOCK_VPR
+
#endif /* _TEGRA210_COMMON_H_ */
--
1.8.2.1.610.g562af5b
___
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http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] T210: P2571: Turn CPU fan on
CPU board (E2530) has a fan - turn it on via GPIO to keep
the SoC cool.
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/mach-tegra/board2.c | 3 +++
board/nvidia/p2571/p2571.c | 12
2 files changed, 15 insertions(+)
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 36bcfb0..2927b4e 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -60,6 +60,7 @@ __weak void pin_mux_usb(void) {}
__weak void pin_mux_spi(void) {}
__weak void gpio_early_init_uart(void) {}
__weak void pin_mux_display(void) {}
+__weak void start_cpu_fan(void) {}
#if defined(CONFIG_TEGRA_NAND)
__weak void pin_mux_nand(void)
@@ -230,6 +231,8 @@ int board_late_init(void)
setenv(cpu_ns_mode, );
}
#endif
+ start_cpu_fan();
+
return 0;
}
diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c
index 842242c..4b0f973 100644
--- a/board/nvidia/p2571/p2571.c
+++ b/board/nvidia/p2571/p2571.c
@@ -9,6 +9,7 @@
#include i2c.h
#include asm/arch/gpio.h
#include asm/arch/pinmux.h
+#include asm/gpio.h
#include max77620_init.h
#include pinmux-config-p2571.h
@@ -49,3 +50,14 @@ void pinmux_init(void)
pinmux_config_drvgrp_table(p2571_drvgrps,
ARRAY_SIZE(p2571_drvgrps));
}
+
+/*
+ * Routine: start_cpu_fan
+ * Description: Enable/start PWM CPU fan on Foster-FFD
+ */
+void start_cpu_fan(void)
+{
+ /* GPIO_PE4 is PS_VDD_FAN_ENABLE */
+ gpio_request(GPIO_PE4, FAN_VDD);
+ gpio_direction_output(GPIO_PE4, 1);
+}
--
1.8.2.1.610.g562af5b
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[U-Boot] [PATCH] T210: P2571: Enable SD-card power via PMIC LDO2
This was done in the 32-bit AVP loader (SPL) but is
board-specific so should be moved to the CPU portion.
Signed-off-by: Tom Warren twar...@nvidia.com
---
board/nvidia/p2571/Makefile| 1 -
board/nvidia/p2571/max77620_init.c | 85 --
board/nvidia/p2571/max77620_init.h | 3 +-
board/nvidia/p2571/p2571.c | 22 ++
4 files changed, 24 insertions(+), 87 deletions(-)
delete mode 100644 board/nvidia/p2571/max77620_init.c
diff --git a/board/nvidia/p2571/Makefile b/board/nvidia/p2571/Makefile
index 223062e..627b7ef 100644
--- a/board/nvidia/p2571/Makefile
+++ b/board/nvidia/p2571/Makefile
@@ -5,5 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += max77620_init.o
obj-y += p2571.o
diff --git a/board/nvidia/p2571/max77620_init.c
b/board/nvidia/p2571/max77620_init.c
deleted file mode 100644
index ed8d4dc..000
--- a/board/nvidia/p2571/max77620_init.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2013-2015
- * NVIDIA Corporation www.nvidia.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include common.h
-#include asm/io.h
-#include asm/arch-tegra/tegra_i2c.h
-#include max77620_init.h
-
-/* MAX77620-PMIC-specific early init code - get CPU rails up, etc */
-
-void tegra_i2c_ll_write_addr(uint addr, uint config)
-{
- struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
-
- writel(addr, reg-cmd_addr0);
- writel(config, reg-cnfg);
-}
-
-void tegra_i2c_ll_write_data(uint data, uint config)
-{
- struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
-
- writel(data, reg-cmd_data1);
- writel(config, reg-cnfg);
-}
-
-void pmic_enable_cpu_vdd(void)
-{
- uint reg;
- debug(%s entry\n, __func__);
-
- /* Setup/Enable GPIO5 - VDD_CPU_REG_EN */
- debug(%s: Setting GPIO5 to enable CPU regulator\n, __func__);
- /* B3=1=logic high,B2=dontcare,B1=0=output,B0=1=push-pull */
- reg = 0x0900 | MAX77620_GPIO5_REG;
- tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
- udelay(10 * 1000);
-
- /* Setup/Enable GPIO1 - VDD_HDMI_5V0_BST_EN */
- debug(%s: Setting GPIO1 to enable HDMI\n, __func__);
- reg = 0x0900 | MAX77620_GPIO1_REG;
- tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
- udelay(10 * 1000);
-
- /* GPIO 0,1,5,6,7 = GPIO, 2,3,4 = alt mode */
- reg = 0x1C00 | MAX77620_AME_GPIO;
- tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
- udelay(10 * 1000);
-
- /* Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125v */
- debug(%s: Set SD1 for LPDDR4, disable SD1RS, voltage to 1.125v\n,
- __func__);
- /* bit1=0, SD1 remote sense disabled */
- reg = 0x0400 | MAX77620_CNFG2SD_REG;
- tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
- udelay(10 * 1000);
-
- /* SD1 output = 1.125V */
- reg = 0x2A00 | MAX77620_SD1_REG;
- tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
- udelay(10 * 1000);
-
- debug(%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n, __func__);
- /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
- reg = 0xF200 | MAX77620_CNFG1_L2_REG;
- tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
- udelay(10 * 1000);
-
- debug(%s: Set LDO1 for USB3 phy power to 1.05V??\n, __func__);
- /* 0xCA for 105v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
- reg = 0xCA00 | MAX77620_CNFG1_L1_REG;
- tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
- udelay(10 * 1000);
-}
diff --git a/board/nvidia/p2571/max77620_init.h
b/board/nvidia/p2571/max77620_init.h
index 9d5cce7..92c3719 100644
--- a/board/nvidia/p2571/max77620_init.h
+++ b/board/nvidia/p2571/max77620_init.h
@@ -10,7 +10,8 @@
/* MAX77620-PMIC-specific early init regs */
-#define MAX77620_I2C_ADDR 0x78/* or 0x3C 7-bit */
+#define MAX77620_I2C_ADDR 0x78
+#define MAX77620_I2C_ADDR_7BIT 0x3C
#define MAX77620_SD0_REG 0x16
#define MAX77620_SD1_REG 0x17
diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c
index fc710c1..842242c 100644
--- a/board/nvidia/p2571/p2571.c
+++ b/board/nvidia/p2571/p2571.c
@@ -6,10 +6,32 @@
*/
#include common.h
+#include i2c.h
#include asm/arch/gpio.h
#include asm/arch/pinmux.h
+#include max77620_init.h
#include pinmux-config-p2571.h
+void pin_mux_mmc(void)
+{
+ struct udevice *dev;
+ uchar val;
+ int ret;
+
+ /* Turn on MAX77620 LDO2 to 3.3V for SD card power */
+ debug(%s: Set LDO2
[U-Boot] [PATCH] T210: P2571: Restore USB gadget mode (ums)
The tegra-common-usb-gadget.h include was causing some build problems in ci_udc.c with a 64-bit gcc in an earlier version of the T210 patches, but it is working fine now, so restore it. Signed-off-by: Tom Warren twar...@nvidia.com --- include/configs/p2571.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/p2571.h b/include/configs/p2571.h index 77faf5f..d39fa2a 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -68,6 +68,7 @@ * TODO(twar...@nvidia.com) - add tegra-common-usb-gadget.h back * breaks 64-bit build in ci_udc.c */ +#include tegra-common-usb-gadget.h #include tegra-common-post.h #define COUNTER_FREQUENCY 3840 -- 1.8.2.1.610.g562af5b ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V3 6/6] T210: Add support for 64-bit T210-based P2571 board
-Original Message- From: Thierry Reding Sent: Wednesday, July 29, 2015 4:08 AM To: Stephen Warren Cc: Tom Warren; u-boot@lists.denx.de; Stephen Warren; tomcwarren3...@gmail.com Subject: Re: [U-Boot] [PATCH V3 6/6] T210: Add support for 64-bit T210-based P2571 board On Tue, Jul 28, 2015 at 01:27:07PM -0600, Stephen Warren wrote: On 07/24/2015 04:01 PM, Tom Warren wrote: Based on Venice2, incorporates Stephen Warren's latest P2571 pinmux table. With Thierry Reding's 64-bit build fixes, this will build and and boot in 64-bit on my P2571 (when used with a 32-bit AVP loader). diff --git a/board/nvidia/p2571/max77620_init.c b/board/nvidia/p2571/max77620_init.c +void pmic_enable_cpu_vdd(void) This function is never called, or even linked into the binary. For previous Tegra SoCs, it was called from the SPL before booting the CCPLEX. Since there is no SPL for Tegra210, nothing calls this. + debug(%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n, __func__); + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + reg = 0xF200 | MAX77620_CNFG1_L2_REG; + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); + udelay(10 * 1000); This explains why the SD card isn't working for me on p2371-2180; I guess the PMIC OTP on that board has this regulator disabled, and since this code never runs, it never gets turned on. If I manually turn it on using the i2c command, then mmc dev 1 works. For p2571, I think we should either delete this file entirely. Or, at least strip it down so that it's not touching global PMIC configuration but rather just enabling any non-CCPLEX rails that U-Boot might need such as SD card and USB, then rename the function and arrange for it to be called from somewhere. I'm not sure what a good name and call-site would be yet. Have you looked at my P2371 support patches? Specifically commit ARM: tegra: Add NVIDIA P2371 support has the board-level code that I've used to boot upstream on the device. There's a board_mmc_power_init() implementation which overrides the weak dummy provided in drivers/mmc/mmc.c. Thierry There's also pin_mux_mmc() which a few Tegra boards are already using. I have an implementation for P2571 that I'll be uploading soon for review. Tom -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] ARM: tegra: Add p2371-0000 board
Stephen,
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Wednesday, July 29, 2015 12:49 PM
To: u-boot@lists.denx.de; Simon Glass; Tom Warren; Stephen Warren
Cc: Thierry Reding
Subject: [PATCH 2/2] ARM: tegra: Add p2371- board
From: Stephen Warren swar...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/tegra210-p2371-.dts | 59 +
arch/arm/mach-tegra/tegra210/Kconfig | 6 +
board/nvidia/p2371-/Kconfig| 12 +
board/nvidia/p2371-/MAINTAINERS| 6 +
board/nvidia/p2371-/Makefile | 8 +
board/nvidia/p2371-/p2371-.c | 48
board/nvidia/p2371-/pinmux-config-p2371-.h | 260
+
configs/p2371-_defconfig | 16 ++
include/configs/p2371-.h | 72 ++
10 files changed, 488 insertions(+)
create mode 100644 arch/arm/dts/tegra210-p2371-.dts
create mode 100644 board/nvidia/p2371-/Kconfig create mode 100644
board/nvidia/p2371-/MAINTAINERS
create mode 100644 board/nvidia/p2371-/Makefile create mode 100644
board/nvidia/p2371-/p2371-.c
create mode 100644 board/nvidia/p2371-/pinmux-config-p2371-.h
create mode 100644 configs/p2371-_defconfig create mode 100644
include/configs/p2371-.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
d8e1841eb4d8..f61060fc92e5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -34,6 +34,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra124-nyan-big.dtb \
tegra124-venice2.dtb \
tegra210-e2220-1170.dtb \
+ tegra210-p2371-.dtb \
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
diff --git a/arch/arm/dts/tegra210-p2371-.dts b/arch/arm/dts/tegra210-
p2371-.dts
new file mode 100644
index ..10172a23ad70
--- /dev/null
+++ b/arch/arm/dts/tegra210-p2371-.dts
@@ -0,0 +1,59 @@
+/dts-v1/;
+
+#include tegra210.dtsi
+
+/ {
+ model = NVIDIA P2371-;
+ compatible = nvidia,p2371-, nvidia,tegra210;
+
+ chosen {
+ stdout-path = uarta;
+ };
+
+ aliases {
+ i2c0 = /i2c@0,7000d000;
+ sdhci0 = /sdhci@0,700b0600;
+ sdhci1 = /sdhci@0,700b;
+ usb0 = /usb@0,7d00;
+ };
+
+ memory {
+ reg = 0x0 0x8000 0x0 0xc000;
+ };
+
+ sdhci@0,700b {
+ status = okay;
+ cd-gpios = gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW;
+ power-gpios = gpio TEGRA_GPIO(Z, 4)
GPIO_ACTIVE_HIGH;
+ bus-width = 4;
+ };
+
+ sdhci@0,700b0600 {
+ status = okay;
+ bus-width = 8;
+ };
+
+ i2c@0,7000d000 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ usb@0,7d00 {
+ status = okay;
+ dr_mode = otg;
+ nvidia,vbus-gpio = gpio TEGRA_GPIO(CC, 4)
GPIO_ACTIVE_HIGH;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ clk32k_in: clock@0 {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 32768;
+ };
+ };
+};
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-
tegra/tegra210/Kconfig
index 9633ba8c629e..895002c5942b 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -8,6 +8,11 @@ config TARGET_E2220_1170
help
E2220-1170 ERS
+config TARGET_P2371_
+ bool NVIDIA Tegra210 P2371- base board
+ help
+ P2371-
+
config TARGET_P2571
bool NVIDIA Tegra210 P2571 base board
help
@@ -19,6 +24,7 @@ config SYS_SOC
default tegra210
source board/nvidia/e2220-1170/Kconfig
+source board/nvidia/p2371-/Kconfig
source board/nvidia/p2571/Kconfig
endif
diff --git a/board/nvidia/p2371-/Kconfig b/board/nvidia/p2371-
/Kconfig new file mode 100644 index ..f94be12be1a0
--- /dev/null
+++ b/board/nvidia/p2371-/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P2371_
+
+config SYS_BOARD
+ default p2371-
+
+config SYS_VENDOR
+ default nvidia
+
+config SYS_CONFIG_NAME
+ default p2371-
+
+endif
diff --git a/board/nvidia/p2371-/MAINTAINERS b/board/nvidia/p2371-
/MAINTAINERS
new file mode 100644
index ..e6d04bf7c5e1
--- /dev/null
+++ b/board/nvidia/p2371-/MAINTAINERS
@@ -0,0 +1,6 @@
+P2371- BOARD
+M: Tom Warren twar...@nvidia.com
Shouldn't
[U-Boot] [PATCH 2/2] Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Added PLL variables (dividers mask/shift, lock enable/detect, etc.)
to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X.
Used pllinfo struct in all clock functions, validated on T210.
Should be equivalent to prior code on T124/114/30/20 but needs test.
Corrections to divm mask vs shift and T20/30 divN masks thanks to
Marcel Ziswiler.
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/include/asm/arch-tegra/clk_rst.h | 32 +--
arch/arm/include/asm/arch-tegra/clock.h | 21 +
arch/arm/include/asm/arch-tegra210/clock-tables.h | 1 +
arch/arm/mach-tegra/clock.c | 108 --
arch/arm/mach-tegra/cpu.c | 18 ++--
arch/arm/mach-tegra/tegra114/clock.c | 57 +---
arch/arm/mach-tegra/tegra114/cpu.c| 39 +++-
arch/arm/mach-tegra/tegra124/clock.c | 44 -
arch/arm/mach-tegra/tegra124/cpu.c| 31 +++
arch/arm/mach-tegra/tegra20/clock.c | 32 +++
arch/arm/mach-tegra/tegra210/clock.c | 31 ++-
arch/arm/mach-tegra/tegra30/clock.c | 45 ++---
12 files changed, 285 insertions(+), 174 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h
b/arch/arm/include/asm/arch-tegra/clk_rst.h
index f690260..ee9436e 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -249,17 +249,6 @@ struct clk_rst_ctlr {
#define PLL_LOCK_SHIFT 27
#define PLL_LOCK_MASK (1U PLL_LOCK_SHIFT)
-#define PLL_DIVP_SHIFT 20
-#define PLL_DIVP_MASK (7U PLL_DIVP_SHIFT)
-/* Special case for T210 PLLU DIVP */
-#define PLLU_DIVP_SHIFT16
-
-#define PLL_DIVN_SHIFT 8
-#define PLL_DIVN_MASK (0x3ffU PLL_DIVN_SHIFT)
-
-#define PLL_DIVM_SHIFT 0
-#define PLL_DIVM_MASK (0x1f PLL_DIVM_SHIFT)
-
/* CLK_RST_CONTROLLER_PLLx_OUTx_0 */
#define PLL_OUT_RSTN (1 0)
#define PLL_OUT_CLKEN (1 1)
@@ -272,24 +261,6 @@ struct clk_rst_ctlr {
#define PLL_DCCON_SHIFT20
#define PLL_DCCON_MASK (1U PLL_DCCON_SHIFT)
-#define PLL_LOCK_ENABLE_SHIFT 18
-#define PLL_LOCK_ENABLE_MASK (1U PLL_LOCK_ENABLE_SHIFT)
-
-#define PLL_CPCON_SHIFT8
-#define PLL_CPCON_MASK (15U PLL_CPCON_SHIFT)
-
-#define PLL_LFCON_SHIFT4
-#define PLL_LFCON_MASK (15U PLL_LFCON_SHIFT)
-
-/* CPCON/LFCON replaced by KCP/KVCO in T210 PLLU */
-#define PLLU_KVCO_SHIFT24
-#define PLLU_KVCO_MASK (3U PLLU_KVCO_SHIFT)
-#define PLLU_KCP_SHIFT 25
-#define PLLU_KCP_MASK (1U PLLU_KCP_SHIFT)
-
-#define PLLU_VCO_FREQ_SHIFT20
-#define PLLU_VCO_FREQ_MASK (1U PLLU_VCO_FREQ_SHIFT)
-
#define PLLP_OUT1_OVR (1 2)
#define PLLP_OUT2_OVR (1 18)
#define PLLP_OUT3_OVR (1 2)
@@ -475,4 +446,7 @@ enum {
#define PLLDP_SS_CFG_UNDOCUMENTED (1 24)
#define PLLDP_SS_CFG_DITHER(1 28)
+/* CLK_RST_PLLD_MISC */
+#define PLLD_CLKENABLE 30
+
#endif /* _TEGRA_CLK_RST_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/clock.h
b/arch/arm/include/asm/arch-tegra/clock.h
index 2274b14..d570d7f 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -338,6 +338,27 @@ void arch_timer_init(void);
void tegra30_set_up_pllp(void);
+/* Number of PLL-based clocks (i.e. not OSC or 32KHz) */
+#define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 2)
+
+struct clk_pll_info {
+ u32 m_shift:5; /* DIVM_SHIFT */
+ u32 n_shift:5; /* DIVN_SHIFT */
+ u32 p_shift:5; /* DIVP_SHIFT */
+ u32 kcp_shift:5;/* KCP/cpcon SHIFT */
+ u32 kvco_shift:5; /* KVCO/lfcon SHIFT */
+ u32 lock_ena:6; /* LOCK_ENABLE/EN_LOCKDET shift */
+ u32 rsvd:1;
+ u32 m_mask:10; /* DIVM_MASK */
+ u32 n_mask:12; /* DIVN_MASK */
+ u32 p_mask:10; /* DIVP_MASK or VCO_MASK */
+ u32 kcp_mask:10;/* KCP/CPCON MASK */
+ u32 kvco_mask:10; /* KVCO/LFCON MASK */
+ u32 lock_det:6; /* LOCK_DETECT/LOCKED shift */
+ u32 rsvd2:6;
+};
+extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT];
+
/**
* Enable output clock for external peripherals
*
diff --git a/arch/arm/include/asm/arch-tegra210/clock-tables.h
b/arch/arm/include/asm/arch-tegra210/clock-tables.h
index b62e070..175040d 100644
--- a/arch/arm/include/asm/arch-tegra210/clock-tables.h
+++ b/arch/arm/include/asm/arch-tegra210/clock-tables.h
@@ -25,6 +25,7 @@ enum clock_id {
CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
CLOCK_ID_EPCI,
CLOCK_ID_SFROM32KHZ,
+ CLOCK_ID_DP,
/* These are the base clocks (inputs to the Tegra SoC) */
CLOCK_ID_32KHZ,
diff --git a/arch/arm/mach
[U-Boot] [PATCH 1/2] Tegra: clocks: Add 38.4MHz OSC support for T210 use
Added 38.4MHz/48MHz entries to pll_x_table for CPU PLL. Needs
to be measured - should be close to 700MHz (1.4G/2).
Note that some freqs aren't in the PLLU table in T210 TRM
(13, 26MHz), so I used the 12MHz table entry for them. They
shouldn't be selected since they're not viable T210 OSC freqs.
Since there are now 2 new OSC defines, all tables (pll_x_table,
PLLU) had to increase by two entries, but since 38.4/48MHz are
not viable osc freqs on T20/30/114, etc, they're just set to 0.
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/include/asm/arch-tegra/clock.h | 2 ++
arch/arm/mach-tegra/clock.c | 13 +
arch/arm/mach-tegra/cpu.c | 12
arch/arm/mach-tegra/tegra210/clock.c| 8 ++--
drivers/usb/host/ehci-tegra.c | 18 +-
5 files changed, 42 insertions(+), 11 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/clock.h
b/arch/arm/include/asm/arch-tegra/clock.h
index f9dd3c8..2274b14 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -16,6 +16,8 @@ enum clock_osc_freq {
CLOCK_OSC_FREQ_19_2,
CLOCK_OSC_FREQ_12_0,
CLOCK_OSC_FREQ_26_0,
+ CLOCK_OSC_FREQ_38_4,
+ CLOCK_OSC_FREQ_48_0,
CLOCK_OSC_FREQ_COUNT,
};
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 5d968d8..d0eebd2 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -44,6 +44,8 @@ static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
1920,
1200,
2600,
+ 3840,
+ 4800,
};
/* return 1 if a peripheral ID is in range */
@@ -620,17 +622,20 @@ int clock_verify(void)
void clock_init(void)
{
+ pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
- pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
+ pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB);
pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY);
- pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
- pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
+ pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
+ pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
+
debug(Osc = %d\n, pll_rate[CLOCK_ID_OSC]);
+ debug(PLLC = %d\n, pll_rate[CLOCK_ID_CGENERAL]);
debug(PLLM = %d\n, pll_rate[CLOCK_ID_MEMORY]);
debug(PLLP = %d\n, pll_rate[CLOCK_ID_PERIPH]);
- debug(PLLC = %d\n, pll_rate[CLOCK_ID_CGENERAL]);
+ debug(PLLU = %d\n, pll_rate[CLOCK_ID_USB]);
debug(PLLD = %d\n, pll_rate[CLOCK_ID_DISPLAY]);
debug(PLLX = %d\n, pll_rate[CLOCK_ID_XCPU]);
}
diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c
index f7d45e8..b9391d6 100644
--- a/arch/arm/mach-tegra/cpu.c
+++ b/arch/arm/mach-tegra/cpu.c
@@ -67,6 +67,8 @@ struct clk_pll_table
tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
{ .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
{ .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
+ { .n =0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz
(N/A) */
+ { .n =0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz
(N/A) */
},
/*
* T25: 1.2 GHz
@@ -83,6 +85,8 @@ struct clk_pll_table
tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
{ .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
{ .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz
(N/A) */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz
(N/A) */
},
/*
* T30: 600 MHz
@@ -99,6 +103,8 @@ struct clk_pll_table
tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
{ .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
{ .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz
(N/A) */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz
(N/A) */
},
/*
* T114: 700 MHz
@@ -114,6 +120,8 @@ struct clk_pll_table
tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz
Re: [U-Boot] [PATCH V2 1/2] ARM: tegra: Add e2220-1170 board
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Wednesday, July 29, 2015 1:17 PM
To: u-boot@lists.denx.de; Simon Glass; Tom Warren; Stephen Warren
Cc: Thierry Reding
Subject: [PATCH V2 1/2] ARM: tegra: Add e2220-1170 board
From: Stephen Warren swar...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
v2: Use named constants for PMIC I2C and register addresses.
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/tegra210-e2220-1170.dts | 58 +
arch/arm/mach-tegra/tegra210/Kconfig | 6 +
board/nvidia/e2220-1170/Kconfig| 12 +
board/nvidia/e2220-1170/MAINTAINERS| 6 +
board/nvidia/e2220-1170/Makefile | 8 +
board/nvidia/e2220-1170/e2220-1170.c | 51
board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 269
+
configs/e2220-1170_defconfig | 16 ++
include/configs/e2220-1170.h | 72 ++
10 files changed, 499 insertions(+)
create mode 100644 arch/arm/dts/tegra210-e2220-1170.dts
create mode 100644 board/nvidia/e2220-1170/Kconfig create mode 100644
board/nvidia/e2220-1170/MAINTAINERS
create mode 100644 board/nvidia/e2220-1170/Makefile create mode 100644
board/nvidia/e2220-1170/e2220-1170.c
create mode 100644 board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
create mode 100644 configs/e2220-1170_defconfig create mode 100644
include/configs/e2220-1170.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
ba6355379cba..d8e1841eb4d8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -33,6 +33,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-venice2.dtb \
+ tegra210-e2220-1170.dtb \
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
diff --git a/arch/arm/dts/tegra210-e2220-1170.dts b/arch/arm/dts/tegra210-
e2220-1170.dts
new file mode 100644
index ..75efbba1061e
--- /dev/null
+++ b/arch/arm/dts/tegra210-e2220-1170.dts
@@ -0,0 +1,58 @@
+/dts-v1/;
+
+#include tegra210.dtsi
+
+/ {
+ model = NVIDIA E2220-1170;
+ compatible = nvidia,e2220-1170, nvidia,tegra210;
+
+ chosen {
+ stdout-path = uarta;
+ };
+
+ aliases {
+ i2c0 = /i2c@0,7000d000;
+ sdhci0 = /sdhci@0,700b0600;
+ sdhci1 = /sdhci@0,700b;
+ usb0 = /usb@0,7d00;
+ };
+
+ memory {
+ reg = 0x0 0x8000 0x0 0xc000;
+ };
+
+ sdhci@0,700b {
+ status = okay;
+ cd-gpios = gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW;
+ power-gpios = gpio TEGRA_GPIO(Z, 4)
GPIO_ACTIVE_HIGH;
+ bus-width = 4;
+ };
+
+ sdhci@0,700b0600 {
+ status = okay;
+ bus-width = 8;
+ };
+
+ i2c@0,7000d000 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ usb@0,7d00 {
+ status = okay;
+ dr_mode = peripheral;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ clk32k_in: clock@0 {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 32768;
+ };
+ };
+};
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-
tegra/tegra210/Kconfig
index 147e6a83d722..9633ba8c629e 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -3,6 +3,11 @@ if TEGRA210
choice
prompt Tegra210 board select
+config TARGET_E2220_1170
+ bool NVIDIA Tegra210 E2220-1170 base board
+ help
+ E2220-1170 ERS
+
config TARGET_P2571
bool NVIDIA Tegra210 P2571 base board
help
@@ -13,6 +18,7 @@ endchoice
config SYS_SOC
default tegra210
+source board/nvidia/e2220-1170/Kconfig
source board/nvidia/p2571/Kconfig
endif
diff --git a/board/nvidia/e2220-1170/Kconfig b/board/nvidia/e2220-
1170/Kconfig new file mode 100644 index ..0a30f4936223
--- /dev/null
+++ b/board/nvidia/e2220-1170/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_E2220_1170
+
+config SYS_BOARD
+ default e2220-1170
+
+config SYS_VENDOR
+ default nvidia
+
+config SYS_CONFIG_NAME
+ default e2220-1170
+
+endif
diff --git a/board/nvidia/e2220-1170/MAINTAINERS b/board/nvidia/e2220-
1170/MAINTAINERS
new file mode 100644
index ..0abb37884018
--- /dev/null
+++ b/board/nvidia/e2220-1170/MAINTAINERS
@@ -0,0 +1,6 @@
+E2220-1170 BOARD
+M: Tom Warren twar...@nvidia.com
+S: Maintained
+F: board/nvidia/e2220-1170
Re: [U-Boot] [PATCH 1/2] ARM: tegra: Add e2220-1170 board
Simon,
I can respond to your Kconfig questions below.
-Original Message-
From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
Sent: Wednesday, July 29, 2015 4:02 PM
To: Stephen Warren
Cc: U-Boot Mailing List; Tom Warren; Stephen Warren; Thierry Reding
Subject: Re: [PATCH 1/2] ARM: tegra: Add e2220-1170 board
Hi Stephen,
On 29 July 2015 at 13:48, Stephen Warren swar...@wwwdotorg.org wrote:
Commit message?
From: Stephen Warren swar...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/tegra210-e2220-1170.dts | 58 +
arch/arm/mach-tegra/tegra210/Kconfig | 6 +
board/nvidia/e2220-1170/Kconfig| 12 +
board/nvidia/e2220-1170/MAINTAINERS| 6 +
board/nvidia/e2220-1170/Makefile | 8 +
board/nvidia/e2220-1170/e2220-1170.c | 48
board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 269
+
configs/e2220-1170_defconfig | 16 ++
include/configs/e2220-1170.h | 72 ++
10 files changed, 496 insertions(+)
create mode 100644 arch/arm/dts/tegra210-e2220-1170.dts
create mode 100644 board/nvidia/e2220-1170/Kconfig create mode
100644 board/nvidia/e2220-1170/MAINTAINERS
create mode 100644 board/nvidia/e2220-1170/Makefile create mode
100644 board/nvidia/e2220-1170/e2220-1170.c
create mode 100644 board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
create mode 100644 configs/e2220-1170_defconfig create mode 100644
include/configs/e2220-1170.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
ba6355379cba..d8e1841eb4d8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -33,6 +33,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-venice2.dtb \
+ tegra210-e2220-1170.dtb \
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
diff --git a/arch/arm/dts/tegra210-e2220-1170.dts
b/arch/arm/dts/tegra210-e2220-1170.dts
new file mode 100644
index ..75efbba1061e
--- /dev/null
+++ b/arch/arm/dts/tegra210-e2220-1170.dts
@@ -0,0 +1,58 @@
+/dts-v1/;
+
+#include tegra210.dtsi
+
+/ {
+ model = NVIDIA E2220-1170;
+ compatible = nvidia,e2220-1170, nvidia,tegra210;
+
+ chosen {
+ stdout-path = uarta;
+ };
+
+ aliases {
+ i2c0 = /i2c@0,7000d000;
+ sdhci0 = /sdhci@0,700b0600;
+ sdhci1 = /sdhci@0,700b;
+ usb0 = /usb@0,7d00;
+ };
+
+ memory {
+ reg = 0x0 0x8000 0x0 0xc000;
+ };
+
+ sdhci@0,700b {
+ status = okay;
+ cd-gpios = gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW;
+ power-gpios = gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH;
+ bus-width = 4;
+ };
+
+ sdhci@0,700b0600 {
+ status = okay;
+ bus-width = 8;
+ };
+
+ i2c@0,7000d000 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ usb@0,7d00 {
+ status = okay;
+ dr_mode = peripheral;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ clk32k_in: clock@0 {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 32768;
+ };
+ };
+};
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig
b/arch/arm/mach-tegra/tegra210/Kconfig
index 147e6a83d722..9633ba8c629e 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -3,6 +3,11 @@ if TEGRA210
choice
prompt Tegra210 board select
+config TARGET_E2220_1170
+ bool NVIDIA Tegra210 E2220-1170 base board
+ help
+ E2220-1170 ERS
Er, description?
+
config TARGET_P2571
bool NVIDIA Tegra210 P2571 base board
help
@@ -13,6 +18,7 @@ endchoice
config SYS_SOC
default tegra210
+source board/nvidia/e2220-1170/Kconfig
source board/nvidia/p2571/Kconfig
endif
diff --git a/board/nvidia/e2220-1170/Kconfig
b/board/nvidia/e2220-1170/Kconfig new file mode 100644 index
..0a30f4936223
--- /dev/null
+++ b/board/nvidia/e2220-1170/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_E2220_1170
+
+config SYS_BOARD
+ default e2220-1170
+
+config SYS_VENDOR
+ default nvidia
[U-Boot] Pull request: u-boot-tegra/master
Tom, Please pull u-boot-tegra/master into U-Boot/master. Thanks! ./MAKEALL -s tegra is OK (all 32-bit builds), and ./MAKEALL -a aarch64 is OK (includes p2571) The following changes since commit 26473945ad6667183296e7edee2a65edf31bb6f7: Merge branch 'master' of http://git.denx.de/u-boot-sunxi (2015-07-25 09:04:18 -0400) are available in the git repository at: git://git.denx.de/u-boot-tegra.git master for you to fetch changes up to e3ab4e38ef7f4df76896be415a47cc8f7de64f8a: T210: Add support for 64-bit T210-based P2571 board (2015-07-27 15:55:55 -0700) Simon Glass (3): tegra124: Implement spl_was_boot_source() tegra: nyan-big: Allow TPM on I2C tegra124: Expand SPL space by 8KB Stephen Warren (2): pxe: add AArch64 image support dfu: fix 64-bit compile warnings Thierry Reding (10): i2c: tegra: Build warning fixes for 64-bit mmc: tegra: Build warning fixes for 64-bit ARM: tegra: Build warning fixes for 64-bit arm64: Handle arbitrary CONFIG_SYS_MALLOC_F_LEN values armv8: Allow SoCs to override the generic timer armv8/cache: Fix page table creation fdt: Fix fdtdec_get_addr_size() for 64-bit ARM: tegra: Restrict usable RAM to 32-bit on 64-bit SoCs ARM: tegra: Use standard cache enable for 64-bit ARM: tegra: Disable SPL and non-cached memory on 64-bit Tom Warren (6): Tegra210: Fix 64-bit build warning about save_boot_params_ret() Tegra: Rework KConfig options to allow 64-bit builds (T210) ARM: Tegra210: Add SoC code/include files for T210 ARM: Tegra210: Add support to common Tegra source/config files P2571: dts: Add DT file for Tegra210 P2571 board T210: Add support for 64-bit T210-based P2571 board arch/arm/Kconfig | 11 - arch/arm/cpu/armv8/cache_v8.c |4 +- arch/arm/cpu/armv8/generic_timer.c|2 + arch/arm/dts/Makefile |3 +- arch/arm/dts/tegra210-p2571.dts | 106 ++ arch/arm/dts/tegra210.dtsi| 283 ++ arch/arm/include/asm/arch-tegra/ap.h |6 +- arch/arm/include/asm/arch-tegra/clk_rst.h | 36 +- arch/arm/include/asm/arch-tegra/gp_padctrl.h |3 +- arch/arm/include/asm/arch-tegra/pmc.h |7 +- arch/arm/include/asm/arch-tegra/tegra.h |4 +- arch/arm/include/asm/arch-tegra/usb.h |3 + arch/arm/include/asm/arch-tegra210/ahb.h | 91 ++ arch/arm/include/asm/arch-tegra210/clock-tables.h | 566 +++ arch/arm/include/asm/arch-tegra210/clock.h| 27 + arch/arm/include/asm/arch-tegra210/flow.h | 45 + arch/arm/include/asm/arch-tegra210/funcmux.h | 23 + arch/arm/include/asm/arch-tegra210/gp_padctrl.h | 74 ++ arch/arm/include/asm/arch-tegra210/gpio.h | 303 ++ arch/arm/include/asm/arch-tegra210/mc.h | 72 ++ arch/arm/include/asm/arch-tegra210/pmu.h | 14 + arch/arm/include/asm/arch-tegra210/powergate.h| 12 + arch/arm/include/asm/arch-tegra210/sysctr.h | 26 + arch/arm/include/asm/arch-tegra210/tegra.h| 32 + arch/arm/lib/crt0_64.S|3 +- arch/arm/mach-tegra/Kconfig | 30 + arch/arm/mach-tegra/Makefile |5 +- arch/arm/mach-tegra/ap.c | 15 +- arch/arm/mach-tegra/board.c | 30 +- arch/arm/mach-tegra/board2.c | 16 + arch/arm/mach-tegra/cache.c |2 + arch/arm/mach-tegra/clock.c | 30 +- arch/arm/mach-tegra/cpu.c | 55 +- arch/arm/mach-tegra/cpu.h | 10 +- arch/arm/mach-tegra/lowlevel_init.S | 15 + arch/arm/mach-tegra/pinmux-common.c |2 +- arch/arm/mach-tegra/tegra210/Kconfig | 18 + arch/arm/mach-tegra/tegra210/Makefile | 11 + arch/arm/mach-tegra/tegra210/clock.c | 1091 + arch/arm/mach-tegra/tegra210/funcmux.c| 40 + arch/arm/mach-tegra/tegra210/xusb-padctl.c| 495 ++ board/nvidia/nyan-big/pinmux-config-nyan-big.h|8 +- board/nvidia/p2571/Kconfig| 12 + board/nvidia/p2571/MAINTAINERS|6 + board/nvidia/p2571/Makefile |9 + board/nvidia/p2571/max77620_init.c| 85 ++ board/nvidia/p2571/max77620_init.h| 67 ++ board/nvidia/p2571/p2571.c| 29 + board/nvidia/p2571/pinmux-config-p2571.h | 235 + common/cmd_pxe.c |8 +- configs/p2571_defconfig | 16 + drivers/dfu/dfu.c
Re: [U-Boot] Pull request: u-boot-tegra/master
Yep, saw Thierry's update after I sent the PR. I'll rework it, test and resend. Thanks. On Tue, Jul 28, 2015 at 8:51 AM, Stephen Warren swar...@wwwdotorg.org wrote: On 07/28/2015 09:31 AM, Tom Warren wrote: Tom, Please pull u-boot-tegra/master into U-Boot/master. Thanks! Thierry Reding (10): armv8: Allow SoCs to override the generic timer Apparently there were objections to that patch the last time it was posted: http://lists.denx.de/pipermail/u-boot/2015-July/220918.html Re: [PATCH] armv8: Allow SoCs to override the generic timer Thierry posted a couple of replacement patches for this: http://lists.denx.de/pipermail/u-boot/2015-July/220919.html [PATCH 1/2] ARM: tegra: Initialize timer earlier http://lists.denx.de/pipermail/u-boot/2015-July/220920.html [PATCH 2/2] ARM: tegra: Use architected timer on ARMv8 I suspect we should drop this pull request and swap in the new patch, provided it tests out OK? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-tegra/master, 2nd try
Tom, Please pull u-boot-tegra/master into U-Boot/master. Thierry's ARM timer patches have been updated. Thanks! ./MAKEALL -s tegra is OK (all 32-bit builds), and ./MAKEALL -a aarch64 is OK (includes p2571) The following changes since commit 26473945ad6667183296e7edee2a65edf31bb6f7: Merge branch 'master' of http://git.denx.de/u-boot-sunxi (2015-07-25 09:04:18 -0400) are available in the git repository at: git://git.denx.de/u-boot-tegra.git master for you to fetch changes up to 873e3ef90ba98c764af6e05251354332205b9d3a: T210: Add support for 64-bit T210-based P2571 board (2015-07-28 10:30:20 -0700) Simon Glass (3): tegra124: Implement spl_was_boot_source() tegra: nyan-big: Allow TPM on I2C tegra124: Expand SPL space by 8KB Stephen Warren (2): pxe: add AArch64 image support dfu: fix 64-bit compile warnings Thierry Reding (11): i2c: tegra: Build warning fixes for 64-bit mmc: tegra: Build warning fixes for 64-bit ARM: tegra: Build warning fixes for 64-bit arm64: Handle arbitrary CONFIG_SYS_MALLOC_F_LEN values armv8/cache: Fix page table creation fdt: Fix fdtdec_get_addr_size() for 64-bit ARM: tegra: Restrict usable RAM to 32-bit on 64-bit SoCs ARM: tegra: Use standard cache enable for 64-bit ARM: tegra: Disable SPL and non-cached memory on 64-bit ARM: tegra: Initialize timer earlier ARM: tegra: Use architected timer on ARMv8 Tom Warren (6): Tegra210: Fix 64-bit build warning about save_boot_params_ret() Tegra: Rework KConfig options to allow 64-bit builds (T210) ARM: Tegra210: Add SoC code/include files for T210 ARM: Tegra210: Add support to common Tegra source/config files P2571: dts: Add DT file for Tegra210 P2571 board T210: Add support for 64-bit T210-based P2571 board arch/arm/Kconfig | 11 - arch/arm/cpu/armv8/cache_v8.c |4 +- arch/arm/dts/Makefile |3 +- arch/arm/dts/tegra210-p2571.dts | 106 ++ arch/arm/dts/tegra210.dtsi| 283 ++ arch/arm/include/asm/arch-tegra/ap.h |6 +- arch/arm/include/asm/arch-tegra/clk_rst.h | 36 +- arch/arm/include/asm/arch-tegra/gp_padctrl.h |3 +- arch/arm/include/asm/arch-tegra/pmc.h |7 +- arch/arm/include/asm/arch-tegra/tegra.h |4 +- arch/arm/include/asm/arch-tegra/usb.h |3 + arch/arm/include/asm/arch-tegra210/ahb.h | 91 ++ arch/arm/include/asm/arch-tegra210/clock-tables.h | 566 +++ arch/arm/include/asm/arch-tegra210/clock.h| 27 + arch/arm/include/asm/arch-tegra210/flow.h | 45 + arch/arm/include/asm/arch-tegra210/funcmux.h | 23 + arch/arm/include/asm/arch-tegra210/gp_padctrl.h | 74 ++ arch/arm/include/asm/arch-tegra210/gpio.h | 303 ++ arch/arm/include/asm/arch-tegra210/mc.h | 72 ++ arch/arm/include/asm/arch-tegra210/pmu.h | 14 + arch/arm/include/asm/arch-tegra210/powergate.h| 12 + arch/arm/include/asm/arch-tegra210/sysctr.h | 26 + arch/arm/include/asm/arch-tegra210/tegra.h| 32 + arch/arm/lib/crt0_64.S|3 +- arch/arm/mach-tegra/Kconfig | 30 + arch/arm/mach-tegra/Makefile |5 +- arch/arm/mach-tegra/ap.c | 15 +- arch/arm/mach-tegra/board.c | 30 +- arch/arm/mach-tegra/board2.c | 22 + arch/arm/mach-tegra/cache.c |2 + arch/arm/mach-tegra/clock.c | 36 +- arch/arm/mach-tegra/cpu.c | 55 +- arch/arm/mach-tegra/cpu.h | 10 +- arch/arm/mach-tegra/lowlevel_init.S | 15 + arch/arm/mach-tegra/pinmux-common.c |2 +- arch/arm/mach-tegra/tegra210/Kconfig | 18 + arch/arm/mach-tegra/tegra210/Makefile | 11 + arch/arm/mach-tegra/tegra210/clock.c | 1091 + arch/arm/mach-tegra/tegra210/funcmux.c| 40 + arch/arm/mach-tegra/tegra210/xusb-padctl.c| 495 ++ board/nvidia/nyan-big/pinmux-config-nyan-big.h|8 +- board/nvidia/p2571/Kconfig| 12 + board/nvidia/p2571/MAINTAINERS|6 + board/nvidia/p2571/Makefile |9 + board/nvidia/p2571/max77620_init.c| 85 ++ board/nvidia/p2571/max77620_init.h| 67 ++ board/nvidia/p2571/p2571.c| 29 + board/nvidia/p2571/pinmux-config-p2571.h | 235 + common/cmd_pxe.c |8 +- configs/p2571_defconfig | 16 + drivers
Re: [U-Boot] [PATCH V3 6/6] T210: Add support for 64-bit T210-based P2571 board
-Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Tuesday, July 28, 2015 12:27 PM To: Tom Warren Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren; tomcwarren3...@gmail.com Subject: Re: [U-Boot] [PATCH V3 6/6] T210: Add support for 64-bit T210-based P2571 board On 07/24/2015 04:01 PM, Tom Warren wrote: Based on Venice2, incorporates Stephen Warren's latest P2571 pinmux table. With Thierry Reding's 64-bit build fixes, this will build and and boot in 64-bit on my P2571 (when used with a 32-bit AVP loader). diff --git a/board/nvidia/p2571/max77620_init.c b/board/nvidia/p2571/max77620_init.c +void pmic_enable_cpu_vdd(void) This function is never called, or even linked into the binary. For previous Tegra SoCs, it was called from the SPL before booting the CCPLEX. Since there is no SPL for Tegra210, nothing calls this. + debug(%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n, __func__); + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + reg = 0xF200 | MAX77620_CNFG1_L2_REG; + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); + udelay(10 * 1000); This explains why the SD card isn't working for me on p2371-2180; I guess the PMIC OTP on that board has this regulator disabled, and since this code never runs, it never gets turned on. If I manually turn it on using the i2c command, then mmc dev 1 works. Makes sense. My initial development was on a 32-bit build (32-bit AVP SPL + 32-bit U-Boot CPU), so this was called from the AVP code. I still use this 32-bit AVP SPL 'portion' to load my 64-bit CPU binary, so LDO2 does get inited. Your flow is with a different AVP 32-bit 'loader', so some PMIC rails aren't set. For p2571, I think we should either delete this file entirely. Or, at least strip it down so that it's not touching global PMIC configuration but rather just enabling any non-CCPLEX rails that U-Boot might need such as SD card and USB, then rename the function and arrange for it to be called from somewhere. I'm not sure what a good name and call-site would be yet. Sounds reasonable. I'll look into rewriting this and calling it in the CPU binary, unless you get to it first. Tom -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V3 3/6] ARM: Tegra210: Add SoC code/include files for T210
Stephen,
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Monday, July 27, 2015 10:53 AM
To: Tom Warren
Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren;
tomcwarren3...@gmail.com
Subject: Re: [U-Boot] [PATCH V3 3/6] ARM: Tegra210: Add SoC code/include
files for T210
On 07/24/2015 04:00 PM, Tom Warren wrote:
All based off of Tegra124. As a Tegra210 board is brought up, these
may change a bit to match the HW more closely, but probably 90% of
this is identical to T124.
Note that since T210 is a 64-bit build, it has no SPL component, and
hence no cpu.c for Tegra210.
diff --git a/arch/arm/include/asm/arch-tegra210/funcmux.h
b/arch/arm/include/asm/arch-tegra210/funcmux.h
+#include asm/arch-tegra/funcmux.h
+
+/* Configs supported by the func mux */ enum {
+ FUNCMUX_DEFAULT = 0,/* default config */
+
+ /* UART configs */
+ FUNCMUX_UART1_UART1 = 0,
+ FUNCMUX_UART4_UART4 = 0,
+};
Since FUNCMUX_UART* aren't implemented, perhaps don't define them?
you'd need to edit the next patch not to reference these symbols too.
I left these in so the array (uart_configs) would be filled for T210 (even
though it's not used, to avoid a warning.
Also, setup_uarts() should be fixed not to call funcmux_select() if
uart_configs[i]==-1, since funcmux_select() will print an error if DEBUG is
defined since those values aren't implemnted. Perhaps you could ifdef out the
call for T210+ rather than checking the funcmux value.
I thought of doing that, but to me it was too messy. Since all boards call
pinmux_init before this, I'll look into a follow-on patch to fix them all (i.e.
none need funcmux_select now for UART setup).
This could all be done in a followon patch if you wanted.
--
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Re: [U-Boot] [PATCH V3 4/6] ARM: Tegra210: Add support to common Tegra source/config files
Stephen,
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Monday, July 27, 2015 10:55 AM
To: Tom Warren
Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren;
tomcwarren3...@gmail.com
Subject: Re: [U-Boot] [PATCH V3 4/6] ARM: Tegra210: Add support to common
Tegra source/config files
On 07/24/2015 04:00 PM, Tom Warren wrote:
Derived from Tegra124, modified as appropriate during T210 board
bringup. Cleaned up debug statements to conserve string space, too.
This also adds misc 64-bit changes from Thierry Reding/Stephen Warren.
diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi
+ gpio: gpio@0,6000d000 {
+ compatible = nvidia,tegra210-gpio, nvidia,tegra124-gpio,
+nvidia,tegra30-gpio;
I think only the 210 and 30 values are required? Feel free to fix this up when
applying; no need to resend.
This came from Thierry's DTSI file IIRC, but I'll pull the tegra124 value when
I apply it. Thanks.
--
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Re: [U-Boot] [PATCH V3 0/6] Tegra210/P2571 initial support
Thanks, Stephen! -Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Monday, July 27, 2015 11:01 AM To: Tom Warren Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren; tomcwarren3...@gmail.com Subject: Re: [U-Boot] [PATCH V3 0/6] Tegra210/P2571 initial support On 07/24/2015 04:00 PM, Tom Warren wrote: This patch series adds support for the Tegra210 SoC and the P2571 board. Most of the T210 info is identical to T124 at this point, so I just cloned Venice2/Jetson-TK1 board files and T124 header/SoC code. Pinmux is the major area of difference at this time, but other changes will be made as more features of the board are brought up. The series, Acked-by: Stephen Warren swar...@nvidia.com I've also validated that: a) I can compile it when applied to upstream u-boot/master (a couple days old). b) I applied it to our internal L4T U-Boot branch, ported it to another T210 board, flashed it, and booted an L4T kernel (with a few other L4T-specific patches on top). I don't think that's quite enough for a Tested-by tag upstream since I haven't actually booted the upstream code, but it's good enough for me to consider the series tested:-) --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V3 0/6] Tegra210/P2571 initial support
TomR/Albert, -Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Monday, July 27, 2015 11:01 AM To: Tom Warren Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren; tomcwarren3...@gmail.com Subject: Re: [U-Boot] [PATCH V3 0/6] Tegra210/P2571 initial support On 07/24/2015 04:00 PM, Tom Warren wrote: This patch series adds support for the Tegra210 SoC and the P2571 board. Most of the T210 info is identical to T124 at this point, so I just cloned Venice2/Jetson-TK1 board files and T124 header/SoC code. Pinmux is the major area of difference at this time, but other changes will be made as more features of the board are brought up. The series, Acked-by: Stephen Warren swar...@nvidia.com I've also validated that: a) I can compile it when applied to upstream u-boot/master (a couple days old). b) I applied it to our internal L4T U-Boot branch, ported it to another T210 board, flashed it, and booted an L4T kernel (with a few other L4T-specific patches on top). I don't think that's quite enough for a Tested-by tag upstream since I haven't actually booted the upstream code, but it's good enough for me to consider the series tested:-) I've applied my T210 work on top of Stephen's recent 10-patch 'arm' 64-bit cleanup series and his 3-patch 'tegra' 64-bit fixes, onto my current u-boot-tegra/master after rebasing it against TOT u-boot/master. Everything builds OK (all Tegra 32-bit, and all ARM 64-bit), and my T210 boots OK to cmd prompt, with all periphs working (USB, I2C, SPI, GPIO, MMC). So my question is, how should I go about issuing a PR for the T210 work? It should apply OK w/o Stephen's 64-bit fixes, but it won't build w/o them. But only a few are actually Tegra-specific (the 3 from today). Is it OK if I send one PR with _all_ these patches in u-boot-tegra/master, including the 'arm' 64-bit, the 'tegra' 64-bit, and finally my T210 series on top? Or do you want them split up and the 'arm' 64-bit fixes taken in to either u-boot-arm/master or u-boot/master first (just pulled from the list, I guess), then a PR from me for the 3 Tegra 64-bit fixes plus my T210 series? Let me know, Tom -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V3 0/6] Tegra210/P2571 initial support
Thanks, Tom. Simon Glass reviewed the earlier 64-bit patches, so I'll take that as the stamp of approval for them. Stephen/Thierry - what about the most recent 3 'ARM: tegra' 64-bit patches? Do I need to wait until someone else has Ack'd / reviewed them, or do you feel they're good to go? I guess I can say that I've 'tested' them, but I'd really like someone besides myself to approve them. Tom -- nvpublic -Original Message- From: Tom Rini [mailto:tr...@konsulko.com] Sent: Monday, July 27, 2015 3:08 PM To: Tom Warren Cc: Albert Aribaud; u-boot@lists.denx.de; Thierry Reding; Stephen Warren; tomcwarren3...@gmail.com Subject: Re: [U-Boot] [PATCH V3 0/6] Tegra210/P2571 initial support * PGP Signed by an unknown key On Mon, Jul 27, 2015 at 09:51:11PM +, Tom Warren wrote: TomR/Albert, -Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Monday, July 27, 2015 11:01 AM To: Tom Warren Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren; tomcwarren3...@gmail.com Subject: Re: [U-Boot] [PATCH V3 0/6] Tegra210/P2571 initial support On 07/24/2015 04:00 PM, Tom Warren wrote: This patch series adds support for the Tegra210 SoC and the P2571 board. Most of the T210 info is identical to T124 at this point, so I just cloned Venice2/Jetson-TK1 board files and T124 header/SoC code. Pinmux is the major area of difference at this time, but other changes will be made as more features of the board are brought up. The series, Acked-by: Stephen Warren swar...@nvidia.com I've also validated that: a) I can compile it when applied to upstream u-boot/master (a couple days old). b) I applied it to our internal L4T U-Boot branch, ported it to another T210 board, flashed it, and booted an L4T kernel (with a few other L4T-specific patches on top). I don't think that's quite enough for a Tested-by tag upstream since I haven't actually booted the upstream code, but it's good enough for me to consider the series tested:-) I've applied my T210 work on top of Stephen's recent 10-patch 'arm' 64-bit cleanup series and his 3-patch 'tegra' 64-bit fixes, onto my current u-boot- tegra/master after rebasing it against TOT u-boot/master. Everything builds OK (all Tegra 32-bit, and all ARM 64-bit), and my T210 boots OK to cmd prompt, with all periphs working (USB, I2C, SPI, GPIO, MMC). So my question is, how should I go about issuing a PR for the T210 work? It should apply OK w/o Stephen's 64-bit fixes, but it won't build w/o them. But only a few are actually Tegra-specific (the 3 from today). Is it OK if I send one PR with _all_ these patches in u-boot-tegra/master, including the 'arm' 64-bit, the 'tegra' 64-bit, and finally my T210 series on top? Or do you want them split up and the 'arm' 64-bit fixes taken in to either u- boot-arm/master or u-boot/master first (just pulled from the list, I guess), then a PR from me for the 3 Tegra 64-bit fixes plus my T210 series? One PR with everything sounds OK to me. -- Tom * Unknown Key * 0x56D6FECD ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 3/6] ARM: Tegra210: Add SoC code/include files for T210
All based off of Tegra124. As a Tegra210 board is brought
up, these may change a bit to match the HW more closely,
but probably 90% of this is identical to T124.
Note that since T210 is a 64-bit build, it has no SPL
component, and hence no cpu.c for Tegra210.
Signed-off-by: Tom Warren twar...@nvidia.com
---
Changes in V3:
- removed funcmux UART init on T210 - pinmux_init does it all
- fix redundant strings in xusb-padctl.c
- updated tegra210-car dt bindings from treding
Changes in V2:
- minor fixes as per swarren review
arch/arm/include/asm/arch-tegra210/ahb.h | 91 ++
arch/arm/include/asm/arch-tegra210/clock-tables.h | 566 +++
arch/arm/include/asm/arch-tegra210/clock.h| 27 +
arch/arm/include/asm/arch-tegra210/flow.h | 45 +
arch/arm/include/asm/arch-tegra210/funcmux.h | 23 +
arch/arm/include/asm/arch-tegra210/gp_padctrl.h | 74 ++
arch/arm/include/asm/arch-tegra210/gpio.h | 303 ++
arch/arm/include/asm/arch-tegra210/mc.h | 72 ++
arch/arm/include/asm/arch-tegra210/pmu.h | 14 +
arch/arm/include/asm/arch-tegra210/powergate.h| 12 +
arch/arm/include/asm/arch-tegra210/sysctr.h | 26 +
arch/arm/include/asm/arch-tegra210/tegra.h| 32 +
arch/arm/mach-tegra/tegra210/Kconfig | 11 +
arch/arm/mach-tegra/tegra210/Makefile | 11 +
arch/arm/mach-tegra/tegra210/clock.c | 1091 +
arch/arm/mach-tegra/tegra210/funcmux.c| 40 +
arch/arm/mach-tegra/tegra210/xusb-padctl.c| 495 ++
include/dt-bindings/clock/tegra210-car.h | 342 +++
18 files changed, 3275 insertions(+)
create mode 100644 arch/arm/include/asm/arch-tegra210/ahb.h
create mode 100644 arch/arm/include/asm/arch-tegra210/clock-tables.h
create mode 100644 arch/arm/include/asm/arch-tegra210/clock.h
create mode 100644 arch/arm/include/asm/arch-tegra210/flow.h
create mode 100644 arch/arm/include/asm/arch-tegra210/funcmux.h
create mode 100644 arch/arm/include/asm/arch-tegra210/gp_padctrl.h
create mode 100644 arch/arm/include/asm/arch-tegra210/gpio.h
create mode 100644 arch/arm/include/asm/arch-tegra210/mc.h
create mode 100644 arch/arm/include/asm/arch-tegra210/pmu.h
create mode 100644 arch/arm/include/asm/arch-tegra210/powergate.h
create mode 100644 arch/arm/include/asm/arch-tegra210/sysctr.h
create mode 100644 arch/arm/include/asm/arch-tegra210/tegra.h
create mode 100644 arch/arm/mach-tegra/tegra210/Kconfig
create mode 100644 arch/arm/mach-tegra/tegra210/Makefile
create mode 100644 arch/arm/mach-tegra/tegra210/clock.c
create mode 100644 arch/arm/mach-tegra/tegra210/funcmux.c
create mode 100644 arch/arm/mach-tegra/tegra210/xusb-padctl.c
create mode 100644 include/dt-bindings/clock/tegra210-car.h
diff --git a/arch/arm/include/asm/arch-tegra210/ahb.h
b/arch/arm/include/asm/arch-tegra210/ahb.h
new file mode 100644
index 000..3a37af4
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/ahb.h
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation www.nvidia.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA210_AHB_H_
+#define _TEGRA210_AHB_H_
+
+struct ahb_ctlr {
+ u32 reserved0; /* 00h */
+ u32 arbitration_disable;/* _ARBITRATION_DISABLE_0, 04h */
+ u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */
+ u32 arbitration_usr_protect;/* _ARBITRATION_USR_PROTECT_0, 0ch */
+ u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0,10h */
+ u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0,14h */
+ u32 reserved6[2]; /* 18h, 1ch */
+ u32 gizmo_usb; /* _GIZMO_USB_0,20h */
+ u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0,24h */
+ u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */
+ u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */
+ u32 gizmo_xbar_apb_ctlr;/* _GIZMO_XBAR_APB_CTLR_0, 30h */
+ u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */
+ u32 reserved13[2]; /* 38h, 3ch */
+ u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */
+ u32 reserved15; /* 44h */
+ u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */
+ u32 reserved17; /* 4ch */
+ u32 gizmo_se; /* _GIZMO_SE_0, 50h */
+ u32 gizmo_tzram;/* _GIZMO_TZRAM_0, 54h */
+ u32 reserved20[3]; /* 58h, 5ch, 60h */
+ u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */
+ u32 reserved22[3]; /* 68h, 6ch, 70h */
+ u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */
+ u32 gizmo_nor
[U-Boot] [PATCH V3 4/6] ARM: Tegra210: Add support to common Tegra source/config files
Derived from Tegra124, modified as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too. This also adds misc 64-bit changes
from Thierry Reding/Stephen Warren.
Signed-off-by: Tom Warren twar...@nvidia.com
Signed-off-by: Thierry Reding tred...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
Changes in V3:
- moved DTSI file into SoC patch, made DTS files conform with 64-bit FDT
- removed untested/unneeded nodes like APBDMA, PWM, etc.
- fix/update PLLU/ehci-tegra support for T210: USB works now
- roll in some 64-bit Tegra fixes from treding/swarren
- add fdt_high/initrd_high 64-bit fix from treading/swarren
Changes in V2:
- minor fixes as per swarren review
arch/arm/dts/tegra210.dtsi | 283 +++
arch/arm/include/asm/arch-tegra/ap.h | 6 +-
arch/arm/include/asm/arch-tegra/clk_rst.h| 36 +++-
arch/arm/include/asm/arch-tegra/gp_padctrl.h | 3 +-
arch/arm/include/asm/arch-tegra/pmc.h| 7 +-
arch/arm/include/asm/arch-tegra/tegra.h | 4 +-
arch/arm/include/asm/arch-tegra/usb.h| 3 +
arch/arm/mach-tegra/Kconfig | 12 ++
arch/arm/mach-tegra/Makefile | 5 +-
arch/arm/mach-tegra/ap.c | 11 +-
arch/arm/mach-tegra/board.c | 10 +-
arch/arm/mach-tegra/cache.c | 2 +
arch/arm/mach-tegra/clock.c | 30 ++-
arch/arm/mach-tegra/cpu.c| 55 --
arch/arm/mach-tegra/cpu.h| 10 +-
arch/arm/mach-tegra/lowlevel_init.S | 15 ++
drivers/mmc/tegra_mmc.c | 12 +-
drivers/usb/host/ehci-tegra.c| 31 ++-
include/configs/tegra-common-post.h | 12 +-
include/fdtdec.h | 3 +
lib/fdtdec.c | 2 +
21 files changed, 509 insertions(+), 43 deletions(-)
create mode 100644 arch/arm/dts/tegra210.dtsi
diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi
new file mode 100644
index 000..eca48d3
--- /dev/null
+++ b/arch/arm/dts/tegra210.dtsi
@@ -0,0 +1,283 @@
+#include dt-bindings/clock/tegra210-car.h
+#include dt-bindings/gpio/tegra-gpio.h
+#include dt-bindings/pinctrl/pinctrl-tegra.h
+#include dt-bindings/interrupt-controller/arm-gic.h
+#include dt-bindings/pinctrl/pinctrl-tegra-xusb.h
+
+#include skeleton.dtsi
+
+/ {
+ compatible = nvidia,tegra210;
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ gic: interrupt-controller@0,50041000 {
+ compatible = arm,gic-400;
+ #interrupt-cells = 3;
+ interrupt-controller;
+ reg = 0x0 0x50041000 0x0 0x1000,
+ 0x0 0x50042000 0x0 0x2000,
+ 0x0 0x50044000 0x0 0x2000,
+ 0x0 0x50046000 0x0 0x2000;
+ interrupts = GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH);
+ interrupt-parent = gic;
+ };
+
+ tegra_car: clock@0,60006000 {
+ compatible = nvidia,tegra210-car;
+ reg = 0x0 0x60006000 0x0 0x1000;
+ #clock-cells = 1;
+ #reset-cells = 1;
+ };
+
+ gpio: gpio@0,6000d000 {
+ compatible = nvidia,tegra210-gpio, nvidia,tegra124-gpio,
nvidia,tegra30-gpio;
+ reg = 0x0 0x6000d000 0x0 0x1000;
+ interrupts = GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH;
+ #gpio-cells = 2;
+ gpio-controller;
+ #interrupt-cells = 2;
+ interrupt-controller;
+ };
+
+ i2c@0,7000c000 {
+ compatible = nvidia,tegra210-i2c, nvidia,tegra114-i2c;
+ reg = 0x0 0x7000c000 0x0 0x100;
+ interrupts = 0 38 0x04;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = tegra_car 12;
+ status = disabled;
+ };
+
+ i2c@0,7000c400 {
+ compatible = nvidia,tegra210-i2c, nvidia,tegra114-i2c;
+ reg = 0x0 0x7000c400 0x0 0x100;
+ interrupts = 0 84 0x04;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = tegra_car 54;
+ status = disabled;
+ };
+
+ i2c@0,7000c500 {
+ compatible = nvidia,tegra210-i2c, nvidia,tegra114-i2c;
+ reg = 0x0 0x7000c500 0x0 0x100;
+ interrupts = 0
[U-Boot] [PATCH V3 6/6] T210: Add support for 64-bit T210-based P2571 board
Based on Venice2, incorporates Stephen Warren's
latest P2571 pinmux table.
With Thierry Reding's 64-bit build fixes, this
will build and and boot in 64-bit on my P2571
(when used with a 32-bit AVP loader).
Signed-off-by: Tom Warren twar...@nvidia.com
---
Changes in V3:
- fix COUNTER_FREQUENCY to match T210/P2571 OSC freq (38.4)
- Add back USB net config switches now that USB is working
Changes in V2:
- minor fixes as per swarren review
arch/arm/mach-tegra/tegra210/Kconfig | 7 +
board/nvidia/{beaver = p2571}/Kconfig | 6 +-
board/nvidia/p2571/MAINTAINERS | 6 +
.../tegra210 = board/nvidia/p2571}/Makefile | 6 +-
board/nvidia/p2571/max77620_init.c | 85
board/nvidia/p2571/max77620_init.h | 67 ++
board/nvidia/p2571/p2571.c | 29 +++
board/nvidia/p2571/pinmux-config-p2571.h | 235 +
configs/{beaver_defconfig = p2571_defconfig} | 6 +-
include/configs/{venice2.h = p2571.h} | 33 +--
.../{tegra124-common.h = tegra210-common.h} | 15 +-
11 files changed, 467 insertions(+), 28 deletions(-)
copy board/nvidia/{beaver = p2571}/Kconfig (61%)
create mode 100644 board/nvidia/p2571/MAINTAINERS
copy {arch/arm/mach-tegra/tegra210 = board/nvidia/p2571}/Makefile (59%)
create mode 100644 board/nvidia/p2571/max77620_init.c
create mode 100644 board/nvidia/p2571/max77620_init.h
create mode 100644 board/nvidia/p2571/p2571.c
create mode 100644 board/nvidia/p2571/pinmux-config-p2571.h
copy configs/{beaver_defconfig = p2571_defconfig} (77%)
copy include/configs/{venice2.h = p2571.h} (67%)
copy include/configs/{tegra124-common.h = tegra210-common.h} (89%)
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig
b/arch/arm/mach-tegra/tegra210/Kconfig
index f2a0059..147e6a8 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -3,9 +3,16 @@ if TEGRA210
choice
prompt Tegra210 board select
+config TARGET_P2571
+ bool NVIDIA Tegra210 P2571 base board
+ help
+ P2571 is a P2530 married to a P1963 I/O board
+
endchoice
config SYS_SOC
default tegra210
+source board/nvidia/p2571/Kconfig
+
endif
diff --git a/board/nvidia/beaver/Kconfig b/board/nvidia/p2571/Kconfig
similarity index 61%
copy from board/nvidia/beaver/Kconfig
copy to board/nvidia/p2571/Kconfig
index 23f7c94..7bc4874 100644
--- a/board/nvidia/beaver/Kconfig
+++ b/board/nvidia/p2571/Kconfig
@@ -1,12 +1,12 @@
-if TARGET_BEAVER
+if TARGET_P2571
config SYS_BOARD
- default beaver
+ default p2571
config SYS_VENDOR
default nvidia
config SYS_CONFIG_NAME
- default beaver
+ default p2571
endif
diff --git a/board/nvidia/p2571/MAINTAINERS b/board/nvidia/p2571/MAINTAINERS
new file mode 100644
index 000..c165135
--- /dev/null
+++ b/board/nvidia/p2571/MAINTAINERS
@@ -0,0 +1,6 @@
+P2571 BOARD
+M: Tom Warren twar...@nvidia.com
+S: Maintained
+F: board/nvidia/p2571/
+F: include/configs/p2571.h
+F: configs/p2571_defconfig
diff --git a/arch/arm/mach-tegra/tegra210/Makefile b/board/nvidia/p2571/Makefile
similarity index 59%
copy from arch/arm/mach-tegra/tegra210/Makefile
copy to board/nvidia/p2571/Makefile
index 1fb8d1a..223062e 100644
--- a/arch/arm/mach-tegra/tegra210/Makefile
+++ b/board/nvidia/p2571/Makefile
@@ -5,7 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += clock.o
-obj-y += funcmux.o
-obj-y += pinmux.o
-obj-y += xusb-padctl.o
+obj-y += max77620_init.o
+obj-y += p2571.o
diff --git a/board/nvidia/p2571/max77620_init.c
b/board/nvidia/p2571/max77620_init.c
new file mode 100644
index 000..ed8d4dc
--- /dev/null
+++ b/board/nvidia/p2571/max77620_init.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation www.nvidia.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch-tegra/tegra_i2c.h
+#include max77620_init.h
+
+/* MAX77620-PMIC-specific early init code - get CPU rails up, etc */
+
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+ struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+ writel(addr, reg-cmd_addr0);
+ writel(config, reg-cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+ struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+ writel(data, reg-cmd_data1);
+ writel(config, reg-cnfg);
+}
+
+void pmic_enable_cpu_vdd(void)
+{
+ uint reg;
+ debug(%s entry\n, __func__);
+
+ /* Setup/Enable GPIO5 - VDD_CPU_REG_EN */
+ debug(%s: Setting GPIO5 to enable CPU regulator\n, __func__);
+ /* B3=1=logic high,B2=dontcare,B1=0=output,B0=1=push-pull */
+ reg = 0x0900 | MAX77620_GPIO5_REG;
+ tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
+ udelay(10 * 1000
[U-Boot] [PATCH V3 0/6] Tegra210/P2571 initial support
This patch series adds support for the Tegra210 SoC and the P2571 board. Most of the T210 info is identical to T124 at this point, so I just cloned Venice2/Jetson-TK1 board files and T124 header/SoC code. Pinmux is the major area of difference at this time, but other changes will be made as more features of the board are brought up. Changes in V3: - moved DTSI file into SoC patch, made DTS files conform with 64-bit FDT - removed untested/unneeded DT nodes like APBDMA, PWM, etc. - used common ARMV7 Kconfig option for 32-bit T210 Tegra SoCs - removed funcmux UART init on T210 - pinmux_init does it all - fix redundant strings in xusb-padctl.c - updated tegra210-car dt binding from treding - fix/update PLLU/ehci-tegra support for T210: USB works now - roll in some 64-bit Tegra fixes from treding/swarren - add fdt_high/initrd_high 64-bit fix from treading/swarren - fix COUNTER_FREQUENCY to match T210/P2571 OSC freq (38.4) Changes in V2: - minor fixes as per swarren review Tom Warren (6): Tegra210: Fix 64-bit build warning about save_boot_params_ret() Tegra: Rework KConfig options to allow 64-bit builds (T210) ARM: Tegra210: Add SoC code/include files for T210 ARM: Tegra210: Add support to common Tegra source/config files P2571: dts: Add DT file for Tegra210 P2571 board T210: Add support for 64-bit T210-based P2571 board arch/arm/Kconfig | 11 - arch/arm/dts/Makefile |3 +- arch/arm/dts/tegra210-p2571.dts | 106 ++ arch/arm/dts/tegra210.dtsi| 283 ++ arch/arm/include/asm/arch-tegra/ap.h |6 +- arch/arm/include/asm/arch-tegra/clk_rst.h | 36 +- arch/arm/include/asm/arch-tegra/gp_padctrl.h |3 +- arch/arm/include/asm/arch-tegra/pmc.h |7 +- arch/arm/include/asm/arch-tegra/tegra.h |4 +- arch/arm/include/asm/arch-tegra/usb.h |3 + arch/arm/include/asm/arch-tegra210/ahb.h | 91 ++ arch/arm/include/asm/arch-tegra210/clock-tables.h | 566 +++ arch/arm/include/asm/arch-tegra210/clock.h| 27 + arch/arm/include/asm/arch-tegra210/flow.h | 45 + arch/arm/include/asm/arch-tegra210/funcmux.h | 23 + arch/arm/include/asm/arch-tegra210/gp_padctrl.h | 74 ++ arch/arm/include/asm/arch-tegra210/gpio.h | 303 ++ arch/arm/include/asm/arch-tegra210/mc.h | 72 ++ arch/arm/include/asm/arch-tegra210/pmu.h | 14 + arch/arm/include/asm/arch-tegra210/powergate.h| 12 + arch/arm/include/asm/arch-tegra210/sysctr.h | 26 + arch/arm/include/asm/arch-tegra210/tegra.h| 32 + arch/arm/mach-tegra/Kconfig | 30 + arch/arm/mach-tegra/Makefile |5 +- arch/arm/mach-tegra/ap.c | 11 +- arch/arm/mach-tegra/board.c | 12 +- arch/arm/mach-tegra/board2.c |3 + arch/arm/mach-tegra/cache.c |2 + arch/arm/mach-tegra/clock.c | 30 +- arch/arm/mach-tegra/cpu.c | 55 +- arch/arm/mach-tegra/cpu.h | 10 +- arch/arm/mach-tegra/lowlevel_init.S | 15 + arch/arm/mach-tegra/tegra210/Kconfig | 18 + arch/arm/mach-tegra/tegra210/Makefile | 11 + arch/arm/mach-tegra/tegra210/clock.c | 1091 + arch/arm/mach-tegra/tegra210/funcmux.c| 40 + arch/arm/mach-tegra/tegra210/xusb-padctl.c| 495 ++ board/nvidia/p2571/Kconfig| 12 + board/nvidia/p2571/MAINTAINERS|6 + board/nvidia/p2571/Makefile |9 + board/nvidia/p2571/max77620_init.c| 85 ++ board/nvidia/p2571/max77620_init.h| 67 ++ board/nvidia/p2571/p2571.c| 41 + board/nvidia/p2571/pinmux-config-p2571.h | 237 + configs/p2571_defconfig | 16 + drivers/mmc/tegra_mmc.c | 12 +- drivers/usb/host/ehci-tegra.c | 31 +- include/configs/p2571.h | 78 ++ include/configs/tegra-common-post.h | 12 +- include/configs/tegra210-common.h | 76 ++ include/dt-bindings/clock/tegra210-car.h | 342 +++ include/fdtdec.h |3 + lib/fdtdec.c |2 + 53 files changed, 4974 insertions(+), 55 deletions(-) create mode 100644 arch/arm/dts/tegra210-p2571.dts create mode 100644 arch/arm/dts/tegra210.dtsi create mode 100644 arch/arm/include/asm/arch-tegra210/ahb.h create mode 100644 arch/arm/include/asm/arch-tegra210/clock-tables.h create mode 100644 arch/arm/include/asm/arch-tegra210/clock.h create mode 100644 arch/arm
[U-Boot] [PATCH V3 2/6] Tegra: Rework KConfig options to allow 64-bit builds (T210)
Moved Tegra config options to mach-tegra/Kconfig so that both 32-bit and 64-bit builds can co-exist for Tegra SoCs. T210 will be 64-bit only (no SPL) and will require a 32-bit AVP/BPMP loader. Signed-off-by: Tom Warren twar...@nvidia.com --- Changes in V3: - used common ARMV7 Kconfig option for 32-bit T210 Tegra SoCs Changes in V2: None arch/arm/Kconfig| 11 --- arch/arm/mach-tegra/Kconfig | 18 ++ 2 files changed, 18 insertions(+), 11 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 506463c..20ab398 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -681,17 +681,6 @@ config TARGET_XILINX_ZYNQMP config TEGRA bool NVIDIA Tegra - select SUPPORT_SPL - select SPL - select OF_CONTROL - select SPL_DISABLE_OF_CONTROL - select CPU_V7 - select DM - select DM_SPI_FLASH - select DM_SERIAL - select DM_I2C - select DM_SPI - select DM_GPIO config TARGET_VEXPRESS64_AEMV8A bool Support vexpress_aemv8a diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 54bd648..7533e57 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -1,20 +1,38 @@ if TEGRA +config TEGRA_ARMV7_COMMON + bool Tegra 32-bit + select SUPPORT_SPL + select SPL + select OF_CONTROL + select SPL_DISABLE_OF_CONTROL + select CPU_V7 + select DM + select DM_SPI_FLASH + select DM_SERIAL + select DM_I2C + select DM_SPI + select DM_GPIO + choice prompt Tegra SoC select optional config TEGRA20 bool Tegra20 family + select TEGRA_ARMV7_COMMON config TEGRA30 bool Tegra30 family + select TEGRA_ARMV7_COMMON config TEGRA114 bool Tegra114 family + select TEGRA_ARMV7_COMMON config TEGRA124 bool Tegra124 family + select TEGRA_ARMV7_COMMON endchoice -- 1.8.2.1.610.g562af5b ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 1/6] Tegra210: Fix 64-bit build warning about save_boot_params_ret()
Simon's 'tegra124: Implement spl_was_boot_source()' needs
a prototype for save_boot_params_ret() to build cleanly
for 64-bit Tegra210.
Signed-off-by: Tom Warren twar...@nvidia.com
---
Changes in V3: None
Changes in V2: New patch
arch/arm/mach-tegra/board.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index f113041..036bf5e 100644
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -18,6 +18,8 @@
#include asm/arch-tegra/sys_proto.h
#include asm/arch-tegra/warmboot.h
+void save_boot_params_ret(void);
+
DECLARE_GLOBAL_DATA_PTR;
enum {
--
1.8.2.1.610.g562af5b
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 5/6] P2571: dts: Add DT file for Tegra210 P2571 board
Based on T124 Venice2. SDMMC1 is SD-card slot.
Signed-off-by: Tom Warren twar...@nvidia.com
---
Changes in V3:
- made DTS file conform with 64-bit FDT
- removed untested/unneeded nodes like APBDMA, PWM, etc.
Changes in V2: None
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/tegra210-p2571.dts | 106
2 files changed, 108 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/tegra210-p2571.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 19e1de6..9bd7014 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -32,7 +32,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra114-dalmore.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
- tegra124-venice2.dtb
+ tegra124-venice2.dtb \
+ tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
uniphier-ph1-pro4-ref.dtb \
diff --git a/arch/arm/dts/tegra210-p2571.dts b/arch/arm/dts/tegra210-p2571.dts
new file mode 100644
index 000..de35bba
--- /dev/null
+++ b/arch/arm/dts/tegra210-p2571.dts
@@ -0,0 +1,106 @@
+/dts-v1/;
+
+#include tegra210.dtsi
+
+/ {
+ model = NVIDIA P2571;
+ compatible = nvidia,p2571, nvidia,tegra210;
+
+ chosen {
+ stdout-path = uarta;
+ };
+
+ aliases {
+ i2c0 = /i2c@0,7000d000;
+ i2c1 = /i2c@0,7000c000;
+ i2c2 = /i2c@0,7000c400;
+ i2c3 = /i2c@0,7000c500;
+ i2c4 = /i2c@0,7000c700;
+ i2c5 = /i2c@0,7000d100;
+ sdhci0 = /sdhci@0,700b0600;
+ sdhci1 = /sdhci@0,700b;
+ spi0 = /spi@0,7000d400;
+ spi1 = /spi@0,7000da00;
+ spi2 = /spi@0,7041;
+ usb0 = /usb@0,7d00;
+ };
+
+ memory {
+ reg = 0x0 0x8000 0x0 0xc000;
+ };
+
+ i2c@0,7000c000 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@0,7000c400 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@0,7000c500 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@0,7000c700 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@0,7000d000 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ i2c@0,7000d100 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ spi@0,7000d400 {
+ status = okay;
+ spi-max-frequency = 2500;
+ };
+
+ spi@0,7000da00 {
+ status = okay;
+ spi-max-frequency = 2500;
+ };
+
+ spi@0,7041 {
+ status = okay;
+ spi-max-frequency = 2400;
+ };
+
+ sdhci@0,700b {
+ status = okay;
+ cd-gpios = gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW;
+ power-gpios = gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH;
+ bus-width = 4;
+ };
+
+ sdhci@0,700b0600 {
+ status = okay;
+ bus-width = 8;
+ };
+
+ usb@0,7d00 {
+ status = okay;
+ dr_mode = otg;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ clk32k_in: clock@0 {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 32768;
+ };
+ };
+};
--
1.8.2.1.610.g562af5b
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Re: [U-Boot] [PATCH V2 6/6] T210: Add support for 64-bit T210-based P2571 board
Stephen, -Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Wednesday, July 22, 2015 11:05 AM To: Tom Warren Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren; tomcwarren3...@gmail.com Subject: Re: [U-Boot] [PATCH V2 6/6] T210: Add support for 64-bit T210-based P2571 board On 07/20/2015 01:50 PM, Tom Warren wrote: Based on Venice2, incorporates Stephen Warren's latest P2571 pinmux table. With Thierry Reding's 64-bit build fixes, this will build and and boot in 64-bit on my P2571 (when used with a 32-bit AVP loader). diff --git a/include/configs/venice2.h b/include/configs/p2571.h /* USB Host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA -#define CONFIG_USB_MAX_CONTROLLER_COUNT2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT1 Why's that? There's only 1 usable USB2.0 port on P2571 (micro-USB). AFAIK the other ports on the other controller aren't usable in U-Boot. -/* USB networking support */ -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX - -/* General networking support */ -#define CONFIG_CMD_DHCP I assume that's to solve some compile issue? If so, a FIXME/TODO comment (like you added for tegra-common-usb-gadget.h) would be better, so it's obvious we need to go back and re-enable it. +#if defined(CONFIG_ARM64) +#define COUNTER_FREQUENCY 1200 +#define CPU_RELEASE_ADDR 0x8000 +#endif CONFIG_ARM64 is always true now. True. I'll remove it. According to the schematics, the crystal frequency is 38.4MHz. Where did the value of CPU_RELEASE_ADDR come from? It's odd that there are 4 CPUs but only 1 release address. Both of these came from Thierry's staging/work branch - perhaps he can answer (I'll change the freq to 38.4MHz). diff --git a/include/configs/tegra124-common.h b/include/configs/tegra210-common.h -#define CONFIG_SYS_TEXT_BASE 0x8011 +#define CONFIG_SYS_TEXT_BASE 0x8010E000 It'd be best to keep that consistent with earlier chips. This is due to a change Simon just put in for Tegra124 only (running out of SPL space, I assume due to the Nyan-Big ChromeOS-isms). I don't think it's needed right now for T210 w/o SPL, and everyone tends to think of the CPU starting address as 0x8010E000, so I thought I'd keep T210 there. -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 3/6] ARM: Tegra210: Add SoC code/include files for T210
Stephen,
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Wednesday, July 22, 2015 10:45 AM
To: Tom Warren
Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren;
tomcwarren3...@gmail.com
Subject: Re: [U-Boot] [PATCH V2 3/6] ARM: Tegra210: Add SoC code/include
files for T210
On 07/20/2015 01:50 PM, Tom Warren wrote:
All based off of Tegra124. As a Tegra210 board is brought up, these
may change a bit to match the HW more closely, but probably 90% of
this is identical to T124.
Note that since T210 is a 64-bit build, it has no SPL component, and
hence no cpu.c for Tegra210.
diff --git a/arch/arm/mach-tegra/tegra210/funcmux.c
b/arch/arm/mach-tegra/tegra210/funcmux.c
+int funcmux_select(enum periph_id id, int config) {
+ int bad_config = config != FUNCMUX_DEFAULT;
+
+ switch (id) {
+ case PERIPH_ID_UART4:
+ switch (config) {
+ case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
+ pinmux_set_func(PMUX_PINGRP_UART4_TX_PI4,
+ PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_UART4_RX_PI5,
+ PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_UART4_CTS_PI7,
+ PMUX_FUNC_UARTD);
+ pinmux_set_func(PMUX_PINGRP_UART4_RTS_PI6,
+ PMUX_FUNC_UARTD);
...
+ case PERIPH_ID_UART1:
+ switch (config) {
+ case FUNCMUX_UART1_KBC:
+ pinmux_set_func(PMUX_PINGRP_UART1_TX_PU0,
+ PMUX_FUNC_UARTA);
+ pinmux_set_func(PMUX_PINGRP_UART1_RX_PU1,
Those are the wrong FUNCMUX_* enum names; they're supposed to be
FUNCMUX_${hwblock}_${pinset}. ${hwblock} is correctly UART1/4 above.
${pinset} doesn't look right to me; I see no GPIO or KBC pins being used.
Rather, I'd expect FUNCMUX_UART4_UART4 and FUNCMUX_UART1_UART1.
These were cloned from T124. I'll add FUNCMUX_UARTx_ to uart_configs[] in
board.c and use them here. Thanks.
Tom
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Re: [U-Boot] [PATCH V2 5/6] P2571: dts: Add DT files for Tegra210/P2571 board
Stephen,
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Thursday, July 23, 2015 11:00 AM
To: Tom Warren
Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren;
tomcwarren3...@gmail.com
Subject: Re: [U-Boot] [PATCH V2 5/6] P2571: dts: Add DT files for
Tegra210/P2571 board
On 07/23/2015 11:44 AM, Tom Warren wrote:
Stephen,
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Wednesday, July 22, 2015 11:17 AM
To: Tom Warren
Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren;
tomcwarren3...@gmail.com
Subject: Re: [U-Boot] [PATCH V2 5/6] P2571: dts: Add DT files for
Tegra210/P2571 board
On 07/20/2015 01:50 PM, Tom Warren wrote:
Based on T124 Venice2. SDMMC1 is SD-card slot.
arch/arm/dts/{tegra124.dtsi = tegra210.dtsi} | 153
-
There's also a lot of stuff in that file that isn't used in U-Boot or
isn't validated yet (audio, SPI?, PWM, I2C?, APBDMA, PCIe). I'd
suggest trimming the DT down to the absolute bare minimum for what
U-Boot is using right now. That will help prevent any inconsistencies
between the U-Boot and kernel DT files for Tegra210.
Audio, PCIE make sense. UART and SPI both have DMA properties, so I can' t
remove APBDMA. I'll do a cleanup run and see what shakes out.
I believe the DMA properties should be optional in the bindings for UART and
SPI. So, you should be able to remove the DMA properties from the client
nodes and hence also the APBDMA node. (Especially given that the U-Boot
drivers those HW blocks don't do DMA).
If they're optional, why are they in tegra124.dtsi? (and T114 and T30). I
wonder how they got in there originally?
Regardless, I'll remove 'em from T210 if you feel that strongly about it.
--
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Re: [U-Boot] [PATCH V2 5/6] P2571: dts: Add DT files for Tegra210/P2571 board
Stephen,
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Wednesday, July 22, 2015 10:57 AM
To: Tom Warren
Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren;
tomcwarren3...@gmail.com
Subject: Re: [U-Boot] [PATCH V2 5/6] P2571: dts: Add DT files for
Tegra210/P2571 board
On 07/20/2015 01:50 PM, Tom Warren wrote:
Based on T124 Venice2. SDMMC1 is SD-card slot.
I would expect the SoC DT file to be part of the previous patch which adds
Tegra210 support.
I would expect the P2571 file to be part of the next patch which adds
P2571 board support.
The DT files are split in the same manner as I did for T124/Venice2 back in Jan
of '14, and Dalmore/T114 back in Jan '13. This is the way I've always done it.
But I see the value in having the DTSI file in with the Tegra210 support patch
- I'll move it there.
diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra210.dtsi
I'd expect many more changes in this file, to add the tegra210 compatible
values to the compatible properties (or replace the tegra124 values with
tegra210 as appropriate depending on actual HW compatibility).
Also, both #address-cells=2 and #size-cells=2 should be present, since
this
is a 64-bit SoC. That'd also require that all reg values be updated to
include 2
cells for address and size, and the unit address in the node names to be
updated.
pwm: pwm@7000a000 {
compatible = nvidia,tegra124-pwm, nvidia,tegra20-pwm;
reg = 0x7000a000 0x100;
For example, that should probably be:
pwm: pwm@0,7000a000 {
compatible = nvidia,tegra210-pwm, nvidia,tegra20-pwm;
reg = 0 0x7000a000 0 0x100;
}
(Assuming the new PWM HW module is still a 100%-backwards-compatible
superset of Tegra20 PWM)
This was cloned/ported from T124 (32-bit), so it's the first 64-bit Tegra SoC -
I'm not up-to-speed on 64-bit DT requirements. I'll make the changes and see
how it builds/boots.
Fixing this issue might mean depending on more of Thierry's local 64-bit
fixes,
especially w.r.t. DT parsing. I'm not sure.
--
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Re: [U-Boot] [PATCH V2 5/6] P2571: dts: Add DT files for Tegra210/P2571 board
Stephen,
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Wednesday, July 22, 2015 11:17 AM
To: Tom Warren
Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren;
tomcwarren3...@gmail.com
Subject: Re: [U-Boot] [PATCH V2 5/6] P2571: dts: Add DT files for
Tegra210/P2571 board
On 07/20/2015 01:50 PM, Tom Warren wrote:
Based on T124 Venice2. SDMMC1 is SD-card slot.
arch/arm/dts/{tegra124.dtsi = tegra210.dtsi} | 153
-
There's also a lot of stuff in that file that isn't used in U-Boot or isn't
validated
yet (audio, SPI?, PWM, I2C?, APBDMA, PCIe). I'd suggest trimming the DT down
to the absolute bare minimum for what U-Boot is using right now. That will
help
prevent any inconsistencies between the U-Boot and kernel DT files for
Tegra210.
Audio, PCIE make sense. UART and SPI both have DMA properties, so I can' t
remove APBDMA. I'll do a cleanup run and see what shakes out.
--
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Re: [U-Boot] [PATCH V2 2/6] Tegra: Rework KConfig options to allow 64-bit builds (T210)
Stephen, -Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Wednesday, July 22, 2015 10:40 AM To: Tom Warren Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren; tomcwarren3...@gmail.com Subject: Re: [U-Boot] [PATCH V2 2/6] Tegra: Rework KConfig options to allow 64-bit builds (T210) On 07/20/2015 01:50 PM, Tom Warren wrote: Moved Tegra config options to mach-tegra/Kconfig so that both 32-bit and 64-bit builds can co-exist for Tegra SoCs. T210 will be 64-bit only (no SPL) and will requires a 32-bit AVP/BPMP loader. diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig config TEGRA20 bool Tegra20 family + select SUPPORT_SPL + select SPL + select OF_CONTROL + select SPL_DISABLE_OF_CONTROL + select CPU_V7 + select DM + select DM_SPI_FLASH + select DM_SERIAL + select DM_I2C + select DM_SPI + select DM_GPIO This patch duplicates all those added lines for all current chips. Could we add a new config variable to share these; something like: config TEGRA_ARMV7_COMMON select SUPPORT_SPL select SPL select OF_CONTROL select SPL_DISABLE_OF_CONTROL select CPU_V7 select DM select DM_SPI_FLASH select DM_SERIAL select DM_I2C select DM_SPI select DM_GPIO config TEGRA20 bool Tegra20 family select TEGRA_ARMv7_COMMON Great idea - I'll do that for V3. Thanks. -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 0/6] Tegra210/P2571 initial support
-Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Wednesday, July 22, 2015 1:35 PM To: Tom Warren Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren; tomcwarren3...@gmail.com Subject: Re: [U-Boot] [PATCH V2 0/6] Tegra210/P2571 initial support On 07/20/2015 01:50 PM, Tom Warren wrote: This patch series adds support for the Tegra210 SoC and the P2571 board. Most of the T210 info is identical to T124 at this point, so I just cloned Venice2/Jetson-TK1 board files and T124 header/SoC code. Pinmux is the major area of difference at this time, but other changes will be made as more features of the board are brought up. T210 is a 64-bit build, and hence has no SPL portion. A separate 32-bit AVP/BPMP loader must be used to get the 64-bit CPU portion running. Once that procedure is locked down, a README will be added to outline the process. Thierry Reding's dozen or so patches to fix various 64-bit build problems are also required to get this to build boot. They should precede this series so git-bisect will work. Somewhere in this series, fdt_high/initrd_high need to be modified from to . In an old downstream version of this series, this was done by ARM: Tegra210: Thierry's FDT/DTS changes for 64-bit, WIP. It's coming in a future patch. Only needed to boot the kernel, so I withheld it to get basic T210 support in. -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 0/6] Tegra210/P2571 initial support
This patch series adds support for the Tegra210 SoC and the P2571 board. Most of the T210 info is identical to T124 at this point, so I just cloned Venice2/Jetson-TK1 board files and T124 header/SoC code. Pinmux is the major area of difference at this time, but other changes will be made as more features of the board are brought up. T210 is a 64-bit build, and hence has no SPL portion. A separate 32-bit AVP/BPMP loader must be used to get the 64-bit CPU portion running. Once that procedure is locked down, a README will be added to outline the process. Thierry Reding's dozen or so patches to fix various 64-bit build problems are also required to get this to build boot. They should precede this series so git-bisect will work. Tom Warren (6): Tegra210: Fix 64-bit build warning about save_boot_params_ret() Tegra: Rework KConfig options to allow 64-bit builds (T210) ARM: Tegra210: Add SoC code/include files for T210 ARM: Tegra210: Add support to common Tegra source/config files P2571: dts: Add DT files for Tegra210/P2571 board T210: Add support for 64-bit T210-based P2571 board arch/arm/Kconfig | 11 - arch/arm/dts/Makefile |3 +- arch/arm/dts/tegra210-p2571.dts | 106 ++ arch/arm/dts/tegra210.dtsi| 511 ++ arch/arm/include/asm/arch-tegra/ap.h |6 +- arch/arm/include/asm/arch-tegra/clk_rst.h | 28 +- arch/arm/include/asm/arch-tegra/gp_padctrl.h |3 +- arch/arm/include/asm/arch-tegra/pmc.h |7 +- arch/arm/include/asm/arch-tegra/tegra.h |4 +- arch/arm/include/asm/arch-tegra210/ahb.h | 91 ++ arch/arm/include/asm/arch-tegra210/clock-tables.h | 566 +++ arch/arm/include/asm/arch-tegra210/clock.h| 27 + arch/arm/include/asm/arch-tegra210/flow.h | 45 + arch/arm/include/asm/arch-tegra210/funcmux.h | 23 + arch/arm/include/asm/arch-tegra210/gp_padctrl.h | 74 ++ arch/arm/include/asm/arch-tegra210/gpio.h | 303 ++ arch/arm/include/asm/arch-tegra210/mc.h | 72 ++ arch/arm/include/asm/arch-tegra210/pmu.h | 14 + arch/arm/include/asm/arch-tegra210/powergate.h| 12 + arch/arm/include/asm/arch-tegra210/sysctr.h | 26 + arch/arm/include/asm/arch-tegra210/tegra.h| 32 + arch/arm/mach-tegra/Kconfig | 56 ++ arch/arm/mach-tegra/Makefile |5 +- arch/arm/mach-tegra/ap.c |9 +- arch/arm/mach-tegra/board.c |2 + arch/arm/mach-tegra/clock.c |3 +- arch/arm/mach-tegra/cpu.c | 55 +- arch/arm/mach-tegra/cpu.h | 10 +- arch/arm/mach-tegra/tegra210/Kconfig | 18 + arch/arm/mach-tegra/tegra210/Makefile | 11 + arch/arm/mach-tegra/tegra210/clock.c | 1091 + arch/arm/mach-tegra/tegra210/funcmux.c| 80 ++ arch/arm/mach-tegra/tegra210/xusb-padctl.c| 495 ++ board/nvidia/p2571/Kconfig| 12 + board/nvidia/p2571/MAINTAINERS|6 + board/nvidia/p2571/Makefile |9 + board/nvidia/p2571/max77620_init.c| 85 ++ board/nvidia/p2571/max77620_init.h| 67 ++ board/nvidia/p2571/p2571.c| 29 + board/nvidia/p2571/pinmux-config-p2571.h | 235 + configs/p2571_defconfig | 16 + include/configs/p2571.h | 71 ++ include/configs/tegra210-common.h | 76 ++ include/dt-bindings/clock/tegra210-car.h | 342 +++ include/fdtdec.h |3 + lib/fdtdec.c |2 + 46 files changed, 4704 insertions(+), 48 deletions(-) create mode 100644 arch/arm/dts/tegra210-p2571.dts create mode 100644 arch/arm/dts/tegra210.dtsi create mode 100644 arch/arm/include/asm/arch-tegra210/ahb.h create mode 100644 arch/arm/include/asm/arch-tegra210/clock-tables.h create mode 100644 arch/arm/include/asm/arch-tegra210/clock.h create mode 100644 arch/arm/include/asm/arch-tegra210/flow.h create mode 100644 arch/arm/include/asm/arch-tegra210/funcmux.h create mode 100644 arch/arm/include/asm/arch-tegra210/gp_padctrl.h create mode 100644 arch/arm/include/asm/arch-tegra210/gpio.h create mode 100644 arch/arm/include/asm/arch-tegra210/mc.h create mode 100644 arch/arm/include/asm/arch-tegra210/pmu.h create mode 100644 arch/arm/include/asm/arch-tegra210/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra210/sysctr.h create mode 100644 arch/arm/include/asm/arch-tegra210/tegra.h create mode 100644 arch/arm/mach-tegra/tegra210/Kconfig create mode 100644 arch/arm/mach-tegra/tegra210/Makefile create
[U-Boot] [PATCH V2 3/6] ARM: Tegra210: Add SoC code/include files for T210
All based off of Tegra124. As a Tegra210 board is brought
up, these may change a bit to match the HW more closely,
but probably 90% of this is identical to T124.
Note that since T210 is a 64-bit build, it has no SPL
component, and hence no cpu.c for Tegra210.
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/include/asm/arch-tegra210/ahb.h | 91 ++
arch/arm/include/asm/arch-tegra210/clock-tables.h | 566 +++
arch/arm/include/asm/arch-tegra210/clock.h| 27 +
arch/arm/include/asm/arch-tegra210/flow.h | 45 +
arch/arm/include/asm/arch-tegra210/funcmux.h | 23 +
arch/arm/include/asm/arch-tegra210/gp_padctrl.h | 74 ++
arch/arm/include/asm/arch-tegra210/gpio.h | 303 ++
arch/arm/include/asm/arch-tegra210/mc.h | 72 ++
arch/arm/include/asm/arch-tegra210/pmu.h | 14 +
arch/arm/include/asm/arch-tegra210/powergate.h| 12 +
arch/arm/include/asm/arch-tegra210/sysctr.h | 26 +
arch/arm/include/asm/arch-tegra210/tegra.h| 32 +
arch/arm/mach-tegra/tegra210/Kconfig | 11 +
arch/arm/mach-tegra/tegra210/Makefile | 11 +
arch/arm/mach-tegra/tegra210/clock.c | 1091 +
arch/arm/mach-tegra/tegra210/funcmux.c| 80 ++
arch/arm/mach-tegra/tegra210/xusb-padctl.c| 495 ++
include/dt-bindings/clock/tegra210-car.h | 342 +++
18 files changed, 3315 insertions(+)
create mode 100644 arch/arm/include/asm/arch-tegra210/ahb.h
create mode 100644 arch/arm/include/asm/arch-tegra210/clock-tables.h
create mode 100644 arch/arm/include/asm/arch-tegra210/clock.h
create mode 100644 arch/arm/include/asm/arch-tegra210/flow.h
create mode 100644 arch/arm/include/asm/arch-tegra210/funcmux.h
create mode 100644 arch/arm/include/asm/arch-tegra210/gp_padctrl.h
create mode 100644 arch/arm/include/asm/arch-tegra210/gpio.h
create mode 100644 arch/arm/include/asm/arch-tegra210/mc.h
create mode 100644 arch/arm/include/asm/arch-tegra210/pmu.h
create mode 100644 arch/arm/include/asm/arch-tegra210/powergate.h
create mode 100644 arch/arm/include/asm/arch-tegra210/sysctr.h
create mode 100644 arch/arm/include/asm/arch-tegra210/tegra.h
create mode 100644 arch/arm/mach-tegra/tegra210/Kconfig
create mode 100644 arch/arm/mach-tegra/tegra210/Makefile
create mode 100644 arch/arm/mach-tegra/tegra210/clock.c
create mode 100644 arch/arm/mach-tegra/tegra210/funcmux.c
create mode 100644 arch/arm/mach-tegra/tegra210/xusb-padctl.c
create mode 100644 include/dt-bindings/clock/tegra210-car.h
diff --git a/arch/arm/include/asm/arch-tegra210/ahb.h
b/arch/arm/include/asm/arch-tegra210/ahb.h
new file mode 100644
index 000..3a37af4
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/ahb.h
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation www.nvidia.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA210_AHB_H_
+#define _TEGRA210_AHB_H_
+
+struct ahb_ctlr {
+ u32 reserved0; /* 00h */
+ u32 arbitration_disable;/* _ARBITRATION_DISABLE_0, 04h */
+ u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */
+ u32 arbitration_usr_protect;/* _ARBITRATION_USR_PROTECT_0, 0ch */
+ u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0,10h */
+ u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0,14h */
+ u32 reserved6[2]; /* 18h, 1ch */
+ u32 gizmo_usb; /* _GIZMO_USB_0,20h */
+ u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0,24h */
+ u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */
+ u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */
+ u32 gizmo_xbar_apb_ctlr;/* _GIZMO_XBAR_APB_CTLR_0, 30h */
+ u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */
+ u32 reserved13[2]; /* 38h, 3ch */
+ u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */
+ u32 reserved15; /* 44h */
+ u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */
+ u32 reserved17; /* 4ch */
+ u32 gizmo_se; /* _GIZMO_SE_0, 50h */
+ u32 gizmo_tzram;/* _GIZMO_TZRAM_0, 54h */
+ u32 reserved20[3]; /* 58h, 5ch, 60h */
+ u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */
+ u32 reserved22[3]; /* 68h, 6ch, 70h */
+ u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */
+ u32 gizmo_nor; /* _GIZMO_NOR_0,78h */
+ u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */
+ u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */
+ u32
[U-Boot] [PATCH V2 2/6] Tegra: Rework KConfig options to allow 64-bit builds (T210)
Moved Tegra config options to mach-tegra/Kconfig so that both 32-bit and 64-bit builds can co-exist for Tegra SoCs. T210 will be 64-bit only (no SPL) and will requires a 32-bit AVP/BPMP loader. Signed-off-by: Tom Warren twar...@nvidia.com --- arch/arm/Kconfig| 11 --- arch/arm/mach-tegra/Kconfig | 44 2 files changed, 44 insertions(+), 11 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 506463c..20ab398 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -681,17 +681,6 @@ config TARGET_XILINX_ZYNQMP config TEGRA bool NVIDIA Tegra - select SUPPORT_SPL - select SPL - select OF_CONTROL - select SPL_DISABLE_OF_CONTROL - select CPU_V7 - select DM - select DM_SPI_FLASH - select DM_SERIAL - select DM_I2C - select DM_SPI - select DM_GPIO config TARGET_VEXPRESS64_AEMV8A bool Support vexpress_aemv8a diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 54bd648..7494f8d 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -6,15 +6,59 @@ choice config TEGRA20 bool Tegra20 family + select SUPPORT_SPL + select SPL + select OF_CONTROL + select SPL_DISABLE_OF_CONTROL + select CPU_V7 + select DM + select DM_SPI_FLASH + select DM_SERIAL + select DM_I2C + select DM_SPI + select DM_GPIO config TEGRA30 bool Tegra30 family + select SUPPORT_SPL + select SPL + select OF_CONTROL + select SPL_DISABLE_OF_CONTROL + select CPU_V7 + select DM + select DM_SPI_FLASH + select DM_SERIAL + select DM_I2C + select DM_SPI + select DM_GPIO config TEGRA114 bool Tegra114 family + select SUPPORT_SPL + select SPL + select OF_CONTROL + select SPL_DISABLE_OF_CONTROL + select CPU_V7 + select DM + select DM_SPI_FLASH + select DM_SERIAL + select DM_I2C + select DM_SPI + select DM_GPIO config TEGRA124 bool Tegra124 family + select SUPPORT_SPL + select SPL + select OF_CONTROL + select SPL_DISABLE_OF_CONTROL + select CPU_V7 + select DM + select DM_SPI_FLASH + select DM_SERIAL + select DM_I2C + select DM_SPI + select DM_GPIO endchoice -- 1.8.2.1.610.g562af5b ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 4/6] ARM: Tegra210: Add support to common Tegra source/config files
Derived from Tegra124, modified as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too.
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/include/asm/arch-tegra/ap.h | 6 +--
arch/arm/include/asm/arch-tegra/clk_rst.h| 28 +++---
arch/arm/include/asm/arch-tegra/gp_padctrl.h | 3 +-
arch/arm/include/asm/arch-tegra/pmc.h| 7 ++--
arch/arm/include/asm/arch-tegra/tegra.h | 4 +-
arch/arm/mach-tegra/Kconfig | 12 ++
arch/arm/mach-tegra/Makefile | 5 ++-
arch/arm/mach-tegra/ap.c | 9 -
arch/arm/mach-tegra/clock.c | 3 +-
arch/arm/mach-tegra/cpu.c| 55
arch/arm/mach-tegra/cpu.h| 10 +++--
include/fdtdec.h | 3 ++
lib/fdtdec.c | 2 +
13 files changed, 111 insertions(+), 36 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/ap.h
b/arch/arm/include/asm/arch-tegra/ap.h
index ca40e4e..76773b7 100644
--- a/arch/arm/include/asm/arch-tegra/ap.h
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010-2011
+ * (C) Copyright 2010-2015
* NVIDIA Corporation www.nvidia.com
*
* SPDX-License-Identifier:GPL-2.0+
@@ -24,8 +24,6 @@
#define PG_UP_TAG_0_PID_CPU0x /* CPU aka a9 aka mpcore */
#define PG_UP_TAG_00x0
-#define CORESIGHT_UNLOCK 0xC5ACCE55;
-
/* AP base physical address of internal SRAM */
#define NV_PA_BASE_SRAM0x4000
@@ -66,7 +64,7 @@ int tegra_get_sku_info(void);
/* Do any chip-specific cache config */
void config_cache(void);
-#if defined(CONFIG_TEGRA124)
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
/* Do chip-specific vpr config */
void config_vpr(void);
#else
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h
b/arch/arm/include/asm/arch-tegra/clk_rst.h
index de50e08..43efa65 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -48,6 +48,7 @@ enum {
TEGRA_CLK_REGS_VW = 2,/* Number of clock enable regs V/W */
TEGRA_CLK_SOURCES_VW= 32, /* Number of ppl clock sources V/W */
TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */
+ TEGRA_CLK_SOURCES_Y = 18, /* Number of ppl clock sources Y */
};
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@@ -94,7 +95,15 @@ struct clk_rst_ctlr {
uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0,0x290 */
uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0,0x294 */
- uint crc_reserved21[23];/* _reserved_21,0x298-2f0 */
+ uint crc_clk_out_enb_y; /* _CLK_OUT_ENB_Y_0,0x298 */
+ uint crc_clk_enb_y_set; /* _CLK_ENB_Y_SET_0,0x29c */
+ uint crc_clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0,0x2a0 */
+
+ uint crc_rst_devices_y; /* _RST_DEVICES_Y_0,0x2a4 */
+ uint crc_rst_dev_y_set; /* _RST_DEV_Y_SET_0,0x2a8 */
+ uint crc_rst_dev_y_clr; /* _RST_DEV_Y_CLR_0,0x2ac */
+
+ uint crc_reserved21[17];/* _reserved_21,0x2b0-2f0 */
uint crc_dfll_base; /* _DFLL_BASE_0,0x2f4 */
@@ -136,7 +145,7 @@ struct clk_rst_ctlr {
struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
- /* Additional (T114) registers */
+ /* Additional (T114+) registers */
uint crc_rst_cpug_cmplx_set;/* _RST_CPUG_CMPLX_SET_0, 0x450 */
uint crc_rst_cpug_cmplx_clr;/* _RST_CPUG_CMPLX_CLR_0, 0x454 */
uint crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */
@@ -207,9 +216,18 @@ struct clk_rst_ctlr {
u32 _rsv32_1[7];/* 0x574-58c */
struct clk_pll_simple plldp;/* _PLLDP_BASE, 0x590 _PLLDP_MISC */
u32 crc_plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
- u32 _rsrv32_2[25];
- /* Tegra124 */
- uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */
+
+ /* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */
+ uint _rsrv32_2[25]; /* _0x59C - 0x5FC */
+ uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */
+
+ /* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */
+ uint crc_reserved61[5]; /* _reserved_61, 0x680 - 0x690 */
+ /*
+* NOTE: PLLA1 regs are in the middle of this Y region. Break this in
+* two later if PLLA1 is needed, but for now this is cleaner.
+*/
+ uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */
};
/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
diff --git a/arch/arm
[U-Boot] [PATCH V2 1/6] Tegra210: Fix 64-bit build warning about save_boot_params_ret()
Simon's 'tegra124: Implement spl_was_boot_source()' needs
a prototype for save_boot_params_ret() to build cleanly
for 64-bit Tegra210.
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/mach-tegra/board.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index f113041..036bf5e 100644
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -18,6 +18,8 @@
#include asm/arch-tegra/sys_proto.h
#include asm/arch-tegra/warmboot.h
+void save_boot_params_ret(void);
+
DECLARE_GLOBAL_DATA_PTR;
enum {
--
1.8.2.1.610.g562af5b
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 5/6] P2571: dts: Add DT files for Tegra210/P2571 board
Based on T124 Venice2. SDMMC1 is SD-card slot.
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/dts/Makefile | 3 +-
.../{tegra124-venice2.dts = tegra210-p2571.dts} | 40 --
arch/arm/dts/{tegra124.dtsi = tegra210.dtsi} | 153 -
3 files changed, 56 insertions(+), 140 deletions(-)
copy arch/arm/dts/{tegra124-venice2.dts = tegra210-p2571.dts} (65%)
copy arch/arm/dts/{tegra124.dtsi = tegra210.dtsi} (76%)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 19e1de6..9bd7014 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -32,7 +32,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra114-dalmore.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
- tegra124-venice2.dtb
+ tegra124-venice2.dtb \
+ tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
uniphier-ph1-pro4-ref.dtb \
diff --git a/arch/arm/dts/tegra124-venice2.dts b/arch/arm/dts/tegra210-p2571.dts
similarity index 65%
copy from arch/arm/dts/tegra124-venice2.dts
copy to arch/arm/dts/tegra210-p2571.dts
index 9e93cf9..ca41390 100644
--- a/arch/arm/dts/tegra124-venice2.dts
+++ b/arch/arm/dts/tegra210-p2571.dts
@@ -1,10 +1,10 @@
/dts-v1/;
-#include tegra124.dtsi
+#include tegra210.dtsi
/ {
- model = NVIDIA Venice2;
- compatible = nvidia,venice2, nvidia,tegra124;
+ model = NVIDIA P2571;
+ compatible = nvidia,p2571, nvidia,tegra210;
chosen {
stdout-path = uarta;
@@ -18,16 +18,15 @@
i2c4 = /i2c@7000c700;
i2c5 = /i2c@7000d100;
sdhci0 = /sdhci@700b0600;
- sdhci1 = /sdhci@700b0400;
+ sdhci1 = /sdhci@700b;
spi0 = /spi@7000d400;
spi1 = /spi@7000da00;
+ spi2 = /spi@7041;
usb0 = /usb@7d00;
- usb1 = /usb@7d008000;
};
memory {
- device_type = memory;
- reg = 0x8000 0x8000;
+ reg = 0x0 0x8000 0x0 0xc000;
};
i2c@7000c000 {
@@ -70,11 +69,15 @@
spi-max-frequency = 2500;
};
- sdhci@700b0400 {
+ spi@7041 {
status = okay;
- cd-gpios = gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH;
- power-gpios = gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH;
- wp-gpios = gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW;
+ spi-max-frequency = 2400;
+ };
+
+ sdhci@700b {
+ status = okay;
+ cd-gpios = gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW;
+ power-gpios = gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH;
bus-width = 4;
};
@@ -86,11 +89,18 @@
usb@7d00 {
status = okay;
dr_mode = otg;
- nvidia,vbus-gpio = gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH;
};
- usb@7d008000 {
- status = okay;
- nvidia,vbus-gpio = gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH;
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ clk32k_in: clock@0 {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 32768;
+ };
};
};
diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra210.dtsi
similarity index 76%
copy from arch/arm/dts/tegra124.dtsi
copy to arch/arm/dts/tegra210.dtsi
index 43b7f22..f09a1a7 100644
--- a/arch/arm/dts/tegra124.dtsi
+++ b/arch/arm/dts/tegra210.dtsi
@@ -1,4 +1,4 @@
-#include dt-bindings/clock/tegra124-car.h
+#include dt-bindings/clock/tegra210-car.h
#include dt-bindings/gpio/tegra-gpio.h
#include dt-bindings/pinctrl/pinctrl-tegra.h
#include dt-bindings/interrupt-controller/arm-gic.h
@@ -7,7 +7,7 @@
#include skeleton.dtsi
/ {
- compatible = nvidia,tegra124;
+ compatible = nvidia,tegra210;
interrupt-parent = gic;
pcie-controller@01003000 {
@@ -35,10 +35,10 @@
0x8200 0 0x1300 0x1300 0 0x0d00 /*
non-prefetchable memory (208 MiB) */
0xc200 0 0x2000 0x2000 0 0x2000; /*
prefetchable memory (512 MiB) */
- clocks = tegra_car TEGRA124_CLK_PCIE,
-tegra_car TEGRA124_CLK_AFI,
-tegra_car TEGRA124_CLK_PLL_E,
-tegra_car TEGRA124_CLK_CML0;
+ clocks = tegra_car TEGRA210_CLK_PCIE,
+tegra_car TEGRA210_CLK_AFI,
+tegra_car TEGRA210_CLK_PLL_E,
+tegra_car TEGRA210_CLK_CML0;
clock-names = pex, afi, pll_e, cml;
resets
[U-Boot] [PATCH V2 6/6] T210: Add support for 64-bit T210-based P2571 board
Based on Venice2, incorporates Stephen Warren's
latest P2571 pinmux table.
With Thierry Reding's 64-bit build fixes, this
will build and and boot in 64-bit on my P2571
(when used with a 32-bit AVP loader).
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/mach-tegra/tegra210/Kconfig | 7 +
board/nvidia/{beaver = p2571}/Kconfig | 6 +-
board/nvidia/p2571/MAINTAINERS | 6 +
.../tegra210 = board/nvidia/p2571}/Makefile | 6 +-
board/nvidia/p2571/max77620_init.c | 85
board/nvidia/p2571/max77620_init.h | 67 ++
board/nvidia/p2571/p2571.c | 29 +++
board/nvidia/p2571/pinmux-config-p2571.h | 235 +
configs/{beaver_defconfig = p2571_defconfig} | 6 +-
include/configs/{venice2.h = p2571.h} | 42 ++--
.../{tegra124-common.h = tegra210-common.h} | 15 +-
11 files changed, 469 insertions(+), 35 deletions(-)
copy board/nvidia/{beaver = p2571}/Kconfig (61%)
create mode 100644 board/nvidia/p2571/MAINTAINERS
copy {arch/arm/mach-tegra/tegra210 = board/nvidia/p2571}/Makefile (59%)
create mode 100644 board/nvidia/p2571/max77620_init.c
create mode 100644 board/nvidia/p2571/max77620_init.h
create mode 100644 board/nvidia/p2571/p2571.c
create mode 100644 board/nvidia/p2571/pinmux-config-p2571.h
copy configs/{beaver_defconfig = p2571_defconfig} (77%)
copy include/configs/{venice2.h = p2571.h} (62%)
copy include/configs/{tegra124-common.h = tegra210-common.h} (89%)
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig
b/arch/arm/mach-tegra/tegra210/Kconfig
index f2a0059..147e6a8 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -3,9 +3,16 @@ if TEGRA210
choice
prompt Tegra210 board select
+config TARGET_P2571
+ bool NVIDIA Tegra210 P2571 base board
+ help
+ P2571 is a P2530 married to a P1963 I/O board
+
endchoice
config SYS_SOC
default tegra210
+source board/nvidia/p2571/Kconfig
+
endif
diff --git a/board/nvidia/beaver/Kconfig b/board/nvidia/p2571/Kconfig
similarity index 61%
copy from board/nvidia/beaver/Kconfig
copy to board/nvidia/p2571/Kconfig
index 23f7c94..7bc4874 100644
--- a/board/nvidia/beaver/Kconfig
+++ b/board/nvidia/p2571/Kconfig
@@ -1,12 +1,12 @@
-if TARGET_BEAVER
+if TARGET_P2571
config SYS_BOARD
- default beaver
+ default p2571
config SYS_VENDOR
default nvidia
config SYS_CONFIG_NAME
- default beaver
+ default p2571
endif
diff --git a/board/nvidia/p2571/MAINTAINERS b/board/nvidia/p2571/MAINTAINERS
new file mode 100644
index 000..c165135
--- /dev/null
+++ b/board/nvidia/p2571/MAINTAINERS
@@ -0,0 +1,6 @@
+P2571 BOARD
+M: Tom Warren twar...@nvidia.com
+S: Maintained
+F: board/nvidia/p2571/
+F: include/configs/p2571.h
+F: configs/p2571_defconfig
diff --git a/arch/arm/mach-tegra/tegra210/Makefile b/board/nvidia/p2571/Makefile
similarity index 59%
copy from arch/arm/mach-tegra/tegra210/Makefile
copy to board/nvidia/p2571/Makefile
index 1fb8d1a..223062e 100644
--- a/arch/arm/mach-tegra/tegra210/Makefile
+++ b/board/nvidia/p2571/Makefile
@@ -5,7 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += clock.o
-obj-y += funcmux.o
-obj-y += pinmux.o
-obj-y += xusb-padctl.o
+obj-y += max77620_init.o
+obj-y += p2571.o
diff --git a/board/nvidia/p2571/max77620_init.c
b/board/nvidia/p2571/max77620_init.c
new file mode 100644
index 000..ed8d4dc
--- /dev/null
+++ b/board/nvidia/p2571/max77620_init.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation www.nvidia.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch-tegra/tegra_i2c.h
+#include max77620_init.h
+
+/* MAX77620-PMIC-specific early init code - get CPU rails up, etc */
+
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+ struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+ writel(addr, reg-cmd_addr0);
+ writel(config, reg-cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+ struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+ writel(data, reg-cmd_data1);
+ writel(config, reg-cnfg);
+}
+
+void pmic_enable_cpu_vdd(void)
+{
+ uint reg;
+ debug(%s entry\n, __func__);
+
+ /* Setup/Enable GPIO5 - VDD_CPU_REG_EN */
+ debug(%s: Setting GPIO5 to enable CPU regulator\n, __func__);
+ /* B3=1=logic high,B2=dontcare,B1=0=output,B0=1=push-pull */
+ reg = 0x0900 | MAX77620_GPIO5_REG;
+ tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
+ udelay(10 * 1000);
+
+ /* Setup/Enable GPIO1 - VDD_HDMI_5V0_BST_EN */
+ debug(%s: Setting GPIO1 to enable HDMI\n, __func__);
+ reg = 0x0900 | MAX77620_GPIO1_REG;
+ tegra_i2c_ll_write_addr
Re: [U-Boot] [PATCH 0/4] Tegra210 support for P2571
Yes, it's a 32-bit T210 U-Boot. T210 supports both AARCH32 and AARCH64. A 64-bit build will follow, but I haven't figured out how to meld the 32-bit AVP SPL portion/build with the 64-bit CPU portion/build in one clean build command, so I'm building them separately and then fusing them together in a separate script. If anyone has ideas on how to generate a hybrid 32-bit (AVP)/64-bit (A57) U-Boot binary in one fell swoop, I'm all ears. :) Tom -Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Wednesday, June 17, 2015 1:07 PM To: Tom Warren Cc: u-boot@lists.denx.de; Stephen Warren; Tom Warren Subject: Re: [U-Boot] [PATCH 0/4] Tegra210 support for P2571 On 06/03/2015 02:35 PM, Tom Warren wrote: Adds support for Tegra210 SoC and P2571 NVIDIA board. Largely based on T124/Venice2. This is a baseline patchset - more will follow to make things more T210- specific as P2571 peripherals/devices are brought up. Does this add support for a 32-bit or a 64-bit U-Boot? Since T210 is a 64-bit CPU I would have expected a 64-bit U-Boot, yet: a) arch/arm/Kconfig contains: config TEGRA ... select CPU_V7 and this patch doesn't modify that. b) I can built an executable with these patches applied (after manually fixing up some merge problems) with an ARMv7 compiler, but not with an ARMv8 compiler. I think that means this is a 32-bit port. We need a 64-bit port. --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files for T210
-Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Tuesday, June 16, 2015 1:29 PM To: Tom Warren; Tom Warren Cc: u-boot@lists.denx.de; Stephen Warren Subject: Re: [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files for T210 On 06/15/2015 04:18 PM, Tom Warren wrote: Update WRT gpio.h and hardware.h, below. Tom Warren wrote at Monday, June 15, 2015 1:05 PM: Stephen Warren wrote at Monday, June 15, 2015 10:11 AM: On 06/03/2015 02:35 PM, Tom Warren wrote: All based off of Tegra124. As a Tegra210 board is brought up, these may change a bit to match the HW more closely, but probably 90% of this is identical to T124. ... diff --git a/arch/arm/include/asm/arch-tegra210/hardware.h b/arch/arm/include/asm/arch-tegra210/hardware.h Can we drop this file? I don't see a hardware.h in any of the other arch-tegra*/ directories. Sure. It's never been used AFAICT. Can't drop hardware.h. It's expected to be in every build, included from arch/arm/include/asm/hardware.h, created by Wolfgang way back in 2003. But there is no hardware.h in any of arch/arm/include/asm/arch-tegra*.h in u-boot.git's master branch as of today. Sorry, I must have been looking at my u-boot-tegra/next branch, which hasn't been sync'd w/master (u-boot or u-boot-tegra) in a while. I'll remove hardware.h in the next patchset. Thanks -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] P2571: dts: Add DT files for Tegra210/P2571 board
-Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Monday, June 15, 2015 10:23 AM To: Tom Warren Cc: u-boot@lists.denx.de; Stephen Warren; Tom Warren Subject: Re: [U-Boot] [PATCH 3/4] P2571: dts: Add DT files for Tegra210/P2571 board On 06/03/2015 02:35 PM, Tom Warren wrote: Based on T124 Venice2. SDMMC1 is SD-card slot. Using tegra124 compat names for now to get everything working. May need minor work to match the real board. This looks OK at a quick glance, although the may need minor rework comment is worrying; can't we simply not add things into the DT until they've been validated? Otherwise, we run the risk of the DT containing incorrect misleading data. That's a disclaimer I had in originally before working through all the bringup issues. Should be removed, the DT files match what I have in my 'fully-ported working' branch. -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] T210: Add support for T210-based P2571 board
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Monday, June 15, 2015 10:59 AM
To: Tom Warren
Cc: u-boot@lists.denx.de; Stephen Warren; Tom Warren
Subject: Re: [U-Boot] [PATCH 4/4] T210: Add support for T210-based P2571
board
On 06/03/2015 02:35 PM, Tom Warren wrote:
Based on Venice2, may change as P2571 board is fully brought up.
Incorporates Stephen Warren's P2571 pinmux table.
diff --git a/board/nvidia/p2571/max77620_init.c
b/board/nvidia/p2571/max77620_init.c
+void tegra_i2c_ll_write_addr(uint addr, uint config) {
+ struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+ writel(addr, reg-cmd_addr0);
+ writel(config, reg-cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config) {
+ struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+ writel(data, reg-cmd_data1);
+ writel(config, reg-cnfg);
+}
+
We really should put that into a lilbrary function, probably along with the
definition of things like I2C_SEND_2_BYTES (or make some more helper
functions to hide that too).
Yep, we should make a PMIC driver for this part, but haven't yet. This is
cutpaste from all the other Tegra boards.
I'll look into moving things around to make it cleaner, but that'll affect all
boards and would be a separate effort.
+void pmic_enable_cpu_vdd(void)
+{
+ debug(%s entry\n, __func__);
+
+//from TegraShell init script: Set GPIO5 to drive CPU_REG_EN
+// then 1.0V on ???
I don't think we should mention internal tool names in upstream source.
Good catch, thanks. This has been addressed in a V2 patchset I did last week
when I ran checkpatch.
+debug(%s: Setting GPIO5 to push-pull out, logic high to enable CPU
regulator\n, __func__);
+tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
+tegra_i2c_ll_write_data(0x2040, I2C_SEND_2_BYTES); //data/reg
+udelay(10*1000);
Need spaces around *.
I'm not sure what data/reg means?
0x2040 is 0x20 data, 0x40 register. Just a note to myself during bringup.
Removed.
+
+tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
+tegra_i2c_ll_write_data(0x093B, I2C_SEND_2_BYTES);
//B3=1=logic
high,B2=dontcare,B1=0=output,B0=1=push-pull
+udelay(10 * 1000);
Can we wrap that put that comment on a separate line, since it's rather long.
I
don't think U-Boot likes // comments.
Does this patch pass checkpatch?
V2 does, all C99 // comments removed, 80-char+ lines fixed, etc. I'll post it
when I address your other concerns.
diff --git a/board/nvidia/p2571/pinmux-config-p2571.h
b/board/nvidia/p2571/pinmux-config-p2571.h
I think I generated this a long time ago. I'd like to get this into
tegra-pinmux-
scripts, and make sure we're pulling in data from the latest board
spreadsheet,
before we commit this. I'll look into that today.
Good idea. Thanks.
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Re: [U-Boot] [PATCH 4/4] T210: Add support for T210-based P2571 board
-Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Monday, June 15, 2015 11:22 AM To: Tom Warren Cc: u-boot@lists.denx.de; Stephen Warren; Tom Warren Subject: Re: [U-Boot] [PATCH 4/4] T210: Add support for T210-based P2571 board On 06/15/2015 11:58 AM, Stephen Warren wrote: On 06/03/2015 02:35 PM, Tom Warren wrote: Based on Venice2, may change as P2571 board is fully brought up. Incorporates Stephen Warren's P2571 pinmux table. ... diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h I think I generated this a long time ago. I'd like to get this into tegra-pinmux-scripts, and make sure we're pulling in data from the latest board spreadsheet, before we commit this. I'll look into that today. I've validated that the pinmux data in this patch is up-to-date. There are some whitespace differences in the definition of the PINCFG() macro, so it might be nice to regenerate pinmux-config-p2571.h before any future patch version to make sure it 100% matches what the scripts output. I don't know how to generate the pinmux table header from the SS, so if you could do that and pass it to me for the next patchset, I'd appreciate it. Tom -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files for T210
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Monday, June 15, 2015 10:11 AM
To: Tom Warren
Cc: u-boot@lists.denx.de; Stephen Warren; Tom Warren
Subject: Re: [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files
for T210
On 06/03/2015 02:35 PM, Tom Warren wrote:
All based off of Tegra124. As a Tegra210 board is brought up, these
may change a bit to match the HW more closely, but probably 90% of
this is identical to T124.
Rather than duplicating lots of headers and code, can we share the content
with other chips?
Sure, but I wasn't looking at this patchset as a reworking of all Tegra common
headers, but an inclusion of T210 support. We can then move to common/shared
content after this is in, or someone (you?) can do it now before I add T210
support, but that'll delay it.
diff --git a/arch/arm/include/asm/arch-tegra210/funcmux.h
b/arch/arm/include/asm/arch-tegra210/funcmux.h
We should be able to drop funcmux support completely now that we're
programming entire board pinmux tables.
I'll look into it, but I believe funcmux is only used to get early UART muxes
set, which is done before the pinmux table is parsed/written.
diff --git a/arch/arm/include/asm/arch-tegra210/gpio.h
b/arch/arm/include/asm/arch-tegra210/gpio.h
+enum gpio_pin {
+ GPIO_PA0 = 0, /* pin 0 */
+ GPIO_PA1,
Given the move to DT, are any of these GPIO_xxx values actually used? I
wonder how many other types/defines in the other files are actually used,
rather than simply left over from times gone by.
Again, that's more of a general Tegra cleanup phase then this patchset is
intended for. I'll take a quick look, but I don't want to get delayed by doing
a bunch of Tegra cleanup stuff right now.
diff --git a/arch/arm/include/asm/arch-tegra210/hardware.h
b/arch/arm/include/asm/arch-tegra210/hardware.h
Can we drop this file? I don't see a hardware.h in any of the other
arch-tegra*/
directories.
Sure. It's never been used AFAICT.
diff --git a/arch/arm/include/asm/arch-tegra210/tegra.h
b/arch/arm/include/asm/arch-tegra210/tegra.h
+#define BCT_ODMDATA_OFFSET 1704/* offset to ODMDATA word */
+
+#undef NVBOOTINFOTABLE_BCTSIZE
+#undef NVBOOTINFOTABLE_BCTPTR
+#define NVBOOTINFOTABLE_BCTSIZE0x48/* BCT size in BIT in
IRAM */
+#define NVBOOTINFOTABLE_BCTPTR 0x4C/* BCT pointer in BIT in
IRAM */
Have you validated those? I'm pretty sure the BCT and perhaps BIT layout
changed in T210, and those values match T124.
Good point. They have changed, since the BCT structure has changed. I'll update
them w/real T210 offsets.
Have all the clock tables and IDs been updated to match T210? If not, I think
we
should do that before checking in the code, or it'll be misleading.
I believe so - I'm using the clock tables from my 'fully working' branch, so
they should be accurate/jibe with the TRM, but I'll double-check.
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Re: [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files for T210
Update WRT gpio.h and hardware.h, below.
-Original Message-
From: Tom Warren
Sent: Monday, June 15, 2015 1:05 PM
To: 'Stephen Warren'; Tom Warren
Cc: u-boot@lists.denx.de; Stephen Warren
Subject: RE: [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files
for T210
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Monday, June 15, 2015 10:11 AM
To: Tom Warren
Cc: u-boot@lists.denx.de; Stephen Warren; Tom Warren
Subject: Re: [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include
files for T210
On 06/03/2015 02:35 PM, Tom Warren wrote:
All based off of Tegra124. As a Tegra210 board is brought up, these
may change a bit to match the HW more closely, but probably 90% of
this is identical to T124.
Rather than duplicating lots of headers and code, can we share the
content with other chips?
Sure, but I wasn't looking at this patchset as a reworking of all Tegra common
headers, but an inclusion of T210 support. We can then move to
common/shared content after this is in, or someone (you?) can do it now
before I add T210 support, but that'll delay it.
diff --git a/arch/arm/include/asm/arch-tegra210/funcmux.h
b/arch/arm/include/asm/arch-tegra210/funcmux.h
We should be able to drop funcmux support completely now that we're
programming entire board pinmux tables.
I'll look into it, but I believe funcmux is only used to get early UART muxes
set,
which is done before the pinmux table is parsed/written.
diff --git a/arch/arm/include/asm/arch-tegra210/gpio.h
b/arch/arm/include/asm/arch-tegra210/gpio.h
+enum gpio_pin {
+ GPIO_PA0 = 0, /* pin 0 */
+ GPIO_PA1,
Given the move to DT, are any of these GPIO_xxx values actually used?
I wonder how many other types/defines in the other files are actually
used, rather than simply left over from times gone by.
Again, that's more of a general Tegra cleanup phase then this patchset is
intended for. I'll take a quick look, but I don't want to get delayed by
doing a
bunch of Tegra cleanup stuff right now.
They're used in the pinmux table (pinmux-config-venice2.h, for example) and
some board files (nyan-big.c, cardhu.c, seaboard.c). Can't remove 'em.
diff --git a/arch/arm/include/asm/arch-tegra210/hardware.h
b/arch/arm/include/asm/arch-tegra210/hardware.h
Can we drop this file? I don't see a hardware.h in any of the other
arch-tegra*/ directories.
Sure. It's never been used AFAICT.
Can't drop hardware.h. It's expected to be in every build, included from
arch/arm/include/asm/hardware.h, created by Wolfgang way back in 2003.
diff --git a/arch/arm/include/asm/arch-tegra210/tegra.h
b/arch/arm/include/asm/arch-tegra210/tegra.h
+#define BCT_ODMDATA_OFFSET 1704/* offset to ODMDATA word */
+
+#undef NVBOOTINFOTABLE_BCTSIZE
+#undef NVBOOTINFOTABLE_BCTPTR
+#define NVBOOTINFOTABLE_BCTSIZE 0x48/* BCT size in BIT in
IRAM */
+#define NVBOOTINFOTABLE_BCTPTR 0x4C/* BCT pointer in BIT in
IRAM */
Have you validated those? I'm pretty sure the BCT and perhaps BIT
layout changed in T210, and those values match T124.
Good point. They have changed, since the BCT structure has changed. I'll
update them w/real T210 offsets.
Have all the clock tables and IDs been updated to match T210? If not,
I think we should do that before checking in the code, or it'll be
misleading.
I believe so - I'm using the clock tables from my 'fully working' branch, so
they
should be accurate/jibe with the TRM, but I'll double-check.
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[U-Boot] Pull request: u-boot-tegra/master
Tom, Please pull u-boot-tegra/master into U-Boot/master. Thanks! ./MAKEALL -s tegra is OK, nyan-big verified by Simon. The following changes since commit 3d0158ae18bef2ac89979f4c90419d3add436c71: Prepare v2015.07-rc2 (2015-06-08 17:48:33 -0400) are available in the git repository at: git://git.denx.de/u-boot-tegra.git master for you to fetch changes up to b7160fabf11f423e879ee9cdcf8f7d0de7964509: tegra: config: nyan-big: Add options required by Chrome OS boot (2015-06-09 09:56:16 -0700) Simon Glass (15): tegra: cros_ec: Add tegra support for Chrome OS EC tegra: spi: Drop the claim_bus() method to correct delays dm: tegra: cros_ec: Enable Chrome OS EC on Nyan-big tegra: spi: Support slow SPI rates tegra: clock: Support enabling external clocks tegra: clock: Adjust PLL access to avoid a warning tegra: Introduce SRAM repair on tegra124 tegra: Add missing tegra124 peripherals tegra: Increase maximum arguments to 32 tegra: lcd: Tidy up clock init tegra: Allow board-specific init tegra: nyan-big: Add additional clock and kernel init tegra: config: Allow Chrome OS environment settings to be included tegra: Replace 'Norrin' with 'Nyan-big' and fix typo tegra: config: nyan-big: Add options required by Chrome OS boot arch/arm/dts/tegra124-nyan-big.dts| 3 + arch/arm/include/asm/arch-tegra/clock.h | 8 +++ arch/arm/include/asm/arch-tegra/sys_proto.h | 7 +++ arch/arm/include/asm/arch-tegra124/clock-tables.h | 12 ++-- arch/arm/include/asm/arch-tegra124/flow.h | 12 arch/arm/mach-tegra/board2.c | 8 ++- arch/arm/mach-tegra/clock.c | 24 +++- arch/arm/mach-tegra/powergate.c | 20 ++- arch/arm/mach-tegra/tegra124/Kconfig | 2 +- arch/arm/mach-tegra/tegra124/clock.c | 2 +- board/nvidia/nyan-big/MAINTAINERS | 2 +- board/nvidia/nyan-big/nyan-big.c | 69 +++ configs/nyan-big_defconfig| 5 ++ drivers/spi/tegra114_spi.c| 40 +++-- drivers/video/tegra124/tegra124-lcd.c | 4 +- include/configs/nyan-big.h| 7 +++ include/configs/tegra-common-post.h | 15 - include/configs/tegra-common.h| 2 +- 18 files changed, 204 insertions(+), 38 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/4] T210: Add support for T210-based P2571 board
Based on Venice2, may change as P2571 board is fully
brought up. Incorporates Stephen Warren's P2571 pinmux table.
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/mach-tegra/tegra210/Kconfig | 7 +
board/nvidia/{beaver = p2571}/Kconfig | 6 +-
board/nvidia/p2571/MAINTAINERS | 6 +
board/nvidia/{venice2 = p2571}/Makefile | 6 +-
board/nvidia/p2571/max77620_init.c | 47 +
board/nvidia/p2571/max77620_init.h | 14 ++
board/nvidia/p2571/p2571.c | 29 +++
board/nvidia/p2571/pinmux-config-p2571.h | 235 +
configs/p2571_defconfig| 5 +
include/configs/{venice2.h = p2571.h} | 17 +-
.../{tegra124-common.h = tegra210-common.h} | 8 +-
11 files changed, 363 insertions(+), 17 deletions(-)
copy board/nvidia/{beaver = p2571}/Kconfig (61%)
create mode 100644 board/nvidia/p2571/MAINTAINERS
copy board/nvidia/{venice2 = p2571}/Makefile (55%)
create mode 100644 board/nvidia/p2571/max77620_init.c
create mode 100644 board/nvidia/p2571/max77620_init.h
create mode 100644 board/nvidia/p2571/p2571.c
create mode 100644 board/nvidia/p2571/pinmux-config-p2571.h
create mode 100644 configs/p2571_defconfig
copy include/configs/{venice2.h = p2571.h} (81%)
copy include/configs/{tegra124-common.h = tegra210-common.h} (95%)
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig
b/arch/arm/mach-tegra/tegra210/Kconfig
index f2a0059..147e6a8 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -3,9 +3,16 @@ if TEGRA210
choice
prompt Tegra210 board select
+config TARGET_P2571
+ bool NVIDIA Tegra210 P2571 base board
+ help
+ P2571 is a P2530 married to a P1963 I/O board
+
endchoice
config SYS_SOC
default tegra210
+source board/nvidia/p2571/Kconfig
+
endif
diff --git a/board/nvidia/beaver/Kconfig b/board/nvidia/p2571/Kconfig
similarity index 61%
copy from board/nvidia/beaver/Kconfig
copy to board/nvidia/p2571/Kconfig
index 23f7c94..7bc4874 100644
--- a/board/nvidia/beaver/Kconfig
+++ b/board/nvidia/p2571/Kconfig
@@ -1,12 +1,12 @@
-if TARGET_BEAVER
+if TARGET_P2571
config SYS_BOARD
- default beaver
+ default p2571
config SYS_VENDOR
default nvidia
config SYS_CONFIG_NAME
- default beaver
+ default p2571
endif
diff --git a/board/nvidia/p2571/MAINTAINERS b/board/nvidia/p2571/MAINTAINERS
new file mode 100644
index 000..c165135
--- /dev/null
+++ b/board/nvidia/p2571/MAINTAINERS
@@ -0,0 +1,6 @@
+P2571 BOARD
+M: Tom Warren twar...@nvidia.com
+S: Maintained
+F: board/nvidia/p2571/
+F: include/configs/p2571.h
+F: configs/p2571_defconfig
diff --git a/board/nvidia/venice2/Makefile b/board/nvidia/p2571/Makefile
similarity index 55%
copy from board/nvidia/venice2/Makefile
copy to board/nvidia/p2571/Makefile
index 5fac5ab..223062e 100644
--- a/board/nvidia/venice2/Makefile
+++ b/board/nvidia/p2571/Makefile
@@ -1,9 +1,9 @@
#
-# (C) Copyright 2013-2014
+# (C) Copyright 2013-2015
# NVIDIA Corporation www.nvidia.com
#
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += as3722_init.o
-obj-y += venice2.o
+obj-y += max77620_init.o
+obj-y += p2571.o
diff --git a/board/nvidia/p2571/max77620_init.c
b/board/nvidia/p2571/max77620_init.c
new file mode 100644
index 000..98c94af
--- /dev/null
+++ b/board/nvidia/p2571/max77620_init.c
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation www.nvidia.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch-tegra/tegra_i2c.h
+#include max77620_init.h
+
+/* MAX77620-PMIC-specific early init code - get CPU rails up, etc */
+
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+ struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+ writel(addr, reg-cmd_addr0);
+ writel(config, reg-cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+ struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+ writel(data, reg-cmd_data1);
+ writel(config, reg-cnfg);
+}
+
+void pmic_enable_cpu_vdd(void)
+{
+ debug(%s entry\n, __func__);
+
+//from TegraShell init script: Set GPIO5 to drive CPU_REG_EN
+// then 1.0V on ???
+debug(%s: Setting GPIO5 to push-pull out, logic high to enable CPU
regulator\n, __func__);
+tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
+tegra_i2c_ll_write_data(0x2040, I2C_SEND_2_BYTES); //data/reg
+udelay(10*1000);
+
+tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
+tegra_i2c_ll_write_data(0x093B, I2C_SEND_2_BYTES); //B3=1=logic
high,B2=dontcare,B1=0=output,B0=1=push-pull
+udelay(10 * 1000);
+
+debug(%s: Set VDD_SDMMC to 3.3V via MAX77620 reg ???\n, __func__);
+}
diff --git
[U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files for T210
All based off of Tegra124. As a Tegra210 board is brought
up, these may change a bit to match the HW more closely,
but probably 90% of this is identical to T124.
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/include/asm/arch-tegra210/ahb.h | 91 ++
arch/arm/include/asm/arch-tegra210/clock-tables.h | 566 +++
arch/arm/include/asm/arch-tegra210/clock.h| 27 +
arch/arm/include/asm/arch-tegra210/flow.h | 45 +
arch/arm/include/asm/arch-tegra210/funcmux.h | 23 +
arch/arm/include/asm/arch-tegra210/gp_padctrl.h | 74 ++
arch/arm/include/asm/arch-tegra210/gpio.h | 303 ++
arch/arm/include/asm/arch-tegra210/hardware.h | 16 +
arch/arm/include/asm/arch-tegra210/mc.h | 72 ++
arch/arm/include/asm/arch-tegra210/pmu.h | 14 +
arch/arm/include/asm/arch-tegra210/powergate.h| 12 +
arch/arm/include/asm/arch-tegra210/sysctr.h | 26 +
arch/arm/include/asm/arch-tegra210/tegra.h| 32 +
arch/arm/mach-tegra/tegra210/Kconfig | 11 +
arch/arm/mach-tegra/tegra210/Makefile | 13 +
arch/arm/mach-tegra/tegra210/clock.c | 1086 +
arch/arm/mach-tegra/tegra210/cpu.c| 328 +++
arch/arm/mach-tegra/tegra210/funcmux.c| 71 ++
arch/arm/mach-tegra/tegra210/xusb-padctl.c| 494 ++
include/dt-bindings/clock/tegra210-car.h | 342 +++
20 files changed, 3646 insertions(+)
create mode 100644 arch/arm/include/asm/arch-tegra210/ahb.h
create mode 100644 arch/arm/include/asm/arch-tegra210/clock-tables.h
create mode 100644 arch/arm/include/asm/arch-tegra210/clock.h
create mode 100644 arch/arm/include/asm/arch-tegra210/flow.h
create mode 100644 arch/arm/include/asm/arch-tegra210/funcmux.h
create mode 100644 arch/arm/include/asm/arch-tegra210/gp_padctrl.h
create mode 100644 arch/arm/include/asm/arch-tegra210/gpio.h
create mode 100644 arch/arm/include/asm/arch-tegra210/hardware.h
create mode 100644 arch/arm/include/asm/arch-tegra210/mc.h
create mode 100644 arch/arm/include/asm/arch-tegra210/pmu.h
create mode 100644 arch/arm/include/asm/arch-tegra210/powergate.h
create mode 100644 arch/arm/include/asm/arch-tegra210/sysctr.h
create mode 100644 arch/arm/include/asm/arch-tegra210/tegra.h
create mode 100644 arch/arm/mach-tegra/tegra210/Kconfig
create mode 100644 arch/arm/mach-tegra/tegra210/Makefile
create mode 100644 arch/arm/mach-tegra/tegra210/clock.c
create mode 100644 arch/arm/mach-tegra/tegra210/cpu.c
create mode 100644 arch/arm/mach-tegra/tegra210/funcmux.c
create mode 100644 arch/arm/mach-tegra/tegra210/xusb-padctl.c
create mode 100644 include/dt-bindings/clock/tegra210-car.h
diff --git a/arch/arm/include/asm/arch-tegra210/ahb.h
b/arch/arm/include/asm/arch-tegra210/ahb.h
new file mode 100644
index 000..3a37af4
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/ahb.h
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation www.nvidia.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA210_AHB_H_
+#define _TEGRA210_AHB_H_
+
+struct ahb_ctlr {
+ u32 reserved0; /* 00h */
+ u32 arbitration_disable;/* _ARBITRATION_DISABLE_0, 04h */
+ u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */
+ u32 arbitration_usr_protect;/* _ARBITRATION_USR_PROTECT_0, 0ch */
+ u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0,10h */
+ u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0,14h */
+ u32 reserved6[2]; /* 18h, 1ch */
+ u32 gizmo_usb; /* _GIZMO_USB_0,20h */
+ u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0,24h */
+ u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */
+ u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */
+ u32 gizmo_xbar_apb_ctlr;/* _GIZMO_XBAR_APB_CTLR_0, 30h */
+ u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */
+ u32 reserved13[2]; /* 38h, 3ch */
+ u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */
+ u32 reserved15; /* 44h */
+ u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */
+ u32 reserved17; /* 4ch */
+ u32 gizmo_se; /* _GIZMO_SE_0, 50h */
+ u32 gizmo_tzram;/* _GIZMO_TZRAM_0, 54h */
+ u32 reserved20[3]; /* 58h, 5ch, 60h */
+ u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */
+ u32 reserved22[3]; /* 68h, 6ch, 70h */
+ u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */
+ u32 gizmo_nor; /* _GIZMO_NOR_0,78h */
+ u32 gizmo_usb2
[U-Boot] [PATCH 2/4] ARM: Tegra210: Add support to common Tegra source/config files
Derived from Tegra124, modify as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too.
Note that the 'empty' Kconfig for Tegra210 will cause
an innocuous build warning, but it'll go away when a
real T210 board is instantiated.
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/include/asm/arch-tegra/ap.h | 6 +--
arch/arm/include/asm/arch-tegra/clk_rst.h| 28 +++---
arch/arm/include/asm/arch-tegra/gp_padctrl.h | 3 +-
arch/arm/include/asm/arch-tegra/pmc.h| 7 ++--
arch/arm/include/asm/arch-tegra/tegra.h | 4 +-
arch/arm/mach-tegra/Kconfig | 4 ++
arch/arm/mach-tegra/Makefile | 4 +-
arch/arm/mach-tegra/ap.c | 9 -
arch/arm/mach-tegra/clock.c | 3 +-
arch/arm/mach-tegra/cpu.c| 55
arch/arm/mach-tegra/cpu.h| 10 +++--
include/fdtdec.h | 4 ++
lib/fdtdec.c | 3 ++
13 files changed, 104 insertions(+), 36 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/ap.h
b/arch/arm/include/asm/arch-tegra/ap.h
index ca40e4e..76773b7 100644
--- a/arch/arm/include/asm/arch-tegra/ap.h
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010-2011
+ * (C) Copyright 2010-2015
* NVIDIA Corporation www.nvidia.com
*
* SPDX-License-Identifier:GPL-2.0+
@@ -24,8 +24,6 @@
#define PG_UP_TAG_0_PID_CPU0x /* CPU aka a9 aka mpcore */
#define PG_UP_TAG_00x0
-#define CORESIGHT_UNLOCK 0xC5ACCE55;
-
/* AP base physical address of internal SRAM */
#define NV_PA_BASE_SRAM0x4000
@@ -66,7 +64,7 @@ int tegra_get_sku_info(void);
/* Do any chip-specific cache config */
void config_cache(void);
-#if defined(CONFIG_TEGRA124)
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
/* Do chip-specific vpr config */
void config_vpr(void);
#else
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h
b/arch/arm/include/asm/arch-tegra/clk_rst.h
index de50e08..43efa65 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -48,6 +48,7 @@ enum {
TEGRA_CLK_REGS_VW = 2,/* Number of clock enable regs V/W */
TEGRA_CLK_SOURCES_VW= 32, /* Number of ppl clock sources V/W */
TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */
+ TEGRA_CLK_SOURCES_Y = 18, /* Number of ppl clock sources Y */
};
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@@ -94,7 +95,15 @@ struct clk_rst_ctlr {
uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0,0x290 */
uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0,0x294 */
- uint crc_reserved21[23];/* _reserved_21,0x298-2f0 */
+ uint crc_clk_out_enb_y; /* _CLK_OUT_ENB_Y_0,0x298 */
+ uint crc_clk_enb_y_set; /* _CLK_ENB_Y_SET_0,0x29c */
+ uint crc_clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0,0x2a0 */
+
+ uint crc_rst_devices_y; /* _RST_DEVICES_Y_0,0x2a4 */
+ uint crc_rst_dev_y_set; /* _RST_DEV_Y_SET_0,0x2a8 */
+ uint crc_rst_dev_y_clr; /* _RST_DEV_Y_CLR_0,0x2ac */
+
+ uint crc_reserved21[17];/* _reserved_21,0x2b0-2f0 */
uint crc_dfll_base; /* _DFLL_BASE_0,0x2f4 */
@@ -136,7 +145,7 @@ struct clk_rst_ctlr {
struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
- /* Additional (T114) registers */
+ /* Additional (T114+) registers */
uint crc_rst_cpug_cmplx_set;/* _RST_CPUG_CMPLX_SET_0, 0x450 */
uint crc_rst_cpug_cmplx_clr;/* _RST_CPUG_CMPLX_CLR_0, 0x454 */
uint crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */
@@ -207,9 +216,18 @@ struct clk_rst_ctlr {
u32 _rsv32_1[7];/* 0x574-58c */
struct clk_pll_simple plldp;/* _PLLDP_BASE, 0x590 _PLLDP_MISC */
u32 crc_plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
- u32 _rsrv32_2[25];
- /* Tegra124 */
- uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */
+
+ /* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */
+ uint _rsrv32_2[25]; /* _0x59C - 0x5FC */
+ uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */
+
+ /* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */
+ uint crc_reserved61[5]; /* _reserved_61, 0x680 - 0x690 */
+ /*
+* NOTE: PLLA1 regs are in the middle of this Y region. Break this in
+* two later if PLLA1 is needed, but for now this is cleaner.
+*/
+ uint
[U-Boot] [PATCH 3/4] P2571: dts: Add DT files for Tegra210/P2571 board
Based on T124 Venice2. SDMMC1 is SD-card slot.
Using tegra124 compat names for now to get everything
working. May need minor work to match the real board.
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/dts/Makefile | 3 +-
.../{tegra124-venice2.dts = tegra210-p2571.dts} | 40 --
arch/arm/dts/{tegra124.dtsi = tegra210.dtsi} | 153 -
3 files changed, 56 insertions(+), 140 deletions(-)
copy arch/arm/dts/{tegra124-venice2.dts = tegra210-p2571.dts} (65%)
copy arch/arm/dts/{tegra124.dtsi = tegra210.dtsi} (76%)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f897e6d..3e09cb5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -33,7 +33,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra114-dalmore.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
- tegra124-venice2.dtb
+ tegra124-venice2.dtb \
+ tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
uniphier-ph1-pro4-ref.dtb \
diff --git a/arch/arm/dts/tegra124-venice2.dts b/arch/arm/dts/tegra210-p2571.dts
similarity index 65%
copy from arch/arm/dts/tegra124-venice2.dts
copy to arch/arm/dts/tegra210-p2571.dts
index 9e93cf9..ca41390 100644
--- a/arch/arm/dts/tegra124-venice2.dts
+++ b/arch/arm/dts/tegra210-p2571.dts
@@ -1,10 +1,10 @@
/dts-v1/;
-#include tegra124.dtsi
+#include tegra210.dtsi
/ {
- model = NVIDIA Venice2;
- compatible = nvidia,venice2, nvidia,tegra124;
+ model = NVIDIA P2571;
+ compatible = nvidia,p2571, nvidia,tegra210;
chosen {
stdout-path = uarta;
@@ -18,16 +18,15 @@
i2c4 = /i2c@7000c700;
i2c5 = /i2c@7000d100;
sdhci0 = /sdhci@700b0600;
- sdhci1 = /sdhci@700b0400;
+ sdhci1 = /sdhci@700b;
spi0 = /spi@7000d400;
spi1 = /spi@7000da00;
+ spi2 = /spi@7041;
usb0 = /usb@7d00;
- usb1 = /usb@7d008000;
};
memory {
- device_type = memory;
- reg = 0x8000 0x8000;
+ reg = 0x0 0x8000 0x0 0xc000;
};
i2c@7000c000 {
@@ -70,11 +69,15 @@
spi-max-frequency = 2500;
};
- sdhci@700b0400 {
+ spi@7041 {
status = okay;
- cd-gpios = gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH;
- power-gpios = gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH;
- wp-gpios = gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW;
+ spi-max-frequency = 2400;
+ };
+
+ sdhci@700b {
+ status = okay;
+ cd-gpios = gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW;
+ power-gpios = gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH;
bus-width = 4;
};
@@ -86,11 +89,18 @@
usb@7d00 {
status = okay;
dr_mode = otg;
- nvidia,vbus-gpio = gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH;
};
- usb@7d008000 {
- status = okay;
- nvidia,vbus-gpio = gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH;
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ clk32k_in: clock@0 {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 32768;
+ };
};
};
diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra210.dtsi
similarity index 76%
copy from arch/arm/dts/tegra124.dtsi
copy to arch/arm/dts/tegra210.dtsi
index 43b7f22..f09a1a7 100644
--- a/arch/arm/dts/tegra124.dtsi
+++ b/arch/arm/dts/tegra210.dtsi
@@ -1,4 +1,4 @@
-#include dt-bindings/clock/tegra124-car.h
+#include dt-bindings/clock/tegra210-car.h
#include dt-bindings/gpio/tegra-gpio.h
#include dt-bindings/pinctrl/pinctrl-tegra.h
#include dt-bindings/interrupt-controller/arm-gic.h
@@ -7,7 +7,7 @@
#include skeleton.dtsi
/ {
- compatible = nvidia,tegra124;
+ compatible = nvidia,tegra210;
interrupt-parent = gic;
pcie-controller@01003000 {
@@ -35,10 +35,10 @@
0x8200 0 0x1300 0x1300 0 0x0d00 /*
non-prefetchable memory (208 MiB) */
0xc200 0 0x2000 0x2000 0 0x2000; /*
prefetchable memory (512 MiB) */
- clocks = tegra_car TEGRA124_CLK_PCIE,
-tegra_car TEGRA124_CLK_AFI,
-tegra_car TEGRA124_CLK_PLL_E,
-tegra_car TEGRA124_CLK_CML0;
+ clocks = tegra_car TEGRA210_CLK_PCIE,
+tegra_car TEGRA210_CLK_AFI,
+tegra_car TEGRA210_CLK_PLL_E
[U-Boot] [PATCH 0/4] Tegra210 support for P2571
Adds support for Tegra210 SoC and P2571 NVIDIA board. Largely based on T124/Venice2. This is a baseline patchset - more will follow to make things more T210- specific as P2571 peripherals/devices are brought up. Tom Warren (4): ARM: Tegra210: Add SoC code/include files for T210 ARM: Tegra210: Add support to common Tegra source/config files P2572: dts: Add DT files for Tegra210/P2572 board T210: Add support for T210-based P2571 board arch/arm/dts/Makefile |3 +- arch/arm/dts/tegra210-p2571.dts | 106 ++ arch/arm/dts/tegra210.dtsi| 511 ++ arch/arm/include/asm/arch-tegra/ap.h |6 +- arch/arm/include/asm/arch-tegra/clk_rst.h | 28 +- arch/arm/include/asm/arch-tegra/gp_padctrl.h |3 +- arch/arm/include/asm/arch-tegra/pmc.h |7 +- arch/arm/include/asm/arch-tegra/tegra.h |4 +- arch/arm/include/asm/arch-tegra210/ahb.h | 91 ++ arch/arm/include/asm/arch-tegra210/clock-tables.h | 566 +++ arch/arm/include/asm/arch-tegra210/clock.h| 27 + arch/arm/include/asm/arch-tegra210/flow.h | 45 + arch/arm/include/asm/arch-tegra210/funcmux.h | 23 + arch/arm/include/asm/arch-tegra210/gp_padctrl.h | 74 ++ arch/arm/include/asm/arch-tegra210/gpio.h | 303 ++ arch/arm/include/asm/arch-tegra210/hardware.h | 16 + arch/arm/include/asm/arch-tegra210/mc.h | 72 ++ arch/arm/include/asm/arch-tegra210/pmu.h | 14 + arch/arm/include/asm/arch-tegra210/powergate.h| 12 + arch/arm/include/asm/arch-tegra210/sysctr.h | 26 + arch/arm/include/asm/arch-tegra210/tegra.h| 32 + arch/arm/mach-tegra/Kconfig |4 + arch/arm/mach-tegra/Makefile |4 +- arch/arm/mach-tegra/ap.c |9 +- arch/arm/mach-tegra/clock.c |3 +- arch/arm/mach-tegra/cpu.c | 55 +- arch/arm/mach-tegra/cpu.h | 10 +- arch/arm/mach-tegra/tegra210/Kconfig | 18 + arch/arm/mach-tegra/tegra210/Makefile | 13 + arch/arm/mach-tegra/tegra210/clock.c | 1086 + arch/arm/mach-tegra/tegra210/cpu.c| 328 +++ arch/arm/mach-tegra/tegra210/funcmux.c| 71 ++ arch/arm/mach-tegra/tegra210/xusb-padctl.c| 494 ++ board/nvidia/p2571/Kconfig| 12 + board/nvidia/p2571/MAINTAINERS|6 + board/nvidia/p2571/Makefile |9 + board/nvidia/p2571/max77620_init.c| 47 + board/nvidia/p2571/max77620_init.h| 14 + board/nvidia/p2571/p2571.c| 29 + board/nvidia/p2571/pinmux-config-p2571.h | 235 + configs/p2571_defconfig |5 + include/configs/p2571.h | 72 ++ include/configs/tegra210-common.h | 73 ++ include/dt-bindings/clock/tegra210-car.h | 342 +++ include/fdtdec.h |4 + lib/fdtdec.c |3 + 46 files changed, 4878 insertions(+), 37 deletions(-) create mode 100644 arch/arm/dts/tegra210-p2571.dts create mode 100644 arch/arm/dts/tegra210.dtsi create mode 100644 arch/arm/include/asm/arch-tegra210/ahb.h create mode 100644 arch/arm/include/asm/arch-tegra210/clock-tables.h create mode 100644 arch/arm/include/asm/arch-tegra210/clock.h create mode 100644 arch/arm/include/asm/arch-tegra210/flow.h create mode 100644 arch/arm/include/asm/arch-tegra210/funcmux.h create mode 100644 arch/arm/include/asm/arch-tegra210/gp_padctrl.h create mode 100644 arch/arm/include/asm/arch-tegra210/gpio.h create mode 100644 arch/arm/include/asm/arch-tegra210/hardware.h create mode 100644 arch/arm/include/asm/arch-tegra210/mc.h create mode 100644 arch/arm/include/asm/arch-tegra210/pmu.h create mode 100644 arch/arm/include/asm/arch-tegra210/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra210/sysctr.h create mode 100644 arch/arm/include/asm/arch-tegra210/tegra.h create mode 100644 arch/arm/mach-tegra/tegra210/Kconfig create mode 100644 arch/arm/mach-tegra/tegra210/Makefile create mode 100644 arch/arm/mach-tegra/tegra210/clock.c create mode 100644 arch/arm/mach-tegra/tegra210/cpu.c create mode 100644 arch/arm/mach-tegra/tegra210/funcmux.c create mode 100644 arch/arm/mach-tegra/tegra210/xusb-padctl.c create mode 100644 board/nvidia/p2571/Kconfig create mode 100644 board/nvidia/p2571/MAINTAINERS create mode 100644 board/nvidia/p2571/Makefile create mode 100644 board/nvidia/p2571/max77620_init.c create mode 100644 board/nvidia/p2571/max77620_init.h create mode 100644 board/nvidia/p2571/p2571.c create mode 100644 board/nvidia/p2571/pinmux-config-p2571.h
Re: [U-Boot] [PATCH v2 00/16] tegra: Expand Nyan-big support
Simon, Applied to u-boot-tegra/master, then I rebased against u-boot/master and uploaded it back to denx.de/u-boot-tegra/master. ./MAKEALL -s tegra works OK. I didn't test on any real HW - my nyan-big system is offline temporarily. PTAL and let me know if it's working OK and I'll get a PR out to TomR first thing next week. Tom -Original Message- From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass Sent: Friday, June 05, 2015 9:25 AM To: Tom Warren Cc: U-Boot Mailing List; Jagannadha Sutradharudu Teki; Stephen Warren; Marek Vasut; Pavel Herrmann; Stephen Warren Subject: Re: [PATCH v2 00/16] tegra: Expand Nyan-big support Hi Tom, On 4 June 2015 at 10:22, Tom Warren twar...@nvidia.com wrote: Simon, Tried applying your patchset. Two or three had minor 'git am' conflicts that were easy to resolve with 'patch', but #11 (tegra: Allow board-specific init) conflicts with Mashiro's move of board.c to board2.c in mach-tegra: Author: Masahiro Yamada yamada.masah...@socionext.com Date: Mon Apr 13 10:51:14 2015 +0900 ARM: tegra: move NVIDIA common files to arch/arm/mach-tegra Please rebase your patches against current TOT u-boot-tegra/master and let me know when they're up on patchwork and I'll retry. OK I'm just running a test now and will get this out this morning. Regards, Simon Thanks, Tom -Original Message- From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass Sent: Thursday, June 04, 2015 8:46 AM To: Tom Warren Cc: U-Boot Mailing List; Jagannadha Sutradharudu Teki; Stephen Warren; Marek Vasut; Pavel Herrmann; Stephen Warren Subject: Re: [PATCH v2 00/16] tegra: Expand Nyan-big support Hi Tom, On 4 June 2015 at 09:42, Tom Warren twar...@nvidia.com wrote: Sorry, I've been busy with T210 stuff. I'll try to take a look at it before the EOW. Great to see progress on T210. IIRC, there was some push-back from Stephen on boot scripts, etc. Have these concerns all been addressed? Have you gotten Acks? No the boot script patch is the one that should be left out. I talked to Stephen about it - there are some things we could do, but not in the timeframe of this release. Regards, Simon Tom -Original Message- From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass Sent: Thursday, June 04, 2015 8:16 AM To: U-Boot Mailing List Cc: Simon Glass; Tom Warren; Jagannadha Sutradharudu Teki; Stephen Warren; Marek Vasut; Pavel Herrmann; Stephen Warren Subject: Re: [PATCH v2 00/16] tegra: Expand Nyan-big support Hi Tom, On 13 May 2015 at 07:45, Simon Glass s...@chromium.org wrote: This series expands Nyan-big support: - Enable Chrome OS EC, so that the keyboard works - Add some extra clock and pre-kernel init required for reliable operation - Add Chrome OS environment variables, including 'run nvboot' to allow booting Chrome OS more easily Still missing are audio and USB. Changes in v2: - Use spi-max-frequency in both the bus and slave nodes - Remove unnecessary ODMDATA mangling - Use existing __stringify() macro - Drop tegra timer patch as it is not needed - Drop a few patches that have already been applied Doug Anderson (1): Add Chrome OS config header Apart from the above patch, can this series be applied please? Simon Glass (15): tegra: cros_ec: Add tegra support for Chrome OS EC tegra: spi: Drop the claim_bus() method to correct delays dm: tegra: cros_ec: Enable Chrome OS EC on Nyan-big tegra: spi: Support slow SPI rates tegra: clock: Support enabling external clocks tegra: clock: Adjust PLL access to avoid a warning tegra: Introduce SRAM repair on tegra124 tegra: Add missing tegra124 peripherals tegra: Increase maximum arguments to 32 tegra: lcd: Tidy up clock init tegra: Allow board-specific init tegra: nyan-big: Add additional clock and kernel init tegra: config: Allow Chrome OS environment settings to be included tegra: Replace 'Norrin' with 'Nyan-big' and fix typo tegra: config: nyan-big: Add options required by Chrome OS boot arch/arm/dts/tegra124-nyan-big.dts| 3 + arch/arm/include/asm/arch-tegra/clock.h | 8 + arch/arm/include/asm/arch-tegra/sys_proto.h | 7 + arch/arm/include/asm/arch-tegra124/clock-tables.h | 12 +- arch/arm/include/asm/arch-tegra124/flow.h | 12 + arch/arm/mach-tegra/clock.c | 24 +- arch/arm/mach-tegra/powergate.c | 20 +- arch/arm/mach-tegra/tegra124/Kconfig | 2 +- arch/arm/mach-tegra/tegra124/clock.c | 2 +- board/nvidia/common/board.c
Re: [U-Boot] [PATCH v2 00/16] tegra: Expand Nyan-big support
Sorry, I've been busy with T210 stuff. I'll try to take a look at it before the EOW. IIRC, there was some push-back from Stephen on boot scripts, etc. Have these concerns all been addressed? Have you gotten Acks? Tom -Original Message- From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass Sent: Thursday, June 04, 2015 8:16 AM To: U-Boot Mailing List Cc: Simon Glass; Tom Warren; Jagannadha Sutradharudu Teki; Stephen Warren; Marek Vasut; Pavel Herrmann; Stephen Warren Subject: Re: [PATCH v2 00/16] tegra: Expand Nyan-big support Hi Tom, On 13 May 2015 at 07:45, Simon Glass s...@chromium.org wrote: This series expands Nyan-big support: - Enable Chrome OS EC, so that the keyboard works - Add some extra clock and pre-kernel init required for reliable operation - Add Chrome OS environment variables, including 'run nvboot' to allow booting Chrome OS more easily Still missing are audio and USB. Changes in v2: - Use spi-max-frequency in both the bus and slave nodes - Remove unnecessary ODMDATA mangling - Use existing __stringify() macro - Drop tegra timer patch as it is not needed - Drop a few patches that have already been applied Doug Anderson (1): Add Chrome OS config header Apart from the above patch, can this series be applied please? Simon Glass (15): tegra: cros_ec: Add tegra support for Chrome OS EC tegra: spi: Drop the claim_bus() method to correct delays dm: tegra: cros_ec: Enable Chrome OS EC on Nyan-big tegra: spi: Support slow SPI rates tegra: clock: Support enabling external clocks tegra: clock: Adjust PLL access to avoid a warning tegra: Introduce SRAM repair on tegra124 tegra: Add missing tegra124 peripherals tegra: Increase maximum arguments to 32 tegra: lcd: Tidy up clock init tegra: Allow board-specific init tegra: nyan-big: Add additional clock and kernel init tegra: config: Allow Chrome OS environment settings to be included tegra: Replace 'Norrin' with 'Nyan-big' and fix typo tegra: config: nyan-big: Add options required by Chrome OS boot arch/arm/dts/tegra124-nyan-big.dts| 3 + arch/arm/include/asm/arch-tegra/clock.h | 8 + arch/arm/include/asm/arch-tegra/sys_proto.h | 7 + arch/arm/include/asm/arch-tegra124/clock-tables.h | 12 +- arch/arm/include/asm/arch-tegra124/flow.h | 12 + arch/arm/mach-tegra/clock.c | 24 +- arch/arm/mach-tegra/powergate.c | 20 +- arch/arm/mach-tegra/tegra124/Kconfig | 2 +- arch/arm/mach-tegra/tegra124/clock.c | 2 +- board/nvidia/common/board.c | 8 +- board/nvidia/nyan-big/MAINTAINERS | 2 +- board/nvidia/nyan-big/nyan-big.c | 69 configs/nyan-big_defconfig| 5 + drivers/spi/tegra114_spi.c| 40 +- drivers/video/tegra124/tegra124-lcd.c | 4 +- include/configs/chromeos.h| 457 ++ include/configs/nyan-big.h| 9 + include/configs/tegra-common-post.h | 15 +- include/configs/tegra-common.h| 2 +- 19 files changed, 663 insertions(+), 38 deletions(-) create mode 100644 include/configs/chromeos.h -- 2.2.0.rc0.207.ga3a616c Regards, Simon -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 00/16] tegra: Expand Nyan-big support
Simon, Tried applying your patchset. Two or three had minor 'git am' conflicts that were easy to resolve with 'patch', but #11 (tegra: Allow board-specific init) conflicts with Mashiro's move of board.c to board2.c in mach-tegra: Author: Masahiro Yamada yamada.masah...@socionext.com Date: Mon Apr 13 10:51:14 2015 +0900 ARM: tegra: move NVIDIA common files to arch/arm/mach-tegra Please rebase your patches against current TOT u-boot-tegra/master and let me know when they're up on patchwork and I'll retry. Thanks, Tom -Original Message- From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass Sent: Thursday, June 04, 2015 8:46 AM To: Tom Warren Cc: U-Boot Mailing List; Jagannadha Sutradharudu Teki; Stephen Warren; Marek Vasut; Pavel Herrmann; Stephen Warren Subject: Re: [PATCH v2 00/16] tegra: Expand Nyan-big support Hi Tom, On 4 June 2015 at 09:42, Tom Warren twar...@nvidia.com wrote: Sorry, I've been busy with T210 stuff. I'll try to take a look at it before the EOW. Great to see progress on T210. IIRC, there was some push-back from Stephen on boot scripts, etc. Have these concerns all been addressed? Have you gotten Acks? No the boot script patch is the one that should be left out. I talked to Stephen about it - there are some things we could do, but not in the timeframe of this release. Regards, Simon Tom -Original Message- From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass Sent: Thursday, June 04, 2015 8:16 AM To: U-Boot Mailing List Cc: Simon Glass; Tom Warren; Jagannadha Sutradharudu Teki; Stephen Warren; Marek Vasut; Pavel Herrmann; Stephen Warren Subject: Re: [PATCH v2 00/16] tegra: Expand Nyan-big support Hi Tom, On 13 May 2015 at 07:45, Simon Glass s...@chromium.org wrote: This series expands Nyan-big support: - Enable Chrome OS EC, so that the keyboard works - Add some extra clock and pre-kernel init required for reliable operation - Add Chrome OS environment variables, including 'run nvboot' to allow booting Chrome OS more easily Still missing are audio and USB. Changes in v2: - Use spi-max-frequency in both the bus and slave nodes - Remove unnecessary ODMDATA mangling - Use existing __stringify() macro - Drop tegra timer patch as it is not needed - Drop a few patches that have already been applied Doug Anderson (1): Add Chrome OS config header Apart from the above patch, can this series be applied please? Simon Glass (15): tegra: cros_ec: Add tegra support for Chrome OS EC tegra: spi: Drop the claim_bus() method to correct delays dm: tegra: cros_ec: Enable Chrome OS EC on Nyan-big tegra: spi: Support slow SPI rates tegra: clock: Support enabling external clocks tegra: clock: Adjust PLL access to avoid a warning tegra: Introduce SRAM repair on tegra124 tegra: Add missing tegra124 peripherals tegra: Increase maximum arguments to 32 tegra: lcd: Tidy up clock init tegra: Allow board-specific init tegra: nyan-big: Add additional clock and kernel init tegra: config: Allow Chrome OS environment settings to be included tegra: Replace 'Norrin' with 'Nyan-big' and fix typo tegra: config: nyan-big: Add options required by Chrome OS boot arch/arm/dts/tegra124-nyan-big.dts| 3 + arch/arm/include/asm/arch-tegra/clock.h | 8 + arch/arm/include/asm/arch-tegra/sys_proto.h | 7 + arch/arm/include/asm/arch-tegra124/clock-tables.h | 12 +- arch/arm/include/asm/arch-tegra124/flow.h | 12 + arch/arm/mach-tegra/clock.c | 24 +- arch/arm/mach-tegra/powergate.c | 20 +- arch/arm/mach-tegra/tegra124/Kconfig | 2 +- arch/arm/mach-tegra/tegra124/clock.c | 2 +- board/nvidia/common/board.c | 8 +- board/nvidia/nyan-big/MAINTAINERS | 2 +- board/nvidia/nyan-big/nyan-big.c | 69 configs/nyan-big_defconfig| 5 + drivers/spi/tegra114_spi.c| 40 +- drivers/video/tegra124/tegra124-lcd.c | 4 +- include/configs/chromeos.h| 457 ++ include/configs/nyan-big.h| 9 + include/configs/tegra-common-post.h | 15 +- include/configs/tegra-common.h| 2 +- 19 files changed, 663 insertions(+), 38 deletions(-) create mode 100644 include/configs/chromeos.h -- 2.2.0.rc0.207.ga3a616c Regards, Simon -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-tegra/master
create mode 100644 drivers/video/tegra124/dp.c create mode 100644 drivers/video/tegra124/sor.c create mode 100644 drivers/video/tegra124/sor.h create mode 100644 drivers/video/tegra124/tegra124-lcd.c create mode 100644 include/displayport.h create mode 100644 include/linux/drm_dp_helper.h On Wed, May 13, 2015 at 9:38 AM, Tom Warren tcwarren3...@gmail.com wrote: Sorry, Masahiro. Missed that one. I'll apply it and send a new PR if everything builds OK. Tom - note that I screwed up and didn't push my rebase of u-boot-tegra/master against u-boot/master (it's still rebased against ARM/master). I'll fix that before the next PR later today, so you can ignore the above PR. Tom On Tue, May 12, 2015 at 6:45 PM, Masahiro Yamada yamada.masah...@socionext.com wrote: Hi Tom Warren, 2015-05-13 6:49 GMT+09:00 Tom Warren tcwarren3...@gmail.com: Tom, Please pull u-boot-tegra/master into u-boot/master. ./MAKEALL -s tegra is clean. Thanks. The following changes since commit b939689c7b87773c44275a578ffc8674a867e39d: Merge branch 'u-boot/master' into 'u-boot-arm/master' (2015-05-05 10:09:06 +0200) are available in the git repository at: git://git.denx.de/u-boot-tegra.git master for you to fetch changes up to 5168604f3b7e5b8ea077a69fe9acb7c14a36adf7: jetson-tk1: Add PSCI configuration options and reserve secure code (2015-05-11 08:35:13 -0700) What about my patch (http://patchwork.ozlabs.org/patch/460596/)? Has it been rejected or deferred? -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-tegra/master
Sorry, Masahiro. Missed that one. I'll apply it and send a new PR if everything builds OK. Tom - note that I screwed up and didn't push my rebase of u-boot-tegra/master against u-boot/master (it's still rebased against ARM/master). I'll fix that before the next PR later today, so you can ignore the above PR. Tom On Tue, May 12, 2015 at 6:45 PM, Masahiro Yamada yamada.masah...@socionext.com wrote: Hi Tom Warren, 2015-05-13 6:49 GMT+09:00 Tom Warren tcwarren3...@gmail.com: Tom, Please pull u-boot-tegra/master into u-boot/master. ./MAKEALL -s tegra is clean. Thanks. The following changes since commit b939689c7b87773c44275a578ffc8674a867e39d: Merge branch 'u-boot/master' into 'u-boot-arm/master' (2015-05-05 10:09:06 +0200) are available in the git repository at: git://git.denx.de/u-boot-tegra.git master for you to fetch changes up to 5168604f3b7e5b8ea077a69fe9acb7c14a36adf7: jetson-tk1: Add PSCI configuration options and reserve secure code (2015-05-11 08:35:13 -0700) What about my patch (http://patchwork.ozlabs.org/patch/460596/)? Has it been rejected or deferred? -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-tegra/master
Tom,
Please pull u-boot-tegra/master into u-boot/master. ./MAKEALL -s tegra is
clean. Thanks.
The following changes since commit b939689c7b87773c44275a578ffc8674a867e39d:
Merge branch 'u-boot/master' into 'u-boot-arm/master' (2015-05-05
10:09:06 +0200)
are available in the git repository at:
git://git.denx.de/u-boot-tegra.git master
for you to fetch changes up to 5168604f3b7e5b8ea077a69fe9acb7c14a36adf7:
jetson-tk1: Add PSCI configuration options and reserve secure code
(2015-05-11 08:35:13 -0700)
Ian Campbell (3):
tegra124: Add more registers to struct mc_ctlr
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0
jetson-tk1: Add PSCI configuration options and reserve secure code
Jan Kiszka (13):
ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditions
sun7i: Remove duplicate call to psci_arch_init
ARM: Factor out common psci_get_cpu_id
ARM: Factor out reusable psci_cpu_off_common
ARM: Factor out reusable psci_cpu_entry
ARM: Factor out reusable psci_get_cpu_stack_top
ARM: Put target PC for PSCI CPU_ON on per-CPU stack
virt-dt: Allow reservation of secure region when in a RAM carveout
tegra: Make tegra_powergate_power_on public
ARM: Add board-specific initialization hook for PSCI
tegra124: Add PSCI support for Tegra124
tegra: Set CNTFRQ for secondary CPUs
tegra: Boot in non-secure mode by default
Simon Glass (26):
dm: core: Sort the uclasses
dm: gpio: Add error handling and a function to claim vector GPIOs
fdt: Add binding decode function for display-timings
tegra: Move the pwm into tegra-common
tegra: pwm: Allow the clock rate to be left as is
tegra: Move checkboard() into the board code
tegra: Add a board ID function
power: Export register access functions from as3722
tegra: Provide a function to allow LCD PMIC setup
tegra: Add support for setting up a as3722 PMIC
tegra: nyan-big: Add LCD PMIC init and board ID
tegra124: dts: Add host1x node to provide display information
tegra: config: Use CONFIG_LCD to detect LCD presence
tegra: clock: Add checking for invalid clock IDs
tegra: clock: Split the clock source code into a separate function
tegra124: clock: Add display clocks and functions
tegra: Move display controller header into common
video: Add drm_dp_helper.h
edid: Add a function to read detailed monitor timings
dm: video: Add a uclass for display port
tegra: dts: nyan-big: Add definitions for eDP display
tegra: video: Support serial output resource (SOR) on tegra124
tegra: video: Add Embedded DisplayPort driver
tegra: video: support eDP displays on Tegra124 devices
tegra: config: nyan-big: Enable LCD
tegra124: video: Add full link training for eDP
Stephen Warren (2):
ARM: tegra: CONFIG_{SYS_, }LOAD{_, }ADDR rationalization
ARM: tegra: enable STDIO deregistration
Thierry Reding (1):
ARM: tegra: Enable SMMU when going non-secure
arch/arm/cpu/armv7/Kconfig |2 +-
arch/arm/cpu/armv7/Makefile|2 +-
arch/arm/cpu/armv7/ls102xa/cpu.c |2 +-
arch/arm/cpu/armv7/psci.S | 121 ++
arch/arm/cpu/armv7/sunxi/psci.S| 112 +-
arch/arm/cpu/armv7/virt-dt.c | 31 +-
arch/arm/cpu/armv7/virt-v7.c | 11 +
arch/arm/cpu/u-boot.lds|2 +-
arch/arm/dts/tegra124-nyan-big.dts | 47 +
arch/arm/dts/tegra124.dtsi | 84 +
arch/arm/include/asm/arch-tegra/clk_rst.h | 15 +-
arch/arm/include/asm/arch-tegra/clock.h| 14 +
.../include/asm/{arch-tegra20 = arch-tegra}/dc.h | 67 +-
arch/arm/include/asm/arch-tegra/powergate.h|1 +
arch/arm/include/asm/arch-tegra/pwm.h | 60 +
arch/arm/include/asm/arch-tegra/sys_proto.h| 19 +-
arch/arm/include/asm/arch-tegra124/clock-tables.h |3 +-
arch/arm/include/asm/arch-tegra124/clock.h | 21 +
arch/arm/include/asm/arch-tegra124/display.h | 58 +
arch/arm/include/asm/arch-tegra124/flow.h |6 +
arch/arm/include/asm/arch-tegra124/mc.h| 37 +-
arch/arm/include/asm/arch-tegra124/pwm.h | 14 +
arch/arm/include/asm/arch-tegra20/display.h|2 +-
arch/arm/include/asm/arch-tegra20/pwm.h| 54 +-
arch/arm/include/asm/armv7.h |5 +-
arch/arm/include/asm/psci.h|1 +
arch/arm/include/asm/system.h |1 +
arch/arm/lib/bootm-fdt.c |8 +-
arch/arm/lib/bootm.c |6 +-
arch/arm/mach-tegra/Makefile |5 +
Re: [U-Boot] [PATCH v7 00/17] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix
Sorry, Jan. Too many unmaskable interrupts lately ;). I'll take a look today - if it applies OK to u-boot-tegra/master and builds OK, I'll try to get a PR out to Tom/Albert first thing next week. Tom -Original Message- From: Jan Kiszka [mailto:jan.kis...@siemens.com] Sent: Thursday, May 07, 2015 11:01 PM To: U-Boot Mailing List; Tom Rini Cc: Marc Zyngier; Steve Rae; Andre Przywara; Tom Warren; Paul Walmsley; Ian Campbell; Thierry Reding; York Sun Subject: Re: [PATCH v7 00/17] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix On 2015-04-21 07:18, Jan Kiszka wrote: Changes in v7: - rebased over master - fixed issue that prevented secure boot with all cores = replace ap_pm_init with psci_board_init hook - enable CONFIG_ARMV7_BOOT_SEC_DEFAULT for tegra to avoid problems with default config of current Linux - add cleanup patch for CONFIG_ARMV7_NONSEC/VIRT/PSCI Note that I've removed reviewed and tested tags from modified patches. Tom, there were only trivial remarks regarding this series, and it still applies on master. Do you plan to merge it? Or should I resend, addressing them? Jan -- Siemens AG, Corporate Technology, CT RTC ITP SES-DE Corporate Competence Center Embedded Linux --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 24/24] tegra124: Expand SPL space by 8KB
LGTM, but it s/b 'Add a _little_ more space' in the commit msg. Should we change the TEXT_BASE for the CPU portion in all Tegra builds? -Original Message- From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass Sent: Tuesday, May 05, 2015 9:04 AM To: U-Boot Mailing List Cc: Simon Glass; Heiko Schocher; Tom Rini; Tom Warren Subject: Re: [PATCH 24/24] tegra124: Expand SPL space by 8KB +Tom Warren On 4 May 2015 at 11:31, Simon Glass s...@chromium.org wrote: We are getting very close to running out of space in SPL, and with the currently Chrome OS gcc 4.9 we exceed the limit. Add a litle more space. Signed-off-by: Simon Glass s...@chromium.org --- include/configs/tegra124-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index f2b3774..0347132 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -30,7 +30,7 @@ /*--- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x8010E000 +#define CONFIG_SYS_TEXT_BASE 0x8011 /* * Memory layout for where various images get loaded by boot scripts: -- 2.2.0.rc0.207.ga3a616c --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 0/26] tegra: Add eDP support for nyan-big
I had a problem with the first patch in the V6 patchset (uclass-id.h sorted
list), but after I fixed that it all applied to u-boot-tegra/master OK. Just
need to find time to test it on my Nyan, unless someone else can say that
they've done that and it's good-to-go.
Tom
-Original Message-
From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
Sent: Monday, April 27, 2015 8:03 PM
To: U-Boot Mailing List
Cc: Jimmy Zhang; Tom Warren; Stephen Warren; Simon Glass; Stephen
Warren; Marek Vasut; Pavel Herrmann; Lukasz Majewski; Jerry Van Baren;
Anatolij Gustschin
Subject: Re: [PATCH v6 0/26] tegra: Add eDP support for nyan-big
Hi Tom, Jimmy,
On 14 April 2015 at 21:03, Simon Glass s...@chromium.org wrote:
This series adds eDP support for nyan-big so that the display works.
Nyan-big is based on tegra124.
Some support is added for new clocks to make this work. The
drm_dp_helper.h file is brought in from Linux since many of the
DisplayPort constants are generic. A very simple uclass is added for
DisplayPort, and the Tegra driver makes use of that. The U-Boot EDID
support is enhanced to read some additional information (detailed
timings).
There is existing video support for Tegra20, but I don't think it
works for
Tegra30/114 (is this correct?). This series relies on detecting the
display at run-time as I cannot find a good device tree binding for
things like display depth. But if we could resolve that then it might
be possible to move Tegra20 over to use the same driver, etc. There is
clearly a lot in common with the display controllers - I have
exploited this with the header file but not with the C file.
HDMI is not supported at present. If this is easy and there is an
existing driver to follow along with then I might be able to incorporate it
later.
This series is available at u-boot-dm/nyan-working
Any comments on this new version please?
Changes in v6:
- Add a comment about tegra_dc_dp_check_sink()
- Add more debug() statements
- Add new patch to sort the uclasses
- Fix incorrect use of DP_MAIN_LINK_CHANNEL_CODING_SET register
- Improve retry logic in tegra_dc_dp_check_sink()
- Report failure when we cannot init the eDP display
Changes in v4:
- Rebase on u-boot-dm/next since this series is still pending
Changes in v3:
- Add full link training support
- Change parameters of update_display_mode()
- Fix 64-bit maths error
- Fix trainging typo
- Reorder parameters to tegra_dc_sor_attach()
- Set scramble_ena to 1 on start-up so that link training succeeds
- Simplify timouts to remove repeated multiplication by 1000
- Use real error return values in tegra_dc_dpaux_write_chunk() and
others
- Use sor pointer in struct tegra_dp_priv
Changes in v2:
- Rebase on top of u-boot-dm
- Remove definition of BIT()
Simon Glass (26):
dm: core: Sort the uclasses
dm: gpio: Add error handling and a function to claim vector GPIOs
fdt: Add binding decode function for display-timings
tegra: Move the pwm into tegra-common
tegra: pwm: Allow the clock rate to be left as is
tegra: Move checkboard() into the board code
tegra: Add a board ID function
power: Export register access functions from as3722
tegra: Provide a function to allow LCD PMIC setup
tegra: Add support for setting up a as3722 PMIC
tegra: nyan-big: Add LCD PMIC init and board ID
tegra124: dts: Add host1x node to provide display information
tegra: config: Use CONFIG_LCD to detect LCD presence
tegra: clock: Add checking for invalid clock IDs
tegra: clock: Split the clock source code into a separate function
tegra124: clock: Add display clocks and functions
tegra: Move display controller header into common
video: Add drm_dp_helper.h
edid: Add a function to read detailed monitor timings
dm: video: Add a uclass for display port
tegra: dts: nyan-big: Add definitions for eDP display
tegra: video: Support serial output resource (SOR) on tegra124
tegra: video: Add Embedded DisplayPort driver
tegra: video: support eDP displays on Tegra124 devices
tegra: config: nyan-big: Enable LCD
tegra124: video: Add full link training for eDP
arch/arm/dts/tegra124-nyan-big.dts | 47 +
arch/arm/dts/tegra124.dtsi | 84 +
arch/arm/include/asm/arch-tegra/clk_rst.h | 15 +-
arch/arm/include/asm/arch-tegra/clock.h| 14 +
.../include/asm/{arch-tegra20 = arch-tegra}/dc.h | 67 +-
arch/arm/include/asm/arch-tegra/pwm.h | 60 +
arch/arm/include/asm/arch-tegra/sys_proto.h| 19 +-
arch/arm/include/asm/arch-tegra124/clock-tables.h |3 +-
arch/arm/include/asm/arch-tegra124/clock.h | 21 +
arch/arm/include/asm/arch-tegra124/display.h | 58 +
arch/arm/include/asm/arch-tegra124/pwm.h | 14 +
arch/arm/include/asm
Re: [U-Boot] [PATCH v2 0/2] rename colibri_t20
Marcel, This series applied to u-boot-tegra/next. I'll push an update today or tomorrow to Denx.de. Tom -Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Thursday, March 26, 2015 7:15 AM To: Marcel Ziswiler Cc: u-boot@lists.denx.de; Marek Vasut; Akshay Saraswat; Fabio Estevam; Tom Rini; Pavel Machek; Michal Simek; Masahiro Yamada; Tom Warren; Hyungwon Hwang; Stephen Warren; Stefan Roese Subject: Re: [U-Boot] [PATCH v2 0/2] rename colibri_t20 On 03/25/2015 06:31 PM, Marcel Ziswiler wrote: In accordance with our other modules supported by U-Boot and as agreed upon for Apalis/Colibri T30 [1] get rid of the carrier board post fix in the board/configuration/device-tree naming. [1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/192041 The series, Acked-by: Stephen Warren swar...@nvidia.com --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/2] ARM: tegra: pinmux/colibri_t20: fix nand pinmux
Marcel, This series applied to u-boot-tegra/next. I'll push an update today or tomorrow to Denx.de. Tom -Original Message- From: Marcel Ziswiler [mailto:mar...@ziswiler.com] Sent: Thursday, March 26, 2015 5:32 PM To: u-boot@lists.denx.de Cc: Tom Warren; Albert Aribaud; Tom Rini; Lucas Stach; Stephen Warren; Simon Glass; Masahiro Yamada; Marcel Ziswiler Subject: [PATCH v2 0/2] ARM: tegra: pinmux/colibri_t20: fix nand pinmux Fix FUNCMUX_NDFLASH_KBC_8_BIT and pingroup ATC clashing. Please note that the first patch has already been submitted once but based on feedback from Stephen I now split it up into a generic fix part plus a board specific ATC pingroup clashing workaround. That's why I call this series already v2 to avoid any confusion. Lucas Stach (1): tegra: pinmux: fix FUNCMUX_NDFLASH_KBC_8_BIT Marcel Ziswiler (1): ARM: tegra: colibri_t20: fix nand pinmux arch/arm/mach-tegra/tegra20/funcmux.c | 2 ++ board/toradex/colibri_t20/colibri_t20.c | 6 ++ 2 files changed, 8 insertions(+) -- 1.9.3 --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] tegra: seaboard: Remove unused CONFIG_UART_DISABLE_GPIO
If you want to rework them against current u-boot-tegra/master and resend, I'll apply them, and maybe get a chance later this week to test them on my Nyan. Thanks. -Original Message- From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass Sent: Monday, March 30, 2015 10:15 AM To: Tom Warren Cc: Stephen Warren; U-Boot Mailing List; Stephen Warren Subject: Re: [PATCH 1/2] tegra: seaboard: Remove unused CONFIG_UART_DISABLE_GPIO Hi Tom, On 30 March 2015 at 11:02, Tom Warren twar...@nvidia.com wrote: Simon, This series applied to u-boot-tegra/next locally. I've got to look at some patches from Marcel to see if they've been ACK'd. Once I've collected any other pending patches, I'll push a new /next to Denx. Thanks - also what do you think about applying the Nyan display patches? They work fine on my board, but apparently they are not perfect. Still it might be better than letting them sit. I can rebase and resend. Regards, Simon Tom -Original Message- From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass Sent: Sunday, March 29, 2015 6:10 AM To: Stephen Warren Cc: U-Boot Mailing List; Tom Warren; Stephen Warren Subject: Re: [PATCH 1/2] tegra: seaboard: Remove unused CONFIG_UART_DISABLE_GPIO Hi Tom, On 9 March 2015 at 20:49, Stephen Warren swar...@wwwdotorg.org wrote: On 03/09/2015 07:12 PM, Simon Glass wrote: This CONFIG is not used, so drop it. The series, Tested-by: Stephen Warren swar...@wwwdotorg.org Acked-by: Stephen Warren swar...@wwwdotorg.org Can you please apply this fix? Regards, Simon -- - This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. -- - ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] ARM: tegra: pinctrl: move Tegra210 code to the correct dir
Stephen,
Applied this series to u-boot-tegra/next. I'm still working on some of Simon's
and Marcel's latest patches; when I'm done I'll push a new /next to Denx.
Tom
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Wednesday, March 25, 2015 11:05 AM
To: u-boot@lists.denx.de; Simon Glass; Tom Warren; Stephen Warren
Subject: [PATCH 1/4] ARM: tegra: pinctrl: move Tegra210 code to the correct
dir
From: Stephen Warren swar...@nvidia.com
Patches that added the Tegra210 pinctrl driver and renamed directories
arch/arm/cpu/tegra{$soc}-common - arch/arm/mach-tegra/tegra-${soc}
crossed. Move the Tegra210 pinctrl driver to the correct location. This wasn't
detected since Tegra210 support is in the process of being added, and isn't
buildable yet.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
This series mainly adds support for configuring the MIPI pad control
registers,
along with a few fixes/cleanups first. I'll enhance the Jetson TK1 pinmux
header to actually include MIPI pad control settings as soon as I've cleared
up
one other change in the latest spreadsheet.
---
arch/arm/{cpu/tegra210-common = mach-tegra/tegra210}/pinmux.c | 0
1 file changed, 0 insertions(+), 0 deletions(-) rename
arch/arm/{cpu/tegra210-common = mach-tegra/tegra210}/pinmux.c (100%)
diff --git a/arch/arm/cpu/tegra210-common/pinmux.c b/arch/arm/mach-
tegra/tegra210/pinmux.c
similarity index 100%
rename from arch/arm/cpu/tegra210-common/pinmux.c
rename to arch/arm/mach-tegra/tegra210/pinmux.c
--
1.9.1
---
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Re: [U-Boot] [PATCH 1/2] tegra: seaboard: Remove unused CONFIG_UART_DISABLE_GPIO
Simon, This series applied to u-boot-tegra/next locally. I've got to look at some patches from Marcel to see if they've been ACK'd. Once I've collected any other pending patches, I'll push a new /next to Denx. Tom -Original Message- From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass Sent: Sunday, March 29, 2015 6:10 AM To: Stephen Warren Cc: U-Boot Mailing List; Tom Warren; Stephen Warren Subject: Re: [PATCH 1/2] tegra: seaboard: Remove unused CONFIG_UART_DISABLE_GPIO Hi Tom, On 9 March 2015 at 20:49, Stephen Warren swar...@wwwdotorg.org wrote: On 03/09/2015 07:12 PM, Simon Glass wrote: This CONFIG is not used, so drop it. The series, Tested-by: Stephen Warren swar...@wwwdotorg.org Acked-by: Stephen Warren swar...@wwwdotorg.org Can you please apply this fix? Regards, Simon --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 00/14] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix
I'd asked Stephen Warren (who asked Thierry Reding) to look at these as they were more expert in PSCI than I, and I'm currently swamped w/another bringup. I don't want to ACK something I'm not sure about, so I have to defer to Stephen or Thierry. Thierry - please try and give this some attention. Thanks. Tom -Original Message- From: Jan Kiszka [mailto:jan.kis...@siemens.com] Sent: Tuesday, March 17, 2015 11:40 PM To: Tom Warren; Ian Campbell; Hans de Goede; Albert Aribaud Cc: Tom Rini; U-Boot Mailing List; Marc Zyngier; Paul Walmsley; Thierry Reding Subject: Re: [U-Boot] [PATCH v5 00/14] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix On 2015-03-11 16:11, Tom Rini wrote: On Mon, Mar 09, 2015 at 08:00:10AM +0100, Jan Kiszka wrote: Changes in v4: - rebased over master - implemented psci_get_cpu_id as weak function - implemented psci_disable/enable_smp as weak functions - adjusted register interface of psci_get_cpu_stack_top This version (+ the non-cached memory init fix) can also be found at https://github.com/siemens/u-boot/tree/jetson-tk1-v5. So, I don't know where exactly this should come in. Hans or Ian, if you can ack the sunxi changes (I saw you tested it Ian, thanks!) and Tom W., if you can ack the Tegra parts, I can take this in or Albert, do you want to chime in too since this is kinda core ARM stuff too? Thanks everyone! Ping... Jan -- Siemens AG, Corporate Technology, CT RTC ITP SES-DE Corporate Competence Center Embedded Linux --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-tegra.git/master
THanks, Tom. -Original Message- From: Tom Rini [mailto:tr...@konsulko.com] Sent: Tuesday, March 10, 2015 5:56 PM To: Tom Warren Cc: Tom Warren; Albert ARIBAUD; u-boot@lists.denx.de; Stephen Warren; Marcel Ziswiler Subject: Re: [U-Boot] Please pull u-boot-tegra.git/master * PGP Signed by an unknown key On Tue, Mar 10, 2015 at 10:25:03PM +, Tom Warren wrote: Albert – are you getting these emails? I know they’re bouncing from the list (need to find a mailer that doesn’t use MIME64), but I haven’t heard back from you for the last 2 PRs. FWIW, you can make git send-email do the sending of the PR and that may help. Esp since it looks like you already have gmail setup to know your work email (if not it's an easy enough thing to make it send from it, I did it back at TI even). Should I send these to Tom Rini instead? Please let me know. Yeah, I'm doing ARM SoC PRs now. Tom From: Tom Warren [mailto:tomcwarren3...@gmail.com] Sent: Thursday, March 05, 2015 4:27 PM To: Albert ARIBAUD Cc: u-boot@lists.denx.de; Marcel Ziswiler; Stephen Warren; Tom Warren Subject: Please pull u-boot-tegra.git/master Albert, Please pull u-boot-tegra.git/master into ARM master. ./MAKEALL -s tegra is clean. Stephen confirmed that Jetson-TK1 looks OK. NOTE: This PR includes some of Stephen's patches from a previous PR that never went in AFAICT (Sent Feb 3rd). I'm sending this from my Gmail account since my work Outlook always bounces from the list due to base64 MIME errors. The following changes since commit 02251eefc95c477f4ff6aa7568dfd4be7c69c31f: ARM: HYP/non-sec: relocation before enable secondary cores (2015-03-01 16:33:21 +0100) are available in the git repository at: git://git.denx.de/u-boot-tegra.githttp://git.denx.de/u-boot-tegra.git master for you to fetch changes up to d5338c693e6a35a7108c184839d688a7377d117c: apalis/colibri_t30: add misc cmds increase buf sizes and max args (2015-03-04 10:09:02 -0700) Applied to u-boot/master, thanks! -- Tom * Unknown Key * 0x56D6FECD --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-tegra.git/master
Thanks, Tom. Should I send future PRs to you instead of Albert? On Mar 10, 2015 5:55 PM, Tom Rini tr...@konsulko.com wrote: On Tue, Mar 10, 2015 at 10:25:03PM +, Tom Warren wrote: Albert – are you getting these emails? I know they’re bouncing from the list (need to find a mailer that doesn’t use MIME64), but I haven’t heard back from you for the last 2 PRs. FWIW, you can make git send-email do the sending of the PR and that may help. Esp since it looks like you already have gmail setup to know your work email (if not it's an easy enough thing to make it send from it, I did it back at TI even). Should I send these to Tom Rini instead? Please let me know. Yeah, I'm doing ARM SoC PRs now. Tom From: Tom Warren [mailto:tomcwarren3...@gmail.com] Sent: Thursday, March 05, 2015 4:27 PM To: Albert ARIBAUD Cc: u-boot@lists.denx.de; Marcel Ziswiler; Stephen Warren; Tom Warren Subject: Please pull u-boot-tegra.git/master Albert, Please pull u-boot-tegra.git/master into ARM master. ./MAKEALL -s tegra is clean. Stephen confirmed that Jetson-TK1 looks OK. NOTE: This PR includes some of Stephen's patches from a previous PR that never went in AFAICT (Sent Feb 3rd). I'm sending this from my Gmail account since my work Outlook always bounces from the list due to base64 MIME errors. The following changes since commit 02251eefc95c477f4ff6aa7568dfd4be7c69c31f: ARM: HYP/non-sec: relocation before enable secondary cores (2015-03-01 16:33:21 +0100) are available in the git repository at: git://git.denx.de/u-boot-tegra.githttp://git.denx.de/u-boot-tegra.git master for you to fetch changes up to d5338c693e6a35a7108c184839d688a7377d117c: apalis/colibri_t30: add misc cmds increase buf sizes and max args (2015-03-04 10:09:02 -0700) Applied to u-boot/master, thanks! -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-tegra.git/master
Albert – are you getting these emails? I know they’re bouncing from the list (need to find a mailer that doesn’t use MIME64), but I haven’t heard back from you for the last 2 PRs. Should I send these to Tom Rini instead? Please let me know. Tom From: Tom Warren [mailto:tomcwarren3...@gmail.com] Sent: Thursday, March 05, 2015 4:27 PM To: Albert ARIBAUD Cc: u-boot@lists.denx.de; Marcel Ziswiler; Stephen Warren; Tom Warren Subject: Please pull u-boot-tegra.git/master Albert, Please pull u-boot-tegra.git/master into ARM master. ./MAKEALL -s tegra is clean. Stephen confirmed that Jetson-TK1 looks OK. NOTE: This PR includes some of Stephen's patches from a previous PR that never went in AFAICT (Sent Feb 3rd). I'm sending this from my Gmail account since my work Outlook always bounces from the list due to base64 MIME errors. The following changes since commit 02251eefc95c477f4ff6aa7568dfd4be7c69c31f: ARM: HYP/non-sec: relocation before enable secondary cores (2015-03-01 16:33:21 +0100) are available in the git repository at: git://git.denx.de/u-boot-tegra.githttp://git.denx.de/u-boot-tegra.git master for you to fetch changes up to d5338c693e6a35a7108c184839d688a7377d117c: apalis/colibri_t30: add misc cmds increase buf sizes and max args (2015-03-04 10:09:02 -0700) Marcel Ziswiler (4): dm: tegra: dts: add aliases for spi on apalis_t30 apalis/colibri_t30: fix MMC/SD card detect GPIOs apalis_t30: enable gigabit ethernet via pcie apalis/colibri_t30: add misc cmds increase buf sizes and max args Stephen Warren (16): common: board: support systems with where RAM ends beyond 4GB ARM: tegra: fix variable naming in query_sdram_size() ARM: tegra: support large RAM sizes ARM: tegra: move common config defines centrally ARM: tegra: support running in non-secure mode ARM: tegra: add function to clear pinmux CLAMPING bit ARM: tegra: import latest Jetson TK1 pinmux ARM: tegra: pinmux: add note re: drive group field defines ARM: tegra: pinmux: simplify some defines ARM: tegra: pinmux: handle feature removal on newer SoCs ARM: tegra: pinmux: move some type definitions ARM: tegra: pinmux: partially handle varying register layouts ARM: tegra: pinmux: support hsm/schmitt on pins ARM: tegra: pinmux: account for different drivegroup base registers ARM: tegra: pinmux: support Tegra210's e_io_hv pin option ARM: tegra: pinmux: add Tegra210 support README | 7 + arch/arm/cpu/tegra210-common/pinmux.c | 195 ++ arch/arm/dts/tegra30-apalis.dts| 13 +- arch/arm/dts/tegra30-colibri.dts | 4 +- arch/arm/include/asm/arch-tegra/ap.h | 4 + arch/arm/include/asm/arch-tegra/pinmux.h | 110 -- arch/arm/include/asm/arch-tegra114/pinmux.h| 14 +- arch/arm/include/asm/arch-tegra124/pinmux.h| 14 +- arch/arm/include/asm/arch-tegra20/pinmux.h | 1 + arch/arm/include/asm/arch-tegra210/pinmux.h| 416 + arch/arm/include/asm/arch-tegra30/pinmux.h | 11 +- arch/arm/mach-tegra/board.c| 56 ++- arch/arm/mach-tegra/clock.c| 6 +- arch/arm/mach-tegra/pinmux-common.c| 223 +-- board/nvidia/common/board.c| 9 + board/nvidia/jetson-tk1/jetson-tk1.c | 2 +- board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h | 303 +++ common/board_f.c | 12 + include/configs/apalis_t30.h | 31 +- include/configs/beaver.h | 2 - include/configs/cardhu.h | 2 - include/configs/colibri_t20_iris.h | 2 - include/configs/colibri_t30.h | 26 +- include/configs/dalmore.h | 2 - include/configs/harmony.h | 3 - include/configs/jetson-tk1.h | 2 - include/configs/medcom-wide.h | 3 - include/configs/nyan-big.h | 2 - include/configs/paz00.h| 3 - include/configs/plutux.h | 3 - include/configs/seaboard.h | 3 - include/configs/tec-ng.h | 2 - include/configs/tec.h | 3 - include/configs/tegra-common.h | 2 + include/configs/trimslice.h| 2 - include/configs/venice2.h | 2 - include/configs/ventana.h | 3 - include/configs/whistler.h | 2 - 38 files changed, 1197 insertions(+), 303 deletions(-) create mode 100644
Re: [U-Boot] [PATCH 0/9] ARM: tegra: pinmux: Tegra210 support
I'm using this locally, so I'll apply it and push a new u-boot-tegra/next. -Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Tuesday, March 03, 2015 1:20 PM To: Tom Warren Cc: u-boot@lists.denx.de; Simon Glass; Stephen Warren Subject: Re: [U-Boot] [PATCH 0/9] ARM: tegra: pinmux: Tegra210 support On 02/24/2015 02:08 PM, Stephen Warren wrote: This series performs a few small cleanups to or parameterizations of the existing Tegra pinmux driver, and adds Tegra210 support. The Tegra210 code isn't actually used yet, since the balance of the Tegra210 support is not yet present. However, it should start appearing soon. I've at least compile-tested this by over-writing the Tegra124 pinmux driver and Jetson TK1 board pinmux data tables with the Tegra210 versions. TomW, note I made a couple minor tweaks since the latest version I sent internally; let's apply this version upstream. Tom, Are you waiting for anything before applying this series? --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 2/2] ARM: tegra: import latest Jetson TK1 pinmux
I've been side-tracked with other work. Let me take another look, if it's all gravy I'll apply them to u-boot-tegra/next. -Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Tuesday, March 03, 2015 1:19 PM To: Tom Warren Cc: u-boot@lists.denx.de; Simon Glass; Stephen Warren Subject: Re: [U-Boot] [PATCH V2 2/2] ARM: tegra: import latest Jetson TK1 pinmux On 02/18/2015 01:27 PM, Stephen Warren wrote: From: Stephen Warren swar...@nvidia.com Syseng has revamped the Jetson TK1 pinmux spreadsheet, basing the content completely on correct configuration for the board/schematic, rather than the previous version which was based on the bare minimum changes relative to another reference board. The new spreadsheet sets TRISTATE for any input-only pins. This only works correctly if the global CLAMP bit is not set, so the Jetson TK1 board code has been adjusted accordingly. Apparently syseng have changed their mind since the previous advice that this needed to be set:-/ This content comes from Jetson_TK1_customer_pinmux.xlsm (v09) downloaded from https://developer.nvidia.com/hardware-design-and- development. Tom, do these two patches look OK? --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] common: board: support systems with where RAM ends beyond 4GB
Sorry, missed this. Yes, looks good to me. I can apply it to u-boot-tegra/master, or TomR can take it in to master U-Boot directly. Tom -Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Monday, January 19, 2015 3:57 PM To: u-boot@lists.denx.de; Simon Glass; Tom Warren; Stephen Warren Cc: Tom Rini Subject: Re: [U-Boot] [PATCH 1/3] common: board: support systems with where RAM ends beyond 4GB On 12/23/2014 10:34 AM, Stephen Warren wrote: From: Stephen Warren swar...@nvidia.com Some systems have so much RAM that the end of RAM is beyond 4GB. An example would be a Tegra124 system (where RAM starts at 2GB physical) that has more than 2GB of RAM. In this case, we can gd-ram_size to represent the actual RAM size, so that the actual RAM size is passed to the OS. This is useful if the OS implements LPAE, and can actually use the extra RAM. However, U-Boot does not implement LPAE and so must deal with 32-bit physical addresses. To this end, we enhance board_get_usable_ram_top() to detect the over-sized case, and limit the relocation addres so that it fits into 32-bits of physical address space. TomW, TomR, does this series look good? --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] common: board: support systems with where RAM ends beyond 4GB
I've merged that patch series w/u-boot-tegra/next and /master, done a MAKEALL -s tegra, and rebased against ARM /master and pushed to denx.de. Stephen - please test and if it looks OK, I'll prepare a PR. -Original Message- From: Tom Warren Sent: Tuesday, January 20, 2015 8:28 AM To: 'Stephen Warren'; u-boot@lists.denx.de; Simon Glass; Stephen Warren Cc: Tom Rini Subject: RE: [U-Boot] [PATCH 1/3] common: board: support systems with where RAM ends beyond 4GB Sorry, missed this. Yes, looks good to me. I can apply it to u-boot- tegra/master, or TomR can take it in to master U-Boot directly. Tom -Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Monday, January 19, 2015 3:57 PM To: u-boot@lists.denx.de; Simon Glass; Tom Warren; Stephen Warren Cc: Tom Rini Subject: Re: [U-Boot] [PATCH 1/3] common: board: support systems with where RAM ends beyond 4GB On 12/23/2014 10:34 AM, Stephen Warren wrote: From: Stephen Warren swar...@nvidia.com Some systems have so much RAM that the end of RAM is beyond 4GB. An example would be a Tegra124 system (where RAM starts at 2GB physical) that has more than 2GB of RAM. In this case, we can gd-ram_size to represent the actual RAM size, so that the actual RAM size is passed to the OS. This is useful if the OS implements LPAE, and can actually use the extra RAM. However, U-Boot does not implement LPAE and so must deal with 32-bit physical addresses. To this end, we enhance board_get_usable_ram_top() to detect the over-sized case, and limit the relocation addres so that it fits into 32-bits of physical address space. TomW, TomR, does this series look good? --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-tegra/master into ARM/master
MAKEALL -s tegra is error/warning-free. The following changes since commit 3d420cbd355a5f09e4f113eb10579a264a8ef138: Merge branch 'u-boot-socfpga/topic/arm/socfpga-20141010' into 'u-boot-arm/master' (2014-10-11 01:20:55 +0200) are available in the git repository at: git://git.denx.de/u-boot-tegra.git master for you to fetch changes up to 9aafef4f360616a507578b8868092f096b093aa9: tegra: apalis_t30: master revamp (2014-10-22 09:30:55 -0700) Marcel Ziswiler (11): arm: tegra: initial support for apalis t30 arm: tegra: use architecture specific memcpy mmc: Tegra: Fix timeout issue seen on certain eMMC parts tegra: gpio: fix null label regression tegra: colibri_t30: asix usb ethernet reset regression gpio: header file comment spelling fixes tegra: clean-up useless define ARM: tegra: Use mem size from MC in combination with get_ram_size() tegra: colibri_t30: clean-up spurious new line tegra: dts: colibri_t30 add serial port details tegra: apalis_t30: master revamp Stephen Warren (1): ARM: tegra: add PCIe-related pins to the Jetson TK1 pinmux tables arch/arm/cpu/armv7/tegra30/Kconfig | 4 + arch/arm/cpu/tegra-common/board.c | 64 +--- arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra30-apalis.dts| 304 ++ arch/arm/dts/tegra30-colibri.dts | 4 + arch/arm/include/asm/arch-tegra114/mc.h| 37 +++ arch/arm/include/asm/arch-tegra114/tegra.h | 1 + arch/arm/include/asm/arch-tegra20/mc.h | 36 +++ arch/arm/include/asm/arch-tegra20/tegra.h | 1 + arch/arm/include/asm/arch-tegra30/mc.h | 38 +++ arch/arm/include/asm/arch-tegra30/tegra.h | 1 + arch/arm/include/asm/mach-types.h | 13 + board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h | 5 + board/toradex/apalis_t30/Kconfig | 12 + board/toradex/apalis_t30/MAINTAINERS | 7 + board/toradex/apalis_t30/Makefile | 6 + board/toradex/apalis_t30/apalis_t30.c | 92 ++ .../toradex/apalis_t30/pinmux-config-apalis_t30.h | 347 + board/toradex/colibri_t30/colibri_t30.c| 2 +- configs/apalis_t30_defconfig | 5 + drivers/gpio/tegra_gpio.c | 3 + drivers/mmc/tegra_mmc.c| 2 +- include/asm-generic/gpio.h | 10 +- include/configs/apalis_t30.h | 75 + include/configs/colibri_t30.h | 1 - include/configs/tegra-common-post.h| 4 - include/configs/tegra-common.h | 2 + 27 files changed, 1014 insertions(+), 63 deletions(-) create mode 100644 arch/arm/dts/tegra30-apalis.dts create mode 100644 arch/arm/include/asm/arch-tegra114/mc.h create mode 100644 arch/arm/include/asm/arch-tegra20/mc.h create mode 100644 arch/arm/include/asm/arch-tegra30/mc.h create mode 100644 board/toradex/apalis_t30/Kconfig create mode 100644 board/toradex/apalis_t30/MAINTAINERS create mode 100644 board/toradex/apalis_t30/Makefile create mode 100644 board/toradex/apalis_t30/apalis_t30.c create mode 100644 board/toradex/apalis_t30/pinmux-config-apalis_t30.h create mode 100644 configs/apalis_t30_defconfig create mode 100644 include/configs/apalis_t30.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: tegra: add PCIe-related pins to the Jetson TK1 pinmux tables
Albert, I did a Makeall -s tegra before sending the PR (as I always do), and I saw no failures. But I haven't rebased against ARM master in a few weeks. I think the Jetson TK1 change is still valid and should go in. Thanks, Tom -Original Message- From: Albert ARIBAUD [mailto:albert.u.b...@aribaud.net] Sent: Wednesday, October 15, 2014 8:40 AM To: Stephen Warren Cc: Tom Warren; u-boot@lists.denx.de; Simon Glass; Tom Rini; Stephen Warren; Thierry Reding Subject: Re: [U-Boot] [PATCH] ARM: tegra: add PCIe-related pins to the Jetson TK1 pinmux tables Hi Stephen, On Wed, 15 Oct 2014 09:34:49 -0600, Stephen Warren swar...@wwwdotorg.org wrote: On 10/15/2014 05:43 AM, Albert ARIBAUD wrote: Hi Tom, On Tue, 14 Oct 2014 23:14:24 +, Tom Warren twar...@nvidia.com wrote: Albert, Please pull u-boot-tegra/master into ARM/master. Thanks! The following changes since commit a7f99bf139b3aaa0d5494693fd0395084355e41a: arm: Fix _start for CONFIG_SYS_DV_NOR_BOOT_CFG (2014-09-11 18:04:39 +0200) are available in the git repository at: git://git.denx.de/u-boot-tegra.git master for you to fetch changes up to 90a565acf3a18c61170ec0e0b2046c98cb7ecc85: arm: tegra: initial support for apalis t30 (2014-09-17 11:15:04 -0700) Marcel Ziswiler (1): arm: tegra: initial support for apalis t30 Stephen Warren (1): ARM: tegra: add PCIe-related pins to the Jetson TK1 pinmux tables This new board fails when I merge this branch to u-boot-arm/master, with the following diagnostics: include/configs/apalis_t30.h:17:0: warning: CONFIG_OF_SEPARATE redefined [enabled by default] In file included from /home/albert.u.boot/src/u-boot-arm/include/linux/kconfig.h:4:0, from command-line:0: include/generated/autoconf.h:8:0: note: this is the location of the previous definition (actually, there is a lot of these, for various config options) Device Tree Source is not correctly specified. Please define 'CONFIG_DEFAULT_DEVICE_TREE' or build with 'DEVICE_TREE=device_tree' argument (This one is fatal even though it does not explicitly state error:) This failure does not happen on the tegra branch; it is obviously due to the Kbuild stuff. This issue should be fixed by: https://patchwork.ozlabs.org/patch/398793/ [U-Boot] tegra: apalis_t30: master revamp However, I would assert that at this point during the release cycle, we probably shouldn't be adding new boards/features, but just fixing bugs. Perhaps we should drop the Apalis patch completely and re-apply it once the release is out? Ok. Should I still apply the TK1 pinmux patch, or should I consider the whole PR to be for -next? Amicalement, -- Albert. --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: tegra: add PCIe-related pins to the Jetson TK1 pinmux tables
My gmail account has been in flux for a few weeks, so I can't say for sure whether I sent a PR or not. I'll resend one today to Albert. Tom -Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Tuesday, October 14, 2014 8:25 AM To: Tom Warren; Tom Rini; albert.u.b...@aribaud.net Cc: u-boot@lists.denx.de; Simon Glass; Stephen Warren; Thierry Reding Subject: Re: [U-Boot] [PATCH] ARM: tegra: add PCIe-related pins to the Jetson TK1 pinmux tables On 09/17/2014 10:16 AM, Stephen Warren wrote: On 08/22/2014 03:04 PM, Stephen Warren wrote: From: Stephen Warren swar...@nvidia.com This pinmux tables currently omit any configuration for PCIe clk_req, wake, and rst pins, which in turn causes intermittent failures in U-Boot's PCIe support. Import an updated version of the pinmux tables which rectifies this. Signed-off-by: Stephen Warren swar...@nvidia.com Could this please make it into the imminent v2014.10 release? I see this in u-boot-tegra/master, but it doesn't seem to be in u-boot- arm/master or u-boot/master. Did a pull request get sent for this commit? I'd really like to see this bugfix get applied to the main U-Boot repo ASAP... --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
