[PATCH] board: freescale: Update MAINTAINERS List
From: Wasim Khan Update MAINTAINERS List for LS2088ARDB and LS2088AQDS platforms Signed-off-by: Wasim Khan --- board/freescale/ls2080aqds/MAINTAINERS | 1 + board/freescale/ls2080ardb/MAINTAINERS | 2 ++ 2 files changed, 3 insertions(+) diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS index 84735dce28..39d02ae3f4 100644 --- a/board/freescale/ls2080aqds/MAINTAINERS +++ b/board/freescale/ls2080aqds/MAINTAINERS @@ -1,6 +1,7 @@ LS2080A BOARD M: Priyanka Jain M: Rajesh Bhagat +M: Wasim Khan S: Maintained F: board/freescale/ls2080aqds/ F: board/freescale/ls2080a/ls2080aqds.c diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS index 6e25b82db5..f49d26af3a 100644 --- a/board/freescale/ls2080ardb/MAINTAINERS +++ b/board/freescale/ls2080ardb/MAINTAINERS @@ -1,5 +1,6 @@ LS2080A BOARD M: Priyanka Jain +M: Wasim Khan S: Maintained F: board/freescale/ls2080ardb/ F: board/freescale/ls2080a/ls2080ardb.c @@ -10,6 +11,7 @@ F:configs/ls2080ardb_nand_defconfig LS2088A_QSPI-boot BOARD M: Priyanka Jain M: Rajesh Bhagat +M: Wasim Khan S: Maintained F: configs/ls2088ardb_qspi_defconfig F: configs/ls2088ardb_tfa_defconfig -- 2.25.1
RE: [PATCH] armv8: fsl-layerscape: use previous aligned address for gic_lpi_base
Hi Marc, Zhiqiang > -Original Message- > From: Marc Zyngier > Sent: Monday, February 21, 2022 4:23 PM > To: Michael Walle > Cc: Wasim Khan (OSS) ; s...@chromium.org; > Priyanka Jain ; tred...@nvidia.com; > twar...@nvidia.com; Varun Sethi ; u- > b...@lists.denx.de; Wasim Khan > Subject: Re: [PATCH] armv8: fsl-layerscape: use previous aligned address for > gic_lpi_base > > On Mon, 21 Feb 2022 10:24:36 +, > Michael Walle wrote: > > > > Hi, > > > > Am 2022-02-21 11:16, schrieb Wasim Khan: > > > From: Wasim Khan > > > > > > Memory after gd->arch.resv_ram is reserved for MC block. > > > Use ALIGN_DOWN to avoid updating MC block for unaligned address. > > > > I cannot really tell what you are trying to do here. But I know Marc > > has offered to also take a look at the GIC/LPI stuff. So I've put him > > on CC. > > > > -michael > > > > > > > > Signed-off-by: Wasim Khan > > > --- > > > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c > > > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c > > > index d3a5cfaac1..746c93cf51 100644 > > > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c > > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c > > > @@ -65,7 +65,7 @@ int ls_gic_rd_tables_init(void *blob) > > > u64 gic_lpi_base; > > > int ret; > > > > > > - gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K); > > > + gic_lpi_base = ALIGN_DOWN(gd->arch.resv_ram - GIC_LPI_SIZE, > > > +SZ_64K); > > > ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, > > > GIC_LPI_SIZE); > > > if (ret) > > > return ret; > > > > It is the usual accumulation of nonsense. We have > > #define ITS_MAX_LPI_NRBITS16 > > which is not necessarily what the HW exposes > > #define PENDTABLE_MAX_SZALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K) > > The *base* of the pending table has to be 64kB aligned, but not its size. Yes, > that's a helpful shortcut, but that's still wrong. > > #define PROPTABLE_MAX_SZALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, > SZ_64K) > > This 64kB alignment is silly, specially considering the hardcoding of the > number of ID bits. > > #define GIC_LPI_SIZEALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + > \ > PROPTABLE_MAX_SZ, SZ_1M) > > This 1MB alignment doesn't exist. Convenience again? > > And then this patch adds some bizarre alignment for reasons that have > nothing to do with the GIC, but because there is so other reservations this > steps on, which probably means that the allocator is doing something wrong... > > The whole thing needs reworking from first principle, at which point it will > become clearer what this is trying to do. > > M. > > -- > Without deviation from the norm, progress is not possible. Added Zhiqiang to respond to Marc's questions. Regarding this patch: if gd->arch.resv_ram points to some address which is not 64K aligned (as per current code), Using ALIGN can be problematic in that case. Ex: Currently MC reserved regions is [0x27_8000_ , 0x27__] gd->arch.resv_ram point to 0x27_8000_. Now suppose if I have requirement to reserve a block (say XYZ) of 32KB size just before MC block, i will update gd->arch.resv_ram to point to 0x27_7FFF_8000. Now, Calling ' gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);' will eat up space reserved for XYZ. So, I think ALIGN_DOWN should be used for gic_lpi_base . gic_lpi_base = ALIGN_DOWN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
[PATCH] armv8: fsl-layerscape: use previous aligned address for gic_lpi_base
From: Wasim Khan Memory after gd->arch.resv_ram is reserved for MC block. Use ALIGN_DOWN to avoid updating MC block for unaligned address. Signed-off-by: Wasim Khan --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index d3a5cfaac1..746c93cf51 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -65,7 +65,7 @@ int ls_gic_rd_tables_init(void *blob) u64 gic_lpi_base; int ret; - gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K); + gic_lpi_base = ALIGN_DOWN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K); ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE); if (ret) return ret; -- 2.25.1
RE: [PATCH] board/freescale/vid : move platform specific definitions
Hi Tom, > -Original Message- > From: U-Boot On Behalf Of Tom Rini > Sent: Friday, September 24, 2021 5:24 PM > To: Wasim Khan (OSS) > Cc: Priyanka Jain ; Varun Sethi ; u- > b...@lists.denx.de > Subject: Re: [PATCH] board/freescale/vid : move platform specific definitions > > On Fri, Sep 24, 2021 at 08:36:45AM +, Wasim Khan (OSS) wrote: > > Hi Tom, > > > > > -Original Message- > > > From: Tom Rini > > > Sent: Tuesday, September 21, 2021 8:14 PM > > > To: Wasim Khan (OSS) > > > Cc: Priyanka Jain ; Varun Sethi > > > ; u- b...@lists.denx.de; Wasim Khan > > > > > > Subject: Re: [PATCH] board/freescale/vid : move platform specific > > > definitions > > > > > > On Tue, Sep 21, 2021 at 04:24:57PM +0200, Wasim Khan wrote: > > > > > > > From: Wasim Khan > > > > > > > > VID is a common driver. Move platform specific definitions to > > > > platform specific header files > > > > > > > > Signed-off-by: Wasim Khan > > > > --- > > > > board/freescale/common/vid.h | 10 -- > > > > include/configs/lx2160a_common.h | 7 +++ > > > > 2 files changed, 7 insertions(+), 10 deletions(-) > > > > > > NAK. Things need to move out of include/configs/ and not in to > > > them, please find another common header file to use. > > > > > > -- > > > Tom > > > > Thank you so much for review. > > Header files 'include/configs/' are auto picked for platform we are using. > > I find it useful especially for common drivers like VID to auto pick > > required > values for underneath platform from > 'include/configs/.h' and we don't need changes > in common driver. > > > > (arch/Kconfig) > > config SYS_CONFIG_NAME > > string > > help > > This option should contain the base name of board header file. > > The header file include/configs/.h > > should be included from include/config.h. > > > > > > (Same is recommended for add/remove boards: doc/README.kconfig) > > Define CONFIG_SYS_CONFIG_NAME="target" to include > > include/configs/.h > > > > > > Currently all NXP platforms (except LX2 series) are using > CONFIG_SYS_CONFIG_NAME to include platform specific header file for VID > driver. I extended the support for LX2 and because the changes are common for > lx2160ardb, lx2160aqds and lx2162aqds , I added them to lx2160a_common.h. > > > > Do you want me to move changes from ' include/configs/lx2160a_common.h' > to ' include/configs/lx2160ardb.h', ' include/configs/lx2160aqds.h' and ' > include/configs/lx2162aqds.h' ? > > > > Or you want me to avoid adding anything to > 'include/configs/.h ' files ? Is there any reason to > do so ? > > I want you to find a place outside of include/config/ for these values to > reside, > yes. The long term goal of moving everything to Kconfig means that we will > not > have include/config/ headers anymore. Further, values like this which are not > actually user-configurable should neither be CONFIG-prefixed (which these are > not, good!) nor reside in include/config/ at all. There should be some > appropriate header perhaps under arch/arm/include/asm/arch-fsl-layerscape/ > to put these values. > And if they need to be shared a bit wider, a fsl-layerscape-common or similar > directory could be used (similar to arch/arm/include/asm/ti-common/). Does > this make sense? Thanks. > > -- > Tom Thanks for explaining it to me. Because VID driver is applicable for arm/x86 platforms, I need to check what would be best place for the header file , but I understood your point. Thanks, Wasim
RE: [PATCH] board/freescale/vid : move platform specific definitions
Hi Tom, > -Original Message- > From: Tom Rini > Sent: Tuesday, September 21, 2021 8:14 PM > To: Wasim Khan (OSS) > Cc: Priyanka Jain ; Varun Sethi ; u- > b...@lists.denx.de; Wasim Khan > Subject: Re: [PATCH] board/freescale/vid : move platform specific definitions > > On Tue, Sep 21, 2021 at 04:24:57PM +0200, Wasim Khan wrote: > > > From: Wasim Khan > > > > VID is a common driver. Move platform specific definitions to platform > > specific header files > > > > Signed-off-by: Wasim Khan > > --- > > board/freescale/common/vid.h | 10 -- > > include/configs/lx2160a_common.h | 7 +++ > > 2 files changed, 7 insertions(+), 10 deletions(-) > > NAK. Things need to move out of include/configs/ and not in to them, please > find another common header file to use. > > -- > Tom Thank you so much for review. Header files 'include/configs/' are auto picked for platform we are using. I find it useful especially for common drivers like VID to auto pick required values for underneath platform from 'include/configs/.h' and we don't need changes in common driver. (arch/Kconfig) config SYS_CONFIG_NAME string help This option should contain the base name of board header file. The header file include/configs/.h should be included from include/config.h. (Same is recommended for add/remove boards: doc/README.kconfig) Define CONFIG_SYS_CONFIG_NAME="target" to include include/configs/.h Currently all NXP platforms (except LX2 series) are using CONFIG_SYS_CONFIG_NAME to include platform specific header file for VID driver. I extended the support for LX2 and because the changes are common for lx2160ardb, lx2160aqds and lx2162aqds , I added them to lx2160a_common.h. Do you want me to move changes from ' include/configs/lx2160a_common.h' to ' include/configs/lx2160ardb.h', ' include/configs/lx2160aqds.h' and ' include/configs/lx2162aqds.h' ? Or you want me to avoid adding anything to 'include/configs/.h ' files ? Is there any reason to do so ?
[PATCH] board/freescale/vid : move platform specific definitions
From: Wasim Khan VID is a common driver. Move platform specific definitions to platform specific header files Signed-off-by: Wasim Khan --- board/freescale/common/vid.h | 10 -- include/configs/lx2160a_common.h | 7 +++ 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h index b34c080b4b..32e68fceb2 100644 --- a/board/freescale/common/vid.h +++ b/board/freescale/common/vid.h @@ -59,16 +59,6 @@ #define PMBUS_CMD_VOUT_COMMAND 0x21 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 -#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \ -defined(CONFIG_TARGET_LX2160ARDB) -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT3 -#define I2C_VOL_MONITOR_ADDR0x63 -#define I2C_MUX_CH_VOL_MONITOR 0xA -#endif - int adjust_vdd(ulong vdd_override); u16 soc_get_fuse_vid(int vid_index); diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 1ae7d37dd9..c2c4a8c7a1 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -86,6 +86,13 @@ #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F2 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT3 +#define I2C_VOL_MONITOR_ADDR 0x63 +#define I2C_MUX_CH_VOL_MONITOR 0xA + /* Define phy_reset function to boot the MC based on mcinitcmd. * This happens late enough to properly fixup u-boot env MAC addresses. */ -- 2.25.1
[PATCH v2] board: freescale: lx216x : increase fdt blob size
From: Wasim Khan
Increase fdt blob size for lx2160 and lx2162 series
to fix below errors/warnings during device tree fixup.
Unable to update property /soc/spi@210:status, err=FDT_ERR_NOSPACE
Unable to update property /soc/spi@211:status, err=FDT_ERR_NOSPACE
Unable to update property /soc/spi@212:status, err=FDT_ERR_NOSPACE
WARNING: could not set reg FDT_ERR_NOSPACE.
WARNING unable to set iommus: FDT_ERR_NOSPACE
Signed-off-by: Wasim Khan
---
Change in v2:
- Return error code if fdt_increase_size() fails
board/freescale/lx2160a/lx2160a.c | 8
1 file changed, 8 insertions(+)
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index f505e82fb9..ba3d62a002 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -828,10 +828,18 @@ int ft_board_setup(void *blob, struct bd_info *bd)
u64 mc_memory_base = 0;
u64 mc_memory_size = 0;
u16 total_memory_banks;
+ int err;
#if CONFIG_IS_ENABLED(TARGET_LX2160ARDB)
u8 board_rev;
#endif
+ err = fdt_increase_size(blob, 512);
+ if (err) {
+ printf("%s fdt_increase_size: err=%s\n", __func__,
+ fdt_strerror(err));
+ return err;
+ }
+
ft_cpu_setup(blob, bd);
fdt_fixup_mc_ddr(_memory_base, _memory_size);
--
2.25.1
RE: [PATCH] configs: lx2162a: Enable CONFIG_SPI_FLASH_MT35XU for lx2162a-qds
> -Original Message- > From: U-Boot On Behalf Of Kuldeep Singh > Sent: Wednesday, September 15, 2021 3:34 PM > To: u-boot@lists.denx.de > Cc: Priyanka Jain ; Kuldeep Singh > > Subject: [PATCH] configs: lx2162a: Enable CONFIG_SPI_FLASH_MT35XU for > lx2162a-qds > > LX2162A-QDS has micron mt35xu512aba flash which requires flag > CONFIG_SPI_FLASH_MT35XU on to probe flash successfully. > > Signed-off-by: Kuldeep Singh Reviewed-by: Wasim Khan Tested-by: Wasim Khan
[PATCH] board: freescale: lx216x : increase fdt blob size
From: Wasim Khan
Increase fdt blob size for lx2160 and lx2162 series
to fix below errors/warnings during device tree fixup.
Unable to update property /soc/spi@210:status, err=FDT_ERR_NOSPACE
Unable to update property /soc/spi@211:status, err=FDT_ERR_NOSPACE
Unable to update property /soc/spi@212:status, err=FDT_ERR_NOSPACE
WARNING: could not set reg FDT_ERR_NOSPACE.
WARNING unable to set iommus: FDT_ERR_NOSPACE
Signed-off-by: Wasim Khan
---
board/freescale/lx2160a/lx2160a.c | 8
1 file changed, 8 insertions(+)
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index f505e82fb9..d03168d6a2 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -828,10 +828,18 @@ int ft_board_setup(void *blob, struct bd_info *bd)
u64 mc_memory_base = 0;
u64 mc_memory_size = 0;
u16 total_memory_banks;
+ int err;
#if CONFIG_IS_ENABLED(TARGET_LX2160ARDB)
u8 board_rev;
#endif
+ err = fdt_increase_size(blob, 512);
+ if (err) {
+ printf("%s fdt_increase_size: err=%s\n", __func__,
+ fdt_strerror(err));
+ return 1;
+ }
+
ft_cpu_setup(blob, bd);
fdt_fixup_mc_ddr(_memory_base, _memory_size);
--
2.25.1
[PATCH v2] armv8: fsl : create bootcmd and mcinitcmd as per boot source
From: Wasim Khan
NXP platforms expect custom bootcmd and mcinitcmd to be
updated as per boot source with default environment.
Check env variable fsl_bootcmd_mcinitcmd_set to prepare
bootcmd and mcinitcmd
Fixes: cbf77d201870 (armv8: fsl-layerscape: Fix automatic
setting of bootmcd with TF-A)
Signed-off-by: Wasim Khan
---
Changes in v2:
Updated commit description as per review comments
Earlier: Fixes: cbf77d2018
Now :Fixes: cbf77d201870 (armv8: fsl-layerscape: Fix automatic
setting of bootmcd with TF-A
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 0562d28705..a77128b424 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -953,12 +953,15 @@ int board_late_init(void)
#endif
#ifdef CONFIG_TFABOOT
/*
-* Set bootcmd and mcinitcmd if they don't exist in the environment.
+* Set bootcmd and mcinitcmd if "fsl_bootcmd_mcinitcmd_set" does
+* not exists in env
*/
- if (!env_get("bootcmd"))
+ if (env_get_yesno("fsl_bootcmd_mcinitcmd_set") <= 0) {
+ // Set bootcmd and mcinitcmd as per boot source
fsl_setenv_bootcmd();
- if (!env_get("mcinitcmd"))
fsl_setenv_mcinitcmd();
+ env_set("fsl_bootcmd_mcinitcmd_set", "y");
+ }
#endif
#ifdef CONFIG_QSPI_AHB_INIT
qspi_ahb_init();
--
2.25.1
[PATCH] armv8: fsl : create bootcmd and mcinitcmd as per boot source
From: Wasim Khan
NXP platforms expect custom bootcmd and mcinitcmd to be
updated as per boot source with default environment.
Check env variable fsl_bootcmd_mcinitcmd_set to prepare
bootcmd and mcinitcmd
Fixes cbf77d2018
Suggested-by: Alban Bedel
Signed-off-by: Wasim Khan
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index c3cd6c7ac7..f804a7f68d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -953,12 +953,15 @@ int board_late_init(void)
#endif
#ifdef CONFIG_TFABOOT
/*
-* Set bootcmd and mcinitcmd if they don't exist in the environment.
+* Set bootcmd and mcinitcmd if "fsl_bootcmd_mcinitcmd_set" does
+* not exists in env
*/
- if (!env_get("bootcmd"))
+ if (env_get_yesno("fsl_bootcmd_mcinitcmd_set") <= 0) {
+ // Set bootcmd and mcinitcmd as per boot source
fsl_setenv_bootcmd();
- if (!env_get("mcinitcmd"))
fsl_setenv_mcinitcmd();
+ env_set("fsl_bootcmd_mcinitcmd_set", "y");
+ }
#endif
#ifdef CONFIG_QSPI_AHB_INIT
qspi_ahb_init();
--
2.25.1
RE: [PATCH] armv8: fsl : fix bootcmd and mcinitcmd default value
Hi Alban,
> -Original Message-
> From: U-Boot On Behalf Of Bedel, Alban
> Sent: Wednesday, June 30, 2021 7:08 PM
> To: Priyanka Jain ; Varun Sethi ;
> Wasim Khan (OSS)
> Cc: u-boot@lists.denx.de
> Subject: Re: [PATCH] armv8: fsl : fix bootcmd and mcinitcmd default value
>
> On Wed, 2021-06-30 at 12:44 +, Wasim Khan (OSS) wrote:
> >
> >
> > > -Original Message-
> > > From: Bedel, Alban
> > > Sent: Wednesday, June 30, 2021 6:03 PM
> > > To: Priyanka Jain ; Varun Sethi <
> > > v.se...@nxp.com>; Wasim Khan ; Wasim Khan (OSS)
> > >
> > > Cc: u-boot@lists.denx.de
> > > Subject: Re: [PATCH] armv8: fsl : fix bootcmd and mcinitcmd default
> > > value
> > >
> > > On Wed, 2021-06-30 at 11:12 +, Priyanka Jain wrote:
> > > >
> > > > snip
> >
> > >
> > > * After issuing `env default -a ; saveenv' the board didn't boot
> > > anymore because `bootcmd` was then empty.
> >
> > This is not the case with latest u-boot code. 'env default -a' set
> > bootcmd to default one (run distro_bootcmd).
> > So, we are safe here.
> >
> >
> > >
> > > * If redundant env on eMMC was enabled `bootcmd` was then
> > > overwritten at every boot, preventing me from using a custom `bootcmd` at
> all.
> > >
> >
> > Priyanka, Alban
> > Can you help me to understand what does enabling 'redundant env' on
> > eMMC mean and how to enable it ?
>
> See env/Kconfig:
>
> config SYS_REDUNDAND_ENVIRONMENT
> bool "Enable redundant environment support"
> depends on ENV_IS_IN_EEPROM || ENV_IS_IN_FLASH || ENV_IS_IN_MMC
> || \
> ENV_IS_IN_NAND || ENV_IS_IN_SPI_FLASH || ENV_IS_IN_UBI
> help
> Normally, the environemt is stored in a single location. By
> selecting this option, you can then define where to hold a redundant
> copy of the environment data, so that there is a valid backup copy
> in
> case there is a power failure during a "saveenv" operation.
>
> When this option is enabled the internals of the env change significantly and
> the
> old code then always detected the env as being the default, erasing any
> previously user set value at every boot.
>
> But beside the fact that it didn't work properly with all configurations, the
> old
> code didn't really detect if the env was the default. When it worked, it
> detected
> the case where no valid env was stored and u-boot was using its internal in-
> memory defaults. That's why resetting the env to default would then break the
> boot.
>
> In my patch I replaced this logic by looking if `bootcmd` has the default
> value,
> which worked well as long as the default value was "unset". But as we see
> this is
> not a viable solution in the long run.
> My suggestion would be to have something like this:
>
>if (env_get_yesno("fsl_bootcmd_set") <= 0) {
> // Set the default bootcmd according to the boot device
> ...
> env_set("fsl_bootcmd_set", "y");
>}
>
> That way it doesn't matter what the default value of `bootcmd` is and boards
> also have the possibility to disable this code by setting `fsl_bootcmd_set`
> to `y`
> in their default env.
>
> I think it would also make sense to have some code that set the TF-A boot
> device in the env, that might allow handling this in the boot scripts directly
> instead of all this hard coded logic.
>
> Alban
Thank you for explaining it. I could reproduce the issue in case we enable
SYS_REDUNDAND_ENVIRONMENT.
Fixed it using another env variable as you suggested. Below are my test steps
on lx2160ardb with xspi and SD boot.
XSPI BOOT ###
=> qixis_reset altbank
Loading Environment from SPIFlash... SF: Detected mt35xu512aba with page size
256 Bytes, erase size 128 KiB, total 64 MiB
*** Warning - bad CRC, using default environment
=> pri bootcmd
bootcmd=sf probe 0:0; sf read 0x806c 0x6c 0x4; env exists mcinitcmd
&& env exists secureboot && esbc_validate 0x806c; sf read 0x80d0
0xd0 0x10; env exists mcinitcmd && fsl_mc lazyapply dpl 0x80d0; run
distro_bootcmd;run xspi_bootcmd; env exists secureboot && esbc_halt;
=> pri mcinitcmd
mcinitcmd=sf probe 0:0 && sf read 0x8064 0x64 0x8 && env exists
secureboot && esbc_validate 0x8064 && esbc_validate 0x8068; sf read
0x80a0 0xa0 0x30 && sf read 0x80e0 0xe0 0x10; fsl_mc
start mc 0x80a0 0x80e
RE: [PATCH] armv8: fsl : fix bootcmd and mcinitcmd default value
> -Original Message- > From: Bedel, Alban > Sent: Wednesday, June 30, 2021 6:03 PM > To: Priyanka Jain ; Varun Sethi ; > Wasim Khan ; Wasim Khan (OSS) > > Cc: u-boot@lists.denx.de > Subject: Re: [PATCH] armv8: fsl : fix bootcmd and mcinitcmd default value > > On Wed, 2021-06-30 at 11:12 +, Priyanka Jain wrote: > > >> snip > > * After issuing `env default -a ; saveenv' the board didn't boot > anymore because `bootcmd` was then empty. This is not the case with latest u-boot code. 'env default -a' set bootcmd to default one (run distro_bootcmd). So, we are safe here. > > * If redundant env on eMMC was enabled `bootcmd` was then overwritten > at every boot, preventing me from using a custom `bootcmd` at all. > Priyanka, Alban Can you help me to understand what does enabling 'redundant env' on eMMC mean and how to enable it ? > snip
buildman error
Hi, I am using latest u-boot code and trying to run buildman with my local patch for lx2160 platform on master branch. Getting below error . u-boot$ ./tools/buildman/buildman --list-tool-chains aarch64 : /opt/gcc-linaro-7.4.1-2019.02-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-gcc arm : /opt/gcc-linaro-7.4.1-2019.02-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc u-boot$ ./tools/buildman/buildman -b master lx2160ardb -ve Building 2 commits for 3 boards (3 threads, 3 jobs per thread) 000 /6 -6 (starting)Thread exception: git checkout (['git', '--git-dir', '../master/.bm-work/02/.git', '--work-tree', '../master/.bm-work/02', 'checkout', '-f', '3ef4572110a43acdd7d401b0cb184c6ebd6eaa17']): fatal: not a git repository: u-boot/.git/worktrees/-2 Thread exception: git checkout (['git', '--git-dir', '../master/.bm-work/00/.git', '--work-tree', '../master/.bm-work/00', 'checkout', '-f', '3ef4572110a43acdd7d401b0cb184c6ebd6eaa17']): fatal: not a git repository: u-boot/.git/worktrees/- Thread exception: git checkout (['git', '--git-dir', '../master/.bm-work/01/.git', '--work-tree', '../master/.bm-work/01', 'checkout', '-f', '3ef4572110a43acdd7d401b0cb184c6ebd6eaa17']): fatal: not a git repository: -boot/.git/worktrees/-1 Completed: 6 total built Failed: 3 thread exceptions Regards, Wasim
[PATCH 3/3] board: freescale: LX2162AQDS: Add MAINTAINER
From: Wasim Khan Add "Wasim Khan " as MAINTAINER for LX2162AQDS board Signed-off-by: Wasim Khan --- Change in v2: Fix typo board/freescale/lx2160a/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/lx2160a/MAINTAINERS b/board/freescale/lx2160a/MAINTAINERS index fca828148e..c60b2af6e4 100644 --- a/board/freescale/lx2160a/MAINTAINERS +++ b/board/freescale/lx2160a/MAINTAINERS @@ -31,6 +31,7 @@ F:configs/lx2160aqds_tfa_SECURE_BOOT_defconfig LX2162AQDS BOARD M: Meenakshi Aggarwal +M: Wasim Khan S: Maintained F: board/freescale/lx2160a/eth_lx2162aqds.h F: include/configs/lx2162aqds.h -- 2.25.1
[v2 PATCH 2/3] board: freescale: LX2160AQDS: Add MAINTAINER
From: Wasim Khan Add "Wasim Khan " as MAINTAINER for LX2160AQDS board Signed-off-by: Wasim Khan --- Change in v2: Fix typo board/freescale/lx2160a/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/lx2160a/MAINTAINERS b/board/freescale/lx2160a/MAINTAINERS index fd33c51ac7..fca828148e 100644 --- a/board/freescale/lx2160a/MAINTAINERS +++ b/board/freescale/lx2160a/MAINTAINERS @@ -17,6 +17,7 @@ F:configs/lx2160ardb_tfa_SECURE_BOOT_defconfig LX2160AQDS BOARD M: Meenakshi Aggarwal +M: Wasim Khan S: Maintained F: board/freescale/lx2160a/eth_lx2160aqds.h F: include/configs/lx2160aqds.h -- 2.25.1
[v2 PATCH 1/3] board: freescale: LX2160ARDB: Add MAINTAINER
From: Wasim Khan Add "Wasim Khan " as MAINTAINER for LX2160ARDB board Signed-off-by: Wasim Khan --- Change in v2: Fix typo board/freescale/lx2160a/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/lx2160a/MAINTAINERS b/board/freescale/lx2160a/MAINTAINERS index cc69de2970..fd33c51ac7 100644 --- a/board/freescale/lx2160a/MAINTAINERS +++ b/board/freescale/lx2160a/MAINTAINERS @@ -1,6 +1,7 @@ LX2160ARDB BOARD M: Meenakshi Aggarwal M: Priyanka Jain +M: Wasim Khan S: Maintained F: board/freescale/lx2160a/ F: include/configs/lx2160a_common.h -- 2.25.1
[PATCH 3/3] board: freescale: LX2162AQDS: Add MAINTAINER
From: Wasim Khan Add "Wasim Khan " as MAINTAINER for LX2162AQDS board Signed-off-by: Wasim Khan --- board/freescale/lx2160a/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/lx2160a/MAINTAINERS b/board/freescale/lx2160a/MAINTAINERS index fca828148e..c60b2af6e4 100644 --- a/board/freescale/lx2160a/MAINTAINERS +++ b/board/freescale/lx2160a/MAINTAINERS @@ -31,6 +31,7 @@ F:configs/lx2160aqds_tfa_SECURE_BOOT_defconfig LX2162AQDS BOARD M: Meenakshi Aggarwal +M: Wasim Khan S: Maintained F: board/freescale/lx2160a/eth_lx2162aqds.h F: include/configs/lx2162aqds.h -- 2.25.1
[PATCH 2/3] board: freescale: LX2160AQDS: Add MAINTAINER
From: Wasim Khan Add "Wasim Khan " as MAINTAINER for LX2160AQDS board Signed-off-by: Wasim Khan --- board/freescale/lx2160a/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/lx2160a/MAINTAINERS b/board/freescale/lx2160a/MAINTAINERS index fd33c51ac7..fca828148e 100644 --- a/board/freescale/lx2160a/MAINTAINERS +++ b/board/freescale/lx2160a/MAINTAINERS @@ -17,6 +17,7 @@ F:configs/lx2160ardb_tfa_SECURE_BOOT_defconfig LX2160AQDS BOARD M: Meenakshi Aggarwal +M: Wasim Khan S: Maintained F: board/freescale/lx2160a/eth_lx2160aqds.h F: include/configs/lx2160aqds.h -- 2.25.1
[PATCH 1/3] board: freescale: LX2160ARDB: Add MAINTAINER
From: Wasim Khan Add "Wasim Khan " as MAINTAINER for LX2160ARDB board Signed-off-by: Wasim Khan --- board/freescale/lx2160a/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/lx2160a/MAINTAINERS b/board/freescale/lx2160a/MAINTAINERS index cc69de2970..fd33c51ac7 100644 --- a/board/freescale/lx2160a/MAINTAINERS +++ b/board/freescale/lx2160a/MAINTAINERS @@ -1,6 +1,7 @@ LX2160ARDB BOARD M: Meenakshi Aggarwal M: Priyanka Jain +M: Wasim Khan S: Maintained F: board/freescale/lx2160a/ F: include/configs/lx2160a_common.h -- 2.25.1
RE: [PATCH] armv8: fsl : fix bootcmd and mcinitcmd default value
Hi Alban, > -Original Message- > From: Bedel, Alban > Sent: Wednesday, June 23, 2021 6:38 PM > To: Priyanka Jain ; Varun Sethi ; > Wasim Khan (OSS) > Cc: u-boot@lists.denx.de; Wasim Khan > Subject: Re: [PATCH] armv8: fsl : fix bootcmd and mcinitcmd default value > > On Wed, 2021-06-16 at 14:19 +0200, Wasim Khan wrote: > > From: Wasim Khan > > > > NXP platforms expect bootcmd and mcinitcmd to be updated as per boot > > source. > > > > commit cbf77d201870f2d12227e2d95718a416b16ec98b breaks this behaviour. > > Revert commit cbf77d201870f2d12227e2d95718a416b16ec98b > > As I already explained in the prior exchanges we had, I'm fully convinced that > reverting this patch is not the solution to your problem. Please see the log > of my > patch for a full explanation, but basically the old code not only rely on the > a > broken assumption, it also fails to implement it correctly. > > The current code set `bootcmd` and `mcinicmd` only if they are not set which a > simple and sane behaviour. As I have explained earlier that the bootcmd is always set with default value as " run distro_bootcmd". So fsl_setenv_bootcmd() never gets executed which is causing the issue. > When I submitted my patch these variables were not > set in the default so I suspect that another patch now set these in the > default > env. I hard reset my tree to your commit and I still see the issue. Please refer to below logs. I don’t see any other patch causing this issue. Would let @Priyanka Jain to share her comments. U-Boot 2021.01-rc3-00115-gcbf77d2018 (Jun 25 2021 - 10:51:56 +0200) SoC: LX2160ACE Rev2.0 (0x87360020) ... ... MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from SPIFlash... SF: Detected mt35xu512aba with page size 256 Bytes, erase size 128 KiB, total 64 MiB *** Warning - bad CRC, using default environment EEPROM: NXID v1 ... ... => pri bootcmd bootcmd=run distro_bootcmd Regards, Wasim > > Alban
[PATCH v2] armv8: lx2160ardb: Add thermal node fixup for revc board
From: Wasim Khan
lx2160ardb Rev-C board has i2c node for thermal monitors
connected to different chip offset.
Add device tree fixup to use lx2160ardb dts and apply
thernal node fixups for lx2160ardb Rev-C board.
Signed-off-by: Wasim Khan
---
Changes in v2:
- Fix compilation warnings for lx2160aqds
board/freescale/lx2160a/lx2160a.c | 121 +-
1 file changed, 120 insertions(+), 1 deletion(-)
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index 47a7024f33..b5cf45e9b4 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2021 NXP
*/
#include
@@ -726,6 +726,116 @@ void board_quiesce_devices(void)
}
#endif
+#if CONFIG_IS_ENABLED(TARGET_LX2160ARDB)
+int fdt_fixup_add_thermal(void *blob, int mux_node, int channel, int reg)
+{
+ int err;
+ int noff;
+ int offset;
+ char channel_node_name[50];
+ char thermal_node_name[50];
+ u32 phandle;
+
+ snprintf(channel_node_name, sizeof(channel_node_name),
+"i2c@%x", channel);
+ debug("channel_node_name = %s\n", channel_node_name);
+
+ snprintf(thermal_node_name, sizeof(thermal_node_name),
+"temperature-sensor@%x", reg);
+ debug("thermal_node_name = %s\n", thermal_node_name);
+
+ err = fdt_increase_size(blob, 200);
+ if (err) {
+ printf("fdt_increase_size: err=%s\n", fdt_strerror(err));
+ return err;
+ }
+
+ noff = fdt_subnode_offset(blob, mux_node, (const char *)
+ channel_node_name);
+ if (noff < 0) {
+ /* channel node not found - create it */
+ noff = fdt_add_subnode(blob, mux_node, channel_node_name);
+ if (noff < 0) {
+ printf("fdt_add_subnode: err=%s\n", fdt_strerror(err));
+ return err;
+ }
+ fdt_setprop_u32 (blob, noff, "#address-cells", 1);
+ fdt_setprop_u32 (blob, noff, "#size-cells", 0);
+ fdt_setprop_u32 (blob, noff, "reg", channel);
+ }
+
+ /* Create thermal node*/
+ offset = fdt_add_subnode(blob, noff, thermal_node_name);
+ fdt_setprop(blob, offset, "compatible", "nxp,sa56004",
+ strlen("nxp,sa56004") + 1);
+ fdt_setprop_u32 (blob, offset, "reg", reg);
+
+ /* fixup phandle*/
+ noff = fdt_node_offset_by_compatible(blob, -1, "regulator-fixed");
+ if (noff < 0) {
+ printf("%s : failed to get phandle\n", __func__);
+ return noff;
+ }
+ phandle = fdt_get_phandle(blob, noff);
+ fdt_setprop_u32 (blob, offset, "vcc-supply", phandle);
+
+ return 0;
+}
+
+void fdt_fixup_delete_thermal(void *blob, int mux_node, int channel, int reg)
+{
+ int node;
+ int value;
+ int err;
+ int subnode;
+
+ fdt_for_each_subnode(subnode, blob, mux_node) {
+ value = fdtdec_get_uint(blob, subnode, "reg", -1);
+ if (value == channel) {
+ /* delete thermal node */
+ fdt_for_each_subnode(node, blob, subnode) {
+ value = fdtdec_get_uint(blob, node, "reg", -1);
+ err = fdt_node_check_compatible(blob, node,
+ "nxp,sa56004");
+ if (!err && value == reg) {
+ fdt_del_node(blob, node);
+ break;
+ }
+ }
+ }
+ }
+}
+
+void fdt_fixup_i2c_thermal_node(void *blob)
+{
+ int i2coffset;
+ int mux_node;
+ int reg;
+ int err;
+
+ i2coffset = fdt_node_offset_by_compat_reg(blob, "fsl,vf610-i2c",
+ 0x200);
+ if (i2coffset != -FDT_ERR_NOTFOUND) {
+ fdt_for_each_subnode(mux_node, blob, i2coffset) {
+ reg = fdtdec_get_uint(blob, mux_node, "reg", -1);
+ err = fdt_node_check_compatible(blob, mux_node,
+ "nxp,pca9547");
+ if (!err && reg == 0x77) {
+ fdt_fixup_delete_thermal(blob, mux_node,
+0x3, 0x4d);
+ err = fdt_fixup_add_thermal(blob, mux_node,
+
[PATCH] armv8: fsl : fix bootcmd and mcinitcmd default value
From: Wasim Khan
NXP platforms expect bootcmd and mcinitcmd to be updated
as per boot source.
commit cbf77d201870f2d12227e2d95718a416b16ec98b breaks this
behaviour.
Revert commit cbf77d201870f2d12227e2d95718a416b16ec98b
Signed-off-by: Wasim Khan
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 27 +
1 file changed, 23 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 7553b5bce2..ad209bde33 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -33,10 +33,13 @@
#include
#endif
#include
+#ifdef CONFIG_TFABOOT
+#include
+#endif
#include
#include
#include
-#ifdef CONFIG_GIC_V3_ITS
+#if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS)
DECLARE_GLOBAL_DATA_PTR;
#endif
@@ -953,12 +956,28 @@ int board_late_init(void)
#endif
#ifdef CONFIG_TFABOOT
/*
-* Set bootcmd and mcinitcmd if they don't exist in the environment.
+* check if gd->env_addr is default_environment; then setenv bootcmd
+* and mcinitcmd.
+*/
+#ifdef CONFIG_SYS_RELOC_GD_ENV_ADDR
+ if (gd->env_addr == (ulong)_environment[0]) {
+#else
+ if (gd->env_addr + gd->reloc_off == (ulong)_environment[0]) {
+#endif
+ fsl_setenv_bootcmd();
+ fsl_setenv_mcinitcmd();
+ }
+
+ /*
+* If the boot mode is secure, default environment is not present then
+* setenv command needs to be run by default
*/
- if (!env_get("bootcmd"))
+#ifdef CONFIG_CHAIN_OF_TRUST
+ if ((fsl_check_boot_mode_secure() == 1)) {
fsl_setenv_bootcmd();
- if (!env_get("mcinitcmd"))
fsl_setenv_mcinitcmd();
+ }
+#endif
#endif
#ifdef CONFIG_QSPI_AHB_INIT
qspi_ahb_init();
--
2.25.1
RE: [PATCH] armv8: lx2160ardb: Add thermal node fixup for revc board
Hi Priyanka,
These changes have been tested and validated .
If no comments, please merge them . Ethernet changes for RevC boards has
dependency on this patch.
Regards,
Wasim
> -Original Message-
> From: Wasim Khan
> Sent: Saturday, April 17, 2021 11:34 PM
> To: Priyanka Jain ; Varun Sethi
> Cc: u-boot@lists.denx.de; Wasim Khan
> Subject: [PATCH] armv8: lx2160ardb: Add thermal node fixup for revc board
>
> From: Wasim Khan
>
> lx2160ardb Rev-C board has i2c node for thermal monitors connected to
> different chip offset.
> Add device tree fixup to use lx2160ardb dts and apply thernal node fixups for
> lx2160ardb Rev-C board.
>
> Signed-off-by: Wasim Khan
> ---
> board/freescale/lx2160a/lx2160a.c | 119 +-
> 1 file changed, 118 insertions(+), 1 deletion(-)
>
> diff --git a/board/freescale/lx2160a/lx2160a.c
> b/board/freescale/lx2160a/lx2160a.c
> index 47a7024f33..8f75b48f95 100644
> --- a/board/freescale/lx2160a/lx2160a.c
> +++ b/board/freescale/lx2160a/lx2160a.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2018-2020 NXP
> + * Copyright 2018-2021 NXP
> */
>
> #include
> @@ -726,6 +726,116 @@ void board_quiesce_devices(void) } #endif
>
> +#if CONFIG_IS_ENABLED(TARGET_LX2160ARDB)
> +int fdt_fixup_add_thermal(void *blob, int mux_node, int channel, int
> +reg) {
> + int err;
> + int noff;
> + int offset;
> + char channel_node_name[50];
> + char thermal_node_name[50];
> + u32 phandle;
> +
> + snprintf(channel_node_name, sizeof(channel_node_name),
> + "i2c@%x", channel);
> + debug("channel_node_name = %s\n", channel_node_name);
> +
> + snprintf(thermal_node_name, sizeof(thermal_node_name),
> + "temperature-sensor@%x", reg);
> + debug("thermal_node_name = %s\n", thermal_node_name);
> +
> + err = fdt_increase_size(blob, 200);
> + if (err) {
> + printf("fdt_increase_size: err=%s\n", fdt_strerror(err));
> + return err;
> + }
> +
> + noff = fdt_subnode_offset(blob, mux_node, (const char *)
> + channel_node_name);
> + if (noff < 0) {
> + /* channel node not found - create it */
> + noff = fdt_add_subnode(blob, mux_node, channel_node_name);
> + if (noff < 0) {
> + printf("fdt_add_subnode: err=%s\n", fdt_strerror(err));
> + return err;
> + }
> + fdt_setprop_u32 (blob, noff, "#address-cells", 1);
> + fdt_setprop_u32 (blob, noff, "#size-cells", 0);
> + fdt_setprop_u32 (blob, noff, "reg", channel);
> + }
> +
> + /* Create thermal node*/
> + offset = fdt_add_subnode(blob, noff, thermal_node_name);
> + fdt_setprop(blob, offset, "compatible", "nxp,sa56004",
> + strlen("nxp,sa56004") + 1);
> + fdt_setprop_u32 (blob, offset, "reg", reg);
> +
> + /* fixup phandle*/
> + noff = fdt_node_offset_by_compatible(blob, -1, "regulator-fixed");
> + if (noff < 0) {
> + printf("%s : failed to get phandle\n", __func__);
> + return noff;
> + }
> + phandle = fdt_get_phandle(blob, noff);
> + fdt_setprop_u32 (blob, offset, "vcc-supply", phandle);
> +
> + return 0;
> +}
> +
> +void fdt_fixup_delete_thermal(void *blob, int mux_node, int channel,
> +int reg) {
> + int node;
> + int value;
> + int err;
> + int subnode;
> +
> + fdt_for_each_subnode(subnode, blob, mux_node) {
> + value = fdtdec_get_uint(blob, subnode, "reg", -1);
> + if (value == channel) {
> + /* delete thermal node */
> + fdt_for_each_subnode(node, blob, subnode) {
> + value = fdtdec_get_uint(blob, node, "reg", -1);
> + err = fdt_node_check_compatible(blob, node,
> +
> "nxp,sa56004");
> + if (!err && value == reg) {
> + fdt_del_node(blob, node);
> + break;
> + }
> + }
> + }
> + }
> +}
> +
> +void fdt_fixup_i2c_thermal_node(void *blob) {
> + int i2coffset;
> + int mux_node;
> + int reg;
> + int err;
> +
> + i2coff
[PATCH] armv8: lx2160ardb: Add thermal node fixup for revc board
From: Wasim Khan
lx2160ardb Rev-C board has i2c node for thermal monitors
connected to different chip offset.
Add device tree fixup to use lx2160ardb dts and apply
thernal node fixups for lx2160ardb Rev-C board.
Signed-off-by: Wasim Khan
---
board/freescale/lx2160a/lx2160a.c | 119 +-
1 file changed, 118 insertions(+), 1 deletion(-)
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index 47a7024f33..8f75b48f95 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2021 NXP
*/
#include
@@ -726,6 +726,116 @@ void board_quiesce_devices(void)
}
#endif
+#if CONFIG_IS_ENABLED(TARGET_LX2160ARDB)
+int fdt_fixup_add_thermal(void *blob, int mux_node, int channel, int reg)
+{
+ int err;
+ int noff;
+ int offset;
+ char channel_node_name[50];
+ char thermal_node_name[50];
+ u32 phandle;
+
+ snprintf(channel_node_name, sizeof(channel_node_name),
+"i2c@%x", channel);
+ debug("channel_node_name = %s\n", channel_node_name);
+
+ snprintf(thermal_node_name, sizeof(thermal_node_name),
+"temperature-sensor@%x", reg);
+ debug("thermal_node_name = %s\n", thermal_node_name);
+
+ err = fdt_increase_size(blob, 200);
+ if (err) {
+ printf("fdt_increase_size: err=%s\n", fdt_strerror(err));
+ return err;
+ }
+
+ noff = fdt_subnode_offset(blob, mux_node, (const char *)
+ channel_node_name);
+ if (noff < 0) {
+ /* channel node not found - create it */
+ noff = fdt_add_subnode(blob, mux_node, channel_node_name);
+ if (noff < 0) {
+ printf("fdt_add_subnode: err=%s\n", fdt_strerror(err));
+ return err;
+ }
+ fdt_setprop_u32 (blob, noff, "#address-cells", 1);
+ fdt_setprop_u32 (blob, noff, "#size-cells", 0);
+ fdt_setprop_u32 (blob, noff, "reg", channel);
+ }
+
+ /* Create thermal node*/
+ offset = fdt_add_subnode(blob, noff, thermal_node_name);
+ fdt_setprop(blob, offset, "compatible", "nxp,sa56004",
+ strlen("nxp,sa56004") + 1);
+ fdt_setprop_u32 (blob, offset, "reg", reg);
+
+ /* fixup phandle*/
+ noff = fdt_node_offset_by_compatible(blob, -1, "regulator-fixed");
+ if (noff < 0) {
+ printf("%s : failed to get phandle\n", __func__);
+ return noff;
+ }
+ phandle = fdt_get_phandle(blob, noff);
+ fdt_setprop_u32 (blob, offset, "vcc-supply", phandle);
+
+ return 0;
+}
+
+void fdt_fixup_delete_thermal(void *blob, int mux_node, int channel, int reg)
+{
+ int node;
+ int value;
+ int err;
+ int subnode;
+
+ fdt_for_each_subnode(subnode, blob, mux_node) {
+ value = fdtdec_get_uint(blob, subnode, "reg", -1);
+ if (value == channel) {
+ /* delete thermal node */
+ fdt_for_each_subnode(node, blob, subnode) {
+ value = fdtdec_get_uint(blob, node, "reg", -1);
+ err = fdt_node_check_compatible(blob, node,
+ "nxp,sa56004");
+ if (!err && value == reg) {
+ fdt_del_node(blob, node);
+ break;
+ }
+ }
+ }
+ }
+}
+
+void fdt_fixup_i2c_thermal_node(void *blob)
+{
+ int i2coffset;
+ int mux_node;
+ int reg;
+ int err;
+
+ i2coffset = fdt_node_offset_by_compat_reg(blob, "fsl,vf610-i2c",
+ 0x200);
+ if (i2coffset != -FDT_ERR_NOTFOUND) {
+ fdt_for_each_subnode(mux_node, blob, i2coffset) {
+ reg = fdtdec_get_uint(blob, mux_node, "reg", -1);
+ err = fdt_node_check_compatible(blob, mux_node,
+ "nxp,pca9547");
+ if (!err && reg == 0x77) {
+ fdt_fixup_delete_thermal(blob, mux_node,
+0x3, 0x4d);
+ err = fdt_fixup_add_thermal(blob, mux_node,
+ 0x3, 0x48);
+ if (err)
+
RE: [PATCH v2 4/4] sandbox: enable IRQ using select for sandbox architecture
Hi Tom, > -Original Message- > From: Simon Glass > Sent: Tuesday, March 30, 2021 10:27 PM > To: Wasim Khan (OSS) > Cc: Bin Meng ; Mario Six ; Bharat > Gooty ; Rayagonda Kokatanur > ; Tero Kristo ; Varun > Sethi ; U-Boot Mailing List ; Wasim > Khan > Subject: Re: [PATCH v2 4/4] sandbox: enable IRQ using select for sandbox > architecture > > Hi Wasim, > > On Tue, 9 Mar 2021 at 04:48, Wasim Khan wrote: > > > > From: Wasim Khan > > > > Enable IRQ using select for sandbox architecture. > > > > Signed-off-by: Wasim Khan > > Reviewed-by: Simon Glass > > --- > > Changes in v2: > > - no change > > > > arch/Kconfig | 1 + > > configs/sandbox64_defconfig| 1 - > > configs/sandbox_defconfig | 1 - > > configs/sandbox_flattree_defconfig | 1 - > > configs/sandbox_spl_defconfig | 1 - > > 5 files changed, 1 insertion(+), 4 deletions(-) > > You can see the status of your series here: > > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatchwor > k.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D232773data=0 > 4%7C01%7Cwasim.khan%40nxp.com%7Cbabc6763976e4d9c257808d8f39cd77b > %7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637527202242089410 > %7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJB > TiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=cmOzxfmhlIdP6A0G1P%2 > BAXg%2FhPVky02%2BeUEMxd5y1bHs%3Dreserved=0 > > It is assigned to Tom Rini. > > Regards, > Simon https://patchwork.ozlabs.org/project/uboot/list/?series=232773 this series is tested, reviewed. It can be merged after https://patchwork.ozlabs.org/project/uboot/patch/20210305070235.13547-1-zhiqiang@nxp.com/ Kindly do the needful Regards, Wasim
RE: [PATCHv3] arm64: gic-v3-its: Clear the Pending table before enabling LPIs
> -Original Message- > From: U-Boot On Behalf Of Zhiqiang Hou > Sent: Friday, March 5, 2021 12:33 PM > To: u-boot@lists.denx.de > Cc: s...@chromium.org; rayagonda.kokata...@broadcom.com; Priyanka Jain > ; Z.q. Hou > Subject: [PATCHv3] arm64: gic-v3-its: Clear the Pending table before enabling > LPIs > > From: Hou Zhiqiang > > The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables must > contain only zeros on initial allocation, and this must be visible to the > Redistributors, or else the effect is UNPREDICTABLE". > > And as the following statement, we here clear the whole Pending tables instead > of the first 1KB. > "An LPI Pending table that contains only zeros, including in the first 1KB, > indicates that there are no pending LPIs. > The first 1KB of the LPI Pending table is IMPLEMENTATION DEFINED. However, > if the first 1KB of the LPI Pending table and the rest of the table contain > only > zeros, this must indicate that there are no pending LPIs." > > And there isn't any pending LPI under U-Boot, so it's unnecessary to load the > contents of the Pending table during the enablement, then set the > GICR_PENDBASER.PTZ flag. > > Signed-off-by: Hou Zhiqiang > --- > V3: > - Fix a mistake code delete in v2. > Reviewed-by: Wasim Khan
[PATCH v2 4/4] sandbox: enable IRQ using select for sandbox architecture
From: Wasim Khan Enable IRQ using select for sandbox architecture. Signed-off-by: Wasim Khan Reviewed-by: Simon Glass --- Changes in v2: - no change arch/Kconfig | 1 + configs/sandbox64_defconfig| 1 - configs/sandbox_defconfig | 1 - configs/sandbox_flattree_defconfig | 1 - configs/sandbox_spl_defconfig | 1 - 5 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index 362b220948..336a5a68ef 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -109,6 +109,7 @@ config SANDBOX select SPI select SUPPORT_OF_CONTROL select SYSRESET_CMD_POWEROFF + select IRQ imply BITREVERSE select BLOBLIST imply CMD_DM diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 5fbbfd7236..534f58f868 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -133,7 +133,6 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y -CONFIG_IRQ=y CONFIG_P2SB=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index f1ec701a9f..56f83695e0 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -160,7 +160,6 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y -CONFIG_IRQ=y CONFIG_P2SB=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index edca7f1808..8098d652dc 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -114,7 +114,6 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y -CONFIG_IRQ=y CONFIG_P2SB=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 479f0226e3..0afb0bec34 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -134,7 +134,6 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y -CONFIG_IRQ=y CONFIG_P2SB=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y -- 2.25.1
[PATCH v2 3/4] arch: Kconfig: enable IRQ using select for x86 architecture
From: Wasim Khan use 'select' to enable IRQ as it does not have architecture specific dependency. Signed-off-by: Wasim Khan Reviewed-by: Hou Zhiqiang Reviewed-by: Simon Glass --- Changes in v2: - no change arch/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/Kconfig b/arch/Kconfig index 3aa99e08fc..362b220948 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -167,6 +167,7 @@ config X86 select TIMER select USE_PRIVATE_LIBGCC select X86_TSC_TIMER + select IRQ imply HAS_ROM if X86_RESET_VECTOR imply BLK imply CMD_DM @@ -197,7 +198,6 @@ config X86 imply USB_HOST_ETHER imply PCH imply RTC_MC146818 - imply IRQ imply ACPIGEN if !QEMU imply SYSINFO if GENERATE_SMBIOS_TABLE imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE -- 2.25.1
[PATCH v2 1/4] misc: make CONFIG_IRQ selectable for all platforms
From: Wasim Khan UCLASS_IRQ driver is not Intel specific. Make CONFIG_IRQ selectable for all platforms. Signed-off-by: Wasim Khan Tested-by: Vladimir Oltean Reviewed-by: Simon Glass --- Changes in v2: - Corrected typo in commit description drivers/misc/Kconfig | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 29432ae7eb..5eab1ed9c6 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -211,10 +211,9 @@ config FSL_SEC_MON like software violations or hardware security violations. config IRQ - bool "Intel Interrupt controller" - depends on X86 || SANDBOX + bool "Interrupt controller" help - This enables support for Intel interrupt controllers, including ITSS. + This enables support for interrupt controllers, including ITSS. Some devices have extra features, such as Apollo Lake. The device has its own uclass since there are several operations involved. -- 2.25.1
[PATCH v2 2/4] arch: arm: update Kconfig to select IRQ when GIC_V3_ITS is enabled
From: Wasim Khan GIC_V3_ITS uses UCLASS_IRQ driver. Update Kconfig to select IRQ when GIC_V3_ITS is enabled. Signed-off-by: Wasim Khan Reviewed-by: Hou Zhiqiang Reviewed-by: Simon Glass --- Changes in v2: - no change arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fbe90875ae..f8b4d422d9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -67,6 +67,7 @@ config GIC_V3_ITS bool "ARM GICV3 ITS" select REGMAP select SYSCON + select IRQ help ARM GICV3 Interrupt translation service (ITS). Basic support for programming locality specific peripheral -- 2.25.1
[PATCH v5] arm: fsl: common: Improve NXP VID driver PMBus support
From: Stephen Carlson
This patch adds support for more PMBus compatible devices to the NXP
drivers for its QorIQ family devices. At runtime, the voltage regulator is
queried over I2C, and the required voltage multiplier determined. This
change supports the DIRECT and LINEAR PMBus voltage reporting modes.
Previously, the driver only supported a few specific devices such as the
IR36021 and LTC3882, so this change allows the QorIQ series to be used
with a much larger variety of core voltage regulator devices.
checkpatch warning "Use if (IS_DEFINED (...))" was ignored to maintain
consistency with the existing code.
Signed-off-by: Stephen Carlson
Signed-off-by: Wasim Khan
Tested-by: Wasim Khan
---
Changes in v5:
- fix compilation issues on ls2080a_emu and ls2080a_simu
- fix compilation issues on powerpc platforms
Changes in v4:
- Included upstream commit ada19fd2
- compilation fix for platforms using IR36021
- read_voltage() fix for devices using INA220
- compilation fix for ls1088
- removed soc_get_fuse_vid() support for ls1028
board/freescale/common/Kconfig | 27 +-
board/freescale/common/vid.c| 820 ++--
board/freescale/common/vid.h| 11 +-
board/freescale/ls1088a/ls1088a.c | 40 ++
board/freescale/ls2080ardb/ls2080ardb.c | 42 ++
board/freescale/lx2160a/lx2160a.c | 42 ++
include/configs/ls1088aqds.h| 6 -
include/configs/ls1088ardb.h| 8 +-
8 files changed, 477 insertions(+), 519 deletions(-)
diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig
index 1b1fd69cb2..17db755951 100644
--- a/board/freescale/common/Kconfig
+++ b/board/freescale/common/Kconfig
@@ -21,18 +21,37 @@ config CMD_ESBC_VALIDATE
esbc_validate - validate signature using RSA verification
esbc_halt - put the core in spin loop (Secure Boot Only)
+config VID
+ depends on DM_I2C
+ bool "Enable Freescale VID"
+ help
+This option enables setting core voltage based on individual
+values saved in SoC fuses.
+
config VOL_MONITOR_LTC3882_READ
depends on VID
bool "Enable the LTC3882 voltage monitor read"
- default n
help
This option enables LTC3882 voltage monitor read
-functionality. It is used by common VID driver.
+functionality. It is used by the common VID driver.
config VOL_MONITOR_LTC3882_SET
depends on VID
bool "Enable the LTC3882 voltage monitor set"
- default n
help
This option enables LTC3882 voltage monitor set
-functionality. It is used by common VID driver.
+functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_ISL68233_READ
+ depends on VID
+ bool "Enable the ISL68233 voltage monitor read"
+ help
+This option enables ISL68233 voltage monitor read
+functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_ISL68233_SET
+ depends on VID
+ bool "Enable the ISL68233 voltage monitor set"
+ help
+This option enables ISL68233 voltage monitor set
+functionality. It is used by the common VID driver.
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index 2617f61520..845d5f6a89 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -2,6 +2,7 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
+ * Copyright 2020 Stephen Carlson
*/
#include
@@ -21,14 +22,22 @@
#include
#include "vid.h"
+/* Voltages are generally handled in mV to keep them as integers */
+#define MV_PER_V 1000
+
+/*
+ * Select the channel on the I2C mux (on some NXP boards) that contains
+ * the voltage regulator to use for VID. Return 0 for success or nonzero
+ * for failure.
+ */
int __weak i2c_multiplexer_select_vid_channel(u8 channel)
{
return 0;
}
/*
- * Compensate for a board specific voltage drop between regulator and SoC
- * return a value in mV
+ * Compensate for a board specific voltage drop between regulator and SoC.
+ * Returns the voltage offset in mV.
*/
int __weak board_vdd_drop_compensation(void)
{
@@ -36,13 +45,94 @@ int __weak board_vdd_drop_compensation(void)
}
/*
- * Board specific settings for specific voltage value
+ * Performs any board specific adjustments after the VID voltage has been
+ * set. Return 0 for success or nonzero for failure.
*/
int __weak board_adjust_vdd(int vdd)
{
return 0;
}
+/*
+ * Processor specific method of converting the fuse value read from VID
+ * registers into the core voltage to supply. Return the voltage in mV.
+ */
+u16 __weak soc_get_fuse_vid(int vid_index)
+{
+ /* Default VDD for Layerscape Chassis 1 devices */
+ static const u16 vdd[32] = {
+ 0, /* unused */
+ 9875, /* 0.987
RE: [PATCH v4] arm: fsl: common: Improve NXP VID driver PMBus support
> -Original Message- > From: U-Boot On Behalf Of Wasim Khan (OSS) > Sent: Friday, February 5, 2021 2:52 PM > To: Priyanka Jain ; Wasim Khan (OSS) > ; Stephen Carlson ; > Varun Sethi ; Thirupathaiah Annapureddy > > Cc: u-boot@lists.denx.de; Stephen Carlson ; > Poonam Aggrwal > Subject: RE: [PATCH v4] arm: fsl: common: Improve NXP VID driver PMBus > support > > Hi Priyanka, > > > > -Original Message- > > From: Priyanka Jain > > Sent: Friday, February 5, 2021 2:15 PM > > To: Wasim Khan (OSS) ; Stephen Carlson > > ; Varun Sethi ; Thirupathaiah > > Annapureddy > > Cc: u-boot@lists.denx.de; Stephen Carlson > > ; Wasim Khan ; > > Poonam Aggrwal > > Subject: RE: [PATCH v4] arm: fsl: common: Improve NXP VID driver PMBus > > support > > > > >-Original Message- > > >From: Wasim Khan (OSS) > > >Sent: Thursday, February 4, 2021 11:44 AM > > >To: Stephen Carlson ; Varun Sethi > > >; Priyanka Jain ; > > >Thirupathaiah Annapureddy > > >Cc: u-boot@lists.denx.de; Stephen Carlson > > >; Wasim Khan > > >Subject: [PATCH v4] arm: fsl: common: Improve NXP VID driver PMBus > > >support > > > > > >From: Stephen Carlson > > > > > >This patch adds support for more PMBus compatible devices to the NXP > > >drivers for its QorIQ family devices. At runtime, the voltage > > >regulator is queried over I2C, and the required voltage multiplier > > >determined. > > >This change supports the DIRECT and LINEAR PMBus voltage reporting > modes. > > > > > >Previously, the driver only supported a few specific devices such as > > >the > > >IR36021 and LTC3882, so this change allows the QorIQ series to be > > >used with a much larger variety of core voltage regulator devices. > > > > > >checkpatch warning "Use if (IS_DEFINED (...))" was ignored to > > >maintain consistency with the existing code. > > > > > >Signed-off-by: Stephen Carlson > > >Signed-off-by: Wasim Khan > > >Tested-by: Wasim Khan > > >--- > > >Changes in v4: > > > - Included upstream commit ada19fd2 > > > - compilation fix for platforms using IR36021 > > > - read_voltage() fix for devices using INA220 > > > - compilation fix for ls1088 > > > - removed soc_get_fuse_vid() support for ls1028 > > > > > > board/freescale/common/Kconfig| 27 +- > > > board/freescale/common/vid.c | 816 -- > > > board/freescale/common/vid.h | 11 +- > > > board/freescale/ls1088a/ls1088a.c | 40 ++ > > >board/freescale/ls2080a/ls2080a.c | > > >49 ++ board/freescale/lx2160a/lx2160a.c | 42 ++ > > > include/configs/ls1088aqds.h | 6 - > > > include/configs/ls1088ardb.h | 8 +- > > > 8 files changed, 480 insertions(+), 519 deletions(-) > > > > > > > Kindly fix build issue on all powerpc platforms (T2080RDB > > T2080RDB_NAND T2080RDB_SDCARD T2080RDB_SECURE_BOOT > T2080RDB_SPIFLASH > > T2080RDB_SRIO_PCIE_BOOT, and others) and layerscape (ls2080a_emu > > ls2080a_simu) platforms. > > Observing build error like below: > > > > 2021-02-04T15:45:01.1295212Zpowerpc: + T2080RDB > > 2021-02-04T15:45:01.1295768Z +board/freescale/common/vid.c: In > > function > > 'adjust_vdd': > > 2021-02-04T15:45:01.1296428Z +board/freescale/common/vid.c:579:24: > error: > > 'I2C_VOL_MONITOR_ADDR' undeclared (first use in this function); did > > you mean 'I2C_VOL_MONITOR_BUS'? > > 2021-02-04T15:45:01.1296854Z + 579 | int ret, i2caddress = > > I2C_VOL_MONITOR_ADDR; > > 2021-02-04T15:45:01.1297145Z + | > > ^~~~ > > 2021-02-04T15:45:01.1297413Z + | > > I2C_VOL_MONITOR_BUS > > 2021-02-04T15:45:01.1297774Z +board/freescale/common/vid.c:579:24: > note: > > each undeclared identifier is reported only once for each function it > > appears in 2021-02-04T15:45:01.1298319Z +board/freescale/common/vid.c: > > In function > > 'print_vdd': > > 2021-02-04T15:45:01.1298926Z +board/freescale/common/vid.c:752:34: > error: > > 'I2C_VOL_MONITOR_ADDR' undeclared (first use in this function); did > > you mean 'I2C_VOL_MONITOR_BUS'? > > 2021-02-04T15:45:01.1299348Z + 752 | int vdd_last, ret, i2caddress = > > I2C_VOL_MONITOR_ADDR; > > 2021-02-04T15:45:01.1299642Z + | > > ^~~~ > > 2021-02-04T15:45:
RE: [PATCH v4] arm: fsl: common: Improve NXP VID driver PMBus support
Hi Priyanka, > -Original Message- > From: Priyanka Jain > Sent: Friday, February 5, 2021 2:15 PM > To: Wasim Khan (OSS) ; Stephen Carlson > ; Varun Sethi ; Thirupathaiah > Annapureddy > Cc: u-boot@lists.denx.de; Stephen Carlson ; > Wasim Khan ; Poonam Aggrwal > > Subject: RE: [PATCH v4] arm: fsl: common: Improve NXP VID driver PMBus > support > > >-Original Message- > >From: Wasim Khan (OSS) > >Sent: Thursday, February 4, 2021 11:44 AM > >To: Stephen Carlson ; Varun Sethi > >; Priyanka Jain ; Thirupathaiah > >Annapureddy > >Cc: u-boot@lists.denx.de; Stephen Carlson > >; Wasim Khan > >Subject: [PATCH v4] arm: fsl: common: Improve NXP VID driver PMBus > >support > > > >From: Stephen Carlson > > > >This patch adds support for more PMBus compatible devices to the NXP > >drivers for its QorIQ family devices. At runtime, the voltage regulator > >is queried over I2C, and the required voltage multiplier determined. > >This change supports the DIRECT and LINEAR PMBus voltage reporting modes. > > > >Previously, the driver only supported a few specific devices such as > >the > >IR36021 and LTC3882, so this change allows the QorIQ series to be used > >with a much larger variety of core voltage regulator devices. > > > >checkpatch warning "Use if (IS_DEFINED (...))" was ignored to maintain > >consistency with the existing code. > > > >Signed-off-by: Stephen Carlson > >Signed-off-by: Wasim Khan > >Tested-by: Wasim Khan > >--- > >Changes in v4: > > - Included upstream commit ada19fd2 > > - compilation fix for platforms using IR36021 > > - read_voltage() fix for devices using INA220 > > - compilation fix for ls1088 > > - removed soc_get_fuse_vid() support for ls1028 > > > > board/freescale/common/Kconfig| 27 +- > > board/freescale/common/vid.c | 816 -- > > board/freescale/common/vid.h | 11 +- > > board/freescale/ls1088a/ls1088a.c | 40 ++ > >board/freescale/ls2080a/ls2080a.c | > >49 ++ board/freescale/lx2160a/lx2160a.c | 42 ++ > > include/configs/ls1088aqds.h | 6 - > > include/configs/ls1088ardb.h | 8 +- > > 8 files changed, 480 insertions(+), 519 deletions(-) > > > > Kindly fix build issue on all powerpc platforms (T2080RDB T2080RDB_NAND > T2080RDB_SDCARD T2080RDB_SECURE_BOOT T2080RDB_SPIFLASH > T2080RDB_SRIO_PCIE_BOOT, and others) and layerscape (ls2080a_emu > ls2080a_simu) platforms. > Observing build error like below: > > 2021-02-04T15:45:01.1295212Zpowerpc: + T2080RDB > 2021-02-04T15:45:01.1295768Z +board/freescale/common/vid.c: In function > 'adjust_vdd': > 2021-02-04T15:45:01.1296428Z +board/freescale/common/vid.c:579:24: error: > 'I2C_VOL_MONITOR_ADDR' undeclared (first use in this function); did you mean > 'I2C_VOL_MONITOR_BUS'? > 2021-02-04T15:45:01.1296854Z + 579 | int ret, i2caddress = > I2C_VOL_MONITOR_ADDR; > 2021-02-04T15:45:01.1297145Z + | > ^~~~ > 2021-02-04T15:45:01.1297413Z + | > I2C_VOL_MONITOR_BUS > 2021-02-04T15:45:01.1297774Z +board/freescale/common/vid.c:579:24: note: > each undeclared identifier is reported only once for each function it appears > in > 2021-02-04T15:45:01.1298319Z +board/freescale/common/vid.c: In function > 'print_vdd': > 2021-02-04T15:45:01.1298926Z +board/freescale/common/vid.c:752:34: error: > 'I2C_VOL_MONITOR_ADDR' undeclared (first use in this function); did you mean > 'I2C_VOL_MONITOR_BUS'? > 2021-02-04T15:45:01.1299348Z + 752 | int vdd_last, ret, i2caddress = > I2C_VOL_MONITOR_ADDR; > 2021-02-04T15:45:01.1299642Z + | > ^~~~ > 2021-02-04T15:45:01.1299956Z + | > I2C_VOL_MONITOR_BUS > 2021-02-04T15:45:01.1300239Z +make[2]: *** > [board/freescale/common/vid.o] Error 1 2021-02-04T15:45:01.1300527Z > +make[1]: *** [board/freescale/common] Error 2 2021-02- > 04T15:45:01.1300894Z +make: *** [sub-make] Error 2 2021-02- > 04T15:45:01.1301006Z > Thanks for reporting this. I have not built the power PC platforms. Can you please share the build steps for powerpc platforms and the toolchain to be used. Also share the commands/step to check compilation for all platforms so that I can run it for future commits while updating a common driver. > 2021-02-04T15:14:59.9216814Z Summary of current source for 16 boards (2 > threads, 1 job per thread) > 2021-02-04T15:14:59.9218141Zaarch64: w+ ls2080aqds ls2080aqds_nand > ls2080aqds_qspi ls2080aqds_sdcard ls2080ardb ls2080ardb_nand ls2081ardb > ls2080aqds_SECURE_BOOT ls2080ardb_SE
[PATCH v2] cmd: fdt: skip board specific fixup using env variable
From: Wasim Khan
Sometimes it is useful to boot OS with already fixed-up
device tree. Check for env variable 'skip_board_fixup'
before calling ft_board_setup().
Current behaviour is unchanged, additionally user can
set skip_board_fixup to 1 to skip the fixup.
Signed-off-by: Wasim Khan
---
Changes in v2:
- Added check for skip_board_fixup in checkpatch.pl
common/image-fdt.c| 17 -
scripts/checkpatch.pl | 6 ++
2 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/common/image-fdt.c b/common/image-fdt.c
index 327a8c4c39..0435176863 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -572,11 +572,18 @@ int image_setup_libfdt(bootm_headers_t *images, void
*blob,
fdt_fixup_pstore(blob);
#endif
if (IMAGE_OF_BOARD_SETUP) {
- fdt_ret = ft_board_setup(blob, gd->bd);
- if (fdt_ret) {
- printf("ERROR: board-specific fdt fixup failed: %s\n",
- fdt_strerror(fdt_ret));
- goto err;
+ const char *skip_board_fixup;
+
+ skip_board_fixup = env_get("skip_board_fixup");
+ if (skip_board_fixup && ((int)simple_strtol(skip_board_fixup,
NULL, 10) == 1)) {
+ printf("skip board fdt fixup\n");
+ } else {
+ fdt_ret = ft_board_setup(blob, gd->bd);
+ if (fdt_ret) {
+ printf("ERROR: board-specific fdt fixup failed:
%s\n",
+ fdt_strerror(fdt_ret));
+ goto err;
+ }
}
}
if (IMAGE_OF_SYSTEM_SETUP) {
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 4ed7e124c9..7b76894fb4 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -2366,6 +2366,12 @@ sub u_boot_line {
"fdt or initrd relocation disabled at boot time\n" .
$herecurr);
}
+ # make sure 'skip_board_fixup' is not
+ if ($rawline =~ /.*skip_board_fixup.*/) {
+ ERROR("SKIP_BOARD_FIXUP",
+"Avoid setting skip_board_fixup env variable\n" .
$herecurr);
+ }
+
# Do not use CONFIG_ prefix in CONFIG_IS_ENABLED() calls
if ($line =~ /^\+.*CONFIG_IS_ENABLED\(CONFIG_\w*\).*/) {
ERROR("CONFIG_IS_ENABLED_CONFIG",
--
2.25.1
RE: [PATCH] cmd: fdt: skip board specific fixup using env variable
Hi Tom, > -Original Message- > From: U-Boot On Behalf Of Tom Rini > Sent: Saturday, January 30, 2021 12:53 AM > To: Wasim Khan (OSS) > Cc: s...@chromium.org; t-kri...@ti.com; Varun Sethi ; u- > b...@lists.denx.de > Subject: Re: [PATCH] cmd: fdt: skip board specific fixup using env variable > > On Thu, Jan 28, 2021 at 08:15:33AM +, Wasim Khan (OSS) wrote: > > Hi Tom, > > > > > -Original Message- > > > From: Tom Rini > > > Sent: Wednesday, January 27, 2021 7:41 PM > > > To: Wasim Khan (OSS) > > > Cc: s...@chromium.org; t-kri...@ti.com; Varun Sethi > > > ; u- b...@lists.denx.de; Wasim Khan > > > > > > Subject: Re: [PATCH] cmd: fdt: skip board specific fixup using env > > > variable > > > > > > On Wed, Jan 27, 2021 at 02:09:48PM +0100, Wasim Khan wrote: > > > > > > > From: Wasim Khan > > > > > > > > Sometimes it is useful to boot OS with already fixed-up device tree. > > > > Check for env variable 'skip_board_fixup' > > > > before calling ft_board_setup(). > > > > Current behaviour is unchanged, additionally user can set > > > > skip_board_fixup to 1 to skip the fixup. > > > > > > > > Signed-off-by: Wasim Khan > > > > --- > > > > common/image-fdt.c | 17 - > > > > 1 file changed, 12 insertions(+), 5 deletions(-) > > > > > > Can you provide a specific example or two here? Thanks! > > > > Thank you for your comments. > > > > Recently I faced issue where Linux crash in PCIe was observed in customer's > env. > > Whereas same Linux was booting fine in my environment. After debugging > we found that U-boot was doing fixup based on SVR value. SVR check was > failing in customer's env because of different SoC personality which was > causing the crash in OS. > > So I thought it is good idea to have an option to bypass U-boot fixup and > > use > an already fixed-up device tree so that we can quickly check if the problem > is in > OS or it is caused because of missed/wrong fixup from Uboot. > > > > Another use case I can think of is suppose if we want to introduce a new dtb > fixup , we can directly add the change in a fixed-up device tree, do all > experiments and once validated thoroughly , we can do the same change via > Uboot fixup. > > OK, I can see how this can be useful in some circumstances, thanks. > What I'd like to see is updating checkpatch.pl to have a check that we aren't > setting this by default in environments (something like the check that exists > now > for (fdt|initrd)_high=0x should be a good > reference) as my worry is that someone will decide that's how to work-around > some issue and we'll end up in another nightmare down the road of > uncorrected dtbs causing other problems. Thanks! > > -- > Tom Thanks, If I understood your comment correctly, you suggesting to add 'skip_board_fixup' to CONFIG_EXTRA_ENV_SETTINGS for all of our platforms and check its default value in checkpatch.pl , which must be 0 ?
[PATCH v4] arm: fsl: common: Improve NXP VID driver PMBus support
From: Stephen Carlson
This patch adds support for more PMBus compatible devices to the NXP
drivers for its QorIQ family devices. At runtime, the voltage regulator is
queried over I2C, and the required voltage multiplier determined. This
change supports the DIRECT and LINEAR PMBus voltage reporting modes.
Previously, the driver only supported a few specific devices such as the
IR36021 and LTC3882, so this change allows the QorIQ series to be used
with a much larger variety of core voltage regulator devices.
checkpatch warning "Use if (IS_DEFINED (...))" was ignored to maintain
consistency with the existing code.
Signed-off-by: Stephen Carlson
Signed-off-by: Wasim Khan
Tested-by: Wasim Khan
---
Changes in v4:
- Included upstream commit ada19fd2
- compilation fix for platforms using IR36021
- read_voltage() fix for devices using INA220
- compilation fix for ls1088
- removed soc_get_fuse_vid() support for ls1028
board/freescale/common/Kconfig| 27 +-
board/freescale/common/vid.c | 816 --
board/freescale/common/vid.h | 11 +-
board/freescale/ls1088a/ls1088a.c | 40 ++
board/freescale/ls2080a/ls2080a.c | 49 ++
board/freescale/lx2160a/lx2160a.c | 42 ++
include/configs/ls1088aqds.h | 6 -
include/configs/ls1088ardb.h | 8 +-
8 files changed, 480 insertions(+), 519 deletions(-)
diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig
index 1b1fd69cb2..17db755951 100644
--- a/board/freescale/common/Kconfig
+++ b/board/freescale/common/Kconfig
@@ -21,18 +21,37 @@ config CMD_ESBC_VALIDATE
esbc_validate - validate signature using RSA verification
esbc_halt - put the core in spin loop (Secure Boot Only)
+config VID
+ depends on DM_I2C
+ bool "Enable Freescale VID"
+ help
+This option enables setting core voltage based on individual
+values saved in SoC fuses.
+
config VOL_MONITOR_LTC3882_READ
depends on VID
bool "Enable the LTC3882 voltage monitor read"
- default n
help
This option enables LTC3882 voltage monitor read
-functionality. It is used by common VID driver.
+functionality. It is used by the common VID driver.
config VOL_MONITOR_LTC3882_SET
depends on VID
bool "Enable the LTC3882 voltage monitor set"
- default n
help
This option enables LTC3882 voltage monitor set
-functionality. It is used by common VID driver.
+functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_ISL68233_READ
+ depends on VID
+ bool "Enable the ISL68233 voltage monitor read"
+ help
+This option enables ISL68233 voltage monitor read
+functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_ISL68233_SET
+ depends on VID
+ bool "Enable the ISL68233 voltage monitor set"
+ help
+This option enables ISL68233 voltage monitor set
+functionality. It is used by the common VID driver.
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index 2617f61520..14bef19aea 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -2,6 +2,7 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
+ * Copyright 2020 Stephen Carlson
*/
#include
@@ -21,14 +22,22 @@
#include
#include "vid.h"
+/* Voltages are generally handled in mV to keep them as integers */
+#define MV_PER_V 1000
+
+/*
+ * Select the channel on the I2C mux (on some NXP boards) that contains
+ * the voltage regulator to use for VID. Return 0 for success or nonzero
+ * for failure.
+ */
int __weak i2c_multiplexer_select_vid_channel(u8 channel)
{
return 0;
}
/*
- * Compensate for a board specific voltage drop between regulator and SoC
- * return a value in mV
+ * Compensate for a board specific voltage drop between regulator and SoC.
+ * Returns the voltage offset in mV.
*/
int __weak board_vdd_drop_compensation(void)
{
@@ -36,13 +45,90 @@ int __weak board_vdd_drop_compensation(void)
}
/*
- * Board specific settings for specific voltage value
+ * Performs any board specific adjustments after the VID voltage has been
+ * set. Return 0 for success or nonzero for failure.
*/
int __weak board_adjust_vdd(int vdd)
{
return 0;
}
+/*
+ * Processor specific method of converting the fuse value read from VID
+ * registers into the core voltage to supply. Return the voltage in mV.
+ */
+u16 __weak soc_get_fuse_vid(int vid_index)
+{
+ /* Default VDD for Layerscape Chassis 1 devices */
+ static const u16 vdd[32] = {
+ 0, /* unused */
+ 9875, /* 0.9875V */
+ 9750,
+ 9625,
+ 9500,
+ 9375,
+ 9250,
+ 9125,
+
RE: [PATCHv2] pci: layerscape: Remove the shadow SVR definitions
> -Original Message- > From: Z.q. Hou > Sent: Friday, January 29, 2021 10:17 AM > To: u-boot@lists.denx.de; Priyanka Jain > Cc: Wasim Khan ; Z.q. Hou > Subject: [PATCHv2] pci: layerscape: Remove the shadow SVR definitions > > From: Hou Zhiqiang > > This patch moves the SVR definitions to a new svr.h for Layerscape armv7 and > armv8 platforms respectively, so that the PCIe driver can reuse them. > > Signed-off-by: Hou Zhiqiang > --- > V2: > - rebase the patch and correct the typos in the subject Reviewed-by: Wasim Khan
RE: [PATCH] pci: kconfig: layerscape: Change LX2162A PCIe node compatible string
> -Original Message- > From: Z.q. Hou > Sent: Friday, January 29, 2021 10:52 AM > To: u-boot@lists.denx.de; Priyanka Jain ; Wasim Khan > > Cc: Z.q. Hou > Subject: [PATCH] pci: kconfig: layerscape: Change LX2162A PCIe node > compatible string > > From: Hou Zhiqiang > > LX2162A is not like LX2160A which has different PCIe controller in rev1 and > rev2 > silicon. It supports only one configuration of PCIe controller, which is same > as > LS2088A. So update PCIe compatible string same as LS2088A. > > Signed-off-by: Hou Zhiqiang Reviewed-by: Wasim Khan Tested-by: Wasim Khan
RE: [PATCH] cmd: fdt: skip board specific fixup using env variable
Hi Tom, > -Original Message- > From: Tom Rini > Sent: Wednesday, January 27, 2021 7:41 PM > To: Wasim Khan (OSS) > Cc: s...@chromium.org; t-kri...@ti.com; Varun Sethi ; u- > b...@lists.denx.de; Wasim Khan > Subject: Re: [PATCH] cmd: fdt: skip board specific fixup using env variable > > On Wed, Jan 27, 2021 at 02:09:48PM +0100, Wasim Khan wrote: > > > From: Wasim Khan > > > > Sometimes it is useful to boot OS with already fixed-up device tree. > > Check for env variable 'skip_board_fixup' > > before calling ft_board_setup(). > > Current behaviour is unchanged, additionally user can set > > skip_board_fixup to 1 to skip the fixup. > > > > Signed-off-by: Wasim Khan > > --- > > common/image-fdt.c | 17 - > > 1 file changed, 12 insertions(+), 5 deletions(-) > > Can you provide a specific example or two here? Thanks! Thank you for your comments. Recently I faced issue where Linux crash in PCIe was observed in customer's env. Whereas same Linux was booting fine in my environment. After debugging we found that U-boot was doing fixup based on SVR value. SVR check was failing in customer's env because of different SoC personality which was causing the crash in OS. So I thought it is good idea to have an option to bypass U-boot fixup and use an already fixed-up device tree so that we can quickly check if the problem is in OS or it is caused because of missed/wrong fixup from Uboot. Another use case I can think of is suppose if we want to introduce a new dtb fixup , we can directly add the change in a fixed-up device tree, do all experiments and once validated thoroughly , we can do the same change via Uboot fixup.
RE: [PATCH 2/4] arch: arm: update Kconfig to select IRQ when GIC_V3_ITS is enabled
Vladimir, > -Original Message- > From: Vladimir Oltean > Sent: Wednesday, January 27, 2021 9:20 PM > To: Wasim Khan (OSS) > Cc: u-boot@lists.denx.de; s...@chromium.org; bmeng...@gmail.com; > mario@gdsys.cc; bharat.go...@broadcom.com; > rayagonda.kokata...@broadcom.com; t-kri...@ti.com; Varun Sethi > ; Wasim Khan > Subject: Re: [PATCH 2/4] arch: arm: update Kconfig to select IRQ when > GIC_V3_ITS is enabled > > Wasim, > > On Tue, Jan 12, 2021 at 10:05:07AM +0100, Wasim Khan wrote: > > From: Wasim Khan > > > > GIC_V3_ITS uses UCLASS_IRQ driver. Update Kconfig to select > > IRQ when GIC_V3_ITS is enabled. > > > > Signed-off-by: Wasim Khan > > --- > > While this fixes my U-Boot booting issue on NXP LS1028A-RDB (thank you for > that): > > I'm thinking it would be unwise to apply the patches as-is, since now, > the GIC-v3 ITS driver does bind, but when Linux boots, apparently it now > sees some IRQ storms and dies very quickly in the boot process. Did you > try to boot Linux after these patches? > > On the other hand, the board works just fine with CONFIG_GIC_V3_ITS > disabled. The kontron_sl28_defconfig doesn't even have it. What do we > use the GIC ITS for in U-Boot? > > One boot attempt: > > [1.940732] 000: Unable to handle kernel NULL pointer dereference at > virtual > address Thanks for reporting this. Yes, I tested LX2162aqds and did not face any issue in the limited trials I performed. I agree with you to hold on this series until crash you reported is fixed.
[PATCH] cmd: fdt: skip board specific fixup using env variable
From: Wasim Khan
Sometimes it is useful to boot OS with already fixed-up
device tree. Check for env variable 'skip_board_fixup'
before calling ft_board_setup().
Current behaviour is unchanged, additionally user can
set skip_board_fixup to 1 to skip the fixup.
Signed-off-by: Wasim Khan
---
common/image-fdt.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/common/image-fdt.c b/common/image-fdt.c
index 327a8c4c39..0435176863 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -572,11 +572,18 @@ int image_setup_libfdt(bootm_headers_t *images, void
*blob,
fdt_fixup_pstore(blob);
#endif
if (IMAGE_OF_BOARD_SETUP) {
- fdt_ret = ft_board_setup(blob, gd->bd);
- if (fdt_ret) {
- printf("ERROR: board-specific fdt fixup failed: %s\n",
- fdt_strerror(fdt_ret));
- goto err;
+ const char *skip_board_fixup;
+
+ skip_board_fixup = env_get("skip_board_fixup");
+ if (skip_board_fixup && ((int)simple_strtol(skip_board_fixup,
NULL, 10) == 1)) {
+ printf("skip board fdt fixup\n");
+ } else {
+ fdt_ret = ft_board_setup(blob, gd->bd);
+ if (fdt_ret) {
+ printf("ERROR: board-specific fdt fixup failed:
%s\n",
+ fdt_strerror(fdt_ret));
+ goto err;
+ }
}
}
if (IMAGE_OF_SYSTEM_SETUP) {
--
2.25.1
[PATCH v2] armv8: lx2: SVR_SOC_VER: Mask CAN_FD and security bit
From: Wasim Khan Multiple LX2(LX2160A/LX2162A SoC) personality variants exists based on CAN-FD and security bit in SVR. Currenly SVR_SOC_VER mask only security bit. Update SVR_SOC_VER to mask CAN_FD and security bit for LX2 products. Signed-off-by: Wasim Khan --- Changes in v2: - Updated commit subject and description arch/arm/include/asm/arch-fsl-layerscape/soc.h | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index b24f38cac9..887954eaa5 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017-2020 NXP + * Copyright 2017-2021 NXP * Copyright 2015 Freescale Semiconductor */ @@ -113,10 +113,13 @@ enum boot_src get_boot_src(void); #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_REV(svr) (((svr) >> 0) & 0xff) -#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr)(!((svr >> 8) & 0x1)) #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define IS_C_PROCESSOR(svr)(!((svr >> 12) & 0x1)) +#define SVR_WO_CE 0xEE +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_CE) +#else +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #endif #ifdef CONFIG_ARCH_LS1028A #define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1)) -- 2.25.1
[PATCH 3/4] arch: Kconfig: enable IRQ using select for x86 architecture
From: Wasim Khan use 'select' to enable IRQ as it does not have architecture specific dependency. Signed-off-by: Wasim Khan --- arch/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/Kconfig b/arch/Kconfig index 3aa99e08fc..362b220948 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -167,6 +167,7 @@ config X86 select TIMER select USE_PRIVATE_LIBGCC select X86_TSC_TIMER + select IRQ imply HAS_ROM if X86_RESET_VECTOR imply BLK imply CMD_DM @@ -197,7 +198,6 @@ config X86 imply USB_HOST_ETHER imply PCH imply RTC_MC146818 - imply IRQ imply ACPIGEN if !QEMU imply SYSINFO if GENERATE_SMBIOS_TABLE imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE -- 2.25.1
[PATCH 4/4] sandbox: enable IRQ using select for sandbox architecture
From: Wasim Khan Enable IRQ using select for sandbox architecture. Signed-off-by: Wasim Khan --- arch/Kconfig | 1 + configs/sandbox64_defconfig| 1 - configs/sandbox_defconfig | 1 - configs/sandbox_flattree_defconfig | 1 - configs/sandbox_spl_defconfig | 1 - 5 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index 362b220948..336a5a68ef 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -109,6 +109,7 @@ config SANDBOX select SPI select SUPPORT_OF_CONTROL select SYSRESET_CMD_POWEROFF + select IRQ imply BITREVERSE select BLOBLIST imply CMD_DM diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 5fbbfd7236..534f58f868 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -133,7 +133,6 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y -CONFIG_IRQ=y CONFIG_P2SB=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index f1ec701a9f..56f83695e0 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -160,7 +160,6 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y -CONFIG_IRQ=y CONFIG_P2SB=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index edca7f1808..8098d652dc 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -114,7 +114,6 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y -CONFIG_IRQ=y CONFIG_P2SB=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 479f0226e3..0afb0bec34 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -134,7 +134,6 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y -CONFIG_IRQ=y CONFIG_P2SB=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y -- 2.25.1
[PATCH 2/4] arch: arm: update Kconfig to select IRQ when GIC_V3_ITS is enabled
From: Wasim Khan GIC_V3_ITS uses UCLASS_IRQ driver. Update Kconfig to select IRQ when GIC_V3_ITS is enabled. Signed-off-by: Wasim Khan --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fbe90875ae..f8b4d422d9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -67,6 +67,7 @@ config GIC_V3_ITS bool "ARM GICV3 ITS" select REGMAP select SYSCON + select IRQ help ARM GICV3 Interrupt translation service (ITS). Basic support for programming locality specific peripheral -- 2.25.1
[PATCH 1/4] misc: make CONFIG_IRQ selectable for all platforms
From: Wasim Khan UCLASS_IRQ driver is not Intel specific. Make CONFIG_IRQ selectable for all platfroms. Signed-off-by: Wasim Khan --- drivers/misc/Kconfig | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 29432ae7eb..5eab1ed9c6 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -211,10 +211,9 @@ config FSL_SEC_MON like software violations or hardware security violations. config IRQ - bool "Intel Interrupt controller" - depends on X86 || SANDBOX + bool "Interrupt controller" help - This enables support for Intel interrupt controllers, including ITSS. + This enables support for interrupt controllers, including ITSS. Some devices have extra features, such as Apollo Lake. The device has its own uclass since there are several operations involved. -- 2.25.1
[PATCH] armv8: update SVR_SOC_VER to mask CAN_FD and security bit for LX2 products
Multiple product varients exists based on CAN-FD and security bit in SVR. Currenly SVR_SOC_VER mask only security bit. Update SVR_SOC_VER to mask CAN_FD and security bit for LX2 products. Signed-off-by: Wasim Khan --- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index b24f38cac9..887954eaa5 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017-2020 NXP + * Copyright 2017-2021 NXP * Copyright 2015 Freescale Semiconductor */ @@ -113,10 +113,13 @@ enum boot_src get_boot_src(void); #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_REV(svr) (((svr) >> 0) & 0xff) -#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr)(!((svr >> 8) & 0x1)) #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define IS_C_PROCESSOR(svr)(!((svr >> 12) & 0x1)) +#define SVR_WO_CE 0xEE +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_CE) +#else +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #endif #ifdef CONFIG_ARCH_LS1028A #define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1)) -- 2.25.1
RE: [PATCH v3] arm: fsl: common: Improve NXP VID driver PMBus support
> -Original Message-
> From: U-Boot On Behalf Of Stephen Carlson
> Sent: Thursday, December 10, 2020 9:55 AM
> To: U-Boot Mailing List
> Cc: Priyanka Jain
> Subject: [PATCH v3] arm: fsl: common: Improve NXP VID driver PMBus support
>
> This patch adds support for more PMBus compatible devices to the NXP drivers
> for its QorIQ family devices. At runtime, the voltage regulator is queried
> over
> I2C, and the required voltage multiplier determined. This change supports the
> DIRECT and LINEAR PMBus voltage reporting modes.
>
> Previously, the driver only supported a few specific devices such as the
> IR36021 and LTC3882, so this change allows the QorIQ series to be used with a
> much larger variety of core voltage regulator devices.
>
> checkpatch warning "Use if (IS_DEFINED (...))" was ignored to maintain
> consistency with the existing code.
>
> Signed-off-by: Stephen Carlson
> Cc: Priyanka Jain
Reviewed-by: Wasim Khan
> ---
> board/freescale/common/Kconfig| 27 +-
> board/freescale/common/vid.c | 815 --
> board/freescale/common/vid.h | 13 +-
> board/freescale/ls1028a/ls1028a.c | 42 ++
> board/freescale/ls1088a/ls1088a.c | 40 ++
> board/freescale/ls2080a/ls2080a.c | 49 ++
> board/freescale/lx2160a/lx2160a.c | 42 ++
> include/configs/ls1088aqds.h | 6 -
> include/configs/ls1088ardb.h | 8 +-
> 9 files changed, 526 insertions(+), 516 deletions(-)
>
> diff --git a/board/freescale/common/Kconfig
> b/board/freescale/common/Kconfig index 1b1fd69cb2..17db755951 100644
> --- a/board/freescale/common/Kconfig
> +++ b/board/freescale/common/Kconfig
> @@ -21,18 +21,37 @@ config CMD_ESBC_VALIDATE
> esbc_validate - validate signature using RSA verification
> esbc_halt - put the core in spin loop (Secure Boot Only)
>
> +config VID
> + depends on DM_I2C
> + bool "Enable Freescale VID"
> + help
> + This option enables setting core voltage based on individual
> + values saved in SoC fuses.
> +
> config VOL_MONITOR_LTC3882_READ
> depends on VID
> bool "Enable the LTC3882 voltage monitor read"
> - default n
> help
>This option enables LTC3882 voltage monitor read
> - functionality. It is used by common VID driver.
> + functionality. It is used by the common VID driver.
>
> config VOL_MONITOR_LTC3882_SET
> depends on VID
> bool "Enable the LTC3882 voltage monitor set"
> - default n
> help
>This option enables LTC3882 voltage monitor set
> - functionality. It is used by common VID driver.
> + functionality. It is used by the common VID driver.
> +
> +config VOL_MONITOR_ISL68233_READ
> + depends on VID
> + bool "Enable the ISL68233 voltage monitor read"
> + help
> + This option enables ISL68233 voltage monitor read
> + functionality. It is used by the common VID driver.
> +
> +config VOL_MONITOR_ISL68233_SET
> + depends on VID
> + bool "Enable the ISL68233 voltage monitor set"
> + help
> + This option enables ISL68233 voltage monitor set
> + functionality. It is used by the common VID driver.
> diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
> index 9c51f50260..2df3adf3bc 100644
> --- a/board/freescale/common/vid.c
> +++ b/board/freescale/common/vid.c
> @@ -1,6 +1,8 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
>* Copyright 2014 Freescale Semiconductor, Inc.
> + *
> + * Copyright 2020 Stephen Carlson
>*/
>
> #include
> @@ -20,14 +22,22 @@
> #include
> #include "vid.h"
>
> +/* Voltages are generally handled in mV to keep them as integers */
> +#define MV_PER_V 1000
> +
> +/*
> + * Select the channel on the I2C mux (on some NXP boards) that contains
> + * the voltage regulator to use for VID. Return 0 for success or
> +nonzero
> + * for failure.
> + */
> int __weak i2c_multiplexer_select_vid_channel(u8 channel)
> {
> return 0;
> }
>
> /*
> - * Compensate for a board specific voltage drop between regulator and SoC
> - * return a value in mV
> + * Compensate for a board specific voltage drop between regulator and SoC.
> + * Returns the voltage offset in mV.
>*/
> int __weak board_vdd_drop_compensation(void)
> {
> @@ -35,13 +45,90 @@ int __weak board_vdd_drop_compensation(void)
> }
>
> /*
> - * Board specific settings for specific voltage value
> + * Performs any board specific adjustments after the VID voltage has
> + been
> + * set.
RE: [PATCH] armv8: lx2162aqds: disable non existing pcie controllers
> -Original Message- > From: Priyanka Jain > Sent: Friday, December 11, 2020 1:49 PM > To: Wasim Khan ; u-boot@lists.denx.de; Priyanka Jain > (OSS) ; Varun Sethi ; > Meenakshi Aggarwal > Cc: Wasim Khan > Subject: RE: [PATCH] armv8: lx2162aqds: disable non existing pcie controllers > > >-Original Message----- > >From: U-Boot On Behalf Of Wasim Khan > >Sent: Tuesday, September 29, 2020 12:09 PM > >To: u-boot@lists.denx.de; Priyanka Jain (OSS) > >; Varun Sethi ; Meenakshi > >Aggarwal > >Cc: Wasim Khan > >Subject: [PATCH] armv8: lx2162aqds: disable non existing pcie > >controllers > > > >disable non existing pcie controllers on lx2162aqds > > > >Signed-off-by: Wasim Khan > >--- > LX2162QDS base support is now merged in fsl-qoriq tree. > https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq > > Kindly rebase this patch. https://patchwork.ozlabs.org/project/uboot/patch/1607677011-15059-1-git-send-email-wasim.k...@nxp.com/ > > Regards > Priyanka
[PATCH v2] armv8: lx2162aqds: disable non existing pcie controllers
disable non existing pcie controllers on lx2162aqds
Signed-off-by: Wasim Khan
---
Changes in v2:
- Rebased to u-boot-fsl-qoriq
arch/arm/dts/fsl-lx2162a-qds.dts | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts
index b165265..a2592c9 100644
--- a/arch/arm/dts/fsl-lx2162a-qds.dts
+++ b/arch/arm/dts/fsl-lx2162a-qds.dts
@@ -13,22 +13,20 @@
/ {
model = "NXP Layerscape LX2162AQDS Board";
compatible = "fsl,lx2162aqds", "fsl,lx2160a";
+};
- aliases {
- pcie@350 {
- status = "disabled";
- };
+ {
+ status = "disabled";
+};
- pcie@380 {
- status = "disabled";
- };
+ {
+ status = "disabled";
+};
- pcie@390 {
- status = "disabled";
- };
- };
+ {
+ status = "disabled";
};
- {
+ {
status = "disabled";
};
--
2.7.4
RE: [PATCH v2] arm: fsl: common: Improve NXP VID driver PMBus support
-Original Message- From: U-Boot On Behalf Of Priyanka Jain Sent: Monday, December 7, 2020 5:56 PM To: Stephen Carlson ; U-Boot Mailing List Subject: RE: [PATCH v2] arm: fsl: common: Improve NXP VID driver PMBus support >-Original Message- >From: Stephen Carlson >Sent: Tuesday, November 3, 2020 3:06 AM >To: U-Boot Mailing List >Cc: Priyanka Jain >Subject: [PATCH v2] arm: fsl: common: Improve NXP VID driver PMBus >support > >This patch adds support for more PMBus compatible devices to the NXP >drivers for its QorIQ family devices. At runtime, the voltage regulator >is queried over I2C, and the required voltage multiplier determined. >This change supports the DIRECT and LINEAR PMBus voltage reporting modes. > >Previously, the driver only supported a few specific devices such as >the >IR36021 and LTC3882, so this change allows the QorIQ series to be used >with a much larger variety of core voltage regulator devices. > >checkpatch warning "Use if (IS_DEFINED (...))" was ignored to maintain >consistency with the existing code. Hi Shephen, Can you please help to fix the checkpatch warnings . Even a additional patch on top should work. > >Signed-off-by: Stephen Carlson >Cc: Priyanka Jain >--- Kindly help to rebase the patch to master branch of u-boot tree (git://git.denx.de/u-boot.git). Regards Priyanka
[PATCH] armv8: lx2162aqds: disable non existing pcie controllers
disable non existing pcie controllers on lx2162aqds
Signed-off-by: Wasim Khan
---
Depends on https://patchwork.ozlabs.org/project/uboot/list/?series=199900
arch/arm/dts/fsl-lx2162a-qds.dts | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts
index 2195607..42113ed 100644
--- a/arch/arm/dts/fsl-lx2162a-qds.dts
+++ b/arch/arm/dts/fsl-lx2162a-qds.dts
@@ -16,21 +16,21 @@
aliases {
spi0 =
+ };
+};
- pcie@350 {
- status = "disabled";
- };
+ {
+ status = "disabled";
+};
- pcie@380 {
- status = "disabled";
- };
+ {
+ status = "disabled";
+};
- pcie@390 {
- status = "disabled";
- };
- };
+ {
+ status = "disabled";
};
- {
+ {
status = "disabled";
};
--
2.7.4
[PATCH v2 12/12] pci: ls_pcie_g4: Add size check for config resource
resource "config" is required to have minimum 4KB space
to access all config space of PCI Express EP.
Signed-off-by: Wasim Khan
---
Changes in V2:
- Updated commit description
- Fix CheckPatch issue
- Change size check to 4KB to access PCIe config space
Changes in V3:
- No Change
drivers/pci/pcie_layerscape_gen4.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/pci/pcie_layerscape_gen4.c
b/drivers/pci/pcie_layerscape_gen4.c
index 0226bde..6e71173 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -455,6 +455,7 @@ static int ls_pcie_g4_probe(struct udevice *dev)
u32 link_ctrl_sta;
u32 val;
int ret;
+ fdt_size_t cfg_size;
pcie->bus = dev;
@@ -488,6 +489,13 @@ static int ls_pcie_g4_probe(struct udevice *dev)
return ret;
}
+ cfg_size = fdt_resource_size(>cfg_res);
+ if (cfg_size < SZ_4K) {
+ printf("PCIe%d: %s Invalid size(0x%llx) for resource
\"config\",expected minimum 0x%x\n",
+ PCIE_SRDS_PRTCL(pcie->idx), dev->name, cfg_size, SZ_4K);
+ return 0;
+ }
+
pcie->cfg = map_physmem(pcie->cfg_res.start,
fdt_resource_size(>cfg_res),
MAP_NOCACHE);
--
2.7.4
[PATCH v2 10/12] arm: dts: ls1028a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan
---
Changes in V2:
- Updated commit description
Changes in V3:
- No Change
arch/arm/dts/fsl-ls1028a.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 9911690..ccf1a8d 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -2,7 +2,7 @@
/*
* NXP ls1028a SOC common device tree source
*
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
*
*/
@@ -85,7 +85,7 @@
status = "disabled";
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8
0x00 0x0348 0x0 0x4 /* lut registers */
@@ -101,7 +101,7 @@
0x8200 0x0 0x4000 0x80 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@350 {
+ pcie2: pcie@350 {
compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x8
0x00 0x0358 0x0 0x4 /* lut registers */
--
2.7.4
[PATCH v2 09/12] arm: dts: ls1043a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan
---
Changes in V2:
- Updated commit description
Changes in V3:
- No Change
arch/arm/dts/fsl-ls1043a.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index f7db44c..8ca57ea 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -1,7 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ * Device Tree Include file for NXP Layerscape-1043A family SoC.
*
+ * Copyright 2020 NXP
* Copyright (C) 2014-2015, Freescale Semiconductor
*
* Mingkai Hu
@@ -240,7 +241,7 @@
dr_mode = "host";
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x1 /* dbi registers */
0x00 0x0341 0x0 0x1 /* lut registers */
@@ -255,7 +256,7 @@
0x8200 0x0 0x4000 0x40 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@350 {
+ pcie2: pcie@350 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x1 /* dbi registers */
0x00 0x0351 0x0 0x1 /* lut registers */
@@ -271,7 +272,7 @@
0x8200 0x0 0x4000 0x48 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@360 {
+ pcie3: pcie@360 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0360 0x0 0x1 /* dbi registers */
0x00 0x0361 0x0 0x1 /* lut registers */
--
2.7.4
[PATCH v2 07/12] arm: dts: ls1088a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan
---
Changes in V2:
- Updated commit description
Changes in V3:
- No Change
arch/arm/dts/fsl-ls1088a.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index bf303c6..8de7998 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -2,7 +2,7 @@
/*
* NXP ls1088a SOC common device tree source
*
- * Copyright 2017 NXP
+ * Copyright 2017, 2020 NXP
*/
/ {
@@ -129,7 +129,7 @@
dr_mode = "host";
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8 /* dbi registers */
0x00 0x0348 0x0 0x8 /* lut registers */
@@ -145,7 +145,7 @@
0x8200 0x0 0x4000 0x20 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@350 {
+ pcie2: pcie@350 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x8 /* dbi registers */
0x00 0x0358 0x0 0x8 /* lut registers */
@@ -161,7 +161,7 @@
0x8200 0x0 0x4000 0x28 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@360 {
+ pcie3: pcie@360 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0360 0x0 0x8 /* dbi registers */
0x00 0x0368 0x0 0x8 /* lut registers */
--
2.7.4
[PATCH v2 08/12] arm: dts: ls1012a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan
---
Changes in V2:
- Updated commit description
Changes in V3:
- No Change
arch/arm/dts/fsl-ls1012a.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 2d70c82..c401ba3 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
+ * Copyright 2020 NXP
* Copyright 2016 Freescale Semiconductor
*/
@@ -116,7 +117,7 @@
status = "disabled";
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8 /* dbi registers */
0x00 0x0348 0x0 0x4 /* lut registers */
--
2.7.4
[PATCH v2 11/12] pci: layerscape: Add size check for config resource
resource "config" is required to have minimum 8KB space
as per hardware documentation.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Wasim Khan
---
Changes in V2:
- Updated commit description
- Fix CheckPatch issue
Changes in V3:
- Fix compilation issue with ls102xa platforms
drivers/pci/pcie_layerscape_rc.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index f9e3089..cdfcad6 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -314,6 +314,13 @@ static int ls_pcie_probe(struct udevice *dev)
return ret;
}
+ cfg_size = fdt_resource_size(_rc->cfg_res);
+ if (cfg_size < SZ_8K) {
+ printf("PCIe%d: %s Invalid size(0x%llx) for resource
\"config\",expected minimum 0x%x\n",
+ PCIE_SRDS_PRTCL(pcie->idx), dev->name, (u64)cfg_size,
SZ_8K);
+ return 0;
+ }
+
/*
* Fix the pcie memory map address and PF control registers address
* for LS2088A series SoCs
@@ -323,7 +330,6 @@ static int ls_pcie_probe(struct udevice *dev)
if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
svr == SVR_LS2048A || svr == SVR_LS2044A ||
svr == SVR_LS2081A || svr == SVR_LS2041A) {
- cfg_size = fdt_resource_size(_rc->cfg_res);
pcie_rc->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
LS2088A_PCIE_PHYS_SIZE * pcie->idx;
pcie_rc->cfg_res.end = pcie_rc->cfg_res.start + cfg_size;
--
2.7.4
[PATCH v2 05/12] arm: dts: ls1046a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan
---
Changes in V2:
- Updated commit description
Changes in V3:
- No Change
arch/arm/dts/fsl-ls1046a.dtsi | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 3f11d6c..155455d 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -241,7 +241,7 @@
dr_mode = "host";
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8 /* dbi registers */
0x00 0x0348 0x0 0x4 /* lut registers */
@@ -257,7 +257,7 @@
0x8200 0x0 0x4000 0x40 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie_ep@340 {
+ pcie_ep1: pcie_ep@340 {
compatible = "fsl,ls-pcie-ep";
reg = <0x00 0x0340 0x0 0x8
0x00 0x034c 0x0 0x4
@@ -268,7 +268,7 @@
big-endian;
};
- pcie@350 {
+ pcie2: pcie@350 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x8 /* dbi registers */
0x00 0x0358 0x0 0x4 /* lut registers */
@@ -285,7 +285,7 @@
0x8200 0x0 0x4000 0x48 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie_ep@350 {
+ pcie_ep2: pcie_ep@350 {
compatible = "fsl,ls-pcie-ep";
reg = <0x00 0x0350 0x0 0x8
0x00 0x035c 0x0 0x4
@@ -296,7 +296,7 @@
big-endian;
};
- pcie@360 {
+ pcie3: pcie@360 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0360 0x0 0x8 /* dbi registers */
0x00 0x0368 0x0 0x4 /* lut registers */
@@ -312,7 +312,7 @@
0x8200 0x0 0x4000 0x50 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie_ep@360 {
+ pcie_ep3: pcie_ep@360 {
compatible = "fsl,ls-pcie-ep";
reg = <0x00 0x0360 0x0 0x8
0x00 0x036c 0x0 0x4
--
2.7.4
[PATCH v2 02/12] pci: layerscape: Print pcie controller number starting from 1
Print pcie controller number starting from 1
Signed-off-by: Wasim Khan
---
Changes in V2:
- No Change
Changes in V3:
- No Change
drivers/pci/pcie_layerscape_ep.c | 4 +++-
drivers/pci/pcie_layerscape_rc.c | 6 --
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index eba230e..26c04a9 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
#include
@@ -294,7 +295,8 @@ static int ls_pcie_ep_probe(struct udevice *dev)
pcie_ep->num_ob_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"num-ob-windows", 8);
- printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+ printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+ "Endpoint");
ls_pcie_setup_ep(pcie_ep);
if (!ls_pcie_link_up(pcie)) {
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index 25c6dde..f9e3089 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -273,7 +273,8 @@ static int ls_pcie_probe(struct udevice *dev)
pcie_rc->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
if (!pcie_rc->enabled) {
- printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+ printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx),
+ dev->name);
return 0;
}
@@ -342,7 +343,8 @@ static int ls_pcie_probe(struct udevice *dev)
(unsigned long)pcie->ctrl, (unsigned long)pcie_rc->cfg0,
pcie->big_endian);
- printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+ printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+ "Root Complex");
ls_pcie_setup_ctrl(pcie_rc);
if (!ls_pcie_link_up(pcie)) {
--
2.7.4
[PATCH v2 06/12] arm: dts: ls2080a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan
---
Changes in V2:
- Updated commit description
Changes in V3:
- No Change
arch/arm/dts/fsl-ls2080a.dtsi | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 90a0a3f..fae46c4 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -1,7 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Freescale ls2080a SOC common device tree source
+ * NXP ls2080a SOC common device tree source
*
+ * Copyright 2020 NXP
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*/
@@ -127,7 +128,7 @@
dr_mode = "host";
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8 /* dbi registers */
0x00 0x0348 0x0 0x8 /* lut registers */
@@ -142,7 +143,7 @@
0x8200 0x0 0x4000 0x10 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@350 {
+ pcie2: pcie@350 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x8 /* dbi registers */
0x00 0x0358 0x0 0x8 /* lut registers */
@@ -157,7 +158,7 @@
0x8200 0x0 0x4000 0x12 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@360 {
+ pcie3: pcie@360 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0360 0x0 0x8 /* dbi registers */
0x00 0x0368 0x0 0x8 /* lut registers */
@@ -172,7 +173,7 @@
0x8200 0x0 0x4000 0x14 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@370 {
+ pcie4: pcie@370 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0370 0x0 0x8 /* dbi registers */
0x00 0x0378 0x0 0x8 /* lut registers */
--
2.7.4
[PATCH v2 03/12] pci: ls_pcie_g4: Print pcie controller number starting from 1
Print pcie controller number starting from 1
Signed-off-by: Wasim Khan
---
Changes in V2:
- No Change
Changes in V3:
- No Change
drivers/pci/pcie_layerscape_gen4.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_gen4.c
b/drivers/pci/pcie_layerscape_gen4.c
index 428bfca..0226bde 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
*
* PCIe Gen4 driver for NXP Layerscape SoCs
* Author: Hou Zhiqiang
@@ -472,7 +472,8 @@ static int ls_pcie_g4_probe(struct udevice *dev)
pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
if (!pcie->enabled) {
- printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+ printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx),
+ dev->name);
return 0;
}
@@ -522,10 +523,12 @@ static int ls_pcie_g4_probe(struct udevice *dev)
pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f;
if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
- printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+ printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+ "Endpoint");
ls_pcie_g4_setup_ep(pcie);
} else {
- printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+ printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+ "Root Complex");
ls_pcie_g4_setup_ctrl(pcie);
}
--
2.7.4
[PATCH v2 00/12] Add label to pcie nodes
This patch series - Adds label to pcie nodes in dts file for NXP's layerscape SoCs - Print the pcie controller number starting from 1 to match RMs - Add checks for config resource size and fix indendation. Changes in V2: - Enable CONFIG_PCIE_LAYERSCAPE_GEN4 to make LX2160A-Rev1 work - Fix CheckPatch issues - Change 1KB size check to 4KB size check for ls_pcie_g4. - Commit description updates Changes in V3: - fix compilation issue on ls102xa platforms Wasim Khan (12): configs: lx2160a: Enable CONFIG_PCIE_LAYERSCAPE_GEN4 pci: layerscape: Print pcie controller number starting from 1 pci: ls_pcie_g4: Print pcie controller number starting from 1 arm: dts: lx2160a: add label to pcie nodes in dts arm: dts: ls1046a: add label to pcie nodes in dts arm: dts: ls2080a: add label to pcie nodes in dts arm: dts: ls1088a: add label to pcie nodes in dts arm: dts: ls1012a: add label to pcie nodes in dts arm: dts: ls1043a: add label to pcie nodes in dts arm: dts: ls1028a: add label to pcie nodes in dts pci: layerscape: Add size check for config resource pci: ls_pcie_g4: Add size check for config resource arch/arm/dts/fsl-ls1012a.dtsi| 3 ++- arch/arm/dts/fsl-ls1028a.dtsi| 6 +++--- arch/arm/dts/fsl-ls1043a.dtsi| 9 + arch/arm/dts/fsl-ls1046a.dtsi| 12 ++-- arch/arm/dts/fsl-ls1088a.dtsi| 8 arch/arm/dts/fsl-ls2080a.dtsi| 11 ++- arch/arm/dts/fsl-lx2160a.dtsi| 12 ++-- configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + configs/lx2160ardb_tfa_stmm_defconfig| 1 + drivers/pci/pcie_layerscape_ep.c | 4 +++- drivers/pci/pcie_layerscape_gen4.c | 19 +++ drivers/pci/pcie_layerscape_rc.c | 14 +++--- 15 files changed, 66 insertions(+), 37 deletions(-) -- 2.7.4
[PATCH v2 01/12] configs: lx2160a: Enable CONFIG_PCIE_LAYERSCAPE_GEN4
LX2160A-Rev1 uses PCIe layerscape Gen4 controller. Enable CONFIG_PCIE_LAYERSCAPE_GEN4 for lx2160a. Signed-off-by: Wasim Khan --- Changes in V2: - Added as new commit in V2 Changes in V3: - No Change configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + configs/lx2160ardb_tfa_stmm_defconfig| 1 + 5 files changed, 5 insertions(+) diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 06d84be..7aa2f94 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -68,6 +68,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index af010af..a553fa7 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -75,6 +75,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index 5e30890..7f30922 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -59,6 +59,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 7021223..c882a5a 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -66,6 +66,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index b0dc3c0..e07c7a8 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -68,6 +68,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y -- 2.7.4
[PATCH v2 04/12] arm: dts: lx2160a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan
---
Changes in V2:
- Updated commit description
Changes in V3:
- No Change
arch/arm/dts/fsl-lx2160a.dtsi | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index dee1e2f..69fcc0c 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -286,7 +286,7 @@
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0340 0x0 0x8 /* PAB registers */
0x00 0x0348 0x0 0x4 /* LUT registers */
@@ -300,7 +300,7 @@
ranges = <0x8200 0x0 0x4000 0x80 0x4000 0x0
0x4000>;
};
- pcie@350 {
+ pcie2: pcie@350 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0350 0x0 0x8 /* PAB registers */
0x00 0x0358 0x0 0x4 /* LUT registers */
@@ -315,7 +315,7 @@
ranges = <0x8200 0x0 0x4000 0x88 0x4000 0x0
0x4000>;
};
- pcie@360 {
+ pcie3: pcie@360 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0360 0x0 0x8 /* PAB registers */
0x00 0x0368 0x0 0x4 /* LUT registers */
@@ -329,7 +329,7 @@
ranges = <0x8200 0x0 0x4000 0x90 0x4000 0x0
0x4000>;
};
- pcie@370 {
+ pcie4: pcie@370 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0370 0x0 0x8 /* PAB registers */
0x00 0x0378 0x0 0x4 /* LUT registers */
@@ -343,7 +343,7 @@
ranges = <0x8200 0x0 0x4000 0x98 0x4000 0x0
0x4000>;
};
- pcie@380 {
+ pcie5: pcie@380 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0380 0x0 0x8 /* PAB registers */
0x00 0x0388 0x0 0x4 /* LUT registers */
@@ -357,7 +357,7 @@
ranges = <0x8200 0x0 0x4000 0xa0 0x4000 0x0
0x4000>;
};
- pcie@390 {
+ pcie6: pcie@390 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0390 0x0 0x8 /* PAB registers */
0x00 0x0398 0x0 0x4 /* LUT registers */
--
2.7.4
[PATCH v2] arm: dts: lx2160a: Add IO range
Add IO range property to fix below error on uboot
PCI: Failed autoconfig bar 18
Signed-off-by: Wasim Khan
---
Changes in v2:
- Updated commit subject
arch/arm/dts/fsl-lx2160a.dtsi | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index dee1e2f..70efbbf 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -297,7 +297,8 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
- ranges = <0x8200 0x0 0x4000 0x80 0x4000 0x0
0x4000>;
+ ranges = <0x8100 0x0 0x 0x80 0x0002 0x0
0x0001 /* downstream I/O */
+ 0x8200 0x0 0x4000 0x80 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
pcie@350 {
@@ -312,7 +313,8 @@
device_type = "pci";
num-lanes = <2>;
bus-range = <0x0 0xff>;
- ranges = <0x8200 0x0 0x4000 0x88 0x4000 0x0
0x4000>;
+ ranges = <0x8100 0x0 0x 0x88 0x0002 0x0
0x0001 /* downstream I/O */
+ 0x8200 0x0 0x4000 0x88 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
pcie@360 {
@@ -326,7 +328,8 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
- ranges = <0x8200 0x0 0x4000 0x90 0x4000 0x0
0x4000>;
+ ranges = <0x8100 0x0 0x 0x90 0x0002 0x0
0x0001 /* downstream I/O */
+ 0x8200 0x0 0x4000 0x90 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
pcie@370 {
@@ -340,7 +343,8 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
- ranges = <0x8200 0x0 0x4000 0x98 0x4000 0x0
0x4000>;
+ ranges = <0x8100 0x0 0x 0x98 0x0002 0x0
0x0001 /* downstream I/O */
+ 0x8200 0x0 0x4000 0x98 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
pcie@380 {
@@ -354,7 +358,8 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
- ranges = <0x8200 0x0 0x4000 0xa0 0x4000 0x0
0x4000>;
+ ranges = <0x8100 0x0 0x 0xa0 0x0002 0x0
0x0001 /* downstream I/O */
+ 0x8200 0x0 0x4000 0xa0 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
pcie@390 {
@@ -368,7 +373,8 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
- ranges = <0x8200 0x0 0x4000 0xa8 0x4000 0x0
0x4000>;
+ ranges = <0x8100 0x0 0x 0xa8 0x0002 0x0
0x0001 /* downstream I/O */
+ 0x8200 0x0 0x4000 0xa8 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
fsl_mc: fsl-mc@80c00 {
--
2.7.4
[PATCH v2] configs: Enable NVME support for Layerscape platforms
Enable CONFIG_NVME and CONFIG_CMD_NVME for Layerscape platforms Signed-off-by: Wasim Khan --- Changes in v2: - Updated commit subject and description configs/ls1012afrdm_qspi_defconfig | 2 ++ configs/ls1012afrdm_tfa_defconfig| 2 ++ configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1012afrwy_qspi_defconfig | 2 ++ configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig| 2 ++ configs/ls1012afrwy_tfa_defconfig| 2 ++ configs/ls1012aqds_qspi_defconfig| 2 ++ configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1012aqds_tfa_defconfig | 2 ++ configs/ls1012ardb_qspi_SECURE_BOOT_defconfig| 2 ++ configs/ls1012ardb_qspi_defconfig| 2 ++ configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1012ardb_tfa_defconfig | 2 ++ configs/ls1021aiot_qspi_defconfig| 2 ++ configs/ls1021aiot_sdcard_defconfig | 2 ++ configs/ls1021aqds_ddr4_nor_defconfig| 2 ++ configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 2 ++ configs/ls1021aqds_nand_defconfig| 2 ++ configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 2 ++ configs/ls1021aqds_nor_defconfig | 2 ++ configs/ls1021aqds_nor_lpuart_defconfig | 2 ++ configs/ls1021aqds_qspi_defconfig| 2 ++ configs/ls1021aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1021aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1021atsn_qspi_defconfig| 2 ++ configs/ls1021atsn_sdcard_defconfig | 2 ++ configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 ++ configs/ls1021atwr_nor_defconfig | 2 ++ configs/ls1021atwr_nor_lpuart_defconfig | 2 ++ configs/ls1021atwr_qspi_defconfig| 2 ++ configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 ++ configs/ls1021atwr_sdcard_ifc_defconfig | 2 ++ configs/ls1021atwr_sdcard_qspi_defconfig | 2 ++ configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1028aqds_tfa_defconfig | 2 ++ configs/ls1028aqds_tfa_lpuart_defconfig | 2 ++ configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1028ardb_tfa_defconfig | 2 ++ configs/ls1043aqds_defconfig | 2 ++ configs/ls1043aqds_lpuart_defconfig | 2 ++ configs/ls1043aqds_nand_defconfig| 2 ++ configs/ls1043aqds_nor_ddr3_defconfig| 2 ++ configs/ls1043aqds_qspi_defconfig| 2 ++ configs/ls1043aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1043aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1043aqds_tfa_defconfig | 2 ++ configs/ls1043ardb_SECURE_BOOT_defconfig | 2 ++ configs/ls1043ardb_defconfig | 2 ++ configs/ls1043ardb_nand_SECURE_BOOT_defconfig| 2 ++ configs/ls1043ardb_nand_defconfig| 2 ++ configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 2 ++ configs/ls1043ardb_sdcard_defconfig | 2 ++ configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1043ardb_tfa_defconfig | 2 ++ configs/ls1046afrwy_tfa_defconfig| 2 ++ configs/ls1046aqds_SECURE_BOOT_defconfig | 2 ++ configs/ls1046aqds_defconfig | 2 ++ configs/ls1046aqds_lpuart_defconfig | 2 ++ configs/ls1046aqds_nand_defconfig| 2 ++ configs/ls1046aqds_qspi_defconfig| 2 ++ configs/ls1046aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1046aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1046aqds_tfa_defconfig | 2 ++ configs/ls1046ardb_emmc_defconfig| 2 ++ configs/ls1046ardb_qspi_SECURE_BOOT_defconfig| 2 ++ configs/ls1046ardb_qspi_defconfig| 2 ++ configs/ls1046ardb_qspi_spl_defconfig| 2 ++ configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 2 ++ configs/ls1046ardb_sdcard_defconfig | 2 ++ configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1046ardb_tfa_defconfig | 2 ++ configs/ls1088aqds_defconfig | 2 ++ configs/ls1088aqds_qspi_SECURE_BOOT_defconfig| 2 ++ configs/ls1088aqds_qspi_defconfig| 2 ++ configs/ls1088aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1088aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1088aqds_tfa_defconfig | 2 ++ configs
[PATCH v2] board: freescale: emc2305: Pass chip_addr to set_fan_speed
emc2305 is a common driver. It should not use platform specific
i2c address for slave device.
Pass chip_addr as agrument to emc2305_init() and set_fan_speed()
so that emc2305 driver can be used with different platforms.
Signed-off-by: Wasim Khan
---
Changes in v2:
- Update commit subject
board/freescale/common/emc2305.c | 15 +++
board/freescale/common/emc2305.h | 7 +++
board/freescale/lx2160a/lx2160a.c | 4 ++--
3 files changed, 12 insertions(+), 14 deletions(-)
diff --git a/board/freescale/common/emc2305.c b/board/freescale/common/emc2305.c
index b1ca051..050b679 100644
--- a/board/freescale/common/emc2305.c
+++ b/board/freescale/common/emc2305.c
@@ -1,8 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP.
+ * Copyright 2018-2020 NXP.
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include
@@ -14,7 +13,7 @@
DECLARE_GLOBAL_DATA_PTR;
-void set_fan_speed(u8 data)
+void set_fan_speed(u8 data, int chip_addr)
{
u8 index;
u8 Fan[NUM_OF_FANS] = {I2C_EMC2305_FAN1,
@@ -25,14 +24,14 @@ void set_fan_speed(u8 data)
for (index = 0; index < NUM_OF_FANS; index++) {
#ifndef CONFIG_DM_I2C
- if (i2c_write(I2C_EMC2305_ADDR, Fan[index], 1, , 1) != 0) {
+ if (i2c_write(chip_addr, Fan[index], 1, , 1) != 0) {
printf("Error: failed to change fan speed @%x\n",
Fan[index]);
}
#else
struct udevice *dev;
- if (i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, ))
+ if (i2c_get_chip_for_busnum(0, chip_addr, 1, ))
continue;
if (dm_i2c_write(dev, Fan[index], , 1) != 0) {
@@ -43,18 +42,18 @@ void set_fan_speed(u8 data)
}
}
-void emc2305_init(void)
+void emc2305_init(int chip_addr)
{
u8 data;
data = I2C_EMC2305_CMD;
#ifndef CONFIG_DM_I2C
- if (i2c_write(I2C_EMC2305_ADDR, I2C_EMC2305_CONF, 1, , 1) != 0)
+ if (i2c_write(chip_addr, I2C_EMC2305_CONF, 1, , 1) != 0)
printf("Error: failed to configure EMC2305\n");
#else
struct udevice *dev;
- if (!i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, ))
+ if (!i2c_get_chip_for_busnum(0, chip_addr, 1, ))
if (dm_i2c_write(dev, I2C_EMC2305_CONF, , 1))
printf("Error: failed to configure EMC2305\n");
#endif
diff --git a/board/freescale/common/emc2305.h b/board/freescale/common/emc2305.h
index eddf537..24c5410 100644
--- a/board/freescale/common/emc2305.h
+++ b/board/freescale/common/emc2305.h
@@ -1,8 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __EMC2305_H_
@@ -17,7 +16,7 @@
#define NUM_OF_FANS5
-void emc2305_init(void);
-void set_fan_speed(u8 data);
+void emc2305_init(int chip_addr);
+void set_fan_speed(u8 data, int chip_addr);
#endif /* __EMC2305_H_ */
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index ace2a19..0ff987e 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -114,8 +114,8 @@ int board_early_init_f(void)
#ifdef CONFIG_EMC2305
select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
- emc2305_init();
- set_fan_speed(I2C_EMC2305_PWM);
+ emc2305_init(I2C_EMC2305_ADDR);
+ set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
#endif
--
2.7.4
[PATCH v2] board/freescale: emc2305: Pass chip_addr emc2305_init() and set_fan_speed()
emc2305 is a common driver. It should not use platform specific
i2c address for slave device.
Pass chip_addr as agrument to emc2305_init() and set_fan_speed()
so that emc2305 driver can be used with different platforms.
Signed-off-by: Wasim Khan
---
Changes in V2:
- Pass chip_addr to emc2305_init() also
- Updated commit message
board/freescale/common/emc2305.c | 15 +++
board/freescale/common/emc2305.h | 7 +++
board/freescale/lx2160a/lx2160a.c | 4 ++--
3 files changed, 12 insertions(+), 14 deletions(-)
diff --git a/board/freescale/common/emc2305.c b/board/freescale/common/emc2305.c
index b1ca051..050b679 100644
--- a/board/freescale/common/emc2305.c
+++ b/board/freescale/common/emc2305.c
@@ -1,8 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP.
+ * Copyright 2018-2020 NXP.
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include
@@ -14,7 +13,7 @@
DECLARE_GLOBAL_DATA_PTR;
-void set_fan_speed(u8 data)
+void set_fan_speed(u8 data, int chip_addr)
{
u8 index;
u8 Fan[NUM_OF_FANS] = {I2C_EMC2305_FAN1,
@@ -25,14 +24,14 @@ void set_fan_speed(u8 data)
for (index = 0; index < NUM_OF_FANS; index++) {
#ifndef CONFIG_DM_I2C
- if (i2c_write(I2C_EMC2305_ADDR, Fan[index], 1, , 1) != 0) {
+ if (i2c_write(chip_addr, Fan[index], 1, , 1) != 0) {
printf("Error: failed to change fan speed @%x\n",
Fan[index]);
}
#else
struct udevice *dev;
- if (i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, ))
+ if (i2c_get_chip_for_busnum(0, chip_addr, 1, ))
continue;
if (dm_i2c_write(dev, Fan[index], , 1) != 0) {
@@ -43,18 +42,18 @@ void set_fan_speed(u8 data)
}
}
-void emc2305_init(void)
+void emc2305_init(int chip_addr)
{
u8 data;
data = I2C_EMC2305_CMD;
#ifndef CONFIG_DM_I2C
- if (i2c_write(I2C_EMC2305_ADDR, I2C_EMC2305_CONF, 1, , 1) != 0)
+ if (i2c_write(chip_addr, I2C_EMC2305_CONF, 1, , 1) != 0)
printf("Error: failed to configure EMC2305\n");
#else
struct udevice *dev;
- if (!i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, ))
+ if (!i2c_get_chip_for_busnum(0, chip_addr, 1, ))
if (dm_i2c_write(dev, I2C_EMC2305_CONF, , 1))
printf("Error: failed to configure EMC2305\n");
#endif
diff --git a/board/freescale/common/emc2305.h b/board/freescale/common/emc2305.h
index eddf537..24c5410 100644
--- a/board/freescale/common/emc2305.h
+++ b/board/freescale/common/emc2305.h
@@ -1,8 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __EMC2305_H_
@@ -17,7 +16,7 @@
#define NUM_OF_FANS5
-void emc2305_init(void);
-void set_fan_speed(u8 data);
+void emc2305_init(int chip_addr);
+void set_fan_speed(u8 data, int chip_addr);
#endif /* __EMC2305_H_ */
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index ace2a19..0ff987e 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -114,8 +114,8 @@ int board_early_init_f(void)
#ifdef CONFIG_EMC2305
select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
- emc2305_init();
- set_fan_speed(I2C_EMC2305_PWM);
+ emc2305_init(I2C_EMC2305_ADDR);
+ set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
#endif
--
2.7.4
[PATCH] board/freescale/common: emc2305: Pass chip_addr to set_fan_speed()
emc2305 is a common driver. It should not use platform specific
i2c address for slave device.
Pass chip_addr as agrument to set_fan_speed() so that emc2305 driver
can be used with different platforms.
Signed-off-by: Wasim Khan
---
board/freescale/common/emc2305.c | 9 -
board/freescale/common/emc2305.h | 5 ++---
board/freescale/lx2160a/lx2160a.c | 2 +-
3 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/board/freescale/common/emc2305.c b/board/freescale/common/emc2305.c
index b1ca051..7dd49c5 100644
--- a/board/freescale/common/emc2305.c
+++ b/board/freescale/common/emc2305.c
@@ -1,8 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP.
+ * Copyright 2018-2020 NXP.
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include
@@ -14,7 +13,7 @@
DECLARE_GLOBAL_DATA_PTR;
-void set_fan_speed(u8 data)
+void set_fan_speed(u8 data, int chip_addr)
{
u8 index;
u8 Fan[NUM_OF_FANS] = {I2C_EMC2305_FAN1,
@@ -25,14 +24,14 @@ void set_fan_speed(u8 data)
for (index = 0; index < NUM_OF_FANS; index++) {
#ifndef CONFIG_DM_I2C
- if (i2c_write(I2C_EMC2305_ADDR, Fan[index], 1, , 1) != 0) {
+ if (i2c_write(chip_addr, Fan[index], 1, , 1) != 0) {
printf("Error: failed to change fan speed @%x\n",
Fan[index]);
}
#else
struct udevice *dev;
- if (i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, ))
+ if (i2c_get_chip_for_busnum(0, chip_addr, 1, ))
continue;
if (dm_i2c_write(dev, Fan[index], , 1) != 0) {
diff --git a/board/freescale/common/emc2305.h b/board/freescale/common/emc2305.h
index eddf537..f730c49 100644
--- a/board/freescale/common/emc2305.h
+++ b/board/freescale/common/emc2305.h
@@ -1,8 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __EMC2305_H_
@@ -18,6 +17,6 @@
#define NUM_OF_FANS5
void emc2305_init(void);
-void set_fan_speed(u8 data);
+void set_fan_speed(u8 data, int chip_addr);
#endif /* __EMC2305_H_ */
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index ace2a19..06c00ea 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -115,7 +115,7 @@ int board_early_init_f(void)
#ifdef CONFIG_EMC2305
select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
emc2305_init();
- set_fan_speed(I2C_EMC2305_PWM);
+ set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
#endif
--
2.7.4
[PATCH] configs: Enable NVME support for NXP platforms
Enable CONFIG_NVME and CONFIG_CMD_NVME for NXP platforms Signed-off-by: Wasim Khan --- configs/ls1012afrdm_qspi_defconfig | 2 ++ configs/ls1012afrdm_tfa_defconfig| 2 ++ configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1012afrwy_qspi_defconfig | 2 ++ configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig| 2 ++ configs/ls1012afrwy_tfa_defconfig| 2 ++ configs/ls1012aqds_qspi_defconfig| 2 ++ configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1012aqds_tfa_defconfig | 2 ++ configs/ls1012ardb_qspi_SECURE_BOOT_defconfig| 2 ++ configs/ls1012ardb_qspi_defconfig| 2 ++ configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1012ardb_tfa_defconfig | 2 ++ configs/ls1021aiot_qspi_defconfig| 2 ++ configs/ls1021aiot_sdcard_defconfig | 2 ++ configs/ls1021aqds_ddr4_nor_defconfig| 2 ++ configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 2 ++ configs/ls1021aqds_nand_defconfig| 2 ++ configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 2 ++ configs/ls1021aqds_nor_defconfig | 2 ++ configs/ls1021aqds_nor_lpuart_defconfig | 2 ++ configs/ls1021aqds_qspi_defconfig| 2 ++ configs/ls1021aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1021aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1021atsn_qspi_defconfig| 2 ++ configs/ls1021atsn_sdcard_defconfig | 2 ++ configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 ++ configs/ls1021atwr_nor_defconfig | 2 ++ configs/ls1021atwr_nor_lpuart_defconfig | 2 ++ configs/ls1021atwr_qspi_defconfig| 2 ++ configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 ++ configs/ls1021atwr_sdcard_ifc_defconfig | 2 ++ configs/ls1021atwr_sdcard_qspi_defconfig | 2 ++ configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1028aqds_tfa_defconfig | 2 ++ configs/ls1028aqds_tfa_lpuart_defconfig | 2 ++ configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1028ardb_tfa_defconfig | 2 ++ configs/ls1043aqds_defconfig | 2 ++ configs/ls1043aqds_lpuart_defconfig | 2 ++ configs/ls1043aqds_nand_defconfig| 2 ++ configs/ls1043aqds_nor_ddr3_defconfig| 2 ++ configs/ls1043aqds_qspi_defconfig| 2 ++ configs/ls1043aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1043aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1043aqds_tfa_defconfig | 2 ++ configs/ls1043ardb_SECURE_BOOT_defconfig | 2 ++ configs/ls1043ardb_defconfig | 2 ++ configs/ls1043ardb_nand_SECURE_BOOT_defconfig| 2 ++ configs/ls1043ardb_nand_defconfig| 2 ++ configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 2 ++ configs/ls1043ardb_sdcard_defconfig | 2 ++ configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1043ardb_tfa_defconfig | 2 ++ configs/ls1046afrwy_tfa_defconfig| 2 ++ configs/ls1046aqds_SECURE_BOOT_defconfig | 2 ++ configs/ls1046aqds_defconfig | 2 ++ configs/ls1046aqds_lpuart_defconfig | 2 ++ configs/ls1046aqds_nand_defconfig| 2 ++ configs/ls1046aqds_qspi_defconfig| 2 ++ configs/ls1046aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1046aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1046aqds_tfa_defconfig | 2 ++ configs/ls1046ardb_emmc_defconfig| 2 ++ configs/ls1046ardb_qspi_SECURE_BOOT_defconfig| 2 ++ configs/ls1046ardb_qspi_defconfig| 2 ++ configs/ls1046ardb_qspi_spl_defconfig| 2 ++ configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 2 ++ configs/ls1046ardb_sdcard_defconfig | 2 ++ configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1046ardb_tfa_defconfig | 2 ++ configs/ls1088aqds_defconfig | 2 ++ configs/ls1088aqds_qspi_SECURE_BOOT_defconfig| 2 ++ configs/ls1088aqds_qspi_defconfig| 2 ++ configs/ls1088aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1088aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1088aqds_tfa_defconfig | 2 ++ configs/ls1088ardb_qspi_SECURE_BOOT_defconfig| 2 ++ configs
[PATCH] arm: dts: lx2160a: Add IO range
Add IO range property to fix below error on uboot
PCI: Failed autoconfig bar 18
Signed-off-by: Wasim Khan
---
arch/arm/dts/fsl-lx2160a.dtsi | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index dee1e2f..70efbbf 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -297,7 +297,8 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
- ranges = <0x8200 0x0 0x4000 0x80 0x4000 0x0
0x4000>;
+ ranges = <0x8100 0x0 0x 0x80 0x0002 0x0
0x0001 /* downstream I/O */
+ 0x8200 0x0 0x4000 0x80 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
pcie@350 {
@@ -312,7 +313,8 @@
device_type = "pci";
num-lanes = <2>;
bus-range = <0x0 0xff>;
- ranges = <0x8200 0x0 0x4000 0x88 0x4000 0x0
0x4000>;
+ ranges = <0x8100 0x0 0x 0x88 0x0002 0x0
0x0001 /* downstream I/O */
+ 0x8200 0x0 0x4000 0x88 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
pcie@360 {
@@ -326,7 +328,8 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
- ranges = <0x8200 0x0 0x4000 0x90 0x4000 0x0
0x4000>;
+ ranges = <0x8100 0x0 0x 0x90 0x0002 0x0
0x0001 /* downstream I/O */
+ 0x8200 0x0 0x4000 0x90 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
pcie@370 {
@@ -340,7 +343,8 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
- ranges = <0x8200 0x0 0x4000 0x98 0x4000 0x0
0x4000>;
+ ranges = <0x8100 0x0 0x 0x98 0x0002 0x0
0x0001 /* downstream I/O */
+ 0x8200 0x0 0x4000 0x98 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
pcie@380 {
@@ -354,7 +358,8 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
- ranges = <0x8200 0x0 0x4000 0xa0 0x4000 0x0
0x4000>;
+ ranges = <0x8100 0x0 0x 0xa0 0x0002 0x0
0x0001 /* downstream I/O */
+ 0x8200 0x0 0x4000 0xa0 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
pcie@390 {
@@ -368,7 +373,8 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
- ranges = <0x8200 0x0 0x4000 0xa8 0x4000 0x0
0x4000>;
+ ranges = <0x8100 0x0 0x 0xa8 0x0002 0x0
0x0001 /* downstream I/O */
+ 0x8200 0x0 0x4000 0xa8 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
fsl_mc: fsl-mc@80c00 {
--
2.7.4
[PATCH 1/2] board/freescale/vid: rework of VID support
The VID code does not properly set the voltages on all chips.
It does not properly reports voltage changes.
For IR, the read accuracy was incorrect and for
the LTC the step width was too wide.
This patchset fix above problems and also make LTC channel
use configurable to deal properly with single and dual
channel setups.
Signed-off-by: Dan Nica
Signed-off-by: Heinz Wrobel
Signed-off-by: Wasim Khan
---
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 19 +-
board/freescale/common/vid.c | 662 +++--
board/freescale/common/vid.h | 42 +-
3 files changed, 403 insertions(+), 320 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index baa9fa8..6147fad 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -2,7 +2,7 @@
/*
* LayerScape Internal Memory Map
*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
* Copyright 2014 Freescale Semiconductor, Inc.
*/
@@ -324,15 +324,14 @@ struct ccsr_gur {
u32 gpporcr3;
u32 gpporcr4;
u8 res_030[0x60-0x30];
-#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
-#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
-#if defined(CONFIG_ARCH_LS1088A)
-#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
-#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
-#else
-#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
-#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
-#endif
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK0x1F
+#define FSL_CHASSIS3_DCFG_FUSESR_LOW_VID_SHIFT 2
+#define FSL_CHASSIS3_DCFG_FUSESR_LOW_VID_MASK 0x1F
+#define FSL_CHASSIS3_DCFG_FUSESR_LOW_ALTVID_SHIFT 7
+#define FSL_CHASSIS3_DCFG_FUSESR_LOW_ALTVID_MASK0x1F
u32 dcfg_fusesr;/* Fuse status register */
u8 res_064[0x70-0x64];
u32 devdisr;/* Device disable control 1 */
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index ed0d9b4..0ba672d 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
*/
#include
@@ -20,6 +21,8 @@
#include
#include "vid.h"
+DECLARE_GLOBAL_DATA_PTR;
+
int __weak i2c_multiplexer_select_vid_channel(u8 channel)
{
return 0;
@@ -42,10 +45,8 @@ int __weak board_adjust_vdd(int vdd)
return 0;
}
-#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
- defined(CONFIG_VOL_MONITOR_IR36021_READ)
/*
- * Get the i2c address configuration for the IR regulator chip
+ * Get the i2c address configuration for the regulator chip
*
* There are some variance in the RDB HW regarding the I2C address
configuration
* for the IR regulator chip, which is likely a problem of external resistor
@@ -56,9 +57,14 @@ int __weak board_adjust_vdd(int vdd)
* 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA)
* 0x09 (Verified on T1040RDB-PA)
* 0x38 (Verified on T2080QDS, T2081QDS, T4240RDB)
+ *
+ * For other types of regulator chips, we check the IDs before we
+ * return the address to avoid making damaging mistakes
*/
-static int find_ir_chip_on_i2c(void)
+static int find_vid_chip_on_i2c(void)
{
+#if defined(CONFIG_VOL_MONITOR_IR36021_READ) || \
+ defined(CONFIG_VOL_MONITOR_IR36021_SET)
int i2caddress;
int ret;
u8 byte;
@@ -81,33 +87,75 @@ static int find_ir_chip_on_i2c(void)
ret = dm_i2c_read(dev, IR36021_MFR_ID_OFFSET,
(void *), sizeof(byte));
#endif
- if ((ret >= 0) && (byte == IR36021_MFR_ID))
+ if (!ret && byte == IR36021_MFR_ID)
+ return i2caddress;
+ }
+#endif
+#if defined(CONFIG_VOL_MONITOR_LTC3882_READ) || \
+ defined(CONFIG_VOL_MONITOR_LTC3882_SET)
+ int i2caddress = I2C_VOL_MONITOR_ADDR;
+ int ret;
+ u8 buf[8];
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
+
+#ifndef CONFIG_DM_I2C
+ ret = i2c_read(i2caddress,
+ LTC3882_MFR_ID, 1, (void *)[0],
+ 4);
+#else
+ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, );
+ if (!ret)
+ ret = dm_i2c_read(dev, LTC3882_MFR_ID,
+ (void *)[0], 4);
+#endif
+ if (!ret && memcmp(buf, "\3LTC", 4) == 0) {
+#ifndef CONFIG_DM_I2C
+ ret = i2c_read(i2caddress,
+ LTC3882_MFR_MODEL, 1, (void *)[0],
+ 8);
+#else
+ ret = i2c_get_chip_for_busnu
[PATCH 0/2] board/freescale/vid: rework of VID support
The VID code does not properly set the voltages on all chips. It does not properly reports voltage changes. For IR, the read accuracy was incorrect and for the LTC the step width was too wide. - This patchset rework the vid driver and make LTC channel use configurable to deal properly with single and dual channel setups. - Add support for LTC7132 Wasim Khan (2): board/freescale/vid: rework of VID support board/freescale/vid: Add support for LTC7132 voltage regulator .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 19 +- board/freescale/common/vid.c | 685 +++-- board/freescale/common/vid.h | 42 +- 3 files changed, 423 insertions(+), 323 deletions(-) -- 2.7.4
[PATCH 2/2] board/freescale/vid: Add support for LTC7132 voltage regulator
Add support for LTC7132 voltage regulator
Signed-off-by: Wasim Khan
Reviewed-by: Heinz Wrobel
---
board/freescale/common/vid.c | 121 ---
board/freescale/common/vid.h | 32 ++--
2 files changed, 85 insertions(+), 68 deletions(-)
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index 0ba672d..095781f 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -92,7 +92,9 @@ static int find_vid_chip_on_i2c(void)
}
#endif
#if defined(CONFIG_VOL_MONITOR_LTC3882_READ) || \
- defined(CONFIG_VOL_MONITOR_LTC3882_SET)
+ defined(CONFIG_VOL_MONITOR_LTC7132_READ) || \
+ defined(CONFIG_VOL_MONITOR_LTC3882_SET) || \
+ defined(CONFIG_VOL_MONITOR_LTC7132_SET)
int i2caddress = I2C_VOL_MONITOR_ADDR;
int ret;
u8 buf[8];
@@ -102,27 +104,35 @@ static int find_vid_chip_on_i2c(void)
#ifndef CONFIG_DM_I2C
ret = i2c_read(i2caddress,
- LTC3882_MFR_ID, 1, (void *)[0],
+ LTC_MFR_ID, 1, (void *)[0],
4);
#else
ret = i2c_get_chip_for_busnum(0, i2caddress, 1, );
if (!ret)
- ret = dm_i2c_read(dev, LTC3882_MFR_ID,
+ ret = dm_i2c_read(dev, LTC_MFR_ID,
(void *)[0], 4);
#endif
if (!ret && memcmp(buf, "\3LTC", 4) == 0) {
#ifndef CONFIG_DM_I2C
ret = i2c_read(i2caddress,
- LTC3882_MFR_MODEL, 1, (void *)[0],
+ LTC_MFR_MODEL, 1, (void *)[0],
8);
#else
ret = i2c_get_chip_for_busnum(0, i2caddress, 1, );
if (!ret)
- ret = dm_i2c_read(dev, LTC3882_MFR_MODEL,
+ ret = dm_i2c_read(dev, LTC_MFR_MODEL,
(void *)[0], 8);
#endif
- if (!ret && memcmp(buf, "\7LTC3882", 8) == 0)
- return i2caddress;
+ if (!ret) {
+#if defined(CONFIG_VOL_MONITOR_LTC3882_SET) || \
+ defined(CONFIG_VOL_MONITOR_LTC3882_READ)
+ if (memcmp(buf, "\7LTC3882", 8) == 0)
+#elif defined(CONFIG_VOL_MONITOR_LTC7132_SET) || \
+ defined(CONFIG_VOL_MONITOR_LTC7132_READ)
+ if (memcmp(buf, "\7LTC7132", 8) == 0)
+#endif
+ return i2caddress;
+ }
}
#endif
return -1;
@@ -148,7 +158,8 @@ static int find_vid_chip_on_i2c(void)
#define VDD_STEP_UPIR_VDD_STEP_UP
#define VDD_STEP_DOWN IR_VDD_STEP_DOWN
#endif
-#ifdef CONFIG_VOL_MONITOR_LTC3882_READ
+#if defined(CONFIG_VOL_MONITOR_LTC3882_READ) || \
+ defined(CONFIG_VOL_MONITOR_LTC7132_READ)
#define WAIT_FOR_ADC 0
#define ADC_MIN_ACCURACY LTC_ADC_MIN_ACCURACY
#define VDD_STEP_UPLTC_VDD_STEP_UP
@@ -253,14 +264,15 @@ static int read_voltage_from_IR(int i2caddress)
}
#endif
-#ifdef CONFIG_VOL_MONITOR_LTC3882_READ
+#if defined(CONFIG_VOL_MONITOR_LTC3882_READ) || \
+ defined(CONFIG_VOL_MONITOR_LTC7132_READ)
/* read the current value of the LTC Regulator Voltage.
* This will only read the first channel for dual channel setups
*/
static int read_voltage_from_LTC(int i2caddress)
{
int ret, vcode = 0;
- u8 chan = LTC3882_VID_CHANNEL;
+ u8 chan = LTC_VID_CHANNEL;
u8 buf[2];
#ifdef CONFIG_DM_I2C
struct udevice *dev;
@@ -269,11 +281,11 @@ static int read_voltage_from_LTC(int i2caddress)
/* select the PAGE 0 using PMBus commands PAGE for VDD*/
#ifndef CONFIG_DM_I2C
ret = i2c_write(i2caddress,
- LTC3882_PAGE, 1, , 1);
+ LTC_PAGE, 1, , 1);
#else
ret = i2c_get_chip_for_busnum(0, i2caddress, 1, );
if (!ret)
- ret = dm_i2c_write(dev, LTC3882_PAGE, , 1);
+ ret = dm_i2c_write(dev, LTC_PAGE, , 1);
#endif
if (ret) {
printf("VID: failed to select VDD Page\n");
@@ -283,11 +295,11 @@ static int read_voltage_from_LTC(int i2caddress)
/*read the output voltage using PMBus command READ_VOUT*/
#ifndef CONFIG_DM_I2C
ret = i2c_read(i2caddress,
- LTC3882_READ_VOUT, 1, (void *)[0], 2);
+ LTC_READ_VOUT, 1, (void *)[0], 2);
#else
ret = i2c_get_chip_for_busnum(0, i2caddress, 1, );
if (!ret)
- ret = dm_i2c_read(dev, LTC3882_READ_VOUT,
+ ret = dm_i2c_read(dev, LTC_READ_VOUT,
(void *)[0], 2);
#endif
if (ret) {
@@ -310,7 +322,8 @@ static int read_voltage(int i2caddress)
voltage_read = read_voltage_from_INA220(I2C_VOL_MONITOR_ADDR);
#elif defined CONFIG_VOL_MONITOR_IR36021_READ
voltage_read = read_voltage_from_IR(i2caddre
[PATCH v2 12/12] pci: ls_pcie_g4: Add size check for config resource
resource "config" is required to have minimum 4KB space
to access all config space of PCI Express EP.
Signed-off-by: Wasim Khan
---
Changes in V2:
- Updated commit description
- Fix CheckPatch issue
- Change size check to 4KB to access PCIe config space
drivers/pci/pcie_layerscape_gen4.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/pci/pcie_layerscape_gen4.c
b/drivers/pci/pcie_layerscape_gen4.c
index 0226bde..6e71173 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -455,6 +455,7 @@ static int ls_pcie_g4_probe(struct udevice *dev)
u32 link_ctrl_sta;
u32 val;
int ret;
+ fdt_size_t cfg_size;
pcie->bus = dev;
@@ -488,6 +489,13 @@ static int ls_pcie_g4_probe(struct udevice *dev)
return ret;
}
+ cfg_size = fdt_resource_size(>cfg_res);
+ if (cfg_size < SZ_4K) {
+ printf("PCIe%d: %s Invalid size(0x%llx) for resource
\"config\",expected minimum 0x%x\n",
+ PCIE_SRDS_PRTCL(pcie->idx), dev->name, cfg_size, SZ_4K);
+ return 0;
+ }
+
pcie->cfg = map_physmem(pcie->cfg_res.start,
fdt_resource_size(>cfg_res),
MAP_NOCACHE);
--
2.7.4
[PATCH v2 11/12] pci: layerscape: Add size check for config resource
resource "config" is required to have minimum 8KB space
as per hardware documentation.
Signed-off-by: Wasim Khan
---
Changes in V2:
- Updated commit description
- Fix CheckPatch issue
drivers/pci/pcie_layerscape_rc.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index f9e3089..7e232be 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -314,6 +314,13 @@ static int ls_pcie_probe(struct udevice *dev)
return ret;
}
+ cfg_size = fdt_resource_size(_rc->cfg_res);
+ if (cfg_size < SZ_8K) {
+ printf("PCIe%d: %s Invalid size(0x%llx) for resource
\"config\",expected minimum 0x%x\n",
+ PCIE_SRDS_PRTCL(pcie->idx), dev->name, cfg_size, SZ_8K);
+ return 0;
+ }
+
/*
* Fix the pcie memory map address and PF control registers address
* for LS2088A series SoCs
@@ -323,7 +330,6 @@ static int ls_pcie_probe(struct udevice *dev)
if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
svr == SVR_LS2048A || svr == SVR_LS2044A ||
svr == SVR_LS2081A || svr == SVR_LS2041A) {
- cfg_size = fdt_resource_size(_rc->cfg_res);
pcie_rc->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
LS2088A_PCIE_PHYS_SIZE * pcie->idx;
pcie_rc->cfg_res.end = pcie_rc->cfg_res.start + cfg_size;
--
2.7.4
[PATCH v2 08/12] arm: dts: ls1012a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan
---
Changes in V2:
- Updated commit description
arch/arm/dts/fsl-ls1012a.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 2d70c82..c401ba3 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
+ * Copyright 2020 NXP
* Copyright 2016 Freescale Semiconductor
*/
@@ -116,7 +117,7 @@
status = "disabled";
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8 /* dbi registers */
0x00 0x0348 0x0 0x4 /* lut registers */
--
2.7.4
[PATCH v2 07/12] arm: dts: ls1088a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan
---
Changes in V2:
- Updated commit description
arch/arm/dts/fsl-ls1088a.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index bf303c6..8de7998 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -2,7 +2,7 @@
/*
* NXP ls1088a SOC common device tree source
*
- * Copyright 2017 NXP
+ * Copyright 2017, 2020 NXP
*/
/ {
@@ -129,7 +129,7 @@
dr_mode = "host";
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8 /* dbi registers */
0x00 0x0348 0x0 0x8 /* lut registers */
@@ -145,7 +145,7 @@
0x8200 0x0 0x4000 0x20 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@350 {
+ pcie2: pcie@350 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x8 /* dbi registers */
0x00 0x0358 0x0 0x8 /* lut registers */
@@ -161,7 +161,7 @@
0x8200 0x0 0x4000 0x28 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@360 {
+ pcie3: pcie@360 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0360 0x0 0x8 /* dbi registers */
0x00 0x0368 0x0 0x8 /* lut registers */
--
2.7.4
[PATCH v2 05/12] arm: dts: ls1046a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan
---
Changes in V2:
- Updated commit description
arch/arm/dts/fsl-ls1046a.dtsi | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 3f11d6c..155455d 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -241,7 +241,7 @@
dr_mode = "host";
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8 /* dbi registers */
0x00 0x0348 0x0 0x4 /* lut registers */
@@ -257,7 +257,7 @@
0x8200 0x0 0x4000 0x40 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie_ep@340 {
+ pcie_ep1: pcie_ep@340 {
compatible = "fsl,ls-pcie-ep";
reg = <0x00 0x0340 0x0 0x8
0x00 0x034c 0x0 0x4
@@ -268,7 +268,7 @@
big-endian;
};
- pcie@350 {
+ pcie2: pcie@350 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x8 /* dbi registers */
0x00 0x0358 0x0 0x4 /* lut registers */
@@ -285,7 +285,7 @@
0x8200 0x0 0x4000 0x48 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie_ep@350 {
+ pcie_ep2: pcie_ep@350 {
compatible = "fsl,ls-pcie-ep";
reg = <0x00 0x0350 0x0 0x8
0x00 0x035c 0x0 0x4
@@ -296,7 +296,7 @@
big-endian;
};
- pcie@360 {
+ pcie3: pcie@360 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0360 0x0 0x8 /* dbi registers */
0x00 0x0368 0x0 0x4 /* lut registers */
@@ -312,7 +312,7 @@
0x8200 0x0 0x4000 0x50 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie_ep@360 {
+ pcie_ep3: pcie_ep@360 {
compatible = "fsl,ls-pcie-ep";
reg = <0x00 0x0360 0x0 0x8
0x00 0x036c 0x0 0x4
--
2.7.4
[PATCH v2 10/12] arm: dts: ls1028a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan
---
Changes in V2:
- Updated commit description
arch/arm/dts/fsl-ls1028a.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 9911690..ccf1a8d 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -2,7 +2,7 @@
/*
* NXP ls1028a SOC common device tree source
*
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
*
*/
@@ -85,7 +85,7 @@
status = "disabled";
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8
0x00 0x0348 0x0 0x4 /* lut registers */
@@ -101,7 +101,7 @@
0x8200 0x0 0x4000 0x80 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@350 {
+ pcie2: pcie@350 {
compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x8
0x00 0x0358 0x0 0x4 /* lut registers */
--
2.7.4
[PATCH v2 09/12] arm: dts: ls1043a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan
---
Changes in V2:
- Updated commit description
arch/arm/dts/fsl-ls1043a.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index f7db44c..8ca57ea 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -1,7 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ * Device Tree Include file for NXP Layerscape-1043A family SoC.
*
+ * Copyright 2020 NXP
* Copyright (C) 2014-2015, Freescale Semiconductor
*
* Mingkai Hu
@@ -240,7 +241,7 @@
dr_mode = "host";
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x1 /* dbi registers */
0x00 0x0341 0x0 0x1 /* lut registers */
@@ -255,7 +256,7 @@
0x8200 0x0 0x4000 0x40 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@350 {
+ pcie2: pcie@350 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x1 /* dbi registers */
0x00 0x0351 0x0 0x1 /* lut registers */
@@ -271,7 +272,7 @@
0x8200 0x0 0x4000 0x48 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@360 {
+ pcie3: pcie@360 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0360 0x0 0x1 /* dbi registers */
0x00 0x0361 0x0 0x1 /* lut registers */
--
2.7.4
[PATCH v2 04/12] arm: dts: lx2160a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan
---
Changes in V2:
- Updated commit description
arch/arm/dts/fsl-lx2160a.dtsi | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index dee1e2f..69fcc0c 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -286,7 +286,7 @@
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0340 0x0 0x8 /* PAB registers */
0x00 0x0348 0x0 0x4 /* LUT registers */
@@ -300,7 +300,7 @@
ranges = <0x8200 0x0 0x4000 0x80 0x4000 0x0
0x4000>;
};
- pcie@350 {
+ pcie2: pcie@350 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0350 0x0 0x8 /* PAB registers */
0x00 0x0358 0x0 0x4 /* LUT registers */
@@ -315,7 +315,7 @@
ranges = <0x8200 0x0 0x4000 0x88 0x4000 0x0
0x4000>;
};
- pcie@360 {
+ pcie3: pcie@360 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0360 0x0 0x8 /* PAB registers */
0x00 0x0368 0x0 0x4 /* LUT registers */
@@ -329,7 +329,7 @@
ranges = <0x8200 0x0 0x4000 0x90 0x4000 0x0
0x4000>;
};
- pcie@370 {
+ pcie4: pcie@370 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0370 0x0 0x8 /* PAB registers */
0x00 0x0378 0x0 0x4 /* LUT registers */
@@ -343,7 +343,7 @@
ranges = <0x8200 0x0 0x4000 0x98 0x4000 0x0
0x4000>;
};
- pcie@380 {
+ pcie5: pcie@380 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0380 0x0 0x8 /* PAB registers */
0x00 0x0388 0x0 0x4 /* LUT registers */
@@ -357,7 +357,7 @@
ranges = <0x8200 0x0 0x4000 0xa0 0x4000 0x0
0x4000>;
};
- pcie@390 {
+ pcie6: pcie@390 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0390 0x0 0x8 /* PAB registers */
0x00 0x0398 0x0 0x4 /* LUT registers */
--
2.7.4
[PATCH v2 06/12] arm: dts: ls2080a: add label to pcie nodes in dts
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan
---
Changes in V2:
- Updated commit description
arch/arm/dts/fsl-ls2080a.dtsi | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 90a0a3f..fae46c4 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -1,7 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Freescale ls2080a SOC common device tree source
+ * NXP ls2080a SOC common device tree source
*
+ * Copyright 2020 NXP
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*/
@@ -127,7 +128,7 @@
dr_mode = "host";
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8 /* dbi registers */
0x00 0x0348 0x0 0x8 /* lut registers */
@@ -142,7 +143,7 @@
0x8200 0x0 0x4000 0x10 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@350 {
+ pcie2: pcie@350 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x8 /* dbi registers */
0x00 0x0358 0x0 0x8 /* lut registers */
@@ -157,7 +158,7 @@
0x8200 0x0 0x4000 0x12 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@360 {
+ pcie3: pcie@360 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0360 0x0 0x8 /* dbi registers */
0x00 0x0368 0x0 0x8 /* lut registers */
@@ -172,7 +173,7 @@
0x8200 0x0 0x4000 0x14 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@370 {
+ pcie4: pcie@370 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0370 0x0 0x8 /* dbi registers */
0x00 0x0378 0x0 0x8 /* lut registers */
--
2.7.4
[PATCH v2 03/12] pci: ls_pcie_g4: Print pcie controller number starting from 1
Print pcie controller number starting from 1
Signed-off-by: Wasim Khan
---
Changes in V2:
- No Change
drivers/pci/pcie_layerscape_gen4.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_gen4.c
b/drivers/pci/pcie_layerscape_gen4.c
index 428bfca..0226bde 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
*
* PCIe Gen4 driver for NXP Layerscape SoCs
* Author: Hou Zhiqiang
@@ -472,7 +472,8 @@ static int ls_pcie_g4_probe(struct udevice *dev)
pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
if (!pcie->enabled) {
- printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+ printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx),
+ dev->name);
return 0;
}
@@ -522,10 +523,12 @@ static int ls_pcie_g4_probe(struct udevice *dev)
pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f;
if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
- printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+ printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+ "Endpoint");
ls_pcie_g4_setup_ep(pcie);
} else {
- printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+ printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+ "Root Complex");
ls_pcie_g4_setup_ctrl(pcie);
}
--
2.7.4
[PATCH v2 01/12] configs: lx2160a: Enable CONFIG_PCIE_LAYERSCAPE_GEN4
LX2160A-Rev1 uses PCIe layerscape Gen4 controller. Enable CONFIG_PCIE_LAYERSCAPE_GEN4 for lx2160a. Signed-off-by: Wasim Khan --- Changes in V2: - Added as new commit in V2 configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + configs/lx2160ardb_tfa_stmm_defconfig| 1 + 5 files changed, 5 insertions(+) diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index f2faf7b..3aa5793 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -68,6 +68,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index b6a099b..27951b7 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -75,6 +75,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index a225f21..8e8bef0 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -59,6 +59,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index d147453..ac6b5bf 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -66,6 +66,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index 799fc12..c6b7230 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -68,6 +68,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y -- 2.7.4
[PATCH v2 02/12] pci: layerscape: Print pcie controller number starting from 1
Print pcie controller number starting from 1
Signed-off-by: Wasim Khan
---
drivers/pci/pcie_layerscape_ep.c | 4 +++-
drivers/pci/pcie_layerscape_rc.c | 6 --
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index eba230e..35bb726 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
#include
@@ -294,7 +295,8 @@ static int ls_pcie_ep_probe(struct udevice *dev)
pcie_ep->num_ob_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"num-ob-windows", 8);
- printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+ printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+ "Endpoint");
ls_pcie_setup_ep(pcie_ep);
if (!ls_pcie_link_up(pcie)) {
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index 25c6dde..f9e3089 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -273,7 +273,8 @@ static int ls_pcie_probe(struct udevice *dev)
pcie_rc->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
if (!pcie_rc->enabled) {
- printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+ printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx),
+ dev->name);
return 0;
}
@@ -342,7 +343,8 @@ static int ls_pcie_probe(struct udevice *dev)
(unsigned long)pcie->ctrl, (unsigned long)pcie_rc->cfg0,
pcie->big_endian);
- printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+ printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+ "Root Complex");
ls_pcie_setup_ctrl(pcie_rc);
if (!ls_pcie_link_up(pcie)) {
--
2.7.4
[PATCH v2 02/12] pci: layerscape: Print pcie controller number starting from 1
Print pcie controller number starting from 1
Signed-off-by: Wasim Khan
---
Changes in V2:
- No Change
drivers/pci/pcie_layerscape_ep.c | 4 +++-
drivers/pci/pcie_layerscape_rc.c | 6 --
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index eba230e..26c04a9 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
#include
@@ -294,7 +295,8 @@ static int ls_pcie_ep_probe(struct udevice *dev)
pcie_ep->num_ob_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"num-ob-windows", 8);
- printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+ printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+ "Endpoint");
ls_pcie_setup_ep(pcie_ep);
if (!ls_pcie_link_up(pcie)) {
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index 25c6dde..f9e3089 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -273,7 +273,8 @@ static int ls_pcie_probe(struct udevice *dev)
pcie_rc->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
if (!pcie_rc->enabled) {
- printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+ printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx),
+ dev->name);
return 0;
}
@@ -342,7 +343,8 @@ static int ls_pcie_probe(struct udevice *dev)
(unsigned long)pcie->ctrl, (unsigned long)pcie_rc->cfg0,
pcie->big_endian);
- printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+ printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+ "Root Complex");
ls_pcie_setup_ctrl(pcie_rc);
if (!ls_pcie_link_up(pcie)) {
--
2.7.4
[PATCH v2 00/12] Add label to pcie nodes
This patch series - Adds label to pcie nodes in dts file for NXP's layerscape SoCs - Print the pcie controller number starting from 1 to match RMs - Add checks for config resource size and fix indendation. Changes in V2: - Enable CONFIG_PCIE_LAYERSCAPE_GEN4 to make LX2160A-Rev1 work - Fix CheckPatch issues - Change 1KB size check to 4KB size check for ls_pcie_g4. - Commit description updates Wasim Khan (12): configs: lx2160a: Enable CONFIG_PCIE_LAYERSCAPE_GEN4 pci: layerscape: Print pcie controller number starting from 1 pci: ls_pcie_g4: Print pcie controller number starting from 1 arm: dts: lx2160a: add label to pcie nodes in dts arm: dts: ls1046a: add label to pcie nodes in dts arm: dts: ls2080a: add label to pcie nodes in dts arm: dts: ls1088a: add label to pcie nodes in dts arm: dts: ls1012a: add label to pcie nodes in dts arm: dts: ls1043a: add label to pcie nodes in dts arm: dts: ls1028a: add label to pcie nodes in dts pci: layerscape: Add size check for config resource pci: ls_pcie_g4: Add size check for config resource arch/arm/dts/fsl-ls1012a.dtsi| 3 ++- arch/arm/dts/fsl-ls1028a.dtsi| 6 +++--- arch/arm/dts/fsl-ls1043a.dtsi| 9 + arch/arm/dts/fsl-ls1046a.dtsi| 12 ++-- arch/arm/dts/fsl-ls1088a.dtsi| 8 arch/arm/dts/fsl-ls2080a.dtsi| 11 ++- arch/arm/dts/fsl-lx2160a.dtsi| 12 ++-- configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + configs/lx2160ardb_tfa_stmm_defconfig| 1 + drivers/pci/pcie_layerscape_ep.c | 4 +++- drivers/pci/pcie_layerscape_gen4.c | 19 +++ drivers/pci/pcie_layerscape_rc.c | 14 +++--- 15 files changed, 66 insertions(+), 37 deletions(-) -- 2.7.4
[PATCH 12/12] pci: layerscape: indentation correction
correct the indentation.
Signed-off-by: Wasim Khan
---
drivers/pci/pcie_layerscape.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 8f64e53..60f5031 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -532,11 +532,11 @@ static int ls_pcie_probe(struct udevice *dev)
if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
"Endpoint");
- ls_pcie_setup_ep(pcie);
+ ls_pcie_setup_ep(pcie);
} else {
printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
"Root Complex");
- ls_pcie_setup_ctrl(pcie);
+ ls_pcie_setup_ctrl(pcie);
}
if (!ls_pcie_link_up(pcie)) {
--
2.7.4
[PATCH 11/12] pci: ls_pcie_g4: Add size check for config resource
resource "config" is required to have minimum 1KB space.
Signed-off-by: Wasim Khan
---
drivers/pci/pcie_layerscape_gen4.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/pci/pcie_layerscape_gen4.c
b/drivers/pci/pcie_layerscape_gen4.c
index 0226bde..f9e3e04 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -455,6 +455,7 @@ static int ls_pcie_g4_probe(struct udevice *dev)
u32 link_ctrl_sta;
u32 val;
int ret;
+ fdt_size_t cfg_size;
pcie->bus = dev;
@@ -488,6 +489,14 @@ static int ls_pcie_g4_probe(struct udevice *dev)
return ret;
}
+ cfg_size = fdt_resource_size(>cfg_res);
+ if (cfg_size < SZ_1K) {
+ printf("PCIe%d: %s Invalid size(0x%x) for resource \"config\",
+ expected minimum 0x%x \n", PCIE_SRDS_PRTCL(pcie->idx),
+ dev->name, cfg_size, SZ_1K);
+ return 0;
+ }
+
pcie->cfg = map_physmem(pcie->cfg_res.start,
fdt_resource_size(>cfg_res),
MAP_NOCACHE);
--
2.7.4
[PATCH 10/12] pci: layerscape: Add size check for config resource
resource "config" is required to have minimum 8KB space.
Signed-off-by: Wasim Khan
---
drivers/pci/pcie_layerscape.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 2f17176..8f64e53 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -493,6 +493,13 @@ static int ls_pcie_probe(struct udevice *dev)
return ret;
}
+ cfg_size = fdt_resource_size(>cfg_res);
+ if (cfg_size < SZ_8K) {
+ printf("PCIe%d: %s Invalid size(0x%x) for resource \"config\",
+ expected minimum 0x%x \n", PCIE_SRDS_PRTCL(pcie->idx),
+ dev->name, cfg_size, SZ_8K);
+ return 0;
+ }
/*
* Fix the pcie memory map address and PF control registers address
* for LS2088A series SoCs
@@ -502,7 +509,6 @@ static int ls_pcie_probe(struct udevice *dev)
if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
svr == SVR_LS2048A || svr == SVR_LS2044A ||
svr == SVR_LS2081A || svr == SVR_LS2041A) {
- cfg_size = fdt_resource_size(>cfg_res);
pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
LS2088A_PCIE_PHYS_SIZE * pcie->idx;
pcie->cfg_res.end = pcie->cfg_res.start + cfg_size;
--
2.7.4
[PATCH 09/12] arm: dts: ls1028a: add label to pcie nodes in dts
add label to pcie nodes in dts
Signed-off-by: Wasim Khan
---
arch/arm/dts/fsl-ls1028a.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 9911690..ccf1a8d 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -2,7 +2,7 @@
/*
* NXP ls1028a SOC common device tree source
*
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
*
*/
@@ -85,7 +85,7 @@
status = "disabled";
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8
0x00 0x0348 0x0 0x4 /* lut registers */
@@ -101,7 +101,7 @@
0x8200 0x0 0x4000 0x80 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@350 {
+ pcie2: pcie@350 {
compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x8
0x00 0x0358 0x0 0x4 /* lut registers */
--
2.7.4
[PATCH 08/12] arm: dts: ls1043a: add label to pcie nodes in dts
add label to pcie nodes in dts
Signed-off-by: Wasim Khan
---
arch/arm/dts/fsl-ls1043a.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index f7db44c..8ca57ea 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -1,7 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ * Device Tree Include file for NXP Layerscape-1043A family SoC.
*
+ * Copyright 2020 NXP
* Copyright (C) 2014-2015, Freescale Semiconductor
*
* Mingkai Hu
@@ -240,7 +241,7 @@
dr_mode = "host";
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x1 /* dbi registers */
0x00 0x0341 0x0 0x1 /* lut registers */
@@ -255,7 +256,7 @@
0x8200 0x0 0x4000 0x40 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@350 {
+ pcie2: pcie@350 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x1 /* dbi registers */
0x00 0x0351 0x0 0x1 /* lut registers */
@@ -271,7 +272,7 @@
0x8200 0x0 0x4000 0x48 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@360 {
+ pcie3: pcie@360 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0360 0x0 0x1 /* dbi registers */
0x00 0x0361 0x0 0x1 /* lut registers */
--
2.7.4
[PATCH 07/12] arm: dts: ls1012a: add label to pcie nodes in dts
add label to pcie nodes in dts
Signed-off-by: Wasim Khan
---
arch/arm/dts/fsl-ls1012a.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 2d70c82..c401ba3 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
+ * Copyright 2020 NXP
* Copyright 2016 Freescale Semiconductor
*/
@@ -116,7 +117,7 @@
status = "disabled";
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8 /* dbi registers */
0x00 0x0348 0x0 0x4 /* lut registers */
--
2.7.4
[PATCH 06/12] arm: dts: ls1088a: add label to pcie nodes in dts
add label to pcie nodes in dts
Signed-off-by: Wasim Khan
---
arch/arm/dts/fsl-ls1088a.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index bf303c6..8de7998 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -2,7 +2,7 @@
/*
* NXP ls1088a SOC common device tree source
*
- * Copyright 2017 NXP
+ * Copyright 2017, 2020 NXP
*/
/ {
@@ -129,7 +129,7 @@
dr_mode = "host";
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8 /* dbi registers */
0x00 0x0348 0x0 0x8 /* lut registers */
@@ -145,7 +145,7 @@
0x8200 0x0 0x4000 0x20 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@350 {
+ pcie2: pcie@350 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x8 /* dbi registers */
0x00 0x0358 0x0 0x8 /* lut registers */
@@ -161,7 +161,7 @@
0x8200 0x0 0x4000 0x28 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@360 {
+ pcie3: pcie@360 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0360 0x0 0x8 /* dbi registers */
0x00 0x0368 0x0 0x8 /* lut registers */
--
2.7.4
[PATCH 04/12] arm: dts: ls1046a: add label to pcie nodes in dts
add label to pcie nodes in dts
Signed-off-by: Wasim Khan
---
arch/arm/dts/fsl-ls1046a.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 8673a5d..8a0c6fc 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -1,7 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ * Device Tree Include file for NXP Layerscape-1046A family SoC.
*
+ * Copyright 2020 NXP
* Copyright (C) 2016, Freescale Semiconductor
*
* Mingkai Hu
@@ -241,7 +242,7 @@
dr_mode = "host";
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8 /* dbi registers */
0x00 0x0348 0x0 0x4 /* lut registers */
@@ -257,7 +258,7 @@
0x8200 0x0 0x4000 0x40 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@350 {
+ pcie2: pcie@350 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x8 /* dbi registers */
0x00 0x0358 0x0 0x4 /* lut registers */
@@ -274,7 +275,7 @@
0x8200 0x0 0x4000 0x48 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@360 {
+ pcie3: pcie@360 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0360 0x0 0x8 /* dbi registers */
0x00 0x0368 0x0 0x4 /* lut registers */
--
2.7.4
[PATCH 05/12] arm: dts: ls2080a: add label to pcie nodes in dts
add label to pcie nodes in dts
Signed-off-by: Wasim Khan
---
arch/arm/dts/fsl-ls2080a.dtsi | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 90a0a3f..fae46c4 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -1,7 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Freescale ls2080a SOC common device tree source
+ * NXP ls2080a SOC common device tree source
*
+ * Copyright 2020 NXP
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*/
@@ -127,7 +128,7 @@
dr_mode = "host";
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8 /* dbi registers */
0x00 0x0348 0x0 0x8 /* lut registers */
@@ -142,7 +143,7 @@
0x8200 0x0 0x4000 0x10 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@350 {
+ pcie2: pcie@350 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x8 /* dbi registers */
0x00 0x0358 0x0 0x8 /* lut registers */
@@ -157,7 +158,7 @@
0x8200 0x0 0x4000 0x12 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@360 {
+ pcie3: pcie@360 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0360 0x0 0x8 /* dbi registers */
0x00 0x0368 0x0 0x8 /* lut registers */
@@ -172,7 +173,7 @@
0x8200 0x0 0x4000 0x14 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
- pcie@370 {
+ pcie4: pcie@370 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0370 0x0 0x8 /* dbi registers */
0x00 0x0378 0x0 0x8 /* lut registers */
--
2.7.4
[PATCH 03/12] arm: dts: lx2160a: add label to pcie nodes in dts
add label to pcie nodes in dts
Signed-off-by: Wasim Khan
---
arch/arm/dts/fsl-lx2160a.dtsi | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index c62960e..dcf0073 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -279,7 +279,7 @@
};
- pcie@340 {
+ pcie1: pcie@340 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0340 0x0 0x8 /* PAB registers */
0x00 0x0348 0x0 0x4 /* LUT registers */
@@ -293,7 +293,7 @@
ranges = <0x8200 0x0 0x4000 0x80 0x4000 0x0
0x4000>;
};
- pcie@350 {
+ pcie2: pcie@350 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0350 0x0 0x8 /* PAB registers */
0x00 0x0358 0x0 0x4 /* LUT registers */
@@ -308,7 +308,7 @@
ranges = <0x8200 0x0 0x4000 0x88 0x4000 0x0
0x4000>;
};
- pcie@360 {
+ pcie3: pcie@360 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0360 0x0 0x8 /* PAB registers */
0x00 0x0368 0x0 0x4 /* LUT registers */
@@ -322,7 +322,7 @@
ranges = <0x8200 0x0 0x4000 0x90 0x4000 0x0
0x4000>;
};
- pcie@370 {
+ pcie4: pcie@370 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0370 0x0 0x8 /* PAB registers */
0x00 0x0378 0x0 0x4 /* LUT registers */
@@ -336,7 +336,7 @@
ranges = <0x8200 0x0 0x4000 0x98 0x4000 0x0
0x4000>;
};
- pcie@380 {
+ pcie5: pcie@380 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0380 0x0 0x8 /* PAB registers */
0x00 0x0388 0x0 0x4 /* LUT registers */
@@ -350,7 +350,7 @@
ranges = <0x8200 0x0 0x4000 0xa0 0x4000 0x0
0x4000>;
};
- pcie@390 {
+ pcie6: pcie@390 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0390 0x0 0x8 /* PAB registers */
0x00 0x0398 0x0 0x4 /* LUT registers */
--
2.7.4
