[U-Boot] [v3 2/2] armv8: ls1043a: Discard the needless cpu nodes

[Wenbin song]

Using "cpu_pos_mask()" function to detect the real online cpus,
and discard the needless cpu nodes on kernel dts.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
Changes for v2:
None.
---
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index d1a7d0de9c..39ffe1ab4d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -42,6 +42,33 @@ void ft_fixup_cpu(void *blob)
int addr_cells;
u64 val, core_id;
size_t *boot_code_size = &(__secondary_boot_code_size);
+   u32 mask = cpu_pos_mask();
+   int off_prev = -1;
+
+   off = fdt_path_offset(blob, "/cpus");
+   if (off < 0) {
+   puts("couldn't find /cpus node\n");
+   return;
+   }
+
+   fdt_support_default_count_cells(blob, off, _cells, NULL);
+
+   off = fdt_node_offset_by_prop_value(blob, off_prev, "device_type",
+   "cpu", 4);
+   while (off != -FDT_ERR_NOTFOUND) {
+   reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
+   if (reg) {
+   core_id = fdt_read_number(reg, addr_cells);
+   if (!test_bit(id_to_core(core_id), )) {
+   fdt_del_node(blob, off);
+   off = off_prev;
+   }
+   }
+   off_prev = off;
+   off = fdt_node_offset_by_prop_value(blob, off_prev,
+   "device_type", "cpu", 4);
+   }
+
 #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
int node;
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [v4 2/2] armv8: layerscape: Discard the needless cpu nodes

[Wenbin song]

Using "cpu_pos_mask()" function to detect the real online cpus,
and discard the needless cpu nodes on kernel dts.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
Changes for v1:
Remove the config option.
Use id_to_core() funcation to find the position of core.
Changes for v2:
None.
Changes for v3:
Replace "ls1043a" with "layerscape" on the subject.
---
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index d1a7d0de9c..39ffe1ab4d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -42,6 +42,33 @@ void ft_fixup_cpu(void *blob)
int addr_cells;
u64 val, core_id;
size_t *boot_code_size = &(__secondary_boot_code_size);
+   u32 mask = cpu_pos_mask();
+   int off_prev = -1;
+
+   off = fdt_path_offset(blob, "/cpus");
+   if (off < 0) {
+   puts("couldn't find /cpus node\n");
+   return;
+   }
+
+   fdt_support_default_count_cells(blob, off, _cells, NULL);
+
+   off = fdt_node_offset_by_prop_value(blob, off_prev, "device_type",
+   "cpu", 4);
+   while (off != -FDT_ERR_NOTFOUND) {
+   reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
+   if (reg) {
+   core_id = fdt_read_number(reg, addr_cells);
+   if (!test_bit(id_to_core(core_id), )) {
+   fdt_del_node(blob, off);
+   off = off_prev;
+   }
+   }
+   off_prev = off;
+   off = fdt_node_offset_by_prop_value(blob, off_prev,
+   "device_type", "cpu", 4);
+   }
+
 #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
int node;
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [v4 1/2] armv8: ls1043a/ls2080a: check SoC by device ID

[Wenbin song]

Check LS1043A/LS2080a by device ID without using personality ID to
determine revision number. This check applies to all various
personalities of the same SoC family.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
Changes for V1:
None.
Changes for v2:
Modify the commit message and subject.
Add SVR_DEV and IS_SVR_DEV mocros. 
Changes for V3:
None.
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 8 
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 4 ++--
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   | 9 -
 arch/arm/include/asm/arch-fsl-layerscape/soc.h | 4 ++--
 drivers/net/fsl-mc/dpio/qbman_private.h| 4 ++--
 drivers/usb/common/fsl-errata.c| 7 +--
 6 files changed, 19 insertions(+), 17 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index ab5d76ea3b..021eb377a2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -502,8 +502,8 @@ int arch_early_init_r(void)
 * erratum A009635 is valid only for LS2080A SoC and
 * its personalitiesi
 */
-   svr_dev_id = get_svr() >> 16;
-   if (svr_dev_id == SVR_DEV_LS2080A)
+   svr_dev_id = get_svr();
+   if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
erratum_a009635();
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
@@ -566,8 +566,8 @@ int timer_init(void)
 * For LS2080A SoC and its personalities, timer controller
 * offset is different
 */
-   svr_dev_id = get_svr() >> 16;
-   if (svr_dev_id == SVR_DEV_LS2080A)
+   svr_dev_id = get_svr();
+   if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
 
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index cae59da803..d1a7d0de9c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -145,7 +145,7 @@ static void fdt_fixup_gic(void *blob)
 
val = gur_in32(>svr);
 
-   if (SVR_SOC_VER(val) != SVR_LS1043A) {
+   if (!IS_SVR_DEV(val, SVR_DEV(SVR_LS1043A))) {
align_64k = 1;
} else if (SVR_REV(val) != REV1_0) {
val = scfg_in32(>gic_align) & (0x01 << GIC_ADDR_BIT);
@@ -327,7 +327,7 @@ static void fdt_fixup_msi(void *blob)
 
rev = gur_in32(>svr);
 
-   if (SVR_SOC_VER(rev) != SVR_LS1043A)
+   if (!IS_SVR_DEV(rev, SVR_DEV(SVR_LS1043A)))
return;
 
rev = SVR_REV(rev);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index fa93096c68..c089ceef32 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -37,9 +37,8 @@ ENTRY(get_gic_offset)
ldr x2, =DCFG_CCSR_SVR
ldr w2, [x2]
rev w2, w2
-   mov w3, w2
-   andsw3, w3, #SVR_WO_E << 8
-   mov w4, #SVR_LS1043A << 8
+   lsr w3, w2, #16
+   ldr w4, =SVR_DEV(SVR_LS1043A)
cmp w3, w4
b.ne1f
andsw2, w2, #0xff
@@ -92,7 +91,7 @@ ENTRY(lowlevel_init)
 */
bl  get_svr
lsr w0, w0, #16
-   ldr w1, =SVR_DEV_LS2080A
+   ldr w1, =SVR_DEV(SVR_LS2080A)
cmp w0, w1
b.eq1f
 
@@ -224,7 +223,7 @@ ENTRY(lowlevel_init)
 */
bl  get_svr
lsr w0, w0, #16
-   ldr w1, =SVR_DEV_LS2080A
+   ldr w1, =SVR_DEV(SVR_LS2080A)
cmp w0, w1
b.eq1f
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 247f09e0f5..09f64e7bd7 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -76,8 +76,6 @@ struct cpu_type {
 #define SVR_LS2081A0x870918
 #define SVR_LS2041A0x870914
 
-#define SVR_DEV_LS2080A0x8701
-
 #define SVR_MAJ(svr)   (((svr) >> 4) & 0xf)
 #define SVR_MIN(svr)   (((svr) >> 0) & 0xf)
 #define SVR_REV(svr)   (((svr) >> 0) & 0xff)
@@ -85,6 +83,8 @@ struct cpu_type {
 #define IS_E_PROCESSOR(svr)(!((svr >> 8) & 0x1))
 #define IS_SVR_REV(svr, maj, min) \
((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
+#define SVR_DEV(svr)   ((svr) >> 8)
+#define IS_SVR_DEV(svr, dev)   (((svr) >> 16) == (dev))
 
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG0xa003fffe
diff --git a/drivers/net/fsl-mc/dpio/qbman_private.h 
b/drivers/net/fsl-mc/dpio/qbman_private.h
index 73bbae373e..873323be0f 100644
--- a/drivers/net

[U-Boot] [v3 2/2] armv8: ls1043a: Discard the needless cpu nodes

[Wenbin song]

Using "cpu_pos_mask()" function to detect the real online cpus,
and discard the needless cpu nodes on kernel dts.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
Changes for v2:
None.
---
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index d1a7d0de9c..39ffe1ab4d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -42,6 +42,33 @@ void ft_fixup_cpu(void *blob)
int addr_cells;
u64 val, core_id;
size_t *boot_code_size = &(__secondary_boot_code_size);
+   u32 mask = cpu_pos_mask();
+   int off_prev = -1;
+
+   off = fdt_path_offset(blob, "/cpus");
+   if (off < 0) {
+   puts("couldn't find /cpus node\n");
+   return;
+   }
+
+   fdt_support_default_count_cells(blob, off, _cells, NULL);
+
+   off = fdt_node_offset_by_prop_value(blob, off_prev, "device_type",
+   "cpu", 4);
+   while (off != -FDT_ERR_NOTFOUND) {
+   reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
+   if (reg) {
+   core_id = fdt_read_number(reg, addr_cells);
+   if (!test_bit(id_to_core(core_id), )) {
+   fdt_del_node(blob, off);
+   off = off_prev;
+   }
+   }
+   off_prev = off;
+   off = fdt_node_offset_by_prop_value(blob, off_prev,
+   "device_type", "cpu", 4);
+   }
+
 #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
int node;
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [v3 1/2] armv8: ls1043a/ls2080a: check SoC by device ID

[Wenbin song]

Check LS1043A/LS2080a by device ID without using personality ID to
determine revision number. This check applies to all various
personalities of the same SoC family.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
Changes for v2:
Modify the commit message and subject.
Add SVR_DEV and IS_SVR_DEV mocros. 
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 8 
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 4 ++--
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   | 9 -
 arch/arm/include/asm/arch-fsl-layerscape/soc.h | 4 ++--
 drivers/net/fsl-mc/dpio/qbman_private.h| 4 ++--
 drivers/usb/common/fsl-errata.c| 7 +--
 6 files changed, 19 insertions(+), 17 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index ab5d76ea3b..021eb377a2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -502,8 +502,8 @@ int arch_early_init_r(void)
 * erratum A009635 is valid only for LS2080A SoC and
 * its personalitiesi
 */
-   svr_dev_id = get_svr() >> 16;
-   if (svr_dev_id == SVR_DEV_LS2080A)
+   svr_dev_id = get_svr();
+   if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
erratum_a009635();
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
@@ -566,8 +566,8 @@ int timer_init(void)
 * For LS2080A SoC and its personalities, timer controller
 * offset is different
 */
-   svr_dev_id = get_svr() >> 16;
-   if (svr_dev_id == SVR_DEV_LS2080A)
+   svr_dev_id = get_svr();
+   if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
 
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index cae59da803..d1a7d0de9c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -145,7 +145,7 @@ static void fdt_fixup_gic(void *blob)
 
val = gur_in32(>svr);
 
-   if (SVR_SOC_VER(val) != SVR_LS1043A) {
+   if (!IS_SVR_DEV(val, SVR_DEV(SVR_LS1043A))) {
align_64k = 1;
} else if (SVR_REV(val) != REV1_0) {
val = scfg_in32(>gic_align) & (0x01 << GIC_ADDR_BIT);
@@ -327,7 +327,7 @@ static void fdt_fixup_msi(void *blob)
 
rev = gur_in32(>svr);
 
-   if (SVR_SOC_VER(rev) != SVR_LS1043A)
+   if (!IS_SVR_DEV(rev, SVR_DEV(SVR_LS1043A)))
return;
 
rev = SVR_REV(rev);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index fa93096c68..c089ceef32 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -37,9 +37,8 @@ ENTRY(get_gic_offset)
ldr x2, =DCFG_CCSR_SVR
ldr w2, [x2]
rev w2, w2
-   mov w3, w2
-   andsw3, w3, #SVR_WO_E << 8
-   mov w4, #SVR_LS1043A << 8
+   lsr w3, w2, #16
+   ldr w4, =SVR_DEV(SVR_LS1043A)
cmp w3, w4
b.ne1f
andsw2, w2, #0xff
@@ -92,7 +91,7 @@ ENTRY(lowlevel_init)
 */
bl  get_svr
lsr w0, w0, #16
-   ldr w1, =SVR_DEV_LS2080A
+   ldr w1, =SVR_DEV(SVR_LS2080A)
cmp w0, w1
b.eq1f
 
@@ -224,7 +223,7 @@ ENTRY(lowlevel_init)
 */
bl  get_svr
lsr w0, w0, #16
-   ldr w1, =SVR_DEV_LS2080A
+   ldr w1, =SVR_DEV(SVR_LS2080A)
cmp w0, w1
b.eq1f
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 247f09e0f5..09f64e7bd7 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -76,8 +76,6 @@ struct cpu_type {
 #define SVR_LS2081A0x870918
 #define SVR_LS2041A0x870914
 
-#define SVR_DEV_LS2080A0x8701
-
 #define SVR_MAJ(svr)   (((svr) >> 4) & 0xf)
 #define SVR_MIN(svr)   (((svr) >> 0) & 0xf)
 #define SVR_REV(svr)   (((svr) >> 0) & 0xff)
@@ -85,6 +83,8 @@ struct cpu_type {
 #define IS_E_PROCESSOR(svr)(!((svr >> 8) & 0x1))
 #define IS_SVR_REV(svr, maj, min) \
((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
+#define SVR_DEV(svr)   ((svr) >> 8)
+#define IS_SVR_DEV(svr, dev)   (((svr) >> 16) == (dev))
 
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG0xa003fffe
diff --git a/drivers/net/fsl-mc/dpio/qbman_private.h 
b/drivers/net/fsl-mc/dpio/qbman_private.h
index 73bbae373e..873323be0f 100644
--- a/drivers/net/fsl-mc/dpio/qbman_private.h
+++ b/drivers/net/fsl-mc/dpio/qbman_private.h

[U-Boot] [V2 2/2] armv8: ls1043a: Discard the needless cpu nodes

[Wenbin song]

Using "cpu_pos_mask()" function to detect the real online cpus,
and discard the needless cpu nodes on kernel dts.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
Changes for v1:
Remove the config option.
Use id_to_core() funcation to find the position of core.
---
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 3c32c0f860..0cada6abe4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -42,6 +42,33 @@ void ft_fixup_cpu(void *blob)
int addr_cells;
u64 val, core_id;
size_t *boot_code_size = &(__secondary_boot_code_size);
+   u32 mask = cpu_pos_mask();
+   int off_prev = -1;
+
+   off = fdt_path_offset(blob, "/cpus");
+   if (off < 0) {
+   puts("couldn't find /cpus node\n");
+   return;
+   }
+
+   fdt_support_default_count_cells(blob, off, _cells, NULL);
+
+   off = fdt_node_offset_by_prop_value(blob, off_prev, "device_type",
+   "cpu", 4);
+   while (off != -FDT_ERR_NOTFOUND) {
+   reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
+   if (reg) {
+   core_id = fdt_read_number(reg, addr_cells);
+   if (!test_bit(id_to_core(core_id), )) {
+   fdt_del_node(blob, off);
+   off = off_prev;
+   }
+   }
+   off_prev = off;
+   off = fdt_node_offset_by_prop_value(blob, off_prev,
+   "device_type", "cpu", 4);
+   }
+
 #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
int node;
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 2/2] armv8: ls1043a: Discard the needless cpu nodes

[Wenbin Song]

Hi York, 
Yes, you are right. 
I have tested it on others SoCs (LS1043a/LS1023a, LS2088a/LS2048a).  It works 
fine.

So, I will remove the config and the #if condition.

Thank you and Prabhakar for the advice.

Best Regards
Wenbin Song

 

-Original Message-
From: York Sun 
Sent: Friday, December 01, 2017 1:41 AM
To: Wenbin Song <wenbin.s...@nxp.com>; Prabhakar Kushwaha 
<prabhakar.kushw...@nxp.com>; Ran Wang <ran.wan...@nxp.com>; Mingkai Hu 
<mingkai...@nxp.com>; u-boot@lists.denx.de
Subject: Re: [PATCH 2/2] armv8: ls1043a: Discard the needless cpu nodes

On 11/29/2017 07:16 PM, Wenbin song wrote:
> Using "cpu_pos_mask()" function to detect the real online cpus, and 
> discard the needless cpu nodes on kernel dft.
> 
> Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig |  4 
>  arch/arm/cpu/armv8/fsl-layerscape/fdt.c   | 32 
> +++
>  2 files changed, 36 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index 47145a2432..971a98c6cc 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -176,6 +176,10 @@ config HAS_FEATURE_ENHANCED_MSI
>   bool
>   default y if ARCH_LS1043A
>  
> +config DISCARD_OFFLINE_CPU_NODES
> + bool
> + default y if ARCH_LS1043A
> +
>  menu "Layerscape PPA"
>  config FSL_LS_PPA
>   bool "FSL Layerscape PPA firmware support"
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
> b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> index 33f3e64848..241f0abe18 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> @@ -44,6 +44,38 @@ void ft_fixup_cpu(void *blob)
>   int addr_cells;
>   u64 val, core_id;
>   size_t *boot_code_size = &(__secondary_boot_code_size);
> +
> +#if defined(CONFIG_DISCARD_OFFLINE_CPU_NODES)
> + u32 mask = cpu_pos_mask();
> + int off_prev = -1;
> + int pos;
> +
> + off = fdt_path_offset(blob, "/cpus");
> + if (off < 0) {
> + puts("couldn't find /cpus node\n");
> + return;
> + }
> +
> + fdt_support_default_count_cells(blob, off, _cells, NULL);
> +
> + off = fdt_node_offset_by_prop_value(blob, off_prev, "device_type",
> + "cpu", 4);
> + while (off != -FDT_ERR_NOTFOUND) {
> + reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
> + if (reg) {
> + core_id = fdt_read_number(reg, addr_cells);
> + pos = ((core_id & 0xff00) >> 5) + (core_id & 0xff);
> + if (!test_bit(pos, )) {
> + fdt_del_node(blob, off);
> + off = off_prev;
> + }
> + }
> + off_prev = off;
> + off = fdt_node_offset_by_prop_value(blob, off_prev,
> + "device_type", "cpu", 4);
> + }
> +#endif
> +
>  #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
>   defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
>   int node;
> 

Wenbin,

Using topology registers to identify the existence of cores is correct.
Do you need the new config option to gate the code? It is a correct operation 
for all SoCs, isn't it?

York
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [V2 1/2] armv8: ls1043a: modify the detecting way to cover all variants

[Wenbin song]

There are many variants for ls1043a. Modify the detecting way to
make that the below fixup apply to all variants of ls1043a.
- Fix GIC offset for rev1.1
- Fix msi node for rev1.1
- erratum_a010151

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
Changes for V1:
None.
---
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 4 ++--
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   | 5 ++---
 arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 +++
 drivers/usb/common/fsl-errata.c| 7 +--
 4 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index cae59da803..3c32c0f860 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -145,7 +145,7 @@ static void fdt_fixup_gic(void *blob)
 
val = gur_in32(>svr);
 
-   if (SVR_SOC_VER(val) != SVR_LS1043A) {
+   if (!IS_SVR_DEV(val, SVR_DEV_LS1043A)) {
align_64k = 1;
} else if (SVR_REV(val) != REV1_0) {
val = scfg_in32(>gic_align) & (0x01 << GIC_ADDR_BIT);
@@ -327,7 +327,7 @@ static void fdt_fixup_msi(void *blob)
 
rev = gur_in32(>svr);
 
-   if (SVR_SOC_VER(rev) != SVR_LS1043A)
+   if (!IS_SVR_DEV(rev, SVR_DEV_LS1043A))
return;
 
rev = SVR_REV(rev);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index fa93096c68..54b825a626 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -37,9 +37,8 @@ ENTRY(get_gic_offset)
ldr x2, =DCFG_CCSR_SVR
ldr w2, [x2]
rev w2, w2
-   mov w3, w2
-   andsw3, w3, #SVR_WO_E << 8
-   mov w4, #SVR_LS1043A << 8
+   lsr w3, w2, #16
+   ldr w4, =SVR_DEV_LS1043A
cmp w3, w4
b.ne1f
andsw2, w2, #0xff
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 247f09e0f5..a2a039ec53 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -77,6 +77,7 @@ struct cpu_type {
 #define SVR_LS2041A0x870914
 
 #define SVR_DEV_LS2080A0x8701
+#define SVR_DEV_LS1043A0x8792
 
 #define SVR_MAJ(svr)   (((svr) >> 4) & 0xf)
 #define SVR_MIN(svr)   (((svr) >> 0) & 0xf)
@@ -85,6 +86,8 @@ struct cpu_type {
 #define IS_E_PROCESSOR(svr)(!((svr >> 8) & 0x1))
 #define IS_SVR_REV(svr, maj, min) \
((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
+#define IS_SVR_DEV(svr, dev) \
+   (((svr) >> 16) == (dev))
 
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG0xa003fffe
diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c
index 823beb32f6..c20c9a3567 100644
--- a/drivers/usb/common/fsl-errata.c
+++ b/drivers/usb/common/fsl-errata.c
@@ -198,6 +198,11 @@ bool has_erratum_a010151(void)
u32 svr = get_svr();
u32 soc = SVR_SOC_VER(svr);
 
+#ifdef CONFIG_ARM64
+   if (IS_SVR_DEV(svr, SVR_DEV_LS1043A))
+   return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+#endif
+
switch (soc) {
 #ifdef CONFIG_ARM64
case SVR_LS2080A:
@@ -209,8 +214,6 @@ bool has_erratum_a010151(void)
case SVR_LS1046A:
case SVR_LS1012A:
return IS_SVR_REV(svr, 1, 0);
-   case SVR_LS1043A:
-   return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
 #endif
 #ifdef CONFIG_ARCH_LS1021A
case SOC_VER_LS1020:
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 2/2] armv8: ls1043a: Discard the needless cpu nodes

[Wenbin Song]

Hi Prabhakar,

In my opinion, this is a common feature for all Layerscapes. As I know, all 
chips belonged to Layerscape have the capacity to disable some cores, just like 
ls1043a /ls1023a. 
If we will support another variant in the future, for example: ls1046a/ls1026a, 
just configure it rather than modify the codes.
Am I correct?

Best Regards
Wenbin Song


-Original Message-
From: Prabhakar Kushwaha 
Sent: Thursday, November 30, 2017 12:56 PM
To: Wenbin Song <wenbin.s...@nxp.com>; York Sun <york@nxp.com>; Ran Wang 
<ran.wan...@nxp.com>; Mingkai Hu <mingkai...@nxp.com>; u-boot@lists.denx.de
Cc: Wenbin Song <wenbin.s...@nxp.com>
Subject: RE: [PATCH 2/2] armv8: ls1043a: Discard the needless cpu nodes


> -----Original Message-
> From: Wenbin song [mailto:wenbin.s...@nxp.com]
> Sent: Thursday, November 30, 2017 8:27 AM
> To: York Sun <york@nxp.com>; Prabhakar Kushwaha 
> <prabhakar.kushw...@nxp.com>; Ran Wang <ran.wan...@nxp.com>; Mingkai 
> Hu <mingkai...@nxp.com>; u-boot@lists.denx.de
> Cc: Wenbin Song <wenbin.s...@nxp.com>
> Subject: [PATCH 2/2] armv8: ls1043a: Discard the needless cpu nodes
> 
> Using "cpu_pos_mask()" function to detect the real online cpus, and 
> discard the needless cpu nodes on kernel dft.
> 
> Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig |  4 
>  arch/arm/cpu/armv8/fsl-layerscape/fdt.c   | 32
> +++
>  2 files changed, 36 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index 47145a2432..971a98c6cc 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -176,6 +176,10 @@ config HAS_FEATURE_ENHANCED_MSI
>   bool
>   default y if ARCH_LS1043A
> 
> +config DISCARD_OFFLINE_CPU_NODES
> + bool
> + default y if ARCH_LS1043A
> +

As per understanding this feature is for taking care of SoC personalities with 
reduced cores. 

Why a new config is required? Why cannot this be taken care at run time by 
reading SVR.

-pk

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 1/2] armv8: ls1043a: modify the detecting way to cover all variants

[Wenbin song]

There are many variants for ls1043a. Modify the detecting way to
make that the below fixup apply to all variants of ls1043a.
- Fix GIC offset for rev1.1
- Fix msi node for rev1.1
- erratum_a010151

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 4 ++--
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   | 5 ++---
 arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 +++
 drivers/usb/common/fsl-errata.c| 7 +--
 4 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index d6794708c9..33f3e64848 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -147,7 +147,7 @@ static void fdt_fixup_gic(void *blob)
 
val = gur_in32(>svr);
 
-   if (SVR_SOC_VER(val) != SVR_LS1043A) {
+   if (!IS_SVR_DEV(val, SVR_DEV_LS1043A)) {
align_64k = 1;
} else if (SVR_REV(val) != REV1_0) {
val = scfg_in32(>gic_align) & (0x01 << GIC_ADDR_BIT);
@@ -329,7 +329,7 @@ static void fdt_fixup_msi(void *blob)
 
rev = gur_in32(>svr);
 
-   if (SVR_SOC_VER(rev) != SVR_LS1043A)
+   if (!IS_SVR_DEV(rev, SVR_DEV_LS1043A))
return;
 
rev = SVR_REV(rev);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 28a31b21a9..666e842b99 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -37,9 +37,8 @@ ENTRY(get_gic_offset)
ldr x2, =DCFG_CCSR_SVR
ldr w2, [x2]
rev w2, w2
-   mov w3, w2
-   andsw3, w3, #SVR_WO_E << 8
-   mov w4, #SVR_LS1043A << 8
+   lsr w3, w2, #16
+   ldr w4, =SVR_DEV_LS1043A
cmp w3, w4
b.ne1f
andsw2, w2, #0xff
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 08a42b9c9e..7c189530c1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -73,6 +73,7 @@ struct cpu_type {
 #define SVR_LS2041A0x870914
 
 #define SVR_DEV_LS2080A0x8701
+#define SVR_DEV_LS1043A0x8792
 
 #define SVR_MAJ(svr)   (((svr) >> 4) & 0xf)
 #define SVR_MIN(svr)   (((svr) >> 0) & 0xf)
@@ -81,6 +82,8 @@ struct cpu_type {
 #define IS_E_PROCESSOR(svr)(!((svr >> 8) & 0x1))
 #define IS_SVR_REV(svr, maj, min) \
((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
+#define IS_SVR_DEV(svr, dev) \
+   (((svr) >> 16) == (dev))
 
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG0xa003fffe
diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c
index 823beb32f6..c20c9a3567 100644
--- a/drivers/usb/common/fsl-errata.c
+++ b/drivers/usb/common/fsl-errata.c
@@ -198,6 +198,11 @@ bool has_erratum_a010151(void)
u32 svr = get_svr();
u32 soc = SVR_SOC_VER(svr);
 
+#ifdef CONFIG_ARM64
+   if (IS_SVR_DEV(svr, SVR_DEV_LS1043A))
+   return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+#endif
+
switch (soc) {
 #ifdef CONFIG_ARM64
case SVR_LS2080A:
@@ -209,8 +214,6 @@ bool has_erratum_a010151(void)
case SVR_LS1046A:
case SVR_LS1012A:
return IS_SVR_REV(svr, 1, 0);
-   case SVR_LS1043A:
-   return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
 #endif
 #ifdef CONFIG_ARCH_LS1021A
case SOC_VER_LS1020:
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 2/2] armv8: ls1043a: Discard the needless cpu nodes

[Wenbin song]

Using "cpu_pos_mask()" function to detect the real online cpus,
and discard the needless cpu nodes on kernel dft.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |  4 
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c   | 32 +++
 2 files changed, 36 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 47145a2432..971a98c6cc 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -176,6 +176,10 @@ config HAS_FEATURE_ENHANCED_MSI
bool
default y if ARCH_LS1043A
 
+config DISCARD_OFFLINE_CPU_NODES
+   bool
+   default y if ARCH_LS1043A
+
 menu "Layerscape PPA"
 config FSL_LS_PPA
bool "FSL Layerscape PPA firmware support"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 33f3e64848..241f0abe18 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -44,6 +44,38 @@ void ft_fixup_cpu(void *blob)
int addr_cells;
u64 val, core_id;
size_t *boot_code_size = &(__secondary_boot_code_size);
+
+#if defined(CONFIG_DISCARD_OFFLINE_CPU_NODES)
+   u32 mask = cpu_pos_mask();
+   int off_prev = -1;
+   int pos;
+
+   off = fdt_path_offset(blob, "/cpus");
+   if (off < 0) {
+   puts("couldn't find /cpus node\n");
+   return;
+   }
+
+   fdt_support_default_count_cells(blob, off, _cells, NULL);
+
+   off = fdt_node_offset_by_prop_value(blob, off_prev, "device_type",
+   "cpu", 4);
+   while (off != -FDT_ERR_NOTFOUND) {
+   reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
+   if (reg) {
+   core_id = fdt_read_number(reg, addr_cells);
+   pos = ((core_id & 0xff00) >> 5) + (core_id & 0xff);
+   if (!test_bit(pos, )) {
+   fdt_del_node(blob, off);
+   off = off_prev;
+   }
+   }
+   off_prev = off;
+   off = fdt_node_offset_by_prop_value(blob, off_prev,
+   "device_type", "cpu", 4);
+   }
+#endif
+
 #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
int node;
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] armv8: ls1046aqds: update IFC NOR timings

[Wenbin song]

Update IFC NOR timings to fix that the NOR flash can not
be erased with V4 FPGA image on ls1046aqds.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
 include/configs/ls1046aqds.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index df70bd398f..b619dc7939 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -194,10 +194,10 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NOR_FTIM1   (FTIM1_NOR_TACO(0x35) | \
FTIM1_NOR_TRAD_NOR(0x1a) | \
FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2   (FTIM2_NOR_TCS(0x4) | \
-   FTIM2_NOR_TCH(0x4) | \
+#define CONFIG_SYS_NOR_FTIM2   (FTIM2_NOR_TCS(0x8) | \
+   FTIM2_NOR_TCH(0x8) | \
FTIM2_NOR_TWPH(0xe) | \
-   FTIM2_NOR_TWP(0x1c))
+   FTIM2_NOR_TWP(0x38))
 #define CONFIG_SYS_NOR_FTIM3   0
 
 #define CONFIG_SYS_MAX_FLASH_BANKS 2   /* number of banks */
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [patch v3] armv8: ls1043a/ls1046aqds: fix the offsets of MTD partitions on Nor flash

[Wenbin song]

Fix the offsets of MTD partitions on Nor flash on ls1043ardb, ls1043aqds
and ls1046aqds boards.
Delete the rcw, uboot env and fman partitions.
Add user partitions for general usage.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
Changes for v1:
Delete the rcw, uboot env and fman partitions.
Add user partitions for general usage.
---
 include/configs/ls1043a_common.h | 14 --
 include/configs/ls1046aqds.h | 14 --
 2 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 9a01e48..d5d1388 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -188,12 +188,14 @@
 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
"5m(kernel),1m(dtb),9m(file_system)"
 #else
-#define MTDPARTS_DEFAULT "mtdparts=6000.nor:1m(nor_bank0_rcw)," \
-   "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
-   "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
-   "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
-   "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
-   "40m(nor_bank4_fit);7e80.flash:" \
+#define MTDPARTS_DEFAULT "mtdparts=6000.nor:" \
+   "2m@0x10(nor_bank0_uboot),"\
+   "40m@0x110(nor_bank0_fit)," \
+   "7m(nor_bank0_user)," \
+   "2m@0x410(nor_bank4_uboot)," \
+   "40m@0x510(nor_bank4_fit),"\
+   "-(nor_bank4_user);" \
+   "7e80.flash:" \
"1m(nand_uboot),1m(nand_uboot_env)," \
"20m(nand_fit);spi0.0:1m(uboot)," \
"5m(kernel),1m(dtb),9m(file_system)"
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 4b3b21e..476387d 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -485,12 +485,14 @@ unsigned long get_board_ddr_clk(void);
 #define MTDPARTS_DEFAULT "mtdparts=155.quadspi:2m(uboot)," \
"14m(free)"
 #else
-#define MTDPARTS_DEFAULT "mtdparts=6000.nor:1m(nor_bank0_rcw)," \
-   "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
-   "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
-   "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
-   "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
-   "40m(nor_bank4_fit);7e80.flash:" \
+#define MTDPARTS_DEFAULT "mtdparts=6000.nor:" \
+   "2m@0x10(nor_bank0_uboot),"\
+   "40m@0x110(nor_bank0_fit)," \
+   "7m(nor_bank0_user)," \
+   "2m@0x410(nor_bank4_uboot)," \
+   "40m@0x510(nor_bank4_fit),"\
+   "-(nor_bank4_user);" \
+   "7e80.flash:" \
"4m(nand_uboot),36m(nand_kernel)," \
"472m(nand_free);spi0.0:2m(uboot)," \
"14m(free)"
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [patch v2] armv8: ls1043a/ls1046aqds: fix the offsets of MTD partitions on Nor flash

[Wenbin song]

Fix the offsets of MTD partitions on Nor flash on ls1043ardb, ls1043aqds
and ls1046aqds boards.
Delete the rcw, uboot env and fman partitions.
Add user partitions for general usage.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
Changes for v1:
Delete the rcw, uboot env and fman partitions.
Add user partitions for general usage.
---
 include/configs/ls1043a_common.h | 14 --
 include/configs/ls1046aqds.h | 14 --
 2 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 9a01e48..b311d92 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -188,12 +188,14 @@
 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
"5m(kernel),1m(dtb),9m(file_system)"
 #else
-#define MTDPARTS_DEFAULT "mtdparts=6000.nor:1m(nor_bank0_rcw)," \
-   "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
-   "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
-   "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
-   "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
-   "40m(nor_bank4_fit);7e80.flash:" \
+#define MTDPARTS_DEFAULT "mtdparts=6000.nor:" \
+   "2m@10(nor_bank0_uboot),"\
+   "40m@110(nor_bank0_fit)," \
+   "7m(nor_bank0_user)," \
+   "2m@410(nor_bank4_uboot)," \
+   "40m@51(nor_bank4_fit);"\
+   "-(nor_bank4_user)," \
+   "7e80.flash:" \
"1m(nand_uboot),1m(nand_uboot_env)," \
"20m(nand_fit);spi0.0:1m(uboot)," \
"5m(kernel),1m(dtb),9m(file_system)"
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 4b3b21e..5cd9d4a 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -485,12 +485,14 @@ unsigned long get_board_ddr_clk(void);
 #define MTDPARTS_DEFAULT "mtdparts=155.quadspi:2m(uboot)," \
"14m(free)"
 #else
-#define MTDPARTS_DEFAULT "mtdparts=6000.nor:1m(nor_bank0_rcw)," \
-   "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
-   "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
-   "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
-   "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
-   "40m(nor_bank4_fit);7e80.flash:" \
+#define MTDPARTS_DEFAULT "mtdparts=6000.nor:" \
+   "2m@10(nor_bank0_uboot),"\
+   "40m@110(nor_bank0_fit)," \
+   "7m(nor_bank0_user)," \
+   "2m@410(nor_bank4_uboot)," \
+   "40m@51(nor_bank4_fit);"\
+   "-(nor_bank4_user)," \
+   "7e80.flash:" \
"4m(nand_uboot),36m(nand_kernel)," \
"472m(nand_free);spi0.0:2m(uboot)," \
"14m(free)"
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] armv8: ls1043a/ls1046aqds: fix the offsets of MTD partitions on Nor flash

[Wenbin Song]

Hi york,

Do you mean it is not necessary  to supply so much partitions for user, just 
supplying two partitions, one is reserved for firmware(including RCW, U-boot, 
Env, PPA, kernel.itb and so on), the other  is the rest of flashes, if not, 
Could you give me more details?

Best Regards
Wenbin Song



-Original Message-
From: york sun 
Sent: Thursday, March 16, 2017 1:14 AM
To: Wenbin Song <wenbin.s...@nxp.com>; Mingkai Hu <mingkai...@nxp.com>; 
s...@chromium.org; Z.Q. Hou <zhiqiang@nxp.com>; M.H. Lian 
<minghuan.l...@nxp.com>; u-boot@lists.denx.de
Subject: Re: [PATCH] armv8: ls1043a/ls1046aqds: fix the offsets of MTD 
partitions on Nor flash

On 03/13/2017 11:06 PM, Wenbin song wrote:
> Fix the offsets of MTD partitions on Nor flash on ls1043ardb, 
> ls1043aqds and ls1046aqds boards.
>
> Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
> ---
>  include/configs/ls1043a_common.h | 7 ---
>  include/configs/ls1046aqds.h | 7 ---
>  2 files changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/include/configs/ls1043a_common.h 
> b/include/configs/ls1043a_common.h
> index c4b05e0..ca845b6 100644
> --- a/include/configs/ls1043a_common.h
> +++ b/include/configs/ls1043a_common.h
> @@ -192,10 +192,11 @@
>  #else
>  #define MTDPARTS_DEFAULT "mtdparts=6000.nor:1m(nor_bank0_rcw)," \
>   "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
> - "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
> - "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
> + "1m(nor_bank0_fman_uconde),"\
> + "40m@110(nor_bank0_fit)," \
> + "1m@400(nor_bank4_rcw),1m(nor_bank4_uboot)," \
>   "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
> - "40m(nor_bank4_fit);7e80.flash:" \
> + "40m@510(nor_bank4_fit);7e80.flash:" \
>   "1m(nand_uboot),1m(nand_uboot_env)," \
>   "20m(nand_fit);spi0.0:1m(uboot)," \
>   "5m(kernel),1m(dtb),9m(file_system)"
> diff --git a/include/configs/ls1046aqds.h 
> b/include/configs/ls1046aqds.h index 4b3b21e..e045249 100644
> --- a/include/configs/ls1046aqds.h
> +++ b/include/configs/ls1046aqds.h
> @@ -487,10 +487,11 @@ unsigned long get_board_ddr_clk(void);  #else  
> #define MTDPARTS_DEFAULT "mtdparts=6000.nor:1m(nor_bank0_rcw)," \
>   "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
> - "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
> - "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
> + "1m(nor_bank0_fman_uconde),"\
> + "40m@110(nor_bank0_fit)," \
> + "1m@400(nor_bank4_rcw),1m(nor_bank4_uboot)," \
>   "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
> - "40m(nor_bank4_fit);7e80.flash:" \
> + "40m@510(nor_bank4_fit);7e80.flash:" \
>   "4m(nand_uboot),36m(nand_kernel)," \
>   "472m(nand_free);spi0.0:2m(uboot)," \
>   "14m(free)"
>

Wenbin,

Maybe you can use more generic partitions for the NOR and put more detail in 
comment. I believe the RCW, U-Boot, Env, Fman ucode, PPA are at fixed 
locations. But the rest is up to user. We cannot assume the layout is identical 
to SDK. Same goes to NAND partitions.

York
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] armv8: ls1043a/ls1046aqds: fix the offsets of MTD partitions on Nor flash

[Wenbin song]

Fix the offsets of MTD partitions on Nor flash on ls1043ardb, ls1043aqds
and ls1046aqds boards.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
 include/configs/ls1043a_common.h | 7 ---
 include/configs/ls1046aqds.h | 7 ---
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index c4b05e0..ca845b6 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -192,10 +192,11 @@
 #else
 #define MTDPARTS_DEFAULT "mtdparts=6000.nor:1m(nor_bank0_rcw)," \
"1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
-   "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
-   "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
+   "1m(nor_bank0_fman_uconde),"\
+   "40m@110(nor_bank0_fit)," \
+   "1m@400(nor_bank4_rcw),1m(nor_bank4_uboot)," \
"1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
-   "40m(nor_bank4_fit);7e80.flash:" \
+   "40m@510(nor_bank4_fit);7e80.flash:" \
"1m(nand_uboot),1m(nand_uboot_env)," \
"20m(nand_fit);spi0.0:1m(uboot)," \
"5m(kernel),1m(dtb),9m(file_system)"
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 4b3b21e..e045249 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -487,10 +487,11 @@ unsigned long get_board_ddr_clk(void);
 #else
 #define MTDPARTS_DEFAULT "mtdparts=6000.nor:1m(nor_bank0_rcw)," \
"1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
-   "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
-   "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
+   "1m(nor_bank0_fman_uconde),"\
+   "40m@110(nor_bank0_fit)," \
+   "1m@400(nor_bank4_rcw),1m(nor_bank4_uboot)," \
"1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
-   "40m(nor_bank4_fit);7e80.flash:" \
+   "40m@510(nor_bank4_fit);7e80.flash:" \
"4m(nand_uboot),36m(nand_kernel)," \
"472m(nand_free);spi0.0:2m(uboot)," \
"14m(free)"
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [RESEND V7 1/2] armv8/ls1043a: fixup GIC offset for ls1043a rev1

[Wenbin song]

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment
and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose
which offset will be used.

The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment.

If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used.
64K alignment is the default setting.

Overriding the weak smp_kick_all_cpus, the new impletment is able to detect
GIC offset.

The default GIC offset in kernel device tree is using 4K alignment, it
need to be fixed if 64K alignment is detected.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
Changes in v7:
Use the full SVR to check if a Soc needs the fix.
Use 4K alignment as the default alignment.
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  4 ++
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 64 ++
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   | 55 +--
 arch/arm/include/asm/arch-fsl-layerscape/config.h  | 24 
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  3 +-
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |  1 +
 6 files changed, 146 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index cc0dc88..cb24ce7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -168,4 +168,8 @@ config SYS_FSL_DDR4
help
  Enable Freescale DDR4 controller.
 
+config HAS_FEATURE_GIC64K_ALIGN
+   bool
+   default y if ARCH_LS1043A
+
 endmenu
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index c10ccf9..3244a21 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -133,6 +133,67 @@ void fsl_fdt_disable_usb(void *blob)
}
 }
 
+#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
+static void fdt_fixup_gic(void *blob)
+{
+   int offset, err;
+   u64 reg[8];
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   unsigned int val;
+   struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+   int align_64k = 0;
+
+   val = gur_in32(>svr);
+
+   if (SVR_SOC_VER(val) != SVR_LS1043A) {
+   align_64k = 1;
+   } else if (SVR_REV(val) != REV1_0) {
+   val = scfg_in32(>gic_align) & (0x01 << GIC_ADDR_BIT);
+   if (!val)
+   align_64k = 1;
+   }
+
+   offset = fdt_subnode_offset(blob, 0, "interrupt-controller@140");
+   if (offset < 0) {
+   printf("WARNING: fdt_subnode_offset can't find node %s: %s\n",
+  "interrupt-controller@140", fdt_strerror(offset));
+   return;
+   }
+
+   /* Fixup gic node align with 64K */
+   if (align_64k) {
+   reg[0] = cpu_to_fdt64(GICD_BASE_64K);
+   reg[1] = cpu_to_fdt64(GICD_SIZE_64K);
+   reg[2] = cpu_to_fdt64(GICC_BASE_64K);
+   reg[3] = cpu_to_fdt64(GICC_SIZE_64K);
+   reg[4] = cpu_to_fdt64(GICH_BASE_64K);
+   reg[5] = cpu_to_fdt64(GICH_SIZE_64K);
+   reg[6] = cpu_to_fdt64(GICV_BASE_64K);
+   reg[7] = cpu_to_fdt64(GICV_SIZE_64K);
+   } else {
+   /* Fixup gic node align with 4K */
+   reg[0] = cpu_to_fdt64(GICD_BASE);
+   reg[1] = cpu_to_fdt64(GICD_SIZE);
+   reg[2] = cpu_to_fdt64(GICC_BASE);
+   reg[3] = cpu_to_fdt64(GICC_SIZE);
+   reg[4] = cpu_to_fdt64(GICH_BASE);
+   reg[5] = cpu_to_fdt64(GICH_SIZE);
+   reg[6] = cpu_to_fdt64(GICV_BASE);
+   reg[7] = cpu_to_fdt64(GICV_SIZE);
+   }
+
+   err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg));
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
+  "reg", "interrupt-controller@140",
+  fdt_strerror(err));
+   return;
+   }
+
+   return;
+}
+#endif
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 #ifdef CONFIG_FSL_LSCH2
@@ -177,4 +238,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #endif
fsl_fdt_disable_usb(blob);
 
+#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
+   fdt_fixup_gic(blob);
+#endif
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 72f2c11..67c9636 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -19,6 +19,53 @@
 #endif
 #include 
 
+/* Get GIC offset
+* For LS1043a rev1.0, GIC base address align with 4k.
+* For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
+* is set, GI

[U-Boot] [RESEND V7 2/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI node

[Wenbin song]

The default MSI node in kernel tree is for LS1043A rev1.0 silicon,
if rev1.1 silicon used, need to fixup the MSI node to match it.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
Changes in v7:
Use a new MSI node on rev1.1.
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |   3 +
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c   | 154 ++
 2 files changed, 157 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index cb24ce7..0941bf8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -172,4 +172,7 @@ config HAS_FEATURE_GIC64K_ALIGN
bool
default y if ARCH_LS1043A
 
+config HAS_FEATURE_ENHANCED_MSI
+   bool
+   default y if ARCH_LS1043A
 endmenu
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 3244a21..4a1683a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -194,6 +194,157 @@ static void fdt_fixup_gic(void *blob)
 }
 #endif
 
+#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
+static int _fdt_fixup_msi_node(void *blob, const char *name,
+ int irq_0, int irq_1, int rev)
+{
+   int err, offset, len;
+   u32 tmp[4][3];
+   void *p;
+
+   offset = fdt_path_offset(blob, name);
+   if (offset < 0) {
+   printf("WARNING: fdt_path_offset can't find path %s: %s\n",
+  name, fdt_strerror(offset));
+   return 0;
+   }
+
+   /*fixup the property of interrupts*/
+
+   tmp[0][0] = cpu_to_fdt32(0x0);
+   tmp[0][1] = cpu_to_fdt32(irq_0);
+   tmp[0][2] = cpu_to_fdt32(0x4);
+
+   if (rev > REV1_0) {
+   tmp[1][0] = cpu_to_fdt32(0x0);
+   tmp[1][1] = cpu_to_fdt32(irq_1);
+   tmp[1][2] = cpu_to_fdt32(0x4);
+   tmp[2][0] = cpu_to_fdt32(0x0);
+   tmp[2][1] = cpu_to_fdt32(irq_1 + 1);
+   tmp[2][2] = cpu_to_fdt32(0x4);
+   tmp[3][0] = cpu_to_fdt32(0x0);
+   tmp[3][1] = cpu_to_fdt32(irq_1 + 2);
+   tmp[3][2] = cpu_to_fdt32(0x4);
+   len = sizeof(tmp);
+   } else {
+   len = sizeof(tmp[0]);
+   }
+
+   err = fdt_setprop(blob, offset, "interrupts", tmp, len);
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
+  "interrupts", name, fdt_strerror(err));
+   return 0;
+   }
+
+   /*fixup the property of reg*/
+   p = (char *)fdt_getprop(blob, offset, "reg", );
+   if (!p) {
+   printf("WARNING: fdt_getprop can't get %s from node %s\n",
+  "reg", name);
+   return 0;
+   }
+
+   memcpy((char *)tmp, p, len);
+
+   if (rev > REV1_0)
+   *((u32 *)tmp + 3) = cpu_to_fdt32(0x1000);
+   else
+   *((u32 *)tmp + 3) = cpu_to_fdt32(0x8);
+
+   err = fdt_setprop(blob, offset, "reg", tmp, len);
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
+  "reg", name, fdt_strerror(err));
+   return 0;
+   }
+
+   /*fixup the property of compatible*/
+   if (rev > REV1_0)
+   err = fdt_setprop_string(blob, offset, "compatible",
+"fsl,ls1043a-v1.1-msi");
+   else
+   err = fdt_setprop_string(blob, offset, "compatible",
+"fsl,ls1043a-msi");
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
+  "compatible", name, fdt_strerror(err));
+   return 0;
+   }
+
+   return 1;
+}
+
+static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev)
+{
+   int offset, len, err;
+   void *p;
+   int val;
+   u32 tmp[4][8];
+
+   offset = fdt_path_offset(blob, name);
+   if (offset < 0) {
+   printf("WARNING: fdt_path_offset can't find path %s: %s\n",
+  name, fdt_strerror(offset));
+   return 0;
+   }
+
+   p = (char *)fdt_getprop(blob, offset, "interrupt-map", );
+   if (!p || len != sizeof(tmp)) {
+   printf("WARNING: fdt_getprop can't get %s from node %s\n",
+  "interrupt-map", name);
+   return 0;
+   }
+
+   memcpy((char *)tmp, p, len);
+
+   val = fdt32_to_cpu(tmp[0][6]);
+   if (rev > REV1_0) {
+   tmp[1][6] = cpu_to_fdt32(val + 1)

Re: [U-Boot] [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node

[Wenbin Song]

Hi, york

Because the other patch [patch v6 2/2 ] in this set depends on the format of  
MSI  node  which is not yet ready to upstream. 
I planed  to send them together. 

Do you have any idea?


Best Regards
Wenbin Song

> -Original Message-
> From: york sun
> Sent: Friday, December 09, 2016 3:07 AM
> To: Wenbin Song <wenbin.s...@nxp.com>; albert.u.b...@aribaud.net;
> Mingkai Hu <mingkai...@nxp.com>; u-boot@lists.denx.de
> Subject: Re: [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC
> node
> 
> On 11/16/2016 05:14 PM, Wenbin Song wrote:
> > []  ok, I will make this change  in the next version of the patch.
> >
> 
> Wenbin,
> 
> Have you sent an update for this set?
> 
> York

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node

[Wenbin Song]

Hi, york

Best Regards
Wenbin Song


> -Original Message-
> From: york sun
> Sent: Thursday, November 17, 2016 1:05 AM
> To: Wenbin Song <wenbin.s...@nxp.com>; albert.u.b...@aribaud.net;
> Mingkai Hu <mingkai...@nxp.com>; u-boot@lists.denx.de
> Subject: Re: [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC
> node
> 
> On 11/16/2016 01:23 AM, Wenbin Song wrote:
> > Hi: york
> >
> > Best Regards
> > Wenbin Song
> >
> >
> >> -Original Message-----
> >> From: york sun
> >> Sent: Tuesday, November 15, 2016 5:24 AM
> >> To: Wenbin Song <wenbin.s...@nxp.com>; albert.u.b...@aribaud.net;
> >> Mingkai Hu <mingkai...@nxp.com>; u-boot@lists.denx.de
> >> Subject: Re: [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A
> >> rev1 GIC node
> >>
> >> On 10/31/2016 08:35 PM, Wenbin song wrote:
> >>> The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
> >>> alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
> >>> is used to choose which offset will be used. If GIC_ADDR_BIT bit is
> >>> set, 4K alignment is used, or else 64K alignment is used. The rev1.0
> >>> silicon only supports the CIG offset with 4K alignment.
> >>
> >> Wenbin,
> >>
> >> According to your patch and your explanation, the rev 1 SoC supports
> >> 4K alignment only. The rev 1.1 and newer SoC supports both 4K and
> >> 64K. If you don't do anything in PBI, the default is 64K.
> >
> > [] yes. You are  correct .
> 
> I would prefer it has 4K alignment if you do nothing in PBI. But I guess it 
> is too
> late to change the hardware.
> 
> >
> > Does this 64k alignment apply to
> >> any other SoCs?
> >>
> > []   This patch only apply  to ls1043a.  and the other SOCs  only support 
> > one
> kind of alignment style.  For example, ls1046a align with 64k, ls1012a align 
> with
> 4k.
> 
> In this case, you patch is OK. You can add full SVR check if a future SoC 
> needs
> the same fix.

[]  ok, I will make this change  in the next version of the patch.
 

> 
> York
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node

[Wenbin Song]

Hi: york

Best Regards
Wenbin Song


> -Original Message-
> From: york sun
> Sent: Tuesday, November 15, 2016 5:24 AM
> To: Wenbin Song <wenbin.s...@nxp.com>; albert.u.b...@aribaud.net;
> Mingkai Hu <mingkai...@nxp.com>; u-boot@lists.denx.de
> Subject: Re: [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC
> node
> 
> On 10/31/2016 08:35 PM, Wenbin song wrote:
> > The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
> > alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
> > is used to choose which offset will be used. If GIC_ADDR_BIT bit is
> > set, 4K alignment is used, or else 64K alignment is used. The rev1.0
> > silicon only supports the CIG offset with 4K alignment.
> 
> Wenbin,
> 
> According to your patch and your explanation, the rev 1 SoC supports 4K
> alignment only. The rev 1.1 and newer SoC supports both 4K and 64K. If you
> don't do anything in PBI, the default is 64K. 

[] yes. You are  correct .

Does this 64k alignment apply to
> any other SoCs?
> 
[]   This patch only apply  to ls1043a.  and the other SOCs  only support one 
kind of alignment style.  For example, ls1046a align with 64k, ls1012a align 
with 4k.
> York
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v6 2/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI node

[Wenbin Song]

Hi: york

There is  a bit of change for  MSI node of kernel , so I will update this patch 
on next version and with new comments you mentioned. 

Best Regards
Wenbin Song


> -Original Message-
> From: york sun
> Sent: Tuesday, November 15, 2016 5:36 AM
> To: Wenbin Song <wenbin.s...@nxp.com>; albert.u.b...@aribaud.net;
> Mingkai Hu <mingkai...@nxp.com>; u-boot@lists.denx.de
> Subject: Re: [PATCH v6 2/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI
> node
> 
> On 10/31/2016 08:35 PM, Wenbin song wrote:
> > There are two types of msi node in kernel device tree, one is for
> > LS1043A rev1.1 silicon, the other is for rev1.0.
> 
> This doesn't explain the difference between the two versions. I don't see
> comments below either.
> 
> >
> > According to revision number, fixup the msi node.
> >
> > Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
> > Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
> > ---
> > Change in v6:
> > None
> > Change in v5:
> > Fixup the msi node used on rev1.0 when running on rev1.1.
> > ---
> >  arch/arm/cpu/armv8/fsl-layerscape/Kconfig |   3 +
> >  arch/arm/cpu/armv8/fsl-layerscape/fdt.c   | 115
> ++
> >  2 files changed, 118 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > index f415868..34ac867 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > @@ -139,4 +139,7 @@ config HAS_FEATURE_GIC4K_ALIGN
> > bool
> > default y if ARCH_LS1043A
> >
> > +config HAS_FEATURE_ENHANCED_MSI
> > +   bool
> > +   default y if ARCH_LS1043A
> >  endmenu
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> > index 9936be1..e87ba19 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> > @@ -194,6 +194,118 @@ static void fdt_fixup_gic(void *blob)  }  #endif
> >
> > +#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI static int
> > +_fdt_fixup_msi_subnode(void *blob, int offset, const char *name,
> > + int irq_0, int irq_1, int rev)
> > +{
> > +   int err, sub_offset, len;
> > +   u32 tmp[4][3];
> > +
> > +   sub_offset = fdt_subnode_offset(blob, offset, name);
> > +   if (offset < 0) {
> > +   printf("WARNING: fdt_subnode_offset can't find %s: %s\n",
> > +  name, fdt_strerror(sub_offset));
> > +   return 0;
> > +   }
> > +
> > +   tmp[0][0] = cpu_to_fdt32(0x0);
> > +   tmp[0][1] = cpu_to_fdt32(irq_0);
> > +   tmp[0][2] = cpu_to_fdt32(0x4);
> > +
> > +   if (rev > REV1_0) {
> > +   tmp[1][0] = cpu_to_fdt32(0x0);
> > +   tmp[1][1] = cpu_to_fdt32(irq_1);
> > +   tmp[1][2] = cpu_to_fdt32(0x4);
> > +   tmp[2][0] = cpu_to_fdt32(0x0);
> > +   tmp[2][1] = cpu_to_fdt32(irq_1 + 1);
> > +   tmp[2][2] = cpu_to_fdt32(0x4);
> > +   tmp[3][0] = cpu_to_fdt32(0x0);
> > +   tmp[3][1] = cpu_to_fdt32(irq_1 + 2);
> > +   tmp[3][2] = cpu_to_fdt32(0x4);
> > +   len = sizeof(tmp);
> 
> Looks like you are adding three more interrupts. Some comments here would
> be nice.
> 
> > +   } else {
> > +   len = sizeof(tmp[0]);
> > +   }
> > +
> > +   err = fdt_setprop(blob, sub_offset, "interrupts", tmp, len);
> > +   if (err < 0) {
> > +   printf("WARNING: fdt_setprop can't set %s from
> node %s: %s\n",
> > +  "interrupts", name, fdt_strerror(err));
> > +   return 0;
> > +   }
> > +
> > +   return 1;
> > +}
> > +
> > +static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev)
> > +{
> > +   int offset, len, err;
> > +   void *p;
> > +   int val;
> > +   u32 tmp[4][8];
> > +
> > +   offset = fdt_path_offset(blob, name);
> > +   if (offset < 0) {
> > +   printf("WARNING: fdt_path_offset can't find path %s: %s\n",
> > +  name, fdt_strerror(offset));
> > +   return 0;
> > +   }
> > +
> > +   p = (char *)fdt_getprop(blob, offset, "interrupt-map", );
> > +   if (!p || len != sizeof(tmp)) {
> 
> Is the length check always accurate here?
> 
> > +   printf("WARNIN

[U-Boot] [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node

[Wenbin song]

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment
and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose
which offset will be used. If GIC_ADDR_BIT bit is set, 4K alignment is used,
or else 64K alignment is used. The rev1.0 silicon only supports the CIG offset
with 4K alignment.

GIC offset is decided by SVR and GIC_ADDR_BIT bit.

Overriding the weak smp_kick_all_cpus, the new impletment is able to detect
GIC offset.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
Changes in v6:
Add comments around checking the revision. 
Changes in v5:
Replace fix_gic_off with get_gic_off.
Add #if condition to check CONFIG_GICV2 and CONFIG_GICV3 on 
smp_kick_all_cpus.
Fixup gic node with 64K alignment when running on rev1.1 with 
GIC_ADDR_BIT cleared. 
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  4 ++
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 71 ++
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   | 57 +++--
 arch/arm/include/asm/arch-fsl-layerscape/config.h  | 26 +++-
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  3 +-
 5 files changed, 154 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 94ec8d5..f415868 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -135,4 +135,8 @@ config SYS_FSL_DDR4
help
  Enable Freescale DDR4 controller.
 
+config HAS_FEATURE_GIC4K_ALIGN
+   bool
+   default y if ARCH_LS1043A
+
 endmenu
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 1a8321b..9936be1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -126,6 +126,74 @@ void fsl_fdt_disable_usb(void *blob)
}
 }
 
+#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
+static void fdt_fixup_gic(void *blob)
+{
+   int offset, err;
+   u64 reg[8];
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   unsigned int rev;
+   struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+   int align_4k = 1;
+
+   rev = gur_in32(>svr) & 0xff;
+   /*
+* For ls1043a rev1.0, the GIC offset aligns with 4K.
+* For ls1043a rev1.1 or more higher, the GIC offset
+* is decided by gic_align register.
+*/
+
+   if (rev > REV1_0) {
+   /*
+* The GIC_ADDR_BIT on gic_align was set by
+* PBI to select GIC offset.
+*/
+   rev = scfg_in32(>gic_align) & (0x01 << GIC_ADDR_BIT);
+   if (!rev)
+   align_4k = 0;
+   }
+
+   offset = fdt_subnode_offset(blob, 0, "interrupt-controller@140");
+   if (offset < 0) {
+   printf("WARNING: fdt_subnode_offset can't find node %s: %s\n",
+  "interrupt-controller@140", fdt_strerror(offset));
+   return;
+   }
+
+   /* Fixup gic node align with 4K */
+   if (align_4k) {
+   reg[0] = cpu_to_fdt64(GICD_BASE_4K);
+   reg[1] = cpu_to_fdt64(GICD_SIZE_4K);
+   reg[2] = cpu_to_fdt64(GICC_BASE_4K);
+   reg[3] = cpu_to_fdt64(GICC_SIZE_4K);
+   reg[4] = cpu_to_fdt64(GICH_BASE_4K);
+   reg[5] = cpu_to_fdt64(GICH_SIZE_4K);
+   reg[6] = cpu_to_fdt64(GICV_BASE_4K);
+   reg[7] = cpu_to_fdt64(GICV_SIZE_4K);
+   } else {
+   /* Fixup gic node align with 64K */
+   reg[0] = cpu_to_fdt64(GICD_BASE);
+   reg[1] = cpu_to_fdt64(GICD_SIZE);
+   reg[2] = cpu_to_fdt64(GICC_BASE);
+   reg[3] = cpu_to_fdt64(GICC_SIZE);
+   reg[4] = cpu_to_fdt64(GICH_BASE);
+   reg[5] = cpu_to_fdt64(GICH_SIZE);
+   reg[6] = cpu_to_fdt64(GICV_BASE);
+   reg[7] = cpu_to_fdt64(GICV_SIZE);
+   }
+
+   err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg));
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
+  "reg", "interrupt-controller@140",
+  fdt_strerror(err));
+   return;
+   }
+
+   return;
+}
+#endif
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 #ifdef CONFIG_FSL_LSCH2
@@ -170,4 +238,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #endif
fsl_fdt_disable_usb(blob);
 
+#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
+   fdt_fixup_gic(blob);
+#endif
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5d0b7a4..d50096c 100644
--- a/arch/arm/cpu/armv8/fsl

[U-Boot] [PATCH v6 2/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI node

[Wenbin song]

There are two types of msi node in kernel device tree, one is for
LS1043A rev1.1 silicon, the other is for rev1.0.

According to revision number, fixup the msi node.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
Change in v6:
None
Change in v5:
Fixup the msi node used on rev1.0 when running on rev1.1.   
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |   3 +
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c   | 115 ++
 2 files changed, 118 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index f415868..34ac867 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -139,4 +139,7 @@ config HAS_FEATURE_GIC4K_ALIGN
bool
default y if ARCH_LS1043A
 
+config HAS_FEATURE_ENHANCED_MSI
+   bool
+   default y if ARCH_LS1043A
 endmenu
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 9936be1..e87ba19 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -194,6 +194,118 @@ static void fdt_fixup_gic(void *blob)
 }
 #endif
 
+#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
+static int _fdt_fixup_msi_subnode(void *blob, int offset, const char *name,
+ int irq_0, int irq_1, int rev)
+{
+   int err, sub_offset, len;
+   u32 tmp[4][3];
+
+   sub_offset = fdt_subnode_offset(blob, offset, name);
+   if (offset < 0) {
+   printf("WARNING: fdt_subnode_offset can't find %s: %s\n",
+  name, fdt_strerror(sub_offset));
+   return 0;
+   }
+
+   tmp[0][0] = cpu_to_fdt32(0x0);
+   tmp[0][1] = cpu_to_fdt32(irq_0);
+   tmp[0][2] = cpu_to_fdt32(0x4);
+
+   if (rev > REV1_0) {
+   tmp[1][0] = cpu_to_fdt32(0x0);
+   tmp[1][1] = cpu_to_fdt32(irq_1);
+   tmp[1][2] = cpu_to_fdt32(0x4);
+   tmp[2][0] = cpu_to_fdt32(0x0);
+   tmp[2][1] = cpu_to_fdt32(irq_1 + 1);
+   tmp[2][2] = cpu_to_fdt32(0x4);
+   tmp[3][0] = cpu_to_fdt32(0x0);
+   tmp[3][1] = cpu_to_fdt32(irq_1 + 2);
+   tmp[3][2] = cpu_to_fdt32(0x4);
+   len = sizeof(tmp);
+   } else {
+   len = sizeof(tmp[0]);
+   }
+
+   err = fdt_setprop(blob, sub_offset, "interrupts", tmp, len);
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
+  "interrupts", name, fdt_strerror(err));
+   return 0;
+   }
+
+   return 1;
+}
+
+static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev)
+{
+   int offset, len, err;
+   void *p;
+   int val;
+   u32 tmp[4][8];
+
+   offset = fdt_path_offset(blob, name);
+   if (offset < 0) {
+   printf("WARNING: fdt_path_offset can't find path %s: %s\n",
+  name, fdt_strerror(offset));
+   return 0;
+   }
+
+   p = (char *)fdt_getprop(blob, offset, "interrupt-map", );
+   if (!p || len != sizeof(tmp)) {
+   printf("WARNING: fdt_getprop can't get %s from node %s\n",
+  "interrupt-map", name);
+   return 0;
+   }
+
+   memcpy((char *)tmp, p, len);
+
+   val = fdt32_to_cpu(tmp[0][6]);
+   if (rev > REV1_0) {
+   tmp[1][6] = cpu_to_fdt32(val + 1);
+   tmp[2][6] = cpu_to_fdt32(val + 2);
+   tmp[3][6] = cpu_to_fdt32(val + 3);
+   } else {
+   tmp[1][6] = cpu_to_fdt32(val);
+   tmp[2][6] = cpu_to_fdt32(val);
+   tmp[3][6] = cpu_to_fdt32(val);
+   }
+
+   err = fdt_setprop(blob, offset, "interrupt-map", tmp, sizeof(tmp));
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s.\n",
+  "interrupt-map", name, fdt_strerror(err));
+   return 0;
+   }
+   return 1;
+}
+
+/* Fixup msi to v1_0*/
+
+static void fdt_fixup_msi(void *blob)
+{
+   int nodeoffset;
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   unsigned int rev;
+
+   rev = gur_in32(>svr) & 0xff;
+
+   nodeoffset = fdt_path_offset(blob, "/soc/msi-controller");
+   if (nodeoffset < 0) {
+   printf("WARNING: fdt_path_offset can't find path %s: %s\n",
+  "/soc/msi-controller", fdt_strerror(nodeoffset));
+   return;
+   }
+   _fdt_fixup_msi_subnode(blob, nodeoffset, "msi0@1571000", 116, 111, rev);
+   _fdt_fixup_msi_subnode(blob, nodeoffset, "msi1@1572000"

Re: [U-Boot] [PATCH v5 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node

[Wenbin Song]

Hi york:


Best Regards
Wenbin Song

> -Original Message-
> From: york sun
> Sent: Friday, October 28, 2016 11:40 PM
> To: Wenbin Song <wenbin.s...@nxp.com>; albert.u.b...@aribaud.net;
> Mingkai Hu <mingkai...@nxp.com>; u-boot@lists.denx.de
> Subject: Re: [PATCH v5 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC
> node
> 
> On 10/27/2016 02:06 AM, Wenbin song wrote:
> > The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
> > alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
> > is used to choose which offset will be used. If GIC_ADDR_BIT bit is
> > set, 4K alignment is used, or else 64K alignment is used. The rev1.0
> > silicon only supports the CIG offset with 4K alignment.
> >
> > GIC offset is decided by SVR and GIC_ADDR_BIT bit.
> >
> > Overriding the weak smp_kick_all_cpus, the new impletment is able to
> > detect GIC offset.
> >
> > Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
> > Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
> > ---
> > Changes in v5:
> > Replace fix_gic_off with get_gic_off.
> > Add #if condition to check CONFIG_GICV2 and CONFIG_GICV3 on
> smp_kick_all_cpus.
> > Fixup gic node with 64K alignment when running on rev1.1 with
> GIC_ADDR_BIT cleared.
> > ---
> 
> 
> 
> >
> > +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN static void fdt_fixup_gic(void
> > +*blob) {
> > +   int offset, err;
> > +   u64 reg[8];
> > +   struct ccsr_gur __iomem *gur = (void
> *)(CONFIG_SYS_FSL_GUTS_ADDR);
> > +   unsigned int rev;
> > +   struct ccsr_scfg __iomem *scfg = (void
> *)CONFIG_SYS_FSL_SCFG_ADDR;
> > +   int align_4k = 1;
> > +
> > +   rev = gur_in32(>svr) & 0xff;
> > +
> > +   if (rev > REV1_0) {
> > +   rev = scfg_in32(>gic_align) & (0x01 << GIC_ADDR_BIT);
> > +   if (!rev)
> > +   align_4k = 0;
> > +   }
> > +
> 
> Does this register scfg->gic_align exist for other SoCs? Can you get a 
> consistent
> reading from this register if not set by PBI? If yes, can you revert the 
> logic in PBI
> command to set this bit in backward compatible way?


[]  scfg->gic_align  is a new added  register on ls1043a rev1.1 or more higher  
to select the GIC offset by PBI.
If it is set by PBI,  GIC offset is 4K alignment.
If it is cleared by PBI, GIC offset is 64K alignment.
The reset value is cleared.

So for ls1043a rev1.1 or more higher , we are be able to select the GIC offset  
by using different rcw. 
If  not set by PBI, reading from it always gets  0. 

 And the scfg->gic_align is reserved for other SoCs. 
> 
> York

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v5 2/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI node

[Wenbin song]

There are two types of msi node in kernel device tree, one is for
LS1043A rev1.1 silicon, the other is for rev1.0.

According to revision number, fixup the msi node.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
Change in v5:
Fixup the msi node used on rev1.0 when running on rev1.1.   
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |   3 +
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c   | 115 ++
 2 files changed, 118 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index f415868..34ac867 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -139,4 +139,7 @@ config HAS_FEATURE_GIC4K_ALIGN
bool
default y if ARCH_LS1043A
 
+config HAS_FEATURE_ENHANCED_MSI
+   bool
+   default y if ARCH_LS1043A
 endmenu
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index e90adb0..5bac380 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -185,6 +185,118 @@ static void fdt_fixup_gic(void *blob)
 }
 #endif
 
+#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
+static int _fdt_fixup_msi_subnode(void *blob, int offset, const char *name,
+ int irq_0, int irq_1, int rev)
+{
+   int err, sub_offset, len;
+   u32 tmp[4][3];
+
+   sub_offset = fdt_subnode_offset(blob, offset, name);
+   if (offset < 0) {
+   printf("WARNING: fdt_subnode_offset can't find %s: %s\n",
+  name, fdt_strerror(sub_offset));
+   return 0;
+   }
+
+   tmp[0][0] = cpu_to_fdt32(0x0);
+   tmp[0][1] = cpu_to_fdt32(irq_0);
+   tmp[0][2] = cpu_to_fdt32(0x4);
+
+   if (rev > REV1_0) {
+   tmp[1][0] = cpu_to_fdt32(0x0);
+   tmp[1][1] = cpu_to_fdt32(irq_1);
+   tmp[1][2] = cpu_to_fdt32(0x4);
+   tmp[2][0] = cpu_to_fdt32(0x0);
+   tmp[2][1] = cpu_to_fdt32(irq_1 + 1);
+   tmp[2][2] = cpu_to_fdt32(0x4);
+   tmp[3][0] = cpu_to_fdt32(0x0);
+   tmp[3][1] = cpu_to_fdt32(irq_1 + 2);
+   tmp[3][2] = cpu_to_fdt32(0x4);
+   len = sizeof(tmp);
+   } else {
+   len = sizeof(tmp[0]);
+   }
+
+   err = fdt_setprop(blob, sub_offset, "interrupts", tmp, len);
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
+  "interrupts", name, fdt_strerror(err));
+   return 0;
+   }
+
+   return 1;
+}
+
+static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev)
+{
+   int offset, len, err;
+   void *p;
+   int val;
+   u32 tmp[4][8];
+
+   offset = fdt_path_offset(blob, name);
+   if (offset < 0) {
+   printf("WARNING: fdt_path_offset can't find path %s: %s\n",
+  name, fdt_strerror(offset));
+   return 0;
+   }
+
+   p = (char *)fdt_getprop(blob, offset, "interrupt-map", );
+   if (!p || len != sizeof(tmp)) {
+   printf("WARNING: fdt_getprop can't get %s from node %s\n",
+  "interrupt-map", name);
+   return 0;
+   }
+
+   memcpy((char *)tmp, p, len);
+
+   val = fdt32_to_cpu(tmp[0][6]);
+   if (rev > REV1_0) {
+   tmp[1][6] = cpu_to_fdt32(val + 1);
+   tmp[2][6] = cpu_to_fdt32(val + 2);
+   tmp[3][6] = cpu_to_fdt32(val + 3);
+   } else {
+   tmp[1][6] = cpu_to_fdt32(val);
+   tmp[2][6] = cpu_to_fdt32(val);
+   tmp[3][6] = cpu_to_fdt32(val);
+   }
+
+   err = fdt_setprop(blob, offset, "interrupt-map", tmp, sizeof(tmp));
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s.\n",
+  "interrupt-map", name, fdt_strerror(err));
+   return 0;
+   }
+   return 1;
+}
+
+/* Fixup msi to v1_0*/
+
+static void fdt_fixup_msi(void *blob)
+{
+   int nodeoffset;
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   unsigned int rev;
+
+   rev = gur_in32(>svr) & 0xff;
+
+   nodeoffset = fdt_path_offset(blob, "/soc/msi-controller");
+   if (nodeoffset < 0) {
+   printf("WARNING: fdt_path_offset can't find path %s: %s\n",
+  "/soc/msi-controller", fdt_strerror(nodeoffset));
+   return;
+   }
+   _fdt_fixup_msi_subnode(blob, nodeoffset, "msi0@1571000", 116, 111, rev);
+   _fdt_fixup_msi_subnode(blob, nodeoffset, "msi1@1572000", 126, 121, rev);

[U-Boot] [PATCH v5 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node

[Wenbin song]

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment
and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose
which offset will be used. If GIC_ADDR_BIT bit is set, 4K alignment is used,
or else 64K alignment is used. The rev1.0 silicon only supports the CIG offset
with 4K alignment.

GIC offset is decided by SVR and GIC_ADDR_BIT bit.

Overriding the weak smp_kick_all_cpus, the new impletment is able to detect
GIC offset.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
Changes in v5:
Replace fix_gic_off with get_gic_off.
Add #if condition to check CONFIG_GICV2 and CONFIG_GICV3 on 
smp_kick_all_cpus.
Fixup gic node with 64K alignment when running on rev1.1 with 
GIC_ADDR_BIT cleared. 
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  4 ++
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 62 ++
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   | 57 ++--
 arch/arm/include/asm/arch-fsl-layerscape/config.h  | 26 -
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  3 +-
 5 files changed, 145 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 94ec8d5..f415868 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -135,4 +135,8 @@ config SYS_FSL_DDR4
help
  Enable Freescale DDR4 controller.
 
+config HAS_FEATURE_GIC4K_ALIGN
+   bool
+   default y if ARCH_LS1043A
+
 endmenu
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 1a8321b..e90adb0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -126,6 +126,65 @@ void fsl_fdt_disable_usb(void *blob)
}
 }
 
+#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
+static void fdt_fixup_gic(void *blob)
+{
+   int offset, err;
+   u64 reg[8];
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   unsigned int rev;
+   struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+   int align_4k = 1;
+
+   rev = gur_in32(>svr) & 0xff;
+
+   if (rev > REV1_0) {
+   rev = scfg_in32(>gic_align) & (0x01 << GIC_ADDR_BIT);
+   if (!rev)
+   align_4k = 0;
+   }
+
+   offset = fdt_subnode_offset(blob, 0, "interrupt-controller@140");
+   if (offset < 0) {
+   printf("WARNING: fdt_subnode_offset can't find node %s: %s\n",
+  "interrupt-controller@140", fdt_strerror(offset));
+   return;
+   }
+
+   /* Fixup gic node align with 4K */
+   if (align_4k) {
+   reg[0] = cpu_to_fdt64(GICD_BASE_4K);
+   reg[1] = cpu_to_fdt64(GICD_SIZE_4K);
+   reg[2] = cpu_to_fdt64(GICC_BASE_4K);
+   reg[3] = cpu_to_fdt64(GICC_SIZE_4K);
+   reg[4] = cpu_to_fdt64(GICH_BASE_4K);
+   reg[5] = cpu_to_fdt64(GICH_SIZE_4K);
+   reg[6] = cpu_to_fdt64(GICV_BASE_4K);
+   reg[7] = cpu_to_fdt64(GICV_SIZE_4K);
+   } else {
+   /* Fixup gic node align with 64K */
+   reg[0] = cpu_to_fdt64(GICD_BASE);
+   reg[1] = cpu_to_fdt64(GICD_SIZE);
+   reg[2] = cpu_to_fdt64(GICC_BASE);
+   reg[3] = cpu_to_fdt64(GICC_SIZE);
+   reg[4] = cpu_to_fdt64(GICH_BASE);
+   reg[5] = cpu_to_fdt64(GICH_SIZE);
+   reg[6] = cpu_to_fdt64(GICV_BASE);
+   reg[7] = cpu_to_fdt64(GICV_SIZE);
+   }
+
+   err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg));
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
+  "reg", "interrupt-controller@140",
+  fdt_strerror(err));
+   return;
+   }
+
+   return;
+}
+#endif
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 #ifdef CONFIG_FSL_LSCH2
@@ -170,4 +229,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #endif
fsl_fdt_disable_usb(blob);
 
+#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
+   fdt_fixup_gic(blob);
+#endif
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5d0b7a4..d50096c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -14,6 +14,55 @@
 #include 
 #endif
 
+
+/* Get GIC offset
+* For LS1043a rev1.0, GIC base address align with 4k.
+* For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
+* is set, GIC base address align with 4K, or else align
+* with 64k.
+* output:
+*   for GICv2:
+*  x0-> the base address of GICD
+*  x1-> t

Re: [U-Boot] [PATCH v4 1/2] armv8/ls1043a: fixup GIC offset according to SVR and SCFG_GIC400_ALIGN[GIC_ADDR_BIT]

[Wenbin Song]

Hi: york

Best Regards
Wenbin Song


> -Original Message-
> From: york sun
> Sent: Wednesday, October 26, 2016 4:35 AM
> To: Wenbin Song <wenbin.s...@nxp.com>; albert.u.b...@aribaud.net;
> Mingkai Hu <mingkai...@nxp.com>; u-boot@lists.denx.de
> Subject: Re: [PATCH v4 1/2] armv8/ls1043a: fixup GIC offset according to SVR
> and SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
> 
> >
> > Overriding the weekly smp_kick_all_cpus, the new impletment is able to
> > detect GIC offset.
> 
> I think you meant "weak" here. :)

[wenbin] sorry, this is my carelessness.


> 
> >
> > The default GIC offset in kernel device tree is using 64K alignment,
> > it need to be fixed if 4K alignment is detected.
> 
> The "default" offset in device tree is also created by us, isn't it? I am not 
> against
> you fixing it. Don't you want to check the alignment first? If the device 
> tree has
> 4K alignment but you run on rev 1.1, do you want to use 64K alignment?

[wenbin]  Yes,  I will modify them.


> 
> >
> > +
> > +   if (val == REV1_1) {
> 
> This is problematic. How about for future SoCs, or other than LS1043A?
> Can we just check GIC_ADDR_BIT?
> 
[wenbin] it is  not clear about the future revise ,including whether has the 
new revise,  whether the new revise supports GIC 4K alignment and  how to 
detect  it. 
So  I  could only  suppose the future revise is  as same as rev1.1. 
Therefore, I will modify it to " if (val  != REV1_0) {"  in next 
version.

> > +   val = scfg_in32(>gic_align) & (0x01 << GIC_ADDR_BIT);
> > +   if (!val)
> > +   return;
> > +   }
> > +
> > +   offset = fdt_subnode_offset(blob, 0, "interrupt-controller@140");
> > +   if (offset < 0) {
> > +   printf("WARNING: fdt_subnode_offset can't find
> node %s: %s\n",
> > +  "interrupt-controller@140", fdt_strerror(offset));
> > +   return;
> > +   }
> > +
> > +   reg[0] = cpu_to_fdt64(GICD_BASE_4K);
> > +   reg[1] = cpu_to_fdt64(GICD_SIZE_4K);
> > +   reg[2] = cpu_to_fdt64(GICC_BASE_4K);
> > +   reg[3] = cpu_to_fdt64(GICC_SIZE_4K);
> > +   reg[4] = cpu_to_fdt64(GICH_BASE_4K);
> > +   reg[5] = cpu_to_fdt64(GICH_SIZE_4K);
> > +   reg[6] = cpu_to_fdt64(GICV_BASE_4K);
> > +   reg[7] = cpu_to_fdt64(GICV_SIZE_4K);
> > +
> > +   err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg));
> > +   if (err < 0) {
> > +   printf("WARNING: fdt_setprop can't set %s from
> node %s: %s\n",
> > +  "reg", "interrupt-controller@140",
> > +  fdt_strerror(err));
> > +   return;
> > +   }
> > +
> > +   return;
> > +}
> > +#endif
> > +
> >  void ft_cpu_setup(void *blob, bd_t *bd)  {  #ifdef CONFIG_FSL_LSCH2
> > @@ -170,4 +216,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)  #endif
> > fsl_fdt_disable_usb(blob);
> >
> > +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
> > +   fdt_fixup_gic(blob);
> > +#endif
> >  }
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> > b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> > index 5d0b7a4..e2b8698 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> > @@ -14,6 +14,48 @@
> >  #include 
> >  #endif
> >
> > +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
> > +
> > +/* fixup GIC offset
> > +* For LS1043a rev1.0, GIC base address align with 4k.
> > +* For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
> > +* is set, GIC base address align with 4K, or else align
> > +* with 64k.
> > +* output:
> > +*  x0: the base address of GICD
> > +*  x1: the base address of GICC
> > +*/
> > +ENTRY(fix_gic_offset)
> > +   ldr x0, =GICD_BASE
> > +   ldr x1, =GICC_BASE
> > +   ldr x3, =DCFG_CCSR_SVR
> > +   ldr w3, [x3]
> > +   rev w3, w3
> > +   andsw3, w3, #0xff
> > +   cmp w3, #REV1_0
> > +   b.eq1f
> > +   ldr x3, =SCFG_GIC400_ALIGN
> > +   ldr w3, [x3]
> > +   rev w3, w3
> > +   tbnzw3, #GIC_ADDR_BIT, 1f
> > +   ret
> > +1:
> > +   ldr x0, =GICD_BASE_4K
> > +   ldr x1, =GICC_BASE_4K
> > +   ret
> > +ENDPROC(fix_gic_offset)
> 
> The more I read it, the more I think the function name should be called
> get_gic_offset. You are not fixing it, the return value is the corr

[U-Boot] [PATCH v4 1/2] armv8/ls1043a: fixup GIC offset according to SVR and SCFG_GIC400_ALIGN[GIC_ADDR_BIT]

[Wenbin song]

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment
and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose
which offset will be used.

The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment.

If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used.
64K alignment is the default setting.

Overriding the weekly smp_kick_all_cpus, the new impletment is able to detect
GIC offset.

The default GIC offset in kernel device tree is using 64K alignment, it
need to be fixed if 4K alignment is detected.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
Changes in v4:
Squash [patch 2/3 v3] with this patch.
Add comments on fix_gic_offest.
Add the descriptions of rev1.0 GIC offset.
Use macros to define the offset and size of GIC components.  
Changes in v3:
Add descriptions about smp_kick_all_cpus on commit message.
Rename the macros on commit message to match with them used in the 
change.
Replace CONFIG_LS1043A with HAS_FEATURE_GIC4K_ALIGN.
Changes in v2:
None
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  4 ++
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 49 +++
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   | 55 ++
 arch/arm/include/asm/arch-fsl-layerscape/config.h  | 20 +++-
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  3 +-
 5 files changed, 128 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 94ec8d5..c66c497 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -12,6 +12,7 @@ config ARCH_LS1043A
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
+   select HAS_FEATURE_GIC4K_ALIGN
 
 config ARCH_LS1046A
bool
@@ -135,4 +136,7 @@ config SYS_FSL_DDR4
help
  Enable Freescale DDR4 controller.
 
+config HAS_FEATURE_GIC4K_ALIGN
+   bool
+
 endmenu
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 1a8321b..ebc7863 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -126,6 +126,52 @@ void fsl_fdt_disable_usb(void *blob)
}
 }
 
+#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
+/* Fixup gic node align with 4K */
+static void fdt_fixup_gic(void *blob)
+{
+   int offset, err;
+   u64 reg[8];
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   unsigned int val;
+   struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+   val = gur_in32(>svr) & 0xff;
+
+   if (val == REV1_1) {
+   val = scfg_in32(>gic_align) & (0x01 << GIC_ADDR_BIT);
+   if (!val)
+   return;
+   }
+
+   offset = fdt_subnode_offset(blob, 0, "interrupt-controller@140");
+   if (offset < 0) {
+   printf("WARNING: fdt_subnode_offset can't find node %s: %s\n",
+  "interrupt-controller@140", fdt_strerror(offset));
+   return;
+   }
+
+   reg[0] = cpu_to_fdt64(GICD_BASE_4K);
+   reg[1] = cpu_to_fdt64(GICD_SIZE_4K);
+   reg[2] = cpu_to_fdt64(GICC_BASE_4K);
+   reg[3] = cpu_to_fdt64(GICC_SIZE_4K);
+   reg[4] = cpu_to_fdt64(GICH_BASE_4K);
+   reg[5] = cpu_to_fdt64(GICH_SIZE_4K);
+   reg[6] = cpu_to_fdt64(GICV_BASE_4K);
+   reg[7] = cpu_to_fdt64(GICV_SIZE_4K);
+
+   err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg));
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
+  "reg", "interrupt-controller@140",
+  fdt_strerror(err));
+   return;
+   }
+
+   return;
+}
+#endif
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 #ifdef CONFIG_FSL_LSCH2
@@ -170,4 +216,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #endif
fsl_fdt_disable_usb(blob);
 
+#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
+   fdt_fixup_gic(blob);
+#endif
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5d0b7a4..e2b8698 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -14,6 +14,48 @@
 #include 
 #endif
 
+#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
+
+/* fixup GIC offset
+* For LS1043a rev1.0, GIC base address align with 4k.
+* For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
+* is set, GIC base address align with 4K, or else align
+* with 64k.
+* output:
+*  x0: the base address of GICD
+*  x1: the base address of GICC
+*/
+ENTRY(fix_

Re: [U-Boot] [PATCH v3 2/3] armv8/fsl-layerscape: fdt: fixup GIC node for LS1043A rev1.0

[Wenbin Song]

hi

Best Regards
Wenbin Song

> -Original Message-
> From: york sun
> Sent: Friday, October 21, 2016 10:16 PM
> To: Wenbin Song <wenbin.s...@nxp.com>; albert.u.b...@aribaud.net;
> Mingkai Hu <mingkai...@nxp.com>; u-boot@lists.denx.de
> Subject: Re: [PATCH v3 2/3] armv8/fsl-layerscape: fdt: fixup GIC node for
> LS1043A rev1.0
> 
> On 10/21/2016 03:28 AM, Wenbin song wrote:
> > The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
> > alignment and 64K alignment. 4K alignment is consistent with rev1.0
> implement.
> >
> > The default GIC offset in kernel device tree is using 64K alignment,
> > if rev1.0 silicon used, need to fixup the GIC node to use 4K alignment.
> >
> > Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
> > Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
> > ---
> > Changes for v3:
> > Replace CONFIG_LS1043A with HAS_FEATURE_GIC4K_ALIGN.
> > ---
> >  arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 49
> ++
> >  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  3 +-
> >  2 files changed, 51 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> > index 1a8321b..54f8492 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> > @@ -126,6 +126,52 @@ void fsl_fdt_disable_usb(void *blob)
> > }
> >  }
> >
> > +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
> > +/* Fixup gic node align with 4K */
> > +static void fdt_fixup_gic(void *blob) {
> > +   int offset, err;
> > +   u64 reg[8];
> > +   struct ccsr_gur __iomem *gur = (void
> *)(CONFIG_SYS_FSL_GUTS_ADDR);
> > +   unsigned int val;
> > +   struct ccsr_scfg __iomem *scfg = (void
> *)CONFIG_SYS_FSL_SCFG_ADDR;
> > +
> > +   val = gur_in32(>svr) & 0xff;
> > +
> > +   if (val == REV1_1) {
> > +   val = scfg_in32(>gic_align) & (0x01 << GIC_ADDR_BIT);
> > +   if (!val)
> > +   return;
> > +   }
> 
> For rev 1.0 SoC, it runs through here, right? If that what you want?
[wenbin]  For rev1.0 , it should be fixed, too. Because  rev1.0 is  using 4K 
offset alignment, but the default is using 64K alignment.
 I will give some descriptions on commit message about it. 


> > +
> > +   offset = fdt_subnode_offset(blob, 0, "interrupt-controller@140");
> > +   if (offset < 0) {
> > +   printf("WARNING: fdt_subnode_offset can't find
> node %s: %s\n",
> > +  "interrupt-controller@140", fdt_strerror(offset));
> > +   return;
> > +   }
> > +
> > +   reg[0] = cpu_to_fdt64(0x1401000);
> > +   reg[1] = cpu_to_fdt64(0x1000);
> > +   reg[2] = cpu_to_fdt64(0x1402000);
> > +   reg[3] = cpu_to_fdt64(0x2000);
> > +   reg[4] = cpu_to_fdt64(0x1404000);
> > +   reg[5] = cpu_to_fdt64(0x2000);
> > +   reg[6] = cpu_to_fdt64(0x1406000);
> > +   reg[7] = cpu_to_fdt64(0x2000);
> 
> What are these magic numbers?
[wenbin]  they are the offset and size for each GIC components.  I will 
redefine them using macros. 
> 
> > +
> > +   err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg));
> > +   if (err < 0) {
> > +   printf("WARNING: fdt_setprop can't set %s from
> node %s: %s\n",
> > +  "reg", "interrupt-controller@140",
> > +  fdt_strerror(err));
> > +   return;
> > +   }
> > +
> > +   return;
> > +}
> > +#endif
> > +
> >  void ft_cpu_setup(void *blob, bd_t *bd)  {  #ifdef CONFIG_FSL_LSCH2
> > @@ -170,4 +216,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)  #endif
> > fsl_fdt_disable_usb(blob);
> >
> > +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
> > +   fdt_fixup_gic(blob);
> > +#endif
> >  }
> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> > b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> > index d88543d..1dfef53 100644
> > --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> > @@ -359,7 +359,8 @@ struct ccsr_scfg {
> > u32 qspi_cfg;
> > u8 res_160[0x180-0x160];
> > u32 dmamcr;
> > -   u8 res_184[0x18c-0x184];
> > +   u8 res_184[0x188-0x184];
> > +   u32 gic_align;
> > u32 debug_icid;
> > u8 res_190[0x1a4-0x190];
> > u32 snpcnfgcr;
> >
> 
> Would it be reasonable to squash this patch with previous one in this set? 
> They
> both deal with the same thing. If you run git bisect between this two, you 
> don't
> get correct gic offset in device tree, do you?
> 
[wenbin]yes , I will squash it . 
> York

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v4 2/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI node

[Wenbin song]

The default MSI node in kernel tree is for LS1043A rev1.1 silicon,
if rev1.0 silicon used, need to fixup the MSI node to match it.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
Changes in v4:
None
Changes in v3:
Replace CONFIG_LS1043A with HAS_FEATURE_ENHACED_MSI.
Changes in v2:
None
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |  3 +
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c   | 94 +++
 2 files changed, 97 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index c66c497..d2537bb 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -13,6 +13,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
select HAS_FEATURE_GIC4K_ALIGN
+   select HAS_FEATURE_ENHANCED_MSI
 
 config ARCH_LS1046A
bool
@@ -138,5 +139,7 @@ config SYS_FSL_DDR4
 
 config HAS_FEATURE_GIC4K_ALIGN
bool
+config HAS_FEATURE_ENHANCED_MSI
+   bool
 
 endmenu
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index ebc7863..90114b2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -171,6 +171,97 @@ static void fdt_fixup_gic(void *blob)
return;
 }
 #endif
+#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
+static int _fdt_fixup_msi_subnode(void *blob, int parentoffset,
+   const char *name, int irq_no)
+{
+   int err, offset;
+   u32 tmp[3];
+
+   offset = fdt_subnode_offset(blob, parentoffset, name);
+   if (offset < 0) {
+   printf("WARNING: fdt_subnode_offset can't find %s: %s\n",
+  name, fdt_strerror(offset));
+   return 0;
+   }
+
+   tmp[0] = cpu_to_fdt32(0x0);
+   tmp[1] = cpu_to_fdt32(irq_no);
+   tmp[2] = cpu_to_fdt32(0x4);
+
+   err = fdt_setprop(blob, offset, "interrupts", tmp, sizeof(tmp));
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
+  "interrupts", name, fdt_strerror(err));
+   return 0;
+   }
+
+   return 1;
+}
+
+static int _fdt_fixup_pci_msi(void *blob, const char *name)
+{
+   int offset, len, err;
+   void *p;
+   int val;
+   u32 tmp[4][8];
+
+   offset = fdt_path_offset(blob, name);
+   if (offset < 0) {
+   printf("WARNING: fdt_path_offset can't find path %s: %s\n",
+  name, fdt_strerror(offset));
+   return 0;
+   }
+
+   p = (char *)fdt_getprop(blob, offset, "interrupt-map", );
+   if (!p || len != sizeof(tmp)) {
+   printf("WARNING: fdt_getprop can't get %s from node %s\n",
+  "interrupt-map", name);
+   return 0;
+   }
+
+   memcpy((char *)tmp, p, len);
+   val = fdt32_to_cpu(tmp[0][6]);
+   tmp[1][6] = cpu_to_fdt32(val + 1);
+   tmp[2][6] = cpu_to_fdt32(val + 2);
+   tmp[3][6] = cpu_to_fdt32(val + 3);
+
+   err = fdt_setprop(blob, offset, "interrupt-map", tmp, sizeof(tmp));
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s.\n",
+  "interrupt-map", name, fdt_strerror(err));
+   return 0;
+   }
+   return 1;
+}
+
+/* Fixup msi to v1_0*/
+
+static void fdt_fixup_msi(void *blob)
+{
+   int nodeoffset;
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   unsigned int val;
+
+   val = gur_in32(>svr) & 0xff;
+   if (val == REV1_1)
+   return;
+
+   nodeoffset = fdt_path_offset(blob, "/soc/msi-controller");
+   if (nodeoffset < 0) {
+   printf("WARNING: fdt_path_offset can't find path %s: %s\n",
+  "/soc/msi-controller", fdt_strerror(nodeoffset));
+   return;
+   }
+   _fdt_fixup_msi_subnode(blob, nodeoffset, "msi0@1571000", 116);
+   _fdt_fixup_msi_subnode(blob, nodeoffset, "msi1@1572000", 126);
+   _fdt_fixup_msi_subnode(blob, nodeoffset, "msi2@1573000", 160);
+
+   _fdt_fixup_pci_msi(blob, "/soc/pcie@340");
+   _fdt_fixup_pci_msi(blob, "/soc/pcie@350");
+   _fdt_fixup_pci_msi(blob, "/soc/pcie@360");
+}
+#endif
 
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
@@ -219,4 +310,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
fdt_fixup_gic(blob);
 #endif
+#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
+   fdt_fixup_msi(blob);
+#endif
 }
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v3 2/3] armv8/fsl-layerscape: fdt: fixup GIC node for LS1043A rev1.0

[Wenbin song]

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment
and 64K alignment. 4K alignment is consistent with rev1.0 implement.

The default GIC offset in kernel device tree is using 64K alignment,
if rev1.0 silicon used, need to fixup the GIC node to use 4K alignment.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
Changes for v3:
Replace CONFIG_LS1043A with HAS_FEATURE_GIC4K_ALIGN.
---
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 49 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  3 +-
 2 files changed, 51 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 1a8321b..54f8492 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -126,6 +126,52 @@ void fsl_fdt_disable_usb(void *blob)
}
 }
 
+#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
+/* Fixup gic node align with 4K */
+static void fdt_fixup_gic(void *blob)
+{
+   int offset, err;
+   u64 reg[8];
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   unsigned int val;
+   struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+   val = gur_in32(>svr) & 0xff;
+
+   if (val == REV1_1) {
+   val = scfg_in32(>gic_align) & (0x01 << GIC_ADDR_BIT);
+   if (!val)
+   return;
+   }
+
+   offset = fdt_subnode_offset(blob, 0, "interrupt-controller@140");
+   if (offset < 0) {
+   printf("WARNING: fdt_subnode_offset can't find node %s: %s\n",
+  "interrupt-controller@140", fdt_strerror(offset));
+   return;
+   }
+
+   reg[0] = cpu_to_fdt64(0x1401000);
+   reg[1] = cpu_to_fdt64(0x1000);
+   reg[2] = cpu_to_fdt64(0x1402000);
+   reg[3] = cpu_to_fdt64(0x2000);
+   reg[4] = cpu_to_fdt64(0x1404000);
+   reg[5] = cpu_to_fdt64(0x2000);
+   reg[6] = cpu_to_fdt64(0x1406000);
+   reg[7] = cpu_to_fdt64(0x2000);
+
+   err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg));
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
+  "reg", "interrupt-controller@140",
+  fdt_strerror(err));
+   return;
+   }
+
+   return;
+}
+#endif
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 #ifdef CONFIG_FSL_LSCH2
@@ -170,4 +216,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #endif
fsl_fdt_disable_usb(blob);
 
+#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
+   fdt_fixup_gic(blob);
+#endif
 }
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d88543d..1dfef53 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -359,7 +359,8 @@ struct ccsr_scfg {
u32 qspi_cfg;
u8 res_160[0x180-0x160];
u32 dmamcr;
-   u8 res_184[0x18c-0x184];
+   u8 res_184[0x188-0x184];
+   u32 gic_align;
u32 debug_icid;
u8 res_190[0x1a4-0x190];
u32 snpcnfgcr;
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v3 3/3] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI node

[Wenbin song]

The default MSI node in kernel tree is for LS1043A rev1.1 silicon,
if rev1.0 silicon used, need to fixup the MSI node to match it.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
Changes for v3:
Replace CONFIG_LS1043A with HAS_FEATURE_ENHACED_MSI.
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |  3 +
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c   | 94 +++
 2 files changed, 97 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index c66c497..d2537bb 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -13,6 +13,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
select HAS_FEATURE_GIC4K_ALIGN
+   select HAS_FEATURE_ENHANCED_MSI
 
 config ARCH_LS1046A
bool
@@ -138,5 +139,7 @@ config SYS_FSL_DDR4
 
 config HAS_FEATURE_GIC4K_ALIGN
bool
+config HAS_FEATURE_ENHANCED_MSI
+   bool
 
 endmenu
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 54f8492..7a1e445 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -171,6 +171,97 @@ static void fdt_fixup_gic(void *blob)
return;
 }
 #endif
+#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
+static int _fdt_fixup_msi_subnode(void *blob, int parentoffset,
+   const char *name, int irq_no)
+{
+   int err, offset;
+   u32 tmp[3];
+
+   offset = fdt_subnode_offset(blob, parentoffset, name);
+   if (offset < 0) {
+   printf("WARNING: fdt_subnode_offset can't find %s: %s\n",
+  name, fdt_strerror(offset));
+   return 0;
+   }
+
+   tmp[0] = cpu_to_fdt32(0x0);
+   tmp[1] = cpu_to_fdt32(irq_no);
+   tmp[2] = cpu_to_fdt32(0x4);
+
+   err = fdt_setprop(blob, offset, "interrupts", tmp, sizeof(tmp));
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
+  "interrupts", name, fdt_strerror(err));
+   return 0;
+   }
+
+   return 1;
+}
+
+static int _fdt_fixup_pci_msi(void *blob, const char *name)
+{
+   int offset, len, err;
+   void *p;
+   int val;
+   u32 tmp[4][8];
+
+   offset = fdt_path_offset(blob, name);
+   if (offset < 0) {
+   printf("WARNING: fdt_path_offset can't find path %s: %s\n",
+  name, fdt_strerror(offset));
+   return 0;
+   }
+
+   p = (char *)fdt_getprop(blob, offset, "interrupt-map", );
+   if (!p || len != sizeof(tmp)) {
+   printf("WARNING: fdt_getprop can't get %s from node %s\n",
+  "interrupt-map", name);
+   return 0;
+   }
+
+   memcpy((char *)tmp, p, len);
+   val = fdt32_to_cpu(tmp[0][6]);
+   tmp[1][6] = cpu_to_fdt32(val + 1);
+   tmp[2][6] = cpu_to_fdt32(val + 2);
+   tmp[3][6] = cpu_to_fdt32(val + 3);
+
+   err = fdt_setprop(blob, offset, "interrupt-map", tmp, sizeof(tmp));
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s.\n",
+  "interrupt-map", name, fdt_strerror(err));
+   return 0;
+   }
+   return 1;
+}
+
+/* Fixup msi to v1_0*/
+
+static void fdt_fixup_msi(void *blob)
+{
+   int nodeoffset;
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   unsigned int val;
+
+   val = gur_in32(>svr) & 0xff;
+   if (val == REV1_1)
+   return;
+
+   nodeoffset = fdt_path_offset(blob, "/soc/msi-controller");
+   if (nodeoffset < 0) {
+   printf("WARNING: fdt_path_offset can't find path %s: %s\n",
+  "/soc/msi-controller", fdt_strerror(nodeoffset));
+   return;
+   }
+   _fdt_fixup_msi_subnode(blob, nodeoffset, "msi0@1571000", 116);
+   _fdt_fixup_msi_subnode(blob, nodeoffset, "msi1@1572000", 126);
+   _fdt_fixup_msi_subnode(blob, nodeoffset, "msi2@1573000", 160);
+
+   _fdt_fixup_pci_msi(blob, "/soc/pcie@340");
+   _fdt_fixup_pci_msi(blob, "/soc/pcie@350");
+   _fdt_fixup_pci_msi(blob, "/soc/pcie@360");
+}
+#endif
 
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
@@ -219,4 +310,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
fdt_fixup_gic(blob);
 #endif
+#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
+   fdt_fixup_msi(blob);
+#endif
 }
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v3 1/3] armv8/ls1043a: fixup GIC offset according to SVR and SCFG_GIC400_ALIGN[GIC_ADDR_BIT]

[Wenbin song]

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment
and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose
which offset will be used.

If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used.
64K alignment is the default setting.

Overriding the weekly smp_kick_all_cpus, the new impletment is able to detect
GIC offset.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
Changes in v3:
Add description about smp_kick_all_cpus on commit message.
Rename the macros on commit message to match with them used in the 
change.
Replace CONFIG_LS1043A with HAS_FEATURE_GIC4K_ALIGN.
Changes in v2:
None
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |  4 ++
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S  | 47 +++
 arch/arm/include/asm/arch-fsl-layerscape/config.h | 12 +-
 3 files changed, 61 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 94ec8d5..c66c497 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -12,6 +12,7 @@ config ARCH_LS1043A
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
+   select HAS_FEATURE_GIC4K_ALIGN
 
 config ARCH_LS1046A
bool
@@ -135,4 +136,7 @@ config SYS_FSL_DDR4
help
  Enable Freescale DDR4 controller.
 
+config HAS_FEATURE_GIC4K_ALIGN
+   bool
+
 endmenu
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5d0b7a4..f0da559 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -14,6 +14,40 @@
 #include 
 #endif
 
+#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
+
+/* fixup GIC offset */
+ENTRY(fix_gic_offset)
+   ldr x0, =GICD_BASE
+   ldr x1, =GICC_BASE
+   ldr x3, =DCFG_CCSR_SVR
+   ldr w3, [x3]
+   rev w3, w3
+   andsw3, w3, #0xff
+   cmp w3, #REV1_0
+   b.eq1f
+   ldr x3, =SCFG_GIC400_ALIGN
+   ldr w3, [x3]
+   rev w3, w3
+   tbnzw3, #GIC_ADDR_BIT, 1f
+   ret
+1:
+   ldr x0, =GICD_BASE_4K
+   ldr x1, =GICC_BASE_4K
+   ret
+ENDPROC(fix_gic_offset)
+
+ENTRY(smp_kick_all_cpus)
+   /* Kick secondary cpus up by SGI 0 interrupt */
+   mov x29, lr /* Save LR */
+   bl  fix_gic_offset
+   bl  gic_kick_secondary_cpus
+   mov lr, x29 /* Restore LR */
+   ret
+ENDPROC(smp_kick_all_cpus)
+
+#endif
+
 ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
 
@@ -105,15 +139,23 @@ ENTRY(lowlevel_init)
/* Initialize GIC Secure Bank Status */
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
branch_if_slave x0, 1f
+#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
+   bl  fix_gic_offset
+#else
ldr x0, =GICD_BASE
+#endif
bl  gic_init_secure
 1:
 #ifdef CONFIG_GICV3
ldr x0, =GICR_BASE
bl  gic_init_secure_percpu
 #elif defined(CONFIG_GICV2)
+#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
+   bl  fix_gic_offset
+#else
ldr x0, =GICD_BASE
ldr x1, =GICC_BASE
+#endif
bl  gic_init_secure_percpu
 #endif
 #endif
@@ -335,7 +377,12 @@ ENTRY(secondary_boot_func)
 #if defined(CONFIG_GICV3)
gic_wait_for_interrupt_m x0
 #elif defined(CONFIG_GICV2)
+#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
+   bl  fix_gic_offset
+   mov x0, x1
+#else
 ldr x0, =GICC_BASE
+#endif
 gic_wait_for_interrupt_m x0, w1
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 4201e0f..eb6e58d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -172,8 +172,16 @@
 #define SMMU_BASE  0x0900
 
 /* Generic Interrupt Controller Definitions */
-#define GICD_BASE  0x01401000
-#define GICC_BASE  0x01402000
+#define GICD_BASE  0x0141
+#define GICC_BASE  0x0142
+#define GICD_BASE_4K0x01401000
+#define GICC_BASE_4K0x01402000
+
+#define DCFG_CCSR_SVR  0x1ee00a4
+#define REV1_0 0x10
+#define REV1_1 0x11
+#define GIC_ADDR_BIT   31
+#define SCFG_GIC400_ALIGN  0x1570188
 
 #define CONFIG_SYS_FSL_ERRATUM_A008850
 #define CONFIG_SYS_FSL_ERRATUM_A009663
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 3/3] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI node

[Wenbin song]

The default MSI node in kernel tree is for LS1043A rev1.1 silicon,
if rev1.0 silicon used, need to fixup the MSI node to match it.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
v2: 
  Call fdt_fixup_msi when CONFIG_LS1043A is defined.
---
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 91 +
 1 file changed, 91 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 1e0d5d2..b46f310 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -170,6 +170,96 @@ static void fdt_fixup_gic(void *blob)
 
return;
 }
+
+static int _fdt_fixup_msi_subnode(void *blob, int parentoffset,
+   const char *name, int irq_no)
+{
+   int err, offset;
+   u32 tmp[3];
+
+   offset = fdt_subnode_offset(blob, parentoffset, name);
+   if (offset < 0) {
+   printf("WARNING: fdt_subnode_offset can't find %s: %s\n",
+  name, fdt_strerror(offset));
+   return 0;
+   }
+
+   tmp[0] = cpu_to_fdt32(0x0);
+   tmp[1] = cpu_to_fdt32(irq_no);
+   tmp[2] = cpu_to_fdt32(0x4);
+
+   err = fdt_setprop(blob, offset, "interrupts", tmp, sizeof(tmp));
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
+  "interrupts", name, fdt_strerror(err));
+   return 0;
+   }
+
+   return 1;
+}
+
+static int _fdt_fixup_pci_msi(void *blob, const char *name)
+{
+   int offset, len, err;
+   void *p;
+   int val;
+   u32 tmp[4][8];
+
+   offset = fdt_path_offset(blob, name);
+   if (offset < 0) {
+   printf("WARNING: fdt_path_offset can't find path %s: %s\n",
+  name, fdt_strerror(offset));
+   return 0;
+   }
+
+   p = (char *)fdt_getprop(blob, offset, "interrupt-map", );
+   if (!p || len != sizeof(tmp)) {
+   printf("WARNING: fdt_getprop can't get %s from node %s\n",
+  "interrupt-map", name);
+   return 0;
+   }
+
+   memcpy((char *)tmp, p, len);
+   val = fdt32_to_cpu(tmp[0][6]);
+   tmp[1][6] = cpu_to_fdt32(val + 1);
+   tmp[2][6] = cpu_to_fdt32(val + 2);
+   tmp[3][6] = cpu_to_fdt32(val + 3);
+
+   err = fdt_setprop(blob, offset, "interrupt-map", tmp, sizeof(tmp));
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s.\n",
+  "interrupt-map", name, fdt_strerror(err));
+   return 0;
+   }
+   return 1;
+}
+
+/* Fixup msi to v1_0*/
+
+static void fdt_fixup_msi(void *blob)
+{
+   int nodeoffset;
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   unsigned int val;
+
+   val = gur_in32(>svr) & 0xff;
+   if (val == REV1_1)
+   return;
+
+   nodeoffset = fdt_path_offset(blob, "/soc/msi-controller");
+   if (nodeoffset < 0) {
+   printf("WARNING: fdt_path_offset can't find path %s: %s\n",
+  "/soc/msi-controller", fdt_strerror(nodeoffset));
+   return;
+   }
+   _fdt_fixup_msi_subnode(blob, nodeoffset, "msi0@1571000", 116);
+   _fdt_fixup_msi_subnode(blob, nodeoffset, "msi1@1572000", 126);
+   _fdt_fixup_msi_subnode(blob, nodeoffset, "msi2@1573000", 160);
+
+   _fdt_fixup_pci_msi(blob, "/soc/pcie@340");
+   _fdt_fixup_pci_msi(blob, "/soc/pcie@350");
+   _fdt_fixup_pci_msi(blob, "/soc/pcie@360");
+}
 #endif
 
 void ft_cpu_setup(void *blob, bd_t *bd)
@@ -218,5 +308,6 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 
 #ifdef CONFIG_LS1043A
fdt_fixup_gic(blob);
+   fdt_fixup_msi(blob);
 #endif
 }
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 1/3] armv8/ls1043a: fixup GIC offset according to SVR and GIC400_ADDR_ALIGN_64K[GIC_ADDR]

[Wenbin song]

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment
and 64K alignment. The bit GIC400_ADDR_ALIGN_64K[GIC_ADDR] is used to choose
which offset will be used.

If GIC_ADDR bit is set, 4K alignment is used, or else 64K alignment is used.
64K alignment is the default setting.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
v2: 
   None
---
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S  | 47 +++
 arch/arm/include/asm/arch-fsl-layerscape/config.h | 12 +-
 2 files changed, 57 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5d0b7a4..569d2c2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -14,6 +14,40 @@
 #include 
 #endif
 
+#ifdef CONFIG_LS1043A
+
+/* fixup GIC offset */
+ENTRY(fix_gic_offset)
+   ldr x0, =GICD_BASE
+   ldr x1, =GICC_BASE
+   ldr x3, =DCFG_CCSR_SVR
+   ldr w3, [x3]
+   rev w3, w3
+   andsw3, w3, #0xff
+   cmp w3, #REV1_0
+   b.eq1f
+   ldr x3, =SCFG_GIC400_ALIGN
+   ldr w3, [x3]
+   rev w3, w3
+   tbnzw3, #GIC_ADDR_BIT, 1f
+   ret
+1:
+   ldr x0, =GICD_BASE_4K
+   ldr x1, =GICC_BASE_4K
+   ret
+ENDPROC(fix_gic_offset)
+
+ENTRY(smp_kick_all_cpus)
+   /* Kick secondary cpus up by SGI 0 interrupt */
+   mov x29, lr /* Save LR */
+   bl  fix_gic_offset
+   bl  gic_kick_secondary_cpus
+   mov lr, x29 /* Restore LR */
+   ret
+ENDPROC(smp_kick_all_cpus)
+
+#endif
+
 ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
 
@@ -105,15 +139,23 @@ ENTRY(lowlevel_init)
/* Initialize GIC Secure Bank Status */
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
branch_if_slave x0, 1f
+#ifdef CONFIG_LS1043A
+   bl  fix_gic_offset
+#else
ldr x0, =GICD_BASE
+#endif
bl  gic_init_secure
 1:
 #ifdef CONFIG_GICV3
ldr x0, =GICR_BASE
bl  gic_init_secure_percpu
 #elif defined(CONFIG_GICV2)
+#ifdef CONFIG_LS1043A
+   bl  fix_gic_offset
+#else
ldr x0, =GICD_BASE
ldr x1, =GICC_BASE
+#endif
bl  gic_init_secure_percpu
 #endif
 #endif
@@ -335,7 +377,12 @@ ENTRY(secondary_boot_func)
 #if defined(CONFIG_GICV3)
gic_wait_for_interrupt_m x0
 #elif defined(CONFIG_GICV2)
+#ifdef CONFIG_LS1043A
+   bl  fix_gic_offset
+   mov x0, x1
+#else
 ldr x0, =GICC_BASE
+#endif
 gic_wait_for_interrupt_m x0, w1
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 4201e0f..eb6e58d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -172,8 +172,16 @@
 #define SMMU_BASE  0x0900
 
 /* Generic Interrupt Controller Definitions */
-#define GICD_BASE  0x01401000
-#define GICC_BASE  0x01402000
+#define GICD_BASE  0x0141
+#define GICC_BASE  0x0142
+#define GICD_BASE_4K0x01401000
+#define GICC_BASE_4K0x01402000
+
+#define DCFG_CCSR_SVR  0x1ee00a4
+#define REV1_0 0x10
+#define REV1_1 0x11
+#define GIC_ADDR_BIT   31
+#define SCFG_GIC400_ALIGN  0x1570188
 
 #define CONFIG_SYS_FSL_ERRATUM_A008850
 #define CONFIG_SYS_FSL_ERRATUM_A009663
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 2/3] armv8/fsl-layerscape: fdt: fixup GIC node for LS1043A rev1

[Wenbin song]

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment
and 64K alignment. 4K alignment is consistent with rev1 implement.

The default GIC offset in kernel device tree is using 64K alignment,
if rev1 silicon used, need to fixup the GIC node to use 4K alignment.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
v2:
Call fdt_fixup_gic when CONFIG_LS1043A is defined.
---
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 49 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  3 +-
 2 files changed, 51 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 1a8321b..1e0d5d2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -126,6 +126,52 @@ void fsl_fdt_disable_usb(void *blob)
}
 }
 
+#ifdef CONFIG_LS1043A
+/* Fixup gic node align with 4K */
+static void fdt_fixup_gic(void *blob)
+{
+   int offset, err;
+   u64 reg[8];
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   unsigned int val;
+   struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+   val = gur_in32(>svr) & 0xff;
+
+   if (val == REV1_1) {
+   val = scfg_in32(>gic_align) & (0x01 << GIC_ADDR_BIT);
+   if (!val)
+   return;
+   }
+
+   offset = fdt_subnode_offset(blob, 0, "interrupt-controller@140");
+   if (offset < 0) {
+   printf("WARNING: fdt_subnode_offset can't find node %s: %s\n",
+  "interrupt-controller@140", fdt_strerror(offset));
+   return;
+   }
+
+   reg[0] = cpu_to_fdt64(0x1401000);
+   reg[1] = cpu_to_fdt64(0x1000);
+   reg[2] = cpu_to_fdt64(0x1402000);
+   reg[3] = cpu_to_fdt64(0x2000);
+   reg[4] = cpu_to_fdt64(0x1404000);
+   reg[5] = cpu_to_fdt64(0x2000);
+   reg[6] = cpu_to_fdt64(0x1406000);
+   reg[7] = cpu_to_fdt64(0x2000);
+
+   err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg));
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
+  "reg", "interrupt-controller@140",
+  fdt_strerror(err));
+   return;
+   }
+
+   return;
+}
+#endif
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 #ifdef CONFIG_FSL_LSCH2
@@ -170,4 +216,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #endif
fsl_fdt_disable_usb(blob);
 
+#ifdef CONFIG_LS1043A
+   fdt_fixup_gic(blob);
+#endif
 }
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d88543d..1dfef53 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -359,7 +359,8 @@ struct ccsr_scfg {
u32 qspi_cfg;
u8 res_160[0x180-0x160];
u32 dmamcr;
-   u8 res_184[0x18c-0x184];
+   u8 res_184[0x188-0x184];
+   u32 gic_align;
u32 debug_icid;
u8 res_190[0x1a4-0x190];
u32 snpcnfgcr;
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 2/3] armv8/fsl-layerscape: fdt: fixup GIC node for LS1043A rev1

[Wenbin song]

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment
and 64K alignment. 4K alignment is consistent with rev1 implement.

The default GIC offset in kernel device tree is using 64K alignment,
if rev1 silicon used, need to fixup the GIC node to use 4K alignment.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 47 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  3 +-
 2 files changed, 49 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 1a8321b..5a80ff2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -126,6 +126,52 @@ void fsl_fdt_disable_usb(void *blob)
}
 }
 
+#ifdef CONFIG_LS1043A
+/* Fixup gic node align with 4K */
+static void fdt_fixup_gic(void *blob)
+{
+   int offset, err;
+   u64 reg[8];
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   unsigned int val;
+   struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+   val = gur_in32(>svr) & 0xff;
+
+   if (val == REV1_1) {
+   val = scfg_in32(>gic_align) & (0x01 << GIC_ADDR_BIT);
+   if (!val)
+   return;
+   }
+
+   offset = fdt_subnode_offset(blob, 0, "interrupt-controller@140");
+   if (offset < 0) {
+   printf("WARNING: fdt_subnode_offset can't find node %s: %s\n",
+  "interrupt-controller@140", fdt_strerror(offset));
+   return;
+   }
+
+   reg[0] = cpu_to_fdt64(0x1401000);
+   reg[1] = cpu_to_fdt64(0x1000);
+   reg[2] = cpu_to_fdt64(0x1402000);
+   reg[3] = cpu_to_fdt64(0x2000);
+   reg[4] = cpu_to_fdt64(0x1404000);
+   reg[5] = cpu_to_fdt64(0x2000);
+   reg[6] = cpu_to_fdt64(0x1406000);
+   reg[7] = cpu_to_fdt64(0x2000);
+
+   err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg));
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
+  "reg", "interrupt-controller@140",
+  fdt_strerror(err));
+   return;
+   }
+
+   return;
+}
+#endif
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 #ifdef CONFIG_FSL_LSCH2
@@ -143,6 +189,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_fixup_crypto_node(blob, sec_in32(>secvid_ms));
}
 #endif
+   fdt_fixup_gic(blob);
 #endif
 
 #ifdef CONFIG_MP
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d88543d..1dfef53 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -359,7 +359,8 @@ struct ccsr_scfg {
u32 qspi_cfg;
u8 res_160[0x180-0x160];
u32 dmamcr;
-   u8 res_184[0x18c-0x184];
+   u8 res_184[0x188-0x184];
+   u32 gic_align;
u32 debug_icid;
u8 res_190[0x1a4-0x190];
u32 snpcnfgcr;
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 1/3] armv8/ls1043a: fixup GIC offset according to SVR and GIC400_ADDR_ALIGN_64K[GIC_ADDR]

[Wenbin song]

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment
and 64K alignment. The bit GIC400_ADDR_ALIGN_64K[GIC_ADDR] is used to choose
which offset will be used.

If GIC_ADDR bit is set, 4K alignment is used, or else 64K alignment is used.
64K alignment is the default setting.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S  | 47 +++
 arch/arm/include/asm/arch-fsl-layerscape/config.h | 12 +-
 2 files changed, 57 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5d0b7a4..569d2c2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -14,6 +14,40 @@
 #include 
 #endif
 
+#ifdef CONFIG_LS1043A
+
+/* fixup GIC offset */
+ENTRY(fix_gic_offset)
+   ldr x0, =GICD_BASE
+   ldr x1, =GICC_BASE
+   ldr x3, =DCFG_CCSR_SVR
+   ldr w3, [x3]
+   rev w3, w3
+   andsw3, w3, #0xff
+   cmp w3, #REV1_0
+   b.eq1f
+   ldr x3, =SCFG_GIC400_ALIGN
+   ldr w3, [x3]
+   rev w3, w3
+   tbnzw3, #GIC_ADDR_BIT, 1f
+   ret
+1:
+   ldr x0, =GICD_BASE_4K
+   ldr x1, =GICC_BASE_4K
+   ret
+ENDPROC(fix_gic_offset)
+
+ENTRY(smp_kick_all_cpus)
+   /* Kick secondary cpus up by SGI 0 interrupt */
+   mov x29, lr /* Save LR */
+   bl  fix_gic_offset
+   bl  gic_kick_secondary_cpus
+   mov lr, x29 /* Restore LR */
+   ret
+ENDPROC(smp_kick_all_cpus)
+
+#endif
+
 ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
 
@@ -105,15 +139,23 @@ ENTRY(lowlevel_init)
/* Initialize GIC Secure Bank Status */
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
branch_if_slave x0, 1f
+#ifdef CONFIG_LS1043A
+   bl  fix_gic_offset
+#else
ldr x0, =GICD_BASE
+#endif
bl  gic_init_secure
 1:
 #ifdef CONFIG_GICV3
ldr x0, =GICR_BASE
bl  gic_init_secure_percpu
 #elif defined(CONFIG_GICV2)
+#ifdef CONFIG_LS1043A
+   bl  fix_gic_offset
+#else
ldr x0, =GICD_BASE
ldr x1, =GICC_BASE
+#endif
bl  gic_init_secure_percpu
 #endif
 #endif
@@ -335,7 +377,12 @@ ENTRY(secondary_boot_func)
 #if defined(CONFIG_GICV3)
gic_wait_for_interrupt_m x0
 #elif defined(CONFIG_GICV2)
+#ifdef CONFIG_LS1043A
+   bl  fix_gic_offset
+   mov x0, x1
+#else
 ldr x0, =GICC_BASE
+#endif
 gic_wait_for_interrupt_m x0, w1
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 4201e0f..eb6e58d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -172,8 +172,16 @@
 #define SMMU_BASE  0x0900
 
 /* Generic Interrupt Controller Definitions */
-#define GICD_BASE  0x01401000
-#define GICC_BASE  0x01402000
+#define GICD_BASE  0x0141
+#define GICC_BASE  0x0142
+#define GICD_BASE_4K0x01401000
+#define GICC_BASE_4K0x01402000
+
+#define DCFG_CCSR_SVR  0x1ee00a4
+#define REV1_0 0x10
+#define REV1_1 0x11
+#define GIC_ADDR_BIT   31
+#define SCFG_GIC400_ALIGN  0x1570188
 
 #define CONFIG_SYS_FSL_ERRATUM_A008850
 #define CONFIG_SYS_FSL_ERRATUM_A009663
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 3/3] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI node

[Wenbin song]

The default MSI node in kernel tree is for LS1043A rev1.1 silicon,
if rev1.0 silicon used, need to fixup the MSI node to match it.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 91 +
 1 file changed, 91 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 5a80ff2..14458dc 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -170,6 +170,96 @@ static void fdt_fixup_gic(void *blob)
 
return;
 }
+
+static int _fdt_fixup_msi_subnode(void *blob, int parentoffset,
+   const char *name, int irq_no)
+{
+   int err, offset;
+   u32 tmp[3];
+
+   offset = fdt_subnode_offset(blob, parentoffset, name);
+   if (offset < 0) {
+   printf("WARNING: fdt_subnode_offset can't find %s: %s\n",
+  name, fdt_strerror(offset));
+   return 0;
+   }
+
+   tmp[0] = cpu_to_fdt32(0x0);
+   tmp[1] = cpu_to_fdt32(irq_no);
+   tmp[2] = cpu_to_fdt32(0x4);
+
+   err = fdt_setprop(blob, offset, "interrupts", tmp, sizeof(tmp));
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
+  "interrupts", name, fdt_strerror(err));
+   return 0;
+   }
+
+   return 1;
+}
+
+static int _fdt_fixup_pci_msi(void *blob, const char *name)
+{
+   int offset, len, err;
+   void *p;
+   int val;
+   u32 tmp[4][8];
+
+   offset = fdt_path_offset(blob, name);
+   if (offset < 0) {
+   printf("WARNING: fdt_path_offset can't find path %s: %s\n",
+  name, fdt_strerror(offset));
+   return 0;
+   }
+
+   p = (char *)fdt_getprop(blob, offset, "interrupt-map", );
+   if (!p || len != sizeof(tmp)) {
+   printf("WARNING: fdt_getprop can't get %s from node %s\n",
+  "interrupt-map", name);
+   return 0;
+   }
+
+   memcpy((char *)tmp, p, len);
+   val = fdt32_to_cpu(tmp[0][6]);
+   tmp[1][6] = cpu_to_fdt32(val + 1);
+   tmp[2][6] = cpu_to_fdt32(val + 2);
+   tmp[3][6] = cpu_to_fdt32(val + 3);
+
+   err = fdt_setprop(blob, offset, "interrupt-map", tmp, sizeof(tmp));
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s.\n",
+  "interrupt-map", name, fdt_strerror(err));
+   return 0;
+   }
+   return 1;
+}
+
+/* Fixup msi to v1_0*/
+
+static void fdt_fixup_msi(void *blob)
+{
+   int nodeoffset;
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   unsigned int val;
+
+   val = gur_in32(>svr) & 0xff;
+   if (val == REV1_1)
+   return;
+
+   nodeoffset = fdt_path_offset(blob, "/soc/msi-controller");
+   if (nodeoffset < 0) {
+   printf("WARNING: fdt_path_offset can't find path %s: %s\n",
+  "/soc/msi-controller", fdt_strerror(nodeoffset));
+   return;
+   }
+   _fdt_fixup_msi_subnode(blob, nodeoffset, "msi0@1571000", 116);
+   _fdt_fixup_msi_subnode(blob, nodeoffset, "msi1@1572000", 126);
+   _fdt_fixup_msi_subnode(blob, nodeoffset, "msi2@1573000", 160);
+
+   _fdt_fixup_pci_msi(blob, "/soc/pcie@340");
+   _fdt_fixup_pci_msi(blob, "/soc/pcie@350");
+   _fdt_fixup_pci_msi(blob, "/soc/pcie@360");
+}
 #endif
 
 void ft_cpu_setup(void *blob, bd_t *bd)
@@ -190,6 +280,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
}
 #endif
fdt_fixup_gic(blob);
+   fdt_fixup_msi(blob);
 #endif
 
 #ifdef CONFIG_MP
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] armv8/fsl-layerscape: print SoC revsion number

[Wenbin song]

The exact SoC revsion number can be recognized from U-Boot log.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 340d9f9..37a96e4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -43,6 +43,9 @@ void cpu_name(char *name)
 
if (IS_E_PROCESSOR(svr))
strcat(name, "E");
+
+   sprintf(name + strlen(name), " Rev%d.%d",
+   SVR_MAJ(svr), SVR_MIN(svr));
break;
}
 
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] armv8/fsl-layerscape: print SoC revsion number

[Wenbin song]

The exact SoC revsion number can be recognized from U-Boot log.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 340d9f9..5cada6d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -40,6 +40,8 @@ void cpu_name(char *name)
for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
strcpy(name, cpu_type_list[i].name);
+   sprintf(name + strlen(name), " Rev%d.%d\n",
+   SVR_MAJ(svr), SVR_MIN(svr));
 
if (IS_E_PROCESSOR(svr))
strcat(name, "E");
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [patch v3 2/2] pxe: Modify README to add the description about FIT image

[Wenbin song]

Use environment variable "kernel_addr_r" to indicate the location
in RAM where FIT image will be stored.
Use label command "kernel" to indicate which  the FIT image at.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
Changes for v2: Fixup the email address of author.
---
 doc/README.pxe | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/doc/README.pxe b/doc/README.pxe
index cc182c9..db11658 100644
--- a/doc/README.pxe
+++ b/doc/README.pxe
@@ -78,9 +78,9 @@ pxe boot
  address of the tftp server from which other files will be retrieved.
 
  kernel_addr_r, initrd_addr_r - locations in RAM at which 'pxe boot' will
- store the kernel and initrd it retrieves from tftp. These locations will
- be passed to the bootm command to boot the kernel. These environment
- variables are required to be set.
+ store the kernel(or FIT image) and initrd it retrieves from tftp. These
+ locations will be passed to the bootm command to boot the kernel. These
+ environment variables are required to be set.
 
  fdt_addr_r - location in RAM at which 'pxe boot' will store the fdt blob 
it
  retrieves from tftp. The retrieval is possible if 'fdt' label is defined 
in
@@ -138,9 +138,9 @@ menu default- set this label as the default 
label to boot; this is
  specified in a different way
 
 kernel   - if this label is chosen, use tftp to retrieve the kernel
- at . it will be stored at the address indicated in
- the kernel_addr_r environment variable, and that address
- will be passed to bootm to boot this kernel.
+ (or FIT image) at . it will be stored at the address
+ indicated in the kernel_addr_r environment variable, and
+ that address will be passed to bootm to boot this kernel.
 
 append - use  as the kernel command line when 
booting this
  label.
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [patch v3 1/2] pxe: Fix pxe boot with FIT image

[Wenbin song]

From: York Sun <york@nxp.com>

When FIT image is used, a single image provides kernel, device
tree and optionally ramdisk. Argc and argv need to be adjusted
to support this.

Test cases:
1. Booting with legacy images
2. Booting with legacy images without initrd
3. Booting with FIT image
Test commands:
1. pxe get && pxe boot
2. sysboot

Signed-off-by: York Sun <york@nxp.com>
Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
Changes for v2: no change
---
 cmd/pxe.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/cmd/pxe.c b/cmd/pxe.c
index 9434a18..0a07f14 100644
--- a/cmd/pxe.c
+++ b/cmd/pxe.c
@@ -620,7 +620,7 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label 
*label)
char initrd_str[22];
char mac_str[29] = "";
char ip_str[68] = "";
-   int bootm_argc = 3;
+   int bootm_argc = 2;
int len = 0;
ulong kernel_addr;
void *buf;
@@ -652,8 +652,6 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label 
*label)
strcpy(bootm_argv[2], getenv("ramdisk_addr_r"));
strcat(bootm_argv[2], ":");
strcat(bootm_argv[2], getenv("filesize"));
-   } else {
-   bootm_argv[2] = "-";
}
 
if (get_relfile_envaddr(cmdtp, label->kernel, "kernel_addr_r") < 0) {
@@ -785,8 +783,11 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label 
*label)
if (!bootm_argv[3])
bootm_argv[3] = getenv("fdt_addr");
 
-   if (bootm_argv[3])
+   if (bootm_argv[3]) {
+   if (!bootm_argv[2])
+   bootm_argv[2] = "-";
bootm_argc = 4;
+   }
 
kernel_addr = genimg_get_kernel_addr(bootm_argv[1]);
buf = map_sysmem(kernel_addr, 0);
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [patch v2 2/2] pxe: Modify README to add the description about FIT image

[Wenbin song]

From: Wenbin song <qianyu.g...@nxp.com>

Use environment variable "kernel_addr_r" to indicate the location
in RAM where FIT image will be stored.
Use label command "kernel" to indicate which  the FIT image at.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
v2: new add.
---
 doc/README.pxe | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/doc/README.pxe b/doc/README.pxe
index cc182c9..db11658 100644
--- a/doc/README.pxe
+++ b/doc/README.pxe
@@ -78,9 +78,9 @@ pxe boot
  address of the tftp server from which other files will be retrieved.
 
  kernel_addr_r, initrd_addr_r - locations in RAM at which 'pxe boot' will
- store the kernel and initrd it retrieves from tftp. These locations will
- be passed to the bootm command to boot the kernel. These environment
- variables are required to be set.
+ store the kernel(or FIT image) and initrd it retrieves from tftp. These
+ locations will be passed to the bootm command to boot the kernel. These
+ environment variables are required to be set.
 
  fdt_addr_r - location in RAM at which 'pxe boot' will store the fdt blob 
it
  retrieves from tftp. The retrieval is possible if 'fdt' label is defined 
in
@@ -138,9 +138,9 @@ menu default- set this label as the default 
label to boot; this is
  specified in a different way
 
 kernel   - if this label is chosen, use tftp to retrieve the kernel
- at . it will be stored at the address indicated in
- the kernel_addr_r environment variable, and that address
- will be passed to bootm to boot this kernel.
+ (or FIT image) at . it will be stored at the address
+ indicated in the kernel_addr_r environment variable, and
+ that address will be passed to bootm to boot this kernel.
 
 append - use  as the kernel command line when 
booting this
  label.
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [patch v2 1/2] pxe: Fix pxe boot with FIT image

[Wenbin song]

From: York Sun <york@nxp.com>

When FIT image is used, a single image provides kernel, device
tree and optionally ramdisk. Argc and argv need to be adjusted
to support this.

Test cases:
1. Booting with legacy images
2. Booting with legacy images without initrd
3. Booting with FIT image
Test commands:
1. pxe get && pxe boot
2. sysboot

Signed-off-by: York Sun <york@nxp.com>
Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
v2: Add test cases on submit message.
---
 cmd/pxe.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/cmd/pxe.c b/cmd/pxe.c
index 9434a18..0a07f14 100644
--- a/cmd/pxe.c
+++ b/cmd/pxe.c
@@ -620,7 +620,7 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label 
*label)
char initrd_str[22];
char mac_str[29] = "";
char ip_str[68] = "";
-   int bootm_argc = 3;
+   int bootm_argc = 2;
int len = 0;
ulong kernel_addr;
void *buf;
@@ -652,8 +652,6 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label 
*label)
strcpy(bootm_argv[2], getenv("ramdisk_addr_r"));
strcat(bootm_argv[2], ":");
strcat(bootm_argv[2], getenv("filesize"));
-   } else {
-   bootm_argv[2] = "-";
}
 
if (get_relfile_envaddr(cmdtp, label->kernel, "kernel_addr_r") < 0) {
@@ -785,8 +783,11 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label 
*label)
if (!bootm_argv[3])
bootm_argv[3] = getenv("fdt_addr");
 
-   if (bootm_argv[3])
+   if (bootm_argv[3]) {
+   if (!bootm_argv[2])
+   bootm_argv[2] = "-";
bootm_argc = 4;
+   }
 
kernel_addr = genimg_get_kernel_addr(bootm_argv[1]);
buf = map_sysmem(kernel_addr, 0);
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] pxe: Fix pxe boot with FIT image

[Wenbin Song]

Hi, Tom

Yes, I have tested all kinds of cases.

Best Regards
Wenbin Song

> -Original Message-
> From: Tom Rini [mailto:tr...@konsulko.com]
> Sent: Tuesday, August 30, 2016 8:22 AM
> To: Wenbin Song <wenbin.s...@nxp.com>
> Cc: s...@chromium.org; bmeng...@gmail.com; h...@denx.de;
> p.marc...@samsung.com; s...@denx.de; york sun <york@nxp.com>; u-
> b...@lists.denx.de; Mingkai Hu <mingkai...@nxp.com>; Qianyu Gong
> <qianyu.g...@nxp.com>; Shaohui Xie <shaohui@nxp.com>;
> zhiqian@nxp.com
> Subject: Re: [U-Boot] [PATCH] pxe: Fix pxe boot with FIT image
> 
> On Thu, Aug 04, 2016 at 03:44:50PM +0800, Wenbin song wrote:
> 
> > From: York Sun <york@nxp.com>
> >
> > When FIT image is used, a single image provides kernel, device tree
> > and optionally ramdisk. Argc and argv need to be adjusted to support
> > this.
> >
> > Signed-off-by: York Sun <york@nxp.com>
> > ---
> >  cmd/pxe.c | 9 +
> >  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> Can you please confirm you tested the other common cases of PXE booting still
> work with this change?  Thanks!
> 
> --
> Tom
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] pxe: Fix pxe boot with FIT image

[Wenbin Song]

Hi,  

What would you advise?

Thanks.


Best Regards
Wenbin Song

> -Original Message-
> From: Wenbin song [mailto:wenbin.s...@nxp.com]
> Sent: Thursday, August 04, 2016 3:45 PM
> To: s...@chromium.org; bmeng...@gmail.com; h...@denx.de;
> p.marc...@samsung.com; s...@denx.de; york sun <york@nxp.com>; u-
> b...@lists.denx.de; Mingkai Hu <mingkai...@nxp.com>; Wenbin Song
> <wenbin.s...@nxp.com>; Qianyu Gong <qianyu.g...@nxp.com>; Shaohui Xie
> <shaohui@nxp.com>; zhiqian@nxp.com
> Subject: [PATCH] pxe: Fix pxe boot with FIT image
> 
> From: York Sun <york@nxp.com>
> 
> When FIT image is used, a single image provides kernel, device tree and
> optionally ramdisk. Argc and argv need to be adjusted to support this.
> 
> Signed-off-by: York Sun <york@nxp.com>
> ---
>  cmd/pxe.c | 9 +
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/cmd/pxe.c b/cmd/pxe.c
> index 9434a18..0a07f14 100644
> --- a/cmd/pxe.c
> +++ b/cmd/pxe.c
> @@ -620,7 +620,7 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label
> *label)
>   char initrd_str[22];
>   char mac_str[29] = "";
>   char ip_str[68] = "";
> - int bootm_argc = 3;
> + int bootm_argc = 2;
>   int len = 0;
>   ulong kernel_addr;
>   void *buf;
> @@ -652,8 +652,6 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label
> *label)
>   strcpy(bootm_argv[2], getenv("ramdisk_addr_r"));
>   strcat(bootm_argv[2], ":");
>   strcat(bootm_argv[2], getenv("filesize"));
> - } else {
> - bootm_argv[2] = "-";
>   }
> 
>   if (get_relfile_envaddr(cmdtp, label->kernel, "kernel_addr_r") < 0) { @@
> -785,8 +783,11 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label
> *label)
>   if (!bootm_argv[3])
>   bootm_argv[3] = getenv("fdt_addr");
> 
> - if (bootm_argv[3])
> + if (bootm_argv[3]) {
> + if (!bootm_argv[2])
> + bootm_argv[2] = "-";
>   bootm_argc = 4;
> + }
> 
>   kernel_addr = genimg_get_kernel_addr(bootm_argv[1]);
>   buf = map_sysmem(kernel_addr, 0);
> --
> 2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] pxe: Fix pxe boot with FIT image

[Wenbin song]

From: York Sun 

When FIT image is used, a single image provides kernel, device
tree and optionally ramdisk. Argc and argv need to be adjusted
to support this.

Signed-off-by: York Sun 
---
 cmd/pxe.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/cmd/pxe.c b/cmd/pxe.c
index 9434a18..0a07f14 100644
--- a/cmd/pxe.c
+++ b/cmd/pxe.c
@@ -620,7 +620,7 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label 
*label)
char initrd_str[22];
char mac_str[29] = "";
char ip_str[68] = "";
-   int bootm_argc = 3;
+   int bootm_argc = 2;
int len = 0;
ulong kernel_addr;
void *buf;
@@ -652,8 +652,6 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label 
*label)
strcpy(bootm_argv[2], getenv("ramdisk_addr_r"));
strcat(bootm_argv[2], ":");
strcat(bootm_argv[2], getenv("filesize"));
-   } else {
-   bootm_argv[2] = "-";
}
 
if (get_relfile_envaddr(cmdtp, label->kernel, "kernel_addr_r") < 0) {
@@ -785,8 +783,11 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label 
*label)
if (!bootm_argv[3])
bootm_argv[3] = getenv("fdt_addr");
 
-   if (bootm_argv[3])
+   if (bootm_argv[3]) {
+   if (!bootm_argv[2])
+   bootm_argv[2] = "-";
bootm_argc = 4;
+   }
 
kernel_addr = genimg_get_kernel_addr(bootm_argv[1]);
buf = map_sysmem(kernel_addr, 0);
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] ARMv8/ls1046a: Cleanup the environment variables

[Wenbin song]

Cleanup the variables: "kernel_addr","ramdisk_addr",
"ramdisk_size","console".

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
 include/configs/ls1043a_common.h | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index b0d4a8d..a651130 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -245,15 +245,12 @@
 #define CONFIG_EXTRA_ENV_SETTINGS  \
"hwconfig=fsl_ddr:bank_intlv=auto\0"\
"loadaddr=0x8010\0" \
-   "kernel_addr=0x10\0"\
-   "ramdisk_addr=0x80\0"   \
-   "ramdisk_size=0x200\0"  \
"fdt_high=0x\0" \
"initrd_high=0x\0"  \
"kernel_start=0x6110\0" \
"kernel_load=0xa000\0"  \
"kernel_size=0x280\0"   \
-   "console=ttyAMA0,38400n8\0"
+   "console=ttyS0,115200\0"
 
 #define CONFIG_BOOTARGS"console=ttyS0,115200 
root=/dev/ram0 " \
"earlycon=uart8250,mmio,0x21c0500"
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [patch v2] armv8/ls1043a: Add MTD partition scheme

[Wenbin song]

From: Wenbin Song <wenbin.s...@nxp.com>

Add and share the the MTD partition scheme with kernel by defualt bootargs.
And add the "mtdparts" env.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
Changes for v2: rebase 
---
 include/configs/ls1043a_common.h | 22 --
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index a651130..0ad5261 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -241,6 +241,21 @@
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE   128
 
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
+   "5m(kernel),1m(dtb),9m(file_system)"
+#else
+#define MTDPARTS_DEFAULT "mtdparts=6000.nor:1m(nor_bank0_rcw)," \
+   "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
+   "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
+   "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
+   "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
+   "40m(nor_bank4_fit);7e80.flash:" \
+   "1m(nand_uboot),1m(nand_uboot_env)," \
+   "20m(nand_fit);spi0.0:1m(uboot)," \
+   "5m(kernel),1m(dtb),9m(file_system)"
+#endif
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS  \
"hwconfig=fsl_ddr:bank_intlv=auto\0"\
@@ -250,10 +265,13 @@
"kernel_start=0x6110\0" \
"kernel_load=0xa000\0"  \
"kernel_size=0x280\0"   \
-   "console=ttyS0,115200\0"
+   "console=ttyS0,115200\0"\
+   "mtdparts=" MTDPARTS_DEFAULT "\0"
 
 #define CONFIG_BOOTARGS"console=ttyS0,115200 
root=/dev/ram0 " \
-   "earlycon=uart8250,mmio,0x21c0500"
+   "earlycon=uart8250,mmio,0x21c0500 "\
+   MTDPARTS_DEFAULT
+
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load "\
"e f0 && bootm $kernel_load"
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] armv8/ls1043a: Add MTD partition scheme

[Wenbin Song]

Hi: York

I'm sorry to have misunderstood you mean.
I think it is a good idea that modify/remove the wrong/useless variables  in a 
new patch.
And I will make it later.
Do you have any suggestion?

Best Regards
Wenbin Song

> -Original Message-
> From: york sun
> Sent: Wednesday, July 20, 2016 6:02 AM
> To: Wenbin Song <wenbin.s...@nxp.com>; Mingkai Hu <mingkai...@nxp.com>;
> u-boot@lists.denx.de
> Cc: Qianyu Gong <qianyu.g...@nxp.com>; Shaohui Xie <shaohui@nxp.com>;
> Zhiqiang Hou <zhiqiang@nxp.com>
> Subject: Re: [PATCH] armv8/ls1043a: Add MTD partition scheme
> 
> On 04/06/2016 10:46 PM, Wenbin Song wrote:
> > Hi: York
> >
> > Please see my inline comments.
> >
> > Best Regards
> > Wenbin Song
> >
> >> -Original Message-
> >> From: York Sun [mailto:york@nxp.com]
> >> Sent: Thursday, April 07, 2016 1:18 AM
> >> To: Wenbin Song <wenbin.s...@nxp.com>; Mingkai Hu
> >> <mingkai...@nxp.com>; u-boot@lists.denx.de
> >> Cc: Qianyu Gong <qianyu.g...@nxp.com>; Shaohui Xie
> >> <shaohui@nxp.com>; Zhiqiang Hou <zhiqiang@nxp.com>
> >> Subject: Re: [PATCH] armv8/ls1043a: Add MTD partition scheme
> >>
> >> On 04/06/2016 12:11 AM, Wenbin Song wrote:
> >>> Hi: York
> >>>
> >>> I set bootargs  as the following steps:
> >>>
> >>> => env default mtdparts
> >>> => printenv mtdparts
> >>>
> >> mtdparts=mtdparts=6000.nor:1m(nor_bank0_rcw),1m(nor_bank0_uboot)
> >> ,1
> >>>
> >> m(nor_bank0_uboot_env),1m(nor_bank0_fman_uconde),40m(nor_bank0_fit
> >> ),1m
> >>>
> >> (nor_bank4_rcw),1m(nor_bank4_uboot),1m(nor_bank4_uboot_env),1m(nor_
> >> ban
> >>>
> >> k4_fman_ucode),40m(nor_bank4_fit);7e80.flash:1m(nand_uboot),1m(na
> >> n
> >>> d_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(fi
> >>> le
> >>> _system)
> >>> => env default bootargs
> >>> => printenv bootargs
> >>> bootargs=console=ttyS0,115200 root=/dev/ram0
> >>> earlycon=uart8250,mmio,0x21c0500 ${mtdparts}
> >>>
> >>>
> >>> The macro  CONFIG_BOOTARGS  only be extern as an char-string, and it
> >>> will
> >> be spliced into default_environment array .
> >>>
> >>>  const uchar default_environment[] = { #ifdef  CONFIG_BOOTARGS
> >>>   "bootargs=" CONFIG_BOOTARGS "\0"
> >>>  #endif
> >>>
> >>> The variable we use to have $consoledev, $othbootargs  was used in
> >>> the
> >> following cases:
> >>>
> >>> 858  #define CONFIG_BOOTCOMMAND \
> >>> 859 "setenv bootargs root=/dev/ram rw " \
> >>> 860 "console=$consoledev,$baudrate $othbootargs;"   \
> >>> 861 "setenv ramdiskaddr 0x0200;"\
> >>> 862 "setenv fdtaddr 0x00c0;"\
> >>> 863 "setenv loadaddr 0x100;"\
> >>> 864 "bootm $loadaddr $ramdiskaddr $fdtaddr"
> >>>
> >>> Because the "setenv"  will be executed  , So the variable could be 
> >>> extended.
> >>
> >> I see what you mean. I am trying to reduce the environmental variables.
> >> Do you need the variable "mtdparts"?
> >
> > [wenbin]
> >
> > I export this variable in order to make easier  to modify the bootargs under
> uboot command-line.
> >
> > For example:
> > =>setenv bootargs  "console=ttyS0,115200  root=/dev/ram0  $mtdparts"
> > =>setenv bootargs  "console=ttyLP0,115200  root=/dev/ram0  $mtdparts"
> >
> > Use the $mtdparts to instead of a long string.
> >
> >
> >> Would it be a better idea to set bootargs using the bootcmd?
> > [wenbin]
> >
> >  yes, It is a good idea.
> >  But we need all kinds of  ways to boot kernel  with this  "bootargs".  The
> bootcmd only can specify one boot-way.
> > IOW,  only the way specified by this "bootcmd"  can  execute " setenv  
> > bootargs".
> > So I want to supply the default bootargs  by the CONFIG_BOOTARGS .
> >
> >
> >>
> >> While you are on it, I suggest you take a look at other variables.
> >> "console=ttyAMA0,38400n8" is wrong here.
> >>
> >> We don't have to copy kernel image from NOR flash to DDR if the
> >> ramdisk load address is set properly in its file. So you can remove the 
> >> copying
> from bootcmd.
> >>
> > [wenbin]
> >
> > Ok, thanks for your advices,  I will modify them on the later patch.
> >
> 
> Wenbin,
> 
> Do you have an update?
> 
> York

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] armv8: ls1043a: add pxe commands

[Wenbin Song]

Configure to support U-boot's pxe.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
 include/configs/ls1043a_common.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index b0d4a8d..2083b0d 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -175,6 +175,8 @@
 
 /* Command line configuration */
 #define CONFIG_CMD_ENV
+#define CONFIG_MENU
+#define CONFIG_CMD_PXE
 
 /*  MMC  */
 #define CONFIG_MMC
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] armv8/ls1043a: Add MTD partition scheme

[Wenbin Song]

Hi: York

Please see my inline comments.

Best Regards
Wenbin Song

> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Thursday, April 07, 2016 1:18 AM
> To: Wenbin Song <wenbin.s...@nxp.com>; Mingkai Hu
> <mingkai...@nxp.com>; u-boot@lists.denx.de
> Cc: Qianyu Gong <qianyu.g...@nxp.com>; Shaohui Xie
> <shaohui@nxp.com>; Zhiqiang Hou <zhiqiang@nxp.com>
> Subject: Re: [PATCH] armv8/ls1043a: Add MTD partition scheme
> 
> On 04/06/2016 12:11 AM, Wenbin Song wrote:
> > Hi: York
> >
> > I set bootargs  as the following steps:
> >
> > => env default mtdparts
> > => printenv mtdparts
> >
> mtdparts=mtdparts=6000.nor:1m(nor_bank0_rcw),1m(nor_bank0_uboot)
> ,1
> >
> m(nor_bank0_uboot_env),1m(nor_bank0_fman_uconde),40m(nor_bank0_fit
> ),1m
> >
> (nor_bank4_rcw),1m(nor_bank4_uboot),1m(nor_bank4_uboot_env),1m(nor_
> ban
> >
> k4_fman_ucode),40m(nor_bank4_fit);7e80.flash:1m(nand_uboot),1m(na
> n
> > d_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file
> > _system)
> > => env default bootargs
> > => printenv bootargs
> > bootargs=console=ttyS0,115200 root=/dev/ram0
> > earlycon=uart8250,mmio,0x21c0500 ${mtdparts}
> >
> >
> > The macro  CONFIG_BOOTARGS  only be extern as an char-string, and it will
> be spliced into default_environment array .
> >
> >  const uchar default_environment[] = { #ifdef  CONFIG_BOOTARGS
> >   "bootargs=" CONFIG_BOOTARGS "\0"
> >  #endif
> >
> > The variable we use to have $consoledev, $othbootargs  was used in the
> following cases:
> >
> > 858  #define CONFIG_BOOTCOMMAND \
> > 859 "setenv bootargs root=/dev/ram rw " \
> > 860 "console=$consoledev,$baudrate $othbootargs;"   \
> > 861 "setenv ramdiskaddr 0x0200;"\
> > 862 "setenv fdtaddr 0x00c0;"\
> > 863 "setenv loadaddr 0x100;"\
> > 864 "bootm $loadaddr $ramdiskaddr $fdtaddr"
> >
> > Because the "setenv"  will be executed  , So the variable could be extended.
> 
> I see what you mean. I am trying to reduce the environmental variables.
> Do you need the variable "mtdparts"?

[wenbin] 

I export this variable in order to make easier  to modify the bootargs under 
uboot command-line.

For example:
=>setenv bootargs  "console=ttyS0,115200  root=/dev/ram0  $mtdparts"
=>setenv bootargs  "console=ttyLP0,115200  root=/dev/ram0  $mtdparts"

Use the $mtdparts to instead of a long string.


> Would it be a better idea to set bootargs using the bootcmd?
[wenbin]

 yes, It is a good idea.
 But we need all kinds of  ways to boot kernel  with this  "bootargs".  The 
bootcmd only can specify one boot-way.
IOW,  only the way specified by this "bootcmd"  can  execute " setenv  
bootargs".
So I want to supply the default bootargs  by the CONFIG_BOOTARGS .


> 
> While you are on it, I suggest you take a look at other variables.
> "console=ttyAMA0,38400n8" is wrong here.
> 
> We don't have to copy kernel image from NOR flash to DDR if the ramdisk load
> address is set properly in its file. So you can remove the copying from 
> bootcmd.
> 
[wenbin]

Ok, thanks for your advices,  I will modify them on the later patch. 

> York

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] armv8/ls1043a: Add MTD partition scheme

[Wenbin Song]

Hi: York

I set bootargs  as the following steps:

=> env default mtdparts
=> printenv mtdparts
mtdparts=mtdparts=6000.nor:1m(nor_bank0_rcw),1m(nor_bank0_uboot),1m(nor_bank0_uboot_env),1m(nor_bank0_fman_uconde),40m(nor_bank0_fit),1m(nor_bank4_rcw),1m(nor_bank4_uboot),1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode),40m(nor_bank4_fit);7e80.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)
=> env default bootargs
=> printenv bootargs
bootargs=console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 
${mtdparts}


The macro  CONFIG_BOOTARGS  only be extern as an char-string, and it will be 
spliced into default_environment array . 

 const uchar default_environment[] = {
#ifdef  CONFIG_BOOTARGS
  "bootargs=" CONFIG_BOOTARGS "\0"
 #endif
 
The variable we use to have $consoledev, $othbootargs  was used in the 
following cases:

858  #define CONFIG_BOOTCOMMAND \
859 "setenv bootargs root=/dev/ram rw " \
860 "console=$consoledev,$baudrate $othbootargs;"   \
861 "setenv ramdiskaddr 0x0200;"\
862 "setenv fdtaddr 0x00c0;"\
863 "setenv loadaddr 0x100;"\
864 "bootm $loadaddr $ramdiskaddr $fdtaddr"

Because the "setenv"  will be executed  , So the variable could be extended.

What do you suggest?

Best Regards
Wenbin Song


> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Wednesday, April 06, 2016 12:39 PM
> To: Wenbin Song <wenbin.s...@nxp.com>; Mingkai Hu
> <mingkai...@nxp.com>; u-boot@lists.denx.de
> Cc: Qianyu Gong <qianyu.g...@nxp.com>; Shaohui Xie
> <shaohui@nxp.com>; Zhiqiang Hou <zhiqiang@nxp.com>
> Subject: Re: [PATCH] armv8/ls1043a: Add MTD partition scheme
> 
> On 04/05/2016 09:20 PM, Wenbin Song wrote:
> > Hi: York
> >
> > Do you mean that I should use $mtdpart to instead of
> "MTDPARTS_DEFAULT" ?
> >
> > As follows:
> >#define CONFIG_BOOTARGS "console=ttyS0,115200
> root=/dev/ram0 " \
> >  
> > "earlycon=uart8250,mmio,0x21c0500 " \
> >"$mtdparts"
> >
> > If so, the variable $mtdparts can't  be extend ,like that:
> >
> > root@ls1043aqds:~# cat /proc/cmdline
> > console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500
> > ${mtdparts}
> >
> 
> What do you see "print bootargs" under U-Boot?
> I thought the variable can be extended when U-Boot runs the command. Like
> we used to have $consoledev, $othbootargs, etc.
> 
> York

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] armv8/ls1043a: Add MTD partition scheme

[Wenbin Song]

Hi: York

1, There is an issue for sdk2.0 kernel that the nor-flash can't be probed . we 
can fix it as follow:

$make menuconfig

  x -> Device Drivers   


  x-> Memory Technology Device (MTD) support 
  x  -> RAM/ROM/Flash chip drivers  
  
  x-> Flash chip driver advanced configuration options 
  x-> Flash cmd/query data swapping 

   x x  ( ) NO   
   x x  (X) BIG_ENDIAN_BYTE 
   x x  ( ) LITTLE_ENDIAN_BYTE   

Enable BIG_ENDIAN_BYTE .

2,  The  spi-nor flash can working on  ls1043aqds , and I use the sdk2.0 kernel 
(ce5a3841f3).
  [1.598954] m25p80 spi0.0: n25q128a11 (16384 Kbytes)
[1.603923] 4 cmdlinepart partitions found on MTD device spi0.0
[1.609842] Creating 4 MTD partitions on "spi0.0":
[1.614624] 0x-0x0010 : "uboot"
[1.624205] ftl_cs: FTL header not found.
[1.628421] 0x0010-0x0060 : "kernel"
[1.638086] ftl_cs: FTL header not found.
[1.642316] 0x0060-0x0070 : "dtb"
[1.651702] ftl_cs: FTL header not found.
[1.655932] 0x0070-0x0100 : "file_system"
[1.666028] ftl_cs: FTL header not found.

Best Regards
Wenbin Song


> -Original Message-
> From: York Sun [mailto:york....@nxp.com]
> Sent: Wednesday, April 06, 2016 5:02 AM
> To: Wenbin Song <wenbin.s...@nxp.com>; Mingkai Hu
> <mingkai...@nxp.com>; u-boot@lists.denx.de
> Cc: Qianyu Gong <qianyu.g...@nxp.com>; Shaohui Xie
> <shaohui@nxp.com>; Zhiqiang Hou <zhiqiang@nxp.com>
> Subject: Re: [PATCH] armv8/ls1043a: Add MTD partition scheme
> 
> On 04/05/2016 01:32 PM, York Sun wrote:
> > On 04/01/2016 02:37 AM, Wenbin Song wrote:
> >> Add and share the the MTD partition scheme with kernel by defualt
> bootargs.
> >> And add the "mtdparts" env.
> >>
> >> Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
> >> ---
> >>  include/configs/ls1043a_common.h | 22 --
> >>  1 file changed, 20 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/include/configs/ls1043a_common.h
> >> b/include/configs/ls1043a_common.h
> >> index fd243b1..6964873 100644
> >> --- a/include/configs/ls1043a_common.h
> >> +++ b/include/configs/ls1043a_common.h
> >> @@ -236,6 +236,21 @@
> >>  #define CONFIG_HWCONFIG
> >>  #define HWCONFIG_BUFFER_SIZE  128
> >>
> >> +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
> >> +#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
> >> +  "5m(kernel),1m(dtb),9m(file_system)"
> >> +#else
> >> +#define MTDPARTS_DEFAULT
> "mtdparts=6000.nor:1m(nor_bank0_rcw)," \
> >> +  "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env),"
> \
> >> +  "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit),"
> \
> >> +  "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
> >> +
>   "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
> >> +  "40m(nor_bank4_fit);7e80.flash:" \
> >> +  "1m(nand_uboot),1m(nand_uboot_env)," \
> >> +  "20m(nand_fit);spi0.0:1m(uboot)," \
> >> +  "5m(kernel),1m(dtb),9m(file_system)"
> >> +#endif
> >> +
> >>  /* Initial environment variables */
> >>  #define CONFIG_EXTRA_ENV_SETTINGS \
> >>"hwconfig=fsl_ddr:bank_intlv=auto\0"\
> >> @@ -248,10 +263,13 @@
> >>"kernel_start=0x6110\0" \
> >>"kernel_load=0xa000\0"  \
> >>"kernel_size=0x280\0"   \
> >> -  "console=ttyAMA0,38400n8\0"
> >> +  "console=ttyAMA0,38400n8\0" \
> >> +  "mtdparts=" MTDPARTS_DEFAULT "\0"
> >>
> >>  #define CONFIG_BOOTARGS   "console=ttyS0,115200
> root=/dev/ram0 " \
> >> -  "earlycon=uart8250,mmio,0x21c0500"
> >> +  "earlycon=uart8250,mmio,0x21c0500 " \
> >> +  MTDPARTS_DEFAULT
> >
> > You could use $mtdparts here so your bootcmd doesn't get too long.
> >
> 
> Wenbin,
> 
> A related question regarding MTD, how do you make NOR MTD device working
> on these boards (ls1043aqds and ls1043ardb)? This is a common file for both
> RDB and QDS. I presume you have verified on both. I have nand working on
> both, spi-nor working on rdb only. I don't have NOR working on either of them.
> It may be not a U-Boot issue though.
> 
> York
> 

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] armv8/ls1043a: Add MTD partition scheme

[Wenbin Song]

Hi: York

Do you mean that I should use $mtdpart to instead of "MTDPARTS_DEFAULT" ?
 
As follows: 
   #define CONFIG_BOOTARGS "console=ttyS0,115200 
root=/dev/ram0 " \
 
"earlycon=uart8250,mmio,0x21c0500 " \
   "$mtdparts"

If so, the variable $mtdparts can't  be extend ,like that:

root@ls1043aqds:~# cat /proc/cmdline
console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ${mtdparts}


Best Regards
Wenbin Song


> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Wednesday, April 06, 2016 4:33 AM
> To: Wenbin Song <wenbin.s...@nxp.com>; Mingkai Hu
> <mingkai...@nxp.com>; u-boot@lists.denx.de
> Cc: Qianyu Gong <qianyu.g...@nxp.com>; Shaohui Xie
> <shaohui@nxp.com>; Zhiqiang Hou <zhiqiang@nxp.com>
> Subject: Re: [PATCH] armv8/ls1043a: Add MTD partition scheme
> 
> On 04/01/2016 02:37 AM, Wenbin Song wrote:
> > Add and share the the MTD partition scheme with kernel by defualt bootargs.
> > And add the "mtdparts" env.
> >
> > Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
> > ---
> >  include/configs/ls1043a_common.h | 22 --
> >  1 file changed, 20 insertions(+), 2 deletions(-)
> >
> > diff --git a/include/configs/ls1043a_common.h
> > b/include/configs/ls1043a_common.h
> > index fd243b1..6964873 100644
> > --- a/include/configs/ls1043a_common.h
> > +++ b/include/configs/ls1043a_common.h
> > @@ -236,6 +236,21 @@
> >  #define CONFIG_HWCONFIG
> >  #define HWCONFIG_BUFFER_SIZE   128
> >
> > +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
> #define
> > +MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
> > +   "5m(kernel),1m(dtb),9m(file_system)"
> > +#else
> > +#define MTDPARTS_DEFAULT
> "mtdparts=6000.nor:1m(nor_bank0_rcw)," \
> > +   "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env),"
> \
> > +   "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit),"
> \
> > +   "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
> > +
>   "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
> > +   "40m(nor_bank4_fit);7e80.flash:" \
> > +   "1m(nand_uboot),1m(nand_uboot_env)," \
> > +   "20m(nand_fit);spi0.0:1m(uboot)," \
> > +   "5m(kernel),1m(dtb),9m(file_system)"
> > +#endif
> > +
> >  /* Initial environment variables */
> >  #define CONFIG_EXTRA_ENV_SETTINGS  \
> > "hwconfig=fsl_ddr:bank_intlv=auto\0"\
> > @@ -248,10 +263,13 @@
> > "kernel_start=0x6110\0" \
> > "kernel_load=0xa000\0"  \
> > "kernel_size=0x280\0"   \
> > -   "console=ttyAMA0,38400n8\0"
> > +   "console=ttyAMA0,38400n8\0" \
> > +   "mtdparts=" MTDPARTS_DEFAULT "\0"
> >
> >  #define CONFIG_BOOTARGS"console=ttyS0,115200
> root=/dev/ram0 " \
> > -   "earlycon=uart8250,mmio,0x21c0500"
> > +   "earlycon=uart8250,mmio,0x21c0500 " \
> > +   MTDPARTS_DEFAULT
> 
> You could use $mtdparts here so your bootcmd doesn't get too long.
> 
> York

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] armv8/ls1043aqds modify CONFIG_SYS_MAX_FLASH_BANKS to 1

[Wenbin Song]

There is only one flash bank for ls1043aqds.
Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
 include/configs/ls1043aqds.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 7b99d36..7c19122 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -162,7 +162,7 @@ unsigned long get_board_ddr_clk(void);
FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3   0
 
-#define CONFIG_SYS_MAX_FLASH_BANKS 2   /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1   /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT  1024/* sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT6   /* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT500 /* Flash Write Timeout (ms) */
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] armv8/ls1043a: Add MTD partition scheme

[Wenbin Song]

Add and share the the MTD partition scheme with kernel by defualt bootargs.
And add the "mtdparts" env.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
 include/configs/ls1043a_common.h | 22 --
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index fd243b1..6964873 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -236,6 +236,21 @@
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE   128
 
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
+   "5m(kernel),1m(dtb),9m(file_system)"
+#else
+#define MTDPARTS_DEFAULT "mtdparts=6000.nor:1m(nor_bank0_rcw)," \
+   "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
+   "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
+   "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
+   "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
+   "40m(nor_bank4_fit);7e80.flash:" \
+   "1m(nand_uboot),1m(nand_uboot_env)," \
+   "20m(nand_fit);spi0.0:1m(uboot)," \
+   "5m(kernel),1m(dtb),9m(file_system)"
+#endif
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS  \
"hwconfig=fsl_ddr:bank_intlv=auto\0"\
@@ -248,10 +263,13 @@
"kernel_start=0x6110\0" \
"kernel_load=0xa000\0"  \
"kernel_size=0x280\0"   \
-   "console=ttyAMA0,38400n8\0"
+   "console=ttyAMA0,38400n8\0" \
+   "mtdparts=" MTDPARTS_DEFAULT "\0"
 
 #define CONFIG_BOOTARGS"console=ttyS0,115200 
root=/dev/ram0 " \
-   "earlycon=uart8250,mmio,0x21c0500"
+   "earlycon=uart8250,mmio,0x21c0500 " \
+   MTDPARTS_DEFAULT
+
 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
"$kernel_size && bootm $kernel_load"
 #define CONFIG_BOOTDELAY   10
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 2/3] armv8/ls1043aqds: Return i2c mux to default chennel

[Wenbin Song]

Return i2c mux to the default channel after accessing retimer.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
Change for v2:
-Rework the commit message and the subject
---
 board/freescale/ls1043aqds/ls1043aqds.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c 
b/board/freescale/ls1043aqds/ls1043aqds.c
index a72fe52..fba6b88 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -170,8 +170,7 @@ void board_retimer_init(void)
u8 reg;
 
/* Retimer is connected to I2C1_CH7_CH5 */
-   reg = I2C_MUX_CH7;
-   i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, , 1);
+   select_i2c_ch_pca9547(I2C_MUX_CH7);
reg = I2C_MUX_CH5;
i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, , 1);
 
@@ -219,6 +218,9 @@ void board_retimer_init(void)
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, , 1);
reg = 0xcd;
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, , 1);
+
+   /* Return the default channel */
+   select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 }
 
 int board_early_init_f(void)
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 3/3] armv8/ls1043aqds: Enable ID_EEPROM support for ls1043aqds

[Wenbin Song]

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
Changes for v2:
-Rework the subject
---
 include/configs/ls1043aqds.h | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 158cf02..e269522 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -114,6 +114,16 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_DOS_PARTITION
 #define CONFIG_BOARD_LATE_INIT
 
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM  0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS  3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  5
+
 #define CONFIG_SYS_SATAAHCI_BASE_ADDR
 
 #define CONFIG_SYS_SCSI_MAX_SCSI_ID1
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 1/3] freescale: vid: Return i2c mux to default channel

[Wenbin Song]

IR chip is on one of the channels on multiplexed I2C-bus.
Reset to default channel after accessing.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
Changes for v2:
-Rework the commit message and the tag int the subject.
---
 board/freescale/common/vid.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index 1bd65a8..a6a132a 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -454,6 +454,9 @@ int adjust_vdd(ulong vdd_override)
 exit:
if (re_enable)
enable_interrupts();
+
+   i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
+
return ret;
 }
 
@@ -469,7 +472,7 @@ static int print_vdd(void)
ret = find_ir_chip_on_i2c();
if (ret < 0) {
printf("VID: Could not find voltage regulator on I2C.\n");
-   return -1;
+   goto exit;
} else {
i2caddress = ret;
debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
@@ -481,11 +484,14 @@ static int print_vdd(void)
vdd_last = read_voltage(i2caddress);
if (vdd_last < 0) {
printf("VID: Couldn't read sensor abort VID adjustment\n");
-   return -1;
+   goto exit;
}
printf("VID: Core voltage is at %d mV\n", vdd_last);
+exit:
+   i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
+
+   return ret < 0 ? -1 : 0;
 
-   return 0;
 }
 
 static int do_vdd_override(cmd_tbl_t *cmdtp,
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 2/3] armv8/ls1043aqds: Return the default chennel

[Wenbin Song]

In order to avoid effecting some i2c devices
mounted on default channel, return the default
channel after retimer initialization.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
 board/freescale/ls1043aqds/ls1043aqds.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c 
b/board/freescale/ls1043aqds/ls1043aqds.c
index a72fe52..fba6b88 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -170,8 +170,7 @@ void board_retimer_init(void)
u8 reg;
 
/* Retimer is connected to I2C1_CH7_CH5 */
-   reg = I2C_MUX_CH7;
-   i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, , 1);
+   select_i2c_ch_pca9547(I2C_MUX_CH7);
reg = I2C_MUX_CH5;
i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, , 1);
 
@@ -219,6 +218,9 @@ void board_retimer_init(void)
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, , 1);
reg = 0xcd;
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, , 1);
+
+   /* Return the default channel */
+   select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 }
 
 int board_early_init_f(void)
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 1/3] vid: Return to default channel of the i2c multiplexer

[Wenbin Song]

If the IR chip is connected to one of the channel of I2C-bus
multiplexer, Set to the default channel after accessing the IR chip.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
 board/freescale/common/vid.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index 1bd65a8..a6a132a 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -454,6 +454,9 @@ int adjust_vdd(ulong vdd_override)
 exit:
if (re_enable)
enable_interrupts();
+
+   i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
+
return ret;
 }
 
@@ -469,7 +472,7 @@ static int print_vdd(void)
ret = find_ir_chip_on_i2c();
if (ret < 0) {
printf("VID: Could not find voltage regulator on I2C.\n");
-   return -1;
+   goto exit;
} else {
i2caddress = ret;
debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
@@ -481,11 +484,14 @@ static int print_vdd(void)
vdd_last = read_voltage(i2caddress);
if (vdd_last < 0) {
printf("VID: Couldn't read sensor abort VID adjustment\n");
-   return -1;
+   goto exit;
}
printf("VID: Core voltage is at %d mV\n", vdd_last);
+exit:
+   i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
+
+   return ret < 0 ? -1 : 0;
 
-   return 0;
 }
 
 static int do_vdd_override(cmd_tbl_t *cmdtp,
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 3/3] armv8/ls1043aqds: Add SYS_EEPROM support

[Wenbin Song]

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
 include/configs/ls1043aqds.h | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 158cf02..e269522 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -114,6 +114,16 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_DOS_PARTITION
 #define CONFIG_BOARD_LATE_INIT
 
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM  0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS  3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  5
+
 #define CONFIG_SYS_SATAAHCI_BASE_ADDR
 
 #define CONFIG_SYS_SCSI_MAX_SCSI_ID1
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v3 1/3] armv8/ls1043aqds: Select lpuart pins of various muxes

[Wenbin Song]

From: Shaohui Xie 

Set Board Configuration Register to select the lpuart pins of various
muxes.

Signed-off-by: Shaohui Xie 
Signed-off-by: Mingkai Hu 
---
 board/freescale/ls1043aqds/ls1043aqds.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c 
b/board/freescale/ls1043aqds/ls1043aqds.c
index d6696ca..67f4c4b 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -40,6 +40,9 @@ enum {
 #define CFG_SD_MUX3_MUX4   0x1 /* MUX4 */
 #define CFG_SD_MUX4_SLOT3  0x0 /* SLOT3 TX/RX1 */
 #define CFG_SD_MUX4_SLOT1  0x1 /* SLOT1 TX/RX3 */
+#define CFG_UART_MUX_MASK  0x6
+#define CFG_UART_MUX_SHIFT 1
+#define CFG_LPUART_EN  0x1
 
 int checkboard(void)
 {
@@ -218,7 +221,19 @@ void board_retimer_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_LPUART
+   u8 uart;
+#endif
fsl_lsch2_early_init_f();
+#ifdef CONFIG_LPUART
+
+/* We use lpuart1 as system console. */
+
+   uart = QIXIS_READ(brdcfg[14]);
+   uart &= ~CFG_UART_MUX_MASK;
+   uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
+   QIXIS_WRITE(brdcfg[14], uart);
+#endif
 
return 0;
 }
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] Patch dependency

[Wenbin Song]

The below patches depend on the series 
patches(http://patchwork.ozlabs.org/patch/567250/).
 
[PATCH v3 1/3] armv8/ls1043aqds: Select lpuart pins of various muxes
[PATCH v3 2/3] armv8/ls1043aqds: Spilt off board device tree
[PATCH v3 3/3] armv8/ls1043aqds: Add lpuart support
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v3 3/3] armv8/ls1043aqds: Add lpuart support

[Wenbin Song]

Add lpuart support using the driver model.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
 arch/arm/dts/Makefile   |  1 +
 arch/arm/dts/fsl-ls1043a-qds-lpuart.dts | 16 ++
 arch/arm/dts/fsl-ls1043a-qds.dtsi   |  4 +++
 arch/arm/dts/fsl-ls1043a.dtsi   | 54 +
 configs/ls1043aqds_lpuart_defconfig | 10 ++
 include/configs/ls1043aqds.h|  7 +
 6 files changed, 92 insertions(+)
 create mode 100644 arch/arm/dts/fsl-ls1043a-qds-lpuart.dts
 create mode 100644 configs/ls1043aqds_lpuart_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 302456c..a51275c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -97,6 +97,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
+   fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb
 
 dtb-$(CONFIG_MACH_SUN4I) += \
diff --git a/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts 
b/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts
new file mode 100644
index 000..18adb97
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1043a-qds.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi 
b/arch/arm/dts/fsl-ls1043a-qds.dtsi
index 6fa16b8..b9dad72 100644
--- a/arch/arm/dts/fsl-ls1043a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi
@@ -121,3 +121,7 @@
  {
status = "okay";
 };
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 85ea81e..12ea0ab 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -182,5 +182,59 @@
interrupts = <0 55 0x4>;
clocks = < 4 0>;
};
+
+   lpuart0: serial@295 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x295 0x0 0x1000>;
+   interrupts = <0 48 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart1: serial@296 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x296 0x0 0x1000>;
+   interrupts = <0 49 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart2: serial@297 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x297 0x0 0x1000>;
+   interrupts = <0 50 0x4>;
+   clock-names = "ipg";
+   clocks = <>;
+   status = "disabled";
+   };
+
+   lpuart3: serial@298 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x298 0x0 0x1000>;
+   interrupts = <0 51 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart4: serial@299 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x299 0x0 0x1000>;
+   interrupts = <0 52 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart5: serial@29a {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x29a 0x0 0x1000>;
+   interrupts = <0 53 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
};
 };
diff --git a/configs/ls1043aqds_lpuart_defconfig 
b/configs/ls1043aqds_lpuart_defconfig
new file mode 100644
index 000..21d6407
--- /dev/null
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -0,0 +1,10 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL

[U-Boot] [PATCH v3 2/3] armv8/ls1043aqds: Spilt off board device tree

[Wenbin Song]

Move new /chosen node out of the board device tree.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
 arch/arm/dts/Makefile|  2 +-
 arch/arm/dts/fsl-ls1043a-qds-duart.dts   | 16 
 .../dts/{fsl-ls1043a-qds.dts => fsl-ls1043a-qds.dtsi}|  1 -
 configs/ls1043aqds_defconfig |  2 +-
 4 files changed, 18 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/dts/fsl-ls1043a-qds-duart.dts
 rename arch/arm/dts/{fsl-ls1043a-qds.dts => fsl-ls1043a-qds.dtsi} (99%)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7706b41..302456c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -96,7 +96,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb
-dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds.dtb \
+dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-rdb.dtb
 
 dtb-$(CONFIG_MACH_SUN4I) += \
diff --git a/arch/arm/dts/fsl-ls1043a-qds-duart.dts 
b/arch/arm/dts/fsl-ls1043a-qds-duart.dts
new file mode 100644
index 000..2124e38
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1043a-qds-duart.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1043a-qds.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dts 
b/arch/arm/dts/fsl-ls1043a-qds.dtsi
similarity index 99%
rename from arch/arm/dts/fsl-ls1043a-qds.dts
rename to arch/arm/dts/fsl-ls1043a-qds.dtsi
index 7435222..6fa16b8 100644
--- a/arch/arm/dts/fsl-ls1043a-qds.dts
+++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi
@@ -10,7 +10,6 @@
  * warranty of any kind, whether express or implied.
  */
 
-/dts-v1/;
 /include/ "fsl-ls1043a.dtsi"
 
 / {
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index 60fb0ad..1fd530d 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -2,5 +2,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043AQDS=y
 CONFIG_SYS_NS16550=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_OF_CONTROL=y
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v4 3/3] armv8/ls1043aqds: Add lpuart support

[Wenbin Song]

Add lpuart support using the driver model.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
Changes in v4:
- No change
---
 arch/arm/dts/Makefile   |  1 +
 arch/arm/dts/fsl-ls1043a-qds-lpuart.dts | 16 ++
 arch/arm/dts/fsl-ls1043a-qds.dtsi   |  4 +++
 arch/arm/dts/fsl-ls1043a.dtsi   | 54 +
 configs/ls1043aqds_lpuart_defconfig | 10 ++
 include/configs/ls1043aqds.h|  5 +++
 6 files changed, 90 insertions(+)
 create mode 100644 arch/arm/dts/fsl-ls1043a-qds-lpuart.dts
 create mode 100644 configs/ls1043aqds_lpuart_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 302456c..a51275c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -97,6 +97,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
+   fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb
 
 dtb-$(CONFIG_MACH_SUN4I) += \
diff --git a/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts 
b/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts
new file mode 100644
index 000..18adb97
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1043a-qds.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi 
b/arch/arm/dts/fsl-ls1043a-qds.dtsi
index 6fa16b8..b9dad72 100644
--- a/arch/arm/dts/fsl-ls1043a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi
@@ -121,3 +121,7 @@
  {
status = "okay";
 };
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 85ea81e..12ea0ab 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -182,5 +182,59 @@
interrupts = <0 55 0x4>;
clocks = < 4 0>;
};
+
+   lpuart0: serial@295 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x295 0x0 0x1000>;
+   interrupts = <0 48 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart1: serial@296 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x296 0x0 0x1000>;
+   interrupts = <0 49 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart2: serial@297 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x297 0x0 0x1000>;
+   interrupts = <0 50 0x4>;
+   clock-names = "ipg";
+   clocks = <>;
+   status = "disabled";
+   };
+
+   lpuart3: serial@298 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x298 0x0 0x1000>;
+   interrupts = <0 51 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart4: serial@299 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x299 0x0 0x1000>;
+   interrupts = <0 52 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart5: serial@29a {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x29a 0x0 0x1000>;
+   interrupts = <0 53 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
};
 };
diff --git a/configs/ls1043aqds_lpuart_defconfig 
b/configs/ls1043aqds_lpuart_defconfig
new file mode 100644
index 000..21d6407
--- /dev/null
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -0,0 +1,10 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart"
+CONFIG_SYS_EXTR

[U-Boot] [PATCH v4 2/3] armv8/ls1043aqds: Spilt off board device tree

[Wenbin Song]

Move new /chosen node out of the board device tree.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
Changes in v4:
- No change
---
 arch/arm/dts/Makefile|  2 +-
 arch/arm/dts/fsl-ls1043a-qds-duart.dts   | 16 
 .../dts/{fsl-ls1043a-qds.dts => fsl-ls1043a-qds.dtsi}|  1 -
 configs/ls1043aqds_defconfig |  2 +-
 4 files changed, 18 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/dts/fsl-ls1043a-qds-duart.dts
 rename arch/arm/dts/{fsl-ls1043a-qds.dts => fsl-ls1043a-qds.dtsi} (99%)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7706b41..302456c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -96,7 +96,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb
-dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds.dtb \
+dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-rdb.dtb
 
 dtb-$(CONFIG_MACH_SUN4I) += \
diff --git a/arch/arm/dts/fsl-ls1043a-qds-duart.dts 
b/arch/arm/dts/fsl-ls1043a-qds-duart.dts
new file mode 100644
index 000..2124e38
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1043a-qds-duart.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1043a-qds.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dts 
b/arch/arm/dts/fsl-ls1043a-qds.dtsi
similarity index 99%
rename from arch/arm/dts/fsl-ls1043a-qds.dts
rename to arch/arm/dts/fsl-ls1043a-qds.dtsi
index 7435222..6fa16b8 100644
--- a/arch/arm/dts/fsl-ls1043a-qds.dts
+++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi
@@ -10,7 +10,6 @@
  * warranty of any kind, whether express or implied.
  */
 
-/dts-v1/;
 /include/ "fsl-ls1043a.dtsi"
 
 / {
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index 60fb0ad..1fd530d 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -2,5 +2,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043AQDS=y
 CONFIG_SYS_NS16550=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_OF_CONTROL=y
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v4 1/3] armv8/ls1043aqds: Select lpuart pins of various muxes

[Wenbin Song]

From: Shaohui Xie 

Set Board Configuration Register to select the lpuart pins of various
muxes.

Signed-off-by: Shaohui Xie 
Signed-off-by: Mingkai Hu 
---
Changes in v4:
- remove the blank line and ending period
- modify the suffix of lpuart to 0 on the comment 
---
 board/freescale/ls1043aqds/ls1043aqds.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c 
b/board/freescale/ls1043aqds/ls1043aqds.c
index d6696ca..080d5b5 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -40,6 +40,9 @@ enum {
 #define CFG_SD_MUX3_MUX4   0x1 /* MUX4 */
 #define CFG_SD_MUX4_SLOT3  0x0 /* SLOT3 TX/RX1 */
 #define CFG_SD_MUX4_SLOT1  0x1 /* SLOT1 TX/RX3 */
+#define CFG_UART_MUX_MASK  0x6
+#define CFG_UART_MUX_SHIFT 1
+#define CFG_LPUART_EN  0x1
 
 int checkboard(void)
 {
@@ -218,7 +221,17 @@ void board_retimer_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_LPUART
+   u8 uart;
+#endif
fsl_lsch2_early_init_f();
+#ifdef CONFIG_LPUART
+   /* We use lpuart0 as system console */
+   uart = QIXIS_READ(brdcfg[14]);
+   uart &= ~CFG_UART_MUX_MASK;
+   uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
+   QIXIS_WRITE(brdcfg[14], uart);
+#endif
 
return 0;
 }
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 3/3] armv8/ls1043aqds: Add lpuart support

[Wenbin Song]

Hi: all,

This patch depends on the series 
patches(http://patchwork.ozlabs.org/patch/567250/).


Regards

Wenbin Song

-Original Message-
From: Wenbin Song [mailto:wenbin.s...@nxp.com] 
Sent: Wednesday, January 20, 2016 8:26 PM
To: york...@freescale.com; Mingkai Hu <mingkai...@nxp.com>; Qianyu Gong 
<qianyu.g...@nxp.com>; Shaohui Xie <shaohui@nxp.com>; Wenbin Song 
<wenbin.s...@nxp.com>; u-boot@lists.denx.de; bmeng...@gmail.com
Subject: [PATCH v2 3/3] armv8/ls1043aqds: Add lpuart support

Add lpuart support using the driver model.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
 arch/arm/dts/Makefile   |  1 +
 arch/arm/dts/fsl-ls1043a-qds-lpuart.dts | 20 
 arch/arm/dts/fsl-ls1043a.dtsi   | 54 +
 configs/ls1043aqds_lpuart_defconfig | 10 ++
 include/configs/ls1043aqds.h|  7 +
 5 files changed, 92 insertions(+)
 create mode 100644 arch/arm/dts/fsl-ls1043a-qds-lpuart.dts
 create mode 100644 configs/ls1043aqds_lpuart_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 
302456c..a51275c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -97,6 +97,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
+   fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb
 
 dtb-$(CONFIG_MACH_SUN4I) += \
diff --git a/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts 
b/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts
new file mode 100644
index 000..24168ad
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts
@@ -0,0 +1,20 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * Wenbin Song <wenbin.s...@nxp.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "fsl-ls1043a-qds.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi 
index 85ea81e..12ea0ab 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -182,5 +182,59 @@
interrupts = <0 55 0x4>;
clocks = < 4 0>;
};
+
+   lpuart0: serial@295 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x295 0x0 0x1000>;
+   interrupts = <0 48 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart1: serial@296 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x296 0x0 0x1000>;
+   interrupts = <0 49 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart2: serial@297 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x297 0x0 0x1000>;
+   interrupts = <0 50 0x4>;
+   clock-names = "ipg";
+   clocks = <>;
+   status = "disabled";
+   };
+
+   lpuart3: serial@298 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x298 0x0 0x1000>;
+   interrupts = <0 51 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart4: serial@299 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x299 0x0 0x1000>;
+   interrupts = <0 52 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart5: serial@29a {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x29a 0x0 0x1000>;
+   interrupts = <0 53 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
 

Re: [U-Boot] [PATCH v2 2/3] armv8/ls1043aqds: Spilt off board device tree

[Wenbin Song]

Hi: all,

This patch depends on the series 
patches(http://patchwork.ozlabs.org/patch/567250/).


Regards

Wenbin Song

-Original Message-
From: Wenbin Song [mailto:wenbin.s...@nxp.com] 
Sent: Wednesday, January 20, 2016 8:26 PM
To: york...@freescale.com; Mingkai Hu <mingkai...@nxp.com>; Qianyu Gong 
<qianyu.g...@nxp.com>; Shaohui Xie <shaohui@nxp.com>; Wenbin Song 
<wenbin.s...@nxp.com>; u-boot@lists.denx.de; bmeng...@gmail.com
Subject: [PATCH v2 2/3] armv8/ls1043aqds: Spilt off board device tree

Move new /chosen node out of the board device tree.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
 arch/arm/dts/Makefile  |   2 +-
 arch/arm/dts/fsl-ls1043a-qds-duart.dts |  20 ++
 arch/arm/dts/fsl-ls1043a-qds.dts   | 124 -
 arch/arm/dts/fsl-ls1043a-qds.dtsi  | 123 
 configs/ls1043aqds_defconfig   |   2 +-
 5 files changed, 145 insertions(+), 126 deletions(-)  create mode 100644 
arch/arm/dts/fsl-ls1043a-qds-duart.dts
 delete mode 100644 arch/arm/dts/fsl-ls1043a-qds.dts  create mode 100644 
arch/arm/dts/fsl-ls1043a-qds.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 
7706b41..302456c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -96,7 +96,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb
-dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds.dtb \
+dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-rdb.dtb
 
 dtb-$(CONFIG_MACH_SUN4I) += \
diff --git a/arch/arm/dts/fsl-ls1043a-qds-duart.dts 
b/arch/arm/dts/fsl-ls1043a-qds-duart.dts
new file mode 100644
index 000..2715b3d
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1043a-qds-duart.dts
@@ -0,0 +1,20 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * Wenbin Song <wenbin.s...@nxp.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "fsl-ls1043a-qds.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dts b/arch/arm/dts/fsl-ls1043a-qds.dts
deleted file mode 100644
index 7435222..000
--- a/arch/arm/dts/fsl-ls1043a-qds.dts
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Device Tree Include file for Freescale Layerscape-1043A family SoC.
- *
- * Copyright (C) 2015, Freescale Semiconductor
- *
- * Mingkai Hu <mingkai...@freescale.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-/dts-v1/;
-/include/ "fsl-ls1043a.dtsi"
-
-/ {
-   model = "LS1043A QDS Board";
-};
-
- {
-   status = "okay";
-   pca9547@77 {
-   compatible = "philips,pca9547";
-   reg = <0x77>;
-   #address-cells = <1>;
-   #size-cells = <0>;
-
-   i2c@0 {
-   #address-cells = <1>;
-   #size-cells = <0>;
-   reg = <0x0>;
-
-   rtc@68 {
-   compatible = "dallas,ds3232";
-   reg = <0x68>;
-   /* IRQ10_B */
-   interrupts = <0 150 0x4>;
-   };
-   };
-
-   i2c@2 {
-   #address-cells = <1>;
-   #size-cells = <0>;
-   reg = <0x2>;
-
-   ina220@40 {
-   compatible = "ti,ina220";
-   reg = <0x40>;
-   shunt-resistor = <1000>;
-   };
-
-   ina220@41 {
-   compatible = "ti,ina220";
-   reg = <0x41>;
-   shunt-resistor = <1000>;
-   };
-   };
-
-   i2c@3 {
-   #address-cells = <1>;
-   #size-cells = <0>;
-   reg = <0x3>;
-
-   eeprom@56 {
-   compatible = "at24,24c512";
-   reg = <0x56>;
-   };
-
-   eeprom@57 {
-  

Re: [U-Boot] [PATCH v2 1/3] armv8/ls1043aqds: Select lpuart pins of various muxes

[Wenbin Song]

Hi: all,

This patch depends on the series 
patches(http://patchwork.ozlabs.org/patch/567250/).


Regards

Wenbin Song



-Original Message-
From: Wenbin Song [mailto:wenbin.s...@nxp.com] 
Sent: Wednesday, January 20, 2016 8:26 PM
To: york...@freescale.com; Mingkai Hu <mingkai...@nxp.com>; Qianyu Gong 
<qianyu.g...@nxp.com>; Shaohui Xie <shaohui@nxp.com>; Wenbin Song 
<wenbin.s...@nxp.com>; u-boot@lists.denx.de; bmeng...@gmail.com
Cc: Shaohui Xie <shaohui@freescale.com>; Mingkai Hu 
<mingkai...@freescale.com>
Subject: [PATCH v2 1/3] armv8/ls1043aqds: Select lpuart pins of various muxes

From: Shaohui Xie <shaohui@freescale.com>

Set Board Configuration Register to select the lpuart pins of various muxes.

Signed-off-by: Shaohui Xie <shaohui@freescale.com>
Signed-off-by: Mingkai Hu <mingkai...@freescale.com>
---
 board/freescale/ls1043aqds/ls1043aqds.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c 
b/board/freescale/ls1043aqds/ls1043aqds.c
index d6696ca..4e38cb0 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -40,6 +40,9 @@ enum {
 #define CFG_SD_MUX3_MUX4   0x1 /* MUX4 */
 #define CFG_SD_MUX4_SLOT3  0x0 /* SLOT3 TX/RX1 */
 #define CFG_SD_MUX4_SLOT1  0x1 /* SLOT1 TX/RX3 */
+#define CFG_UART_MUX_MASK  0x6
+#define CFG_UART_MUX_SHIFT 1
+#define CFG_LPUART_EN  0x1
 
 int checkboard(void)
 {
@@ -218,7 +221,19 @@ void board_retimer_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_LPUART
+   u8 uart;
+#endif
fsl_lsch2_early_init_f();
+#ifdef CONFIG_LPUART
+   /*
+* we use lpuart1 as system console.
+*/
+   uart = QIXIS_READ(brdcfg[14]);
+   uart &= ~CFG_UART_MUX_MASK;
+   uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
+   QIXIS_WRITE(brdcfg[14], uart);
+#endif
 
return 0;
 }
--
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] (no subject)

[Wenbin Song]

These patches depend on the series 
patches(http://patchwork.ozlabs.org/patch/567250/). 
 
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 2/3] armv8/ls1043aqds: Spilt off board device tree

[Wenbin Song]

Move new /chosen node out of the board device tree.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
 arch/arm/dts/Makefile  |   2 +-
 arch/arm/dts/fsl-ls1043a-qds-duart.dts |  20 ++
 arch/arm/dts/fsl-ls1043a-qds.dts   | 124 -
 arch/arm/dts/fsl-ls1043a-qds.dtsi  | 123 
 configs/ls1043aqds_defconfig   |   2 +-
 5 files changed, 145 insertions(+), 126 deletions(-)
 create mode 100644 arch/arm/dts/fsl-ls1043a-qds-duart.dts
 delete mode 100644 arch/arm/dts/fsl-ls1043a-qds.dts
 create mode 100644 arch/arm/dts/fsl-ls1043a-qds.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7706b41..302456c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -96,7 +96,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb
-dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds.dtb \
+dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-rdb.dtb
 
 dtb-$(CONFIG_MACH_SUN4I) += \
diff --git a/arch/arm/dts/fsl-ls1043a-qds-duart.dts 
b/arch/arm/dts/fsl-ls1043a-qds-duart.dts
new file mode 100644
index 000..2715b3d
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1043a-qds-duart.dts
@@ -0,0 +1,20 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * Wenbin Song <wenbin.s...@nxp.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "fsl-ls1043a-qds.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dts b/arch/arm/dts/fsl-ls1043a-qds.dts
deleted file mode 100644
index 7435222..000
--- a/arch/arm/dts/fsl-ls1043a-qds.dts
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Device Tree Include file for Freescale Layerscape-1043A family SoC.
- *
- * Copyright (C) 2015, Freescale Semiconductor
- *
- * Mingkai Hu <mingkai...@freescale.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-/dts-v1/;
-/include/ "fsl-ls1043a.dtsi"
-
-/ {
-   model = "LS1043A QDS Board";
-};
-
- {
-   status = "okay";
-   pca9547@77 {
-   compatible = "philips,pca9547";
-   reg = <0x77>;
-   #address-cells = <1>;
-   #size-cells = <0>;
-
-   i2c@0 {
-   #address-cells = <1>;
-   #size-cells = <0>;
-   reg = <0x0>;
-
-   rtc@68 {
-   compatible = "dallas,ds3232";
-   reg = <0x68>;
-   /* IRQ10_B */
-   interrupts = <0 150 0x4>;
-   };
-   };
-
-   i2c@2 {
-   #address-cells = <1>;
-   #size-cells = <0>;
-   reg = <0x2>;
-
-   ina220@40 {
-   compatible = "ti,ina220";
-   reg = <0x40>;
-   shunt-resistor = <1000>;
-   };
-
-   ina220@41 {
-   compatible = "ti,ina220";
-   reg = <0x41>;
-   shunt-resistor = <1000>;
-   };
-   };
-
-   i2c@3 {
-   #address-cells = <1>;
-   #size-cells = <0>;
-   reg = <0x3>;
-
-   eeprom@56 {
-   compatible = "at24,24c512";
-   reg = <0x56>;
-   };
-
-   eeprom@57 {
-   compatible = "at24,24c512";
-   reg = <0x57>;
-   };
-
-   adt7461a@4c {
-   compatible = "adt7461a";
-   reg = <0x4c>;
-   };
-   };
-   };
-};
-
- {
-   #address-cells = <2>;
-   #size-cells = <1>;
-   /* NOR, NAND Flashes and FPGA on board */
-   ranges = <0x0 0x0 0x0 0x6000 0x0800
- 0x2 0x0 0x0 0x7e80 0x0001

[U-Boot] [PATCH v2 1/3] armv8/ls1043aqds: Select lpuart pins of various muxes

[Wenbin Song]

From: Shaohui Xie 

Set Board Configuration Register to select the lpuart pins of various
muxes.

Signed-off-by: Shaohui Xie 
Signed-off-by: Mingkai Hu 
---
 board/freescale/ls1043aqds/ls1043aqds.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c 
b/board/freescale/ls1043aqds/ls1043aqds.c
index d6696ca..4e38cb0 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -40,6 +40,9 @@ enum {
 #define CFG_SD_MUX3_MUX4   0x1 /* MUX4 */
 #define CFG_SD_MUX4_SLOT3  0x0 /* SLOT3 TX/RX1 */
 #define CFG_SD_MUX4_SLOT1  0x1 /* SLOT1 TX/RX3 */
+#define CFG_UART_MUX_MASK  0x6
+#define CFG_UART_MUX_SHIFT 1
+#define CFG_LPUART_EN  0x1
 
 int checkboard(void)
 {
@@ -218,7 +221,19 @@ void board_retimer_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_LPUART
+   u8 uart;
+#endif
fsl_lsch2_early_init_f();
+#ifdef CONFIG_LPUART
+   /*
+* we use lpuart1 as system console.
+*/
+   uart = QIXIS_READ(brdcfg[14]);
+   uart &= ~CFG_UART_MUX_MASK;
+   uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
+   QIXIS_WRITE(brdcfg[14], uart);
+#endif
 
return 0;
 }
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 3/3] armv8/ls1043aqds: Add lpuart support

[Wenbin Song]

Add lpuart support using the driver model.

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
 arch/arm/dts/Makefile   |  1 +
 arch/arm/dts/fsl-ls1043a-qds-lpuart.dts | 20 
 arch/arm/dts/fsl-ls1043a.dtsi   | 54 +
 configs/ls1043aqds_lpuart_defconfig | 10 ++
 include/configs/ls1043aqds.h|  7 +
 5 files changed, 92 insertions(+)
 create mode 100644 arch/arm/dts/fsl-ls1043a-qds-lpuart.dts
 create mode 100644 configs/ls1043aqds_lpuart_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 302456c..a51275c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -97,6 +97,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
+   fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb
 
 dtb-$(CONFIG_MACH_SUN4I) += \
diff --git a/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts 
b/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts
new file mode 100644
index 000..24168ad
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts
@@ -0,0 +1,20 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * Wenbin Song <wenbin.s...@nxp.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "fsl-ls1043a-qds.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 85ea81e..12ea0ab 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -182,5 +182,59 @@
interrupts = <0 55 0x4>;
clocks = < 4 0>;
};
+
+   lpuart0: serial@295 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x295 0x0 0x1000>;
+   interrupts = <0 48 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart1: serial@296 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x296 0x0 0x1000>;
+   interrupts = <0 49 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart2: serial@297 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x297 0x0 0x1000>;
+   interrupts = <0 50 0x4>;
+   clock-names = "ipg";
+   clocks = <>;
+   status = "disabled";
+   };
+
+   lpuart3: serial@298 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x298 0x0 0x1000>;
+   interrupts = <0 51 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart4: serial@299 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x299 0x0 0x1000>;
+   interrupts = <0 52 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart5: serial@29a {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x29a 0x0 0x1000>;
+   interrupts = <0 53 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
};
 };
diff --git a/configs/ls1043aqds_lpuart_defconfig 
b/configs/ls1043aqds_lpuart_defconfig
new file mode 100644
index 000..2d6bb7b
--- /dev/null
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -0,0 +1,10 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_LPUART=y
+CONFIG_DM_SERIAL=y
diff --git a/include/conf

Re: [U-Boot] [PATCH 2/4] armv8/ls1043aqds: Add lpuart defconfig

[Wenbin Song]

Hi: Bin,

Could you tell me which  tree your patches have been merged into ? 

Regards

Wenbin Song



-Original Message-
From: Bin Meng [mailto:bmeng...@gmail.com] 
Sent: Tuesday, January 19, 2016 4:03 PM
To: Wenbin Song <wenbin.s...@nxp.com>
Cc: York Sun <york...@freescale.com>; Mingkai Hu <mingkai...@nxp.com>; Qianyu 
Gong <qianyu.g...@nxp.com>; Shaohui Xie <shaohui@nxp.com>; U-Boot Mailing 
List <u-boot@lists.denx.de>
Subject: Re: [U-Boot] [PATCH 2/4] armv8/ls1043aqds: Add lpuart defconfig

Hi Wenbin,

On Tue, Jan 19, 2016 at 2:48 PM, Wenbin Song <wenbin.s...@nxp.com> wrote:
> ---

Please include a commit message and SoB here.

>  configs/ls1043aqds_lpuart_defconfig | 8 
>  1 file changed, 8 insertions(+)
>  create mode 100644 configs/ls1043aqds_lpuart_defconfig
>
> diff --git a/configs/ls1043aqds_lpuart_defconfig 
> b/configs/ls1043aqds_lpuart_defconfig
> new file mode 100644
> index 000..ca06abe
> --- /dev/null
> +++ b/configs/ls1043aqds_lpuart_defconfig
> @@ -0,0 +1,8 @@
> +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
> +CONFIG_ARM=y
> +CONFIG_TARGET_LS1043AQDS=y
> +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
> +CONFIG_OF_CONTROL=y
> +CONFIG_DM=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_DM_SPI=y
> --

Please use the driver model LPUART driver in this series 
(http://patchwork.ozlabs.org/patch/567250/).

Regards,
Bin
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 4/4] armv8/ls1043aqds: Initizlize NS16550 if enalbed LPUART

[Wenbin Song]

Hi: Bin,
  Because we use the ns16550  as the early console when booting  kernel , 
and the earlycon driver on kernel  cannot initialize port->uartclk rightly, So 
if we want to use it, we must initialize ns16550 on uboot, and use the bootargs 
 as follow :
  "console=ttyS0,115200 root=/dev/ram0  earlycon=uart8250,0x21c0500 "  

int __init early_serial8250_setup(struct earlycon_device *device,
 const char *options)
{
if (!(device->port.membase || device->port.iobase))
return -ENODEV;

if (!device->baud) {
struct uart_port *port = >port;
unsigned int ier;

/* assume the device was initialized, only mask interrupts */
ier = serial8250_early_in(port, UART_IER);
serial8250_early_out(port, UART_IER, ier & UART_IER_UUE);
} else
init_port(device);

device->con->write = early_serial8250_write;
    return 0;
}

Regards

Wenbin Song


-Original Message-
From: Bin Meng [mailto:bmeng...@gmail.com] 
Sent: Tuesday, January 19, 2016 4:08 PM
To: Wenbin Song <wenbin.s...@nxp.com>
Cc: York Sun <york...@freescale.com>; Mingkai Hu <mingkai...@nxp.com>; Qianyu 
Gong <qianyu.g...@nxp.com>; Shaohui Xie <shaohui@nxp.com>; U-Boot Mailing 
List <u-boot@lists.denx.de>; Wenbin Song <wenbin.s...@freescale.com>
Subject: Re: [U-Boot] [PATCH 4/4] armv8/ls1043aqds: Initizlize NS16550 if 
enalbed LPUART

Hi Wenbin,

On Tue, Jan 19, 2016 at 2:48 PM, Wenbin Song <wenbin.s...@nxp.com> wrote:
> From: Wenbin Song <wenbin.s...@freescale.com>
>
> Need to initialize ns16550 to support earlycon on kernel.
>
> Signed-off-by: Wenbin Song <wenbin.s...@freescale.com>
> Signed-off-by: Mingkai Hu <mingkai...@freescale.com>
> ---
>  board/freescale/ls1043aqds/ls1043aqds.c | 12 
>  configs/ls1043aqds_lpuart_defconfig |  1 +
>  include/configs/ls1043aqds.h|  3 ++-
>  3 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/board/freescale/ls1043aqds/ls1043aqds.c 
> b/board/freescale/ls1043aqds/ls1043aqds.c
> index 1da3fe1..fcbd95c 100644
> --- a/board/freescale/ls1043aqds/ls1043aqds.c
> +++ b/board/freescale/ls1043aqds/ls1043aqds.c
> @@ -21,6 +21,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>
>  #include "../common/qixis.h"
>  #include "ls1043aqds_qixis.h"
> @@ -219,6 +220,17 @@ void board_retimer_init(void)
> i2c_write(I2C_RETIMER_ADDR, 0x64, 1, , 1);  }
>
> +int board_early_init_r(void)
> +{
> +#ifdef CONFIG_LPUART
> +/* Initialize ns16500 for earlycon on kernel.*/
> +   NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
> +DIV_ROUND_CLOSEST(CONFIG_SYS_NS16550_CLK,
> +  16 * CONFIG_BAUDRATE)); #endif

This change does not make a lot sense to me. Since U-Boot is using LPUART as 
its system console, why do you want to load a kernel that uses the NS16550 as 
the system console? IMHO we should ask kernel to use LPUART as well, IOW keep 
in sync with the underlying bootloader.

> +   return 0;
> +}
> +
>  int board_early_init_f(void)
>  {
>  #ifdef CONFIG_LPUART
> diff --git a/configs/ls1043aqds_lpuart_defconfig 
> b/configs/ls1043aqds_lpuart_defconfig
> index ca06abe..26f7b36 100644
> --- a/configs/ls1043aqds_lpuart_defconfig
> +++ b/configs/ls1043aqds_lpuart_defconfig
> @@ -1,6 +1,7 @@
>  CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
>  CONFIG_ARM=y
>  CONFIG_TARGET_LS1043AQDS=y
> +CONFIG_SYS_NS16550=y
>  CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
>  CONFIG_OF_CONTROL=y
>  CONFIG_DM=y
> diff --git a/include/configs/ls1043aqds.h 
> b/include/configs/ls1043aqds.h index 88f4bc0..d66d8f9 100644
> --- a/include/configs/ls1043aqds.h
> +++ b/include/configs/ls1043aqds.h
> @@ -30,6 +30,8 @@ unsigned long get_board_ddr_clk(void);
>
>  #define CONFIG_LAYERSCAPE_NS_ACCESS
>
> +#define CONFIG_BOARD_EARLY_INIT_R
> +
>  #define CONFIG_DIMM_SLOTS_PER_CTLR 1
>  /* Physical Memory Map */
>  #define CONFIG_CHIP_SELECTS_PER_CTRL   4
> @@ -96,7 +98,6 @@ unsigned long get_board_ddr_clk(void);  #define 
> CONFIG_LPUART_32B_REG  #undef CONFIG_CONS_INDEX  #undef 
> CONFIG_SYS_NS16550_SERIAL -#undef CONFIG_SYS_NS16550_CLK  #endif
>
>  /* SATA */
> --

Regards,
Bin
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 4/4] armv8/ls1043aqds: Initizlize NS16550 if enalbed LPUART

[Wenbin Song]

Hi:Bin
Thanks for your advice! I realize that I can use the lpuart as earlycon on 
kernel . So I will remove this patch on next vesion.

Thanks 

Wenbin Song 

Sent from my iPhone

> On Jan 19, 2016, at 18:42, Bin Meng <bmeng...@gmail.com> wrote:
> 
> Hi Wenbin,
> 
>> On Tue, Jan 19, 2016 at 6:21 PM, Wenbin Song <wenbin.s...@nxp.com> wrote:
>> Hi: Bin,
>>  Because we use the ns16550  as the early console when booting  kernel , 
>> and the earlycon driver on kernel  cannot initialize port->uartclk rightly, 
>> So if we want to use it, we must initialize ns16550 on uboot, and use the 
>> bootargs  as follow :
>>  "console=ttyS0,115200 root=/dev/ram0  earlycon=uart8250,0x21c0500 "
> 
> I understand this. My question was: U-Boot was booted using LPUART as
> its serial console, why do you bother loading a kernel with another
> serial port as the early console?
> 
>> int __init early_serial8250_setup(struct earlycon_device *device,
>> const char *options)
>> {
>>if (!(device->port.membase || device->port.iobase))
>>return -ENODEV;
>> 
>>if (!device->baud) {
>>struct uart_port *port = >port;
>>unsigned int ier;
>> 
>>/* assume the device was initialized, only mask interrupts */
>>ier = serial8250_early_in(port, UART_IER);
>>serial8250_early_out(port, UART_IER, ier & UART_IER_UUE);
>>} else
>>init_port(device);
>> 
>>device->con->write = early_serial8250_write;
>>return 0;
>> }
> 
> [snip]
> 
> Regards,
> Bin
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 3/4] armv8/ls1043aqds: Fix CONFIG_LPUART

[Wenbin Song]

From: songwenbin <wenbin.s...@freescale.com>

If configured CONFIG_LPUART, should undefine the NS16550

Signed-off-by: Wenbin Song <wenbin.s...@nxp.com>
---
 include/configs/ls1043aqds.h | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 398f1c3..88f4bc0 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -88,6 +88,17 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FSL_PBL_RCW 
board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
 #endif
 
+/*
+ * LPUART
+ */
+#ifdef CONFIG_LPUART
+#define CONFIG_FSL_LPUART
+#define CONFIG_LPUART_32B_REG
+#undef CONFIG_CONS_INDEX
+#undef CONFIG_SYS_NS16550_SERIAL
+#undef CONFIG_SYS_NS16550_CLK
+#endif
+
 /* SATA */
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 4/4] armv8/ls1043aqds: Initizlize NS16550 if enalbed LPUART

[Wenbin Song]

From: Wenbin Song <wenbin.s...@freescale.com>

Need to initialize ns16550 to support earlycon on kernel.

Signed-off-by: Wenbin Song <wenbin.s...@freescale.com>
Signed-off-by: Mingkai Hu <mingkai...@freescale.com>
---
 board/freescale/ls1043aqds/ls1043aqds.c | 12 
 configs/ls1043aqds_lpuart_defconfig |  1 +
 include/configs/ls1043aqds.h|  3 ++-
 3 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c 
b/board/freescale/ls1043aqds/ls1043aqds.c
index 1da3fe1..fcbd95c 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -21,6 +21,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "../common/qixis.h"
 #include "ls1043aqds_qixis.h"
@@ -219,6 +220,17 @@ void board_retimer_init(void)
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, , 1);
 }
 
+int board_early_init_r(void)
+{
+#ifdef CONFIG_LPUART
+/* Initialize ns16500 for earlycon on kernel.*/
+   NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+DIV_ROUND_CLOSEST(CONFIG_SYS_NS16550_CLK,
+  16 * CONFIG_BAUDRATE));
+#endif
+   return 0;
+}
+
 int board_early_init_f(void)
 {
 #ifdef CONFIG_LPUART
diff --git a/configs/ls1043aqds_lpuart_defconfig 
b/configs/ls1043aqds_lpuart_defconfig
index ca06abe..26f7b36 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SYS_NS16550=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 88f4bc0..d66d8f9 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -30,6 +30,8 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_LAYERSCAPE_NS_ACCESS
 
+#define CONFIG_BOARD_EARLY_INIT_R
+
 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
 /* Physical Memory Map */
 #define CONFIG_CHIP_SELECTS_PER_CTRL   4
@@ -96,7 +98,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_LPUART_32B_REG
 #undef CONFIG_CONS_INDEX
 #undef CONFIG_SYS_NS16550_SERIAL
-#undef CONFIG_SYS_NS16550_CLK
 #endif
 
 /* SATA */
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 1/4] armv8/ls1043aqds: added lpuart support

[Wenbin Song]

From: Shaohui Xie 

Signed-off-by: Shaohui Xie 
Signed-off-by: Mingkai Hu 
---
 board/freescale/ls1043aqds/ls1043aqds.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c 
b/board/freescale/ls1043aqds/ls1043aqds.c
index d6696ca..1da3fe1 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -40,6 +40,9 @@ enum {
 #define CFG_SD_MUX3_MUX4   0x1 /* MUX4 */
 #define CFG_SD_MUX4_SLOT3  0x0 /* SLOT3 TX/RX1 */
 #define CFG_SD_MUX4_SLOT1  0x1 /* SLOT1 TX/RX3 */
+#define CFG_UART_MUX_MASK  0x6
+#define CFG_UART_MUX_SHIFT 1
+#define CFG_LPUART_EN  0x1
 
 int checkboard(void)
 {
@@ -218,7 +221,19 @@ void board_retimer_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_LPUART
+   u8 uart;
+#endif
fsl_lsch2_early_init_f();
+#ifdef CONFIG_LPUART
+   /*FIXME: need to check which lpuart is enabled in rcw, for now
+* we use lpuart1.
+*/
+   uart = QIXIS_READ(brdcfg[14]);
+   uart &= ~CFG_UART_MUX_MASK;
+   uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
+   QIXIS_WRITE(brdcfg[14], uart);
+#endif
 
return 0;
 }
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 2/4] armv8/ls1043aqds: Add lpuart defconfig

[Wenbin Song]

---
 configs/ls1043aqds_lpuart_defconfig | 8 
 1 file changed, 8 insertions(+)
 create mode 100644 configs/ls1043aqds_lpuart_defconfig

diff --git a/configs/ls1043aqds_lpuart_defconfig 
b/configs/ls1043aqds_lpuart_defconfig
new file mode 100644
index 000..ca06abe
--- /dev/null
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -0,0 +1,8 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot