RE: [v2, 3/3] armv8: layerscape: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
> -Original Message- > From: Michael Walle > Sent: 2021年6月2日 15:03 > To: Y.b. Lu > Cc: u-boot@lists.denx.de; Peng Fan ; Priyanka Jain > ; Shengzhou Liu ; Pramod > Kumar ; Rajesh Bhagat > ; Andy Tang ; Ashish Kumar > ; Meenakshi Aggarwal > > Subject: Re: [v2, 3/3] armv8: layerscape: drop > CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 > > Am 2021-06-02 06:19, schrieb Yangbo Lu: > > Drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33. > > CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT > > is used instead. > > > > Signed-off-by: Yangbo Lu > > --- > > > diff --git a/include/configs/kontron_sl28.h > > b/include/configs/kontron_sl28.h index 5f11205802..4e9ea9d7fe 100644 > > --- a/include/configs/kontron_sl28.h > > +++ b/include/configs/kontron_sl28.h > > @@ -1,4 +1,7 @@ > > /* SPDX-License-Identifier: GPL-2.0+ */ > > +/* > > + * Copyright 2021 NXP > > + */ > > NAK. Are you serious? Sorry. I just realized this was not nxp file among these files. Dropped it in v2. Thank you. > > > > > #ifndef __SL28_H > > #define __SL28_H > > @@ -56,11 +59,6 @@ > > #define CONFIG_DDR_CLK_FREQ1 > > #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) > > > > -/* MMC */ > > -#ifdef CONFIG_MMC > > -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 > > -#endif > > - > > /* ethernet */ > > #define CONFIG_SYS_RX_ETH_BUFFER 8 > > > > diff --git a/include/configs/ls1012a2g5rdb.h > > b/include/configs/ls1012a2g5rdb.h index 9962b9872a..1c016dee97 100644 > > --- a/include/configs/ls1012a2g5rdb.h > > +++ b/include/configs/ls1012a2g5rdb.h > > -michael
RE: [v2, 1/3] mmc: fsl_esdhc: convert to CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT
Hi Jaehoon,
> -Original Message-
> From: Jaehoon Chung
> Sent: 2021年6月2日 14:58
> To: Y.b. Lu ; u-boot@lists.denx.de; Peng Fan
>
> Cc: Priyanka Jain ; Shengzhou Liu
> ; Michael Walle ; Pramod
> Kumar ; Rajesh Bhagat
> ; Andy Tang ; Ashish Kumar
> ; Meenakshi Aggarwal
>
> Subject: Re: [v2, 1/3] mmc: fsl_esdhc: convert to
> CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT
>
> Hi,
>
> On 6/2/21 1:19 PM, Yangbo Lu wrote:
> > For eSDHC, power supply is through peripheral circuit. So, 3.3V power
> > supply capability from register bit does not reflect the truth. 3.3V
> > is common for SD/MMC, and is supported for all boards with eSDHC in
> > current u-boot. So, let's use a Kconfig
> > CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT making 3.3V is supported in
> default.
> >
> > This is also a fix-up for one previous patch, which converted to use
> > IS_ENABLED() for CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 that is not a
> > Kconfig option.
> >
> > Fixes: 52faec31827e ("mmc: fsl_esdhc: replace most #ifdefs by
> > IS_ENABLED()")
> > Signed-off-by: Yangbo Lu
> > ---
> > Changes for v2:
> > - Updated copyright.
> > ---
> > drivers/mmc/Kconfig | 7 +++
> > drivers/mmc/fsl_esdhc.c | 8 +---
> > 2 files changed, 12 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index
> > 8901456967..0909f502a1 100644
> > --- a/drivers/mmc/Kconfig
> > +++ b/drivers/mmc/Kconfig
> > @@ -798,6 +798,13 @@ config
> FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
> > This option assumes no hotplug, and u-boot has to make all the way to
> > to linux to use 1.8v UHS-I speed mode if has card.
> >
> > +config FSL_ESDHC_VS33_NOT_SUPPORT
> > + bool "3.3V power supply not supported"
> > + depends on FSL_ESDHC
> > + help
> > + For eSDHC, power supply is through peripheral circuit. 3.3V support is
> > + common. Select this if 3.3V power supply not supported.
> > +
> > config FSL_ESDHC_IMX
> > bool "Freescale/NXP i.MX eSDHC controller support"
> > help
> > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index
> > 7501fdb71e..b3c71c8695 100644
> > --- a/drivers/mmc/fsl_esdhc.c
> > +++ b/drivers/mmc/fsl_esdhc.c
> > @@ -1,7 +1,7 @@
> > // SPDX-License-Identifier: GPL-2.0+
> > /*
> > * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
> > - * Copyright 2019-2020 NXP
> > + * Copyright 2019-2021 NXP
> > * Andy Fleming
> > *
> > * Based vaguely on the pxa mmc code:
> > @@ -795,10 +795,12 @@ static void fsl_esdhc_get_cfg_common(struct
> fsl_esdhc_priv *priv,
> > u32 caps;
> >
> > caps = esdhc_read32(>hostcapblt);
> > +
> > + if (!IS_ENABLED(CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT))
> > + caps |= HOSTCAPBLT_VS33;
> > +
>
> If 3.3V is supported by default, how about below code?
>
> caps |= HOSTCAPBLT_VS33;
> if (IS_ENABLED(CONFIG_xxx_NOT_SUPPORT))
> caps &= ~HOSTCAPBLT_VS33;
You are right. I should have used such logic...
Thanks. Updated in v2.
>
> I don't know exactly about hostcapblt register.
> If possible to read wrong capability value from regsiter, I think that it's
> better.
> Just my opinion.
>
> Best Regards,
> Jaehoon Chung
>
> > if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135))
> > caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 |
> HOSTCAPBLT_VS30);
> > - if (IS_ENABLED(CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33))
> > - caps |= HOSTCAPBLT_VS33;
> > if (caps & HOSTCAPBLT_VS18)
> > cfg->voltages |= MMC_VDD_165_195;
> > if (caps & HOSTCAPBLT_VS30)
> >
RE: [PATCH] arm: dts: lx2162aqds: support eMMC HS400 mode on esdhc1
May I know the status of the patch?
Thanks.
> -Original Message-
> From: Y.b. Lu
> Sent: 2021年5月14日 10:25
> To: Priyanka Jain ; Meenakshi Aggarwal
>
> Cc: u-boot@lists.denx.de
> Subject: RE: [PATCH] arm: dts: lx2162aqds: support eMMC HS400 mode on
> esdhc1
>
> Sent out v2 to update copyright.
> Any comments on v2.
>
> Thank you.
>
> > -Original Message-
> > From: Yangbo Lu
> > Sent: 2021年4月27日 16:28
> > To: u-boot@lists.denx.de; Priyanka Jain ;
> > Meenakshi Aggarwal
> > Cc: Y.b. Lu
> > Subject: [PATCH] arm: dts: lx2162aqds: support eMMC HS400 mode on
> > esdhc1
> >
> > Add properties related to eMMC HS400 mode for esdhc1.
> >
> > Signed-off-by: Yangbo Lu
> > ---
> > arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 6 ++
> > arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 6 ++
> > arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi | 6 ++
> > arch/arm/dts/fsl-lx2162a-qds.dts | 6 ++
> > 4 files changed, 24 insertions(+)
> >
> > diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
> > b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
> > index 60f5a4ee43..3b6fddba7c 100644
> > --- a/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
> > +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
> > @@ -56,3 +56,9 @@
> > reg = <0x3>;
> > };
> > };
> > +
> > + {
> > + mmc-hs200-1_8v;
> > + mmc-hs400-1_8v;
> > + bus-width = <8>;
> > +};
> > diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
> > b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
> > index 8e11b0680a..0f4329f587 100644
> > --- a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
> > +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
> > @@ -59,3 +59,9 @@
> > reg = <0x1>;
> > };
> > };
> > +
> > + {
> > + mmc-hs200-1_8v;
> > + mmc-hs400-1_8v;
> > + bus-width = <8>;
> > +};
> > diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
> > b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
> > index faf4285eab..8c856a19d4 100644
> > --- a/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
> > +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
> > @@ -24,3 +24,9 @@
> > reg = <0x0>;
> > };
> > };
> > +
> > + {
> > + mmc-hs200-1_8v;
> > + mmc-hs400-1_8v;
> > + bus-width = <8>;
> > +};
> > diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts
> > b/arch/arm/dts/fsl-lx2162a-qds.dts
> > index 341610ccf4..68cb328716 100644
> > --- a/arch/arm/dts/fsl-lx2162a-qds.dts
> > +++ b/arch/arm/dts/fsl-lx2162a-qds.dts
> > @@ -135,3 +135,9 @@
> > reg = <2>;
> > };
> > };
> > +
> > + {
> > + mmc-hs200-1_8v;
> > + mmc-hs400-1_8v;
> > + bus-width = <8>;
> > +};
> > --
> > 2.25.1
RE: [PATCH] armv8: layerscape: enable eMMC HS400 workarounds for LX2160A/LX2162A
May I know the status of the patch? Thanks. > -Original Message- > From: Y.b. Lu > Sent: 2021年5月14日 10:25 > To: Priyanka Jain ; Meenakshi Aggarwal > > Cc: u-boot@lists.denx.de > Subject: RE: [PATCH] armv8: layerscape: enable eMMC HS400 workarounds for > LX2160A/LX2162A > > Any comments. > Thanks! > > > -Original Message- > > From: Yangbo Lu > > Sent: 2021年4月27日 16:42 > > To: u-boot@lists.denx.de; Priyanka Jain ; > > Meenakshi Aggarwal > > Cc: Y.b. Lu > > Subject: [PATCH] armv8: layerscape: enable eMMC HS400 workarounds for > > LX2160A/LX2162A > > > > Enable eMMC HS400 workarounds for LX2160A/LX2162A. > > > > Signed-off-by: Yangbo Lu > > --- > > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 > > 1 file changed, 4 insertions(+) > > > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > > b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > > index 9d1ba4c771..395e5ccaad 100644 > > --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > > @@ -224,6 +224,8 @@ config ARCH_LX2162A > > select SYS_FSL_EC1 > > select SYS_FSL_EC2 > > select SYS_FSL_ERRATUM_A050106 > > + select SYS_FSL_ERRATUM_A011334 > > + select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND > > select SYS_FSL_HAS_RGMII > > select SYS_FSL_HAS_SEC > > select SYS_FSL_HAS_CCN508 > > @@ -254,6 +256,8 @@ config ARCH_LX2160A > > select SYS_FSL_EC1 > > select SYS_FSL_EC2 > > select SYS_FSL_ERRATUM_A050106 > > + select SYS_FSL_ERRATUM_A011334 > > + select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND > > select SYS_FSL_HAS_RGMII > > select SYS_FSL_HAS_SEC > > select SYS_FSL_HAS_CCN508 > > -- > > 2.25.1
RE: [PATCH] arm: dts: lx2162aqds: support eMMC HS400 mode on esdhc1
Sent out v2 to update copyright.
Any comments on v2.
Thank you.
> -Original Message-
> From: Yangbo Lu
> Sent: 2021年4月27日 16:28
> To: u-boot@lists.denx.de; Priyanka Jain ; Meenakshi
> Aggarwal
> Cc: Y.b. Lu
> Subject: [PATCH] arm: dts: lx2162aqds: support eMMC HS400 mode on esdhc1
>
> Add properties related to eMMC HS400 mode for esdhc1.
>
> Signed-off-by: Yangbo Lu
> ---
> arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 6 ++
> arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 6 ++
> arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi | 6 ++
> arch/arm/dts/fsl-lx2162a-qds.dts | 6 ++
> 4 files changed, 24 insertions(+)
>
> diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
> b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
> index 60f5a4ee43..3b6fddba7c 100644
> --- a/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
> +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
> @@ -56,3 +56,9 @@
> reg = <0x3>;
> };
> };
> +
> + {
> + mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + bus-width = <8>;
> +};
> diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
> b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
> index 8e11b0680a..0f4329f587 100644
> --- a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
> +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
> @@ -59,3 +59,9 @@
> reg = <0x1>;
> };
> };
> +
> + {
> + mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + bus-width = <8>;
> +};
> diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
> b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
> index faf4285eab..8c856a19d4 100644
> --- a/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
> +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
> @@ -24,3 +24,9 @@
> reg = <0x0>;
> };
> };
> +
> + {
> + mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + bus-width = <8>;
> +};
> diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts
> b/arch/arm/dts/fsl-lx2162a-qds.dts
> index 341610ccf4..68cb328716 100644
> --- a/arch/arm/dts/fsl-lx2162a-qds.dts
> +++ b/arch/arm/dts/fsl-lx2162a-qds.dts
> @@ -135,3 +135,9 @@
> reg = <2>;
> };
> };
> +
> + {
> + mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + bus-width = <8>;
> +};
> --
> 2.25.1
RE: [PATCH] armv8: layerscape: enable eMMC HS400 workarounds for LX2160A/LX2162A
Any comments. Thanks! > -Original Message- > From: Yangbo Lu > Sent: 2021年4月27日 16:42 > To: u-boot@lists.denx.de; Priyanka Jain ; Meenakshi > Aggarwal > Cc: Y.b. Lu > Subject: [PATCH] armv8: layerscape: enable eMMC HS400 workarounds for > LX2160A/LX2162A > > Enable eMMC HS400 workarounds for LX2160A/LX2162A. > > Signed-off-by: Yangbo Lu > --- > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > index 9d1ba4c771..395e5ccaad 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > @@ -224,6 +224,8 @@ config ARCH_LX2162A > select SYS_FSL_EC1 > select SYS_FSL_EC2 > select SYS_FSL_ERRATUM_A050106 > + select SYS_FSL_ERRATUM_A011334 > + select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND > select SYS_FSL_HAS_RGMII > select SYS_FSL_HAS_SEC > select SYS_FSL_HAS_CCN508 > @@ -254,6 +256,8 @@ config ARCH_LX2160A > select SYS_FSL_EC1 > select SYS_FSL_EC2 > select SYS_FSL_ERRATUM_A050106 > + select SYS_FSL_ERRATUM_A011334 > + select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND > select SYS_FSL_HAS_RGMII > select SYS_FSL_HAS_SEC > select SYS_FSL_HAS_CCN508 > -- > 2.25.1
RE: [PATCH 55/57] ppc: Remove T1023RDB board
Hi Tom, > -Original Message- > From: U-Boot On Behalf Of Tom Rini > Sent: Sunday, February 21, 2021 9:07 AM > To: u-boot@lists.denx.de > Cc: Priyanka Jain > Subject: [PATCH 55/57] ppc: Remove T1023RDB board > > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. As this is the last ARCH_T1023 platform, remove that support > as well. > > Cc: Priyanka Jain > Signed-off-by: Tom Rini > --- > arch/powerpc/cpu/mpc85xx/Kconfig| 38 +- > arch/powerpc/cpu/mpc85xx/Makefile | 2 - > arch/powerpc/cpu/mpc85xx/speed.c| 4 +- > arch/powerpc/include/asm/config_mpc85xx.h | 2 +- > arch/powerpc/include/asm/fsl_secure_boot.h | 1 - > arch/powerpc/include/asm/immap_85xx.h | 4 +- > board/freescale/t102xrdb/Kconfig| 14 - > board/freescale/t102xrdb/MAINTAINERS| 15 - > board/freescale/t102xrdb/Makefile | 17 - > board/freescale/t102xrdb/README | 340 -- > board/freescale/t102xrdb/cpld.c | 102 --- > board/freescale/t102xrdb/cpld.h | 48 -- > board/freescale/t102xrdb/ddr.c | 258 --- > board/freescale/t102xrdb/eth_t102xrdb.c | 149 > board/freescale/t102xrdb/law.c | 31 - > board/freescale/t102xrdb/pci.c | 25 - > board/freescale/t102xrdb/spl.c | 142 > board/freescale/t102xrdb/t1023_nand_rcw.cfg | 8 - > board/freescale/t102xrdb/t1023_sd_rcw.cfg | 8 - > board/freescale/t102xrdb/t1023_spi_rcw.cfg | 8 - > board/freescale/t102xrdb/t1024_nand_rcw.cfg | 8 - > board/freescale/t102xrdb/t1024_pbi.cfg | 26 - > board/freescale/t102xrdb/t1024_sd_rcw.cfg | 8 - > board/freescale/t102xrdb/t1024_spi_rcw.cfg | 8 - > board/freescale/t102xrdb/t102xrdb.c | 397 --- > board/freescale/t102xrdb/t102xrdb.h | 15 - > board/freescale/t102xrdb/tlb.c | 116 > configs/T1023RDB_NAND_defconfig | 80 --- > configs/T1023RDB_SDCARD_defconfig | 77 --- > configs/T1023RDB_SECURE_BOOT_defconfig | 67 -- > configs/T1023RDB_SPIFLASH_defconfig | 79 --- > configs/T1023RDB_defconfig | 64 -- > configs/T1024RDB_NAND_defconfig | 93 --- > configs/T1024RDB_SDCARD_defconfig | 90 --- > configs/T1024RDB_SECURE_BOOT_defconfig | 71 -- > configs/T1024RDB_SPIFLASH_defconfig | 92 --- > configs/T1024RDB_defconfig | 78 --- DM_MMC had already been in use for T1024RDB. The board is still in maintaining. Can we keep it? Thanks. > drivers/net/Kconfig | 1 - > drivers/net/fm/Makefile | 1 - > include/configs/T102xRDB.h | 709 > 40 files changed, 6 insertions(+), 3290 deletions(-) > delete mode 100644 board/freescale/t102xrdb/Kconfig > delete mode 100644 board/freescale/t102xrdb/MAINTAINERS > delete mode 100644 board/freescale/t102xrdb/Makefile > delete mode 100644 board/freescale/t102xrdb/README > delete mode 100644 board/freescale/t102xrdb/cpld.c > delete mode 100644 board/freescale/t102xrdb/cpld.h > delete mode 100644 board/freescale/t102xrdb/ddr.c > delete mode 100644 board/freescale/t102xrdb/eth_t102xrdb.c > delete mode 100644 board/freescale/t102xrdb/law.c > delete mode 100644 board/freescale/t102xrdb/pci.c > delete mode 100644 board/freescale/t102xrdb/spl.c > delete mode 100644 board/freescale/t102xrdb/t1023_nand_rcw.cfg > delete mode 100644 board/freescale/t102xrdb/t1023_sd_rcw.cfg > delete mode 100644 board/freescale/t102xrdb/t1023_spi_rcw.cfg > delete mode 100644 board/freescale/t102xrdb/t1024_nand_rcw.cfg > delete mode 100644 board/freescale/t102xrdb/t1024_pbi.cfg > delete mode 100644 board/freescale/t102xrdb/t1024_sd_rcw.cfg > delete mode 100644 board/freescale/t102xrdb/t1024_spi_rcw.cfg > delete mode 100644 board/freescale/t102xrdb/t102xrdb.c > delete mode 100644 board/freescale/t102xrdb/t102xrdb.h > delete mode 100644 board/freescale/t102xrdb/tlb.c > delete mode 100644 configs/T1023RDB_NAND_defconfig > delete mode 100644 configs/T1023RDB_SDCARD_defconfig > delete mode 100644 configs/T1023RDB_SECURE_BOOT_defconfig > delete mode 100644 configs/T1023RDB_SPIFLASH_defconfig > delete mode 100644 configs/T1023RDB_defconfig > delete mode 100644 configs/T1024RDB_NAND_defconfig > delete mode 100644 configs/T1024RDB_SDCARD_defconfig > delete mode 100644 configs/T1024RDB_SECURE_BOOT_defconfig > delete mode 100644 configs/T1024RDB_SPIFLASH_defconfig > delete mode 100644 configs/T1024RDB_defconfig > delete mode 100644 include/configs/T102xRDB.h > > diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig > b/arch/powerpc/cpu/mpc85xx/Kconfig > index 55cce515ccf0..42c4d1f0399e 100644 > --- a/arch/powerpc/cpu/mpc85xx/Kconfig > +++ b/arch/powerpc/cpu/mpc85xx/Kconfig > @@ -124,16 +124,6 @@ config TARGET_QEMU_PPCE500 > select ARCH_QEMU_E500 >
RE: [PATCH 56/57] ppc: Remove T4160RDB board
Hi Tom, > -Original Message- > From: U-Boot On Behalf Of Tom Rini > Sent: Sunday, February 21, 2021 9:07 AM > To: u-boot@lists.denx.de > Cc: Priyanka Jain > Subject: [PATCH 56/57] ppc: Remove T4160RDB board > > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. As this is the last ARCH_T1023 platform, remove that support > as well. > > Cc: Priyanka Jain > Signed-off-by: Tom Rini > --- > arch/powerpc/cpu/mpc85xx/Kconfig | 39 +- > arch/powerpc/cpu/mpc85xx/Makefile | 2 - > arch/powerpc/cpu/mpc85xx/fdt.c| 5 +- > .../powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 2 +- > arch/powerpc/cpu/mpc85xx/speed.c | 3 +- > arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 202 -- > arch/powerpc/include/asm/config_mpc85xx.h | 5 +- > arch/powerpc/include/asm/fsl_secure_boot.h| 1 - > arch/powerpc/include/asm/immap_85xx.h | 4 +- > board/freescale/t4rdb/Kconfig | 14 - > board/freescale/t4rdb/MAINTAINERS | 8 - > board/freescale/t4rdb/Makefile| 19 - > board/freescale/t4rdb/cpld.c | 129 > board/freescale/t4rdb/cpld.h | 48 -- > board/freescale/t4rdb/ddr.c | 128 > board/freescale/t4rdb/ddr.h | 77 -- > board/freescale/t4rdb/eth.c | 152 > board/freescale/t4rdb/law.c | 30 - > board/freescale/t4rdb/pci.c | 25 - > board/freescale/t4rdb/spl.c | 98 --- > board/freescale/t4rdb/t4240rdb.c | 153 > board/freescale/t4rdb/t4_pbi.cfg | 27 - > board/freescale/t4rdb/t4_sd_rcw.cfg | 7 - > board/freescale/t4rdb/t4rdb.h | 17 - > board/freescale/t4rdb/tlb.c | 123 > configs/T4160RDB_defconfig| 57 -- > configs/T4240RDB_SDCARD_defconfig | 78 -- > configs/T4240RDB_defconfig| 66 -- DM_MMC had already been in use for T4240RDB. The board is still in maintaining. Can we keep it? Thanks. > drivers/ddr/fsl/Kconfig | 3 +- > drivers/net/Kconfig | 1 - > drivers/net/fm/Makefile | 1 - > include/configs/T4240RDB.h| 667 -- > 32 files changed, 9 insertions(+), 2182 deletions(-) > delete mode 100644 board/freescale/t4rdb/Kconfig > delete mode 100644 board/freescale/t4rdb/MAINTAINERS > delete mode 100644 board/freescale/t4rdb/Makefile > delete mode 100644 board/freescale/t4rdb/cpld.c > delete mode 100644 board/freescale/t4rdb/cpld.h > delete mode 100644 board/freescale/t4rdb/ddr.c > delete mode 100644 board/freescale/t4rdb/ddr.h > delete mode 100644 board/freescale/t4rdb/eth.c > delete mode 100644 board/freescale/t4rdb/law.c > delete mode 100644 board/freescale/t4rdb/pci.c > delete mode 100644 board/freescale/t4rdb/spl.c > delete mode 100644 board/freescale/t4rdb/t4240rdb.c > delete mode 100644 board/freescale/t4rdb/t4_pbi.cfg > delete mode 100644 board/freescale/t4rdb/t4_sd_rcw.cfg > delete mode 100644 board/freescale/t4rdb/t4rdb.h > delete mode 100644 board/freescale/t4rdb/tlb.c > delete mode 100644 configs/T4160RDB_defconfig > delete mode 100644 configs/T4240RDB_SDCARD_defconfig > delete mode 100644 configs/T4240RDB_defconfig > delete mode 100644 include/configs/T4240RDB.h > > diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig > b/arch/powerpc/cpu/mpc85xx/Kconfig > index 42c4d1f0399e..143ddaec2e6a 100644 > --- a/arch/powerpc/cpu/mpc85xx/Kconfig > +++ b/arch/powerpc/cpu/mpc85xx/Kconfig > @@ -179,13 +179,6 @@ config TARGET_T2080RDB > imply CMD_SATA > imply PANIC_HANG > > -config TARGET_T4160RDB > - bool "Support T4160RDB" > - select ARCH_T4160 > - select SUPPORT_SPL > - select PHYS_64BIT > - imply PANIC_HANG > - > config TARGET_T4240RDB > bool "Support T4240RDB" > select ARCH_T4240 > @@ -810,31 +803,6 @@ config ARCH_T2080 > imply CMD_REGINFO > imply FSL_SATA > > -config ARCH_T4160 > - bool > - select E500MC > - select E6500 > - select FSL_LAW > - select SYS_FSL_DDR_VER_47 > - select SYS_FSL_ERRATUM_A004468 > - select SYS_FSL_ERRATUM_A005871 > - select SYS_FSL_ERRATUM_A006379 > - select SYS_FSL_ERRATUM_A006593 > - select SYS_FSL_ERRATUM_A007186 > - select SYS_FSL_ERRATUM_A007798 > - select SYS_FSL_ERRATUM_A009942 > - select SYS_FSL_HAS_DDR3 > - select SYS_FSL_HAS_SEC > - select SYS_FSL_QORIQ_CHASSIS2 > - select SYS_FSL_SEC_BE > - select SYS_FSL_SEC_COMPAT_4 > - select SYS_PPC64 > - select FSL_IFC > - imply CMD_SATA > - imply CMD_NAND > - imply CMD_REGINFO > - imply FSL_SATA > - > config ARCH_T4240 > bool > select E500MC > @@ -903,8 +871,7 @@ config NXP_ESBC > config MAX_CPUS >
RE: [PATCH 42/57] ppc: Remove T1040RDB boards
Hi Tom, > -Original Message- > From: U-Boot On Behalf Of Priyanka Jain > Sent: Monday, February 22, 2021 2:17 PM > To: Tom Rini ; u-boot@lists.denx.de > Cc: Jiafei Pan ; Xiaobo Xie ; > Poonam Aggrwal > Subject: RE: [PATCH 42/57] ppc: Remove T1040RDB boards > > >-Original Message- > >From: Tom Rini > >Sent: Sunday, February 21, 2021 6:36 AM > >To: u-boot@lists.denx.de > >Cc: Priyanka Jain ; Ruchika Gupta > >; Sumit Garg > >Subject: [PATCH 42/57] ppc: Remove T1040RDB boards > > > >These boards have not been converted to CONFIG_DM_MMC by the > >deadline. > >Remove them. > > > >Cc: Priyanka Jain > >Cc: Ruchika Gupta > >Cc: Sumit Garg > >Signed-off-by: Tom Rini > >--- > > arch/powerpc/cpu/mpc85xx/Kconfig | 19 - > > arch/powerpc/include/asm/fsl_secure_boot.h| 2 - > > board/freescale/t104xrdb/Kconfig | 16 - > > board/freescale/t104xrdb/MAINTAINERS | 38 - > > board/freescale/t104xrdb/Makefile | 16 - > > board/freescale/t104xrdb/README | 386 - > > board/freescale/t104xrdb/cpld.c | 115 --- > > board/freescale/t104xrdb/cpld.h | 46 - > > board/freescale/t104xrdb/ddr.c| 146 > > board/freescale/t104xrdb/ddr.h| 56 -- > > board/freescale/t104xrdb/diu.c| 84 -- > > board/freescale/t104xrdb/eth.c| 157 > > board/freescale/t104xrdb/law.c| 31 - > > board/freescale/t104xrdb/pci.c| 25 - > > board/freescale/t104xrdb/spl.c| 141 --- > > board/freescale/t104xrdb/t1040_nand_rcw.cfg | 7 - > > board/freescale/t104xrdb/t1040_sd_rcw.cfg | 7 - > > board/freescale/t104xrdb/t1040_spi_rcw.cfg| 7 - > > board/freescale/t104xrdb/t1040d4_nand_rcw.cfg | 7 - > > board/freescale/t104xrdb/t1040d4_sd_rcw.cfg | 7 - > > board/freescale/t104xrdb/t1040d4_spi_rcw.cfg | 7 - > > board/freescale/t104xrdb/t1042_nand_rcw.cfg | 7 - > > .../freescale/t104xrdb/t1042_pi_nand_rcw.cfg | 7 - > > board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg | 7 - > > board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg | 7 - > > board/freescale/t104xrdb/t1042_sd_rcw.cfg | 7 - > > board/freescale/t104xrdb/t1042_spi_rcw.cfg| 7 - > > board/freescale/t104xrdb/t1042d4_nand_rcw.cfg | 7 - > > board/freescale/t104xrdb/t1042d4_sd_rcw.cfg | 7 - > > board/freescale/t104xrdb/t1042d4_spi_rcw.cfg | 7 - > > board/freescale/t104xrdb/t104x_pbi.cfg| 36 - > > board/freescale/t104xrdb/t104x_pbi_sb.cfg | 38 - > > board/freescale/t104xrdb/t104xrdb.c | 164 > > board/freescale/t104xrdb/t104xrdb.h | 12 - > > board/freescale/t104xrdb/tlb.c| 131 --- > > configs/T1040D4RDB_NAND_defconfig | 78 -- > > configs/T1040D4RDB_SDCARD_defconfig | 75 -- > > configs/T1040D4RDB_SECURE_BOOT_defconfig | 64 -- > > configs/T1040D4RDB_SPIFLASH_defconfig | 77 -- > > configs/T1040D4RDB_defconfig | 62 -- > > configs/T1040RDB_NAND_defconfig | 79 -- > > configs/T1040RDB_SDCARD_defconfig | 76 -- > > configs/T1040RDB_SECURE_BOOT_defconfig| 65 -- > > configs/T1040RDB_SPIFLASH_defconfig | 78 -- > > configs/T1040RDB_defconfig| 63 -- > > configs/T1042D4RDB_NAND_defconfig | 86 -- > > configs/T1042D4RDB_SDCARD_defconfig | 83 -- > > configs/T1042D4RDB_SECURE_BOOT_defconfig | 63 -- > > configs/T1042D4RDB_SPIFLASH_defconfig | 85 -- > > configs/T1042D4RDB_defconfig | 71 -- DM_MMC had already been in use for T1042D4RDB. The board is still in maintaining. Can we keep it? Thanks. > > .../T1042RDB_PI_NAND_SECURE_BOOT_defconfig| 84 -- > > configs/T1042RDB_PI_NAND_defconfig| 79 -- > > configs/T1042RDB_PI_SDCARD_defconfig | 76 -- > > configs/T1042RDB_PI_SPIFLASH_defconfig| 78 -- > > configs/T1042RDB_PI_defconfig | 63 -- > > configs/T1042RDB_SECURE_BOOT_defconfig| 64 -- > > configs/T1042RDB_defconfig| 62 -- > > include/configs/T104xRDB.h| 806 -- > > 58 files changed, 4181 deletions(-) > > delete mode 100644 board/freescale/t104xrdb/Kconfig > > delete mode 100644 board/freescale/t104xrdb/MAINTAINERS > > delete mode 100644 board/freescale/t104xrdb/Makefile > > delete mode 100644 board/freescale/t104xrdb/README > > delete mode 100644 board/freescale/t104xrdb/cpld.c > > delete mode 100644 board/freescale/t104xrdb/cpld.h > > delete mode 100644 board/freescale/t104xrdb/ddr.c > > delete mode 100644 board/freescale/t104xrdb/ddr.h > > delete mode 100644 board/freescale/t104xrdb/diu.c > > delete mode 100644 board/freescale/t104xrdb/eth.c > > delete mode 100644 board/freescale/t104xrdb/law.c > > delete mode 100644 board/freescale/t104xrdb/pci.c > > delete mode 100644 board/freescale/t104xrdb/spl.c > >
RE: [v2, 0/2] mmc: fsl_esdhc: fix up for eMMC HS400
Hi Peng, Any comments on the patches. Thanks. Best regards, Yangbo Lu > -Original Message- > From: Yangbo Lu > Sent: Tuesday, October 20, 2020 11:05 AM > To: u-boot@lists.denx.de; Peng Fan ; 'Jaehoon Chung' > > Cc: Y.b. Lu > Subject: [v2, 0/2] mmc: fsl_esdhc: fix up for eMMC HS400 > > This patch-set provides fix up for eMMC HS400 for a potential > DLL lock issue during mmc rescan. > > Changes for v2: > - Added "Reviewed-by". > - Explained more in patch 2 commit message. > > Yangbo Lu (2): > mmc: fsl_esdhc: set sysctl register for clock initialization > mmc: fsl_esdhc: make sure delay chain locked for HS400 > > drivers/mmc/fsl_esdhc.c | 30 ++ > include/fsl_esdhc.h | 4 > 2 files changed, 30 insertions(+), 4 deletions(-) > > -- > 2.7.4
RE: [PATCH v3 1/2] armv8: lx2162a: Add Soc changes to support LX2162A
Hi Meenakshi, > -Original Message- > From: U-Boot On Behalf Of > meenakshi.aggar...@nxp.com > Sent: Monday, September 7, 2020 6:12 PM > To: u-boot@lists.denx.de; Priyanka Jain > Cc: Varun Sethi ; Meenakshi Aggarwal > > Subject: [PATCH v3 1/2] armv8: lx2162a: Add Soc changes to support LX2162A > > From: Meenakshi Aggarwal > > LX2162 is LX2160 based SoC, it has same die as of LX2160 > with different packaging. > > LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, > microSD card, eMMC support, serial console, qspi nor flash, qsgmii, > sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes > interface to support three PCIe gen3 interface. > > Signed-off-by: Meenakshi Aggarwal > --- > arch/arm/cpu/armv8/Kconfig | 2 +- > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 +-- > arch/arm/cpu/armv8/fsl-layerscape/Makefile | 5 ++ > arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 9 ++-- > arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 58 > ++ > .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c| 8 +-- > arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 19 ++- > arch/arm/cpu/armv8/fsl-layerscape/soc.c| 10 ++-- > arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 +-- > arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 +- > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 12 ++--- > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 7 ++- > .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 10 ++-- > drivers/ddr/fsl/Kconfig| 1 + > drivers/net/fsl-mc/Kconfig | 4 +- > drivers/net/ldpaa_eth/Makefile | 1 + > drivers/pci/Kconfig| 4 +- > drivers/pci/pcie_layerscape_ep.c | 4 +- > drivers/pci/pcie_layerscape_fixup_common.c | 7 ++- > 19 files changed, 170 insertions(+), 40 deletions(-) > > diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig > index 3655990..f247441 100644 > --- a/arch/arm/cpu/armv8/Kconfig > +++ b/arch/arm/cpu/armv8/Kconfig > @@ -115,7 +115,7 @@ config PSCI_RESET > !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ > !TARGET_LS1046AFRWY && \ > !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ > -!TARGET_LX2160AQDS && \ > +!TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \ > !ARCH_UNIPHIER && !TARGET_S32V234EVB > help > Most armv8 systems have PSCI support enabled in EL3, either through > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > index be51b7d..4d46587 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > @@ -208,6 +208,35 @@ config ARCH_LS2080A > imply DISTRO_DEFAULTS > imply PANIC_HANG > > +config ARCH_LX2162A > + bool > + select ARMV8_SET_SMPEN > + select FSL_LSCH3 > + select NXP_LSCH3_2 > + select SYS_HAS_SERDES > + select SYS_FSL_SRDS_1 > + select SYS_FSL_SRDS_2 > + select SYS_FSL_DDR > + select SYS_FSL_DDR_LE > + select SYS_FSL_DDR_VER_50 > + select SYS_FSL_EC1 > + select SYS_FSL_EC2 > + select SYS_FSL_ERRATUM_A050106 > + select SYS_FSL_HAS_RGMII > + select SYS_FSL_HAS_SEC > + select SYS_FSL_HAS_CCN508 > + select SYS_FSL_HAS_DDR4 > + select SYS_FSL_SEC_COMPAT_5 > + select SYS_FSL_SEC_LE > + select ARCH_EARLY_INIT_R > + select BOARD_EARLY_INIT_F > + select SYS_I2C_MXC > + select RESV_RAM if GIC_V3_ITS > + imply DISTRO_DEFAULTS > + imply PANIC_HANG > + imply SCSI > + imply SCSI_AHCI > + > config ARCH_LX2160A > bool > select ARMV8_SET_SMPEN > @@ -345,7 +374,7 @@ config SYS_FSL_ERRATUM_A050106 > help > USB3.0 Receiver needs to enable fixed equalization > for each of PHY instances in an SOC. This is similar > - to erratum A-009007, but this one is for LX2160A, > + to erratum A-009007, but this one is for LX2160A and LX2162A, > and the register value is different. > > config SYS_FSL_ERRATUM_A010315 > @@ -362,6 +391,7 @@ config MAX_CPUS > default 16 if ARCH_LS2080A > default 8 if ARCH_LS1088A > default 16 if ARCH_LX2160A > + default 16 if ARCH_LX2162A > default 1 > help > Set this number to the maximum number of possible CPUs in the SoC. > @@ -491,6 +521,7 @@ config SYS_FSL_DUART_CLK_DIV > int "DUART clock divider" > default 1 if ARCH_LS1043A > default 4 if ARCH_LX2160A > + default 4 if ARCH_LX2162A > default 2 > help > This is the divider that is used to derive DUART clock from Platform > @@ -502,6 +533,7 @@ config SYS_FSL_I2C_CLK_DIV > default 4 if ARCH_LS1012A > default 4 if ARCH_LS1028A >
RE: [PATCH 2/2] mmc: fsl_esdhc: make sure delay chain locked for HS400
Hi Jaehoon,
> -Original Message-
> From: Jaehoon Chung
> Sent: Tuesday, October 20, 2020 5:52 AM
> To: Y.b. Lu ; u-boot@lists.denx.de; Peng Fan
>
> Subject: Re: [PATCH 2/2] mmc: fsl_esdhc: make sure delay chain locked for
> HS400
>
> Dear Yangbo,
>
> On 10/16/20 12:13 PM, Yangbo Lu wrote:
> > For eMMC HS400 mode, the DLL reset is a required step for mmc rescan.
> > This step has not been documented in reference manual, but the RM will
> > be fixed sooner or later.
> >
> > This patch is to add the step of DLL reset, and make sure delay chain
> > locked for HS400.
> >
> > Fixes: db8f93672b42 ("mmc: fsl_esdhc: support eMMC HS400 mode")
> > Signed-off-by: Yangbo Lu
>
> Reviewed-by: Jaehoon Chung
>
> Just added minor comments.
>
>
> > ---
> > drivers/mmc/fsl_esdhc.c | 28 +---
> > include/fsl_esdhc.h | 4
> > 2 files changed, 29 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> > index 68130ee..a18316e 100644
> > --- a/drivers/mmc/fsl_esdhc.c
> > +++ b/drivers/mmc/fsl_esdhc.c
> > @@ -70,7 +70,9 @@ struct fsl_esdhc {
> > uintsdtimingctl;/* SD timing control register */
> > charreserved8[20]; /* reserved */
> > uintdllcfg0;/* DLL config 0 register */
> > - charreserved9[680]; /* reserved */
> > + charreserved9[12]; /* reserved */
> > + uintdllstat0; /* DLL status 0 register */
> > + charreserved10[664];/* reserved */
> > uintesdhcctl; /* eSDHC control register */
> > };
> >
> > @@ -617,9 +619,11 @@ static void esdhc_exit_hs400(struct fsl_esdhc_priv
> *priv)
> > esdhc_tuning_block_enable(priv, false);
> > }
> >
> > -static void esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode
> mode)
> > +static int esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode
> mode)
> > {
> > struct fsl_esdhc *regs = priv->esdhc_regs;
> > + ulong start;
> > + u32 val;
> >
> > /* Exit HS400 mode before setting any other mode */
> > if (esdhc_read32(>tbctl) & HS400_MODE &&
> > @@ -640,17 +644,33 @@ static void esdhc_set_timing(struct fsl_esdhc_priv
> *priv, enum bus_mode mode)
> > esdhc_setbits32(>dllcfg0, DLL_FREQ_SEL);
> >
> > esdhc_setbits32(>dllcfg0, DLL_ENABLE);
> > +
> > + esdhc_setbits32(>dllcfg0, DLL_RESET);
> > + udelay(1);
>
> Could you add a light comment why need to put udelay(1)?
Actually this is just per fixed reference manual.
I sent out v2 patch, to explain in commit message in case some one what to know
why.
"In previous commit to support eMMC HS400,
db8f936 mmc: fsl_esdhc: support eMMC HS400 mode
the steps to configure DLL could be found in commit message,
13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL].
14. Wait for delay chain to lock.
these would be fixed as,
13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL].
13.1 Write DLLCFG0[DLL_RESET] to 1 and wait for 1us,
then write DLLCFG0[DLL_RESET]
14. Wait for delay chain to lock."
Thanks.
>
> Best Regards,
> Jaehoon Chung
>
> > + esdhc_clrbits32(>dllcfg0, DLL_RESET);
> > +
> > + start = get_timer(0);
> > + val = DLL_STS_SLV_LOCK;
> > + while (!(esdhc_read32(>dllstat0) & val)) {
> > + if (get_timer(start) > 1000) {
> > + printf("fsl_esdhc: delay chain lock timeout\n");
> > + return -ETIMEDOUT;
> > + }
> > + }
> > +
> > esdhc_setbits32(>tbctl, HS400_WNDW_ADJUST);
> >
> > esdhc_clock_control(priv, false);
> > esdhc_flush_async_fifo(priv);
> > }
> > esdhc_clock_control(priv, true);
> > + return 0;
> > }
> >
> > static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc
> *mmc)
> > {
> > struct fsl_esdhc *regs = priv->esdhc_regs;
> > + int ret;
> >
> > if (priv->is_sdhc_per_clk) {
> > /* Select to use peripheral clock */
> > @@ -667,7 +687,9 @@ static int esdhc_set_ios_common(struct
> fsl_esdhc_priv *priv, struct mmc *mmc)
> > set_sysctl(priv, mmc, mmc->clock);
> >
> > /* Set timing */
> > - esdhc_set_timing(priv, mmc->selected_m
RE: [v4, 00/11] mmc: fsl_esdhc: support eMMC HS200/HS400 modes
Hi Jaehoon and Peng, Any comments on the v4 patch-set? Thank you. Best regards, Yangbo Lu > -Original Message- > From: Yangbo Lu > Sent: Tuesday, September 1, 2020 4:58 PM > To: u-boot@lists.denx.de; Peng Fan ; Priyanka Jain > ; 'Jaehoon Chung' > Cc: Y.b. Lu > Subject: [v4, 00/11] mmc: fsl_esdhc: support eMMC HS200/HS400 modes > > This patch-set is to support eMMC HS200 and HS400 speed modes for > eSDHC, and enable them on LX2160ARDB board. > > CI build link > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Ftravis-ci > .org%2Fgithub%2Fyangbolu1991%2Fu-boot-test%2Fbuilds%2F720875619 > mp;data=02%7C01%7Cyangbo.lu%40nxp.com%7Caf6b8adab90444f93e1208d > 84e563a07%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637345 > 479527036436sdata=L26QnuiL3ETvLbr4P1oJqxVJAoVlYY3ROg%2FWpb > J%2B6cc%3Dreserved=0 > > Changes for v2: > - Added two patches to fix stability issue. > Changes for v3: > - Explained more in commit messages. > - Added HS400 exit code for downgrade. > Changes for v4: > - Checked returning of mmc_hs400_prepare_ddr(). > - Added Reviewed-by. > - Rebased. > > Yangbo Lu (11): > mmc: add a reinit() API > mmc: fsl_esdhc: add a reinit() callback > mmc: fsl_esdhc: support tuning for eMMC HS200 > mmc: fsl_esdhc: clean TBCTL[TB_EN] manually during init > mmc: add a hs400_tuning flag > mmc: add a mmc_hs400_prepare_ddr() interface > mmc: fsl_esdhc: support eMMC HS400 mode > mmc: fsl_esdhc: fix mmc->clock with actual clock > mmc: fsl_esdhc: fix eMMC HS400 stability issue > arm: dts: lx2160ardb: support eMMC HS400 mode > configs: lx2160ardb: enable eMMC HS400 mode support > > arch/arm/dts/fsl-lx2160a-rdb.dts | 2 + > configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + > configs/lx2160ardb_tfa_defconfig | 1 + > configs/lx2160ardb_tfa_stmm_defconfig| 1 + > drivers/mmc/fsl_esdhc.c | 176 > ++- > drivers/mmc/mmc-uclass.c | 30 + > drivers/mmc/mmc.c| 14 ++- > include/fsl_esdhc.h | 29 - > include/mmc.h| 26 +++- > 9 files changed, 270 insertions(+), 10 deletions(-) > > -- > 2.7.4
RE: [v3, 06/11] mmc: add a mmc_hs400_prepare_ddr() interface
Hi Jaehoon,
> -Original Message-
> From: Jaehoon Chung
> Sent: Tuesday, August 25, 2020 6:54 AM
> To: Y.b. Lu ; u-boot@lists.denx.de; Peng Fan
> ; Priyanka Jain
> Subject: Re: [v3, 06/11] mmc: add a mmc_hs400_prepare_ddr() interface
>
> On 7/23/20 1:30 PM, Yangbo Lu wrote:
> > Add a mmc_hs400_prepare_ddr() interface for controllers
> > which needs preparation before switching to DDR mode for
> > HS400 mode.
> >
> > Signed-off-by: Yangbo Lu
> > ---
> > Changes for v2:
> > - None.
> > Changes for v3:
> > - None.
> > ---
> > drivers/mmc/mmc-uclass.c | 15 +++
> > drivers/mmc/mmc.c| 2 ++
> > include/mmc.h| 15 ++-
> > 3 files changed, 31 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
> > index b9f0880..240b205 100644
> > --- a/drivers/mmc/mmc-uclass.c
> > +++ b/drivers/mmc/mmc-uclass.c
> > @@ -141,6 +141,21 @@ int mmc_set_enhanced_strobe(struct mmc *mmc)
> > }
> > #endif
> >
> > +int dm_mmc_hs400_prepare_ddr(struct udevice *dev)
> > +{
> > + struct dm_mmc_ops *ops = mmc_get_ops(dev);
> > +
> > + if (ops->hs400_prepare_ddr)
> > + return ops->hs400_prepare_ddr(dev);
> > +
> > + return 0;
> > +}
> > +
> > +int mmc_hs400_prepare_ddr(struct mmc *mmc)
> > +{
> > + return dm_mmc_hs400_prepare_ddr(mmc->dev);
> > +}
> > +
> > int dm_mmc_host_power_cycle(struct udevice *dev)
> > {
> > struct dm_mmc_ops *ops = mmc_get_ops(dev);
> > diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
> > index f020a8e..935fa72 100644
> > --- a/drivers/mmc/mmc.c
> > +++ b/drivers/mmc/mmc.c
> > @@ -1992,6 +1992,8 @@ static int mmc_select_hs400(struct mmc *mmc)
> > /* Set back to HS */
> > mmc_set_card_speed(mmc, MMC_HS, true);
> >
> > + mmc_hs400_prepare_ddr(mmc);
>
> not need to get the return value? you have defined
> mmc_hs400_prepare_ddr() as int return type.
I will add returning checking.
Thanks!
>
> Best Regards,
> Jaehoon Chung
>
> > +
> > err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
> EXT_CSD_BUS_WIDTH,
> > EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
> > if (err)
> > diff --git a/include/mmc.h b/include/mmc.h
> > index 2399cc2..659df75 100644
> > --- a/include/mmc.h
> > +++ b/include/mmc.h
> > @@ -513,6 +513,14 @@ struct dm_mmc_ops {
> > * @return maximum number of blocks for this transfer
> > */
> > int (*get_b_max)(struct udevice *dev, void *dst, lbaint_t blkcnt);
> > +
> > + /**
> > +* hs400_prepare_ddr - prepare to switch to DDR mode
> > +*
> > +* @dev:Device to check
> > +* @return 0 if success, -ve on error
> > +*/
> > + int (*hs400_prepare_ddr)(struct udevice *dev);
> > };
> >
> > #define mmc_get_ops(dev)((struct dm_mmc_ops
> *)(dev)->driver->ops)
> > @@ -540,7 +548,7 @@ int mmc_host_power_cycle(struct mmc *mmc);
> > int mmc_deferred_probe(struct mmc *mmc);
> > int mmc_reinit(struct mmc *mmc);
> > int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt);
> > -
> > +int mmc_hs400_prepare_ddr(struct mmc *mmc);
> > #else
> > struct mmc_ops {
> > int (*send_cmd)(struct mmc *mmc,
> > @@ -552,6 +560,11 @@ struct mmc_ops {
> > int (*host_power_cycle)(struct mmc *mmc);
> > int (*get_b_max)(struct mmc *mmc, void *dst, lbaint_t blkcnt);
> > };
> > +
> > +static inline int mmc_hs400_prepare_ddr(struct mmc *mmc)
> > +{
> > + return 0;
> > +}
> > #endif
> >
> > struct mmc_config {
> >
RE: [v3, 05/11] mmc: add a hs400_tuning flag
Hi Jaehoon,
> -Original Message-
> From: Jaehoon Chung
> Sent: Tuesday, August 25, 2020 6:54 AM
> To: Y.b. Lu ; u-boot@lists.denx.de; Peng Fan
> ; Priyanka Jain
> Subject: Re: [v3, 05/11] mmc: add a hs400_tuning flag
>
> On 7/23/20 1:30 PM, Yangbo Lu wrote:
> > Some controllers may have difference between HS200 tuning
> > and HS400 tuning, such as different registers setting,
> > different procedure, or different errata.
> >
> > This patch is to add a hs400_tuning flag to identify the
> > tuning for HS400 mode.
> >
> > Signed-off-by: Yangbo Lu
> > ---
> > Changes for v2:
> > - None.
> > Changes for v3:
> > - Explained more in commit messages.
> > ---
> > drivers/mmc/mmc.c | 2 ++
> > include/mmc.h | 1 +
> > 2 files changed, 3 insertions(+)
> >
> > diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
> > index a4c6153..f020a8e 100644
> > --- a/drivers/mmc/mmc.c
> > +++ b/drivers/mmc/mmc.c
> > @@ -1981,7 +1981,9 @@ static int mmc_select_hs400(struct mmc *mmc)
> > mmc_set_clock(mmc, mmc->tran_speed, false);
> >
> > /* execute tuning if needed */
> > + mmc->hs400_tuning = 1;
> > err = mmc_execute_tuning(mmc,
> MMC_CMD_SEND_TUNING_BLOCK_HS200);
> > + mmc->hs400_tuning = 0;
>
> It seems that it's fsl_esdhc specific flag. Is it need to set to 0?
From mmc driver, both HS200 and HS400 tuning are through
mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200).
But as I commented in commit message,
"Some controllers may have difference between HS200 tuning
and HS400 tuning, such as different registers setting,
different procedure, or different errata."
So we could use such flag to indicate the tuning in progress is for HS400. Set
it before tuning and clean after tuning.
By now, only fsl_esdhc is using it. I can't predict whether there will be other
controllers use it, but at least we need a method to identify HS400 tuning to
support eSDHC HS400 currently.
There are also errata for eSDHC HS400 tuning. I will send patches in the future.
Thanks.
>
> Best Regards,
> Jaehoon Chung
>
> > if (err) {
> > debug("tuning failed\n");
> > return err;
> > diff --git a/include/mmc.h b/include/mmc.h
> > index 161b8bc..2399cc2 100644
> > --- a/include/mmc.h
> > +++ b/include/mmc.h
> > @@ -707,6 +707,7 @@ struct mmc {
> > * accessing the boot partitions
> > */
> > u32 quirks;
> > + u8 hs400_tuning;
> > };
> >
> > struct mmc_hwpart_conf {
> >
RE: [v3, 00/11] mmc: fsl_esdhc: support eMMC HS200/HS400 modes
Any commets on the v3 patch-set. Thanks! Best regards, Yangbo Lu > -Original Message- > From: Yangbo Lu > Sent: Thursday, July 23, 2020 12:30 PM > To: u-boot@lists.denx.de; Peng Fan ; Priyanka Jain > ; 'Jaehoon Chung' > Cc: Y.b. Lu > Subject: [v3, 00/11] mmc: fsl_esdhc: support eMMC HS200/HS400 modes > > This patch-set is to support eMMC HS200 and HS400 speed modes for > eSDHC, and enable them on LX2160ARDB board. > > CI build link > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Ftravis-ci > .org%2Fgithub%2Fyangbolu1991%2Fu-boot-test%2Fbuilds%2F710977092 > mp;data=02%7C01%7Cyangbo.lu%40nxp.com%7Cad44ad82358841b1750d08 > d82ec207a0%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63731 > 0758167126235sdata=u8fiHRayfKhk%2FiFGjXItjlHmyWWk9MMqbWHz > WeId60c%3Dreserved=0 > > Changes for v2: > - Added two patches to fix stability issue. > Changes for v3: > - Explained more in commit messages. > - Added HS400 exit code for downgrade. > > Yangbo Lu (11): > mmc: add a reinit() API > mmc: fsl_esdhc: add a reinit() callback > mmc: fsl_esdhc: support tuning for eMMC HS200 > mmc: fsl_esdhc: clean TBCTL[TB_EN] manually during init > mmc: add a hs400_tuning flag > mmc: add a mmc_hs400_prepare_ddr() interface > mmc: fsl_esdhc: support eMMC HS400 mode > mmc: fsl_esdhc: fix mmc->clock with actual clock > mmc: fsl_esdhc: fix eMMC HS400 stability issue > arm: dts: lx2160ardb: support eMMC HS400 mode > configs: lx2160ardb: enable eMMC HS400 mode support > > arch/arm/dts/fsl-lx2160a-rdb.dts | 2 + > configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + > configs/lx2160ardb_tfa_defconfig | 1 + > configs/lx2160ardb_tfa_stmm_defconfig| 1 + > drivers/mmc/fsl_esdhc.c | 176 > ++- > drivers/mmc/mmc-uclass.c | 30 + > drivers/mmc/mmc.c| 12 +- > include/fsl_esdhc.h | 29 - > include/mmc.h| 26 +++- > 9 files changed, 268 insertions(+), 10 deletions(-) > > -- > 2.7.4
RE: [v2, 10/11] arm: dts: lx2160ardb: support eMMC HS400 mode
Hi Peng,
> -Original Message-
> From: Peng Fan
> Sent: Monday, July 20, 2020 9:45 AM
> To: Y.b. Lu ; u-boot@lists.denx.de; Priyanka Jain
> ; 'Jaehoon Chung'
> Cc: Y.b. Lu
> Subject: RE: [v2, 10/11] arm: dts: lx2160ardb: support eMMC HS400 mode
>
> > Subject: [v2, 10/11] arm: dts: lx2160ardb: support eMMC HS400 mode
> >
> > Add properties related to eMMC HS400 mode.
> >
> > mmc-hs400-1_8v;
> > bus-width = <8>;
> >
> > Signed-off-by: Yangbo Lu
> > ---
> > Changes for v2:
> > - None.
> > ---
> > arch/arm/dts/fsl-lx2160a-rdb.dts | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts
> > b/arch/arm/dts/fsl-lx2160a-rdb.dts
> > index d787778..5fbdd90 100644
> > --- a/arch/arm/dts/fsl-lx2160a-rdb.dts
> > +++ b/arch/arm/dts/fsl-lx2160a-rdb.dts
> > @@ -80,6 +80,8 @@
> > {
> > status = "okay";
> > mmc-hs200-1_8v;
> > + mmc-hs400-1_8v;
> > + bus-width = <8>;
>
> If kernel already has this, please add kernel commit.
> If not, please use fsl-lx2160a-rdb-u-boot.dtsi to include.
Thanks! Kernel had already has this since the first board dts patch.
b068890 arm64: dts: add LX2160ARDB board support
Do you want me to mention it in commit message?
>
> Regards,
> Peng.
>
> > };
> >
> > {
> > --
> > 2.7.4
RE: [v2, 07/11] mmc: fsl_esdhc: support eMMC HS400 mode
Hi Peng,
> -Original Message-
> From: Peng Fan
> Sent: Monday, July 20, 2020 9:42 AM
> To: Y.b. Lu ; u-boot@lists.denx.de; Priyanka Jain
> ; 'Jaehoon Chung'
> Cc: Y.b. Lu
> Subject: RE: [v2, 07/11] mmc: fsl_esdhc: support eMMC HS400 mode
>
> > Subject: [v2, 07/11] mmc: fsl_esdhc: support eMMC HS400 mode
> >
> > The process for eMMC HS400 mode for eSDHC is,
> >
> > 1. Perform the Tuning Process at the HS400 target operating frequency.
> >Latched the clock division value.
> > 2. if read transaction, then set the SDTIMNGCTL[FLW_CTL_BG].
> > 3. Switch to High Speed mode and then set the card clock frequency to
> >a value not greater than 52Mhz
> > 4. Clear TBCTL[TB_EN],tuning block enable bit.
> > 5. Change to 8 bit DDR Mode
> > 6. Switch the card to HS400 mode.
> > 7. Set TBCTL[TB_EN], tuning block enable bit.
> > 8. Clear SYSCTL[SDCLKEN]
> > 9. Wait for PRSSTAT[SDSTB] to be set
> > 10. Change the clock division to latched value.Set TBCTL[HS 400 mode]
> > and Set SDCLKCTL[CMD_CLK_CTRL]
> > 11. Set SYSCTL[SDCLKEN]
> > 12. Wait for PRSSTAT[SDSTB] to be set
> > 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL].
> > 14. Wait for delay chain to lock.
> > 15. Set TBCTL[HS400_WNDW_ADJUST]
> > 16. Again clear SYSCTL[SDCLKEN]
> > 17. Wait for PRSSTAT[SDSTB] to be set
> > 18. Set ESDHCCTL[FAF]
> > 19. Wait for ESDHCCTL[FAF] to be cleared 20. Set SYSCTL[SDCLKEN] 21. Wait
> > for PRSSTAT[SDSTB] to be set.
> >
> > Signed-off-by: Yangbo Lu
> > ---
> > Changes for v2:
> > - None.
> > ---
> > drivers/mmc/fsl_esdhc.c | 98
> > -
> > include/fsl_esdhc.h | 12 ++
> > 2 files changed, 76 insertions(+), 34 deletions(-)
> >
> > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index
> > 607b420..c1a127c 100644
> > --- a/drivers/mmc/fsl_esdhc.c
> > +++ b/drivers/mmc/fsl_esdhc.c
> > @@ -62,7 +62,12 @@ struct fsl_esdhc {
> > uinthostcapblt2;/* Host controller capabilities register 2 */
> > charreserved6[8]; /* reserved */
> > uinttbctl; /* Tuning block control register */
> > - charreserved7[744]; /* reserved */
> > + charreserved7[32]; /* reserved */
> > + uintsdclkctl; /* SD clock control register */
> > + uintsdtimingctl;/* SD timing control register */
> > + charreserved8[20]; /* reserved */
> > + uintdllcfg0;/* DLL config 0 register */
> > + charreserved9[680]; /* reserved */
> > uintesdhcctl; /* eSDHC control register */
> > };
> >
> > @@ -568,6 +573,38 @@ static void esdhc_clock_control(struct
> > fsl_esdhc_priv *priv, bool enable)
> > }
> > }
> >
> > +static void esdhc_flush_async_fifo(struct fsl_esdhc_priv *priv) {
> > + struct fsl_esdhc *regs = priv->esdhc_regs;
> > + u32 time_out;
> > +
> > + esdhc_setbits32(>esdhcctl, ESDHCCTL_FAF);
> > +
> > + time_out = 20;
> > + while (esdhc_read32(>esdhcctl) & ESDHCCTL_FAF) {
> > + if (time_out == 0) {
> > + printf("fsl_esdhc: Flush asynchronous FIFO timeout.\n");
> > + break;
> > + }
> > + time_out--;
> > + mdelay(1);
> > + }
> > +}
> > +
> > +static void esdhc_tuning_block_enable(struct fsl_esdhc_priv *priv,
> > + bool en)
> > +{
> > + struct fsl_esdhc *regs = priv->esdhc_regs;
> > +
> > + esdhc_clock_control(priv, false);
> > + esdhc_flush_async_fifo(priv);
> > + if (en)
> > + esdhc_setbits32(>tbctl, TBCTL_TB_EN);
> > + else
> > + esdhc_clrbits32(>tbctl, TBCTL_TB_EN);
> > + esdhc_clock_control(priv, true);
> > +}
> > +
> > static void esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode
> > mode) {
> > struct fsl_esdhc *regs = priv->esdhc_regs; @@ -577,7 +614,17 @@
> > static void esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode
> > mode)
> > if (mode == MMC_HS_200)
> > esdhc_clrsetbits32(>autoc12err, UHSM_MASK,
> >UHSM_SDR104_HS200);
> > + if (mode == MMC_HS_400) {
> > + esdhc_setbits32(>tbctl, HS400_MODE);
> > + esdhc_setbits32(>sdclkctl, CMD_CLK_CTL);
> > + esdhc_clock_control(priv, true);
> >
> > + esdhc_
RE: [v2, 06/11] mmc: add a mmc_hs400_prepare_ddr() interface
Hi Peng,
> -Original Message-
> From: Peng Fan
> Sent: Monday, July 20, 2020 9:40 AM
> To: Y.b. Lu ; u-boot@lists.denx.de; Priyanka Jain
> ; 'Jaehoon Chung'
> Cc: Y.b. Lu
> Subject: RE: [v2, 06/11] mmc: add a mmc_hs400_prepare_ddr() interface
>
> > Subject: [v2, 06/11] mmc: add a mmc_hs400_prepare_ddr() interface
> >
> > Add a mmc_hs400_prepare_ddr() interface for controllers which needs
> > preparation before switching to DDR mode for
> > HS400 mode.
>
> This is LSx specific? If yes, could this be done in fsl_esdhc.c?
Yes. Actually I desire to put these esdhc specific setting in its own driver
too.
However the HS400 procedure of esdhc indeed break the standard process.
As you see in my patch #7 commit message, the tuning block has to be disabled
after switching to HS and before switching to DDR.
> 3. Switch to High Speed mode and then set the card clock frequency to
>a value not greater than 52Mhz
> 4. Clear TBCTL[TB_EN],tuning block enable bit.
> 5. Change to 8 bit DDR Mode
I have to make code changed as below expecting some controllers drivers may
utilize mmc_hs400_prepare_ddr() too.
We had done same thing in linux too. (cc14eec mmc: core: Add
->hs400_prepare_ddr() callback)
Do you have any suggestion?
mmc_set_card_speed(mmc, MMC_HS, true);
+ mmc_hs400_prepare_ddr(mmc);
+
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
Thanks.
>
> Thanks,
> Peng.
>
> >
> > Signed-off-by: Yangbo Lu
> > ---
> > Changes for v2:
> > - None.
> > ---
> > drivers/mmc/mmc-uclass.c | 15 +++
> > drivers/mmc/mmc.c| 2 ++
> > include/mmc.h| 15 ++-
> > 3 files changed, 31 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index
> > b9f0880..240b205 100644
> > --- a/drivers/mmc/mmc-uclass.c
> > +++ b/drivers/mmc/mmc-uclass.c
> > @@ -141,6 +141,21 @@ int mmc_set_enhanced_strobe(struct mmc
> > *mmc) } #endif
> >
> > +int dm_mmc_hs400_prepare_ddr(struct udevice *dev) {
> > + struct dm_mmc_ops *ops = mmc_get_ops(dev);
> > +
> > + if (ops->hs400_prepare_ddr)
> > + return ops->hs400_prepare_ddr(dev);
> > +
> > + return 0;
> > +}
> > +
> > +int mmc_hs400_prepare_ddr(struct mmc *mmc) {
> > + return dm_mmc_hs400_prepare_ddr(mmc->dev);
> > +}
> > +
> > int dm_mmc_host_power_cycle(struct udevice *dev) {
> > struct dm_mmc_ops *ops = mmc_get_ops(dev); diff --git
> > a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index a18e75d..e396207
> > 100644
> > --- a/drivers/mmc/mmc.c
> > +++ b/drivers/mmc/mmc.c
> > @@ -1987,6 +1987,8 @@ static int mmc_select_hs400(struct mmc *mmc)
> > /* Set back to HS */
> > mmc_set_card_speed(mmc, MMC_HS, true);
> >
> > + mmc_hs400_prepare_ddr(mmc);
> > +
> > err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
> > EXT_CSD_BUS_WIDTH,
> > EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
> > if (err)
> > diff --git a/include/mmc.h b/include/mmc.h index 2399cc2..659df75 100644
> > --- a/include/mmc.h
> > +++ b/include/mmc.h
> > @@ -513,6 +513,14 @@ struct dm_mmc_ops {
> > * @return maximum number of blocks for this transfer
> > */
> > int (*get_b_max)(struct udevice *dev, void *dst, lbaint_t blkcnt);
> > +
> > + /**
> > +* hs400_prepare_ddr - prepare to switch to DDR mode
> > +*
> > +* @dev:Device to check
> > +* @return 0 if success, -ve on error
> > +*/
> > + int (*hs400_prepare_ddr)(struct udevice *dev);
> > };
> >
> > #define mmc_get_ops(dev)((struct dm_mmc_ops
> > *)(dev)->driver->ops)
> > @@ -540,7 +548,7 @@ int mmc_host_power_cycle(struct mmc *mmc);
> int
> > mmc_deferred_probe(struct mmc *mmc); int mmc_reinit(struct mmc
> > *mmc); int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt);
> > -
> > +int mmc_hs400_prepare_ddr(struct mmc *mmc);
> > #else
> > struct mmc_ops {
> > int (*send_cmd)(struct mmc *mmc,
> > @@ -552,6 +560,11 @@ struct mmc_ops {
> > int (*host_power_cycle)(struct mmc *mmc);
> > int (*get_b_max)(struct mmc *mmc, void *dst, lbaint_t blkcnt); };
> > +
> > +static inline int mmc_hs400_prepare_ddr(struct mmc *mmc) {
> > + return 0;
> > +}
> > #endif
> >
> > struct mmc_config {
> > --
> > 2.7.4
RE: [v2, 05/11] mmc: add a hs400_tuning flag
Hi Peng,
> -Original Message-
> From: Peng Fan
> Sent: Monday, July 20, 2020 9:37 AM
> To: Y.b. Lu ; u-boot@lists.denx.de; Priyanka Jain
> ; 'Jaehoon Chung'
> Cc: Y.b. Lu
> Subject: RE: [v2, 05/11] mmc: add a hs400_tuning flag
>
> > Subject: [v2, 05/11] mmc: add a hs400_tuning flag
> >
> > Add a hs400_tuning flag to identify the tuning for HS400 mode.
>
> Why? Please explain a bit more.
Some specific controllers may have difference between HS400 tuning and HS200
tuning.
For eSDHC, as you saw in my patch #7, and there are also some eSDHC errata
related to HS400 tuning which I will upstream patches in the future.
In kernel drivers/mmc/host/sdhci.c, there is a flag SDHCI_HS400_TUNING used by
sdhci-msm.c and sdhci-of-esdhc.c for specific handling.
I will explain more in commit message.
>
> Thanks,
> Peng.
>
> >
> > Signed-off-by: Yangbo Lu
> > ---
> > Changes for v2:
> > - None.
> > ---
> > drivers/mmc/mmc.c | 2 ++
> > include/mmc.h | 1 +
> > 2 files changed, 3 insertions(+)
> >
> > diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index
> > a53f93a..a18e75d 100644
> > --- a/drivers/mmc/mmc.c
> > +++ b/drivers/mmc/mmc.c
> > @@ -1976,7 +1976,9 @@ static int mmc_select_hs400(struct mmc *mmc)
> > mmc_set_clock(mmc, mmc->tran_speed, false);
> >
> > /* execute tuning if needed */
> > + mmc->hs400_tuning = 1;
> > err = mmc_execute_tuning(mmc,
> > MMC_CMD_SEND_TUNING_BLOCK_HS200);
> > + mmc->hs400_tuning = 0;
> > if (err) {
> > debug("tuning failed\n");
> > return err;
> > diff --git a/include/mmc.h b/include/mmc.h index 161b8bc..2399cc2 100644
> > --- a/include/mmc.h
> > +++ b/include/mmc.h
> > @@ -707,6 +707,7 @@ struct mmc {
> > * accessing the boot partitions
> > */
> > u32 quirks;
> > + u8 hs400_tuning;
> > };
> >
> > struct mmc_hwpart_conf {
> > --
> > 2.7.4
RE: [v2, 01/11] mmc: add a reinit() API
Hi Peng,
> -Original Message-
> From: Peng Fan
> Sent: Monday, July 20, 2020 9:33 AM
> To: Y.b. Lu ; u-boot@lists.denx.de; Priyanka Jain
> ; 'Jaehoon Chung'
> Cc: Y.b. Lu
> Subject: RE: [v2, 01/11] mmc: add a reinit() API
>
> > Subject: [v2, 01/11] mmc: add a reinit() API
> >
> > For DM_MMC, the controller re-initialization is needed to clear old
> > configuration for mmc rescan.
> >
> > Signed-off-by: Yangbo Lu
> > ---
> > Changes for v2:
> > - None.
> > ---
> > drivers/mmc/mmc-uclass.c | 15 +++
> > drivers/mmc/mmc.c| 8 ++--
> > include/mmc.h| 10 ++
> > 3 files changed, 31 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index
> > c5b7872..b9f0880 100644
> > --- a/drivers/mmc/mmc-uclass.c
> > +++ b/drivers/mmc/mmc-uclass.c
> > @@ -170,6 +170,21 @@ int mmc_deferred_probe(struct mmc *mmc)
> > return dm_mmc_deferred_probe(mmc->dev); }
> >
> > +int dm_mmc_reinit(struct udevice *dev)
> > +{
> > + struct dm_mmc_ops *ops = mmc_get_ops(dev);
> > +
> > + if (ops->reinit)
> > + return ops->reinit(dev);
> > +
> > + return 0;
> > +}
> > +
> > +int mmc_reinit(struct mmc *mmc)
> > +{
> > + return dm_mmc_reinit(mmc->dev);
> > +}
> > +
> > int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg) {
> > int val;
> > diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index
> > 50f47d4..a53f93a 100644
> > --- a/drivers/mmc/mmc.c
> > +++ b/drivers/mmc/mmc.c
> > @@ -2813,13 +2813,17 @@ int mmc_get_op_cond(struct mmc *mmc)
> > return err;
> >
> > #if CONFIG_IS_ENABLED(DM_MMC)
> > - /* The device has already been probed ready for use */
> > + /*
> > +* Re-initialization is needed to clear old configuration for
> > +* mmc rescan.
>
> You mean cmd "mmc rescan" ?
Yes. The flag has_init is being used to skip the reinitialization if the card
has been initialized once.
Going through the mmc driver, the only place where we want to actually and
completely reinitialize the SD card is "mmc rescan".
For "mmc rescan", before sending CMD0 to reset card, the controller is still
needed to be reset/re-initialized.
Otherwise the controller may be still in previous status (registers setting)
communicating with the card.
>
> > +*/
> > + err = mmc_reinit(mmc);
>
> Probe could not provide what you need? You need a different settings?
Probe is called only once. The controller still needs to be
reset/re-initialized to clean all previous registers setting, before sending
CMD0 for mmc rescan.
For example, the eSDHC controller is now in 8-bit 200MHz eMMC HS400 mode (in
tuning mode).
When we want mmc rescan to completely reinitialize the card starting from CMD0,
we needs to reset/re-initialize the controller to clean previous HS400 mode
setting.
>
> Regards,
> Peng.
>
> > #else
> > /* made sure it's not NULL earlier */
> > err = mmc->cfg->ops->init(mmc);
> > +#endif
> > if (err)
> > return err;
> > -#endif
> > mmc->ddr_mode = 0;
> >
> > retry:
> > diff --git a/include/mmc.h b/include/mmc.h index 8256219..161b8bc
> 100644
> > --- a/include/mmc.h
> > +++ b/include/mmc.h
> > @@ -422,6 +422,14 @@ struct dm_mmc_ops {
> > */
> > int (*deferred_probe)(struct udevice *dev);
> > /**
> > +* reinit() - Re-initialization to clear old configuration for
> > +* mmc rescan.
> > +*
> > +* @dev:Device to reinit
> > +* @return 0 if Ok, -ve if error
> > +*/
> > + int (*reinit)(struct udevice *dev);
> > + /**
> > * send_cmd() - Send a command to the MMC device
> > *
> > * @dev:Device to receive the command
> > @@ -518,6 +526,7 @@ int dm_mmc_execute_tuning(struct udevice *dev,
> > uint opcode); int dm_mmc_wait_dat0(struct udevice *dev, int state, int
> > timeout_us); int dm_mmc_host_power_cycle(struct udevice *dev); int
> > dm_mmc_deferred_probe(struct udevice *dev);
> > +int dm_mmc_reinit(struct udevice *dev);
> > int dm_mmc_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt);
> >
> > /* Transition functions for compatibility */ @@ -529,6 +538,7 @@ int
> > mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us); int
> > mmc_set_enhanced_strobe(struct mmc *mmc); int
> > mmc_host_power_cycle(struct mmc *mmc); int
> > mmc_deferred_probe(struct mmc *mmc);
> > +int mmc_reinit(struct mmc *mmc);
> > int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt);
> >
> > #else
> > --
> > 2.7.4
RE: [PATCH 0/9] mmc: fsl_esdhc: support eMMC HS200/HS400 modes
ite: dev # 1, block # 0, count 2097152 ... 2097152 blocks written: OK MMC write: dev # 1, block # 0, count 2097152 ... 2097152 blocks written: OK MMC write: dev # 1, block # 0, count 2097152 ... 2097152 blocks written: OK MMC write: dev # 1, block # 0, count 2097152 ... 2097152 blocks written: OK Date: 2020-07-17 (Friday)Time: 7:48:03 => mw.l 8100 1000;mw.l 8200 1000;mmc write 8100 0 100;mmc read 8200 0 100;cmp.b 8100 8200 100 MMC write: dev # 1, block # 0, count 256 ... 256 blocks written: OK MMC read: dev # 1, block # 0, count 256 ... 256 blocks read: OK Total of 256 byte(s) were the same => Best regards, Yangbo Lu > -Original Message- > From: Jaehoon Chung > Sent: Friday, July 17, 2020 8:31 AM > To: Y.b. Lu ; u-boot@lists.denx.de; Peng Fan > ; Priyanka Jain > Subject: Re: [PATCH 0/9] mmc: fsl_esdhc: support eMMC HS200/HS400 modes > > Hi Yangbo, > > On 7/16/20 11:29 AM, Yangbo Lu wrote: > > This patch-set is to support eMMC HS200 and HS400 speed modes for > > eSDHC, and enable them on LX2160ARDB board. > > Is there any result about performance? > > Best Regards, > Jaehoon Chung > > > > > CI build link > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Ftravis-ci > .org%2Fgithub%2Fyangbolu1991%2Fu-boot-test%2Fbuilds%2F708215558 > mp;data=02%7C01%7Cyangbo.lu%40nxp.com%7Ca438d5eb0d9b4c7c660708 > d829e8bc25%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63730 > 5426855786897sdata=h54G7iKDdtmVRyuU0mZ7aZ06To3EqDc%2BRL3 > 0SFYtaWE%3Dreserved=0 > > > > Yangbo Lu (9): > > mmc: add a reinit() API > > mmc: fsl_esdhc: add a reinit() callback > > mmc: fsl_esdhc: support tuning for eMMC HS200 > > mmc: fsl_esdhc: clean TBCTL[TB_EN] manually during init > > mmc: add a hs400_tuning flag > > mmc: add a mmc_hs400_prepare_ddr() interface > > mmc: fsl_esdhc: support eMMC HS400 mode > > arm: dts: lx2160ardb: support eMMC HS400 mode > > configs: lx2160ardb: enable eMMC HS400 mode support > > > > arch/arm/dts/fsl-lx2160a-rdb.dts | 2 + > > configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + > > configs/lx2160ardb_tfa_defconfig | 1 + > > configs/lx2160ardb_tfa_stmm_defconfig| 1 + > > drivers/mmc/fsl_esdhc.c | 148 > ++- > > drivers/mmc/mmc-uclass.c | 30 ++ > > drivers/mmc/mmc.c| 12 ++- > > include/fsl_esdhc.h | 29 +- > > include/mmc.h| 26 - > > 9 files changed, 240 insertions(+), 10 deletions(-) > >
RE: [PATCH 0/4] Move eSDHC adapter card code to board files
CC Xiaobo, Jiafei > -Original Message- > From: Y.b. Lu > Sent: Monday, July 6, 2020 10:47 AM > To: u-boot@lists.denx.de; Priyanka Jain ; Peng Fan > > Subject: RE: [PATCH 0/4] Move eSDHC adapter card code to board files > > Hi Priyanka, > > Any comments on this patch-set? > Thanks a lot. > > Best regards, > Yangbo Lu > > > -Original Message- > > From: Yangbo Lu > > Sent: Wednesday, June 17, 2020 6:09 PM > > To: u-boot@lists.denx.de; Priyanka Jain ; Peng Fan > > > > Cc: Y.b. Lu > > Subject: [PATCH 0/4] Move eSDHC adapter card code to board files > > > > The eSDHC adapter card identification and multiplexing configuration > > through FPGA had been implemented in both common mmc driver and > > fsl_esdhc driver. However it is proper to move these code to board > > files and do it during board initialization. The FPGA registers are > > also board specific. > > > > This patch-set is to move eSDHC adapter card identification and > > multiplexing configuration from mmc driver to specific board files. > > Add eSDHC adapter card identification for LX2 QDS. > > And the option CONFIG_FSL_ESDHC_ADAPTER_IDENT is no longer needed. > > > > CI build result > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Ftravis-ci > > .org%2Fgithub%2Fyangbolu1991%2Fu-boot-test%2Fbuilds%2F699180417& > a > > > mp;data=02%7C01%7Cyangbo.lu%40nxp.com%7C2351c69f76e142be1c4108d > > > 812a73fd6%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637279 > > > 856821151607sdata=doJR9jInaSGNQHqZlOar%2BKb3kY%2F7xuQzNgA > > 88ADf8B0%3Dreserved=0 > > > > Yangbo Lu (4): > > Drop global data sdhc_adapter for powerpc > > Move eSDHC adapter card identification to board files > > board: fsl: lx2160aqds: identify SDHC adapter during board init > > configs: lx2160aqds: enable CONFIG_BOARD_EARLY_INIT_R > > > > arch/powerpc/include/asm/global_data.h | 4 +-- > > board/freescale/common/qixis.h | 14 +++--- > > board/freescale/lx2160a/lx2160a.c| 36 > > +++-- > > board/freescale/t1040qds/t1040qds.c | 29 > > - > > board/freescale/t208xqds/t208xqds.c | 29 > > - > > configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + > > configs/lx2160aqds_tfa_defconfig | 1 + > > doc/README.fsl-esdhc | 14 -- > > drivers/mmc/fsl_esdhc.c | 39 > > > > drivers/mmc/mmc-uclass.c | 4 +-- > > drivers/mmc/mmc.c| 7 + > > drivers/mmc/mmc_legacy.c | 7 + > > drivers/mmc/mmc_private.h| 4 +-- > > include/configs/T1040QDS.h | 1 - > > include/configs/T208xQDS.h | 1 - > > include/fsl_esdhc.h | 4 --- > > scripts/config_whitelist.txt | 1 - > > 17 files changed, 108 insertions(+), 88 deletions(-) > > > > -- > > 2.7.4
RE: [PATCH 0/4] Move eSDHC adapter card code to board files
Hi Priyanka, Any comments on this patch-set? Thanks a lot. Best regards, Yangbo Lu > -Original Message- > From: Yangbo Lu > Sent: Wednesday, June 17, 2020 6:09 PM > To: u-boot@lists.denx.de; Priyanka Jain ; Peng Fan > > Cc: Y.b. Lu > Subject: [PATCH 0/4] Move eSDHC adapter card code to board files > > The eSDHC adapter card identification and multiplexing configuration > through FPGA had been implemented in both common mmc driver and > fsl_esdhc driver. However it is proper to move these code to board > files and do it during board initialization. The FPGA registers are > also board specific. > > This patch-set is to move eSDHC adapter card identification and > multiplexing configuration from mmc driver to specific board files. > Add eSDHC adapter card identification for LX2 QDS. > And the option CONFIG_FSL_ESDHC_ADAPTER_IDENT is no longer needed. > > CI build result > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Ftravis-ci > .org%2Fgithub%2Fyangbolu1991%2Fu-boot-test%2Fbuilds%2F699180417 > mp;data=02%7C01%7Cyangbo.lu%40nxp.com%7C2351c69f76e142be1c4108d > 812a73fd6%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637279 > 856821151607sdata=doJR9jInaSGNQHqZlOar%2BKb3kY%2F7xuQzNgA > 88ADf8B0%3Dreserved=0 > > Yangbo Lu (4): > Drop global data sdhc_adapter for powerpc > Move eSDHC adapter card identification to board files > board: fsl: lx2160aqds: identify SDHC adapter during board init > configs: lx2160aqds: enable CONFIG_BOARD_EARLY_INIT_R > > arch/powerpc/include/asm/global_data.h | 4 +-- > board/freescale/common/qixis.h | 14 +++--- > board/freescale/lx2160a/lx2160a.c| 36 > +++-- > board/freescale/t1040qds/t1040qds.c | 29 > - > board/freescale/t208xqds/t208xqds.c | 29 > - > configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + > configs/lx2160aqds_tfa_defconfig | 1 + > doc/README.fsl-esdhc | 14 -- > drivers/mmc/fsl_esdhc.c | 39 > > drivers/mmc/mmc-uclass.c | 4 +-- > drivers/mmc/mmc.c| 7 + > drivers/mmc/mmc_legacy.c | 7 + > drivers/mmc/mmc_private.h| 4 +-- > include/configs/T1040QDS.h | 1 - > include/configs/T208xQDS.h | 1 - > include/fsl_esdhc.h | 4 --- > scripts/config_whitelist.txt | 1 - > 17 files changed, 108 insertions(+), 88 deletions(-) > > -- > 2.7.4
RE: [PATCH] configs: disable eMMC HS200 support on layerscape platforms
Hi Jaehoon, > -Original Message- > From: Jaehoon Chung > Sent: Thursday, March 19, 2020 5:01 PM > To: Y.b. Lu ; u-boot@lists.denx.de; Priyanka Jain > > Subject: Re: [PATCH] configs: disable eMMC HS200 support on layerscape > platforms > > Hi, > > On 3/19/20 4:22 PM, Y.b. Lu wrote: > > Any comments? > > Thanks! > > > > Best regards, > > Yangbo Lu > > > >> -Original Message- > >> From: Yangbo Lu > >> Sent: Tuesday, March 3, 2020 10:33 AM > >> To: u-boot@lists.denx.de; Priyanka Jain > >> Cc: Y.b. Lu > >> Subject: [PATCH] configs: disable eMMC HS200 support on layerscape > >> platforms > >> > >> The eMMC HS200 speed mode on Layerscape platforms has not been > >> supported properly. The eSDHC clock tuning has not been implemented > >> by now. So disable it until it is supported properly in case of > >> any potential issues. > > > If it's not working fine, looks good to me. > BTW, I didn't have tested on its platform. Do you have a plan to fix it? [Yangbo Lu] Because we got issues with HS200 mode in testing, I sent this patch to disable it for now. The tuning support with eSDHC tuning block is in my plan. Thanks. > > Reviewed-by: Jaehoon Chung > > > >> > >> Signed-off-by: Yangbo Lu > >> --- > >> configs/ls1012ardb_tfa_defconfig | 1 - > >> configs/ls1028ardb_tfa_defconfig | 1 - > >> configs/lx2160ardb_tfa_defconfig | 1 - > >> 3 files changed, 3 deletions(-) > >> > >> diff --git a/configs/ls1012ardb_tfa_defconfig > >> b/configs/ls1012ardb_tfa_defconfig > >> index b47a47d..0e994f5 100644 > >> --- a/configs/ls1012ardb_tfa_defconfig > >> +++ b/configs/ls1012ardb_tfa_defconfig > >> @@ -38,7 +38,6 @@ CONFIG_NET_RANDOM_ETHADDR=y > >> CONFIG_DM=y > >> CONFIG_SATA_CEVA=y > >> CONFIG_DM_MMC=y > >> -CONFIG_MMC_HS200_SUPPORT=y > >> CONFIG_FSL_ESDHC=y > >> CONFIG_MTD=y > >> CONFIG_DM_SPI_FLASH=y > >> diff --git a/configs/ls1028ardb_tfa_defconfig > >> b/configs/ls1028ardb_tfa_defconfig > >> index 3ef5520..7ffd1c3 100644 > >> --- a/configs/ls1028ardb_tfa_defconfig > >> +++ b/configs/ls1028ardb_tfa_defconfig > >> @@ -45,7 +45,6 @@ CONFIG_I2C_DEFAULT_BUS_NUMBER=0 > >> CONFIG_I2C_MUX=y > >> CONFIG_I2C_MUX_PCA954x=y > >> CONFIG_DM_MMC=y > >> -CONFIG_MMC_HS200_SUPPORT=y > >> CONFIG_FSL_ESDHC=y > >> CONFIG_MTD=y > >> CONFIG_DM_SPI_FLASH=y > >> diff --git a/configs/lx2160ardb_tfa_defconfig > >> b/configs/lx2160ardb_tfa_defconfig > >> index b998cb6..0799cd4 100644 > >> --- a/configs/lx2160ardb_tfa_defconfig > >> +++ b/configs/lx2160ardb_tfa_defconfig > >> @@ -41,7 +41,6 @@ CONFIG_DM_I2C=y > >> CONFIG_I2C_SET_DEFAULT_BUS_NUM=y > >> CONFIG_I2C_DEFAULT_BUS_NUMBER=0 > >> CONFIG_DM_MMC=y > >> -CONFIG_MMC_HS200_SUPPORT=y > >> CONFIG_FSL_ESDHC=y > >> CONFIG_MTD=y > >> CONFIG_DM_SPI_FLASH=y > >> -- > >> 2.7.4 > > > > > >
RE: [PATCH] configs: disable eMMC HS200 support on layerscape platforms
Any comments? Thanks! Best regards, Yangbo Lu > -Original Message- > From: Yangbo Lu > Sent: Tuesday, March 3, 2020 10:33 AM > To: u-boot@lists.denx.de; Priyanka Jain > Cc: Y.b. Lu > Subject: [PATCH] configs: disable eMMC HS200 support on layerscape > platforms > > The eMMC HS200 speed mode on Layerscape platforms has not been > supported properly. The eSDHC clock tuning has not been implemented > by now. So disable it until it is supported properly in case of > any potential issues. > > Signed-off-by: Yangbo Lu > --- > configs/ls1012ardb_tfa_defconfig | 1 - > configs/ls1028ardb_tfa_defconfig | 1 - > configs/lx2160ardb_tfa_defconfig | 1 - > 3 files changed, 3 deletions(-) > > diff --git a/configs/ls1012ardb_tfa_defconfig > b/configs/ls1012ardb_tfa_defconfig > index b47a47d..0e994f5 100644 > --- a/configs/ls1012ardb_tfa_defconfig > +++ b/configs/ls1012ardb_tfa_defconfig > @@ -38,7 +38,6 @@ CONFIG_NET_RANDOM_ETHADDR=y > CONFIG_DM=y > CONFIG_SATA_CEVA=y > CONFIG_DM_MMC=y > -CONFIG_MMC_HS200_SUPPORT=y > CONFIG_FSL_ESDHC=y > CONFIG_MTD=y > CONFIG_DM_SPI_FLASH=y > diff --git a/configs/ls1028ardb_tfa_defconfig > b/configs/ls1028ardb_tfa_defconfig > index 3ef5520..7ffd1c3 100644 > --- a/configs/ls1028ardb_tfa_defconfig > +++ b/configs/ls1028ardb_tfa_defconfig > @@ -45,7 +45,6 @@ CONFIG_I2C_DEFAULT_BUS_NUMBER=0 > CONFIG_I2C_MUX=y > CONFIG_I2C_MUX_PCA954x=y > CONFIG_DM_MMC=y > -CONFIG_MMC_HS200_SUPPORT=y > CONFIG_FSL_ESDHC=y > CONFIG_MTD=y > CONFIG_DM_SPI_FLASH=y > diff --git a/configs/lx2160ardb_tfa_defconfig > b/configs/lx2160ardb_tfa_defconfig > index b998cb6..0799cd4 100644 > --- a/configs/lx2160ardb_tfa_defconfig > +++ b/configs/lx2160ardb_tfa_defconfig > @@ -41,7 +41,6 @@ CONFIG_DM_I2C=y > CONFIG_I2C_SET_DEFAULT_BUS_NUM=y > CONFIG_I2C_DEFAULT_BUS_NUMBER=0 > CONFIG_DM_MMC=y > -CONFIG_MMC_HS200_SUPPORT=y > CONFIG_FSL_ESDHC=y > CONFIG_MTD=y > CONFIG_DM_SPI_FLASH=y > -- > 2.7.4
RE: [PATCH] mmc: fsl_esdhc: actually enable cache snooping on mpc830x
> -Original Message-
> From: Peng Fan
> Sent: Wednesday, February 5, 2020 3:08 PM
> To: Rasmus Villemoes ; u-boot@lists.denx.de;
> Y.b. Lu
> Cc: Mario Six
> Subject: RE: [PATCH] mmc: fsl_esdhc: actually enable cache snooping on
> mpc830x
>
> > Subject: [PATCH] mmc: fsl_esdhc: actually enable cache snooping on
> mpc830x
>
> + Y.b
>
> Are you ok with this patch?
The mpc830x is old Freescale PowerPC platforms I don't have.
But I agree the fix-up.
Reviewed-by: Yangbo Lu
>
> Thanks,
> Peng.
>
> >
> > The reference manuals for MPC8308 and MPC8309 both say that the
> esdhcctl
> > aka DMA Control Register "is implemented as SDHCCR" in the System
> > configuration registers. Unfortunately, that doesn't mean that the registers
> are
> > just mirrors of each other - any write to esdhcctl is simply ignored. So to
> > actually enable cache snooping, we unfortunately have to add a little
> > ifdeffery.
> >
> > There is, naturally, no description of the bit fields of esdhcctl in the
> > MPC8309
> > manual, but comparing the description of esdhcctl from the LS1021A
> > reference manual to the description of the sdhccr in MPC8309, one also finds
> > that the fields are bit-reversed, so the bit to set is
> > 0x0200 rather than 0x0040 - this is also what board_mmc_init()
> > uses in the two gdsys/mpc8308/ boards.
> >
> > Signed-off-by: Rasmus Villemoes
> > ---
> > drivers/mmc/fsl_esdhc.c | 15 +--
> > 1 file changed, 13 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index
> > 1e7d606cd8..34e5bd270f 100644
> > --- a/drivers/mmc/fsl_esdhc.c
> > +++ b/drivers/mmc/fsl_esdhc.c
> > @@ -577,6 +577,18 @@ static int esdhc_set_ios_common(struct
> > fsl_esdhc_priv *priv, struct mmc *mmc)
> > return 0;
> > }
> >
> > +static void esdhc_enable_cache_snooping(struct fsl_esdhc *regs) {
> > +#ifdef CONFIG_ARCH_MPC830X
> > + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
> > + sysconf83xx_t *sysconf = >sysconf;
> > +
> > + setbits_be32(>sdhccr, 0x0200); #else
> > + esdhc_write32(>esdhcctl, 0x0040); #endif }
> > +
> > static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc
> *mmc)
> > {
> > struct fsl_esdhc *regs = priv->esdhc_regs; @@ -592,8 +604,7 @@ static
> > int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
> > return -ETIMEDOUT;
> > }
> >
> > - /* Enable cache snooping */
> > - esdhc_write32(>esdhcctl, 0x0040);
> > + esdhc_enable_cache_snooping(regs);
> >
> > esdhc_setbits32(>sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
> >
> > --
> > 2.23.0
RE: [PATCH 0/6] Clean up eSDHC periperhal clock code
Hi Peng and Priyanka, Happy new year! Could you help to review this patch-set? It's related to MMC and QorIQ PowerPC/ARM. Thanks. Best regards, Yangbo Lu > -Original Message- > From: Y.b. Lu > Sent: Friday, December 20, 2019 11:56 AM > To: Yangbo Lu ; u-boot@lists.denx.de > Cc: Peng Fan ; Priyanka Jain ; > Wolfgang Denk > Subject: RE: [PATCH 0/6] Clean up eSDHC periperhal clock code > > Here is CI build result. > https://travis-ci.org/yangbolu1991/u-boot-test/builds/627093385 > > Thanks. > > > -Original Message- > > From: Yangbo Lu > > Sent: Thursday, December 19, 2019 6:59 PM > > To: u-boot@lists.denx.de > > Cc: Peng Fan ; Priyanka Jain ; > > Wolfgang Denk ; Y.b. Lu > > Subject: [PATCH 0/6] Clean up eSDHC periperhal clock code > > > > This patch-set is to clean up eSDHC peripheral clock code. > > - Drop useless code in esdhc/esdhc_imx drivers and powerpc/. > > - Add global variable sdhc_per_clk for peripehral clock. > > - Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option and let > > driver decides which clock to use. > > - Some fixes for peripehral clock calcualtion. > > > > Yangbo Lu (6): > > mmc: fsl_esdhc_imx: drop QorIQ eSDHC specific peripheral clock code > > mmc: fsl_esdhc: drop useless fdt fixup > > powerpc/mpc85xx: drop eSDHC periperhal clock code > > Add global variable sdhc_per_clk for arm/powerpc > > configs: ls1028a: use default SDHC clock divider value > > Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usage > > > > .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 29 + > > .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 22 +- > > arch/arm/include/asm/global_data.h | 4 ++ > > arch/powerpc/cpu/mpc85xx/speed.c | 49 > > +- > > arch/powerpc/include/asm/config_mpc85xx.h | 8 > > arch/powerpc/include/asm/global_data.h | 1 + > > configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 1 - > > configs/ls1028aqds_tfa_defconfig | 1 - > > configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 1 - > > configs/ls1028ardb_tfa_defconfig | 1 - > > drivers/mmc/Kconfig| 9 > > drivers/mmc/fsl_esdhc.c| 41 > > +- > > drivers/mmc/fsl_esdhc_imx.c| 40 -- > > include/configs/T1040QDS.h | 1 - > > include/configs/T208xQDS.h | 1 - > > include/e500.h | 1 - > > scripts/config_whitelist.txt | 2 - > > 17 files changed, 48 insertions(+), 164 deletions(-) > > > > -- > > 2.7.4
RE: [PATCH 0/6] Clean up eSDHC periperhal clock code
Here is CI build result. https://travis-ci.org/yangbolu1991/u-boot-test/builds/627093385 Thanks. > -Original Message- > From: Yangbo Lu > Sent: Thursday, December 19, 2019 6:59 PM > To: u-boot@lists.denx.de > Cc: Peng Fan ; Priyanka Jain ; > Wolfgang Denk ; Y.b. Lu > Subject: [PATCH 0/6] Clean up eSDHC periperhal clock code > > This patch-set is to clean up eSDHC peripheral clock code. > - Drop useless code in esdhc/esdhc_imx drivers and powerpc/. > - Add global variable sdhc_per_clk for peripehral clock. > - Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option and let > driver decides which clock to use. > - Some fixes for peripehral clock calcualtion. > > Yangbo Lu (6): > mmc: fsl_esdhc_imx: drop QorIQ eSDHC specific peripheral clock code > mmc: fsl_esdhc: drop useless fdt fixup > powerpc/mpc85xx: drop eSDHC periperhal clock code > Add global variable sdhc_per_clk for arm/powerpc > configs: ls1028a: use default SDHC clock divider value > Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usage > > .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 29 + > .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 22 +- > arch/arm/include/asm/global_data.h | 4 ++ > arch/powerpc/cpu/mpc85xx/speed.c | 49 > +- > arch/powerpc/include/asm/config_mpc85xx.h | 8 > arch/powerpc/include/asm/global_data.h | 1 + > configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 1 - > configs/ls1028aqds_tfa_defconfig | 1 - > configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 1 - > configs/ls1028ardb_tfa_defconfig | 1 - > drivers/mmc/Kconfig| 9 > drivers/mmc/fsl_esdhc.c| 41 > +- > drivers/mmc/fsl_esdhc_imx.c| 40 -- > include/configs/T1040QDS.h | 1 - > include/configs/T208xQDS.h | 1 - > include/e500.h | 1 - > scripts/config_whitelist.txt | 2 - > 17 files changed, 48 insertions(+), 164 deletions(-) > > -- > 2.7.4
Re: [U-Boot] [PATCH 0/4] Drop redundant code for eSDHC clock getting
Any comments? Thanks. > -Original Message- > From: Yangbo Lu > Sent: Tuesday, November 12, 2019 7:29 PM > To: u-boot@lists.denx.de > Cc: Peng Fan ; Feng Li ; Alison > Wang ; Sumit Garg ; Priyanka > Jain ; Mario Six ; Y.b. Lu > > Subject: [PATCH 0/4] Drop redundant code for eSDHC clock getting > > This patch-set is to drop redundant code for eSDHC clock getting. > The fsl_esdhc driver is able to simply get clock from gd->arch.sdhc_clk. > > The CI build link: > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Ftravis-ci > .org%2Fyangbolu1991%2Fu-boot-test%2Fbuilds%2F610688748data=02 > %7C01%7Cyangbo.lu%40nxp.com%7C631a406c77594a0d737808d767637ae2 > %7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637091549269378 > 396sdata=7FT0Vn3oB0dMB5K1csOnNF5O9o61QxHheVtOeBJjDJw%3D > reserved=0 > > Yangbo Lu (4): > mmc: fsl_esdhc: get clock directly from global data > arm: ls1021a: drop redundant board_mmc_init() > arm: drop eSDHC clock getting in mxc_get_clock() for layerscape > mpc83xx: remove unused clock.h > > arch/arm/cpu/armv7/ls102xa/clock.c | 2 -- > .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 15 > -- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 15 -- > arch/arm/include/asm/arch-fsl-layerscape/clock.h | 2 -- > arch/arm/include/asm/arch-ls102xa/clock.h | 1 - > arch/powerpc/include/asm/arch-mpc83xx/clock.h | 22 -- > board/freescale/ls1021aiot/ls1021aiot.c| 15 -- > board/freescale/ls1021aqds/ls1021aqds.c| 14 - > board/freescale/ls1021atwr/ls1021atwr.c| 14 - > drivers/mmc/fsl_esdhc.c| 34 > +++--- > 10 files changed, 4 insertions(+), 130 deletions(-) delete mode 100644 > arch/powerpc/include/asm/arch-mpc83xx/clock.h > > -- > 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 0/7] mmc: fsl_esdhc: clean up and shrink the driver
Here is the CI build result. https://travis-ci.org/yangbolu1991/u-boot-test/builds/605435128 I had verified both SD and eMMC with both DM_MMC and non-DM_MMC modes. Thanks a lot. Best regards, Yangbo Lu > -Original Message- > From: Yangbo Lu > Sent: Thursday, October 31, 2019 6:54 PM > To: u-boot@lists.denx.de; Peng Fan > Cc: Y.b. Lu > Subject: [PATCH 0/7] mmc: fsl_esdhc: clean up and shrink the driver > > This patch-set is to clean up and shrink the fsl_esdhc driver. > > Yangbo Lu (7): > mmc: fsl_esdhc: drop controller initialization in fsl_esdhc_init() > mmc: fsl_esdhc: fix voltage validation > mmc: fsl_esdhc: clean up bus width configuration code > mmc: fsl_esdhc: convert to use fsl_esdhc_get_cfg_common() > mmc: fsl_esdhc: drop redundant code for non-removable feature > mmc: fsl_esdhc: always check write protect state > mmc: fsl_esdhc: clean up DM and non-DM code > > drivers/mmc/fsl_esdhc.c | 370 > > include/fsl_esdhc.h | 14 +- > 2 files changed, 129 insertions(+), 255 deletions(-) > > -- > 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 0/3] mmc: fsl_esdhc: clean up driver
Any comments? Thanks a lot. Best regards, Yangbo Lu > -Original Message- > From: Yangbo Lu > Sent: Monday, October 21, 2019 6:09 PM > To: u-boot@lists.denx.de; Peng Fan > Cc: Y.b. Lu > Subject: [PATCH 0/3] mmc: fsl_esdhc: clean up driver > > This patch-set is to clean up driver. There is still a lot of work to clean > up the > driver, and patches will be sent in the future. > > Yangbo Lu (3): > mmc: fsl_esdhc: make BLK as hard requirement of DM_MMC > mmc: fsl_esdhc: remove redundant DM_MMC checking > mmc: fsl_esdhc: drop i.MX DDR support code > > drivers/mmc/fsl_esdhc.c | 43 +++ > 1 file changed, 3 insertions(+), 40 deletions(-) > > -- > 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [v2, 0/3] mmc: fsl_esdhc: clean up code
Hi Peng, Any comments on this patch-set? Thanks a lot. Best regards, Yangbo Lu > -Original Message- > From: Yangbo Lu > Sent: Friday, September 6, 2019 2:05 PM > To: u-boot@lists.denx.de; Peng Fan > Cc: Y.b. Lu > Subject: [v2, 0/3] mmc: fsl_esdhc: clean up code > > This patch-set is to clean up fsl_esdhc code. > > Changes for v2: > - Involved esdhc_ops in non-DM conditional build. > > Yangbo Lu (3): > mmc: fsl_esdhc: make BLK as hard requirement of DM_MMC > mmc: fsl_esdhc: clean up code > mmc: fsl_esdhc: rename fsl_esdhc_init to fsl_esdhc_get_cfg > > drivers/mmc/fsl_esdhc.c | 369 > +++- > include/fsl_esdhc.h | 203 -- > 2 files changed, 240 insertions(+), 332 deletions(-) > > -- > 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] Convert CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE to Kconfig
Hi, > -Original Message- > From: Peng Fan > Sent: Tuesday, September 10, 2019 9:29 AM > To: Sébastien Szymanski ; > u-boot@lists.denx.de; Y.b. Lu > Cc: Fabio Estevam ; Otavio Salvador > > Subject: RE: [PATCH 1/2] Convert CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE > to Kconfig > > +Y.b > > > -Original Message- > > From: Sébastien Szymanski > > Sent: 2019年9月9日 14:36 > > To: Peng Fan ; u-boot@lists.denx.de > > Cc: Fabio Estevam ; Otavio Salvador > > > > Subject: Re: [PATCH 1/2] Convert CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE > to > > Kconfig > > > > Hello, > > > > On 9/9/19 3:59 AM, Peng Fan wrote: > > >> Subject: [PATCH 1/2] Convert CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE > > to > > >> Kconfig > > >> > > >> This converts the following to Kconfig: > > >> > > >> CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE > > >> > > >> Signed-off-by: Sébastien Szymanski > > > > >> --- > > >> configs/warp7_defconfig | 1 + > > >> configs/warp_defconfig | 1 + > > >> drivers/mmc/Kconfig | 6 ++ > > >> include/configs/warp.h | 1 - > > >> include/configs/warp7.h | 1 - > > >> scripts/config_whitelist.txt | 1 - > > >> 6 files changed, 8 insertions(+), 3 deletions(-) > > >> > > >> diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig > > >> index > > >> a022454976..9a167d2c43 100644 > > >> --- a/configs/warp7_defconfig > > >> +++ b/configs/warp7_defconfig > > >> @@ -40,6 +40,7 @@ CONFIG_DM_I2C=y > > >> CONFIG_DM_MMC=y > > >> CONFIG_SUPPORT_EMMC_BOOT=y > > >> CONFIG_FSL_USDHC=y > > >> +CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE=y > > >> CONFIG_PINCTRL=y > > >> CONFIG_PINCTRL_IMX7=y > > >> CONFIG_DM_PMIC=y > > >> diff --git a/configs/warp_defconfig b/configs/warp_defconfig index > > >> 7a6ea6f8c6..d719dc779a 100644 > > >> --- a/configs/warp_defconfig > > >> +++ b/configs/warp_defconfig > > >> @@ -31,6 +31,7 @@ CONFIG_ENV_IS_IN_MMC=y > > CONFIG_DFU_MMC=y > > >> CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y > > >> +CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE=y > > >> CONFIG_USB=y > > >> CONFIG_USB_STORAGE=y > > >> CONFIG_USB_GADGET=y > > >> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index > > >> 0ccb1ea701..f61b17b86b 100644 > > >> --- a/drivers/mmc/Kconfig > > >> +++ b/drivers/mmc/Kconfig > > >> @@ -701,6 +701,12 @@ config FSL_USDHC > > >> help > > >>This enables the Ultra Secured Digital Host Controller > > >> enhancements > > >> > > >> +config SYS_FSL_ESDHC_HAS_DDR_MODE > > >> +depends on FSL_ESDHC || FSL_ESDHC_IMX > > > > > > Please drop FSL_ESDHC. > > > > Why ? SYS_FSL_ESDHC_HAS_DDR_MODE is used in fsl_esdhc.c too. > > Y.b, is this currently used by fsl_esdhc.c? [Y.b. Lu] Yes. This was introduced before fsl_esdhc_imx.c was split out. The patch introducing it was as below. 0e1bf61 mmc: fsl_esdhc: Add support for DDR mode This was for i.mx eSDHC actually. I should remove SYS_FSL_ESDHC_HAS_DDR_MODE for fsl_esdhc.c. Although fsl_esdhc supports DDR52, the RCW (reset configure words) for SoC and FPGA should be configured accordingly (for SDHC_CLK_SYNC_OUT/IN signals) to support it. So let me send a patch to remove it. You can feel free to add it in your new version patch too. BTW, I think "mmc-ddr-1_8v" dts property is a good idea instead of config option. Thanks. > > Thanks, > Peng. > > > > > Regards, > > > > > > > > Regards, > > > Peng. > > > > > >> +bool "Enable Dual Data Rate support" > > >> +help > > >> + This enables Dual Data Rate support (DDR52) > > >> + > > >> endmenu > > >> > > >> config SYS_FSL_ERRATUM_ESDHC111 > > >> diff --git a/include/configs/warp.h b/include/configs/warp.h index > > >> 5345f5314d..a00c535b50 100644 > > >> --- a/include/configs/warp.h > > >> +++ b/include/configs/warp.h > > >> @@ -22,7 +22,6 @@ > > >> > > >> /* MMC Configs */ > > >> #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR > > >> -#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE > > >
Re: [U-Boot] [PATCH 0/3] mmc: fsl_esdhc: clean up code
Hi Peng, > -Original Message- > From: Peng Fan > Sent: Friday, September 6, 2019 10:12 AM > To: Y.b. Lu ; u-boot@lists.denx.de > Subject: RE: [PATCH 0/3] mmc: fsl_esdhc: clean up code > > > Subject: RE: [PATCH 0/3] mmc: fsl_esdhc: clean up code > > > > Any comments? > > Patchset break build https://travis-ci.org/MrVan/u-boot/jobs/581073165 > > Please take a look. [Y.b. Lu] Sorry. I hadn't seen this issue with my toolchain. I have reproduced with buildman. Let me send out v2 patch-set. The esdhc_ops declaration should be involved in non-DM conditional build. Thanks. > > Regards, > Peng. > > > Thanks:) > > > > > -Original Message- > > > From: Yangbo Lu > > > Sent: Monday, August 19, 2019 4:28 PM > > > To: u-boot@lists.denx.de; Peng Fan > > > Cc: Y.b. Lu > > > Subject: [PATCH 0/3] mmc: fsl_esdhc: clean up code > > > > > > This patch-set is to clean up fsl_esdhc code. > > > > > > Yangbo Lu (3): > > > mmc: fsl_esdhc: make BLK as hard requirement of DM_MMC > > > mmc: fsl_esdhc: clean up code > > > mmc: fsl_esdhc: rename fsl_esdhc_init to fsl_esdhc_get_cfg > > > > > > drivers/mmc/fsl_esdhc.c | 371 > > +++- > > > include/fsl_esdhc.h | 203 -- > > > 2 files changed, 240 insertions(+), 334 deletions(-) > > > > > > -- > > > 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 0/3] mmc: fsl_esdhc: clean up code
Any comments? Thanks:) > -Original Message- > From: Yangbo Lu > Sent: Monday, August 19, 2019 4:28 PM > To: u-boot@lists.denx.de; Peng Fan > Cc: Y.b. Lu > Subject: [PATCH 0/3] mmc: fsl_esdhc: clean up code > > This patch-set is to clean up fsl_esdhc code. > > Yangbo Lu (3): > mmc: fsl_esdhc: make BLK as hard requirement of DM_MMC > mmc: fsl_esdhc: clean up code > mmc: fsl_esdhc: rename fsl_esdhc_init to fsl_esdhc_get_cfg > > drivers/mmc/fsl_esdhc.c | 371 > +++- > include/fsl_esdhc.h | 203 -- > 2 files changed, 240 insertions(+), 334 deletions(-) > > -- > 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] mmc: fsl_esdhc: clean up code
Hi Lukasz,
Sorry for my late response. Please see my comments inline.
> -Original Message-
> From: Lukasz Majewski
> Sent: Friday, August 23, 2019 4:45 PM
> To: Y.b. Lu
> Cc: u-boot@lists.denx.de; Peng Fan
> Subject: Re: [U-Boot] [PATCH 2/3] mmc: fsl_esdhc: clean up code
>
> On Mon, 19 Aug 2019 16:27:49 +0800
> Yangbo Lu wrote:
>
> > /* Return the XFERTYP flags for a given command and data packet */
> > -static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
> > +static uint esdhc_setup_xfertyp(struct mmc_cmd *cmd, struct mmc_data
> > *data) {
> > uint xfertyp = 0;
> >
> > @@ -310,9 +310,9 @@ static int esdhc_setup_data(struct fsl_esdhc_priv
> > *priv, struct mmc *mmc, return 0;
> > }
> >
> > -static void check_and_invalidate_dcache_range
> > - (struct mmc_cmd *cmd,
> > -struct mmc_data *data) {
> > +static void esdhc_invalidate_dcache_range(struct mmc_cmd *cmd,
> > + struct mmc_data *data)
> - it shall be aligned
> with the (
[Y.b. Lu] Although it's not aligned with the ( in email, it's aligned after
applying the patch.
I believe there is no issue, and the checkpatch passed before I sent out the
patches.
Thanks.
>
> Could you double check this patch set with ./tools/checkpatch.py if it
> is clean?
>
> (You can also test tools/patman - which does automatic checkpatch check)
>
> > +{
>
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lu...@denx.de
___
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Re: [U-Boot] [v3, 5/5] mmc: fsl_esdhc_imx: drop useless code
Hi Angelo,
> -Original Message-
> From: Angelo Dureghello
> Sent: 2019年6月23日 5:43
> To: Y.b. Lu
> Cc: u-boot@lists.denx.de
> Subject: Re: [v3, 5/5] mmc: fsl_esdhc_imx: drop useless code
>
> Hi Lu,
>
> On Mon, Jun 03, 2019 at 04:28:24AM +, Y.b. Lu wrote:
> > Hi,
> >
> > > -Original Message-
> > > From: Angelo Dureghello
> > > Sent: 2019年5月31日 15:15
> > > To: Y.b. Lu
> > > Cc: u-boot@lists.denx.de
> > > Subject: Re: [v3, 5/5] mmc: fsl_esdhc_imx: drop useless code
> > >
> > > Hi Lu,
> > >
> > > On Fri, May 31, 2019 at 06:12:12AM +, Y.b. Lu wrote:
> > > > Hi Angelo,
> > > >
> > > > > -Original Message-
> > > > > From: Angelo Dureghello
> > > > > Sent: 2019年5月31日 2:23
> > > > > To: Y.b. Lu
> > > > > Cc: u-boot@lists.denx.de; Stefano Babic ; Fabio
> > > > > Estevam ; dl-uboot-imx
> ;
> > > > > Albert Aribaud ; Eddy Petrișor
> > > > > ; Akshay Bhat ;
> > > Ken
> > > > > Lin ; Heiko Schocher ;
> > > > > Christian Gmeiner ; Stefan Roese
> > > > > ; Patrick Bruenn ; Troy Kisky
> > > > > ; Uri Mashiach
> > > > > ; Nikita Kiryanov
> > > > > ; Otavio Salvador
> > > > > ; Andreas Geisreiter
> > > > > ; Ludwig Zenz
> > > > > ; Eric Bénard ; Peng
> > > > > Fan ; Jason Liu ; Ye Li
> > > > > ; Adrian Alonso ; Alison
> > > > > Wang ; thar...@gateworks.com; Ian Ray
> > > > > ; Marcin Niestroj ;
> > > > > Andrej Rosano ; Marek Vasut
> > > ;
> > > > > Lukasz Majewski ; Adam Ford
> ;
> > > > > Olaf Mandel ; Martyn Welch
> > > > > ; Ingo Schroeck
> > > ;
> > > > > Boris Brezillon ; Soeren
> > > > > Moch ; Richard Hu ;
> > > > > Vanessa Maegima ; Max Krummenacher
> > > > > ; Stefan Agner
> > > > > ; Markus Niebel
> > > > > ; Breno Matheus Lima
> > > > > ; Francesco Montefoschi
> > > > > ; Parthiban Nallathambi
> > > > > ; Albert ARIBAUD ;
> > > > > Jagan Teki ; Raffaele RECALCATI
> > > > > ; Simone CIANNI
> > > > > ; Bhaskar Upadhaya
> > > > > ; Vinitha V Pillai
> > > > > ; Prabhakar Kushwaha
> > > > > ; Rajesh Bhagat
> > > ;
> > > > > Antti Mäentausta ; Sébastien Szymanski
> > > > > ; Lucile Quirion
> > > > > ; Alexey Brodkin
> > > > > ; Trevor Woerner ;
> > > > > Anatolij Gustschin ; Denis Zalevskiy
> > > > > ; Fabien Lahoudere
> > > > > ; Joe Hershberger
> > > > > ; Simon Goldschmidt
> > > > > ; James Byrne
> > > > >
> > > > > Subject: Re: [v3, 5/5] mmc: fsl_esdhc_imx: drop useless code
> > > > >
> > > > > Hi Lu,
> > > > >
> > > > > On Tue, May 21, 2019 at 08:53:04AM +, Y.b. Lu wrote:
> > > > > > Dropped useless code for i.MX eSDHC driver.
> > > > > >
> > > > > > Signed-off-by: Yangbo Lu
> > > > > > ---
> > > > > > Changes for v2:
> > > > > > - Added this patch.
> > > > > > Changes for v3:
> > > > > > - None.
> > > > > > ---
> > > > > > drivers/mmc/fsl_esdhc_imx.c | 96
> > > > > > ++---
> > > > > > include/fsl_esdhc_imx.h | 4 --
> > > > > > 2 files changed, 4 insertions(+), 96 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/mmc/fsl_esdhc_imx.c
> > > > > > b/drivers/mmc/fsl_esdhc_imx.c index faf133390f..1c02e0eef1
> > > > > > 100644
> > > > > > --- a/drivers/mmc/fsl_esdhc_imx.c
> > > > > > +++ b/drivers/mmc/fsl_esdhc_imx.c
> > > > > > @@ -259,8 +259,7 @@ static int esdhc_setup_data(struct
> > > > > > fsl_esdhc_priv *priv, struct mmc *mmc, {
> > > > > > int timeout;
> > > > > > struct fsl_esdhc *regs = priv->esdhc_regs; -#if
> > > > > > defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
> > > > > > - defined(CONFIG_IMX8) || defined(CON
Re: [U-Boot] [v6, 5/5] mmc: fsl_esdhc_imx: drop useless code
> -Original Message-
> From: Y.b. Lu
> Sent: 2019年6月20日 11:34
> To: Lukasz Majewski
> Cc: u-boot@lists.denx.de; Stefano Babic ; Fabio Estevam
> ; dl-uboot-imx ; Albert Aribaud
> ; Eddy Petrișor ;
> Akshay Bhat ; Ken Lin
> ; Heiko Schocher ; Christian
> Gmeiner ; Stefan Roese ; Patrick
> Bruenn ; Troy Kisky
> ; Uri Mashiach
> ; Nikita Kiryanov ;
> Otavio Salvador ; Andreas Geisreiter
> ; Ludwig Zenz ;
> Peng Fan ; Jason Liu ; Ye Li
> ; Adrian Alonso ; Alison Wang
> ; thar...@gateworks.com; Ian Ray
> ; Marcin Niestroj ; Andrej
> Rosano ; Marek Vasut ; Adam
> Ford ; Olaf Mandel ;
> Martyn Welch ; Ingo Schroeck
> ; Soeren Moch ; Richard Hu
> ; Vanessa Maegima
> ; Max Krummenacher
> ; Stefan Agner
> ; Markus Niebel ;
> Breno Matheus Lima ; Francesco Montefoschi
> ; Parthiban Nallathambi
> ; Albert ARIBAUD ; Jagan
> Teki ; Raffaele RECALCATI
> ; Simone CIANNI ;
> Bhaskar Upadhaya ; Prabhakar Kushwaha
> ; Rajesh Bhagat ;
> Antti Mäentausta
> Subject: RE: [v6, 5/5] mmc: fsl_esdhc_imx: drop useless code
>
>
>
> > -Original Message-
> > From: Lukasz Majewski
> > Sent: 2019年6月19日 14:48
> > To: Y.b. Lu
> > Cc: u-boot@lists.denx.de; Stefano Babic ; Fabio
> > Estevam ; dl-uboot-imx ;
> Albert
> > Aribaud ; Eddy Petrișor
> > ; Akshay Bhat ; Ken
> > Lin ; Heiko Schocher ; Christian
> > Gmeiner ; Stefan Roese ;
> > Patrick Bruenn ; Troy Kisky
> > ; Uri Mashiach
> > ; Nikita Kiryanov
> > ; Otavio Salvador ;
> > Andreas Geisreiter ; Ludwig Zenz
> > ; Peng Fan ; Jason Liu
> > ; Ye Li ; Adrian Alonso
> > ; Alison Wang ;
> > thar...@gateworks.com; Ian Ray ; Marcin Niestroj
> > ; Andrej Rosano ;
> > Marek Vasut ; Adam Ford ; Olaf
> > Mandel ; Martyn Welch
> > ; Ingo Schroeck ;
> > Soeren Moch ; Richard Hu ;
> > Vanessa Maegima ; Max Krummenacher
> > ; Stefan Agner
> > ; Markus Niebel
> > ; Breno Matheus Lima
> ;
> > Francesco Montefoschi ; Parthiban
> > Nallathambi ; Albert ARIBAUD
> > ; Jagan Teki ;
> > Raffaele RECALCATI ; Simone CIANNI
> > ; Bhaskar Upadhaya
> > ; Prabhakar Kushwaha
> > ; Rajesh Bhagat ;
> > Antti Mäentausta
> > Subject: Re: [v6, 5/5] mmc: fsl_esdhc_imx: drop useless code
> >
> > On Wed, 19 Jun 2019 12:24:30 +0800
> > Yangbo Lu wrote:
> >
> > > Dropped useless code for i.MX eSDHC driver.
> > >
> > > Signed-off-by: Yangbo Lu
> > > Tested-by: Steffen Dirkwinkel
> > > Reviewed-by: Peng Fan
> > > ---
> > > Changes for v2:
> > > - Added this patch.
> > > Changes for v3:
> > > - None.
> > > Changes for v4:
> > > - Dropped PPC code introduced recently.
> > > Changes for v5:
> > > - Kept MCF5441x code.
> > > Changes for v6:
> > > - None.
> > > ---
> > > drivers/mmc/fsl_esdhc_imx.c | 65
> > > +++--
> > > include/fsl_esdhc_imx.h | 4 --- 2 files changed, 4
> > > insertions(+), 65 deletions(-)
> > >
> > > diff --git a/drivers/mmc/fsl_esdhc_imx.c
> > > b/drivers/mmc/fsl_esdhc_imx.c index 1474e2c..2c0ad18 100644
> > > --- a/drivers/mmc/fsl_esdhc_imx.c
> > > +++ b/drivers/mmc/fsl_esdhc_imx.c
> > > @@ -261,8 +261,7 @@ static int esdhc_setup_data(struct
> > > fsl_esdhc_priv *priv, struct mmc *mmc, {
> > > int timeout;
> > > struct fsl_esdhc *regs = priv->esdhc_regs; -#if
> > > defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
> > > - defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
> > > +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) ||
> > > defined(CONFIG_IMX8M) dma_addr_t addr; #endif
> > > uint wml_value;
> > > @@ -275,8 +274,7 @@ static int esdhc_setup_data(struct
> > > fsl_esdhc_priv *priv, struct mmc *mmc,
> > > esdhc_clrsetbits32(>wml, WML_RD_WML_MASK,
> wml_value);
> > #ifndef
> > > CONFIG_SYS_FSL_ESDHC_USE_PIO -#if defined(CONFIG_FSL_LAYERSCAPE)
> ||
> > > defined(CONFIG_S32V234) || \
> > > - defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
> > > +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) ||
> > > defined(CONFIG_IMX8M) addr = virt_to_phys((void *)(data->dest));
> > > if (upper_32_bits(addr))
> > > printf("Error found for upper 32 bits\n"); @@ -312,8
> +310,7
> > @@
> > > static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc
> > &
Re: [U-Boot] [v6, 5/5] mmc: fsl_esdhc_imx: drop useless code
> -Original Message-
> From: Lukasz Majewski
> Sent: 2019年6月19日 14:48
> To: Y.b. Lu
> Cc: u-boot@lists.denx.de; Stefano Babic ; Fabio Estevam
> ; dl-uboot-imx ; Albert Aribaud
> ; Eddy Petrișor ;
> Akshay Bhat ; Ken Lin
> ; Heiko Schocher ; Christian
> Gmeiner ; Stefan Roese ; Patrick
> Bruenn ; Troy Kisky
> ; Uri Mashiach
> ; Nikita Kiryanov ;
> Otavio Salvador ; Andreas Geisreiter
> ; Ludwig Zenz ;
> Peng Fan ; Jason Liu ; Ye Li
> ; Adrian Alonso ; Alison Wang
> ; thar...@gateworks.com; Ian Ray
> ; Marcin Niestroj ; Andrej
> Rosano ; Marek Vasut ; Adam
> Ford ; Olaf Mandel ;
> Martyn Welch ; Ingo Schroeck
> ; Soeren Moch ; Richard Hu
> ; Vanessa Maegima
> ; Max Krummenacher
> ; Stefan Agner
> ; Markus Niebel ;
> Breno Matheus Lima ; Francesco Montefoschi
> ; Parthiban Nallathambi
> ; Albert ARIBAUD ; Jagan
> Teki ; Raffaele RECALCATI
> ; Simone CIANNI ;
> Bhaskar Upadhaya ; Prabhakar Kushwaha
> ; Rajesh Bhagat ;
> Antti Mäentausta
> Subject: Re: [v6, 5/5] mmc: fsl_esdhc_imx: drop useless code
>
> On Wed, 19 Jun 2019 12:24:30 +0800
> Yangbo Lu wrote:
>
> > Dropped useless code for i.MX eSDHC driver.
> >
> > Signed-off-by: Yangbo Lu
> > Tested-by: Steffen Dirkwinkel
> > Reviewed-by: Peng Fan
> > ---
> > Changes for v2:
> > - Added this patch.
> > Changes for v3:
> > - None.
> > Changes for v4:
> > - Dropped PPC code introduced recently.
> > Changes for v5:
> > - Kept MCF5441x code.
> > Changes for v6:
> > - None.
> > ---
> > drivers/mmc/fsl_esdhc_imx.c | 65
> > +++--
> > include/fsl_esdhc_imx.h | 4 --- 2 files changed, 4
> > insertions(+), 65 deletions(-)
> >
> > diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
> > index 1474e2c..2c0ad18 100644
> > --- a/drivers/mmc/fsl_esdhc_imx.c
> > +++ b/drivers/mmc/fsl_esdhc_imx.c
> > @@ -261,8 +261,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv
> > *priv, struct mmc *mmc, {
> > int timeout;
> > struct fsl_esdhc *regs = priv->esdhc_regs; -#if
> > defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
> > - defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
> > +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) ||
> > defined(CONFIG_IMX8M) dma_addr_t addr; #endif
> > uint wml_value;
> > @@ -275,8 +274,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv
> > *priv, struct mmc *mmc,
> > esdhc_clrsetbits32(>wml, WML_RD_WML_MASK, wml_value);
> #ifndef
> > CONFIG_SYS_FSL_ESDHC_USE_PIO -#if defined(CONFIG_FSL_LAYERSCAPE) ||
> > defined(CONFIG_S32V234) || \
> > - defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
> > +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) ||
> > defined(CONFIG_IMX8M) addr = virt_to_phys((void *)(data->dest));
> > if (upper_32_bits(addr))
> > printf("Error found for upper 32 bits\n"); @@ -312,8
> > +310,7
> @@
> > static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc
> > *mmc, esdhc_clrsetbits32(>wml, WML_WR_WML_MASK, wml_value
> <<
> > 16); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO -#if
> > defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
> > - defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
> > +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) ||
> > defined(CONFIG_IMX8M) addr = virt_to_phys((void *)(data->src));
> > if (upper_32_bits(addr))
> > printf("Error found for upper 32 bits\n"); @@ -378,8
> > +375,7
> @@
> > static void check_and_invalidate_dcache_range
> > unsigned end = 0;
> > unsigned size = roundup(ARCH_DMA_MINALIGN,
> > data->blocks*data->blocksize);
> > -#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
> > - defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
> > +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) ||
> > defined(CONFIG_IMX8M) dma_addr_t addr;
> >
> > addr = virt_to_phys((void *)(data->dest)); @@ -1364,45 +1360,6 @@
> > int fsl_esdhc_mmc_init(bd_t *bis) } #endif
> >
> > -#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT -void
> > mmc_adapter_card_type_ident(void) -{
> > - u8 card_id;
> > - u8 value;
> > -
> > - card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
> > - gd->arch.sdhc_adapter = card_id;
> > -
> > - switch (card_id) {
> > - case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45
Re: [U-Boot] [v3, 5/5] mmc: fsl_esdhc_imx: drop useless code
Hi,
> -Original Message-
> From: Angelo Dureghello
> Sent: 2019年5月31日 15:15
> To: Y.b. Lu
> Cc: u-boot@lists.denx.de
> Subject: Re: [v3, 5/5] mmc: fsl_esdhc_imx: drop useless code
>
> Hi Lu,
>
> On Fri, May 31, 2019 at 06:12:12AM +, Y.b. Lu wrote:
> > Hi Angelo,
> >
> > > -Original Message-
> > > From: Angelo Dureghello
> > > Sent: 2019年5月31日 2:23
> > > To: Y.b. Lu
> > > Cc: u-boot@lists.denx.de; Stefano Babic ; Fabio
> > > Estevam ; dl-uboot-imx ;
> > > Albert Aribaud ; Eddy Petrișor
> > > ; Akshay Bhat ;
> Ken
> > > Lin ; Heiko Schocher ;
> > > Christian Gmeiner ; Stefan Roese
> > > ; Patrick Bruenn ; Troy Kisky
> > > ; Uri Mashiach
> > > ; Nikita Kiryanov
> > > ; Otavio Salvador ;
> > > Andreas Geisreiter ; Ludwig Zenz
> > > ; Eric Bénard ; Peng Fan
> > > ; Jason Liu ; Ye Li
> > > ; Adrian Alonso ; Alison Wang
> > > ; thar...@gateworks.com; Ian Ray
> > > ; Marcin Niestroj ;
> > > Andrej Rosano ; Marek Vasut
> ;
> > > Lukasz Majewski ; Adam Ford ;
> > > Olaf Mandel ; Martyn Welch
> > > ; Ingo Schroeck
> ;
> > > Boris Brezillon ; Soeren Moch
> > > ; Richard Hu ; Vanessa
> > > Maegima ; Max Krummenacher
> > > ; Stefan Agner
> > > ; Markus Niebel
> > > ; Breno Matheus Lima
> > > ; Francesco Montefoschi
> > > ; Parthiban Nallathambi
> > > ; Albert ARIBAUD ;
> > > Jagan Teki ; Raffaele RECALCATI
> > > ; Simone CIANNI
> > > ; Bhaskar Upadhaya
> > > ; Vinitha V Pillai
> > > ; Prabhakar Kushwaha
> > > ; Rajesh Bhagat
> ;
> > > Antti Mäentausta ; Sébastien Szymanski
> > > ; Lucile Quirion
> > > ; Alexey Brodkin
> > > ; Trevor Woerner ;
> > > Anatolij Gustschin ; Denis Zalevskiy
> > > ; Fabien Lahoudere
> > > ; Joe Hershberger
> > > ; Simon Goldschmidt
> > > ; James Byrne
> > >
> > > Subject: Re: [v3, 5/5] mmc: fsl_esdhc_imx: drop useless code
> > >
> > > Hi Lu,
> > >
> > > On Tue, May 21, 2019 at 08:53:04AM +, Y.b. Lu wrote:
> > > > Dropped useless code for i.MX eSDHC driver.
> > > >
> > > > Signed-off-by: Yangbo Lu
> > > > ---
> > > > Changes for v2:
> > > > - Added this patch.
> > > > Changes for v3:
> > > > - None.
> > > > ---
> > > > drivers/mmc/fsl_esdhc_imx.c | 96 ++---
> > > > include/fsl_esdhc_imx.h | 4 --
> > > > 2 files changed, 4 insertions(+), 96 deletions(-)
> > > >
> > > > diff --git a/drivers/mmc/fsl_esdhc_imx.c
> > > > b/drivers/mmc/fsl_esdhc_imx.c index faf133390f..1c02e0eef1 100644
> > > > --- a/drivers/mmc/fsl_esdhc_imx.c
> > > > +++ b/drivers/mmc/fsl_esdhc_imx.c
> > > > @@ -259,8 +259,7 @@ static int esdhc_setup_data(struct
> > > > fsl_esdhc_priv *priv, struct mmc *mmc, {
> > > > int timeout;
> > > > struct fsl_esdhc *regs = priv->esdhc_regs; -#if
> > > > defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
> > > > - defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
> > > > +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) ||
> > > > +defined(CONFIG_IMX8M)
> > > > dma_addr_t addr;
> > > > #endif
> > > > uint wml_value;
> > > > @@ -273,8 +272,7 @@ static int esdhc_setup_data(struct
> > > > fsl_esdhc_priv *priv, struct mmc *mmc,
> > > >
> > > > esdhc_clrsetbits32(>wml, WML_RD_WML_MASK,
> wml_value);
> > > > #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO -#if
> > > > defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
> > > > - defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
> > > > +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) ||
> > > > +defined(CONFIG_IMX8M)
> > > > addr = virt_to_phys((void *)(data->dest));
> > > > if (upper_32_bits(addr))
> > > > printf("Error found for upper 32 bits\n"); @@
> > > > -310,8
> +308,7
> > > @@
> > > > static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc
> *mmc,
> > > > esdhc_clrsetbits32(>wml, WML_WR_WML_MASK,
> > > >
Re: [U-Boot] [v3, 5/5] mmc: fsl_esdhc_imx: drop useless code
Hi Angelo,
> -Original Message-
> From: Angelo Dureghello
> Sent: 2019年5月31日 2:23
> To: Y.b. Lu
> Cc: u-boot@lists.denx.de; Stefano Babic ; Fabio Estevam
> ; dl-uboot-imx ; Albert Aribaud
> ; Eddy Petrișor ;
> Akshay Bhat ; Ken Lin
> ; Heiko Schocher ; Christian
> Gmeiner ; Stefan Roese ; Patrick
> Bruenn ; Troy Kisky
> ; Uri Mashiach
> ; Nikita Kiryanov ;
> Otavio Salvador ; Andreas Geisreiter
> ; Ludwig Zenz ; Eric
> Bénard ; Peng Fan ; Jason Liu
> ; Ye Li ; Adrian Alonso
> ; Alison Wang ;
> thar...@gateworks.com; Ian Ray ; Marcin Niestroj
> ; Andrej Rosano ;
> Marek Vasut ; Lukasz Majewski ; Adam
> Ford ; Olaf Mandel ;
> Martyn Welch ; Ingo Schroeck
> ; Boris Brezillon
> ; Soeren Moch ;
> Richard Hu ; Vanessa Maegima
> ; Max Krummenacher
> ; Stefan Agner
> ; Markus Niebel ;
> Breno Matheus Lima ; Francesco Montefoschi
> ; Parthiban Nallathambi
> ; Albert ARIBAUD ; Jagan
> Teki ; Raffaele RECALCATI
> ; Simone CIANNI ;
> Bhaskar Upadhaya ; Vinitha V Pillai
> ; Prabhakar Kushwaha
> ; Rajesh Bhagat ;
> Antti Mäentausta ; Sébastien Szymanski
> ; Lucile Quirion
> ; Alexey Brodkin
> ; Trevor Woerner ;
> Anatolij Gustschin ; Denis Zalevskiy
> ; Fabien Lahoudere
> ; Joe Hershberger
> ; Simon Goldschmidt
> ; James Byrne
>
> Subject: Re: [v3, 5/5] mmc: fsl_esdhc_imx: drop useless code
>
> Hi Lu,
>
> On Tue, May 21, 2019 at 08:53:04AM +, Y.b. Lu wrote:
> > Dropped useless code for i.MX eSDHC driver.
> >
> > Signed-off-by: Yangbo Lu
> > ---
> > Changes for v2:
> > - Added this patch.
> > Changes for v3:
> > - None.
> > ---
> > drivers/mmc/fsl_esdhc_imx.c | 96 ++---
> > include/fsl_esdhc_imx.h | 4 --
> > 2 files changed, 4 insertions(+), 96 deletions(-)
> >
> > diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
> > index faf133390f..1c02e0eef1 100644
> > --- a/drivers/mmc/fsl_esdhc_imx.c
> > +++ b/drivers/mmc/fsl_esdhc_imx.c
> > @@ -259,8 +259,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv
> > *priv, struct mmc *mmc, {
> > int timeout;
> > struct fsl_esdhc *regs = priv->esdhc_regs; -#if
> > defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
> > - defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
> > +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) ||
> > +defined(CONFIG_IMX8M)
> > dma_addr_t addr;
> > #endif
> > uint wml_value;
> > @@ -273,8 +272,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv
> > *priv, struct mmc *mmc,
> >
> > esdhc_clrsetbits32(>wml, WML_RD_WML_MASK, wml_value);
> > #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO -#if
> > defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
> > - defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
> > +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) ||
> > +defined(CONFIG_IMX8M)
> > addr = virt_to_phys((void *)(data->dest));
> > if (upper_32_bits(addr))
> > printf("Error found for upper 32 bits\n"); @@ -310,8
> > +308,7
> @@
> > static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
> > esdhc_clrsetbits32(>wml, WML_WR_WML_MASK,
> > wml_value << 16);
> > #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
> > -#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
> > - defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
> > +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) ||
> > +defined(CONFIG_IMX8M)
> > addr = virt_to_phys((void *)(data->src));
> > if (upper_32_bits(addr))
> > printf("Error found for upper 32 bits\n"); @@ -376,8
> > +373,7
> @@
> > static void check_and_invalidate_dcache_range
> > unsigned end = 0;
> > unsigned size = roundup(ARCH_DMA_MINALIGN,
> > data->blocks*data->blocksize);
> > -#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
> > - defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
> > +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) ||
> > +defined(CONFIG_IMX8M)
> > dma_addr_t addr;
> >
> > addr = virt_to_phys((void *)(data->dest)); @@ -392,25 +388,6 @@
> > static void check_and_invalidate_dcache_range
> > invalidate_dcache_range(start, end); }
> >
> > -#ifdef CONFIG_MCF5441x
> > -/*
> > - * Swaps 32-bit words to little-endian byte order.
> > - */
&
Re: [U-Boot] [v4, 0/5] Split fsl_esdhc driver for i.MX
Hi Lukasz, > -Original Message- > From: Lukasz Majewski > Sent: 2019年5月29日 20:54 > To: Y.b. Lu > Cc: u-boot@lists.denx.de; Stefano Babic ; Fabio Estevam > ; dl-uboot-imx ; Albert Aribaud > ; Eddy Petrișor ; > Akshay Bhat ; Ken Lin > ; Heiko Schocher ; Christian > Gmeiner ; Stefan Roese ; Patrick > Bruenn ; Troy Kisky > ; Uri Mashiach > ; Nikita Kiryanov ; > Otavio Salvador ; Andreas Geisreiter > ; Ludwig Zenz ; > Peng Fan ; Jason Liu ; Ye Li > ; Adrian Alonso ; Alison Wang > ; thar...@gateworks.com; Ian Ray > ; Marcin Niestroj ; Andrej > Rosano ; Marek Vasut ; Adam > Ford ; Olaf Mandel ; > Martyn Welch ; Ingo Schroeck > ; Soeren Moch ; Richard Hu > ; Vanessa Maegima > ; Max Krummenacher > ; Stefan Agner > ; Markus Niebel ; > Breno Matheus Lima ; Francesco Montefoschi > ; Parthiban Nallathambi > ; Albert ARIBAUD ; Jagan > Teki ; Raffaele RECALCATI > ; Simone CIANNI ; > Bhaskar Upadhaya ; Prabhakar Kushwaha > ; Rajesh Bhagat ; > Antti Mäentausta ; Sébastien Szymanski > ; Lucile Quirion > ; Alexey Brodkin > ; Trevor Woerner ; > Anatolij Gustschin ; Denis Zalevskiy > ; Fabien Lahoudere > ; Joe Hershberger > ; Simon Goldschmidt > ; James Byrne > ; Angelo Dureghello > Subject: Re: [v4, 0/5] Split fsl_esdhc driver for i.MX > > Hi "Y.b. Lu", > > > The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX > > initially. The later QoriQ series PowerPC processors (which were > > evolutions of MPC83XX/MPC85XX), QorIQ series ARM processors, and i.MX > > series processors were using this driver for their eSDHCs too. > > > > For the two series processors, the eSDHCs are becoming more and more > > different. We should have split it into two drivers, like them > > (sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel. > > > > It's ideal to keep common part for reusing. However, it's hard to find > > out a little which could be reused. The truth is there will be more > > and more different registers, bits and operatiing processes. > > Even some code is common now, it may have to be split in the future. > > So let's just split is as two drivers. > > > > Patch #2 just created a fsl_esdhc_imx driver which was a copy of > > fsl_esdhc driver for i.MX processors. > > Patch #3 converted i.MX platforms to use fsl_esdhc_imx. > > Patch #4 and #5 just dropped useless code for the two driver. > > There are still many cleaning up works needed to be done in the > > future, because the eSDHC driver is mess for a long time. > > Since I'm only owner for QorIQ eSDHC driver, I dropped only a little > > things which I'm sure for fsl_esdhc_imx. Let i.MX eSDHC owner do > > futhur cleaning up. > > I also guess that this series passes without any issues the travis-CI tests? > > (e.g. https://travis-ci.org/lmajewski/u-boot-dfu/builds) [Y.b. Lu] I didn’t know Travis-CI. It seems interesting. I had set up it for building. Hope there will be result tomorrow. https://travis-ci.org/yangbolu1991/u-boot-test/builds/539118619 > > > > > Yangbo Lu (5): > > Move CONFIG_FSL_ESDHC to defconfig > > mmc: split fsl_esdhc driver for i.MX > > Convert to use fsl_esdhc_imx for i.MX platforms > > mmc: fsl_esdhc: drop i.MX code > > mmc: fsl_esdhc_imx: drop useless code > > > > arch/arm/cpu/arm1136/mx35/generic.c | 10 +- > > arch/arm/cpu/arm926ejs/mx25/generic.c | 8 +- > > arch/arm/cpu/armv7/vf610/generic.c| 10 +- > > arch/arm/cpu/armv8/s32v234/generic.c | 2 +- > > arch/arm/include/asm/global_data.h| 2 +- > > arch/arm/mach-imx/cpu.c | 6 +- > > arch/arm/mach-imx/mx6/litesom.c | 4 +- > > arch/arm/mach-imx/mx7/clock.c | 4 +- > > arch/arm/mach-imx/mx7ulp/clock.c | 2 +- > > arch/arm/mach-imx/speed.c | 4 +- > > board/advantech/dms-ba16/dms-ba16.c | 4 +- > > board/aristainetos/aristainetos-v1.c | 2 +- > > board/aristainetos/aristainetos-v2.c | 2 +- > > board/aristainetos/aristainetos.c | 4 +- > > board/bachmann/ot1200/ot1200.c| 2 +- > > board/barco/platinum/platinum.c | 2 +- > > board/barco/titanium/titanium.c | 4 +- > > board/boundary/nitrogen6x/nitrogen6x.c| 4 +- > > board/ccv/xpress/xpress.c | 2 +- > > board/compulab/cl-som-imx7/cl-som-imx7.c | 6 +- > > board/compulab/cl-som-imx7/common.c | 6 +- > > board/compulab/cl-som-imx7/c
Re: [U-Boot] [v3, 2/5] mmc: split fsl_esdhc driver for i.MX
> -Original Message-
> From: Y.b. Lu
> Sent: 2019年5月29日 15:10
> To: Lukasz Majewski
> Cc: u-boot@lists.denx.de; Stefano Babic ; Fabio Estevam
> ; dl-uboot-imx ; Albert Aribaud
> ; Eddy Petrișor ;
> Akshay Bhat ; Ken Lin
> ; Heiko Schocher ; Christian
> Gmeiner ; Stefan Roese ; Patrick
> Bruenn ; Troy Kisky
> ; Uri Mashiach
> ; Nikita Kiryanov ;
> Otavio Salvador ; Andreas Geisreiter
> ; Ludwig Zenz ;
> Peng Fan ; Jason Liu ; Ye Li
> ; Adrian Alonso ; Alison Wang
> ; thar...@gateworks.com; Ian Ray
> ; Marcin Niestroj ; Andrej
> Rosano ; Marek Vasut ; Adam
> Ford ; Olaf Mandel ;
> Martyn Welch ; Ingo Schroeck
> ; Soeren Moch ; Richard Hu
> ; Vanessa Maegima
> ; Max Krummenacher
> ; Stefan Agner
> ; Markus Niebel ;
> Breno Matheus Lima ; Francesco Montefoschi
> ; Parthiban Nallathambi
> ; Albert ARIBAUD ; Jagan
> Teki ; Raffaele RECALCATI
> ; Simone CIANNI ;
> Bhaskar Upadhaya ; Prabhakar Kushwaha
> ; Rajesh Bhagat ;
> Antti Mäentausta ; Sébastien Szymanski
> ; Lucile Quirion
> ; Alexey Brodkin
> ; Trevor Woerner ;
> Anatolij Gustschin ; Denis Zalevskiy
> ; Fabien Lahoudere
> ; Joe Hershberger
> ; Simon Goldschmidt
> ; James Byrne
> ; Angelo Dureghello
> Subject: RE: [v3, 2/5] mmc: split fsl_esdhc driver for i.MX
>
> > -Original Message-
> > From: Lukasz Majewski
> > Sent: 2019年5月29日 14:30
> > To: Y.b. Lu
> > Cc: u-boot@lists.denx.de; Stefano Babic ; Fabio
> > Estevam ; dl-uboot-imx ;
> Albert
> > Aribaud ; Eddy Petrișor
> > ; Akshay Bhat ; Ken
> > Lin ; Heiko Schocher ; Christian
> > Gmeiner ; Stefan Roese ;
> > Patrick Bruenn ; Troy Kisky
> > ; Uri Mashiach
> > ; Nikita Kiryanov
> > ; Otavio Salvador ;
> > Andreas Geisreiter ; Ludwig Zenz
> > ; Eric Bénard ; Peng Fan
> > ; Jason Liu ; Ye Li
> > ; Adrian Alonso ; Alison Wang
> > ; thar...@gateworks.com; Ian Ray
> > ; Marcin Niestroj ;
> > Andrej Rosano ; Marek Vasut ;
> > Adam Ford ; Olaf Mandel
> > ; Martyn Welch
> > ; Ingo Schroeck ;
> > Boris Brezillon ; Soeren Moch
> > ; Richard Hu ; Vanessa
> > Maegima ; Max Krummenacher
> > ; Stefan Agner
> > ; Markus Niebel
> > ; Breno Matheus Lima
> ;
> > Francesco Montefoschi ; Parthiban
> > Nallathambi ; Albert ARIBAUD
> > ; Jagan Teki ;
> > Raffaele RECALCATI ; Simone CIANNI
> > ; Bhaskar Upadhaya
> > ; Vinitha V Pillai ;
> > Prabhakar Kushwaha ; Rajesh Bhagat
> > ; Antti Mäentausta ;
> > Sébastien Szymanski ; Lucile Quirion
> > ; Alexey Brodkin
> > ; Trevor Woerner ;
> > Anatolij Gustschin ; Denis Zalevskiy
> > ; Fabien Lahoudere
> > ; Joe Hershberger
> > ; Simon Goldschmidt
> > ; James Byrne
> > ; Angelo Dureghello
> > Subject: Re: [v3, 2/5] mmc: split fsl_esdhc driver for i.MX
> >
> > Hi Y.b. Lu,
> >
> > > The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
> > > initially. The later QoriQ series PowerPC processors (which were
> > > evolutions of MPC83XX/MPC85XX), QorIQ series ARM processors, and
> > > i.MX series processors were using this driver for their eSDHCs too.
> > >
> > > For the two series processors, the eSDHCs are becoming more and more
> > > different. We should have split it into two drivers, like them
> > > (sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel.
> > >
> > > This patch is just to create a fsl_esdhc_imx driver which is a copy
> > > of fsl_esdhc driver for i.MX processors. We will convert i.MX
> > > processors to use fsl_esdhc_imx, and clean up the two drivers
> > > separately in the future patches.
> > >
> > > Signed-off-by: Yangbo Lu
> > > ---
> > > Changes for v2:
> > > - None.
> > > Changes for v3:
> > > - None.
> > > ---
> > > drivers/mmc/Kconfig | 6 ++
> > > drivers/mmc/Makefile | 1 +
> > > drivers/mmc/{fsl_esdhc.c => fsl_esdhc_imx.c} | 5 +++--
> > > include/{fsl_esdhc.h => fsl_esdhc_imx.h} | 11 ++-
> > > 4 files changed, 16 insertions(+), 7 deletions(-) copy
> > > drivers/mmc/{fsl_esdhc.c => fsl_esdhc_imx.c} (99%) copy
> > > include/{fsl_esdhc.h => fsl_esdhc_imx.h} (97%)
> > >
> > > diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index
> > > c23299ea96..4e33fa1b2d 100644
> > > --- a/drivers/mmc/Kconfig
> > > +++ b/drivers/mmc/Kconfig
> > > @@ -671,6 +671,12 @@ config FSL_ESDHC
> > > This
[U-Boot] [v4, 5/5] mmc: fsl_esdhc_imx: drop useless code
Dropped useless code for i.MX eSDHC driver.
Signed-off-by: Yangbo Lu
Tested-by: Steffen Dirkwinkel
Reviewed-by: Peng Fan
---
Changes for v2:
- Added this patch.
Changes for v3:
- None.
Changes for v4:
- Dropped PPC code introduced recently.
---
drivers/mmc/fsl_esdhc_imx.c | 105 ++--
include/fsl_esdhc_imx.h | 4 --
2 files changed, 4 insertions(+), 105 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 1474e2cee9..11bff76ca3 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -261,8 +261,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
{
int timeout;
struct fsl_esdhc *regs = priv->esdhc_regs;
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
dma_addr_t addr;
#endif
uint wml_value;
@@ -275,8 +274,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
esdhc_clrsetbits32(>wml, WML_RD_WML_MASK, wml_value);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
addr = virt_to_phys((void *)(data->dest));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -312,8 +310,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
esdhc_clrsetbits32(>wml, WML_WR_WML_MASK,
wml_value << 16);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
addr = virt_to_phys((void *)(data->src));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -378,8 +375,7 @@ static void check_and_invalidate_dcache_range
unsigned end = 0;
unsigned size = roundup(ARCH_DMA_MINALIGN,
data->blocks*data->blocksize);
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
dma_addr_t addr;
addr = virt_to_phys((void *)(data->dest));
@@ -394,25 +390,6 @@ static void check_and_invalidate_dcache_range
invalidate_dcache_range(start, end);
}
-#ifdef CONFIG_MCF5441x
-/*
- * Swaps 32-bit words to little-endian byte order.
- */
-static inline void sd_swap_dma_buff(struct mmc_data *data)
-{
- int i, size = data->blocksize >> 2;
- u32 *buffer = (u32 *)data->dest;
- u32 sw;
-
- while (data->blocks--) {
- for (i = 0; i < size; i++) {
- sw = __sw32(*buffer);
- *buffer++ = sw;
- }
- }
-}
-#endif
-
/*
* Sends a command out on the bus. Takes the mmc pointer,
* a command pointer, and an optional data pointer.
@@ -577,9 +554,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc,
*/
if (data->flags & MMC_DATA_READ) {
check_and_invalidate_dcache_range(cmd, data);
-#ifdef CONFIG_MCF5441x
- sd_swap_dma_buff(data);
-#endif
}
#endif
}
@@ -1062,12 +1036,8 @@ static int esdhc_init_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc)
/* Disable the BRR and BWR bits in IRQSTAT */
esdhc_clrbits32(>irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
-#ifdef CONFIG_MCF5441x
- esdhc_write32(>proctl, PROCTL_INIT | PROCTL_D3CD);
-#else
/* Put the PROCTL reg back to the default */
esdhc_write32(>proctl, PROCTL_INIT);
-#endif
/* Set timout to the maximum value */
esdhc_clrsetbits32(>sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
@@ -1175,11 +1145,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
if (ret)
return ret;
-#ifdef CONFIG_MCF5441x
- /* ColdFire, using SDHC_DATA[3] for card detection */
- esdhc_write32(>proctl, PROCTL_INIT | PROCTL_D3CD);
-#endif
-
#ifndef CONFIG_FSL_USDHC
esdhc_setbits32(>sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
| SYSCTL_IPGEN | SYSCTL_CKEN);
@@ -1204,15 +1169,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
voltage_caps = 0;
caps = esdhc_read32(>hostcapblt);
-#ifdef CONFIG_MCF5441x
- /*
-* MCF5441x RM declares in more points that sdhc clock speed must
-* never
[U-Boot] [v4, 4/5] mmc: fsl_esdhc: drop i.MX code
Dropped i.MX code which couldn't be reused.
Signed-off-by: Yangbo Lu
Tested-by: Steffen Dirkwinkel
Acked-by: Peng Fan
---
Changes for v2:
- Added this patch.
Changes for v3:
- Rebased.
Changes for v4:
- Rebased.
- Added Tested-by/Acked-by.
---
drivers/mmc/fsl_esdhc.c | 586 ++--
include/fsl_esdhc.h | 57
2 files changed, 16 insertions(+), 627 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 672691fa6a..450b0c8357 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -16,14 +16,11 @@
#include
#include
#include
-#include
#include
#include
#include
#include
#include
-#include
-#include
DECLARE_GLOBAL_DATA_PTR;
@@ -33,8 +30,6 @@ DECLARE_GLOBAL_DATA_PTR;
IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE
| \
IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR
| \
IRQSTATEN_DINT)
-#define MAX_TUNING_LOOP 40
-
struct fsl_esdhc {
uintdsaddr; /* SDMA system address register */
uintblkattr;/* Block attributes register */
@@ -54,37 +49,20 @@ struct fsl_esdhc {
uintautoc12err; /* Auto CMD error status register */
uinthostcapblt; /* Host controller capabilities register */
uintwml;/* Watermark level register */
- uintmixctrl;/* For USDHC */
- charreserved1[4]; /* reserved */
+ charreserved1[8]; /* reserved */
uintfevt; /* Force event register */
uintadmaes; /* ADMA error status register */
uintadsaddr;/* ADMA system address register */
- charreserved2[4];
- uintdllctrl;
- uintdllstat;
- uintclktunectrlstatus;
- charreserved3[4];
- uintstrobe_dllctrl;
- uintstrobe_dllstat;
- charreserved4[72];
- uintvendorspec;
- uintmmcboot;
- uintvendorspec2;
- uinttuning_ctrl;/* on i.MX6/7/8 */
- charreserved5[44];
+ charreserved2[160];
uinthostver;/* Host controller version register */
- charreserved6[4]; /* reserved */
+ charreserved3[4]; /* reserved */
uintdmaerraddr; /* DMA error address register */
- charreserved7[4]; /* reserved */
+ charreserved4[4]; /* reserved */
uintdmaerrattr; /* DMA error attribute register */
- charreserved8[4]; /* reserved */
+ charreserved5[4]; /* reserved */
uinthostcapblt2;/* Host controller capabilities register 2 */
- charreserved9[8]; /* reserved */
- uinttcr;/* Tuning control register */
- charreserved10[28]; /* reserved */
- uintsddirctl; /* SD direction control register */
- charreserved11[712];/* reserved */
- uintscr;/* eSDHC control register */
+ charreserved6[756]; /* reserved */
+ uintesdhcctl; /* eSDHC control register */
};
struct fsl_esdhc_plat {
@@ -92,11 +70,6 @@ struct fsl_esdhc_plat {
struct mmc mmc;
};
-struct esdhc_soc_data {
- u32 flags;
- u32 caps;
-};
-
/**
* struct fsl_esdhc_priv
*
@@ -109,13 +82,6 @@ struct esdhc_soc_data {
* @dev: pointer for the device
* @non_removable: 0: removable; 1: non-removable
* @wp_enable: 1: enable checking wp; 0: no check
- * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
- * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
- * @caps: controller capabilities
- * @tuning_step: tuning step setting in tuning_ctrl register
- * @start_tuning_tap: the start point for tuning in tuning_ctrl register
- * @strobe_dll_delay_target: settings in strobe_dllctrl
- * @signal_voltage: indicating the current voltage
* @cd_gpio: gpio for card detection
* @wp_gpio: gpio for write protection
*/
@@ -124,7 +90,6 @@ struct fsl_esdhc_priv {
unsigned int sdhc_clk;
struct clk per_clk;
unsigned int clock;
- unsigned int mode;
unsigned int bus_width;
#if !CONFIG_IS_ENABLED(BLK)
struct mmc *mmc;
@@ -132,21 +97,6 @@ struct fsl_esdhc_priv {
struct udevice *dev;
int non_removable;
int wp_enable;
- int vs18_enable;
- u32 flags;
- u32 caps;
- u32 tuning_step;
- u32 tuning_start_tap;
- u32 strobe_dll_delay_target;
- u32 signal_voltage;
-#if IS_ENABLED(CONFIG_DM_REGULATOR)
- struct udevice *vqmmc_dev;
- struct udevice *vmmc_dev;
-#endif
-#ifdef CONFIG_DM_GPIO
- struct gpio_desc cd_gpio;
- struct gpio_desc wp_gpio;
-#endif
};
/* Return the XFERTYP flags for a given command and data packet */
@@ -258,8 +208,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
[U-Boot] [v4, 1/5] Move CONFIG_FSL_ESDHC to defconfig
Moved CONFIG_FSL_ESDHC from header files to defconfig files. Signed-off-by: Yangbo Lu Tested-by: Steffen Dirkwinkel Reviewed-by: Peng Fan Reviewed-by: Lukasz Majewski Acked-by: Jason Liu --- Changes for v2: - Rebased. Changes for v3: - Rebased. Changes for v4: - Added Tested-by/Reviewed-by/Acked-by. --- configs/imx8mq_evk_defconfig | 1 + configs/imx8qm_mek_defconfig | 1 + configs/imx8qxp_mek_defconfig | 1 + configs/kp_imx6q_tpc_defconfig | 1 + configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1012afrwy_qspi_defconfig | 1 + configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1012afrwy_tfa_defconfig | 1 + include/configs/imx8mq_evk.h | 1 - include/configs/imx8qm_mek.h | 1 - include/configs/imx8qxp_mek.h | 1 - include/configs/kp_imx6q_tpc.h | 1 - include/configs/ls1012afrwy.h | 1 - 13 files changed, 8 insertions(+), 5 deletions(-) diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index bc84a66b5f..1c857bcc0b 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -31,6 +31,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_DM_ETH=y CONFIG_PINCTRL=y diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index 1c67b98c5d..f1155d6eea 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -52,6 +52,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ATHEROS=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index d735d34b8b..1ce175eec1 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -55,6 +55,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig index 0ca83cbfea..9b6ff4a85b 100644 --- a/configs/kp_imx6q_tpc_defconfig +++ b/configs/kp_imx6q_tpc_defconfig @@ -34,6 +34,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y CONFIG_FEC_MXC=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index bf98466576..0360d9d4e8 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -31,6 +31,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index aa3256fb43..08eedec827 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -32,6 +32,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index b0fdad6dd0..2c3d8931e7 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -31,6 +31,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index 6a70f5881b..19aae5aa1a 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -32,6 +32,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index e4fa2df342..16e4136fa9 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -216,7 +216,6 @@ #define CONFIG_IMX_BOOTAUX #define CONFIG_CMD_MMC -#define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 2bdf3be654..3679b487e1 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -47,7 +47,6 @@ #undef CONFIG_CMD_CRC32 #undef CONFIG_BOOTM_NETBSD -#define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR0x5B01 diff --git
[U-Boot] [v4, 2/5] mmc: split fsl_esdhc driver for i.MX
The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
initially. The later QoriQ series PowerPC processors (which were
evolutions of MPC83XX/MPC85XX), QorIQ series ARM processors, and
i.MX series processors were using this driver for their eSDHCs too.
For the two series processors, the eSDHCs are becoming more and
more different. We should have split it into two drivers, like them
(sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel.
This patch is just to create a fsl_esdhc_imx driver which is a copy
of fsl_esdhc driver for i.MX processors. We will convert i.MX processors
to use fsl_esdhc_imx, and clean up the two drivers separately in the
future patches.
Signed-off-by: Yangbo Lu
Tested-by: Steffen Dirkwinkel
Reviewed-by: Peng Fan
---
Changes for v2:
- None.
Changes for v3:
- None.
Changes for v4:
- Used "Enhanced Secure Digital Host" in Kconfig help.
- Moved copyright to top line and added my info.
- Added Tested-by/Reviewed-by.
---
drivers/mmc/Kconfig | 10 --
drivers/mmc/Makefile | 1 +
drivers/mmc/{fsl_esdhc.c => fsl_esdhc_imx.c} | 7 +--
include/{fsl_esdhc.h => fsl_esdhc_imx.h} | 13 -
4 files changed, 22 insertions(+), 9 deletions(-)
copy drivers/mmc/{fsl_esdhc.c => fsl_esdhc_imx.c} (99%)
copy include/{fsl_esdhc.h => fsl_esdhc_imx.h} (97%)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index c23299ea96..93588725f2 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -668,8 +668,14 @@ config TEGRA124_MMC_DISABLE_EXT_LOOPBACK
config FSL_ESDHC
bool "Freescale/NXP eSDHC controller support"
help
- This selects support for the eSDHC (enhanced secure digital host
- controller) found on numerous Freescale/NXP SoCs.
+ This selects support for the eSDHC (Enhanced Secure Digital Host
+ Controller) found on numerous Freescale/NXP SoCs.
+
+config FSL_ESDHC_IMX
+ bool "Freescale/NXP i.MX eSDHC controller support"
+ help
+ This selects support for the i.MX eSDHC (Enhanced Secure Digital Host
+ Controller) found on numerous Freescale/NXP SoCs.
endmenu
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 0076fc393b..3c8c53a9e1 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_MMC_DW_ROCKCHIP) += rockchip_dw_mmc.o
obj-$(CONFIG_MMC_DW_SOCFPGA) += socfpga_dw_mmc.o
obj-$(CONFIG_MMC_DW_SNPS) += snps_dw_mmc.o
obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
+obj-$(CONFIG_FSL_ESDHC_IMX) += fsl_esdhc_imx.o
obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
obj-$(CONFIG_MMC_MESON_GX) += meson_gx_mmc.o
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc_imx.c
similarity index 99%
copy from drivers/mmc/fsl_esdhc.c
copy to drivers/mmc/fsl_esdhc_imx.c
index 672691fa6a..1474e2cee9 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -1,5 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
+ * Copyright 2019 NXP
+ * Yangbo Lu
+ *
* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
* Andy Fleming
*
@@ -18,7 +21,7 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
@@ -110,7 +113,7 @@ struct esdhc_soc_data {
* @non_removable: 0: removable; 1: non-removable
* @wp_enable: 1: enable checking wp; 0: no check
* @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
- * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
+ * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
* @caps: controller capabilities
* @tuning_step: tuning step setting in tuning_ctrl register
* @start_tuning_tap: the start point for tuning in tuning_ctrl register
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc_imx.h
similarity index 97%
copy from include/fsl_esdhc.h
copy to include/fsl_esdhc_imx.h
index 8dbd5249a7..67fd28926e 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc_imx.h
@@ -3,11 +3,14 @@
* FSL SD/MMC Defines
*---
*
+ * Copyright 2019 NXP
+ * Yangbo Lu
+ *
* Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
*/
-#ifndef __FSL_ESDHC_H__
-#define__FSL_ESDHC_H__
+#ifndef __FSL_ESDHC_IMX_H__
+#define __FSL_ESDHC_IMX_H__
#include
#include
@@ -258,15 +261,15 @@ struct fsl_esdhc_cfg {
#error "Endianess is not defined: please fix to continue"
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
int fsl_esdhc_mmc_init(bd_t *bis);
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
void fdt_fixup_esdhc(void *blob, bd_t *bd);
#else
static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
void __noreturn mmc_boot(void);
void mmc_spl_load_image(uint32_t offs, unsigned
[U-Boot] [v4, 0/5] Split fsl_esdhc driver for i.MX
The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX initially. The later QoriQ series PowerPC processors (which were evolutions of MPC83XX/MPC85XX), QorIQ series ARM processors, and i.MX series processors were using this driver for their eSDHCs too. For the two series processors, the eSDHCs are becoming more and more different. We should have split it into two drivers, like them (sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel. It's ideal to keep common part for reusing. However, it's hard to find out a little which could be reused. The truth is there will be more and more different registers, bits and operatiing processes. Even some code is common now, it may have to be split in the future. So let's just split is as two drivers. Patch #2 just created a fsl_esdhc_imx driver which was a copy of fsl_esdhc driver for i.MX processors. Patch #3 converted i.MX platforms to use fsl_esdhc_imx. Patch #4 and #5 just dropped useless code for the two driver. There are still many cleaning up works needed to be done in the future, because the eSDHC driver is mess for a long time. Since I'm only owner for QorIQ eSDHC driver, I dropped only a little things which I'm sure for fsl_esdhc_imx. Let i.MX eSDHC owner do futhur cleaning up. Yangbo Lu (5): Move CONFIG_FSL_ESDHC to defconfig mmc: split fsl_esdhc driver for i.MX Convert to use fsl_esdhc_imx for i.MX platforms mmc: fsl_esdhc: drop i.MX code mmc: fsl_esdhc_imx: drop useless code arch/arm/cpu/arm1136/mx35/generic.c | 10 +- arch/arm/cpu/arm926ejs/mx25/generic.c | 8 +- arch/arm/cpu/armv7/vf610/generic.c| 10 +- arch/arm/cpu/armv8/s32v234/generic.c | 2 +- arch/arm/include/asm/global_data.h| 2 +- arch/arm/mach-imx/cpu.c | 6 +- arch/arm/mach-imx/mx6/litesom.c | 4 +- arch/arm/mach-imx/mx7/clock.c | 4 +- arch/arm/mach-imx/mx7ulp/clock.c | 2 +- arch/arm/mach-imx/speed.c | 4 +- board/advantech/dms-ba16/dms-ba16.c | 4 +- board/aristainetos/aristainetos-v1.c | 2 +- board/aristainetos/aristainetos-v2.c | 2 +- board/aristainetos/aristainetos.c | 4 +- board/bachmann/ot1200/ot1200.c| 2 +- board/barco/platinum/platinum.c | 2 +- board/barco/titanium/titanium.c | 4 +- board/boundary/nitrogen6x/nitrogen6x.c| 4 +- board/ccv/xpress/xpress.c | 2 +- board/compulab/cl-som-imx7/cl-som-imx7.c | 6 +- board/compulab/cl-som-imx7/common.c | 6 +- board/compulab/cl-som-imx7/common.h | 8 +- board/compulab/cl-som-imx7/mux.c | 8 +- board/compulab/cl-som-imx7/spl.c | 6 +- board/compulab/cm_fx6/cm_fx6.c| 4 +- board/compulab/cm_fx6/common.c| 4 +- board/compulab/cm_fx6/spl.c | 2 +- board/congatec/cgtqmx6eval/cgtqmx6eval.c | 4 +- board/dhelectronics/dh_imx6/dh_imx6.c | 4 +- board/dhelectronics/dh_imx6/dh_imx6_spl.c | 2 +- board/el/el6x/el6x.c | 4 +- board/embest/mx6boards/mx6boards.c| 4 +- board/freescale/imx8mq_evk/imx8mq_evk.c | 2 +- board/freescale/imx8mq_evk/spl.c | 2 +- board/freescale/imx8qxp_mek/imx8qxp_mek.c | 2 +- board/freescale/mx25pdk/mx25pdk.c | 6 +- board/freescale/mx35pdk/mx35pdk.c | 4 +- board/freescale/mx51evk/mx51evk.c | 6 +- board/freescale/mx53ard/mx53ard.c | 4 +- board/freescale/mx53evk/mx53evk.c | 4 +- board/freescale/mx53loco/mx53loco.c | 4 +- board/freescale/mx53smd/mx53smd.c | 4 +- board/freescale/mx6qarm2/mx6qarm2.c | 4 +- board/freescale/mx6sabreauto/mx6sabreauto.c | 4 +- board/freescale/mx6sabresd/mx6sabresd.c | 4 +- board/freescale/mx6slevk/mx6slevk.c | 2 +- .../freescale/mx6sxsabreauto/mx6sxsabreauto.c | 2 +- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 2 +- .../mx6ul_14x14_evk/mx6ul_14x14_evk.c | 4 +- board/freescale/mx6ullevk/mx6ullevk.c | 2 +- board/freescale/mx7dsabresd/mx7dsabresd.c | 2 +- board/freescale/s32v234evb/s32v234evb.c | 4 +- board/freescale/vf610twr/vf610twr.c | 4 +- board/gateworks/gw_ventana/common.c | 6 +- board/gateworks/gw_ventana/gw_ventana.c | 2 +- board/ge/bx50v3/bx50v3.c | 2 +- board/ge/mx53ppd/mx53ppd.c| 2 +- board/grinn/liteboard/board.c | 4 +- board/inversepath/usbarmory/usbarmory.c | 2 +- board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c | 4 +- board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c | 2 +- board/kosagi/novena/novena.c | 4 +- board/kosagi/novena/novena_spl.c | 6
Re: [U-Boot] [v3, 5/5] mmc: fsl_esdhc_imx: drop useless code
> -Original Message-
> From: Lukasz Majewski
> Sent: 2019年5月29日 14:43
> To: Y.b. Lu
> Cc: u-boot@lists.denx.de; Stefano Babic ; Fabio Estevam
> ; dl-uboot-imx ; Albert Aribaud
> ; Eddy Petrișor ;
> Akshay Bhat ; Ken Lin
> ; Heiko Schocher ; Christian
> Gmeiner ; Stefan Roese ; Patrick
> Bruenn ; Troy Kisky
> ; Uri Mashiach
> ; Nikita Kiryanov ;
> Otavio Salvador ; Andreas Geisreiter
> ; Ludwig Zenz ; Eric
> Bénard ; Peng Fan ; Jason Liu
> ; Ye Li ; Adrian Alonso
> ; Alison Wang ;
> thar...@gateworks.com; Ian Ray ; Marcin Niestroj
> ; Andrej Rosano ;
> Marek Vasut ; Adam Ford ; Olaf
> Mandel ; Martyn Welch
> ; Ingo Schroeck ;
> Boris Brezillon ; Soeren Moch
> ; Richard Hu ; Vanessa
> Maegima ; Max Krummenacher
> ; Stefan Agner
> ; Markus Niebel ;
> Breno Matheus Lima ; Francesco Montefoschi
> ; Parthiban Nallathambi
> ; Albert ARIBAUD ; Jagan
> Teki ; Raffaele RECALCATI
> ; Simone CIANNI ;
> Bhaskar Upadhaya ; Vinitha V Pillai
> ; Prabhakar Kushwaha
> ; Rajesh Bhagat ;
> Antti Mäentausta ; Sébastien Szymanski
> ; Lucile Quirion
> ; Alexey Brodkin
> ; Trevor Woerner ;
> Anatolij Gustschin ; Denis Zalevskiy
> ; Fabien Lahoudere
> ; Joe Hershberger
> ; Simon Goldschmidt
> ; James Byrne
> ; Angelo Dureghello
> Subject: Re: [v3, 5/5] mmc: fsl_esdhc_imx: drop useless code
>
> On Tue, 21 May 2019 08:53:04 +
> "Y.b. Lu" wrote:
>
> > Dropped useless code for i.MX eSDHC driver.
> >
> > Signed-off-by: Yangbo Lu
> > ---
> > Changes for v2:
> > - Added this patch.
> > Changes for v3:
> > - None.
> > ---
> > drivers/mmc/fsl_esdhc_imx.c | 96
> > ++--- include/fsl_esdhc_imx.h |
> > 4 -- 2 files changed, 4 insertions(+), 96 deletions(-)
> >
> > diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
> > index faf133390f..1c02e0eef1 100644
> > --- a/drivers/mmc/fsl_esdhc_imx.c
> > +++ b/drivers/mmc/fsl_esdhc_imx.c
> > @@ -259,8 +259,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv
> > *priv, struct mmc *mmc, {
> > int timeout;
> > struct fsl_esdhc *regs = priv->esdhc_regs; -#if
> > defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
> > - defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
> > +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) ||
> > defined(CONFIG_IMX8M) dma_addr_t addr; #endif
> > uint wml_value;
> > @@ -273,8 +272,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv
> > *priv, struct mmc *mmc,
> > esdhc_clrsetbits32(>wml, WML_RD_WML_MASK, wml_value);
> #ifndef
> > CONFIG_SYS_FSL_ESDHC_USE_PIO -#if defined(CONFIG_FSL_LAYERSCAPE) ||
> > defined(CONFIG_S32V234) || \
> > - defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
> > +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) ||
> > defined(CONFIG_IMX8M) addr = virt_to_phys((void *)(data->dest));
> > if (upper_32_bits(addr))
> > printf("Error found for upper 32 bits\n"); @@ -310,8
> > +308,7
> @@
> > static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc
> > *mmc, esdhc_clrsetbits32(>wml, WML_WR_WML_MASK, wml_value
> <<
> > 16); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO -#if
> > defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
> > - defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
> > +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) ||
> > defined(CONFIG_IMX8M) addr = virt_to_phys((void *)(data->src));
> > if (upper_32_bits(addr))
> > printf("Error found for upper 32 bits\n"); @@ -376,8
> > +373,7
> @@
> > static void check_and_invalidate_dcache_range
> > unsigned end = 0;
> > unsigned size = roundup(ARCH_DMA_MINALIGN,
> > data->blocks*data->blocksize);
> > -#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
> > - defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
> > +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) ||
> > defined(CONFIG_IMX8M) dma_addr_t addr;
> >
> > addr = virt_to_phys((void *)(data->dest)); @@ -392,25 +388,6 @@
> > static void check_and_invalidate_dcache_range
> > invalidate_dcache_range(start, end); }
> >
> > -#ifdef CONFIG_MCF5441x
> > -/*
> > - * Swaps 32-bit words to little-endian byte order.
> > - */
> > -static inline void sd_swap_dma_buff(struct mmc_data *data) -{
> > - int i, size = data->blocksize >> 2;
> > - u32
Re: [U-Boot] [v3, 4/5] mmc: fsl_esdhc: drop i.MX code
> -Original Message-
> From: Lukasz Majewski
> Sent: 2019年5月29日 14:40
> To: Y.b. Lu
> Cc: u-boot@lists.denx.de; Stefano Babic ; Fabio Estevam
> ; dl-uboot-imx ; Albert Aribaud
> ; Eddy Petrișor ;
> Akshay Bhat ; Ken Lin
> ; Heiko Schocher ; Christian
> Gmeiner ; Stefan Roese ; Patrick
> Bruenn ; Troy Kisky
> ; Uri Mashiach
> ; Nikita Kiryanov ;
> Otavio Salvador ; Andreas Geisreiter
> ; Ludwig Zenz ; Eric
> Bénard ; Peng Fan ; Jason Liu
> ; Ye Li ; Adrian Alonso
> ; Alison Wang ;
> thar...@gateworks.com; Ian Ray ; Marcin Niestroj
> ; Andrej Rosano ;
> Marek Vasut ; Adam Ford ; Olaf
> Mandel ; Martyn Welch
> ; Ingo Schroeck ;
> Boris Brezillon ; Soeren Moch
> ; Richard Hu ; Vanessa
> Maegima ; Max Krummenacher
> ; Stefan Agner
> ; Markus Niebel ;
> Breno Matheus Lima ; Francesco Montefoschi
> ; Parthiban Nallathambi
> ; Albert ARIBAUD ; Jagan
> Teki ; Raffaele RECALCATI
> ; Simone CIANNI ;
> Bhaskar Upadhaya ; Vinitha V Pillai
> ; Prabhakar Kushwaha
> ; Rajesh Bhagat ;
> Antti Mäentausta ; Sébastien Szymanski
> ; Lucile Quirion
> ; Alexey Brodkin
> ; Trevor Woerner ;
> Anatolij Gustschin ; Denis Zalevskiy
> ; Fabien Lahoudere
> ; Joe Hershberger
> ; Simon Goldschmidt
> ; James Byrne
> ; Angelo Dureghello
> Subject: Re: [v3, 4/5] mmc: fsl_esdhc: drop i.MX code
>
> On Tue, 21 May 2019 08:52:44 +
> "Y.b. Lu" wrote:
>
> > Dropped i.MX code which couldn't be reused.
> >
> > Signed-off-by: Yangbo Lu
> > ---
> > Changes for v2:
> > - Added this patch.
> > Changes for v3:
> > - Rebased.
> > ---
> > drivers/mmc/fsl_esdhc.c | 609
> > ++-- include/fsl_esdhc.h |
> > 57 2 files changed, 21 insertions(+), 645 deletions(-)
> >
> > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index
> > 1b7de74a72..3f4f75ae4c 100644
> > --- a/drivers/mmc/fsl_esdhc.c
> > +++ b/drivers/mmc/fsl_esdhc.c
> > @@ -16,14 +16,11 @@
> > #include
> > #include
> > #include
> > -#include
> > #include
> > #include
> > #include
> > #include
> > #include
> > -#include
> > -#include
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > @@ -33,8 +30,6 @@ DECLARE_GLOBAL_DATA_PTR;
> > IRQSTATEN_CIE | IRQSTATEN_DTOE |
> > IRQSTATEN_DCE | \ IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR
> | \
> > IRQSTATEN_DINT)
> > -#define MAX_TUNING_LOOP 40
> > -
> > struct fsl_esdhc {
> > uintdsaddr; /* SDMA system address
> > register */ uintblkattr;/* Block attributes register */
> > @@ -54,37 +49,20 @@ struct fsl_esdhc {
> > uintautoc12err; /* Auto CMD error status register
> > */ uinthostcapblt; /* Host controller capabilities
> > register */ uintwml;/* Watermark level register */
> > - uintmixctrl;/* For USDHC */
> > - charreserved1[4]; /* reserved */
> > + charreserved1[8]; /* reserved */
> > uintfevt; /* Force event register */
> > uintadmaes; /* ADMA error status register
> > */ uintadsaddr; /* ADMA system address register */
> > - charreserved2[4];
> > - uintdllctrl;
> > - uintdllstat;
> > - uintclktunectrlstatus;
> > - charreserved3[4];
> > - uintstrobe_dllctrl;
> > - uintstrobe_dllstat;
> > - charreserved4[72];
> > - uintvendorspec;
> > - uintmmcboot;
> > - uintvendorspec2;
> > - uinttuning_ctrl;/* on i.MX6/7/8 */
> > - charreserved5[44];
> > + charreserved2[160];
> > uinthostver;/* Host controller version register
> > */
> > - charreserved6[4]; /* reserved */
> > + charreserved3[4]; /* reserved */
> > uintdmaerraddr; /* DMA error address register */
> > - charreserved7[4]; /* reserved */
> > + charreserved4[4]; /* reserved */
> > uintdmaerrattr; /* DMA error attribute register */
> > - charreserved8[4]; /* reserved */
> > + charreserved5[4]; /* reserved */
> > uinthostcapblt2;/* Host controller capabilities
> > register 2 */
> > - charreserved9[8]; /* reserved */
> > - uinttcr;/* Tuning control register */
> > - charreserved10[28]; /* reserved */
> > - uintsddirctl; /* SD direction control register */
> >
Re: [U-Boot] [v3, 2/5] mmc: split fsl_esdhc driver for i.MX
> -Original Message-
> From: Lukasz Majewski
> Sent: 2019年5月29日 14:30
> To: Y.b. Lu
> Cc: u-boot@lists.denx.de; Stefano Babic ; Fabio Estevam
> ; dl-uboot-imx ; Albert Aribaud
> ; Eddy Petrișor ;
> Akshay Bhat ; Ken Lin
> ; Heiko Schocher ; Christian
> Gmeiner ; Stefan Roese ; Patrick
> Bruenn ; Troy Kisky
> ; Uri Mashiach
> ; Nikita Kiryanov ;
> Otavio Salvador ; Andreas Geisreiter
> ; Ludwig Zenz ; Eric
> Bénard ; Peng Fan ; Jason Liu
> ; Ye Li ; Adrian Alonso
> ; Alison Wang ;
> thar...@gateworks.com; Ian Ray ; Marcin Niestroj
> ; Andrej Rosano ;
> Marek Vasut ; Adam Ford ; Olaf
> Mandel ; Martyn Welch
> ; Ingo Schroeck ;
> Boris Brezillon ; Soeren Moch
> ; Richard Hu ; Vanessa
> Maegima ; Max Krummenacher
> ; Stefan Agner
> ; Markus Niebel ;
> Breno Matheus Lima ; Francesco Montefoschi
> ; Parthiban Nallathambi
> ; Albert ARIBAUD ; Jagan
> Teki ; Raffaele RECALCATI
> ; Simone CIANNI ;
> Bhaskar Upadhaya ; Vinitha V Pillai
> ; Prabhakar Kushwaha
> ; Rajesh Bhagat ;
> Antti Mäentausta ; Sébastien Szymanski
> ; Lucile Quirion
> ; Alexey Brodkin
> ; Trevor Woerner ;
> Anatolij Gustschin ; Denis Zalevskiy
> ; Fabien Lahoudere
> ; Joe Hershberger
> ; Simon Goldschmidt
> ; James Byrne
> ; Angelo Dureghello
> Subject: Re: [v3, 2/5] mmc: split fsl_esdhc driver for i.MX
>
> Hi Y.b. Lu,
>
> > The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
> > initially. The later QoriQ series PowerPC processors (which were
> > evolutions of MPC83XX/MPC85XX), QorIQ series ARM processors, and i.MX
> > series processors were using this driver for their eSDHCs too.
> >
> > For the two series processors, the eSDHCs are becoming more and more
> > different. We should have split it into two drivers, like them
> > (sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel.
> >
> > This patch is just to create a fsl_esdhc_imx driver which is a copy of
> > fsl_esdhc driver for i.MX processors. We will convert i.MX processors
> > to use fsl_esdhc_imx, and clean up the two drivers separately in the
> > future patches.
> >
> > Signed-off-by: Yangbo Lu
> > ---
> > Changes for v2:
> > - None.
> > Changes for v3:
> > - None.
> > ---
> > drivers/mmc/Kconfig | 6 ++
> > drivers/mmc/Makefile | 1 +
> > drivers/mmc/{fsl_esdhc.c => fsl_esdhc_imx.c} | 5 +++--
> > include/{fsl_esdhc.h => fsl_esdhc_imx.h} | 11 ++-
> > 4 files changed, 16 insertions(+), 7 deletions(-) copy
> > drivers/mmc/{fsl_esdhc.c => fsl_esdhc_imx.c} (99%) copy
> > include/{fsl_esdhc.h => fsl_esdhc_imx.h} (97%)
> >
> > diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index
> > c23299ea96..4e33fa1b2d 100644
> > --- a/drivers/mmc/Kconfig
> > +++ b/drivers/mmc/Kconfig
> > @@ -671,6 +671,12 @@ config FSL_ESDHC
> > This selects support for the eSDHC (enhanced secure digital host
> > controller) found on numerous Freescale/NXP SoCs.
> >
> > +config FSL_ESDHC_IMX
> > + bool "Freescale/NXP i.MX eSDHC controller support"
> > + help
> > + This selects support for the i.MX eSDHC (enhanced secure
> > digital host
> > + controller) found on numerous Freescale/NXP SoCs.
> > +
>
> You shall use capital letters for "Enhanced Secure Digital Host"
[Y.b. Lu] Get it. Will fix that.
>
> > endmenu
> >
> > config SYS_FSL_ERRATUM_ESDHC111
> > diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index
> > 0076fc393b..3c8c53a9e1 100644
> > --- a/drivers/mmc/Makefile
> > +++ b/drivers/mmc/Makefile
> > @@ -26,6 +26,7 @@ obj-$(CONFIG_MMC_DW_ROCKCHIP) +=
> > rockchip_dw_mmc.o obj-$(CONFIG_MMC_DW_SOCFPGA) +=
> > socfpga_dw_mmc.o obj-$(CONFIG_MMC_DW_SNPS) +=
> > snps_dw_mmc.o obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
> > +obj-$(CONFIG_FSL_ESDHC_IMX) += fsl_esdhc_imx.o
> > obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
> > obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
> > obj-$(CONFIG_MMC_MESON_GX) += meson_gx_mmc.o diff --git
> > a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc_imx.c similarity
> > index 99% copy from drivers/mmc/fsl_esdhc.c copy to
> > drivers/mmc/fsl_esdhc_imx.c index 1b7de74a72..faf133390f 100644
> > --- a/drivers/mmc/fsl_esdhc.c
> > +++ b/drivers/mmc/fsl_esdhc_imx.c
> > @@ -2,6 +2,7 @@
> > /*
> > * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
> > * Andy Fleming
> > + * Copyright 2019 NXP
>
> This line
Re: [U-Boot] [v3, 5/5] mmc: fsl_esdhc_imx: drop useless code
> -Original Message-
> From: Peng Fan
> Sent: 2019年5月29日 9:53
> To: Y.b. Lu ; u-boot@lists.denx.de
> Cc: Stefano Babic ; Fabio Estevam ;
> dl-uboot-imx ; Albert Aribaud
> ; Eddy Petrișor ;
> Akshay Bhat ; Ken Lin
> ; Heiko Schocher ; Christian
> Gmeiner ; Stefan Roese ; Patrick
> Bruenn ; Troy Kisky
> ; Uri Mashiach
> ; Nikita Kiryanov ;
> Otavio Salvador ; Andreas Geisreiter
> ; Ludwig Zenz ; Eric
> Bénard ; Jason Liu ; Ye Li
> ; Adrian Alonso ; Alison Wang
> ; thar...@gateworks.com; Ian Ray
> ; Marcin Niestroj ; Andrej
> Rosano ; Marek Vasut ; Lukasz
> Majewski ; Adam Ford ; Olaf
> Mandel ; Martyn Welch
> ; Ingo Schroeck ;
> Boris Brezillon ; Soeren Moch
> ; Richard Hu ; Vanessa
> Maegima ; Max Krummenacher
> ; Stefan Agner
> ; Markus Niebel ;
> Breno Matheus Lima ; Francesco Montefoschi
> ; Parthiban Nallathambi
> ; Albert ARIBAUD ; Jagan
> Teki ; Raffaele RECALCATI
> ; Simone CIANNI ;
> Bhaskar Upadhaya ; Vinitha V Pillai
> ; Prabhakar Kushwaha
> ; Rajesh Bhagat ;
> Antti Mäentausta ; Sébastien Szymanski
> ; Lucile Quirion
> ; Alexey Brodkin
> ; Trevor Woerner ;
> Anatolij Gustschin ; Denis Zalevskiy
> ; Fabien Lahoudere
> ; Joe Hershberger
> ; Simon Goldschmidt
> ; James Byrne
> ; Angelo Dureghello
> Subject: RE: [v3, 5/5] mmc: fsl_esdhc_imx: drop useless code
>
>
> > Subject: [v3, 5/5] mmc: fsl_esdhc_imx: drop useless code
> >
> > Dropped useless code for i.MX eSDHC driver.
> >
> > Signed-off-by: Yangbo Lu
> > ---
> > Changes for v2:
> > - Added this patch.
> > Changes for v3:
> > - None.
> > ---
> > drivers/mmc/fsl_esdhc_imx.c | 96 ++---
> > include/fsl_esdhc_imx.h | 4 --
> > 2 files changed, 4 insertions(+), 96 deletions(-)
> >
>
> [.....]
>
> > - { .compatible = "fsl,esdhc", },
>
> Please keep this, the following 2 dts using this compatible.
> ./arch/arm/dts/vf.dtsi
> ./arch/arm/dts/imx53-ppd.dts
>
> With this addressed, you could have my
> `Reviewed-by: Peng Fan `
[Y.b. Lu] Ok, thanks Peng.
May I know which u-boot subtree and branch should I use to rebase these patches?
Thanks!
>
> > { /* sentinel */ }
> > };
> >
> > diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h index
> > e05b24e7e8..8abd28ea50 100644
> > --- a/include/fsl_esdhc_imx.h
> > +++ b/include/fsl_esdhc_imx.h
> > @@ -17,10 +17,6 @@
> > /* needed for the mmc_cfg definition */ #include
> >
> > -#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT -#include
> > "../board/freescale/common/qixis.h"
> > -#endif
> > -
> > /* FSL eSDHC-specific constants */
> > #define SYSCTL 0x0002e02c
> > #define SYSCTL_INITA 0x0800
> > --
> > 2.17.1
___
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Re: [U-Boot] [v3, 0/5] Split fsl_esdhc driver for i.MX
> -Original Message- > From: Lukasz Majewski > Sent: 2019年5月23日 17:15 > To: linux-kernel-dev > Cc: Y.b. Lu ; u-boot@lists.denx.de; Steffen Dirkwinkel > ; Patrick Brünn > Subject: Re: [U-Boot] [v3, 0/5] Split fsl_esdhc driver for i.MX > > Hi > > > Hi > > > > On Tue, 2019-05-21 at 08:51 +, Y.b. Lu wrote: > > > The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX > > > initially. The later QoriQ series PowerPC processors (which were > > > evolutions of MPC83XX/MPC85XX), QorIQ series ARM processors, and > > > i.MX series processors were using this driver for their eSDHCs too. > > > > > > For the two series processors, the eSDHCs are becoming more and more > > > different. We should have split it into two drivers, like them > > > (sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel. > > > > > > It's ideal to keep common part for reusing. However, it's hard to > > > find out a little which could be reused. The truth is there will be > > > more and more different registers, bits and operatiing processes. > > > Even some code is common now, it may have to be split in the future. > > > So let's just split is as two drivers. > > > > > > Patch #2 just created a fsl_esdhc_imx driver which was a copy of > > > fsl_esdhc driver for i.MX processors. > > > Patch #3 converted i.MX platforms to use fsl_esdhc_imx. > > > Patch #4 and #5 just dropped useless code for the two driver. > > > There are still many cleaning up works needed to be done in the > > > future, because the eSDHC driver is mess for a long time. > > > Since I'm only owner for QorIQ eSDHC driver, I dropped only a little > > > things which I'm sure for fsl_esdhc_imx. Let i.MX eSDHC owner do > > > futhur cleaning up. > > > > Tested-by: Steffen Dirkwinkel s.dirkwin...@beckhoff.com > > > > I've tested this on the beckhoff/mx53cx9020 board. It still boots from > > sd after the changes. When rebasing to master this board only needs > > the defconfig change as we've recently removed the unused mmc code in > > "mx53cx9020.c". > > [Y.b. Lu] Get it. > > Thanks for testing. I will strive to provide review soon. [Y.b. Lu] Thanks Steffen and Lukasz. > > > Regards, > > Steffen Dirkwinkel > > > > > > > > Yangbo Lu (5): > > > Move CONFIG_FSL_ESDHC to defconfig > > > mmc: split fsl_esdhc driver for i.MX > > > Convert to use fsl_esdhc_imx for i.MX platforms > > > mmc: fsl_esdhc: drop i.MX code > > > mmc: fsl_esdhc_imx: drop useless code > > > > > > arch/arm/cpu/arm1136/mx35/generic.c | 10 +- > > > arch/arm/cpu/arm926ejs/mx25/generic.c | 8 +- > > > arch/arm/cpu/armv7/vf610/generic.c| 10 +- > > > arch/arm/cpu/armv8/s32v234/generic.c | 2 +- > > > arch/arm/include/asm/global_data.h| 2 +- > > > arch/arm/mach-imx/cpu.c | 6 +- > > > arch/arm/mach-imx/mx6/litesom.c | 4 +- > > > arch/arm/mach-imx/mx7/clock.c | 4 +- > > > arch/arm/mach-imx/mx7ulp/clock.c | 2 +- > > > arch/arm/mach-imx/speed.c | 4 +- > > > board/advantech/dms-ba16/dms-ba16.c | 4 +- > > > board/aristainetos/aristainetos-v1.c | 2 +- > > > board/aristainetos/aristainetos-v2.c | 2 +- > > > board/aristainetos/aristainetos.c | 4 +- > > > board/bachmann/ot1200/ot1200.c| 2 +- > > > board/barco/platinum/platinum.c | 2 +- > > > board/barco/titanium/titanium.c | 4 +- > > > board/beckhoff/mx53cx9020/mx53cx9020.c| 4 +- > > > board/boundary/nitrogen6x/nitrogen6x.c| 4 +- > > > board/ccv/xpress/xpress.c | 2 +- > > > board/compulab/cl-som-imx7/cl-som-imx7.c | 6 +- > > > board/compulab/cl-som-imx7/common.c | 6 +- > > > board/compulab/cl-som-imx7/common.h | 8 +- > > > board/compulab/cl-som-imx7/mux.c | 8 +- > > > board/compulab/cl-som-imx7/spl.c | 6 +- > > > board/compulab/cm_fx6/cm_fx6.c| 4 +- > > > board/compulab/cm_fx6/common.c| 4 +- > > > board/compulab/cm_fx6/spl.c | 2 +- > > > board/congatec/cgtqmx6eval/cgtqmx6eval.c | 4 +- > > > board/dhelectronics/dh_imx6/dh_imx6.c
[U-Boot] [v3, 0/5] Split fsl_esdhc driver for i.MX
The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX initially. The later QoriQ series PowerPC processors (which were evolutions of MPC83XX/MPC85XX), QorIQ series ARM processors, and i.MX series processors were using this driver for their eSDHCs too. For the two series processors, the eSDHCs are becoming more and more different. We should have split it into two drivers, like them (sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel. It's ideal to keep common part for reusing. However, it's hard to find out a little which could be reused. The truth is there will be more and more different registers, bits and operatiing processes. Even some code is common now, it may have to be split in the future. So let's just split is as two drivers. Patch #2 just created a fsl_esdhc_imx driver which was a copy of fsl_esdhc driver for i.MX processors. Patch #3 converted i.MX platforms to use fsl_esdhc_imx. Patch #4 and #5 just dropped useless code for the two driver. There are still many cleaning up works needed to be done in the future, because the eSDHC driver is mess for a long time. Since I'm only owner for QorIQ eSDHC driver, I dropped only a little things which I'm sure for fsl_esdhc_imx. Let i.MX eSDHC owner do futhur cleaning up. Yangbo Lu (5): Move CONFIG_FSL_ESDHC to defconfig mmc: split fsl_esdhc driver for i.MX Convert to use fsl_esdhc_imx for i.MX platforms mmc: fsl_esdhc: drop i.MX code mmc: fsl_esdhc_imx: drop useless code arch/arm/cpu/arm1136/mx35/generic.c | 10 +- arch/arm/cpu/arm926ejs/mx25/generic.c | 8 +- arch/arm/cpu/armv7/vf610/generic.c| 10 +- arch/arm/cpu/armv8/s32v234/generic.c | 2 +- arch/arm/include/asm/global_data.h| 2 +- arch/arm/mach-imx/cpu.c | 6 +- arch/arm/mach-imx/mx6/litesom.c | 4 +- arch/arm/mach-imx/mx7/clock.c | 4 +- arch/arm/mach-imx/mx7ulp/clock.c | 2 +- arch/arm/mach-imx/speed.c | 4 +- board/advantech/dms-ba16/dms-ba16.c | 4 +- board/aristainetos/aristainetos-v1.c | 2 +- board/aristainetos/aristainetos-v2.c | 2 +- board/aristainetos/aristainetos.c | 4 +- board/bachmann/ot1200/ot1200.c| 2 +- board/barco/platinum/platinum.c | 2 +- board/barco/titanium/titanium.c | 4 +- board/beckhoff/mx53cx9020/mx53cx9020.c| 4 +- board/boundary/nitrogen6x/nitrogen6x.c| 4 +- board/ccv/xpress/xpress.c | 2 +- board/compulab/cl-som-imx7/cl-som-imx7.c | 6 +- board/compulab/cl-som-imx7/common.c | 6 +- board/compulab/cl-som-imx7/common.h | 8 +- board/compulab/cl-som-imx7/mux.c | 8 +- board/compulab/cl-som-imx7/spl.c | 6 +- board/compulab/cm_fx6/cm_fx6.c| 4 +- board/compulab/cm_fx6/common.c| 4 +- board/compulab/cm_fx6/spl.c | 2 +- board/congatec/cgtqmx6eval/cgtqmx6eval.c | 4 +- board/dhelectronics/dh_imx6/dh_imx6.c | 4 +- board/dhelectronics/dh_imx6/dh_imx6_spl.c | 2 +- board/el/el6x/el6x.c | 4 +- board/embest/mx6boards/mx6boards.c| 4 +- board/freescale/imx8mq_evk/imx8mq_evk.c | 2 +- board/freescale/imx8mq_evk/spl.c | 2 +- board/freescale/imx8qxp_mek/imx8qxp_mek.c | 2 +- board/freescale/mx25pdk/mx25pdk.c | 6 +- board/freescale/mx35pdk/mx35pdk.c | 4 +- board/freescale/mx51evk/mx51evk.c | 6 +- board/freescale/mx53ard/mx53ard.c | 4 +- board/freescale/mx53evk/mx53evk.c | 4 +- board/freescale/mx53loco/mx53loco.c | 4 +- board/freescale/mx53smd/mx53smd.c | 4 +- board/freescale/mx6qarm2/mx6qarm2.c | 4 +- board/freescale/mx6sabreauto/mx6sabreauto.c | 4 +- board/freescale/mx6sabresd/mx6sabresd.c | 4 +- board/freescale/mx6slevk/mx6slevk.c | 2 +- .../freescale/mx6sxsabreauto/mx6sxsabreauto.c | 2 +- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 2 +- .../mx6ul_14x14_evk/mx6ul_14x14_evk.c | 4 +- board/freescale/mx6ullevk/mx6ullevk.c | 2 +- board/freescale/mx7dsabresd/mx7dsabresd.c | 2 +- board/freescale/s32v234evb/s32v234evb.c | 4 +- board/freescale/vf610twr/vf610twr.c | 4 +- board/gateworks/gw_ventana/common.c | 6 +- board/gateworks/gw_ventana/gw_ventana.c | 2 +- board/ge/bx50v3/bx50v3.c | 2 +- board/ge/mx53ppd/mx53ppd.c| 2 +- board/grinn/liteboard/board.c | 4 +- board/inversepath/usbarmory/usbarmory.c | 2 +- board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c | 4 +- board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c | 2 +- board/kosagi/novena/novena.c | 4
[U-Boot] [v3, 5/5] mmc: fsl_esdhc_imx: drop useless code
Dropped useless code for i.MX eSDHC driver.
Signed-off-by: Yangbo Lu
---
Changes for v2:
- Added this patch.
Changes for v3:
- None.
---
drivers/mmc/fsl_esdhc_imx.c | 96 ++---
include/fsl_esdhc_imx.h | 4 --
2 files changed, 4 insertions(+), 96 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index faf133390f..1c02e0eef1 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -259,8 +259,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
{
int timeout;
struct fsl_esdhc *regs = priv->esdhc_regs;
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
dma_addr_t addr;
#endif
uint wml_value;
@@ -273,8 +272,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
esdhc_clrsetbits32(>wml, WML_RD_WML_MASK, wml_value);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
addr = virt_to_phys((void *)(data->dest));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -310,8 +308,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
esdhc_clrsetbits32(>wml, WML_WR_WML_MASK,
wml_value << 16);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
addr = virt_to_phys((void *)(data->src));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -376,8 +373,7 @@ static void check_and_invalidate_dcache_range
unsigned end = 0;
unsigned size = roundup(ARCH_DMA_MINALIGN,
data->blocks*data->blocksize);
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
dma_addr_t addr;
addr = virt_to_phys((void *)(data->dest));
@@ -392,25 +388,6 @@ static void check_and_invalidate_dcache_range
invalidate_dcache_range(start, end);
}
-#ifdef CONFIG_MCF5441x
-/*
- * Swaps 32-bit words to little-endian byte order.
- */
-static inline void sd_swap_dma_buff(struct mmc_data *data)
-{
- int i, size = data->blocksize >> 2;
- u32 *buffer = (u32 *)data->dest;
- u32 sw;
-
- while (data->blocks--) {
- for (i = 0; i < size; i++) {
- sw = __sw32(*buffer);
- *buffer++ = sw;
- }
- }
-}
-#endif
-
/*
* Sends a command out on the bus. Takes the mmc pointer,
* a command pointer, and an optional data pointer.
@@ -575,9 +552,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc,
*/
if (data->flags & MMC_DATA_READ) {
check_and_invalidate_dcache_range(cmd, data);
-#ifdef CONFIG_MCF5441x
- sd_swap_dma_buff(data);
-#endif
}
#endif
}
@@ -1073,12 +1047,8 @@ static int esdhc_init_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc)
/* Disable the BRR and BWR bits in IRQSTAT */
esdhc_clrbits32(>irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
-#ifdef CONFIG_MCF5441x
- esdhc_write32(>proctl, PROCTL_INIT | PROCTL_D3CD);
-#else
/* Put the PROCTL reg back to the default */
esdhc_write32(>proctl, PROCTL_INIT);
-#endif
/* Set timout to the maximum value */
esdhc_clrsetbits32(>sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
@@ -1186,11 +1156,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
if (ret)
return ret;
-#ifdef CONFIG_MCF5441x
- /* ColdFire, using SDHC_DATA[3] for card detection */
- esdhc_write32(>proctl, PROCTL_INIT | PROCTL_D3CD);
-#endif
-
#ifndef CONFIG_FSL_USDHC
esdhc_setbits32(>sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
| SYSCTL_IPGEN | SYSCTL_CKEN);
@@ -1215,15 +1180,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
voltage_caps = 0;
caps = esdhc_read32(>hostcapblt);
-#ifdef CONFIG_MCF5441x
- /*
-* MCF5441x RM declares in more points that sdhc clock speed must
-* never exceed 25 Mhz. From this, the HS bit needs to be disabled
-* from host capabilities.
-*/
- caps &=
[U-Boot] [v3, 4/5] mmc: fsl_esdhc: drop i.MX code
Dropped i.MX code which couldn't be reused.
Signed-off-by: Yangbo Lu
---
Changes for v2:
- Added this patch.
Changes for v3:
- Rebased.
---
drivers/mmc/fsl_esdhc.c | 609 ++--
include/fsl_esdhc.h | 57
2 files changed, 21 insertions(+), 645 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 1b7de74a72..3f4f75ae4c 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -16,14 +16,11 @@
#include
#include
#include
-#include
#include
#include
#include
#include
#include
-#include
-#include
DECLARE_GLOBAL_DATA_PTR;
@@ -33,8 +30,6 @@ DECLARE_GLOBAL_DATA_PTR;
IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE
| \
IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR
| \
IRQSTATEN_DINT)
-#define MAX_TUNING_LOOP 40
-
struct fsl_esdhc {
uintdsaddr; /* SDMA system address register */
uintblkattr;/* Block attributes register */
@@ -54,37 +49,20 @@ struct fsl_esdhc {
uintautoc12err; /* Auto CMD error status register */
uinthostcapblt; /* Host controller capabilities register */
uintwml;/* Watermark level register */
- uintmixctrl;/* For USDHC */
- charreserved1[4]; /* reserved */
+ charreserved1[8]; /* reserved */
uintfevt; /* Force event register */
uintadmaes; /* ADMA error status register */
uintadsaddr;/* ADMA system address register */
- charreserved2[4];
- uintdllctrl;
- uintdllstat;
- uintclktunectrlstatus;
- charreserved3[4];
- uintstrobe_dllctrl;
- uintstrobe_dllstat;
- charreserved4[72];
- uintvendorspec;
- uintmmcboot;
- uintvendorspec2;
- uinttuning_ctrl;/* on i.MX6/7/8 */
- charreserved5[44];
+ charreserved2[160];
uinthostver;/* Host controller version register */
- charreserved6[4]; /* reserved */
+ charreserved3[4]; /* reserved */
uintdmaerraddr; /* DMA error address register */
- charreserved7[4]; /* reserved */
+ charreserved4[4]; /* reserved */
uintdmaerrattr; /* DMA error attribute register */
- charreserved8[4]; /* reserved */
+ charreserved5[4]; /* reserved */
uinthostcapblt2;/* Host controller capabilities register 2 */
- charreserved9[8]; /* reserved */
- uinttcr;/* Tuning control register */
- charreserved10[28]; /* reserved */
- uintsddirctl; /* SD direction control register */
- charreserved11[712];/* reserved */
- uintscr;/* eSDHC control register */
+ charreserved6[756]; /* reserved */
+ uintesdhcctl; /* eSDHC control register */
};
struct fsl_esdhc_plat {
@@ -92,11 +70,6 @@ struct fsl_esdhc_plat {
struct mmc mmc;
};
-struct esdhc_soc_data {
- u32 flags;
- u32 caps;
-};
-
/**
* struct fsl_esdhc_priv
*
@@ -109,13 +82,6 @@ struct esdhc_soc_data {
* @dev: pointer for the device
* @non_removable: 0: removable; 1: non-removable
* @wp_enable: 1: enable checking wp; 0: no check
- * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
- * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
- * @caps: controller capabilities
- * @tuning_step: tuning step setting in tuning_ctrl register
- * @start_tuning_tap: the start point for tuning in tuning_ctrl register
- * @strobe_dll_delay_target: settings in strobe_dllctrl
- * @signal_voltage: indicating the current voltage
* @cd_gpio: gpio for card detection
* @wp_gpio: gpio for write protection
*/
@@ -124,7 +90,6 @@ struct fsl_esdhc_priv {
unsigned int sdhc_clk;
struct clk per_clk;
unsigned int clock;
- unsigned int mode;
unsigned int bus_width;
#if !CONFIG_IS_ENABLED(BLK)
struct mmc *mmc;
@@ -132,21 +97,6 @@ struct fsl_esdhc_priv {
struct udevice *dev;
int non_removable;
int wp_enable;
- int vs18_enable;
- u32 flags;
- u32 caps;
- u32 tuning_step;
- u32 tuning_start_tap;
- u32 strobe_dll_delay_target;
- u32 signal_voltage;
-#if IS_ENABLED(CONFIG_DM_REGULATOR)
- struct udevice *vqmmc_dev;
- struct udevice *vmmc_dev;
-#endif
-#ifdef CONFIG_DM_GPIO
- struct gpio_desc cd_gpio;
- struct gpio_desc wp_gpio;
-#endif
};
/* Return the XFERTYP flags for a given command and data packet */
@@ -258,8 +208,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
{
int timeout;
struct fsl_esdhc *regs = priv->esdhc_regs;
-#if defined(CONFIG_FSL_LAYERSCAPE)
[U-Boot] [v3, 2/5] mmc: split fsl_esdhc driver for i.MX
The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
initially. The later QoriQ series PowerPC processors (which were
evolutions of MPC83XX/MPC85XX), QorIQ series ARM processors, and
i.MX series processors were using this driver for their eSDHCs too.
For the two series processors, the eSDHCs are becoming more and
more different. We should have split it into two drivers, like them
(sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel.
This patch is just to create a fsl_esdhc_imx driver which is a copy
of fsl_esdhc driver for i.MX processors. We will convert i.MX processors
to use fsl_esdhc_imx, and clean up the two drivers separately in the
future patches.
Signed-off-by: Yangbo Lu
---
Changes for v2:
- None.
Changes for v3:
- None.
---
drivers/mmc/Kconfig | 6 ++
drivers/mmc/Makefile | 1 +
drivers/mmc/{fsl_esdhc.c => fsl_esdhc_imx.c} | 5 +++--
include/{fsl_esdhc.h => fsl_esdhc_imx.h} | 11 ++-
4 files changed, 16 insertions(+), 7 deletions(-)
copy drivers/mmc/{fsl_esdhc.c => fsl_esdhc_imx.c} (99%)
copy include/{fsl_esdhc.h => fsl_esdhc_imx.h} (97%)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index c23299ea96..4e33fa1b2d 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -671,6 +671,12 @@ config FSL_ESDHC
This selects support for the eSDHC (enhanced secure digital host
controller) found on numerous Freescale/NXP SoCs.
+config FSL_ESDHC_IMX
+ bool "Freescale/NXP i.MX eSDHC controller support"
+ help
+ This selects support for the i.MX eSDHC (enhanced secure digital host
+ controller) found on numerous Freescale/NXP SoCs.
+
endmenu
config SYS_FSL_ERRATUM_ESDHC111
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 0076fc393b..3c8c53a9e1 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_MMC_DW_ROCKCHIP) += rockchip_dw_mmc.o
obj-$(CONFIG_MMC_DW_SOCFPGA) += socfpga_dw_mmc.o
obj-$(CONFIG_MMC_DW_SNPS) += snps_dw_mmc.o
obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
+obj-$(CONFIG_FSL_ESDHC_IMX) += fsl_esdhc_imx.o
obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
obj-$(CONFIG_MMC_MESON_GX) += meson_gx_mmc.o
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc_imx.c
similarity index 99%
copy from drivers/mmc/fsl_esdhc.c
copy to drivers/mmc/fsl_esdhc_imx.c
index 1b7de74a72..faf133390f 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -2,6 +2,7 @@
/*
* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
* Andy Fleming
+ * Copyright 2019 NXP
*
* Based vaguely on the pxa mmc code:
* (C) Copyright 2003
@@ -18,7 +19,7 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
@@ -110,7 +111,7 @@ struct esdhc_soc_data {
* @non_removable: 0: removable; 1: non-removable
* @wp_enable: 1: enable checking wp; 0: no check
* @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
- * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
+ * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
* @caps: controller capabilities
* @tuning_step: tuning step setting in tuning_ctrl register
* @start_tuning_tap: the start point for tuning in tuning_ctrl register
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc_imx.h
similarity index 97%
copy from include/fsl_esdhc.h
copy to include/fsl_esdhc_imx.h
index 8dbd5249a7..e05b24e7e8 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc_imx.h
@@ -4,10 +4,11 @@
*---
*
* Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
+ * Copyright 2019 NXP
*/
-#ifndef __FSL_ESDHC_H__
-#define__FSL_ESDHC_H__
+#ifndef __FSL_ESDHC_IMX_H__
+#define __FSL_ESDHC_IMX_H__
#include
#include
@@ -258,15 +259,15 @@ struct fsl_esdhc_cfg {
#error "Endianess is not defined: please fix to continue"
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
int fsl_esdhc_mmc_init(bd_t *bis);
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
void fdt_fixup_esdhc(void *blob, bd_t *bd);
#else
static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
void __noreturn mmc_boot(void);
void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
-#endif /* __FSL_ESDHC_H__ */
+#endif /* __FSL_ESDHC_IMX_H__ */
--
2.17.1
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[U-Boot] [v3, 1/5] Move CONFIG_FSL_ESDHC to defconfig
Moved CONFIG_FSL_ESDHC from header files to defconfig files. Signed-off-by: Yangbo Lu --- Changes for v2: - Rebased. Changes for v3: - Rebased. --- configs/imx8mq_evk_defconfig | 1 + configs/imx8qm_mek_defconfig | 1 + configs/imx8qxp_mek_defconfig | 1 + configs/kp_imx6q_tpc_defconfig | 1 + configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1012afrwy_qspi_defconfig | 1 + configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1012afrwy_tfa_defconfig | 1 + include/configs/imx8mq_evk.h | 1 - include/configs/imx8qm_mek.h | 1 - include/configs/imx8qxp_mek.h | 1 - include/configs/kp_imx6q_tpc.h | 1 - include/configs/ls1012afrwy.h | 1 - 13 files changed, 8 insertions(+), 5 deletions(-) diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 7383124851..534cf96c58 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -31,6 +31,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_DM_ETH=y CONFIG_PINCTRL=y diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index 1a6ce3abf8..173568c0da 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -52,6 +52,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ATHEROS=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index c4a8cf3881..7021bd5da8 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -55,6 +55,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig index 0ca83cbfea..9b6ff4a85b 100644 --- a/configs/kp_imx6q_tpc_defconfig +++ b/configs/kp_imx6q_tpc_defconfig @@ -34,6 +34,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y CONFIG_FEC_MXC=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index bf98466576..0360d9d4e8 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -31,6 +31,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index aa3256fb43..08eedec827 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -32,6 +32,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index b0fdad6dd0..2c3d8931e7 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -31,6 +31,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index 6a70f5881b..19aae5aa1a 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -32,6 +32,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index e4fa2df342..16e4136fa9 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -216,7 +216,6 @@ #define CONFIG_IMX_BOOTAUX #define CONFIG_CMD_MMC -#define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 2bdf3be654..3679b487e1 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -47,7 +47,6 @@ #undef CONFIG_CMD_CRC32 #undef CONFIG_BOOTM_NETBSD -#define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR0x5B01 diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 261661a978..18cc930de2 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -46,7 +46,6 @@
Re: [U-Boot] [v2, 0/5] Split fsl_esdhc driver for i.MX
Hi Peng and Stefano, There were 300+ board defconfig files for QorIQ, and only 100+ board defconfig files for i.MX. So current patches had minimized code/files changes. I have rebased the patch-set and sent out adding more reviewers with get_maintainer.pl. I have no idea and I have to go ahead to split esdhc driver since it's blocking new features coding. Thanks a lot. Best regards, Yangbo Lu > -Original Message- > From: Y.b. Lu > Sent: Tuesday, May 14, 2019 7:15 PM > To: Peng Fan ; u-boot@lists.denx.de; sba...@denx.de > Cc: Prabhakar Kushwaha > Subject: RE: [v2, 0/5] Split fsl_esdhc driver for i.MX > > Hi Peng, > > Sorry. I missed this email. I almost forget it. > I'm ok to create a new esdhc driver for either i.mx or qoriq. The reason I > used > esdhc-imx.c is to align with linux. (sdhci-of-esdhc.c/sdhci-esdhc-imx.c) > > Do you want to rework the patches creating qoriq esdhc driver. > Thanks a lot. > > Best regards, > Yangbo Lu > > > > -Original Message- > > From: Peng Fan > > Sent: Monday, April 22, 2019 1:22 PM > > To: Y.b. Lu ; u-boot@lists.denx.de; sba...@denx.de > > Cc: Prabhakar Kushwaha > > Subject: RE: [v2, 0/5] Split fsl_esdhc driver for i.MX > > > > Hi Y.b > > > > Sorry for top post, just a general comments for now. > > Is it ok to keep FSL_ESDHC for i.MX compatible devices and use > > FSL_ESDHC_XX for QoriQ devices? In this way, you could minimize code > changes. > > . > > Regards, > > Peng. > > > > > > > > > > > -Original Message- > > > > > > From: Y.b. Lu > > > > > > Sent: Thursday, March 21, 2019 12:32 PM > > > > > > To: u-boot@lists.denx.de > > > > > > Cc: Prabhakar Kushwaha ; Peng Fan > > > > > > ; sba...@denx.de; Y.b. Lu > > > > > > > > > > > > Subject: [v2, 0/5] Split fsl_esdhc driver for i.MX > > > > > > > > > > > > The fsl_esdhc driver was for Freescale eSDHC on > > > > > > MPC83XX/MPC85XX > > > > > initially. > > > > > > The later QoriQ series PowerPC processors (which were > > > > > > evolutions of MPC83XX/MPC85XX), QorIQ series ARM processors, > > > > > > and i.MX series processors were using this driver for their eSDHCs > > > > > > too. > > > > > > > > > > > > For the two series processors, the eSDHCs are becoming more > > > > > > and more different. We should have split it into two drivers, > > > > > > like them > > > > > > (sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel. > > > > > > > > > > > > It's ideal to keep common part for reusing. However, it's hard > > > > > > to find out a little which could be reused. The truth is there > > > > > > will be more and more different registers, bits and operatiing > processes. > > > > > > Even some code is common now, it may have to be split in the future. > > > > > > So let's just split is as two drivers. > > > > > > > > > > > > Patch #2 just created a fsl_esdhc_imx driver which was a copy > > > > > > of fsl_esdhc driver for i.MX processors. > > > > > > Patch #3 converted i.MX platforms to use fsl_esdhc_imx. > > > > > > Patch #4 and #5 just dropped useless code for the two driver. > > > > > > There are still many cleaning up works needed to be done in > > > > > > the future, because the eSDHC driver is mess for a long time. > > > > > > Since I'm only owner for QorIQ eSDHC driver, I dropped only a > > > > > > little things which I'm sure for fsl_esdhc_imx. Let i.MX eSDHC > > > > > > owner do futhur > > > > > cleaning up. > > > > > > > > > > > > Yangbo Lu (5): > > > > > > Move CONFIG_FSL_ESDHC to defconfig > > > > > > mmc: split fsl_esdhc driver for i.MX > > > > > > Convert to use fsl_esdhc_imx for i.MX platforms > > > > > > mmc: fsl_esdhc: drop i.MX code > > > > > > mmc: fsl_esdhc_imx: drop useless code > > > > > > > > > > > > arch/arm/cpu/arm1136/mx35/generic.c | 10 +- > > > > > > arch/arm/cpu/arm926ejs/mx25/generic.c | 8 +- > > > > > > arch/arm/cpu/armv7/vf610/generic.c| 10 +- > > > > > > arc
Re: [U-Boot] [v2, 0/5] Split fsl_esdhc driver for i.MX
Hi Peng, Sorry. I missed this email. I almost forget it. I'm ok to create a new esdhc driver for either i.mx or qoriq. The reason I used esdhc-imx.c is to align with linux. (sdhci-of-esdhc.c/sdhci-esdhc-imx.c) Do you want to rework the patches creating qoriq esdhc driver. Thanks a lot. Best regards, Yangbo Lu > -Original Message- > From: Peng Fan > Sent: Monday, April 22, 2019 1:22 PM > To: Y.b. Lu ; u-boot@lists.denx.de; sba...@denx.de > Cc: Prabhakar Kushwaha > Subject: RE: [v2, 0/5] Split fsl_esdhc driver for i.MX > > Hi Y.b > > Sorry for top post, just a general comments for now. > Is it ok to keep FSL_ESDHC for i.MX compatible devices and use FSL_ESDHC_XX > for QoriQ devices? In this way, you could minimize code changes. > . > Regards, > Peng. > > > > > > > > > -Original Message- > > > > > From: Y.b. Lu > > > > > Sent: Thursday, March 21, 2019 12:32 PM > > > > > To: u-boot@lists.denx.de > > > > > Cc: Prabhakar Kushwaha ; Peng Fan > > > > > ; sba...@denx.de; Y.b. Lu > > > > > Subject: [v2, 0/5] Split fsl_esdhc driver for i.MX > > > > > > > > > > The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX > > > > initially. > > > > > The later QoriQ series PowerPC processors (which were evolutions > > > > > of MPC83XX/MPC85XX), QorIQ series ARM processors, and i.MX > > > > > series processors were using this driver for their eSDHCs too. > > > > > > > > > > For the two series processors, the eSDHCs are becoming more and > > > > > more different. We should have split it into two drivers, like > > > > > them > > > > > (sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel. > > > > > > > > > > It's ideal to keep common part for reusing. However, it's hard > > > > > to find out a little which could be reused. The truth is there > > > > > will be more and more different registers, bits and operatiing > > > > > processes. > > > > > Even some code is common now, it may have to be split in the future. > > > > > So let's just split is as two drivers. > > > > > > > > > > Patch #2 just created a fsl_esdhc_imx driver which was a copy of > > > > > fsl_esdhc driver for i.MX processors. > > > > > Patch #3 converted i.MX platforms to use fsl_esdhc_imx. > > > > > Patch #4 and #5 just dropped useless code for the two driver. > > > > > There are still many cleaning up works needed to be done in the > > > > > future, because the eSDHC driver is mess for a long time. > > > > > Since I'm only owner for QorIQ eSDHC driver, I dropped only a > > > > > little things which I'm sure for fsl_esdhc_imx. Let i.MX eSDHC > > > > > owner do futhur > > > > cleaning up. > > > > > > > > > > Yangbo Lu (5): > > > > > Move CONFIG_FSL_ESDHC to defconfig > > > > > mmc: split fsl_esdhc driver for i.MX > > > > > Convert to use fsl_esdhc_imx for i.MX platforms > > > > > mmc: fsl_esdhc: drop i.MX code > > > > > mmc: fsl_esdhc_imx: drop useless code > > > > > > > > > > arch/arm/cpu/arm1136/mx35/generic.c | 10 +- > > > > > arch/arm/cpu/arm926ejs/mx25/generic.c | 8 +- > > > > > arch/arm/cpu/armv7/vf610/generic.c| 10 +- > > > > > arch/arm/cpu/armv8/s32v234/generic.c | 2 +- > > > > > arch/arm/include/asm/global_data.h| 2 +- > > > > > arch/arm/mach-imx/cpu.c | 6 +- > > > > > arch/arm/mach-imx/mx6/litesom.c | 4 +- > > > > > arch/arm/mach-imx/mx7/clock.c | 4 +- > > > > > arch/arm/mach-imx/mx7ulp/clock.c | 2 +- > > > > > arch/arm/mach-imx/speed.c | 4 +- > > > > > board/Arcturus/ucp1020/spl.c | 2 +- > > > > > board/advantech/dms-ba16/dms-ba16.c | 4 +- > > > > > board/aristainetos/aristainetos-v1.c | 2 +- > > > > > board/aristainetos/aristainetos-v2.c | 2 +- > > > > > board/aristainetos/aristainetos.c | 4 +- > > > > > board/bachmann/ot1200/ot1200.c| 2 +- > > > > > board/barco/platinum/platinum.c | 2
Re: [U-Boot] [v2, 0/5] Split fsl_esdhc driver for i.MX
Hi, May I know whether this patch-set is in reviewing? Actually it's blocking QorIQ eSDHC UHS-I/HS200 new features development, since the way of implementation is totally different with i.MX. Thanks a lot. Best regards, Yangbo Lu > -Original Message- > From: Y.b. Lu > Sent: Wednesday, April 10, 2019 10:59 PM > To: u-boot@lists.denx.de; sba...@denx.de > Cc: Prabhakar Kushwaha ; Peng Fan > > Subject: RE: [v2, 0/5] Split fsl_esdhc driver for i.MX > > Hi Stefano, > > Did you get any chance to review it? > Thanks. > > Best regards, > Yangbo Lu > > > -Original Message- > > From: Y.b. Lu > > Sent: Monday, April 8, 2019 11:04 PM > > To: u-boot@lists.denx.de > > Cc: Prabhakar Kushwaha ; Peng Fan > > ; sba...@denx.de > > Subject: RE: [v2, 0/5] Split fsl_esdhc driver for i.MX > > > > Any comments? > > Thanks a lot :) > > > > > -Original Message- > > > From: Y.b. Lu > > > Sent: Thursday, March 21, 2019 12:32 PM > > > To: u-boot@lists.denx.de > > > Cc: Prabhakar Kushwaha ; Peng Fan > > > ; sba...@denx.de; Y.b. Lu > > > Subject: [v2, 0/5] Split fsl_esdhc driver for i.MX > > > > > > The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX > > initially. > > > The later QoriQ series PowerPC processors (which were evolutions of > > > MPC83XX/MPC85XX), QorIQ series ARM processors, and i.MX series > > > processors were using this driver for their eSDHCs too. > > > > > > For the two series processors, the eSDHCs are becoming more and more > > > different. We should have split it into two drivers, like them > > > (sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel. > > > > > > It's ideal to keep common part for reusing. However, it's hard to > > > find out a little which could be reused. The truth is there will be > > > more and more different registers, bits and operatiing processes. > > > Even some code is common now, it may have to be split in the future. > > > So let's just split is as two drivers. > > > > > > Patch #2 just created a fsl_esdhc_imx driver which was a copy of > > > fsl_esdhc driver for i.MX processors. > > > Patch #3 converted i.MX platforms to use fsl_esdhc_imx. > > > Patch #4 and #5 just dropped useless code for the two driver. > > > There are still many cleaning up works needed to be done in the > > > future, because the eSDHC driver is mess for a long time. > > > Since I'm only owner for QorIQ eSDHC driver, I dropped only a little > > > things which I'm sure for fsl_esdhc_imx. Let i.MX eSDHC owner do > > > futhur > > cleaning up. > > > > > > Yangbo Lu (5): > > > Move CONFIG_FSL_ESDHC to defconfig > > > mmc: split fsl_esdhc driver for i.MX > > > Convert to use fsl_esdhc_imx for i.MX platforms > > > mmc: fsl_esdhc: drop i.MX code > > > mmc: fsl_esdhc_imx: drop useless code > > > > > > arch/arm/cpu/arm1136/mx35/generic.c | 10 +- > > > arch/arm/cpu/arm926ejs/mx25/generic.c | 8 +- > > > arch/arm/cpu/armv7/vf610/generic.c| 10 +- > > > arch/arm/cpu/armv8/s32v234/generic.c | 2 +- > > > arch/arm/include/asm/global_data.h| 2 +- > > > arch/arm/mach-imx/cpu.c | 6 +- > > > arch/arm/mach-imx/mx6/litesom.c | 4 +- > > > arch/arm/mach-imx/mx7/clock.c | 4 +- > > > arch/arm/mach-imx/mx7ulp/clock.c | 2 +- > > > arch/arm/mach-imx/speed.c | 4 +- > > > board/Arcturus/ucp1020/spl.c | 2 +- > > > board/advantech/dms-ba16/dms-ba16.c | 4 +- > > > board/aristainetos/aristainetos-v1.c | 2 +- > > > board/aristainetos/aristainetos-v2.c | 2 +- > > > board/aristainetos/aristainetos.c | 4 +- > > > board/bachmann/ot1200/ot1200.c| 2 +- > > > board/barco/platinum/platinum.c | 2 +- > > > board/barco/titanium/titanium.c | 4 +- > > > board/beckhoff/mx53cx9020/mx53cx9020.c| 4 +- > > > board/boundary/nitrogen6x/nitrogen6x.c| 4 +- > > > board/ccv/xpress/xpress.c | 2 +- > > > board/compulab/cl-som-imx7/cl-som-imx7.c | 6 +- > > > board/compulab/cl-som-imx7/common.c | 6 +- > > > board/compulab/cl-som-imx7/common.h | 8 +- > > > boa
Re: [U-Boot] [v2, 0/5] Split fsl_esdhc driver for i.MX
Hi Stefano, Did you get any chance to review it? Thanks. Best regards, Yangbo Lu > -Original Message- > From: Y.b. Lu > Sent: Monday, April 8, 2019 11:04 PM > To: u-boot@lists.denx.de > Cc: Prabhakar Kushwaha ; Peng Fan > ; sba...@denx.de > Subject: RE: [v2, 0/5] Split fsl_esdhc driver for i.MX > > Any comments? > Thanks a lot :) > > > -----Original Message- > > From: Y.b. Lu > > Sent: Thursday, March 21, 2019 12:32 PM > > To: u-boot@lists.denx.de > > Cc: Prabhakar Kushwaha ; Peng Fan > > ; sba...@denx.de; Y.b. Lu > > Subject: [v2, 0/5] Split fsl_esdhc driver for i.MX > > > > The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX > initially. > > The later QoriQ series PowerPC processors (which were evolutions of > > MPC83XX/MPC85XX), QorIQ series ARM processors, and i.MX series > > processors were using this driver for their eSDHCs too. > > > > For the two series processors, the eSDHCs are becoming more and more > > different. We should have split it into two drivers, like them > > (sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel. > > > > It's ideal to keep common part for reusing. However, it's hard to find > > out a little which could be reused. The truth is there will be more > > and more different registers, bits and operatiing processes. > > Even some code is common now, it may have to be split in the future. > > So let's just split is as two drivers. > > > > Patch #2 just created a fsl_esdhc_imx driver which was a copy of > > fsl_esdhc driver for i.MX processors. > > Patch #3 converted i.MX platforms to use fsl_esdhc_imx. > > Patch #4 and #5 just dropped useless code for the two driver. > > There are still many cleaning up works needed to be done in the > > future, because the eSDHC driver is mess for a long time. > > Since I'm only owner for QorIQ eSDHC driver, I dropped only a little > > things which I'm sure for fsl_esdhc_imx. Let i.MX eSDHC owner do futhur > cleaning up. > > > > Yangbo Lu (5): > > Move CONFIG_FSL_ESDHC to defconfig > > mmc: split fsl_esdhc driver for i.MX > > Convert to use fsl_esdhc_imx for i.MX platforms > > mmc: fsl_esdhc: drop i.MX code > > mmc: fsl_esdhc_imx: drop useless code > > > > arch/arm/cpu/arm1136/mx35/generic.c | 10 +- > > arch/arm/cpu/arm926ejs/mx25/generic.c | 8 +- > > arch/arm/cpu/armv7/vf610/generic.c| 10 +- > > arch/arm/cpu/armv8/s32v234/generic.c | 2 +- > > arch/arm/include/asm/global_data.h| 2 +- > > arch/arm/mach-imx/cpu.c | 6 +- > > arch/arm/mach-imx/mx6/litesom.c | 4 +- > > arch/arm/mach-imx/mx7/clock.c | 4 +- > > arch/arm/mach-imx/mx7ulp/clock.c | 2 +- > > arch/arm/mach-imx/speed.c | 4 +- > > board/Arcturus/ucp1020/spl.c | 2 +- > > board/advantech/dms-ba16/dms-ba16.c | 4 +- > > board/aristainetos/aristainetos-v1.c | 2 +- > > board/aristainetos/aristainetos-v2.c | 2 +- > > board/aristainetos/aristainetos.c | 4 +- > > board/bachmann/ot1200/ot1200.c| 2 +- > > board/barco/platinum/platinum.c | 2 +- > > board/barco/titanium/titanium.c | 4 +- > > board/beckhoff/mx53cx9020/mx53cx9020.c| 4 +- > > board/boundary/nitrogen6x/nitrogen6x.c| 4 +- > > board/ccv/xpress/xpress.c | 2 +- > > board/compulab/cl-som-imx7/cl-som-imx7.c | 6 +- > > board/compulab/cl-som-imx7/common.c | 6 +- > > board/compulab/cl-som-imx7/common.h | 8 +- > > board/compulab/cl-som-imx7/mux.c | 8 +- > > board/compulab/cl-som-imx7/spl.c | 6 +- > > board/compulab/cm_fx6/cm_fx6.c| 4 +- > > board/compulab/cm_fx6/common.c| 4 +- > > board/compulab/cm_fx6/spl.c | 2 +- > > board/congatec/cgtqmx6eval/cgtqmx6eval.c | 4 +- > > board/dhelectronics/dh_imx6/dh_imx6.c | 4 +- > > board/dhelectronics/dh_imx6/dh_imx6_spl.c | 2 +- > > board/el/el6x/el6x.c | 4 +- > > board/embest/mx6boards/mx6boards.c| 4 +- > > board/freescale/imx8mq_evk/imx8mq_evk.c | 2 +- > > board/freescale/imx8mq_evk/spl.c | 2 +- > > board/freescale/imx8qxp_mek/imx8qxp_mek.c | 2 +- > > board/freescale/m54418twr/m54418twr.c | 2 +- > > b
Re: [U-Boot] [v2, 0/5] Split fsl_esdhc driver for i.MX
Any comments? Thanks a lot :) > -Original Message- > From: Y.b. Lu > Sent: Thursday, March 21, 2019 12:32 PM > To: u-boot@lists.denx.de > Cc: Prabhakar Kushwaha ; Peng Fan > ; sba...@denx.de; Y.b. Lu > Subject: [v2, 0/5] Split fsl_esdhc driver for i.MX > > The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX initially. > The later QoriQ series PowerPC processors (which were evolutions of > MPC83XX/MPC85XX), QorIQ series ARM processors, and i.MX series processors > were using this driver for their eSDHCs too. > > For the two series processors, the eSDHCs are becoming more and more > different. We should have split it into two drivers, like them > (sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel. > > It's ideal to keep common part for reusing. However, it's hard to find out a > little which could be reused. The truth is there will be more and more > different > registers, bits and operatiing processes. > Even some code is common now, it may have to be split in the future. > So let's just split is as two drivers. > > Patch #2 just created a fsl_esdhc_imx driver which was a copy of fsl_esdhc > driver for i.MX processors. > Patch #3 converted i.MX platforms to use fsl_esdhc_imx. > Patch #4 and #5 just dropped useless code for the two driver. > There are still many cleaning up works needed to be done in the future, > because the eSDHC driver is mess for a long time. > Since I'm only owner for QorIQ eSDHC driver, I dropped only a little things > which I'm sure for fsl_esdhc_imx. Let i.MX eSDHC owner do futhur cleaning up. > > Yangbo Lu (5): > Move CONFIG_FSL_ESDHC to defconfig > mmc: split fsl_esdhc driver for i.MX > Convert to use fsl_esdhc_imx for i.MX platforms > mmc: fsl_esdhc: drop i.MX code > mmc: fsl_esdhc_imx: drop useless code > > arch/arm/cpu/arm1136/mx35/generic.c | 10 +- > arch/arm/cpu/arm926ejs/mx25/generic.c | 8 +- > arch/arm/cpu/armv7/vf610/generic.c| 10 +- > arch/arm/cpu/armv8/s32v234/generic.c | 2 +- > arch/arm/include/asm/global_data.h| 2 +- > arch/arm/mach-imx/cpu.c | 6 +- > arch/arm/mach-imx/mx6/litesom.c | 4 +- > arch/arm/mach-imx/mx7/clock.c | 4 +- > arch/arm/mach-imx/mx7ulp/clock.c | 2 +- > arch/arm/mach-imx/speed.c | 4 +- > board/Arcturus/ucp1020/spl.c | 2 +- > board/advantech/dms-ba16/dms-ba16.c | 4 +- > board/aristainetos/aristainetos-v1.c | 2 +- > board/aristainetos/aristainetos-v2.c | 2 +- > board/aristainetos/aristainetos.c | 4 +- > board/bachmann/ot1200/ot1200.c| 2 +- > board/barco/platinum/platinum.c | 2 +- > board/barco/titanium/titanium.c | 4 +- > board/beckhoff/mx53cx9020/mx53cx9020.c| 4 +- > board/boundary/nitrogen6x/nitrogen6x.c| 4 +- > board/ccv/xpress/xpress.c | 2 +- > board/compulab/cl-som-imx7/cl-som-imx7.c | 6 +- > board/compulab/cl-som-imx7/common.c | 6 +- > board/compulab/cl-som-imx7/common.h | 8 +- > board/compulab/cl-som-imx7/mux.c | 8 +- > board/compulab/cl-som-imx7/spl.c | 6 +- > board/compulab/cm_fx6/cm_fx6.c| 4 +- > board/compulab/cm_fx6/common.c| 4 +- > board/compulab/cm_fx6/spl.c | 2 +- > board/congatec/cgtqmx6eval/cgtqmx6eval.c | 4 +- > board/dhelectronics/dh_imx6/dh_imx6.c | 4 +- > board/dhelectronics/dh_imx6/dh_imx6_spl.c | 2 +- > board/el/el6x/el6x.c | 4 +- > board/embest/mx6boards/mx6boards.c| 4 +- > board/freescale/imx8mq_evk/imx8mq_evk.c | 2 +- > board/freescale/imx8mq_evk/spl.c | 2 +- > board/freescale/imx8qxp_mek/imx8qxp_mek.c | 2 +- > board/freescale/m54418twr/m54418twr.c | 2 +- > board/freescale/mx25pdk/mx25pdk.c | 6 +- > board/freescale/mx35pdk/mx35pdk.c | 4 +- > board/freescale/mx51evk/mx51evk.c | 6 +- > board/freescale/mx53ard/mx53ard.c | 4 +- > board/freescale/mx53evk/mx53evk.c | 4 +- > board/freescale/mx53loco/mx53loco.c | 4 +- > board/freescale/mx53smd/mx53smd.c | 4 +- > board/freescale/mx6qarm2/mx6qarm2.c | 4 +- > board/freescale/mx6sabreauto/mx6sabreauto.c | 4 +- > board/freescale/mx6sabresd/mx6sabresd.c | 4 +- > board/freescale/mx6slevk/mx6slevk.c | 2 +- > .../freescale/mx6sxsabreauto/mx6sxsabreauto.c | 2 +- > board/free
[U-Boot] [v2, 5/5] mmc: fsl_esdhc_imx: drop useless code
Dropped useless code for i.MX eSDHC driver.
Signed-off-by: Yangbo Lu
---
Changes for v2:
- Added this patch.
---
drivers/mmc/fsl_esdhc_imx.c | 96 ++---
include/fsl_esdhc_imx.h | 4 --
2 files changed, 4 insertions(+), 96 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index a031c628ea..596542bec4 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -259,8 +259,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
{
int timeout;
struct fsl_esdhc *regs = priv->esdhc_regs;
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
dma_addr_t addr;
#endif
uint wml_value;
@@ -273,8 +272,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
esdhc_clrsetbits32(>wml, WML_RD_WML_MASK, wml_value);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
addr = virt_to_phys((void *)(data->dest));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -303,8 +301,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
esdhc_clrsetbits32(>wml, WML_WR_WML_MASK,
wml_value << 16);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
addr = virt_to_phys((void *)(data->src));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -369,8 +366,7 @@ static void check_and_invalidate_dcache_range
unsigned end = 0;
unsigned size = roundup(ARCH_DMA_MINALIGN,
data->blocks*data->blocksize);
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
dma_addr_t addr;
addr = virt_to_phys((void *)(data->dest));
@@ -385,25 +381,6 @@ static void check_and_invalidate_dcache_range
invalidate_dcache_range(start, end);
}
-#ifdef CONFIG_MCF5441x
-/*
- * Swaps 32-bit words to little-endian byte order.
- */
-static inline void sd_swap_dma_buff(struct mmc_data *data)
-{
- int i, size = data->blocksize >> 2;
- u32 *buffer = (u32 *)data->dest;
- u32 sw;
-
- while (data->blocks--) {
- for (i = 0; i < size; i++) {
- sw = __sw32(*buffer);
- *buffer++ = sw;
- }
- }
-}
-#endif
-
/*
* Sends a command out on the bus. Takes the mmc pointer,
* a command pointer, and an optional data pointer.
@@ -568,9 +545,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc,
*/
if (data->flags & MMC_DATA_READ) {
check_and_invalidate_dcache_range(cmd, data);
-#ifdef CONFIG_MCF5441x
- sd_swap_dma_buff(data);
-#endif
}
#endif
}
@@ -1053,12 +1027,8 @@ static int esdhc_init_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc)
/* Disable the BRR and BWR bits in IRQSTAT */
esdhc_clrbits32(>irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
-#ifdef CONFIG_MCF5441x
- esdhc_write32(>proctl, PROCTL_INIT | PROCTL_D3CD);
-#else
/* Put the PROCTL reg back to the default */
esdhc_write32(>proctl, PROCTL_INIT);
-#endif
/* Set timout to the maximum value */
esdhc_clrsetbits32(>sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
@@ -1166,11 +1136,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
if (ret)
return ret;
-#ifdef CONFIG_MCF5441x
- /* ColdFire, using SDHC_DATA[3] for card detection */
- esdhc_write32(>proctl, PROCTL_INIT | PROCTL_D3CD);
-#endif
-
#ifndef CONFIG_FSL_USDHC
esdhc_setbits32(>sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
| SYSCTL_IPGEN | SYSCTL_CKEN);
@@ -1195,15 +1160,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
voltage_caps = 0;
caps = esdhc_read32(>hostcapblt);
-#ifdef CONFIG_MCF5441x
- /*
-* MCF5441x RM declares in more points that sdhc clock speed must
-* never exceed 25 Mhz. From this, the HS bit needs to be disabled
-* from host capabilities.
-*/
- caps &= ~ESDHC_HOSTCAPBLT_HSS;
-#endif
-
[U-Boot] [v2, 4/5] mmc: fsl_esdhc: drop i.MX code
Dropped i.MX code which couldn't be reused.
Signed-off-by: Yangbo Lu
---
Changes for v2:
- Added this patch.
---
drivers/mmc/fsl_esdhc.c | 576 ++--
include/fsl_esdhc.h | 57
2 files changed, 15 insertions(+), 618 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 9e34557d16..3f4f75ae4c 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -16,14 +16,11 @@
#include
#include
#include
-#include
#include
#include
#include
#include
#include
-#include
-#include
DECLARE_GLOBAL_DATA_PTR;
@@ -33,8 +30,6 @@ DECLARE_GLOBAL_DATA_PTR;
IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE
| \
IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR
| \
IRQSTATEN_DINT)
-#define MAX_TUNING_LOOP 40
-
struct fsl_esdhc {
uintdsaddr; /* SDMA system address register */
uintblkattr;/* Block attributes register */
@@ -54,37 +49,20 @@ struct fsl_esdhc {
uintautoc12err; /* Auto CMD error status register */
uinthostcapblt; /* Host controller capabilities register */
uintwml;/* Watermark level register */
- uintmixctrl;/* For USDHC */
- charreserved1[4]; /* reserved */
+ charreserved1[8]; /* reserved */
uintfevt; /* Force event register */
uintadmaes; /* ADMA error status register */
uintadsaddr;/* ADMA system address register */
- charreserved2[4];
- uintdllctrl;
- uintdllstat;
- uintclktunectrlstatus;
- charreserved3[4];
- uintstrobe_dllctrl;
- uintstrobe_dllstat;
- charreserved4[72];
- uintvendorspec;
- uintmmcboot;
- uintvendorspec2;
- uinttuning_ctrl;/* on i.MX6/7/8 */
- charreserved5[44];
+ charreserved2[160];
uinthostver;/* Host controller version register */
- charreserved6[4]; /* reserved */
+ charreserved3[4]; /* reserved */
uintdmaerraddr; /* DMA error address register */
- charreserved7[4]; /* reserved */
+ charreserved4[4]; /* reserved */
uintdmaerrattr; /* DMA error attribute register */
- charreserved8[4]; /* reserved */
+ charreserved5[4]; /* reserved */
uinthostcapblt2;/* Host controller capabilities register 2 */
- charreserved9[8]; /* reserved */
- uinttcr;/* Tuning control register */
- charreserved10[28]; /* reserved */
- uintsddirctl; /* SD direction control register */
- charreserved11[712];/* reserved */
- uintscr;/* eSDHC control register */
+ charreserved6[756]; /* reserved */
+ uintesdhcctl; /* eSDHC control register */
};
struct fsl_esdhc_plat {
@@ -92,11 +70,6 @@ struct fsl_esdhc_plat {
struct mmc mmc;
};
-struct esdhc_soc_data {
- u32 flags;
- u32 caps;
-};
-
/**
* struct fsl_esdhc_priv
*
@@ -109,13 +82,6 @@ struct esdhc_soc_data {
* @dev: pointer for the device
* @non_removable: 0: removable; 1: non-removable
* @wp_enable: 1: enable checking wp; 0: no check
- * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
- * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
- * @caps: controller capabilities
- * @tuning_step: tuning step setting in tuning_ctrl register
- * @start_tuning_tap: the start point for tuning in tuning_ctrl register
- * @strobe_dll_delay_target: settings in strobe_dllctrl
- * @signal_voltage: indicating the current voltage
* @cd_gpio: gpio for card detection
* @wp_gpio: gpio for write protection
*/
@@ -124,7 +90,6 @@ struct fsl_esdhc_priv {
unsigned int sdhc_clk;
struct clk per_clk;
unsigned int clock;
- unsigned int mode;
unsigned int bus_width;
#if !CONFIG_IS_ENABLED(BLK)
struct mmc *mmc;
@@ -132,21 +97,6 @@ struct fsl_esdhc_priv {
struct udevice *dev;
int non_removable;
int wp_enable;
- int vs18_enable;
- u32 flags;
- u32 caps;
- u32 tuning_step;
- u32 tuning_start_tap;
- u32 strobe_dll_delay_target;
- u32 signal_voltage;
-#if IS_ENABLED(CONFIG_DM_REGULATOR)
- struct udevice *vqmmc_dev;
- struct udevice *vmmc_dev;
-#endif
-#ifdef CONFIG_DM_GPIO
- struct gpio_desc cd_gpio;
- struct gpio_desc wp_gpio;
-#endif
};
/* Return the XFERTYP flags for a given command and data packet */
@@ -258,8 +208,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
{
int timeout;
struct fsl_esdhc *regs = priv->esdhc_regs;
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
-
[U-Boot] [v2, 2/5] mmc: split fsl_esdhc driver for i.MX
The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
initially. The later QoriQ series PowerPC processors (which were
evolutions of MPC83XX/MPC85XX), QorIQ series ARM processors, and
i.MX series processors were using this driver for their eSDHCs too.
For the two series processors, the eSDHCs are becoming more and
more different. We should have split it into two drivers, like them
(sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel.
This patch is just to create a fsl_esdhc_imx driver which is a copy
of fsl_esdhc driver for i.MX processors. We will convert i.MX processors
to use fsl_esdhc_imx, and clean up the two drivers separately in the
future patches.
Signed-off-by: Yangbo Lu
---
Changes for v2:
- None.
---
drivers/mmc/Kconfig | 6 ++
drivers/mmc/Makefile | 1 +
drivers/mmc/{fsl_esdhc.c => fsl_esdhc_imx.c} | 5 +++--
include/{fsl_esdhc.h => fsl_esdhc_imx.h} | 11 ++-
4 files changed, 16 insertions(+), 7 deletions(-)
copy drivers/mmc/{fsl_esdhc.c => fsl_esdhc_imx.c} (99%)
copy include/{fsl_esdhc.h => fsl_esdhc_imx.h} (97%)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 04a4e7716f..09bc02fe9c 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -641,6 +641,12 @@ config FSL_ESDHC
This selects support for the eSDHC (enhanced secure digital host
controller) found on numerous Freescale/NXP SoCs.
+config FSL_ESDHC_IMX
+ bool "Freescale/NXP i.MX eSDHC controller support"
+ help
+ This selects support for the i.MX eSDHC (enhanced secure digital host
+ controller) found on numerous Freescale/NXP SoCs.
+
endmenu
config SYS_FSL_ERRATUM_ESDHC111
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 7892c468f0..1287ad4cc1 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_MMC_DW_K3) +=
hi6220_dw_mmc.o
obj-$(CONFIG_MMC_DW_ROCKCHIP) += rockchip_dw_mmc.o
obj-$(CONFIG_MMC_DW_SOCFPGA) += socfpga_dw_mmc.o
obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
+obj-$(CONFIG_FSL_ESDHC_IMX) += fsl_esdhc_imx.o
obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
obj-$(CONFIG_MMC_MESON_GX) += meson_gx_mmc.o
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc_imx.c
similarity index 99%
copy from drivers/mmc/fsl_esdhc.c
copy to drivers/mmc/fsl_esdhc_imx.c
index 9e34557d16..a031c628ea 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -2,6 +2,7 @@
/*
* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
* Andy Fleming
+ * Copyright 2019 NXP
*
* Based vaguely on the pxa mmc code:
* (C) Copyright 2003
@@ -18,7 +19,7 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
@@ -110,7 +111,7 @@ struct esdhc_soc_data {
* @non_removable: 0: removable; 1: non-removable
* @wp_enable: 1: enable checking wp; 0: no check
* @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
- * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
+ * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
* @caps: controller capabilities
* @tuning_step: tuning step setting in tuning_ctrl register
* @start_tuning_tap: the start point for tuning in tuning_ctrl register
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc_imx.h
similarity index 97%
copy from include/fsl_esdhc.h
copy to include/fsl_esdhc_imx.h
index 8dbd5249a7..e05b24e7e8 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc_imx.h
@@ -4,10 +4,11 @@
*---
*
* Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
+ * Copyright 2019 NXP
*/
-#ifndef __FSL_ESDHC_H__
-#define__FSL_ESDHC_H__
+#ifndef __FSL_ESDHC_IMX_H__
+#define __FSL_ESDHC_IMX_H__
#include
#include
@@ -258,15 +259,15 @@ struct fsl_esdhc_cfg {
#error "Endianess is not defined: please fix to continue"
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
int fsl_esdhc_mmc_init(bd_t *bis);
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
void fdt_fixup_esdhc(void *blob, bd_t *bd);
#else
static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
void __noreturn mmc_boot(void);
void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
-#endif /* __FSL_ESDHC_H__ */
+#endif /* __FSL_ESDHC_IMX_H__ */
--
2.17.1
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[U-Boot] [v2, 1/5] Move CONFIG_FSL_ESDHC to defconfig
Moved CONFIG_FSL_ESDHC from header files to defconfig files. Signed-off-by: Yangbo Lu --- Changes for v2: - Rebased. --- configs/imx8mq_evk_defconfig | 1 + configs/imx8qxp_mek_defconfig | 1 + configs/kp_imx53_defconfig | 1 + configs/kp_imx6q_tpc_defconfig | 1 + configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1012afrwy_qspi_defconfig | 1 + configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1012afrwy_tfa_defconfig | 1 + include/configs/imx8mq_evk.h | 1 - include/configs/imx8qxp_mek.h | 1 - include/configs/kp_imx53.h | 1 - include/configs/kp_imx6q_tpc.h | 1 - include/configs/ls1012afrwy.h | 1 - 13 files changed, 8 insertions(+), 5 deletions(-) diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 46100b6719..9e2ff29a04 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -28,6 +28,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_DM_ETH=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX8M=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index a94998b8b5..88da3ac784 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -51,6 +51,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ATHEROS=y diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig index cfe96fcce5..d00c8cde62 100644 --- a/configs/kp_imx53_defconfig +++ b/configs/kp_imx53_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx53-kp" CONFIG_ENV_IS_IN_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1 CONFIG_PHYLIB=y diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig index cb58ed6678..3f48463c0c 100644 --- a/configs/kp_imx6q_tpc_defconfig +++ b/configs/kp_imx6q_tpc_defconfig @@ -33,6 +33,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y CONFIG_FEC_MXC=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index d5034b7b26..9608141ab4 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -31,6 +31,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index 6fa13b205e..8b88b6df83 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -32,6 +32,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index 02f5dedfa2..676c588938 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -31,6 +31,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index 1da166e43a..92ea06951b 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -32,6 +32,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index a9e38a70e6..e15745018e 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -219,7 +219,6 @@ #define CONFIG_IMX_BOOTAUX #define CONFIG_CMD_MMC -#define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 312e30dc6c..c262736d8b 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -49,7 +49,6 @@ #undef CONFIG_CMD_CRC32 #undef CONFIG_BOOTM_NETBSD -#define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR0x5B01 diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index 080eec47ca..d0be94bdb9 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -16,7 +16,6 @@
[U-Boot] [v2, 0/5] Split fsl_esdhc driver for i.MX
The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX initially. The later QoriQ series PowerPC processors (which were evolutions of MPC83XX/MPC85XX), QorIQ series ARM processors, and i.MX series processors were using this driver for their eSDHCs too. For the two series processors, the eSDHCs are becoming more and more different. We should have split it into two drivers, like them (sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel. It's ideal to keep common part for reusing. However, it's hard to find out a little which could be reused. The truth is there will be more and more different registers, bits and operatiing processes. Even some code is common now, it may have to be split in the future. So let's just split is as two drivers. Patch #2 just created a fsl_esdhc_imx driver which was a copy of fsl_esdhc driver for i.MX processors. Patch #3 converted i.MX platforms to use fsl_esdhc_imx. Patch #4 and #5 just dropped useless code for the two driver. There are still many cleaning up works needed to be done in the future, because the eSDHC driver is mess for a long time. Since I'm only owner for QorIQ eSDHC driver, I dropped only a little things which I'm sure for fsl_esdhc_imx. Let i.MX eSDHC owner do futhur cleaning up. Yangbo Lu (5): Move CONFIG_FSL_ESDHC to defconfig mmc: split fsl_esdhc driver for i.MX Convert to use fsl_esdhc_imx for i.MX platforms mmc: fsl_esdhc: drop i.MX code mmc: fsl_esdhc_imx: drop useless code arch/arm/cpu/arm1136/mx35/generic.c | 10 +- arch/arm/cpu/arm926ejs/mx25/generic.c | 8 +- arch/arm/cpu/armv7/vf610/generic.c| 10 +- arch/arm/cpu/armv8/s32v234/generic.c | 2 +- arch/arm/include/asm/global_data.h| 2 +- arch/arm/mach-imx/cpu.c | 6 +- arch/arm/mach-imx/mx6/litesom.c | 4 +- arch/arm/mach-imx/mx7/clock.c | 4 +- arch/arm/mach-imx/mx7ulp/clock.c | 2 +- arch/arm/mach-imx/speed.c | 4 +- board/Arcturus/ucp1020/spl.c | 2 +- board/advantech/dms-ba16/dms-ba16.c | 4 +- board/aristainetos/aristainetos-v1.c | 2 +- board/aristainetos/aristainetos-v2.c | 2 +- board/aristainetos/aristainetos.c | 4 +- board/bachmann/ot1200/ot1200.c| 2 +- board/barco/platinum/platinum.c | 2 +- board/barco/titanium/titanium.c | 4 +- board/beckhoff/mx53cx9020/mx53cx9020.c| 4 +- board/boundary/nitrogen6x/nitrogen6x.c| 4 +- board/ccv/xpress/xpress.c | 2 +- board/compulab/cl-som-imx7/cl-som-imx7.c | 6 +- board/compulab/cl-som-imx7/common.c | 6 +- board/compulab/cl-som-imx7/common.h | 8 +- board/compulab/cl-som-imx7/mux.c | 8 +- board/compulab/cl-som-imx7/spl.c | 6 +- board/compulab/cm_fx6/cm_fx6.c| 4 +- board/compulab/cm_fx6/common.c| 4 +- board/compulab/cm_fx6/spl.c | 2 +- board/congatec/cgtqmx6eval/cgtqmx6eval.c | 4 +- board/dhelectronics/dh_imx6/dh_imx6.c | 4 +- board/dhelectronics/dh_imx6/dh_imx6_spl.c | 2 +- board/el/el6x/el6x.c | 4 +- board/embest/mx6boards/mx6boards.c| 4 +- board/freescale/imx8mq_evk/imx8mq_evk.c | 2 +- board/freescale/imx8mq_evk/spl.c | 2 +- board/freescale/imx8qxp_mek/imx8qxp_mek.c | 2 +- board/freescale/m54418twr/m54418twr.c | 2 +- board/freescale/mx25pdk/mx25pdk.c | 6 +- board/freescale/mx35pdk/mx35pdk.c | 4 +- board/freescale/mx51evk/mx51evk.c | 6 +- board/freescale/mx53ard/mx53ard.c | 4 +- board/freescale/mx53evk/mx53evk.c | 4 +- board/freescale/mx53loco/mx53loco.c | 4 +- board/freescale/mx53smd/mx53smd.c | 4 +- board/freescale/mx6qarm2/mx6qarm2.c | 4 +- board/freescale/mx6sabreauto/mx6sabreauto.c | 4 +- board/freescale/mx6sabresd/mx6sabresd.c | 4 +- board/freescale/mx6slevk/mx6slevk.c | 2 +- .../freescale/mx6sxsabreauto/mx6sxsabreauto.c | 2 +- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 2 +- .../mx6ul_14x14_evk/mx6ul_14x14_evk.c | 4 +- board/freescale/mx6ullevk/mx6ullevk.c | 2 +- board/freescale/mx7dsabresd/mx7dsabresd.c | 2 +- board/freescale/s32v234evb/s32v234evb.c | 4 +- board/freescale/vf610twr/vf610twr.c | 4 +- board/gateworks/gw_ventana/common.c | 6 +- board/gateworks/gw_ventana/gw_ventana.c | 2 +- board/ge/bx50v3/bx50v3.c | 4 +- board/ge/mx53ppd/mx53ppd.c| 4 +- board/grinn/liteboard/board.c | 4 +- board/inversepath/usbarmory/usbarmory.c | 2 +- board/k+p/kp_imx53/kp_imx53.c | 4
Re: [U-Boot] [PATCH 2/3] mmc: split fsl_esdhc driver for i.MX
Hi Stefano,
> -Original Message-
> From: Stefano Babic
> Sent: Wednesday, March 13, 2019 7:53 PM
> To: Y.b. Lu ; u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH 2/3] mmc: split fsl_esdhc driver for i.MX
>
> Hi Y.B lu,
>
> On 21/02/19 08:55, Y.b. Lu wrote:
> > The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
> > initially. The later QoriQ series PowerPC processors (which were
> > evolutions of MPC83XX/MPC85XX), QorIQ series ARM processors, and i.MX
> > series processors were using this driver for their eSDHCs too.
> >
> > For the two series processors, the eSDHCs are becoming more and more
> > different. We should have split it into two drivers, like them
> > (sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel.
> >
> > This patch is just to create a fsl_esdhc_imx driver which is a copy of
> > fsl_esdhc driver for i.MX processors. We will convert i.MX processors
> > to use fsl_esdhc_imx, and clean up the two drivers separately in the
> > future patches.
> >
> > Signed-off-by: Yangbo Lu
> > ---
> > drivers/mmc/Kconfig | 6 ++
> > drivers/mmc/Makefile | 1 +
> > drivers/mmc/{fsl_esdhc.c => fsl_esdhc_imx.c} | 5 +++--
> > include/{fsl_esdhc.h => fsl_esdhc_imx.h} | 11 ++-
> > 4 files changed, 16 insertions(+), 7 deletions(-) copy
> > drivers/mmc/{fsl_esdhc.c => fsl_esdhc_imx.c} (99%) copy
> > include/{fsl_esdhc.h => fsl_esdhc_imx.h} (97%)
> >
>
> IMHO we can do better - if we split the code, we should be able to factorize
> common code (if any) into a separate file and move the specific parts into
> processor specific files. And at the same time, clean up what is not required
> (for example, CONFIG_MCF5441x should not appear in imx code, and so on).
[Y.b. Lu] It's ideal to reuse common code. However I could find little which
could be re-used.
As you see in the driver, there is conditional compiling in almost each
function. (Some macros are specific for esdhc, and some are for esdhc_imx)
And the function is usually for a very basic function which is not worth to be
split for common part.
Even some functions which are not in conditional compiling are specific for
esdhc or esdhc_imx.
Besides, there will be two different registers structures for esdhc/esdhc_imx,
since they are having more and more different registers and bits.
So I suggest just to split them, and there will be two totally different driver
after cleaning up.
Regarding to MCF5441x, that's really a surprise to me. eSDHC actually is IP of
only Freescale/NXP processors.
I don’t know any detail about it. But we can keep it in esdhc driver after
splitting.
Do you think it's ok?
>
> > diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index
> > 04a4e7716f..09bc02fe9c 100644
> > --- a/drivers/mmc/Kconfig
> > +++ b/drivers/mmc/Kconfig
> > @@ -641,6 +641,12 @@ config FSL_ESDHC
> > This selects support for the eSDHC (enhanced secure digital host
> > controller) found on numerous Freescale/NXP SoCs.
> >
> > +config FSL_ESDHC_IMX
> > + bool "Freescale/NXP i.MX eSDHC controller support"
>
> We need a depend clause (ARCH_MX6, ARCH_MX5, ..)
[Y.b. Lu] Yes... Will add them.
>
> > + help
> > + This selects support for the i.MX eSDHC (enhanced secure digital host
> > + controller) found on numerous Freescale/NXP SoCs.
> > +
> > endmenu
> >
> > config SYS_FSL_ERRATUM_ESDHC111
> > diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index
> > 7892c468f0..1287ad4cc1 100644
> > --- a/drivers/mmc/Makefile
> > +++ b/drivers/mmc/Makefile
> > @@ -25,6 +25,7 @@ obj-$(CONFIG_MMC_DW_K3) +=
> hi6220_dw_mmc.o
> > obj-$(CONFIG_MMC_DW_ROCKCHIP) += rockchip_dw_mmc.o
> > obj-$(CONFIG_MMC_DW_SOCFPGA) += socfpga_dw_mmc.o
> > obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
> > +obj-$(CONFIG_FSL_ESDHC_IMX) += fsl_esdhc_imx.o
> > obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
> > obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
> > obj-$(CONFIG_MMC_MESON_GX) += meson_gx_mmc.o diff --git
> > a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc_imx.c similarity
> > index 99% copy from drivers/mmc/fsl_esdhc.c copy to
> > drivers/mmc/fsl_esdhc_imx.c index 21fa2ab1d4..9c823e86e2 100644
> > --- a/drivers/mmc/fsl_esdhc.c
> > +++ b/drivers/mmc/fsl_esdhc_imx.c
> > @@ -2,6 +2,7 @@
> > /*
> > * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
> > * Andy Fleming
> > + * Copyright 2019 NXP
> > *
> > * Based vaguely on the pxa mmc c
Re: [U-Boot] [PATCH 1/3] Move CONFIG_FSL_ESDHC to defconfig
Thanks a lot, Stefano. Please let me know if you need me to do anything. Once they are picked up, I will start the work for driver cleaning up. Best regards, Yangbo Lu > -Original Message- > From: Stefano Babic > Sent: Wednesday, March 13, 2019 2:14 AM > To: Y.b. Lu ; u-boot@lists.denx.de > Subject: Re: [U-Boot] [PATCH 1/3] Move CONFIG_FSL_ESDHC to defconfig > > Hi Y.B., > > On 01/03/19 04:15, Y.b. Lu wrote: > > Any comments on the patch-set? > > Thanks a lot. > > Patch is tin the right direction, it just touch (as it must be) a huge number > of > boards. I cannot pick it up now, so I will push it into my -next branch. > > Regards, > Stefano > > > > >> -Original Message- > >> From: Y.b. Lu > >> Sent: Thursday, February 21, 2019 3:55 PM > >> To: u-boot@lists.denx.de > >> Cc: Jaehoon Chung ; Prabhakar Kushwaha > >> ; Peng Fan ; Lukasz > >> Majewski ; Y.b. Lu > >> Subject: [PATCH 1/3] Move CONFIG_FSL_ESDHC to defconfig > >> > >> Moved CONFIG_FSL_ESDHC from header files to defconfig files. > >> > >> Signed-off-by: Yangbo Lu > >> --- > >> configs/imx8mq_evk_defconfig | 1 + > >> configs/imx8qxp_mek_defconfig | 1 + > >> configs/kp_imx53_defconfig | 1 + > >> configs/kp_imx6q_tpc_defconfig | 1 + > >> configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 1 + > >> configs/ls1012afrwy_qspi_defconfig | 1 + > >> configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 1 + > >> configs/ls1012afrwy_tfa_defconfig | 1 + > >> include/configs/imx8mq_evk.h | 1 - > >> include/configs/imx8qxp_mek.h | 1 - > >> include/configs/kp_imx53.h | 1 - > >> include/configs/kp_imx6q_tpc.h | 1 - > >> include/configs/ls1012afrwy.h | 1 - > >> 13 files changed, 8 insertions(+), 5 deletions(-) > >> > >> diff --git a/configs/imx8mq_evk_defconfig > >> b/configs/imx8mq_evk_defconfig index 53025e45bc..8f6d66b741 100644 > >> --- a/configs/imx8mq_evk_defconfig > >> +++ b/configs/imx8mq_evk_defconfig > >> @@ -27,6 +27,7 @@ CONFIG_DM_GPIO=y > >> CONFIG_DM_I2C=y > >> CONFIG_SYS_I2C_MXC=y > >> CONFIG_DM_MMC=y > >> +CONFIG_FSL_ESDHC=y > >> CONFIG_DM_ETH=y > >> CONFIG_PINCTRL=y > >> CONFIG_DM_REGULATOR=y > >> diff --git a/configs/imx8qxp_mek_defconfig > >> b/configs/imx8qxp_mek_defconfig index a94998b8b5..88da3ac784 100644 > >> --- a/configs/imx8qxp_mek_defconfig > >> +++ b/configs/imx8qxp_mek_defconfig > >> @@ -51,6 +51,7 @@ CONFIG_I2C_MUX=y > >> CONFIG_I2C_MUX_PCA954x=y > >> CONFIG_MISC=y > >> CONFIG_DM_MMC=y > >> +CONFIG_FSL_ESDHC=y > >> CONFIG_PHYLIB=y > >> CONFIG_PHY_ADDR_ENABLE=y > >> CONFIG_PHY_ATHEROS=y > >> diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig > >> index > >> cfe96fcce5..d00c8cde62 100644 > >> --- a/configs/kp_imx53_defconfig > >> +++ b/configs/kp_imx53_defconfig > >> @@ -29,6 +29,7 @@ CONFIG_CMD_FS_GENERIC=y > CONFIG_OF_CONTROL=y > >> CONFIG_DEFAULT_DEVICE_TREE="imx53-kp" > >> CONFIG_ENV_IS_IN_MMC=y > >> +CONFIG_FSL_ESDHC=y > >> CONFIG_I2C_SET_DEFAULT_BUS_NUM=y > >> CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1 > >> CONFIG_PHYLIB=y > >> diff --git a/configs/kp_imx6q_tpc_defconfig > >> b/configs/kp_imx6q_tpc_defconfig index cb58ed6678..3f48463c0c 100644 > >> --- a/configs/kp_imx6q_tpc_defconfig > >> +++ b/configs/kp_imx6q_tpc_defconfig > >> @@ -33,6 +33,7 @@ CONFIG_CMD_EXT4_WRITE=y # > CONFIG_ISO_PARTITION is > >> not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y > >> +CONFIG_FSL_ESDHC=y > >> CONFIG_PHYLIB=y > >> CONFIG_PHY_ATHEROS=y > >> CONFIG_FEC_MXC=y > >> diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig > >> b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig > >> index c273dc937e..35a606ce23 100644 > >> --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig > >> +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig > >> @@ -30,6 +30,7 @@ CONFIG_NET_RANDOM_ETHADDR=y > CONFIG_DM=y # > >> CONFIG_BLK is not set CONFIG_DM_MMC=y > >> +CONFIG_FSL_ESDHC=y > >> CONFIG_DM_SPI_FLASH=y > >> CONFIG_SPI_FLASH=y > >> CONFIG_SPI_FLASH_WINBOND=y &g
Re: [U-Boot] [PATCH 1/3] Move CONFIG_FSL_ESDHC to defconfig
Any comments on the patch-set? Thanks a lot. > -Original Message- > From: Y.b. Lu > Sent: Thursday, February 21, 2019 3:55 PM > To: u-boot@lists.denx.de > Cc: Jaehoon Chung ; Prabhakar Kushwaha > ; Peng Fan ; Lukasz > Majewski ; Y.b. Lu > Subject: [PATCH 1/3] Move CONFIG_FSL_ESDHC to defconfig > > Moved CONFIG_FSL_ESDHC from header files to defconfig files. > > Signed-off-by: Yangbo Lu > --- > configs/imx8mq_evk_defconfig | 1 + > configs/imx8qxp_mek_defconfig | 1 + > configs/kp_imx53_defconfig | 1 + > configs/kp_imx6q_tpc_defconfig | 1 + > configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 1 + > configs/ls1012afrwy_qspi_defconfig | 1 + > configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 1 + > configs/ls1012afrwy_tfa_defconfig | 1 + > include/configs/imx8mq_evk.h | 1 - > include/configs/imx8qxp_mek.h | 1 - > include/configs/kp_imx53.h | 1 - > include/configs/kp_imx6q_tpc.h | 1 - > include/configs/ls1012afrwy.h | 1 - > 13 files changed, 8 insertions(+), 5 deletions(-) > > diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig > index 53025e45bc..8f6d66b741 100644 > --- a/configs/imx8mq_evk_defconfig > +++ b/configs/imx8mq_evk_defconfig > @@ -27,6 +27,7 @@ CONFIG_DM_GPIO=y > CONFIG_DM_I2C=y > CONFIG_SYS_I2C_MXC=y > CONFIG_DM_MMC=y > +CONFIG_FSL_ESDHC=y > CONFIG_DM_ETH=y > CONFIG_PINCTRL=y > CONFIG_DM_REGULATOR=y > diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig > index a94998b8b5..88da3ac784 100644 > --- a/configs/imx8qxp_mek_defconfig > +++ b/configs/imx8qxp_mek_defconfig > @@ -51,6 +51,7 @@ CONFIG_I2C_MUX=y > CONFIG_I2C_MUX_PCA954x=y > CONFIG_MISC=y > CONFIG_DM_MMC=y > +CONFIG_FSL_ESDHC=y > CONFIG_PHYLIB=y > CONFIG_PHY_ADDR_ENABLE=y > CONFIG_PHY_ATHEROS=y > diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig index > cfe96fcce5..d00c8cde62 100644 > --- a/configs/kp_imx53_defconfig > +++ b/configs/kp_imx53_defconfig > @@ -29,6 +29,7 @@ CONFIG_CMD_FS_GENERIC=y > CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx53-kp" > CONFIG_ENV_IS_IN_MMC=y > +CONFIG_FSL_ESDHC=y > CONFIG_I2C_SET_DEFAULT_BUS_NUM=y > CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1 > CONFIG_PHYLIB=y > diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig > index cb58ed6678..3f48463c0c 100644 > --- a/configs/kp_imx6q_tpc_defconfig > +++ b/configs/kp_imx6q_tpc_defconfig > @@ -33,6 +33,7 @@ CONFIG_CMD_EXT4_WRITE=y # > CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set > CONFIG_ENV_IS_IN_MMC=y > +CONFIG_FSL_ESDHC=y > CONFIG_PHYLIB=y > CONFIG_PHY_ATHEROS=y > CONFIG_FEC_MXC=y > diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig > b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig > index c273dc937e..35a606ce23 100644 > --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig > +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig > @@ -30,6 +30,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y > # CONFIG_BLK is not set CONFIG_DM_MMC=y > +CONFIG_FSL_ESDHC=y > CONFIG_DM_SPI_FLASH=y > CONFIG_SPI_FLASH=y > CONFIG_SPI_FLASH_WINBOND=y > diff --git a/configs/ls1012afrwy_qspi_defconfig > b/configs/ls1012afrwy_qspi_defconfig > index 85523ba2d3..50068a12d7 100644 > --- a/configs/ls1012afrwy_qspi_defconfig > +++ b/configs/ls1012afrwy_qspi_defconfig > @@ -31,6 +31,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y > # CONFIG_BLK is not set CONFIG_DM_MMC=y > +CONFIG_FSL_ESDHC=y > CONFIG_DM_SPI_FLASH=y > CONFIG_SPI_FLASH=y > CONFIG_SPI_FLASH_WINBOND=y > diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig > b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig > index d9020c5281..1b281c90a2 100644 > --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig > +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig > @@ -30,6 +30,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y > # CONFIG_BLK is not set CONFIG_DM_MMC=y > +CONFIG_FSL_ESDHC=y > CONFIG_DM_SPI_FLASH=y > CONFIG_SPI_FLASH=y > CONFIG_SPI_FLASH_WINBOND=y > diff --git a/configs/ls1012afrwy_tfa_defconfig > b/configs/ls1012afrwy_tfa_defconfig > index 08b3692f97..060cf47156 100644 > --- a/configs/ls1012afrwy_tfa_defconfig > +++ b/configs/ls1012afrwy_tfa_defconfig > @@ -31,6 +31,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y > # CONFIG_BLK is not set CONFIG_DM_MMC=y > +CONFIG_FSL_ESDHC=y > CONFIG_DM_SPI_FLASH=y > CONFIG_SPI_FLASH=y > CONFIG_SPI_FLASH_WINBOND=y > diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h >
Re: [U-Boot] [v2, 1/3] mmc: fsl_esdhc: add esdhc_imx flag
[...] > > > > > > My current patch-set is also to cleaning up the driver waiting for > > > splitting them someday on the other hand. After you check > > > CONFIG_FSL_ESDHC in u-boot source, if you think it's better we > > > should split them right now, I could work on the driver splitting. > > > > You can think about having common part (in one file - fsl_esdhc.c) and > > then separate files with code specific to imx and ppc. This would > > reduce the number of changes needed. > > [Y.b. Lu] Actually, it's not only imx and ppc. > In linux, esdhc driver is for MPC83XX/MPC85XX, QorIQ PowerPC processors, > QoriQ ARM processors (Layerscape). > Esdhc-imx driver is for i.MX processors. > > Anyway there would be a lot files changed if we split the driver. Let me send > out a patch-set to split them for your reviewing. > Thanks a lot for your comments. > [Y.b. Lu] Any comments or suggestions on the patch-set. Thanks a lot :) http://patchwork.ozlabs.org/project/uboot/list/?series=93317=* [...] ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/3] mmc: split fsl_esdhc driver for i.MX
The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
initially. The later QoriQ series PowerPC processors (which were
evolutions of MPC83XX/MPC85XX), QorIQ series ARM processors, and
i.MX series processors were using this driver for their eSDHCs too.
For the two series processors, the eSDHCs are becoming more and
more different. We should have split it into two drivers, like them
(sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel.
This patch is just to create a fsl_esdhc_imx driver which is a copy
of fsl_esdhc driver for i.MX processors. We will convert i.MX processors
to use fsl_esdhc_imx, and clean up the two drivers separately in the
future patches.
Signed-off-by: Yangbo Lu
---
drivers/mmc/Kconfig | 6 ++
drivers/mmc/Makefile | 1 +
drivers/mmc/{fsl_esdhc.c => fsl_esdhc_imx.c} | 5 +++--
include/{fsl_esdhc.h => fsl_esdhc_imx.h} | 11 ++-
4 files changed, 16 insertions(+), 7 deletions(-)
copy drivers/mmc/{fsl_esdhc.c => fsl_esdhc_imx.c} (99%)
copy include/{fsl_esdhc.h => fsl_esdhc_imx.h} (97%)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 04a4e7716f..09bc02fe9c 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -641,6 +641,12 @@ config FSL_ESDHC
This selects support for the eSDHC (enhanced secure digital host
controller) found on numerous Freescale/NXP SoCs.
+config FSL_ESDHC_IMX
+ bool "Freescale/NXP i.MX eSDHC controller support"
+ help
+ This selects support for the i.MX eSDHC (enhanced secure digital host
+ controller) found on numerous Freescale/NXP SoCs.
+
endmenu
config SYS_FSL_ERRATUM_ESDHC111
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 7892c468f0..1287ad4cc1 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_MMC_DW_K3) +=
hi6220_dw_mmc.o
obj-$(CONFIG_MMC_DW_ROCKCHIP) += rockchip_dw_mmc.o
obj-$(CONFIG_MMC_DW_SOCFPGA) += socfpga_dw_mmc.o
obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
+obj-$(CONFIG_FSL_ESDHC_IMX) += fsl_esdhc_imx.o
obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
obj-$(CONFIG_MMC_MESON_GX) += meson_gx_mmc.o
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc_imx.c
similarity index 99%
copy from drivers/mmc/fsl_esdhc.c
copy to drivers/mmc/fsl_esdhc_imx.c
index 21fa2ab1d4..9c823e86e2 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -2,6 +2,7 @@
/*
* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
* Andy Fleming
+ * Copyright 2019 NXP
*
* Based vaguely on the pxa mmc code:
* (C) Copyright 2003
@@ -18,7 +19,7 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
@@ -110,7 +111,7 @@ struct esdhc_soc_data {
* @non_removable: 0: removable; 1: non-removable
* @wp_enable: 1: enable checking wp; 0: no check
* @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
- * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
+ * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
* @caps: controller capabilities
* @tuning_step: tuning step setting in tuning_ctrl register
* @start_tuning_tap: the start point for tuning in tuning_ctrl register
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc_imx.h
similarity index 97%
copy from include/fsl_esdhc.h
copy to include/fsl_esdhc_imx.h
index 8dbd5249a7..e05b24e7e8 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc_imx.h
@@ -4,10 +4,11 @@
*---
*
* Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
+ * Copyright 2019 NXP
*/
-#ifndef __FSL_ESDHC_H__
-#define__FSL_ESDHC_H__
+#ifndef __FSL_ESDHC_IMX_H__
+#define __FSL_ESDHC_IMX_H__
#include
#include
@@ -258,15 +259,15 @@ struct fsl_esdhc_cfg {
#error "Endianess is not defined: please fix to continue"
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
int fsl_esdhc_mmc_init(bd_t *bis);
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
void fdt_fixup_esdhc(void *blob, bd_t *bd);
#else
static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
void __noreturn mmc_boot(void);
void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
-#endif /* __FSL_ESDHC_H__ */
+#endif /* __FSL_ESDHC_IMX_H__ */
--
2.17.1
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Re: [U-Boot] [v2, 1/3] mmc: fsl_esdhc: add esdhc_imx flag
Hi Lukasz,
> -Original Message-
> From: Lukasz Majewski
> Sent: Tuesday, February 19, 2019 2:39 PM
> To: Y.b. Lu
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] [v2, 1/3] mmc: fsl_esdhc: add esdhc_imx flag
>
> Hi "Y.b. Lu",
>
> > Hi Lukasz,
> >
> > > -Original Message-
> > > From: Lukasz Majewski
> > > Sent: Monday, February 18, 2019 7:12 AM
> > > To: Y.b. Lu
> > > Cc: u-boot@lists.denx.de
> > > Subject: Re: [U-Boot] [v2, 1/3] mmc: fsl_esdhc: add esdhc_imx flag
> > >
> > > Dear "Y.b. Lu",
> > >
> > > > The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
> > > > initially. The later QoriQ series processors (which were
> > > > evolutions of MPC83XX/MPC85XX) and i.MX series processors were
> > > > using this driver for their eSDHCs too.
> > > >
> > > > So there are two evolution directions for eSDHC now. For the two
> > > > series processors, the eSDHCs are becoming more and more
> > > > different. We should have split it into two drivers, like them
> > > > (sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel.
> > >
> > > Why we cannot do it right just from the very beginning?
> > >
> > > In the end of the day we will try to mimic Linux kernel anyway, IMHO
> > > it is better to start the split now and save some effort on a
> > > half-step solution.
> >
> > [Y.b. Lu] I understand. The perfect way is to split them.
> > However, if you grep 'CONFIG_FSL_ESDHC' in the whole u-boot source,
> > you would find there are 607 results.
>
> Those are boards, which use the driver. The modification would be done in one
> or two files (fsl_esdhc.c|h).
[Y.b. Lu] Sorry, I can't get your point.
Since we split fsl_esdhc into fsl_esdhc and fsl_esdhc_imx driver, all i.mx
boards files should convert to use new CONFIG_FSL_ESDHC_IMX instead as I
understand.
>
> > There will be so many companies
> > boards affected.
>
> I guess that the task of your patch set is to separate imx6q and ppc specific
> code for those IP blocks.
>
> > I just don't know who could make all of these boards tested.
>
> Your patch set also makes some changes in the generic driver depending on
> the priv->esdhc_imx flag. Those changes also need to be tested on all before
> mentioned boards.
[Y.b. Lu] Right...
>
> In the end you logically split the driver, having it in a single file, which
> IMHO is
> not proper long-term solution.
>
> >
> > My current patch-set is also to cleaning up the driver waiting for
> > splitting them someday on the other hand. After you check
> > CONFIG_FSL_ESDHC in u-boot source, if you think it's better we should
> > split them right now, I could work on the driver splitting.
>
> You can think about having common part (in one file - fsl_esdhc.c) and then
> separate files with code specific to imx and ppc. This would reduce the number
> of changes needed.
[Y.b. Lu] Actually, it's not only imx and ppc.
In linux, esdhc driver is for MPC83XX/MPC85XX, QorIQ PowerPC processors, QoriQ
ARM processors (Layerscape).
Esdhc-imx driver is for i.MX processors.
Anyway there would be a lot files changed if we split the driver. Let me send
out a patch-set to split them for your reviewing.
Thanks a lot for your comments.
>
> >
> > Thanks a lot.
> >
> > > > But it seemed
> > > > to be a lot of work now. So let's keep as it is. Be very careful
> > > > to change the driver if the changes are not common for all eSDHCs,
> > > > and clarify i.MX eSDHC specific things to distingush them with
> > > > QorIQ eSDHC.
> > > >
> > > > This patch is to added an esdhc_imx flag for the development of
> > > > i.MX eSDHC, to distinguish it with QoriQ eSDHC.
> > > >
> > > > Signed-off-by: Yangbo Lu
> > > > ---
> > > > Changes for v2:
> > > > - Converted to use device_is_compatible().
> > > > ---
> > > > drivers/mmc/fsl_esdhc.c | 11 +++
> > > > 1 file changed, 11 insertions(+)
> > > >
> > > > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> > > > index 21fa2ab1d4..a647bc7f1c 100644
> > > > --- a/drivers/mmc/fsl_esdhc.c
> > > > +++ b/drivers/mmc/fsl_esdhc.c
> > > > @@ -147,6 +147,7 @@ struct fsl_esdhc_priv {
> > > > struct gpio_desc cd_gpio;
> > > > struct gpio_desc wp_gpio;
> > > > #endif
> > > > +
[U-Boot] [PATCH 1/3] Move CONFIG_FSL_ESDHC to defconfig
Moved CONFIG_FSL_ESDHC from header files to defconfig files. Signed-off-by: Yangbo Lu --- configs/imx8mq_evk_defconfig | 1 + configs/imx8qxp_mek_defconfig | 1 + configs/kp_imx53_defconfig | 1 + configs/kp_imx6q_tpc_defconfig | 1 + configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1012afrwy_qspi_defconfig | 1 + configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1012afrwy_tfa_defconfig | 1 + include/configs/imx8mq_evk.h | 1 - include/configs/imx8qxp_mek.h | 1 - include/configs/kp_imx53.h | 1 - include/configs/kp_imx6q_tpc.h | 1 - include/configs/ls1012afrwy.h | 1 - 13 files changed, 8 insertions(+), 5 deletions(-) diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 53025e45bc..8f6d66b741 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -27,6 +27,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_DM_ETH=y CONFIG_PINCTRL=y CONFIG_DM_REGULATOR=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index a94998b8b5..88da3ac784 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -51,6 +51,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ATHEROS=y diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig index cfe96fcce5..d00c8cde62 100644 --- a/configs/kp_imx53_defconfig +++ b/configs/kp_imx53_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx53-kp" CONFIG_ENV_IS_IN_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1 CONFIG_PHYLIB=y diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig index cb58ed6678..3f48463c0c 100644 --- a/configs/kp_imx6q_tpc_defconfig +++ b/configs/kp_imx6q_tpc_defconfig @@ -33,6 +33,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y CONFIG_FEC_MXC=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index c273dc937e..35a606ce23 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -30,6 +30,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y # CONFIG_BLK is not set CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index 85523ba2d3..50068a12d7 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -31,6 +31,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y # CONFIG_BLK is not set CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index d9020c5281..1b281c90a2 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -30,6 +30,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y # CONFIG_BLK is not set CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index 08b3692f97..060cf47156 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -31,6 +31,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y # CONFIG_BLK is not set CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index f0430224cb..492e89a20c 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -220,7 +220,6 @@ #define CONFIG_IMX_BOOTAUX #define CONFIG_CMD_MMC -#define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 312e30dc6c..c262736d8b 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -49,7 +49,6 @@ #undef CONFIG_CMD_CRC32 #undef CONFIG_BOOTM_NETBSD -#define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR0x5B01 diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index 080eec47ca..d0be94bdb9 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -16,7 +16,6 @@ #define
Re: [U-Boot] [v2, 1/3] mmc: fsl_esdhc: add esdhc_imx flag
Hi Lukasz,
> -Original Message-
> From: Lukasz Majewski
> Sent: Monday, February 18, 2019 7:12 AM
> To: Y.b. Lu
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] [v2, 1/3] mmc: fsl_esdhc: add esdhc_imx flag
>
> Dear "Y.b. Lu",
>
> > The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
> > initially. The later QoriQ series processors (which were evolutions of
> > MPC83XX/MPC85XX) and i.MX series processors were using this driver for
> > their eSDHCs too.
> >
> > So there are two evolution directions for eSDHC now. For the two
> > series processors, the eSDHCs are becoming more and more different.
> > We should have split it into two drivers, like them
> > (sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel.
>
> Why we cannot do it right just from the very beginning?
>
> In the end of the day we will try to mimic Linux kernel anyway, IMHO it is
> better to start the split now and save some effort on a half-step solution.
>
[Y.b. Lu] I understand. The perfect way is to split them.
However, if you grep 'CONFIG_FSL_ESDHC' in the whole u-boot source, you would
find there are 607 results.
There will be so many companies boards affected. I just don't know who could
make all of these boards tested.
My current patch-set is also to cleaning up the driver waiting for splitting
them someday on the other hand.
After you check CONFIG_FSL_ESDHC in u-boot source, if you think it's better we
should split them right now, I could work on the driver splitting.
Thanks a lot.
> > But it seemed
> > to be a lot of work now. So let's keep as it is. Be very careful to
> > change the driver if the changes are not common for all eSDHCs, and
> > clarify i.MX eSDHC specific things to distingush them with QorIQ
> > eSDHC.
> >
> > This patch is to added an esdhc_imx flag for the development of i.MX
> > eSDHC, to distinguish it with QoriQ eSDHC.
> >
> > Signed-off-by: Yangbo Lu
> > ---
> > Changes for v2:
> > - Converted to use device_is_compatible().
> > ---
> > drivers/mmc/fsl_esdhc.c | 11 +++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index
> > 21fa2ab1d4..a647bc7f1c 100644
> > --- a/drivers/mmc/fsl_esdhc.c
> > +++ b/drivers/mmc/fsl_esdhc.c
> > @@ -147,6 +147,7 @@ struct fsl_esdhc_priv {
> > struct gpio_desc cd_gpio;
> > struct gpio_desc wp_gpio;
> > #endif
> > + bool esdhc_imx;
> > };
> >
> > /* Return the XFERTYP flags for a given command and data packet */ @@
> > -1462,6 +1463,16 @@ static int fsl_esdhc_probe(struct udevice *dev)
> > priv->caps = data->caps;
> > }
> >
> > + /*
> > +* This is to specify whether current eSDHC is an i.MX eSDHC,
> > +* since the i.MX eSDHC has been becoming more and more
> > different
> > +* with QorIQ eSDHC and initial MPC83XX/MPC85XX.
> > +*/
> > + if (!device_is_compatible(dev, "fsl,esdhc"))
> > + priv->esdhc_imx = true;
> > + else
> > + priv->esdhc_imx = false;
> > +
> > val = dev_read_u32_default(dev, "bus-width", -1);
> > if (val == 8)
> > priv->bus_width = 8;
>
>
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lu...@denx.de
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] mmc: fsl_esdhc: add esdhc_imx flag
> -Original Message- > From: Peng Fan > Sent: Thursday, February 14, 2019 5:11 PM > To: Y.b. Lu ; u-boot@lists.denx.de > Cc: Jaehoon Chung ; Prabhakar Kushwaha > > Subject: RE: [PATCH 1/3] mmc: fsl_esdhc: add esdhc_imx flag > > > > > -----Original Message- > > From: Y.b. Lu > > Sent: 2019年2月14日 16:21 > > To: u-boot@lists.denx.de > > Cc: Jaehoon Chung ; Prabhakar Kushwaha > > ; Peng Fan ; Y.b. Lu > > > > Subject: [PATCH 1/3] mmc: fsl_esdhc: add esdhc_imx flag > > [...] > > + /* > > +* This is to specify whether current eSDHC is an i.MX eSDHC, > > +* since the i.MX eSDHC has been becoming more and more different > > +* with QorIQ eSDHC and initial MPC83XX/MPC85XX. > > +*/ > > + if (!fdt_node_check_compatible(fdt, node, "fsl,esdhc")) > > + priv->esdhc_imx = true; > > + else > > + priv->esdhc_imx = false; > > Suggest use device_is_compatible(dev, "fsl,esdhc") > > Regards, > Peng. > [Y.b. Lu] Sent out v2, and converted to use device_is_compatible(). Thanks a lot. > > + > > val = dev_read_u32_default(dev, "bus-width", -1); > > if (val == 8) > > priv->bus_width = 8; > > -- > > 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [v2, 2/3] mmc: fsl_esdhc: clean up register definition
The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
initially. The later QoriQ series processors (which are evolutions
of MPC83XX/MPC85XX) and i.MX series processors were using this
driver for their eSDHCs too.
So there are two evolution directions for eSDHC now. For the two
series processors, the eSDHCs are becoming more and more different.
We should have split it into two drivers, like them
(sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel. But it seemed
to be a lot of work now. So let's keep as it is. Be very careful to
change the driver if the changes are not common for all eSDHCs, and
clarify i.MX eSDHC specific things to distingush them with QorIQ
eSDHC.
This patch is to clean up register definition. Besides the QorIQ
eSDHC register definition, the i.MX eSDHC specific registers should
be clarified.
Signed-off-by: Yangbo Lu
Acked-by: Peng Fan
---
Changes for v2:
- Added "Acked-by: Peng Fan".
---
drivers/mmc/fsl_esdhc.c | 66 ++---
include/fsl_esdhc.h | 208 ++--
2 files changed, 149 insertions(+), 125 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index a647bc7f1c..e9622ce9a4 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -54,23 +54,23 @@ struct fsl_esdhc {
uintautoc12err; /* Auto CMD error status register */
uinthostcapblt; /* Host controller capabilities register */
uintwml;/* Watermark level register */
- uintmixctrl;/* For USDHC */
+ uintmixctrl;/* For i.MX USDHC */
charreserved1[4]; /* reserved */
uintfevt; /* Force event register */
uintadmaes; /* ADMA error status register */
uintadsaddr;/* ADMA system address register */
charreserved2[4];
- uintdllctrl;
- uintdllstat;
- uintclktunectrlstatus;
+ uintdllctrl;/* For i.MX USDHC */
+ uintdllstat;/* For i.MX USDHC */
+ uintclktunectrlstatus; /* For i.MX USDHC */
charreserved3[4];
- uintstrobe_dllctrl;
- uintstrobe_dllstat;
+ uintstrobe_dllctrl; /* For i.MX USDHC */
+ uintstrobe_dllstat; /* For i.MX USDHC */
charreserved4[72];
- uintvendorspec;
- uintmmcboot;
- uintvendorspec2;
- uinttuning_ctrl;/* on i.MX6/7/8 */
+ uintvendorspec; /* For i.MX USDHC */
+ uintmmcboot;/* For i.MX USDHC */
+ uintvendorspec2;/* For i.MX USDHC */
+ uinttuning_ctrl;/* For i.MX USDHC, on i.MX6/7/8 */
charreserved5[44];
uinthostver;/* Host controller version register */
charreserved6[4]; /* reserved */
@@ -80,11 +80,11 @@ struct fsl_esdhc {
charreserved8[4]; /* reserved */
uinthostcapblt2;/* Host controller capabilities register 2 */
charreserved9[8]; /* reserved */
- uinttcr;/* Tuning control register */
+ uinttbctl; /* Tuning block control register */
charreserved10[28]; /* reserved */
uintsddirctl; /* SD direction control register */
charreserved11[712];/* reserved */
- uintscr;/* eSDHC control register */
+ uintesdhcctl; /* eSDHC control register */
};
struct fsl_esdhc_plat {
@@ -496,7 +496,7 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc,
/* Switch voltage to 1.8V if CMD11 succeeded */
if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
- esdhc_setbits32(>vendorspec, ESDHC_VENDORSPEC_VSELECT);
+ esdhc_setbits32(>vendorspec, VENDORSPEC_VSELECT);
printf("Run CMD11 1.8V switch\n");
/* Sleep for 5 ms - max time for card to switch to 1.8V */
@@ -728,23 +728,23 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
struct fsl_esdhc *regs = priv->esdhc_regs;
u32 val;
- if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
- writel(ESDHC_STROBE_DLL_CTRL_RESET, >strobe_dllctrl);
+ if (priv->clock > STROBE_DLL_CLK_FREQ) {
+ writel(STROBE_DLL_CTRL_RESET, >strobe_dllctrl);
/*
* enable strobe dll ctrl and adjust the delay target
* for the uSDHC loopback read clock
*/
- val = ESDHC_STROBE_DLL_CTRL_ENABLE |
+ val = STROBE_DLL_CTRL_ENABLE |
(priv->strobe_dll_delay_target <<
-ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
+STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
writel(val, >strobe_dllctrl);
/* wait 1us to make sure strobe dll status register stable */
mdelay(1);
[U-Boot] [v2, 3/3] mmc: fsl_esdhc: clarify i.MX eSDHC specific functions
A previous patch had added SDR104/HS200 support for fsl_esdhc.
However this was only for i.MX eSDHC, and QorIQ eSDHC used
different registers and method.
This patch is to clarify i.MX eSDHC specific functions defined
in that patch, and to use them only for i.MX eSDHC. The QorIQ
eSDHC SDR104/HS200 support will be added in the future.
Fixes: 51313b49f2b8 (mmc: fsl_esdhc: support SDR104 and HS200)
Signed-off-by: Yangbo Lu
Reviewed-by: Peng Fan
---
Changes for v2:
- Added "Reviewed-by: Peng Fan".
---
drivers/mmc/fsl_esdhc.c | 79 +
1 file changed, 41 insertions(+), 38 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index e9622ce9a4..92924b63ac 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -682,7 +682,7 @@ static void esdhc_clock_control(struct fsl_esdhc_priv
*priv, bool enable)
#endif
#ifdef MMC_SUPPORTS_TUNING
-static int esdhc_change_pinstate(struct udevice *dev)
+static int esdhc_imx_change_pinstate(struct udevice *dev)
{
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
int ret;
@@ -708,7 +708,7 @@ static int esdhc_change_pinstate(struct udevice *dev)
return ret;
}
-static void esdhc_reset_tuning(struct mmc *mmc)
+static void esdhc_imx_reset_tuning(struct mmc *mmc)
{
struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
struct fsl_esdhc *regs = priv->esdhc_regs;
@@ -722,7 +722,7 @@ static void esdhc_reset_tuning(struct mmc *mmc)
}
}
-static void esdhc_set_strobe_dll(struct mmc *mmc)
+static void esdhc_imx_set_strobe_dll(struct mmc *mmc)
{
struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
struct fsl_esdhc *regs = priv->esdhc_regs;
@@ -749,7 +749,7 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
}
}
-static int esdhc_set_timing(struct mmc *mmc)
+static int esdhc_imx_set_timing(struct mmc *mmc)
{
struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
struct fsl_esdhc *regs = priv->esdhc_regs;
@@ -761,13 +761,13 @@ static int esdhc_set_timing(struct mmc *mmc)
switch (mmc->selected_mode) {
case MMC_LEGACY:
case SD_LEGACY:
- esdhc_reset_tuning(mmc);
+ esdhc_imx_reset_tuning(mmc);
writel(mixctrl, >mixctrl);
break;
case MMC_HS_400:
mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
writel(mixctrl, >mixctrl);
- esdhc_set_strobe_dll(mmc);
+ esdhc_imx_set_strobe_dll(mmc);
break;
case MMC_HS:
case MMC_HS_52:
@@ -791,14 +791,13 @@ static int esdhc_set_timing(struct mmc *mmc)
priv->mode = mmc->selected_mode;
- return esdhc_change_pinstate(mmc->dev);
+ return esdhc_imx_change_pinstate(mmc->dev);
}
-static int esdhc_set_voltage(struct mmc *mmc)
+static int esdhc_imx_set_voltage(struct mmc *mmc)
{
struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
struct fsl_esdhc *regs = priv->esdhc_regs;
- int ret;
priv->signal_voltage = mmc->signal_voltage;
switch (mmc->signal_voltage) {
@@ -975,18 +974,18 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc)
#endif
}
- if (priv->mode != mmc->selected_mode) {
- ret = esdhc_set_timing(mmc);
+ if (priv->esdhc_imx && priv->mode != mmc->selected_mode) {
+ ret = esdhc_imx_set_timing(mmc);
if (ret) {
- printf("esdhc_set_timing error %d\n", ret);
+ printf("esdhc_imx_set_timing error %d\n", ret);
return ret;
}
}
- if (priv->signal_voltage != mmc->signal_voltage) {
- ret = esdhc_set_voltage(mmc);
+ if (priv->esdhc_imx && priv->signal_voltage != mmc->signal_voltage) {
+ ret = esdhc_imx_set_voltage(mmc);
if (ret) {
- printf("esdhc_set_voltage error %d\n", ret);
+ printf("esdhc_imx_set_voltage error %d\n", ret);
return ret;
}
}
@@ -1267,20 +1266,21 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
- writel(0, >dllctrl);
- if (priv->flags & ESDHC_FLAG_USDHC) {
- if (priv->flags & ESDHC_FLAG_STD_TUNING) {
- u32 val = readl(>tuning_ctrl);
-
- val |= STD_TUNING_EN;
- val &= ~TUNING_START_TAP_MASK;
- val |= priv->tuning_start_tap;
- val &= ~TUNING_STEP_MASK;
- val |= (priv->tuning_step) << TUNING_STEP_SHIFT;
- writel(val, >tuning_ctrl);
+ if (priv->esdhc_imx) {
+ writel(0, >dllctrl);
+ if (priv->flags & ESDHC_FLAG_USDHC) {
+
[U-Boot] [v2, 1/3] mmc: fsl_esdhc: add esdhc_imx flag
The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
initially. The later QoriQ series processors (which were evolutions
of MPC83XX/MPC85XX) and i.MX series processors were using this
driver for their eSDHCs too.
So there are two evolution directions for eSDHC now. For the two
series processors, the eSDHCs are becoming more and more different.
We should have split it into two drivers, like them
(sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel. But it seemed
to be a lot of work now. So let's keep as it is. Be very careful to
change the driver if the changes are not common for all eSDHCs, and
clarify i.MX eSDHC specific things to distingush them with QorIQ
eSDHC.
This patch is to added an esdhc_imx flag for the development of i.MX
eSDHC, to distinguish it with QoriQ eSDHC.
Signed-off-by: Yangbo Lu
---
Changes for v2:
- Converted to use device_is_compatible().
---
drivers/mmc/fsl_esdhc.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 21fa2ab1d4..a647bc7f1c 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -147,6 +147,7 @@ struct fsl_esdhc_priv {
struct gpio_desc cd_gpio;
struct gpio_desc wp_gpio;
#endif
+ bool esdhc_imx;
};
/* Return the XFERTYP flags for a given command and data packet */
@@ -1462,6 +1463,16 @@ static int fsl_esdhc_probe(struct udevice *dev)
priv->caps = data->caps;
}
+ /*
+* This is to specify whether current eSDHC is an i.MX eSDHC,
+* since the i.MX eSDHC has been becoming more and more different
+* with QorIQ eSDHC and initial MPC83XX/MPC85XX.
+*/
+ if (!device_is_compatible(dev, "fsl,esdhc"))
+ priv->esdhc_imx = true;
+ else
+ priv->esdhc_imx = false;
+
val = dev_read_u32_default(dev, "bus-width", -1);
if (val == 8)
priv->bus_width = 8;
--
2.17.1
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[U-Boot] [PATCH 3/3] mmc: fsl_esdhc: clarify i.MX eSDHC specific functions
A previous patch had added SDR104/HS200 support for fsl_esdhc.
However this was only for i.MX eSDHC, and QorIQ eSDHC used
different registers and method.
This patch is to clarify i.MX eSDHC specific functions defined
in that patch, and to use them only for i.MX eSDHC. The QorIQ
eSDHC SDR104/HS200 support will be added in the future.
Fixes: 51313b49f2b8 (mmc: fsl_esdhc: support SDR104 and HS200)
Signed-off-by: Yangbo Lu
---
drivers/mmc/fsl_esdhc.c | 79 +
1 file changed, 41 insertions(+), 38 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 63f922382f..44c040eb8d 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -682,7 +682,7 @@ static void esdhc_clock_control(struct fsl_esdhc_priv
*priv, bool enable)
#endif
#ifdef MMC_SUPPORTS_TUNING
-static int esdhc_change_pinstate(struct udevice *dev)
+static int esdhc_imx_change_pinstate(struct udevice *dev)
{
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
int ret;
@@ -708,7 +708,7 @@ static int esdhc_change_pinstate(struct udevice *dev)
return ret;
}
-static void esdhc_reset_tuning(struct mmc *mmc)
+static void esdhc_imx_reset_tuning(struct mmc *mmc)
{
struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
struct fsl_esdhc *regs = priv->esdhc_regs;
@@ -722,7 +722,7 @@ static void esdhc_reset_tuning(struct mmc *mmc)
}
}
-static void esdhc_set_strobe_dll(struct mmc *mmc)
+static void esdhc_imx_set_strobe_dll(struct mmc *mmc)
{
struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
struct fsl_esdhc *regs = priv->esdhc_regs;
@@ -749,7 +749,7 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
}
}
-static int esdhc_set_timing(struct mmc *mmc)
+static int esdhc_imx_set_timing(struct mmc *mmc)
{
struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
struct fsl_esdhc *regs = priv->esdhc_regs;
@@ -761,13 +761,13 @@ static int esdhc_set_timing(struct mmc *mmc)
switch (mmc->selected_mode) {
case MMC_LEGACY:
case SD_LEGACY:
- esdhc_reset_tuning(mmc);
+ esdhc_imx_reset_tuning(mmc);
writel(mixctrl, >mixctrl);
break;
case MMC_HS_400:
mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
writel(mixctrl, >mixctrl);
- esdhc_set_strobe_dll(mmc);
+ esdhc_imx_set_strobe_dll(mmc);
break;
case MMC_HS:
case MMC_HS_52:
@@ -791,14 +791,13 @@ static int esdhc_set_timing(struct mmc *mmc)
priv->mode = mmc->selected_mode;
- return esdhc_change_pinstate(mmc->dev);
+ return esdhc_imx_change_pinstate(mmc->dev);
}
-static int esdhc_set_voltage(struct mmc *mmc)
+static int esdhc_imx_set_voltage(struct mmc *mmc)
{
struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
struct fsl_esdhc *regs = priv->esdhc_regs;
- int ret;
priv->signal_voltage = mmc->signal_voltage;
switch (mmc->signal_voltage) {
@@ -975,18 +974,18 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc)
#endif
}
- if (priv->mode != mmc->selected_mode) {
- ret = esdhc_set_timing(mmc);
+ if (priv->esdhc_imx && priv->mode != mmc->selected_mode) {
+ ret = esdhc_imx_set_timing(mmc);
if (ret) {
- printf("esdhc_set_timing error %d\n", ret);
+ printf("esdhc_imx_set_timing error %d\n", ret);
return ret;
}
}
- if (priv->signal_voltage != mmc->signal_voltage) {
- ret = esdhc_set_voltage(mmc);
+ if (priv->esdhc_imx && priv->signal_voltage != mmc->signal_voltage) {
+ ret = esdhc_imx_set_voltage(mmc);
if (ret) {
- printf("esdhc_set_voltage error %d\n", ret);
+ printf("esdhc_imx_set_voltage error %d\n", ret);
return ret;
}
}
@@ -1267,20 +1266,21 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
- writel(0, >dllctrl);
- if (priv->flags & ESDHC_FLAG_USDHC) {
- if (priv->flags & ESDHC_FLAG_STD_TUNING) {
- u32 val = readl(>tuning_ctrl);
-
- val |= STD_TUNING_EN;
- val &= ~TUNING_START_TAP_MASK;
- val |= priv->tuning_start_tap;
- val &= ~TUNING_STEP_MASK;
- val |= (priv->tuning_step) << TUNING_STEP_SHIFT;
- writel(val, >tuning_ctrl);
+ if (priv->esdhc_imx) {
+ writel(0, >dllctrl);
+ if (priv->flags & ESDHC_FLAG_USDHC) {
+ if (priv->flags & ESDHC_FLAG_STD_TUNING) {
+
[U-Boot] [PATCH 2/3] mmc: fsl_esdhc: clean up register definition
The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
initially. The later QoriQ series processors (which are evolutions
of MPC83XX/MPC85XX) and i.MX series processors were using this
driver for their eSDHCs too.
So there are two evolution directions for eSDHC now. For the two
series processors, the eSDHCs are becoming more and more different.
We should have split it into two drivers, like them
(sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel. But it seemed
to be a lot of work now. So let's keep as it is. Be very careful to
change the driver if the changes are not common for all eSDHCs, and
clarify i.MX eSDHC specific things to distingush them with QorIQ
eSDHC.
This patch is to clean up register definition. Besides the QorIQ
eSDHC register definition, the i.MX eSDHC specific registers should
be clarified.
Signed-off-by: Yangbo Lu
---
drivers/mmc/fsl_esdhc.c | 66 ++---
include/fsl_esdhc.h | 208 ++--
2 files changed, 149 insertions(+), 125 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 787a13a8a9..63f922382f 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -54,23 +54,23 @@ struct fsl_esdhc {
uintautoc12err; /* Auto CMD error status register */
uinthostcapblt; /* Host controller capabilities register */
uintwml;/* Watermark level register */
- uintmixctrl;/* For USDHC */
+ uintmixctrl;/* For i.MX USDHC */
charreserved1[4]; /* reserved */
uintfevt; /* Force event register */
uintadmaes; /* ADMA error status register */
uintadsaddr;/* ADMA system address register */
charreserved2[4];
- uintdllctrl;
- uintdllstat;
- uintclktunectrlstatus;
+ uintdllctrl;/* For i.MX USDHC */
+ uintdllstat;/* For i.MX USDHC */
+ uintclktunectrlstatus; /* For i.MX USDHC */
charreserved3[4];
- uintstrobe_dllctrl;
- uintstrobe_dllstat;
+ uintstrobe_dllctrl; /* For i.MX USDHC */
+ uintstrobe_dllstat; /* For i.MX USDHC */
charreserved4[72];
- uintvendorspec;
- uintmmcboot;
- uintvendorspec2;
- uinttuning_ctrl;/* on i.MX6/7/8 */
+ uintvendorspec; /* For i.MX USDHC */
+ uintmmcboot;/* For i.MX USDHC */
+ uintvendorspec2;/* For i.MX USDHC */
+ uinttuning_ctrl;/* For i.MX USDHC, on i.MX6/7/8 */
charreserved5[44];
uinthostver;/* Host controller version register */
charreserved6[4]; /* reserved */
@@ -80,11 +80,11 @@ struct fsl_esdhc {
charreserved8[4]; /* reserved */
uinthostcapblt2;/* Host controller capabilities register 2 */
charreserved9[8]; /* reserved */
- uinttcr;/* Tuning control register */
+ uinttbctl; /* Tuning block control register */
charreserved10[28]; /* reserved */
uintsddirctl; /* SD direction control register */
charreserved11[712];/* reserved */
- uintscr;/* eSDHC control register */
+ uintesdhcctl; /* eSDHC control register */
};
struct fsl_esdhc_plat {
@@ -496,7 +496,7 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc,
/* Switch voltage to 1.8V if CMD11 succeeded */
if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
- esdhc_setbits32(>vendorspec, ESDHC_VENDORSPEC_VSELECT);
+ esdhc_setbits32(>vendorspec, VENDORSPEC_VSELECT);
printf("Run CMD11 1.8V switch\n");
/* Sleep for 5 ms - max time for card to switch to 1.8V */
@@ -728,23 +728,23 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
struct fsl_esdhc *regs = priv->esdhc_regs;
u32 val;
- if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
- writel(ESDHC_STROBE_DLL_CTRL_RESET, >strobe_dllctrl);
+ if (priv->clock > STROBE_DLL_CLK_FREQ) {
+ writel(STROBE_DLL_CTRL_RESET, >strobe_dllctrl);
/*
* enable strobe dll ctrl and adjust the delay target
* for the uSDHC loopback read clock
*/
- val = ESDHC_STROBE_DLL_CTRL_ENABLE |
+ val = STROBE_DLL_CTRL_ENABLE |
(priv->strobe_dll_delay_target <<
-ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
+STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
writel(val, >strobe_dllctrl);
/* wait 1us to make sure strobe dll status register stable */
mdelay(1);
val = readl(>strobe_dllstat);
- if (!(val &
[U-Boot] [PATCH 1/3] mmc: fsl_esdhc: add esdhc_imx flag
The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
initially. The later QoriQ series processors (which are evolutions
of MPC83XX/MPC85XX) and i.MX series processors were using this
driver for their eSDHCs too.
So there are two evolution directions for eSDHC now. For the two
series processors, the eSDHCs are becoming more and more different.
We should have split it into two drivers, like them
(sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel. But it seemed
to be a lot of work now. So let's keep as it is. Be very careful to
change the driver if the changes are not common for all eSDHCs, and
clarify i.MX eSDHC specific things to distingush them with QorIQ
eSDHC.
This patch is to added an esdhc_imx flag for the development of i.MX
eSDHC, to distinguish it with QoriQ eSDHC.
Signed-off-by: Yangbo Lu
---
drivers/mmc/fsl_esdhc.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 21fa2ab1d4..787a13a8a9 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -147,6 +147,7 @@ struct fsl_esdhc_priv {
struct gpio_desc cd_gpio;
struct gpio_desc wp_gpio;
#endif
+ bool esdhc_imx;
};
/* Return the XFERTYP flags for a given command and data packet */
@@ -1462,6 +1463,16 @@ static int fsl_esdhc_probe(struct udevice *dev)
priv->caps = data->caps;
}
+ /*
+* This is to specify whether current eSDHC is an i.MX eSDHC,
+* since the i.MX eSDHC has been becoming more and more different
+* with QorIQ eSDHC and initial MPC83XX/MPC85XX.
+*/
+ if (!fdt_node_check_compatible(fdt, node, "fsl,esdhc"))
+ priv->esdhc_imx = true;
+ else
+ priv->esdhc_imx = false;
+
val = dev_read_u32_default(dev, "bus-width", -1);
if (val == 8)
priv->bus_width = 8;
--
2.17.1
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Re: [U-Boot] [PATCH v1] LS2080ardb: MMC: disable esdhc for dspi
Hi Yinbo, > -Original Message- > From: Yinbo Zhu > Sent: Thursday, November 22, 2018 4:17 PM > To: york...@freescale.com; Y.B. LU ; > u-boot@lists.denx.de > Cc: Yinbo Zhu ; Xiaobo Xie ; > Chuanhua Han > Subject: [PATCH v1] LS2080ardb: MMC: disable esdhc for dspi > > esdhc and dspi have Multiplexed pins, if dspi is enabled and esdhc need to be > disabled, This patch is to disable esdhc when rcw config dspi enabled. [Y.b. Lu] The title and commit message is confusing. From the code changes, I think you can rephrase like, armv8: ls2080ardb: enable eSDHC pin mux support CONFIG_FSL_ESDHC_PIN_MUX should be enabled for ls2080ardb whose eSDHC has pin mux with DSPI. This config makes sure esdhc dts node would be fixed with disabled status if DSPI is used, in case of any mmc issue in linux. Also, esdhc should be added in default hwconfig since eSDHC is used in default. > > Signed-off-by: Yinbo Zhu > --- > include/configs/ls2080ardb.h |5 +++-- > 1 files changed, 3 insertions(+), 2 deletions(-) > > diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index > f6aa4ed..d2e80a8 100644 > --- a/include/configs/ls2080ardb.h > +++ b/include/configs/ls2080ardb.h > @@ -331,6 +331,7 @@ unsigned long get_board_sys_clk(void); > /* MMC */ > #ifdef CONFIG_MMC > #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 > +#define CONFIG_FSL_ESDHC_PIN_MUX > #endif > > #define BOOT_TARGET_DEVICES(func) \ > @@ -390,7 +391,7 @@ unsigned long get_board_sys_clk(void); #undef > CONFIG_EXTRA_ENV_SETTINGS #ifdef CONFIG_TFABOOT > #define CONFIG_EXTRA_ENV_SETTINGS\ > - "hwconfig=fsl_ddr:bank_intlv=auto\0"\ > + "hwconfig=fsl_ddr:bank_intlv=auto;esdhc\0" \ > "ramdisk_addr=0x80\0" \ > "ramdisk_size=0x200\0" \ > "fdt_high=0xa000\0" \ > @@ -459,7 +460,7 @@ unsigned long get_board_sys_clk(void); > "bootm $load_addr#$board\0" > #else > #define CONFIG_EXTRA_ENV_SETTINGS\ > - "hwconfig=fsl_ddr:bank_intlv=auto\0"\ > + "hwconfig=fsl_ddr:bank_intlv=auto;esdhc\0" \ > "ramdisk_addr=0x80\0" \ > "ramdisk_size=0x200\0" \ > "fdt_high=0xa000\0" \ > -- > 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 3/8] Enable CONFIG_BLK and CONFIG_DM_MMC to Kconfig
Hi Yinbo, Better to apply this patch as the final one of this patch-set, after these dts node patches. Otherwise, mmc couldn't work at this commit on all boards. Best regards, Yangbo Lu > -Original Message- > From: Yinbo Zhu [mailto:yinbo@nxp.com] > Sent: Friday, August 10, 2018 3:52 PM > To: Yinbo Zhu ; york...@freescale.com; > u-boot@lists.denx.de > Cc: Y.b. Lu ; Xiaobo Xie ; Andy > Tang ; Peng Ma > Subject: [PATCH v5 3/8] Enable CONFIG_BLK and CONFIG_DM_MMC to > Kconfig > > This enables the folowing to Kconfig: > CONFIG_BLK > CONFIG_DM_MMC > > Signed-off-by: Yinbo Zhu > --- > configs/ls1021atwr_nor_SECURE_BOOT_defconfig |2 ++ > configs/ls1021atwr_nor_defconfig |2 ++ > configs/ls1021atwr_nor_lpuart_defconfig|2 ++ > configs/ls1021atwr_qspi_defconfig |2 ++ > .../ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig|2 ++ > configs/ls1021atwr_sdcard_ifc_defconfig|2 ++ > configs/ls1021atwr_sdcard_qspi_defconfig |2 ++ > configs/ls1043aqds_defconfig |2 ++ > configs/ls1043aqds_lpuart_defconfig|2 ++ > configs/ls1043aqds_nand_defconfig |2 ++ > configs/ls1043aqds_nor_ddr3_defconfig |2 ++ > configs/ls1043aqds_qspi_defconfig |2 ++ > configs/ls1043aqds_sdcard_ifc_defconfig|2 ++ > configs/ls1043aqds_sdcard_qspi_defconfig |2 ++ > configs/ls1043ardb_SECURE_BOOT_defconfig |2 ++ > configs/ls1043ardb_defconfig |2 ++ > configs/ls1043ardb_nand_SECURE_BOOT_defconfig |2 ++ > configs/ls1043ardb_nand_defconfig |2 ++ > configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig|2 ++ > configs/ls1043ardb_sdcard_defconfig|2 ++ > configs/ls1046aqds_SECURE_BOOT_defconfig |2 ++ > configs/ls1046aqds_defconfig |2 ++ > configs/ls1046aqds_lpuart_defconfig|2 ++ > configs/ls1046aqds_nand_defconfig |2 ++ > configs/ls1046aqds_qspi_defconfig |2 ++ > configs/ls1046aqds_sdcard_ifc_defconfig|2 ++ > configs/ls1046aqds_sdcard_qspi_defconfig |2 ++ > configs/ls1046ardb_emmc_defconfig |2 ++ > configs/ls1046ardb_qspi_SECURE_BOOT_defconfig |2 ++ > configs/ls1046ardb_qspi_defconfig |2 ++ > configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig|2 ++ > configs/ls1046ardb_sdcard_defconfig|2 ++ > configs/ls1088aqds_defconfig |2 ++ > configs/ls1088aqds_qspi_SECURE_BOOT_defconfig |2 ++ > configs/ls1088aqds_qspi_defconfig |2 ++ > configs/ls1088aqds_sdcard_ifc_defconfig|2 ++ > configs/ls1088aqds_sdcard_qspi_defconfig |2 ++ > configs/ls1088ardb_qspi_SECURE_BOOT_defconfig |2 ++ > configs/ls1088ardb_qspi_defconfig |2 ++ > .../ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig |2 ++ > configs/ls1088ardb_sdcard_qspi_defconfig |2 ++ > configs/ls2080a_emu_defconfig |2 ++ > configs/ls2080a_simu_defconfig |2 ++ > configs/ls2080aqds_SECURE_BOOT_defconfig |2 ++ > configs/ls2080aqds_defconfig |2 ++ > configs/ls2080aqds_nand_defconfig |2 ++ > configs/ls2080aqds_qspi_defconfig |2 ++ > configs/ls2080aqds_sdcard_defconfig|2 ++ > configs/ls2080ardb_SECURE_BOOT_defconfig |2 ++ > configs/ls2080ardb_defconfig |2 ++ > configs/ls2080ardb_nand_defconfig |2 ++ > configs/ls2088ardb_qspi_SECURE_BOOT_defconfig |2 ++ > configs/ls2088ardb_qspi_defconfig |2 ++ > 53 files changed, 106 insertions(+), 0 deletions(-) > > diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig > b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig > index 17a202d..4d85983 100644 > --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig > +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig > @@ -48,3 +48,5 @@ CONFIG_VIDEO=y > # CONFIG_VIDEO_SW_CURSOR is not set > CONFIG_RSA=y > CONFIG_SPL_RSA=y > +CONFIG_BLK=y > +CONFIG_DM_MMC=y > diff --git a/configs/ls1021atwr_nor_defconfig > b/configs/ls1021atwr_nor_defconfig > index a18426e..f4f7998 100644 > --- a/configs/ls1021atwr_nor_defconfig > +++ b/configs/ls1021atwr_nor_defconfig > @@ -48,3 +48,5 @@ CONFIG_USB_STORAGE=y > CONFIG_VIDEO_FSL_DCU_FB=y >
Re: [U-Boot] [PATCH v5 1/8] dm: mmc: use block layer in mmc driver
Hi Yinbo,
> -Original Message-
> From: Yinbo Zhu [mailto:yinbo@nxp.com]
> Sent: Friday, August 10, 2018 3:52 PM
> To: Yinbo Zhu ; york...@freescale.com;
> u-boot@lists.denx.de
> Cc: Y.b. Lu ; Xiaobo Xie ; Andy
> Tang ; Peng Ma
> Subject: [PATCH v5 1/8] dm: mmc: use block layer in mmc driver
>
> At present the MMC subsystem maintains its own list of MMC devices. This
> cannot work with driver model when CONFIG_BLK is enabled, use blk_dread to
> replace previous mmc read interface, use mmc_get_blk_desc to get the mmc
> device property
>
> Signed-off-by: Yinbo Zhu
> ---
> Change in v5:
> use block layer in mmc driver
>
> arch/arm/cpu/armv8/fsl-layerscape/ppa.c |5 ++---
> drivers/mmc/mmc_legacy.c| 10 +-
> drivers/net/fm/fm.c |2 +-
> drivers/qe/qe.c |2 +-
> 4 files changed, 9 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
> b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
> index a31c4d9..95875d3 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
> @@ -99,7 +99,7 @@ int ppa_init(void)
> cnt = DIV_ROUND_UP(fdt_header_len, 512);
> debug("%s: MMC read PPA FIT header: dev # %u, block # %u,
> count %u\n",
> __func__, dev, blk, cnt);
> - ret = mmc->block_dev.block_read(>block_dev, blk, cnt, fitp);
> + ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, fitp);
> if (ret != cnt) {
> free(fitp);
> printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",
> @@
> -149,8 +149,7 @@ int ppa_init(void)
> cnt = DIV_ROUND_UP(fw_length, 512);
> debug("%s: MMC read PPA FIT image: dev # %u, block # %u, count %u\n",
> __func__, dev, blk, cnt);
> - ret = mmc->block_dev.block_read(>block_dev,
> - blk, cnt, ppa_fit_addr);
> + ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, ppa_fit_addr);
> if (ret != cnt) {
> free(ppa_fit_addr);
> printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",
> diff
> --git a/drivers/mmc/mmc_legacy.c b/drivers/mmc/mmc_legacy.c index
> 66a7cda..29d94e9 100644
> --- a/drivers/mmc/mmc_legacy.c
> +++ b/drivers/mmc/mmc_legacy.c
[Y.b. Lu] Please don't apply this change to mmc_legacy.c which is for operation
where CONFIG_BLK is never enabled.
> @@ -42,7 +42,7 @@ struct mmc *find_mmc_device(int dev_num)
> list_for_each(entry, _devices) {
> m = list_entry(entry, struct mmc, link);
>
> - if (m->block_dev.devnum == dev_num)
> + if (mmc_get_blk_desc(m)->devnum == dev_num)
> return m;
> }
>
> @@ -60,7 +60,7 @@ int mmc_get_next_devnum(void)
>
> struct blk_desc *mmc_get_blk_desc(struct mmc *mmc) {
> - return >block_dev;
> + return mmc_get_blk_desc(mmc);
> }
>
> int get_mmc_num(void)
> @@ -113,7 +113,7 @@ void print_mmc_devices(char separator)
> else
> mmc_type = NULL;
>
> - printf("%s: %d", m->cfg->name, m->block_dev.devnum);
> + printf("%s: %d", m->cfg->name, mmc_get_blk_desc(m)->devnum);
> if (mmc_type)
> printf(" (%s)", mmc_type);
>
> @@ -218,7 +218,7 @@ static int mmc_select_hwpartp(struct blk_desc *desc,
> int hwpart)
> if (!mmc)
> return -ENODEV;
>
> - if (mmc->block_dev.hwpart == hwpart)
> + if (mmc_get_blk_desc(mmc)->hwpart == hwpart)
> return 0;
>
> if (mmc->part_config == MMCPART_NOAVAILABLE) @@ -242,7 +242,7
> @@ static int mmc_get_dev(int dev, struct blk_desc **descp)
> if (ret)
> return ret;
>
> - *descp = >block_dev;
> + *descp = mmc_get_blk_desc(mmc);
>
> return 0;
> }
> diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 3327073..c5cf188
> 100644
> --- a/drivers/net/fm/fm.c
> +++ b/drivers/net/fm/fm.c
> @@ -402,7 +402,7 @@ int fm_init_common(int index, struct ccsr_fman *reg)
> printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
> dev, blk, cnt);
> mmc_init(mmc);
> - (void)mmc->block_dev.block_read(>block_dev, blk, cnt,
> + (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
> addr);
> }
> #elif defined(CO
Re: [U-Boot] [PATCH v4 1/8] armv8: enable BLK code configuration
Hi Yinbo,
> -Original Message-
> From: York Sun
> Sent: Wednesday, August 8, 2018 6:09 AM
> To: Yinbo Zhu ; york...@freescale.com;
> u-boot@lists.denx.de
> Cc: Y.b. Lu ; Xiaobo Xie ; Andy
> Tang ; Peng Ma
> Subject: Re: [PATCH v4 1/8] armv8: enable BLK code configuration
>
> On 08/06/2018 12:15 AM, Yinbo Zhu wrote:
> > This patch is to enable BLK code configuration for SD boot.
> >
> > Signed-off-by: Yinbo Zhu
> > ---
> > Change in v4:
> > keep the same revision v4 for the entire set.
> >
> > include/mmc.h |2 +-
> > 1 files changed, 1 insertions(+), 1 deletions(-)
> >
> > diff --git a/include/mmc.h b/include/mmc.h index 534c317..66e69b7
> > 100644
> > --- a/include/mmc.h
> > +++ b/include/mmc.h
> > @@ -604,7 +604,7 @@ struct mmc {
> > u64 enh_user_start;
> > u64 enh_user_size;
> > #endif
> > -#if !CONFIG_IS_ENABLED(BLK)
> > +#if CONFIG_IS_ENABLED(BLK)
> > struct blk_desc block_dev;
> > #endif
> > char op_cond_pending; /* 1 if we are waiting on an op_cond command
> */
> >
>
> You ignored my comment on your v3 patch. See it here
> http://patchwork.ozlabs.org/patch/945479/
[Y.b. Lu] MMC block reading should use blk_dread() now. The old function
mmc->block_dev.block_read() would cause compile issue when CONFIG_BLK is
enabled.
Please generate patches to fix this in any driver which still used the old
block read function.
You can refer to below patches.
bcfde7f mmc: use block layer in mmc command
c40fdca dm: mmc: Move the device list into a separate file
>
> York
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Re: [U-Boot] dm: mmc: fsl_esdhc: Drop mmc_init() call from fsl_esdhc_init()
Hi Simon, Sorry for my late response. Please see my comments inline. Thanks a lot. > -Original Message- > From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass > Sent: 2017年11月25日 6:36 > To: Y.b. Lu <yangbo...@nxp.com> > Cc: u-boot@lists.denx.de; Jaehoon Chung <jh80.ch...@samsung.com>; Yinbo > Zhu <yinbo@nxp.com>; Xiaobo Xie <xiaobo@nxp.com> > Subject: Re: dm: mmc: fsl_esdhc: Drop mmc_init() call from fsl_esdhc_init() > > Hi, > > On 20 November 2017 at 23:11, Y.b. Lu <yangbo...@nxp.com> wrote: > > Hi Simon, > > > > > > > > I found your below patch just dropping mmc_create() for probe > > procedure of DM. > > > > Actually the description seemed to be not the things this patch did. > > > > > > > > dm: mmc: fsl_esdhc: Drop mmc_init() call from fsl_esdhc_init() > > > > > > > > Do you have any suggestion to fix it? > > > > mmc_create() will allocate mmc structure and the DM in fsl_esdhc also > > allocate mmc structure in fsl_esdhc_plat structure. > > > > Do we need to rework the mmc_create(), or move rest initialization of > > mmc_create() in to fsl_esdhc_probe() ? > > But mmc_create() is only used in legacy code, not with driver model. > > Why do you want to call it here? Does your board not use CONFIG_DM_MMC? [Y.b. Lu] As I understand, mmc_create() is used for mmc host driver in which CONFIG_BLK is not implemented. Currently ls1012ardb board is using DM but CONFIG_BLK isn’t implemented. So now it couldn’t be added into mmc device list in initialization, and mmc command warns no MMC device. > > > > > > > > > Thanks a lot. > > Regards, > Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [v3] armv8: ls1012a: enable/disable eSDHC1 through hwconfig for new RDB
Sent out v4 patch-set. Please help to review.
Thanks a lot :)
> -Original Message-
> From: York Sun
> Sent: 2017年12月8日 1:34
> To: Y.b. Lu <yangbo...@nxp.com>; u-boot@lists.denx.de
> Subject: Re: [v3] armv8: ls1012a: enable/disable eSDHC1 through hwconfig for
> new RDB
>
> On 12/07/2017 12:10 AM, Y.b. Lu wrote:
>
>
>
> >
> >>
> >>> printf("Error reading i2c boot information!\n");
> >>> - return 0; /* Don't want to hang() on this error */
> >>> + return 0;
> >>
> >> What does I2C failure mean here? Returning 0 will cause the code keep
> >> going in fdt_fixup_esdhc().
> >
> > [Y.b. Lu] I don’t know the possibility of I2C failure. If the failure
> > happens, just
> print error message, leave 'status' as it is, and return 0 because the other
> fix-ups in fdt_fixup_esdhc() are still needed like clock-frequency.
>
> You can move on if it makes sense to do so.
>
> >
> >>
> >>> + }
> >>> +
> >>> + if ((in1 & (~__SW_REV_MASK)) <= __SW_REV_D) {
> >>> + if (hwconfig("esdhc1"))
> >>
> >> Please double check. I remember in the past if hwconfig is not
> >> enabled, any check returns true.
> >
> > [Y.b. Lu] You're right. It's -ENOSYS. But what should I do here ?
>
> It depends on which one is safe. If you want to presume esdhc1 is available,
> you can keep current code. If you'd rather not to enable it, add a check of
> #ifdef.
>
> >
> >>
> >>> + sdhc2_en = true;
> >>> + } else {
> >>> + /*
> >>> + * The I2C IO-expander for mux select is used to control
> >>> + * the muxing of various onboard interfaces.
> >>> + *
> >>> + * IO1[3:2] indicates SDHC2 interface demultiplexer
> >>> + * select lines.
> >>> + * 00 - SDIO wifi
> >>> + * 01 - GPIO (to Arduino)
> >>> + * 10 - eMMC Memory
> >>> + * 11 - SPI
> >>> + */
> >>> + if (i2c_read(I2C_MUX_IO1_ADDR, 0, 1, , 1) < 0) {
> >>> + printf("Error reading i2c boot information!\n");
> >>> + return 0; /* Don't want to hang() on this error */
> >>> + }
> >>> +
> >>> + mux_sdhc2 = (io & 0x0c) >> 2;
> >>> + /* Enable SDHC2 only when use SDIO wifi and eMMC */
> >>> + if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
> >>> + sdhc2_en = true;
> >>> }
> >>>
> >>> - mux_sdhc2 = (io & 0x0c) >> 2;
> >>> - /* Enable SDHC2 only when use SDIO wifi and eMMC */
> >>> - if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
> >>> + if (sdhc2_en)
> >>> do_fixup_by_path(blob, esdhc1_path, "status", "okay",
> >>>sizeof("okay"), 1);
> >>> else
> >>> do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
> >>> sizeof("disabled"), 1);
> >>> +
> >>> return 0;
> >>> }
> >>>
> >>> diff --git a/include/configs/ls1012ardb.h
> >>> b/include/configs/ls1012ardb.h index 794117062f..d5384e6027 100644
> >>> --- a/include/configs/ls1012ardb.h
> >>> +++ b/include/configs/ls1012ardb.h
> >>> @@ -32,6 +32,10 @@
> >>> #define __SW_REV_MASK0x07
> >>> #define __SW_REV_A 0xF8
> >>> #define __SW_REV_B 0xF0
> >>> +#define __SW_REV_C 0xE8
> >>> +#define __SW_REV_C1 0xE0
> >>> +#define __SW_REV_C2 0xD8
> >>> +#define __SW_REV_D 0xD0
> >>
> >> I don't have strong opinion about these macros. I would not use
> >> underscore myself. I guess I missed them at the first place.
> >
> > [Y.b. Lu] It's confusing why define macro like this...
> > And the __SW_BOOT_EMU is wrong, it should be 0x02, not 0x10.
>
> Add another patch before this one to clean them up, please.
>
> York
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Re: [U-Boot] [v3] armv8: ls1012a: enable/disable eSDHC1 through hwconfig for new RDB
Hi York,
> -Original Message-
> From: York Sun
> Sent: 2017年12月7日 3:08
> To: Y.b. Lu <yangbo...@nxp.com>; u-boot@lists.denx.de
> Subject: Re: [v3] armv8: ls1012a: enable/disable eSDHC1 through hwconfig for
> new RDB
>
> On 12/06/2017 02:19 AM, Yangbo Lu wrote:
> > For LS1012ARDB RevD and later versions, the I2C reading for DIP switch
> > setting had been no longer reliable since the board was reworked. This
> > patch is to add hwconfig support to enable/disable
>
> I think this message is not accurate. How about saying "I2C reading for DIP
> switch setting is not reliable for LS1012ARDB rev D and later revisions."?
>
[Y.b. Lu] Thanks. This is better.
> > eSDHC1 manually for these boards. Also let kernel decide status of
> > esdhc0.
>
> I see you dropped fixing up esdhc0. What do you mean "let kernel decide"?
> How?
[Y.b. Lu] I mean unless to avoid some issue, we don’t need to do any fix-up for
'status'.
Let me rephrase it as "Also drop 'status' fix-up for esdhc0 and leave it as it
is. It shouldn’t be always fixed up with 'okay'. ".
>
> >
> > Signed-off-by: Yangbo Lu <yangbo...@nxp.com>
> > ---
> > Changes for v2:
> > - Just used hwconfig() instead of getenv() and hwconfig_f().
> > Changes for v3:
> > - only applied hwconfig support for RevD and later versions.
> > ---
> > board/freescale/ls1012ardb/ls1012ardb.c | 51
> +
> > include/configs/ls1012ardb.h| 4 +++
> > 2 files changed, 36 insertions(+), 19 deletions(-)
> >
> > diff --git a/board/freescale/ls1012ardb/ls1012ardb.c
> > b/board/freescale/ls1012ardb/ls1012ardb.c
> > index c6c1c71202..b73c7d6639 100644
> > --- a/board/freescale/ls1012ardb/ls1012ardb.c
> > +++ b/board/freescale/ls1012ardb/ls1012ardb.c
> > @@ -132,39 +132,52 @@ int board_init(void)
> >
> > int esdhc_status_fixup(void *blob, const char *compat) {
> > - char esdhc0_path[] = "/soc/esdhc@156";
> > char esdhc1_path[] = "/soc/esdhc@158";
> > + u8 in1;
>
> I think you can reuse "io". Not a big deal though.
[Y.b. Lu] Ok. Will do that.
>
> > u8 io = 0;
> > u8 mux_sdhc2;
> > -
> > - do_fixup_by_path(blob, esdhc0_path, "status", "okay",
> > -sizeof("okay"), 1);
> > + bool sdhc2_en = false;
> >
> > i2c_set_bus_num(0);
> >
> > - /*
> > -* The I2C IO-expander for mux select is used to control the muxing
> > -* of various onboard interfaces.
> > -*
> > -* IO1[3:2] indicates SDHC2 interface demultiplexer select lines.
> > -* 00 - SDIO wifi
> > -* 01 - GPIO (to Arduino)
> > -* 10 - eMMC Memory
> > -* 11 - SPI
> > -*/
> > - if (i2c_read(I2C_MUX_IO1_ADDR, 0, 1, , 1) < 0) {
> > + if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, , 1) < 0) {
>
> It would be helpful to use a named macro instead of "1" here as the register
> address. It is not obvious that you are reading a revision number. You can
> also
> put a comment.
[Y.b. Lu] Let me put a comment here for this patch. I think it's proper to
replace all the numbers with macro in this file in another patch.
>
> You said I2C reading the DIP is not reliable. Is this reading reliable?
[Y.b. Lu] This is a question... Although I had verified this patch on RevE(the
value read is correct), let me confirm with Kinjalk before sending new version
patch.
>
> > printf("Error reading i2c boot information!\n");
> > - return 0; /* Don't want to hang() on this error */
> > + return 0;
>
> What does I2C failure mean here? Returning 0 will cause the code keep going in
> fdt_fixup_esdhc().
[Y.b. Lu] I don’t know the possibility of I2C failure. If the failure happens,
just print error message, leave 'status' as it is, and return 0 because the
other fix-ups in fdt_fixup_esdhc() are still needed like clock-frequency.
>
> > + }
> > +
> > + if ((in1 & (~__SW_REV_MASK)) <= __SW_REV_D) {
> > + if (hwconfig("esdhc1"))
>
> Please double check. I remember in the past if hwconfig is not enabled, any
> check returns true.
[Y.b. Lu] You're right. It's -ENOSYS. But what should I do here ?
>
> > + sdhc2_en = true;
> > + } else {
> > + /*
> > +* The I2C IO-expander for mux select is used to control
> > +* the muxing of various onboard interfaces.
> > +*
>
Re: [U-Boot] [v2] armv8: ls1012a: enable/disable eSDHC1 through hwconfig for RDB
Hi York, Thank you for your suggestion. I sent out v3 patch which is backward-compatible. Please check. Thanks a lot. Best regards, Yangbo Lu > -Original Message- > From: York Sun > Sent: 2017年12月1日 1:59 > To: Y.b. Lu <yangbo...@nxp.com>; u-boot@lists.denx.de > Cc: Xiaobo Xie <xiaobo@nxp.com> > Subject: Re: [v2] armv8: ls1012a: enable/disable eSDHC1 through hwconfig for > RDB > > On 11/29/2017 08:44 PM, Y.b. Lu wrote: > > Hi York, > > > > I copied hardware team Kinjalk's explain here. > > > > "Enabling SDHC2 on ‘00’ is not correct on revision D and later boards as the > sd wifi is not on there on these revs. > > The IO expander was designed to override the dip switch values. So, the DIP > switch values are driven through low strength drivers. The I2C reads of DIP > switch settings may not be correct and reliable as the noise margin is very > low. > If the IO expander is driving CFG than the situation is different and reads > will > always be reliable." > > > > It seemed ls1012ardb RevD reworked the SDHC2 circuit. The SDIO wifi device > was removed and I2C reading of DIP switch setting was not reliable. > > This changes is causing many kernel error messages on RevD boards. > > "mmc1: Controller never released inhibit bit(s)." > > It's safe to disable SDHC2 in default and enable it manually when hardware > configuration(DIP switch) is correct for SDHC2 since software doesn’t have > way to check. > > > > Do you think this should be fixed by hardware? If so, I will try to suggest > > that. > > Yangbo, > > If the hardware can be fixed to operate the same way, please push for a fix. > If > rev D board (and later) removes the feature to read DIP switches, and you can > make the code backward-compatible, then we can accept this change. > > Your change is to use hwconfig to determine if eSDHC1 is available. This will > cause all previous boards losing the ability to automatically select eSDHC1. > Is > that acceptable to existing users, and clearly documented? > > York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [v2] armv8: ls1012a: enable/disable eSDHC1 through hwconfig for RDB
Hi York, I copied hardware team Kinjalk's explain here. "Enabling SDHC2 on ‘00’ is not correct on revision D and later boards as the sd wifi is not on there on these revs. The IO expander was designed to override the dip switch values. So, the DIP switch values are driven through low strength drivers. The I2C reads of DIP switch settings may not be correct and reliable as the noise margin is very low. If the IO expander is driving CFG than the situation is different and reads will always be reliable." It seemed ls1012ardb RevD reworked the SDHC2 circuit. The SDIO wifi device was removed and I2C reading of DIP switch setting was not reliable. This changes is causing many kernel error messages on RevD boards. "mmc1: Controller never released inhibit bit(s)." It's safe to disable SDHC2 in default and enable it manually when hardware configuration(DIP switch) is correct for SDHC2 since software doesn’t have way to check. Do you think this should be fixed by hardware? If so, I will try to suggest that. Thanks a lot. Best regards, Yangbo Lu > -Original Message- > From: York Sun > Sent: 2017年11月30日 3:45 > To: Y.b. Lu <yangbo...@nxp.com>; u-boot@lists.denx.de > Subject: Re: [v2] armv8: ls1012a: enable/disable eSDHC1 through hwconfig for > RDB > > On 11/27/2017 12:58 AM, Yangbo Lu wrote: > > For LS1012ARDB RevD and later versions, the I2C reading for DIP switch > > setting had been no longer reliable since the board was reworked. This > > patch is to add hwconfig support to enable/disable > > eSDHC1 manually. > > What do you mean "no longer reliable"? This should be addressed by fixing the > board. > > York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] armv8: ls1088ardb: support force SDHC mode by hwconfig
Hi York,
See my comments inline.
Thanks a lot.
Best regards,
Yangbo Lu
> -Original Message-
> From: York Sun
> Sent: 2017年11月30日 3:43
> To: Y.b. Lu <yangbo...@nxp.com>; u-boot@lists.denx.de
> Subject: Re: [PATCH] armv8: ls1088ardb: support force SDHC mode by
> hwconfig
>
> On 11/26/2017 11:59 PM, Yangbo Lu wrote:
> > The BRDCFG5[SPISDHC] register field of Qixis device is used to control
> > SPI and SDHC signal routing.
> >
> > 10 = Force SDHC Mode
> > - SPI_CS[0] is routed to CPLD for SDHC_VS use.
> > - SPI_CS[1] is unused.
> > - SPI_CS[2:3] are routed to the TDMRiser slot.
> >
> > 11 = Force eMMC Mode
> > - SPI_CS[0:3] are routed to the eMMC card.
> >
> > 0X = Auto Mode
> > - If SDHC_CS_B=0 (SDHC card installed): Use SDHC mode
> > described above.
> > - Else SDHC_CS_B=1 (no SDHC card installed): Use eMMC
> > mode described above.
> >
> > In default the hardware uses auto mode, but sometimes we need to use
> > force SDHC mode to support SD card hotplug, or SD sleep waking up in
> > kernel. This patch is to support force SDHC mode by hwconfig.
>
>
> Help me understand this. When you eject the SD card, does the CPLD logic
> detect the SDHC_CS_B and change the signal routing? Are you trying to fix the
> signal routing by forcing the mode?
>
[Y.b. Lu] In default auto mode, signals would be switched automatically.
(Actually I found signals routing issue, I will explain it later.)
When there is a SD card hotplug, it means there also is a eMMC hotplug.
For kernel, there is no way to detect eMMC hotplug which is a non-removable
device. So kernel couldn’t handle SD/eMMC automatic switching case.
With the auto mode, we couldn’t support SD hotplug and SD waking up for sleep
such cases.
So I added this hwconfig to use force SD mode.
Let's see the signals routing issue I mentioned above.
Actually I found SDHC_CD signal and SDHC_WP signal were mixed up in auto mode.
The SDHC_CD signal of chip was routed to SDHC_WP signal of card slot in default
auto mode. The SDHC_WP couldn’t work as expect either.
In force SD mode, the SDHC_CD worked well. I will add you into the email about
this issue.
Anyway, hwconfig for force SD mode enabling is needed.
Thanks a lot.
> >
> > Signed-off-by: Yangbo Lu <yangbo...@nxp.com>
> > ---
> > board/freescale/ls1088a/ls1088a.c | 18 ++
> > board/freescale/ls1088a/ls1088a_qixis.h | 6 ++
> > include/configs/ls1088ardb.h| 2 ++
> > 3 files changed, 26 insertions(+)
> >
> > diff --git a/board/freescale/ls1088a/ls1088a.c
> > b/board/freescale/ls1088a/ls1088a.c
> > index 96d9ae7f1d..60f40edb5a 100644
> > --- a/board/freescale/ls1088a/ls1088a.c
> > +++ b/board/freescale/ls1088a/ls1088a.c
> > @@ -18,6 +18,7 @@
> > #include
> > #include #include
> > +#include
> >
> > #include "../common/qixis.h"
> > #include "ls1088a_qixis.h"
> > @@ -296,6 +297,23 @@ void board_retimer_init(void)
> > select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
> > }
> >
> > +#ifdef CONFIG_MISC_INIT_R
> > +int misc_init_r(void)
> > +{
> > +#ifdef CONFIG_TARGET_LS1088ARDB
> > + u8 brdcfg5;
> > +
> > + if (hwconfig("esdhc-force-sd")) {
> > + brdcfg5 = QIXIS_READ(brdcfg[5]);
> > + brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
> > + brdcfg5 |= BRDCFG5_FORCE_SD;
> > + QIXIS_WRITE(brdcfg[5], brdcfg5);
> > + }
> > +#endif
>
> Would it be appropriate to check if eMMC is used before taking the forced
> value?
>
> York
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Re: [U-Boot] dm: mmc: fsl_esdhc: Drop mmc_init() call from fsl_esdhc_init()
Any suggestion? Thanks. From: Y.b. Lu Sent: 2017年11月21日 14:11 To: u-boot@lists.denx.de Cc: 'Simon Glass' <s...@chromium.org>; Jaehoon Chung <jh80.ch...@samsung.com>; Yinbo Zhu <yinbo@nxp.com>; Xiaobo Xie <xiaobo@nxp.com> Subject: dm: mmc: fsl_esdhc: Drop mmc_init() call from fsl_esdhc_init() Hi Simon, I found your below patch just dropping mmc_create() for probe procedure of DM. Actually the description seemed to be not the things this patch did. dm: mmc: fsl_esdhc: Drop mmc_init() call from fsl_esdhc_init() Do you have any suggestion to fix it? mmc_create() will allocate mmc structure and the DM in fsl_esdhc also allocate mmc structure in fsl_esdhc_plat structure. Do we need to rework the mmc_create(), or move rest initialization of mmc_create() in to fsl_esdhc_probe() ? Thanks a lot. Best regards, Yangbo Lu ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] dm: mmc: fsl_esdhc: Drop mmc_init() call from fsl_esdhc_init()
Hi Simon, I found your below patch just dropping mmc_create() for probe procedure of DM. Actually the description seemed to be not the things this patch did. dm: mmc: fsl_esdhc: Drop mmc_init() call from fsl_esdhc_init() Do you have any suggestion to fix it? mmc_create() will allocate mmc structure and the DM in fsl_esdhc also allocate mmc structure in fsl_esdhc_plat structure. Do we need to rework the mmc_create(), or move rest initialization of mmc_create() in to fsl_esdhc_probe() ? Thanks a lot. Best regards, Yangbo Lu ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] armv8: ls1012a: enable/disable eSDHC1 through hwconfig for RDB
+ York
-Original Message-
From: Yangbo Lu [mailto:yangbo...@nxp.com]
Sent: 2017年11月16日 10:28
To: u-boot@lists.denx.de; Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>;
Sumit Garg <sumit.g...@nxp.com>
Cc: Y.b. Lu <yangbo...@nxp.com>
Subject: [PATCH] armv8: ls1012a: enable/disable eSDHC1 through hwconfig for RDB
For LS1012ARDB RevD and later versions, the I2C reading for DIP switch setting
had been no longer reliable since the board was reworked. This patch is to add
hwconfig support to enable/disable
eSDHC1 manually.
Signed-off-by: Yangbo Lu <yangbo...@nxp.com>
---
board/freescale/ls1012ardb/ls1012ardb.c | 29 -
1 file changed, 4 insertions(+), 25 deletions(-)
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c
b/board/freescale/ls1012ardb/ls1012ardb.c
index 41283dba42..19f0c3f941 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -128,39 +128,18 @@ int board_init(void)
int esdhc_status_fixup(void *blob, const char *compat) {
- char esdhc0_path[] = "/soc/esdhc@156";
char esdhc1_path[] = "/soc/esdhc@158";
- u8 io = 0;
- u8 mux_sdhc2;
+ char *env_hwconfig;
- do_fixup_by_path(blob, esdhc0_path, "status", "okay",
-sizeof("okay"), 1);
+ env_hwconfig = getenv("hwconfig");
- i2c_set_bus_num(0);
-
- /*
-* The I2C IO-expander for mux select is used to control the muxing
-* of various onboard interfaces.
-*
-* IO1[3:2] indicates SDHC2 interface demultiplexer select lines.
-* 00 - SDIO wifi
-* 01 - GPIO (to Arduino)
-* 10 - eMMC Memory
-* 11 - SPI
-*/
- if (i2c_read(I2C_MUX_IO1_ADDR, 0, 1, , 1) < 0) {
- printf("Error reading i2c boot information!\n");
- return 0; /* Don't want to hang() on this error */
- }
-
- mux_sdhc2 = (io & 0x0c) >> 2;
- /* Enable SDHC2 only when use SDIO wifi and eMMC */
- if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
+ if (hwconfig_f("esdhc1", env_hwconfig))
do_fixup_by_path(blob, esdhc1_path, "status", "okay",
sizeof("okay"), 1);
else
do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
sizeof("disabled"), 1);
+
return 0;
}
--
2.14.1
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Re: [U-Boot] [PATCH] armv8: ls1043ardb: disable PPA loading during SPL stage for SD boot
Hi York, Yes. We got below crash on ls1046ardb if we write ppa to SD card. => cpld reset sd U-Boot SPL 2017.07-g25cd705 (Sep 15 2017 - 03:27:02) Initializing DDRusing SPD WARNING: Calling __hwconfig without a buffer and before environment is ready WARNING: Calling __hwconfig without a buffer and before environment is ready WARNING: Calling __hwconfig without a buffer and before environment is ready WARNING: Calling __hwconfig without a buffer and before environment is ready PPA Firmware: Version LSDK-17.09-TC3 "Synchronous Abort" handler, esr 0x9640 ELR: 1000a270 LR: 1000277c x0 : ec000cb28a045000 x1 : 8f080318 x2 : bcd0 x3 : x4 : 179a x5 : bcd0 x6 : aa1e03ec100d x7 : 0094 x8 : 1001f770 x9 : 0080 x10: 1001f5fd x11: x12: x13: x14: 1001f80c x15: 8f080240 x16: 1001f644 x17: 0001 x18: 1001fa20 x19: ec000cb28a045000 x20: 8f080240 x21: 8f00 x22: 01570604 x23: 01570600 x24: 0157060c x25: 01570608 x26: 100128e4 x27: bcd0 x28: fff7a990 x29: 1001f8b0 Resetting CPU ... resetting ... Thanks a lot. Best regards, Yangbo Lu -Original Message- From: York Sun Sent: 2017年9月18日 22:58 To: Y.b. Lu <yangbo...@nxp.com>; u-boot@lists.denx.de Subject: Re: [PATCH] armv8: ls1043ardb: disable PPA loading during SPL stage for SD boot On 09/18/2017 12:16 AM, Yangbo Lu wrote: > PPA loading during SPL stage is not required for nornal SD boot > scenario. > Once PPA is loaded during SPL boot, RAM version U-Boot won't load it again. It is used for falcon boot. Does it hurt anything? York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] armv8: ls1043a: disable IFC in SPL only when QSPI is used
Hi York, Thanks for your comments. The v2 patch had been sent out. Best regards, Yangbo Lu -Original Message- From: York Sun Sent: 2017年9月15日 5:18 To: Y.b. Lu <yangbo...@nxp.com>; u-boot@lists.denx.de Subject: Re: [PATCH] armv8: ls1043a: disable IFC in SPL only when QSPI is used On 09/12/2017 11:03 PM, Yangbo Lu wrote: > SD boot couldn't work with ls1043aqds_sdcard_ifc_defconfig since IFC > in SPL is disabled. This patch is to fix this issue. You subject matches the change. But the commit message is confusing. Please rephrase it. York > > Signed-off-by: Yangbo Lu <yangbo...@nxp.com> > --- > include/configs/ls1043a_common.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/configs/ls1043a_common.h > b/include/configs/ls1043a_common.h > index 002830c27e..1f9efffa56 100644 > --- a/include/configs/ls1043a_common.h > +++ b/include/configs/ls1043a_common.h > @@ -22,7 +22,7 @@ > #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT)) > #define SPL_NO_MMC > #endif > -#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT)) > +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI)) > #define SPL_NO_IFC > #endif > > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] blk: Remove various places that do flush cache after read
> -Original Message- > From: Bin Meng [mailto:bmeng...@gmail.com] > Sent: Wednesday, August 23, 2017 1:29 PM > To: Y.b. Lu > Cc: Qiang Zhao; York Sun; Grygorii Strashko; Michal Simek; Angelo > Dureghello; Kever Yang; Jaehoon Chung; Albert Aribaud; Marcel Ziswiler; > Markus Niebel; Z.q. Hou; Sumit Garg; Joe Hershberger; Stefan Roese; > Wenbin Song; Simon Glass; Max Krummenacher; Masahiro Yamada; Tomas Melin; > Q.y. Gong; Tom Rini; U-Boot Mailing List > Subject: Re: [PATCH] blk: Remove various places that do flush cache after > read > > Hi Yangbo, > > On Wed, Aug 23, 2017 at 11:29 AM, Y.b. Lu <yangbo...@nxp.com> wrote: > > cmd/mmc.c > > > > Maybe SD controller on some vendor platforms doesn't support SNOOP. > > flush_cache() is required to sync between DDR and cache. > > Should be careful to remove this. > > > > Please do not top-posting. > > What you mentioned if snoop is not supported, flush_cache() is required, > is true, however that's not the issue I am trying to fix here. The > flush_cache() here after a DMA read will cause issues because stale data > in the cache will overwrite the correct data in the RAM that is DMAed by > hardware (in this case, MMC controller). > [Lu Yangbo-B47093] Sorry for my misunderstanding. It looks ok to me now. flush_cache is indeed redundant after DMA reading. > Regards, > Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
