[PATCH] arch: arm: recode the initialization of GICv3 ITS Re-Distributor tables
From: Hou Zhiqiang
The current implementation needs the caller provides the memory region
for the property and pending tables and the number of re-distibutor,
and it doesn't handle the address alignment of the tables and doesn't
help to add the reserved-memory node for the tables.
This patch change to use the device tree blob as argument and deal with
the aboves in the internal of this helper to make it easier to use.
Signed-off-by: Hou Zhiqiang
---
arch/arm/Kconfig| 1 -
arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 4 +-
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 46 +---
arch/arm/include/asm/gic-v3.h | 4 +-
arch/arm/lib/gic-v3-its.c | 142 ++--
5 files changed, 62 insertions(+), 135 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 391a77c2b4..0f6a32b428 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -82,7 +82,6 @@ config GICV3
config GIC_V3_ITS
bool "ARM GICV3 ITS"
- select IRQ
help
ARM GICV3 Interrupt translation service (ITS).
Basic support for programming locality specific peripheral
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 2fa7ebf163..10cb675fae 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
- * Copyright 2020-2021 NXP
+ * Copyright 2020-2022 NXP
*/
#include
@@ -653,7 +653,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
get_board_sys_clk(), 1);
#ifdef CONFIG_GIC_V3_ITS
- ls_gic_rd_tables_init(blob);
+ gic_lpi_tables_init(blob);
#endif
#if defined(CONFIG_PCIE_LAYERSCAPE) || defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index d3a5cfaac1..51ed942f57 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -1,17 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014-2015 Freescale Semiconductor
- * Copyright 2019-2021 NXP
+ * Copyright 2019-2022 NXP
*/
#include
#include
-#include
#include
#include
#include
#include
-#include
#include
#include
#include
@@ -21,7 +19,6 @@
#include
#include
#include
-#include
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
#include
#endif
@@ -36,47 +33,6 @@
#include
#include
#include
-#ifdef CONFIG_GIC_V3_ITS
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-#ifdef CONFIG_GIC_V3_ITS
-#define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
-#define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
-#define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
- PROPTABLE_MAX_SZ, SZ_1M)
-static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
-{
- int err;
- struct fdt_memory gic_rd_tables;
-
- gic_rd_tables.start = base;
- gic_rd_tables.end = base + size - 1;
- err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", _rd_tables,
-NULL, 0, NULL, 0);
- if (err < 0)
- debug("%s: failed to add reserved memory: %d\n", __func__, err);
-
- return err;
-}
-
-int ls_gic_rd_tables_init(void *blob)
-{
- u64 gic_lpi_base;
- int ret;
-
- gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
- ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
- if (ret)
- return ret;
-
- ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
- if (ret)
- debug("%s: failed to init gic-lpi-tables\n", __func__);
-
- return ret;
-}
-#endif
bool soc_has_dp_ddr(void)
{
diff --git a/arch/arm/include/asm/gic-v3.h b/arch/arm/include/asm/gic-v3.h
index 5131fabec4..e2e175f065 100644
--- a/arch/arm/include/asm/gic-v3.h
+++ b/arch/arm/include/asm/gic-v3.h
@@ -127,9 +127,9 @@
#define GIC_REDISTRIBUTOR_OFFSET 0x2
#ifdef CONFIG_GIC_V3_ITS
-int gic_lpi_tables_init(u64 base, u32 max_redist);
+int gic_lpi_tables_init(void *blob);
#else
-int gic_lpi_tables_init(u64 base, u32 max_redist)
+int gic_lpi_tables_init(void *blob);
{
return 0;
}
diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
index f6211a2d92..3ef1e74954 100644
--- a/arch/arm/lib/gic-v3-its.c
+++ b/arch/arm/lib/gic-v3-its.c
@@ -1,92 +1,65 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 Broadcom.
+ * Copyright 2022 NXP
*/
+
#include
#include
-#include
+#include
#include
#include
#include
#include
#include
+#include
static u32 lpi_id_bits;
#define LPI_NRBITS lpi_id_bits
-#define LPI_PROPBASE_SZALIGN(BIT(LPI_NRBITS), SZ_64K)
+#define LPI_PROPBASE_SZ
[PATCH] tools: pblimage: fix image header verification function
From: Hou Zhiqiang
The Layerscape platforms have different RCW header value from FSL
PowerPC platforms, the current image header verification callback
is only working on PowerPC, it will fail on Layerscape, this patch
is to fix this issue.
This is a historical problem and exposed by the following patch:
http://patchwork.ozlabs.org/project/uboot/patch/20220114173443.9877-1-p...@kernel.org
Signed-off-by: Hou Zhiqiang
---
Makefile | 2 +-
tools/pblimage.c | 10 --
tools/pblimage.h | 3 ++-
3 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/Makefile b/Makefile
index 4b152249ca..3c2bc9741c 100644
--- a/Makefile
+++ b/Makefile
@@ -1410,7 +1410,7 @@ MKIMAGEFLAGS_u-boot-spl.kwb = -n $(KWD_CONFIG_FILE) \
$(if $(KEYDIR),-k $(KEYDIR))
MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
- -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
+ -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -A $(ARCH) -T
pblimage
ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
UBOOT_BIN := u-boot-with-dtb.bin
diff --git a/tools/pblimage.c b/tools/pblimage.c
index 3c823e96cf..bd639c276f 100644
--- a/tools/pblimage.c
+++ b/tools/pblimage.c
@@ -230,19 +230,25 @@ static int pblimage_verify_header(unsigned char *ptr, int
image_size,
struct image_tool_params *params)
{
struct pbl_header *pbl_hdr = (struct pbl_header *) ptr;
+ uint32_t rcwheader;
+
+ if (params->arch == IH_ARCH_ARM)
+ rcwheader = RCW_ARM_HEADER;
+ else
+ rcwheader = RCW_PPC_HEADER;
/* Only a few checks can be done: search for magic numbers */
if (ENDIANNESS == 'l') {
if (pbl_hdr->preamble != reverse_byte(RCW_PREAMBLE))
return -FDT_ERR_BADSTRUCTURE;
- if (pbl_hdr->rcwheader != reverse_byte(RCW_HEADER))
+ if (pbl_hdr->rcwheader != reverse_byte(rcwheader))
return -FDT_ERR_BADSTRUCTURE;
} else {
if (pbl_hdr->preamble != RCW_PREAMBLE)
return -FDT_ERR_BADSTRUCTURE;
- if (pbl_hdr->rcwheader != RCW_HEADER)
+ if (pbl_hdr->rcwheader != rcwheader)
return -FDT_ERR_BADSTRUCTURE;
}
return 0;
diff --git a/tools/pblimage.h b/tools/pblimage.h
index 81c5492926..0222e8067b 100644
--- a/tools/pblimage.h
+++ b/tools/pblimage.h
@@ -8,7 +8,8 @@
#define RCW_BYTES 64
#define RCW_PREAMBLE 0xaa55aa55
-#define RCW_HEADER 0x010e0100
+#define RCW_ARM_HEADER 0x01ee0100
+#define RCW_PPC_HEADER 0x010e0100
struct pbl_header {
uint32_t preamble;
--
2.25.1
[PATCH] checkpatch: report ERROR only on disabling of fdt and initrd relocation
From: Hou Zhiqiang
Let the check pass when patches have these patterns in their context.
Signed-off-by: Hou Zhiqiang
---
scripts/checkpatch.pl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 5696d3a5f3..cf59e2bb70 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -2617,7 +2617,7 @@ sub u_boot_line {
}
# Do not disable fdt / initrd relocation
- if ($rawline =~ /.*(fdt|initrd)_high=0x/) {
+ if ($rawline =~ /^\+.*(fdt|initrd)_high=0x/) {
ERROR("DISABLE_FDT_OR_INITRD_RELOC",
"fdt or initrd relocation disabled at boot time\n" .
$herecurr);
}
--
2.25.1
[PATCHv2] pci: layerscape: update the searching compatible of LX2160A PCIe
From: Hou Zhiqiang
The current fixup of LX2160A PCIe nodes is based on non-production
rev1 silicon, and in Linux the nodes have been updated for rev2
silicon, so update the searching compatible string to match the
kernel changes. And for compatibility with the rev1 nodes, move
forward the board specific fixup.
Signed-off-by: Hou Zhiqiang
---
V2:
- Fix build issue on LS1021A platform.
drivers/pci/Kconfig | 4 +---
drivers/pci/pcie_layerscape_fixup.c | 9 +
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ba41787f64..16647bed54 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -219,8 +219,7 @@ config FSL_PCIE_COMPAT
default "fsl,ls1046a-pcie" if ARCH_LS1046A
default "fsl,ls2080a-pcie" if ARCH_LS2080A
default "fsl,ls1088a-pcie" if ARCH_LS1088A
- default "fsl,lx2160a-pcie" if ARCH_LX2160A
- default "fsl,ls2088a-pcie" if ARCH_LX2162A
+ default "fsl,ls2088a-pcie" if ARCH_LX2160A || ARCH_LX2162A
default "fsl,ls1021a-pcie" if ARCH_LS1021A
help
This compatible is used to find pci controller node in Kernel DT
@@ -229,7 +228,6 @@ config FSL_PCIE_COMPAT
config FSL_PCIE_EP_COMPAT
string "PCIe EP compatible of Kernel DT"
depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4
- default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A
default "fsl,ls-pcie-ep"
help
This compatible is used to find pci controller ep node in Kernel DT
diff --git a/drivers/pci/pcie_layerscape_fixup.c
b/drivers/pci/pcie_layerscape_fixup.c
index 8a2a0e1f4a..44d82bf856 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -527,7 +527,7 @@ static void fdt_fixup_pcie_ls(void *blob)
}
if (!IS_ENABLED(CONFIG_PCI_IOMMU_EXTRA_MAPPINGS))
- goto skip;
+ return;
list_for_each_entry(pcie_rc, _pcie_list, list) {
nodeoffset = fdt_pcie_get_nodeoffset(blob, pcie_rc);
@@ -568,9 +568,6 @@ static void fdt_fixup_pcie_ls(void *blob)
}
free(entries);
}
-
-skip:
- pcie_board_fix_fdt(blob);
}
#endif
@@ -619,6 +616,10 @@ void ft_pci_setup_ls(void *blob, struct bd_info *bd)
{
struct ls_pcie_rc *pcie_rc;
+#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
+ pcie_board_fix_fdt(blob);
+#endif
+
list_for_each_entry(pcie_rc, _pcie_list, list)
ft_pcie_ls_setup(blob, pcie_rc);
--
2.17.1
[PATCH] pci: layerscape: update the searching compatible of LX2160A PCIe
From: Hou Zhiqiang
The current fixup of LX2160A PCIe nodes is based on non-production
rev1 silicon, and in Linux the nodes have been updated for rev2
silicon, so update the searching compatible string to match the
kernel changes. And for compatibility with the rev1 nodes, move
forward the board specific fixup.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/Kconfig | 4 +---
drivers/pci/pcie_layerscape_fixup.c | 7 +++
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ba41787f64..16647bed54 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -219,8 +219,7 @@ config FSL_PCIE_COMPAT
default "fsl,ls1046a-pcie" if ARCH_LS1046A
default "fsl,ls2080a-pcie" if ARCH_LS2080A
default "fsl,ls1088a-pcie" if ARCH_LS1088A
- default "fsl,lx2160a-pcie" if ARCH_LX2160A
- default "fsl,ls2088a-pcie" if ARCH_LX2162A
+ default "fsl,ls2088a-pcie" if ARCH_LX2160A || ARCH_LX2162A
default "fsl,ls1021a-pcie" if ARCH_LS1021A
help
This compatible is used to find pci controller node in Kernel DT
@@ -229,7 +228,6 @@ config FSL_PCIE_COMPAT
config FSL_PCIE_EP_COMPAT
string "PCIe EP compatible of Kernel DT"
depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4
- default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A
default "fsl,ls-pcie-ep"
help
This compatible is used to find pci controller ep node in Kernel DT
diff --git a/drivers/pci/pcie_layerscape_fixup.c
b/drivers/pci/pcie_layerscape_fixup.c
index 48aeb50e68..6fdb0ac1d6 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -527,7 +527,7 @@ static void fdt_fixup_pcie_ls(void *blob)
}
if (!IS_ENABLED(CONFIG_PCI_IOMMU_EXTRA_MAPPINGS))
- goto skip;
+ return;
list_for_each_entry(pcie_rc, _pcie_list, list) {
nodeoffset = fdt_pcie_get_nodeoffset(blob, pcie_rc);
@@ -568,9 +568,6 @@ static void fdt_fixup_pcie_ls(void *blob)
}
free(entries);
}
-
-skip:
- pcie_board_fix_fdt(blob);
}
#endif
@@ -619,6 +616,8 @@ void ft_pci_setup_ls(void *blob, struct bd_info *bd)
{
struct ls_pcie_rc *pcie_rc;
+ pcie_board_fix_fdt(blob);
+
list_for_each_entry(pcie_rc, _pcie_list, list)
ft_pcie_ls_setup(blob, pcie_rc);
--
2.25.1
[PATCHv2] pci: layerscape: Fix the LUT and msi-map mismatch issue
From: Hou Zhiqiang
In the current code, it doesn't reset the cursors of LUT entry and
StreamID at the beginning of the fixup, so it can result in LUT entry
setup and msi-map mismatch and LUT entries and StreamID leaking
when reload and fixup the DTB.
This patch move the initialization of LUT entry and StreamID cursors
to the beginning of the fixup to resolve the issues.
Signed-off-by: Hou Zhiqiang
---
V2:
- Add fix for gen4 driver.
drivers/pci/pcie_layerscape_fixup.c| 8 +++-
drivers/pci/pcie_layerscape_fixup_common.c | 6 +++---
drivers/pci/pcie_layerscape_gen4.c | 4 +---
drivers/pci/pcie_layerscape_gen4_fixup.c | 5 -
drivers/pci/pcie_layerscape_rc.c | 3 +--
5 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_fixup.c
b/drivers/pci/pcie_layerscape_fixup.c
index a58e7a3892..8a2a0e1f4a 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2020 NXP
+ * Copyright 2017-2021 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Layerscape PCIe driver
*/
@@ -24,6 +24,8 @@
#include "pcie_layerscape.h"
#include "pcie_layerscape_fixup_common.h"
+int next_stream_id;
+
static int fdt_pcie_get_nodeoffset(void *blob, struct ls_pcie_rc *pcie_rc)
{
int nodeoffset;
@@ -607,6 +609,9 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie_rc
*pcie_rc)
{
ft_pcie_ep_fix(blob, pcie_rc);
ft_pcie_rc_fix(blob, pcie_rc);
+
+ pcie_rc->stream_id_cur = 0;
+ pcie_rc->next_lut_index = 0;
}
/* Fixup Kernel DT for PCIe */
@@ -618,6 +623,7 @@ void ft_pci_setup_ls(void *blob, struct bd_info *bd)
ft_pcie_ls_setup(blob, pcie_rc);
#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
+ next_stream_id = FSL_PEX_STREAM_ID_START;
fdt_fixup_pcie_ls(blob);
#endif
}
diff --git a/drivers/pci/pcie_layerscape_fixup_common.c
b/drivers/pci/pcie_layerscape_fixup_common.c
index 8b924d404c..257b4241a9 100644
--- a/drivers/pci/pcie_layerscape_fixup_common.c
+++ b/drivers/pci/pcie_layerscape_fixup_common.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2021 NXP
*
* PCIe DT fixup for NXP Layerscape SoCs
* Author: Wasim Khan
@@ -14,6 +14,8 @@
#include
#include "pcie_layerscape_fixup_common.h"
+extern int next_stream_id;
+
void ft_pci_setup(void *blob, struct bd_info *bd)
{
#if defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
@@ -146,8 +148,6 @@ int pcie_next_streamid(int currentid, int idx)
/* returns the next available streamid for pcie, -errno if failed */
int pcie_next_streamid(int currentid, int idx)
{
- static int next_stream_id = FSL_PEX_STREAM_ID_START;
-
if (next_stream_id > FSL_PEX_STREAM_ID_END)
return -EINVAL;
diff --git a/drivers/pci/pcie_layerscape_gen4.c
b/drivers/pci/pcie_layerscape_gen4.c
index 255e73181d..6ecdd6af40 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2021 NXP
*
* PCIe Gen4 driver for NXP Layerscape SoCs
* Author: Hou Zhiqiang
@@ -305,8 +305,6 @@ static void ls_pcie_g4_setup_ctrl(struct ls_pcie_g4 *pcie)
ccsr_writel(pcie, PAB_AXI_PIO_CTRL(0), val);
ls_pcie_g4_setup_wins(pcie);
-
- pcie->stream_id_cur = 0;
}
static void ls_pcie_g4_ep_inbound_win_set(struct ls_pcie_g4 *pcie, int pf,
diff --git a/drivers/pci/pcie_layerscape_gen4_fixup.c
b/drivers/pci/pcie_layerscape_gen4_fixup.c
index e9ee15558e..7d11234106 100644
--- a/drivers/pci/pcie_layerscape_gen4_fixup.c
+++ b/drivers/pci/pcie_layerscape_gen4_fixup.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2021 NXP
*
* PCIe Gen4 driver for NXP Layerscape SoCs
* Author: Hou Zhiqiang
@@ -223,6 +223,9 @@ static void ft_pcie_layerscape_gen4_setup(void *blob,
struct ls_pcie_g4 *pcie)
{
ft_pcie_rc_layerscape_gen4_fix(blob, pcie);
ft_pcie_ep_layerscape_gen4_fix(blob, pcie);
+
+ pcie->stream_id_cur = 0;
+ pcie->next_lut_index = 0;
}
/* Fixup Kernel DT for PCIe */
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index bd2c19f7f0..5dc71fc75a 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2020 NXP
+ * Copyright 2020,2021 NXP
* Layerscape PCIe driver
*/
@@ -238,7 +238,6 @@ static void ls_pcie_setup_ctrl(struct ls_pcie_rc *pcie_rc)
ls_pcie_dbi_ro_wr_dis(pcie);
ls_pcie_disable_bars(pcie_rc);
- pcie_rc->stream_id_cur = 0;
}
static int ls_pcie_probe(struct udevice *dev)
--
2.17.1
[PATCH] pci: layerscape: Fix the LUT and msi-map mismatch issue
From: Hou Zhiqiang
In the current code, it doesn't reset the cursors of LUT entry and
StreamID at the beginning of the fixup, so it can result in LUT entry
setup and msi-map mismatch and LUT entries and StreamID leaking
when reload and fixup the DTB.
This patch move the initialization of LUT entry and StreamID cursors
to the beginning of the fixup to resolve the issues.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pcie_layerscape_fixup.c| 8 +++-
drivers/pci/pcie_layerscape_fixup_common.c | 6 +++---
drivers/pci/pcie_layerscape_rc.c | 3 +--
3 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_fixup.c
b/drivers/pci/pcie_layerscape_fixup.c
index a58e7a3892..8a2a0e1f4a 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2020 NXP
+ * Copyright 2017-2021 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Layerscape PCIe driver
*/
@@ -24,6 +24,8 @@
#include "pcie_layerscape.h"
#include "pcie_layerscape_fixup_common.h"
+int next_stream_id;
+
static int fdt_pcie_get_nodeoffset(void *blob, struct ls_pcie_rc *pcie_rc)
{
int nodeoffset;
@@ -607,6 +609,9 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie_rc
*pcie_rc)
{
ft_pcie_ep_fix(blob, pcie_rc);
ft_pcie_rc_fix(blob, pcie_rc);
+
+ pcie_rc->stream_id_cur = 0;
+ pcie_rc->next_lut_index = 0;
}
/* Fixup Kernel DT for PCIe */
@@ -618,6 +623,7 @@ void ft_pci_setup_ls(void *blob, struct bd_info *bd)
ft_pcie_ls_setup(blob, pcie_rc);
#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
+ next_stream_id = FSL_PEX_STREAM_ID_START;
fdt_fixup_pcie_ls(blob);
#endif
}
diff --git a/drivers/pci/pcie_layerscape_fixup_common.c
b/drivers/pci/pcie_layerscape_fixup_common.c
index 8b924d404c..257b4241a9 100644
--- a/drivers/pci/pcie_layerscape_fixup_common.c
+++ b/drivers/pci/pcie_layerscape_fixup_common.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2021 NXP
*
* PCIe DT fixup for NXP Layerscape SoCs
* Author: Wasim Khan
@@ -14,6 +14,8 @@
#include
#include "pcie_layerscape_fixup_common.h"
+extern int next_stream_id;
+
void ft_pci_setup(void *blob, struct bd_info *bd)
{
#if defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
@@ -146,8 +148,6 @@ int pcie_next_streamid(int currentid, int idx)
/* returns the next available streamid for pcie, -errno if failed */
int pcie_next_streamid(int currentid, int idx)
{
- static int next_stream_id = FSL_PEX_STREAM_ID_START;
-
if (next_stream_id > FSL_PEX_STREAM_ID_END)
return -EINVAL;
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index bd2c19f7f0..5dc71fc75a 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2020 NXP
+ * Copyright 2020,2021 NXP
* Layerscape PCIe driver
*/
@@ -238,7 +238,6 @@ static void ls_pcie_setup_ctrl(struct ls_pcie_rc *pcie_rc)
ls_pcie_dbi_ro_wr_dis(pcie);
ls_pcie_disable_bars(pcie_rc);
- pcie_rc->stream_id_cur = 0;
}
static int ls_pcie_probe(struct udevice *dev)
--
2.17.1
[PATCHv2] configs: Layerscape: Remove the 'fdt_addr' env
From: Hou Zhiqiang On Layerscape platforms, the DTB is loaded from boot filesystem, per the fdt_addr description in doc/README.distro, it must be removed. Signed-off-by: Hou Zhiqiang --- V2: - Removed unrelated description in change log. include/configs/ls1012a2g5rdb.h | 1 - include/configs/ls1012afrdm.h| 2 +- include/configs/ls1012afrwy.h| 1 - include/configs/ls1012aqds.h | 1 - include/configs/ls1012ardb.h | 1 - include/configs/ls1021atsn.h | 3 +-- include/configs/ls1021atwr.h | 4 +--- include/configs/ls1028aqds.h | 3 +-- include/configs/ls1028ardb.h | 3 +-- include/configs/ls1043a_common.h | 1 - include/configs/ls1046a_common.h | 1 - include/configs/ls1088ardb.h | 2 -- include/configs/ls2080ardb.h | 2 -- include/configs/lx2160a_common.h | 1 - 14 files changed, 5 insertions(+), 21 deletions(-) diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index 44f9da7306..d9ff011bac 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -29,7 +29,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0x\0" \ - "fdt_addr=0x00f0\0" \ "kernel_addr=0x0100\0" \ "kernelheader_addr=0x80\0" \ "scriptaddr=0x8000\0" \ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 2711f651d7..c7fdd10cf5 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #ifndef __LS1012ARDB_H__ @@ -24,7 +25,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "fdt_high=0x\0" \ - "fdt_addr=0x00f0\0" \ "kernel_addr=0x0100\0" \ "scriptaddr=0x8000\0" \ "fdtheader_addr_r=0x8010\0" \ diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index f8b386125c..7ffca56d72 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -41,7 +41,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0x\0" \ - "fdt_addr=0x00f0\0" \ "kernel_addr=0x0100\0" \ "kernel_size_sd=0x16000\0" \ "kernelhdr_size_sd=0x10\0" \ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 3e5fdadc40..d0bfd3e494 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -101,7 +101,6 @@ #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ - "fdt_addr=0x00f0\0" \ "kernel_addr=0x0100\0" \ "kernelheader_addr=0x60\0" \ "scriptaddr=0x8000\0" \ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index c8a2f120dc..6fff966ee2 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -46,7 +46,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0x\0" \ - "fdt_addr=0x00f0\0" \ "kernel_addr=0x0100\0" \ "kernelheader_addr=0x60\0" \ "scriptaddr=0x8000\0" \ diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 58c2d97a32..97fd61f6f9 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 - * Copyright 2016-2019 NXP Semiconductors + * Copyright 2016-2019, 2021 NXP Semiconductors * Copyright 2019 Vladimir Oltean */ @@ -151,7 +151,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "initrd_high=0x\0" \ - "fdt_addr=0x64f0\0" \ "kernel_addr=0x6100\0" \ "kernelheader_addr=0x6080\0"\ "scriptaddr=0x8000\0" \ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index ba308c514b..5be179a36b 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2019 NXP + *
[PATCH] configs: Layerscape: Remove the 'fdt_addr' env
From: Hou Zhiqiang On Layerscape platforms, the DTB is loaded from boot filesystem, per the fdt_addr description in doc/README.distro, it must be removed. And on many platforms, like ls1046a, ls1088a, ls2088a and lx216xa, the 'fdt_addr' pointed address is not accessible. And with the current EFI boot process, since the EFI_LOADER and CMD_BOOTEFI_BOOTMGR are enabled by default, if the EFI boot components are not deployed in the boot filesystem, it will try to get DTB at address 'fdt_addr' and then result in "SError" or "Synchronous Abort": Error log on ls1046ardb: => run distro_bootcmd switch to partitions #0, OK mmc0 is current device Scanning mmc 0:1... libfdt fdt_check_header(): FDT_ERR_BADMAGIC Scanning disk es...@156.blk... Found 5 disks No EFI system partition "Error" handler, esr 0xbf00 elr: 820704f4 lr : 820080d4 (reloc) elr: fbd914f4 lr : fbd290d4 x0 : 64f0 x1 : edfe0dd0 x2 : x3 : x4 : fbc2ee1a x5 : 000f x6 : x7 : 0008 x8 : 0010 x9 : 0008 x10: 0044 x11: 00080220 x12: fbdaa748 x13: fbda70f8 x14: fbd21d20 x15: fbc194e8 x16: fbd70fc8 x17: x18: fbc1cdb0 x19: fbd21bf0 x20: 64f0 x21: fbda6fb8 x22: 0018 x23: 0018 x24: fbde6344 x25: x26: x27: x28: fbc53660 x29: fbc19220 Code: 7a419060 1a9f3000 a8c17bfd d65f03c0 (12800100) Resetting CPU ... Signed-off-by: Hou Zhiqiang --- include/configs/ls1012a2g5rdb.h | 1 - include/configs/ls1012afrdm.h| 2 +- include/configs/ls1012afrwy.h| 1 - include/configs/ls1012aqds.h | 1 - include/configs/ls1012ardb.h | 1 - include/configs/ls1021atsn.h | 3 +-- include/configs/ls1021atwr.h | 4 +--- include/configs/ls1028aqds.h | 3 +-- include/configs/ls1028ardb.h | 3 +-- include/configs/ls1043a_common.h | 1 - include/configs/ls1046a_common.h | 1 - include/configs/ls1088ardb.h | 2 -- include/configs/ls2080ardb.h | 2 -- include/configs/lx2160a_common.h | 1 - 14 files changed, 5 insertions(+), 21 deletions(-) diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index 44f9da7306..d9ff011bac 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -29,7 +29,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0x\0" \ - "fdt_addr=0x00f0\0" \ "kernel_addr=0x0100\0" \ "kernelheader_addr=0x80\0" \ "scriptaddr=0x8000\0" \ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 2711f651d7..c7fdd10cf5 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #ifndef __LS1012ARDB_H__ @@ -24,7 +25,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "fdt_high=0x\0" \ - "fdt_addr=0x00f0\0" \ "kernel_addr=0x0100\0" \ "scriptaddr=0x8000\0" \ "fdtheader_addr_r=0x8010\0" \ diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index f8b386125c..7ffca56d72 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -41,7 +41,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0x\0" \ - "fdt_addr=0x00f0\0" \ "kernel_addr=0x0100\0" \ "kernel_size_sd=0x16000\0" \ "kernelhdr_size_sd=0x10\0" \ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 3e5fdadc40..d0bfd3e494 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -101,7 +101,6 @@ #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ - "fdt_addr=0x00f0\0" \ "kernel_addr=0x0100\0" \ "kernelheader_addr=0x60\0" \ "scriptaddr=0x8000\0" \ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index
[PATCH] configs: layerscape: Disable the EFI_LOADER feature
From: Hou Zhiqiang
The feature BOOTENV_SHARED_EFI is not supported on layerscape
boards, it didn't result kernel boot crash previously since
there isn't the efi/boot/"BOOTEFI_NAME" and it skip calling of
'boot_efi_binary'.
But since the commit f3866909e350 ("distro_bootcmd: call EFI
bootmgr even without having /EFI/boot"), it will cause kernel
boot crash as there isn't a valid fdt_addr and it finially uses
the device tree blob of U-Boot and further cause errors.
As this feature is enabled by default for armv7 and armv8, so
disable it explicitly to avoid calling the 'scan_dev_for_efi'.
Signed-off-by: Hou Zhiqiang
---
configs/ls1012a2g5rdb_qspi_defconfig | 1 +
configs/ls1012a2g5rdb_tfa_defconfig | 1 +
configs/ls1012afrdm_qspi_defconfig | 1 +
configs/ls1012afrdm_tfa_defconfig| 1 +
configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 1 +
configs/ls1012afrwy_qspi_defconfig | 1 +
configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig| 1 +
configs/ls1012afrwy_tfa_defconfig| 1 +
configs/ls1012aqds_qspi_defconfig| 1 +
configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 1 +
configs/ls1012aqds_tfa_defconfig | 1 +
configs/ls1012ardb_qspi_SECURE_BOOT_defconfig| 1 +
configs/ls1012ardb_qspi_defconfig| 1 +
configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 1 +
configs/ls1012ardb_tfa_defconfig | 1 +
configs/ls1021aiot_qspi_defconfig| 1 +
configs/ls1021aiot_sdcard_defconfig | 1 +
configs/ls1021aqds_ddr4_nor_defconfig| 1 +
configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 +
configs/ls1021aqds_nand_defconfig| 1 +
configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 +
configs/ls1021aqds_nor_defconfig | 1 +
configs/ls1021aqds_nor_lpuart_defconfig | 1 +
configs/ls1021aqds_qspi_defconfig| 1 +
configs/ls1021aqds_sdcard_ifc_defconfig | 1 +
configs/ls1021aqds_sdcard_qspi_defconfig | 1 +
configs/ls1021atsn_qspi_defconfig| 1 +
configs/ls1021atsn_sdcard_defconfig | 1 +
configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 +
configs/ls1021atwr_nor_defconfig | 1 +
configs/ls1021atwr_nor_lpuart_defconfig | 1 +
configs/ls1021atwr_qspi_defconfig| 1 +
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 +
configs/ls1021atwr_sdcard_ifc_defconfig | 1 +
configs/ls1021atwr_sdcard_qspi_defconfig | 1 +
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 1 +
configs/ls1028aqds_tfa_defconfig | 1 +
configs/ls1028aqds_tfa_lpuart_defconfig | 1 +
configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 1 +
configs/ls1028ardb_tfa_defconfig | 1 +
configs/ls1043aqds_defconfig | 1 +
configs/ls1043aqds_lpuart_defconfig | 1 +
configs/ls1043aqds_nand_defconfig| 1 +
configs/ls1043aqds_nor_ddr3_defconfig| 1 +
configs/ls1043aqds_qspi_defconfig| 1 +
configs/ls1043aqds_sdcard_ifc_defconfig | 1 +
configs/ls1043aqds_sdcard_qspi_defconfig | 1 +
configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 1 +
configs/ls1043aqds_tfa_defconfig | 1 +
configs/ls1043ardb_SECURE_BOOT_defconfig | 1 +
configs/ls1043ardb_defconfig | 1 +
configs/ls1043ardb_nand_SECURE_BOOT_defconfig| 1 +
configs/ls1043ardb_nand_defconfig| 1 +
configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 +
configs/ls1043ardb_sdcard_defconfig | 1 +
configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 1 +
configs/ls1043ardb_tfa_defconfig | 1 +
configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig| 1 +
configs/ls1046afrwy_tfa_defconfig| 1 +
configs/ls1046aqds_SECURE_BOOT_defconfig | 1 +
configs/ls1046aqds_defconfig | 1 +
configs/ls1046aqds_lpuart_defconfig | 1 +
configs/ls1046aqds_nand_defconfig| 1 +
configs/ls1046aqds_qspi_defconfig| 1 +
configs/ls1046aqds_sdcard_ifc_defconfig | 1 +
configs/ls1046aqds_sdcard_qspi_defconfig | 1 +
configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 1 +
configs/ls1046aqds_tfa_defconfig | 1 +
configs/ls1046ardb_emmc_defconfig| 1 +
configs/ls1046ardb_qspi_SECURE_BOOT_defconfig| 1 +
configs/ls1046ardb_qspi_defconfig| 1 +
configs/ls1046ardb_qspi_spl_defconfig| 1 +
configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
[PATCH] net: fm: Fix a memory leak issue
From: Hou Zhiqiang
Fix a memory leak issue in the RX port initialization.
Signed-off-by: Hou Zhiqiang
---
drivers/net/fm/eth.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 0e89e663f7..7c23ccc1f0 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -288,8 +288,10 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth
*fm_eth)
/* alloc Rx buffer from main memory */
rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
- if (!rx_buf_pool)
+ if (!rx_buf_pool) {
+ free(rx_bd_ring_base);
return -ENOMEM;
+ }
memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
--
2.17.1
[PATCH] net: e1000: Fix Unchecked return value coverity
From: Hou Zhiqiang
Added check for return value of e1000_read_phy_reg().
Signed-off-by: Hou Zhiqiang
---
drivers/net/e1000.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 694114eca7..1f0d559415 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -4738,12 +4738,16 @@ e1000_phy_init_script(struct e1000_hw *hw)
uint16_t fused, fine, coarse;
/* Move to analog registers page */
- e1000_read_phy_reg(hw,
- IGP01E1000_ANALOG_SPARE_FUSE_STATUS, );
+ if (e1000_read_phy_reg(hw,
+
IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
+ ))
+ return;
if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
- e1000_read_phy_reg(hw,
- IGP01E1000_ANALOG_FUSE_STATUS, );
+ if (e1000_read_phy_reg(hw,
+
IGP01E1000_ANALOG_FUSE_STATUS,
+ ))
+ return;
fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
coarse = fused
--
2.17.1
[PATCH] pci: layerscape: Change to allocate zeroed memery for struct ls_pcie
From: Hou Zhiqiang
As on some incipient Layerscape platforms (LS1043A series) there isn't
separate PF control register block, these registers reside in the LUT
register block, so when the driver detected there isn't 'ctrl', it will
assign the 'lut' address to the ls_pcie->ctrl.
The current code allocate memory for the struct ls_pcie with random
contents, this can result in skipping to assign the ls_pcie->ctrl with
the 'lut' address, then further crash with the incorrect address.
Fixes: 118e58e26eba ("pci: layerscape: Split the EP and RC driver")
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pcie_layerscape_ep.c | 2 +-
drivers/pci/pcie_layerscape_rc.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index 14983cce4f..c7231635e4 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -244,7 +244,7 @@ static int ls_pcie_ep_probe(struct udevice *dev)
int ret;
u32 svr;
- pcie = devm_kmalloc(dev, sizeof(*pcie), GFP_KERNEL);
+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
if (!pcie)
return -ENOMEM;
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index b055ed5165..bd2c19f7f0 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -254,7 +254,7 @@ static int ls_pcie_probe(struct udevice *dev)
pcie_rc->bus = dev;
- pcie = devm_kmalloc(dev, sizeof(*pcie), GFP_KERNEL);
+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
if (!pcie)
return -ENOMEM;
--
2.17.1
[PATCHv3] arm64: gic-v3-its: Clear the Pending table before enabling LPIs
From: Hou Zhiqiang
The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables
must contain only zeros on initial allocation, and this must be visible
to the Redistributors, or else the effect is UNPREDICTABLE".
And as the following statement, we here clear the whole Pending tables
instead of the first 1KB.
"An LPI Pending table that contains only zeros, including in the first 1KB,
indicates that there are no pending LPIs.
The first 1KB of the LPI Pending table is IMPLEMENTATION DEFINED. However,
if the first 1KB of the LPI Pending table and the rest of the table contain
only zeros, this must indicate that there are no pending LPIs."
And there isn't any pending LPI under U-Boot, so it's unnecessary to
load the contents of the Pending table during the enablement, then set
the GICR_PENDBASER.PTZ flag.
Signed-off-by: Hou Zhiqiang
---
V3:
- Fix a mistake code delete in v2.
arch/arm/lib/gic-v3-its.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
index f5a921b3d1..2d3fdb600e 100644
--- a/arch/arm/lib/gic-v3-its.c
+++ b/arch/arm/lib/gic-v3-its.c
@@ -3,6 +3,7 @@
* Copyright 2019 Broadcom.
*/
#include
+#include
#include
#include
#include
@@ -108,6 +109,8 @@ int gic_lpi_tables_init(void)
int i;
u64 redist_lpi_base;
u64 pend_base;
+ ulong pend_tab_total_sz;
+ void *pend_tab_va;
if (gic_v3_its_get_gic_addr())
return -EINVAL;
@@ -161,6 +164,12 @@ int gic_lpi_tables_init(void)
}
redist_lpi_base = priv.lpi_base + LPI_PROPBASE_SZ;
+ pend_tab_total_sz = priv.num_redist * LPI_PENDBASE_SZ;
+ pend_tab_va = map_physmem(redist_lpi_base, pend_tab_total_sz,
+ MAP_NOCACHE);
+ memset(pend_tab_va, 0, pend_tab_total_sz);
+ flush_cache((ulong)pend_tab_va, pend_tab_total_sz);
+ unmap_physmem(pend_tab_va, MAP_NOCACHE);
pend_base = priv.gicr_base + GICR_PENDBASER;
for (i = 0; i < priv.num_redist; i++) {
@@ -168,7 +177,8 @@ int gic_lpi_tables_init(void)
val = ((redist_lpi_base + (i * LPI_PENDBASE_SZ)) |
GICR_PENDBASER_INNERSHAREABLE |
- GICR_PENDBASER_RAWAWB);
+ GICR_PENDBASER_RAWAWB |
+ GICR_PENDBASER_PTZ);
writeq(val, (uintptr_t)(pend_base + offset));
tmp = readq((uintptr_t)(pend_base + offset));
--
2.17.1
[PATCHv2] arm64: gic-v3-its: Clear the Pending table before enabling LPIs
From: Hou Zhiqiang
The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables
must contain only zeros on initial allocation, and this must be visible
to the Redistributors, or else the effect is UNPREDICTABLE".
And as the following statement, we here clear the whole Pending tables
instead of the first 1KB.
"An LPI Pending table that contains only zeros, including in the first 1KB,
indicates that there are no pending LPIs.
The first 1KB of the LPI Pending table is IMPLEMENTATION DEFINED. However,
if the first 1KB of the LPI Pending table and the rest of the table contain
only zeros, this must indicate that there are no pending LPIs."
And there isn't any pending LPI under U-Boot, so it's unnecessary to
load the contents of the Pending table during the enablement, then set
the GICR_PENDBASER.PTZ flag.
Signed-off-by: Hou Zhiqiang
---
V2:
- Clear the Pending tables using virtual address.
- Correct some typos in the change log.
arch/arm/lib/gic-v3-its.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
index f5a921b3d1..2dadc48a50 100644
--- a/arch/arm/lib/gic-v3-its.c
+++ b/arch/arm/lib/gic-v3-its.c
@@ -3,6 +3,7 @@
* Copyright 2019 Broadcom.
*/
#include
+#include
#include
#include
#include
@@ -108,6 +109,8 @@ int gic_lpi_tables_init(void)
int i;
u64 redist_lpi_base;
u64 pend_base;
+ ulong pend_tab_total_sz;
+ void *pend_tab_va;
if (gic_v3_its_get_gic_addr())
return -EINVAL;
@@ -160,7 +163,12 @@ int gic_lpi_tables_init(void)
}
}
- redist_lpi_base = priv.lpi_base + LPI_PROPBASE_SZ;
+ pend_tab_total_sz = priv.num_redist * LPI_PENDBASE_SZ;
+ pend_tab_va = map_physmem(redist_lpi_base, pend_tab_total_sz,
+ MAP_NOCACHE);
+ memset(pend_tab_va, 0, pend_tab_total_sz);
+ flush_cache((ulong)pend_tab_va, pend_tab_total_sz);
+ unmap_physmem(pend_tab_va, MAP_NOCACHE);
pend_base = priv.gicr_base + GICR_PENDBASER;
for (i = 0; i < priv.num_redist; i++) {
@@ -168,7 +176,8 @@ int gic_lpi_tables_init(void)
val = ((redist_lpi_base + (i * LPI_PENDBASE_SZ)) |
GICR_PENDBASER_INNERSHAREABLE |
- GICR_PENDBASER_RAWAWB);
+ GICR_PENDBASER_RAWAWB |
+ GICR_PENDBASER_PTZ);
writeq(val, (uintptr_t)(pend_base + offset));
tmp = readq((uintptr_t)(pend_base + offset));
--
2.17.1
[PATCH] arm64: gic-v3-its: Clear the Pending talbe before enabling LPIs
From: Hou Zhiqiang
The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables
must contain only zeros on initial allocation, and this must be visible
to the Redistributors, or else the effect is UNPREDICTABLE".
And as the following statement, we here clear the whole Pending talbes
instead of the first 1KB.
"An LPI Pending table that contains only zeros, including in the first 1KB,
indicates that there are no pending LPIs.
The first 1KB of the LPI Pending table is IMPLEMENTATION DEFINED. However,
if the first 1KB of the LPI Pending table and the rest of the table contain
only zeros, this must indicate that there are no pending LPIs."
And there isn't any pending LPI under U-Boot, so it's unnecessary to
loading the contents of the Pending talbe during the enablement, then set
the GICR_PENDBASER.PTZ flag.
Signed-off-by: Hou Zhiqiang
---
arch/arm/lib/gic-v3-its.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
index f5a921b3d1..5620e67ce3 100644
--- a/arch/arm/lib/gic-v3-its.c
+++ b/arch/arm/lib/gic-v3-its.c
@@ -3,6 +3,7 @@
* Copyright 2019 Broadcom.
*/
#include
+#include
#include
#include
#include
@@ -161,6 +162,8 @@ int gic_lpi_tables_init(void)
}
redist_lpi_base = priv.lpi_base + LPI_PROPBASE_SZ;
+ memset((void *)redist_lpi_base, 0, priv.num_redist * LPI_PENDBASE_SZ);
+ flush_cache(redist_lpi_base, priv.num_redist * LPI_PENDBASE_SZ);
pend_base = priv.gicr_base + GICR_PENDBASER;
for (i = 0; i < priv.num_redist; i++) {
@@ -168,7 +171,8 @@ int gic_lpi_tables_init(void)
val = ((redist_lpi_base + (i * LPI_PENDBASE_SZ)) |
GICR_PENDBASER_INNERSHAREABLE |
- GICR_PENDBASER_RAWAWB);
+ GICR_PENDBASER_RAWAWB |
+ GICR_PENDBASER_PTZ);
writeq(val, (uintptr_t)(pend_base + offset));
tmp = readq((uintptr_t)(pend_base + offset));
--
2.17.1
[PATCH] configs: T1042: Drop the CONFIG_VIDEO
From: Hou Zhiqiang Drop the CONFIG_VIDEO to fix the following build warning. = WARNING == This board does not use CONFIG_DM_VIDEO Please update the board to use CONFIG_DM_VIDEO before the v2019.07 release. UPD include/generated/dt.h Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. UPD include/generated/timestamp_autogenerated.h Signed-off-by: Hou Zhiqiang --- configs/T1042D4RDB_NAND_defconfig | 1 - configs/T1042D4RDB_SDCARD_defconfig| 1 - configs/T1042D4RDB_SECURE_BOOT_defconfig | 1 - configs/T1042D4RDB_SPIFLASH_defconfig | 1 - configs/T1042D4RDB_defconfig | 1 - configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig | 1 - configs/T1042RDB_PI_NAND_defconfig | 1 - configs/T1042RDB_PI_SDCARD_defconfig | 1 - configs/T1042RDB_PI_SPIFLASH_defconfig | 1 - configs/T1042RDB_PI_defconfig | 1 - 10 files changed, 10 deletions(-) diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 855b00ad53..ee7b6faa42 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -84,7 +84,6 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index b43998a9a7..c64ad0b1fd 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -81,7 +81,6 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig index b3ad98a957..5ce39120c5 100644 --- a/configs/T1042D4RDB_SECURE_BOOT_defconfig +++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig @@ -57,7 +57,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 91f29c6ceb..46eaf5e979 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -83,7 +83,6 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 444c797f2e..3ac43772ae 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -69,7 +69,6 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig index f93ca9c573..ebe361b5a5 100644 --- a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig +++ b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig @@ -78,7 +78,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig index 5a8a35f8ad..f0329297df 100644 --- a/configs/T1042RDB_PI_NAND_defconfig +++ b/configs/T1042RDB_PI_NAND_defconfig @@ -76,7 +76,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig index 70cd3e7fa0..04fda7b2cc 100644 --- a/configs/T1042RDB_PI_SDCARD_defconfig +++ b/configs/T1042RDB_PI_SDCARD_defconfig @@ -73,7 +73,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig index 3b4e2a4fbf..2bd9b8ce88 100644 --- a/configs/T1042RDB_PI_SPIFLASH_defconfig +++ b/configs/T1042RDB_PI_SPIFLASH_defconfig @@ -75,7 +75,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig index b1daa41b23..07bf31fd18 100644 --- a/configs/T1042RDB_PI_defconfig +++ b/configs/T1042RDB_PI_defconfig @@ -60,7 +60,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 -- 2.17.1
[PATCH] armv7: ls102xa: Enable I-Cache to speed up the boot time
From: Hou Zhiqiang Enable the I-Cache to speed up the boot time, especailly for the NOR boot, currently it takes about 15 seconds from power up to the U-Boot prompt, and with the I-Cache enabled it only takes around 2.5 seconds. Signed-off-by: Hou Zhiqiang --- arch/arm/cpu/armv7/ls102xa/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index ce472aa9bd..c6a39aa341 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -316,6 +316,8 @@ int arch_cpu_init(void) struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; u32 state; + icache_enable(); + /* * The RCPM FSM state may not be reset after power-on. * So, reset them. -- 2.17.1
[PATCH] pci: kconfig: layerscape: Change LX2162A PCIe node compatible string
From: Hou Zhiqiang LX2162A is not like LX2160A which has different PCIe controller in rev1 and rev2 silicon. It supports only one configuration of PCIe controller, which is same as LS2088A. So update PCIe compatible string same as LS2088A. Signed-off-by: Hou Zhiqiang --- drivers/pci/Kconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index b1de38f766..ba41787f64 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -219,7 +219,8 @@ config FSL_PCIE_COMPAT default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A default "fsl,ls1088a-pcie" if ARCH_LS1088A - default "fsl,lx2160a-pcie" if ARCH_LX2160A || ARCH_LX2162A + default "fsl,lx2160a-pcie" if ARCH_LX2160A + default "fsl,ls2088a-pcie" if ARCH_LX2162A default "fsl,ls1021a-pcie" if ARCH_LS1021A help This compatible is used to find pci controller node in Kernel DT @@ -228,7 +229,7 @@ config FSL_PCIE_COMPAT config FSL_PCIE_EP_COMPAT string "PCIe EP compatible of Kernel DT" depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4 - default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A || ARCH_LX2162A + default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A default "fsl,ls-pcie-ep" help This compatible is used to find pci controller ep node in Kernel DT -- 2.17.1
[PATCHv2] pci: layerscape: Remove the shadow SVR definitions
From: Hou Zhiqiang This patch moves the SVR definitions to a new svr.h for Layerscape armv7 and armv8 platforms respectively, so that the PCIe driver can reuse them. Signed-off-by: Hou Zhiqiang --- V2: - rebase the patch and correct the typos in the subject .../arm/include/asm/arch-fsl-layerscape/soc.h | 33 +-- .../arm/include/asm/arch-fsl-layerscape/svr.h | 42 +++ arch/arm/include/asm/arch-ls102xa/svr.h | 13 ++ drivers/pci/pcie_layerscape.h | 12 +- 4 files changed, 58 insertions(+), 42 deletions(-) create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/svr.h create mode 100644 arch/arm/include/asm/arch-ls102xa/svr.h diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index b24f38cac9..367171cc97 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -16,6 +16,7 @@ #include #endif #endif +#include #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE #define gur_in32(a) in_le32(a) @@ -77,38 +78,6 @@ enum boot_src get_boot_src(void); #endif #endif #define SVR_WO_E 0xFE -#define SVR_LS1012A0x870400 -#define SVR_LS1043A0x879200 -#define SVR_LS1023A0x879208 -/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ -#define SVR_LS1043A_P230x879202 -#define SVR_LS1023A_P230x87920A -#define SVR_LS1017A0x870B24 -#define SVR_LS1018A0x870B20 -#define SVR_LS1027A0x870B04 -#define SVR_LS1028A0x870B00 -#define SVR_LS1046A0x870700 -#define SVR_LS1026A0x870708 -#define SVR_LS1048A0x870320 -#define SVR_LS1084A0x870302 -#define SVR_LS1088A0x870300 -#define SVR_LS1044A0x870322 -#define SVR_LS2045A0x870120 -#define SVR_LS2080A0x870110 -#define SVR_LS2085A0x870100 -#define SVR_LS2040A0x870130 -#define SVR_LS2088A0x870900 -#define SVR_LS2084A0x870910 -#define SVR_LS2048A0x870920 -#define SVR_LS2044A0x870930 -#define SVR_LS2081A0x870918 -#define SVR_LS2041A0x870914 -#define SVR_LX2160A0x873600 -#define SVR_LX2120A0x873620 -#define SVR_LX2080A0x873602 -#define SVR_LX2162A0x873608 -#define SVR_LX2122A0x873628 -#define SVR_LX2082A0x87360A #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/svr.h b/arch/arm/include/asm/arch-fsl-layerscape/svr.h new file mode 100644 index 00..e37c4a88b5 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/svr.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ +#define _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ + +#define SVR_LS1012A0x870400 +#define SVR_LS1043A0x879200 +#define SVR_LS1023A0x879208 +/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ +#define SVR_LS1043A_P230x879202 +#define SVR_LS1023A_P230x87920A +#define SVR_LS1017A0x870B24 +#define SVR_LS1018A0x870B20 +#define SVR_LS1027A0x870B04 +#define SVR_LS1028A0x870B00 +#define SVR_LS1046A0x870700 +#define SVR_LS1026A0x870708 +#define SVR_LS1048A0x870320 +#define SVR_LS1084A0x870302 +#define SVR_LS1088A0x870300 +#define SVR_LS1044A0x870322 +#define SVR_LS2045A0x870120 +#define SVR_LS2080A0x870110 +#define SVR_LS2085A0x870100 +#define SVR_LS2040A0x870130 +#define SVR_LS2088A0x870900 +#define SVR_LS2084A0x870910 +#define SVR_LS2048A0x870920 +#define SVR_LS2044A0x870930 +#define SVR_LS2081A0x870918 +#define SVR_LS2041A0x870914 +#define SVR_LX2160A0x873600 +#define SVR_LX2120A0x873620 +#define SVR_LX2080A0x873602 +#define SVR_LX2162A0x873608 +#define SVR_LX2122A0x873628 +#define SVR_LX2082A0x87360A + +#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/svr.h b/arch/arm/include/asm/arch-ls102xa/svr.h new file mode 100644 index 00..52b27e2d67 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/svr.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#ifndef _ASM_LS102X_SVR_H_ +#define _ASM_LS102X_SVR_H_ + +#define SVR_LS102XA0 +#define SVR_VAR_PER_SHIFT 8 +#define SVR_LS102XA_MASK 0x700 + +#endif /* _ASM_LS102X_SVR_H_ */ diff --git
[PATCH] pci: layerscape: fix a dead loop issue
From: Hou Zhiqiang
The commit 8ec619f8fd84 added the PCIe EP nodes fixup of LX2160A, but it
didn't update the condition value when there isn't a property 'apio-wins'.
Fixes: 8ec619f8fd84 ("pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A
rev2")
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pcie_layerscape_fixup_common.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pci/pcie_layerscape_fixup_common.c
b/drivers/pci/pcie_layerscape_fixup_common.c
index 0a42997696..b97c67ad84 100644
--- a/drivers/pci/pcie_layerscape_fixup_common.c
+++ b/drivers/pci/pcie_layerscape_fixup_common.c
@@ -99,6 +99,8 @@ int lx2_board_fix_fdt(void *fdt)
if (!prop) {
printf("%s: Failed to fixup PCIe EP node @0x%x\n",
__func__, off);
+ off = fdt_node_offset_by_compatible(fdt, off,
+
"fsl,lx2160a-pcie-ep");
continue;
}
--
2.17.1
[PATCH] dm: pci: fsl: Correct the workaround of erratum A-007815
From: Hou Zhiqiang
The register to enable/disable the write-permission of DBI RO
registers should be accessed via the CFG_ADDR/CFG_DATA registers
instead of accessing directly.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pcie_fsl.c | 20
drivers/pci/pcie_fsl.h | 2 ++
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index ab33459e28..fb50b8f518 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -396,6 +396,19 @@ static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)
return 0;
}
+static void fsl_pcie_dbi_read_only_reg_write_enable(struct fsl_pcie *pcie,
+ bool enable)
+{
+ u32 val;
+
+ fsl_pcie_hose_read_config_dword(pcie, DBI_RO_WR_EN, );
+ if (enable)
+ val |= 1;
+ else
+ val &= ~1;
+ fsl_pcie_hose_write_config_dword(pcie, DBI_RO_WR_EN, val);
+}
+
static int fsl_pcie_init_port(struct fsl_pcie *pcie)
{
ccsr_fsl_pci_t *regs = pcie->regs;
@@ -470,7 +483,7 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie)
* Set to 0 to protect the read-only registers.
*/
#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
- clrbits_be32(>dbi_ro_wr_en, 0x01);
+ fsl_pcie_dbi_read_only_reg_write_enable(pcie, false);
#endif
/*
@@ -504,13 +517,12 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie)
static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
{
- ccsr_fsl_pci_t *regs = pcie->regs;
u32 classcode_reg;
u32 val;
if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
classcode_reg = PCI_CLASS_REVISION;
- setbits_be32(>dbi_ro_wr_en, 0x01);
+ fsl_pcie_dbi_read_only_reg_write_enable(pcie, true);
} else {
classcode_reg = CSR_CLASSCODE;
}
@@ -521,7 +533,7 @@ static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);
if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
- clrbits_be32(>dbi_ro_wr_en, 0x01);
+ fsl_pcie_dbi_read_only_reg_write_enable(pcie, false);
return 0;
}
diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h
index dc8368d559..70c5f4e4cf 100644
--- a/drivers/pci/pcie_fsl.h
+++ b/drivers/pci/pcie_fsl.h
@@ -26,6 +26,8 @@
/* PCIe Link Status Register */
#define PCI_LSR(FSL_PCIE_CAP_ID + 0x12)
+#define DBI_RO_WR_EN 0x8bc
+
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
#define CONFIG_SYS_PCI_MEMORY_BUS 0
#endif
--
2.17.1
[PATCHv2] pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A rev2
From: Hou Zhiqiang
LX2160A rev2 uses different PCIe controller, so EP mode DT
nodes also need to be fixed up.
Signed-off-by: Hou Zhiqiang
---
V2:
- Fix a dead loop issue.
drivers/pci/pcie_layerscape_fixup_common.c | 28 ++
1 file changed, 28 insertions(+)
diff --git a/drivers/pci/pcie_layerscape_fixup_common.c
b/drivers/pci/pcie_layerscape_fixup_common.c
index fef0a75f11..b97c67ad84 100644
--- a/drivers/pci/pcie_layerscape_fixup_common.c
+++ b/drivers/pci/pcie_layerscape_fixup_common.c
@@ -41,6 +41,8 @@ int lx2_board_fix_fdt(void *fdt)
{ "config_axi_slave", "config" }
};
int off = -1, i;
+ const fdt32_t *prop;
+ u32 ob_wins, ib_wins;
off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
while (off != -FDT_ERR_NOTFOUND) {
@@ -86,6 +88,32 @@ int lx2_board_fix_fdt(void *fdt)
off = fdt_node_offset_by_compatible(fdt, off,
"fsl,lx2160a-pcie");
}
+
+ /* Fixup PCIe EP nodes */
+ off = -1;
+ off = fdt_node_offset_by_compatible(fdt, off, "fsl,lx2160a-pcie-ep");
+ while (off != -FDT_ERR_NOTFOUND) {
+ fdt_setprop_string(fdt, off, "compatible",
+ "fsl,lx2160ar2-pcie-ep");
+ prop = fdt_getprop(fdt, off, "apio-wins", NULL);
+ if (!prop) {
+ printf("%s: Failed to fixup PCIe EP node @0x%x\n",
+ __func__, off);
+ off = fdt_node_offset_by_compatible(fdt, off,
+
"fsl,lx2160a-pcie-ep");
+ continue;
+ }
+
+ ob_wins = fdt32_to_cpu(*prop);
+ ib_wins = (ob_wins == 256) ? 24 : 8;
+ fdt_setprop_u32(fdt, off, "num-ib-windows", ib_wins);
+ fdt_setprop_u32(fdt, off, "num-ob-windows", ob_wins);
+ fdt_delprop(fdt, off, "apio-wins");
+
+ off = fdt_node_offset_by_compatible(fdt, off,
+ "fsl,lx2160a-pcie-ep");
+ }
+
return 0;
}
--
2.17.1
[PATCHv6 16/18] dts: powerpc: p2020rdb: Add eTSEC DT nodes
From: Hou Zhiqiang
P2020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang
---
V6:
- No change.
arch/powerpc/dts/p2020-post.dtsi | 8 +++--
arch/powerpc/dts/p2020rdb-pc.dts | 1 +
arch/powerpc/dts/p2020rdb-pc.dtsi| 50
arch/powerpc/dts/p2020rdb-pc_36b.dts | 1 +
arch/powerpc/dts/pq3-etsec1-0.dtsi | 28
arch/powerpc/dts/pq3-etsec1-1.dtsi | 28
arch/powerpc/dts/pq3-etsec1-2.dtsi | 28
arch/powerpc/dts/pq3-etsec1-3.dtsi | 28
8 files changed, 170 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/dts/p2020rdb-pc.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-0.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-1.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-2.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-3.dtsi
diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index 4ed093dad4..11945295d1 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -38,8 +38,12 @@
clock-frequency = <0>;
};
- /include/ "pq3-i2c-0.dtsi"
- /include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec1-0.dtsi"
+/include/ "pq3-etsec1-1.dtsi"
+/include/ "pq3-etsec1-2.dtsi"
};
/* PCIe controller base address 0x8000 */
diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts
index 08befd4c59..f3f6be1080 100644
--- a/arch/powerpc/dts/p2020rdb-pc.dts
+++ b/arch/powerpc/dts/p2020rdb-pc.dts
@@ -37,4 +37,5 @@
};
};
+/include/ "p2020rdb-pc.dtsi"
/include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/p2020rdb-pc.dtsi
b/arch/powerpc/dts/p2020rdb-pc.dtsi
new file mode 100644
index 00..0d2acc746e
--- /dev/null
+++ b/arch/powerpc/dts/p2020rdb-pc.dtsi
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ {
+ mdio@24520 {
+ phy0: ethernet-phy@0 {
+ interrupts = <3 1 0 0>;
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy@1 {
+ interrupts = <2 1 0 0>;
+ reg = <0x1>;
+ };
+ };
+
+ mdio@25520 {
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ mdio@26520 {
+ status = "disabled";
+ };
+
+ enet0: ethernet@24000 {
+ phy-connection-type = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ enet1: ethernet@25000 {
+ tbi-handle = <>;
+ phy-handle = <>;
+ phy-connection-type = "sgmii";
+ };
+
+ enet2: ethernet@26000 {
+ phy-handle = <>;
+ phy-connection-type = "rgmii-id";
+ };
+};
diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts
b/arch/powerpc/dts/p2020rdb-pc_36b.dts
index 04b2519e1a..6d983b7d71 100644
--- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
@@ -37,4 +37,5 @@
};
};
+/include/ "p2020rdb-pc.dtsi"
/include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/pq3-etsec1-0.dtsi
b/arch/powerpc/dts/pq3-etsec1-0.dtsi
new file mode 100644
index 00..8800243f34
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-0.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ fsl,magic-packet;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
+};
+
+mdio@24520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x24520 0x20>;
+};
diff --git a/arch/powerpc/dts/pq3-etsec1-1.dtsi
b/arch/powerpc/dts/pq3-etsec1-1.dtsi
new file mode 100644
index 00..2bc62d1a57
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-1.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
+ *
+ * Copyright 2011-2012
[PATCHv6 13/18] dts: powerpc: p1010rdb: Add eTSEC DT nodes
From: Hou Zhiqiang
P1010RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII PHY AR8033
eTSEC2: Connected to SGMII PHY AR8033
eTSEC3: Connected to SGMII PHY AR8033
Signed-off-by: Hou Zhiqiang
---
V6:
- No change.
arch/powerpc/dts/p1010rdb-pa.dts | 1 +
arch/powerpc/dts/p1010rdb-pa_36b.dts | 1 +
arch/powerpc/dts/p1010rdb.dtsi | 50
arch/powerpc/dts/p1010si-post.dtsi | 25 ++
4 files changed, 77 insertions(+)
diff --git a/arch/powerpc/dts/p1010rdb-pa.dts b/arch/powerpc/dts/p1010rdb-pa.dts
index c66c4923ac..360d254d91 100644
--- a/arch/powerpc/dts/p1010rdb-pa.dts
+++ b/arch/powerpc/dts/p1010rdb-pa.dts
@@ -15,3 +15,4 @@
};
/include/ "p1010si-post.dtsi"
+/include/ "p1010rdb.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb-pa_36b.dts
b/arch/powerpc/dts/p1010rdb-pa_36b.dts
index b943de7cbb..062086a8c0 100644
--- a/arch/powerpc/dts/p1010rdb-pa_36b.dts
+++ b/arch/powerpc/dts/p1010rdb-pa_36b.dts
@@ -15,3 +15,4 @@
};
/include/ "p1010si-post.dtsi"
+/include/ "p1010rdb.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb.dtsi b/arch/powerpc/dts/p1010rdb.dtsi
index 4f58ee2446..5964270878 100644
--- a/arch/powerpc/dts/p1010rdb.dtsi
+++ b/arch/powerpc/dts/p1010rdb.dtsi
@@ -5,6 +5,56 @@
* Copyright 2020 NXP
*/
{
+ mdio@24000 {
+ phy0: ethernet-phy@0 {
+ reg = <0x1>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <0x0>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ tbi-phy@3 {
+ device_type = "tbi-phy";
+ reg = <0x3>;
+ };
+ };
+
+ mdio@25000 {
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ mdio@26000 {
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet0: ethernet@b {
+ phy-handle = <>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ enet1: ethernet@b1000 {
+ phy-handle = <>;
+ tbi-handle = <>;
+ phy-connection-type = "sgmii";
+ };
+
+ enet2: ethernet@b2000 {
+ phy-handle = <>;
+ tbi-handle = <>;
+ phy-connection-type = "sgmii";
+ };
+
i2c@3000 {
rtc@68 {
compatible = "pericom,pt7c4338";
diff --git a/arch/powerpc/dts/p1010si-post.dtsi
b/arch/powerpc/dts/p1010si-post.dtsi
index 0289441381..f825208056 100644
--- a/arch/powerpc/dts/p1010si-post.dtsi
+++ b/arch/powerpc/dts/p1010si-post.dtsi
@@ -25,6 +25,31 @@
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec2-0.dtsi"
+ enet0: ethernet@b {
+ queue-group@b {
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ };
+ };
+
+/include/ "pq3-etsec2-1.dtsi"
+ enet1: ethernet@b1000 {
+ queue-group@b1000 {
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ };
+ };
+
+/include/ "pq3-etsec2-2.dtsi"
+ enet2: ethernet@b2000 {
+ queue-group@b2000 {
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ };
+
+ };
};
/* controller at 0x9000 */
--
2.17.1
[PATCHv6 15/18] configs: P1010RDB: Enable DM_ETH config
From: Hou Zhiqiang Enable the DM_ETH and DM_MDIO config. Signed-off-by: Hou Zhiqiang --- V6: - No change. configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PA_NAND_defconfig | 2 ++ configs/P1010RDB-PA_NOR_defconfig| 2 ++ configs/P1010RDB-PA_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PB_NAND_defconfig | 2 ++ configs/P1010RDB-PB_NOR_defconfig| 2 ++ configs/P1010RDB-PB_SDCARD_defconfig | 2 ++ configs/P1010RDB-PB_SPIFLASH_defconfig | 2 ++ 16 files changed, 32 insertions(+) diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index b77a5d056c..8179992d93 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -73,8 +73,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index 1ea7e3e641..fc011e3e6e 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -55,8 +55,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 7b6b70f37b..5c5c24eb68 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -67,8 +67,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 4bc60f148a..6a25c16d39 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -69,8 +69,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index ea9f905807..7464e123bb 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -72,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index f8093c17d7..4e928978d5 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -54,8 +54,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index e0a75a1a82..36c7cf0c8e 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -66,8 +66,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index c8212d7800..0855944b04 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -68,8 +68,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index e109e9cf67..592c092031 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -73,8 +73,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y
[PATCHv6 14/18] powerpc: p1010rdb: Compile legacy ethernet init function when no DM_ETH
From: Hou Zhiqiang
The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
board/freescale/p1010rdb/p1010rdb.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/p1010rdb/p1010rdb.c
b/board/freescale/p1010rdb/p1010rdb.c
index accf2f24e5..4c3a03e7cd 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -484,6 +484,7 @@ int checkboard(void)
return 0;
}
+#ifndef CONFIG_DM_ETH
int board_eth_init(struct bd_info *bis)
{
#ifdef CONFIG_TSEC_ENET
@@ -524,6 +525,7 @@ int board_eth_init(struct bd_info *bis)
return pci_eth_init(bis);
}
+#endif
#if defined(CONFIG_OF_BOARD_SETUP)
void fdt_del_flexcan(void *blob)
--
2.17.1
[PATCHv6 18/18] configs: enable DM_MDIO for LS1021A-TWR and LS1021A-TSN
From: Vladimir Oltean The tsec driver now requires DM_MDIO when DM_ETH is enabled. To avoid build errors, enable DM_MDIO in these boards' configs before we actually add DM_MDIO support to tsec. Signed-off-by: Vladimir Oltean Signed-off-by: Hou Zhiqiang --- V6: - No code change, just move it to the tail of this series. configs/ls1021atsn_qspi_defconfig | 1 + configs/ls1021atsn_sdcard_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig| 1 + configs/ls1021atwr_nor_defconfig| 1 + configs/ls1021atwr_nor_lpuart_defconfig | 1 + configs/ls1021atwr_qspi_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig| 1 + 9 files changed, 9 insertions(+) diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index 06a139be1a..43f9e511cc 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -44,6 +44,7 @@ CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_TSEC_ENET=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index 8046f6452f..49197eeed4 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -55,6 +55,7 @@ CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_TSEC_ENET=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 30511dd425..d62dcfa751 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -46,6 +46,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 60622b1879..f49a882e0a 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -48,6 +48,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index fa0a118eb0..e75c7b43d2 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -50,6 +50,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 30c107924f..767c364b3e 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -49,6 +49,7 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 0911b9c151..5b3ac2a348 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -61,6 +61,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index eaf5b98f9f..5cc0b90aa7 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -63,6 +63,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 2743848ac9..e3e64f9790 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -- 2.17.1
[PATCHv6 17/18] configs: P2020RDB: Enable DM_ETH config
From: Hou Zhiqiang Enable the DM_ETH and DM_MDIO config. On P2020RDB, the eTSEC1 is connecting with a switch VSC7385, so also enable the fixed PHY support. Signed-off-by: Hou Zhiqiang Reviewed-by: Vladimir Oltean --- V6: - No change. configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_defconfig | 3 +++ configs/P2020RDB-PC_NAND_defconfig | 3 +++ configs/P2020RDB-PC_SDCARD_defconfig | 3 +++ configs/P2020RDB-PC_SPIFLASH_defconfig | 3 +++ configs/P2020RDB-PC_defconfig| 3 +++ 8 files changed, 24 insertions(+) diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 1e0bd202ea..ba4dd7fe1d 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -67,6 +67,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -78,8 +79,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index df57340c7d..ef98374ea3 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -62,6 +62,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -73,8 +74,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 1b250214e7..e1ebb1f896 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -64,6 +64,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -75,8 +76,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index e5573cd22a..4a7d726e2f 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -51,6 +51,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -62,8 +63,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 6232b18aa9..5d8d531f69 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -66,6 +66,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -77,8 +78,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 4d3b872f72..61b1c1f8b4 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -72,8 +73,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 7b97d9186a..f649c494e1 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -63,6 +63,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000
[PATCHv6 12/18] configs: P1020RDB: Enable DM_ETH config
From: Hou Zhiqiang Enable the DM_ETH and DM_MDIO config. On P1020RDB, the eTSEC1 is connecting with a switch VSC7385, so also enable the fixed PHY support. Signed-off-by: Hou Zhiqiang --- V6: - No change. configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_defconfig | 3 +++ configs/P1020RDB-PC_NAND_defconfig | 3 +++ configs/P1020RDB-PC_SDCARD_defconfig | 3 +++ configs/P1020RDB-PC_SPIFLASH_defconfig | 3 +++ configs/P1020RDB-PC_defconfig| 3 +++ configs/P1020RDB-PD_NAND_defconfig | 3 +++ configs/P1020RDB-PD_SDCARD_defconfig | 3 +++ configs/P1020RDB-PD_SPIFLASH_defconfig | 3 +++ configs/P1020RDB-PD_defconfig| 3 +++ 12 files changed, 36 insertions(+) diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 6db4bd7d52..e69595102a 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -62,6 +62,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -73,8 +74,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index cacce4d5ec..974bcb15c7 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -57,6 +57,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -68,8 +69,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 3c9e491b08..f3e599869d 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -59,6 +59,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -70,8 +71,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 5c68ea060a..445e796afb 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -46,6 +46,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -57,8 +58,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 9883204787..43fdbdffe4 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -72,8 +73,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 22ba4f6501..282453a290 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -56,6 +56,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -67,8 +68,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 250b56d216..0a7fa606bf 100644 ---
[PATCHv6 04/18] net: tsec: convert to use DM_MDIO when DM_ETH enabled
From: Hou Zhiqiang
For the platforms on which the eTSEC driver uses DM_ETH, convert its
MDIO controller code to also use DM_MDIO.
Note that for handling the TBI PHY (the MAC PCS for SGMII), we still
don't register a udevice for it, since we can drive it locally and there
is no point in doing otherwise.
Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang
---
V6:
- No change.
drivers/net/tsec.c | 43 ++-
1 file changed, 10 insertions(+), 33 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 5d12e4b775..9d68c6f829 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
@@ -681,8 +682,12 @@ static int init_phy(struct tsec_private *priv)
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
tsec_configure_serdes(priv);
+#ifdef CONFIG_DM_ETH
+ phydev = dm_eth_phy_connect(priv->dev);
+#else
phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
priv->interface);
+#endif
if (!phydev)
return 0;
@@ -789,14 +794,17 @@ int tsec_standard_init(struct bd_info *bis)
return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
}
#else /* CONFIG_DM_ETH */
+
+#ifndef CONFIG_DM_MDIO
+#error "TSEC with DM_ETH also requires DM_MDIO"
+#endif
+
int tsec_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct tsec_private *priv = dev_get_priv(dev);
- struct tsec_mii_mng __iomem *ext_phyregs_mii;
struct ofnode_phandle_args phandle_args;
u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
- struct fsl_pq_mdio_info mdio_info;
const char *phy_mode;
fdt_addr_t reg;
ofnode parent;
@@ -805,31 +813,6 @@ int tsec_probe(struct udevice *dev)
pdata->iobase = (phys_addr_t)dev_read_addr(dev);
priv->regs = dev_remap_addr(dev);
- if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
- _args)) {
- printf("phy-handle does not exist under tsec %s\n", dev->name);
- return -ENOENT;
- } else {
- int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
-
- priv->phyaddr = reg;
- }
-
- parent = ofnode_get_parent(phandle_args.node);
- if (!ofnode_valid(parent)) {
- printf("No parent node for PHY?\n");
- return -ENOENT;
- }
-
- reg = ofnode_get_addr_index(parent, 0);
- if (reg == FDT_ADDR_T_NONE) {
- printf("No 'reg' property of MII for external PHY\n");
- return -ENOENT;
- }
-
- ext_phyregs_mii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0,
- MAP_NOCACHE);
-
ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
_args);
if (ret == 0) {
@@ -867,12 +850,6 @@ int tsec_probe(struct udevice *dev)
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
priv->flags |= TSEC_SGMII;
- mdio_info.regs = ext_phyregs_mii;
- mdio_info.name = (char *)dev->name;
- ret = fsl_pq_mdio_init(NULL, _info);
- if (ret)
- return ret;
-
/* Reset the MAC */
setbits_be32(>regs->maccfg1, MACCFG1_SOFT_RESET);
udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
--
2.17.1
[PATCHv6 10/18] dts: powerpc: p1020rdb: Add eTSEC DT nodes
From: Hou Zhiqiang
P1020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
arch/powerpc/dts/p1020-post.dtsi| 20 -
arch/powerpc/dts/p1020rdb-pc.dts| 1 +
arch/powerpc/dts/p1020rdb-pc.dtsi | 55 +
arch/powerpc/dts/p1020rdb-pc_36b.dts| 1 +
arch/powerpc/dts/p1020rdb-pd.dts| 45
arch/powerpc/dts/pq3-etsec2-0.dtsi | 35
arch/powerpc/dts/pq3-etsec2-1.dtsi | 35
arch/powerpc/dts/pq3-etsec2-2.dtsi | 35
arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi | 16 +++
arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi | 16 +++
arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi | 16 +++
11 files changed, 273 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/dts/p1020rdb-pc.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-0.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-1.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-2.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi
diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi
index 1dce8e86e9..c73539ad5c 100644
--- a/arch/powerpc/dts/p1020-post.dtsi
+++ b/arch/powerpc/dts/p1020-post.dtsi
@@ -44,10 +44,26 @@
clock-frequency = <0>;
};
- /include/ "pq3-i2c-0.dtsi"
- /include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec2-0.dtsi"
+ enet0: enet0_grp2: ethernet@b {
+ };
+
+/include/ "pq3-etsec2-1.dtsi"
+ enet1: enet1_grp2: ethernet@b1000 {
+ };
+
+/include/ "pq3-etsec2-2.dtsi"
+ enet2: enet2_grp2: ethernet@b2000 {
+ };
};
+/include/ "pq3-etsec2-grp2-0.dtsi"
+/include/ "pq3-etsec2-grp2-1.dtsi"
+/include/ "pq3-etsec2-grp2-2.dtsi"
+
/* PCIe controller base address 0x9000 */
{
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts
index 7ebaa619df..715330dc50 100644
--- a/arch/powerpc/dts/p1020rdb-pc.dts
+++ b/arch/powerpc/dts/p1020rdb-pc.dts
@@ -32,4 +32,5 @@
};
};
+/include/ "p1020rdb-pc.dtsi"
/include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pc.dtsi
b/arch/powerpc/dts/p1020rdb-pc.dtsi
new file mode 100644
index 00..6bf424fd3f
--- /dev/null
+++ b/arch/powerpc/dts/p1020rdb-pc.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ {
+ mdio@24000 {
+ phy0: ethernet-phy@0 {
+ interrupt-parent = <>;
+ interrupts = <3 1 0 0>;
+ reg = <0x0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ interrupt-parent = <>;
+ interrupts = <2 1 0 0>;
+ reg = <0x1>;
+ };
+
+ tbi0: tbi-phy@11 {
+ device_type = "tbi-phy";
+ reg = <0x11>;
+ };
+ };
+
+ mdio@25000 {
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet0: ethernet@b {
+ phy-connection-type = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+
+ };
+
+ enet1: ethernet@b1000 {
+ phy-handle = <>;
+ tbi-handle = <>;
+ phy-connection-type = "sgmii";
+ };
+
+ enet2: ethernet@b2000 {
+ phy-handle = <>;
+ phy-connection-type = "rgmii-id";
+ };
+};
diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts
b/arch/powerpc/dts/p1020rdb-pc_36b.dts
index c0e5ef4cf4..7680b7c7e1 100644
--- a/arch/powerpc/dts/p1020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts
@@ -32,4 +32,5 @@
};
};
+/include/ "p1020rdb-pc.dtsi"
/include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts
index 21174a09be..e0e8993dab 100644
--- a/arch/powerpc/dts/p1020rdb-pd.dts
+++ b/arch/powerpc/dts/p1020rdb-pd.dts
@@ -17,6 +17,51 @@
soc: soc@ffe0 {
ranges = <0x0 0x0 0xffe0 0x10>;
+
+ mdio@24000 {
+ phy0: ethernet-phy@0 {
+ interrupts = <3 1 0
[PATCHv6 09/18] configs: p1_p2_rdb: Add the default address of vsc7385 firmware
From: Hou Zhiqiang Add the environment 'vscfw_addr' to assign a default address for vsc7385 firmware uploading. Signed-off-by: Hou Zhiqiang --- V6: - No change. include/configs/p1_p2_rdb_pc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 1b74177b2f..a159285c98 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -451,6 +451,7 @@ /* Vsc7385 switch */ #ifdef CONFIG_VSC7385_ENET +#define __VSCFW_ADDR "vscfw_addr=ef00" #define CONFIG_SYS_VSC7385_BASE0xffb0 #ifdef CONFIG_PHYS_64BIT @@ -809,6 +810,7 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset "ramdisk_size=12\0"\ "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ +__stringify(__VSCFW_ADDR)"\0" \ __stringify(__NOR_RST_CMD)"\0" \ __stringify(__SPI_RST_CMD)"\0" \ __stringify(__SD_RST_CMD)"\0" \ -- 2.17.1
[PATCHv6 11/18] powerpc: p1_p2_rdb: Don't compile board_eth_init() when DM_ETH enabled
From: Hou Zhiqiang
The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index d0562ba95a..ba12bea92f 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -359,6 +359,7 @@ int board_early_init_r(void)
return 0;
}
+#ifndef CONFIG_DM_ETH
int board_eth_init(struct bd_info *bis)
{
struct fsl_pq_mdio_info mdio_info;
@@ -406,6 +407,7 @@ int board_eth_init(struct bd_info *bis)
return pci_eth_init(bis);
}
+#endif
#if defined(CONFIG_QE) && \
(defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
--
2.17.1
[PATCHv6 07/18] powerpc: mpc8xxx: Don't compile cpu_eth_init() when DM_ETH enabled
From: Hou Zhiqiang
The cpu_eth_init() is only used by the legacy ethernet driver framework.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
arch/powerpc/cpu/mpc8xxx/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 2b24e755fa..67857c3760 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -347,6 +347,7 @@ int fixup_cpu(void)
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
+#ifndef CONFIG_DM_ETH
int cpu_eth_init(struct bd_info *bis)
{
#if defined(CONFIG_ETHER_ON_FCC)
@@ -370,3 +371,4 @@ int cpu_eth_init(struct bd_info *bis)
#endif
return 0;
}
+#endif
--
2.17.1
[PATCHv6 01/18] phy: make phy_connect_fixed work with a null mdio bus
From: Vladimir Oltean
It is utterly pointless to require an MDIO bus pointer for a fixed PHY
device. The fixed.c implementation does not require it, only
phy_device_create. Fix that.
Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang
Reviewed-by: Hou Zhiqiang
---
V6:
- No change.
drivers/net/phy/phy.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 67789897c2..9587e6b9fa 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -664,7 +664,7 @@ static struct phy_device *phy_device_create(struct mii_dev
*bus, int addr,
dev = malloc(sizeof(*dev));
if (!dev) {
printf("Failed to allocate PHY device for %s:%d\n",
- bus->name, addr);
+ bus ? bus->name : "(null bus)", addr);
return NULL;
}
@@ -692,7 +692,7 @@ static struct phy_device *phy_device_create(struct mii_dev
*bus, int addr,
return NULL;
}
- if (addr >= 0 && addr < PHY_MAX_ADDR)
+ if (addr >= 0 && addr < PHY_MAX_ADDR && phy_id != PHY_FIXED_ID)
bus->phymap[addr] = dev;
return dev;
--
2.17.1
[PATCHv6 08/18] fsl: p1_p2_rdb: Move vsc7835 firmware uploading to board_early_init_r()
From: Hou Zhiqiang
Move vsc7835 firmware uploading to board_early_init_r(), so that
the switch also can work in DM eTSEC driver.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 35 +++--
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 7c703b354f..d0562ba95a 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -316,6 +316,10 @@ int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
+#ifdef CONFIG_VSC7385_ENET
+ unsigned int vscfw_addr;
+ char *tmp;
+#endif
/*
* Remap Boot flash region to caching-inhibited
@@ -338,6 +342,20 @@ int board_early_init_r(void)
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
+
+#ifdef CONFIG_VSC7385_ENET
+ /* If a VSC7385 microcode image is present, then upload it. */
+ tmp = env_get("vscfw_addr");
+ if (tmp) {
+ vscfw_addr = simple_strtoul(tmp, NULL, 16);
+ printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
+ if (vsc7385_upload_firmware((void *)vscfw_addr,
+ CONFIG_VSC7385_IMAGE_SIZE))
+ puts("Failure uploading VSC7385 microcode.\n");
+ } else {
+ puts("No address specified for VSC7385 microcode.\n");
+ }
+#endif
return 0;
}
@@ -348,10 +366,6 @@ int board_eth_init(struct bd_info *bis)
ccsr_gur_t *gur __attribute__((unused)) =
(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int num = 0;
-#ifdef CONFIG_VSC7385_ENET
- char *tmp;
- unsigned int vscfw_addr;
-#endif
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
@@ -375,19 +389,6 @@ int board_eth_init(struct bd_info *bis)
return 0;
}
-#ifdef CONFIG_VSC7385_ENET
- /* If a VSC7385 microcode image is present, then upload it. */
- tmp = env_get("vscfw_addr");
- if (tmp) {
- vscfw_addr = simple_strtoul(tmp, NULL, 16);
- printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
- if (vsc7385_upload_firmware((void *) vscfw_addr,
- CONFIG_VSC7385_IMAGE_SIZE))
- puts("Failure uploading VSC7385 microcode.\n");
- } else
- puts("No address specified for VSC7385 microcode.\n");
-#endif
-
mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
mdio_info.name = DEFAULT_MII_NAME;
--
2.17.1
[PATCHv6 05/18] net: tsec: Add fixed-link PHY support
From: Hou Zhiqiang The info of fixed-link PHY is described in DT node instead of getting from MII, so detect the fixed-link PHY DT node first, if it doesn't exist then probe the MII. Signed-off-by: Vladimir Oltean Signed-off-by: Hou Zhiqiang --- V6: - No change. drivers/net/tsec.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 9d68c6f829..1e04a89102 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -683,7 +683,10 @@ static int init_phy(struct tsec_private *priv) tsec_configure_serdes(priv); #ifdef CONFIG_DM_ETH - phydev = dm_eth_phy_connect(priv->dev); + if (ofnode_valid(ofnode_find_subnode(priv->dev->node, "fixed-link"))) + phydev = phy_connect(NULL, 0, priv->dev, priv->interface); + else + phydev = dm_eth_phy_connect(priv->dev); #else phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev, priv->interface); -- 2.17.1
[PATCHv6 03/18] net: fsl_mdio: Correct the MII management register block address
From: Hou Zhiqiang
The MII management register block offset is different between
gianfar and etsec2 compatible devices, this patch is to fix
this issue by adding driver data for different compatible
string.
Fixes: 2932c5a802a9 ("net: tsec: fsl_mdio: add DM MDIO support")
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
drivers/net/fsl_mdio.c | 28 ++--
include/fsl_mdio.h | 4
2 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index ae96ce4c7b..77f1a96a2e 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#ifdef CONFIG_DM_MDIO
struct tsec_mdio_priv {
@@ -190,17 +191,30 @@ static const struct mdio_ops tsec_mdio_ops = {
.reset = tsec_mdio_reset,
};
+static struct fsl_pq_mdio_data etsec2_data = {
+ .mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
+};
+
+static struct fsl_pq_mdio_data gianfar_data = {
+ .mdio_regs_off = 0x0,
+};
+
+static struct fsl_pq_mdio_data fman_data = {
+ .mdio_regs_off = 0x0,
+};
+
static const struct udevice_id tsec_mdio_ids[] = {
- { .compatible = "fsl,gianfar-tbi" },
- { .compatible = "fsl,gianfar-mdio" },
- { .compatible = "fsl,etsec2-tbi" },
- { .compatible = "fsl,etsec2-mdio" },
- { .compatible = "fsl,fman-mdio" },
+ { .compatible = "fsl,gianfar-tbi", .data = (ulong)_data },
+ { .compatible = "fsl,gianfar-mdio", .data = (ulong)_data },
+ { .compatible = "fsl,etsec2-tbi", .data = (ulong)_data },
+ { .compatible = "fsl,etsec2-mdio", .data = (ulong)_data },
+ { .compatible = "fsl,fman-mdio", .data = (ulong)_data },
{}
};
static int tsec_mdio_probe(struct udevice *dev)
{
+ struct fsl_pq_mdio_data *data;
struct tsec_mdio_priv *priv = (dev) ? dev_get_priv(dev) : NULL;
struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
NULL;
@@ -213,7 +227,9 @@ static int tsec_mdio_probe(struct udevice *dev)
printf("dev_get_priv(dev %p) = NULL\n", dev);
return -1;
}
- priv->regs = dev_remap_addr(dev);
+
+ data = (struct fsl_pq_mdio_data *)dev_get_driver_data(dev);
+ priv->regs = dev_remap_addr(dev) + data->mdio_regs_off;
debug("%s priv %p @ regs %p, pdata %p\n", __func__,
priv, priv->regs, pdata);
diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h
index 41cb73717b..b6c02cf342 100644
--- a/include/fsl_mdio.h
+++ b/include/fsl_mdio.h
@@ -55,6 +55,10 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int
dev_addr,
int regnum);
int memac_mdio_reset(struct mii_dev *bus);
+struct fsl_pq_mdio_data {
+ u32 mdio_regs_off;
+};
+
struct fsl_pq_mdio_info {
struct tsec_mii_mng __iomem *regs;
char *name;
--
2.17.1
[PATCHv6 02/18] net: fsl_mdio: Change to use virtual address
From: Hou Zhiqiang
Use virtual address to access the MII block registers instead
of physical address.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
drivers/net/fsl_mdio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index d2edd1751c..ae96ce4c7b 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -213,7 +213,7 @@ static int tsec_mdio_probe(struct udevice *dev)
printf("dev_get_priv(dev %p) = NULL\n", dev);
return -1;
}
- priv->regs = (void *)(uintptr_t)dev_read_addr(dev);
+ priv->regs = dev_remap_addr(dev);
debug("%s priv %p @ regs %p, pdata %p\n", __func__,
priv, priv->regs, pdata);
--
2.17.1
[PATCHv6 06/18] net: tsec: Add the compatible string "gianfar" support
From: Hou Zhiqiang
Add compatible string "gianfar" support and update the
device-tree-bindings doc.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
doc/device-tree-bindings/net/fsl-tsec-phy.txt | 2 +-
drivers/net/tsec.c| 16 ++--
include/tsec.h| 4
3 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/doc/device-tree-bindings/net/fsl-tsec-phy.txt
b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
index 8e8574bc97..a44c5fd9d9 100644
--- a/doc/device-tree-bindings/net/fsl-tsec-phy.txt
+++ b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
@@ -2,7 +2,7 @@
Properties:
- - compatible : Should be "fsl,etsec2"
+ - compatible : Should be "fsl,etsec2" or "gianfar"
- reg : Offset and length of the register set for the device
- phy-handle : See ethernet.txt file in the same directory.
- phy-connection-type : See ethernet.txt file in the same directory. This
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 1e04a89102..e59a107ea8 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -808,11 +808,14 @@ int tsec_probe(struct udevice *dev)
struct tsec_private *priv = dev_get_priv(dev);
struct ofnode_phandle_args phandle_args;
u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
+ struct tsec_data *data;
const char *phy_mode;
fdt_addr_t reg;
ofnode parent;
int ret;
+ data = (struct tsec_data *)dev_get_driver_data(dev);
+
pdata->iobase = (phys_addr_t)dev_read_addr(dev);
priv->regs = dev_remap_addr(dev);
@@ -833,7 +836,7 @@ int tsec_probe(struct udevice *dev)
return -ENOENT;
}
- priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET,
+ priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off,
0, MAP_NOCACHE);
}
@@ -885,8 +888,17 @@ static const struct eth_ops tsec_ops = {
.mcast = tsec_mcast_addr,
};
+static struct tsec_data etsec2_data = {
+ .mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
+};
+
+static struct tsec_data gianfar_data = {
+ .mdio_regs_off = 0x0,
+};
+
static const struct udevice_id tsec_ids[] = {
- { .compatible = "fsl,etsec2" },
+ { .compatible = "fsl,etsec2", .data = (ulong)_data },
+ { .compatible = "gianfar", .data = (ulong)_data },
{ }
};
diff --git a/include/tsec.h b/include/tsec.h
index 43255e538f..5433cfd966 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -394,6 +394,10 @@ struct tsec {
#define TX_BUF_CNT 2
+struct tsec_data {
+ u32 mdio_regs_off;
+};
+
struct tsec_private {
struct txbd8 __iomem txbd[TX_BUF_CNT];
struct rxbd8 __iomem rxbd[PKTBUFSRX];
--
2.17.1
[PATCHv6 00/18] powerpc: convert p1010, p1020 and p2020 RDB boards to DM_ETH
From: Hou Zhiqiang This patchset is to convert P1010, P1020 and P2020 RDB boards to DM_ETH. V5: Merged the following thread: https://patchwork.ozlabs.org/project/uboot/list/?series=174343=both=* Hou Zhiqiang (16): net: fsl_mdio: Change to use virtual address net: fsl_mdio: Correct the MII management register block address net: tsec: convert to use DM_MDIO when DM_ETH enabled net: tsec: Add fixed-link PHY support net: tsec: Add the compatible string "gianfar" support powerpc: mpc8xxx: Don't compile cpu_eth_init() when DM_ETH enabled fsl: p1_p2_rdb: Move vsc7835 firmware uploading to board_early_init_r() configs: p1_p2_rdb: Add the default address of vsc7385 firmware dts: powerpc: p1020rdb: Add eTSEC DT nodes powerpc: p1_p2_rdb: Don't compile board_eth_init() when DM_ETH enabled configs: P1020RDB: Enable DM_ETH config dts: powerpc: p1010rdb: Add eTSEC DT nodes powerpc: p1010rdb: Compile legacy ethernet init function when no DM_ETH configs: P1010RDB: Enable DM_ETH config dts: powerpc: p2020rdb: Add eTSEC DT nodes configs: P2020RDB: Enable DM_ETH config Vladimir Oltean (2): phy: make phy_connect_fixed work with a null mdio bus configs: enable DM_MDIO for LS1021A-TWR and LS1021A-TSN arch/powerpc/cpu/mpc8xxx/cpu.c| 2 + arch/powerpc/dts/p1010rdb-pa.dts | 1 + arch/powerpc/dts/p1010rdb-pa_36b.dts | 1 + arch/powerpc/dts/p1010rdb.dtsi| 50 +++ arch/powerpc/dts/p1010si-post.dtsi| 25 arch/powerpc/dts/p1020-post.dtsi | 20 +- arch/powerpc/dts/p1020rdb-pc.dts | 1 + arch/powerpc/dts/p1020rdb-pc.dtsi | 55 arch/powerpc/dts/p1020rdb-pc_36b.dts | 1 + arch/powerpc/dts/p1020rdb-pd.dts | 45 ++ arch/powerpc/dts/p2020-post.dtsi | 8 ++- arch/powerpc/dts/p2020rdb-pc.dts | 1 + arch/powerpc/dts/p2020rdb-pc.dtsi | 50 +++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 1 + arch/powerpc/dts/pq3-etsec1-0.dtsi| 28 + arch/powerpc/dts/pq3-etsec1-1.dtsi| 28 + arch/powerpc/dts/pq3-etsec1-2.dtsi| 28 + arch/powerpc/dts/pq3-etsec1-3.dtsi| 28 + arch/powerpc/dts/pq3-etsec2-0.dtsi| 35 +++ arch/powerpc/dts/pq3-etsec2-1.dtsi| 35 +++ arch/powerpc/dts/pq3-etsec2-2.dtsi| 35 +++ arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi | 16 + arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi | 16 + arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi | 16 + board/freescale/p1010rdb/p1010rdb.c | 2 + board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 37 ++- configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig| 2 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 + configs/P1010RDB-PA_NAND_defconfig| 2 + configs/P1010RDB-PA_NOR_defconfig | 2 + configs/P1010RDB-PA_SDCARD_defconfig | 2 + configs/P1010RDB-PA_SPIFLASH_defconfig| 2 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig| 2 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 + configs/P1010RDB-PB_NAND_defconfig| 2 + configs/P1010RDB-PB_NOR_defconfig | 2 + configs/P1010RDB-PB_SDCARD_defconfig | 2 + configs/P1010RDB-PB_SPIFLASH_defconfig| 2 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig| 3 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 3 + configs/P1020RDB-PC_36BIT_defconfig | 3 + configs/P1020RDB-PC_NAND_defconfig| 3 + configs/P1020RDB-PC_SDCARD_defconfig | 3 + configs/P1020RDB-PC_SPIFLASH_defconfig| 3 + configs/P1020RDB-PC_defconfig | 3 + configs/P1020RDB-PD_NAND_defconfig| 3 + configs/P1020RDB-PD_SDCARD_defconfig | 3 + configs/P1020RDB-PD_SPIFLASH_defconfig| 3 + configs/P1020RDB-PD_defconfig | 3 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig| 3 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 3 + configs/P2020RDB-PC_36BIT_defconfig | 3 + configs/P2020RDB-PC_NAND_defconfig| 3 + configs/P2020RDB-PC_SDCARD_defconfig | 3 + configs/P2020RDB-PC_SPIFLASH_defconfig| 3 + configs/P2020RDB-PC_defconfig | 3 + configs/ls1021atsn_qspi_defconfig | 1 + configs/ls1021atsn_sdcard_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_nor_defconfig | 1 +
[PATCHv6 18/18] configs: enable DM_MDIO for LS1021A-TWR and LS1021A-TSN
From: Vladimir Oltean The tsec driver now requires DM_MDIO when DM_ETH is enabled. To avoid build errors, enable DM_MDIO in these boards' configs before we actually add DM_MDIO support to tsec. Signed-off-by: Vladimir Oltean Signed-off-by: Hou Zhiqiang --- V6: - No code change, just move it to the tail of this series. configs/ls1021atsn_qspi_defconfig | 1 + configs/ls1021atsn_sdcard_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig| 1 + configs/ls1021atwr_nor_defconfig| 1 + configs/ls1021atwr_nor_lpuart_defconfig | 1 + configs/ls1021atwr_qspi_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig| 1 + 9 files changed, 9 insertions(+) diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index 06a139be1a..43f9e511cc 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -44,6 +44,7 @@ CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_TSEC_ENET=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index 8046f6452f..49197eeed4 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -55,6 +55,7 @@ CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_TSEC_ENET=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 30511dd425..d62dcfa751 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -46,6 +46,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 60622b1879..f49a882e0a 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -48,6 +48,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index fa0a118eb0..e75c7b43d2 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -50,6 +50,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 30c107924f..767c364b3e 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -49,6 +49,7 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 0911b9c151..5b3ac2a348 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -61,6 +61,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index eaf5b98f9f..5cc0b90aa7 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -63,6 +63,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 2743848ac9..e3e64f9790 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -- 2.17.1
[PATCHv6 16/18] dts: powerpc: p2020rdb: Add eTSEC DT nodes
From: Hou Zhiqiang
P2020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang
---
V6:
- No change.
arch/powerpc/dts/p2020-post.dtsi | 8 +++--
arch/powerpc/dts/p2020rdb-pc.dts | 1 +
arch/powerpc/dts/p2020rdb-pc.dtsi| 50
arch/powerpc/dts/p2020rdb-pc_36b.dts | 1 +
arch/powerpc/dts/pq3-etsec1-0.dtsi | 28
arch/powerpc/dts/pq3-etsec1-1.dtsi | 28
arch/powerpc/dts/pq3-etsec1-2.dtsi | 28
arch/powerpc/dts/pq3-etsec1-3.dtsi | 28
8 files changed, 170 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/dts/p2020rdb-pc.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-0.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-1.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-2.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-3.dtsi
diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index 4ed093dad4..11945295d1 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -38,8 +38,12 @@
clock-frequency = <0>;
};
- /include/ "pq3-i2c-0.dtsi"
- /include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec1-0.dtsi"
+/include/ "pq3-etsec1-1.dtsi"
+/include/ "pq3-etsec1-2.dtsi"
};
/* PCIe controller base address 0x8000 */
diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts
index 08befd4c59..f3f6be1080 100644
--- a/arch/powerpc/dts/p2020rdb-pc.dts
+++ b/arch/powerpc/dts/p2020rdb-pc.dts
@@ -37,4 +37,5 @@
};
};
+/include/ "p2020rdb-pc.dtsi"
/include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/p2020rdb-pc.dtsi
b/arch/powerpc/dts/p2020rdb-pc.dtsi
new file mode 100644
index 00..0d2acc746e
--- /dev/null
+++ b/arch/powerpc/dts/p2020rdb-pc.dtsi
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ {
+ mdio@24520 {
+ phy0: ethernet-phy@0 {
+ interrupts = <3 1 0 0>;
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy@1 {
+ interrupts = <2 1 0 0>;
+ reg = <0x1>;
+ };
+ };
+
+ mdio@25520 {
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ mdio@26520 {
+ status = "disabled";
+ };
+
+ enet0: ethernet@24000 {
+ phy-connection-type = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ enet1: ethernet@25000 {
+ tbi-handle = <>;
+ phy-handle = <>;
+ phy-connection-type = "sgmii";
+ };
+
+ enet2: ethernet@26000 {
+ phy-handle = <>;
+ phy-connection-type = "rgmii-id";
+ };
+};
diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts
b/arch/powerpc/dts/p2020rdb-pc_36b.dts
index 04b2519e1a..6d983b7d71 100644
--- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
@@ -37,4 +37,5 @@
};
};
+/include/ "p2020rdb-pc.dtsi"
/include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/pq3-etsec1-0.dtsi
b/arch/powerpc/dts/pq3-etsec1-0.dtsi
new file mode 100644
index 00..8800243f34
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-0.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ fsl,magic-packet;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
+};
+
+mdio@24520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x24520 0x20>;
+};
diff --git a/arch/powerpc/dts/pq3-etsec1-1.dtsi
b/arch/powerpc/dts/pq3-etsec1-1.dtsi
new file mode 100644
index 00..2bc62d1a57
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-1.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
+ *
+ * Copyright 2011-2012
[PATCHv6 15/18] configs: P1010RDB: Enable DM_ETH config
From: Hou Zhiqiang Enable the DM_ETH and DM_MDIO config. Signed-off-by: Hou Zhiqiang --- V6: - No change. configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PA_NAND_defconfig | 2 ++ configs/P1010RDB-PA_NOR_defconfig| 2 ++ configs/P1010RDB-PA_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PB_NAND_defconfig | 2 ++ configs/P1010RDB-PB_NOR_defconfig| 2 ++ configs/P1010RDB-PB_SDCARD_defconfig | 2 ++ configs/P1010RDB-PB_SPIFLASH_defconfig | 2 ++ 16 files changed, 32 insertions(+) diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index b77a5d056c..8179992d93 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -73,8 +73,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index 1ea7e3e641..fc011e3e6e 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -55,8 +55,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 7b6b70f37b..5c5c24eb68 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -67,8 +67,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 4bc60f148a..6a25c16d39 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -69,8 +69,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index ea9f905807..7464e123bb 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -72,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index f8093c17d7..4e928978d5 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -54,8 +54,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index e0a75a1a82..36c7cf0c8e 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -66,8 +66,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index c8212d7800..0855944b04 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -68,8 +68,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index e109e9cf67..592c092031 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -73,8 +73,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y
[PATCHv6 17/18] configs: P2020RDB: Enable DM_ETH config
From: Hou Zhiqiang Enable the DM_ETH and DM_MDIO config. On P2020RDB, the eTSEC1 is connecting with a switch VSC7385, so also enable the fixed PHY support. Signed-off-by: Hou Zhiqiang Reviewed-by: Vladimir Oltean --- V6: - No change. configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_defconfig | 3 +++ configs/P2020RDB-PC_NAND_defconfig | 3 +++ configs/P2020RDB-PC_SDCARD_defconfig | 3 +++ configs/P2020RDB-PC_SPIFLASH_defconfig | 3 +++ configs/P2020RDB-PC_defconfig| 3 +++ 8 files changed, 24 insertions(+) diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 1e0bd202ea..ba4dd7fe1d 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -67,6 +67,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -78,8 +79,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index df57340c7d..ef98374ea3 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -62,6 +62,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -73,8 +74,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 1b250214e7..e1ebb1f896 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -64,6 +64,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -75,8 +76,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index e5573cd22a..4a7d726e2f 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -51,6 +51,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -62,8 +63,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 6232b18aa9..5d8d531f69 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -66,6 +66,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -77,8 +78,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 4d3b872f72..61b1c1f8b4 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -72,8 +73,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 7b97d9186a..f649c494e1 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -63,6 +63,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000
[PATCHv6 10/18] dts: powerpc: p1020rdb: Add eTSEC DT nodes
From: Hou Zhiqiang
P1020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
arch/powerpc/dts/p1020-post.dtsi| 20 -
arch/powerpc/dts/p1020rdb-pc.dts| 1 +
arch/powerpc/dts/p1020rdb-pc.dtsi | 55 +
arch/powerpc/dts/p1020rdb-pc_36b.dts| 1 +
arch/powerpc/dts/p1020rdb-pd.dts| 45
arch/powerpc/dts/pq3-etsec2-0.dtsi | 35
arch/powerpc/dts/pq3-etsec2-1.dtsi | 35
arch/powerpc/dts/pq3-etsec2-2.dtsi | 35
arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi | 16 +++
arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi | 16 +++
arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi | 16 +++
11 files changed, 273 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/dts/p1020rdb-pc.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-0.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-1.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-2.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi
diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi
index 1dce8e86e9..c73539ad5c 100644
--- a/arch/powerpc/dts/p1020-post.dtsi
+++ b/arch/powerpc/dts/p1020-post.dtsi
@@ -44,10 +44,26 @@
clock-frequency = <0>;
};
- /include/ "pq3-i2c-0.dtsi"
- /include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec2-0.dtsi"
+ enet0: enet0_grp2: ethernet@b {
+ };
+
+/include/ "pq3-etsec2-1.dtsi"
+ enet1: enet1_grp2: ethernet@b1000 {
+ };
+
+/include/ "pq3-etsec2-2.dtsi"
+ enet2: enet2_grp2: ethernet@b2000 {
+ };
};
+/include/ "pq3-etsec2-grp2-0.dtsi"
+/include/ "pq3-etsec2-grp2-1.dtsi"
+/include/ "pq3-etsec2-grp2-2.dtsi"
+
/* PCIe controller base address 0x9000 */
{
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts
index 7ebaa619df..715330dc50 100644
--- a/arch/powerpc/dts/p1020rdb-pc.dts
+++ b/arch/powerpc/dts/p1020rdb-pc.dts
@@ -32,4 +32,5 @@
};
};
+/include/ "p1020rdb-pc.dtsi"
/include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pc.dtsi
b/arch/powerpc/dts/p1020rdb-pc.dtsi
new file mode 100644
index 00..6bf424fd3f
--- /dev/null
+++ b/arch/powerpc/dts/p1020rdb-pc.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ {
+ mdio@24000 {
+ phy0: ethernet-phy@0 {
+ interrupt-parent = <>;
+ interrupts = <3 1 0 0>;
+ reg = <0x0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ interrupt-parent = <>;
+ interrupts = <2 1 0 0>;
+ reg = <0x1>;
+ };
+
+ tbi0: tbi-phy@11 {
+ device_type = "tbi-phy";
+ reg = <0x11>;
+ };
+ };
+
+ mdio@25000 {
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet0: ethernet@b {
+ phy-connection-type = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+
+ };
+
+ enet1: ethernet@b1000 {
+ phy-handle = <>;
+ tbi-handle = <>;
+ phy-connection-type = "sgmii";
+ };
+
+ enet2: ethernet@b2000 {
+ phy-handle = <>;
+ phy-connection-type = "rgmii-id";
+ };
+};
diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts
b/arch/powerpc/dts/p1020rdb-pc_36b.dts
index c0e5ef4cf4..7680b7c7e1 100644
--- a/arch/powerpc/dts/p1020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts
@@ -32,4 +32,5 @@
};
};
+/include/ "p1020rdb-pc.dtsi"
/include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts
index 21174a09be..e0e8993dab 100644
--- a/arch/powerpc/dts/p1020rdb-pd.dts
+++ b/arch/powerpc/dts/p1020rdb-pd.dts
@@ -17,6 +17,51 @@
soc: soc@ffe0 {
ranges = <0x0 0x0 0xffe0 0x10>;
+
+ mdio@24000 {
+ phy0: ethernet-phy@0 {
+ interrupts = <3 1 0
[PATCHv6 12/18] configs: P1020RDB: Enable DM_ETH config
From: Hou Zhiqiang Enable the DM_ETH and DM_MDIO config. On P1020RDB, the eTSEC1 is connecting with a switch VSC7385, so also enable the fixed PHY support. Signed-off-by: Hou Zhiqiang --- V6: - No change. configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_defconfig | 3 +++ configs/P1020RDB-PC_NAND_defconfig | 3 +++ configs/P1020RDB-PC_SDCARD_defconfig | 3 +++ configs/P1020RDB-PC_SPIFLASH_defconfig | 3 +++ configs/P1020RDB-PC_defconfig| 3 +++ configs/P1020RDB-PD_NAND_defconfig | 3 +++ configs/P1020RDB-PD_SDCARD_defconfig | 3 +++ configs/P1020RDB-PD_SPIFLASH_defconfig | 3 +++ configs/P1020RDB-PD_defconfig| 3 +++ 12 files changed, 36 insertions(+) diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 6db4bd7d52..e69595102a 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -62,6 +62,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -73,8 +74,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index cacce4d5ec..974bcb15c7 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -57,6 +57,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -68,8 +69,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 3c9e491b08..f3e599869d 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -59,6 +59,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -70,8 +71,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 5c68ea060a..445e796afb 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -46,6 +46,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -57,8 +58,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 9883204787..43fdbdffe4 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -72,8 +73,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 22ba4f6501..282453a290 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -56,6 +56,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -67,8 +68,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 250b56d216..0a7fa606bf 100644 ---
[PATCHv6 14/18] powerpc: p1010rdb: Compile legacy ethernet init function when no DM_ETH
From: Hou Zhiqiang
The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
board/freescale/p1010rdb/p1010rdb.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/p1010rdb/p1010rdb.c
b/board/freescale/p1010rdb/p1010rdb.c
index accf2f24e5..4c3a03e7cd 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -484,6 +484,7 @@ int checkboard(void)
return 0;
}
+#ifndef CONFIG_DM_ETH
int board_eth_init(struct bd_info *bis)
{
#ifdef CONFIG_TSEC_ENET
@@ -524,6 +525,7 @@ int board_eth_init(struct bd_info *bis)
return pci_eth_init(bis);
}
+#endif
#if defined(CONFIG_OF_BOARD_SETUP)
void fdt_del_flexcan(void *blob)
--
2.17.1
[PATCHv6 11/18] powerpc: p1_p2_rdb: Don't compile board_eth_init() when DM_ETH enabled
From: Hou Zhiqiang
The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index d0562ba95a..ba12bea92f 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -359,6 +359,7 @@ int board_early_init_r(void)
return 0;
}
+#ifndef CONFIG_DM_ETH
int board_eth_init(struct bd_info *bis)
{
struct fsl_pq_mdio_info mdio_info;
@@ -406,6 +407,7 @@ int board_eth_init(struct bd_info *bis)
return pci_eth_init(bis);
}
+#endif
#if defined(CONFIG_QE) && \
(defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
--
2.17.1
[PATCHv6 13/18] dts: powerpc: p1010rdb: Add eTSEC DT nodes
From: Hou Zhiqiang
P1010RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII PHY AR8033
eTSEC2: Connected to SGMII PHY AR8033
eTSEC3: Connected to SGMII PHY AR8033
Signed-off-by: Hou Zhiqiang
---
V6:
- No change.
arch/powerpc/dts/p1010rdb-pa.dts | 1 +
arch/powerpc/dts/p1010rdb-pa_36b.dts | 1 +
arch/powerpc/dts/p1010rdb.dtsi | 50
arch/powerpc/dts/p1010si-post.dtsi | 25 ++
4 files changed, 77 insertions(+)
diff --git a/arch/powerpc/dts/p1010rdb-pa.dts b/arch/powerpc/dts/p1010rdb-pa.dts
index c66c4923ac..360d254d91 100644
--- a/arch/powerpc/dts/p1010rdb-pa.dts
+++ b/arch/powerpc/dts/p1010rdb-pa.dts
@@ -15,3 +15,4 @@
};
/include/ "p1010si-post.dtsi"
+/include/ "p1010rdb.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb-pa_36b.dts
b/arch/powerpc/dts/p1010rdb-pa_36b.dts
index b943de7cbb..062086a8c0 100644
--- a/arch/powerpc/dts/p1010rdb-pa_36b.dts
+++ b/arch/powerpc/dts/p1010rdb-pa_36b.dts
@@ -15,3 +15,4 @@
};
/include/ "p1010si-post.dtsi"
+/include/ "p1010rdb.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb.dtsi b/arch/powerpc/dts/p1010rdb.dtsi
index 4f58ee2446..5964270878 100644
--- a/arch/powerpc/dts/p1010rdb.dtsi
+++ b/arch/powerpc/dts/p1010rdb.dtsi
@@ -5,6 +5,56 @@
* Copyright 2020 NXP
*/
{
+ mdio@24000 {
+ phy0: ethernet-phy@0 {
+ reg = <0x1>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <0x0>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ tbi-phy@3 {
+ device_type = "tbi-phy";
+ reg = <0x3>;
+ };
+ };
+
+ mdio@25000 {
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ mdio@26000 {
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet0: ethernet@b {
+ phy-handle = <>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ enet1: ethernet@b1000 {
+ phy-handle = <>;
+ tbi-handle = <>;
+ phy-connection-type = "sgmii";
+ };
+
+ enet2: ethernet@b2000 {
+ phy-handle = <>;
+ tbi-handle = <>;
+ phy-connection-type = "sgmii";
+ };
+
i2c@3000 {
rtc@68 {
compatible = "pericom,pt7c4338";
diff --git a/arch/powerpc/dts/p1010si-post.dtsi
b/arch/powerpc/dts/p1010si-post.dtsi
index 0289441381..f825208056 100644
--- a/arch/powerpc/dts/p1010si-post.dtsi
+++ b/arch/powerpc/dts/p1010si-post.dtsi
@@ -25,6 +25,31 @@
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec2-0.dtsi"
+ enet0: ethernet@b {
+ queue-group@b {
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ };
+ };
+
+/include/ "pq3-etsec2-1.dtsi"
+ enet1: ethernet@b1000 {
+ queue-group@b1000 {
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ };
+ };
+
+/include/ "pq3-etsec2-2.dtsi"
+ enet2: ethernet@b2000 {
+ queue-group@b2000 {
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ };
+
+ };
};
/* controller at 0x9000 */
--
2.17.1
[PATCHv6 06/18] net: tsec: Add the compatible string "gianfar" support
From: Hou Zhiqiang
Add compatible string "gianfar" support and update the
device-tree-bindings doc.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
doc/device-tree-bindings/net/fsl-tsec-phy.txt | 2 +-
drivers/net/tsec.c| 16 ++--
include/tsec.h| 4
3 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/doc/device-tree-bindings/net/fsl-tsec-phy.txt
b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
index 8e8574bc97..a44c5fd9d9 100644
--- a/doc/device-tree-bindings/net/fsl-tsec-phy.txt
+++ b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
@@ -2,7 +2,7 @@
Properties:
- - compatible : Should be "fsl,etsec2"
+ - compatible : Should be "fsl,etsec2" or "gianfar"
- reg : Offset and length of the register set for the device
- phy-handle : See ethernet.txt file in the same directory.
- phy-connection-type : See ethernet.txt file in the same directory. This
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 1e04a89102..e59a107ea8 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -808,11 +808,14 @@ int tsec_probe(struct udevice *dev)
struct tsec_private *priv = dev_get_priv(dev);
struct ofnode_phandle_args phandle_args;
u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
+ struct tsec_data *data;
const char *phy_mode;
fdt_addr_t reg;
ofnode parent;
int ret;
+ data = (struct tsec_data *)dev_get_driver_data(dev);
+
pdata->iobase = (phys_addr_t)dev_read_addr(dev);
priv->regs = dev_remap_addr(dev);
@@ -833,7 +836,7 @@ int tsec_probe(struct udevice *dev)
return -ENOENT;
}
- priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET,
+ priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off,
0, MAP_NOCACHE);
}
@@ -885,8 +888,17 @@ static const struct eth_ops tsec_ops = {
.mcast = tsec_mcast_addr,
};
+static struct tsec_data etsec2_data = {
+ .mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
+};
+
+static struct tsec_data gianfar_data = {
+ .mdio_regs_off = 0x0,
+};
+
static const struct udevice_id tsec_ids[] = {
- { .compatible = "fsl,etsec2" },
+ { .compatible = "fsl,etsec2", .data = (ulong)_data },
+ { .compatible = "gianfar", .data = (ulong)_data },
{ }
};
diff --git a/include/tsec.h b/include/tsec.h
index 43255e538f..5433cfd966 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -394,6 +394,10 @@ struct tsec {
#define TX_BUF_CNT 2
+struct tsec_data {
+ u32 mdio_regs_off;
+};
+
struct tsec_private {
struct txbd8 __iomem txbd[TX_BUF_CNT];
struct rxbd8 __iomem rxbd[PKTBUFSRX];
--
2.17.1
[PATCHv6 07/18] powerpc: mpc8xxx: Don't compile cpu_eth_init() when DM_ETH enabled
From: Hou Zhiqiang
The cpu_eth_init() is only used by the legacy ethernet driver framework.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
arch/powerpc/cpu/mpc8xxx/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 2b24e755fa..67857c3760 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -347,6 +347,7 @@ int fixup_cpu(void)
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
+#ifndef CONFIG_DM_ETH
int cpu_eth_init(struct bd_info *bis)
{
#if defined(CONFIG_ETHER_ON_FCC)
@@ -370,3 +371,4 @@ int cpu_eth_init(struct bd_info *bis)
#endif
return 0;
}
+#endif
--
2.17.1
[PATCHv6 09/18] configs: p1_p2_rdb: Add the default address of vsc7385 firmware
From: Hou Zhiqiang Add the environment 'vscfw_addr' to assign a default address for vsc7385 firmware uploading. Signed-off-by: Hou Zhiqiang --- V6: - No change. include/configs/p1_p2_rdb_pc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 1b74177b2f..a159285c98 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -451,6 +451,7 @@ /* Vsc7385 switch */ #ifdef CONFIG_VSC7385_ENET +#define __VSCFW_ADDR "vscfw_addr=ef00" #define CONFIG_SYS_VSC7385_BASE0xffb0 #ifdef CONFIG_PHYS_64BIT @@ -809,6 +810,7 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset "ramdisk_size=12\0"\ "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ +__stringify(__VSCFW_ADDR)"\0" \ __stringify(__NOR_RST_CMD)"\0" \ __stringify(__SPI_RST_CMD)"\0" \ __stringify(__SD_RST_CMD)"\0" \ -- 2.17.1
[PATCHv6 08/18] fsl: p1_p2_rdb: Move vsc7835 firmware uploading to board_early_init_r()
From: Hou Zhiqiang
Move vsc7835 firmware uploading to board_early_init_r(), so that
the switch also can work in DM eTSEC driver.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 35 +++--
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 7c703b354f..d0562ba95a 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -316,6 +316,10 @@ int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
+#ifdef CONFIG_VSC7385_ENET
+ unsigned int vscfw_addr;
+ char *tmp;
+#endif
/*
* Remap Boot flash region to caching-inhibited
@@ -338,6 +342,20 @@ int board_early_init_r(void)
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
+
+#ifdef CONFIG_VSC7385_ENET
+ /* If a VSC7385 microcode image is present, then upload it. */
+ tmp = env_get("vscfw_addr");
+ if (tmp) {
+ vscfw_addr = simple_strtoul(tmp, NULL, 16);
+ printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
+ if (vsc7385_upload_firmware((void *)vscfw_addr,
+ CONFIG_VSC7385_IMAGE_SIZE))
+ puts("Failure uploading VSC7385 microcode.\n");
+ } else {
+ puts("No address specified for VSC7385 microcode.\n");
+ }
+#endif
return 0;
}
@@ -348,10 +366,6 @@ int board_eth_init(struct bd_info *bis)
ccsr_gur_t *gur __attribute__((unused)) =
(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int num = 0;
-#ifdef CONFIG_VSC7385_ENET
- char *tmp;
- unsigned int vscfw_addr;
-#endif
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
@@ -375,19 +389,6 @@ int board_eth_init(struct bd_info *bis)
return 0;
}
-#ifdef CONFIG_VSC7385_ENET
- /* If a VSC7385 microcode image is present, then upload it. */
- tmp = env_get("vscfw_addr");
- if (tmp) {
- vscfw_addr = simple_strtoul(tmp, NULL, 16);
- printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
- if (vsc7385_upload_firmware((void *) vscfw_addr,
- CONFIG_VSC7385_IMAGE_SIZE))
- puts("Failure uploading VSC7385 microcode.\n");
- } else
- puts("No address specified for VSC7385 microcode.\n");
-#endif
-
mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
mdio_info.name = DEFAULT_MII_NAME;
--
2.17.1
[PATCHv6 05/18] net: tsec: Add fixed-link PHY support
From: Hou Zhiqiang The info of fixed-link PHY is described in DT node instead of getting from MII, so detect the fixed-link PHY DT node first, if it doesn't exist then probe the MII. Signed-off-by: Vladimir Oltean Signed-off-by: Hou Zhiqiang --- V6: - No change. drivers/net/tsec.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 9d68c6f829..1e04a89102 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -683,7 +683,10 @@ static int init_phy(struct tsec_private *priv) tsec_configure_serdes(priv); #ifdef CONFIG_DM_ETH - phydev = dm_eth_phy_connect(priv->dev); + if (ofnode_valid(ofnode_find_subnode(priv->dev->node, "fixed-link"))) + phydev = phy_connect(NULL, 0, priv->dev, priv->interface); + else + phydev = dm_eth_phy_connect(priv->dev); #else phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev, priv->interface); -- 2.17.1
[PATCHv6 01/18] phy: make phy_connect_fixed work with a null mdio bus
From: Vladimir Oltean
It is utterly pointless to require an MDIO bus pointer for a fixed PHY
device. The fixed.c implementation does not require it, only
phy_device_create. Fix that.
Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang
Reviewed-by: Hou Zhiqiang
---
V6:
- No change.
drivers/net/phy/phy.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 67789897c2..9587e6b9fa 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -664,7 +664,7 @@ static struct phy_device *phy_device_create(struct mii_dev
*bus, int addr,
dev = malloc(sizeof(*dev));
if (!dev) {
printf("Failed to allocate PHY device for %s:%d\n",
- bus->name, addr);
+ bus ? bus->name : "(null bus)", addr);
return NULL;
}
@@ -692,7 +692,7 @@ static struct phy_device *phy_device_create(struct mii_dev
*bus, int addr,
return NULL;
}
- if (addr >= 0 && addr < PHY_MAX_ADDR)
+ if (addr >= 0 && addr < PHY_MAX_ADDR && phy_id != PHY_FIXED_ID)
bus->phymap[addr] = dev;
return dev;
--
2.17.1
[PATCHv6 03/18] net: fsl_mdio: Correct the MII management register block address
From: Hou Zhiqiang
The MII management register block offset is different between
gianfar and etsec2 compatible devices, this patch is to fix
this issue by adding driver data for different compatible
string.
Fixes: 2932c5a802a9 ("net: tsec: fsl_mdio: add DM MDIO support")
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
drivers/net/fsl_mdio.c | 28 ++--
include/fsl_mdio.h | 4
2 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index ae96ce4c7b..77f1a96a2e 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#ifdef CONFIG_DM_MDIO
struct tsec_mdio_priv {
@@ -190,17 +191,30 @@ static const struct mdio_ops tsec_mdio_ops = {
.reset = tsec_mdio_reset,
};
+static struct fsl_pq_mdio_data etsec2_data = {
+ .mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
+};
+
+static struct fsl_pq_mdio_data gianfar_data = {
+ .mdio_regs_off = 0x0,
+};
+
+static struct fsl_pq_mdio_data fman_data = {
+ .mdio_regs_off = 0x0,
+};
+
static const struct udevice_id tsec_mdio_ids[] = {
- { .compatible = "fsl,gianfar-tbi" },
- { .compatible = "fsl,gianfar-mdio" },
- { .compatible = "fsl,etsec2-tbi" },
- { .compatible = "fsl,etsec2-mdio" },
- { .compatible = "fsl,fman-mdio" },
+ { .compatible = "fsl,gianfar-tbi", .data = (ulong)_data },
+ { .compatible = "fsl,gianfar-mdio", .data = (ulong)_data },
+ { .compatible = "fsl,etsec2-tbi", .data = (ulong)_data },
+ { .compatible = "fsl,etsec2-mdio", .data = (ulong)_data },
+ { .compatible = "fsl,fman-mdio", .data = (ulong)_data },
{}
};
static int tsec_mdio_probe(struct udevice *dev)
{
+ struct fsl_pq_mdio_data *data;
struct tsec_mdio_priv *priv = (dev) ? dev_get_priv(dev) : NULL;
struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
NULL;
@@ -213,7 +227,9 @@ static int tsec_mdio_probe(struct udevice *dev)
printf("dev_get_priv(dev %p) = NULL\n", dev);
return -1;
}
- priv->regs = dev_remap_addr(dev);
+
+ data = (struct fsl_pq_mdio_data *)dev_get_driver_data(dev);
+ priv->regs = dev_remap_addr(dev) + data->mdio_regs_off;
debug("%s priv %p @ regs %p, pdata %p\n", __func__,
priv, priv->regs, pdata);
diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h
index 41cb73717b..b6c02cf342 100644
--- a/include/fsl_mdio.h
+++ b/include/fsl_mdio.h
@@ -55,6 +55,10 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int
dev_addr,
int regnum);
int memac_mdio_reset(struct mii_dev *bus);
+struct fsl_pq_mdio_data {
+ u32 mdio_regs_off;
+};
+
struct fsl_pq_mdio_info {
struct tsec_mii_mng __iomem *regs;
char *name;
--
2.17.1
[PATCHv6 02/18] net: fsl_mdio: Change to use virtual address
From: Hou Zhiqiang
Use virtual address to access the MII block registers instead
of physical address.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
drivers/net/fsl_mdio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index d2edd1751c..ae96ce4c7b 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -213,7 +213,7 @@ static int tsec_mdio_probe(struct udevice *dev)
printf("dev_get_priv(dev %p) = NULL\n", dev);
return -1;
}
- priv->regs = (void *)(uintptr_t)dev_read_addr(dev);
+ priv->regs = dev_remap_addr(dev);
debug("%s priv %p @ regs %p, pdata %p\n", __func__,
priv, priv->regs, pdata);
--
2.17.1
[PATCHv6 04/18] net: tsec: convert to use DM_MDIO when DM_ETH enabled
From: Hou Zhiqiang
For the platforms on which the eTSEC driver uses DM_ETH, convert its
MDIO controller code to also use DM_MDIO.
Note that for handling the TBI PHY (the MAC PCS for SGMII), we still
don't register a udevice for it, since we can drive it locally and there
is no point in doing otherwise.
Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang
---
V6:
- No change.
drivers/net/tsec.c | 43 ++-
1 file changed, 10 insertions(+), 33 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 5d12e4b775..9d68c6f829 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
@@ -681,8 +682,12 @@ static int init_phy(struct tsec_private *priv)
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
tsec_configure_serdes(priv);
+#ifdef CONFIG_DM_ETH
+ phydev = dm_eth_phy_connect(priv->dev);
+#else
phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
priv->interface);
+#endif
if (!phydev)
return 0;
@@ -789,14 +794,17 @@ int tsec_standard_init(struct bd_info *bis)
return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
}
#else /* CONFIG_DM_ETH */
+
+#ifndef CONFIG_DM_MDIO
+#error "TSEC with DM_ETH also requires DM_MDIO"
+#endif
+
int tsec_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct tsec_private *priv = dev_get_priv(dev);
- struct tsec_mii_mng __iomem *ext_phyregs_mii;
struct ofnode_phandle_args phandle_args;
u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
- struct fsl_pq_mdio_info mdio_info;
const char *phy_mode;
fdt_addr_t reg;
ofnode parent;
@@ -805,31 +813,6 @@ int tsec_probe(struct udevice *dev)
pdata->iobase = (phys_addr_t)dev_read_addr(dev);
priv->regs = dev_remap_addr(dev);
- if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
- _args)) {
- printf("phy-handle does not exist under tsec %s\n", dev->name);
- return -ENOENT;
- } else {
- int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
-
- priv->phyaddr = reg;
- }
-
- parent = ofnode_get_parent(phandle_args.node);
- if (!ofnode_valid(parent)) {
- printf("No parent node for PHY?\n");
- return -ENOENT;
- }
-
- reg = ofnode_get_addr_index(parent, 0);
- if (reg == FDT_ADDR_T_NONE) {
- printf("No 'reg' property of MII for external PHY\n");
- return -ENOENT;
- }
-
- ext_phyregs_mii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0,
- MAP_NOCACHE);
-
ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
_args);
if (ret == 0) {
@@ -867,12 +850,6 @@ int tsec_probe(struct udevice *dev)
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
priv->flags |= TSEC_SGMII;
- mdio_info.regs = ext_phyregs_mii;
- mdio_info.name = (char *)dev->name;
- ret = fsl_pq_mdio_init(NULL, _info);
- if (ret)
- return ret;
-
/* Reset the MAC */
setbits_be32(>regs->maccfg1, MACCFG1_SOFT_RESET);
udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
--
2.17.1
[PATCHv6 00/18] powerpc: convert p1010, p1020 and p2020 RDB boards to DM_ETH
From: Hou Zhiqiang This patchset is to convert P1010, P1020 and P2020 RDB boards to DM_ETH. V5: Merged the following thread: https://patchwork.ozlabs.org/project/uboot/list/?series=174343=both=* Hou Zhiqiang (16): net: fsl_mdio: Change to use virtual address net: fsl_mdio: Correct the MII management register block address net: tsec: convert to use DM_MDIO when DM_ETH enabled net: tsec: Add fixed-link PHY support net: tsec: Add the compatible string "gianfar" support powerpc: mpc8xxx: Don't compile cpu_eth_init() when DM_ETH enabled fsl: p1_p2_rdb: Move vsc7835 firmware uploading to board_early_init_r() configs: p1_p2_rdb: Add the default address of vsc7385 firmware dts: powerpc: p1020rdb: Add eTSEC DT nodes powerpc: p1_p2_rdb: Don't compile board_eth_init() when DM_ETH enabled configs: P1020RDB: Enable DM_ETH config dts: powerpc: p1010rdb: Add eTSEC DT nodes powerpc: p1010rdb: Compile legacy ethernet init function when no DM_ETH configs: P1010RDB: Enable DM_ETH config dts: powerpc: p2020rdb: Add eTSEC DT nodes configs: P2020RDB: Enable DM_ETH config Vladimir Oltean (2): phy: make phy_connect_fixed work with a null mdio bus configs: enable DM_MDIO for LS1021A-TWR and LS1021A-TSN arch/powerpc/cpu/mpc8xxx/cpu.c| 2 + arch/powerpc/dts/p1010rdb-pa.dts | 1 + arch/powerpc/dts/p1010rdb-pa_36b.dts | 1 + arch/powerpc/dts/p1010rdb.dtsi| 50 +++ arch/powerpc/dts/p1010si-post.dtsi| 25 arch/powerpc/dts/p1020-post.dtsi | 20 +- arch/powerpc/dts/p1020rdb-pc.dts | 1 + arch/powerpc/dts/p1020rdb-pc.dtsi | 55 arch/powerpc/dts/p1020rdb-pc_36b.dts | 1 + arch/powerpc/dts/p1020rdb-pd.dts | 45 ++ arch/powerpc/dts/p2020-post.dtsi | 8 ++- arch/powerpc/dts/p2020rdb-pc.dts | 1 + arch/powerpc/dts/p2020rdb-pc.dtsi | 50 +++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 1 + arch/powerpc/dts/pq3-etsec1-0.dtsi| 28 + arch/powerpc/dts/pq3-etsec1-1.dtsi| 28 + arch/powerpc/dts/pq3-etsec1-2.dtsi| 28 + arch/powerpc/dts/pq3-etsec1-3.dtsi| 28 + arch/powerpc/dts/pq3-etsec2-0.dtsi| 35 +++ arch/powerpc/dts/pq3-etsec2-1.dtsi| 35 +++ arch/powerpc/dts/pq3-etsec2-2.dtsi| 35 +++ arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi | 16 + arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi | 16 + arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi | 16 + board/freescale/p1010rdb/p1010rdb.c | 2 + board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 37 ++- configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig| 2 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 + configs/P1010RDB-PA_NAND_defconfig| 2 + configs/P1010RDB-PA_NOR_defconfig | 2 + configs/P1010RDB-PA_SDCARD_defconfig | 2 + configs/P1010RDB-PA_SPIFLASH_defconfig| 2 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig| 2 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 + configs/P1010RDB-PB_NAND_defconfig| 2 + configs/P1010RDB-PB_NOR_defconfig | 2 + configs/P1010RDB-PB_SDCARD_defconfig | 2 + configs/P1010RDB-PB_SPIFLASH_defconfig| 2 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig| 3 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 3 + configs/P1020RDB-PC_36BIT_defconfig | 3 + configs/P1020RDB-PC_NAND_defconfig| 3 + configs/P1020RDB-PC_SDCARD_defconfig | 3 + configs/P1020RDB-PC_SPIFLASH_defconfig| 3 + configs/P1020RDB-PC_defconfig | 3 + configs/P1020RDB-PD_NAND_defconfig| 3 + configs/P1020RDB-PD_SDCARD_defconfig | 3 + configs/P1020RDB-PD_SPIFLASH_defconfig| 3 + configs/P1020RDB-PD_defconfig | 3 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig| 3 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 3 + configs/P2020RDB-PC_36BIT_defconfig | 3 + configs/P2020RDB-PC_NAND_defconfig| 3 + configs/P2020RDB-PC_SDCARD_defconfig | 3 + configs/P2020RDB-PC_SPIFLASH_defconfig| 3 + configs/P2020RDB-PC_defconfig | 3 + configs/ls1021atsn_qspi_defconfig | 1 + configs/ls1021atsn_sdcard_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_nor_defconfig | 1 +
[PATCH] pci: layerscape: Remove the shadow SVR definitiones
From: Hou Zhiqiang This patch moves the SVR definitiones to a new svr.h for Layerscape armv7 and armv8 platforms respectively, so that the PCIe driver can reuse them. Signed-off-by: Hou Zhiqiang --- .../arm/include/asm/arch-fsl-layerscape/soc.h | 30 +--- .../arm/include/asm/arch-fsl-layerscape/svr.h | 34 +++ arch/arm/include/asm/arch-ls102xa/svr.h | 8 + drivers/pci/pcie_layerscape.h | 12 ++- 4 files changed, 45 insertions(+), 39 deletions(-) create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/svr.h create mode 100644 arch/arm/include/asm/arch-ls102xa/svr.h diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 020548ac6c..6946f30f54 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -16,6 +16,7 @@ #include #endif #endif +#include #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE #define gur_in32(a) in_le32(a) @@ -77,35 +78,6 @@ enum boot_src get_boot_src(void); #endif #endif #define SVR_WO_E 0xFE -#define SVR_LS1012A0x870400 -#define SVR_LS1043A0x879200 -#define SVR_LS1023A0x879208 -/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ -#define SVR_LS1043A_P230x879202 -#define SVR_LS1023A_P230x87920A -#define SVR_LS1017A0x870B24 -#define SVR_LS1018A0x870B20 -#define SVR_LS1027A0x870B04 -#define SVR_LS1028A0x870B00 -#define SVR_LS1046A0x870700 -#define SVR_LS1026A0x870708 -#define SVR_LS1048A0x870320 -#define SVR_LS1084A0x870302 -#define SVR_LS1088A0x870300 -#define SVR_LS1044A0x870322 -#define SVR_LS2045A0x870120 -#define SVR_LS2080A0x870110 -#define SVR_LS2085A0x870100 -#define SVR_LS2040A0x870130 -#define SVR_LS2088A0x870900 -#define SVR_LS2084A0x870910 -#define SVR_LS2048A0x870920 -#define SVR_LS2044A0x870930 -#define SVR_LS2081A0x870918 -#define SVR_LS2041A0x870914 -#define SVR_LX2160A0x873600 -#define SVR_LX2120A0x873620 -#define SVR_LX2080A0x873602 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/svr.h b/arch/arm/include/asm/arch-fsl-layerscape/svr.h new file mode 100644 index 00..97c9775644 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/svr.h @@ -0,0 +1,34 @@ +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ +#define _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ + +#define SVR_LS1012A0x870400 +#define SVR_LS1043A0x879200 +#define SVR_LS1023A0x879208 +/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ +#define SVR_LS1043A_P230x879202 +#define SVR_LS1023A_P230x87920A +#define SVR_LS1017A0x870B24 +#define SVR_LS1018A0x870B20 +#define SVR_LS1027A0x870B04 +#define SVR_LS1028A0x870B00 +#define SVR_LS1046A0x870700 +#define SVR_LS1026A0x870708 +#define SVR_LS1048A0x870320 +#define SVR_LS1084A0x870302 +#define SVR_LS1088A0x870300 +#define SVR_LS1044A0x870322 +#define SVR_LS2045A0x870120 +#define SVR_LS2080A0x870110 +#define SVR_LS2085A0x870100 +#define SVR_LS2040A0x870130 +#define SVR_LS2088A0x870900 +#define SVR_LS2084A0x870910 +#define SVR_LS2048A0x870920 +#define SVR_LS2044A0x870930 +#define SVR_LS2081A0x870918 +#define SVR_LS2041A0x870914 +#define SVR_LX2160A0x873600 +#define SVR_LX2120A0x873620 +#define SVR_LX2080A0x873602 + +#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/svr.h b/arch/arm/include/asm/arch-ls102xa/svr.h new file mode 100644 index 00..a069eb2d9e --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/svr.h @@ -0,0 +1,8 @@ +#ifndef _ASM_LS102X_SVR_H_ +#define _ASM_LS102X_SVR_H_ + +#define SVR_LS102XA0 +#define SVR_VAR_PER_SHIFT 8 +#define SVR_LS102XA_MASK 0x700 + +#endif /* _ASM_LS102X_SVR_H_ */ diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index 0124e8e051..8cdf516d9f 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -10,6 +10,8 @@ #include #include +#include +#include #ifndef CONFIG_SYS_PCI_MEMORY_BUS #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE @@ -121,16 +123,6 @@ /* CS2 */ #define PCIE_CS2_OFFSET0x1000 /* For PCIe without SR-IOV */ -#define SVR_LS102XA
[PATCH] pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A rev2
From: Hou Zhiqiang
LX2160A rev2 uses different PCIe controller, so EP mode DT
nodes also need to be fixed up.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pcie_layerscape_fixup_common.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/pci/pcie_layerscape_fixup_common.c
b/drivers/pci/pcie_layerscape_fixup_common.c
index fef0a75f11..0a42997696 100644
--- a/drivers/pci/pcie_layerscape_fixup_common.c
+++ b/drivers/pci/pcie_layerscape_fixup_common.c
@@ -41,6 +41,8 @@ int lx2_board_fix_fdt(void *fdt)
{ "config_axi_slave", "config" }
};
int off = -1, i;
+ const fdt32_t *prop;
+ u32 ob_wins, ib_wins;
off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
while (off != -FDT_ERR_NOTFOUND) {
@@ -86,6 +88,30 @@ int lx2_board_fix_fdt(void *fdt)
off = fdt_node_offset_by_compatible(fdt, off,
"fsl,lx2160a-pcie");
}
+
+ /* Fixup PCIe EP nodes */
+ off = -1;
+ off = fdt_node_offset_by_compatible(fdt, off, "fsl,lx2160a-pcie-ep");
+ while (off != -FDT_ERR_NOTFOUND) {
+ fdt_setprop_string(fdt, off, "compatible",
+ "fsl,lx2160ar2-pcie-ep");
+ prop = fdt_getprop(fdt, off, "apio-wins", NULL);
+ if (!prop) {
+ printf("%s: Failed to fixup PCIe EP node @0x%x\n",
+ __func__, off);
+ continue;
+ }
+
+ ob_wins = fdt32_to_cpu(*prop);
+ ib_wins = (ob_wins == 256) ? 24 : 8;
+ fdt_setprop_u32(fdt, off, "num-ib-windows", ib_wins);
+ fdt_setprop_u32(fdt, off, "num-ob-windows", ob_wins);
+ fdt_delprop(fdt, off, "apio-wins");
+
+ off = fdt_node_offset_by_compatible(fdt, off,
+ "fsl,lx2160a-pcie-ep");
+ }
+
return 0;
}
--
2.17.1
[PATCH] arm64: Layerscape: Survive LPI one-way reset workaround
From: Hou Zhiqiang
The workaround of LPI one-way reset issue is broken by the series:
https://patchwork.ozlabs.org/project/uboot/list/?series=192398
This patch is to add DT node for GIC RD tables and create corresponding
reserved-memory node in kernel DT to fix it.
Signed-off-by: Hou Zhiqiang
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 17 -
arch/arm/dts/fsl-ls1028a.dtsi | 6 ++
arch/arm/dts/fsl-ls1088a.dtsi | 6 ++
arch/arm/dts/fsl-ls2080a.dtsi | 6 ++
arch/arm/dts/fsl-lx2160a.dtsi | 6 ++
5 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index fde893e8c9..53d790f395 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -43,7 +43,22 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_GIC_V3_ITS
int ls_gic_rd_tables_init(void *blob)
{
- int ret;
+ struct fdt_memory lpi_base;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int offset, ret;
+
+ offset = fdt_path_offset(gd->fdt_blob, "/syscon@0x8000");
+ addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, offset, "reg",
+ 0, , false);
+
+ lpi_base.start = addr;
+ lpi_base.end = addr + size - 1;
+ ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", _base, NULL);
+ if (ret) {
+ debug("%s: failed to add reserved memory\n", __func__);
+ return ret;
+ }
ret = gic_lpi_tables_init();
if (ret)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 9911690e5c..bf6373d5ec 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -44,6 +44,12 @@
IRQ_TYPE_LEVEL_LOW)>;
};
+ gic_lpi_base: syscon@0x8000 {
+ compatible = "gic-lpi-base";
+ reg = <0x0 0x8000 0x0 0x10>;
+ max-gic-redistributors = <2>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = ;
};
+ gic_lpi_base: syscon@0x8000 {
+ compatible = "gic-lpi-base";
+ reg = <0x0 0x8000 0x0 0x10>;
+ max-gic-redistributors = <8>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 90a0a3f8fb..6b7bf8eb16 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -26,6 +26,12 @@
interrupts = <1 9 0x4>;
};
+ gic_lpi_base: syscon@0x8000 {
+ compatible = "gic-lpi-base";
+ reg = <0x0 0x8000 0x0 0x10>;
+ max-gic-redistributors = <8>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index dee1e2f215..37a4f39c8f 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -43,6 +43,12 @@
interrupts = <1 9 0x4>;
};
+ gic_lpi_base: syscon@0x8000 {
+ compatible = "gic-lpi-base";
+ reg = <0x0 0x8000 0x0 0x20>;
+ max-gic-redistributors = <16>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
--
2.17.1
[PATCHv5 11/18] dts: powerpc: p1020rdb: Add eTSEC DT nodes
From: Hou Zhiqiang
P1020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V5:
- No change.
arch/powerpc/dts/p1020-post.dtsi| 20 -
arch/powerpc/dts/p1020rdb-pc.dts| 1 +
arch/powerpc/dts/p1020rdb-pc.dtsi | 55 +
arch/powerpc/dts/p1020rdb-pc_36b.dts| 1 +
arch/powerpc/dts/p1020rdb-pd.dts| 45
arch/powerpc/dts/pq3-etsec2-0.dtsi | 35
arch/powerpc/dts/pq3-etsec2-1.dtsi | 35
arch/powerpc/dts/pq3-etsec2-2.dtsi | 35
arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi | 16 +++
arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi | 16 +++
arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi | 16 +++
11 files changed, 273 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/dts/p1020rdb-pc.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-0.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-1.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-2.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi
diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi
index 1dce8e86e9..c73539ad5c 100644
--- a/arch/powerpc/dts/p1020-post.dtsi
+++ b/arch/powerpc/dts/p1020-post.dtsi
@@ -44,10 +44,26 @@
clock-frequency = <0>;
};
- /include/ "pq3-i2c-0.dtsi"
- /include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec2-0.dtsi"
+ enet0: enet0_grp2: ethernet@b {
+ };
+
+/include/ "pq3-etsec2-1.dtsi"
+ enet1: enet1_grp2: ethernet@b1000 {
+ };
+
+/include/ "pq3-etsec2-2.dtsi"
+ enet2: enet2_grp2: ethernet@b2000 {
+ };
};
+/include/ "pq3-etsec2-grp2-0.dtsi"
+/include/ "pq3-etsec2-grp2-1.dtsi"
+/include/ "pq3-etsec2-grp2-2.dtsi"
+
/* PCIe controller base address 0x9000 */
{
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts
index 7ebaa619df..715330dc50 100644
--- a/arch/powerpc/dts/p1020rdb-pc.dts
+++ b/arch/powerpc/dts/p1020rdb-pc.dts
@@ -32,4 +32,5 @@
};
};
+/include/ "p1020rdb-pc.dtsi"
/include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pc.dtsi
b/arch/powerpc/dts/p1020rdb-pc.dtsi
new file mode 100644
index 00..6bf424fd3f
--- /dev/null
+++ b/arch/powerpc/dts/p1020rdb-pc.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ {
+ mdio@24000 {
+ phy0: ethernet-phy@0 {
+ interrupt-parent = <>;
+ interrupts = <3 1 0 0>;
+ reg = <0x0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ interrupt-parent = <>;
+ interrupts = <2 1 0 0>;
+ reg = <0x1>;
+ };
+
+ tbi0: tbi-phy@11 {
+ device_type = "tbi-phy";
+ reg = <0x11>;
+ };
+ };
+
+ mdio@25000 {
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet0: ethernet@b {
+ phy-connection-type = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+
+ };
+
+ enet1: ethernet@b1000 {
+ phy-handle = <>;
+ tbi-handle = <>;
+ phy-connection-type = "sgmii";
+ };
+
+ enet2: ethernet@b2000 {
+ phy-handle = <>;
+ phy-connection-type = "rgmii-id";
+ };
+};
diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts
b/arch/powerpc/dts/p1020rdb-pc_36b.dts
index c0e5ef4cf4..7680b7c7e1 100644
--- a/arch/powerpc/dts/p1020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts
@@ -32,4 +32,5 @@
};
};
+/include/ "p1020rdb-pc.dtsi"
/include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts
index 21174a09be..e0e8993dab 100644
--- a/arch/powerpc/dts/p1020rdb-pd.dts
+++ b/arch/powerpc/dts/p1020rdb-pd.dts
@@ -17,6 +17,51 @@
soc: soc@ffe0 {
ranges = <0x0 0x0 0xffe0 0x10>;
+
+ mdio@24000 {
+ phy0: ethernet-phy@0 {
+ interrupts = <3 1 0
[PATCHv5 18/18] configs: P2020RDB: Enable DM_ETH config
From: Hou Zhiqiang Enable the DM_ETH and DM_MDIO config. On P2020RDB, the eTSEC1 is connecting with a switch VSC7385, so also enable the fixed PHY support. Signed-off-by: Hou Zhiqiang Reviewed-by: Vladimir Oltean --- V5: - No change. configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_defconfig | 3 +++ configs/P2020RDB-PC_NAND_defconfig | 3 +++ configs/P2020RDB-PC_SDCARD_defconfig | 3 +++ configs/P2020RDB-PC_SPIFLASH_defconfig | 3 +++ configs/P2020RDB-PC_defconfig| 3 +++ 8 files changed, 24 insertions(+) diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 3e6ea64ee3..4cd689f55d 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -66,6 +66,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -77,8 +78,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 187cbee0d6..f46463a297 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -72,8 +73,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 88c9224001..73d1be1013 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -63,6 +63,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -74,8 +75,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 88e24c30ba..21a0e85f98 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -50,6 +50,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -61,8 +62,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index dda34dd43e..800c728ed3 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -65,6 +65,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -76,8 +77,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index c2b6ad5f32..81cbac2fe8 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -71,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 3ec208ee00..89308a503b 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -62,6 +62,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000
[PATCHv5 17/18] dts: powerpc: p2020rdb: Add eTSEC DT nodes
From: Hou Zhiqiang
P2020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang
---
V5:
- No change.
arch/powerpc/dts/p2020-post.dtsi | 8 +++--
arch/powerpc/dts/p2020rdb-pc.dts | 1 +
arch/powerpc/dts/p2020rdb-pc.dtsi| 50
arch/powerpc/dts/p2020rdb-pc_36b.dts | 1 +
arch/powerpc/dts/pq3-etsec1-0.dtsi | 28
arch/powerpc/dts/pq3-etsec1-1.dtsi | 28
arch/powerpc/dts/pq3-etsec1-2.dtsi | 28
arch/powerpc/dts/pq3-etsec1-3.dtsi | 28
8 files changed, 170 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/dts/p2020rdb-pc.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-0.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-1.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-2.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-3.dtsi
diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index 4ed093dad4..11945295d1 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -38,8 +38,12 @@
clock-frequency = <0>;
};
- /include/ "pq3-i2c-0.dtsi"
- /include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec1-0.dtsi"
+/include/ "pq3-etsec1-1.dtsi"
+/include/ "pq3-etsec1-2.dtsi"
};
/* PCIe controller base address 0x8000 */
diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts
index 08befd4c59..f3f6be1080 100644
--- a/arch/powerpc/dts/p2020rdb-pc.dts
+++ b/arch/powerpc/dts/p2020rdb-pc.dts
@@ -37,4 +37,5 @@
};
};
+/include/ "p2020rdb-pc.dtsi"
/include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/p2020rdb-pc.dtsi
b/arch/powerpc/dts/p2020rdb-pc.dtsi
new file mode 100644
index 00..0d2acc746e
--- /dev/null
+++ b/arch/powerpc/dts/p2020rdb-pc.dtsi
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ {
+ mdio@24520 {
+ phy0: ethernet-phy@0 {
+ interrupts = <3 1 0 0>;
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy@1 {
+ interrupts = <2 1 0 0>;
+ reg = <0x1>;
+ };
+ };
+
+ mdio@25520 {
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ mdio@26520 {
+ status = "disabled";
+ };
+
+ enet0: ethernet@24000 {
+ phy-connection-type = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ enet1: ethernet@25000 {
+ tbi-handle = <>;
+ phy-handle = <>;
+ phy-connection-type = "sgmii";
+ };
+
+ enet2: ethernet@26000 {
+ phy-handle = <>;
+ phy-connection-type = "rgmii-id";
+ };
+};
diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts
b/arch/powerpc/dts/p2020rdb-pc_36b.dts
index 04b2519e1a..6d983b7d71 100644
--- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
@@ -37,4 +37,5 @@
};
};
+/include/ "p2020rdb-pc.dtsi"
/include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/pq3-etsec1-0.dtsi
b/arch/powerpc/dts/pq3-etsec1-0.dtsi
new file mode 100644
index 00..8800243f34
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-0.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ fsl,magic-packet;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
+};
+
+mdio@24520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x24520 0x20>;
+};
diff --git a/arch/powerpc/dts/pq3-etsec1-1.dtsi
b/arch/powerpc/dts/pq3-etsec1-1.dtsi
new file mode 100644
index 00..2bc62d1a57
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-1.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
+ *
+ * Copyright 2011-2012
[PATCHv5 09/18] fsl: p1_p2_rdb: Move vsc7835 firmware uploading to board_early_init_r()
From: Hou Zhiqiang
Move vsc7835 firmware uploading to board_early_init_r(), so that
the switch also can work in DM eTSEC driver.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V5:
- No change.
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 35 +++--
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 1353debc0e..3dd6178708 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -316,6 +316,10 @@ int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
+#ifdef CONFIG_VSC7385_ENET
+ unsigned int vscfw_addr;
+ char *tmp;
+#endif
/*
* Remap Boot flash region to caching-inhibited
@@ -338,6 +342,20 @@ int board_early_init_r(void)
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
+
+#ifdef CONFIG_VSC7385_ENET
+ /* If a VSC7385 microcode image is present, then upload it. */
+ tmp = env_get("vscfw_addr");
+ if (tmp) {
+ vscfw_addr = simple_strtoul(tmp, NULL, 16);
+ printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
+ if (vsc7385_upload_firmware((void *)vscfw_addr,
+ CONFIG_VSC7385_IMAGE_SIZE))
+ puts("Failure uploading VSC7385 microcode.\n");
+ } else {
+ puts("No address specified for VSC7385 microcode.\n");
+ }
+#endif
return 0;
}
@@ -348,10 +366,6 @@ int board_eth_init(bd_t *bis)
ccsr_gur_t *gur __attribute__((unused)) =
(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int num = 0;
-#ifdef CONFIG_VSC7385_ENET
- char *tmp;
- unsigned int vscfw_addr;
-#endif
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
@@ -375,19 +389,6 @@ int board_eth_init(bd_t *bis)
return 0;
}
-#ifdef CONFIG_VSC7385_ENET
- /* If a VSC7385 microcode image is present, then upload it. */
- tmp = env_get("vscfw_addr");
- if (tmp) {
- vscfw_addr = simple_strtoul(tmp, NULL, 16);
- printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
- if (vsc7385_upload_firmware((void *) vscfw_addr,
- CONFIG_VSC7385_IMAGE_SIZE))
- puts("Failure uploading VSC7385 microcode.\n");
- } else
- puts("No address specified for VSC7385 microcode.\n");
-#endif
-
mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
mdio_info.name = DEFAULT_MII_NAME;
--
2.25.1
[PATCHv5 15/18] powerpc: p1010rdb: Compile legacy ethernet init function when no DM_ETH
From: Hou Zhiqiang
The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V5:
- No change.
board/freescale/p1010rdb/p1010rdb.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/p1010rdb/p1010rdb.c
b/board/freescale/p1010rdb/p1010rdb.c
index 66ccc0bd1e..309f4daa88 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -484,6 +484,7 @@ int checkboard(void)
return 0;
}
+#ifndef CONFIG_DM_ETH
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
@@ -524,6 +525,7 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);
}
+#endif
#if defined(CONFIG_OF_BOARD_SETUP)
void fdt_del_flexcan(void *blob)
--
2.25.1
[PATCHv5 16/18] configs: P1010RDB: Enable DM_ETH config
From: Hou Zhiqiang Enable the DM_ETH and DM_MDIO config. Signed-off-by: Hou Zhiqiang --- V5: - No change. configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PA_NAND_defconfig | 2 ++ configs/P1010RDB-PA_NOR_defconfig| 2 ++ configs/P1010RDB-PA_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PB_NAND_defconfig | 2 ++ configs/P1010RDB-PB_NOR_defconfig| 2 ++ configs/P1010RDB-PB_SDCARD_defconfig | 2 ++ configs/P1010RDB-PB_SPIFLASH_defconfig | 2 ++ 16 files changed, 32 insertions(+) diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index da04cab014..bd31e7c8fa 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -72,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index e6edd395e7..f5c5f0ead5 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -54,8 +54,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index dcd606b0c2..229365a1eb 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -66,8 +66,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index c0800c8d7d..147198fb88 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -68,8 +68,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index 29ba692ca1..1f2472a338 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -71,8 +71,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index d8f87b5dac..35232a87fc 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -53,8 +53,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 9711082529..6a46e3a253 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -65,8 +65,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index de2ac2235f..6c7c12efc1 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -67,8 +67,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 9f4876dd13..832f7ce431 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -72,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y
[PATCHv5 14/18] dts: powerpc: p1010rdb: Add eTSEC DT nodes
From: Hou Zhiqiang
P1010RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII PHY AR8033
eTSEC2: Connected to SGMII PHY AR8033
eTSEC3: Connected to SGMII PHY AR8033
Signed-off-by: Hou Zhiqiang
---
V5:
- No change.
arch/powerpc/dts/p1010rdb-pa.dts | 1 +
arch/powerpc/dts/p1010rdb-pa_36b.dts | 1 +
arch/powerpc/dts/p1010rdb.dtsi | 50
arch/powerpc/dts/p1010si-post.dtsi | 25 ++
4 files changed, 77 insertions(+)
diff --git a/arch/powerpc/dts/p1010rdb-pa.dts b/arch/powerpc/dts/p1010rdb-pa.dts
index c66c4923ac..360d254d91 100644
--- a/arch/powerpc/dts/p1010rdb-pa.dts
+++ b/arch/powerpc/dts/p1010rdb-pa.dts
@@ -15,3 +15,4 @@
};
/include/ "p1010si-post.dtsi"
+/include/ "p1010rdb.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb-pa_36b.dts
b/arch/powerpc/dts/p1010rdb-pa_36b.dts
index b943de7cbb..062086a8c0 100644
--- a/arch/powerpc/dts/p1010rdb-pa_36b.dts
+++ b/arch/powerpc/dts/p1010rdb-pa_36b.dts
@@ -15,3 +15,4 @@
};
/include/ "p1010si-post.dtsi"
+/include/ "p1010rdb.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb.dtsi b/arch/powerpc/dts/p1010rdb.dtsi
index 4f58ee2446..5964270878 100644
--- a/arch/powerpc/dts/p1010rdb.dtsi
+++ b/arch/powerpc/dts/p1010rdb.dtsi
@@ -5,6 +5,56 @@
* Copyright 2020 NXP
*/
{
+ mdio@24000 {
+ phy0: ethernet-phy@0 {
+ reg = <0x1>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <0x0>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ tbi-phy@3 {
+ device_type = "tbi-phy";
+ reg = <0x3>;
+ };
+ };
+
+ mdio@25000 {
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ mdio@26000 {
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet0: ethernet@b {
+ phy-handle = <>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ enet1: ethernet@b1000 {
+ phy-handle = <>;
+ tbi-handle = <>;
+ phy-connection-type = "sgmii";
+ };
+
+ enet2: ethernet@b2000 {
+ phy-handle = <>;
+ tbi-handle = <>;
+ phy-connection-type = "sgmii";
+ };
+
i2c@3000 {
rtc@68 {
compatible = "pericom,pt7c4338";
diff --git a/arch/powerpc/dts/p1010si-post.dtsi
b/arch/powerpc/dts/p1010si-post.dtsi
index 0289441381..f825208056 100644
--- a/arch/powerpc/dts/p1010si-post.dtsi
+++ b/arch/powerpc/dts/p1010si-post.dtsi
@@ -25,6 +25,31 @@
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec2-0.dtsi"
+ enet0: ethernet@b {
+ queue-group@b {
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ };
+ };
+
+/include/ "pq3-etsec2-1.dtsi"
+ enet1: ethernet@b1000 {
+ queue-group@b1000 {
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ };
+ };
+
+/include/ "pq3-etsec2-2.dtsi"
+ enet2: ethernet@b2000 {
+ queue-group@b2000 {
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ };
+
+ };
};
/* controller at 0x9000 */
--
2.25.1
[PATCHv5 10/18] configs: p1_p2_rdb: Add the default address of vsc7385 firmware
From: Hou Zhiqiang Add the environment 'vscfw_addr' to assign a default address for vsc7385 firmware uploading. Signed-off-by: Hou Zhiqiang --- V5: - No change. include/configs/p1_p2_rdb_pc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 219e5d216b..6e00491cd8 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -460,6 +460,7 @@ /* Vsc7385 switch */ #ifdef CONFIG_VSC7385_ENET +#define __VSCFW_ADDR "vscfw_addr=ef00" #define CONFIG_SYS_VSC7385_BASE0xffb0 #ifdef CONFIG_PHYS_64BIT @@ -819,6 +820,7 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset "ramdisk_size=12\0"\ "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ +__stringify(__VSCFW_ADDR)"\0" \ __stringify(__NOR_RST_CMD)"\0" \ __stringify(__SPI_RST_CMD)"\0" \ __stringify(__SD_RST_CMD)"\0" \ -- 2.25.1
[PATCHv5 13/18] configs: P1020RDB: Enable DM_ETH config
From: Hou Zhiqiang Enable the DM_ETH and DM_MDIO config. On P1020RDB, the eTSEC1 is connecting with a switch VSC7385, so also enable the fixed PHY support. Signed-off-by: Hou Zhiqiang --- V5: - No change. configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_defconfig | 3 +++ configs/P1020RDB-PC_NAND_defconfig | 3 +++ configs/P1020RDB-PC_SDCARD_defconfig | 3 +++ configs/P1020RDB-PC_SPIFLASH_defconfig | 3 +++ configs/P1020RDB-PC_defconfig| 3 +++ configs/P1020RDB-PD_NAND_defconfig | 3 +++ configs/P1020RDB-PD_SDCARD_defconfig | 3 +++ configs/P1020RDB-PD_SPIFLASH_defconfig | 3 +++ configs/P1020RDB-PD_defconfig| 3 +++ 12 files changed, 36 insertions(+) diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 6ee52fe5e7..139a0be37e 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -72,8 +73,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 489b91d8e7..f533225f26 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -56,6 +56,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -67,8 +68,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 4a8e4e3726..f3e87f0669 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -58,6 +58,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -69,8 +70,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index f9a4b735ca..04c355585d 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -45,6 +45,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -56,8 +57,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 5c8231cba2..ee663c5861 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -71,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index ad2bb90a49..cabd6c6022 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -55,6 +55,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -66,8 +67,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index b8055e49b0..28a097b0ed 100644 ---
[PATCHv5 12/18] powerpc: p1_p2_rdb: Don't compile board_eth_init() when DM_ETH enabled
From: Hou Zhiqiang
The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V5:
- No change.
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 3dd6178708..41585cf342 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -359,6 +359,7 @@ int board_early_init_r(void)
return 0;
}
+#ifndef CONFIG_DM_ETH
int board_eth_init(bd_t *bis)
{
struct fsl_pq_mdio_info mdio_info;
@@ -406,6 +407,7 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);
}
+#endif
#if defined(CONFIG_QE) && \
(defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
--
2.25.1
[PATCHv5 06/18] net: tsec: Add fixed-link PHY support
From: Hou Zhiqiang The info of fixed-link PHY is described in DT node instead of getting from MII, so detect the fixed-link PHY DT node first, if it doesn't exist then probe the MII. Signed-off-by: Vladimir Oltean Signed-off-by: Hou Zhiqiang --- V5: - No change. drivers/net/tsec.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index babe44691e..cb3e56d439 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -683,7 +683,10 @@ static int init_phy(struct tsec_private *priv) tsec_configure_serdes(priv); #ifdef CONFIG_DM_ETH - phydev = dm_eth_phy_connect(priv->dev); + if (ofnode_valid(ofnode_find_subnode(priv->dev->node, "fixed-link"))) + phydev = phy_connect(NULL, 0, priv->dev, priv->interface); + else + phydev = dm_eth_phy_connect(priv->dev); #else phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev, priv->interface); -- 2.25.1
[PATCHv5 05/18] net: tsec: convert to use DM_MDIO when DM_ETH enabled
From: Hou Zhiqiang
For the platforms on which the eTSEC driver uses DM_ETH, convert its
MDIO controller code to also use DM_MDIO.
Note that for handling the TBI PHY (the MAC PCS for SGMII), we still
don't register a udevice for it, since we can drive it locally and there
is no point in doing otherwise.
Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang
---
V5:
- No change.
drivers/net/tsec.c | 43 ++-
1 file changed, 10 insertions(+), 33 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 3d75acb6b4..babe44691e 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
@@ -681,8 +682,12 @@ static int init_phy(struct tsec_private *priv)
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
tsec_configure_serdes(priv);
+#ifdef CONFIG_DM_ETH
+ phydev = dm_eth_phy_connect(priv->dev);
+#else
phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
priv->interface);
+#endif
if (!phydev)
return 0;
@@ -787,14 +792,17 @@ int tsec_standard_init(bd_t *bis)
return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
}
#else /* CONFIG_DM_ETH */
+
+#ifndef CONFIG_DM_MDIO
+#error "TSEC with DM_ETH also requires DM_MDIO"
+#endif
+
int tsec_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct tsec_private *priv = dev_get_priv(dev);
- struct tsec_mii_mng __iomem *ext_phyregs_mii;
struct ofnode_phandle_args phandle_args;
u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
- struct fsl_pq_mdio_info mdio_info;
const char *phy_mode;
fdt_addr_t reg;
ofnode parent;
@@ -803,31 +811,6 @@ int tsec_probe(struct udevice *dev)
pdata->iobase = (phys_addr_t)dev_read_addr(dev);
priv->regs = dev_remap_addr(dev);
- if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
- _args)) {
- printf("phy-handle does not exist under tsec %s\n", dev->name);
- return -ENOENT;
- } else {
- int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
-
- priv->phyaddr = reg;
- }
-
- parent = ofnode_get_parent(phandle_args.node);
- if (!ofnode_valid(parent)) {
- printf("No parent node for PHY?\n");
- return -ENOENT;
- }
-
- reg = ofnode_get_addr_index(parent, 0);
- if (reg == FDT_ADDR_T_NONE) {
- printf("No 'reg' property of MII for external PHY\n");
- return -ENOENT;
- }
-
- ext_phyregs_mii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0,
- MAP_NOCACHE);
-
ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
_args);
if (ret == 0) {
@@ -865,12 +848,6 @@ int tsec_probe(struct udevice *dev)
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
priv->flags |= TSEC_SGMII;
- mdio_info.regs = ext_phyregs_mii;
- mdio_info.name = (char *)dev->name;
- ret = fsl_pq_mdio_init(NULL, _info);
- if (ret)
- return ret;
-
/* Reset the MAC */
setbits_be32(>regs->maccfg1, MACCFG1_SOFT_RESET);
udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
--
2.25.1
[PATCHv5 07/18] net: tsec: Add the compatible string "gianfar" support
From: Hou Zhiqiang
Add compatible string "gianfar" support and update the
device-tree-bindings doc.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V5:
- No change.
doc/device-tree-bindings/net/fsl-tsec-phy.txt | 2 +-
drivers/net/tsec.c| 16 ++--
include/tsec.h| 4
3 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/doc/device-tree-bindings/net/fsl-tsec-phy.txt
b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
index 8e8574bc97..a44c5fd9d9 100644
--- a/doc/device-tree-bindings/net/fsl-tsec-phy.txt
+++ b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
@@ -2,7 +2,7 @@
Properties:
- - compatible : Should be "fsl,etsec2"
+ - compatible : Should be "fsl,etsec2" or "gianfar"
- reg : Offset and length of the register set for the device
- phy-handle : See ethernet.txt file in the same directory.
- phy-connection-type : See ethernet.txt file in the same directory. This
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index cb3e56d439..22658506b2 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -806,11 +806,14 @@ int tsec_probe(struct udevice *dev)
struct tsec_private *priv = dev_get_priv(dev);
struct ofnode_phandle_args phandle_args;
u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
+ struct tsec_data *data;
const char *phy_mode;
fdt_addr_t reg;
ofnode parent;
int ret;
+ data = (struct tsec_data *)dev_get_driver_data(dev);
+
pdata->iobase = (phys_addr_t)dev_read_addr(dev);
priv->regs = dev_remap_addr(dev);
@@ -831,7 +834,7 @@ int tsec_probe(struct udevice *dev)
return -ENOENT;
}
- priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET,
+ priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off,
0, MAP_NOCACHE);
}
@@ -883,8 +886,17 @@ static const struct eth_ops tsec_ops = {
.mcast = tsec_mcast_addr,
};
+static struct tsec_data etsec2_data = {
+ .mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
+};
+
+static struct tsec_data gianfar_data = {
+ .mdio_regs_off = 0x0,
+};
+
static const struct udevice_id tsec_ids[] = {
- { .compatible = "fsl,etsec2" },
+ { .compatible = "fsl,etsec2", .data = (ulong)_data },
+ { .compatible = "gianfar", .data = (ulong)_data },
{ }
};
diff --git a/include/tsec.h b/include/tsec.h
index b17fa957df..047dd3c373 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -394,6 +394,10 @@ struct tsec {
#define TX_BUF_CNT 2
+struct tsec_data {
+ u32 mdio_regs_off;
+};
+
struct tsec_private {
struct txbd8 __iomem txbd[TX_BUF_CNT];
struct rxbd8 __iomem rxbd[PKTBUFSRX];
--
2.25.1
[PATCHv5 08/18] powerpc: mpc8xxx: Don't compile cpu_eth_init() when DM_ETH enabled
From: Hou Zhiqiang
The cpu_eth_init() is only used by the legacy ethernet driver framework.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V5:
- No change.
arch/powerpc/cpu/mpc8xxx/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index da0a80e6fc..b904943b0e 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -347,6 +347,7 @@ int fixup_cpu(void)
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
+#ifndef CONFIG_DM_ETH
int cpu_eth_init(bd_t *bis)
{
#if defined(CONFIG_ETHER_ON_FCC)
@@ -370,3 +371,4 @@ int cpu_eth_init(bd_t *bis)
#endif
return 0;
}
+#endif
--
2.25.1
[PATCHv5 02/18] configs: enable DM_MDIO for LS1021A-TWR and LS1021A-TSN
From: Vladimir Oltean The tsec driver now requires DM_MDIO when DM_ETH is enabled. To avoid build errors, enable DM_MDIO in these boards' configs before we actually add DM_MDIO support to tsec. Signed-off-by: Vladimir Oltean Signed-off-by: Hou Zhiqiang --- V5: - Pick from https://patchwork.ozlabs.org/project/uboot/patch/20200503185227.28731-3-olte...@gmail.com/. configs/ls1021atsn_qspi_defconfig | 1 + configs/ls1021atsn_sdcard_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig| 1 + configs/ls1021atwr_nor_defconfig| 1 + configs/ls1021atwr_nor_lpuart_defconfig | 1 + configs/ls1021atwr_qspi_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig| 1 + 9 files changed, 9 insertions(+) diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index a62e04e92a..9a659c5512 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -43,6 +43,7 @@ CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_TSEC_ENET=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index db4f0ab796..235265bd74 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -54,6 +54,7 @@ CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_TSEC_ENET=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 0bf4aad102..8946bc1a70 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -45,6 +45,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 5507dbe3c1..12b39703d4 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -47,6 +47,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index cdf81957a8..84b724930f 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -49,6 +49,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 4c82d66899..52a4c5106b 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -50,6 +50,7 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 9039ccc8f2..f6db8850c4 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -60,6 +60,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 478d3df1b8..f011b9ef50 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -62,6 +62,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index de783a8d3d..524ea054aa 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -61,6 +61,7 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -- 2.25.1
[PATCHv5 01/18] phy: make phy_connect_fixed work with a null mdio bus
From: Vladimir Oltean
It is utterly pointless to require an MDIO bus pointer for a fixed PHY
device. The fixed.c implementation does not require it, only
phy_device_create. Fix that.
Signed-off-by: Vladimir Oltean
Reviewed-by: Hou Zhiqiang
Signed-off-by: Hou Zhiqiang
---
V5:
- Pick from
https://patchwork.ozlabs.org/project/uboot/patch/20200503185227.28731-2-olte...@gmail.com/.
drivers/net/phy/phy.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index cce09c47f9..a2dd86dba2 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -664,7 +664,7 @@ static struct phy_device *phy_device_create(struct mii_dev
*bus, int addr,
dev = malloc(sizeof(*dev));
if (!dev) {
printf("Failed to allocate PHY device for %s:%d\n",
- bus->name, addr);
+ bus ? bus->name : "(null bus)", addr);
return NULL;
}
@@ -692,7 +692,7 @@ static struct phy_device *phy_device_create(struct mii_dev
*bus, int addr,
return NULL;
}
- if (addr >= 0 && addr < PHY_MAX_ADDR)
+ if (addr >= 0 && addr < PHY_MAX_ADDR && phy_id != PHY_FIXED_ID)
bus->phymap[addr] = dev;
return dev;
--
2.25.1
[PATCHv5 03/18] net: fsl_mdio: Change to use virtual address
From: Hou Zhiqiang
Use virtual address to access the MII block registers instead
of physical address.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V5:
- No change.
drivers/net/fsl_mdio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index 43040d4c3f..e52daa214d 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -213,7 +213,7 @@ static int tsec_mdio_probe(struct udevice *dev)
printf("dev_get_priv(dev %p) = NULL\n", dev);
return -1;
}
- priv->regs = (void *)(uintptr_t)dev_read_addr(dev);
+ priv->regs = dev_remap_addr(dev);
debug("%s priv %p @ regs %p, pdata %p\n", __func__,
priv, priv->regs, pdata);
--
2.25.1
[PATCHv5 04/18] net: fsl_mdio: Correct the MII management register block address
From: Hou Zhiqiang
The MII management register block offset is different between
gianfar and etsec2 compatible devices, this patch is to fix
this issue by adding driver data for different compatible
string.
Fixes: 2932c5a802a9 ("net: tsec: fsl_mdio: add DM MDIO support")
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V5:
- No change.
drivers/net/fsl_mdio.c | 28 ++--
include/fsl_mdio.h | 4
2 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index e52daa214d..5b615d50f6 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#ifdef CONFIG_DM_MDIO
struct tsec_mdio_priv {
@@ -190,17 +191,30 @@ static const struct mdio_ops tsec_mdio_ops = {
.reset = tsec_mdio_reset,
};
+static struct fsl_pq_mdio_data etsec2_data = {
+ .mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
+};
+
+static struct fsl_pq_mdio_data gianfar_data = {
+ .mdio_regs_off = 0x0,
+};
+
+static struct fsl_pq_mdio_data fman_data = {
+ .mdio_regs_off = 0x0,
+};
+
static const struct udevice_id tsec_mdio_ids[] = {
- { .compatible = "fsl,gianfar-tbi" },
- { .compatible = "fsl,gianfar-mdio" },
- { .compatible = "fsl,etsec2-tbi" },
- { .compatible = "fsl,etsec2-mdio" },
- { .compatible = "fsl,fman-mdio" },
+ { .compatible = "fsl,gianfar-tbi", .data = (ulong)_data },
+ { .compatible = "fsl,gianfar-mdio", .data = (ulong)_data },
+ { .compatible = "fsl,etsec2-tbi", .data = (ulong)_data },
+ { .compatible = "fsl,etsec2-mdio", .data = (ulong)_data },
+ { .compatible = "fsl,fman-mdio", .data = (ulong)_data },
{}
};
static int tsec_mdio_probe(struct udevice *dev)
{
+ struct fsl_pq_mdio_data *data;
struct tsec_mdio_priv *priv = (dev) ? dev_get_priv(dev) : NULL;
struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
NULL;
@@ -213,7 +227,9 @@ static int tsec_mdio_probe(struct udevice *dev)
printf("dev_get_priv(dev %p) = NULL\n", dev);
return -1;
}
- priv->regs = dev_remap_addr(dev);
+
+ data = (struct fsl_pq_mdio_data *)dev_get_driver_data(dev);
+ priv->regs = dev_remap_addr(dev) + data->mdio_regs_off;
debug("%s priv %p @ regs %p, pdata %p\n", __func__,
priv, priv->regs, pdata);
diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h
index 8857d50910..cd612c0954 100644
--- a/include/fsl_mdio.h
+++ b/include/fsl_mdio.h
@@ -55,6 +55,10 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int
dev_addr,
int regnum);
int memac_mdio_reset(struct mii_dev *bus);
+struct fsl_pq_mdio_data {
+ u32 mdio_regs_off;
+};
+
struct fsl_pq_mdio_info {
struct tsec_mii_mng __iomem *regs;
char *name;
--
2.25.1
[PATCHv5 00/18] powerpc: convert p1010, p1020 and p2020 RDB boards to DM_ETH
From: Hou Zhiqiang This patchset is to convert P1010, P1020 and P2020 RDB boards to DM_ETH. V5: Merged the following thread: https://patchwork.ozlabs.org/project/uboot/list/?series=174343=both=* Hou Zhiqiang (16): net: fsl_mdio: Change to use virtual address net: fsl_mdio: Correct the MII management register block address net: tsec: convert to use DM_MDIO when DM_ETH enabled net: tsec: Add fixed-link PHY support net: tsec: Add the compatible string "gianfar" support powerpc: mpc8xxx: Don't compile cpu_eth_init() when DM_ETH enabled fsl: p1_p2_rdb: Move vsc7835 firmware uploading to board_early_init_r() configs: p1_p2_rdb: Add the default address of vsc7385 firmware dts: powerpc: p1020rdb: Add eTSEC DT nodes powerpc: p1_p2_rdb: Don't compile board_eth_init() when DM_ETH enabled configs: P1020RDB: Enable DM_ETH config dts: powerpc: p1010rdb: Add eTSEC DT nodes powerpc: p1010rdb: Compile legacy ethernet init function when no DM_ETH configs: P1010RDB: Enable DM_ETH config dts: powerpc: p2020rdb: Add eTSEC DT nodes configs: P2020RDB: Enable DM_ETH config Vladimir Oltean (2): phy: make phy_connect_fixed work with a null mdio bus configs: enable DM_MDIO for LS1021A-TWR and LS1021A-TSN arch/powerpc/cpu/mpc8xxx/cpu.c| 2 + arch/powerpc/dts/p1010rdb-pa.dts | 1 + arch/powerpc/dts/p1010rdb-pa_36b.dts | 1 + arch/powerpc/dts/p1010rdb.dtsi| 50 +++ arch/powerpc/dts/p1010si-post.dtsi| 25 arch/powerpc/dts/p1020-post.dtsi | 20 +- arch/powerpc/dts/p1020rdb-pc.dts | 1 + arch/powerpc/dts/p1020rdb-pc.dtsi | 55 arch/powerpc/dts/p1020rdb-pc_36b.dts | 1 + arch/powerpc/dts/p1020rdb-pd.dts | 45 ++ arch/powerpc/dts/p2020-post.dtsi | 8 ++- arch/powerpc/dts/p2020rdb-pc.dts | 1 + arch/powerpc/dts/p2020rdb-pc.dtsi | 50 +++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 1 + arch/powerpc/dts/pq3-etsec1-0.dtsi| 28 + arch/powerpc/dts/pq3-etsec1-1.dtsi| 28 + arch/powerpc/dts/pq3-etsec1-2.dtsi| 28 + arch/powerpc/dts/pq3-etsec1-3.dtsi| 28 + arch/powerpc/dts/pq3-etsec2-0.dtsi| 35 +++ arch/powerpc/dts/pq3-etsec2-1.dtsi| 35 +++ arch/powerpc/dts/pq3-etsec2-2.dtsi| 35 +++ arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi | 16 + arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi | 16 + arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi | 16 + board/freescale/p1010rdb/p1010rdb.c | 2 + board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 37 ++- configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig| 2 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 + configs/P1010RDB-PA_NAND_defconfig| 2 + configs/P1010RDB-PA_NOR_defconfig | 2 + configs/P1010RDB-PA_SDCARD_defconfig | 2 + configs/P1010RDB-PA_SPIFLASH_defconfig| 2 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig| 2 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 + configs/P1010RDB-PB_NAND_defconfig| 2 + configs/P1010RDB-PB_NOR_defconfig | 2 + configs/P1010RDB-PB_SDCARD_defconfig | 2 + configs/P1010RDB-PB_SPIFLASH_defconfig| 2 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig| 3 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 3 + configs/P1020RDB-PC_36BIT_defconfig | 3 + configs/P1020RDB-PC_NAND_defconfig| 3 + configs/P1020RDB-PC_SDCARD_defconfig | 3 + configs/P1020RDB-PC_SPIFLASH_defconfig| 3 + configs/P1020RDB-PC_defconfig | 3 + configs/P1020RDB-PD_NAND_defconfig| 3 + configs/P1020RDB-PD_SDCARD_defconfig | 3 + configs/P1020RDB-PD_SPIFLASH_defconfig| 3 + configs/P1020RDB-PD_defconfig | 3 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig| 3 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 3 + configs/P2020RDB-PC_36BIT_defconfig | 3 + configs/P2020RDB-PC_NAND_defconfig| 3 + configs/P2020RDB-PC_SDCARD_defconfig | 3 + configs/P2020RDB-PC_SPIFLASH_defconfig| 3 + configs/P2020RDB-PC_defconfig | 3 + configs/ls1021atsn_qspi_defconfig | 1 + configs/ls1021atsn_sdcard_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_nor_defconfig | 1 +
[PATCHv2 10/10] pci: layerscape: Add specific config entry for RC and EP mode driver
From: Hou Zhiqiang Add Root Complex and Endpoint mode specific config entries, such that it's feasible to enable the RC and/or EP mode driver indepently. Signed-off-by: Hou Zhiqiang --- V2: - New patch. configs/ls1012afrdm_qspi_defconfig| 2 +- configs/ls1012afrdm_tfa_defconfig | 2 +- .../ls1012afrwy_qspi_SECURE_BOOT_defconfig| 2 +- configs/ls1012afrwy_qspi_defconfig| 2 +- configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012afrwy_tfa_defconfig | 2 +- configs/ls1012aqds_qspi_defconfig | 2 +- configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012aqds_tfa_defconfig | 2 +- configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1012ardb_qspi_defconfig | 2 +- configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012ardb_tfa_defconfig | 2 +- configs/ls1021aiot_qspi_defconfig | 2 +- configs/ls1021aiot_sdcard_defconfig | 2 +- configs/ls1021aqds_ddr4_nor_defconfig | 2 +- configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 2 +- configs/ls1021aqds_nand_defconfig | 2 +- configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 2 +- configs/ls1021aqds_nor_defconfig | 2 +- configs/ls1021aqds_nor_lpuart_defconfig | 2 +- configs/ls1021aqds_qspi_defconfig | 2 +- configs/ls1021aqds_sdcard_ifc_defconfig | 2 +- configs/ls1021aqds_sdcard_qspi_defconfig | 2 +- configs/ls1021atsn_qspi_defconfig | 2 +- configs/ls1021atsn_sdcard_defconfig | 2 +- configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 +- configs/ls1021atwr_nor_defconfig | 2 +- configs/ls1021atwr_nor_lpuart_defconfig | 2 +- configs/ls1021atwr_qspi_defconfig | 2 +- ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 +- configs/ls1021atwr_sdcard_ifc_defconfig | 2 +- configs/ls1021atwr_sdcard_qspi_defconfig | 2 +- configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1028aqds_tfa_defconfig | 2 +- configs/ls1028aqds_tfa_lpuart_defconfig | 2 +- configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1028ardb_tfa_defconfig | 2 +- configs/ls1043aqds_defconfig | 2 +- configs/ls1043aqds_lpuart_defconfig | 2 +- configs/ls1043aqds_nand_defconfig | 2 +- configs/ls1043aqds_nor_ddr3_defconfig | 2 +- configs/ls1043aqds_qspi_defconfig | 2 +- configs/ls1043aqds_sdcard_ifc_defconfig | 2 +- configs/ls1043aqds_sdcard_qspi_defconfig | 2 +- configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1043aqds_tfa_defconfig | 2 +- configs/ls1043ardb_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_defconfig | 2 +- configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_nand_defconfig | 2 +- .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_sdcard_defconfig | 2 +- configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_tfa_defconfig | 2 +- configs/ls1046afrwy_tfa_defconfig | 3 +- configs/ls1046aqds_SECURE_BOOT_defconfig | 3 +- configs/ls1046aqds_defconfig | 3 +- configs/ls1046aqds_lpuart_defconfig | 3 +- configs/ls1046aqds_nand_defconfig | 3 +- configs/ls1046aqds_qspi_defconfig | 3 +- configs/ls1046aqds_sdcard_ifc_defconfig | 3 +- configs/ls1046aqds_sdcard_qspi_defconfig | 3 +- configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 3 +- configs/ls1046aqds_tfa_defconfig | 3 +- configs/ls1046ardb_emmc_defconfig | 3 +- configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 3 +- configs/ls1046ardb_qspi_defconfig | 3 +- configs/ls1046ardb_qspi_spl_defconfig | 3 +- .../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 3 +- configs/ls1046ardb_sdcard_defconfig | 3 +- configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 3 +- configs/ls1046ardb_tfa_defconfig | 3 +- configs/ls1088aqds_defconfig | 2 +- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1088aqds_qspi_defconfig | 2 +- configs/ls1088aqds_sdcard_ifc_defconfig | 2 +- configs/ls1088aqds_sdcard_qspi_defconfig | 2 +- configs/ls1088aqds_tfa_defconfig | 2 +- configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1088ardb_qspi_defconfig | 2 +- ...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1088ardb_sdcard_qspi_defconfig | 2 +- configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1088ardb_tfa_defconfig | 2 +- configs/ls2080aqds_SECURE_BOOT_defconfig | 2 +- configs/ls2080aqds_defconfig | 2 +-
[PATCHv2 07/10] pci_ep: layerscape: Add the SRIOV VFs of PF support
From: Xiaowei Bao
Add the INBOUND configuration for VFs of PF.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
V2:
- Rebase the patch without change intent.
drivers/pci/pcie_layerscape.c| 8 +---
drivers/pci/pcie_layerscape.h| 13 +++-
drivers/pci/pcie_layerscape_ep.c | 34 +++-
3 files changed, 42 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index ea0fc43441..0116af8aa5 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -95,7 +95,7 @@ int ls_pcie_link_up(struct ls_pcie *pcie)
}
void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
- u64 phys, u64 bus_addr, pci_size_t size)
+ u64 phys, u64 bus_addr, u64 size)
{
dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT);
dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE);
@@ -108,14 +108,16 @@ void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int
idx, int type,
}
/* Use bar match mode and MEM type as default */
-void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, int type,
-int idx, int bar, u64 phys)
+void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
+int type, int idx, int bar, u64 phys)
{
dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
dbi_writel(pcie, type | PCIE_ATU_FUNC_NUM(pf), PCIE_ATU_CR1);
dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
+ (vf_flag ? PCIE_ATU_FUNC_NUM_MATCH_EN : 0) |
+ (vf_flag ? PCIE_ATU_VFBAR_MATCH_MODE_EN : 0) |
PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
}
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index dabfff32db..26d0177ca2 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -20,7 +20,7 @@
#endif
#ifndef CONFIG_SYS_PCI_MEMORY_SIZE
-#define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */
+#define CONFIG_SYS_PCI_MEMORY_SIZE SZ_4G
#endif
#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
@@ -40,6 +40,7 @@
#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
#define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
#define PCIE_ATU_REGION_NUM6
+#define PCIE_ATU_REGION_NUM_SRIOV 24
#define PCIE_ATU_CR1 0x904
#define PCIE_ATU_TYPE_MEM (0x0 << 0)
#define PCIE_ATU_TYPE_IO (0x2 << 0)
@@ -49,6 +50,8 @@
#define PCIE_ATU_CR2 0x908
#define PCIE_ATU_ENABLE(0x1 << 31)
#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
+#define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
+#define PCIE_ATU_VFBAR_MATCH_MODE_EN BIT(26)
#define PCIE_ATU_BAR_NUM(bar) ((bar) << 8)
#define PCIE_ATU_LOWER_BASE0x90C
#define PCIE_ATU_UPPER_BASE0x910
@@ -88,7 +91,7 @@
#define FSL_PCIE_EP_MIN_APERTURE4096 /* 4 Kbytes */
#define PCIE_PF_NUM2
#define PCIE_VF_NUM64
-#define BAR_NUM4
+#define BAR_NUM8
#define PCIE_BAR0_SIZE SZ_4K
#define PCIE_BAR1_SIZE SZ_8K
@@ -179,9 +182,9 @@ void dbi_writel(struct ls_pcie *pcie, unsigned int value,
unsigned int offset);
unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset);
void ctrl_writel(struct ls_pcie *pcie, unsigned int value, unsigned int
offset);
void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
- u64 phys, u64 bus_addr, pci_size_t size);
-void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, int type,
-int idx, int bar, u64 phys);
+ u64 phys, u64 bus_addr, u64 size);
+void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
+int type, int idx, int bar, u64 phys);
void ls_pcie_dump_atu(struct ls_pcie *pcie);
int ls_pcie_link_up(struct ls_pcie *pcie);
void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie);
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index 20de056b8a..cbf73e72c1 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -46,7 +46,7 @@ static int ls_ep_set_bar(struct udevice *dev, uint fn, struct
pci_bar *ep_bar)
else
type = PCIE_ATU_TYPE_IO;
- ls_pcie_atu_inbound_set(pcie, fn, type, idx, bar, bar_phys);
+ ls_pcie_atu_inbound_set(pcie, fn, 0, type, idx, bar, bar_phys);
dbi_writel(pcie, lower_32_bits(size - 1), reg + PCIE_NO_SRIOV_BAR_BASE);
dbi_writel(pcie, flags, reg);
@@ -67,27 +67,51 @@ static struct pci_ep_ops ls_pcie_ep_ops = {
static void
[PATCHv2 09/10] pci_ep: layerscape: Add the PCIe EP mode support for lx2160a-v2
From: Xiaowei Bao
Add the PCIe EP mode support for lx2160a-v2 platform.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
V2:
- Rebase the patch without change intent.
drivers/pci/pcie_layerscape.h| 9 -
drivers/pci/pcie_layerscape_ep.c | 8 +++-
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 5f5c51d3d6..593798e3e3 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -100,7 +100,7 @@
#define PCIE_SRIOV_VFBAR0 0x19C
-#define PCIE_MASK_OFFSET(flag, pf) ((flag) ? 0 : (0x1000 + 0x2 * (pf)))
+#define PCIE_MASK_OFFSET(flag, pf, off) ((flag) ? 0 : (0x1000 + (off) * (pf)))
/* LUT registers */
#define PCIE_LUT_UDR(n)(0x800 + (n) * 8)
@@ -139,6 +139,12 @@
#define LS1021_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
#define LS1021_LTSSM_STATE_SHIFT 20
+/* LX2160a PF1 offset */
+#define LX2160_PCIE_PF1_OFFSET 0x8000
+
+/* layerscape PF1 offset */
+#define LS_PCIE_PF1_OFFSET 0x2
+
struct ls_pcie {
void __iomem *dbi;
void __iomem *lut;
@@ -170,6 +176,7 @@ struct ls_pcie_ep {
void __iomem *addr;
u32 cfg2_flag;
u32 sriov_flag;
+ u32 pf1_offset;
u32 num_ib_wins;
u32 num_ob_wins;
u8 max_functions;
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index 52d6397064..eba230e3a5 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -198,7 +198,8 @@ static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
writel(0, pcie->dbi + PCIE_MISC_CONTROL_1_OFF);
bar_base = pcie->dbi +
- PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf);
+ PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf,
+ pcie_ep->pf1_offset);
if (pcie_ep->cfg2_flag) {
ctrl_writel(pcie,
@@ -271,6 +272,11 @@ static int ls_pcie_ep_probe(struct udevice *dev)
svr = SVR_SOC_VER(get_svr());
+ if (svr == SVR_LX2160A)
+ pcie_ep->pf1_offset = LX2160_PCIE_PF1_OFFSET;
+ else
+ pcie_ep->pf1_offset = LS_PCIE_PF1_OFFSET;
+
if (svr == SVR_LS2080A || svr == SVR_LS2085A)
pcie_ep->cfg2_flag = 1;
else
--
2.17.1
[PATCHv2 08/10] pci: layerscaple: Modify the ls_pcie_dump_atu function
From: Xiaowei Bao
Modify the ls_pcie_dump_atu function, make it can print the INBOUND
windows registers.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
V2:
- Rebase the patch without change intent.
drivers/pci/pcie_layerscape.c| 25 +
drivers/pci/pcie_layerscape.h| 2 +-
drivers/pci/pcie_layerscape_ep.c | 3 +++
drivers/pci/pcie_layerscape_rc.c | 2 +-
4 files changed, 18 insertions(+), 14 deletions(-)
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 0116af8aa5..25b5272d4e 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -121,24 +121,25 @@ void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32
pf, u32 vf_flag,
PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
}
-void ls_pcie_dump_atu(struct ls_pcie *pcie)
+void ls_pcie_dump_atu(struct ls_pcie *pcie, u32 win_num, u32 type)
{
- int i;
+ int win_idx;
- for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
- dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
- PCIE_ATU_VIEWPORT);
- debug("iATU%d:\n", i);
+ for (win_idx = 0; win_idx < win_num; win_idx++) {
+ dbi_writel(pcie, type | win_idx, PCIE_ATU_VIEWPORT);
+ debug("iATU%d:\n", win_idx);
debug("\tLOWER PHYS 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
debug("\tUPPER PHYS 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
- debug("\tLOWER BUS 0x%08x\n",
- dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
- debug("\tUPPER BUS 0x%08x\n",
- dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
- debug("\tLIMIT 0x%08x\n",
- dbi_readl(pcie, PCIE_ATU_LIMIT));
+ if (type == PCIE_ATU_REGION_OUTBOUND) {
+ debug("\tLOWER BUS 0x%08x\n",
+ dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
+ debug("\tUPPER BUS 0x%08x\n",
+ dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
+ debug("\tLIMIT 0x%08x\n",
+ dbi_readl(pcie, PCIE_ATU_LIMIT));
+ }
debug("\tCR10x%08x\n",
dbi_readl(pcie, PCIE_ATU_CR1));
debug("\tCR20x%08x\n",
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 26d0177ca2..5f5c51d3d6 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -185,7 +185,7 @@ void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int
idx, int type,
u64 phys, u64 bus_addr, u64 size);
void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
int type, int idx, int bar, u64 phys);
-void ls_pcie_dump_atu(struct ls_pcie *pcie);
+void ls_pcie_dump_atu(struct ls_pcie *pcie, u32 win_num, u32 type);
int ls_pcie_link_up(struct ls_pcie *pcie);
void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie);
void ls_pcie_dbi_ro_wr_dis(struct ls_pcie *pcie);
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index cbf73e72c1..52d6397064 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -227,6 +227,9 @@ static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
ls_pcie_ep_setup_atu(pcie_ep, 0);
}
+ ls_pcie_dump_atu(pcie, PCIE_ATU_REGION_NUM_SRIOV,
+PCIE_ATU_REGION_INBOUND);
+
ls_pcie_ep_enable_cfg(pcie_ep);
}
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index e922e5dbcd..25c6ddebce 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -115,7 +115,7 @@ static void ls_pcie_setup_atu(struct ls_pcie_rc *pcie_rc)
pref->bus_start,
pref->size);
- ls_pcie_dump_atu(pcie);
+ ls_pcie_dump_atu(pcie, PCIE_ATU_REGION_NUM, PCIE_ATU_REGION_OUTBOUND);
}
/* Return 0 if the address is valid, -errno if not valid */
--
2.17.1
[PATCHv2 06/10] pci_ep: layerscape: Add Support for ls2085a and ls2080a EP mode
From: Xiaowei Bao
Due to the ls2085a and ls2080a use different way to set the BAR size,
so add the BAR size init code here.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
V2:
- Rebase the patch without change intent.
drivers/pci/pcie_layerscape_ep.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index 3f22c5ef7a..20de056b8a 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -173,17 +173,25 @@ static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
*/
writel(0, pcie->dbi + PCIE_MISC_CONTROL_1_OFF);
+ bar_base = pcie->dbi +
+ PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf);
+
if (pcie_ep->cfg2_flag) {
- for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
+ ctrl_writel(pcie,
+ PCIE_LCTRL0_VAL(pf, 0),
+ PCIE_PF_VF_CTRL);
+ ls_pcie_ep_setup_bars(bar_base);
+
+ for (vf = 1; vf <= PCIE_VF_NUM; vf++) {
ctrl_writel(pcie,
PCIE_LCTRL0_VAL(pf, vf),
PCIE_PF_VF_CTRL);
+ ls_pcie_ep_setup_vf_bars(bar_base);
}
+ } else {
+ ls_pcie_ep_setup_bars(bar_base);
+ ls_pcie_ep_setup_vf_bars(bar_base);
}
- bar_base = pcie->dbi +
- PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf);
- ls_pcie_ep_setup_bars(bar_base);
- ls_pcie_ep_setup_vf_bars(bar_base);
ls_pcie_ep_setup_atu(pcie_ep, pf);
}
--
2.17.1
[PATCHv2 05/10] pci_ep: layerscape: Add the workaround for errata A-009460
From: Xiaowei Bao
The VF_BARn_REG register's Prefetchable and Type bit fields
are overwritten by a write to VF's BAR Mask register.
workaround: Before writing to the VF_BARn_MASK_REG register,
write 0b to the PCIE_MISC_CONTROL_1_OFF register.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
V2:
- Rebase the patch without change intent.
drivers/pci/pcie_layerscape_ep.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index e609607c3a..3f22c5ef7a 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -164,6 +164,15 @@ static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
pcie_ep->sriov_flag = 1;
for (pf = 0; pf < PCIE_PF_NUM; pf++) {
+ /*
+* The VF_BARn_REG register's Prefetchable and Type bit
+* fields are overwritten by a write to VF's BAR Mask
+* register. Before writing to the VF_BARn_MASK_REG
+* register, write 0b to the PCIE_MISC_CONTROL_1_OFF
+* register.
+*/
+ writel(0, pcie->dbi + PCIE_MISC_CONTROL_1_OFF);
+
if (pcie_ep->cfg2_flag) {
for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
ctrl_writel(pcie,
--
2.17.1
[PATCHv2 01/10] pci: layerscape: Split the EP and RC driver
From: Xiaowei Bao
Split the RC and EP driver, and reimplement the EP driver base on
the EP framework.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
V2:
- Rebase the patch without change intent.
drivers/pci/Makefile| 2 +-
drivers/pci/pcie_layerscape.c | 487 ++--
drivers/pci/pcie_layerscape.h | 44 ++-
drivers/pci/pcie_layerscape_ep.c| 241 ++
drivers/pci/pcie_layerscape_fixup.c | 79 +++--
drivers/pci/pcie_layerscape_rc.c| 379 ++
6 files changed, 735 insertions(+), 497 deletions(-)
create mode 100644 drivers/pci/pcie_layerscape_ep.c
create mode 100644 drivers/pci/pcie_layerscape_rc.c
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index c051ecc9f3..440b5af588 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -33,7 +33,7 @@ obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
obj-$(CONFIG_PCIE_FSL) += pcie_fsl.o pcie_fsl_fixup.o
-obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
+obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o pcie_layerscape_rc.o
pcie_layerscape_ep.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
pcie_layerscape_fixup_common.o
obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
pcie_layerscape_gen4_fixup.o \
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 39b6d40802..93018feb7c 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -1,18 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Layerscape PCIe driver
*/
#include
#include
-#include
-#include
#include
#include
#include
-#include
#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
defined(CONFIG_ARM)
#include
@@ -23,18 +20,17 @@ DECLARE_GLOBAL_DATA_PTR;
LIST_HEAD(ls_pcie_list);
-static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
+unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
{
return in_le32(pcie->dbi + offset);
}
-static void dbi_writel(struct ls_pcie *pcie, unsigned int value,
- unsigned int offset)
+void dbi_writel(struct ls_pcie *pcie, unsigned int value, unsigned int offset)
{
out_le32(pcie->dbi + offset, value);
}
-static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
+unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
{
if (pcie->big_endian)
return in_be32(pcie->ctrl + offset);
@@ -42,8 +38,8 @@ static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned
int offset)
return in_le32(pcie->ctrl + offset);
}
-static void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
- unsigned int offset)
+void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
+unsigned int offset)
{
if (pcie->big_endian)
out_be32(pcie->ctrl + offset, value);
@@ -51,6 +47,26 @@ static void ctrl_writel(struct ls_pcie *pcie, unsigned int
value,
out_le32(pcie->ctrl + offset, value);
}
+void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie)
+{
+ u32 reg, val;
+
+ reg = PCIE_MISC_CONTROL_1_OFF;
+ val = dbi_readl(pcie, reg);
+ val |= PCIE_DBI_RO_WR_EN;
+ dbi_writel(pcie, val, reg);
+}
+
+void ls_pcie_dbi_ro_wr_dis(struct ls_pcie *pcie)
+{
+ u32 reg, val;
+
+ reg = PCIE_MISC_CONTROL_1_OFF;
+ val = dbi_readl(pcie, reg);
+ val &= ~PCIE_DBI_RO_WR_EN;
+ dbi_writel(pcie, val, reg);
+}
+
static int ls_pcie_ltssm(struct ls_pcie *pcie)
{
u32 state;
@@ -67,7 +83,7 @@ static int ls_pcie_ltssm(struct ls_pcie *pcie)
return state;
}
-static int ls_pcie_link_up(struct ls_pcie *pcie)
+int ls_pcie_link_up(struct ls_pcie *pcie)
{
int ltssm;
@@ -78,22 +94,8 @@ static int ls_pcie_link_up(struct ls_pcie *pcie)
return 1;
}
-static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
-{
- dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_VIEWPORT);
- dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
-}
-
-static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
-{
- dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
- PCIE_ATU_VIEWPORT);
- dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
-}
-
-static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
- u64 phys, u64 bus_addr, pci_size_t size)
+void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
+ u64 phys, u64 bus_addr, pci_size_t size)
{
dbi_writel(pcie,
[PATCHv2 04/10] PCI_EP: layerscape: Add the multiple function support
From: Xiaowei Bao
Add the multiple function support for Layerscape platform, some PEXs
of Layerscaple platform have more than one PF.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
V2:
- Rebase the patch without change intent.
drivers/pci/pcie_layerscape.c| 6 +-
drivers/pci/pcie_layerscape.h| 21 --
drivers/pci/pcie_layerscape_ep.c | 119 +--
3 files changed, 98 insertions(+), 48 deletions(-)
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 93018feb7c..ea0fc43441 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -108,13 +108,13 @@ void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int
idx, int type,
}
/* Use bar match mode and MEM type as default */
-void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx, int type,
-int bar, u64 phys)
+void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, int type,
+int idx, int bar, u64 phys)
{
dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
- dbi_writel(pcie, type, PCIE_ATU_CR1);
+ dbi_writel(pcie, type | PCIE_ATU_FUNC_NUM(pf), PCIE_ATU_CR1);
dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
}
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 217dcda6d1..dabfff32db 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -9,6 +9,7 @@
#define _PCIE_LAYERSCAPE_H_
#include
#include
+#include
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
@@ -44,6 +45,7 @@
#define PCIE_ATU_TYPE_IO (0x2 << 0)
#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
+#define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)
#define PCIE_ATU_CR2 0x908
#define PCIE_ATU_ENABLE(0x1 << 31)
#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
@@ -86,11 +88,16 @@
#define FSL_PCIE_EP_MIN_APERTURE4096 /* 4 Kbytes */
#define PCIE_PF_NUM2
#define PCIE_VF_NUM64
+#define BAR_NUM4
-#define PCIE_BAR0_SIZE (4 * 1024) /* 4K */
-#define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */
-#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
-#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
+#define PCIE_BAR0_SIZE SZ_4K
+#define PCIE_BAR1_SIZE SZ_8K
+#define PCIE_BAR2_SIZE SZ_4K
+#define PCIE_BAR4_SIZE SZ_1M
+
+#define PCIE_SRIOV_VFBAR0 0x19C
+
+#define PCIE_MASK_OFFSET(flag, pf) ((flag) ? 0 : (0x1000 + 0x2 * (pf)))
/* LUT registers */
#define PCIE_LUT_UDR(n)(0x800 + (n) * 8)
@@ -158,6 +165,8 @@ struct ls_pcie_ep {
struct ls_pcie *pcie;
struct udevice *bus;
void __iomem *addr;
+ u32 cfg2_flag;
+ u32 sriov_flag;
u32 num_ib_wins;
u32 num_ob_wins;
u8 max_functions;
@@ -171,8 +180,8 @@ unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int
offset);
void ctrl_writel(struct ls_pcie *pcie, unsigned int value, unsigned int
offset);
void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
u64 phys, u64 bus_addr, pci_size_t size);
-void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx, int type,
-int bar, u64 phys);
+void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, int type,
+int idx, int bar, u64 phys);
void ls_pcie_dump_atu(struct ls_pcie *pcie);
int ls_pcie_link_up(struct ls_pcie *pcie);
void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie);
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index b463a7734a..e609607c3a 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -46,7 +46,7 @@ static int ls_ep_set_bar(struct udevice *dev, uint fn, struct
pci_bar *ep_bar)
else
type = PCIE_ATU_TYPE_IO;
- ls_pcie_atu_inbound_set(pcie, idx, bar, bar_phys, type);
+ ls_pcie_atu_inbound_set(pcie, fn, type, idx, bar, bar_phys);
dbi_writel(pcie, lower_32_bits(size - 1), reg + PCIE_NO_SRIOV_BAR_BASE);
dbi_writel(pcie, flags, reg);
@@ -64,51 +64,61 @@ static struct pci_ep_ops ls_pcie_ep_ops = {
.set_bar = ls_ep_set_bar,
};
-static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep)
+static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep, u32 pf)
{
struct ls_pcie *pcie = pcie_ep->pcie;
- u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
+ u64 phys = 0;
+ phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M;
+
+ phys =
[PATCHv2 02/10] pci_ep: Add the init function
From: Xiaowei Bao
Some EP deivces need to initialize before RC scan it, e.g. NXP
layerscape platform, so add the init function in pci_ep uclass.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
V2:
- Rebase the patch without change intent.
common/board_r.c | 12
drivers/pci_endpoint/pci_ep-uclass.c | 11 +++
include/init.h | 1 +
3 files changed, 24 insertions(+)
diff --git a/common/board_r.c b/common/board_r.c
index fa57fa9b69..d4db44fc59 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -233,6 +233,15 @@ static int initr_unlock_ram_in_cache(void)
}
#endif
+#ifdef CONFIG_PCI_ENDPOINT
+static int initr_pci_ep(void)
+{
+ pci_ep_init();
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_PCI
static int initr_pci(void)
{
@@ -830,6 +839,9 @@ static init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_BITBANGMII
initr_bbmii,
#endif
+#ifdef CONFIG_PCI_ENDPOINT
+ initr_pci_ep,
+#endif
#ifdef CONFIG_CMD_NET
INIT_FUNC_WATCHDOG_RESET
initr_net,
diff --git a/drivers/pci_endpoint/pci_ep-uclass.c
b/drivers/pci_endpoint/pci_ep-uclass.c
index 9f53a9a9b9..38a5f08376 100644
--- a/drivers/pci_endpoint/pci_ep-uclass.c
+++ b/drivers/pci_endpoint/pci_ep-uclass.c
@@ -209,3 +209,14 @@ UCLASS_DRIVER(pci_ep) = {
.name = "pci_ep",
.flags = DM_UC_FLAG_SEQ_ALIAS,
};
+
+void pci_ep_init(void)
+{
+ struct udevice *dev;
+
+ for (uclass_first_device_check(UCLASS_PCI_EP, );
+dev;
+uclass_next_device_check()) {
+ ;
+ }
+}
diff --git a/include/init.h b/include/init.h
index b5a167b6ed..2d79afc381 100644
--- a/include/init.h
+++ b/include/init.h
@@ -213,6 +213,7 @@ int set_cpu_clk_info(void);
int update_flash_size(int flash_size);
int arch_early_init_r(void);
void pci_init(void);
+void pci_ep_init(void);
int misc_init_r(void);
#if defined(CONFIG_VID)
int init_func_vid(void);
--
2.17.1
[PATCHv2 03/10] armv8: dts: ls1046a: Add the PCIe EP node
From: Xiaowei Bao
Add the PCIe EP node for ls1046a.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
V2:
- Rebase the patch without change intent.
arch/arm/dts/fsl-ls1046a.dtsi | 33 +
1 file changed, 33 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 8673a5db2a..3f11d6cd18 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -257,6 +257,17 @@
0x8200 0x0 0x4000 0x40 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
+ pcie_ep@340 {
+ compatible = "fsl,ls-pcie-ep";
+ reg = <0x00 0x0340 0x0 0x8
+ 0x00 0x034c 0x0 0x4
+ 0x40 0x 0x8 0x>;
+ reg-names = "regs", "ctrl", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ big-endian;
+ };
+
pcie@350 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x8 /* dbi registers */
@@ -274,6 +285,17 @@
0x8200 0x0 0x4000 0x48 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
+ pcie_ep@350 {
+ compatible = "fsl,ls-pcie-ep";
+ reg = <0x00 0x0350 0x0 0x8
+ 0x00 0x035c 0x0 0x4
+ 0x48 0x 0x8 0x>;
+ reg-names = "regs", "ctrl", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ big-endian;
+ };
+
pcie@360 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0360 0x0 0x8 /* dbi registers */
@@ -290,6 +312,17 @@
0x8200 0x0 0x4000 0x50 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
+ pcie_ep@360 {
+ compatible = "fsl,ls-pcie-ep";
+ reg = <0x00 0x0360 0x0 0x8
+ 0x00 0x036c 0x0 0x4
+ 0x50 0x 0x8 0x>;
+ reg-names = "regs", "ctrl", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ big-endian;
+ };
+
sata: sata@320 {
compatible = "fsl,ls1046a-ahci";
reg = <0x0 0x320 0x0 0x1 /* ccsr sata base */
--
2.17.1
[PATCHv2 00/10] pci: layerscape: Split EP mode code into a
From: Hou Zhiqiang Hou Zhiqiang (1): pci: layerscape: Add specific config entry for RC and EP mode driver Xiaowei Bao (9): pci: layerscape: Split the EP and RC driver pci_ep: Add the init function armv8: dts: ls1046a: Add the PCIe EP node PCI_EP: layerscape: Add the multiple function support pci_ep: layerscape: Add the workaround for errata A-009460 pci_ep: layerscape: Add Support for ls2085a and ls2080a EP mode pci_ep: layerscape: Add the SRIOV VFs of PF support pci: layerscaple: Modify the ls_pcie_dump_atu function pci_ep: layerscape: Add the PCIe EP mode support for lx2160a-v2 arch/arm/dts/fsl-ls1046a.dtsi | 33 ++ common/board_r.c | 12 + configs/ls1012afrdm_qspi_defconfig| 2 +- configs/ls1012afrdm_tfa_defconfig | 2 +- .../ls1012afrwy_qspi_SECURE_BOOT_defconfig| 2 +- configs/ls1012afrwy_qspi_defconfig| 2 +- configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012afrwy_tfa_defconfig | 2 +- configs/ls1012aqds_qspi_defconfig | 2 +- configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012aqds_tfa_defconfig | 2 +- configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1012ardb_qspi_defconfig | 2 +- configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012ardb_tfa_defconfig | 2 +- configs/ls1021aiot_qspi_defconfig | 2 +- configs/ls1021aiot_sdcard_defconfig | 2 +- configs/ls1021aqds_ddr4_nor_defconfig | 2 +- configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 2 +- configs/ls1021aqds_nand_defconfig | 2 +- configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 2 +- configs/ls1021aqds_nor_defconfig | 2 +- configs/ls1021aqds_nor_lpuart_defconfig | 2 +- configs/ls1021aqds_qspi_defconfig | 2 +- configs/ls1021aqds_sdcard_ifc_defconfig | 2 +- configs/ls1021aqds_sdcard_qspi_defconfig | 2 +- configs/ls1021atsn_qspi_defconfig | 2 +- configs/ls1021atsn_sdcard_defconfig | 2 +- configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 +- configs/ls1021atwr_nor_defconfig | 2 +- configs/ls1021atwr_nor_lpuart_defconfig | 2 +- configs/ls1021atwr_qspi_defconfig | 2 +- ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 +- configs/ls1021atwr_sdcard_ifc_defconfig | 2 +- configs/ls1021atwr_sdcard_qspi_defconfig | 2 +- configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1028aqds_tfa_defconfig | 2 +- configs/ls1028aqds_tfa_lpuart_defconfig | 2 +- configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1028ardb_tfa_defconfig | 2 +- configs/ls1043aqds_defconfig | 2 +- configs/ls1043aqds_lpuart_defconfig | 2 +- configs/ls1043aqds_nand_defconfig | 2 +- configs/ls1043aqds_nor_ddr3_defconfig | 2 +- configs/ls1043aqds_qspi_defconfig | 2 +- configs/ls1043aqds_sdcard_ifc_defconfig | 2 +- configs/ls1043aqds_sdcard_qspi_defconfig | 2 +- configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1043aqds_tfa_defconfig | 2 +- configs/ls1043ardb_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_defconfig | 2 +- configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_nand_defconfig | 2 +- .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_sdcard_defconfig | 2 +- configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_tfa_defconfig | 2 +- configs/ls1046afrwy_tfa_defconfig | 3 +- configs/ls1046aqds_SECURE_BOOT_defconfig | 3 +- configs/ls1046aqds_defconfig | 3 +- configs/ls1046aqds_lpuart_defconfig | 3 +- configs/ls1046aqds_nand_defconfig | 3 +- configs/ls1046aqds_qspi_defconfig | 3 +- configs/ls1046aqds_sdcard_ifc_defconfig | 3 +- configs/ls1046aqds_sdcard_qspi_defconfig | 3 +- configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 3 +- configs/ls1046aqds_tfa_defconfig | 3 +- configs/ls1046ardb_emmc_defconfig | 3 +- configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 3 +- configs/ls1046ardb_qspi_defconfig | 3 +- configs/ls1046ardb_qspi_spl_defconfig | 3 +- .../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 3 +- configs/ls1046ardb_sdcard_defconfig | 3 +- configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 3 +- configs/ls1046ardb_tfa_defconfig | 3 +- configs/ls1088aqds_defconfig | 2 +- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1088aqds_qspi_defconfig | 2 +- configs
[PATCHv4 16/16] configs: P2020RDB: Enable DM_ETH config
From: Hou Zhiqiang Enable the DM_ETH and DM_MDIO config. On P2020RDB, the eTSEC1 is connecting with a switch VSC7385, so also enable the fixed PHY support. Signed-off-by: Hou Zhiqiang Reviewed-by: Vladimir Oltean --- V4: - No change. configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_defconfig | 3 +++ configs/P2020RDB-PC_NAND_defconfig | 3 +++ configs/P2020RDB-PC_SDCARD_defconfig | 3 +++ configs/P2020RDB-PC_SPIFLASH_defconfig | 3 +++ configs/P2020RDB-PC_defconfig| 3 +++ 8 files changed, 24 insertions(+) diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 3e6ea64ee3..4cd689f55d 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -66,6 +66,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -77,8 +78,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 187cbee0d6..f46463a297 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -72,8 +73,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 88c9224001..73d1be1013 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -63,6 +63,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -74,8 +75,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 88e24c30ba..21a0e85f98 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -50,6 +50,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -61,8 +62,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index dda34dd43e..800c728ed3 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -65,6 +65,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -76,8 +77,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index c2b6ad5f32..81cbac2fe8 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -71,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 3ec208ee00..89308a503b 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -62,6 +62,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000
[PATCHv4 15/16] dts: powerpc: p2020rdb: Add eTSEC DT nodes
From: Hou Zhiqiang
P2020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang
---
V4:
- Remove the ptp_clock node.
- Modify the change log slightly.
arch/powerpc/dts/p2020-post.dtsi | 10 --
arch/powerpc/dts/p2020rdb-pc.dts | 1 +
arch/powerpc/dts/p2020rdb-pc.dtsi| 50
arch/powerpc/dts/p2020rdb-pc_36b.dts | 1 +
arch/powerpc/dts/pq3-etsec1-0.dtsi | 28
arch/powerpc/dts/pq3-etsec1-1.dtsi | 28
arch/powerpc/dts/pq3-etsec1-2.dtsi | 28
arch/powerpc/dts/pq3-etsec1-3.dtsi | 28
8 files changed, 172 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/dts/p2020rdb-pc.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-0.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-1.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-2.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-3.dtsi
diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index 4ed093dad4..f8549b7ddf 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -38,8 +38,12 @@
clock-frequency = <0>;
};
- /include/ "pq3-i2c-0.dtsi"
- /include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec1-0.dtsi"
+/include/ "pq3-etsec1-1.dtsi"
+/include/ "pq3-etsec1-2.dtsi"
};
/* PCIe controller base address 0x8000 */
diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts
index 08befd4c59..f3f6be1080 100644
--- a/arch/powerpc/dts/p2020rdb-pc.dts
+++ b/arch/powerpc/dts/p2020rdb-pc.dts
@@ -37,4 +37,5 @@
};
};
+/include/ "p2020rdb-pc.dtsi"
/include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/p2020rdb-pc.dtsi
b/arch/powerpc/dts/p2020rdb-pc.dtsi
new file mode 100644
index 00..0d2acc746e
--- /dev/null
+++ b/arch/powerpc/dts/p2020rdb-pc.dtsi
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ {
+ mdio@24520 {
+ phy0: ethernet-phy@0 {
+ interrupts = <3 1 0 0>;
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy@1 {
+ interrupts = <2 1 0 0>;
+ reg = <0x1>;
+ };
+ };
+
+ mdio@25520 {
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ mdio@26520 {
+ status = "disabled";
+ };
+
+ enet0: ethernet@24000 {
+ phy-connection-type = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ enet1: ethernet@25000 {
+ tbi-handle = <>;
+ phy-handle = <>;
+ phy-connection-type = "sgmii";
+ };
+
+ enet2: ethernet@26000 {
+ phy-handle = <>;
+ phy-connection-type = "rgmii-id";
+ };
+};
diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts
b/arch/powerpc/dts/p2020rdb-pc_36b.dts
index 04b2519e1a..6d983b7d71 100644
--- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
@@ -37,4 +37,5 @@
};
};
+/include/ "p2020rdb-pc.dtsi"
/include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/pq3-etsec1-0.dtsi
b/arch/powerpc/dts/pq3-etsec1-0.dtsi
new file mode 100644
index 00..8800243f34
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-0.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ fsl,magic-packet;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
+};
+
+mdio@24520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x24520 0x20>;
+};
diff --git a/arch/powerpc/dts/pq3-etsec1-1.dtsi
b/arch/powerpc/dts/pq3-etsec1-1.dtsi
new file mode 100644
index 00..2bc62d1a57
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-1.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub
[PATCHv4 14/16] configs: P1010RDB: Enable DM_ETH config
From: Hou Zhiqiang Enable the DM_ETH and DM_MDIO config. Signed-off-by: Hou Zhiqiang --- V4: - No change. configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PA_NAND_defconfig | 2 ++ configs/P1010RDB-PA_NOR_defconfig| 2 ++ configs/P1010RDB-PA_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PB_NAND_defconfig | 2 ++ configs/P1010RDB-PB_NOR_defconfig| 2 ++ configs/P1010RDB-PB_SDCARD_defconfig | 2 ++ configs/P1010RDB-PB_SPIFLASH_defconfig | 2 ++ 16 files changed, 32 insertions(+) diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index da04cab014..bd31e7c8fa 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -72,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index e6edd395e7..f5c5f0ead5 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -54,8 +54,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index dcd606b0c2..229365a1eb 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -66,8 +66,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index c0800c8d7d..147198fb88 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -68,8 +68,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index 29ba692ca1..1f2472a338 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -71,8 +71,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index d8f87b5dac..35232a87fc 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -53,8 +53,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 9711082529..6a46e3a253 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -65,8 +65,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index de2ac2235f..6c7c12efc1 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -67,8 +67,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 9f4876dd13..832f7ce431 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -72,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y
[PATCHv4 11/16] configs: P1020RDB: Enable DM_ETH config
From: Hou Zhiqiang Enable the DM_ETH and DM_MDIO config. On P1020RDB, the eTSEC1 is connecting with a switch VSC7385, so also enable the fixed PHY support. Signed-off-by: Hou Zhiqiang --- V4: - No change. configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_defconfig | 3 +++ configs/P1020RDB-PC_NAND_defconfig | 3 +++ configs/P1020RDB-PC_SDCARD_defconfig | 3 +++ configs/P1020RDB-PC_SPIFLASH_defconfig | 3 +++ configs/P1020RDB-PC_defconfig| 3 +++ configs/P1020RDB-PD_NAND_defconfig | 3 +++ configs/P1020RDB-PD_SDCARD_defconfig | 3 +++ configs/P1020RDB-PD_SPIFLASH_defconfig | 3 +++ configs/P1020RDB-PD_defconfig| 3 +++ 12 files changed, 36 insertions(+) diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 6ee52fe5e7..139a0be37e 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -72,8 +73,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 489b91d8e7..f533225f26 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -56,6 +56,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -67,8 +68,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 4a8e4e3726..f3e87f0669 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -58,6 +58,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -69,8 +70,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index f9a4b735ca..04c355585d 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -45,6 +45,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -56,8 +57,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 5c8231cba2..ee663c5861 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -71,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index ad2bb90a49..cabd6c6022 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -55,6 +55,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=1000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -66,8 +67,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index b8055e49b0..28a097b0ed 100644 ---
[PATCHv4 12/16] dts: powerpc: p1010rdb: Add eTSEC DT nodes
From: Hou Zhiqiang
P1010RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII PHY AR8033
eTSEC2: Connected to SGMII PHY AR8033
eTSEC3: Connected to SGMII PHY AR8033
Signed-off-by: Hou Zhiqiang
---
V4:
- Remove the ptp_clock node.
arch/powerpc/dts/p1010rdb-pa.dts | 1 +
arch/powerpc/dts/p1010rdb-pa_36b.dts | 1 +
arch/powerpc/dts/p1010rdb.dtsi | 50
arch/powerpc/dts/p1010si-post.dtsi | 25 ++
4 files changed, 77 insertions(+)
diff --git a/arch/powerpc/dts/p1010rdb-pa.dts b/arch/powerpc/dts/p1010rdb-pa.dts
index c66c4923ac..360d254d91 100644
--- a/arch/powerpc/dts/p1010rdb-pa.dts
+++ b/arch/powerpc/dts/p1010rdb-pa.dts
@@ -15,3 +15,4 @@
};
/include/ "p1010si-post.dtsi"
+/include/ "p1010rdb.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb-pa_36b.dts
b/arch/powerpc/dts/p1010rdb-pa_36b.dts
index b943de7cbb..062086a8c0 100644
--- a/arch/powerpc/dts/p1010rdb-pa_36b.dts
+++ b/arch/powerpc/dts/p1010rdb-pa_36b.dts
@@ -15,3 +15,4 @@
};
/include/ "p1010si-post.dtsi"
+/include/ "p1010rdb.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb.dtsi b/arch/powerpc/dts/p1010rdb.dtsi
index 4f58ee2446..5964270878 100644
--- a/arch/powerpc/dts/p1010rdb.dtsi
+++ b/arch/powerpc/dts/p1010rdb.dtsi
@@ -5,6 +5,56 @@
* Copyright 2020 NXP
*/
{
+ mdio@24000 {
+ phy0: ethernet-phy@0 {
+ reg = <0x1>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <0x0>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ tbi-phy@3 {
+ device_type = "tbi-phy";
+ reg = <0x3>;
+ };
+ };
+
+ mdio@25000 {
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ mdio@26000 {
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet0: ethernet@b {
+ phy-handle = <>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ enet1: ethernet@b1000 {
+ phy-handle = <>;
+ tbi-handle = <>;
+ phy-connection-type = "sgmii";
+ };
+
+ enet2: ethernet@b2000 {
+ phy-handle = <>;
+ tbi-handle = <>;
+ phy-connection-type = "sgmii";
+ };
+
i2c@3000 {
rtc@68 {
compatible = "pericom,pt7c4338";
diff --git a/arch/powerpc/dts/p1010si-post.dtsi
b/arch/powerpc/dts/p1010si-post.dtsi
index 0289441381..f825208056 100644
--- a/arch/powerpc/dts/p1010si-post.dtsi
+++ b/arch/powerpc/dts/p1010si-post.dtsi
@@ -25,6 +25,31 @@
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec2-0.dtsi"
+ enet0: ethernet@b {
+ queue-group@b {
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ };
+ };
+
+/include/ "pq3-etsec2-1.dtsi"
+ enet1: ethernet@b1000 {
+ queue-group@b1000 {
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ };
+ };
+
+/include/ "pq3-etsec2-2.dtsi"
+ enet2: ethernet@b2000 {
+ queue-group@b2000 {
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ };
+
+ };
};
/* controller at 0x9000 */
--
2.25.1
[PATCHv4 13/16] powerpc: p1010rdb: Compile legacy ethernet init function when no DM_ETH
From: Hou Zhiqiang
The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang
---
V4:
- No change.
board/freescale/p1010rdb/p1010rdb.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/p1010rdb/p1010rdb.c
b/board/freescale/p1010rdb/p1010rdb.c
index 66ccc0bd1e..309f4daa88 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -484,6 +484,7 @@ int checkboard(void)
return 0;
}
+#ifndef CONFIG_DM_ETH
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
@@ -524,6 +525,7 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);
}
+#endif
#if defined(CONFIG_OF_BOARD_SETUP)
void fdt_del_flexcan(void *blob)
--
2.25.1
