from:"Zong Li"

[PATCH 2/2] riscv: cache: support cache enable in SPL stage

2023-12-14 Thread Zong Li

The power gating feature of pl2 should be enabled as early as possible,
it would be better to put it in SPL stage.

Signed-off-by: Zong Li 
---
 arch/riscv/lib/sifive_cache.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c
index 39b0248c32..d8fe1dfa95 100644
--- a/arch/riscv/lib/sifive_cache.c
+++ b/arch/riscv/lib/sifive_cache.c
@@ -7,7 +7,10 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
+#ifndef CONFIG_SPL_BUILD
 void enable_caches(void)
 {
struct udevice *dev;
@@ -25,3 +28,21 @@ void enable_caches(void)
log_debug("ccache enable failed");
}
 }
+#else
+static inline void probe_cache_device(struct driver *driver, struct udevice 
*dev)
+{
+   for (uclass_find_first_device(UCLASS_CACHE, );
+dev;
+uclass_find_next_device()) {
+   if (dev->driver == driver)
+   device_probe(dev);
+   }
+}
+
+void enable_caches(void)
+{
+   struct udevice *dev = NULL;
+
+   probe_cache_device(DM_DRIVER_GET(sifive_pl2), dev);
+}
+#endif /* !CONFIG_SPL_BUILD */
-- 
2.17.1

[PATCH 0/2] Add SiFive private L2 cache driver

2023-12-14 Thread Zong Li

SiFive private L2 cache is per core cache, add this driver to control
its features by a MMIO register. In this series, we try to enable the
power gating feature of pL2 cache in SPL stage

Zong Li (2):
  cache: add sifive private L2 cache driver
  riscv: cache: support cache enable in SPL stage

 arch/riscv/lib/sifive_cache.c| 21 +++
 drivers/cache/Kconfig|  7 +
 drivers/cache/Makefile   |  1 +
 drivers/cache/cache-sifive-pl2.c | 44 
 4 files changed, 73 insertions(+)
 create mode 100644 drivers/cache/cache-sifive-pl2.c

-- 
2.17.1

[PATCH 1/2] cache: add sifive private L2 cache driver

2023-12-14 Thread Zong Li

This driver is currently responsible for enabling the clock gating
feature of SiFive pre core's private L2 cache.

Signed-off-by: Zong Li 
---
 drivers/cache/Kconfig|  7 +
 drivers/cache/Makefile   |  1 +
 drivers/cache/cache-sifive-pl2.c | 44 
 3 files changed, 52 insertions(+)
 create mode 100644 drivers/cache/cache-sifive-pl2.c

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 6cb8c3e980..26c2d80a1c 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -45,4 +45,11 @@ config SIFIVE_CCACHE
  This driver is for SiFive Composable L2/L3 cache. It enables cache
  ways of composable cache.
 
+config SIFIVE_PL2
+   bool "SiFive private L2 cache"
+   select CACHE
+   help
+ This driver is for SiFive Private L2 cache. It configures registers
+ to enable the clock gating feature.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index ad765774e3..78e673d09e 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
 obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
 obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
 obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o
+obj-$(CONFIG_SIFIVE_PL2) += cache-sifive-pl2.o
diff --git a/drivers/cache/cache-sifive-pl2.c b/drivers/cache/cache-sifive-pl2.c
new file mode 100644
index 00..ae689e18ed
--- /dev/null
+++ b/drivers/cache/cache-sifive-pl2.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 SiFive
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#defineSIFIVE_PL2CHICKENBIT_OFFSET 0x1000
+#defineSIFIVE_PL2CHICKENBIT_REGIONCLOCKDISABLE_MASKBIT(3)
+
+static int sifive_pl2_probe(struct udevice *dev)
+{
+   fdt_addr_t base;
+   u32 val;
+
+   base = dev_read_addr(dev);
+   if (base == FDT_ADDR_T_NONE)
+   return -EINVAL;
+
+   /* Enable regionClockDisable bit */
+   val = readl((void __iomem *)(base + SIFIVE_PL2CHICKENBIT_OFFSET));
+   writel(val & ~SIFIVE_PL2CHICKENBIT_REGIONCLOCKDISABLE_MASK,
+  (void __iomem *)(base + SIFIVE_PL2CHICKENBIT_OFFSET));
+
+   return 0;
+}
+
+static const struct udevice_id sifive_pl2_ids[] = {
+   { .compatible = "sifive,pl2cache0" },
+   { .compatible = "sifive,pl2cache1" },
+   {}
+};
+
+U_BOOT_DRIVER(sifive_pl2) = {
+   .name = "sifive_pl2",
+   .id = UCLASS_CACHE,
+   .of_match = sifive_pl2_ids,
+   .probe = sifive_pl2_probe,
+};
-- 
2.17.1

Re: Docs for RISC-V

2023-02-23 Thread Zong Li

On Mon, Feb 6, 2023 at 3:58 PM Leo Liang  wrote:
>
> Hi Simon,
>
> On Thu, Feb 02, 2023 at 10:25:36AM -0700, Simon Glass wrote:
> > Hi,
> >
> > On Thu, 2 Feb 2023 at 10:18, Simon Glass  wrote:
> > >
> > > Hi Rick & Leo,
> > >
> > > I see docs for one board at [1] but I'm not sure what to do with 
> > > unleashed.
> > >
> > > It seems to need a 'genimage' tool, going on what I see in CI.
> > >
>
> It does seem like that accroding to "sifive_unleashed_sdcard test.py".
> (https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/568342)
>
> > > Could you adjust it to use binman to output an image suitable for
> > > writing to an SD card in a single 'dd' step, as Rockchip does?
> > >
>
> I think I will both take a look at it and forward this message to guys at 
> sifive.

Add Nylon in this thread.

Hi Nylon, I think you took some time to take a look at this, do you
have any idea about that? Thanks.

>
> > > Also, how about adding a RISC-V section here?
> > >
> > > https://u-boot.readthedocs.io/en/latest/arch/index.html
> > >
>
> Sounds great!
> I will reference what other architectures have and create a RISC-V section.
>
> >
> > Also I notice that this is incorrect:
> >
> > https://u-boot.readthedocs.io/en/latest/board/sifive/unleashed.html?highlight=fw_dynamic.bin
> >
> > since 'make PLATFORM=generic' gives errors. I think it needs CROSS_COMPILE
> >
>
> There is already an 'export CROSS_COMPILE' in the previous "building" section
> before 'make PLATFROM=generic', so I guess that is why CROSS_COMPILE is 
> omitted in make command.
>
> > One other thing...binman output is this:
> >
> > binman: Filename 'fw_dynamic.bin' not found in input path (...)
> >
> > You should add something to tools/binman/missing-blob-help so that it
> > tells the user where to find the blob.
> >
>
> Same as the above, I will forward this to guys at sifive to see what they 
> would like to do.
>
>
> Thanks for all the catches!
> Best regards,
> Leo
>
> > Thanks again,
> > Simon
> >
> > > Thanks,
> > > Simon
> > >
> > > [1] https://u-boot.readthedocs.io/en/latest/board/sifive/unmatched.html

Re: Docs for RISC-V

2023-02-08 Thread Zong Li

On Wed, Feb 8, 2023 at 4:07 PM Rick Chen  wrote:
>
> Hi Zong,
>
> > From: Leo Yu-Chi Liang(梁育齊) 
> > Sent: Monday, February 06, 2023 3:58 PM
> > To: Simon Glass 
> > Cc: U-Boot Mailing List ; Rick Jian-Zhi Chen(陳建志) 
> > ; zong...@sifive.com; vincent.c...@sifive.com
> > Subject: Re: Docs for RISC-V
> >
> > Hi Simon,
> >
> > On Thu, Feb 02, 2023 at 10:25:36AM -0700, Simon Glass wrote:
> > > Hi,
> > >
> > > On Thu, 2 Feb 2023 at 10:18, Simon Glass  wrote:
> > > >
> > > > Hi Rick & Leo,
> > > >
> > > > I see docs for one board at [1] but I'm not sure what to do with 
> > > > unleashed.
> > > >
> > > > It seems to need a 'genimage' tool, going on what I see in CI.
>
> Would you please take a look at this item ?

Hi Rick,
No problem, let me take a look at it, and give you all some feedback
later. Thanks.

>
> Thanks,
> Rick
>
> > > >
> >
> > It does seem like that accroding to "sifive_unleashed_sdcard test.py".
> > (https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/568342)
> >
> > > > Could you adjust it to use binman to output an image suitable for
> > > > writing to an SD card in a single 'dd' step, as Rockchip does?
> > > >
> >
> > I think I will both take a look at it and forward this message to guys at 
> > sifive.
> >
> > > > Also, how about adding a RISC-V section here?
> > > >
> > > > https://u-boot.readthedocs.io/en/latest/arch/index.html
> > > >
> >
> > Sounds great!
> > I will reference what other architectures have and create a RISC-V section.
> >
> > >
> > > Also I notice that this is incorrect:
> > >
> > > https://u-boot.readthedocs.io/en/latest/board/sifive/unleashed.html?hi
> > > ghlight=fw_dynamic.bin
> > >
> > > since 'make PLATFORM=generic' gives errors. I think it needs
> > > CROSS_COMPILE
> > >
> >
> > There is already an 'export CROSS_COMPILE' in the previous "building" 
> > section before 'make PLATFROM=generic', so I guess that is why 
> > CROSS_COMPILE is omitted in make command.
> >
> > > One other thing...binman output is this:
> > >
> > > binman: Filename 'fw_dynamic.bin' not found in input path (...)
> > >
> > > You should add something to tools/binman/missing-blob-help so that it
> > > tells the user where to find the blob.
> > >
> >
> > Same as the above, I will forward this to guys at sifive to see what they 
> > would like to do.
> >
> >
> > Thanks for all the catches!
> > Best regards,
> > Leo
> >
> > > Thanks again,
> > > Simon
> > >
> > > > Thanks,
> > > > Simon
> > > >
> > > > [1]
> > > > https://u-boot.readthedocs.io/en/latest/board/sifive/unmatched.html

Re: [PATCH] riscv: use imply instead of select for SPL_SEPARATE_BSS

2022-11-28 Thread Zong Li

On Mon, Nov 21, 2022 at 8:17 PM Zong Li  wrote:
>
> On Mon, Nov 21, 2022 at 12:00 PM Sean Anderson  wrote:
> >
> > On 11/16/22 02:08, Zong Li wrote:
> > > Use imply instead of select, then it can still be disabled by
> > > board-specific defconfig, or be set to n manually.
> > >
> > > Signed-off-by: Zong Li 
> > > ---
> > >   arch/Kconfig | 2 +-
> > >   1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/arch/Kconfig b/arch/Kconfig
> > > index ae39716697..102956d24c 100644
> > > --- a/arch/Kconfig
> > > +++ b/arch/Kconfig
> > > @@ -111,7 +111,7 @@ config RISCV
> > >   select SUPPORT_OF_CONTROL
> > >   select OF_CONTROL
> > >   select DM
> > > - select SPL_SEPARATE_BSS if SPL
> > > + imply SPL_SEPARATE_BSS if SPL
> > >   imply DM_SERIAL
> > >   imply DM_ETH
> > >   imply DM_EVENT
> >
> > Do you have an example of a board which does this?
> >
>
> Hi Sean,
> We'd like to disable 'SPL_SEPARATE_BSS' on our internal platforms that
> don't exist in the mainline. It seems to me that using 'imply' might
> be not only working on the mainline's board, but also making it
> flexible to disable 'SPL_SEPARATE_BSS' by board-specific configuration
> or disable it manually for debug purposes. Hope the idea is good to
> you all. Thanks
>

Hi all,
Thanks for your reviewing, could I know whether this patch makes sense to you?

> > --Sean

Re: [PATCH] riscv: use imply instead of select for SPL_SEPARATE_BSS

2022-11-21 Thread Zong Li

On Mon, Nov 21, 2022 at 12:00 PM Sean Anderson  wrote:
>
> On 11/16/22 02:08, Zong Li wrote:
> > Use imply instead of select, then it can still be disabled by
> > board-specific defconfig, or be set to n manually.
> >
> > Signed-off-by: Zong Li 
> > ---
> >   arch/Kconfig | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/Kconfig b/arch/Kconfig
> > index ae39716697..102956d24c 100644
> > --- a/arch/Kconfig
> > +++ b/arch/Kconfig
> > @@ -111,7 +111,7 @@ config RISCV
> >   select SUPPORT_OF_CONTROL
> >   select OF_CONTROL
> >   select DM
> > - select SPL_SEPARATE_BSS if SPL
> > + imply SPL_SEPARATE_BSS if SPL
> >   imply DM_SERIAL
> >   imply DM_ETH
> >   imply DM_EVENT
>
> Do you have an example of a board which does this?
>

Hi Sean,
We'd like to disable 'SPL_SEPARATE_BSS' on our internal platforms that
don't exist in the mainline. It seems to me that using 'imply' might
be not only working on the mainline's board, but also making it
flexible to disable 'SPL_SEPARATE_BSS' by board-specific configuration
or disable it manually for debug purposes. Hope the idea is good to
you all. Thanks

> --Sean

[PATCH] riscv: use imply instead of select for SPL_SEPARATE_BSS

2022-11-15 Thread Zong Li

Use imply instead of select, then it can still be disabled by
board-specific defconfig, or be set to n manually.

Signed-off-by: Zong Li 
---
 arch/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/Kconfig b/arch/Kconfig
index ae39716697..102956d24c 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -111,7 +111,7 @@ config RISCV
select SUPPORT_OF_CONTROL
select OF_CONTROL
select DM
-   select SPL_SEPARATE_BSS if SPL
+   imply SPL_SEPARATE_BSS if SPL
imply DM_SERIAL
imply DM_ETH
imply DM_EVENT
-- 
2.17.1

Re: [PATCH 1/3] treewide: Remove OF_PRIOR_STAGE from RISC-V boards

2021-09-29 Thread Zong Li

On Wed, Sep 29, 2021 at 6:17 PM Ilias Apalodimas
 wrote:
>
> On Wed, Sep 29, 2021 at 12:02:16PM +0300, Ilias Apalodimas wrote:
> > Hi Zong,
> >
> > [...]
> >
> > > > diff --git a/board/sifive/unleashed/unleashed.c 
> > > > b/board/sifive/unleashed/unleashed.c
> > > > index 8cd514df3005..7e89c3f740a7 100644
> > > > --- a/board/sifive/unleashed/unleashed.c
> > > > +++ b/board/sifive/unleashed/unleashed.c
> > > > @@ -116,12 +116,10 @@ int misc_init_r(void)
> > > >
> > > >  void *board_fdt_blob_setup(void)
> > > >  {
> > > > -   if (IS_ENABLED(CONFIG_OF_SEPARATE)) {
> > > > -   if (gd->arch.firmware_fdt_addr)
> > > > -   return (ulong *)gd->arch.firmware_fdt_addr;
> > > > -   else
> > > > -   return (ulong *)&_end;
> > > > -   }
> > > > +   if (gd->arch.firmware_fdt_addr)
> > > > +   return (void *)gd->arch.firmware_fdt_addr;
> > > > +   else
> > > > +   return (void *)&_end;
> > > >  }
> > >
> > > I was wondering if we need to check CONFIG_OF_BOARD here? I'm not sure
> > > whether we should distinguish the value of a1 register which is
> > > meaningless. It means that if we don't expect the device tree to be
> > > passed by prior stage, then the a1 register might be a trash value at
> > > the beginning, so it would still return the arch.firmware_fdt_addr
> > > here, rather than _end.
> >
> > I thought about it as well.  Those boards were configured up to now with
> > 'CONFIG_OF_SEPARATE'.  Which means we are looking at an existing issue?
> > IOW the device tree was passed as part of U-Boot,  which would mean a1 would
> > have had thrash as well.  Maybe a1 always has a valid DT on those boards
> > so we never noticed?
> >
> >
> > > And do you think that we should enable the
> > > CONFIG_OF_BOARD for unmatched and unleashed? Because it seems to me
> > > that we actually pass the device tree by prior stage (i.e. OpenSBI).
> >
> > Yes in that case what you request makes sense for unmatched/unleashed.
> > Return gd->arch.firmware_fdt_addr in OF_BOARD is selected otherwise return
> > _end (instead of the current check).
> > If that sounds good to you I'll send a v2
>
> Looking a bit more at it...
> Apparently those boards boot from SPL.  So it's SPL->OpenSBI->U-Boot.
> By having the config as OF_SEPARATE the *U-Boot* DTB is used. SPL passes it to
> OpenSBI and OpenSBI passes it on a1 to U-Boot proper.  That's why the register
> reading works for that config.
>
> In that case the pre-existing code is 'wrong' as well,  since the DTB is
> not at _end,  but the bogus path is never taken...
> (check the __weak board_fdt_blob_setup for details).
>

If I remember correctly, the SPL would calculate the size of u-boot
proper, and then put the DTB at the end of  u-boot proper, so the DTB
would fortuitously be put at the _end location.

> So I think I'll send a v2, keeping the config as-is and fixing the return
> address of the DTB in case OF_BOARD is ever selected.
>

Yes, it seems to me that we could use a config to separate the case
between the prior stage and the _end. Just note that, there is a patch
on the fly, it modifies the same snippet of code, you might need to
update your code based on top of it.
https://lists.denx.de/pipermail/u-boot/2021-September/460378.html

> Cheers
> /Ilias
> >
> > [...]
> >
> > Regards
> > /Ilias

Re: [PATCH 1/3] treewide: Remove OF_PRIOR_STAGE from RISC-V boards

2021-09-29 Thread Zong Li

On Mon, Sep 27, 2021 at 2:48 PM Ilias Apalodimas
 wrote:
>
> At some point back in 2018 prior_stage_fdt_address and OF_PRIOR_STAGE got
> introduced,  in order to support a DTB handed over by an earlier stage boo
> loader.  However we have another option in the Kconfig (OF_BOARD) which has
> identical semantics.
>
> On RISC-V boards which during their startup,  some of the platforms, pick
> up the DTB from a1 and copy it in their private gd_t.  Apart from that they
> copy it to prior_stage_fdt_address,  if the Kconfig option is selected,
> which is unnecessary.
>
> So let's switch the config option for those boards to OF_BOARD and define
> the required board_fdt_blob_setup() for them.
>
> Signed-off-by: Ilias Apalodimas 
> ---
>  arch/riscv/cpu/cpu.c|  3 ---
>  arch/riscv/cpu/start.S  |  5 -
>  arch/riscv/dts/binman.dtsi  |  6 +++---
>  board/AndesTech/ax25-ae350/ax25-ae350.c |  1 -
>  board/emulation/qemu-riscv/qemu-riscv.c |  9 +
>  board/sifive/unleashed/unleashed.c  | 10 --
>  board/sifive/unmatched/unmatched.c  | 10 --
>  configs/ae350_rv32_defconfig|  2 +-
>  configs/ae350_rv32_spl_defconfig|  2 +-
>  configs/ae350_rv64_defconfig|  2 +-
>  configs/ae350_rv64_spl_defconfig|  2 +-
>  configs/qemu-riscv32_defconfig  |  2 +-
>  configs/qemu-riscv32_smode_defconfig|  2 +-
>  configs/qemu-riscv32_spl_defconfig  |  2 +-
>  configs/qemu-riscv64_defconfig  |  2 +-
>  configs/qemu-riscv64_smode_defconfig|  2 +-
>  configs/qemu-riscv64_spl_defconfig  |  2 +-
>  dts/Kconfig |  2 +-
>  18 files changed, 31 insertions(+), 35 deletions(-)
>
> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> index c894ac10b536..e16f1df30254 100644
> --- a/arch/riscv/cpu/cpu.c
> +++ b/arch/riscv/cpu/cpu.c
> @@ -16,9 +16,6 @@
>   * The variables here must be stored in the data section since they are used
>   * before the bss section is available.
>   */
> -#ifdef CONFIG_OF_PRIOR_STAGE
> -phys_addr_t prior_stage_fdt_address __section(".data");
> -#endif
>  #ifndef CONFIG_XIP
>  u32 hart_lottery __section(".data") = 0;
>
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index 308b0a97a58f..76850ec9be2c 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -142,11 +142,6 @@ call_harts_early_init:
> bneztp, secondary_hart_loop
>  #endif
>
> -#ifdef CONFIG_OF_PRIOR_STAGE
> -   la  t0, prior_stage_fdt_address
> -   SREGs1, 0(t0)
> -#endif
> -
> jal board_init_f_init_reserve
>
> SREGs1, GD_FIRMWARE_FDT_ADDR(gp)
> diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
> index d26cfdb78a9e..5757ef65ea4b 100644
> --- a/arch/riscv/dts/binman.dtsi
> +++ b/arch/riscv/dts/binman.dtsi
> @@ -48,7 +48,7 @@
> };
> };
>
> -#ifndef CONFIG_OF_PRIOR_STAGE
> +#ifndef CONFIG_OF_BOARD
> @fdt-SEQ {
> description = "NAME";
> type = "flat_dt";
> @@ -60,7 +60,7 @@
> configurations {
> default = "conf-1";
>
> -#ifndef CONFIG_OF_PRIOR_STAGE
> +#ifndef CONFIG_OF_BOARD
> @conf-SEQ {
>  #else
> conf-1 {
> @@ -68,7 +68,7 @@
> description = "NAME";
> firmware = "opensbi";
> loadables = "uboot";
> -#ifndef CONFIG_OF_PRIOR_STAGE
> +#ifndef CONFIG_OF_BOARD
> fdt = "fdt-SEQ";
>  #endif
> };
> diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c 
> b/board/AndesTech/ax25-ae350/ax25-ae350.c
> index 81b0ee992372..4f03806272df 100644
> --- a/board/AndesTech/ax25-ae350/ax25-ae350.c
> +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
> @@ -21,7 +21,6 @@
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> -extern phys_addr_t prior_stage_fdt_address;
>  /*
>   * Miscellaneous platform dependent initializations
>   */
> diff --git a/board/emulation/qemu-riscv/qemu-riscv.c 
> b/board/emulation/qemu-riscv/qemu-riscv.c
> index dcfd3f20bee6..aa91ca91325c 100644
> --- a/board/emulation/qemu-riscv/qemu-riscv.c
> +++ b/board/emulation/qemu-riscv/qemu-riscv.c
> @@ -14,6 +14,8 @@
>  #include 
>  #include 
>
> +DECLARE_GLOBAL_DATA_PTR;
> +
>  int board_init(void)
>  {
> /*
> @@ -69,3 +71,10 @@ int board_fit_config_name_match(const char *name)
> return 0;
>  }
>  #endif
> +
> +void *board_fdt_blob_setup(void)
> +{
> +   /* Stored the DTB address there during our init */
> +   return (void *)gd->arch.firmware_fdt_addr;
> +}
> +
> diff --git a/board/sifive/unleashed/unleashed.c 
> b/board/sifive/unleashed/unleashed.c

[PATCH v5 4/5] board: sifive: use ccache driver instead of helper function

2021-09-01 Thread Zong Li

Invokes the common cache_init function to initialize ccache.

Signed-off-by: Zong Li 
Reviewed-by: Sean Anderson 
---
 arch/riscv/cpu/fu540/Kconfig  |  2 +
 arch/riscv/cpu/fu540/Makefile |  1 -
 arch/riscv/cpu/fu540/cache.c  | 55 ---
 arch/riscv/cpu/fu740/Kconfig  |  2 +
 arch/riscv/cpu/fu740/Makefile |  1 -
 arch/riscv/cpu/fu740/cache.c  | 55 ---
 arch/riscv/include/asm/arch-fu540/cache.h | 14 --
 arch/riscv/include/asm/arch-fu740/cache.h | 14 --
 board/sifive/unleashed/unleashed.c| 10 +
 board/sifive/unmatched/unmatched.c| 11 ++---
 10 files changed, 9 insertions(+), 156 deletions(-)
 delete mode 100644 arch/riscv/cpu/fu540/cache.c
 delete mode 100644 arch/riscv/cpu/fu740/cache.c
 delete mode 100644 arch/riscv/include/asm/arch-fu540/cache.h
 delete mode 100644 arch/riscv/include/asm/arch-fu740/cache.h

diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
index 05463b2625..1604b412b4 100644
--- a/arch/riscv/cpu/fu540/Kconfig
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -19,6 +19,8 @@ config SIFIVE_FU540
imply SMP
imply CLK_SIFIVE
imply CLK_SIFIVE_PRCI
+   imply SIFIVE_CACHE
+   imply SIFIVE_CCACHE
imply SIFIVE_SERIAL
imply MACB
imply MII
diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile
index 088205ef57..043fb961a5 100644
--- a/arch/riscv/cpu/fu540/Makefile
+++ b/arch/riscv/cpu/fu540/Makefile
@@ -8,5 +8,4 @@ obj-y += spl.o
 else
 obj-y += dram.o
 obj-y += cpu.o
-obj-y += cache.o
 endif
diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c
deleted file mode 100644
index 0fc4ef6c00..00
--- a/arch/riscv/cpu/fu540/cache.c
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020 SiFive, Inc
- *
- * Authors:
- *   Pragnesh Patel 
- */
-
-#include 
-#include 
-#include 
-#include 
-
-/* Register offsets */
-#define L2_CACHE_CONFIG0x000
-#define L2_CACHE_ENABLE0x008
-
-#define MASK_NUM_WAYS  GENMASK(15, 8)
-#define NUM_WAYS_SHIFT 8
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int cache_enable_ways(void)
-{
-   const void *blob = gd->fdt_blob;
-   int node;
-   fdt_addr_t base;
-   u32 config;
-   u32 ways;
-
-   volatile u32 *enable;
-
-   node = fdt_node_offset_by_compatible(blob, -1,
-"sifive,fu540-c000-ccache");
-
-   if (node < 0)
-   return node;
-
-   base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
-   NULL, false);
-   if (base == FDT_ADDR_T_NONE)
-   return FDT_ADDR_T_NONE;
-
-   config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
-   ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
-
-   enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
-
-   /* memory barrier */
-   mb();
-   (*enable) = ways - 1;
-   /* memory barrier */
-   mb();
-   return 0;
-}
diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
index 408195f149..049a0a0584 100644
--- a/arch/riscv/cpu/fu740/Kconfig
+++ b/arch/riscv/cpu/fu740/Kconfig
@@ -19,6 +19,8 @@ config SIFIVE_FU740
imply SMP
imply CLK_SIFIVE
imply CLK_SIFIVE_PRCI
+   imply SIFIVE_CACHE
+   imply SIFIVE_CCACHE
imply SIFIVE_SERIAL
imply MACB
imply MII
diff --git a/arch/riscv/cpu/fu740/Makefile b/arch/riscv/cpu/fu740/Makefile
index 5ef8ac18a7..1d1ad98ba7 100644
--- a/arch/riscv/cpu/fu740/Makefile
+++ b/arch/riscv/cpu/fu740/Makefile
@@ -8,5 +8,4 @@ obj-y += spl.o
 else
 obj-y += dram.o
 obj-y += cpu.o
-obj-y += cache.o
 endif
diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c
deleted file mode 100644
index 680955c9e3..00
--- a/arch/riscv/cpu/fu740/cache.c
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020-2021 SiFive, Inc
- *
- * Authors:
- *   Pragnesh Patel 
- */
-
-#include 
-#include 
-#include 
-#include 
-
-/* Register offsets */
-#define L2_CACHE_CONFIG0x000
-#define L2_CACHE_ENABLE0x008
-
-#define MASK_NUM_WAYS  GENMASK(15, 8)
-#define NUM_WAYS_SHIFT 8
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int cache_enable_ways(void)
-{
-   const void *blob = gd->fdt_blob;
-   int node;
-   fdt_addr_t base;
-   u32 config;
-   u32 ways;
-
-   volatile u32 *enable;
-
-   node = fdt_node_offset_by_compatible(blob, -1,
-"sifive,fu740-c000-ccache");
-
-   if (node < 0)
-   return node;
-
-   base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
-   NULL, false);
-   if (base == FDT_ADDR_T_NONE)
-   return

[PATCH v5 5/5] riscv: lib: modify the indent

2021-09-01 Thread Zong Li

We usually use a space in function declaration, rather than a tab.

Signed-off-by: Zong Li 
Reviewed-by: Sean Anderson 
---
 arch/riscv/include/asm/cache.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index ec8fe201d3..874963d731 100644
--- a/arch/riscv/include/asm/cache.h
+++ b/arch/riscv/include/asm/cache.h
@@ -8,7 +8,7 @@
 #define _ASM_RISCV_CACHE_H
 
 /* cache */
-void   cache_flush(void);
+void cache_flush(void);
 
 /*
  * The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
-- 
2.32.0

[PATCH v5 3/5] riscv: lib: implement enable_caches for sifive cache

2021-09-01 Thread Zong Li

The enable_caches is a generic hook for architecture-implemented, we
define this function to enable composable cache of sifive platforms.

In sifive_cache, it invokes the generic cache_enable interface of cache
uclass to execute the relative implementation in SiFive ccache driver.

Signed-off-by: Zong Li 
---
 arch/riscv/Kconfig|  5 +
 arch/riscv/lib/Makefile   |  1 +
 arch/riscv/lib/sifive_cache.c | 27 +++
 3 files changed, 33 insertions(+)
 create mode 100644 arch/riscv/lib/sifive_cache.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 4b0c3dffa6..ec651fe0a4 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT
  The SiFive CLINT block holds memory-mapped control and status 
registers
  associated with software and timer interrupts.
 
+config SIFIVE_CACHE
+   bool
+   help
+ This enables the operations to configure SiFive cache
+
 config ANDES_PLIC
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index c4cc41434b..06020fcc2a 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
 obj-$(CONFIG_CMD_GO) += boot.o
 obj-y  += cache.o
+obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
 ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
 obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c
new file mode 100644
index 00..28154878fc
--- /dev/null
+++ b/arch/riscv/lib/sifive_cache.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 SiFive, Inc
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+void enable_caches(void)
+{
+   struct udevice *dev;
+   int ret;
+
+   /* Enable ways of ccache */
+   ret = uclass_get_device_by_driver(UCLASS_CACHE,
+ DM_DRIVER_GET(sifive_ccache),
+ );
+   if (ret) {
+   log_debug("Cannot enable cache ways");
+   } else {
+   ret = cache_enable(dev);
+   if (ret)
+   log_debug("ccache enable failed");
+   }
+}
-- 
2.32.0

[PATCH v5 2/5] common: board_r: support enable_caches for RISC-V

2021-09-01 Thread Zong Li

The enable_caches is a generic hook for architecture-implemented, we
leverage this function to enable caches for RISC-V

Signed-off-by: Zong Li 
---
 arch/riscv/lib/cache.c | 4 
 common/board_r.c   | 4 ++--
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index b1d42bcc2b..686e699efb 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -70,3 +70,7 @@ __weak int dcache_status(void)
 {
return 0;
 }
+
+__weak void enable_caches(void)
+{
+}
diff --git a/common/board_r.c b/common/board_r.c
index e3e6248a1f..630c2451a2 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -114,7 +114,7 @@ static int initr_reloc(void)
return 0;
 }
 
-#ifdef CONFIG_ARM
+#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
 /*
  * Some of these functions are needed purely because the functions they
  * call return void. If we change them to return 0, these stubs can go away.
@@ -607,7 +607,7 @@ static init_fnc_t init_sequence_r[] = {
initr_trace,
initr_reloc,
/* TODO: could x86/PPC have this also perhaps? */
-#ifdef CONFIG_ARM
+#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
initr_caches,
/* Note: For Freescale LS2 SoCs, new MMU table is created in DDR.
 *   A temporary mapping of IFC high region is since removed,
-- 
2.32.0

[PATCH v5 1/5] cache: add sifive composable cache driver

2021-09-01 Thread Zong Li

This driver is currently responsible for enabling all ccache ways.
Composable cache could be configure as RAM or cache, we will use it as
RAM at the beginning to put the u-boot SPL there. In u-boot proper
phrase, we will use the composable cache as cache, and try to enable the
cache ways.

Signed-off-by: Zong Li 
Reviewed-by: Sean Anderson 
Reviewed-by: Rick Chen 
---
 drivers/cache/Kconfig   |  7 +++
 drivers/cache/Makefile  |  1 +
 drivers/cache/cache-sifive-ccache.c | 75 +
 3 files changed, 83 insertions(+)
 create mode 100644 drivers/cache/cache-sifive-ccache.c

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 1e452ad6d9..40f41a817c 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -39,4 +39,11 @@ config NCORE_CACHE
  controller. The driver initializes cache directories and coherent
  agent interfaces.
 
+config SIFIVE_CCACHE
+   bool "SiFive composable cache"
+   select CACHE
+   help
+ This driver is for SiFive Composable L2/L3 cache. It enables cache
+ ways of composable cache.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index fed50be3f9..ad765774e3 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_SANDBOX) += sandbox_cache.o
 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
 obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
 obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
+obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o
diff --git a/drivers/cache/cache-sifive-ccache.c 
b/drivers/cache/cache-sifive-ccache.c
new file mode 100644
index 00..76c0ab26ae
--- /dev/null
+++ b/drivers/cache/cache-sifive-ccache.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 SiFive
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SIFIVE_CCACHE_CONFIG   0x000
+#define SIFIVE_CCACHE_CONFIG_WAYS  GENMASK(15, 8)
+
+#define SIFIVE_CCACHE_WAY_ENABLE   0x008
+
+struct sifive_ccache {
+   void __iomem *base;
+};
+
+static int sifive_ccache_enable(struct udevice *dev)
+{
+   struct sifive_ccache *priv = dev_get_priv(dev);
+   u32 config;
+   u32 ways;
+
+   /* Enable all ways of composable cache */
+   config = readl(priv->base + SIFIVE_CCACHE_CONFIG);
+   ways = FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS, config);
+
+   writel(ways - 1, priv->base + SIFIVE_CCACHE_WAY_ENABLE);
+
+   return 0;
+}
+
+static int sifive_ccache_get_info(struct udevice *dev, struct cache_info *info)
+{
+   struct sifive_ccache *priv = dev_get_priv(dev);
+
+   info->base = (phys_addr_t)priv->base;
+
+   return 0;
+}
+
+static const struct cache_ops sifive_ccache_ops = {
+   .enable = sifive_ccache_enable,
+   .get_info = sifive_ccache_get_info,
+};
+
+static int sifive_ccache_probe(struct udevice *dev)
+{
+   struct sifive_ccache *priv = dev_get_priv(dev);
+
+   priv->base = dev_read_addr_ptr(dev);
+   if (!priv->base)
+   return -EINVAL;
+
+   return 0;
+}
+
+static const struct udevice_id sifive_ccache_ids[] = {
+   { .compatible = "sifive,fu540-c000-ccache" },
+   { .compatible = "sifive,fu740-c000-ccache" },
+   {}
+};
+
+U_BOOT_DRIVER(sifive_ccache) = {
+   .name = "sifive_ccache",
+   .id = UCLASS_CACHE,
+   .of_match = sifive_ccache_ids,
+   .probe = sifive_ccache_probe,
+   .priv_auto = sizeof(struct sifive_ccache),
+   .ops = _ccache_ops,
+};
-- 
2.32.0

[PATCH v5 0/5] Support SiFive Composable cache driver

2021-09-01 Thread Zong Li

This patch set contains the SiFive composable cache support, and
uses this driver to enable the ways of ccache by overwriting the
enable_caches.

Changed in v5:
 - Fix build error on ae350 platform

Changed in v4:
 - Use generic enable_caches(), rather than cache_init().
 - Rebase code base to v2021.10-rc3

Changed in v3:
 - Combine some patches
 - Drop the subdirectories of vendor in lib/
 - Rebase codebase

Changed in v2:
 - Refine the ccache driver by Sean's suggestions
 - Introduce a common interface for cache initialization

Zong Li (5):
  cache: add sifive composable cache driver
  common: board_r: support enable_caches for RISC-V
  riscv: lib: implement enable_caches for sifive cache
  board: sifive: use ccache driver instead of helper function
  riscv: lib: modify the indent

 arch/riscv/Kconfig|  5 ++
 arch/riscv/cpu/fu540/Kconfig  |  2 +
 arch/riscv/cpu/fu540/Makefile |  1 -
 arch/riscv/cpu/fu540/cache.c  | 55 -
 arch/riscv/cpu/fu740/Kconfig  |  2 +
 arch/riscv/cpu/fu740/Makefile |  1 -
 arch/riscv/cpu/fu740/cache.c  | 55 -
 arch/riscv/include/asm/arch-fu540/cache.h | 14 -
 arch/riscv/include/asm/arch-fu740/cache.h | 14 -
 arch/riscv/include/asm/cache.h|  2 +-
 arch/riscv/lib/Makefile   |  1 +
 arch/riscv/lib/cache.c|  4 ++
 arch/riscv/lib/sifive_cache.c | 27 
 board/sifive/unleashed/unleashed.c| 10 +--
 board/sifive/unmatched/unmatched.c| 11 +---
 common/board_r.c  |  4 +-
 drivers/cache/Kconfig |  7 +++
 drivers/cache/Makefile|  1 +
 drivers/cache/cache-sifive-ccache.c   | 75 +++
 19 files changed, 132 insertions(+), 159 deletions(-)
 delete mode 100644 arch/riscv/cpu/fu540/cache.c
 delete mode 100644 arch/riscv/cpu/fu740/cache.c
 delete mode 100644 arch/riscv/include/asm/arch-fu540/cache.h
 delete mode 100644 arch/riscv/include/asm/arch-fu740/cache.h
 create mode 100644 arch/riscv/lib/sifive_cache.c
 create mode 100644 drivers/cache/cache-sifive-ccache.c

-- 
2.32.0

Re: [PATCH v4 2/4] riscv: lib: implement enable_caches for sifive cache

2021-08-31 Thread Zong Li

On Wed, Sep 1, 2021 at 10:06 AM Rick Chen  wrote:
>
> > From: Zong Li 
> > Sent: Tuesday, August 31, 2021 5:21 PM
> > To: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊) 
> > ; bmeng...@gmail.com; sean...@gmail.com; 
> > green@sifive.com; paul.walms...@sifive.com; s...@chromium.org; 
> > u-boot@lists.denx.de
> > Cc: Zong Li 
> > Subject: [PATCH v4 2/4] riscv: lib: implement enable_caches for sifive cache
> >
> > The enable_caches is a generic hook for architecture-implemented, we define 
> > this function to enable composable cache of sifive platforms.
> >
> > In sifive_cache, it invokes the generic cache_enable interface of cache 
> > uclass to execute the relative implementation in SiFive ccache driver.
> >
> > Signed-off-by: Zong Li 
> > ---
> >  arch/riscv/Kconfig|  5 +
> >  arch/riscv/lib/Makefile   |  1 +
> >  arch/riscv/lib/sifive_cache.c | 27 +++
> >  common/board_r.c  |  4 ++--
> >  4 files changed, 35 insertions(+), 2 deletions(-)  create mode 100644 
> > arch/riscv/lib/sifive_cache.c
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 
> > 4b0c3dffa6..ec651fe0a4 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT
> >   The SiFive CLINT block holds memory-mapped control and status 
> > registers
> >   associated with software and timer interrupts.
> >
> > +config SIFIVE_CACHE
> > +   bool
> > +   help
> > + This enables the operations to configure SiFive cache
> > +
> >  config ANDES_PLIC
> > bool
> > depends on RISCV_MMODE || SPL_RISCV_MMODE diff --git 
> > a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 
> > c4cc41434b..06020fcc2a 100644
> > --- a/arch/riscv/lib/Makefile
> > +++ b/arch/riscv/lib/Makefile
> > @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
> >  obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
> >  obj-$(CONFIG_CMD_GO) += boot.o
> >  obj-y  += cache.o
> > +obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
> >  ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
> >  obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
> >  obj-$(CONFIG_ANDES_PLIC) += andes_plic.o diff --git 
> > a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c new file 
> > mode 100644 index 00..28154878fc
> > --- /dev/null
> > +++ b/arch/riscv/lib/sifive_cache.c
> > @@ -0,0 +1,27 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2021 SiFive, Inc
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +void enable_caches(void)
> > +{
> > +   struct udevice *dev;
> > +   int ret;
> > +
> > +   /* Enable ways of ccache */
> > +   ret = uclass_get_device_by_driver(UCLASS_CACHE,
> > + DM_DRIVER_GET(sifive_ccache),
> > + );
> > +   if (ret) {
> > +   log_debug("Cannot enable cache ways");
> > +   } else {
> > +   ret = cache_enable(dev);
> > +   if (ret)
> > +   log_debug("ccache enable failed");
> > +   }
> > +}
> > diff --git a/common/board_r.c b/common/board_r.c index 
> > e3e6248a1f..630c2451a2 100644
> > --- a/common/board_r.c
> > +++ b/common/board_r.c
> > @@ -114,7 +114,7 @@ static int initr_reloc(void)
> > return 0;
> >  }
> >
> > -#ifdef CONFIG_ARM
> > +#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
>
> Here may cause other RISC-V platforms build error.
> eq, ae350 will compile error as below:
> common/board_r.o: in function `initr_caches':
> /u-boot-riscv/common/board_r.c:124: undefined reference to `enable_caches'
> Makefile:1795: recipe for target 'u-boot' failed
>
> Maybe you can separate this part an isolate patch:
> board_r: enable initr_caches for RISC-V ...
> And also implement the week function for others.
>

Thanks for reviewing that. I would fix it and send the next version.

> Thanks,
> Rick
>
>
>
> >  /*
> >   * Some of these functions are needed purely because the functions they
> >   * call return void. If we change them to return 0, these stubs can go 
> > away.
> > @@ -607,7 +607,7 @@ static init_fnc_t init_sequence_r[] = {
> > initr_trace,
> > initr_reloc,
> > /* TODO: could x86/PPC have this also perhaps? */ -#ifdef CONFIG_ARM
> > +#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
> > initr_caches,
> > /* Note: For Freescale LS2 SoCs, new MMU table is created in DDR.
> >  *   A temporary mapping of IFC high region is since removed,
> > --
> > 2.32.0

Re: [PATCH v3 2/4] riscv: lib: introduce a cache_init interface

2021-08-31 Thread Zong Li

On Tue, Aug 31, 2021 at 12:48 PM Sean Anderson  wrote:
>
> On 8/17/21 5:08 AM, Zong Li wrote:
> > Add an interface for cache initialization. Each platform can overwrite
> > this weak function by their own implementation, such as sifive_cache in
> > this patch.
> >
> > In sifive_cache, it invokes the generic cache_enable interface of cache
> > uclass to execute the relative implementation in SiFive ccache driver.
> >
> > Signed-off-by: Zong Li 
> > ---
> >   arch/riscv/Kconfig |  5 +
> >   arch/riscv/include/asm/cache.h |  1 +
> >   arch/riscv/lib/Makefile|  1 +
> >   arch/riscv/lib/cache.c |  5 +
> >   arch/riscv/lib/sifive_cache.c  | 27 +++
> >   5 files changed, 39 insertions(+)
> >   create mode 100644 arch/riscv/lib/sifive_cache.c
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 4b0c3dffa6..ec651fe0a4 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT
> > The SiFive CLINT block holds memory-mapped control and status 
> > registers
> > associated with software and timer interrupts.
> >
> > +config SIFIVE_CACHE
> > + bool
> > + help
> > +   This enables the operations to configure SiFive cache
> > +
> >   config ANDES_PLIC
> >   bool
> >   depends on RISCV_MMODE || SPL_RISCV_MMODE
> > diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
> > index ec8fe201d3..6ebb2b4329 100644
> > --- a/arch/riscv/include/asm/cache.h
> > +++ b/arch/riscv/include/asm/cache.h
> > @@ -9,6 +9,7 @@
> >
> >   /* cache */
> >   voidcache_flush(void);
> > +int cache_init(void);
> >
> >   /*
> >* The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
> > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > index c4cc41434b..06020fcc2a 100644
> > --- a/arch/riscv/lib/Makefile
> > +++ b/arch/riscv/lib/Makefile
> > @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
> >   obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
> >   obj-$(CONFIG_CMD_GO) += boot.o
> >   obj-y   += cache.o
> > +obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
> >   ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
> >   obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
> >   obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
> > diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
> > index b1d42bcc2b..2cd66504c6 100644
> > --- a/arch/riscv/lib/cache.c
> > +++ b/arch/riscv/lib/cache.c
> > @@ -70,3 +70,8 @@ __weak int dcache_status(void)
> >   {
> >   return 0;
> >   }
> > +
> > +__weak int cache_init(void)
> > +{
> > + return 0;
> > +}
>
> Don't make this generic. Just call a `sifive_cache_init` or whatever.
>
> IMO this pattern shouldn't be duplicated by other platforms, but it is OK to 
> do for now until we have a more generic method.
>

Hi Sean,
I have sent the v4 patch to use generic enable_caches hook, it seems
to me that we could add an additional arch-defined interface in the
future if we really needed it, rather than at this time. Please help
me to review the v4 patch and hope we are on the same page.

> --Sean
>
> > diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c
> > new file mode 100644
> > index 00..94e84e024e
> > --- /dev/null
> > +++ b/arch/riscv/lib/sifive_cache.c
> > @@ -0,0 +1,27 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2021 SiFive, Inc
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +
> > +int cache_init(void)
> > +{
> > + struct udevice *dev;
> > + int ret;
> > +
> > + /* Enable ways of ccache */
> > + ret = uclass_get_device_by_driver(UCLASS_CACHE,
> > +   DM_DRIVER_GET(sifive_ccache),
> > +   );
> > + if (ret)
> > + return log_msg_ret("Cannot enable cache ways", ret);
> > +
> > + ret = cache_enable(dev);
> > + if (ret)
> > + return log_msg_ret("ccache enable failed", ret);
> > +
> > + return 0;
> > +}
> >

[PATCH v4 4/4] riscv: lib: modify the indent

2021-08-31 Thread Zong Li

We usually use a space in function declaration, rather than a tab.

Signed-off-by: Zong Li 
Reviewed-by: Sean Anderson 
---
 arch/riscv/include/asm/cache.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index ec8fe201d3..874963d731 100644
--- a/arch/riscv/include/asm/cache.h
+++ b/arch/riscv/include/asm/cache.h
@@ -8,7 +8,7 @@
 #define _ASM_RISCV_CACHE_H
 
 /* cache */
-void   cache_flush(void);
+void cache_flush(void);
 
 /*
  * The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
-- 
2.32.0

[PATCH v4 3/4] board: sifive: use ccache driver instead of helper function

2021-08-31 Thread Zong Li

Invokes the common cache_init function to initialize ccache.

Signed-off-by: Zong Li 
Reviewed-by: Sean Anderson 
---
 arch/riscv/cpu/fu540/Kconfig  |  2 +
 arch/riscv/cpu/fu540/Makefile |  1 -
 arch/riscv/cpu/fu540/cache.c  | 55 ---
 arch/riscv/cpu/fu740/Kconfig  |  2 +
 arch/riscv/cpu/fu740/Makefile |  1 -
 arch/riscv/cpu/fu740/cache.c  | 55 ---
 arch/riscv/include/asm/arch-fu540/cache.h | 14 --
 arch/riscv/include/asm/arch-fu740/cache.h | 14 --
 board/sifive/unleashed/unleashed.c| 10 +
 board/sifive/unmatched/unmatched.c| 11 ++---
 10 files changed, 9 insertions(+), 156 deletions(-)
 delete mode 100644 arch/riscv/cpu/fu540/cache.c
 delete mode 100644 arch/riscv/cpu/fu740/cache.c
 delete mode 100644 arch/riscv/include/asm/arch-fu540/cache.h
 delete mode 100644 arch/riscv/include/asm/arch-fu740/cache.h

diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
index 05463b2625..1604b412b4 100644
--- a/arch/riscv/cpu/fu540/Kconfig
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -19,6 +19,8 @@ config SIFIVE_FU540
imply SMP
imply CLK_SIFIVE
imply CLK_SIFIVE_PRCI
+   imply SIFIVE_CACHE
+   imply SIFIVE_CCACHE
imply SIFIVE_SERIAL
imply MACB
imply MII
diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile
index 088205ef57..043fb961a5 100644
--- a/arch/riscv/cpu/fu540/Makefile
+++ b/arch/riscv/cpu/fu540/Makefile
@@ -8,5 +8,4 @@ obj-y += spl.o
 else
 obj-y += dram.o
 obj-y += cpu.o
-obj-y += cache.o
 endif
diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c
deleted file mode 100644
index 0fc4ef6c00..00
--- a/arch/riscv/cpu/fu540/cache.c
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020 SiFive, Inc
- *
- * Authors:
- *   Pragnesh Patel 
- */
-
-#include 
-#include 
-#include 
-#include 
-
-/* Register offsets */
-#define L2_CACHE_CONFIG0x000
-#define L2_CACHE_ENABLE0x008
-
-#define MASK_NUM_WAYS  GENMASK(15, 8)
-#define NUM_WAYS_SHIFT 8
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int cache_enable_ways(void)
-{
-   const void *blob = gd->fdt_blob;
-   int node;
-   fdt_addr_t base;
-   u32 config;
-   u32 ways;
-
-   volatile u32 *enable;
-
-   node = fdt_node_offset_by_compatible(blob, -1,
-"sifive,fu540-c000-ccache");
-
-   if (node < 0)
-   return node;
-
-   base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
-   NULL, false);
-   if (base == FDT_ADDR_T_NONE)
-   return FDT_ADDR_T_NONE;
-
-   config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
-   ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
-
-   enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
-
-   /* memory barrier */
-   mb();
-   (*enable) = ways - 1;
-   /* memory barrier */
-   mb();
-   return 0;
-}
diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
index 408195f149..049a0a0584 100644
--- a/arch/riscv/cpu/fu740/Kconfig
+++ b/arch/riscv/cpu/fu740/Kconfig
@@ -19,6 +19,8 @@ config SIFIVE_FU740
imply SMP
imply CLK_SIFIVE
imply CLK_SIFIVE_PRCI
+   imply SIFIVE_CACHE
+   imply SIFIVE_CCACHE
imply SIFIVE_SERIAL
imply MACB
imply MII
diff --git a/arch/riscv/cpu/fu740/Makefile b/arch/riscv/cpu/fu740/Makefile
index 5ef8ac18a7..1d1ad98ba7 100644
--- a/arch/riscv/cpu/fu740/Makefile
+++ b/arch/riscv/cpu/fu740/Makefile
@@ -8,5 +8,4 @@ obj-y += spl.o
 else
 obj-y += dram.o
 obj-y += cpu.o
-obj-y += cache.o
 endif
diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c
deleted file mode 100644
index 680955c9e3..00
--- a/arch/riscv/cpu/fu740/cache.c
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020-2021 SiFive, Inc
- *
- * Authors:
- *   Pragnesh Patel 
- */
-
-#include 
-#include 
-#include 
-#include 
-
-/* Register offsets */
-#define L2_CACHE_CONFIG0x000
-#define L2_CACHE_ENABLE0x008
-
-#define MASK_NUM_WAYS  GENMASK(15, 8)
-#define NUM_WAYS_SHIFT 8
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int cache_enable_ways(void)
-{
-   const void *blob = gd->fdt_blob;
-   int node;
-   fdt_addr_t base;
-   u32 config;
-   u32 ways;
-
-   volatile u32 *enable;
-
-   node = fdt_node_offset_by_compatible(blob, -1,
-"sifive,fu740-c000-ccache");
-
-   if (node < 0)
-   return node;
-
-   base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
-   NULL, false);
-   if (base == FDT_ADDR_T_NONE)
-   return

[PATCH v4 2/4] riscv: lib: implement enable_caches for sifive cache

2021-08-31 Thread Zong Li

The enable_caches is a generic hook for architecture-implemented, we
define this function to enable composable cache of sifive platforms.

In sifive_cache, it invokes the generic cache_enable interface of cache
uclass to execute the relative implementation in SiFive ccache driver.

Signed-off-by: Zong Li 
---
 arch/riscv/Kconfig|  5 +
 arch/riscv/lib/Makefile   |  1 +
 arch/riscv/lib/sifive_cache.c | 27 +++
 common/board_r.c  |  4 ++--
 4 files changed, 35 insertions(+), 2 deletions(-)
 create mode 100644 arch/riscv/lib/sifive_cache.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 4b0c3dffa6..ec651fe0a4 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT
  The SiFive CLINT block holds memory-mapped control and status 
registers
  associated with software and timer interrupts.
 
+config SIFIVE_CACHE
+   bool
+   help
+ This enables the operations to configure SiFive cache
+
 config ANDES_PLIC
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index c4cc41434b..06020fcc2a 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
 obj-$(CONFIG_CMD_GO) += boot.o
 obj-y  += cache.o
+obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
 ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
 obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c
new file mode 100644
index 00..28154878fc
--- /dev/null
+++ b/arch/riscv/lib/sifive_cache.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 SiFive, Inc
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+void enable_caches(void)
+{
+   struct udevice *dev;
+   int ret;
+
+   /* Enable ways of ccache */
+   ret = uclass_get_device_by_driver(UCLASS_CACHE,
+ DM_DRIVER_GET(sifive_ccache),
+ );
+   if (ret) {
+   log_debug("Cannot enable cache ways");
+   } else {
+   ret = cache_enable(dev);
+   if (ret)
+   log_debug("ccache enable failed");
+   }
+}
diff --git a/common/board_r.c b/common/board_r.c
index e3e6248a1f..630c2451a2 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -114,7 +114,7 @@ static int initr_reloc(void)
return 0;
 }
 
-#ifdef CONFIG_ARM
+#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
 /*
  * Some of these functions are needed purely because the functions they
  * call return void. If we change them to return 0, these stubs can go away.
@@ -607,7 +607,7 @@ static init_fnc_t init_sequence_r[] = {
initr_trace,
initr_reloc,
/* TODO: could x86/PPC have this also perhaps? */
-#ifdef CONFIG_ARM
+#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
initr_caches,
/* Note: For Freescale LS2 SoCs, new MMU table is created in DDR.
 *   A temporary mapping of IFC high region is since removed,
-- 
2.32.0

[PATCH v4 1/4] cache: add sifive composable cache driver

2021-08-31 Thread Zong Li

This driver is currently responsible for enabling all ccache ways.
Composable cache could be configure as RAM or cache, we will use it as
RAM at the beginning to put the u-boot SPL there. In u-boot proper
phrase, we will use the composable cache as cache, and try to enable the
cache ways.

Signed-off-by: Zong Li 
Reviewed-by: Sean Anderson 
---
 drivers/cache/Kconfig   |  7 +++
 drivers/cache/Makefile  |  1 +
 drivers/cache/cache-sifive-ccache.c | 75 +
 3 files changed, 83 insertions(+)
 create mode 100644 drivers/cache/cache-sifive-ccache.c

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 1e452ad6d9..40f41a817c 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -39,4 +39,11 @@ config NCORE_CACHE
  controller. The driver initializes cache directories and coherent
  agent interfaces.
 
+config SIFIVE_CCACHE
+   bool "SiFive composable cache"
+   select CACHE
+   help
+ This driver is for SiFive Composable L2/L3 cache. It enables cache
+ ways of composable cache.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index fed50be3f9..ad765774e3 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_SANDBOX) += sandbox_cache.o
 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
 obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
 obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
+obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o
diff --git a/drivers/cache/cache-sifive-ccache.c 
b/drivers/cache/cache-sifive-ccache.c
new file mode 100644
index 00..76c0ab26ae
--- /dev/null
+++ b/drivers/cache/cache-sifive-ccache.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 SiFive
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SIFIVE_CCACHE_CONFIG   0x000
+#define SIFIVE_CCACHE_CONFIG_WAYS  GENMASK(15, 8)
+
+#define SIFIVE_CCACHE_WAY_ENABLE   0x008
+
+struct sifive_ccache {
+   void __iomem *base;
+};
+
+static int sifive_ccache_enable(struct udevice *dev)
+{
+   struct sifive_ccache *priv = dev_get_priv(dev);
+   u32 config;
+   u32 ways;
+
+   /* Enable all ways of composable cache */
+   config = readl(priv->base + SIFIVE_CCACHE_CONFIG);
+   ways = FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS, config);
+
+   writel(ways - 1, priv->base + SIFIVE_CCACHE_WAY_ENABLE);
+
+   return 0;
+}
+
+static int sifive_ccache_get_info(struct udevice *dev, struct cache_info *info)
+{
+   struct sifive_ccache *priv = dev_get_priv(dev);
+
+   info->base = (phys_addr_t)priv->base;
+
+   return 0;
+}
+
+static const struct cache_ops sifive_ccache_ops = {
+   .enable = sifive_ccache_enable,
+   .get_info = sifive_ccache_get_info,
+};
+
+static int sifive_ccache_probe(struct udevice *dev)
+{
+   struct sifive_ccache *priv = dev_get_priv(dev);
+
+   priv->base = dev_read_addr_ptr(dev);
+   if (!priv->base)
+   return -EINVAL;
+
+   return 0;
+}
+
+static const struct udevice_id sifive_ccache_ids[] = {
+   { .compatible = "sifive,fu540-c000-ccache" },
+   { .compatible = "sifive,fu740-c000-ccache" },
+   {}
+};
+
+U_BOOT_DRIVER(sifive_ccache) = {
+   .name = "sifive_ccache",
+   .id = UCLASS_CACHE,
+   .of_match = sifive_ccache_ids,
+   .probe = sifive_ccache_probe,
+   .priv_auto = sizeof(struct sifive_ccache),
+   .ops = _ccache_ops,
+};
-- 
2.32.0

[PATCH v4 0/4] Support SiFive Composable cache driver

2021-08-31 Thread Zong Li

This patch set contains the SiFive composable cache support, and
uses this driver to enable the ways of ccache by overwriting the
enable_caches.

Changed in v4:
 - Use generic enable_caches(), rather than cache_init().
 - Rebase code base to v2021.10-rc3

Changed in v3:
 - Combine some patches
 - Drop the subdirectories of vendor in lib/
 - Rebase codebase

Changed in v2:
 - Refine the ccache driver by Sean's suggestions
 - Introduce a common interface for cache initialization

Zong Li (4):
  cache: add sifive composable cache driver
  riscv: lib: implement enable_caches for sifive cache
  board: sifive: use ccache driver instead of helper function
  riscv: lib: modify the indent

 arch/riscv/Kconfig|  5 ++
 arch/riscv/cpu/fu540/Kconfig  |  2 +
 arch/riscv/cpu/fu540/Makefile |  1 -
 arch/riscv/cpu/fu540/cache.c  | 55 -
 arch/riscv/cpu/fu740/Kconfig  |  2 +
 arch/riscv/cpu/fu740/Makefile |  1 -
 arch/riscv/cpu/fu740/cache.c  | 55 -
 arch/riscv/include/asm/arch-fu540/cache.h | 14 -
 arch/riscv/include/asm/arch-fu740/cache.h | 14 -
 arch/riscv/include/asm/cache.h|  2 +-
 arch/riscv/lib/Makefile   |  1 +
 arch/riscv/lib/sifive_cache.c | 27 
 board/sifive/unleashed/unleashed.c| 10 +--
 board/sifive/unmatched/unmatched.c| 11 +---
 common/board_r.c  |  4 +-
 drivers/cache/Kconfig |  7 +++
 drivers/cache/Makefile|  1 +
 drivers/cache/cache-sifive-ccache.c   | 75 +++
 18 files changed, 128 insertions(+), 159 deletions(-)
 delete mode 100644 arch/riscv/cpu/fu540/cache.c
 delete mode 100644 arch/riscv/cpu/fu740/cache.c
 delete mode 100644 arch/riscv/include/asm/arch-fu540/cache.h
 delete mode 100644 arch/riscv/include/asm/arch-fu740/cache.h
 create mode 100644 arch/riscv/lib/sifive_cache.c
 create mode 100644 drivers/cache/cache-sifive-ccache.c

-- 
2.32.0

Re: [PATCH v3 0/4] Support SiFive Composable cache driver

2021-08-24 Thread Zong Li

On Tue, Aug 17, 2021 at 5:08 PM Zong Li  wrote:
>
> This patch set contains the SiFive composable cache support, and
> indroduce an interface to do cache initialization, each platform can
> overwrite it by their own implementation.
>
> Changed in v3:
>  - Combine some patches
>  - Drop the subdirectories of vendor in lib/
>  - Rebase codebase
>
> Changed in v2:
>  - Refine the ccache driver by Sean's suggestions
>  - Introduce a common interface for cache initialization
>
> Zong Li (4):
>   cache: add sifive composable cache driver
>   riscv: lib: introduce a cache_init interface
>   board: sifive: use ccache driver instead of helper function
>   riscv: lib: modify the indent
>
>  arch/riscv/Kconfig|  5 ++
>  arch/riscv/cpu/fu540/Kconfig  |  2 +
>  arch/riscv/cpu/fu540/Makefile |  1 -
>  arch/riscv/cpu/fu540/cache.c  | 55 -
>  arch/riscv/cpu/fu740/Kconfig  |  2 +
>  arch/riscv/cpu/fu740/Makefile |  1 -
>  arch/riscv/cpu/fu740/cache.c  | 55 -
>  arch/riscv/include/asm/arch-fu540/cache.h | 14 -
>  arch/riscv/include/asm/arch-fu740/cache.h | 14 -
>  arch/riscv/include/asm/cache.h|  3 +-
>  arch/riscv/lib/Makefile   |  1 +
>  arch/riscv/lib/cache.c|  5 ++
>  arch/riscv/lib/sifive_cache.c | 27 
>  board/sifive/unleashed/unleashed.c| 12 +---
>  board/sifive/unmatched/unmatched.c| 11 +---
>  drivers/cache/Kconfig |  7 +++
>  drivers/cache/Makefile|  1 +
>  drivers/cache/cache-sifive-ccache.c   | 75 +++
>  18 files changed, 131 insertions(+), 160 deletions(-)
>  delete mode 100644 arch/riscv/cpu/fu540/cache.c
>  delete mode 100644 arch/riscv/cpu/fu740/cache.c
>  delete mode 100644 arch/riscv/include/asm/arch-fu540/cache.h
>  delete mode 100644 arch/riscv/include/asm/arch-fu740/cache.h
>  create mode 100644 arch/riscv/lib/sifive_cache.c
>  create mode 100644 drivers/cache/cache-sifive-ccache.c
>
> --
> 2.32.0
>

ping

[PATCH v3 3/4] board: sifive: use ccache driver instead of helper function

2021-08-17 Thread Zong Li

Invokes the common cache_init function to initialize ccache.

Signed-off-by: Zong Li 
---
 arch/riscv/cpu/fu540/Kconfig  |  2 +
 arch/riscv/cpu/fu540/Makefile |  1 -
 arch/riscv/cpu/fu540/cache.c  | 55 ---
 arch/riscv/cpu/fu740/Kconfig  |  2 +
 arch/riscv/cpu/fu740/Makefile |  1 -
 arch/riscv/cpu/fu740/cache.c  | 55 ---
 arch/riscv/include/asm/arch-fu540/cache.h | 14 --
 arch/riscv/include/asm/arch-fu740/cache.h | 14 --
 board/sifive/unleashed/unleashed.c| 12 +
 board/sifive/unmatched/unmatched.c| 11 +
 10 files changed, 8 insertions(+), 159 deletions(-)
 delete mode 100644 arch/riscv/cpu/fu540/cache.c
 delete mode 100644 arch/riscv/cpu/fu740/cache.c
 delete mode 100644 arch/riscv/include/asm/arch-fu540/cache.h
 delete mode 100644 arch/riscv/include/asm/arch-fu740/cache.h

diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
index 05463b2625..1604b412b4 100644
--- a/arch/riscv/cpu/fu540/Kconfig
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -19,6 +19,8 @@ config SIFIVE_FU540
imply SMP
imply CLK_SIFIVE
imply CLK_SIFIVE_PRCI
+   imply SIFIVE_CACHE
+   imply SIFIVE_CCACHE
imply SIFIVE_SERIAL
imply MACB
imply MII
diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile
index 088205ef57..043fb961a5 100644
--- a/arch/riscv/cpu/fu540/Makefile
+++ b/arch/riscv/cpu/fu540/Makefile
@@ -8,5 +8,4 @@ obj-y += spl.o
 else
 obj-y += dram.o
 obj-y += cpu.o
-obj-y += cache.o
 endif
diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c
deleted file mode 100644
index 0fc4ef6c00..00
--- a/arch/riscv/cpu/fu540/cache.c
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020 SiFive, Inc
- *
- * Authors:
- *   Pragnesh Patel 
- */
-
-#include 
-#include 
-#include 
-#include 
-
-/* Register offsets */
-#define L2_CACHE_CONFIG0x000
-#define L2_CACHE_ENABLE0x008
-
-#define MASK_NUM_WAYS  GENMASK(15, 8)
-#define NUM_WAYS_SHIFT 8
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int cache_enable_ways(void)
-{
-   const void *blob = gd->fdt_blob;
-   int node;
-   fdt_addr_t base;
-   u32 config;
-   u32 ways;
-
-   volatile u32 *enable;
-
-   node = fdt_node_offset_by_compatible(blob, -1,
-"sifive,fu540-c000-ccache");
-
-   if (node < 0)
-   return node;
-
-   base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
-   NULL, false);
-   if (base == FDT_ADDR_T_NONE)
-   return FDT_ADDR_T_NONE;
-
-   config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
-   ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
-
-   enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
-
-   /* memory barrier */
-   mb();
-   (*enable) = ways - 1;
-   /* memory barrier */
-   mb();
-   return 0;
-}
diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
index 408195f149..049a0a0584 100644
--- a/arch/riscv/cpu/fu740/Kconfig
+++ b/arch/riscv/cpu/fu740/Kconfig
@@ -19,6 +19,8 @@ config SIFIVE_FU740
imply SMP
imply CLK_SIFIVE
imply CLK_SIFIVE_PRCI
+   imply SIFIVE_CACHE
+   imply SIFIVE_CCACHE
imply SIFIVE_SERIAL
imply MACB
imply MII
diff --git a/arch/riscv/cpu/fu740/Makefile b/arch/riscv/cpu/fu740/Makefile
index 5ef8ac18a7..1d1ad98ba7 100644
--- a/arch/riscv/cpu/fu740/Makefile
+++ b/arch/riscv/cpu/fu740/Makefile
@@ -8,5 +8,4 @@ obj-y += spl.o
 else
 obj-y += dram.o
 obj-y += cpu.o
-obj-y += cache.o
 endif
diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c
deleted file mode 100644
index 680955c9e3..00
--- a/arch/riscv/cpu/fu740/cache.c
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020-2021 SiFive, Inc
- *
- * Authors:
- *   Pragnesh Patel 
- */
-
-#include 
-#include 
-#include 
-#include 
-
-/* Register offsets */
-#define L2_CACHE_CONFIG0x000
-#define L2_CACHE_ENABLE0x008
-
-#define MASK_NUM_WAYS  GENMASK(15, 8)
-#define NUM_WAYS_SHIFT 8
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int cache_enable_ways(void)
-{
-   const void *blob = gd->fdt_blob;
-   int node;
-   fdt_addr_t base;
-   u32 config;
-   u32 ways;
-
-   volatile u32 *enable;
-
-   node = fdt_node_offset_by_compatible(blob, -1,
-"sifive,fu740-c000-ccache");
-
-   if (node < 0)
-   return node;
-
-   base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
-   NULL, false);
-   if (base == FDT_ADDR_T_NONE)
-   return FDT_ADDR_T_NONE;
-
-   config

[PATCH v3 4/4] riscv: lib: modify the indent

2021-08-17 Thread Zong Li

We usually use a space in function declaration, rather than a tab.

Signed-off-by: Zong Li 
Reviewed-by: Sean Anderson 
---
 arch/riscv/include/asm/cache.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index 6ebb2b4329..b700ff5021 100644
--- a/arch/riscv/include/asm/cache.h
+++ b/arch/riscv/include/asm/cache.h
@@ -8,7 +8,7 @@
 #define _ASM_RISCV_CACHE_H
 
 /* cache */
-void   cache_flush(void);
+void cache_flush(void);
 int cache_init(void);
 
 /*
-- 
2.32.0

[PATCH v3 2/4] riscv: lib: introduce a cache_init interface

2021-08-17 Thread Zong Li

Add an interface for cache initialization. Each platform can overwrite
this weak function by their own implementation, such as sifive_cache in
this patch.

In sifive_cache, it invokes the generic cache_enable interface of cache
uclass to execute the relative implementation in SiFive ccache driver.

Signed-off-by: Zong Li 
---
 arch/riscv/Kconfig |  5 +
 arch/riscv/include/asm/cache.h |  1 +
 arch/riscv/lib/Makefile|  1 +
 arch/riscv/lib/cache.c |  5 +
 arch/riscv/lib/sifive_cache.c  | 27 +++
 5 files changed, 39 insertions(+)
 create mode 100644 arch/riscv/lib/sifive_cache.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 4b0c3dffa6..ec651fe0a4 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT
  The SiFive CLINT block holds memory-mapped control and status 
registers
  associated with software and timer interrupts.
 
+config SIFIVE_CACHE
+   bool
+   help
+ This enables the operations to configure SiFive cache
+
 config ANDES_PLIC
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index ec8fe201d3..6ebb2b4329 100644
--- a/arch/riscv/include/asm/cache.h
+++ b/arch/riscv/include/asm/cache.h
@@ -9,6 +9,7 @@
 
 /* cache */
 void   cache_flush(void);
+int cache_init(void);
 
 /*
  * The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index c4cc41434b..06020fcc2a 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
 obj-$(CONFIG_CMD_GO) += boot.o
 obj-y  += cache.o
+obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
 ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
 obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index b1d42bcc2b..2cd66504c6 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -70,3 +70,8 @@ __weak int dcache_status(void)
 {
return 0;
 }
+
+__weak int cache_init(void)
+{
+   return 0;
+}
diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c
new file mode 100644
index 00..94e84e024e
--- /dev/null
+++ b/arch/riscv/lib/sifive_cache.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 SiFive, Inc
+ */
+
+#include 
+#include 
+#include 
+
+int cache_init(void)
+{
+   struct udevice *dev;
+   int ret;
+
+   /* Enable ways of ccache */
+   ret = uclass_get_device_by_driver(UCLASS_CACHE,
+ DM_DRIVER_GET(sifive_ccache),
+ );
+   if (ret)
+   return log_msg_ret("Cannot enable cache ways", ret);
+
+   ret = cache_enable(dev);
+   if (ret)
+   return log_msg_ret("ccache enable failed", ret);
+
+   return 0;
+}
-- 
2.32.0

[PATCH v3 1/4] cache: add sifive composable cache driver

2021-08-17 Thread Zong Li

This driver is currently responsible for enabling all ccache ways.
Composable cache could be configure as RAM or cache, we will use it as
RAM at the beginning to put the u-boot SPL there. In u-boot proper
phrase, we will use the composable cache as cache, and try to enable the
cache ways.

Signed-off-by: Zong Li 
Reviewed-by: Sean Anderson 
---
 drivers/cache/Kconfig   |  7 +++
 drivers/cache/Makefile  |  1 +
 drivers/cache/cache-sifive-ccache.c | 75 +
 3 files changed, 83 insertions(+)
 create mode 100644 drivers/cache/cache-sifive-ccache.c

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 1e452ad6d9..40f41a817c 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -39,4 +39,11 @@ config NCORE_CACHE
  controller. The driver initializes cache directories and coherent
  agent interfaces.
 
+config SIFIVE_CCACHE
+   bool "SiFive composable cache"
+   select CACHE
+   help
+ This driver is for SiFive Composable L2/L3 cache. It enables cache
+ ways of composable cache.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index fed50be3f9..ad765774e3 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_SANDBOX) += sandbox_cache.o
 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
 obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
 obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
+obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o
diff --git a/drivers/cache/cache-sifive-ccache.c 
b/drivers/cache/cache-sifive-ccache.c
new file mode 100644
index 00..76c0ab26ae
--- /dev/null
+++ b/drivers/cache/cache-sifive-ccache.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 SiFive
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SIFIVE_CCACHE_CONFIG   0x000
+#define SIFIVE_CCACHE_CONFIG_WAYS  GENMASK(15, 8)
+
+#define SIFIVE_CCACHE_WAY_ENABLE   0x008
+
+struct sifive_ccache {
+   void __iomem *base;
+};
+
+static int sifive_ccache_enable(struct udevice *dev)
+{
+   struct sifive_ccache *priv = dev_get_priv(dev);
+   u32 config;
+   u32 ways;
+
+   /* Enable all ways of composable cache */
+   config = readl(priv->base + SIFIVE_CCACHE_CONFIG);
+   ways = FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS, config);
+
+   writel(ways - 1, priv->base + SIFIVE_CCACHE_WAY_ENABLE);
+
+   return 0;
+}
+
+static int sifive_ccache_get_info(struct udevice *dev, struct cache_info *info)
+{
+   struct sifive_ccache *priv = dev_get_priv(dev);
+
+   info->base = (phys_addr_t)priv->base;
+
+   return 0;
+}
+
+static const struct cache_ops sifive_ccache_ops = {
+   .enable = sifive_ccache_enable,
+   .get_info = sifive_ccache_get_info,
+};
+
+static int sifive_ccache_probe(struct udevice *dev)
+{
+   struct sifive_ccache *priv = dev_get_priv(dev);
+
+   priv->base = dev_read_addr_ptr(dev);
+   if (!priv->base)
+   return -EINVAL;
+
+   return 0;
+}
+
+static const struct udevice_id sifive_ccache_ids[] = {
+   { .compatible = "sifive,fu540-c000-ccache" },
+   { .compatible = "sifive,fu740-c000-ccache" },
+   {}
+};
+
+U_BOOT_DRIVER(sifive_ccache) = {
+   .name = "sifive_ccache",
+   .id = UCLASS_CACHE,
+   .of_match = sifive_ccache_ids,
+   .probe = sifive_ccache_probe,
+   .priv_auto = sizeof(struct sifive_ccache),
+   .ops = _ccache_ops,
+};
-- 
2.32.0

[PATCH v3 0/4] Support SiFive Composable cache driver

2021-08-17 Thread Zong Li

This patch set contains the SiFive composable cache support, and
indroduce an interface to do cache initialization, each platform can
overwrite it by their own implementation.

Changed in v3:
 - Combine some patches
 - Drop the subdirectories of vendor in lib/
 - Rebase codebase

Changed in v2:
 - Refine the ccache driver by Sean's suggestions
 - Introduce a common interface for cache initialization

Zong Li (4):
  cache: add sifive composable cache driver
  riscv: lib: introduce a cache_init interface
  board: sifive: use ccache driver instead of helper function
  riscv: lib: modify the indent

 arch/riscv/Kconfig|  5 ++
 arch/riscv/cpu/fu540/Kconfig  |  2 +
 arch/riscv/cpu/fu540/Makefile |  1 -
 arch/riscv/cpu/fu540/cache.c  | 55 -
 arch/riscv/cpu/fu740/Kconfig  |  2 +
 arch/riscv/cpu/fu740/Makefile |  1 -
 arch/riscv/cpu/fu740/cache.c  | 55 -
 arch/riscv/include/asm/arch-fu540/cache.h | 14 -
 arch/riscv/include/asm/arch-fu740/cache.h | 14 -
 arch/riscv/include/asm/cache.h|  3 +-
 arch/riscv/lib/Makefile   |  1 +
 arch/riscv/lib/cache.c|  5 ++
 arch/riscv/lib/sifive_cache.c | 27 
 board/sifive/unleashed/unleashed.c| 12 +---
 board/sifive/unmatched/unmatched.c| 11 +---
 drivers/cache/Kconfig |  7 +++
 drivers/cache/Makefile|  1 +
 drivers/cache/cache-sifive-ccache.c   | 75 +++
 18 files changed, 131 insertions(+), 160 deletions(-)
 delete mode 100644 arch/riscv/cpu/fu540/cache.c
 delete mode 100644 arch/riscv/cpu/fu740/cache.c
 delete mode 100644 arch/riscv/include/asm/arch-fu540/cache.h
 delete mode 100644 arch/riscv/include/asm/arch-fu740/cache.h
 create mode 100644 arch/riscv/lib/sifive_cache.c
 create mode 100644 drivers/cache/cache-sifive-ccache.c

-- 
2.32.0

Re: [PATCH v2 3/6] riscv: lib: introduce cache_init interface

2021-08-12 Thread Zong Li

On Fri, Aug 13, 2021 at 4:20 AM Sean Anderson  wrote:
>
> On 8/10/21 2:57 AM, Zong Li wrote:
> > On Tue, Aug 10, 2021 at 12:47 PM Sean Anderson  wrote:
> >>
> >> On 8/3/21 12:44 AM, Zong Li wrote:
> >>> Add an interface for cache initialization. Each platform can overwrite
> >>> this weak function by their own implementation, such as sifive_cache in
> >>> this patch.
> >>
> >> Can we call this enable_caches instead of cache_init? This function is
> >> called by initr_caches in board_r.c for ARM. There's even an
> >> eight-year-old TODO on the subject.
> >>
> >
> > I had considered use it, The reason I finally used cache_init here is
> > that it seems to me that cache_init would be more flexible for risc-v
> > platforms to do not only cache enable, but also various
> > platform-specific initialization of cache, even they could decide the
> > time to invoke cache_init if there is particular initialization
> > sequence.
>
> Do you have some example in mind?

It seems to me that not all cache devices are only configured for
operations related to enable/disable. It might refer to the status of
the cache itself or different functionalities, then it might be a bit
weird if we associate them with the "enable" term, It is a
platform-specific implementation.

>
> > If you think that cache_init is OK to you, I would prefer to
> > retain cache_init. I can still use enable_caches instead of cache_init
> > if you think that it is a better way. Please let me know your thoughts
> > and thanks for your review.
>
> I would like to reduce the proliferation of different cache enable
> functions. Right now we have (i|d)cache_enable which are RISC-V-specific
> and called very early during boot; cache_enable, which must be called
> manually; enable_caches, which is implemented only for ARM; and your
> proposed cache_init. I don't think there is need for yet another way to
> accomplish the same thing.
>
> --Sean
>
> >>>
> >>> Signed-off-by: Zong Li 
> >>> ---
> >>>arch/riscv/Kconfig |  5 +
> >>>arch/riscv/include/asm/cache.h |  1 +
> >>>arch/riscv/lib/Makefile|  1 +
> >>>arch/riscv/lib/cache.c |  5 +
> >>>arch/riscv/lib/sifive_cache.c  | 27 +++
> >>>5 files changed, 39 insertions(+)
> >>>create mode 100644 arch/riscv/lib/sifive_cache.c
> >>>
> >>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> >>> index 4b0c3dffa6..ec651fe0a4 100644
> >>> --- a/arch/riscv/Kconfig
> >>> +++ b/arch/riscv/Kconfig
> >>> @@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT
> >>>  The SiFive CLINT block holds memory-mapped control and status 
> >>> registers
> >>>  associated with software and timer interrupts.
> >>>
> >>> +config SIFIVE_CACHE
> >>> + bool
> >>> + help
> >>> +   This enables the operations to configure SiFive cache
> >>> +
> >>>config ANDES_PLIC
> >>>bool
> >>>depends on RISCV_MMODE || SPL_RISCV_MMODE
> >>> diff --git a/arch/riscv/include/asm/cache.h 
> >>> b/arch/riscv/include/asm/cache.h
> >>> index ec8fe201d3..6ebb2b4329 100644
> >>> --- a/arch/riscv/include/asm/cache.h
> >>> +++ b/arch/riscv/include/asm/cache.h
> >>> @@ -9,6 +9,7 @@
> >>>
> >>>/* cache */
> >>>voidcache_flush(void);
> >>> +int cache_init(void);
> >>>
> >>>/*
> >>> * The current upper bound for RISCV L1 data cache line sizes is 32 
> >>> bytes.
> >>> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> >>> index c4cc41434b..06020fcc2a 100644
> >>> --- a/arch/riscv/lib/Makefile
> >>> +++ b/arch/riscv/lib/Makefile
> >>> @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
> >>>obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
> >>>obj-$(CONFIG_CMD_GO) += boot.o
> >>>obj-y   += cache.o
> >>> +obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
> >>>ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
> >>>obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
> >>>obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
> >>> diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
> &g

Re: [PATCH v2 5/6] riscv: lib: move platform-related libraries to sperate folder

2021-08-12 Thread Zong Li

On Fri, Aug 13, 2021 at 4:22 AM Sean Anderson  wrote:
>
> On 8/10/21 3:04 AM, Zong Li wrote:
> > On Tue, Aug 10, 2021 at 12:55 PM Sean Anderson  wrote:
> >>
> >>> Re: [PATCH v2 5/6] riscv: lib: move platform-related libraries to sperate 
> >>> folder
> >>
> >> nit: separate
> >>
> >
> > Thanks for catching it. Fix it in the next version.
> >
> >> On 8/3/21 12:44 AM, Zong Li wrote:
> >>> Put the platform-related implementation into their own folder
> >>> respectively. Just leave the common library in the top of lib
> >>> folder.
> >>>
> >>> Signed-off-by: Zong Li 
> >>> ---
> >>>arch/riscv/Kconfig  | 7 +++
> >>>arch/riscv/lib/Makefile | 9 -
> >>>arch/riscv/lib/andestech/Kconfig| 8 
> >>>arch/riscv/lib/andestech/Makefile   | 7 +++
> >>>arch/riscv/lib/{ => andestech}/andes_plic.c | 0
> >>>arch/riscv/lib/sifive/Kconfig   | 8 
> >>>arch/riscv/lib/sifive/Makefile  | 9 +
> >>>arch/riscv/lib/{ => sifive}/sifive_cache.c  | 0
> >>>arch/riscv/lib/{ => sifive}/sifive_clint.c  | 0
> >>>9 files changed, 43 insertions(+), 5 deletions(-)
> >>>create mode 100644 arch/riscv/lib/andestech/Kconfig
> >>>create mode 100644 arch/riscv/lib/andestech/Makefile
> >>>rename arch/riscv/lib/{ => andestech}/andes_plic.c (100%)
> >>>create mode 100644 arch/riscv/lib/sifive/Kconfig
> >>>create mode 100644 arch/riscv/lib/sifive/Makefile
> >>>rename arch/riscv/lib/{ => sifive}/sifive_cache.c (100%)
> >>>rename arch/riscv/lib/{ => sifive}/sifive_clint.c (100%)
> >>
> >> NAK from me. I'd much rather see organization by function (e.g.
> >> clint/sbi/plic together) than by vendor. Plus, the clint/plic are not
> >> really specific to one vendor like ccache.
> >>
> >
> > Yes, it makes more sense to me. In this case, there are three
> > functionalities, so I'd like to separate clint, plic and cache at this
> > time, does it make sense to you?
>
> No, it does not. clint and plic should be grouped with SBI because in
> U-Boot they are all used for IPIs. But frankly, I don't really see the
> need to place them in subdirectories yet...
>

Okay, I got it, how about only separate cache into a subdirectory? Or
you think that it might be OK to just put all of them in lib/ ?

> --Sean
>
> >
> >> --Sean
> >>
> >>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> >>> index ec651fe0a4..ed1bf2f6c8 100644
> >>> --- a/arch/riscv/Kconfig
> >>> +++ b/arch/riscv/Kconfig
> >>> @@ -72,6 +72,10 @@ source "arch/riscv/cpu/fu540/Kconfig"
> >>>source "arch/riscv/cpu/fu740/Kconfig"
> >>>source "arch/riscv/cpu/generic/Kconfig"
> >>>
> >>> +# library-specific options below
> >>> +source "arch/riscv/lib/sifive/Kconfig"
> >>> +source "arch/riscv/lib/andestech/Kconfig"
> >>> +
> >>># architecture-specific options below
> >>>
> >>>choice
> >>> @@ -175,18 +179,21 @@ config SIFIVE_CLINT
> >>>config SPL_SIFIVE_CLINT
> >>>bool
> >>>depends on SPL_RISCV_MMODE
> >>> + select SIFIVE_LIB
> >>>help
> >>>  The SiFive CLINT block holds memory-mapped control and status 
> >>> registers
> >>>  associated with software and timer interrupts.
> >>>
> >>>config SIFIVE_CACHE
> >>>bool
> >>> + select SIFIVE_LIB
> >>>help
> >>>  This enables the operations to configure SiFive cache
> >>>
> >>>config ANDES_PLIC
> >>>bool
> >>>depends on RISCV_MMODE || SPL_RISCV_MMODE
> >>> + select ANDESTECH_LIB
> >>>select REGMAP
> >>>select SYSCON
> >>>select SPL_REGMAP if SPL
> >>> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> >>> index 06020fcc2a..f58d1f9819 100644
> >>> --- a/arch/riscv/lib/Makefile
> >>> +++ b/arch/riscv/lib/Makefile
> >>> @@ -10,11 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
>

Re: [PATCH v2 5/6] riscv: lib: move platform-related libraries to sperate folder

2021-08-10 Thread Zong Li

On Tue, Aug 10, 2021 at 12:55 PM Sean Anderson  wrote:
>
> > Re: [PATCH v2 5/6] riscv: lib: move platform-related libraries to sperate 
> > folder
>
> nit: separate
>

Thanks for catching it. Fix it in the next version.

> On 8/3/21 12:44 AM, Zong Li wrote:
> > Put the platform-related implementation into their own folder
> > respectively. Just leave the common library in the top of lib
> > folder.
> >
> > Signed-off-by: Zong Li 
> > ---
> >   arch/riscv/Kconfig  | 7 +++
> >   arch/riscv/lib/Makefile | 9 -
> >   arch/riscv/lib/andestech/Kconfig| 8 
> >   arch/riscv/lib/andestech/Makefile   | 7 +++
> >   arch/riscv/lib/{ => andestech}/andes_plic.c | 0
> >   arch/riscv/lib/sifive/Kconfig   | 8 
> >   arch/riscv/lib/sifive/Makefile  | 9 +
> >   arch/riscv/lib/{ => sifive}/sifive_cache.c  | 0
> >   arch/riscv/lib/{ => sifive}/sifive_clint.c  | 0
> >   9 files changed, 43 insertions(+), 5 deletions(-)
> >   create mode 100644 arch/riscv/lib/andestech/Kconfig
> >   create mode 100644 arch/riscv/lib/andestech/Makefile
> >   rename arch/riscv/lib/{ => andestech}/andes_plic.c (100%)
> >   create mode 100644 arch/riscv/lib/sifive/Kconfig
> >   create mode 100644 arch/riscv/lib/sifive/Makefile
> >   rename arch/riscv/lib/{ => sifive}/sifive_cache.c (100%)
> >   rename arch/riscv/lib/{ => sifive}/sifive_clint.c (100%)
>
> NAK from me. I'd much rather see organization by function (e.g.
> clint/sbi/plic together) than by vendor. Plus, the clint/plic are not
> really specific to one vendor like ccache.
>

Yes, it makes more sense to me. In this case, there are three
functionalities, so I'd like to separate clint, plic and cache at this
time, does it make sense to you?

> --Sean
>
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index ec651fe0a4..ed1bf2f6c8 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -72,6 +72,10 @@ source "arch/riscv/cpu/fu540/Kconfig"
> >   source "arch/riscv/cpu/fu740/Kconfig"
> >   source "arch/riscv/cpu/generic/Kconfig"
> >
> > +# library-specific options below
> > +source "arch/riscv/lib/sifive/Kconfig"
> > +source "arch/riscv/lib/andestech/Kconfig"
> > +
> >   # architecture-specific options below
> >
> >   choice
> > @@ -175,18 +179,21 @@ config SIFIVE_CLINT
> >   config SPL_SIFIVE_CLINT
> >   bool
> >   depends on SPL_RISCV_MMODE
> > + select SIFIVE_LIB
> >   help
> > The SiFive CLINT block holds memory-mapped control and status 
> > registers
> > associated with software and timer interrupts.
> >
> >   config SIFIVE_CACHE
> >   bool
> > + select SIFIVE_LIB
> >   help
> > This enables the operations to configure SiFive cache
> >
> >   config ANDES_PLIC
> >   bool
> >   depends on RISCV_MMODE || SPL_RISCV_MMODE
> > + select ANDESTECH_LIB
> >   select REGMAP
> >   select SYSCON
> >   select SPL_REGMAP if SPL
> > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > index 06020fcc2a..f58d1f9819 100644
> > --- a/arch/riscv/lib/Makefile
> > +++ b/arch/riscv/lib/Makefile
> > @@ -10,11 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
> >   obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
> >   obj-$(CONFIG_CMD_GO) += boot.o
> >   obj-y   += cache.o
> > -obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
> > -ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
> > -obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
> > -obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
> > -else
> > +ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),)
> >   obj-$(CONFIG_SBI) += sbi.o
> >   obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> >   endif
> > @@ -42,3 +38,6 @@ extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC)
> >   obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
> >   obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMMOVE) += memmove.o
> >   obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
> > +
> > +obj-$(CONFIG_SIFIVE_LIB) += sifive/
> > +obj-$(CONFIG_ANDESTECH_LIB) += andestech/
> > diff --git a/arch/riscv/lib/andestech/Kconfig 
> > b/arch/riscv/lib/andestech/Kconfig
> > new file mode 100644
> > index 00..75f83a8123
> > --- /dev/null
> > +++ b/arch/riscv/lib/andestech/Kconfig
> > @@ -0,0 +1,8 @@
> > +# SPDX-License-Identifier: GPL-2.0+
> > +#
> &

Re: [PATCH v2 3/6] riscv: lib: introduce cache_init interface

2021-08-10 Thread Zong Li

On Tue, Aug 10, 2021 at 12:47 PM Sean Anderson  wrote:
>
> On 8/3/21 12:44 AM, Zong Li wrote:
> > Add an interface for cache initialization. Each platform can overwrite
> > this weak function by their own implementation, such as sifive_cache in
> > this patch.
>
> Can we call this enable_caches instead of cache_init? This function is
> called by initr_caches in board_r.c for ARM. There's even an
> eight-year-old TODO on the subject.
>

I had considered use it, The reason I finally used cache_init here is
that it seems to me that cache_init would be more flexible for risc-v
platforms to do not only cache enable, but also various
platform-specific initialization of cache, even they could decide the
time to invoke cache_init if there is particular initialization
sequence. If you think that cache_init is OK to you, I would prefer to
retain cache_init. I can still use enable_caches instead of cache_init
if you think that it is a better way. Please let me know your thoughts
and thanks for your review.

> >
> > Signed-off-by: Zong Li 
> > ---
> >   arch/riscv/Kconfig |  5 +
> >   arch/riscv/include/asm/cache.h |  1 +
> >   arch/riscv/lib/Makefile|  1 +
> >   arch/riscv/lib/cache.c |  5 +
> >   arch/riscv/lib/sifive_cache.c  | 27 +++
> >   5 files changed, 39 insertions(+)
> >   create mode 100644 arch/riscv/lib/sifive_cache.c
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 4b0c3dffa6..ec651fe0a4 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT
> > The SiFive CLINT block holds memory-mapped control and status 
> > registers
> > associated with software and timer interrupts.
> >
> > +config SIFIVE_CACHE
> > + bool
> > + help
> > +   This enables the operations to configure SiFive cache
> > +
> >   config ANDES_PLIC
> >   bool
> >   depends on RISCV_MMODE || SPL_RISCV_MMODE
> > diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
> > index ec8fe201d3..6ebb2b4329 100644
> > --- a/arch/riscv/include/asm/cache.h
> > +++ b/arch/riscv/include/asm/cache.h
> > @@ -9,6 +9,7 @@
> >
> >   /* cache */
> >   voidcache_flush(void);
> > +int cache_init(void);
> >
> >   /*
> >* The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
> > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > index c4cc41434b..06020fcc2a 100644
> > --- a/arch/riscv/lib/Makefile
> > +++ b/arch/riscv/lib/Makefile
> > @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
> >   obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
> >   obj-$(CONFIG_CMD_GO) += boot.o
> >   obj-y   += cache.o
> > +obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
> >   ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
> >   obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
> >   obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
> > diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
> > index b1d42bcc2b..2cd66504c6 100644
> > --- a/arch/riscv/lib/cache.c
> > +++ b/arch/riscv/lib/cache.c
> > @@ -70,3 +70,8 @@ __weak int dcache_status(void)
> >   {
> >   return 0;
> >   }
> > +
> > +__weak int cache_init(void)
> > +{
> > + return 0;
> > +}
> > diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c
> > new file mode 100644
> > index 00..94e84e024e
> > --- /dev/null
> > +++ b/arch/riscv/lib/sifive_cache.c
> > @@ -0,0 +1,27 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2021 SiFive, Inc
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +
> > +int cache_init(void)
> > +{
> > + struct udevice *dev;
> > + int ret;
> > +
> > + /* Enable ways of ccache */
> > + ret = uclass_get_device_by_driver(UCLASS_CACHE,
> > +   DM_DRIVER_GET(sifive_ccache),
> > +   );
> > + if (ret)
> > + return log_msg_ret("Cannot enable cache ways", ret);
> > +
> > + ret = cache_enable(dev);
> > + if (ret)
> > + return log_msg_ret("ccache enable failed", ret);
> > +
> > + return 0;
> > +}
> >
>
> Otherwise LGTM

Re: [PATCH v2 2/6] board: sifive: use ccache driver instead of helper function

2021-08-10 Thread Zong Li

On Tue, Aug 10, 2021 at 12:51 PM Sean Anderson  wrote:
>
> On 8/3/21 12:44 AM, Zong Li wrote:
> > Invokes the generic cache_enable interface to execute the relative
> > implementation in SiFive ccache driver.
> >
> > Signed-off-by: Zong Li 
> > ---
> >   arch/riscv/cpu/fu540/Kconfig  |  1 +
> >   arch/riscv/cpu/fu540/cache.c  | 54 ++-
> >   arch/riscv/cpu/fu740/Kconfig  |  1 +
> >   arch/riscv/cpu/fu740/cache.c  | 52 ++
> >   arch/riscv/include/asm/arch-fu540/cache.h |  2 +-
> >   arch/riscv/include/asm/arch-fu740/cache.h |  2 +-
> >   board/sifive/unleashed/unleashed.c| 10 +
> >   board/sifive/unmatched/unmatched.c|  9 +---
> >   8 files changed, 33 insertions(+), 98 deletions(-)
> >
> > diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
> > index 05463b2625..8608741779 100644
> > --- a/arch/riscv/cpu/fu540/Kconfig
> > +++ b/arch/riscv/cpu/fu540/Kconfig
> > @@ -19,6 +19,7 @@ config SIFIVE_FU540
> >   imply SMP
> >   imply CLK_SIFIVE
> >   imply CLK_SIFIVE_PRCI
> > + imply SIFIVE_CCACHE
> >   imply SIFIVE_SERIAL
> >   imply MACB
> >   imply MII
> > diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c
> > index 0fc4ef6c00..bc31f664b8 100644
> > --- a/arch/riscv/cpu/fu540/cache.c
> > +++ b/arch/riscv/cpu/fu540/cache.c
> > @@ -1,55 +1,29 @@
> >   // SPDX-License-Identifier: GPL-2.0+
> >   /*
> > - * Copyright (C) 2020 SiFive, Inc
> > + * Copyright (C) 2020 - 2021 SiFive, Inc
> >*
> >* Authors:
> >*   Pragnesh Patel 
> >*/
> >
> >   #include 
> > -#include 
> > -#include 
> > -#include 
> > +#include 
> > +#include 
> >
> > -/* Register offsets */
> > -#define L2_CACHE_CONFIG  0x000
> > -#define L2_CACHE_ENABLE  0x008
> > -
> > -#define MASK_NUM_WAYSGENMASK(15, 8)
> > -#define NUM_WAYS_SHIFT   8
> > -
> > -DECLARE_GLOBAL_DATA_PTR;
> > -
> > -int cache_enable_ways(void)
> > +int sifive_ccache_enable_ways(void)
> >   {
> > - const void *blob = gd->fdt_blob;
> > - int node;
> > - fdt_addr_t base;
> > - u32 config;
> > - u32 ways;
> > -
> > - volatile u32 *enable;
> > -
> > - node = fdt_node_offset_by_compatible(blob, -1,
> > -  "sifive,fu540-c000-ccache");
> > -
> > - if (node < 0)
> > - return node;
> > -
> > - base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
> > - NULL, false);
> > - if (base == FDT_ADDR_T_NONE)
> > - return FDT_ADDR_T_NONE;
> > + struct udevice *dev;
> > + int ret;
> >
> > - config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
> > - ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
> > + ret = uclass_get_device_by_driver(UCLASS_CACHE,
> > +   DM_DRIVER_GET(sifive_ccache),
> > +   );
> > + if (ret)
> > + return log_msg_ret("Cannot enable cache ways", ret);
> >
> > - enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
> > + ret = cache_enable(dev);
> > + if (ret)
> > + return log_msg_ret("ccache enable failed", ret);
> >
> > - /* memory barrier */
> > - mb();
> > - (*enable) = ways - 1;
> > - /* memory barrier */
> > - mb();
> >   return 0;
> >   }
> > diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
> > index 408195f149..b4cada0ea9 100644
> > --- a/arch/riscv/cpu/fu740/Kconfig
> > +++ b/arch/riscv/cpu/fu740/Kconfig
> > @@ -19,6 +19,7 @@ config SIFIVE_FU740
> >   imply SMP
> >   imply CLK_SIFIVE
> >   imply CLK_SIFIVE_PRCI
> > + imply SIFIVE_CCACHE
> >   imply SIFIVE_SERIAL
> >   imply MACB
> >   imply MII
> > diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c
> > index 680955c9e3..e2782d76c0 100644
> > --- a/arch/riscv/cpu/fu740/cache.c
> > +++ b/arch/riscv/cpu/fu740/cache.c
> > @@ -7,49 +7,23 @@
> >*/
> >
> >   #include 
> > -#include 
> > -#include 
> > -#include

[PATCH v2 6/6] riscv: lib: modify the indent

2021-08-02 Thread Zong Li

We usually use a space in function declaration, rather than a tab.

Signed-off-by: Zong Li 
---
 arch/riscv/include/asm/cache.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index 6ebb2b4329..b700ff5021 100644
--- a/arch/riscv/include/asm/cache.h
+++ b/arch/riscv/include/asm/cache.h
@@ -8,7 +8,7 @@
 #define _ASM_RISCV_CACHE_H
 
 /* cache */
-void   cache_flush(void);
+void cache_flush(void);
 int cache_init(void);
 
 /*
-- 
2.32.0

[PATCH v2 5/6] riscv: lib: move platform-related libraries to sperate folder

2021-08-02 Thread Zong Li

Put the platform-related implementation into their own folder
respectively. Just leave the common library in the top of lib
folder.

Signed-off-by: Zong Li 
---
 arch/riscv/Kconfig  | 7 +++
 arch/riscv/lib/Makefile | 9 -
 arch/riscv/lib/andestech/Kconfig| 8 
 arch/riscv/lib/andestech/Makefile   | 7 +++
 arch/riscv/lib/{ => andestech}/andes_plic.c | 0
 arch/riscv/lib/sifive/Kconfig   | 8 
 arch/riscv/lib/sifive/Makefile  | 9 +
 arch/riscv/lib/{ => sifive}/sifive_cache.c  | 0
 arch/riscv/lib/{ => sifive}/sifive_clint.c  | 0
 9 files changed, 43 insertions(+), 5 deletions(-)
 create mode 100644 arch/riscv/lib/andestech/Kconfig
 create mode 100644 arch/riscv/lib/andestech/Makefile
 rename arch/riscv/lib/{ => andestech}/andes_plic.c (100%)
 create mode 100644 arch/riscv/lib/sifive/Kconfig
 create mode 100644 arch/riscv/lib/sifive/Makefile
 rename arch/riscv/lib/{ => sifive}/sifive_cache.c (100%)
 rename arch/riscv/lib/{ => sifive}/sifive_clint.c (100%)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ec651fe0a4..ed1bf2f6c8 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -72,6 +72,10 @@ source "arch/riscv/cpu/fu540/Kconfig"
 source "arch/riscv/cpu/fu740/Kconfig"
 source "arch/riscv/cpu/generic/Kconfig"
 
+# library-specific options below
+source "arch/riscv/lib/sifive/Kconfig"
+source "arch/riscv/lib/andestech/Kconfig"
+
 # architecture-specific options below
 
 choice
@@ -175,18 +179,21 @@ config SIFIVE_CLINT
 config SPL_SIFIVE_CLINT
bool
depends on SPL_RISCV_MMODE
+   select SIFIVE_LIB
help
  The SiFive CLINT block holds memory-mapped control and status 
registers
  associated with software and timer interrupts.
 
 config SIFIVE_CACHE
bool
+   select SIFIVE_LIB
help
  This enables the operations to configure SiFive cache
 
 config ANDES_PLIC
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
+   select ANDESTECH_LIB
select REGMAP
select SYSCON
select SPL_REGMAP if SPL
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 06020fcc2a..f58d1f9819 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -10,11 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
 obj-$(CONFIG_CMD_GO) += boot.o
 obj-y  += cache.o
-obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
-ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
-obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
-obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
-else
+ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),)
 obj-$(CONFIG_SBI) += sbi.o
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
 endif
@@ -42,3 +38,6 @@ extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC)
 obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
 obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMMOVE) += memmove.o
 obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
+
+obj-$(CONFIG_SIFIVE_LIB) += sifive/
+obj-$(CONFIG_ANDESTECH_LIB) += andestech/
diff --git a/arch/riscv/lib/andestech/Kconfig b/arch/riscv/lib/andestech/Kconfig
new file mode 100644
index 00..75f83a8123
--- /dev/null
+++ b/arch/riscv/lib/andestech/Kconfig
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021 SiFive, Inc
+
+config ANDESTECH_LIB
+   bool
+   help
+ This supports the specific libraries for AndesTech platforms
diff --git a/arch/riscv/lib/andestech/Makefile 
b/arch/riscv/lib/andestech/Makefile
new file mode 100644
index 00..49f45d0a29
--- /dev/null
+++ b/arch/riscv/lib/andestech/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021 SiFive, Inc
+
+ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
+obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
+endif
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andestech/andes_plic.c
similarity index 100%
rename from arch/riscv/lib/andes_plic.c
rename to arch/riscv/lib/andestech/andes_plic.c
diff --git a/arch/riscv/lib/sifive/Kconfig b/arch/riscv/lib/sifive/Kconfig
new file mode 100644
index 00..20574079e9
--- /dev/null
+++ b/arch/riscv/lib/sifive/Kconfig
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021 SiFive, Inc
+
+config SIFIVE_LIB
+   bool
+   help
+ This supports the specific libraries for SiFive platforms
diff --git a/arch/riscv/lib/sifive/Makefile b/arch/riscv/lib/sifive/Makefile
new file mode 100644
index 00..ba120db26a
--- /dev/null
+++ b/arch/riscv/lib/sifive/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021 SiFive, Inc
+
+obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
+
+ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
+obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
+endif
diff --git a/arch/riscv/lib/sifive_cache.c 
b/arch/riscv/lib/sifive/sifive_cache.c
similarity index 100

[PATCH v2 4/6] riscv: sifive: use common cache_init instead of duplicated implementation

2021-08-02 Thread Zong Li

We already extracted the duplicated implementation to common code, so
change to use that and drop the original implementation.

Signed-off-by: Zong Li 
---
 arch/riscv/cpu/fu540/Kconfig  |  1 +
 arch/riscv/cpu/fu540/Makefile |  1 -
 arch/riscv/cpu/fu540/cache.c  | 29 ---
 arch/riscv/cpu/fu740/Kconfig  |  1 +
 arch/riscv/cpu/fu740/Makefile |  1 -
 arch/riscv/cpu/fu740/cache.c  | 29 ---
 arch/riscv/include/asm/arch-fu540/cache.h | 14 ---
 arch/riscv/include/asm/arch-fu740/cache.h | 14 ---
 board/sifive/unleashed/unleashed.c|  4 ++--
 board/sifive/unmatched/unmatched.c|  4 ++--
 10 files changed, 6 insertions(+), 92 deletions(-)
 delete mode 100644 arch/riscv/cpu/fu540/cache.c
 delete mode 100644 arch/riscv/cpu/fu740/cache.c
 delete mode 100644 arch/riscv/include/asm/arch-fu540/cache.h
 delete mode 100644 arch/riscv/include/asm/arch-fu740/cache.h

diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
index 8608741779..1604b412b4 100644
--- a/arch/riscv/cpu/fu540/Kconfig
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -19,6 +19,7 @@ config SIFIVE_FU540
imply SMP
imply CLK_SIFIVE
imply CLK_SIFIVE_PRCI
+   imply SIFIVE_CACHE
imply SIFIVE_CCACHE
imply SIFIVE_SERIAL
imply MACB
diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile
index 088205ef57..043fb961a5 100644
--- a/arch/riscv/cpu/fu540/Makefile
+++ b/arch/riscv/cpu/fu540/Makefile
@@ -8,5 +8,4 @@ obj-y += spl.o
 else
 obj-y += dram.o
 obj-y += cpu.o
-obj-y += cache.o
 endif
diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c
deleted file mode 100644
index bc31f664b8..00
--- a/arch/riscv/cpu/fu540/cache.c
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020 - 2021 SiFive, Inc
- *
- * Authors:
- *   Pragnesh Patel 
- */
-
-#include 
-#include 
-#include 
-
-int sifive_ccache_enable_ways(void)
-{
-   struct udevice *dev;
-   int ret;
-
-   ret = uclass_get_device_by_driver(UCLASS_CACHE,
- DM_DRIVER_GET(sifive_ccache),
- );
-   if (ret)
-   return log_msg_ret("Cannot enable cache ways", ret);
-
-   ret = cache_enable(dev);
-   if (ret)
-   return log_msg_ret("ccache enable failed", ret);
-
-   return 0;
-}
diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
index b4cada0ea9..049a0a0584 100644
--- a/arch/riscv/cpu/fu740/Kconfig
+++ b/arch/riscv/cpu/fu740/Kconfig
@@ -19,6 +19,7 @@ config SIFIVE_FU740
imply SMP
imply CLK_SIFIVE
imply CLK_SIFIVE_PRCI
+   imply SIFIVE_CACHE
imply SIFIVE_CCACHE
imply SIFIVE_SERIAL
imply MACB
diff --git a/arch/riscv/cpu/fu740/Makefile b/arch/riscv/cpu/fu740/Makefile
index 5ef8ac18a7..1d1ad98ba7 100644
--- a/arch/riscv/cpu/fu740/Makefile
+++ b/arch/riscv/cpu/fu740/Makefile
@@ -8,5 +8,4 @@ obj-y += spl.o
 else
 obj-y += dram.o
 obj-y += cpu.o
-obj-y += cache.o
 endif
diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c
deleted file mode 100644
index e2782d76c0..00
--- a/arch/riscv/cpu/fu740/cache.c
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020-2021 SiFive, Inc
- *
- * Authors:
- *   Pragnesh Patel 
- */
-
-#include 
-#include 
-#include 
-
-int sifive_ccache_enable_ways(void)
-{
-   struct udevice *dev;
-   int ret;
-
-   ret = uclass_get_device_by_driver(UCLASS_CACHE,
- DM_DRIVER_GET(sifive_ccache),
- );
-   if (ret)
-   return log_msg_ret("Cannot enable cache ways", ret);
-
-   ret = cache_enable(dev);
-   if (ret)
-   return log_msg_ret("ccache enable failed", ret);
-
-   return 0;
-}
diff --git a/arch/riscv/include/asm/arch-fu540/cache.h 
b/arch/riscv/include/asm/arch-fu540/cache.h
deleted file mode 100644
index c252eb64d1..00
--- a/arch/riscv/include/asm/arch-fu540/cache.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2020 SiFive, Inc.
- *
- * Authors:
- *   Pragnesh Patel 
- */
-
-#ifndef _CACHE_SIFIVE_H
-#define _CACHE_SIFIVE_H
-
-int sifive_ccache_enable_ways(void);
-
-#endif /* _CACHE_SIFIVE_H */
diff --git a/arch/riscv/include/asm/arch-fu740/cache.h 
b/arch/riscv/include/asm/arch-fu740/cache.h
deleted file mode 100644
index 8c456e3658..00
--- a/arch/riscv/include/asm/arch-fu740/cache.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2020-2021 SiFive, Inc.
- *
- * Authors:
- *   Pragnesh Patel 
- */
-
-#ifndef _CACHE_SIFIVE_H
-#define _CACHE_SIFIVE_H
-
-int sifive_ccache_enable_

[PATCH v2 3/6] riscv: lib: introduce cache_init interface

2021-08-02 Thread Zong Li

Add an interface for cache initialization. Each platform can overwrite
this weak function by their own implementation, such as sifive_cache in
this patch.

Signed-off-by: Zong Li 
---
 arch/riscv/Kconfig |  5 +
 arch/riscv/include/asm/cache.h |  1 +
 arch/riscv/lib/Makefile|  1 +
 arch/riscv/lib/cache.c |  5 +
 arch/riscv/lib/sifive_cache.c  | 27 +++
 5 files changed, 39 insertions(+)
 create mode 100644 arch/riscv/lib/sifive_cache.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 4b0c3dffa6..ec651fe0a4 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT
  The SiFive CLINT block holds memory-mapped control and status 
registers
  associated with software and timer interrupts.
 
+config SIFIVE_CACHE
+   bool
+   help
+ This enables the operations to configure SiFive cache
+
 config ANDES_PLIC
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index ec8fe201d3..6ebb2b4329 100644
--- a/arch/riscv/include/asm/cache.h
+++ b/arch/riscv/include/asm/cache.h
@@ -9,6 +9,7 @@
 
 /* cache */
 void   cache_flush(void);
+int cache_init(void);
 
 /*
  * The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index c4cc41434b..06020fcc2a 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
 obj-$(CONFIG_CMD_GO) += boot.o
 obj-y  += cache.o
+obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
 ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
 obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index b1d42bcc2b..2cd66504c6 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -70,3 +70,8 @@ __weak int dcache_status(void)
 {
return 0;
 }
+
+__weak int cache_init(void)
+{
+   return 0;
+}
diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c
new file mode 100644
index 00..94e84e024e
--- /dev/null
+++ b/arch/riscv/lib/sifive_cache.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 SiFive, Inc
+ */
+
+#include 
+#include 
+#include 
+
+int cache_init(void)
+{
+   struct udevice *dev;
+   int ret;
+
+   /* Enable ways of ccache */
+   ret = uclass_get_device_by_driver(UCLASS_CACHE,
+ DM_DRIVER_GET(sifive_ccache),
+ );
+   if (ret)
+   return log_msg_ret("Cannot enable cache ways", ret);
+
+   ret = cache_enable(dev);
+   if (ret)
+   return log_msg_ret("ccache enable failed", ret);
+
+   return 0;
+}
-- 
2.32.0

[PATCH v2 2/6] board: sifive: use ccache driver instead of helper function

2021-08-02 Thread Zong Li

Invokes the generic cache_enable interface to execute the relative
implementation in SiFive ccache driver.

Signed-off-by: Zong Li 
---
 arch/riscv/cpu/fu540/Kconfig  |  1 +
 arch/riscv/cpu/fu540/cache.c  | 54 ++-
 arch/riscv/cpu/fu740/Kconfig  |  1 +
 arch/riscv/cpu/fu740/cache.c  | 52 ++
 arch/riscv/include/asm/arch-fu540/cache.h |  2 +-
 arch/riscv/include/asm/arch-fu740/cache.h |  2 +-
 board/sifive/unleashed/unleashed.c| 10 +
 board/sifive/unmatched/unmatched.c|  9 +---
 8 files changed, 33 insertions(+), 98 deletions(-)

diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
index 05463b2625..8608741779 100644
--- a/arch/riscv/cpu/fu540/Kconfig
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -19,6 +19,7 @@ config SIFIVE_FU540
imply SMP
imply CLK_SIFIVE
imply CLK_SIFIVE_PRCI
+   imply SIFIVE_CCACHE
imply SIFIVE_SERIAL
imply MACB
imply MII
diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c
index 0fc4ef6c00..bc31f664b8 100644
--- a/arch/riscv/cpu/fu540/cache.c
+++ b/arch/riscv/cpu/fu540/cache.c
@@ -1,55 +1,29 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2020 SiFive, Inc
+ * Copyright (C) 2020 - 2021 SiFive, Inc
  *
  * Authors:
  *   Pragnesh Patel 
  */
 
 #include 
-#include 
-#include 
-#include 
+#include 
+#include 
 
-/* Register offsets */
-#define L2_CACHE_CONFIG0x000
-#define L2_CACHE_ENABLE0x008
-
-#define MASK_NUM_WAYS  GENMASK(15, 8)
-#define NUM_WAYS_SHIFT 8
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int cache_enable_ways(void)
+int sifive_ccache_enable_ways(void)
 {
-   const void *blob = gd->fdt_blob;
-   int node;
-   fdt_addr_t base;
-   u32 config;
-   u32 ways;
-
-   volatile u32 *enable;
-
-   node = fdt_node_offset_by_compatible(blob, -1,
-"sifive,fu540-c000-ccache");
-
-   if (node < 0)
-   return node;
-
-   base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
-   NULL, false);
-   if (base == FDT_ADDR_T_NONE)
-   return FDT_ADDR_T_NONE;
+   struct udevice *dev;
+   int ret;
 
-   config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
-   ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
+   ret = uclass_get_device_by_driver(UCLASS_CACHE,
+ DM_DRIVER_GET(sifive_ccache),
+ );
+   if (ret)
+   return log_msg_ret("Cannot enable cache ways", ret);
 
-   enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
+   ret = cache_enable(dev);
+   if (ret)
+   return log_msg_ret("ccache enable failed", ret);
 
-   /* memory barrier */
-   mb();
-   (*enable) = ways - 1;
-   /* memory barrier */
-   mb();
return 0;
 }
diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
index 408195f149..b4cada0ea9 100644
--- a/arch/riscv/cpu/fu740/Kconfig
+++ b/arch/riscv/cpu/fu740/Kconfig
@@ -19,6 +19,7 @@ config SIFIVE_FU740
imply SMP
imply CLK_SIFIVE
imply CLK_SIFIVE_PRCI
+   imply SIFIVE_CCACHE
imply SIFIVE_SERIAL
imply MACB
imply MII
diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c
index 680955c9e3..e2782d76c0 100644
--- a/arch/riscv/cpu/fu740/cache.c
+++ b/arch/riscv/cpu/fu740/cache.c
@@ -7,49 +7,23 @@
  */
 
 #include 
-#include 
-#include 
-#include 
+#include 
+#include 
 
-/* Register offsets */
-#define L2_CACHE_CONFIG0x000
-#define L2_CACHE_ENABLE0x008
-
-#define MASK_NUM_WAYS  GENMASK(15, 8)
-#define NUM_WAYS_SHIFT 8
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int cache_enable_ways(void)
+int sifive_ccache_enable_ways(void)
 {
-   const void *blob = gd->fdt_blob;
-   int node;
-   fdt_addr_t base;
-   u32 config;
-   u32 ways;
-
-   volatile u32 *enable;
-
-   node = fdt_node_offset_by_compatible(blob, -1,
-"sifive,fu740-c000-ccache");
-
-   if (node < 0)
-   return node;
-
-   base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
-   NULL, false);
-   if (base == FDT_ADDR_T_NONE)
-   return FDT_ADDR_T_NONE;
+   struct udevice *dev;
+   int ret;
 
-   config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
-   ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
+   ret = uclass_get_device_by_driver(UCLASS_CACHE,
+ DM_DRIVER_GET(sifive_ccache),
+ );
+   if (ret)
+   return log_msg_ret("Cannot e

[PATCH v2 1/6] cache: add sifive composable cache driver

2021-08-02 Thread Zong Li

This driver is currently responsible for enabling all ccache ways.
Composable cache could be configure as RAM or cache, we will use it as
RAM at the beginning to put the u-boot SPL there. In u-boot proper
phrase, we will use the composable cache as cache, and try to enable the
cache ways.

Signed-off-by: Zong Li 
---
 drivers/cache/Kconfig   |  7 +++
 drivers/cache/Makefile  |  1 +
 drivers/cache/cache-sifive-ccache.c | 75 +
 3 files changed, 83 insertions(+)
 create mode 100644 drivers/cache/cache-sifive-ccache.c

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 1e452ad6d9..40f41a817c 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -39,4 +39,11 @@ config NCORE_CACHE
  controller. The driver initializes cache directories and coherent
  agent interfaces.
 
+config SIFIVE_CCACHE
+   bool "SiFive composable cache"
+   select CACHE
+   help
+ This driver is for SiFive Composable L2/L3 cache. It enables cache
+ ways of composable cache.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index fed50be3f9..ad765774e3 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_SANDBOX) += sandbox_cache.o
 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
 obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
 obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
+obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o
diff --git a/drivers/cache/cache-sifive-ccache.c 
b/drivers/cache/cache-sifive-ccache.c
new file mode 100644
index 00..76c0ab26ae
--- /dev/null
+++ b/drivers/cache/cache-sifive-ccache.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 SiFive
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SIFIVE_CCACHE_CONFIG   0x000
+#define SIFIVE_CCACHE_CONFIG_WAYS  GENMASK(15, 8)
+
+#define SIFIVE_CCACHE_WAY_ENABLE   0x008
+
+struct sifive_ccache {
+   void __iomem *base;
+};
+
+static int sifive_ccache_enable(struct udevice *dev)
+{
+   struct sifive_ccache *priv = dev_get_priv(dev);
+   u32 config;
+   u32 ways;
+
+   /* Enable all ways of composable cache */
+   config = readl(priv->base + SIFIVE_CCACHE_CONFIG);
+   ways = FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS, config);
+
+   writel(ways - 1, priv->base + SIFIVE_CCACHE_WAY_ENABLE);
+
+   return 0;
+}
+
+static int sifive_ccache_get_info(struct udevice *dev, struct cache_info *info)
+{
+   struct sifive_ccache *priv = dev_get_priv(dev);
+
+   info->base = (phys_addr_t)priv->base;
+
+   return 0;
+}
+
+static const struct cache_ops sifive_ccache_ops = {
+   .enable = sifive_ccache_enable,
+   .get_info = sifive_ccache_get_info,
+};
+
+static int sifive_ccache_probe(struct udevice *dev)
+{
+   struct sifive_ccache *priv = dev_get_priv(dev);
+
+   priv->base = dev_read_addr_ptr(dev);
+   if (!priv->base)
+   return -EINVAL;
+
+   return 0;
+}
+
+static const struct udevice_id sifive_ccache_ids[] = {
+   { .compatible = "sifive,fu540-c000-ccache" },
+   { .compatible = "sifive,fu740-c000-ccache" },
+   {}
+};
+
+U_BOOT_DRIVER(sifive_ccache) = {
+   .name = "sifive_ccache",
+   .id = UCLASS_CACHE,
+   .of_match = sifive_ccache_ids,
+   .probe = sifive_ccache_probe,
+   .priv_auto = sizeof(struct sifive_ccache),
+   .ops = _ccache_ops,
+};
-- 
2.32.0

[PATCH v2 0/6] Support SiFive Composable cache driver

2021-08-02 Thread Zong Li

This patch set contains the SiFive composable cache support, and
indroduce an interface to do cache initialization, each platform can
overwrite it by their own implementation.

Changed in v2:
 - Refine the ccache driver by Sean's suggestions
 - Introduce a common interface for cache initialization

Zong Li (6):
  cache: add sifive composable cache driver
  board: sifive: use ccache driver instead of helper function
  riscv: lib: introduce cache_init interface
  riscv: sifive: use common cache_init instead of duplicated
implementation
  riscv: lib: move platform-related libraries to sperate folder
  riscv: lib: modify the indent

 arch/riscv/Kconfig  | 12 
 arch/riscv/cpu/fu540/Kconfig|  2 +
 arch/riscv/cpu/fu540/Makefile   |  1 -
 arch/riscv/cpu/fu540/cache.c| 55 ---
 arch/riscv/cpu/fu740/Kconfig|  2 +
 arch/riscv/cpu/fu740/Makefile   |  1 -
 arch/riscv/cpu/fu740/cache.c| 55 ---
 arch/riscv/include/asm/arch-fu540/cache.h   | 14 
 arch/riscv/include/asm/arch-fu740/cache.h   | 14 
 arch/riscv/include/asm/cache.h  |  3 +-
 arch/riscv/lib/Makefile |  8 +--
 arch/riscv/lib/andestech/Kconfig|  8 +++
 arch/riscv/lib/andestech/Makefile   |  7 ++
 arch/riscv/lib/{ => andestech}/andes_plic.c |  0
 arch/riscv/lib/cache.c  |  5 ++
 arch/riscv/lib/sifive/Kconfig   |  8 +++
 arch/riscv/lib/sifive/Makefile  |  9 +++
 arch/riscv/lib/sifive/sifive_cache.c| 27 
 arch/riscv/lib/{ => sifive}/sifive_clint.c  |  0
 board/sifive/unleashed/unleashed.c  | 12 +---
 board/sifive/unmatched/unmatched.c  | 11 +--
 drivers/cache/Kconfig   |  7 ++
 drivers/cache/Makefile  |  1 +
 drivers/cache/cache-sifive-ccache.c | 75 +
 24 files changed, 173 insertions(+), 164 deletions(-)
 delete mode 100644 arch/riscv/cpu/fu540/cache.c
 delete mode 100644 arch/riscv/cpu/fu740/cache.c
 delete mode 100644 arch/riscv/include/asm/arch-fu540/cache.h
 delete mode 100644 arch/riscv/include/asm/arch-fu740/cache.h
 create mode 100644 arch/riscv/lib/andestech/Kconfig
 create mode 100644 arch/riscv/lib/andestech/Makefile
 rename arch/riscv/lib/{ => andestech}/andes_plic.c (100%)
 create mode 100644 arch/riscv/lib/sifive/Kconfig
 create mode 100644 arch/riscv/lib/sifive/Makefile
 create mode 100644 arch/riscv/lib/sifive/sifive_cache.c
 rename arch/riscv/lib/{ => sifive}/sifive_clint.c (100%)
 create mode 100644 drivers/cache/cache-sifive-ccache.c

-- 
2.32.0

[PATCH] riscv: cpu: fu740: Fix typo of date

2021-08-02 Thread Zong Li

Fixed the typo of date of copyright declaration.

Signed-off-by: Zong Li 
---
 arch/riscv/cpu/fu740/spl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/cpu/fu740/spl.c b/arch/riscv/cpu/fu740/spl.c
index 55e30346ff..c6816e9ed4 100644
--- a/arch/riscv/cpu/fu740/spl.c
+++ b/arch/riscv/cpu/fu740/spl.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2020-201 SiFive, Inc
+ * Copyright (C) 2020-2021 SiFive, Inc
  * Pragnesh Patel 
  */
 
-- 
2.32.0

Re: [PATCH 2/2] board: sifive: use ccache driver instead of helper function

2021-07-30 Thread Zong Li

On Thu, Jul 29, 2021 at 8:26 PM Zong Li  wrote:
>
> On Wed, Jul 28, 2021 at 11:18 PM Sean Anderson  wrote:
> >
> > On 7/28/21 3:25 AM, Zong Li wrote:
> > > On Wed, Jul 28, 2021 at 12:29 PM Sean Anderson  wrote:
> > >>
> > >> On 7/27/21 4:54 AM, Zong Li wrote:
> > >>> Invokes the generic cache_enable interface to execute the relative
> > >>> implementation in SiFive ccache driver.
> > >>>
> > >>> Signed-off-by: Zong Li 
> > >>> ---
> > >>>arch/riscv/cpu/fu540/Kconfig  |  1 +
> > >>>arch/riscv/cpu/fu540/cache.c  | 62 
> > >>> ---
> > >>>arch/riscv/cpu/fu740/Kconfig  |  1 +
> > >>>arch/riscv/cpu/fu740/cache.c  | 60 +++---
> > >>>arch/riscv/include/asm/arch-fu540/cache.h |  2 +-
> > >>>arch/riscv/include/asm/arch-fu740/cache.h |  2 +-
> > >>>board/sifive/unleashed/unleashed.c| 10 +---
> > >>>board/sifive/unmatched/unmatched.c|  9 +---
> > >>>8 files changed, 45 insertions(+), 102 deletions(-)
> > >>>
> > >>> diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
> > >>> index 05463b2625..1f50b823ed 100644
> > >>> --- a/arch/riscv/cpu/fu540/Kconfig
> > >>> +++ b/arch/riscv/cpu/fu540/Kconfig
> > >>> @@ -19,6 +19,7 @@ config SIFIVE_FU540
> > >>>imply SMP
> > >>>imply CLK_SIFIVE
> > >>>imply CLK_SIFIVE_PRCI
> > >>> + imply SIFIVE_CACHE_CCACHE
> > >>>imply SIFIVE_SERIAL
> > >>>imply MACB
> > >>>imply MII
> > >>> diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c
> > >>> index 0fc4ef6c00..3c754c4614 100644
> > >>> --- a/arch/riscv/cpu/fu540/cache.c
> > >>> +++ b/arch/riscv/cpu/fu540/cache.c
> > >>> @@ -1,55 +1,33 @@
> > >>>// SPDX-License-Identifier: GPL-2.0+
> > >>>/*
> > >>> - * Copyright (C) 2020 SiFive, Inc
> > >>> + * Copyright (C) 2020 - 2021 SiFive, Inc
> > >>> *
> > >>> * Authors:
> > >>> *   Pragnesh Patel 
> > >>> */
> > >>>
> > >>>#include 
> > >>> -#include 
> > >>> -#include 
> > >>> -#include 
> > >>> +#include 
> > >>> +#include 
> > >>>
> > >>> -/* Register offsets */
> > >>> -#define L2_CACHE_CONFIG  0x000
> > >>> -#define L2_CACHE_ENABLE  0x008
> > >>> -
> > >>> -#define MASK_NUM_WAYSGENMASK(15, 8)
> > >>> -#define NUM_WAYS_SHIFT   8
> > >>> -
> > >>> -DECLARE_GLOBAL_DATA_PTR;
> > >>> -
> > >>> -int cache_enable_ways(void)
> > >>> +int sifive_ccache_enable_ways(void)
> > >>>{
> > >>
> > >> Is there any reason this function is duplicated? See below for further 
> > >> comments.
> > >
> > > Sorry, I don't completely understand about duplication here. Do you
> > > mean why we need this function? or why is it present in both unleashed
> > > and unmatched?
> >
> > Why it is present in both. Shouldn't it be present in some shared file?
> >
>
> I considered that before, the places to put this ccache function might
> be either 'arch/riscv/lib/' or 'arch/riscv/cpu/generic', these two
> folders put some common stuff for all riscv platforms, but this ccache
> function is actually used in sifive platform only, I'm not sure if it
> is suitable to put the function into them, so I just followed the
> original tree. OTOH, the compiler will drop the unused code, so it
> might be OK to put it into the folders above, and not influence other
> platforms. Do you have any preference or any recommendation?
>

I'm going to add a cache_init() or a weak enable_caches() which is
declared in cpu_func.h into 'arch/riscv/lib/cache.c' for the next
version.

> > >
> > >>
> > >>> - const void *blob = gd->fdt_blob;
> > >>> - int node;
> > >>> - fdt_addr_t base;
> > >>> - u32 config;
> > >>> - u32 ways;
> > >>> -
> > >>> - volatile u32 *enab

Re: [PATCH 2/2] board: sifive: use ccache driver instead of helper function

2021-07-29 Thread Zong Li

On Wed, Jul 28, 2021 at 11:18 PM Sean Anderson  wrote:
>
> On 7/28/21 3:25 AM, Zong Li wrote:
> > On Wed, Jul 28, 2021 at 12:29 PM Sean Anderson  wrote:
> >>
> >> On 7/27/21 4:54 AM, Zong Li wrote:
> >>> Invokes the generic cache_enable interface to execute the relative
> >>> implementation in SiFive ccache driver.
> >>>
> >>> Signed-off-by: Zong Li 
> >>> ---
> >>>arch/riscv/cpu/fu540/Kconfig  |  1 +
> >>>arch/riscv/cpu/fu540/cache.c  | 62 ---
> >>>arch/riscv/cpu/fu740/Kconfig  |  1 +
> >>>arch/riscv/cpu/fu740/cache.c  | 60 +++---
> >>>arch/riscv/include/asm/arch-fu540/cache.h |  2 +-
> >>>arch/riscv/include/asm/arch-fu740/cache.h |  2 +-
> >>>board/sifive/unleashed/unleashed.c| 10 +---
> >>>board/sifive/unmatched/unmatched.c|  9 +---
> >>>8 files changed, 45 insertions(+), 102 deletions(-)
> >>>
> >>> diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
> >>> index 05463b2625..1f50b823ed 100644
> >>> --- a/arch/riscv/cpu/fu540/Kconfig
> >>> +++ b/arch/riscv/cpu/fu540/Kconfig
> >>> @@ -19,6 +19,7 @@ config SIFIVE_FU540
> >>>imply SMP
> >>>imply CLK_SIFIVE
> >>>imply CLK_SIFIVE_PRCI
> >>> + imply SIFIVE_CACHE_CCACHE
> >>>imply SIFIVE_SERIAL
> >>>imply MACB
> >>>imply MII
> >>> diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c
> >>> index 0fc4ef6c00..3c754c4614 100644
> >>> --- a/arch/riscv/cpu/fu540/cache.c
> >>> +++ b/arch/riscv/cpu/fu540/cache.c
> >>> @@ -1,55 +1,33 @@
> >>>// SPDX-License-Identifier: GPL-2.0+
> >>>/*
> >>> - * Copyright (C) 2020 SiFive, Inc
> >>> + * Copyright (C) 2020 - 2021 SiFive, Inc
> >>> *
> >>> * Authors:
> >>> *   Pragnesh Patel 
> >>> */
> >>>
> >>>#include 
> >>> -#include 
> >>> -#include 
> >>> -#include 
> >>> +#include 
> >>> +#include 
> >>>
> >>> -/* Register offsets */
> >>> -#define L2_CACHE_CONFIG  0x000
> >>> -#define L2_CACHE_ENABLE  0x008
> >>> -
> >>> -#define MASK_NUM_WAYSGENMASK(15, 8)
> >>> -#define NUM_WAYS_SHIFT   8
> >>> -
> >>> -DECLARE_GLOBAL_DATA_PTR;
> >>> -
> >>> -int cache_enable_ways(void)
> >>> +int sifive_ccache_enable_ways(void)
> >>>{
> >>
> >> Is there any reason this function is duplicated? See below for further 
> >> comments.
> >
> > Sorry, I don't completely understand about duplication here. Do you
> > mean why we need this function? or why is it present in both unleashed
> > and unmatched?
>
> Why it is present in both. Shouldn't it be present in some shared file?
>

I considered that before, the places to put this ccache function might
be either 'arch/riscv/lib/' or 'arch/riscv/cpu/generic', these two
folders put some common stuff for all riscv platforms, but this ccache
function is actually used in sifive platform only, I'm not sure if it
is suitable to put the function into them, so I just followed the
original tree. OTOH, the compiler will drop the unused code, so it
might be OK to put it into the folders above, and not influence other
platforms. Do you have any preference or any recommendation?

> >
> >>
> >>> - const void *blob = gd->fdt_blob;
> >>> - int node;
> >>> - fdt_addr_t base;
> >>> - u32 config;
> >>> - u32 ways;
> >>> -
> >>> - volatile u32 *enable;
> >>> -
> >>> - node = fdt_node_offset_by_compatible(blob, -1,
> >>> -  "sifive,fu540-c000-ccache");
> >>> -
> >>> - if (node < 0)
> >>> - return node;
> >>> -
> >>> - base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
> >>> - NULL, false);
> >>> - if (base == FDT_ADDR_T_NONE)
> >>> - return FDT_ADDR_T_NONE;
> >>> -
> >>> - config = readl((volatile u32 *)base + L

Re: [PATCH 1/2] cache: add sifive composable cache driver

2021-07-28 Thread Zong Li

On Wed, Jul 28, 2021 at 12:23 PM Sean Anderson  wrote:
>
> On 7/27/21 4:54 AM, Zong Li wrote:
> > This driver is currently responsible for enabling all ccache ways.
>
> Can you expand on this a little? Perhaps describe the hardware a little. For 
> example,
> you could describe what a way/bank is, and that they can't be disabled by the 
> hardware.

Certainly, let me give more details there.

>
> >
> > Signed-off-by: Zong Li 
> > ---
> >   drivers/cache/Kconfig   |  7 +++
> >   drivers/cache/Makefile  |  1 +
> >   drivers/cache/cache-sifive-ccache.c | 69 +
> >   3 files changed, 77 insertions(+)
> >   create mode 100644 drivers/cache/cache-sifive-ccache.c
> >
> > diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
> > index 1e452ad6d9..b903e3e935 100644
> > --- a/drivers/cache/Kconfig
> > +++ b/drivers/cache/Kconfig
> > @@ -39,4 +39,11 @@ config NCORE_CACHE
> > controller. The driver initializes cache directories and coherent
> > agent interfaces.
> >
> > +config SIFIVE_CACHE_CCACHE
>
> Just SIFIVE_CCACHE (or SIFIVE_CACHE) please.

The idea is that the configuration name needs to be able to
distinguish multiple cache devices. For example, if there are other
two devices related to cache, we could give the following three
configurations:
 - SIFIVE_CACHE_CCACHE
 - SIFIVE_CACHE_XXX
 - SIFIVE_CACHE_YYY

SIFIVE_CCACHE is also ok to me, then we would get the following
configuration names in the future.
 - SIFIVE_CCACHE
 - SIFIVE_XXX
 - SIFIVE_YYY

>
> > + bool "SiFive composable cache"
> > + select CACHE
> > + help
> > +   This driver is for SiFive Composable L2/L3 cache. It enables cache
> > +   ways of composable cache.
> > +
> >   endmenu
> > diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
> > index fed50be3f9..92c6c5a83f 100644
> > --- a/drivers/cache/Makefile
> > +++ b/drivers/cache/Makefile
> > @@ -4,3 +4,4 @@ obj-$(CONFIG_SANDBOX) += sandbox_cache.o
> >   obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
> >   obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
> >   obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
> > +obj-$(CONFIG_SIFIVE_CACHE_CCACHE) += cache-sifive-ccache.o
> > diff --git a/drivers/cache/cache-sifive-ccache.c 
> > b/drivers/cache/cache-sifive-ccache.c
> > new file mode 100644
> > index 00..9ea064912f
> > --- /dev/null
> > +++ b/drivers/cache/cache-sifive-ccache.c
> > @@ -0,0 +1,69 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2021 SiFive
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#define SIFIVE_CCACHE_CONFIG 0x000
> > +#define SIFIVE_CCACHE_ENABLE 0x008
>
> WAY_ENABLE?

Changes in the next version.

>
> > +
> > +#define SIFIVE_CCACHE_NUM_WAY_MASK   GENMASK(15, 8)
> > +#define SIFIVE_CCACHE_NUM_WAY_SHIFT  8
> > +
> > +struct sifive_ccache {
> > + void __iomem *base;
> > +};
> > +
> > +static int sifive_ccache_enable_all_ways(struct udevice *dev)
> > +{
> > + struct sifive_ccache *priv = dev_get_priv(dev);
> > + u32 config;
> > + u32 ways;
> > +
> > + config = readl(priv->base + SIFIVE_CCACHE_CONFIG);
> > + ways = (config & SIFIVE_CCACHE_NUM_WAY_MASK) >> 
> > SIFIVE_CCACHE_NUM_WAY_SHIFT;
>
> ways = FIELD_GET(SIFIVE_CCACHE_NUM_WAY_MASK, config);
>
> and perhaps this should be named SIFIVE_CCACHE_CONFIG_WAYS to better match 
> the datasheet?
>

Yes, change it in the next version.

> > +
> > + writel(ways - 1, priv->base + SIFIVE_CCACHE_ENABLE);
> > +
> > + return 0;
> > +}
> > +
> > +static int sifive_ccache_enable(struct udevice *dev)
> > +{
> > + return sifive_ccache_enable_all_ways(dev);
>
> Any reason to have this in a separate function?
>

sifive_ccache_enable isn't clear enough to me, we couldn't be
straightforward to know what to enable.

> > +}
> > +
> > +static const struct cache_ops sifive_ccache_ops = {
> > + .enable = sifive_ccache_enable,
>
> Please implement get_info as well. It should effectively just be
>

Add get_info in the next version. Thanks.

> get_info()
> {
> struct sifive_ccache *priv = dev_get_priv(dev);
>
> info->base = priv->base;
> return 0;
> }
>
> > +};
> > +
> > +static int sifive_ccache_probe(struct udevice *dev)
> > +{
> > + struct sifive_cc

Re: [PATCH 2/2] board: sifive: use ccache driver instead of helper function

2021-07-28 Thread Zong Li

On Wed, Jul 28, 2021 at 12:29 PM Sean Anderson  wrote:
>
> On 7/27/21 4:54 AM, Zong Li wrote:
> > Invokes the generic cache_enable interface to execute the relative
> > implementation in SiFive ccache driver.
> >
> > Signed-off-by: Zong Li 
> > ---
> >   arch/riscv/cpu/fu540/Kconfig  |  1 +
> >   arch/riscv/cpu/fu540/cache.c  | 62 ---
> >   arch/riscv/cpu/fu740/Kconfig  |  1 +
> >   arch/riscv/cpu/fu740/cache.c  | 60 +++---
> >   arch/riscv/include/asm/arch-fu540/cache.h |  2 +-
> >   arch/riscv/include/asm/arch-fu740/cache.h |  2 +-
> >   board/sifive/unleashed/unleashed.c| 10 +---
> >   board/sifive/unmatched/unmatched.c|  9 +---
> >   8 files changed, 45 insertions(+), 102 deletions(-)
> >
> > diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
> > index 05463b2625..1f50b823ed 100644
> > --- a/arch/riscv/cpu/fu540/Kconfig
> > +++ b/arch/riscv/cpu/fu540/Kconfig
> > @@ -19,6 +19,7 @@ config SIFIVE_FU540
> >   imply SMP
> >   imply CLK_SIFIVE
> >   imply CLK_SIFIVE_PRCI
> > + imply SIFIVE_CACHE_CCACHE
> >   imply SIFIVE_SERIAL
> >   imply MACB
> >   imply MII
> > diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c
> > index 0fc4ef6c00..3c754c4614 100644
> > --- a/arch/riscv/cpu/fu540/cache.c
> > +++ b/arch/riscv/cpu/fu540/cache.c
> > @@ -1,55 +1,33 @@
> >   // SPDX-License-Identifier: GPL-2.0+
> >   /*
> > - * Copyright (C) 2020 SiFive, Inc
> > + * Copyright (C) 2020 - 2021 SiFive, Inc
> >*
> >* Authors:
> >*   Pragnesh Patel 
> >*/
> >
> >   #include 
> > -#include 
> > -#include 
> > -#include 
> > +#include 
> > +#include 
> >
> > -/* Register offsets */
> > -#define L2_CACHE_CONFIG  0x000
> > -#define L2_CACHE_ENABLE  0x008
> > -
> > -#define MASK_NUM_WAYSGENMASK(15, 8)
> > -#define NUM_WAYS_SHIFT   8
> > -
> > -DECLARE_GLOBAL_DATA_PTR;
> > -
> > -int cache_enable_ways(void)
> > +int sifive_ccache_enable_ways(void)
> >   {
>
> Is there any reason this function is duplicated? See below for further 
> comments.

Sorry, I don't completely understand about duplication here. Do you
mean why we need this function? or why is it present in both unleashed
and unmatched?

>
> > - const void *blob = gd->fdt_blob;
> > - int node;
> > - fdt_addr_t base;
> > - u32 config;
> > - u32 ways;
> > -
> > - volatile u32 *enable;
> > -
> > - node = fdt_node_offset_by_compatible(blob, -1,
> > -  "sifive,fu540-c000-ccache");
> > -
> > - if (node < 0)
> > - return node;
> > -
> > - base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
> > - NULL, false);
> > - if (base == FDT_ADDR_T_NONE)
> > - return FDT_ADDR_T_NONE;
> > -
> > - config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
> > - ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
> > -
> > - enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
> > + struct udevice *dev;
> > + int ret;
> > +
> > + ret = uclass_get_device_by_driver(UCLASS_CACHE,
> > +   DM_DRIVER_GET(sifive_ccache),
> > +   );
> > + if (ret) {
> > + pr_debug("%s: could not enable cache ways\n", __func__);
> > + return ret;
> > + }
> > +
> > + ret = cache_enable(dev);
> > + if (ret) {
> > + pr_debug("%s: ccache enable filed\n", __func__);
> > + return ret;
> > + }
> >
> > - /* memory barrier */
> > - mb();
> > - (*enable) = ways - 1;
> > - /* memory barrier */
> > - mb();
> >   return 0;
> >   }
> > diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
> > index 8e54310b9c..87d8016c88 100644
> > --- a/arch/riscv/cpu/fu740/Kconfig
> > +++ b/arch/riscv/cpu/fu740/Kconfig
> > @@ -19,6 +19,7 @@ config SIFIVE_FU740
> >   imply SMP
> >   imply CLK_SIFIVE
> >   imply CLK_SIFIVE_PRCI
> > + imply SIFIVE_CACHE_CCACHE
> >   imply SIFIVE_SERIAL
> >   imply MA

[PATCH 2/2] board: sifive: overwrite board_fdt_blob_setup in u-boot proper

2021-07-27 Thread Zong Li

Add board_fdt_blob_setup to return the device tree location which is
passed by prior stage in u-boot proper. The generic board_fdt_blob_setup
always returns _end, it mignt be ok because u-boot SPL would currently
put the dtb there, but it would be broken if we put the dtb to another
place and assigned the location into a1 register for u-boot proper. Use
the location passed by prior stage would make more sence, because we
actually pass the location to u-boot proper and want to use that one,
rather than the dtb which in _end.

We can't use CONFIG_OF_PRIOR_STAGE because it doens't distinguish the
implementation of u-boot SPL and u-boot proper, so u-boot SPL need to
reply on the prior stage to pass device tree location as well, but we
don't pass the DT from boot rom now. In addition, when
CONFIG_OF_PRIOR_STAGE is enabled, the u-boot-spl.bin and u-boot.itb won't
include the device tree.

Signed-off-by: Zong Li 
---
 board/sifive/unleashed/unleashed.c | 11 +++
 board/sifive/unmatched/unmatched.c | 11 +++
 2 files changed, 22 insertions(+)

diff --git a/board/sifive/unleashed/unleashed.c 
b/board/sifive/unleashed/unleashed.c
index a4e78220cb..fa65fcade0 100644
--- a/board/sifive/unleashed/unleashed.c
+++ b/board/sifive/unleashed/unleashed.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /*
  * This define is a value used for error/unknown serial.
@@ -113,6 +114,16 @@ int misc_init_r(void)
 
 #endif
 
+void *board_fdt_blob_setup(void)
+{
+   if (IS_ENABLED(CONFIG_OF_SEPARATE)) {
+   if (gd->arch.firmware_fdt_addr)
+   return (ulong *)gd->arch.firmware_fdt_addr;
+   else
+   return (ulong *)&_end;
+   }
+}
+
 int board_init(void)
 {
int ret;
diff --git a/board/sifive/unmatched/unmatched.c 
b/board/sifive/unmatched/unmatched.c
index 6d60559588..da23a6ce24 100644
--- a/board/sifive/unmatched/unmatched.c
+++ b/board/sifive/unmatched/unmatched.c
@@ -9,6 +9,17 @@
 #include 
 #include 
 #include 
+#include 
+
+void *board_fdt_blob_setup(void)
+{
+   if (IS_ENABLED(CONFIG_OF_SEPARATE)) {
+   if (gd->arch.firmware_fdt_addr)
+   return (ulong *)gd->arch.firmware_fdt_addr;
+   else
+   return (ulong *)&_end;
+   }
+}
 
 int board_init(void)
 {
-- 
2.32.0

[PATCH 1/2] board: sifive: compile stuff only related to SPL in SPL build

2021-07-27 Thread Zong Li

As (3581811dc26f "riscv: sifive/fu540: Move SPL related functions to spl.c"),
we put the SPL stuff in spl.c, we don't need to compile unleashed.c and
unmatched.c in SPL build.

Signed-off-by: Zong Li 
---
 board/sifive/unleashed/Makefile | 4 ++--
 board/sifive/unmatched/Makefile | 3 ++-
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/board/sifive/unleashed/Makefile b/board/sifive/unleashed/Makefile
index 5821679dd9..98e9111cbc 100644
--- a/board/sifive/unleashed/Makefile
+++ b/board/sifive/unleashed/Makefile
@@ -2,8 +2,8 @@
 #
 # Copyright (c) 2019 Western Digital Corporation or its affiliates.
 
-obj-y  += unleashed.o
-
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
+else
+obj-y += unleashed.o
 endif
diff --git a/board/sifive/unmatched/Makefile b/board/sifive/unmatched/Makefile
index e00b330e8c..1345330089 100644
--- a/board/sifive/unmatched/Makefile
+++ b/board/sifive/unmatched/Makefile
@@ -2,9 +2,10 @@
 #
 # Copyright (c) 2020-2021 SiFive, Inc
 
-obj-y   += unmatched.o
 obj-$(CONFIG_ID_EEPROM) += hifive-platform-i2c-eeprom.o
 
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
+else
+obj-y += unmatched.o
 endif
-- 
2.32.0

[PATCH 2/2] board: sifive: use ccache driver instead of helper function

2021-07-27 Thread Zong Li

Invokes the generic cache_enable interface to execute the relative
implementation in SiFive ccache driver.

Signed-off-by: Zong Li 
---
 arch/riscv/cpu/fu540/Kconfig  |  1 +
 arch/riscv/cpu/fu540/cache.c  | 62 ---
 arch/riscv/cpu/fu740/Kconfig  |  1 +
 arch/riscv/cpu/fu740/cache.c  | 60 +++---
 arch/riscv/include/asm/arch-fu540/cache.h |  2 +-
 arch/riscv/include/asm/arch-fu740/cache.h |  2 +-
 board/sifive/unleashed/unleashed.c| 10 +---
 board/sifive/unmatched/unmatched.c|  9 +---
 8 files changed, 45 insertions(+), 102 deletions(-)

diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
index 05463b2625..1f50b823ed 100644
--- a/arch/riscv/cpu/fu540/Kconfig
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -19,6 +19,7 @@ config SIFIVE_FU540
imply SMP
imply CLK_SIFIVE
imply CLK_SIFIVE_PRCI
+   imply SIFIVE_CACHE_CCACHE
imply SIFIVE_SERIAL
imply MACB
imply MII
diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c
index 0fc4ef6c00..3c754c4614 100644
--- a/arch/riscv/cpu/fu540/cache.c
+++ b/arch/riscv/cpu/fu540/cache.c
@@ -1,55 +1,33 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2020 SiFive, Inc
+ * Copyright (C) 2020 - 2021 SiFive, Inc
  *
  * Authors:
  *   Pragnesh Patel 
  */
 
 #include 
-#include 
-#include 
-#include 
+#include 
+#include 
 
-/* Register offsets */
-#define L2_CACHE_CONFIG0x000
-#define L2_CACHE_ENABLE0x008
-
-#define MASK_NUM_WAYS  GENMASK(15, 8)
-#define NUM_WAYS_SHIFT 8
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int cache_enable_ways(void)
+int sifive_ccache_enable_ways(void)
 {
-   const void *blob = gd->fdt_blob;
-   int node;
-   fdt_addr_t base;
-   u32 config;
-   u32 ways;
-
-   volatile u32 *enable;
-
-   node = fdt_node_offset_by_compatible(blob, -1,
-"sifive,fu540-c000-ccache");
-
-   if (node < 0)
-   return node;
-
-   base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
-   NULL, false);
-   if (base == FDT_ADDR_T_NONE)
-   return FDT_ADDR_T_NONE;
-
-   config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
-   ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
-
-   enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
+   struct udevice *dev;
+   int ret;
+
+   ret = uclass_get_device_by_driver(UCLASS_CACHE,
+ DM_DRIVER_GET(sifive_ccache),
+ );
+   if (ret) {
+   pr_debug("%s: could not enable cache ways\n", __func__);
+   return ret;
+   }
+
+   ret = cache_enable(dev);
+   if (ret) {
+   pr_debug("%s: ccache enable filed\n", __func__);
+   return ret;
+   }
 
-   /* memory barrier */
-   mb();
-   (*enable) = ways - 1;
-   /* memory barrier */
-   mb();
return 0;
 }
diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
index 8e54310b9c..87d8016c88 100644
--- a/arch/riscv/cpu/fu740/Kconfig
+++ b/arch/riscv/cpu/fu740/Kconfig
@@ -19,6 +19,7 @@ config SIFIVE_FU740
imply SMP
imply CLK_SIFIVE
imply CLK_SIFIVE_PRCI
+   imply SIFIVE_CACHE_CCACHE
imply SIFIVE_SERIAL
imply MACB
imply MII
diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c
index 680955c9e3..1d6c295d98 100644
--- a/arch/riscv/cpu/fu740/cache.c
+++ b/arch/riscv/cpu/fu740/cache.c
@@ -7,49 +7,27 @@
  */
 
 #include 
-#include 
-#include 
-#include 
+#include 
+#include 
 
-/* Register offsets */
-#define L2_CACHE_CONFIG0x000
-#define L2_CACHE_ENABLE0x008
-
-#define MASK_NUM_WAYS  GENMASK(15, 8)
-#define NUM_WAYS_SHIFT 8
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int cache_enable_ways(void)
+int sifive_ccache_enable_ways(void)
 {
-   const void *blob = gd->fdt_blob;
-   int node;
-   fdt_addr_t base;
-   u32 config;
-   u32 ways;
-
-   volatile u32 *enable;
-
-   node = fdt_node_offset_by_compatible(blob, -1,
-"sifive,fu740-c000-ccache");
-
-   if (node < 0)
-   return node;
-
-   base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
-   NULL, false);
-   if (base == FDT_ADDR_T_NONE)
-   return FDT_ADDR_T_NONE;
-
-   config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
-   ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
-
-   enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
+   struct udevice *dev;
+   int ret;
+
+   ret = uclass_get_device_b

[PATCH 1/2] cache: add sifive composable cache driver

2021-07-27 Thread Zong Li

This driver is currently responsible for enabling all ccache ways.

Signed-off-by: Zong Li 
---
 drivers/cache/Kconfig   |  7 +++
 drivers/cache/Makefile  |  1 +
 drivers/cache/cache-sifive-ccache.c | 69 +
 3 files changed, 77 insertions(+)
 create mode 100644 drivers/cache/cache-sifive-ccache.c

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 1e452ad6d9..b903e3e935 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -39,4 +39,11 @@ config NCORE_CACHE
  controller. The driver initializes cache directories and coherent
  agent interfaces.
 
+config SIFIVE_CACHE_CCACHE
+   bool "SiFive composable cache"
+   select CACHE
+   help
+ This driver is for SiFive Composable L2/L3 cache. It enables cache
+ ways of composable cache.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index fed50be3f9..92c6c5a83f 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_SANDBOX) += sandbox_cache.o
 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
 obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
 obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
+obj-$(CONFIG_SIFIVE_CACHE_CCACHE) += cache-sifive-ccache.o
diff --git a/drivers/cache/cache-sifive-ccache.c 
b/drivers/cache/cache-sifive-ccache.c
new file mode 100644
index 00..9ea064912f
--- /dev/null
+++ b/drivers/cache/cache-sifive-ccache.c
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 SiFive
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SIFIVE_CCACHE_CONFIG   0x000
+#define SIFIVE_CCACHE_ENABLE   0x008
+
+#define SIFIVE_CCACHE_NUM_WAY_MASK GENMASK(15, 8)
+#define SIFIVE_CCACHE_NUM_WAY_SHIFT8
+
+struct sifive_ccache {
+   void __iomem *base;
+};
+
+static int sifive_ccache_enable_all_ways(struct udevice *dev)
+{
+   struct sifive_ccache *priv = dev_get_priv(dev);
+   u32 config;
+   u32 ways;
+
+   config = readl(priv->base + SIFIVE_CCACHE_CONFIG);
+   ways = (config & SIFIVE_CCACHE_NUM_WAY_MASK) >> 
SIFIVE_CCACHE_NUM_WAY_SHIFT;
+
+   writel(ways - 1, priv->base + SIFIVE_CCACHE_ENABLE);
+
+   return 0;
+}
+
+static int sifive_ccache_enable(struct udevice *dev)
+{
+   return sifive_ccache_enable_all_ways(dev);
+}
+
+static const struct cache_ops sifive_ccache_ops = {
+   .enable = sifive_ccache_enable,
+};
+
+static int sifive_ccache_probe(struct udevice *dev)
+{
+   struct sifive_ccache *priv = dev_get_priv(dev);
+
+   priv->base = dev_read_addr_ptr(dev);
+   if (!priv->base)
+   return -ENODEV;
+
+   return 0;
+}
+
+static const struct udevice_id sifive_ccache_ids[] = {
+   { .compatible = "sifive,fu540-c000-ccache" },
+   { .compatible = "sifive,fu740-c000-ccache" },
+   {}
+};
+
+U_BOOT_DRIVER(sifive_ccache) = {
+   .name = "sifive_ccache",
+   .id = UCLASS_CACHE,
+   .of_match = sifive_ccache_ids,
+   .probe = sifive_ccache_probe,
+   .priv_auto = sizeof(struct sifive_ccache),
+   .ops = _ccache_ops,
+};
-- 
2.31.1

Re: [PATCH] board: sifive: drop stuff related to unmatched revision 1

2021-07-20 Thread Zong Li

On Wed, Jul 14, 2021 at 2:56 PM Leo Liang  wrote:
>
> Hi Zong,
>
> On Fri, Jul 09, 2021 at 04:06:01PM +0800, Zong Li wrote:
> > This patch reverts the following commits:
> >  - 4b4159d0f3 ("riscv: dts: add dts for unmatched rev1")
> >  - ffe9a394df ("board: sifive: support spl multi-dtb on unmatched board")
> >
> > We won't plan to support unmatched that the revision below 3 in u-boot,
> > so they can be dropped because they might be useless.
> >
> > Signed-off-by: Zong Li 
> > Suggested-by: David Abdurachmanov 
> > ---
> >  arch/riscv/dts/Makefile   |2 +-
> >  .../fu740-hifive-unmatched-a00-ddr-rev1.dtsi  | 1489 -
> >  .../dts/hifive-unmatched-a00-rev1-u-boot.dtsi |7 -
> >  arch/riscv/dts/hifive-unmatched-a00-rev1.dts  |4 -
> >  board/sifive/unmatched/spl.c  |   28 +-
> >  configs/sifive_unmatched_defconfig|4 -
>
> I found that the order of the CONFIGs in "sifive_unmatched_defconfig"
> has been rearranged by this commit "fd075f77ca configs: Resync with 
> savedefconfig",
> so this patch does not apply anymore.
>
> Could you please rebase on u-boot/master and then send the patch again? 
> Thanks!
>

Hi Leo,
Sorry for being late here, I have sent the second version of this
patch to the mailing list, please feel free to let me know if there is
still any problem. Thanks for your review.

> Best regards,
> Leo
>
> >  6 files changed, 3 insertions(+), 1531 deletions(-)
> >  delete mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
> >  delete mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1-u-boot.dtsi
> >  delete mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1.dts

[PATCH v2] board: sifive: drop stuff related to unmatched revision 1

2021-07-20 Thread Zong Li

This patch reverts the following commits:
 - 4b4159d0f3 ("riscv: dts: add dts for unmatched rev1")
 - ffe9a394df ("board: sifive: support spl multi-dtb on unmatched board")

We won't plan to support unmatched that the revision below 3 in u-boot,
so they can be dropped because they might be useless.

Changed in v2:
 - rebase codebase to the latest master branch

Signed-off-by: Zong Li 
Suggested-by: David Abdurachmanov 
Reviewed-by: Leo Yu-Chi Liang 
---
 arch/riscv/dts/Makefile   |2 +-
 .../fu740-hifive-unmatched-a00-ddr-rev1.dtsi  | 1489 -
 .../dts/hifive-unmatched-a00-rev1-u-boot.dtsi |7 -
 arch/riscv/dts/hifive-unmatched-a00-rev1.dts  |4 -
 board/sifive/unmatched/spl.c  |   28 +-
 configs/sifive_unmatched_defconfig|4 -
 6 files changed, 3 insertions(+), 1531 deletions(-)
 delete mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
 delete mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1-u-boot.dtsi
 delete mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1.dts

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index ba69894eb5..b6e9166767 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -5,7 +5,7 @@ dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += 
microchip-mpfs-icicle-kit.dtb
 dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb
 dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
-dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb 
hifive-unmatched-a00-rev1.dtb
+dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
 
 targets += $(dtb-y)
diff --git a/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi 
b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
deleted file mode 100644
index 0c4dedd166..00
--- a/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
+++ /dev/null
@@ -1,1489 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * (C) Copyright 2020 SiFive, Inc
- */
-
- {
-   sifive,ddr-params = <
-   0x0a00  /* DENALI_CTL_00_DATA */
-   0x  /* DENALI_CTL_01_DATA */
-   0x  /* DENALI_CTL_02_DATA */
-   0x  /* DENALI_CTL_03_DATA */
-   0x  /* DENALI_CTL_04_DATA */
-   0x  /* DENALI_CTL_05_DATA */
-   0x000b  /* DENALI_CTL_06_DATA */
-   0x00033f1e  /* DENALI_CTL_07_DATA */
-   0x00081dcb  /* DENALI_CTL_08_DATA */
-   0x0b200300  /* DENALI_CTL_09_DATA */
-   0x1c1c0400  /* DENALI_CTL_10_DATA */
-   0x04049a0d  /* DENALI_CTL_11_DATA */
-   0x32060406  /* DENALI_CTL_12_DATA */
-   0x100d0823  /* DENALI_CTL_13_DATA */
-   0x080a0a17  /* DENALI_CTL_14_DATA */
-   0x0123b818  /* DENALI_CTL_15_DATA */
-   0x00180b06  /* DENALI_CTL_16_DATA */
-   0x00a01510  /* DENALI_CTL_17_DATA */
-   0x01000118  /* DENALI_CTL_18_DATA */
-   0x10032501  /* DENALI_CTL_19_DATA */
-   0x  /* DENALI_CTL_20_DATA */
-   0x0101  /* DENALI_CTL_21_DATA */
-   0x  /* DENALI_CTL_22_DATA */
-   0x0a00  /* DENALI_CTL_23_DATA */
-   0x  /* DENALI_CTL_24_DATA */
-   0x01750100  /* DENALI_CTL_25_DATA */
-   0x2069  /* DENALI_CTL_26_DATA */
-   0x0005  /* DENALI_CTL_27_DATA */
-   0x001a0007  /* DENALI_CTL_28_DATA */
-   0x017f0300  /* DENALI_CTL_29_DATA */
-   0x0301  /* DENALI_CTL_30_DATA */
-   0x000b0f00  /* DENALI_CTL_31_DATA */
-   0x04030200  /* DENALI_CTL_32_DATA */
-   0x031f  /* DENALI_CTL_33_DATA */
-   0x00070004  /* DENALI_CTL_34_DATA */
-   0x  /* DENALI_CTL_35_DATA */
-   0x  /* DENALI_CTL_36_DATA */
-   0x  /* DENALI_CTL_37_DATA */
-   0x  /* DENALI_CTL_38_DATA */
-   0x  /* DENALI_CTL_39_DATA */
-   0x  /* DENALI_CTL_40_DATA */
-   0x  /* DENALI_CTL_41_DATA */
-   0x  /* DENALI_CTL_42_DATA */
-   0x  /* DENALI_CTL_43_DATA */
-   0x  /* DENALI_CTL_44_DATA */
-   0x  /* DENALI_CTL_45_DATA */
-   0x  /* DENALI_CTL_46_DATA */
-   0x  /* DENALI_CTL_47_DATA */
-   0x  /* DENALI_CTL_48_DATA */
-

[PATCH] board: sifive: remove the command for setting serial number

2021-07-09 Thread Zong Li

We wouldn't like to allow user to change the serial number, so remove
the command for changing serial number in EEPROM.

Signed-off-by: Zong Li 
Suggested-by: David Abdurachmanov 
---
 .../unmatched/hifive-platform-i2c-eeprom.c| 23 +--
 1 file changed, 1 insertion(+), 22 deletions(-)

diff --git a/board/sifive/unmatched/hifive-platform-i2c-eeprom.c 
b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
index a2151f15e0..ad2f3155d0 100644
--- a/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
+++ b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
@@ -401,24 +401,6 @@ static void set_product_id(char *string)
update_crc();
 }
 
-/**
- * set_serial_number() - set the PCB serial number in the in-memory copy
- *
- * Set the board serial number in the in-memory EEPROM copy from the supplied
- * string argument, and update the CRC.
- */
-static void set_serial_number(char *string)
-{
-   if (strlen(string) > SERIAL_NUMBER_BYTES) {
-   printf("Serial number must not be greater than 16 bytes\n");
-   return;
-   }
-
-   memset(e.serial, 0, sizeof(e.serial));
-   strncpy((char *)e.serial, string, sizeof(e.serial));
-   update_crc();
-}
-
 /**
  * init_local_copy() - initialize the in-memory EEPROM copy
  *
@@ -468,10 +450,7 @@ int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char 
*const argv[])
return 0;
}
 
-   if (!strcmp(cmd, "serial_number")) {
-   set_serial_number(argv[2]);
-   return 0;
-   } else if (!strcmp(cmd, "manuf_test_status")) {
+   if (!strcmp(cmd, "manuf_test_status")) {
set_manuf_test_status(argv[2]);
return 0;
} else if (!strcmp(cmd, "mac_address")) {
-- 
2.31.1

[PATCH] board: sifive: drop stuff related to unmatched revision 1

2021-07-09 Thread Zong Li

This patch reverts the following commits:
 - 4b4159d0f3 ("riscv: dts: add dts for unmatched rev1")
 - ffe9a394df ("board: sifive: support spl multi-dtb on unmatched board")

We won't plan to support unmatched that the revision below 3 in u-boot,
so they can be dropped because they might be useless.

Signed-off-by: Zong Li 
Suggested-by: David Abdurachmanov 
---
 arch/riscv/dts/Makefile   |2 +-
 .../fu740-hifive-unmatched-a00-ddr-rev1.dtsi  | 1489 -
 .../dts/hifive-unmatched-a00-rev1-u-boot.dtsi |7 -
 arch/riscv/dts/hifive-unmatched-a00-rev1.dts  |4 -
 board/sifive/unmatched/spl.c  |   28 +-
 configs/sifive_unmatched_defconfig|4 -
 6 files changed, 3 insertions(+), 1531 deletions(-)
 delete mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
 delete mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1-u-boot.dtsi
 delete mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1.dts

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index ba69894eb5..b6e9166767 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -5,7 +5,7 @@ dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += 
microchip-mpfs-icicle-kit.dtb
 dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb
 dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
-dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb 
hifive-unmatched-a00-rev1.dtb
+dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
 
 targets += $(dtb-y)
diff --git a/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi 
b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
deleted file mode 100644
index 0c4dedd166..00
--- a/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
+++ /dev/null
@@ -1,1489 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * (C) Copyright 2020 SiFive, Inc
- */
-
- {
-   sifive,ddr-params = <
-   0x0a00  /* DENALI_CTL_00_DATA */
-   0x  /* DENALI_CTL_01_DATA */
-   0x  /* DENALI_CTL_02_DATA */
-   0x  /* DENALI_CTL_03_DATA */
-   0x  /* DENALI_CTL_04_DATA */
-   0x  /* DENALI_CTL_05_DATA */
-   0x000b  /* DENALI_CTL_06_DATA */
-   0x00033f1e  /* DENALI_CTL_07_DATA */
-   0x00081dcb  /* DENALI_CTL_08_DATA */
-   0x0b200300  /* DENALI_CTL_09_DATA */
-   0x1c1c0400  /* DENALI_CTL_10_DATA */
-   0x04049a0d  /* DENALI_CTL_11_DATA */
-   0x32060406  /* DENALI_CTL_12_DATA */
-   0x100d0823  /* DENALI_CTL_13_DATA */
-   0x080a0a17  /* DENALI_CTL_14_DATA */
-   0x0123b818  /* DENALI_CTL_15_DATA */
-   0x00180b06  /* DENALI_CTL_16_DATA */
-   0x00a01510  /* DENALI_CTL_17_DATA */
-   0x01000118  /* DENALI_CTL_18_DATA */
-   0x10032501  /* DENALI_CTL_19_DATA */
-   0x  /* DENALI_CTL_20_DATA */
-   0x0101  /* DENALI_CTL_21_DATA */
-   0x  /* DENALI_CTL_22_DATA */
-   0x0a00  /* DENALI_CTL_23_DATA */
-   0x  /* DENALI_CTL_24_DATA */
-   0x01750100  /* DENALI_CTL_25_DATA */
-   0x2069  /* DENALI_CTL_26_DATA */
-   0x0005  /* DENALI_CTL_27_DATA */
-   0x001a0007  /* DENALI_CTL_28_DATA */
-   0x017f0300  /* DENALI_CTL_29_DATA */
-   0x0301  /* DENALI_CTL_30_DATA */
-   0x000b0f00  /* DENALI_CTL_31_DATA */
-   0x04030200  /* DENALI_CTL_32_DATA */
-   0x031f  /* DENALI_CTL_33_DATA */
-   0x00070004  /* DENALI_CTL_34_DATA */
-   0x  /* DENALI_CTL_35_DATA */
-   0x  /* DENALI_CTL_36_DATA */
-   0x  /* DENALI_CTL_37_DATA */
-   0x  /* DENALI_CTL_38_DATA */
-   0x  /* DENALI_CTL_39_DATA */
-   0x  /* DENALI_CTL_40_DATA */
-   0x  /* DENALI_CTL_41_DATA */
-   0x  /* DENALI_CTL_42_DATA */
-   0x  /* DENALI_CTL_43_DATA */
-   0x  /* DENALI_CTL_44_DATA */
-   0x  /* DENALI_CTL_45_DATA */
-   0x  /* DENALI_CTL_46_DATA */
-   0x  /* DENALI_CTL_47_DATA */
-   0x  /* DENALI_CTL_48_DATA */
-   0x  /* DENALI_CTL_49_DATA */
-   0x  /* DENALI_CTL_50_DATA */
-

[PATCH 5/6] riscv: dts: add dts for unmatched rev1

2021-06-30 Thread Zong Li

The difference between unmatched rev3 and rev1 is DDR timing, the rev3
uses 1866 MT/s for 16GiB, and rev1 uses 2133 MT/s for 8GiB.

Signed-off-by: Zong Li 
---
 arch/riscv/dts/Makefile   |2 +-
 .../fu740-hifive-unmatched-a00-ddr-rev1.dtsi  | 1489 +
 .../dts/hifive-unmatched-a00-rev1-u-boot.dtsi |7 +
 arch/riscv/dts/hifive-unmatched-a00-rev1.dts  |4 +
 4 files changed, 1501 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
 create mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1-u-boot.dtsi
 create mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1.dts

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 7778874831..7faeeaf664 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -4,7 +4,7 @@ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
 dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
 dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
-dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
+dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb 
hifive-unmatched-a00-rev1.dtb
 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
 
 targets += $(dtb-y)
diff --git a/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi 
b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
new file mode 100644
index 00..0c4dedd166
--- /dev/null
+++ b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
@@ -0,0 +1,1489 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2020 SiFive, Inc
+ */
+
+ {
+   sifive,ddr-params = <
+   0x0a00  /* DENALI_CTL_00_DATA */
+   0x  /* DENALI_CTL_01_DATA */
+   0x  /* DENALI_CTL_02_DATA */
+   0x  /* DENALI_CTL_03_DATA */
+   0x  /* DENALI_CTL_04_DATA */
+   0x  /* DENALI_CTL_05_DATA */
+   0x000b  /* DENALI_CTL_06_DATA */
+   0x00033f1e  /* DENALI_CTL_07_DATA */
+   0x00081dcb  /* DENALI_CTL_08_DATA */
+   0x0b200300  /* DENALI_CTL_09_DATA */
+   0x1c1c0400  /* DENALI_CTL_10_DATA */
+   0x04049a0d  /* DENALI_CTL_11_DATA */
+   0x32060406  /* DENALI_CTL_12_DATA */
+   0x100d0823  /* DENALI_CTL_13_DATA */
+   0x080a0a17  /* DENALI_CTL_14_DATA */
+   0x0123b818  /* DENALI_CTL_15_DATA */
+   0x00180b06  /* DENALI_CTL_16_DATA */
+   0x00a01510  /* DENALI_CTL_17_DATA */
+   0x01000118  /* DENALI_CTL_18_DATA */
+   0x10032501  /* DENALI_CTL_19_DATA */
+   0x  /* DENALI_CTL_20_DATA */
+   0x0101  /* DENALI_CTL_21_DATA */
+   0x  /* DENALI_CTL_22_DATA */
+   0x0a00  /* DENALI_CTL_23_DATA */
+   0x  /* DENALI_CTL_24_DATA */
+   0x01750100  /* DENALI_CTL_25_DATA */
+   0x2069  /* DENALI_CTL_26_DATA */
+   0x0005  /* DENALI_CTL_27_DATA */
+   0x001a0007  /* DENALI_CTL_28_DATA */
+   0x017f0300  /* DENALI_CTL_29_DATA */
+   0x0301  /* DENALI_CTL_30_DATA */
+   0x000b0f00  /* DENALI_CTL_31_DATA */
+   0x04030200  /* DENALI_CTL_32_DATA */
+   0x031f  /* DENALI_CTL_33_DATA */
+   0x00070004  /* DENALI_CTL_34_DATA */
+   0x  /* DENALI_CTL_35_DATA */
+   0x  /* DENALI_CTL_36_DATA */
+   0x  /* DENALI_CTL_37_DATA */
+   0x  /* DENALI_CTL_38_DATA */
+   0x  /* DENALI_CTL_39_DATA */
+   0x  /* DENALI_CTL_40_DATA */
+   0x  /* DENALI_CTL_41_DATA */
+   0x  /* DENALI_CTL_42_DATA */
+   0x  /* DENALI_CTL_43_DATA */
+   0x  /* DENALI_CTL_44_DATA */
+   0x  /* DENALI_CTL_45_DATA */
+   0x  /* DENALI_CTL_46_DATA */
+   0x  /* DENALI_CTL_47_DATA */
+   0x  /* DENALI_CTL_48_DATA */
+   0x  /* DENALI_CTL_49_DATA */
+   0x  /* DENALI_CTL_50_DATA */
+   0x  /* DENALI_CTL_51_DATA */
+   0x  /* DENALI_CTL_52_DATA */
+   0x  /* DENALI_CTL_53_DATA */
+   0x  /* DENALI_CTL_54_DATA */
+   0x  /* DENALI_CTL_55_DATA */
+   0x  /* DENALI_CTL_56_D

[PATCH 6/6] board: sifive: support spl multi-dtb on unmatched board

2021-06-30 Thread Zong Li

There are two revisions of unmatched board with different DDR timing,
we'd like to support multi-dtb mechanism in SPL, then it selects the
right DTB at runtime according to PCB revision in I2C EEPROM.

Signed-off-by: Zong Li 
---
 board/sifive/unmatched/spl.c   | 28 ++--
 configs/sifive_unmatched_defconfig |  4 
 2 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
index 5e1333b09a..74134b03ee 100644
--- a/board/sifive/unmatched/spl.c
+++ b/board/sifive/unmatched/spl.c
@@ -10,11 +10,14 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
 #include 
 #include 
+#include 
 
 #define GEM_PHY_RESET  SIFIVE_GENERIC_GPIO_NR(0, 12)
 
@@ -26,6 +29,16 @@ int spl_board_init_f(void)
 {
int ret;
 
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT)
+   int rescan;
+
+   ret = fdtdec_resetup();
+   if (!ret && rescan) {
+   dm_uninit();
+   dm_init_and_scan(true);
+   }
+#endif
+
ret = spl_soc_init();
if (ret) {
debug("HiFive Unmatched FU740 SPL init failed: %d\n", ret);
@@ -79,7 +92,18 @@ u32 spl_boot_device(void)
 #ifdef CONFIG_SPL_LOAD_FIT
 int board_fit_config_name_match(const char *name)
 {
-   /* boot using first FIT config */
-   return 0;
+   /*
+* Apply different DDR params on different board revision.
+* Use PCB revision which is byte 0x7 in I2C platform EEPROM
+* to distinguish that.
+*/
+   if (get_pcb_revision_from_eeprom() == PCB_REVISION_REV3 &&
+   !strcmp(name, "hifive-unmatched-a00"))
+   return 0;
+   else if (get_pcb_revision_from_eeprom() != PCB_REVISION_REV3 &&
+!strcmp(name, "hifive-unmatched-a00-rev1"))
+   return 0;
+
+   return -1;
 }
 #endif
diff --git a/configs/sifive_unmatched_defconfig 
b/configs/sifive_unmatched_defconfig
index 4c26504867..74b59738cd 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
@@ -40,3 +40,7 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_PCI=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_SPL_OF_LIST="hifive-unmatched-a00 hifive-unmatched-a00-rev1"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x10
-- 
2.31.1

[PATCH 4/6] board: sifive: Add an interface to get PCB revision

2021-06-30 Thread Zong Li

There are different DDR parameter settings for different board
revisions. Add a new interface to get the PCB revision to determine
which DT should be selected at runtime.

Signed-off-by: Zong Li 
---
 arch/riscv/include/asm/arch-fu740/eeprom.h| 15 +
 .../unmatched/hifive-platform-i2c-eeprom.c| 32 +++
 2 files changed, 47 insertions(+)
 create mode 100644 arch/riscv/include/asm/arch-fu740/eeprom.h

diff --git a/arch/riscv/include/asm/arch-fu740/eeprom.h 
b/arch/riscv/include/asm/arch-fu740/eeprom.h
new file mode 100644
index 00..0e1220e558
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu740/eeprom.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 SiFive, Inc.
+ *
+ * Zong Li 
+ */
+
+#ifndef _ASM_RISCV_EEPROM_H
+#define _ASM_RISCV_EEPROM_H
+
+#define PCB_REVISION_REV3  0x3
+
+u8 get_pcb_revision_from_eeprom(void);
+
+#endif /* _ASM_RISCV_EEPROM_H */
diff --git a/board/sifive/unmatched/hifive-platform-i2c-eeprom.c 
b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
index 9a62d32453..a2151f15e0 100644
--- a/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
+++ b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
@@ -540,3 +540,35 @@ int mac_read_from_eeprom(void)
 
return 0;
 }
+
+/**
+ * get_pcb_revision_from_eeprom - get the PCB revision
+ *
+ * Read the EEPROM to determine the board revision.
+ *
+ * This function is called before relocation, so we need to read a private
+ * copy of the EEPROM into a local variable on the stack.
+ */
+u8 get_pcb_revision_from_eeprom(void)
+{
+   struct __attribute__ ((__packed__)) board_eeprom {
+   u8 magic[MAGIC_NUMBER_BYTES];
+   u8 format_ver;
+   u16 product_id;
+   u8 pcb_revision;
+   } be;
+
+   int ret;
+   struct udevice *dev;
+
+   ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ 1,
+ );
+
+   if (!ret)
+   dm_i2c_read(dev, 0, (void *),
+   sizeof(struct board_eeprom));
+
+   return be.pcb_revision;
+}
-- 
2.31.1

[PATCH 3/6] riscv: sifive: fu740: Support i2c in spl

2021-06-30 Thread Zong Li

Enable SPL_I2C_SUPPORT for fu740, and add 'u-boot,dm-spl' property in
i2c node.

Signed-off-by: Zong Li 
---
 arch/riscv/cpu/fu740/Kconfig  | 1 +
 arch/riscv/dts/fu740-c000-u-boot.dtsi | 4 
 2 files changed, 5 insertions(+)

diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
index 1dc052ba31..8e54310b9c 100644
--- a/arch/riscv/cpu/fu740/Kconfig
+++ b/arch/riscv/cpu/fu740/Kconfig
@@ -37,3 +37,4 @@ config SIFIVE_FU740
imply PWM_SIFIVE
imply DM_I2C
imply SYS_I2C_OCORES
+   imply SPL_I2C_SUPPORT
diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi 
b/arch/riscv/dts/fu740-c000-u-boot.dtsi
index a5d0688b06..a6f7a0873e 100644
--- a/arch/riscv/dts/fu740-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi
@@ -95,6 +95,10 @@
u-boot,dm-spl;
 };
 
+ {
+   u-boot,dm-spl;
+};
+
  {
assigned-clocks = < PRCI_CLK_GEMGXLPLL>;
assigned-clock-rates = <125125000>;
-- 
2.31.1

[PATCH 1/6] board: sifive: unmatched: add initial support for a platform ID EEPROM

2021-06-30 Thread Zong Li

Add initial support for the PCB description EEPROM for SiFive HiFive
Unmatched boards.

This implementation is refactored based on Paul Walmsley's porting and
adopt the suggestions from David Abdurachmanov.

Signed-off-by: Paul Walmsley 
Signed-off-by: David Abdurachmanov 
Signed-off-by: Zong Li 
---
 board/sifive/unmatched/Makefile   |   1 +
 .../unmatched/hifive-platform-i2c-eeprom.c| 542 ++
 include/configs/sifive-unmatched.h|   6 +
 3 files changed, 549 insertions(+)
 create mode 100644 board/sifive/unmatched/hifive-platform-i2c-eeprom.c

diff --git a/board/sifive/unmatched/Makefile b/board/sifive/unmatched/Makefile
index 6308c80d64..e00b330e8c 100644
--- a/board/sifive/unmatched/Makefile
+++ b/board/sifive/unmatched/Makefile
@@ -3,6 +3,7 @@
 # Copyright (c) 2020-2021 SiFive, Inc
 
 obj-y   += unmatched.o
+obj-$(CONFIG_ID_EEPROM) += hifive-platform-i2c-eeprom.o
 
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
diff --git a/board/sifive/unmatched/hifive-platform-i2c-eeprom.c 
b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
new file mode 100644
index 00..9a62d32453
--- /dev/null
+++ b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
@@ -0,0 +1,542 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 SiFive, Inc.
+ *
+ * Based on board/freescale/common/sys_eeprom.c:
+ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
+ * York Sun (york...@freescale.com)
+ * Haiying Wang (haiying.w...@freescale.com)
+ * Timur Tabi (ti...@freescale.com)
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifndef CONFIG_SYS_EEPROM_BUS_NUM
+#error Requires CONFIG_SYS_EEPROM_BUS_NUM to be defined
+#endif
+
+#define FORMAT_VERSION 0x1
+
+/* Options for the manuf_test_status field */
+#define SIFIVE_MANUF_TEST_STATUS_UNKNOWN   0
+#define SIFIVE_MANUF_TEST_STATUS_PASS  1
+#define SIFIVE_MANUF_TEST_STATUS_FAIL  2
+
+/*
+ * BYTES_PER_EEPROM_PAGE: the AT24C02 datasheet says that data can
+ * only be written in page mode, which means 8 bytes at a time
+ */
+#define BYTES_PER_EEPROM_PAGE  8
+
+/*
+ * EEPROM_WRITE_DELAY_MS: the AT24C02 datasheet says it takes up to
+ * 5ms to complete a given write
+ */
+#define EEPROM_WRITE_DELAY_MS  5000
+
+/*
+ * MAGIC_NUMBER_BYTES: number of bytes used by the magic number
+ */
+#define MAGIC_NUMBER_BYTES 4
+
+/*
+ * SERIAL_NUMBER_BYTES: number of bytes used by the board serial
+ * number
+ */
+#define SERIAL_NUMBER_BYTES16
+
+/*
+ * MAC_ADDR_BYTES: number of bytes used by the Ethernet MAC address
+ */
+#define MAC_ADDR_BYTES 6
+
+/*
+ * MAC_ADDR_STRLEN: length of mac address string
+ */
+#define MAC_ADDR_STRLEN17
+
+/*
+ * SiFive OUI. Registration Date is 2018-02-15
+ */
+#define SIFIVE_OUI_PREFIX  "70:B3:D5:92:F"
+
+/**
+ * static eeprom: EEPROM layout for the SiFive platform I2C format
+ */
+static struct __attribute__ ((__packed__)) sifive_eeprom {
+   u8 magic[MAGIC_NUMBER_BYTES];
+   u8 format_ver;
+   u16 product_id;
+   u8 pcb_revision;
+   u8 bom_revision;
+   u8 bom_variant;
+   u8 serial[SERIAL_NUMBER_BYTES];
+   u8 manuf_test_status;
+   u8 mac_addr[MAC_ADDR_BYTES];
+   u32 crc;
+} e;
+
+struct sifive_product {
+   u16 id;
+   const char *name;
+};
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read;
+
+/* Magic number at the first four bytes of EEPROM */
+static const unsigned char magic[MAGIC_NUMBER_BYTES] = { 0xf1, 0x5e, 0x50, 
0x45 };
+
+/* Does the magic number match that of a SiFive EEPROM? */
+static inline int is_match_magic(void)
+{
+   return (memcmp(, , MAGIC_NUMBER_BYTES) == 0);
+}
+
+/* Calculate the current CRC */
+static inline u32 calculate_crc32(void)
+{
+   return crc32(0, (void *), sizeof(struct sifive_eeprom) - 
sizeof(e.crc));
+}
+
+/* This function should be called after each update to the EEPROM structure */
+static inline void update_crc(void)
+{
+   e.crc = calculate_crc32();
+}
+
+static struct sifive_product sifive_products[] = {
+   { 0, "Unknown"},
+   { 2, "HiFive Unmatched" },
+};
+
+/**
+ * dump_raw_eeprom - display the raw contents of the EEPROM
+ */
+static void dump_raw_eeprom(void)
+{
+   unsigned int i;
+
+   printf("EEPROM dump: (0x%lx bytes)\n", sizeof(e));
+   for (i = 0; i < sizeof(e); i++) {
+   if ((i % 16) == 0)
+   printf("%02X: ", i);
+   printf("%02X ", ((u8 *))[i]);
+   if (((i % 16) == 15) || (i == sizeof(e) - 1))
+   printf("\n");
+   }
+}
+
+/**
+ * show_eeprom - display the contents of the EEPROM
+ */
+static void show_eeprom(void)
+{
+   unsigned int i;
+   u32 crc

[PATCH 2/6] riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controller

2021-06-30 Thread Zong Li

Enable the Opencores I2C controller on FU740

Signed-off-by: Zong Li 
---
 arch/riscv/cpu/fu740/Kconfig   | 2 ++
 board/sifive/unmatched/Kconfig | 1 +
 2 files changed, 3 insertions(+)

diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
index 3a5f6e47f5..1dc052ba31 100644
--- a/arch/riscv/cpu/fu740/Kconfig
+++ b/arch/riscv/cpu/fu740/Kconfig
@@ -35,3 +35,5 @@ config SIFIVE_FU740
imply SIFIVE_OTP
imply DM_PWM
imply PWM_SIFIVE
+   imply DM_I2C
+   imply SYS_I2C_OCORES
diff --git a/board/sifive/unmatched/Kconfig b/board/sifive/unmatched/Kconfig
index 88b5883cae..fb2c1fbb58 100644
--- a/board/sifive/unmatched/Kconfig
+++ b/board/sifive/unmatched/Kconfig
@@ -47,5 +47,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply PHY_MSCC
imply SYSRESET
imply SYSRESET_GPIO
+   imply CMD_I2C
 
 endif
-- 
2.31.1

[PATCH 0/6] Support multi-dtb in SPL on Unmatched board

2021-06-30 Thread Zong Li

This patch set contains the support I2C platform EEPROM and multi-dtb
mechanism on Unmatched board. There are two revisions of Unmatched with
different DDR timing respectively, so we'd like to support multi-dtb in
SPL, then it can select the right DTB at runtime according to PCB
revision in I2C EEPROM to initialize the right DDR timing.

The I2C EEPROM support is refactored based on Paul Welmsley's porting
and adopt many suggestions from David Abdurachmanov.

Zong Li (6):
  board: sifive: unmatched: add initial support for a platform ID EEPROM
  riscv: sifive: fu740: kconfig: Enable support for Opencores I2C
controller
  riscv: sifive: fu740: Support i2c in spl
  board: sifive: Add an interface to get PCB revision
  riscv: dts: add dts for unmatched rev1
  board: sifive: support spl multi-dtb on unmatched board

 arch/riscv/cpu/fu740/Kconfig  |3 +
 arch/riscv/dts/Makefile   |2 +-
 arch/riscv/dts/fu740-c000-u-boot.dtsi |4 +
 .../fu740-hifive-unmatched-a00-ddr-rev1.dtsi  | 1489 +
 .../dts/hifive-unmatched-a00-rev1-u-boot.dtsi |7 +
 arch/riscv/dts/hifive-unmatched-a00-rev1.dts  |4 +
 arch/riscv/include/asm/arch-fu740/eeprom.h|   15 +
 board/sifive/unmatched/Kconfig|1 +
 board/sifive/unmatched/Makefile   |1 +
 .../unmatched/hifive-platform-i2c-eeprom.c|  574 +++
 board/sifive/unmatched/spl.c  |   28 +-
 configs/sifive_unmatched_defconfig|4 +
 include/configs/sifive-unmatched.h|6 +
 13 files changed, 2135 insertions(+), 3 deletions(-)
 create mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
 create mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1-u-boot.dtsi
 create mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1.dts
 create mode 100644 arch/riscv/include/asm/arch-fu740/eeprom.h
 create mode 100644 board/sifive/unmatched/hifive-platform-i2c-eeprom.c

-- 
2.31.1

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