[U-Boot] [PATCH v3 4/5] ARMv8: Setup PSCI memory and device tree

[macro . wave . z]

From: Hongbo Zhang 

The newly added ARMv8 PSCI needs to be initialized, be copied or reserved in
right place, this patch does all the setup steps.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv8/cpu-dt.c   |  8 
 arch/arm/cpu/armv8/cpu.c  | 22 ++
 arch/arm/include/asm/secure.h |  2 +-
 arch/arm/include/asm/system.h | 11 +++
 arch/arm/lib/bootm.c  |  3 +++
 arch/arm/lib/psci-dt.c|  2 +-
 6 files changed, 46 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c
index 9ffb49c..f227a10 100644
--- a/arch/arm/cpu/armv8/cpu-dt.c
+++ b/arch/arm/cpu/armv8/cpu-dt.c
@@ -6,6 +6,7 @@
 
 #include 
 #include 
+#include 
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include 
 #endif
@@ -25,6 +26,13 @@ int psci_update_dt(void *fdt)
return 0;
 #endif
fdt_psci(fdt);
+
+#ifndef CONFIG_ARMV8_SECURE_BASE
+   /* secure code lives in RAM, keep it alive */
+   fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
+   __secure_end - __secure_start);
+#endif
+
 #endif
 #endif
return 0;
diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
index e06c3cc..5dcb5e2 100644
--- a/arch/arm/cpu/armv8/cpu.c
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 int cleanup_before_linux(void)
@@ -41,3 +42,24 @@ int cleanup_before_linux(void)
 
return 0;
 }
+
+#ifdef CONFIG_ARMV8_PSCI
+static void relocate_secure_section(void)
+{
+#ifdef CONFIG_ARMV8_SECURE_BASE
+   size_t sz = __secure_end - __secure_start;
+
+   memcpy((void *)CONFIG_ARMV8_SECURE_BASE, __secure_start, sz);
+   flush_dcache_range(CONFIG_ARMV8_SECURE_BASE,
+  CONFIG_ARMV8_SECURE_BASE + sz + 1);
+   invalidate_icache_all();
+#endif
+}
+
+void armv8_setup_psci(void)
+{
+   relocate_secure_section();
+   secure_ram_addr(psci_setup_vectors)();
+   secure_ram_addr(psci_arch_init)();
+}
+#endif
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
index 5a403bc..d23044a 100644
--- a/arch/arm/include/asm/secure.h
+++ b/arch/arm/include/asm/secure.h
@@ -6,7 +6,7 @@
 #define __secure __attribute__ ((section ("._secure.text")))
 #define __secure_data __attribute__ ((section ("._secure.data")))
 
-#ifdef CONFIG_ARMV7_SECURE_BASE
+#if defined(CONFIG_ARMV7_SECURE_BASE) || defined(CONFIG_ARMV8_SECURE_BASE)
 /*
  * Warning, horror ahead.
  *
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index b928bd8..9064e6b 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -118,6 +118,17 @@ void smc_call(struct pt_regs *args);
 void __noreturn psci_system_reset(void);
 void __noreturn psci_system_off(void);
 
+#ifdef CONFIG_ARMV8_PSCI
+extern char __secure_start[];
+extern char __secure_end[];
+extern char __secure_stack_start[];
+extern char __secure_stack_end[];
+
+void armv8_setup_psci(void);
+void psci_setup_vectors(void);
+void psci_arch_init(void);
+#endif
+
 #endif /* __ASSEMBLY__ */
 
 #else /* CONFIG_ARM64 */
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 53c3141..9fe1a5f 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -291,6 +291,9 @@ static void boot_jump_linux(bootm_headers_t *images, int 
flag)
announce_and_cleanup(fake);
 
if (!fake) {
+#ifdef CONFIG_ARMV8_PSCI
+   armv8_setup_psci();
+#endif
do_nonsec_virt_switch();
kernel_entry(images->ft_addr, NULL, NULL, NULL);
}
diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c
index baf6d70..a70f3d3 100644
--- a/arch/arm/lib/psci-dt.c
+++ b/arch/arm/lib/psci-dt.c
@@ -65,7 +65,7 @@ int fdt_psci(void *fdt)
 init_psci_node:
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
psci_ver = sec_firmware_support_psci_version();
-#elif defined(CONFIG_ARMV7_PSCI_1_0)
+#elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI)
psci_ver = ARM_PSCI_VER_1_0;
 #endif
switch (psci_ver) {
-- 
2.1.4

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[U-Boot] [PATCH v3 5/5] ARMv8: LS1043A: Enable LS1043A default PSCI support

[macro . wave . z]

From: Hongbo Zhang 

A most basic PSCI implementation with only one psci_version is added for
LS1043A, this can verify the generic PSCI framework, and more platform specific
implementation will be added later.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv8/fsl-layerscape/Makefile   |  1 +
 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S | 20 
 board/freescale/ls1043ardb/Kconfig   |  9 +
 configs/ls1043ardb_defconfig |  3 +++
 4 files changed, 33 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile 
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 51c1cee..423b4b3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -28,6 +28,7 @@ endif
 
 ifneq ($(CONFIG_LS1043A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
+obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o
 endif
 
 ifneq ($(CONFIG_ARCH_LS1012A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S 
b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
new file mode 100644
index 000..86045ac
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Author: Hongbo Zhang 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
+ */
+
+#include 
+#include 
+#include 
+
+   .pushsection ._secure.text, "ax"
+
+.globl psci_version
+psci_version:
+   ldr w0, =0x0001 /* PSCI v1.0 */
+   ret
+
+   .popsection
diff --git a/board/freescale/ls1043ardb/Kconfig 
b/board/freescale/ls1043ardb/Kconfig
index 51818ec..0c596f9 100644
--- a/board/freescale/ls1043ardb/Kconfig
+++ b/board/freescale/ls1043ardb/Kconfig
@@ -13,4 +13,13 @@ config SYS_SOC
 config SYS_CONFIG_NAME
default "ls1043ardb"
 
+config SYS_HAS_ARMV8_SECURE_BASE
+   bool "Enable secure RAM for PSCI image"
+   depends on ARMV8_PSCI
+   default y
+   help
+ PSCI image can be re-located to secure RAM.
+ If enabled, please also define the value for ARMV8_SECURE_BASE,
+ for LS1043ARDB, it is address in OCRAM.
+
 endif
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 79a4eb2..cb189f3 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -28,3 +28,6 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_ARMV8_PSCI=y
+CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4
+CONFIG_ARMV8_SECURE_BASE=0x1001
-- 
2.1.4

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[U-Boot] [PATCH v3 2/5] ARMv8: Add secure sections for PSCI text and data

[macro . wave . z]

From: Hongbo Zhang 

This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to
hold PSCI text and data, and it is based on the legacy implementation of ARMv7.

Signed-off-by: Hongbo Zhang 
Reviewed-by: Tom Rini 
---
 arch/arm/config.mk|  3 ++-
 arch/arm/cpu/armv8/Kconfig| 31 +++
 arch/arm/cpu/armv8/u-boot.lds | 57 +++
 3 files changed, 90 insertions(+), 1 deletion(-)

diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 542b897..112e334 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -118,7 +118,8 @@ endif
 
 # limit ourselves to the sections we want in the .bin.
 ifdef CONFIG_ARM64
-OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
+OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
+   -j .u_boot_list -j .rela.dyn
 else
 OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index cd2d9bb..f2a43b8 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -39,4 +39,35 @@ config PSCI_RESET
 
  Select Y here to make use of PSCI calls for system reset
 
+config ARMV8_PSCI
+   bool "Enable PSCI support" if EXPERT
+   default n
+   help
+ PSCI is Power State Coordination Interface defined by ARM.
+ The PSCI in U-boot provides a general framework and each platform
+ can implement their own specific PSCI functions.
+ Say Y here to enable PSCI support on ARMv8 platform.
+
+config ARMV8_PSCI_NR_CPUS
+   int "Maximum supported CPUs for PSCI"
+   depends on ARMV8_PSCI
+   default 4
+   help
+ The maximum number of CPUs supported in the PSCI firmware.
+ It is no problem to set a larger value than the number of CPUs in
+ the actual hardware implementation.
+
+if SYS_HAS_ARMV8_SECURE_BASE
+
+config ARMV8_SECURE_BASE
+   hex "Secure address for PSCI image"
+   depends on ARMV8_PSCI
+   help
+ Address for placing the PSCI text, data and stack sections.
+ If not defined, the PSCI sections are placed together with the u-boot
+ but platform can choose to place PSCI code image separately in other
+ places such as some secure RAM built-in SOC etc.
+
+endif
+
 endif
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index fd15ad5..22195b8 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -8,11 +8,17 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
+#include 
+#include 
+
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", 
"elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
 ENTRY(_start)
 SECTIONS
 {
+#ifdef CONFIG_ARMV8_SECURE_BASE
+   /DISCARD/ : { *(.rela._secure*) }
+#endif
. = 0x;
 
. = ALIGN(8);
@@ -23,6 +29,57 @@ SECTIONS
*(.text*)
}
 
+#ifdef CONFIG_ARMV8_PSCI
+   .__secure_start :
+#ifndef CONFIG_ARMV8_SECURE_BASE
+   ALIGN(CONSTANT(COMMONPAGESIZE))
+#endif
+   {
+   KEEP(*(.__secure_start))
+   }
+
+#ifndef CONFIG_ARMV8_SECURE_BASE
+#define CONFIG_ARMV8_SECURE_BASE
+#define __ARMV8_PSCI_STACK_IN_RAM
+#endif
+   .secure_text CONFIG_ARMV8_SECURE_BASE :
+   AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
+   {
+   *(._secure.text)
+   }
+
+   .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))
+   {
+   *(._secure.data)
+   }
+
+   .secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data),
+   CONSTANT(COMMONPAGESIZE)) (NOLOAD) :
+#ifdef __ARMV8_PSCI_STACK_IN_RAM
+   AT(ADDR(.secure_stack))
+#else
+   AT(LOADADDR(.secure_data) + SIZEOF(.secure_data))
+#endif
+   {
+   KEEP(*(.__secure_stack_start))
+
+   . = . + CONFIG_ARMV8_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
+
+   . = ALIGN(CONSTANT(COMMONPAGESIZE));
+
+   KEEP(*(.__secure_stack_end))
+   }
+
+#ifndef __ARMV8_PSCI_STACK_IN_RAM
+   . = LOADADDR(.secure_stack);
+#endif
+
+   .__secure_end : AT(ADDR(.__secure_end)) {
+   KEEP(*(.__secure_end))
+   LONG(0x1d1071c);/* Must output something to reset LMA */
+   }
+#endif
+
. = ALIGN(8);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
 
-- 
2.1.4

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[U-Boot] [PATCH v3 3/5] ARMv8: Add basic PSCI framework

[macro . wave . z]

From: Hongbo Zhang 

This patch introduces a generic ARMv8 PSCI framework, with all functions
returning a dummy ARM_PSCI_RET_NI (Not Implemented), then it is up to each
platform to implement their own functions based on this framework.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv8/Kconfig  |  10 ++
 arch/arm/cpu/armv8/Makefile |   1 +
 arch/arm/cpu/armv8/psci.S   | 286 
 arch/arm/include/asm/psci.h |  15 +++
 4 files changed, 312 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/psci.S

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index f2a43b8..173950d 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -57,6 +57,16 @@ config ARMV8_PSCI_NR_CPUS
  It is no problem to set a larger value than the number of CPUs in
  the actual hardware implementation.
 
+config ARMV8_PSCI_CPUS_PER_CLUSTER
+   int "Number of CPUs per cluster"
+   depends on ARMV8_PSCI
+   default 0
+   help
+ The number of CPUs per cluster, suppose each cluster has same number
+ of CPU cores, platforms with asymmetric clusters don't apply here.
+ A value 0 or no definition of it works for single cluster system.
+ System with multi-cluster should difine their own exact value.
+
 if SYS_HAS_ARMV8_SECURE_BASE
 
 config ARMV8_SECURE_BASE
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index dea1465..28ba786 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
 obj-$(CONFIG_S32V234) += s32v234/
 obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
 obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
+obj-$(CONFIG_ARMV8_PSCI) += psci.o
diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S
new file mode 100644
index 000..43d5d6b
--- /dev/null
+++ b/arch/arm/cpu/armv8/psci.S
@@ -0,0 +1,286 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Author: Hongbo Zhang 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
+ */
+
+#include 
+#include 
+#include 
+
+/* Default PSCI function, return -1, Not Implemented */
+#define PSCI_DEFAULT(__fn) \
+   ENTRY(__fn); \
+   mov w0, #ARM_PSCI_RET_NI; \
+   ret; \
+   ENDPROC(__fn); \
+   .weak __fn
+
+/* PSCI function and ID table definition*/
+#define PSCI_TABLE(__id, __fn) \
+   .word __id; \
+   .word __fn
+
+.pushsection ._secure.text, "ax"
+
+/* 32 bits PSCI default functions */
+PSCI_DEFAULT(psci_version)
+PSCI_DEFAULT(psci_cpu_suspend)
+PSCI_DEFAULT(psci_cpu_off)
+PSCI_DEFAULT(psci_cpu_on)
+PSCI_DEFAULT(psci_affinity_info)
+PSCI_DEFAULT(psci_migrate)
+PSCI_DEFAULT(psci_migrate_info_type)
+PSCI_DEFAULT(psci_migrate_info_up_cpu)
+PSCI_DEFAULT(psci_system_off)
+PSCI_DEFAULT(psci_system_reset)
+PSCI_DEFAULT(psci_features)
+PSCI_DEFAULT(psci_cpu_freeze)
+PSCI_DEFAULT(psci_cpu_default_suspend)
+PSCI_DEFAULT(psci_node_hw_state)
+PSCI_DEFAULT(psci_system_suspend)
+PSCI_DEFAULT(psci_set_suspend_mode)
+PSCI_DEFAULT(psi_stat_residency)
+PSCI_DEFAULT(psci_stat_count)
+
+.align 3
+_psci_32_table:
+PSCI_TABLE(ARM_PSCI_FN_CPU_SUSPEND, psci_cpu_suspend)
+PSCI_TABLE(ARM_PSCI_FN_CPU_OFF, psci_cpu_off)
+PSCI_TABLE(ARM_PSCI_FN_CPU_ON, psci_cpu_on)
+PSCI_TABLE(ARM_PSCI_FN_MIGRATE, psci_migrate)
+PSCI_TABLE(ARM_PSCI_0_2_FN_PSCI_VERSION, psci_version)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_SUSPEND, psci_cpu_suspend)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_OFF, psci_cpu_off)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_ON, psci_cpu_on)
+PSCI_TABLE(ARM_PSCI_0_2_FN_AFFINITY_INFO, psci_affinity_info)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE, psci_migrate)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE, psci_migrate_info_type)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU, psci_migrate_info_up_cpu)
+PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_OFF, psci_system_off)
+PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_RESET, psci_system_reset)
+PSCI_TABLE(ARM_PSCI_1_0_FN_PSCI_FEATURES, psci_features)
+PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_FREEZE, psci_cpu_freeze)
+PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND, psci_cpu_default_suspend)
+PSCI_TABLE(ARM_PSCI_1_0_FN_NODE_HW_STATE, psci_node_hw_state)
+PSCI_TABLE(ARM_PSCI_1_0_FN_SYSTEM_SUSPEND, psci_system_suspend)
+PSCI_TABLE(ARM_PSCI_1_0_FN_SET_SUSPEND_MODE, psci_set_suspend_mode)
+PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_RESIDENCY, psi_stat_residency)
+PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_COUNT, psci_stat_count)
+PSCI_TABLE(0, 0)
+
+/* 64 bits PSCI default functions */
+PSCI_DEFAULT(psci_cpu_suspend_64)
+PSCI_DEFAULT(psci_cpu_on_64)
+PSCI_DEFAULT(psci_affinity_info_64)
+PSCI_DEFAULT(psci_migrate_64)
+PSCI_DEFAULT(psci_migrate_info_up_cpu_64)
+PSCI_DEFAULT(psci_cpu_default_suspend_64)
+PSCI_DEFAULT(psci_node_hw_state_64)
+PSCI_DEFAULT(psci_system_suspend_64)
+PSCI_DEFAULT(psci_stat_residency_64)
+PSCI_DEFAULT(psci_stat_count_64)
+

[U-Boot] [PATCH v3 0/5] Add ARMv8 PSCI framework

[macro . wave . z]

From: Hongbo Zhang 

v2-v3 changes:
 - Drop the previous 1/6, since the previous CONFIG_ARMV8_PSCI in common parts
of codes also work for generic PSCI framework, so there are 5 patches in this
iteration.
 - Add "Reviewed-by: Tom Rini " for patches 1/5 and 2/5,
which were 2/6 and 3/6.
 - Move config values for ls1043 from armv8/Kconfig to s1043ardb_defconfig.

v1-v2 changes:
 - The new config options are introduced in Kconfig when used for first time
 - Introduce new config options in armv8/Kconfig instead of LS1043 platform
 - Move previous patch 5/6 to current 2/6 place

v1 notes:

This patch set introduces ARMv8 PSCI framework, all the PSCI functions are
implemented a default dummy one, it is up to each platform to implement their
own specific ones.

The first 1/6 patch is a prepare clean up for adding ARMv8 PSCI.
Patches 2/6 to 5/6 introduce new ARMv8 framework and set it up.
The last 6/6 adds a most simple implementation on NXP LS1043 platform, to
verify this framework.

This patch set mainly introduces ARMv8 PSCI framework, for easier review and
merge, further PSCI implementation on LS1043 is coming later.

Hongbo Zhang (5):
  ARMv8: Enable SMC instruction
  ARMv8: Add secure sections for PSCI text and data
  ARMv8: Add basic PSCI framework
  ARMv8: Setup PSCI memory and device tree
  ARMv8: LS1043A: Enable LS1043A default PSCI support

 arch/arm/config.mk   |   3 +-
 arch/arm/cpu/armv8/Kconfig   |  41 
 arch/arm/cpu/armv8/Makefile  |   1 +
 arch/arm/cpu/armv8/cpu-dt.c  |   8 +
 arch/arm/cpu/armv8/cpu.c |  22 ++
 arch/arm/cpu/armv8/fsl-layerscape/Makefile   |   1 +
 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S |  20 ++
 arch/arm/cpu/armv8/psci.S| 286 +++
 arch/arm/cpu/armv8/u-boot.lds|  57 +
 arch/arm/include/asm/macro.h |   2 +-
 arch/arm/include/asm/psci.h  |  15 ++
 arch/arm/include/asm/secure.h|   2 +-
 arch/arm/include/asm/system.h|  11 +
 arch/arm/lib/bootm.c |   3 +
 arch/arm/lib/psci-dt.c   |   2 +-
 board/freescale/ls1043ardb/Kconfig   |   9 +
 configs/ls1043ardb_defconfig |   3 +
 17 files changed, 482 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
 create mode 100644 arch/arm/cpu/armv8/psci.S

-- 
2.1.4

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[U-Boot] [PATCH v3 1/5] ARMv8: Enable SMC instruction

[macro . wave . z]

From: Hongbo Zhang 

PSCI implementation needs the SMC instruction to be enabled.
Following the legacy codes pattern, no bit macro definition and bit operation
are used, only the immediate data used in line is changed.

Signed-off-by: Hongbo Zhang 
Reviewed-by: Tom Rini 
---
 arch/arm/include/asm/macro.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 9bb0efa..35ea002 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -137,7 +137,7 @@ lr  .reqx30
 
 .macro armv8_switch_to_el2_m, xreg1
/* 64bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
-   mov \xreg1, #0x5b1
+   mov \xreg1, #0x531
msr scr_el3, \xreg1
msr cptr_el3, xzr   /* Disable coprocessor traps to EL3 */
mov \xreg1, #0x33ff
-- 
2.1.4

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[U-Boot] [PATCH v2 5/6] ARMv8: Setup PSCI memory and dt

[macro . wave . z]

From: Hongbo Zhang 

Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right
place, this patch does all the setup steps.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv8/cpu-dt.c   | 10 ++
 arch/arm/cpu/armv8/cpu.c  | 22 ++
 arch/arm/include/asm/secure.h |  2 +-
 arch/arm/include/asm/system.h | 11 +++
 arch/arm/lib/bootm-fdt.c  |  3 ++-
 arch/arm/lib/bootm.c  |  3 +++
 arch/arm/lib/psci-dt.c|  5 +++--
 7 files changed, 52 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c
index 659ec27..753e21f 100644
--- a/arch/arm/cpu/armv8/cpu-dt.c
+++ b/arch/arm/cpu/armv8/cpu-dt.c
@@ -6,6 +6,7 @@
 
 #include 
 #include 
+#include 
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include 
 #endif
@@ -27,5 +28,14 @@ int psci_update_dt(void *fdt)
fdt_psci(fdt);
 #endif
 #endif
+
+#ifdef CONFIG_ARMV8_PSCI
+   fdt_psci(fdt);
+#ifndef CONFIG_ARMV8_SECURE_BASE
+   /* secure code lives in RAM, keep it alive */
+   fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
+   __secure_end - __secure_start);
+#endif
+#endif
return 0;
 }
diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
index e06c3cc..5dcb5e2 100644
--- a/arch/arm/cpu/armv8/cpu.c
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 int cleanup_before_linux(void)
@@ -41,3 +42,24 @@ int cleanup_before_linux(void)
 
return 0;
 }
+
+#ifdef CONFIG_ARMV8_PSCI
+static void relocate_secure_section(void)
+{
+#ifdef CONFIG_ARMV8_SECURE_BASE
+   size_t sz = __secure_end - __secure_start;
+
+   memcpy((void *)CONFIG_ARMV8_SECURE_BASE, __secure_start, sz);
+   flush_dcache_range(CONFIG_ARMV8_SECURE_BASE,
+  CONFIG_ARMV8_SECURE_BASE + sz + 1);
+   invalidate_icache_all();
+#endif
+}
+
+void armv8_setup_psci(void)
+{
+   relocate_secure_section();
+   secure_ram_addr(psci_setup_vectors)();
+   secure_ram_addr(psci_arch_init)();
+}
+#endif
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
index 5a403bc..d23044a 100644
--- a/arch/arm/include/asm/secure.h
+++ b/arch/arm/include/asm/secure.h
@@ -6,7 +6,7 @@
 #define __secure __attribute__ ((section ("._secure.text")))
 #define __secure_data __attribute__ ((section ("._secure.data")))
 
-#ifdef CONFIG_ARMV7_SECURE_BASE
+#if defined(CONFIG_ARMV7_SECURE_BASE) || defined(CONFIG_ARMV8_SECURE_BASE)
 /*
  * Warning, horror ahead.
  *
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index b928bd8..9064e6b 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -118,6 +118,17 @@ void smc_call(struct pt_regs *args);
 void __noreturn psci_system_reset(void);
 void __noreturn psci_system_off(void);
 
+#ifdef CONFIG_ARMV8_PSCI
+extern char __secure_start[];
+extern char __secure_end[];
+extern char __secure_stack_start[];
+extern char __secure_stack_end[];
+
+void armv8_setup_psci(void);
+void psci_setup_vectors(void);
+void psci_arch_init(void);
+#endif
+
 #endif /* __ASSEMBLY__ */
 
 #else /* CONFIG_ARM64 */
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
index 10a56e8..b23bce4 100644
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -53,7 +53,8 @@ int arch_fixup_fdt(void *blob)
return ret;
 #endif
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_FSL_PPA_ARMV8_PSCI)
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_FSL_PPA_ARMV8_PSCI) || \
+   defined(CONFIG_ARMV8_PSCI)
ret = psci_update_dt(blob);
if (ret)
return ret;
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 53c3141..9fe1a5f 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -291,6 +291,9 @@ static void boot_jump_linux(bootm_headers_t *images, int 
flag)
announce_and_cleanup(fake);
 
if (!fake) {
+#ifdef CONFIG_ARMV8_PSCI
+   armv8_setup_psci();
+#endif
do_nonsec_virt_switch();
kernel_entry(images->ft_addr, NULL, NULL, NULL);
}
diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c
index 41e139e..cc5e33d 100644
--- a/arch/arm/lib/psci-dt.c
+++ b/arch/arm/lib/psci-dt.c
@@ -16,7 +16,8 @@
 
 int fdt_psci(void *fdt)
 {
-#if defined(CONFIG_FSL_PPA_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI)
+#if defined(CONFIG_FSL_PPA_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI) || \
+   defined(CONFIG_ARMV8_PSCI)
int nodeoff;
unsigned int psci_ver = 0;
int tmp;
@@ -65,7 +66,7 @@ int fdt_psci(void *fdt)
 init_psci_node:
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
psci_ver = sec_firmware_support_psci_version();
-#elif defined(CONFIG_ARMV7_PSCI_1_0)
+#elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI)
psci_ver = ARM_PSCI_VER_1_0;
 #endif
switch 

[U-Boot] [PATCH v2 6/6] ARMv8: LS1043A: Enable LS1043A default PSCI support

[macro . wave . z]

From: Hongbo Zhang 

A most basic PSCI implementation with only one psci_version is added for
LS1043A, this can verify the generic PSCI framework, and more platform specific
implementation will be added later.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv8/Kconfig   |  3 +++
 arch/arm/cpu/armv8/fsl-layerscape/Makefile   |  1 +
 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S | 20 
 board/freescale/ls1043ardb/Kconfig   |  9 +
 configs/ls1043ardb_defconfig |  1 +
 5 files changed, 34 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 173950d..985bfca 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -51,6 +51,7 @@ config ARMV8_PSCI
 config ARMV8_PSCI_NR_CPUS
int "Maximum supported CPUs for PSCI"
depends on ARMV8_PSCI
+   default 4 if TARGET_LS1043ARDB
default 4
help
  The maximum number of CPUs supported in the PSCI firmware.
@@ -60,6 +61,7 @@ config ARMV8_PSCI_NR_CPUS
 config ARMV8_PSCI_CPUS_PER_CLUSTER
int "Number of CPUs per cluster"
depends on ARMV8_PSCI
+   default 4 if TARGET_LS1043ARDB
default 0
help
  The number of CPUs per cluster, suppose each cluster has same number
@@ -72,6 +74,7 @@ if SYS_HAS_ARMV8_SECURE_BASE
 config ARMV8_SECURE_BASE
hex "Secure address for PSCI image"
depends on ARMV8_PSCI
+   default 0x1001 if TARGET_LS1043ARDB
help
  Address for placing the PSCI text, data and stack sections.
  If not defined, the PSCI sections are placed together with the u-boot
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile 
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 51c1cee..423b4b3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -28,6 +28,7 @@ endif
 
 ifneq ($(CONFIG_LS1043A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
+obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o
 endif
 
 ifneq ($(CONFIG_ARCH_LS1012A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S 
b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
new file mode 100644
index 000..86045ac
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Author: Hongbo Zhang 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
+ */
+
+#include 
+#include 
+#include 
+
+   .pushsection ._secure.text, "ax"
+
+.globl psci_version
+psci_version:
+   ldr w0, =0x0001 /* PSCI v1.0 */
+   ret
+
+   .popsection
diff --git a/board/freescale/ls1043ardb/Kconfig 
b/board/freescale/ls1043ardb/Kconfig
index 51818ec..0c596f9 100644
--- a/board/freescale/ls1043ardb/Kconfig
+++ b/board/freescale/ls1043ardb/Kconfig
@@ -13,4 +13,13 @@ config SYS_SOC
 config SYS_CONFIG_NAME
default "ls1043ardb"
 
+config SYS_HAS_ARMV8_SECURE_BASE
+   bool "Enable secure RAM for PSCI image"
+   depends on ARMV8_PSCI
+   default y
+   help
+ PSCI image can be re-located to secure RAM.
+ If enabled, please also define the value for ARMV8_SECURE_BASE,
+ for LS1043ARDB, it is address in OCRAM.
+
 endif
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 7d627af..4bfd0aa 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -27,3 +27,4 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_ARMV8_PSCI=y
-- 
2.1.4

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[U-Boot] [PATCH v2 3/6] ARMv8: Add secure sections for PSCI text and data

[macro . wave . z]

From: Hongbo Zhang 

This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to
hold PSCI text and data, and it is based on the legacy implementation of ARMv7.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/config.mk|  3 ++-
 arch/arm/cpu/armv8/Kconfig| 31 +++
 arch/arm/cpu/armv8/u-boot.lds | 57 +++
 3 files changed, 90 insertions(+), 1 deletion(-)

diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 542b897..112e334 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -118,7 +118,8 @@ endif
 
 # limit ourselves to the sections we want in the .bin.
 ifdef CONFIG_ARM64
-OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
+OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
+   -j .u_boot_list -j .rela.dyn
 else
 OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index cd2d9bb..f2a43b8 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -39,4 +39,35 @@ config PSCI_RESET
 
  Select Y here to make use of PSCI calls for system reset
 
+config ARMV8_PSCI
+   bool "Enable PSCI support" if EXPERT
+   default n
+   help
+ PSCI is Power State Coordination Interface defined by ARM.
+ The PSCI in U-boot provides a general framework and each platform
+ can implement their own specific PSCI functions.
+ Say Y here to enable PSCI support on ARMv8 platform.
+
+config ARMV8_PSCI_NR_CPUS
+   int "Maximum supported CPUs for PSCI"
+   depends on ARMV8_PSCI
+   default 4
+   help
+ The maximum number of CPUs supported in the PSCI firmware.
+ It is no problem to set a larger value than the number of CPUs in
+ the actual hardware implementation.
+
+if SYS_HAS_ARMV8_SECURE_BASE
+
+config ARMV8_SECURE_BASE
+   hex "Secure address for PSCI image"
+   depends on ARMV8_PSCI
+   help
+ Address for placing the PSCI text, data and stack sections.
+ If not defined, the PSCI sections are placed together with the u-boot
+ but platform can choose to place PSCI code image separately in other
+ places such as some secure RAM built-in SOC etc.
+
+endif
+
 endif
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index fd15ad5..22195b8 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -8,11 +8,17 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
+#include 
+#include 
+
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", 
"elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
 ENTRY(_start)
 SECTIONS
 {
+#ifdef CONFIG_ARMV8_SECURE_BASE
+   /DISCARD/ : { *(.rela._secure*) }
+#endif
. = 0x;
 
. = ALIGN(8);
@@ -23,6 +29,57 @@ SECTIONS
*(.text*)
}
 
+#ifdef CONFIG_ARMV8_PSCI
+   .__secure_start :
+#ifndef CONFIG_ARMV8_SECURE_BASE
+   ALIGN(CONSTANT(COMMONPAGESIZE))
+#endif
+   {
+   KEEP(*(.__secure_start))
+   }
+
+#ifndef CONFIG_ARMV8_SECURE_BASE
+#define CONFIG_ARMV8_SECURE_BASE
+#define __ARMV8_PSCI_STACK_IN_RAM
+#endif
+   .secure_text CONFIG_ARMV8_SECURE_BASE :
+   AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
+   {
+   *(._secure.text)
+   }
+
+   .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))
+   {
+   *(._secure.data)
+   }
+
+   .secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data),
+   CONSTANT(COMMONPAGESIZE)) (NOLOAD) :
+#ifdef __ARMV8_PSCI_STACK_IN_RAM
+   AT(ADDR(.secure_stack))
+#else
+   AT(LOADADDR(.secure_data) + SIZEOF(.secure_data))
+#endif
+   {
+   KEEP(*(.__secure_stack_start))
+
+   . = . + CONFIG_ARMV8_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
+
+   . = ALIGN(CONSTANT(COMMONPAGESIZE));
+
+   KEEP(*(.__secure_stack_end))
+   }
+
+#ifndef __ARMV8_PSCI_STACK_IN_RAM
+   . = LOADADDR(.secure_stack);
+#endif
+
+   .__secure_end : AT(ADDR(.__secure_end)) {
+   KEEP(*(.__secure_end))
+   LONG(0x1d1071c);/* Must output something to reset LMA */
+   }
+#endif
+
. = ALIGN(8);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
 
-- 
2.1.4

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[U-Boot] [PATCH v2 4/6] ARMv8: Add basic PSCI framework

[macro . wave . z]

From: Hongbo Zhang 

This patch introduces a generic ARMv8 PSCI framework, with all functions
returning a dummy ARM_PSCI_RET_NI (Not Implemented), then it is up to each
platform to implement their own functions based on this framework.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv8/Kconfig  |  10 ++
 arch/arm/cpu/armv8/Makefile |   1 +
 arch/arm/cpu/armv8/psci.S   | 286 
 arch/arm/include/asm/psci.h |  15 +++
 4 files changed, 312 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/psci.S

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index f2a43b8..173950d 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -57,6 +57,16 @@ config ARMV8_PSCI_NR_CPUS
  It is no problem to set a larger value than the number of CPUs in
  the actual hardware implementation.
 
+config ARMV8_PSCI_CPUS_PER_CLUSTER
+   int "Number of CPUs per cluster"
+   depends on ARMV8_PSCI
+   default 0
+   help
+ The number of CPUs per cluster, suppose each cluster has same number
+ of CPU cores, platforms with asymmetric clusters don't apply here.
+ A value 0 or no definition of it works for single cluster system.
+ System with multi-cluster should difine their own exact value.
+
 if SYS_HAS_ARMV8_SECURE_BASE
 
 config ARMV8_SECURE_BASE
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index dea1465..28ba786 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
 obj-$(CONFIG_S32V234) += s32v234/
 obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
 obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
+obj-$(CONFIG_ARMV8_PSCI) += psci.o
diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S
new file mode 100644
index 000..43d5d6b
--- /dev/null
+++ b/arch/arm/cpu/armv8/psci.S
@@ -0,0 +1,286 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Author: Hongbo Zhang 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
+ */
+
+#include 
+#include 
+#include 
+
+/* Default PSCI function, return -1, Not Implemented */
+#define PSCI_DEFAULT(__fn) \
+   ENTRY(__fn); \
+   mov w0, #ARM_PSCI_RET_NI; \
+   ret; \
+   ENDPROC(__fn); \
+   .weak __fn
+
+/* PSCI function and ID table definition*/
+#define PSCI_TABLE(__id, __fn) \
+   .word __id; \
+   .word __fn
+
+.pushsection ._secure.text, "ax"
+
+/* 32 bits PSCI default functions */
+PSCI_DEFAULT(psci_version)
+PSCI_DEFAULT(psci_cpu_suspend)
+PSCI_DEFAULT(psci_cpu_off)
+PSCI_DEFAULT(psci_cpu_on)
+PSCI_DEFAULT(psci_affinity_info)
+PSCI_DEFAULT(psci_migrate)
+PSCI_DEFAULT(psci_migrate_info_type)
+PSCI_DEFAULT(psci_migrate_info_up_cpu)
+PSCI_DEFAULT(psci_system_off)
+PSCI_DEFAULT(psci_system_reset)
+PSCI_DEFAULT(psci_features)
+PSCI_DEFAULT(psci_cpu_freeze)
+PSCI_DEFAULT(psci_cpu_default_suspend)
+PSCI_DEFAULT(psci_node_hw_state)
+PSCI_DEFAULT(psci_system_suspend)
+PSCI_DEFAULT(psci_set_suspend_mode)
+PSCI_DEFAULT(psi_stat_residency)
+PSCI_DEFAULT(psci_stat_count)
+
+.align 3
+_psci_32_table:
+PSCI_TABLE(ARM_PSCI_FN_CPU_SUSPEND, psci_cpu_suspend)
+PSCI_TABLE(ARM_PSCI_FN_CPU_OFF, psci_cpu_off)
+PSCI_TABLE(ARM_PSCI_FN_CPU_ON, psci_cpu_on)
+PSCI_TABLE(ARM_PSCI_FN_MIGRATE, psci_migrate)
+PSCI_TABLE(ARM_PSCI_0_2_FN_PSCI_VERSION, psci_version)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_SUSPEND, psci_cpu_suspend)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_OFF, psci_cpu_off)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_ON, psci_cpu_on)
+PSCI_TABLE(ARM_PSCI_0_2_FN_AFFINITY_INFO, psci_affinity_info)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE, psci_migrate)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE, psci_migrate_info_type)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU, psci_migrate_info_up_cpu)
+PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_OFF, psci_system_off)
+PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_RESET, psci_system_reset)
+PSCI_TABLE(ARM_PSCI_1_0_FN_PSCI_FEATURES, psci_features)
+PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_FREEZE, psci_cpu_freeze)
+PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND, psci_cpu_default_suspend)
+PSCI_TABLE(ARM_PSCI_1_0_FN_NODE_HW_STATE, psci_node_hw_state)
+PSCI_TABLE(ARM_PSCI_1_0_FN_SYSTEM_SUSPEND, psci_system_suspend)
+PSCI_TABLE(ARM_PSCI_1_0_FN_SET_SUSPEND_MODE, psci_set_suspend_mode)
+PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_RESIDENCY, psi_stat_residency)
+PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_COUNT, psci_stat_count)
+PSCI_TABLE(0, 0)
+
+/* 64 bits PSCI default functions */
+PSCI_DEFAULT(psci_cpu_suspend_64)
+PSCI_DEFAULT(psci_cpu_on_64)
+PSCI_DEFAULT(psci_affinity_info_64)
+PSCI_DEFAULT(psci_migrate_64)
+PSCI_DEFAULT(psci_migrate_info_up_cpu_64)
+PSCI_DEFAULT(psci_cpu_default_suspend_64)
+PSCI_DEFAULT(psci_node_hw_state_64)
+PSCI_DEFAULT(psci_system_suspend_64)
+PSCI_DEFAULT(psci_stat_residency_64)
+PSCI_DEFAULT(psci_stat_count_64)
+

[U-Boot] [PATCH v2 2/6] ARMv8: Enable SMC instruction

[macro . wave . z]

From: Hongbo Zhang 

PSCI implementation needs the SMC instruction to be enabled.
Following the legacy codes pattern, no bit macro definition and bit operation
are used, only the immediate data used in line is changed.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/include/asm/macro.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 9bb0efa..35ea002 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -137,7 +137,7 @@ lr  .reqx30
 
 .macro armv8_switch_to_el2_m, xreg1
/* 64bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
-   mov \xreg1, #0x5b1
+   mov \xreg1, #0x531
msr scr_el3, \xreg1
msr cptr_el3, xzr   /* Disable coprocessor traps to EL3 */
mov \xreg1, #0x33ff
-- 
2.1.4

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[U-Boot] [PATCH v2 1/6] ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition

[macro . wave . z]

From: Hongbo Zhang 

NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI
implementation in PPA firmware, but this macro naming too generic, so this
patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI.
And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8
which will be added in following patchs.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv8/cpu-dt.c   | 2 +-
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c   | 3 ++-
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c   | 3 ++-
 arch/arm/cpu/armv8/sec_firmware.c | 2 +-
 arch/arm/cpu/armv8/sec_firmware_asm.S | 2 +-
 arch/arm/include/asm/armv8/sec_firmware.h | 2 +-
 arch/arm/lib/bootm-fdt.c  | 2 +-
 arch/arm/lib/psci-dt.c| 2 +-
 include/configs/ls1043ardb.h  | 2 +-
 9 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c
index 9ffb49c..659ec27 100644
--- a/arch/arm/cpu/armv8/cpu-dt.c
+++ b/arch/arm/cpu/armv8/cpu-dt.c
@@ -13,7 +13,7 @@
 int psci_update_dt(void *fdt)
 {
 #ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_FSL_PPA_ARMV8_PSCI)
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
/*
 * If the PSCI in SEC Firmware didn't work, avoid to update the
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index b7a2e0c..e5dd360 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -402,7 +402,8 @@ int arch_early_init_r(void)
 #endif
 
 #ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
+   defined(CONFIG_FSL_PPA_ARMV8_PSCI)
/* Check the psci version to determine if the psci is supported */
psci_ver = sec_firmware_support_psci_version();
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 1a8321b..d95546a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -41,7 +41,8 @@ void ft_fixup_cpu(void *blob)
int addr_cells;
u64 val, core_id;
size_t *boot_code_size = &(__secondary_boot_code_size);
-#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
+   defined(CONFIG_FSL_PPA_ARMV8_PSCI)
int node;
u32 psci_ver;
 
diff --git a/arch/arm/cpu/armv8/sec_firmware.c 
b/arch/arm/cpu/armv8/sec_firmware.c
index 2ddd67e..0b973f0 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -209,7 +209,7 @@ __weak bool sec_firmware_is_valid(const void 
*sec_firmware_img)
return true;
 }
 
-#ifdef CONFIG_ARMV8_PSCI
+#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
 /*
  * The PSCI_VERSION function is added from PSCI v0.2. When the PSCI
  * v0.1 received this function, the NOT_SUPPORTED (0x_) error
diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S 
b/arch/arm/cpu/armv8/sec_firmware_asm.S
index 0c6a462..d4a26b4 100644
--- a/arch/arm/cpu/armv8/sec_firmware_asm.S
+++ b/arch/arm/cpu/armv8/sec_firmware_asm.S
@@ -41,7 +41,7 @@ WEAK(_sec_firmware_entry)
 ret
 ENDPROC(_sec_firmware_entry)
 
-#ifdef CONFIG_ARMV8_PSCI
+#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
 ENTRY(_sec_firmware_support_psci_version)
mov x0, 0x8400
mov x1, 0x0
diff --git a/arch/arm/include/asm/armv8/sec_firmware.h 
b/arch/arm/include/asm/armv8/sec_firmware.h
index eb68185..a4e144b 100644
--- a/arch/arm/include/asm/armv8/sec_firmware.h
+++ b/arch/arm/include/asm/armv8/sec_firmware.h
@@ -14,7 +14,7 @@
 int sec_firmware_init(const void *, u32 *, u32 *);
 int _sec_firmware_entry(const void *, u32 *, u32 *);
 bool sec_firmware_is_valid(const void *);
-#ifdef CONFIG_ARMV8_PSCI
+#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
 unsigned int sec_firmware_support_psci_version(void);
 unsigned int _sec_firmware_support_psci_version(void);
 #endif
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
index a517550..10a56e8 100644
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -53,7 +53,7 @@ int arch_fixup_fdt(void *blob)
return ret;
 #endif
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_FSL_PPA_ARMV8_PSCI)
ret = psci_update_dt(blob);
if (ret)
return ret;
diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c
index baf6d70..41e139e 100644
--- a/arch/arm/lib/psci-dt.c
+++ b/arch/arm/lib/psci-dt.c
@@ -16,7 +16,7 @@
 
 int fdt_psci(void *fdt)
 {
-#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI)
+#if defined(CONFIG_FSL_PPA_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI)
int nodeoff;
unsigned int psci_ver = 0;
int tmp;
diff --git 

[U-Boot] [PATCH v2 0/6] Add ARMv8 PSCI framework

[macro . wave . z]

From: Hongbo Zhang 

v1-v2 changes:
 - The new config options are introduced in Kconfig when used for first time
 - Introduce new config options in armv8/Kconfig instead of LS1043 platform
 - Move previous patch 5/6 to current 2/6 place

v1 notes:

This patch set introduces ARMv8 PSCI framework, all the PSCI functions are
implemented a default dummy one, it is up to each platform to implement their
own specific ones.

The first 1/6 patch is a prepare clean up for adding ARMv8 PSCI.
Patches 2/6 to 5/6 introduce new ARMv8 framework and set it up.
The last 6/6 adds a most simple implementation on NXP LS1043 platform, to
verify this framework.

This patch set mainly introduces ARMv8 PSCI framework, for easier review and
merge, further PSCI implementation on LS1043 is coming later.

Hongbo Zhang (6):
  ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition
  ARMv8: Enable SMC instruction
  ARMv8: Add secure sections for PSCI text and data
  ARMv8: Add basic PSCI framework
  ARMv8: Setup PSCI memory and dt
  ARMv8: LS1043A: Enable LS1043A default PSCI support

 arch/arm/config.mk   |   3 +-
 arch/arm/cpu/armv8/Kconfig   |  44 
 arch/arm/cpu/armv8/Makefile  |   1 +
 arch/arm/cpu/armv8/cpu-dt.c  |  12 +-
 arch/arm/cpu/armv8/cpu.c |  22 ++
 arch/arm/cpu/armv8/fsl-layerscape/Makefile   |   1 +
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c  |   3 +-
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c  |   3 +-
 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S |  20 ++
 arch/arm/cpu/armv8/psci.S| 286 +++
 arch/arm/cpu/armv8/sec_firmware.c|   2 +-
 arch/arm/cpu/armv8/sec_firmware_asm.S|   2 +-
 arch/arm/cpu/armv8/u-boot.lds|  57 +
 arch/arm/include/asm/armv8/sec_firmware.h|   2 +-
 arch/arm/include/asm/macro.h |   2 +-
 arch/arm/include/asm/psci.h  |  15 ++
 arch/arm/include/asm/secure.h|   2 +-
 arch/arm/include/asm/system.h|  11 +
 arch/arm/lib/bootm-fdt.c |   3 +-
 arch/arm/lib/bootm.c |   3 +
 arch/arm/lib/psci-dt.c   |   5 +-
 board/freescale/ls1043ardb/Kconfig   |   9 +
 configs/ls1043ardb_defconfig |   1 +
 include/configs/ls1043ardb.h |   2 +-
 24 files changed, 498 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
 create mode 100644 arch/arm/cpu/armv8/psci.S

-- 
2.1.4

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[U-Boot] [PATCH 5/6] ARMv8: Enable SMC instruction

[macro . wave . z]

From: Hongbo Zhang 

PSCI implementation needs the SMC instruction to be enabled.
Following the legacy codes pattern, no bit macro definition and bit operation
are used, only the immediate data used in line is changed.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/include/asm/macro.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 9bb0efa..35ea002 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -137,7 +137,7 @@ lr  .reqx30
 
 .macro armv8_switch_to_el2_m, xreg1
/* 64bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
-   mov \xreg1, #0x5b1
+   mov \xreg1, #0x531
msr scr_el3, \xreg1
msr cptr_el3, xzr   /* Disable coprocessor traps to EL3 */
mov \xreg1, #0x33ff
-- 
2.1.4

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[U-Boot] [PATCH 6/6] ARMv8: LS1043A: Enable LS1043A default PSCI support

[macro . wave . z]

From: Hongbo Zhang 

A most basic PSCI implementation with only one psci_version is added for
LS1043A, this can verify the generic PSCI framework, and more platform specific
implementation will be added later.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv8/fsl-layerscape/Makefile   |  1 +
 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S | 20 
 board/freescale/ls1043ardb/Kconfig   | 18 ++
 configs/ls1043ardb_defconfig |  1 +
 4 files changed, 40 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile 
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 8c1317f..4eb0227 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -28,6 +28,7 @@ endif
 
 ifneq ($(CONFIG_LS1043A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
+obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o
 endif
 
 ifneq ($(CONFIG_LS1012A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S 
b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
new file mode 100644
index 000..86045ac
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Author: Hongbo Zhang 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
+ */
+
+#include 
+#include 
+#include 
+
+   .pushsection ._secure.text, "ax"
+
+.globl psci_version
+psci_version:
+   ldr w0, =0x0001 /* PSCI v1.0 */
+   ret
+
+   .popsection
diff --git a/board/freescale/ls1043ardb/Kconfig 
b/board/freescale/ls1043ardb/Kconfig
index 51818ec..0dc37eb 100644
--- a/board/freescale/ls1043ardb/Kconfig
+++ b/board/freescale/ls1043ardb/Kconfig
@@ -13,4 +13,22 @@ config SYS_SOC
 config SYS_CONFIG_NAME
default "ls1043ardb"
 
+if ARMV8_PSCI
+
+config ARMV8_PSCI_NR_CPUS
+   int "Number of total CPUs on board"
+   default 4
+
+config CPU_PER_CLUSTER
+   int "Number of CPUs per cluster"
+   default 4
+
+config ARMV8_SECURE_BASE
+   hex "Address of PSCI text, data and stack"
+   default 0x1001
+   help
+ The PSCI is placed in OCRAM2.
+
+endif
+
 endif
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 5c20e44..0f988a4 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -26,3 +26,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_ARMV8_PSCI=y
-- 
2.1.4

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[U-Boot] [PATCH 3/6] ARMv8: Add basic PSCI framework

[macro . wave . z]

From: Hongbo Zhang 

This patch introduces a generic ARMv8 PSCI framework, with all functions
returning a dummy ARM_PSCI_RET_NI (Not Implemented), then it is up to each
platform to implement their own functions based on this framework.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv8/Kconfig  |   6 +
 arch/arm/cpu/armv8/Makefile |   1 +
 arch/arm/cpu/armv8/psci.S   | 286 
 arch/arm/include/asm/psci.h |  15 +++
 4 files changed, 308 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/psci.S

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 7e1fc4c..9d4ea5b 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -21,4 +21,10 @@ config ARMV8_SPIN_TABLE
- Reserve the code for the spin-table and the release address
  via a /memreserve/ region in the Device Tree.
 
+config ARMV8_PSCI
+   bool "Enable PSCI support" if EXPERT
+   default n
+   help
+ Say Y here to enable PSCI support.
+
 endif
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index dea1465..28ba786 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
 obj-$(CONFIG_S32V234) += s32v234/
 obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
 obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
+obj-$(CONFIG_ARMV8_PSCI) += psci.o
diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S
new file mode 100644
index 000..e1271ed
--- /dev/null
+++ b/arch/arm/cpu/armv8/psci.S
@@ -0,0 +1,286 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Author: Hongbo Zhang 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
+ */
+
+#include 
+#include 
+#include 
+
+/* Default PSCI function, return -1, Not Implemented */
+#define PSCI_DEFAULT(__fn) \
+   ENTRY(__fn); \
+   mov w0, #ARM_PSCI_RET_NI; \
+   ret; \
+   ENDPROC(__fn); \
+   .weak __fn
+
+/* PSCI function and ID table definition*/
+#define PSCI_TABLE(__id, __fn) \
+   .word __id; \
+   .word __fn
+
+.pushsection ._secure.text, "ax"
+
+/* 32 bits PSCI default functions */
+PSCI_DEFAULT(psci_version)
+PSCI_DEFAULT(psci_cpu_suspend)
+PSCI_DEFAULT(psci_cpu_off)
+PSCI_DEFAULT(psci_cpu_on)
+PSCI_DEFAULT(psci_affinity_info)
+PSCI_DEFAULT(psci_migrate)
+PSCI_DEFAULT(psci_migrate_info_type)
+PSCI_DEFAULT(psci_migrate_info_up_cpu)
+PSCI_DEFAULT(psci_system_off)
+PSCI_DEFAULT(psci_system_reset)
+PSCI_DEFAULT(psci_features)
+PSCI_DEFAULT(psci_cpu_freeze)
+PSCI_DEFAULT(psci_cpu_default_suspend)
+PSCI_DEFAULT(psci_node_hw_state)
+PSCI_DEFAULT(psci_system_suspend)
+PSCI_DEFAULT(psci_set_suspend_mode)
+PSCI_DEFAULT(psi_stat_residency)
+PSCI_DEFAULT(psci_stat_count)
+
+.align 3
+_psci_32_table:
+PSCI_TABLE(ARM_PSCI_FN_CPU_SUSPEND, psci_cpu_suspend)
+PSCI_TABLE(ARM_PSCI_FN_CPU_OFF, psci_cpu_off)
+PSCI_TABLE(ARM_PSCI_FN_CPU_ON, psci_cpu_on)
+PSCI_TABLE(ARM_PSCI_FN_MIGRATE, psci_migrate)
+PSCI_TABLE(ARM_PSCI_0_2_FN_PSCI_VERSION, psci_version)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_SUSPEND, psci_cpu_suspend)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_OFF, psci_cpu_off)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_ON, psci_cpu_on)
+PSCI_TABLE(ARM_PSCI_0_2_FN_AFFINITY_INFO, psci_affinity_info)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE, psci_migrate)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE, psci_migrate_info_type)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU, psci_migrate_info_up_cpu)
+PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_OFF, psci_system_off)
+PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_RESET, psci_system_reset)
+PSCI_TABLE(ARM_PSCI_1_0_FN_PSCI_FEATURES, psci_features)
+PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_FREEZE, psci_cpu_freeze)
+PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND, psci_cpu_default_suspend)
+PSCI_TABLE(ARM_PSCI_1_0_FN_NODE_HW_STATE, psci_node_hw_state)
+PSCI_TABLE(ARM_PSCI_1_0_FN_SYSTEM_SUSPEND, psci_system_suspend)
+PSCI_TABLE(ARM_PSCI_1_0_FN_SET_SUSPEND_MODE, psci_set_suspend_mode)
+PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_RESIDENCY, psi_stat_residency)
+PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_COUNT, psci_stat_count)
+PSCI_TABLE(0, 0)
+
+/* 64 bits PSCI default functions */
+PSCI_DEFAULT(psci_cpu_suspend_64)
+PSCI_DEFAULT(psci_cpu_on_64)
+PSCI_DEFAULT(psci_affinity_info_64)
+PSCI_DEFAULT(psci_migrate_64)
+PSCI_DEFAULT(psci_migrate_info_up_cpu_64)
+PSCI_DEFAULT(psci_cpu_default_suspend_64)
+PSCI_DEFAULT(psci_node_hw_state_64)
+PSCI_DEFAULT(psci_system_suspend_64)
+PSCI_DEFAULT(psci_stat_residency_64)
+PSCI_DEFAULT(psci_stat_count_64)
+
+.align 3
+_psci_64_table:
+PSCI_TABLE(ARM_PSCI_0_2_FN64_CPU_SUSPEND, psci_cpu_suspend_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_CPU_ON, psci_cpu_on_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_AFFINITY_INFO, psci_affinity_info_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_MIGRATE, psci_migrate_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU, psci_migrate_info_up_cpu_64)

[U-Boot] [PATCH 4/6] ARMv8: Setup PSCI memory and dt

[macro . wave . z]

From: Hongbo Zhang 

Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right
place, this patch does all the setup steps.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv8/cpu-dt.c   | 10 ++
 arch/arm/cpu/armv8/cpu.c  | 22 ++
 arch/arm/include/asm/secure.h |  2 +-
 arch/arm/include/asm/system.h | 11 +++
 arch/arm/lib/bootm-fdt.c  |  3 ++-
 arch/arm/lib/bootm.c  |  3 +++
 arch/arm/lib/psci-dt.c|  5 +++--
 7 files changed, 52 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c
index 659ec27..753e21f 100644
--- a/arch/arm/cpu/armv8/cpu-dt.c
+++ b/arch/arm/cpu/armv8/cpu-dt.c
@@ -6,6 +6,7 @@
 
 #include 
 #include 
+#include 
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include 
 #endif
@@ -27,5 +28,14 @@ int psci_update_dt(void *fdt)
fdt_psci(fdt);
 #endif
 #endif
+
+#ifdef CONFIG_ARMV8_PSCI
+   fdt_psci(fdt);
+#ifndef CONFIG_ARMV8_SECURE_BASE
+   /* secure code lives in RAM, keep it alive */
+   fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
+   __secure_end - __secure_start);
+#endif
+#endif
return 0;
 }
diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
index e06c3cc..5dcb5e2 100644
--- a/arch/arm/cpu/armv8/cpu.c
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 int cleanup_before_linux(void)
@@ -41,3 +42,24 @@ int cleanup_before_linux(void)
 
return 0;
 }
+
+#ifdef CONFIG_ARMV8_PSCI
+static void relocate_secure_section(void)
+{
+#ifdef CONFIG_ARMV8_SECURE_BASE
+   size_t sz = __secure_end - __secure_start;
+
+   memcpy((void *)CONFIG_ARMV8_SECURE_BASE, __secure_start, sz);
+   flush_dcache_range(CONFIG_ARMV8_SECURE_BASE,
+  CONFIG_ARMV8_SECURE_BASE + sz + 1);
+   invalidate_icache_all();
+#endif
+}
+
+void armv8_setup_psci(void)
+{
+   relocate_secure_section();
+   secure_ram_addr(psci_setup_vectors)();
+   secure_ram_addr(psci_arch_init)();
+}
+#endif
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
index 5a403bc..d23044a 100644
--- a/arch/arm/include/asm/secure.h
+++ b/arch/arm/include/asm/secure.h
@@ -6,7 +6,7 @@
 #define __secure __attribute__ ((section ("._secure.text")))
 #define __secure_data __attribute__ ((section ("._secure.data")))
 
-#ifdef CONFIG_ARMV7_SECURE_BASE
+#if defined(CONFIG_ARMV7_SECURE_BASE) || defined(CONFIG_ARMV8_SECURE_BASE)
 /*
  * Warning, horror ahead.
  *
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 7b7b867..e26ec05 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -126,6 +126,17 @@ void smc_call(struct pt_regs *args);
 
 void __noreturn psci_system_reset(bool smc);
 
+#ifdef CONFIG_ARMV8_PSCI
+extern char __secure_start[];
+extern char __secure_end[];
+extern char __secure_stack_start[];
+extern char __secure_stack_end[];
+
+void armv8_setup_psci(void);
+void psci_setup_vectors(void);
+void psci_arch_init(void);
+#endif
+
 #endif /* __ASSEMBLY__ */
 
 #else /* CONFIG_ARM64 */
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
index 10a56e8..b23bce4 100644
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -53,7 +53,8 @@ int arch_fixup_fdt(void *blob)
return ret;
 #endif
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_FSL_PPA_ARMV8_PSCI)
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_FSL_PPA_ARMV8_PSCI) || \
+   defined(CONFIG_ARMV8_PSCI)
ret = psci_update_dt(blob);
if (ret)
return ret;
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 53c3141..9fe1a5f 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -291,6 +291,9 @@ static void boot_jump_linux(bootm_headers_t *images, int 
flag)
announce_and_cleanup(fake);
 
if (!fake) {
+#ifdef CONFIG_ARMV8_PSCI
+   armv8_setup_psci();
+#endif
do_nonsec_virt_switch();
kernel_entry(images->ft_addr, NULL, NULL, NULL);
}
diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c
index 41e139e..cc5e33d 100644
--- a/arch/arm/lib/psci-dt.c
+++ b/arch/arm/lib/psci-dt.c
@@ -16,7 +16,8 @@
 
 int fdt_psci(void *fdt)
 {
-#if defined(CONFIG_FSL_PPA_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI)
+#if defined(CONFIG_FSL_PPA_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI) || \
+   defined(CONFIG_ARMV8_PSCI)
int nodeoff;
unsigned int psci_ver = 0;
int tmp;
@@ -65,7 +66,7 @@ int fdt_psci(void *fdt)
 init_psci_node:
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
psci_ver = sec_firmware_support_psci_version();
-#elif defined(CONFIG_ARMV7_PSCI_1_0)
+#elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI)
psci_ver = ARM_PSCI_VER_1_0;
 #endif
switch (psci_ver) {
-- 
2.1.4

[U-Boot] [PATCH 0/6] Add ARMv8 PSCI framework

[macro . wave . z]

From: Hongbo Zhang 

This patch set introduces ARMv8 PSCI framework, all the PSCI functions are
implemented a default dummy one, it is up to each platform to implement their
own specific ones.

The first 1/6 patch is a prepare clean up for adding ARMv8 PSCI.
Patches 2/6 to 5/6 introduce new ARMv8 framework and set it up.
The last 6/6 adds a most simple implementation on NXP LS1043 platform, to
verify this framework.

This patch set mainly introduces ARMv8 PSCI framework, for easier review and
merge, further PSCI implementation on LS1043 is coming later.

Hongbo Zhang (6):
  ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition
  ARMv8: Add secure sections for PSCI text and data
  ARMv8: Add basic PSCI framework
  ARMv8: Setup PSCI memory and dt
  ARMv8: Enable SMC instruction
  ARMv8: LS1043A: Enable LS1043A default PSCI support

 arch/arm/config.mk   |   3 +-
 arch/arm/cpu/armv8/Kconfig   |   6 +
 arch/arm/cpu/armv8/Makefile  |   1 +
 arch/arm/cpu/armv8/cpu-dt.c  |  12 +-
 arch/arm/cpu/armv8/cpu.c |  22 ++
 arch/arm/cpu/armv8/fsl-layerscape/Makefile   |   1 +
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c  |   3 +-
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c  |   3 +-
 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S |  20 ++
 arch/arm/cpu/armv8/psci.S| 286 +++
 arch/arm/cpu/armv8/sec_firmware.c|   2 +-
 arch/arm/cpu/armv8/sec_firmware_asm.S|   2 +-
 arch/arm/cpu/armv8/u-boot.lds|  65 ++
 arch/arm/include/asm/armv8/sec_firmware.h|   2 +-
 arch/arm/include/asm/macro.h |   2 +-
 arch/arm/include/asm/psci.h  |  15 ++
 arch/arm/include/asm/secure.h|   2 +-
 arch/arm/include/asm/system.h|  11 +
 arch/arm/lib/bootm-fdt.c |   3 +-
 arch/arm/lib/bootm.c |   3 +
 arch/arm/lib/psci-dt.c   |   5 +-
 board/freescale/ls1043ardb/Kconfig   |  18 ++
 configs/ls1043ardb_defconfig |   1 +
 include/configs/ls1043ardb.h |   2 +-
 24 files changed, 477 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
 create mode 100644 arch/arm/cpu/armv8/psci.S

-- 
2.1.4

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[U-Boot] [PATCH 2/6] ARMv8: Add secure sections for PSCI text and data

[macro . wave . z]

From: Hongbo Zhang 

This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to
hold PSCI text and data, and it is based on the legacy implementation of ARMv7.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/config.mk|  3 +-
 arch/arm/cpu/armv8/u-boot.lds | 65 +++
 2 files changed, 67 insertions(+), 1 deletion(-)

diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 8f85862..a3d46ea 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -118,7 +118,8 @@ endif
 
 # limit ourselves to the sections we want in the .bin.
 ifdef CONFIG_ARM64
-OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
+OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
+   -j .u_boot_list -j .rela.dyn
 else
 OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index fd15ad5..464eccf 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -8,11 +8,17 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
+#include 
+#include 
+
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", 
"elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
 ENTRY(_start)
 SECTIONS
 {
+#if defined(CONFIG_ARMV8_SECURE_BASE)
+   /DISCARD/ : { *(.rela._secure*) }
+#endif
. = 0x;
 
. = ALIGN(8);
@@ -23,6 +29,65 @@ SECTIONS
*(.text*)
}
 
+#ifdef CONFIG_ARMV8_PSCI
+   .__secure_start :
+#ifndef CONFIG_ARMV8_SECURE_BASE
+   ALIGN(CONSTANT(COMMONPAGESIZE))
+#endif
+   {
+   KEEP(*(.__secure_start))
+   }
+
+#ifndef CONFIG_ARMV8_SECURE_BASE
+#define CONFIG_ARMV8_SECURE_BASE
+#define __ARMV8_PSCI_STACK_IN_RAM
+#endif
+   .secure_text CONFIG_ARMV8_SECURE_BASE :
+   AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
+   {
+   *(._secure.text)
+   }
+
+   .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))
+   {
+   *(._secure.data)
+   }
+
+   .secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data),
+   CONSTANT(COMMONPAGESIZE)) (NOLOAD) :
+#ifdef __ARMV8_PSCI_STACK_IN_RAM
+   AT(ADDR(.secure_stack))
+#else
+   AT(LOADADDR(.secure_data) + SIZEOF(.secure_data))
+#endif
+   {
+   KEEP(*(.__secure_stack_start))
+
+#ifdef CONFIG_ARMV8_PSCI_NR_CPUS
+   . = . + CONFIG_ARMV8_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
+#else
+   . = . + 4 * ARM_PSCI_STACK_SIZE;
+#endif
+   . = ALIGN(CONSTANT(COMMONPAGESIZE));
+
+   KEEP(*(.__secure_stack_end))
+
+#ifdef CONFIG_ARMV8_SECURE_MAX_SIZE
+   ASSERT((. - ADDR(.secure_text)) <= CONFIG_ARMV8_SECURE_MAX_SIZE,
+  "Error: secure section exceeds secure memory size");
+#endif
+   }
+
+#ifndef __ARMV8_PSCI_STACK_IN_RAM
+   . = LOADADDR(.secure_stack);
+#endif
+
+   .__secure_end : AT(ADDR(.__secure_end)) {
+   KEEP(*(.__secure_end))
+   LONG(0x1d1071c);/* Must output something to reset LMA */
+   }
+#endif
+
. = ALIGN(8);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
 
-- 
2.1.4

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[U-Boot] [PATCH 1/6] ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition

[macro . wave . z]

From: Hongbo Zhang 

NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI
implementation in PPA firmware, but this macro naming too generic, so this
patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI.
And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8
which will be added in following patchs.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv8/cpu-dt.c   | 2 +-
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c   | 3 ++-
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c   | 3 ++-
 arch/arm/cpu/armv8/sec_firmware.c | 2 +-
 arch/arm/cpu/armv8/sec_firmware_asm.S | 2 +-
 arch/arm/include/asm/armv8/sec_firmware.h | 2 +-
 arch/arm/lib/bootm-fdt.c  | 2 +-
 arch/arm/lib/psci-dt.c| 2 +-
 include/configs/ls1043ardb.h  | 2 +-
 9 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c
index 9ffb49c..659ec27 100644
--- a/arch/arm/cpu/armv8/cpu-dt.c
+++ b/arch/arm/cpu/armv8/cpu-dt.c
@@ -13,7 +13,7 @@
 int psci_update_dt(void *fdt)
 {
 #ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_FSL_PPA_ARMV8_PSCI)
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
/*
 * If the PSCI in SEC Firmware didn't work, avoid to update the
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 20be323..2929d45 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -379,7 +379,8 @@ int arch_early_init_r(void)
 #endif
 
 #ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
+   defined(CONFIG_FSL_PPA_ARMV8_PSCI)
/* Check the psci version to determine if the psci is supported */
psci_ver = sec_firmware_support_psci_version();
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 40d6a76..7851d15 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -41,7 +41,8 @@ void ft_fixup_cpu(void *blob)
int addr_cells;
u64 val, core_id;
size_t *boot_code_size = &(__secondary_boot_code_size);
-#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
+   defined(CONFIG_FSL_PPA_ARMV8_PSCI)
int node;
u32 psci_ver;
 
diff --git a/arch/arm/cpu/armv8/sec_firmware.c 
b/arch/arm/cpu/armv8/sec_firmware.c
index e21e199..488ad8a 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -199,7 +199,7 @@ __weak bool sec_firmware_is_valid(const void 
*sec_firmware_img)
return true;
 }
 
-#ifdef CONFIG_ARMV8_PSCI
+#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
 /*
  * The PSCI_VERSION function is added from PSCI v0.2. When the PSCI
  * v0.1 received this function, the NOT_SUPPORTED (0x_) error
diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S 
b/arch/arm/cpu/armv8/sec_firmware_asm.S
index 0c6a462..d4a26b4 100644
--- a/arch/arm/cpu/armv8/sec_firmware_asm.S
+++ b/arch/arm/cpu/armv8/sec_firmware_asm.S
@@ -41,7 +41,7 @@ WEAK(_sec_firmware_entry)
 ret
 ENDPROC(_sec_firmware_entry)
 
-#ifdef CONFIG_ARMV8_PSCI
+#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
 ENTRY(_sec_firmware_support_psci_version)
mov x0, 0x8400
mov x1, 0x0
diff --git a/arch/arm/include/asm/armv8/sec_firmware.h 
b/arch/arm/include/asm/armv8/sec_firmware.h
index eb68185..a4e144b 100644
--- a/arch/arm/include/asm/armv8/sec_firmware.h
+++ b/arch/arm/include/asm/armv8/sec_firmware.h
@@ -14,7 +14,7 @@
 int sec_firmware_init(const void *, u32 *, u32 *);
 int _sec_firmware_entry(const void *, u32 *, u32 *);
 bool sec_firmware_is_valid(const void *);
-#ifdef CONFIG_ARMV8_PSCI
+#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
 unsigned int sec_firmware_support_psci_version(void);
 unsigned int _sec_firmware_support_psci_version(void);
 #endif
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
index a517550..10a56e8 100644
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -53,7 +53,7 @@ int arch_fixup_fdt(void *blob)
return ret;
 #endif
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_FSL_PPA_ARMV8_PSCI)
ret = psci_update_dt(blob);
if (ret)
return ret;
diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c
index baf6d70..41e139e 100644
--- a/arch/arm/lib/psci-dt.c
+++ b/arch/arm/lib/psci-dt.c
@@ -16,7 +16,7 @@
 
 int fdt_psci(void *fdt)
 {
-#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI)
+#if defined(CONFIG_FSL_PPA_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI)
int nodeoff;
unsigned int psci_ver = 0;
int tmp;
diff --git 

[U-Boot] [PATCH v2] ARMv7: LS102xA: Move two macros from header files to Kconfig

[macro . wave . z]

From: Hongbo Zhang 

Following commits 217f92b and 1544698, these two config CPU_V7_HAS_NONSEC
and CPU_V7_HAS_VIRT are moved to Kconfig, for correctly select ARMV7_PSCI.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/Kconfig | 4 
 include/configs/ls1021aqds.h | 2 --
 include/configs/ls1021atwr.h | 2 --
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1560bcc..7fcb1cb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -818,12 +818,16 @@ config TARGET_LS1021AQDS
select CPU_V7
select SUPPORT_SPL
select ARCH_SUPPORT_PSCI
+   select CPU_V7_HAS_NONSEC
+   select CPU_V7_HAS_VIRT
 
 config TARGET_LS1021ATWR
bool "Support ls1021atwr"
select CPU_V7
select SUPPORT_SPL
select ARCH_SUPPORT_PSCI
+   select CPU_V7_HAS_NONSEC
+   select CPU_V7_HAS_VIRT
 
 config TARGET_LS1043AQDS
bool "Support ls1043aqds"
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 5aaecc7..7b608c1 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -563,8 +563,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_CMDLINE_EDITING
 
-#define CONFIG_ARMV7_NONSEC
-#define CONFIG_ARMV7_VIRT
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR0x01ee0200
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index ef238a4..d946224 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -425,8 +425,6 @@
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_CMDLINE_EDITING
 
-#define CONFIG_ARMV7_NONSEC
-#define CONFIG_ARMV7_VIRT
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR0x01ee0200
-- 
2.1.4

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[U-Boot] [PATCH] ARMv7: LS102xA: Move two macros from header files to Kconfig

[macro . wave . z]

From: Hongbo Zhang 

ARMV7_PSCI depends on ARMV7_NONSEC && ARCH_SUPPORT_PSCI, and ARMV7_NONSEC
depends on CPU_V7_HAS_NONSEC, LS102XA didn't enable CPU_V7_HAS_NONSEC, but
defined ARMV7_NONSEC in a internal header file, this cannot be recognized by
Kconfig, so ARMV7_PSCI isn't defined at last.
This patch selects CPU_V7_HAS_NONSEC in Kconfig, and remove ARMV7_NONSEC in
header file, and meanwhile selects CPU_V7_HAS_VIRT in Kconfig and remove
CONFIG_ARMV7_VIRT in header file too.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/Kconfig | 4 
 include/configs/ls1021aqds.h | 2 --
 include/configs/ls1021atwr.h | 2 --
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1560bcc..7fcb1cb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -818,12 +818,16 @@ config TARGET_LS1021AQDS
select CPU_V7
select SUPPORT_SPL
select ARCH_SUPPORT_PSCI
+   select CPU_V7_HAS_NONSEC
+   select CPU_V7_HAS_VIRT
 
 config TARGET_LS1021ATWR
bool "Support ls1021atwr"
select CPU_V7
select SUPPORT_SPL
select ARCH_SUPPORT_PSCI
+   select CPU_V7_HAS_NONSEC
+   select CPU_V7_HAS_VIRT
 
 config TARGET_LS1043AQDS
bool "Support ls1043aqds"
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 5aaecc7..7b608c1 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -563,8 +563,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_CMDLINE_EDITING
 
-#define CONFIG_ARMV7_NONSEC
-#define CONFIG_ARMV7_VIRT
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR0x01ee0200
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index ef238a4..d946224 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -425,8 +425,6 @@
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_CMDLINE_EDITING
 
-#define CONFIG_ARMV7_NONSEC
-#define CONFIG_ARMV7_VIRT
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR0x01ee0200
-- 
2.1.4

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[U-Boot] [UBOOT PATCH 3/4] nxp: ls102xa: add EPU Finite State Machine

[macro . wave . z]

From: Hongbo Zhang 

The EPU Finite State Machie (FSM) is used in both the last stage of system
suspend and the earliest stage of system resume.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv7/ls102xa/fsl_epu.c | 157 +++
 arch/arm/cpu/armv7/ls102xa/fsl_epu.h |   8 ++
 2 files changed, 165 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c 
b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
index 6212640..b4de523 100644
--- a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
@@ -9,6 +9,163 @@
 
 #include "fsl_epu.h"
 
+struct fsm_reg_vals epu_default_val[] = {
+   /* EPGCR (Event Processor Global Control Register) */
+   {EPGCR, 0},
+   /* EPECR (Event Processor Event Control Registers) */
+   {EPECR0 + EPECR_STRIDE * 0, 0},
+   {EPECR0 + EPECR_STRIDE * 1, 0},
+   {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
+   {EPECR0 + EPECR_STRIDE * 3, 0x8084},
+   {EPECR0 + EPECR_STRIDE * 4, 0x2084},
+   {EPECR0 + EPECR_STRIDE * 5, 0x0804},
+   {EPECR0 + EPECR_STRIDE * 6, 0x8084},
+   {EPECR0 + EPECR_STRIDE * 7, 0x8084},
+   {EPECR0 + EPECR_STRIDE * 8, 0x6084},
+   {EPECR0 + EPECR_STRIDE * 9, 0x0884},
+   {EPECR0 + EPECR_STRIDE * 10, 0x4284},
+   {EPECR0 + EPECR_STRIDE * 11, 0x9084},
+   {EPECR0 + EPECR_STRIDE * 12, 0x8084},
+   {EPECR0 + EPECR_STRIDE * 13, 0x0884},
+   {EPECR0 + EPECR_STRIDE * 14, 0x0284},
+   {EPECR0 + EPECR_STRIDE * 15, 0x0004},
+   /*
+* EPEVTCR (Event Processor EVT Pin Control Registers)
+* SCU8 triger EVT2, and SCU11 triger EVT9
+*/
+   {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
+   {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
+   {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x8001},
+   {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
+   {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
+   {EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
+   {EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
+   {EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
+   {EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
+   {EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB001},
+   /* EPCMPR (Event Processor Counter Compare Registers) */
+   {EPCMPR0 + EPCMPR_STRIDE * 0, 0},
+   {EPCMPR0 + EPCMPR_STRIDE * 1, 0},
+   {EPCMPR0 + EPCMPR_STRIDE * 2, 0x00FF},
+   {EPCMPR0 + EPCMPR_STRIDE * 3, 0},
+   {EPCMPR0 + EPCMPR_STRIDE * 4, 0x00FF},
+   {EPCMPR0 + EPCMPR_STRIDE * 5, 0x0020},
+   {EPCMPR0 + EPCMPR_STRIDE * 6, 0},
+   {EPCMPR0 + EPCMPR_STRIDE * 7, 0},
+   {EPCMPR0 + EPCMPR_STRIDE * 8, 0x00FF},
+   {EPCMPR0 + EPCMPR_STRIDE * 9, 0x00FF},
+   {EPCMPR0 + EPCMPR_STRIDE * 10, 0x00FF},
+   {EPCMPR0 + EPCMPR_STRIDE * 11, 0x00FF},
+   {EPCMPR0 + EPCMPR_STRIDE * 12, 0x00FF},
+   {EPCMPR0 + EPCMPR_STRIDE * 13, 0},
+   {EPCMPR0 + EPCMPR_STRIDE * 14, 0x00FF},
+   {EPCMPR0 + EPCMPR_STRIDE * 15, 0x00FF},
+   /* EPCCR (Event Processor Counter Control Registers) */
+   {EPCCR0 + EPCCR_STRIDE * 0, 0},
+   {EPCCR0 + EPCCR_STRIDE * 1, 0},
+   {EPCCR0 + EPCCR_STRIDE * 2, 0x9284},
+   {EPCCR0 + EPCCR_STRIDE * 3, 0},
+   {EPCCR0 + EPCCR_STRIDE * 4, 0x9284},
+   {EPCCR0 + EPCCR_STRIDE * 5, 0x9284},
+   {EPCCR0 + EPCCR_STRIDE * 6, 0},
+   {EPCCR0 + EPCCR_STRIDE * 7, 0},
+   {EPCCR0 + EPCCR_STRIDE * 8, 0x9284},
+   {EPCCR0 + EPCCR_STRIDE * 9, 0x9284},
+   {EPCCR0 + EPCCR_STRIDE * 10, 0x9284},
+   {EPCCR0 + EPCCR_STRIDE * 11, 0x9284},
+   {EPCCR0 + EPCCR_STRIDE * 12, 0x9284},
+   {EPCCR0 + EPCCR_STRIDE * 13, 0},
+   {EPCCR0 + EPCCR_STRIDE * 14, 0x9284},
+   {EPCCR0 + EPCCR_STRIDE * 15, 0x9284},
+   /* EPSMCR (Event Processor SCU Mux Control Registers) */
+   {EPSMCR0 + EPSMCR_STRIDE * 0, 0},
+   {EPSMCR0 + EPSMCR_STRIDE * 1, 0},
+   {EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C70},
+   {EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F00},
+   {EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F},
+   {EPSMCR0 + EPSMCR_STRIDE * 5, 0x2E00},
+   {EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C00},
+   {EPSMCR0 + EPSMCR_STRIDE * 7, 0x3000},
+   {EPSMCR0 + EPSMCR_STRIDE * 8, 0x6430},
+   {EPSMCR0 + EPSMCR_STRIDE * 9, 0x3000},
+   {EPSMCR0 + EPSMCR_STRIDE * 10, 0x6530},
+   {EPSMCR0 + EPSMCR_STRIDE * 11, 0x3174},
+   {EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F00},
+   {EPSMCR0 + EPSMCR_STRIDE * 13, 0x3100},
+   {EPSMCR0 + EPSMCR_STRIDE * 14, 0x0031},
+   {EPSMCR0 + EPSMCR_STRIDE * 15, 0x7600},
+   /* EPACR (Event Processor Action Control Registers) */
+   {EPACR0 + EPACR_STRIDE * 0, 0},
+   {EPACR0 + EPACR_STRIDE * 1, 0},
+   {EPACR0 + EPACR_STRIDE * 2, 0},
+   {EPACR0 + EPACR_STRIDE * 3, 0x0080},
+   {EPACR0 + EPACR_STRIDE * 4, 0},
+   {EPACR0 + EPACR_STRIDE * 

[U-Boot] [UBOOT PATCH 4/4] nxp: ls102xa: add LS1 PSCI system suspend

[macro . wave . z]

From: Hongbo Zhang 

The deep sleep function of LS1 platform, is mapped into PSCI system suspend
function, this patch adds implementation of it.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv7/ls102xa/Makefile   |   2 +-
 arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 236 ++
 arch/arm/cpu/armv7/ls102xa/psci.S |  11 ++
 board/freescale/common/arm_sleep.c|  35 -
 include/configs/ls1021aqds.h  |   1 +
 include/configs/ls1021atwr.h  |   1 +
 6 files changed, 284 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c

diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile 
b/arch/arm/cpu/armv7/ls102xa/Makefile
index 0228300..f8300c7 100644
--- a/arch/arm/cpu/armv7/ls102xa/Makefile
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -16,5 +16,5 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o 
ls102xa_serdes.o
 obj-$(CONFIG_SPL) += spl.o
 
 ifdef CONFIG_ARMV7_PSCI
-obj-y  += psci.o
+obj-y  += psci.o ls102xa_psci.o
 endif
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c 
b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
new file mode 100644
index 000..2ac2e6c
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -0,0 +1,236 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Author: Hongbo Zhang 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "fsl_epu.h"
+
+#define __secure __attribute__((section("._secure.text")))
+
+#define CCSR_GICD_CTLR 0x1000
+#define CCSR_GICC_CTLR 0x2000
+#define DCSR_RCPM_CG1CR0   0x31c
+#define DCSR_RCPM_CSTTACR0 0xb00
+#define DCFG_CRSTSR_WDRFR  0x8
+#define DDR_RESV_LEN   128
+
+#ifdef CONFIG_LS1_DEEP_SLEEP
+/*
+ * DDR controller initialization training breaks the first 128 bytes of DDR,
+ * save them so that the bootloader can restore them while resuming.
+ */
+static void __secure ls1_save_ddr_head(void)
+{
+   const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
+   char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
+   struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+   int i;
+
+   out_le32(>sparecr[2], dest);
+
+   for (i = 0; i < DDR_RESV_LEN; i++)
+   *dest++ = *src++;
+}
+
+static void __secure ls1_fsm_setup(void)
+{
+   void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+   void *dcsr_rcpm_base = (void *)CONFIG_SYS_DCSR_RCPM_ADDR;
+
+   out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x1001);
+   out_be32(dcsr_rcpm_base + DCSR_RCPM_CG1CR0, 0x0001);
+
+   fsl_epu_setup((void *)dcsr_epu_base);
+
+   /* Pull MCKE signal low before enabling deep sleep signal in FPGA */
+   out_be32(dcsr_epu_base + EPECR0, 0x5);
+   out_be32(dcsr_epu_base + EPSMCR15, 0x7630);
+}
+
+static void __secure ls1_deepsleep_irq_cfg(void)
+{
+   struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+   struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+   u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
+
+   /* Mask interrupts from GIC */
+   out_be32(>nfiqoutr, 0x0);
+   out_be32(>nirqoutr, 0x0);
+   /* Mask deep sleep wake-up interrupts while entering deep sleep */
+   out_be32(>dsimskr, 0x0);
+
+   ippdexpcr0 = in_be32(>ippdexpcr0);
+   /*
+* Workaround: There is bug of register ippdexpcr1, when read it always
+* returns zero, so its value is saved to a scrachpad register to be
+* read, that is why we don't read it from register ippdexpcr1 itself.
+*/
+   ippdexpcr1 = in_le32(>sparecr[7]);
+
+   if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
+   pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |
+SCFG_PMCINTECR_ETSECRXG1 |
+SCFG_PMCINTECR_ETSECERRG0 |
+SCFG_PMCINTECR_ETSECERRG1;
+
+   if (ippdexpcr0 & RCPM_IPPDEXPCR0_GPIO)
+   pmcintecr |= SCFG_PMCINTECR_GPIO;
+
+   if (ippdexpcr1 & RCPM_IPPDEXPCR1_LPUART)
+   pmcintecr |= SCFG_PMCINTECR_LPUART;
+
+   if (ippdexpcr1 & RCPM_IPPDEXPCR1_FLEXTIMER)
+   pmcintecr |= SCFG_PMCINTECR_FTM;
+
+   /* Always set external IRQ pins as wakeup source */
+   pmcintecr |= SCFG_PMCINTECR_IRQ0 | SCFG_PMCINTECR_IRQ1;
+
+   out_be32(>pmcintlecr, 0);
+   /* Clear PMC interrupt status */
+   out_be32(>pmcintsr, 0x);
+   /* Enable wakeup interrupt during deep sleep */
+   out_be32(>pmcintecr, pmcintecr);
+}
+
+static void __secure ls1_delay(unsigned int loop)
+{
+   while (loop--) {
+   int i = 1000;
+   while (i--)

[U-Boot] [UBOOT PATCH 2/4] nxp: ls102xa: add registers definition for system sleep

[macro . wave . z]

From: Hongbo Zhang 

This patch adds definitions of all the regesters necessary for system sleep.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/include/asm/arch-ls102xa/config.h|  2 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 52 ++-
 include/configs/ls1021aqds.h  |  7 +++
 3 files changed, 60 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index d408fe4..b995a00 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -18,7 +18,9 @@
 #define CONFIG_SYS_DCSRBAR 0x2000
 
 #define CONFIG_SYS_DCSR_DCFG_ADDR  (CONFIG_SYS_DCSRBAR + 0x0022)
+#define CONFIG_SYS_DCSR_RCPM_ADDR  (CONFIG_SYS_DCSRBAR + 0x00222000)
 
+#define CONFIG_SYS_GIC_ADDR(CONFIG_SYS_IMMR + 0x0040)
 #define CONFIG_SYS_FSL_DDR_ADDR(CONFIG_SYS_IMMR + 
0x0008)
 #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x0018)
 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x0051)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 0a80772..c34fd63 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -161,6 +161,17 @@ struct ccsr_gur {
 #define SCFG_SNPCNFGCR_DBG_RD_WR   0x000c
 #define SCFG_SNPCNFGCR_EDMA_SNP0x0002
 #define SCFG_ENDIANCR_LE   0x8000
+#define SCFG_DPSLPCR_WDRR_EN   0x0001
+#define SCFG_PMCINTECR_LPUART  0x4000
+#define SCFG_PMCINTECR_FTM 0x2000
+#define SCFG_PMCINTECR_GPIO0x1000
+#define SCFG_PMCINTECR_IRQ00x0800
+#define SCFG_PMCINTECR_IRQ10x0400
+#define SCFG_PMCINTECR_ETSECRXG0   0x0080
+#define SCFG_PMCINTECR_ETSECRXG1   0x0040
+#define SCFG_PMCINTECR_ETSECERRG0  0x0008
+#define SCFG_PMCINTECR_ETSECERRG1  0x0004
+#define SCFG_CLUSTERPMCR_WFIL2EN   0x8000
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
@@ -226,7 +237,7 @@ struct ccsr_scfg {
u32 debug_streamid;
u32 resv10[5];
u32 snpcnfgcr;
-   u32 resv11[1];
+   u32 hrstcr;
u32 intpcr;
u32 resv12[20];
u32 scfgrevcr;
@@ -243,6 +254,9 @@ struct ccsr_scfg {
u32 sdhciovserlcr;
u32 resv14[61];
u32 sparecr[8];
+   u32 resv15[248];
+   u32 core0sftrstsr;
+   u32 clusterpmcr;
 };
 
 /* Clocking */
@@ -433,6 +447,42 @@ struct ccsr_ahci {
u32 cmds;   /* port 0/1 CMD status error */
 };
 
+#define RCPM_POWMGTCSR 0x130
+#define RCPM_POWMGTCSR_SERDES_PW   0x8000
+#define RCPM_POWMGTCSR_LPM20_REQ   0x0010
+#define RCPM_POWMGTCSR_LPM20_ST0x0200
+#define RCPM_POWMGTCSR_P_LPM20_ST  0x0100
+#define RCPM_IPPDEXPCR00x140
+#define RCPM_IPPDEXPCR0_ETSEC  0x8000
+#define RCPM_IPPDEXPCR0_GPIO   0x0040
+#define RCPM_IPPDEXPCR10x144
+#define RCPM_IPPDEXPCR1_LPUART 0x4000
+#define RCPM_IPPDEXPCR1_FLEXTIMER  0x2000
+#define RCPM_IPPDEXPCR1_OCRAM1 0x1000
+#define RCPM_NFIQOUTR  0x15c
+#define RCPM_NIRQOUTR  0x16c
+#define RCPM_DSIMSKR   0x18c
+#define RCPM_CLPCL10SETR   0x1c4
+#define RCPM_CLPCL10SETR_C00x0001
+
+struct ccsr_rcpm {
+   u8 rev1[0x4c];
+   u32 twaitsr;
+   u8 rev2[0xe0];
+   u32 powmgtcsr;
+   u8 rev3[0xc];
+   u32 ippdexpcr0;
+   u32 ippdexpcr1;
+   u8 rev4[0x14];
+   u32 nfiqoutr;
+   u8 rev5[0xc];
+   u32 nirqoutr;
+   u8 rev6[0x1c];
+   u32 dsimskr;
+   u8 rev7[0x34];
+   u32 clpcl10setr;
+};
+
 uint get_svr(void);
 
 #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 47180f9..7c12fc9 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -289,6 +289,13 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START  0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
+#define QIXIS_CTL_SYS  0x5
+#define QIXIS_CTL_SYS_EVTSW_MASK   0x0c
+#define QIXIS_CTL_SYS_EVTSW_IRQ0x04
+#define QIXIS_RST_FORCE_3  0x45
+#define QIXIS_RST_FORCE_3_PCIESLOT10x80
+#define QIXIS_PWR_CTL2 0x21
+#define QIXIS_PWR_CTL2_PCTL0x2
 
 #define CONFIG_SYS_FPGA_CSPR_EXT   (0x0)
 #define CONFIG_SYS_FPGA_CSPR   (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
-- 
2.1.4

___
U-Boot 

[U-Boot] [UBOOT PATCH 0/4] Add LS1 PSCI system suspend

[macro . wave . z]

From: Hongbo Zhang 

This patch set is based against latest community uboot tree in which my
PSCIv1.0 support was merged.
Currently doesn't apply our internal SDK uboot, when these get merged in
community we can pull them back into SDK.

We need community kernel to test this PSCI system suspend too, our internal
SDK kernel is too old for PSCI.
And more codes are needed to be added into kernel to do this test, such as
a Flex timer as wake up device, and one peice of code to write IPPDEXPCR
registers before SMC call.

All patches have been tested on both LA1021ATWR and LS1021AQDS.

Hongbo Zhang (4):
  armv7: psci: make v7_flush_dcache_all public for all psci code
  nxp: ls102xa: add registers definition for system sleep
  nxp: ls102xa: add EPU Finite State Machine
  nxp: ls102xa: add LS1 PSCI system suspend

 arch/arm/cpu/armv7/ls102xa/Makefile   |   2 +-
 arch/arm/cpu/armv7/ls102xa/fsl_epu.c  | 157 ++
 arch/arm/cpu/armv7/ls102xa/fsl_epu.h  |   8 +
 arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 236 ++
 arch/arm/cpu/armv7/ls102xa/psci.S |  11 +
 arch/arm/cpu/armv7/psci.S |   6 +-
 arch/arm/include/asm/arch-ls102xa/config.h|   2 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  52 -
 arch/arm/include/asm/psci.h   |   2 +
 board/freescale/common/arm_sleep.c|  35 +++-
 include/configs/ls1021aqds.h  |   8 +
 include/configs/ls1021atwr.h  |   1 +
 12 files changed, 514 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c

-- 
2.1.4

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[U-Boot] [UBOOT PATCH 1/4] armv7: psci: make v7_flush_dcache_all public for all psci code

[macro . wave . z]

From: Hongbo Zhang 

The v7_flush_dcache_all function will be called by ls102xa platform system
suspend, it is necessary to make it a public call instead of a local one, but
changing the LENTRY to ENTRY isn't enough, because there is another one using
the same name, so this one gets a psci_ prefix.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv7/psci.S   | 6 +++---
 arch/arm/include/asm/psci.h | 2 ++
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index f80f6e2..6a36208 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -187,7 +187,7 @@ ENDPROC(psci_get_cpu_id)
 .weak psci_get_cpu_id
 
 /* Imported from Linux kernel */
-LENTRY(v7_flush_dcache_all)
+ENTRY(psci_v7_flush_dcache_all)
stmfd   sp!, {r4-r5, r7, r9-r11, lr}
dmb @ ensure ordering with previous 
memory accesses
mrc p15, 1, r0, c0, c0, 1   @ read clidr
@@ -234,7 +234,7 @@ finished:
isb
ldmfd   sp!, {r4-r5, r7, r9-r11, lr}
bx  lr
-ENDPROC(v7_flush_dcache_all)
+ENDPROC(psci_v7_flush_dcache_all)
 
 ENTRY(psci_disable_smp)
mrc p15, 0, r0, c1, c0, 1   @ ACTLR
@@ -264,7 +264,7 @@ ENTRY(psci_cpu_off_common)
isb
dsb
 
-   bl  v7_flush_dcache_all
+   bl  psci_v7_flush_dcache_all
 
clrex   @ Why???
 
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 8aefaa7..9b068f0 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -86,6 +86,8 @@ void psci_cpu_off_common(void);
 int psci_update_dt(void *fdt);
 void psci_board_init(void);
 int fdt_psci(void *fdt);
+
+void psci_v7_flush_dcache_all(void);
 #endif /* ! __ASSEMBLY__ */
 
 #endif /* __ARM_PSCI_H__ */
-- 
2.1.4

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[U-Boot] [PATCH v6 1/4] ARMv7: PSCI: add PSCI v1.0 functions skeleton

[macro . wave . z]

From: Hongbo Zhang 

This patch adds all the PSCI v1.0 functions in to the common framework, with
all the functions returning "not implemented" by default, as a common framework
all the dummy functions are added here, it is up to every platform developer to
decide which version of PSCI and which functions to implement.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/psci.S| 78 
 arch/arm/cpu/armv7/virt-dt.c | 10 +-
 arch/arm/include/asm/psci.h  | 16 +
 3 files changed, 103 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 350b75c..f80f6e2 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -46,20 +46,62 @@ ENTRY(default_psci_vector)
 ENDPROC(default_psci_vector)
 .weak default_psci_vector
 
+ENTRY(psci_version)
 ENTRY(psci_cpu_suspend)
 ENTRY(psci_cpu_off)
 ENTRY(psci_cpu_on)
+ENTRY(psci_affinity_info)
 ENTRY(psci_migrate)
+ENTRY(psci_migrate_info_type)
+ENTRY(psci_migrate_info_up_cpu)
+ENTRY(psci_system_off)
+ENTRY(psci_system_reset)
+ENTRY(psci_features)
+ENTRY(psci_cpu_freeze)
+ENTRY(psci_cpu_default_suspend)
+ENTRY(psci_node_hw_state)
+ENTRY(psci_system_suspend)
+ENTRY(psci_set_suspend_mode)
+ENTRY(psi_stat_residency)
+ENTRY(psci_stat_count)
mov r0, #ARM_PSCI_RET_NI@ Return -1 (Not Implemented)
mov pc, lr
+ENDPROC(psci_stat_count)
+ENDPROC(psi_stat_residency)
+ENDPROC(psci_set_suspend_mode)
+ENDPROC(psci_system_suspend)
+ENDPROC(psci_node_hw_state)
+ENDPROC(psci_cpu_default_suspend)
+ENDPROC(psci_cpu_freeze)
+ENDPROC(psci_features)
+ENDPROC(psci_system_reset)
+ENDPROC(psci_system_off)
+ENDPROC(psci_migrate_info_up_cpu)
+ENDPROC(psci_migrate_info_type)
 ENDPROC(psci_migrate)
+ENDPROC(psci_affinity_info)
 ENDPROC(psci_cpu_on)
 ENDPROC(psci_cpu_off)
 ENDPROC(psci_cpu_suspend)
+ENDPROC(psci_version)
+.weak psci_version
 .weak psci_cpu_suspend
 .weak psci_cpu_off
 .weak psci_cpu_on
+.weak psci_affinity_info
 .weak psci_migrate
+.weak psci_migrate_info_type
+.weak psci_migrate_info_up_cpu
+.weak psci_system_off
+.weak psci_system_reset
+.weak psci_features
+.weak psci_cpu_freeze
+.weak psci_cpu_default_suspend
+.weak psci_node_hw_state
+.weak psci_system_suspend
+.weak psci_set_suspend_mode
+.weak psi_stat_residency
+.weak psci_stat_count
 
 _psci_table:
.word   ARM_PSCI_FN_CPU_SUSPEND
@@ -70,6 +112,42 @@ _psci_table:
.word   psci_cpu_on
.word   ARM_PSCI_FN_MIGRATE
.word   psci_migrate
+   .word   ARM_PSCI_0_2_FN_PSCI_VERSION
+   .word   psci_version
+   .word   ARM_PSCI_0_2_FN_CPU_SUSPEND
+   .word   psci_cpu_suspend
+   .word   ARM_PSCI_0_2_FN_CPU_OFF
+   .word   psci_cpu_off
+   .word   ARM_PSCI_0_2_FN_CPU_ON
+   .word   psci_cpu_on
+   .word   ARM_PSCI_0_2_FN_AFFINITY_INFO
+   .word   psci_affinity_info
+   .word   ARM_PSCI_0_2_FN_MIGRATE
+   .word   psci_migrate
+   .word   ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE
+   .word   psci_migrate_info_type
+   .word   ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU
+   .word   psci_migrate_info_up_cpu
+   .word   ARM_PSCI_0_2_FN_SYSTEM_OFF
+   .word   psci_system_off
+   .word   ARM_PSCI_0_2_FN_SYSTEM_RESET
+   .word   psci_system_reset
+   .word   ARM_PSCI_1_0_FN_PSCI_FEATURES
+   .word   psci_features
+   .word   ARM_PSCI_1_0_FN_CPU_FREEZE
+   .word   psci_cpu_freeze
+   .word   ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND
+   .word   psci_cpu_default_suspend
+   .word   ARM_PSCI_1_0_FN_NODE_HW_STATE
+   .word   psci_node_hw_state
+   .word   ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
+   .word   psci_system_suspend
+   .word   ARM_PSCI_1_0_FN_SET_SUSPEND_MODE
+   .word   psci_set_suspend_mode
+   .word   ARM_PSCI_1_0_FN_STAT_RESIDENCY
+   .word   psi_stat_residency
+   .word   ARM_PSCI_1_0_FN_STAT_COUNT
+   .word   psci_stat_count
.word   0
.word   0
 
diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
index 32c368f..5e31891 100644
--- a/arch/arm/cpu/armv7/virt-dt.c
+++ b/arch/arm/cpu/armv7/virt-dt.c
@@ -67,7 +67,15 @@ static int fdt_psci(void *fdt)
return nodeoff;
}
 
-   tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci");
+#ifdef CONFIG_ARMV7_PSCI_1_0
+   tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci-1.0");
+   if (tmp)
+   return tmp;
+   tmp = fdt_appendprop_string(fdt, nodeoff, "compatible", "arm,psci-0.2");
+   if (tmp)
+   return tmp;
+#endif
+   tmp = fdt_appendprop_string(fdt, nodeoff, "compatible", "arm,psci");
if (tmp)
return tmp;
tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc");
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 

[U-Boot] [PATCH v6 4/4] ARMv7: PSCI: ls102xa: move secure text section into OCRAM

[macro . wave . z]

From: Hongbo Zhang 

LS1021 offers two secure OCRAM blocks for trustzone.
This patch moves all the secure text sections into the OCRAM.

Signed-off-by: Wang Dongsheng 
Signed-off-by: Hongbo Zhang 
---
 arch/arm/include/asm/arch-ls102xa/config.h | 2 +-
 include/configs/ls1021aqds.h   | 2 ++
 include/configs/ls1021atwr.h   | 2 ++
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index 7a0e4bf..4729044 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -10,7 +10,7 @@
 #define CONFIG_SYS_CACHELINE_SIZE  64
 
 #define OCRAM_BASE_ADDR0x1000
-#define OCRAM_SIZE 0x0002
+#define OCRAM_SIZE 0x0001
 #define OCRAM_BASE_S_ADDR  0x1001
 #define OCRAM_S_SIZE   0x0001
 
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index ba3331f..47180f9 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -13,6 +13,8 @@
 #define CONFIG_ARMV7_PSCI_1_0
 #define CONFIG_ARMV7_PSCI_NR_CPUS  CONFIG_MAX_CPUS
 
+#define CONFIG_ARMV7_SECURE_BASE   OCRAM_BASE_S_ADDR
+
 #define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 96ad683..16b5d9c 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -13,6 +13,8 @@
 #define CONFIG_ARMV7_PSCI_1_0
 #define CONFIG_ARMV7_PSCI_NR_CPUS  CONFIG_MAX_CPUS
 
+#define CONFIG_ARMV7_SECURE_BASE   OCRAM_BASE_S_ADDR
+
 #define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_DISPLAY_CPUINFO
-- 
2.1.4

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[U-Boot] [PATCH v6 0/4] ARMv7: PSCI: add PSCI v1.0 support

[macro . wave . z]

From: Hongbo Zhang 

v6 changes:
- Remove the patch of fixing psci stack and patch of fixing saving target PC
since Chen-Yu Tsai's patches resovle them in other way and already got merged
- Temporarily remove patch of checking ON_PENDING and ALREADY_ON for reasons:
it is better the hardware has bits to show the states, there may be compete
conditions for pure software implementation, and if this is well designed in
future, codes can be placed in the psci-common.c file, currently this patch
series only covers necesary psci 1.0 and some implementation on ls1021.
- Update codes according to Chen-Yu Tsai's review comments.

v5 changes:
- Give up fixing the potential bug of PSCI stack overlap with secure text end
when there is more CPUs in system. Because I just want to keep this series as
simple as it could be: adding basic PSCI v1.0 support and adding more PSCI
v1.0 implements of our platform.
While too compplicated patches in assembly language won't call for effective
reviews, even I think there is potential bug of PSCI stack, let's fix it in
sepetated patch later.
- Move the patch of factoring out psci_cpu_on_common to earlier place 2/8, so
that the following patches can only update the psci_cpu_on_common instead of
touching each platform's psci_cpu_on, this reduces patches size obviously and
make it easier for review.

v4 changes:
- since there is already PSCI v0.2 function IDs definition merged in 5a07abb,
I give up my previous patches 1/11 and 2/11, and move previous 7/11 "ARMv7:
PSCI: add PSCI v1.0 functions skeleton" as current first one 1/9
- accept Andre's comment to add the missed "arm,psci-0,2" into compatible
string

v3 changes:
- patch 3/11, re-init the stack pointer to address like start of page instead
of page end, because for ARM push operation, the stack pointer is encreased
before storing data.
- patch 10/11, delete the previous un-implemented cpu_suspend function for ls1
platform, because there is default blank functions for all those are not
implemented in specific platform.


v2 changes:
- re-organize psci_cpu_on_common, this code should be called by each platform's
psci_cpu_on, should not be a function calling each psci_cpu_on, all related
functions are updated due to this change
- update some registers usage, e.g. if r10 is used without push/pop, u-boot
cannot launch rt-kernel
- update some comments to be clearer, re-organize all patches for easier review
- add patch to check already_on or on_pending for LS102XA

This patch set contains two parts:
ARMv7 PSCI common framework: fix some issues and add v1.0 support
NXP (was Freescale) LS102XA: codes enhancement and add v1.0 implementation
And this patch set was initially created by Dongsheng Wang.

Hongbo Zhang (4):
  ARMv7: PSCI: add PSCI v1.0 functions skeleton
  ARMv7: PSCI: ls102xa: check target CPU ID before further operations
  ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention
  ARMv7: PSCI: ls102xa: move secure text section into OCRAM

 arch/arm/cpu/armv7/ls102xa/psci.S  | 138 -
 arch/arm/cpu/armv7/psci.S  |  78 
 arch/arm/cpu/armv7/virt-dt.c   |  10 ++-
 arch/arm/include/asm/arch-ls102xa/config.h |   3 +-
 arch/arm/include/asm/psci.h|  21 +
 board/freescale/ls1021aqds/Makefile|   1 +
 board/freescale/ls1021aqds/psci.S  |  33 +++
 board/freescale/ls1021atwr/Makefile|   1 +
 board/freescale/ls1021atwr/psci.S  |  25 ++
 include/configs/ls1021aqds.h   |   5 ++
 include/configs/ls1021atwr.h   |   3 +
 11 files changed, 313 insertions(+), 5 deletions(-)
 create mode 100644 board/freescale/ls1021aqds/psci.S
 create mode 100644 board/freescale/ls1021atwr/psci.S

-- 
2.1.4

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[U-Boot] [PATCH v6 3/4] ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention

[macro . wave . z]

From: Hongbo Zhang 

This patch implements PSCI functions for ls102xa SoC following PSCI v1.0,
they are as the list:
psci_version,
psci_features,
psci_cpu_suspend,
psci_affinity_info,
psci_system_reset,
psci_system_off.

Tested on LS1021aQDS, LS1021aTWR.

Signed-off-by: Wang Dongsheng 
Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv7/ls102xa/psci.S  | 103 -
 arch/arm/include/asm/arch-ls102xa/config.h |   1 +
 board/freescale/ls1021aqds/Makefile|   1 +
 board/freescale/ls1021aqds/psci.S  |  33 +
 board/freescale/ls1021atwr/Makefile|   1 +
 board/freescale/ls1021atwr/psci.S  |  25 +++
 include/configs/ls1021aqds.h   |   3 +
 include/configs/ls1021atwr.h   |   1 +
 8 files changed, 166 insertions(+), 2 deletions(-)
 create mode 100644 board/freescale/ls1021aqds/psci.S
 create mode 100644 board/freescale/ls1021atwr/psci.S

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index cba9c1e..8f38680 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -12,19 +12,72 @@
 #include 
 #include 
 
+#define RCPM_TWAITSR   0x04C
+
 #define SCFG_CORE0_SFT_RST  0x130
 #define SCFG_CORESRENCR 0x204
 
-#define DCFG_CCSR_BRR   0x0E4
-#define DCFG_CCSR_SCRATCHRW10x200
+#define DCFG_CCSR_RSTCR0x0B0
+#define DCFG_CCSR_RSTCR_RESET_REQ  0x2
+#define DCFG_CCSR_BRR  0x0E4
+#define DCFG_CCSR_SCRATCHRW1   0x200
+
+#define PSCI_FN_PSCI_VERSION_FEATURE_MASK  0x0
+#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK   0x0
+#define PSCI_FN_CPU_OFF_FEATURE_MASK   0x0
+#define PSCI_FN_CPU_ON_FEATURE_MASK0x0
+#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0
+#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK0x0
+#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK  0x0
 
.pushsection ._secure.text, "ax"
 
.arch_extension sec
 
+   .align  5
+
 #defineONE_MS  (GENERIC_TIMER_CLK / 1000)
 #defineRESET_WAIT  (30 * ONE_MS)
 
+.globl psci_version
+psci_version:
+   movwr0, #0
+   movtr0, #1
+
+   bx  lr
+
+_ls102x_psci_supported_table:
+   .word   ARM_PSCI_0_2_FN_PSCI_VERSION
+   .word   PSCI_FN_PSCI_VERSION_FEATURE_MASK
+   .word   ARM_PSCI_0_2_FN_CPU_SUSPEND
+   .word   PSCI_FN_CPU_SUSPEND_FEATURE_MASK
+   .word   ARM_PSCI_0_2_FN_CPU_OFF
+   .word   PSCI_FN_CPU_OFF_FEATURE_MASK
+   .word   ARM_PSCI_0_2_FN_CPU_ON
+   .word   PSCI_FN_CPU_ON_FEATURE_MASK
+   .word   ARM_PSCI_0_2_FN_AFFINITY_INFO
+   .word   PSCI_FN_AFFINITY_INFO_FEATURE_MASK
+   .word   ARM_PSCI_0_2_FN_SYSTEM_OFF
+   .word   PSCI_FN_SYSTEM_OFF_FEATURE_MASK
+   .word   ARM_PSCI_0_2_FN_SYSTEM_RESET
+   .word   PSCI_FN_SYSTEM_RESET_FEATURE_MASK
+   .word   0
+   .word   ARM_PSCI_RET_NI
+
+.globl psci_features
+psci_features:
+   adr r2, _ls102x_psci_supported_table
+1: ldr r3, [r2]
+   cmp r3, #0
+   beq out_psci_features
+   cmp r1, r3
+   addne   r2, r2, #8
+   bne 1b
+
+out_psci_features:
+   ldr r0, [r2, #4]
+   bx  lr
+
 @ r0: return value ARM_PSCI_RET_SUCCESS or ARM_PSCI_RET_INVAL
 @ r1: input target CPU ID in MPIDR format, original value in r1 may be dropped
 @ r4: output validated CPU ID if ARM_PSCI_RET_SUCCESS returns, meaningless for
@@ -144,4 +197,50 @@ psci_cpu_off:
 1: wfi
b   1b
 
+.globl psci_affinity_info
+psci_affinity_info:
+   push{lr}
+
+   mov r0, #ARM_PSCI_RET_INVAL
+
+   @ Verify Affinity level
+   cmp r2, #0
+   bne out_affinity_info
+
+   bl  psci_check_target_cpu_id
+   cmp r0, #ARM_PSCI_RET_INVAL
+   beq out_affinity_info
+   mov r1, r4
+
+   @ Get RCPM base address
+   movwr4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0x)
+   movtr4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
+
+   mov r0, #PSCI_AFFINITY_LEVEL_ON
+
+   @ Detect target CPU state
+   ldr r2, [r4, #RCPM_TWAITSR]
+   rev r2, r2
+   lsr r2, r2, r1
+   andsr2, r2, #1
+   beq out_affinity_info
+
+   mov r0, #PSCI_AFFINITY_LEVEL_OFF
+
+out_affinity_info:
+   pop {pc}
+
+.globl psci_system_reset
+psci_system_reset:
+   @ Get DCFG base address
+   movwr1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0x)
+   movtr1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+
+   mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
+   rev r2, r2
+   str r2, [r1, #DCFG_CCSR_RSTCR]
+
+1: wfi
+   b   1b
+
.popsection
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index 04abec4..7a0e4bf 100644
--- 

[U-Boot] [PATCH v6 2/4] ARMv7: PSCI: ls102xa: check target CPU ID before further operations

[macro . wave . z]

From: Hongbo Zhang 

The input parameter CPU ID needs to be validated before furher oprations such
as CPU_ON, this patch introduces the function to do this.

Signed-off-by: Wang Dongsheng 
Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv7/ls102xa/psci.S | 35 ++-
 arch/arm/include/asm/psci.h   |  5 +
 2 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index f9b26b4..cba9c1e 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -25,6 +25,36 @@
 #defineONE_MS  (GENERIC_TIMER_CLK / 1000)
 #defineRESET_WAIT  (30 * ONE_MS)
 
+@ r0: return value ARM_PSCI_RET_SUCCESS or ARM_PSCI_RET_INVAL
+@ r1: input target CPU ID in MPIDR format, original value in r1 may be dropped
+@ r4: output validated CPU ID if ARM_PSCI_RET_SUCCESS returns, meaningless for
+@ ARM_PSCI_RET_INVAL,suppose caller saves r4 before calling
+LENTRY(psci_check_target_cpu_id)
+   @ Get the real CPU number
+   and r4, r1, #0xff
+   mov r0, #ARM_PSCI_RET_INVAL
+
+   @ Bit[31:24], bits must be zero.
+   tst r1, #0xff00
+   bxnelr
+
+   @ Affinity level 2 - Cluster: only one cluster in LS1021xa.
+   tst r1, #0xff
+   bxnelr
+
+   @ Affinity level 1 - Processors: should be in 0xf00 format.
+   lsr r1, r1, #8
+   teq r1, #0xf
+   bxnelr
+
+   @ Affinity level 0 - CPU: only 0, 1 are valid in LS1021xa.
+   cmp r4, #2
+   bxgelr
+
+   mov r0, #ARM_PSCI_RET_SUCCESS
+   bx  lr
+ENDPROC(psci_check_target_cpu_id)
+
@ r1 = target CPU
@ r2 = target PC
 .globl psci_cpu_on
@@ -33,7 +63,9 @@ psci_cpu_on:
 
@ Clear and Get the correct CPU number
@ r1 = 0xf01
-   and r4, r1, #0xff
+   bl  psci_check_target_cpu_id
+   cmp r0, #ARM_PSCI_RET_INVAL
+   beq out_psci_cpu_on
 
mov r0, r4
mov r1, r2
@@ -101,6 +133,7 @@ holdoff_release:
@ Return
mov r0, #ARM_PSCI_RET_SUCCESS
 
+out_psci_cpu_on:
pop {r4, r5, r6, lr}
bx  lr
 
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 58f8b39..67f472a 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -67,6 +67,11 @@
 #define ARM_PSCI_STACK_SHIFT   10
 #define ARM_PSCI_STACK_SIZE(1 << ARM_PSCI_STACK_SHIFT)
 
+/* PSCI affinity level state returned by AFFINITY_INFO */
+#define PSCI_AFFINITY_LEVEL_ON 0
+#define PSCI_AFFINITY_LEVEL_OFF1
+#define PSCI_AFFINITY_LEVEL_ON_PENDING 2
+
 #ifndef __ASSEMBLY__
 #include 
 
-- 
2.1.4

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[U-Boot] [PATCH v5 2/8] ARMv7: PSCI: factor out reusable psci_cpu_on_common

[macro . wave . z]

From: Hongbo Zhang 

There are codes for saving target PC in each platform psci_cpu_on routines,
these can be factored out as psci_cpu_on_common.
Another purpose is that the codes of saving target PC will be changed a bit and
a new context ID will be saved in the following patches, then we can update the
psci_cpu_on_common mainly instead of touching every platform's psci_cpu_on
functions more times, this makes it easier for coding and being reviewed.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/ls102xa/psci.S |  5 +
 arch/arm/cpu/armv7/mx7/psci.S |  5 +
 arch/arm/cpu/armv7/psci.S | 12 
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S |  5 +
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S |  5 +
 arch/arm/mach-tegra/psci.S|  5 +
 6 files changed, 17 insertions(+), 20 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index cf5cd48..548c507 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -35,10 +35,7 @@ psci_cpu_on:
@ r1 = 0xf01
and r1, r1, #0xff
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   str r2, [r0]
-   dsb
+   bl  psci_cpu_on_common
 
@ Get DCFG base address
movwr4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0x)
diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S
index 34c6ab3..74fdc4d 100644
--- a/arch/arm/cpu/armv7/mx7/psci.S
+++ b/arch/arm/cpu/armv7/mx7/psci.S
@@ -29,10 +29,7 @@ psci_arch_init:
 psci_cpu_on:
push{lr}
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   str r2, [r0]
-   dsb
+   bl  psci_cpu_on_common
 
ldr r2, =psci_cpu_entry
bl  imx_cpu_on
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 8e25300..3b92f1d 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -253,6 +253,18 @@ ENTRY(psci_enable_smp)
 ENDPROC(psci_enable_smp)
 .weak psci_enable_smp
 
+/* expects target CPU in r1, target PC in r2 */
+ENTRY(psci_cpu_on_common)
+   push{lr}
+
+   mov r0, r1
+   bl  psci_get_cpu_stack_top  @ get stack top of target CPU
+   str r2, [r0]@ store target PC at stack top
+   dsb
+
+   pop {pc}
+ENDPROC(psci_cpu_on_common)
+
 ENTRY(psci_cpu_off_common)
push{lr}
 
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 90b5bfd..016e491 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -134,10 +134,7 @@ out:   mcr p15, 0, r7, c1, c1, 0
 psci_cpu_on:
push{lr}
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   str r2, [r0]@ store target PC at stack top
-   dsb
+   bl  psci_cpu_on_common
 
movwr0, #(SUN6I_CPUCFG_BASE & 0x)
movtr0, #(SUN6I_CPUCFG_BASE >> 16)
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index e15d587..0ebb30e 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -123,10 +123,7 @@ out:   mcr p15, 0, r7, c1, c1, 0
 psci_cpu_on:
push{lr}
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   str r2, [r0]@ store target PC at stack top
-   dsb
+   bl  psci_cpu_on_common
 
movwr0, #(SUN7I_CPUCFG_BASE & 0x)
movtr0, #(SUN7I_CPUCFG_BASE >> 16)
diff --git a/arch/arm/mach-tegra/psci.S b/arch/arm/mach-tegra/psci.S
index b836da1..8a0147c 100644
--- a/arch/arm/mach-tegra/psci.S
+++ b/arch/arm/mach-tegra/psci.S
@@ -90,10 +90,7 @@ ENDPROC(psci_cpu_off)
 ENTRY(psci_cpu_on)
push{lr}
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   str r2, [r0]@ store target PC at stack top
-   dsb
+   bl  psci_cpu_on_common
 
ldr r6, =TEGRA_RESET_EXCEPTION_VECTOR
ldr r5, =psci_cpu_entry
-- 
2.1.4

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[U-Boot] [PATCH v5 3/8] ARMv7: PSCI: update the place of saving target PC

[macro . wave . z]

From: Hongbo Zhang 

The legacy code saves target PC at stack top, this patch changes it to stack
bottom, because we will save more contents for PSCI v1.0, by this way we don't
need to adjust the stack pointer when more contents are saved.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/psci.S   | 9 +
 arch/arm/include/asm/psci.h | 4 
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 3b92f1d..5b235df 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -259,7 +259,8 @@ ENTRY(psci_cpu_on_common)
 
mov r0, r1
bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   str r2, [r0]@ store target PC at stack top
+   sub r5, r0, #PSCI_TARGET_PC_OFFSET
+   str r2, [r5]@ store target PC
dsb
 
pop {pc}
@@ -286,14 +287,13 @@ ENDPROC(psci_cpu_off_common)
 
 @ expects CPU ID in r0 and returns stack top in r0
 ENTRY(psci_get_cpu_stack_top)
-   mov r5, #0x400  @ 1kB of stack per CPU
+   mov r5, #PSCI_PERCPU_STACK_SIZE @ 1kB of stack per CPU
mul r0, r0, r5
 
ldr r5, =psci_text_end  @ end of monitor text
add r5, r5, #0x2000 @ Skip two pages
lsr r5, r5, #12 @ Align to start of page
lsl r5, r5, #12
-   sub r5, r5, #4  @ reserve 1 word for target PC
sub r0, r5, r0  @ here's our stack!
 
bx  lr
@@ -306,7 +306,8 @@ ENTRY(psci_cpu_entry)
 
bl  psci_get_cpu_id @ CPU ID => r0
bl  psci_get_cpu_stack_top  @ stack top => r0
-   ldr r0, [r0]@ target PC at stack top
+   sub r0, r0, #PSCI_TARGET_PC_OFFSET
+   ldr r0, [r0]@ get target PC
b   _do_nonsec_entry
 ENDPROC(psci_cpu_entry)
 
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 2367ec0..cb08544 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -63,6 +63,10 @@
 #define ARM_PSCI_1_0_FN_STAT_RESIDENCY ARM_PSCI_0_2_FN(16)
 #define ARM_PSCI_1_0_FN_STAT_COUNT ARM_PSCI_0_2_FN(17)
 
+/* size of percpu stack, 1kB */
+#define PSCI_PERCPU_STACK_SIZE 0x400
+#define PSCI_TARGET_PC_OFFSET  (PSCI_PERCPU_STACK_SIZE - 4)
+
 #ifndef __ASSEMBLY__
 int psci_update_dt(void *fdt);
 void psci_board_init(void);
-- 
2.1.4

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[U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support

[macro . wave . z]

From: Hongbo Zhang 

v5 changes:
- Give up fixing the potential bug of PSCI stack overlap with secure text end
when there is more CPUs in system. Because I just want to keep this series as
simple as it could be: adding basic PSCI v1.0 support and adding more PSCI
v1.0 implements of our platform.
While too compplicated patches in assembly language won't call for effective
reviews, even I think there is potential bug of PSCI stack, let's fix it in
sepetated patch later.
- Move the patch of factoring out psci_cpu_on_common to earlier place 2/8, so
that the following patches can only update the psci_cpu_on_common instead of
touching each platform's psci_cpu_on, this reduces patches size obviously and
make it easier for review.

v4 changes:
- since there is already PSCI v0.2 function IDs definition merged in 5a07abb,
I give up my previous patches 1/11 and 2/11, and move previous 7/11 "ARMv7:
PSCI: add PSCI v1.0 functions skeleton" as current first one 1/9
- accept Andre's comment to add the missed "arm,psci-0,2" into compatible
string

v3 changes:
- patch 3/11, re-init the stack pointer to address like start of page instead
of page end, because for ARM push operation, the stack pointer is encreased
before storing data.
- patch 10/11, delete the previous un-implemented cpu_suspend function for ls1
platform, because there is default blank functions for all those are not
implemented in specific platform.


v2 changes:
- re-organize psci_cpu_on_common, this code should be called by each platform's
psci_cpu_on, should not be a function calling each psci_cpu_on, all related
functions are updated due to this change
- update some registers usage, e.g. if r10 is used without push/pop, u-boot
cannot launch rt-kernel
- update some comments to be clearer, re-organize all patches for easier review
- add patch to check already_on or on_pending for LS102XA

This patch set contains two parts:
ARMv7 PSCI common framework: fix some issues and add v1.0 support
NXP (was Freescale) LS102XA: codes enhancement and add v1.0 implementation
And this patch set was initially created by Dongsheng Wang.

Hongbo Zhang (8):
  ARMv7: PSCI: add PSCI v1.0 functions skeleton
  ARMv7: PSCI: factor out reusable psci_cpu_on_common
  ARMv7: PSCI: update the place of saving target PC
  ARMv7: PSCI: add codes to save context ID for CPU_ON
  ARMv7: PSCI: ls102xa: check target CPU ID before further operations
  ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON
  ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention
  ARMv7: PSCI: ls102xa: move secure text section into OCRAM

 arch/arm/cpu/armv7/ls102xa/psci.S  | 169 +++--
 arch/arm/cpu/armv7/mx7/psci.S  |   5 +-
 arch/arm/cpu/armv7/nonsec_virt.S   |   7 ++
 arch/arm/cpu/armv7/psci.S  |  99 -
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S  |   5 +-
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S  |   5 +-
 arch/arm/cpu/armv7/virt-dt.c   |  10 +-
 arch/arm/include/asm/arch-ls102xa/config.h |   3 +-
 arch/arm/include/asm/psci.h|  31 ++
 arch/arm/mach-tegra/psci.S |   5 +-
 board/freescale/ls1021aqds/Makefile|   1 +
 board/freescale/ls1021aqds/psci.S  |  36 ++
 board/freescale/ls1021atwr/Makefile|   1 +
 board/freescale/ls1021atwr/psci.S  |  28 +
 include/configs/ls1021aqds.h   |   3 +
 include/configs/ls1021atwr.h   |   3 +
 16 files changed, 383 insertions(+), 28 deletions(-)
 create mode 100644 board/freescale/ls1021aqds/psci.S
 create mode 100644 board/freescale/ls1021atwr/psci.S

-- 
2.1.4

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[U-Boot] [PATCH v5 4/8] ARMv7: PSCI: add codes to save context ID for CPU_ON

[macro . wave . z]

From: Hongbo Zhang 

According to latest PSCI specification, the context ID is needed by CPU_ON.
This patch saves context ID to the second lowest address of the stack (next to
where target PC is saved), and restores it to r0 when needed while target CPU
booting up.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/nonsec_virt.S | 7 +++
 arch/arm/cpu/armv7/psci.S| 4 +++-
 arch/arm/include/asm/psci.h  | 1 +
 3 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index b7563ed..6566643 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 .arch_extension sec
 .arch_extension virt
@@ -89,6 +90,12 @@ _secure_monitor:
movne   r4, #0
mcrrne  p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero
 1:
+#ifdef CONFIG_ARMV7_PSCI
+   bl  psci_get_cpu_id
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
+   ldr r0, [r0]@ get Context ID in r0
+#endif
mov lr, ip
mov ip, #(F_BIT | I_BIT | A_BIT)@ Set A, I and F
tst lr, #1  @ Check for Thumb PC
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 5b235df..3ba9e51 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -253,7 +253,7 @@ ENTRY(psci_enable_smp)
 ENDPROC(psci_enable_smp)
 .weak psci_enable_smp
 
-/* expects target CPU in r1, target PC in r2 */
+/* expects target CPU in r1, target PC in r2, target conetxt ID in r3 */
 ENTRY(psci_cpu_on_common)
push{lr}
 
@@ -261,6 +261,8 @@ ENTRY(psci_cpu_on_common)
bl  psci_get_cpu_stack_top  @ get stack top of target CPU
sub r5, r0, #PSCI_TARGET_PC_OFFSET
str r2, [r5]@ store target PC
+   sub r5, r0, #PSCI_CONTEXT_ID_OFFSET
+   str r3, [r5]@ store target context ID
dsb
 
pop {pc}
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index cb08544..bedcd30 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -66,6 +66,7 @@
 /* size of percpu stack, 1kB */
 #define PSCI_PERCPU_STACK_SIZE 0x400
 #define PSCI_TARGET_PC_OFFSET  (PSCI_PERCPU_STACK_SIZE - 4)
+#define PSCI_CONTEXT_ID_OFFSET (PSCI_PERCPU_STACK_SIZE - 8)
 
 #ifndef __ASSEMBLY__
 int psci_update_dt(void *fdt);
-- 
2.1.4

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[U-Boot] [PATCH v5 8/8] ARMv7: PSCI: ls102xa: move secure text section into OCRAM

[macro . wave . z]

From: Hongbo Zhang 

LS1021 offers two secure OCRAM blocks for trustzone.
This patch moves all the secure text sections into the OCRAM.

Signed-off-by: Wang Dongsheng 
Signed-off-by: Hongbo Zhang 
---
 arch/arm/include/asm/arch-ls102xa/config.h | 2 +-
 include/configs/ls1021atwr.h   | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index 7a0e4bf..4729044 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -10,7 +10,7 @@
 #define CONFIG_SYS_CACHELINE_SIZE  64
 
 #define OCRAM_BASE_ADDR0x1000
-#define OCRAM_SIZE 0x0002
+#define OCRAM_SIZE 0x0001
 #define OCRAM_BASE_S_ADDR  0x1001
 #define OCRAM_S_SIZE   0x0001
 
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 9d0c4fe..e6fbd77 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -12,6 +12,8 @@
 #define CONFIG_ARMV7_PSCI
 #define CONFIG_ARMV7_PSCI_1_0
 
+#define CONFIG_ARMV7_SECURE_BASE   OCRAM_BASE_S_ADDR
+
 #define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_DISPLAY_CPUINFO
-- 
2.1.4

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[U-Boot] [PATCH v5 7/8] ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention

[macro . wave . z]

From: Hongbo Zhang 

This patch implements PSCI functions for ls102xa SoC following PSCI v1.0,
they are as the list:
psci_version,
psci_features,
psci_cpu_suspend,
psci_affinity_info,
psci_system_reset,
psci_system_off.

Tested on LS1021aQDS, LS1021aTWR.

Signed-off-by: Wang Dongsheng 
Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv7/ls102xa/psci.S  | 105 +++--
 arch/arm/include/asm/arch-ls102xa/config.h |   1 +
 arch/arm/include/asm/psci.h|   5 ++
 board/freescale/ls1021aqds/Makefile|   1 +
 board/freescale/ls1021aqds/psci.S  |  36 ++
 board/freescale/ls1021atwr/Makefile|   1 +
 board/freescale/ls1021atwr/psci.S  |  28 
 include/configs/ls1021aqds.h   |   3 +
 include/configs/ls1021atwr.h   |   1 +
 9 files changed, 177 insertions(+), 4 deletions(-)
 create mode 100644 board/freescale/ls1021aqds/psci.S
 create mode 100644 board/freescale/ls1021atwr/psci.S

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index 0188ade..084f914 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -12,19 +12,72 @@
 #include 
 #include 
 
+#define RCPM_TWAITSR   0x04C
+
 #define SCFG_CORE0_SFT_RST  0x130
 #define SCFG_CORESRENCR 0x204
 
-#define DCFG_CCSR_BRR   0x0E4
-#define DCFG_CCSR_SCRATCHRW10x200
+#define DCFG_CCSR_RSTCR0x0B0
+#define DCFG_CCSR_RSTCR_RESET_REQ  0x2
+#define DCFG_CCSR_BRR  0x0E4
+#define DCFG_CCSR_SCRATCHRW1   0x200
+
+#define PSCI_FN_PSCI_VERSION_FEATURE_MASK  0x0
+#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK   0x0
+#define PSCI_FN_CPU_OFF_FEATURE_MASK   0x0
+#define PSCI_FN_CPU_ON_FEATURE_MASK0x0
+#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0
+#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK0x0
+#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK  0x0
 
.pushsection ._secure.text, "ax"
 
.arch_extension sec
 
+   .align  5
+
 #defineONE_MS  (GENERIC_TIMER_CLK / 1000)
 #defineRESET_WAIT  (30 * ONE_MS)
 
+.globl psci_version
+psci_version:
+   movwr0, #0
+   movtr0, #1
+
+   bx  lr
+
+_ls102x_psci_supported_table:
+   .word   ARM_PSCI_0_2_FN_PSCI_VERSION
+   .word   PSCI_FN_PSCI_VERSION_FEATURE_MASK
+   .word   ARM_PSCI_0_2_FN_CPU_SUSPEND
+   .word   PSCI_FN_CPU_SUSPEND_FEATURE_MASK
+   .word   ARM_PSCI_0_2_FN_CPU_OFF
+   .word   PSCI_FN_CPU_OFF_FEATURE_MASK
+   .word   ARM_PSCI_0_2_FN_CPU_ON
+   .word   PSCI_FN_CPU_ON_FEATURE_MASK
+   .word   ARM_PSCI_0_2_FN_AFFINITY_INFO
+   .word   PSCI_FN_AFFINITY_INFO_FEATURE_MASK
+   .word   ARM_PSCI_0_2_FN_SYSTEM_OFF
+   .word   PSCI_FN_SYSTEM_OFF_FEATURE_MASK
+   .word   ARM_PSCI_0_2_FN_SYSTEM_RESET
+   .word   PSCI_FN_SYSTEM_RESET_FEATURE_MASK
+   .word   0
+   .word   ARM_PSCI_RET_NI
+
+.globl psci_features
+psci_features:
+   adr r2, _ls102x_psci_supported_table
+1: ldr r3, [r2]
+   cmp r3, #0
+   beq out_psci_features
+   cmp r1, r3
+   addne   r2, r2, #8
+   bne 1b
+
+out_psci_features:
+   ldr r0, [r2, #4]
+   bx  lr
+
 .globl psci_check_target_cpu_id
 psci_check_target_cpu_id:
@ Get the real CPU number
@@ -169,6 +222,52 @@ psci_cpu_off:
 1: wfi
b   1b
 
+.globl psci_affinity_info
+psci_affinity_info:
+   push{lr}
+
+   mov r0, #ARM_PSCI_RET_INVAL
+
+   @ Verify Affinity level
+   cmp r2, #0
+   bne out_affinity_info
+
+   bl  psci_check_target_cpu_id
+   cmp r0, #ARM_PSCI_RET_INVAL
+   beq out_affinity_info
+   mov r1, r0
+
+   @ Get RCPM base address
+   movwr4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0x)
+   movtr4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
+
+   mov r0, #PSCI_AFFINITY_LEVEL_ON
+
+   @ Detect target CPU state
+   ldr r2, [r4, #RCPM_TWAITSR]
+   rev r2, r2
+   lsr r2, r2, r1
+   andsr2, r2, #1
+   beq out_affinity_info
+
+   mov r0, #PSCI_AFFINITY_LEVEL_OFF
+
+out_affinity_info:
+   pop {pc}
+
+.globl psci_system_reset
+psci_system_reset:
+   @ Get DCFG base address
+   movwr1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0x)
+   movtr1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+
+   mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
+   rev r2, r2
+   str r2, [r1, #DCFG_CCSR_RSTCR]
+
+1: wfi
+   b   1b
+
 .globl psci_arch_init
 psci_arch_init:
mov r6, lr
@@ -179,6 +278,4 @@ psci_arch_init:
 
bx  r6
 
-   .globl psci_text_end
-psci_text_end:
.popsection
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 

[U-Boot] [PATCH v5 6/8] ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON

[macro . wave . z]

From: Hongbo Zhang 

For the robustness of codes, while powering on a CPU, it is better to check
if the target CPU is already on or in the process of power on, if yes the
power on routine shouldn't be executed further and should return with the
corresponding status immediately.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv7/ls102xa/psci.S | 29 +
 arch/arm/include/asm/psci.h   |  5 +
 2 files changed, 34 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index a4482e4..0188ade 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -66,6 +66,22 @@ psci_cpu_on:
beq out_psci_cpu_on
mov r1, r0
 
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CPU_STATUS_OFFSET
+   ldr r5, [r0]
+
+   cmp r5, #PSCI_CPU_STATUS_ON
+   moveq   r0, #ARM_PSCI_RET_ALREADY_ON
+   beq out_psci_cpu_on
+
+   cmp r5, #PSCI_CPU_STATUS_ON_PENDING
+   moveq   r0, #ARM_PSCI_RET_ON_PENDING
+   beq out_psci_cpu_on
+
+   mov r5, #PSCI_CPU_STATUS_ON_PENDING
+   str r5, [r0]
+   dsb
+
bl  psci_cpu_on_common
 
@ Get DCFG base address
@@ -123,6 +139,12 @@ holdoff_release:
rev r6, r6
str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
 
+   mov r0, r1
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CPU_STATUS_OFFSET
+   mov r5, #PSCI_CPU_STATUS_ON
+   str r5, [r0]
+
isb
dsb
 
@@ -137,6 +159,13 @@ out_psci_cpu_on:
 psci_cpu_off:
bl  psci_cpu_off_common
 
+   bl  psci_get_cpu_id
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CPU_STATUS_OFFSET
+   mov r5, #PSCI_CPU_STATUS_OFF
+   str r5, [r0]
+   dsb
+
 1: wfi
b   1b
 
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index bedcd30..89a1ba5 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -67,6 +67,11 @@
 #define PSCI_PERCPU_STACK_SIZE 0x400
 #define PSCI_TARGET_PC_OFFSET  (PSCI_PERCPU_STACK_SIZE - 4)
 #define PSCI_CONTEXT_ID_OFFSET (PSCI_PERCPU_STACK_SIZE - 8)
+#define PSCI_CPU_STATUS_OFFSET (PSCI_PERCPU_STACK_SIZE - 12)
+
+#define PSCI_CPU_STATUS_OFF0
+#define PSCI_CPU_STATUS_ON 1
+#define PSCI_CPU_STATUS_ON_PENDING 2
 
 #ifndef __ASSEMBLY__
 int psci_update_dt(void *fdt);
-- 
2.1.4

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[U-Boot] [PATCH v5 5/8] ARMv7: PSCI: ls102xa: check target CPU ID before further operations

[macro . wave . z]

From: Hongbo Zhang 

The input parameter CPU ID needs to be validated before furher oprations such
as CPU_ON, this patch introduces the function to do this.

Signed-off-by: Wang Dongsheng 
Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv7/ls102xa/psci.S | 34 +-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index 548c507..a4482e4 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -25,6 +25,34 @@
 #defineONE_MS  (GENERIC_TIMER_CLK / 1000)
 #defineRESET_WAIT  (30 * ONE_MS)
 
+.globl psci_check_target_cpu_id
+psci_check_target_cpu_id:
+   @ Get the real CPU number
+   and r0, r1, #0xff
+
+   @ Verify bit[31:24], bits must be zero.
+   tst r1, #0xff00
+   bne out_psci_invalid_target_cpu_id
+
+   @ Verify Affinity level 2: Cluster, only one cluster in LS1021xa SoC.
+   tst r1, #0xff
+   bne out_psci_invalid_target_cpu_id
+
+   @ Verify Affinity level 1: Processors, should be in 0xf00 format.
+   lsr r1, r1, #8
+   teq r1, #0xf
+   bne out_psci_invalid_target_cpu_id
+
+   @ Verify Affinity level 0: CPU, only 0, 1 are valid values.
+   cmp r0, #2
+   bge out_psci_invalid_target_cpu_id
+
+   bx  lr
+
+out_psci_invalid_target_cpu_id:
+   mov r0, #ARM_PSCI_RET_INVAL
+   bx  lr
+
@ r1 = target CPU
@ r2 = target PC
 .globl psci_cpu_on
@@ -33,7 +61,10 @@ psci_cpu_on:
 
@ Clear and Get the correct CPU number
@ r1 = 0xf01
-   and r1, r1, #0xff
+   bl  psci_check_target_cpu_id
+   cmp r0, #ARM_PSCI_RET_INVAL
+   beq out_psci_cpu_on
+   mov r1, r0
 
bl  psci_cpu_on_common
 
@@ -98,6 +129,7 @@ holdoff_release:
@ Return
mov r0, #ARM_PSCI_RET_SUCCESS
 
+out_psci_cpu_on:
pop {lr}
bx  lr
 
-- 
2.1.4

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[U-Boot] [PATCH v5 1/8] ARMv7: PSCI: add PSCI v1.0 functions skeleton

[macro . wave . z]

From: Hongbo Zhang 

This patch adds all the PSCI v1.0 functions in to the common framework, with
all the functions returning "not implemented" by default, as a common framework
all the dummy functions are added here, it is up to every platform developer to
decide which version of PSCI and which functions to implement.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/psci.S| 78 
 arch/arm/cpu/armv7/virt-dt.c | 10 +-
 arch/arm/include/asm/psci.h  | 16 +
 3 files changed, 103 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 87c0c0b..8e25300 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -46,20 +46,62 @@ ENTRY(default_psci_vector)
 ENDPROC(default_psci_vector)
 .weak default_psci_vector
 
+ENTRY(psci_version)
 ENTRY(psci_cpu_suspend)
 ENTRY(psci_cpu_off)
 ENTRY(psci_cpu_on)
+ENTRY(psci_affinity_info)
 ENTRY(psci_migrate)
+ENTRY(psci_migrate_info_type)
+ENTRY(psci_migrate_info_up_cpu)
+ENTRY(psci_system_off)
+ENTRY(psci_system_reset)
+ENTRY(psci_features)
+ENTRY(psci_cpu_freeze)
+ENTRY(psci_cpu_default_suspend)
+ENTRY(psci_node_hw_state)
+ENTRY(psci_system_suspend)
+ENTRY(psci_set_suspend_mode)
+ENTRY(psi_stat_residency)
+ENTRY(psci_stat_count)
mov r0, #ARM_PSCI_RET_NI@ Return -1 (Not Implemented)
mov pc, lr
+ENDPROC(psci_stat_count)
+ENDPROC(psi_stat_residency)
+ENDPROC(psci_set_suspend_mode)
+ENDPROC(psci_system_suspend)
+ENDPROC(psci_node_hw_state)
+ENDPROC(psci_cpu_default_suspend)
+ENDPROC(psci_cpu_freeze)
+ENDPROC(psci_features)
+ENDPROC(psci_system_reset)
+ENDPROC(psci_system_off)
+ENDPROC(psci_migrate_info_up_cpu)
+ENDPROC(psci_migrate_info_type)
 ENDPROC(psci_migrate)
+ENDPROC(psci_affinity_info)
 ENDPROC(psci_cpu_on)
 ENDPROC(psci_cpu_off)
 ENDPROC(psci_cpu_suspend)
+ENDPROC(psci_version)
+.weak psci_version
 .weak psci_cpu_suspend
 .weak psci_cpu_off
 .weak psci_cpu_on
+.weak psci_affinity_info
 .weak psci_migrate
+.weak psci_migrate_info_type
+.weak psci_migrate_info_up_cpu
+.weak psci_system_off
+.weak psci_system_reset
+.weak psci_features
+.weak psci_cpu_freeze
+.weak psci_cpu_default_suspend
+.weak psci_node_hw_state
+.weak psci_system_suspend
+.weak psci_set_suspend_mode
+.weak psi_stat_residency
+.weak psci_stat_count
 
 _psci_table:
.word   ARM_PSCI_FN_CPU_SUSPEND
@@ -70,6 +112,42 @@ _psci_table:
.word   psci_cpu_on
.word   ARM_PSCI_FN_MIGRATE
.word   psci_migrate
+   .word   ARM_PSCI_0_2_FN_PSCI_VERSION
+   .word   psci_version
+   .word   ARM_PSCI_0_2_FN_CPU_SUSPEND
+   .word   psci_cpu_suspend
+   .word   ARM_PSCI_0_2_FN_CPU_OFF
+   .word   psci_cpu_off
+   .word   ARM_PSCI_0_2_FN_CPU_ON
+   .word   psci_cpu_on
+   .word   ARM_PSCI_0_2_FN_AFFINITY_INFO
+   .word   psci_affinity_info
+   .word   ARM_PSCI_0_2_FN_MIGRATE
+   .word   psci_migrate
+   .word   ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE
+   .word   psci_migrate_info_type
+   .word   ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU
+   .word   psci_migrate_info_up_cpu
+   .word   ARM_PSCI_0_2_FN_SYSTEM_OFF
+   .word   psci_system_off
+   .word   ARM_PSCI_0_2_FN_SYSTEM_RESET
+   .word   psci_system_reset
+   .word   ARM_PSCI_1_0_FN_PSCI_FEATURES
+   .word   psci_features
+   .word   ARM_PSCI_1_0_FN_CPU_FREEZE
+   .word   psci_cpu_freeze
+   .word   ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND
+   .word   psci_cpu_default_suspend
+   .word   ARM_PSCI_1_0_FN_NODE_HW_STATE
+   .word   psci_node_hw_state
+   .word   ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
+   .word   psci_system_suspend
+   .word   ARM_PSCI_1_0_FN_SET_SUSPEND_MODE
+   .word   psci_set_suspend_mode
+   .word   ARM_PSCI_1_0_FN_STAT_RESIDENCY
+   .word   psi_stat_residency
+   .word   ARM_PSCI_1_0_FN_STAT_COUNT
+   .word   psci_stat_count
.word   0
.word   0
 
diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
index 32c368f..5e31891 100644
--- a/arch/arm/cpu/armv7/virt-dt.c
+++ b/arch/arm/cpu/armv7/virt-dt.c
@@ -67,7 +67,15 @@ static int fdt_psci(void *fdt)
return nodeoff;
}
 
-   tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci");
+#ifdef CONFIG_ARMV7_PSCI_1_0
+   tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci-1.0");
+   if (tmp)
+   return tmp;
+   tmp = fdt_appendprop_string(fdt, nodeoff, "compatible", "arm,psci-0.2");
+   if (tmp)
+   return tmp;
+#endif
+   tmp = fdt_appendprop_string(fdt, nodeoff, "compatible", "arm,psci");
if (tmp)
return tmp;
tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc");
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 

[U-Boot] [PATCH v4 9/9] ARMv7: PSCI: ls102xa: move secure text section into OCRAM

[macro . wave . z]

From: Hongbo Zhang 

LS1021 offers two secure OCRAM blocks for trustzone.
This patch moves all the secure text sections into the OCRAM.

Signed-off-by: Wang Dongsheng 
Signed-off-by: Hongbo Zhang 
---
 arch/arm/include/asm/arch-ls102xa/config.h | 2 +-
 include/configs/ls1021atwr.h   | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index 7a0e4bf..4729044 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -10,7 +10,7 @@
 #define CONFIG_SYS_CACHELINE_SIZE  64
 
 #define OCRAM_BASE_ADDR0x1000
-#define OCRAM_SIZE 0x0002
+#define OCRAM_SIZE 0x0001
 #define OCRAM_BASE_S_ADDR  0x1001
 #define OCRAM_S_SIZE   0x0001
 
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index ea655c8..bdbd1fc 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -12,6 +12,8 @@
 #define CONFIG_ARMV7_PSCI
 #define CONFIG_ARMV7_PSCI_1_0
 
+#define CONFIG_ARMV7_SECURE_BASE   OCRAM_BASE_S_ADDR
+
 #define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_DISPLAY_CPUINFO
-- 
2.1.4

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[U-Boot] [PATCH v4 6/9] ARMv7: PSCI: ls102xa: check target CPU ID before further operations

[macro . wave . z]

From: Hongbo Zhang 

The input parameter CPU ID needs to be validated before furher oprations such
as CPU_ON, this patch introduces the function to do this.

Signed-off-by: Wang Dongsheng 
Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv7/ls102xa/psci.S | 34 +-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index 973a489..4540bb1 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -25,6 +25,34 @@
 #defineONE_MS  (GENERIC_TIMER_CLK / 1000)
 #defineRESET_WAIT  (30 * ONE_MS)
 
+.globl psci_check_target_cpu_id
+psci_check_target_cpu_id:
+   @ Get the real CPU number
+   and r0, r1, #0xff
+
+   @ Verify bit[31:24], bits must be zero.
+   tst r1, #0xff00
+   bne out_psci_invalid_target_cpu_id
+
+   @ Verify Affinity level 2: Cluster, only one cluster in LS1021xa SoC.
+   tst r1, #0xff
+   bne out_psci_invalid_target_cpu_id
+
+   @ Verify Affinity level 1: Processors, should be in 0xf00 format.
+   lsr r1, r1, #8
+   teq r1, #0xf
+   bne out_psci_invalid_target_cpu_id
+
+   @ Verify Affinity level 0: CPU, only 0, 1 are valid values.
+   cmp r0, #2
+   bge out_psci_invalid_target_cpu_id
+
+   bx  lr
+
+out_psci_invalid_target_cpu_id:
+   mov r0, #ARM_PSCI_RET_INVAL
+   bx  lr
+
@ r1 = target CPU
@ r2 = target PC
@ r3 = target Conetxt ID
@@ -34,7 +62,10 @@ psci_cpu_on:
 
@ Clear and Get the correct CPU number
@ r1 = 0xf01
-   and r1, r1, #0xff
+   bl  psci_check_target_cpu_id
+   cmp r0, #ARM_PSCI_RET_INVAL
+   beq out_psci_cpu_on
+   mov r1, r0
 
bl  psci_cpu_on_common
 
@@ -99,6 +130,7 @@ holdoff_release:
@ Return
mov r0, #ARM_PSCI_RET_SUCCESS
 
+out_psci_cpu_on:
pop {lr}
bx  lr
 
-- 
2.1.4

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[U-Boot] [PATCH v4 7/9] ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON

[macro . wave . z]

From: Hongbo Zhang 

For the robustness of codes, while powering on a CPU, it is better to check
if the target CPU is already on or in the process of power on, if yes the
power on routine shouldn't be executed further and should return with the
corresponding status immediately.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv7/ls102xa/psci.S | 29 +
 arch/arm/include/asm/psci.h   |  5 +
 2 files changed, 34 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index 4540bb1..46fa68c 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -67,6 +67,22 @@ psci_cpu_on:
beq out_psci_cpu_on
mov r1, r0
 
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CPU_STATUS_OFFSET
+   ldr r5, [r0]
+
+   cmp r5, #PSCI_CPU_STATUS_ON
+   moveq   r0, #ARM_PSCI_RET_ALREADY_ON
+   beq out_psci_cpu_on
+
+   cmp r5, #PSCI_CPU_STATUS_ON_PENDING
+   moveq   r0, #ARM_PSCI_RET_ON_PENDING
+   beq out_psci_cpu_on
+
+   mov r5, #PSCI_CPU_STATUS_ON_PENDING
+   str r5, [r0]
+   dsb
+
bl  psci_cpu_on_common
 
@ Get DCFG base address
@@ -124,6 +140,12 @@ holdoff_release:
rev r6, r6
str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
 
+   mov r0, r1
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CPU_STATUS_OFFSET
+   mov r5, #PSCI_CPU_STATUS_ON
+   str r5, [r0]
+
isb
dsb
 
@@ -138,6 +160,13 @@ out_psci_cpu_on:
 psci_cpu_off:
bl  psci_cpu_off_common
 
+   bl  psci_get_cpu_id
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CPU_STATUS_OFFSET
+   mov r5, #PSCI_CPU_STATUS_OFF
+   str r5, [r0]
+   dsb
+
 1: wfi
b   1b
 
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index bedcd30..89a1ba5 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -67,6 +67,11 @@
 #define PSCI_PERCPU_STACK_SIZE 0x400
 #define PSCI_TARGET_PC_OFFSET  (PSCI_PERCPU_STACK_SIZE - 4)
 #define PSCI_CONTEXT_ID_OFFSET (PSCI_PERCPU_STACK_SIZE - 8)
+#define PSCI_CPU_STATUS_OFFSET (PSCI_PERCPU_STACK_SIZE - 12)
+
+#define PSCI_CPU_STATUS_OFF0
+#define PSCI_CPU_STATUS_ON 1
+#define PSCI_CPU_STATUS_ON_PENDING 2
 
 #ifndef __ASSEMBLY__
 int psci_update_dt(void *fdt);
-- 
2.1.4

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[U-Boot] [PATCH v4 8/9] ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention

[macro . wave . z]

From: Hongbo Zhang 

This patch implements PSCI functions for ls102xa SoC following PSCI v1.0,
they are as the list:
psci_version,
psci_features,
psci_cpu_suspend,
psci_affinity_info,
psci_system_reset,
psci_system_off.

Tested on LS1021aQDS, LS1021aTWR.

Signed-off-by: Wang Dongsheng 
Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv7/ls102xa/psci.S  | 105 +++--
 arch/arm/include/asm/arch-ls102xa/config.h |   1 +
 arch/arm/include/asm/psci.h|   5 ++
 board/freescale/ls1021aqds/Makefile|   1 +
 board/freescale/ls1021aqds/psci.S  |  36 ++
 board/freescale/ls1021atwr/Makefile|   1 +
 board/freescale/ls1021atwr/psci.S  |  28 
 include/configs/ls1021aqds.h   |   3 +
 include/configs/ls1021atwr.h   |   1 +
 9 files changed, 177 insertions(+), 4 deletions(-)
 create mode 100644 board/freescale/ls1021aqds/psci.S
 create mode 100644 board/freescale/ls1021atwr/psci.S

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index 46fa68c..e480671 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -12,19 +12,72 @@
 #include 
 #include 
 
+#define RCPM_TWAITSR   0x04C
+
 #define SCFG_CORE0_SFT_RST  0x130
 #define SCFG_CORESRENCR 0x204
 
-#define DCFG_CCSR_BRR   0x0E4
-#define DCFG_CCSR_SCRATCHRW10x200
+#define DCFG_CCSR_RSTCR0x0B0
+#define DCFG_CCSR_RSTCR_RESET_REQ  0x2
+#define DCFG_CCSR_BRR  0x0E4
+#define DCFG_CCSR_SCRATCHRW1   0x200
+
+#define PSCI_FN_PSCI_VERSION_FEATURE_MASK  0x0
+#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK   0x0
+#define PSCI_FN_CPU_OFF_FEATURE_MASK   0x0
+#define PSCI_FN_CPU_ON_FEATURE_MASK0x0
+#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0
+#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK0x0
+#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK  0x0
 
.pushsection ._secure.text, "ax"
 
.arch_extension sec
 
+   .align  5
+
 #defineONE_MS  (GENERIC_TIMER_CLK / 1000)
 #defineRESET_WAIT  (30 * ONE_MS)
 
+.globl psci_version
+psci_version:
+   movwr0, #0
+   movtr0, #1
+
+   bx  lr
+
+_ls102x_psci_supported_table:
+   .word   ARM_PSCI_0_2_FN_PSCI_VERSION
+   .word   PSCI_FN_PSCI_VERSION_FEATURE_MASK
+   .word   ARM_PSCI_0_2_FN_CPU_SUSPEND
+   .word   PSCI_FN_CPU_SUSPEND_FEATURE_MASK
+   .word   ARM_PSCI_0_2_FN_CPU_OFF
+   .word   PSCI_FN_CPU_OFF_FEATURE_MASK
+   .word   ARM_PSCI_0_2_FN_CPU_ON
+   .word   PSCI_FN_CPU_ON_FEATURE_MASK
+   .word   ARM_PSCI_0_2_FN_AFFINITY_INFO
+   .word   PSCI_FN_AFFINITY_INFO_FEATURE_MASK
+   .word   ARM_PSCI_0_2_FN_SYSTEM_OFF
+   .word   PSCI_FN_SYSTEM_OFF_FEATURE_MASK
+   .word   ARM_PSCI_0_2_FN_SYSTEM_RESET
+   .word   PSCI_FN_SYSTEM_RESET_FEATURE_MASK
+   .word   0
+   .word   ARM_PSCI_RET_NI
+
+.globl psci_features
+psci_features:
+   adr r2, _ls102x_psci_supported_table
+1: ldr r3, [r2]
+   cmp r3, #0
+   beq out_psci_features
+   cmp r1, r3
+   addne   r2, r2, #8
+   bne 1b
+
+out_psci_features:
+   ldr r0, [r2, #4]
+   bx  lr
+
 .globl psci_check_target_cpu_id
 psci_check_target_cpu_id:
@ Get the real CPU number
@@ -170,6 +223,52 @@ psci_cpu_off:
 1: wfi
b   1b
 
+.globl psci_affinity_info
+psci_affinity_info:
+   push{lr}
+
+   mov r0, #ARM_PSCI_RET_INVAL
+
+   @ Verify Affinity level
+   cmp r2, #0
+   bne out_affinity_info
+
+   bl  psci_check_target_cpu_id
+   cmp r0, #ARM_PSCI_RET_INVAL
+   beq out_affinity_info
+   mov r1, r0
+
+   @ Get RCPM base address
+   movwr4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0x)
+   movtr4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
+
+   mov r0, #PSCI_AFFINITY_LEVEL_ON
+
+   @ Detect target CPU state
+   ldr r2, [r4, #RCPM_TWAITSR]
+   rev r2, r2
+   lsr r2, r2, r1
+   andsr2, r2, #1
+   beq out_affinity_info
+
+   mov r0, #PSCI_AFFINITY_LEVEL_OFF
+
+out_affinity_info:
+   pop {pc}
+
+.globl psci_system_reset
+psci_system_reset:
+   @ Get DCFG base address
+   movwr1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0x)
+   movtr1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+
+   mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
+   rev r2, r2
+   str r2, [r1, #DCFG_CCSR_RSTCR]
+
+1: wfi
+   b   1b
+
 .globl psci_arch_init
 psci_arch_init:
mov r6, lr
@@ -180,6 +279,4 @@ psci_arch_init:
 
bx  r6
 
-   .globl psci_text_end
-psci_text_end:
.popsection
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 

[U-Boot] [PATCH v4 5/9] ARMv7: PSCI: factor out reusable psci_cpu_on_common

[macro . wave . z]

From: Hongbo Zhang 

There are codes for saving target PC and target context ID in each platform
psci_cpu_on routines, these can be factored out as psci_cpu_on_common.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/ls102xa/psci.S | 12 +---
 arch/arm/cpu/armv7/mx7/psci.S | 12 +---
 arch/arm/cpu/armv7/psci.S | 15 +++
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 12 +---
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 13 +
 arch/arm/mach-tegra/psci.S| 12 +---
 6 files changed, 20 insertions(+), 56 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index 14d232a..973a489 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -36,17 +36,7 @@ psci_cpu_on:
@ r1 = 0xf01
and r1, r1, #0xff
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   sub r0, r0, #PSCI_TARGET_PC_OFFSET
-   str r2, [r0]
-   dsb
-
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
-   str r3, [r0]
-   dsb
+   bl  psci_cpu_on_common
 
@ Get DCFG base address
movwr4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0x)
diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S
index 90b8b9e..c9a7b00 100644
--- a/arch/arm/cpu/armv7/mx7/psci.S
+++ b/arch/arm/cpu/armv7/mx7/psci.S
@@ -29,17 +29,7 @@ psci_arch_init:
 psci_cpu_on:
push{lr}
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   sub r0, r0, #PSCI_TARGET_PC_OFFSET
-   str r2, [r0]
-   dsb
-
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
-   str r3, [r0]
-   dsb
+   bl  psci_cpu_on_common
 
ldr r2, =psci_cpu_entry
bl  imx_cpu_on
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 14ffc85..c347ab8 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -253,6 +253,21 @@ ENTRY(psci_enable_smp)
 ENDPROC(psci_enable_smp)
 .weak psci_enable_smp
 
+/* expects target CPU in r1, target PC in r2, target conetxt ID in r3 */
+ENTRY(psci_cpu_on_common)
+   push{lr}
+
+   mov r0, r1
+   bl  psci_get_cpu_stack_top  @ get stack top of target CPU
+   sub r5, r0, #PSCI_TARGET_PC_OFFSET
+   str r2, [r5]@ save target PC
+   sub r5, r0, #PSCI_CONTEXT_ID_OFFSET
+   str r3, [r5]@ save target context ID
+   dsb
+
+   pop {pc}
+ENDPROC(psci_cpu_on_common)
+
 ENTRY(psci_cpu_off_common)
push{lr}
 
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 6860b0a..62452be 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -135,17 +135,7 @@ out:   mcr p15, 0, r7, c1, c1, 0
 psci_cpu_on:
push{lr}
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   sub r0, r0, #PSCI_TARGET_PC_OFFSET
-   str r2, [r0]@ store target PC
-   dsb
-
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
-   str r3, [r0]
-   dsb
+   bl  psci_cpu_on_common
 
movwr0, #(SUN6I_CPUCFG_BASE & 0x)
movtr0, #(SUN6I_CPUCFG_BASE >> 16)
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index 01d5eac..9dc4c6b 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -124,18 +124,7 @@ out:   mcr p15, 0, r7, c1, c1, 0
 psci_cpu_on:
push{lr}
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   sub r0, r0, #PSCI_TARGET_PC_OFFSET
-   str r2, [r0]@ store target PC
-   dsb
-
-
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
-   str r3, [r0]
-   dsb
+   bl  psci_cpu_on_common
 
movwr0, #(SUN7I_CPUCFG_BASE & 0x)
movtr0, #(SUN7I_CPUCFG_BASE >> 16)
diff --git a/arch/arm/mach-tegra/psci.S b/arch/arm/mach-tegra/psci.S
index d87fd72..8a0147c 100644
--- a/arch/arm/mach-tegra/psci.S
+++ b/arch/arm/mach-tegra/psci.S
@@ -90,17 +90,7 @@ ENDPROC(psci_cpu_off)
 ENTRY(psci_cpu_on)
push{lr}
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   sub r0, r0, #PSCI_TARGET_PC_OFFSET
-   str r2, [r0]@ store target PC
-   dsb
-
-   mov r0, r1
-   bl  

[U-Boot] [PATCH v4 4/9] ARMv7: PSCI: add codes to save context ID for CPU_ON

[macro . wave . z]

From: Hongbo Zhang 

According to latest PSCI specification, the context ID is needed by CPU_ON.
This patch saves context ID to the second lowest address of the stack (next to
where target PC is saved), and restores it to r0 when needed while target CPU
booting up.

This patch in current format is for easier review, there are some lines
duplication with previous saving target PC codes, e.g. codes of calling the
psci_get_cpu_stack_top, this will be optimized by the following patch.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/ls102xa/psci.S | 7 +++
 arch/arm/cpu/armv7/mx7/psci.S | 8 +++-
 arch/arm/cpu/armv7/nonsec_virt.S  | 7 +++
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 7 +++
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 8 
 arch/arm/include/asm/psci.h   | 1 +
 arch/arm/mach-tegra/psci.S| 6 ++
 7 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index 988a1d2..14d232a 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -27,6 +27,7 @@
 
@ r1 = target CPU
@ r2 = target PC
+   @ r3 = target Conetxt ID
 .globl psci_cpu_on
 psci_cpu_on:
push{lr}
@@ -41,6 +42,12 @@ psci_cpu_on:
str r2, [r0]
dsb
 
+   mov r0, r1
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
+   str r3, [r0]
+   dsb
+
@ Get DCFG base address
movwr4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0x)
movtr4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S
index 02ca076..90b8b9e 100644
--- a/arch/arm/cpu/armv7/mx7/psci.S
+++ b/arch/arm/cpu/armv7/mx7/psci.S
@@ -24,7 +24,7 @@ psci_arch_init:
 
@ r1 = target CPU
@ r2 = target PC
-
+   @ r3 = target Conetxt ID
 .globl psci_cpu_on
 psci_cpu_on:
push{lr}
@@ -35,6 +35,12 @@ psci_cpu_on:
str r2, [r0]
dsb
 
+   mov r0, r1
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
+   str r3, [r0]
+   dsb
+
ldr r2, =psci_cpu_entry
bl  imx_cpu_on
 
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index b7563ed..6566643 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 .arch_extension sec
 .arch_extension virt
@@ -89,6 +90,12 @@ _secure_monitor:
movne   r4, #0
mcrrne  p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero
 1:
+#ifdef CONFIG_ARMV7_PSCI
+   bl  psci_get_cpu_id
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
+   ldr r0, [r0]@ get Context ID in r0
+#endif
mov lr, ip
mov ip, #(F_BIT | I_BIT | A_BIT)@ Set A, I and F
tst lr, #1  @ Check for Thumb PC
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 930aa7a..6860b0a 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -130,6 +130,7 @@ out:mcr p15, 0, r7, c1, c1, 0
 
@ r1 = target CPU
@ r2 = target PC
+   @ r3 = target Conetxt ID
 .globl psci_cpu_on
 psci_cpu_on:
push{lr}
@@ -140,6 +141,12 @@ psci_cpu_on:
str r2, [r0]@ store target PC
dsb
 
+   mov r0, r1
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
+   str r3, [r0]
+   dsb
+
movwr0, #(SUN6I_CPUCFG_BASE & 0x)
movtr0, #(SUN6I_CPUCFG_BASE >> 16)
 
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index 7fbeac1..01d5eac 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -119,6 +119,7 @@ out:mcr p15, 0, r7, c1, c1, 0
 
@ r1 = target CPU
@ r2 = target PC
+   @ r3 = target Conetxt ID
 .globl psci_cpu_on
 psci_cpu_on:
push{lr}
@@ -129,6 +130,13 @@ psci_cpu_on:
str r2, [r0]@ store target PC
dsb
 
+
+   mov r0, r1
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
+   str r3, [r0]
+   dsb
+
movwr0, #(SUN7I_CPUCFG_BASE & 0x)
movtr0, #(SUN7I_CPUCFG_BASE >> 16)
 
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index cb08544..bedcd30 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -66,6 +66,7 @@
 /* size of percpu stack, 1kB */
 #define PSCI_PERCPU_STACK_SIZE 0x400
 

[U-Boot] [PATCH v4 0/9] ARMv7: PSCI: add PSCI v1.0 support

[macro . wave . z]

From: Hongbo Zhang 

v4 changes:
- since there is already PSCI v0.2 function IDs definition merged in 5a07abb,
I give up my previous patches 1/11 and 2/11, and move previous 7/11 "ARMv7:
PSCI: add PSCI v1.0 functions skeleton" as current first one 1/9
- accept Andre's comment to add the missed "arm,psci-0,2" into compatible
string

v3 changes:
- patch 3/11, re-init the stack pointer to address like start of page instead
of page end, because for ARM push operation, the stack pointer is encreased
before storing data.
- patch 10/11, delete the previous un-implemented cpu_suspend function for ls1
platform, because there is default blank functions for all those are not
implemented in specific platform.


v2 changes:
- re-organize psci_cpu_on_common, this code should be called by each platform's
psci_cpu_on, should not be a function calling each psci_cpu_on, all related
functions are updated due to this change
- update some registers usage, e.g. if r10 is used without push/pop, u-boot
cannot launch rt-kernel
- update some comments to be clearer, re-organize all patches for easier review
- add patch to check already_on or on_pending for LS102XA

This patch set contains two parts:
ARMv7 PSCI common framework: fix some issues and add v1.0 support
NXP (was Freescale) LS102XA: codes enhancement and add v1.0 implementation
And this patch set was initially created by Dongsheng Wang.

Hongbo Zhang (9):
  ARMv7: PSCI: add PSCI v1.0 functions skeleton
  ARMv7: PSCI: update function psci_get_cpu_stack_top
  ARMv7: PSCI: update the place of saving target PC
  ARMv7: PSCI: add codes to save context ID for CPU_ON
  ARMv7: PSCI: factor out reusable psci_cpu_on_common
  ARMv7: PSCI: ls102xa: check target CPU ID before further operations
  ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON
  ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention
  ARMv7: PSCI: ls102xa: move secure text section into OCRAM

 arch/arm/cpu/armv7/ls102xa/psci.S  | 170 +++--
 arch/arm/cpu/armv7/mx7/psci.S  |   7 +-
 arch/arm/cpu/armv7/nonsec_virt.S   |   7 ++
 arch/arm/cpu/armv7/psci.S  | 106 +-
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S  |   6 +-
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S  |   6 +-
 arch/arm/cpu/armv7/virt-dt.c   |  19 +++-
 arch/arm/include/asm/arch-ls102xa/config.h |   3 +-
 arch/arm/include/asm/psci.h|  31 ++
 arch/arm/mach-tegra/psci.S |   5 +-
 board/freescale/ls1021aqds/Makefile|   1 +
 board/freescale/ls1021aqds/psci.S  |  36 ++
 board/freescale/ls1021atwr/Makefile|   1 +
 board/freescale/ls1021atwr/psci.S  |  28 +
 include/configs/ls1021aqds.h   |   3 +
 include/configs/ls1021atwr.h   |   3 +
 16 files changed, 398 insertions(+), 34 deletions(-)
 create mode 100644 board/freescale/ls1021aqds/psci.S
 create mode 100644 board/freescale/ls1021atwr/psci.S

-- 
2.1.4

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[U-Boot] [PATCH v4 3/9] ARMv7: PSCI: update the place of saving target PC

[macro . wave . z]

From: Hongbo Zhang 

The legacy code reserves one word in each stack for saving target PC, but it
isn't used, the target PC is still saved to where the stack top pointer points.
This patch relocates the place for saving target PC to the lowest address of
each stack, convinience is that we can save more contents if needed ilater next
to saved target PC without re-adjust the stack top pointer.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/ls102xa/psci.S | 1 +
 arch/arm/cpu/armv7/mx7/psci.S | 1 +
 arch/arm/cpu/armv7/psci.S | 3 ++-
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 3 ++-
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 3 ++-
 arch/arm/include/asm/psci.h   | 1 +
 arch/arm/mach-tegra/psci.S| 3 ++-
 7 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index cf5cd48..988a1d2 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -37,6 +37,7 @@ psci_cpu_on:
 
mov r0, r1
bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_TARGET_PC_OFFSET
str r2, [r0]
dsb
 
diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S
index 34c6ab3..02ca076 100644
--- a/arch/arm/cpu/armv7/mx7/psci.S
+++ b/arch/arm/cpu/armv7/mx7/psci.S
@@ -31,6 +31,7 @@ psci_cpu_on:
 
mov r0, r1
bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_TARGET_PC_OFFSET
str r2, [r0]
dsb
 
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 91a1dd1..14ffc85 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -294,7 +294,8 @@ ENTRY(psci_cpu_entry)
 
bl  psci_get_cpu_id @ CPU ID => r0
bl  psci_get_cpu_stack_top  @ stack top => r0
-   ldr r0, [r0]@ target PC at stack top
+   sub r0, r0, #PSCI_TARGET_PC_OFFSET
+   ldr r0, [r0]@ get target PC
b   _do_nonsec_entry
 ENDPROC(psci_cpu_entry)
 
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 90b5bfd..930aa7a 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -136,7 +136,8 @@ psci_cpu_on:
 
mov r0, r1
bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   str r2, [r0]@ store target PC at stack top
+   sub r0, r0, #PSCI_TARGET_PC_OFFSET
+   str r2, [r0]@ store target PC
dsb
 
movwr0, #(SUN6I_CPUCFG_BASE & 0x)
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index e15d587..7fbeac1 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -125,7 +125,8 @@ psci_cpu_on:
 
mov r0, r1
bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   str r2, [r0]@ store target PC at stack top
+   sub r0, r0, #PSCI_TARGET_PC_OFFSET
+   str r2, [r0]@ store target PC
dsb
 
movwr0, #(SUN7I_CPUCFG_BASE & 0x)
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 76c3c92..cb08544 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -65,6 +65,7 @@
 
 /* size of percpu stack, 1kB */
 #define PSCI_PERCPU_STACK_SIZE 0x400
+#define PSCI_TARGET_PC_OFFSET  (PSCI_PERCPU_STACK_SIZE - 4)
 
 #ifndef __ASSEMBLY__
 int psci_update_dt(void *fdt);
diff --git a/arch/arm/mach-tegra/psci.S b/arch/arm/mach-tegra/psci.S
index b836da1..a335276 100644
--- a/arch/arm/mach-tegra/psci.S
+++ b/arch/arm/mach-tegra/psci.S
@@ -92,7 +92,8 @@ ENTRY(psci_cpu_on)
 
mov r0, r1
bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   str r2, [r0]@ store target PC at stack top
+   sub r0, r0, #PSCI_TARGET_PC_OFFSET
+   str r2, [r0]@ store target PC
dsb
 
ldr r6, =TEGRA_RESET_EXCEPTION_VECTOR
-- 
2.1.4

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[U-Boot] [PATCH v4 2/9] ARMv7: PSCI: update function psci_get_cpu_stack_top

[macro . wave . z]

From: Hongbo Zhang 

There are issues of legacy fuction psci_get_cpu_stack_top:

First, the current algorithm arranges stacks from an fixed adress towards
psci_text_end, if there are more CPUs, the stacks will overlap with psci text
segment and even other segments.
This patch places stacks from psci text segment towards highter address, and
all the stack space is reserved, so overlap can be avoided.

Second, even there is one word reserved in each stack for saving target PC, but
this reserved space isn't used at all, the target PC is still saved to where
the stack top pointer points.
This patch doesn't reserve this word as before, new way of saving target PC
will be introduced in following patch.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/psci.S| 10 +-
 arch/arm/cpu/armv7/virt-dt.c |  9 +++--
 arch/arm/include/asm/psci.h  |  3 +++
 3 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 8e25300..91a1dd1 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -274,16 +274,16 @@ ENDPROC(psci_cpu_off_common)
 
 @ expects CPU ID in r0 and returns stack top in r0
 ENTRY(psci_get_cpu_stack_top)
-   mov r5, #0x400  @ 1kB of stack per CPU
-   mul r0, r0, r5
+   mov r5, #PSCI_PERCPU_STACK_SIZE @ 1kB of stack per CPU
+   add r0, r0, #1
+   mul r0, r0, r5  @ offset of each stack
 
ldr r5, =psci_text_end  @ end of monitor text
-   add r5, r5, #0x2000 @ Skip two pages
+   add r5, r5, #0x1000 @ Skip one page
lsr r5, r5, #12 @ Align to start of page
lsl r5, r5, #12
-   sub r5, r5, #4  @ reserve 1 word for target PC
-   sub r0, r5, r0  @ here's our stack!
 
+   add r0, r5, r0  @ here's our stack!
bx  lr
 ENDPROC(psci_get_cpu_stack_top)
 
diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
index 5e31891..4fe6f58 100644
--- a/arch/arm/cpu/armv7/virt-dt.c
+++ b/arch/arm/cpu/armv7/virt-dt.c
@@ -127,14 +127,19 @@ int armv7_apply_memory_carveout(u64 *start, u64 *size)
 
 int psci_update_dt(void *fdt)
 {
+   size_t sec_sz = __secure_end - __secure_start;
+#ifdef CONFIG_ARMV7_PSCI
+   sec_sz += CONFIG_MAX_CPUS * PSCI_PERCPU_STACK_SIZE;
+   /* margin to align psci_text_end to page end*/
+   sec_sz += 0x1000;
+#endif
 #ifdef CONFIG_ARMV7_NONSEC
if (!armv7_boot_nonsec())
return 0;
 #endif
 #ifndef CONFIG_ARMV7_SECURE_BASE
/* secure code lives in RAM, keep it alive */
-   fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
-   __secure_end - __secure_start);
+   fdt_add_mem_rsv(fdt, (unsigned long)__secure_start, sec_sz);
 #endif
 
return fdt_psci(fdt);
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 2367ec0..76c3c92 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -63,6 +63,9 @@
 #define ARM_PSCI_1_0_FN_STAT_RESIDENCY ARM_PSCI_0_2_FN(16)
 #define ARM_PSCI_1_0_FN_STAT_COUNT ARM_PSCI_0_2_FN(17)
 
+/* size of percpu stack, 1kB */
+#define PSCI_PERCPU_STACK_SIZE 0x400
+
 #ifndef __ASSEMBLY__
 int psci_update_dt(void *fdt);
 void psci_board_init(void);
-- 
2.1.4

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[U-Boot] [PATCH v4 1/9] ARMv7: PSCI: add PSCI v1.0 functions skeleton

[macro . wave . z]

From: Hongbo Zhang 

This patch adds all the PSCI v1.0 functions in to the common framework, with
all the functions returning "not implemented" by default, as a common framework
all the dummy functions are added here, it is up to every platform developer to
decide which version of PSCI and which functions to implement.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/psci.S| 78 
 arch/arm/cpu/armv7/virt-dt.c | 10 +-
 arch/arm/include/asm/psci.h  | 16 +
 3 files changed, 103 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 87c0c0b..8e25300 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -46,20 +46,62 @@ ENTRY(default_psci_vector)
 ENDPROC(default_psci_vector)
 .weak default_psci_vector
 
+ENTRY(psci_version)
 ENTRY(psci_cpu_suspend)
 ENTRY(psci_cpu_off)
 ENTRY(psci_cpu_on)
+ENTRY(psci_affinity_info)
 ENTRY(psci_migrate)
+ENTRY(psci_migrate_info_type)
+ENTRY(psci_migrate_info_up_cpu)
+ENTRY(psci_system_off)
+ENTRY(psci_system_reset)
+ENTRY(psci_features)
+ENTRY(psci_cpu_freeze)
+ENTRY(psci_cpu_default_suspend)
+ENTRY(psci_node_hw_state)
+ENTRY(psci_system_suspend)
+ENTRY(psci_set_suspend_mode)
+ENTRY(psi_stat_residency)
+ENTRY(psci_stat_count)
mov r0, #ARM_PSCI_RET_NI@ Return -1 (Not Implemented)
mov pc, lr
+ENDPROC(psci_stat_count)
+ENDPROC(psi_stat_residency)
+ENDPROC(psci_set_suspend_mode)
+ENDPROC(psci_system_suspend)
+ENDPROC(psci_node_hw_state)
+ENDPROC(psci_cpu_default_suspend)
+ENDPROC(psci_cpu_freeze)
+ENDPROC(psci_features)
+ENDPROC(psci_system_reset)
+ENDPROC(psci_system_off)
+ENDPROC(psci_migrate_info_up_cpu)
+ENDPROC(psci_migrate_info_type)
 ENDPROC(psci_migrate)
+ENDPROC(psci_affinity_info)
 ENDPROC(psci_cpu_on)
 ENDPROC(psci_cpu_off)
 ENDPROC(psci_cpu_suspend)
+ENDPROC(psci_version)
+.weak psci_version
 .weak psci_cpu_suspend
 .weak psci_cpu_off
 .weak psci_cpu_on
+.weak psci_affinity_info
 .weak psci_migrate
+.weak psci_migrate_info_type
+.weak psci_migrate_info_up_cpu
+.weak psci_system_off
+.weak psci_system_reset
+.weak psci_features
+.weak psci_cpu_freeze
+.weak psci_cpu_default_suspend
+.weak psci_node_hw_state
+.weak psci_system_suspend
+.weak psci_set_suspend_mode
+.weak psi_stat_residency
+.weak psci_stat_count
 
 _psci_table:
.word   ARM_PSCI_FN_CPU_SUSPEND
@@ -70,6 +112,42 @@ _psci_table:
.word   psci_cpu_on
.word   ARM_PSCI_FN_MIGRATE
.word   psci_migrate
+   .word   ARM_PSCI_0_2_FN_PSCI_VERSION
+   .word   psci_version
+   .word   ARM_PSCI_0_2_FN_CPU_SUSPEND
+   .word   psci_cpu_suspend
+   .word   ARM_PSCI_0_2_FN_CPU_OFF
+   .word   psci_cpu_off
+   .word   ARM_PSCI_0_2_FN_CPU_ON
+   .word   psci_cpu_on
+   .word   ARM_PSCI_0_2_FN_AFFINITY_INFO
+   .word   psci_affinity_info
+   .word   ARM_PSCI_0_2_FN_MIGRATE
+   .word   psci_migrate
+   .word   ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE
+   .word   psci_migrate_info_type
+   .word   ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU
+   .word   psci_migrate_info_up_cpu
+   .word   ARM_PSCI_0_2_FN_SYSTEM_OFF
+   .word   psci_system_off
+   .word   ARM_PSCI_0_2_FN_SYSTEM_RESET
+   .word   psci_system_reset
+   .word   ARM_PSCI_1_0_FN_PSCI_FEATURES
+   .word   psci_features
+   .word   ARM_PSCI_1_0_FN_CPU_FREEZE
+   .word   psci_cpu_freeze
+   .word   ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND
+   .word   psci_cpu_default_suspend
+   .word   ARM_PSCI_1_0_FN_NODE_HW_STATE
+   .word   psci_node_hw_state
+   .word   ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
+   .word   psci_system_suspend
+   .word   ARM_PSCI_1_0_FN_SET_SUSPEND_MODE
+   .word   psci_set_suspend_mode
+   .word   ARM_PSCI_1_0_FN_STAT_RESIDENCY
+   .word   psi_stat_residency
+   .word   ARM_PSCI_1_0_FN_STAT_COUNT
+   .word   psci_stat_count
.word   0
.word   0
 
diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
index 32c368f..5e31891 100644
--- a/arch/arm/cpu/armv7/virt-dt.c
+++ b/arch/arm/cpu/armv7/virt-dt.c
@@ -67,7 +67,15 @@ static int fdt_psci(void *fdt)
return nodeoff;
}
 
-   tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci");
+#ifdef CONFIG_ARMV7_PSCI_1_0
+   tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci-1.0");
+   if (tmp)
+   return tmp;
+   tmp = fdt_appendprop_string(fdt, nodeoff, "compatible", "arm,psci-0.2");
+   if (tmp)
+   return tmp;
+#endif
+   tmp = fdt_appendprop_string(fdt, nodeoff, "compatible", "arm,psci");
if (tmp)
return tmp;
tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc");
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 

[U-Boot] [PATCH v3 07/11] ARMv7: PSCI: add PSCI v1.0 functions skeleton

[macro . wave . z]

From: Hongbo Zhang 

This patch adds all the PSCI v1.0 functions in to the common framework, with
all the functions returning "not sopported" by default, as a common framework
all the functions are added here, it is up to every platform developer to
decide which version of PSCI and which functions in it to be implemented.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/psci.S| 70 
 arch/arm/cpu/armv7/virt-dt.c | 45 +---
 arch/arm/include/asm/psci.h  | 21 +
 3 files changed, 125 insertions(+), 11 deletions(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 28579d7..7d27300 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -46,30 +46,100 @@ ENTRY(default_psci_vector)
 ENDPROC(default_psci_vector)
 .weak default_psci_vector
 
+ENTRY(psci_version)
 ENTRY(psci_cpu_suspend)
 ENTRY(psci_cpu_off)
 ENTRY(psci_cpu_on)
+ENTRY(psci_affinity_info)
 ENTRY(psci_migrate)
+ENTRY(psci_migrate_info_type)
+ENTRY(psci_migrate_info_up_cpu)
+ENTRY(psci_system_off)
+ENTRY(psci_system_reset)
+ENTRY(psci_features)
+ENTRY(psci_cpu_freeze)
+ENTRY(psci_cpu_default_suspend)
+ENTRY(psci_node_hw_state)
+ENTRY(psci_system_suspend)
+ENTRY(psci_set_suspend_mode)
+ENTRY(psi_stat_residency)
+ENTRY(psci_stat_count)
mov r0, #PSCI_RET_NOT_SUPPORTED @ Return -1 (Not Supported)
mov pc, lr
+ENDPROC(psci_stat_count)
+ENDPROC(psi_stat_residency)
+ENDPROC(psci_set_suspend_mode)
+ENDPROC(psci_system_suspend)
+ENDPROC(psci_node_hw_state)
+ENDPROC(psci_cpu_default_suspend)
+ENDPROC(psci_cpu_freeze)
+ENDPROC(psci_features)
+ENDPROC(psci_system_reset)
+ENDPROC(psci_system_off)
+ENDPROC(psci_migrate_info_up_cpu)
+ENDPROC(psci_migrate_info_type)
 ENDPROC(psci_migrate)
+ENDPROC(psci_affinity_info)
 ENDPROC(psci_cpu_on)
 ENDPROC(psci_cpu_off)
 ENDPROC(psci_cpu_suspend)
+ENDPROC(psci_version)
+.weak psci_version
 .weak psci_cpu_suspend
 .weak psci_cpu_off
 .weak psci_cpu_on
+.weak psci_affinity_info
 .weak psci_migrate
+.weak psci_migrate_info_type
+.weak psci_migrate_info_up_cpu
+.weak psci_system_off
+.weak psci_system_reset
+.weak psci_features
+.weak psci_cpu_freeze
+.weak psci_cpu_default_suspend
+.weak psci_node_hw_state
+.weak psci_system_suspend
+.weak psci_set_suspend_mode
+.weak psi_stat_residency
+.weak psci_stat_count
 
 _psci_table:
+   .word   PSCI_FN_PSCI_VERSION
+   .word   psci_version
.word   PSCI_FN_CPU_SUSPEND
.word   psci_cpu_suspend
.word   PSCI_FN_CPU_OFF
.word   psci_cpu_off
.word   PSCI_FN_CPU_ON
.word   psci_cpu_on
+   .word   PSCI_FN_AFFINITY_INFO
+   .word   psci_affinity_info
.word   PSCI_FN_MIGRATE
.word   psci_migrate
+   .word   PSCI_FN_MIGRATE_INFO_TYPE
+   .word   psci_migrate_info_type
+   .word   PSCI_FN_MIGRATE_INFO_UP_CPU
+   .word   psci_migrate_info_up_cpu
+   .word   PSCI_FN_SYSTEM_OFF
+   .word   psci_system_off
+   .word   PSCI_FN_SYSTEM_RESET
+   .word   psci_system_reset
+   .word   PSCI_FN_PSCI_FEATURES
+   .word   psci_features
+   .word   PSCI_FN_CPU_FREEZE
+   .word   psci_cpu_freeze
+   .word   PSCI_FN_CPU_DEFAULT_SUSPEND
+   .word   psci_cpu_default_suspend
+   .word   PSCI_FN_NODE_HW_STATE
+   .word   psci_node_hw_state
+   .word   PSCI_FN_SYSTEM_SUSPEND
+   .word   psci_system_suspend
+   .word   PSCI_FN_SET_SUSPEND_MODE
+   .word   psci_set_suspend_mode
+   .word   PSCI_FN_STAT_RESIDENCY
+   .word   psi_stat_residency
+   .word   PSCI_FN_STAT_COUNT
+   .word   psci_stat_count
.word   0
.word   0
 
diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
index 4953f27..08258a0 100644
--- a/arch/arm/cpu/armv7/virt-dt.c
+++ b/arch/arm/cpu/armv7/virt-dt.c
@@ -26,6 +26,35 @@
 #include 
 #include 
 
+#ifdef CONFIG_ARMV7_PSCI
+#ifdef CONFIG_ARMV7_PSCI_1_0
+static int fdt_psci_1_0_fixup(void *fdt, int nodeoff)
+{
+   return fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci-1.0");
+}
+#endif
+
+static int fdt_psci_0_1_fixup(void *fdt, int nodeoff)
+{
+   int ret;
+
+   ret = fdt_appendprop_string(fdt, nodeoff, "compatible", "arm,psci");
+   if (ret)
+   return ret;
+   ret = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", PSCI_FN_CPU_SUSPEND);
+   if (ret)
+   return ret;
+   ret = fdt_setprop_u32(fdt, nodeoff, "cpu_off", PSCI_FN_CPU_OFF);
+   if (ret)
+   return ret;
+   ret = fdt_setprop_u32(fdt, nodeoff, "cpu_on", PSCI_FN_CPU_ON);
+   if (ret)
+   return ret;
+
+   return fdt_setprop_u32(fdt, nodeoff, "migrate", PSCI_FN_MIGRATE);
+}
+#endif
+
 static int fdt_psci(void *fdt)
 {
 #ifdef CONFIG_ARMV7_PSCI
@@ -67,22 +96,16 @@ static int fdt_psci(void *fdt)
 

[U-Boot] [PATCH v3 09/11] ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON

[macro . wave . z]

From: Hongbo Zhang 

For the robustness of codes, while powering on a CPU, it is better to check
if the target CPU is already on or in the process of power on, if yes the
power on routine shouldn't be executed further and should return with the
corresponding status immediately.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv7/ls102xa/psci.S | 29 +
 arch/arm/include/asm/psci.h   |  5 +
 2 files changed, 34 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index 9de812f..4cb960a 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -67,6 +67,22 @@ psci_cpu_on:
beq out_psci_cpu_on
mov r1, r0
 
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CPU_STATUS_OFFSET
+   ldr r5, [r0]
+
+   cmp r5, #PSCI_CPU_STATUS_ON
+   moveq   r0, #PSCI_RET_ALREADY_ON
+   beq out_psci_cpu_on
+
+   cmp r5, #PSCI_CPU_STATUS_ON_PENDING
+   moveq   r0, #PSCI_RET_ON_PENDING
+   beq out_psci_cpu_on
+
+   mov r5, #PSCI_CPU_STATUS_ON_PENDING
+   str r5, [r0]
+   dsb
+
bl  psci_cpu_on_common
 
@ Get DCFG base address
@@ -124,6 +140,12 @@ holdoff_release:
rev r6, r6
str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
 
+   mov r0, r1
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CPU_STATUS_OFFSET
+   mov r5, #PSCI_CPU_STATUS_ON
+   str r5, [r0]
+
isb
dsb
 
@@ -138,6 +160,13 @@ out_psci_cpu_on:
 psci_cpu_off:
bl  psci_cpu_off_common
 
+   bl  psci_get_cpu_id
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CPU_STATUS_OFFSET
+   mov r5, #PSCI_CPU_STATUS_OFF
+   str r5, [r0]
+   dsb
+
 1: wfi
b   1b
 
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 32ae359..535b77f 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -22,6 +22,7 @@
 #define PSCI_PERCPU_STACK_SIZE 0x400
 #define PSCI_TARGET_PC_OFFSET  (PSCI_PERCPU_STACK_SIZE - 4)
 #define PSCI_CONTEXT_ID_OFFSET (PSCI_PERCPU_STACK_SIZE - 8)
+#define PSCI_CPU_STATUS_OFFSET (PSCI_PERCPU_STACK_SIZE - 12)
 
 /* PSCI interfaces */
 #define PSCI_FN_BASE   0x8400
@@ -47,6 +48,10 @@
 #define PSCI_FN_STAT_COUNT PSCI_FN_ID(17)
 
 
+#define PSCI_CPU_STATUS_OFF0
+#define PSCI_CPU_STATUS_ON 1
+#define PSCI_CPU_STATUS_ON_PENDING 2
+
 /* PSCI return values */
 #define PSCI_RET_SUCCESS   0
 #define PSCI_RET_NOT_SUPPORTED (-1)
-- 
2.1.4

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[U-Boot] [PATCH v3 08/11] ARMv7: PSCI: ls102xa: check target CPU ID before further operations

[macro . wave . z]

From: Hongbo Zhang 

The input parameter CPU ID needs to be validated before furher oprations such
as CPU_ON, this patch introduces the function to do this.

Signed-off-by: Wang Dongsheng 
Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv7/ls102xa/psci.S | 34 +-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index 47bcb29..9de812f 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -25,6 +25,34 @@
 #defineONE_MS  (GENERIC_TIMER_CLK / 1000)
 #defineRESET_WAIT  (30 * ONE_MS)
 
+.globl psci_check_target_cpu_id
+psci_check_target_cpu_id:
+   @ Get the real CPU number
+   and r0, r1, #0xff
+
+   @ Verify bit[31:24], bits must be zero.
+   tst r1, #0xff00
+   bne out_psci_invalid_target_cpu_id
+
+   @ Verify Affinity level 2: Cluster, only one cluster in LS1021xa SoC.
+   tst r1, #0xff
+   bne out_psci_invalid_target_cpu_id
+
+   @ Verify Affinity level 1: Processors, should be in 0xf00 format.
+   lsr r1, r1, #8
+   teq r1, #0xf
+   bne out_psci_invalid_target_cpu_id
+
+   @ Verify Affinity level 0: CPU, only 0, 1 are valid values.
+   cmp r0, #2
+   bge out_psci_invalid_target_cpu_id
+
+   bx  lr
+
+out_psci_invalid_target_cpu_id:
+   mov r0, #PSCI_RET_INVALID_PARAMS
+   bx  lr
+
@ r1 = target CPU
@ r2 = target PC
@ r3 = target Conetxt ID
@@ -34,7 +62,10 @@ psci_cpu_on:
 
@ Clear and Get the correct CPU number
@ r1 = 0xf01
-   and r1, r1, #0xff
+   bl  psci_check_target_cpu_id
+   cmp r0, #PSCI_RET_INVALID_PARAMS
+   beq out_psci_cpu_on
+   mov r1, r0
 
bl  psci_cpu_on_common
 
@@ -99,6 +130,7 @@ holdoff_release:
@ Return
mov r0, #PSCI_RET_SUCCESS
 
+out_psci_cpu_on:
pop {lr}
bx  lr
 
-- 
2.1.4

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[U-Boot] [PATCH v3 11/11] ARMv7: PSCI: ls102xa: move secure text section into OCRAM

[macro . wave . z]

From: Hongbo Zhang 

LS1021 offers two secure OCRAM blocks for trustzone.
This patch moves all the secure text sections into the OCRAM.

Signed-off-by: Wang Dongsheng 
Signed-off-by: Hongbo Zhang 
---
 arch/arm/include/asm/arch-ls102xa/config.h | 2 +-
 include/configs/ls1021atwr.h   | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index 955a074..0266352 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -10,7 +10,7 @@
 #define CONFIG_SYS_CACHELINE_SIZE  64
 
 #define OCRAM_BASE_ADDR0x1000
-#define OCRAM_SIZE 0x0002
+#define OCRAM_SIZE 0x0001
 #define OCRAM_BASE_S_ADDR  0x1001
 #define OCRAM_S_SIZE   0x0001
 
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index f7e1457..54d4439 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -12,6 +12,8 @@
 #define CONFIG_ARMV7_PSCI
 #define CONFIG_ARMV7_PSCI_1_0
 
+#define CONFIG_ARMV7_SECURE_BASE   OCRAM_BASE_S_ADDR
+
 #define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_DISPLAY_CPUINFO
-- 
2.1.4

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[U-Boot] [PATCH v3 10/11] ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention

[macro . wave . z]

From: Hongbo Zhang 

This patch implements PSCI functions for ls102xa SoC following PSCI v1.0,
they are as the list:
psci_version,
psci_features,
psci_cpu_suspend,
psci_affinity_info,
psci_system_reset,
psci_system_off.

Tested on LS1021aQDS, LS1021aTWR.

Signed-off-by: Wang Dongsheng 
Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv7/ls102xa/psci.S  | 105 +++--
 arch/arm/include/asm/arch-ls102xa/config.h |   1 +
 arch/arm/include/asm/psci.h|   4 ++
 board/freescale/ls1021aqds/Makefile|   1 +
 board/freescale/ls1021aqds/psci.S  |  36 ++
 board/freescale/ls1021atwr/Makefile|   1 +
 board/freescale/ls1021atwr/psci.S  |  28 
 include/configs/ls1021aqds.h   |   3 +
 include/configs/ls1021atwr.h   |   1 +
 9 files changed, 176 insertions(+), 4 deletions(-)
 create mode 100644 board/freescale/ls1021aqds/psci.S
 create mode 100644 board/freescale/ls1021atwr/psci.S

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index 4cb960a..ff3978d 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -12,19 +12,72 @@
 #include 
 #include 
 
+#define RCPM_TWAITSR   0x04C
+
 #define SCFG_CORE0_SFT_RST  0x130
 #define SCFG_CORESRENCR 0x204
 
-#define DCFG_CCSR_BRR   0x0E4
-#define DCFG_CCSR_SCRATCHRW10x200
+#define DCFG_CCSR_RSTCR0x0B0
+#define DCFG_CCSR_RSTCR_RESET_REQ  0x2
+#define DCFG_CCSR_BRR  0x0E4
+#define DCFG_CCSR_SCRATCHRW1   0x200
+
+#define PSCI_FN_PSCI_VERSION_FEATURE_MASK  0x0
+#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK   0x0
+#define PSCI_FN_CPU_OFF_FEATURE_MASK   0x0
+#define PSCI_FN_CPU_ON_FEATURE_MASK0x0
+#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0
+#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK0x0
+#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK  0x0
 
.pushsection ._secure.text, "ax"
 
.arch_extension sec
 
+   .align  5
+
 #defineONE_MS  (GENERIC_TIMER_CLK / 1000)
 #defineRESET_WAIT  (30 * ONE_MS)
 
+.globl psci_version
+psci_version:
+   movwr0, #0
+   movtr0, #1
+
+   bx  lr
+
+_ls102x_psci_supported_table:
+   .word   PSCI_FN_PSCI_VERSION
+   .word   PSCI_FN_PSCI_VERSION_FEATURE_MASK
+   .word   PSCI_FN_CPU_SUSPEND
+   .word   PSCI_FN_CPU_SUSPEND_FEATURE_MASK
+   .word   PSCI_FN_CPU_OFF
+   .word   PSCI_FN_CPU_OFF_FEATURE_MASK
+   .word   PSCI_FN_CPU_ON
+   .word   PSCI_FN_CPU_ON_FEATURE_MASK
+   .word   PSCI_FN_AFFINITY_INFO
+   .word   PSCI_FN_AFFINITY_INFO_FEATURE_MASK
+   .word   PSCI_FN_SYSTEM_OFF
+   .word   PSCI_FN_SYSTEM_OFF_FEATURE_MASK
+   .word   PSCI_FN_SYSTEM_RESET
+   .word   PSCI_FN_SYSTEM_RESET_FEATURE_MASK
+   .word   0
+   .word   PSCI_RET_NOT_SUPPORTED
+
+.globl psci_features
+psci_features:
+   adr r2, _ls102x_psci_supported_table
+1: ldr r3, [r2]
+   cmp r3, #0
+   beq out_psci_features
+   cmp r1, r3
+   addne   r2, r2, #8
+   bne 1b
+
+out_psci_features:
+   ldr r0, [r2, #4]
+   bx  lr
+
 .globl psci_check_target_cpu_id
 psci_check_target_cpu_id:
@ Get the real CPU number
@@ -170,6 +223,52 @@ psci_cpu_off:
 1: wfi
b   1b
 
+.globl psci_affinity_info
+psci_affinity_info:
+   push{lr}
+
+   mov r0, #PSCI_RET_INVALID_PARAMS
+
+   @ Verify Affinity level
+   cmp r2, #0
+   bne out_affinity_info
+
+   bl  psci_check_target_cpu_id
+   cmp r0, #PSCI_RET_INVALID_PARAMS
+   beq out_affinity_info
+   mov r1, r0
+
+   @ Get RCPM base address
+   movwr4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0x)
+   movtr4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
+
+   mov r0, #PSCI_AFFINITY_LEVEL_ON
+
+   @ Detect target CPU state
+   ldr r2, [r4, #RCPM_TWAITSR]
+   rev r2, r2
+   lsr r2, r2, r1
+   andsr2, r2, #1
+   beq out_affinity_info
+
+   mov r0, #PSCI_AFFINITY_LEVEL_OFF
+
+out_affinity_info:
+   pop {pc}
+
+.globl psci_system_reset
+psci_system_reset:
+   @ Get DCFG base address
+   movwr1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0x)
+   movtr1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+
+   mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
+   rev r2, r2
+   str r2, [r1, #DCFG_CCSR_RSTCR]
+
+1: wfi
+   b   1b
+
 .globl psci_arch_init
 psci_arch_init:
mov r6, lr
@@ -180,6 +279,4 @@ psci_arch_init:
 
bx  r6
 
-   .globl psci_text_end
-psci_text_end:
.popsection
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index 

[U-Boot] [PATCH v3 06/11] ARMv7: PSCI: factor out reusable psci_cpu_on_common

[macro . wave . z]

From: Hongbo Zhang 

There are codes for saving target PC and target context ID in each platform
psci_cpu_on routines, these can be factored out as psci_cpu_on_common.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/ls102xa/psci.S | 12 +---
 arch/arm/cpu/armv7/mx7/psci.S | 12 +---
 arch/arm/cpu/armv7/psci.S | 15 +++
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 12 +---
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 13 +
 arch/arm/mach-tegra/psci.S| 12 +---
 6 files changed, 20 insertions(+), 56 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index 1303909..47bcb29 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -36,17 +36,7 @@ psci_cpu_on:
@ r1 = 0xf01
and r1, r1, #0xff
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   sub r0, r0, #PSCI_TARGET_PC_OFFSET
-   str r2, [r0]
-   dsb
-
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
-   str r3, [r0]
-   dsb
+   bl  psci_cpu_on_common
 
@ Get DCFG base address
movwr4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0x)
diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S
index 90b8b9e..c9a7b00 100644
--- a/arch/arm/cpu/armv7/mx7/psci.S
+++ b/arch/arm/cpu/armv7/mx7/psci.S
@@ -29,17 +29,7 @@ psci_arch_init:
 psci_cpu_on:
push{lr}
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   sub r0, r0, #PSCI_TARGET_PC_OFFSET
-   str r2, [r0]
-   dsb
-
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
-   str r3, [r0]
-   dsb
+   bl  psci_cpu_on_common
 
ldr r2, =psci_cpu_entry
bl  imx_cpu_on
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 0865712..28579d7 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -175,6 +175,21 @@ ENTRY(psci_enable_smp)
 ENDPROC(psci_enable_smp)
 .weak psci_enable_smp
 
+/* expects target CPU in r1, target PC in r2, target conetxt ID in r3 */
+ENTRY(psci_cpu_on_common)
+   push{lr}
+
+   mov r0, r1
+   bl  psci_get_cpu_stack_top  @ get stack top of target CPU
+   sub r5, r0, #PSCI_TARGET_PC_OFFSET
+   str r2, [r5]@ save target PC
+   sub r5, r0, #PSCI_CONTEXT_ID_OFFSET
+   str r3, [r5]@ save target context ID
+   dsb
+
+   pop {pc}
+ENDPROC(psci_cpu_on_common)
+
 ENTRY(psci_cpu_off_common)
push{lr}
 
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 2c9b078..a94a68d 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -135,17 +135,7 @@ out:   mcr p15, 0, r7, c1, c1, 0
 psci_cpu_on:
push{lr}
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   sub r0, r0, #PSCI_TARGET_PC_OFFSET
-   str r2, [r0]@ store target PC
-   dsb
-
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
-   str r3, [r0]
-   dsb
+   bl  psci_cpu_on_common
 
movwr0, #(SUN6I_CPUCFG_BASE & 0x)
movtr0, #(SUN6I_CPUCFG_BASE >> 16)
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index c1f117a..b0601a7 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -124,18 +124,7 @@ out:   mcr p15, 0, r7, c1, c1, 0
 psci_cpu_on:
push{lr}
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   sub r0, r0, #PSCI_TARGET_PC_OFFSET
-   str r2, [r0]@ store target PC
-   dsb
-
-
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
-   str r3, [r0]
-   dsb
+   bl  psci_cpu_on_common
 
movwr0, #(SUN7I_CPUCFG_BASE & 0x)
movtr0, #(SUN7I_CPUCFG_BASE >> 16)
diff --git a/arch/arm/mach-tegra/psci.S b/arch/arm/mach-tegra/psci.S
index 3837d95..8fa90ce 100644
--- a/arch/arm/mach-tegra/psci.S
+++ b/arch/arm/mach-tegra/psci.S
@@ -90,17 +90,7 @@ ENDPROC(psci_cpu_off)
 ENTRY(psci_cpu_on)
push{lr}
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   sub r0, r0, #PSCI_TARGET_PC_OFFSET
-   str r2, [r0]@ store target PC
-   dsb
-
-   mov r0, r1
-   bl  

[U-Boot] [PATCH v3 05/11] ARMv7: PSCI: add codes to save context ID for CPU_ON

[macro . wave . z]

From: Hongbo Zhang 

According to latest PSCI specification, the context ID is needed by CPU_ON.
This patch saves context ID to the second lowest address of the stack (next to
where target PC is saved), and restores it to r0 when needed while target CPU
booting up.

This patch in current format is for easier review, there are some lines
duplication with previous saving target PC codes, e.g. codes of calling the
psci_get_cpu_stack_top, this will be optimized by the following patch.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/ls102xa/psci.S | 7 +++
 arch/arm/cpu/armv7/mx7/psci.S | 8 +++-
 arch/arm/cpu/armv7/nonsec_virt.S  | 7 +++
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 7 +++
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 8 
 arch/arm/include/asm/psci.h   | 1 +
 arch/arm/mach-tegra/psci.S| 6 ++
 7 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index e1293ed..1303909 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -27,6 +27,7 @@
 
@ r1 = target CPU
@ r2 = target PC
+   @ r3 = target Conetxt ID
 .globl psci_cpu_on
 psci_cpu_on:
push{lr}
@@ -41,6 +42,12 @@ psci_cpu_on:
str r2, [r0]
dsb
 
+   mov r0, r1
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
+   str r3, [r0]
+   dsb
+
@ Get DCFG base address
movwr4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0x)
movtr4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S
index 02ca076..90b8b9e 100644
--- a/arch/arm/cpu/armv7/mx7/psci.S
+++ b/arch/arm/cpu/armv7/mx7/psci.S
@@ -24,7 +24,7 @@ psci_arch_init:
 
@ r1 = target CPU
@ r2 = target PC
-
+   @ r3 = target Conetxt ID
 .globl psci_cpu_on
 psci_cpu_on:
push{lr}
@@ -35,6 +35,12 @@ psci_cpu_on:
str r2, [r0]
dsb
 
+   mov r0, r1
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
+   str r3, [r0]
+   dsb
+
ldr r2, =psci_cpu_entry
bl  imx_cpu_on
 
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index b7563ed..6566643 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 .arch_extension sec
 .arch_extension virt
@@ -89,6 +90,12 @@ _secure_monitor:
movne   r4, #0
mcrrne  p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero
 1:
+#ifdef CONFIG_ARMV7_PSCI
+   bl  psci_get_cpu_id
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
+   ldr r0, [r0]@ get Context ID in r0
+#endif
mov lr, ip
mov ip, #(F_BIT | I_BIT | A_BIT)@ Set A, I and F
tst lr, #1  @ Check for Thumb PC
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 51241ec..2c9b078 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -130,6 +130,7 @@ out:mcr p15, 0, r7, c1, c1, 0
 
@ r1 = target CPU
@ r2 = target PC
+   @ r3 = target Conetxt ID
 .globl psci_cpu_on
 psci_cpu_on:
push{lr}
@@ -140,6 +141,12 @@ psci_cpu_on:
str r2, [r0]@ store target PC
dsb
 
+   mov r0, r1
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
+   str r3, [r0]
+   dsb
+
movwr0, #(SUN6I_CPUCFG_BASE & 0x)
movtr0, #(SUN6I_CPUCFG_BASE >> 16)
 
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index 50ba355..c1f117a 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -119,6 +119,7 @@ out:mcr p15, 0, r7, c1, c1, 0
 
@ r1 = target CPU
@ r2 = target PC
+   @ r3 = target Conetxt ID
 .globl psci_cpu_on
 psci_cpu_on:
push{lr}
@@ -129,6 +130,13 @@ psci_cpu_on:
str r2, [r0]@ store target PC
dsb
 
+
+   mov r0, r1
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
+   str r3, [r0]
+   dsb
+
movwr0, #(SUN7I_CPUCFG_BASE & 0x)
movtr0, #(SUN7I_CPUCFG_BASE >> 16)
 
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index d0f5d26..d703aeb 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -21,6 +21,7 @@
 /* size of percpu stack, 1kB */
 #define PSCI_PERCPU_STACK_SIZE 0x400
 

[U-Boot] [PATCH v3 00/11] ARMv7: PSCI: add PSCI v1.0 support

[macro . wave . z]

From: Hongbo Zhang 

Previous v2 patch set was sent out for a long time but got no comments, this
time I send a v3 with minor updates and with more people in list, they are
contributors for Linux kernel PSCI codes.

v3 changes:
- patch 3/11, re-init the stack pointer to address like start of page instead
of page end, because for ARM push operation, the stack pointer is encreased
before storing data.
- patch 10/11, delete the previous un-implemented cpu_suspend function for ls1
platform, because there is default blank functions for all those are not
implemented in specific platform.


v2 changes:
- re-organize psci_cpu_on_common, this code should be called by each platform's
psci_cpu_on, should not be a function calling each psci_cpu_on, all related
functions are updated due to this change
- update some registers usage, e.g. if r10 is used without push/pop, u-boot
cannot launch rt-kernel
- update some comments to be clearer, re-organize all patches for easier review
- add patch to check already_on or on_pending for LS102XA

This patch set contains two parts:
ARMv7 PSCI common framework: fix some issues and add v1.0 support
NXP (was Freescale) LS102XA: codes enhancement and add v1.0 implementation
And this patch set was initially created by Dongsheng Wang.

Hongbo Zhang (9):
Wang Dongsheng (2):
  ARMv7: PSCI: update function psci_get_cpu_stack_top
  ARMv7: PSCI: update the place of saving target PC
  ARMv7: PSCI: add codes to save context ID for CPU_ON
  ARMv7: PSCI: factor out reusable psci_cpu_on_common
  ARMv7: PSCI: add PSCI v1.0 functions skeleton
  ARMv7: PSCI: ls102xa: check target CPU ID before further operations
  ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON
  ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention
  ARMv7: PSCI: ls102xa: move secure text section into OCRAM
  ARM: PSCI: change PSCI function IDs base and offsets
  ARM: PSCI: change PSCI related macros definition style

 arch/arm/cpu/armv7/ls102xa/psci.S  | 172 +++--
 arch/arm/cpu/armv7/mx7/psci.S  |   7 +-
 arch/arm/cpu/armv7/nonsec_virt.S   |   7 ++
 arch/arm/cpu/armv7/psci.S  | 110 --
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S  |   8 +-
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S  |   8 +-
 arch/arm/cpu/armv7/virt-dt.c   |  54 ++---
 arch/arm/include/asm/arch-ls102xa/config.h |   3 +-
 arch/arm/include/asm/psci.h|  62 ---
 arch/arm/mach-tegra/psci.S |   7 +-
 board/freescale/ls1021aqds/Makefile|   1 +
 board/freescale/ls1021aqds/psci.S  |  36 ++
 board/freescale/ls1021atwr/Makefile|   1 +
 board/freescale/ls1021atwr/psci.S  |  28 +
 include/configs/ls1021aqds.h   |   3 +
 include/configs/ls1021atwr.h   |   3 +
 16 files changed, 443 insertions(+), 67 deletions(-)
 create mode 100644 board/freescale/ls1021aqds/psci.S
 create mode 100644 board/freescale/ls1021atwr/psci.S

-- 
2.1.4

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[U-Boot] [PATCH v3 04/11] ARMv7: PSCI: update the place of saving target PC

[macro . wave . z]

From: Hongbo Zhang 

The legacy code reserves one word in each stack for saving target PC, but it
isn't used, the target PC is still saved to where the stack top pointer points.
This patch relocates the place for saving target PC to the lowest address of
each stack, convinience is that we can save more contents if needed ilater next
to saved target PC without re-adjust the stack top pointer.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/ls102xa/psci.S | 1 +
 arch/arm/cpu/armv7/mx7/psci.S | 1 +
 arch/arm/cpu/armv7/psci.S | 3 ++-
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 3 ++-
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 3 ++-
 arch/arm/include/asm/psci.h   | 1 +
 arch/arm/mach-tegra/psci.S| 3 ++-
 7 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index 0b067d9..e1293ed 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -37,6 +37,7 @@ psci_cpu_on:
 
mov r0, r1
bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_TARGET_PC_OFFSET
str r2, [r0]
dsb
 
diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S
index 34c6ab3..02ca076 100644
--- a/arch/arm/cpu/armv7/mx7/psci.S
+++ b/arch/arm/cpu/armv7/mx7/psci.S
@@ -31,6 +31,7 @@ psci_cpu_on:
 
mov r0, r1
bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_TARGET_PC_OFFSET
str r2, [r0]
dsb
 
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 2913e07..0865712 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -216,7 +216,8 @@ ENTRY(psci_cpu_entry)
 
bl  psci_get_cpu_id @ CPU ID => r0
bl  psci_get_cpu_stack_top  @ stack top => r0
-   ldr r0, [r0]@ target PC at stack top
+   sub r0, r0, #PSCI_TARGET_PC_OFFSET
+   ldr r0, [r0]@ get target PC
b   _do_nonsec_entry
 ENDPROC(psci_cpu_entry)
 
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index ac722e4..51241ec 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -136,7 +136,8 @@ psci_cpu_on:
 
mov r0, r1
bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   str r2, [r0]@ store target PC at stack top
+   sub r0, r0, #PSCI_TARGET_PC_OFFSET
+   str r2, [r0]@ store target PC
dsb
 
movwr0, #(SUN6I_CPUCFG_BASE & 0x)
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index 59d7ff0..50ba355 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -125,7 +125,8 @@ psci_cpu_on:
 
mov r0, r1
bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   str r2, [r0]@ store target PC at stack top
+   sub r0, r0, #PSCI_TARGET_PC_OFFSET
+   str r2, [r0]@ store target PC
dsb
 
movwr0, #(SUN7I_CPUCFG_BASE & 0x)
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 47a2ea4..d0f5d26 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -20,6 +20,7 @@
 
 /* size of percpu stack, 1kB */
 #define PSCI_PERCPU_STACK_SIZE 0x400
+#define PSCI_TARGET_PC_OFFSET  (PSCI_PERCPU_STACK_SIZE - 4)
 
 /* PSCI interfaces */
 #define PSCI_FN_BASE   0x8400
diff --git a/arch/arm/mach-tegra/psci.S b/arch/arm/mach-tegra/psci.S
index 5f326c9..037c142 100644
--- a/arch/arm/mach-tegra/psci.S
+++ b/arch/arm/mach-tegra/psci.S
@@ -92,7 +92,8 @@ ENTRY(psci_cpu_on)
 
mov r0, r1
bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   str r2, [r0]@ store target PC at stack top
+   sub r0, r0, #PSCI_TARGET_PC_OFFSET
+   str r2, [r0]@ store target PC
dsb
 
ldr r6, =TEGRA_RESET_EXCEPTION_VECTOR
-- 
2.1.4

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[U-Boot] [PATCH v3 03/11] ARMv7: PSCI: update function psci_get_cpu_stack_top

[macro . wave . z]

From: Hongbo Zhang 

There are issues of legacy fuction psci_get_cpu_stack_top:

First, the current algorithm arranges stacks from an fixed adress towards
psci_text_end, if there are more CPUs, the stacks will overlap with psci text
segment and even other segments.
This patch places stacks from psci text segment towards highter address, and
all the stack space is reserved, so overlap can be avoided.

Second, even there is one word reserved in each stack for saving target PC, but
this reserved space isn't used at all, the target PC is still saved to where
the stack top pointer points.
This patch doesn't reserve this word as before, new way of saving target PC
will be introduced in following patch.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/psci.S| 10 +-
 arch/arm/cpu/armv7/virt-dt.c |  9 +++--
 arch/arm/include/asm/psci.h  |  2 ++
 3 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index e1fcb5d..2913e07 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -196,16 +196,16 @@ ENDPROC(psci_cpu_off_common)
 
 @ expects CPU ID in r0 and returns stack top in r0
 ENTRY(psci_get_cpu_stack_top)
-   mov r5, #0x400  @ 1kB of stack per CPU
-   mul r0, r0, r5
+   mov r5, #PSCI_PERCPU_STACK_SIZE @ 1kB of stack per CPU
+   add r0, r0, #1
+   mul r0, r0, r5  @ offset of each stack
 
ldr r5, =psci_text_end  @ end of monitor text
-   add r5, r5, #0x2000 @ Skip two pages
+   add r5, r5, #0x1000 @ Skip one page
lsr r5, r5, #12 @ Align to start of page
lsl r5, r5, #12
-   sub r5, r5, #4  @ reserve 1 word for target PC
-   sub r0, r5, r0  @ here's our stack!
 
+   add r0, r5, r0  @ here's our stack!
bx  lr
 ENDPROC(psci_get_cpu_stack_top)
 
diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
index f1251d1..4953f27 100644
--- a/arch/arm/cpu/armv7/virt-dt.c
+++ b/arch/arm/cpu/armv7/virt-dt.c
@@ -124,9 +124,14 @@ int psci_update_dt(void *fdt)
return 0;
 #endif
 #ifndef CONFIG_ARMV7_SECURE_BASE
+   size_t sz = __secure_end - __secure_start;
+#ifdef CONFIG_ARMV7_PSCI
+   sz += CONFIG_MAX_CPUS * PSCI_PERCPU_STACK_SIZE;
+   /* margin to align psci_text_end to page end*/
+   sz += 0x1000;
+#endif
/* secure code lives in RAM, keep it alive */
-   fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
-   __secure_end - __secure_start);
+   fdt_add_mem_rsv(fdt, (unsigned long)__secure_start, sz);
 #endif
 
return fdt_psci(fdt);
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 7c3450c..47a2ea4 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -18,6 +18,8 @@
 #ifndef __ARM_PSCI_H__
 #define __ARM_PSCI_H__
 
+/* size of percpu stack, 1kB */
+#define PSCI_PERCPU_STACK_SIZE 0x400
 
 /* PSCI interfaces */
 #define PSCI_FN_BASE   0x8400
-- 
2.1.4

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[U-Boot] [PATCH v3 02/11] ARM: PSCI: change PSCI related macros definition style

[macro . wave . z]

From: Wang Dongsheng 

Since we are already under the directory of arch/arm/, the prefix ARM_ for
macros isn't so necessary, and with more PSCI interfaces being added later,
there will be much more redundant ARM_ prefixes, what's more, there are no
ARM_/arm_ prefixes for other PSCI variables and functions either, so this patch
updates these macro definitions to make them concise and consistent.

Signed-off-by: Wang Dongsheng 
Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv7/ls102xa/psci.S |  2 +-
 arch/arm/cpu/armv7/psci.S | 12 ++--
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S |  2 +-
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S |  2 +-
 arch/arm/cpu/armv7/virt-dt.c  |  8 
 arch/arm/include/asm/psci.h   | 24 +---
 arch/arm/mach-tegra/psci.S|  2 +-
 7 files changed, 27 insertions(+), 25 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index cf5cd48..0b067d9 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -99,7 +99,7 @@ holdoff_release:
dsb
 
@ Return
-   mov r0, #ARM_PSCI_RET_SUCCESS
+   mov r0, #PSCI_RET_SUCCESS
 
pop {lr}
bx  lr
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 87c0c0b..e1fcb5d 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -50,7 +50,7 @@ ENTRY(psci_cpu_suspend)
 ENTRY(psci_cpu_off)
 ENTRY(psci_cpu_on)
 ENTRY(psci_migrate)
-   mov r0, #ARM_PSCI_RET_NI@ Return -1 (Not Implemented)
+   mov r0, #PSCI_RET_NOT_SUPPORTED @ Return -1 (Not Supported)
mov pc, lr
 ENDPROC(psci_migrate)
 ENDPROC(psci_cpu_on)
@@ -62,13 +62,13 @@ ENDPROC(psci_cpu_suspend)
 .weak psci_migrate
 
 _psci_table:
-   .word   ARM_PSCI_FN_CPU_SUSPEND
+   .word   PSCI_FN_CPU_SUSPEND
.word   psci_cpu_suspend
-   .word   ARM_PSCI_FN_CPU_OFF
+   .word   PSCI_FN_CPU_OFF
.word   psci_cpu_off
-   .word   ARM_PSCI_FN_CPU_ON
+   .word   PSCI_FN_CPU_ON
.word   psci_cpu_on
-   .word   ARM_PSCI_FN_MIGRATE
+   .word   PSCI_FN_MIGRATE
.word   psci_migrate
.word   0
.word   0
@@ -86,7 +86,7 @@ _smc_psci:
 1: ldr r5, [r4]@ Load PSCI function ID
ldr r6, [r4, #4]@ Load target PC
cmp r5, #0  @ If reach the end, bail out
-   moveq   r0, #ARM_PSCI_RET_INVAL @ Return -2 (Invalid)
+   moveq   r0, #PSCI_RET_INVALID_PARAMS@ Return -2 (Invalid)
beq 2f
cmp r0, r5  @ If not matching, try next entry
addne   r4, r4, #8
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 90b5bfd..ac722e4 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -204,7 +204,7 @@ psci_cpu_on:
orr r6, r6, r4
str r6, [r0, #0x1e4]
 
-   mov r0, #ARM_PSCI_RET_SUCCESS   @ Return PSCI_RET_SUCCESS
+   mov r0, #PSCI_RET_SUCCESS   @ Return PSCI_RET_SUCCESS
pop {pc}
 
 .globl psci_cpu_off
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index e15d587..59d7ff0 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -179,7 +179,7 @@ psci_cpu_on:
orr r6, r6, r4
str r6, [r0, #0x1e4]
 
-   mov r0, #ARM_PSCI_RET_SUCCESS   @ Return PSCI_RET_SUCCESS
+   mov r0, #PSCI_RET_SUCCESS   @ Return PSCI_RET_SUCCESS
pop {pc}
 
 .globl psci_cpu_off
diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
index 32c368f..f1251d1 100644
--- a/arch/arm/cpu/armv7/virt-dt.c
+++ b/arch/arm/cpu/armv7/virt-dt.c
@@ -73,16 +73,16 @@ static int fdt_psci(void *fdt)
tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc");
if (tmp)
return tmp;
-   tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", 
ARM_PSCI_FN_CPU_SUSPEND);
+   tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", PSCI_FN_CPU_SUSPEND);
if (tmp)
return tmp;
-   tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", ARM_PSCI_FN_CPU_OFF);
+   tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", PSCI_FN_CPU_OFF);
if (tmp)
return tmp;
-   tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", ARM_PSCI_FN_CPU_ON);
+   tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", PSCI_FN_CPU_ON);
if (tmp)
return tmp;
-   tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", ARM_PSCI_FN_MIGRATE);
+   tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", PSCI_FN_MIGRATE);
if (tmp)
return tmp;
 #endif
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 

[U-Boot] [PATCH v3 01/11] ARM: PSCI: change PSCI function IDs base and offsets

[macro . wave . z]

From: Wang Dongsheng 

According to PSCI specification v1.0, the PSCI functions should start from
0x8400 for SMC32, this patch changes this base value as well as other
function offset values.

Signed-off-by: Wang Dongsheng 
Signed-off-by: Hongbo Zhang 
---
 arch/arm/include/asm/psci.h | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 128a606..a4a19e3 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -19,13 +19,13 @@
 #define __ARM_PSCI_H__
 
 /* PSCI interface */
-#define ARM_PSCI_FN_BASE   0x95c1ba5e
+#define ARM_PSCI_FN_BASE   0x8400
 #define ARM_PSCI_FN(n) (ARM_PSCI_FN_BASE + (n))
 
-#define ARM_PSCI_FN_CPU_SUSPENDARM_PSCI_FN(0)
-#define ARM_PSCI_FN_CPU_OFFARM_PSCI_FN(1)
-#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2)
-#define ARM_PSCI_FN_MIGRATEARM_PSCI_FN(3)
+#define ARM_PSCI_FN_CPU_SUSPENDARM_PSCI_FN(1)
+#define ARM_PSCI_FN_CPU_OFFARM_PSCI_FN(2)
+#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(3)
+#define ARM_PSCI_FN_MIGRATEARM_PSCI_FN(5)
 
 #define ARM_PSCI_RET_SUCCESS   0
 #define ARM_PSCI_RET_NI(-1)
-- 
2.1.4

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[U-Boot] [PATCH v2 11/11] ARMv7: PSCI: ls102xa: move secure text section into OCRAM

[macro . wave . z]

From: Hongbo Zhang 

LS1021 offers two secure OCRAM blocks for trustzone.
This patch moves all the secure text sections into the OCRAM.

Signed-off-by: Wang Dongsheng 
Signed-off-by: Hongbo Zhang 
---
 arch/arm/include/asm/arch-ls102xa/config.h | 2 +-
 include/configs/ls1021atwr.h   | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index 955a074..0266352 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -10,7 +10,7 @@
 #define CONFIG_SYS_CACHELINE_SIZE  64
 
 #define OCRAM_BASE_ADDR0x1000
-#define OCRAM_SIZE 0x0002
+#define OCRAM_SIZE 0x0001
 #define OCRAM_BASE_S_ADDR  0x1001
 #define OCRAM_S_SIZE   0x0001
 
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index f7e1457..54d4439 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -12,6 +12,8 @@
 #define CONFIG_ARMV7_PSCI
 #define CONFIG_ARMV7_PSCI_1_0
 
+#define CONFIG_ARMV7_SECURE_BASE   OCRAM_BASE_S_ADDR
+
 #define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_DISPLAY_CPUINFO
-- 
2.1.4

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[U-Boot] [PATCH v2 08/11] ARMv7: PSCI: ls102xa: check target CPU ID before further operations

[macro . wave . z]

From: Hongbo Zhang 

The input parameter CPU ID needs to be validated before furher oprations such
as CPU_ON, this patch introduces the function to do this.

Signed-off-by: Wang Dongsheng 
Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv7/ls102xa/psci.S | 34 +-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index 47bcb29..9de812f 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -25,6 +25,34 @@
 #defineONE_MS  (GENERIC_TIMER_CLK / 1000)
 #defineRESET_WAIT  (30 * ONE_MS)
 
+.globl psci_check_target_cpu_id
+psci_check_target_cpu_id:
+   @ Get the real CPU number
+   and r0, r1, #0xff
+
+   @ Verify bit[31:24], bits must be zero.
+   tst r1, #0xff00
+   bne out_psci_invalid_target_cpu_id
+
+   @ Verify Affinity level 2: Cluster, only one cluster in LS1021xa SoC.
+   tst r1, #0xff
+   bne out_psci_invalid_target_cpu_id
+
+   @ Verify Affinity level 1: Processors, should be in 0xf00 format.
+   lsr r1, r1, #8
+   teq r1, #0xf
+   bne out_psci_invalid_target_cpu_id
+
+   @ Verify Affinity level 0: CPU, only 0, 1 are valid values.
+   cmp r0, #2
+   bge out_psci_invalid_target_cpu_id
+
+   bx  lr
+
+out_psci_invalid_target_cpu_id:
+   mov r0, #PSCI_RET_INVALID_PARAMS
+   bx  lr
+
@ r1 = target CPU
@ r2 = target PC
@ r3 = target Conetxt ID
@@ -34,7 +62,10 @@ psci_cpu_on:
 
@ Clear and Get the correct CPU number
@ r1 = 0xf01
-   and r1, r1, #0xff
+   bl  psci_check_target_cpu_id
+   cmp r0, #PSCI_RET_INVALID_PARAMS
+   beq out_psci_cpu_on
+   mov r1, r0
 
bl  psci_cpu_on_common
 
@@ -99,6 +130,7 @@ holdoff_release:
@ Return
mov r0, #PSCI_RET_SUCCESS
 
+out_psci_cpu_on:
pop {lr}
bx  lr
 
-- 
2.1.4

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[U-Boot] [PATCH v2 10/11] ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention

[macro . wave . z]

From: Hongbo Zhang 

This patch implements PSCI functions for ls102xa SoC following PSCI v1.0,
they are as the list:
psci_version,
psci_features,
psci_cpu_suspend,
psci_affinity_info,
psci_system_reset,
psci_system_off.

Tested on LS1021aQDS, LS1021aTWR.

Signed-off-by: Wang Dongsheng 
Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv7/ls102xa/psci.S  | 110 +++--
 arch/arm/include/asm/arch-ls102xa/config.h |   1 +
 arch/arm/include/asm/psci.h|   4 ++
 board/freescale/ls1021aqds/Makefile|   1 +
 board/freescale/ls1021aqds/psci.S  |  36 ++
 board/freescale/ls1021atwr/Makefile|   1 +
 board/freescale/ls1021atwr/psci.S  |  28 
 include/configs/ls1021aqds.h   |   3 +
 include/configs/ls1021atwr.h   |   1 +
 9 files changed, 181 insertions(+), 4 deletions(-)
 create mode 100644 board/freescale/ls1021aqds/psci.S
 create mode 100644 board/freescale/ls1021atwr/psci.S

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index 4cb960a..c497274 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -12,19 +12,72 @@
 #include 
 #include 
 
+#define RCPM_TWAITSR   0x04C
+
 #define SCFG_CORE0_SFT_RST  0x130
 #define SCFG_CORESRENCR 0x204
 
-#define DCFG_CCSR_BRR   0x0E4
-#define DCFG_CCSR_SCRATCHRW10x200
+#define DCFG_CCSR_RSTCR0x0B0
+#define DCFG_CCSR_RSTCR_RESET_REQ  0x2
+#define DCFG_CCSR_BRR  0x0E4
+#define DCFG_CCSR_SCRATCHRW1   0x200
+
+#define PSCI_FN_PSCI_VERSION_FEATURE_MASK  0x0
+#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK   0x0
+#define PSCI_FN_CPU_OFF_FEATURE_MASK   0x0
+#define PSCI_FN_CPU_ON_FEATURE_MASK0x0
+#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0
+#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK0x0
+#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK  0x0
 
.pushsection ._secure.text, "ax"
 
.arch_extension sec
 
+   .align  5
+
 #defineONE_MS  (GENERIC_TIMER_CLK / 1000)
 #defineRESET_WAIT  (30 * ONE_MS)
 
+.globl psci_version
+psci_version:
+   movwr0, #0
+   movtr0, #1
+
+   bx  lr
+
+_ls102x_psci_supported_table:
+   .word   PSCI_FN_PSCI_VERSION
+   .word   PSCI_FN_PSCI_VERSION_FEATURE_MASK
+   .word   PSCI_FN_CPU_SUSPEND
+   .word   PSCI_FN_CPU_SUSPEND_FEATURE_MASK
+   .word   PSCI_FN_CPU_OFF
+   .word   PSCI_FN_CPU_OFF_FEATURE_MASK
+   .word   PSCI_FN_CPU_ON
+   .word   PSCI_FN_CPU_ON_FEATURE_MASK
+   .word   PSCI_FN_AFFINITY_INFO
+   .word   PSCI_FN_AFFINITY_INFO_FEATURE_MASK
+   .word   PSCI_FN_SYSTEM_OFF
+   .word   PSCI_FN_SYSTEM_OFF_FEATURE_MASK
+   .word   PSCI_FN_SYSTEM_RESET
+   .word   PSCI_FN_SYSTEM_RESET_FEATURE_MASK
+   .word   0
+   .word   PSCI_RET_NOT_SUPPORTED
+
+.globl psci_features
+psci_features:
+   adr r2, _ls102x_psci_supported_table
+1: ldr r3, [r2]
+   cmp r3, #0
+   beq out_psci_features
+   cmp r1, r3
+   addne   r2, r2, #8
+   bne 1b
+
+out_psci_features:
+   ldr r0, [r2, #4]
+   bx  lr
+
 .globl psci_check_target_cpu_id
 psci_check_target_cpu_id:
@ Get the real CPU number
@@ -170,6 +223,57 @@ psci_cpu_off:
 1: wfi
b   1b
 
+.globl psci_cpu_suspend
+psci_cpu_suspend:
+   mov r0, #PSCI_RET_INVALID_PARAMS
+   bx  lr
+
+.globl psci_affinity_info
+psci_affinity_info:
+   push{lr}
+
+   mov r0, #PSCI_RET_INVALID_PARAMS
+
+   @ Verify Affinity level
+   cmp r2, #0
+   bne out_affinity_info
+
+   bl  psci_check_target_cpu_id
+   cmp r0, #PSCI_RET_INVALID_PARAMS
+   beq out_affinity_info
+   mov r1, r0
+
+   @ Get RCPM base address
+   movwr4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0x)
+   movtr4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
+
+   mov r0, #PSCI_AFFINITY_LEVEL_ON
+
+   @ Detect target CPU state
+   ldr r2, [r4, #RCPM_TWAITSR]
+   rev r2, r2
+   lsr r2, r2, r1
+   andsr2, r2, #1
+   beq out_affinity_info
+
+   mov r0, #PSCI_AFFINITY_LEVEL_OFF
+
+out_affinity_info:
+   pop {pc}
+
+.globl psci_system_reset
+psci_system_reset:
+   @ Get DCFG base address
+   movwr1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0x)
+   movtr1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+
+   mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
+   rev r2, r2
+   str r2, [r1, #DCFG_CCSR_RSTCR]
+
+1: wfi
+   b   1b
+
 .globl psci_arch_init
 psci_arch_init:
mov r6, lr
@@ -180,6 +284,4 @@ psci_arch_init:
 
bx  r6
 
-   .globl psci_text_end
-psci_text_end:
.popsection

[U-Boot] [PATCH v2 07/11] ARMv7: PSCI: add PSCI v1.0 functions skeleton

[macro . wave . z]

From: Hongbo Zhang 

This patch adds all the PSCI v1.0 functions in to the common framework, with
all the functions returning "not sopported" by default, as a common framework
all the functions are added here, it is up to every platform developer to
decide which version of PSCI and which functions in it to be implemented.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/psci.S| 70 
 arch/arm/cpu/armv7/virt-dt.c | 45 +---
 arch/arm/include/asm/psci.h  | 21 +
 3 files changed, 125 insertions(+), 11 deletions(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index eb63581..a7ef786 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -46,30 +46,100 @@ ENTRY(default_psci_vector)
 ENDPROC(default_psci_vector)
 .weak default_psci_vector
 
+ENTRY(psci_version)
 ENTRY(psci_cpu_suspend)
 ENTRY(psci_cpu_off)
 ENTRY(psci_cpu_on)
+ENTRY(psci_affinity_info)
 ENTRY(psci_migrate)
+ENTRY(psci_migrate_info_type)
+ENTRY(psci_migrate_info_up_cpu)
+ENTRY(psci_system_off)
+ENTRY(psci_system_reset)
+ENTRY(psci_features)
+ENTRY(psci_cpu_freeze)
+ENTRY(psci_cpu_default_suspend)
+ENTRY(psci_node_hw_state)
+ENTRY(psci_system_suspend)
+ENTRY(psci_set_suspend_mode)
+ENTRY(psi_stat_residency)
+ENTRY(psci_stat_count)
mov r0, #PSCI_RET_NOT_SUPPORTED @ Return -1 (Not Supported)
mov pc, lr
+ENDPROC(psci_stat_count)
+ENDPROC(psi_stat_residency)
+ENDPROC(psci_set_suspend_mode)
+ENDPROC(psci_system_suspend)
+ENDPROC(psci_node_hw_state)
+ENDPROC(psci_cpu_default_suspend)
+ENDPROC(psci_cpu_freeze)
+ENDPROC(psci_features)
+ENDPROC(psci_system_reset)
+ENDPROC(psci_system_off)
+ENDPROC(psci_migrate_info_up_cpu)
+ENDPROC(psci_migrate_info_type)
 ENDPROC(psci_migrate)
+ENDPROC(psci_affinity_info)
 ENDPROC(psci_cpu_on)
 ENDPROC(psci_cpu_off)
 ENDPROC(psci_cpu_suspend)
+ENDPROC(psci_version)
+.weak psci_version
 .weak psci_cpu_suspend
 .weak psci_cpu_off
 .weak psci_cpu_on
+.weak psci_affinity_info
 .weak psci_migrate
+.weak psci_migrate_info_type
+.weak psci_migrate_info_up_cpu
+.weak psci_system_off
+.weak psci_system_reset
+.weak psci_features
+.weak psci_cpu_freeze
+.weak psci_cpu_default_suspend
+.weak psci_node_hw_state
+.weak psci_system_suspend
+.weak psci_set_suspend_mode
+.weak psi_stat_residency
+.weak psci_stat_count
 
 _psci_table:
+   .word   PSCI_FN_PSCI_VERSION
+   .word   psci_version
.word   PSCI_FN_CPU_SUSPEND
.word   psci_cpu_suspend
.word   PSCI_FN_CPU_OFF
.word   psci_cpu_off
.word   PSCI_FN_CPU_ON
.word   psci_cpu_on
+   .word   PSCI_FN_AFFINITY_INFO
+   .word   psci_affinity_info
.word   PSCI_FN_MIGRATE
.word   psci_migrate
+   .word   PSCI_FN_MIGRATE_INFO_TYPE
+   .word   psci_migrate_info_type
+   .word   PSCI_FN_MIGRATE_INFO_UP_CPU
+   .word   psci_migrate_info_up_cpu
+   .word   PSCI_FN_SYSTEM_OFF
+   .word   psci_system_off
+   .word   PSCI_FN_SYSTEM_RESET
+   .word   psci_system_reset
+   .word   PSCI_FN_PSCI_FEATURES
+   .word   psci_features
+   .word   PSCI_FN_CPU_FREEZE
+   .word   psci_cpu_freeze
+   .word   PSCI_FN_CPU_DEFAULT_SUSPEND
+   .word   psci_cpu_default_suspend
+   .word   PSCI_FN_NODE_HW_STATE
+   .word   psci_node_hw_state
+   .word   PSCI_FN_SYSTEM_SUSPEND
+   .word   psci_system_suspend
+   .word   PSCI_FN_SET_SUSPEND_MODE
+   .word   psci_set_suspend_mode
+   .word   PSCI_FN_STAT_RESIDENCY
+   .word   psi_stat_residency
+   .word   PSCI_FN_STAT_COUNT
+   .word   psci_stat_count
.word   0
.word   0
 
diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
index 4953f27..08258a0 100644
--- a/arch/arm/cpu/armv7/virt-dt.c
+++ b/arch/arm/cpu/armv7/virt-dt.c
@@ -26,6 +26,35 @@
 #include 
 #include 
 
+#ifdef CONFIG_ARMV7_PSCI
+#ifdef CONFIG_ARMV7_PSCI_1_0
+static int fdt_psci_1_0_fixup(void *fdt, int nodeoff)
+{
+   return fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci-1.0");
+}
+#endif
+
+static int fdt_psci_0_1_fixup(void *fdt, int nodeoff)
+{
+   int ret;
+
+   ret = fdt_appendprop_string(fdt, nodeoff, "compatible", "arm,psci");
+   if (ret)
+   return ret;
+   ret = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", PSCI_FN_CPU_SUSPEND);
+   if (ret)
+   return ret;
+   ret = fdt_setprop_u32(fdt, nodeoff, "cpu_off", PSCI_FN_CPU_OFF);
+   if (ret)
+   return ret;
+   ret = fdt_setprop_u32(fdt, nodeoff, "cpu_on", PSCI_FN_CPU_ON);
+   if (ret)
+   return ret;
+
+   return fdt_setprop_u32(fdt, nodeoff, "migrate", PSCI_FN_MIGRATE);
+}
+#endif
+
 static int fdt_psci(void *fdt)
 {
 #ifdef CONFIG_ARMV7_PSCI
@@ -67,22 +96,16 @@ static int fdt_psci(void *fdt)
 

[U-Boot] [PATCH v2 09/11] ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON

[macro . wave . z]

From: Hongbo Zhang 

For the robustness of codes, while powering on a CPU, it is better to check
if the target CPU is already on or in the process of power on, if yes the
power on routine shouldn't be executed further and should return with the
corresponding status immediately.

Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv7/ls102xa/psci.S | 29 +
 arch/arm/include/asm/psci.h   |  5 +
 2 files changed, 34 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index 9de812f..4cb960a 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -67,6 +67,22 @@ psci_cpu_on:
beq out_psci_cpu_on
mov r1, r0
 
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CPU_STATUS_OFFSET
+   ldr r5, [r0]
+
+   cmp r5, #PSCI_CPU_STATUS_ON
+   moveq   r0, #PSCI_RET_ALREADY_ON
+   beq out_psci_cpu_on
+
+   cmp r5, #PSCI_CPU_STATUS_ON_PENDING
+   moveq   r0, #PSCI_RET_ON_PENDING
+   beq out_psci_cpu_on
+
+   mov r5, #PSCI_CPU_STATUS_ON_PENDING
+   str r5, [r0]
+   dsb
+
bl  psci_cpu_on_common
 
@ Get DCFG base address
@@ -124,6 +140,12 @@ holdoff_release:
rev r6, r6
str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
 
+   mov r0, r1
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CPU_STATUS_OFFSET
+   mov r5, #PSCI_CPU_STATUS_ON
+   str r5, [r0]
+
isb
dsb
 
@@ -138,6 +160,13 @@ out_psci_cpu_on:
 psci_cpu_off:
bl  psci_cpu_off_common
 
+   bl  psci_get_cpu_id
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CPU_STATUS_OFFSET
+   mov r5, #PSCI_CPU_STATUS_OFF
+   str r5, [r0]
+   dsb
+
 1: wfi
b   1b
 
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 32ae359..535b77f 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -22,6 +22,7 @@
 #define PSCI_PERCPU_STACK_SIZE 0x400
 #define PSCI_TARGET_PC_OFFSET  (PSCI_PERCPU_STACK_SIZE - 4)
 #define PSCI_CONTEXT_ID_OFFSET (PSCI_PERCPU_STACK_SIZE - 8)
+#define PSCI_CPU_STATUS_OFFSET (PSCI_PERCPU_STACK_SIZE - 12)
 
 /* PSCI interfaces */
 #define PSCI_FN_BASE   0x8400
@@ -47,6 +48,10 @@
 #define PSCI_FN_STAT_COUNT PSCI_FN_ID(17)
 
 
+#define PSCI_CPU_STATUS_OFF0
+#define PSCI_CPU_STATUS_ON 1
+#define PSCI_CPU_STATUS_ON_PENDING 2
+
 /* PSCI return values */
 #define PSCI_RET_SUCCESS   0
 #define PSCI_RET_NOT_SUPPORTED (-1)
-- 
2.1.4

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[U-Boot] [PATCH v2 06/11] ARMv7: PSCI: factor out reusable psci_cpu_on_common

[macro . wave . z]

From: Hongbo Zhang 

There are codes for saving target PC and target context ID in each platform
psci_cpu_on routines, these can be factored out as psci_cpu_on_common.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/ls102xa/psci.S | 12 +---
 arch/arm/cpu/armv7/mx7/psci.S | 12 +---
 arch/arm/cpu/armv7/psci.S | 15 +++
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 12 +---
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 13 +
 arch/arm/mach-tegra/psci.S| 12 +---
 6 files changed, 20 insertions(+), 56 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index 1303909..47bcb29 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -36,17 +36,7 @@ psci_cpu_on:
@ r1 = 0xf01
and r1, r1, #0xff
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   sub r0, r0, #PSCI_TARGET_PC_OFFSET
-   str r2, [r0]
-   dsb
-
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
-   str r3, [r0]
-   dsb
+   bl  psci_cpu_on_common
 
@ Get DCFG base address
movwr4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0x)
diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S
index 90b8b9e..c9a7b00 100644
--- a/arch/arm/cpu/armv7/mx7/psci.S
+++ b/arch/arm/cpu/armv7/mx7/psci.S
@@ -29,17 +29,7 @@ psci_arch_init:
 psci_cpu_on:
push{lr}
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   sub r0, r0, #PSCI_TARGET_PC_OFFSET
-   str r2, [r0]
-   dsb
-
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
-   str r3, [r0]
-   dsb
+   bl  psci_cpu_on_common
 
ldr r2, =psci_cpu_entry
bl  imx_cpu_on
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index f476c2c..eb63581 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -175,6 +175,21 @@ ENTRY(psci_enable_smp)
 ENDPROC(psci_enable_smp)
 .weak psci_enable_smp
 
+/* expects target CPU in r1, target PC in r2, target conetxt ID in r3 */
+ENTRY(psci_cpu_on_common)
+   push{lr}
+
+   mov r0, r1
+   bl  psci_get_cpu_stack_top  @ get stack top of target CPU
+   sub r5, r0, #PSCI_TARGET_PC_OFFSET
+   str r2, [r5]@ save target PC
+   sub r5, r0, #PSCI_CONTEXT_ID_OFFSET
+   str r3, [r5]@ save target context ID
+   dsb
+
+   pop {pc}
+ENDPROC(psci_cpu_on_common)
+
 ENTRY(psci_cpu_off_common)
push{lr}
 
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 2c9b078..a94a68d 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -135,17 +135,7 @@ out:   mcr p15, 0, r7, c1, c1, 0
 psci_cpu_on:
push{lr}
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   sub r0, r0, #PSCI_TARGET_PC_OFFSET
-   str r2, [r0]@ store target PC
-   dsb
-
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
-   str r3, [r0]
-   dsb
+   bl  psci_cpu_on_common
 
movwr0, #(SUN6I_CPUCFG_BASE & 0x)
movtr0, #(SUN6I_CPUCFG_BASE >> 16)
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index c1f117a..b0601a7 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -124,18 +124,7 @@ out:   mcr p15, 0, r7, c1, c1, 0
 psci_cpu_on:
push{lr}
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   sub r0, r0, #PSCI_TARGET_PC_OFFSET
-   str r2, [r0]@ store target PC
-   dsb
-
-
-   mov r0, r1
-   bl  psci_get_cpu_stack_top
-   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
-   str r3, [r0]
-   dsb
+   bl  psci_cpu_on_common
 
movwr0, #(SUN7I_CPUCFG_BASE & 0x)
movtr0, #(SUN7I_CPUCFG_BASE >> 16)
diff --git a/arch/arm/mach-tegra/psci.S b/arch/arm/mach-tegra/psci.S
index 3837d95..8fa90ce 100644
--- a/arch/arm/mach-tegra/psci.S
+++ b/arch/arm/mach-tegra/psci.S
@@ -90,17 +90,7 @@ ENDPROC(psci_cpu_off)
 ENTRY(psci_cpu_on)
push{lr}
 
-   mov r0, r1
-   bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   sub r0, r0, #PSCI_TARGET_PC_OFFSET
-   str r2, [r0]@ store target PC
-   dsb
-
-   mov r0, r1
-   bl  

[U-Boot] [PATCH v2 05/11] ARMv7: PSCI: add codes to save context ID for CPU_ON

[macro . wave . z]

From: Hongbo Zhang 

According to latest PSCI specification, the context ID is needed by CPU_ON.
This patch saves context ID to the second lowest address of the stack (next to
where target PC is saved), and restores it to r0 when needed while target CPU
booting up.

This patch in current format is for easier review, there are some lines
duplication with previous saving target PC codes, e.g. codes of calling the
psci_get_cpu_stack_top, this will be optimized by the following patch.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/ls102xa/psci.S | 7 +++
 arch/arm/cpu/armv7/mx7/psci.S | 8 +++-
 arch/arm/cpu/armv7/nonsec_virt.S  | 7 +++
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 7 +++
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 8 
 arch/arm/include/asm/psci.h   | 1 +
 arch/arm/mach-tegra/psci.S| 6 ++
 7 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index e1293ed..1303909 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -27,6 +27,7 @@
 
@ r1 = target CPU
@ r2 = target PC
+   @ r3 = target Conetxt ID
 .globl psci_cpu_on
 psci_cpu_on:
push{lr}
@@ -41,6 +42,12 @@ psci_cpu_on:
str r2, [r0]
dsb
 
+   mov r0, r1
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
+   str r3, [r0]
+   dsb
+
@ Get DCFG base address
movwr4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0x)
movtr4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S
index 02ca076..90b8b9e 100644
--- a/arch/arm/cpu/armv7/mx7/psci.S
+++ b/arch/arm/cpu/armv7/mx7/psci.S
@@ -24,7 +24,7 @@ psci_arch_init:
 
@ r1 = target CPU
@ r2 = target PC
-
+   @ r3 = target Conetxt ID
 .globl psci_cpu_on
 psci_cpu_on:
push{lr}
@@ -35,6 +35,12 @@ psci_cpu_on:
str r2, [r0]
dsb
 
+   mov r0, r1
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
+   str r3, [r0]
+   dsb
+
ldr r2, =psci_cpu_entry
bl  imx_cpu_on
 
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index b7563ed..6566643 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 .arch_extension sec
 .arch_extension virt
@@ -89,6 +90,12 @@ _secure_monitor:
movne   r4, #0
mcrrne  p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero
 1:
+#ifdef CONFIG_ARMV7_PSCI
+   bl  psci_get_cpu_id
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
+   ldr r0, [r0]@ get Context ID in r0
+#endif
mov lr, ip
mov ip, #(F_BIT | I_BIT | A_BIT)@ Set A, I and F
tst lr, #1  @ Check for Thumb PC
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 51241ec..2c9b078 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -130,6 +130,7 @@ out:mcr p15, 0, r7, c1, c1, 0
 
@ r1 = target CPU
@ r2 = target PC
+   @ r3 = target Conetxt ID
 .globl psci_cpu_on
 psci_cpu_on:
push{lr}
@@ -140,6 +141,12 @@ psci_cpu_on:
str r2, [r0]@ store target PC
dsb
 
+   mov r0, r1
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
+   str r3, [r0]
+   dsb
+
movwr0, #(SUN6I_CPUCFG_BASE & 0x)
movtr0, #(SUN6I_CPUCFG_BASE >> 16)
 
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index 50ba355..c1f117a 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -119,6 +119,7 @@ out:mcr p15, 0, r7, c1, c1, 0
 
@ r1 = target CPU
@ r2 = target PC
+   @ r3 = target Conetxt ID
 .globl psci_cpu_on
 psci_cpu_on:
push{lr}
@@ -129,6 +130,13 @@ psci_cpu_on:
str r2, [r0]@ store target PC
dsb
 
+
+   mov r0, r1
+   bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
+   str r3, [r0]
+   dsb
+
movwr0, #(SUN7I_CPUCFG_BASE & 0x)
movtr0, #(SUN7I_CPUCFG_BASE >> 16)
 
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index d0f5d26..d703aeb 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -21,6 +21,7 @@
 /* size of percpu stack, 1kB */
 #define PSCI_PERCPU_STACK_SIZE 0x400
 

[U-Boot] [PATCH v2 02/11] ARM: PSCI: change PSCI related macros definition style

[macro . wave . z]

From: Wang Dongsheng 

Since we are already under the directory of arch/arm/, the prefix ARM_ for
macros isn't so necessary, and with more PSCI interfaces being added later,
there will be much more redundant ARM_ prefixes, what's more, there are no
ARM_/arm_ prefixes for other PSCI variables and functions either, so this patch
updates these macro definitions to make them concise and consistent.

Signed-off-by: Wang Dongsheng 
Signed-off-by: Hongbo Zhang 
---
 arch/arm/cpu/armv7/ls102xa/psci.S |  2 +-
 arch/arm/cpu/armv7/psci.S | 12 ++--
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S |  2 +-
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S |  2 +-
 arch/arm/cpu/armv7/virt-dt.c  |  8 
 arch/arm/include/asm/psci.h   | 24 +---
 arch/arm/mach-tegra/psci.S|  2 +-
 7 files changed, 27 insertions(+), 25 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index cf5cd48..0b067d9 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -99,7 +99,7 @@ holdoff_release:
dsb
 
@ Return
-   mov r0, #ARM_PSCI_RET_SUCCESS
+   mov r0, #PSCI_RET_SUCCESS
 
pop {lr}
bx  lr
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 87c0c0b..e1fcb5d 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -50,7 +50,7 @@ ENTRY(psci_cpu_suspend)
 ENTRY(psci_cpu_off)
 ENTRY(psci_cpu_on)
 ENTRY(psci_migrate)
-   mov r0, #ARM_PSCI_RET_NI@ Return -1 (Not Implemented)
+   mov r0, #PSCI_RET_NOT_SUPPORTED @ Return -1 (Not Supported)
mov pc, lr
 ENDPROC(psci_migrate)
 ENDPROC(psci_cpu_on)
@@ -62,13 +62,13 @@ ENDPROC(psci_cpu_suspend)
 .weak psci_migrate
 
 _psci_table:
-   .word   ARM_PSCI_FN_CPU_SUSPEND
+   .word   PSCI_FN_CPU_SUSPEND
.word   psci_cpu_suspend
-   .word   ARM_PSCI_FN_CPU_OFF
+   .word   PSCI_FN_CPU_OFF
.word   psci_cpu_off
-   .word   ARM_PSCI_FN_CPU_ON
+   .word   PSCI_FN_CPU_ON
.word   psci_cpu_on
-   .word   ARM_PSCI_FN_MIGRATE
+   .word   PSCI_FN_MIGRATE
.word   psci_migrate
.word   0
.word   0
@@ -86,7 +86,7 @@ _smc_psci:
 1: ldr r5, [r4]@ Load PSCI function ID
ldr r6, [r4, #4]@ Load target PC
cmp r5, #0  @ If reach the end, bail out
-   moveq   r0, #ARM_PSCI_RET_INVAL @ Return -2 (Invalid)
+   moveq   r0, #PSCI_RET_INVALID_PARAMS@ Return -2 (Invalid)
beq 2f
cmp r0, r5  @ If not matching, try next entry
addne   r4, r4, #8
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 90b5bfd..ac722e4 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -204,7 +204,7 @@ psci_cpu_on:
orr r6, r6, r4
str r6, [r0, #0x1e4]
 
-   mov r0, #ARM_PSCI_RET_SUCCESS   @ Return PSCI_RET_SUCCESS
+   mov r0, #PSCI_RET_SUCCESS   @ Return PSCI_RET_SUCCESS
pop {pc}
 
 .globl psci_cpu_off
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index e15d587..59d7ff0 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -179,7 +179,7 @@ psci_cpu_on:
orr r6, r6, r4
str r6, [r0, #0x1e4]
 
-   mov r0, #ARM_PSCI_RET_SUCCESS   @ Return PSCI_RET_SUCCESS
+   mov r0, #PSCI_RET_SUCCESS   @ Return PSCI_RET_SUCCESS
pop {pc}
 
 .globl psci_cpu_off
diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
index 32c368f..f1251d1 100644
--- a/arch/arm/cpu/armv7/virt-dt.c
+++ b/arch/arm/cpu/armv7/virt-dt.c
@@ -73,16 +73,16 @@ static int fdt_psci(void *fdt)
tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc");
if (tmp)
return tmp;
-   tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", 
ARM_PSCI_FN_CPU_SUSPEND);
+   tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", PSCI_FN_CPU_SUSPEND);
if (tmp)
return tmp;
-   tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", ARM_PSCI_FN_CPU_OFF);
+   tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", PSCI_FN_CPU_OFF);
if (tmp)
return tmp;
-   tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", ARM_PSCI_FN_CPU_ON);
+   tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", PSCI_FN_CPU_ON);
if (tmp)
return tmp;
-   tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", ARM_PSCI_FN_MIGRATE);
+   tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", PSCI_FN_MIGRATE);
if (tmp)
return tmp;
 #endif
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 

[U-Boot] [PATCH v2 01/11] ARM: PSCI: change PSCI function IDs base and offsets

[macro . wave . z]

From: Wang Dongsheng 

According to PSCI specification v1.0, the PSCI functions should start from
0x8400 for SMC32, this patch changes this base value as well as other
function offset values.

Signed-off-by: Wang Dongsheng 
Signed-off-by: Hongbo Zhang 
---
 arch/arm/include/asm/psci.h | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 128a606..a4a19e3 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -19,13 +19,13 @@
 #define __ARM_PSCI_H__
 
 /* PSCI interface */
-#define ARM_PSCI_FN_BASE   0x95c1ba5e
+#define ARM_PSCI_FN_BASE   0x8400
 #define ARM_PSCI_FN(n) (ARM_PSCI_FN_BASE + (n))
 
-#define ARM_PSCI_FN_CPU_SUSPENDARM_PSCI_FN(0)
-#define ARM_PSCI_FN_CPU_OFFARM_PSCI_FN(1)
-#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2)
-#define ARM_PSCI_FN_MIGRATEARM_PSCI_FN(3)
+#define ARM_PSCI_FN_CPU_SUSPENDARM_PSCI_FN(1)
+#define ARM_PSCI_FN_CPU_OFFARM_PSCI_FN(2)
+#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(3)
+#define ARM_PSCI_FN_MIGRATEARM_PSCI_FN(5)
 
 #define ARM_PSCI_RET_SUCCESS   0
 #define ARM_PSCI_RET_NI(-1)
-- 
2.1.4

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[U-Boot] [PATCH v2 04/11] ARMv7: PSCI: update the place of saving target PC

[macro . wave . z]

From: Hongbo Zhang 

The legacy code reserves one word in each stack for saving target PC, but it
isn't used, the target PC is still saved to where the stack top pointer points.
This patch relocates the place for saving target PC to the lowest address of
each stack, convinience is that we can save more contents if needed ilater next
to saved target PC without re-adjust the stack top pointer.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/ls102xa/psci.S | 1 +
 arch/arm/cpu/armv7/mx7/psci.S | 1 +
 arch/arm/cpu/armv7/psci.S | 3 ++-
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 3 ++-
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 3 ++-
 arch/arm/include/asm/psci.h   | 1 +
 arch/arm/mach-tegra/psci.S| 3 ++-
 7 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S 
b/arch/arm/cpu/armv7/ls102xa/psci.S
index 0b067d9..e1293ed 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -37,6 +37,7 @@ psci_cpu_on:
 
mov r0, r1
bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_TARGET_PC_OFFSET
str r2, [r0]
dsb
 
diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S
index 34c6ab3..02ca076 100644
--- a/arch/arm/cpu/armv7/mx7/psci.S
+++ b/arch/arm/cpu/armv7/mx7/psci.S
@@ -31,6 +31,7 @@ psci_cpu_on:
 
mov r0, r1
bl  psci_get_cpu_stack_top
+   sub r0, r0, #PSCI_TARGET_PC_OFFSET
str r2, [r0]
dsb
 
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 42116e8..f476c2c 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -215,7 +215,8 @@ ENTRY(psci_cpu_entry)
 
bl  psci_get_cpu_id @ CPU ID => r0
bl  psci_get_cpu_stack_top  @ stack top => r0
-   ldr r0, [r0]@ target PC at stack top
+   sub r0, r0, #PSCI_TARGET_PC_OFFSET
+   ldr r0, [r0]@ get target PC
b   _do_nonsec_entry
 ENDPROC(psci_cpu_entry)
 
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index ac722e4..51241ec 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -136,7 +136,8 @@ psci_cpu_on:
 
mov r0, r1
bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   str r2, [r0]@ store target PC at stack top
+   sub r0, r0, #PSCI_TARGET_PC_OFFSET
+   str r2, [r0]@ store target PC
dsb
 
movwr0, #(SUN6I_CPUCFG_BASE & 0x)
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index 59d7ff0..50ba355 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -125,7 +125,8 @@ psci_cpu_on:
 
mov r0, r1
bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   str r2, [r0]@ store target PC at stack top
+   sub r0, r0, #PSCI_TARGET_PC_OFFSET
+   str r2, [r0]@ store target PC
dsb
 
movwr0, #(SUN7I_CPUCFG_BASE & 0x)
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 47a2ea4..d0f5d26 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -20,6 +20,7 @@
 
 /* size of percpu stack, 1kB */
 #define PSCI_PERCPU_STACK_SIZE 0x400
+#define PSCI_TARGET_PC_OFFSET  (PSCI_PERCPU_STACK_SIZE - 4)
 
 /* PSCI interfaces */
 #define PSCI_FN_BASE   0x8400
diff --git a/arch/arm/mach-tegra/psci.S b/arch/arm/mach-tegra/psci.S
index 5f326c9..037c142 100644
--- a/arch/arm/mach-tegra/psci.S
+++ b/arch/arm/mach-tegra/psci.S
@@ -92,7 +92,8 @@ ENTRY(psci_cpu_on)
 
mov r0, r1
bl  psci_get_cpu_stack_top  @ get stack top of target CPU
-   str r2, [r0]@ store target PC at stack top
+   sub r0, r0, #PSCI_TARGET_PC_OFFSET
+   str r2, [r0]@ store target PC
dsb
 
ldr r6, =TEGRA_RESET_EXCEPTION_VECTOR
-- 
2.1.4

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[U-Boot] [PATCH v2 03/11] ARMv7: PSCI: update function psci_get_cpu_stack_top

[macro . wave . z]

From: Hongbo Zhang 

There are issues of legacy fuction psci_get_cpu_stack_top:

First, because the stack grows in descending address order, it is better the
stack starts from page end or some similiar address, but currently the
algorithm is based on address of page start, if so some stack starts at page
start and then grows into the next page only after pushing one word.
This patch recalculate stacks based on address of page end.

Second, the current algorithm arranges stacks from an fixed adress towards
psci_text_end, if there are more CPUs, the stacks will overlap with psci text
segment and even other segments.
This patch places stacks from psci text segment towards highter address, and
all the stack space is reserved, so overlap can be avoided.

Third, even there is one word reserved in each stack for saving target PC, but
this reserved space isn't used at all, the target PC is still saved to where
the stack top pointer points.
This patch doesn't reserve this word as before, new way of saving target PC
will be introduced in following patch.

Signed-off-by: Hongbo Zhang 
Signed-off-by: Wang Dongsheng 
---
 arch/arm/cpu/armv7/psci.S| 13 ++---
 arch/arm/cpu/armv7/virt-dt.c |  9 +++--
 arch/arm/include/asm/psci.h  |  2 ++
 3 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index e1fcb5d..42116e8 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -196,16 +196,15 @@ ENDPROC(psci_cpu_off_common)
 
 @ expects CPU ID in r0 and returns stack top in r0
 ENTRY(psci_get_cpu_stack_top)
-   mov r5, #0x400  @ 1kB of stack per CPU
-   mul r0, r0, r5
+   mov r5, #PSCI_PERCPU_STACK_SIZE @ 1kB of stack per CPU
+   add r0, r0, #1
+   mul r0, r0, r5  @ offset of each stack
 
ldr r5, =psci_text_end  @ end of monitor text
-   add r5, r5, #0x2000 @ Skip two pages
-   lsr r5, r5, #12 @ Align to start of page
-   lsl r5, r5, #12
-   sub r5, r5, #4  @ reserve 1 word for target PC
-   sub r0, r5, r0  @ here's our stack!
+   orr r5, r5, #0xff0  @ align to end of page
+   orr r5, r5, #0x00c
 
+   add r0, r5, r0  @ here's our stack!
bx  lr
 ENDPROC(psci_get_cpu_stack_top)
 
diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
index f1251d1..4953f27 100644
--- a/arch/arm/cpu/armv7/virt-dt.c
+++ b/arch/arm/cpu/armv7/virt-dt.c
@@ -124,9 +124,14 @@ int psci_update_dt(void *fdt)
return 0;
 #endif
 #ifndef CONFIG_ARMV7_SECURE_BASE
+   size_t sz = __secure_end - __secure_start;
+#ifdef CONFIG_ARMV7_PSCI
+   sz += CONFIG_MAX_CPUS * PSCI_PERCPU_STACK_SIZE;
+   /* margin to align psci_text_end to page end*/
+   sz += 0x1000;
+#endif
/* secure code lives in RAM, keep it alive */
-   fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
-   __secure_end - __secure_start);
+   fdt_add_mem_rsv(fdt, (unsigned long)__secure_start, sz);
 #endif
 
return fdt_psci(fdt);
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 7c3450c..47a2ea4 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -18,6 +18,8 @@
 #ifndef __ARM_PSCI_H__
 #define __ARM_PSCI_H__
 
+/* size of percpu stack, 1kB */
+#define PSCI_PERCPU_STACK_SIZE 0x400
 
 /* PSCI interfaces */
 #define PSCI_FN_BASE   0x8400
-- 
2.1.4

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[U-Boot] [PATCH v2 00/11] ARMv7: PSCI: add PSCI v1.0 support

[macro . wave . z]

From: Hongbo Zhang 

This patch set contains two parts:
ARMv7 PSCI common framework: fix some issues and add v1.0 support
NXP (was Freescale) LS102XA: codes enhancement and add v1.0 implementation

Changes since v1:
- re-organize psci_cpu_on_common, this code should be called by each platform's
psci_cpu_on, should not be a function calling each psci_cpu_on, all related
functions are updated due to this change
- update some registers usage, e.g. if r10 is used without push/pop, u-boot
cannot launch rt-kernel
- update some comments to be clearer, re-organize all patches for easier review
- add patch to check already_on or on_pending for LS102XA


Hongbo Zhang:
Wang Dongsheng:
  ARMv7: PSCI: update function psci_get_cpu_stack_top
  ARMv7: PSCI: update the place of saving target PC
  ARMv7: PSCI: add codes to save context ID for CPU_ON
  ARMv7: PSCI: factor out reusable psci_cpu_on_common
  ARMv7: PSCI: add PSCI v1.0 functions skeleton
  ARMv7: PSCI: ls102xa: check target CPU ID before further operations
  ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON
  ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention
  ARMv7: PSCI: ls102xa: move secure text section into OCRAM
  ARM: PSCI: change PSCI function IDs base and offsets
  ARM: PSCI: change PSCI related macros definition style

 arch/arm/cpu/armv7/ls102xa/psci.S  | 177 +++--
 arch/arm/cpu/armv7/mx7/psci.S  |   7 +-
 arch/arm/cpu/armv7/nonsec_virt.S   |   7 ++
 arch/arm/cpu/armv7/psci.S  | 113 +++---
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S  |   8 +-
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S  |   8 +-
 arch/arm/cpu/armv7/virt-dt.c   |  54 ++---
 arch/arm/include/asm/arch-ls102xa/config.h |   3 +-
 arch/arm/include/asm/psci.h|  62 +++---
 arch/arm/mach-tegra/psci.S |   7 +-
 board/freescale/ls1021aqds/Makefile|   1 +
 board/freescale/ls1021aqds/psci.S  |  36 ++
 board/freescale/ls1021atwr/Makefile|   1 +
 board/freescale/ls1021atwr/psci.S  |  28 +
 include/configs/ls1021aqds.h   |   3 +
 include/configs/ls1021atwr.h   |   3 +
 16 files changed, 449 insertions(+), 69 deletions(-)
 create mode 100644 board/freescale/ls1021aqds/psci.S
 create mode 100644 board/freescale/ls1021atwr/psci.S

-- 
2.1.4

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