Re: [U-Boot] [PATCH v2 2/2] arm: ls102xa: Enable regulation of outstanding read transactions for slave interface S2
-Original Message- From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Alison Wang Sent: Thursday, March 12, 2015 9:02 AM To: Sun York-R58495; u-boot@lists.denx.de; Jin Zhengxiong-R64188 Subject: [U-Boot] [PATCH v2 2/2] arm: ls102xa: Enable regulation of outstanding read transactions for slave interface S2 Patch subject is too long. Please try to make it = 78 charecters. This patch will enable regulation of outstanding read transactions for slave interface S2 for silicon VER1.0. It is already a patch. So please avoid This patch --prabhakar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] powerpc/t1023rdb: Add T1023 RDB board support
-Original Message- From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Shengzhou Liu Sent: Monday, March 16, 2015 3:07 PM To: u-boot@lists.denx.de; Sun York-R58495 Subject: [U-Boot] [PATCH v3] powerpc/t1023rdb: Add T1023 RDB board support T1023RDB is a Freescale Reference Design Board that hosts the T1023 SoC. T1023RDB board Overview --- - T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 without ECC - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - one 1G RGMII port on-board(RTL8211F PHY) - one 1G SGMII port on-board(RTL8211F PHY) - one 2.5G SGMII port on-board(AQR105 PHY) - PCIe: Two Mini-PCIe connectors on-board. - SerDes: 4 lanes up to 10.3125GHz - NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash - NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash - eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash. - USB: one Type-A USB 2.0 port with internal PHY - eSDHC: support SD/MMC and eMMC card - 256Kbit M24256 I2C EEPROM - RTC: Real-time clock DS1339 on I2C bus - UART: one serial port on-board with RJ45 connector - Debugging: JTAG/COP for T1023 debugging As well updated T1024RDB to add T1023RDB. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- v3: updated readme. v2: updated the printout of serdes refclk. board/freescale/t102xrdb/Makefile | 2 +- board/freescale/t102xrdb/README | 96 ++ --- board/freescale/t102xrdb/eth_t102xrdb.c | 23 ++-- board/freescale/t102xrdb/t1023_rcw.cfg | 8 +++ board/freescale/t102xrdb/t102xrdb.c | 93 ++-- board/freescale/t102xrdb/t102xrdb.h | 4 +- include/configs/T102xRDB.h | 73 + 7 files changed, 262 insertions(+), 37 deletions(-) create mode 100644 board/freescale/t102xrdb/t1023_rcw.cfg diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile index a0cf8f6..0520066 100644 --- a/board/freescale/t102xrdb/Makefile +++ b/board/freescale/t102xrdb/Makefile @@ -8,7 +8,7 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else obj-y += t102xrdb.o -obj-y += cpld.o +obj-$(CONFIG_T1024RDB) += cpld.o obj-y += eth_t102xrdb.o obj-$(CONFIG_PCI) += pci.o endif diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README index 2b17f50..35edfbd 100644 --- a/board/freescale/t102xrdb/README +++ b/board/freescale/t102xrdb/README @@ -98,6 +98,29 @@ T1024RDB board Overview - Four I2C ports +T1023RDB board Overview +--- +- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz +- CoreNet fabric supporting coherent and noncoherent transactions with + prioritization and bandwidth allocation +- SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC +- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC +- Ethernet interfaces: + - one 1G RGMII port on-board(RTL8211FS PHY) + - one 1G SGMII port on-board(RTL8211FS PHY) + - one 2.5G SGMII port on-board(AQR105 PHY) +- PCIe: Two Mini-PCIe connectors on-board. +- SerDes: 4 lanes up to 10.3125GHz +- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash +- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash +- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash. +- USB: one Type-A USB 2.0 port with internal PHY +- eSDHC: support SD/MMC and eMMC card +- 256Kbit M24256 I2C EEPROM +- RTC: Real-time clock DS1339U on I2C bus +- UART: one serial port on-board with RJ45 connector +- Debugging: JTAG/COP for T1023 debugging + Memory map on T1024RDB -- Start Address End Address Description Size @@ -124,22 +147,32 @@ Start Address End Address Definition Max size 0xEFF2 0xEFF3 u-boot env (current bank)128KB 0xEFF0 0xEFF1 FMAN Ucode (current bank)128KB 0xEFE0 0xEFE3 QE firmware (current bank) 256KB -0xED30 0xEFEF rootfs (alt bank)44MB +0xED30 0xEFDF rootfs (alt bank)44MB +0xED00 0xED2F Guest image #3 (alternate bank) 3MB +0xECD0 0xECFF Guest image #2 (alternate bank) 3MB +0xECA0 0xECCF Guest image #1 (alternate bank) 3MB +0xEC90 0xEC9F HV config device tree(alt bank) 1MB 0xEC80 0xEC8F Hardware device tree (alt bank) 1MB -0xEC02 0xEC7F Linux.uImage (alt bank) 7MB + 875KB +0xEC70 0xEC7F HV.uImage (alternate bank) 1MB +0xEC02 0xEC6F Linux.uImage (alt bank) ~7MB 0xEC00 0xEC01 RCW
Re: [U-Boot] [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support
-Original Message- From: Sun York-R58495 Sent: Tuesday, March 24, 2015 9:15 PM To: Wood Scott-B07421 Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579 Subject: Re: [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support On 03/23/2015 06:34 PM, Scott Wood wrote: On Fri, 2015-03-20 at 19:28 -0700, York Sun wrote: +Generage NAND image +--- +To form the NAND image, build u-boot with LS2085AQDS_NAND_defconfig. +Append u-boot-with-spl.bin after RCW image. The RCW image should +have these PBI commands + +1) CCSR 4-byte write to 0x00e00404, data=0x +2) CCSR 4-byte write to 0x00e00400, data=0x1800a000 +3) Block Copy: SRC=0x0104, SRC_ADDR=0x00c0, +DEST_ADDR=0x1800a000, +BLOCK_SIZE=0x00014000 The RCW source should probably be 0x107, not 0x104. Bit 0x002 requests first/last bad block markers rather than first/second, and bit 0x001 enables ECC. Also, this documentation is LS2085A-specific (most of it will probably apply to all chips with this chassis), not RDB or QDS specific, with the exception of the RCW source ID which depends on the specific NAND chip. It would be better to put it in one place rather than duplicate it, with a table of RCW source IDs for each board. Also, you have RDB as having SRC=0x104, but that (as well as 0x107) is for a 2K-page NAND chip. RDB has a 4K-page NAND, so I think you want RCW source to be 0x111. for RDB. I think RCW source should be 0x119. bad block at first/last page(ONFI requirement) and 4bit ECC -prabhakar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V4] mpc85xx/T104xD4RDB: Add T104xD4RDB boards support
-Original Message-
From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Vijay Rai
Sent: Wednesday, March 18, 2015 2:50 PM
To: Sun York-R58495; u-boot@lists.denx.de
Subject: [U-Boot] [PATCH V4] mpc85xx/T104xD4RDB: Add T104xD4RDB boards
support
T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
T1040D4RDB is re-designed T1040RDB board with following changes :
- Support of DDR4 memory
- Support of 0x66 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
- Support of QE-TDM
Similarily T1042D4RDB is a Freescale reference board that hosts the T1040
SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
- Support of DDR4 memory
- Support for 0x86 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 3 SGMII on DTSEC1, DTSEC2 DTSEC3
- Support of DIU
Signed-off-by: Vijay Rai vijay@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
changes from v2 :
- removes checkpatch error
Please maintain version history while sending the patch revision.
board/freescale/t104xrdb/MAINTAINERS |8 ++
board/freescale/t104xrdb/ddr.c |6
board/freescale/t104xrdb/ddr.h | 13 -
board/freescale/t104xrdb/eth.c | 20 +++--
board/freescale/t104xrdb/t1040d4_rcw.cfg |7 +
board/freescale/t104xrdb/t1042d4_rcw.cfg |7 +
board/freescale/t104xrdb/t104xrdb.c | 17 +--
configs/T1040D4RDB_NAND_defconfig|5
configs/T1040D4RDB_SDCARD_defconfig |5
configs/T1040D4RDB_SPIFLASH_defconfig|5
configs/T1040D4RDB_defconfig |4 +++
configs/T1042D4RDB_NAND_defconfig|5
configs/T1042D4RDB_SDCARD_defconfig |5
configs/T1042D4RDB_SPIFLASH_defconfig|5
configs/T1042D4RDB_defconfig |4 +++
include/configs/T104xRDB.h | 46
--
16 files changed, 148 insertions(+), 14 deletions(-) create mode 100644
board/freescale/t104xrdb/t1040d4_rcw.cfg
create mode 100644 board/freescale/t104xrdb/t1042d4_rcw.cfg
create mode 100644 configs/T1040D4RDB_NAND_defconfig create mode
100644 configs/T1040D4RDB_SDCARD_defconfig
create mode 100644 configs/T1040D4RDB_SPIFLASH_defconfig
create mode 100644 configs/T1040D4RDB_defconfig create mode 100644
configs/T1042D4RDB_NAND_defconfig create mode 100644
configs/T1042D4RDB_SDCARD_defconfig
create mode 100644 configs/T1042D4RDB_SPIFLASH_defconfig
create mode 100644 configs/T1042D4RDB_defconfig
diff --git a/board/freescale/t104xrdb/MAINTAINERS
b/board/freescale/t104xrdb/MAINTAINERS
index 13d9be9..32e044f 100644
--- a/board/freescale/t104xrdb/MAINTAINERS
+++ b/board/freescale/t104xrdb/MAINTAINERS
@@ -6,7 +6,13 @@ F: include/configs/T104xRDB.h
F: configs/T1040RDB_defconfig
F: configs/T1040RDB_NAND_defconfig
F: configs/T1040RDB_SPIFLASH_defconfig
+F: configs/T1040D4RDB_defconfig
+F: configs/T1040D4RDB_NAND_defconfig
+F: configs/T1040D4RDB_SPIFLASH_defconfig
F: configs/T1042RDB_defconfig
+F: configs/T1042D4RDB_defconfig
+F: configs/T1042D4RDB_NAND_defconfig
+F: configs/T1042D4RDB_SPIFLASH_defconfig
F: configs/T1042RDB_PI_defconfig
F: configs/T1042RDB_PI_NAND_defconfig
F: configs/T1042RDB_PI_SPIFLASH_defconfig
@@ -15,6 +21,8 @@ T1040RDB_SDCARD BOARD
#M: -
S: Maintained
F: configs/T1040RDB_SDCARD_defconfig
+F: configs/T1040D4RDB_SDCARD_defconfig
+F: configs/T1042D4RDB_SDCARD_defconfig
F: configs/T1042RDB_PI_SDCARD_defconfig
T1040RDB_SECURE_BOOT BOARD
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
index e1148e5..3c4eabf 100644
--- a/board/freescale/t104xrdb/ddr.c
+++ b/board/freescale/t104xrdb/ddr.c
@@ -91,8 +91,14 @@ found:
popts-zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
+#ifdef CONFIG_SYS_FSL_DDR4
+ popts-ddr_cdr1 = DDR_CDR1_DHC_EN |
DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+ popts-ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+ DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+#else
popts-ddr_cdr1 = DDR_CDR1_DHC_EN |
DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts-ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
}
#if defined(CONFIG_DEEP_SLEEP)
diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h
index ab1c32d..eb6ec70 100644
--- a/board/freescale/t104xrdb/ddr.h
+++ b/board/freescale/t104xrdb/ddr.h
@@ -28,6 +28,13 @@ static const struct board_specific_parameters udimm0[] =
{
* num| hi| rank| clk| wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2
*/
+#ifdef CONFIG_SYS_FSL_DDR4
+ {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
+ {2, 1900, 0, 4,
Re: [U-Boot] [PATCH v2] T2080QDS/PCIe: Soft Reset PCIe for down-training issue
Hi Zhao,
-Original Message-
From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Zhao Qiang
Sent: Wednesday, March 11, 2015 2:42 PM
To: u-boot@lists.denx.de; Sun York-R58495
Cc: Zhao Qiang-B45475
Subject: [U-Boot] [PATCH v2] T2080QDS/PCIe: Soft Reset PCIe for down-training
issue
T2080QDS PEX1/Slot#1 will down-train from x4 to x2, Soft reset PCIe can fix
this
issue, this is a workaround.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
changes for v2
- modify the commit message
drivers/pci/fsl_pci_init.c | 17 + include/configs/T208xQDS.h
| 1 +
2 files changed, 18 insertions(+)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index
231b075..327fa7d 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -481,6 +481,23 @@ void fsl_pci_init(struct pci_controller *hose, struct
fsl_pci_info *pci_info) #endif
}
+#ifdef CONFIG_FSL_PCIE_T2080QDS_RESET
+ int i;
+ /* assert PCIe reset */
+ setbits_be32(pci-pdb_stat, 0x0800);
+ (void) in_be32(pci-pdb_stat);
+ udelay(1000);
+ /* clear PCIe reset */
+ clrbits_be32(pci-pdb_stat, 0x0800);
+ asm(sync;isync);
+ for (i = 0; i 100 ltssm PCI_LTSSM_L0; i++) {
+ pci_hose_read_config_word(hose, dev, PCI_LTSSM,
+ ltssm);
+ udelay(1000);
+ }
+
+#endif
+
#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
if (enabled == 0) {
serdes_corenet_t *srds_regs = (void
*)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index
395472b..851b4f9 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -558,6 +558,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_PCIE2 /* PCIE controler 2 */
#define CONFIG_PCIE3 /* PCIE controler 3 */
#define CONFIG_PCIE4 /* PCIE controler 4 */
+#define CONFIG_FSL_PCIE_T2080QDS_RESET
do we really require this new define?
Can we not manage with CONFIG_FSL_PCIE_RESET?
-prabhakar
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] FW: [PATCH] T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issue
Resending as some issue in my mail-box.
Regards,
Prabhakar
-Original Message-
From: Kushwaha Prabhakar-B32579
Sent: Wednesday, March 11, 2015 10:01 AM
To: 'Zhao Qiang'; u-boot@lists.denx.de; Sun York-R58495
Subject: RE: [U-Boot] [PATCH] T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for
down-training issue
Hi Zhao,
Can you please rephrase the subject.
No need to mention T2080QDS twice in the subject
-Original Message-
From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Zhao
Qiang
Sent: Tuesday, March 10, 2015 2:55 PM
To: u-boot@lists.denx.de; Sun York-R58495
Cc: Zhao Qiang-B45475
Subject: [U-Boot] [PATCH] T2080QDS/PCIe: Soft Reset PCIe on T2080QDS
for down-training issue
T2080QDS PEX1/Slot#1 will down-train from x4 to x2, with SRDS_PRTCL_S1
=
0x66 and SRDS_PRTCL_S2 = 0x15.
Soft reset PCIe can fix this issue, this is a workaround.
Can you please rephrase the description.
is this issue only occur with mentioned protocol or other SerDes protocol has
not been tested?
Signed-off-by: Zhao Qiang b45...@freescale.com
---
drivers/pci/fsl_pci_init.c | 17 +
include/configs/T208xQDS.h
| 1 +
2 files changed, 18 insertions(+)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 231b075..327fa7d 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -481,6 +481,23 @@ void fsl_pci_init(struct pci_controller *hose,
struct fsl_pci_info *pci_info) #endif
}
+#ifdef CONFIG_FSL_PCIE_T2080QDS_RESET
+ int i;
+ /* assert PCIe reset */
+ setbits_be32(pci-pdb_stat, 0x0800);
+ (void) in_be32(pci-pdb_stat);
+ udelay(1000);
+ /* clear PCIe reset */
+ clrbits_be32(pci-pdb_stat, 0x0800);
+ asm(sync;isync);
+ for (i = 0; i 100 ltssm PCI_LTSSM_L0; i++) {
+ pci_hose_read_config_word(hose, dev, PCI_LTSSM,
+ ltssm);
+ udelay(1000);
+ }
+
+#endif
+
#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
if (enabled == 0) {
serdes_corenet_t *srds_regs = (void
*)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index
395472b..851b4f9 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -558,6 +558,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_PCIE2 /* PCIE controler 2 */
#define CONFIG_PCIE3 /* PCIE controler 3 */
#define CONFIG_PCIE4 /* PCIE controler 4 */
+#define CONFIG_FSL_PCIE_T2080QDS_RESET
As your patch is reseting PCIe independent of SerDes Protocols What about
defining CONFIG_FSL_PCIE_RESET
Regards,
Prabhakar
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issue
Hi Zhao,
Can you please rephrase the subject.
No need to mention T2080QDS twice in the subject
-Original Message-
From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Zhao Qiang
Sent: Tuesday, March 10, 2015 2:55 PM
To: u-boot@lists.denx.de; Sun York-R58495
Cc: Zhao Qiang-B45475
Subject: [U-Boot] [PATCH] T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for
down-training issue
T2080QDS PEX1/Slot#1 will down-train from x4 to x2, with SRDS_PRTCL_S1 =
0x66 and SRDS_PRTCL_S2 = 0x15.
Soft reset PCIe can fix this issue, this is a workaround.
Can you please rephrase the description.
is this issue only occur with mentioned protocol or other SerDes protocol has
not been tested?
Signed-off-by: Zhao Qiang b45...@freescale.com
---
drivers/pci/fsl_pci_init.c | 17 + include/configs/T208xQDS.h
| 1 +
2 files changed, 18 insertions(+)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index
231b075..327fa7d 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -481,6 +481,23 @@ void fsl_pci_init(struct pci_controller *hose, struct
fsl_pci_info *pci_info) #endif
}
+#ifdef CONFIG_FSL_PCIE_T2080QDS_RESET
+ int i;
+ /* assert PCIe reset */
+ setbits_be32(pci-pdb_stat, 0x0800);
+ (void) in_be32(pci-pdb_stat);
+ udelay(1000);
+ /* clear PCIe reset */
+ clrbits_be32(pci-pdb_stat, 0x0800);
+ asm(sync;isync);
+ for (i = 0; i 100 ltssm PCI_LTSSM_L0; i++) {
+ pci_hose_read_config_word(hose, dev, PCI_LTSSM,
+ ltssm);
+ udelay(1000);
+ }
+
+#endif
+
#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
if (enabled == 0) {
serdes_corenet_t *srds_regs = (void
*)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index
395472b..851b4f9 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -558,6 +558,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_PCIE2 /* PCIE controler 2 */
#define CONFIG_PCIE3 /* PCIE controler 3 */
#define CONFIG_PCIE4 /* PCIE controler 4 */
+#define CONFIG_FSL_PCIE_T2080QDS_RESET
As your patch is reseting PCIe independent of SerDes Protocols
What about defining CONFIG_FSL_PCIE_RESET
Regards,
Prabhakar
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issue
Resending because some issue in my mail-box.
Regards,
Prabhakar
-Original Message-
From: Kushwaha Prabhakar-B32579
Sent: Wednesday, March 11, 2015 10:01 AM
To: 'Zhao Qiang'; u-boot@lists.denx.de; Sun York-R58495
Subject: RE: [U-Boot] [PATCH] T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for
down-training issue
Hi Zhao,
Can you please rephrase the subject.
No need to mention T2080QDS twice in the subject
-Original Message-
From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Zhao
Qiang
Sent: Tuesday, March 10, 2015 2:55 PM
To: u-boot@lists.denx.de; Sun York-R58495
Cc: Zhao Qiang-B45475
Subject: [U-Boot] [PATCH] T2080QDS/PCIe: Soft Reset PCIe on T2080QDS
for down-training issue
T2080QDS PEX1/Slot#1 will down-train from x4 to x2, with SRDS_PRTCL_S1
=
0x66 and SRDS_PRTCL_S2 = 0x15.
Soft reset PCIe can fix this issue, this is a workaround.
Can you please rephrase the description.
is this issue only occur with mentioned protocol or other SerDes protocol has
not been tested?
Signed-off-by: Zhao Qiang b45...@freescale.com
---
drivers/pci/fsl_pci_init.c | 17 +
include/configs/T208xQDS.h
| 1 +
2 files changed, 18 insertions(+)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 231b075..327fa7d 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -481,6 +481,23 @@ void fsl_pci_init(struct pci_controller *hose,
struct fsl_pci_info *pci_info) #endif
}
+#ifdef CONFIG_FSL_PCIE_T2080QDS_RESET
+ int i;
+ /* assert PCIe reset */
+ setbits_be32(pci-pdb_stat, 0x0800);
+ (void) in_be32(pci-pdb_stat);
+ udelay(1000);
+ /* clear PCIe reset */
+ clrbits_be32(pci-pdb_stat, 0x0800);
+ asm(sync;isync);
+ for (i = 0; i 100 ltssm PCI_LTSSM_L0; i++) {
+ pci_hose_read_config_word(hose, dev, PCI_LTSSM,
+ ltssm);
+ udelay(1000);
+ }
+
+#endif
+
#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
if (enabled == 0) {
serdes_corenet_t *srds_regs = (void
*)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index
395472b..851b4f9 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -558,6 +558,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_PCIE2 /* PCIE controler 2 */
#define CONFIG_PCIE3 /* PCIE controler 3 */
#define CONFIG_PCIE4 /* PCIE controler 4 */
+#define CONFIG_FSL_PCIE_T2080QDS_RESET
As your patch is reseting PCIe independent of SerDes Protocols What about
defining CONFIG_FSL_PCIE_RESET
Regards,
Prabhakar
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
