Re: [PATCH] board: beagleplay: Fix the bootpart to pick from root partition
On Mon, Jun 17, 2024 at 8:53 AM Simon Glass wrote:
>
> Hi Dhruva,
>
> On Thu, 13 Jun 2024 at 02:06, Dhruva Gole wrote:
> >
> > The Kernel Image and DTB files are supposed to be picked from the rootfs
> > of the SD Card, this fails in legacy boot flow because bootpart is set
> > to 1:1. Fix it.
> >
> > Fixes: a200f428b5b21 ("board: ti: am62x: Add am62x_beagleplay_* defconfigs
> > and env file")
> > Signed-off-by: Dhruva Gole
> > ---
> > board/beagle/beagleplay/beagleplay.env | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
>
> What is the legacy boot flow?
Here's the fun part. From BeagleBoard.org, all BeaglePlay's
manufactured by Seeed has the eMMC booting via extlinux.conf. All
BeagleBoard.org images use extlinux.conf by default for this hardware.
Dhruva's just looking to make sure it works with TI's currently
released sdk's. (So last year, and this quarter's releases..)
Regards,
--
Robert Nelson
https://rcn-ee.com/
Re: [PATCH] board: beagleplay: Fix the bootpart to pick from root partition
On Fri, Jun 14, 2024 at 1:04 AM Dhruva Gole wrote: > > Robert, > > On Jun 13, 2024 at 16:51:24 -0500, Robert Nelson wrote: > > On Thu, Jun 13, 2024 at 4:47 PM Robert Nelson > > wrote: > > > > > > On Thu, Jun 13, 2024 at 3:06 AM Dhruva Gole wrote: > > > > > > > > The Kernel Image and DTB files are supposed to be picked from the rootfs > > > > of the SD Card, this fails in legacy boot flow because bootpart is set > > > > to 1:1. Fix it. > > > > > > and where is that rule defined? > > > > > > Production boards ship with Kernel Image and DTB's in the 1st fat > > > partition.. > > > > Besides, u-boot should scan for extlinux.conf on "any" partition. > > I can see where you come from, and I agree on the above points when it > comes to stdboot. > However when a user wishes to use legacy boot, and in the case there > isn't extlinux.conf in such a case u-boot will rely on information in > the env file (please correct me if my understanding is wrong). > > The env file says: > bootdir=/boot > > Thus u-boot ends up looking for Image and dtb in /boot/Image under BOOT > partition, and ultimately fails, because the /boot/Image path is > generally found inside the root partition ie. 1:2 > > The idea of this patch is to keep support for such legacy boot alive, if > you feel there's another way to do this feel free to suggest. For BeagleBoard.org we never used the legacy boot path on this target (or BeagleBone-AI64), this was put in place mostly for TI's u-boot scripts. ;) Regards, -- Robert Nelson https://rcn-ee.com/
Re: [PATCH] board: beagleplay: Fix the bootpart to pick from root partition
On Sat, Jun 15, 2024 at 8:55 PM Bryan Brattlof wrote:
>
> On June 13, 2024 thus sayeth Dhruva Gole:
> > The Kernel Image and DTB files are supposed to be picked from the rootfs
> > of the SD Card, this fails in legacy boot flow because bootpart is set
> > to 1:1. Fix it.
> >
> > Fixes: a200f428b5b21 ("board: ti: am62x: Add am62x_beagleplay_*
> > defconfigs and env file")
> > Signed-off-by: Dhruva Gole
> > ---
> > board/beagle/beagleplay/beagleplay.env | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/board/beagle/beagleplay/beagleplay.env
> > b/board/beagle/beagleplay/beagleplay.env
> > index bbf6b925d02c..190181c8ad0c 100644
> > --- a/board/beagle/beagleplay/beagleplay.env
> > +++ b/board/beagle/beagleplay/beagleplay.env
> > @@ -11,7 +11,7 @@ set_led_state_start_load=led led-0 on; led led-1 off;
> > led led-2 on; led led-3 off; led led-4 on
> > boot=mmc
> > mmcdev=1
> > -bootpart=1:1
> > +bootpart=1:2
> > bootdir=/boot
> > boot_targets=mmc1 mmc0
> > bootmeths=script extlinux efi pxe
>
> Shouldn't the fix be to just drop 'script' from bootmeths. These TI
> scripts needed to go away years ago.
I agree! nuke the non bootmeth's. ;)
Regards,
--
Robert Nelson
https://rcn-ee.com/
Re: [PATCH] board: beagleplay: Fix the bootpart to pick from root partition
On Thu, Jun 13, 2024 at 4:47 PM Robert Nelson wrote: > > On Thu, Jun 13, 2024 at 3:06 AM Dhruva Gole wrote: > > > > The Kernel Image and DTB files are supposed to be picked from the rootfs > > of the SD Card, this fails in legacy boot flow because bootpart is set > > to 1:1. Fix it. > > and where is that rule defined? > > Production boards ship with Kernel Image and DTB's in the 1st fat partition.. Besides, u-boot should scan for extlinux.conf on "any" partition. Regards, -- Robert Nelson https://rcn-ee.com/
Re: [PATCH] board: beagleplay: Fix the bootpart to pick from root partition
On Thu, Jun 13, 2024 at 3:06 AM Dhruva Gole wrote: > > The Kernel Image and DTB files are supposed to be picked from the rootfs > of the SD Card, this fails in legacy boot flow because bootpart is set > to 1:1. Fix it. and where is that rule defined? Production boards ship with Kernel Image and DTB's in the 1st fat partition.. Regards, -- Robert Nelson https://rcn-ee.com/
[PATCH v3 4/5] net: add Qualcomm ESS EDMA adapter
This adds the driver for the ESS EDMA ethernet adapter
found inside of Qualcomm IPQ40xx SoC series.
This driver also integrates the built in modified QCA8337N
switch support as they are tightly integrated.
Co-Developed-by: Gabor Juhos
Signed-off-by: Gabor Juhos
Signed-off-by: Robert Marko
---
Changes in v3:
* Use dev_dbg for printing
* Switch to ofnode_read_u32() instead of ofnode_read_u32_default()
Changes in v2:
* Adapt to the Linux pending DT node instead
* Check if port node is enabled
drivers/net/Kconfig |8 +
drivers/net/Makefile |1 +
drivers/net/essedma.c | 1192 +
drivers/net/essedma.h | 198 +++
4 files changed, 1399 insertions(+)
create mode 100644 drivers/net/essedma.c
create mode 100644 drivers/net/essedma.h
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index b2d7b49976..9b7626e1c5 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -307,6 +307,14 @@ config EEPRO100
This driver supports Intel(R) PRO/100 82557/82559/82559ER fast
ethernet family of adapters.
+config ESSEDMA
+ bool "Qualcomm ESS Edma support"
+ depends on DM_ETH && ARCH_IPQ40XX
+ select PHYLIB
+ help
+ This driver supports ethernet DMA adapter found in
+ Qualcomm IPQ40xx series SoC-s.
+
config ETH_SANDBOX
depends on SANDBOX
default y
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index dc3404519d..8533793de5 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_DWC_ETH_QOS_STM32) += dwc_eth_qos_stm32.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
+obj-$(CONFIG_ESSEDMA) += essedma.o
obj-$(CONFIG_ETHOC) += ethoc.o
obj-$(CONFIG_ETH_DESIGNWARE) += designware.o
obj-$(CONFIG_ETH_DESIGNWARE_MESON8B) += dwmac_meson8b.o
diff --git a/drivers/net/essedma.c b/drivers/net/essedma.c
new file mode 100644
index 00..0de363806f
--- /dev/null
+++ b/drivers/net/essedma.c
@@ -0,0 +1,1192 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Sartura Ltd.
+ *
+ * Author: Robert Marko
+ *
+ * Copyright (c) 2021 Toco Technologies FZE
+ * Copyright (c) 2021 Gabor Juhos
+ *
+ * Qualcomm ESS EDMA ethernet driver
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "essedma.h"
+
+#define EDMA_MAX_PKT_SIZE (PKTSIZE_ALIGN + PKTALIGN)
+
+#define EDMA_RXQ_ID0
+#define EDMA_TXQ_ID0
+
+/* descriptor ring */
+struct edma_ring {
+ u16 count; /* number of descriptors in the ring */
+ void *hw_desc; /* descriptor ring virtual address */
+ unsigned int hw_size; /* hw descriptor ring length in bytes */
+ dma_addr_t dma; /* descriptor ring physical address */
+ u16 head; /* next Tx descriptor to fill */
+ u16 tail; /* next Tx descriptor to clean */
+};
+
+struct ess_switch {
+ phys_addr_t base;
+ struct phy_device *phydev[ESS_PORTS_NUM];
+ u32 phy_mask;
+ ofnode ports_node;
+ phy_interface_t port_wrapper_mode;
+ int num_phy;
+};
+
+struct essedma_priv {
+ phys_addr_t base;
+ struct udevice *dev;
+ struct clk ess_clk;
+ struct reset_ctl ess_rst;
+ struct udevice *mdio_dev;
+ struct ess_switch esw;
+ phys_addr_t psgmii_base;
+ struct edma_ring tpd_ring;
+ struct edma_ring rfd_ring;
+};
+
+static void esw_port_loopback_set(struct ess_switch *esw, int port,
+ bool enable)
+{
+ u32 t;
+
+ t = readl(esw->base + ESS_PORT_LOOKUP_CTRL(port));
+ if (enable)
+ t |= ESS_PORT_LOOP_BACK_EN;
+ else
+ t &= ~ESS_PORT_LOOP_BACK_EN;
+ writel(t, esw->base + ESS_PORT_LOOKUP_CTRL(port));
+}
+
+static void esw_port_loopback_set_all(struct ess_switch *esw, bool enable)
+{
+ int i;
+
+ for (i = 1; i < ESS_PORTS_NUM; i++)
+ esw_port_loopback_set(esw, i, enable);
+}
+
+static void ess_reset(struct udevice *dev)
+{
+ struct essedma_priv *priv = dev_get_priv(dev);
+
+ reset_assert(>ess_rst);
+ mdelay(10);
+
+ reset_deassert(>ess_rst);
+ mdelay(10);
+}
+
+void qca8075_ess_reset(struct udevice *dev)
+{
+ struct essedma_priv *priv = dev_get_priv(dev);
+ struct phy_device *psgmii_phy;
+ int i, val;
+
+ /* Find the PSGMII PHY */
+ psgmii_phy = priv->esw.phydev[priv->esw.num_phy - 1];
+
+ /* Fix phy psgmii RX 20bit */
+ phy_write(psgmii_phy, MDIO_DEVAD_NONE, MII_BMCR, 0x005b);
+
+ /* Reset phy psgmii */
+ phy_write(psgmii_phy, MDIO_DEVAD_NONE, MII_BMCR, 0x001b);
+
+ /* Release reset phy psgmii */
+ phy_write(psgmii_phy, MDIO_DEVAD_NONE, MII_BMCR, 0x005b);
+ for (i = 0; i < 100; i++) {
+
[PATCH v3 3/5] clock: qcom: ipq4019: add missing networking resets
IPQ4019 has more networking related resets that will be required for future
wired networking support, so lets add them.
This syncs the driver with Linux.
Signed-off-by: Robert Marko
Reviewed-by: Caleb Connolly
---
drivers/clk/qcom/clock-ipq4019.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c
index 09be203d4b..fca7626ada 100644
--- a/drivers/clk/qcom/clock-ipq4019.c
+++ b/drivers/clk/qcom/clock-ipq4019.c
@@ -124,6 +124,12 @@ static const struct qcom_reset_map gcc_ipq4019_resets[] = {
[GCC_TCSR_BCR] = {0x22000, 0},
[GCC_MPM_BCR] = {0x24000, 0},
[GCC_SPDM_BCR] = {0x25000, 0},
+ [ESS_MAC1_ARES] = {0x1200C, 0},
+ [ESS_MAC2_ARES] = {0x1200C, 1},
+ [ESS_MAC3_ARES] = {0x1200C, 2},
+ [ESS_MAC4_ARES] = {0x1200C, 3},
+ [ESS_MAC5_ARES] = {0x1200C, 4},
+ [ESS_PSGMII_ARES] = {0x1200C, 5},
};
static struct msm_clk_data ipq4019_clk_data = {
--
2.45.1
[PATCH v3 5/5] arm: dts: add IPQ4019 ESS EDMA U-Boot additions
IPQ4019 ESS EDMA support is not yet in upstream Linux, so for now lets use
the latest pending Linux DTS node for wired networking.
Signed-off-by: Robert Marko
---
Chanes in v2:
* Use the latest pending Linux DT node for EDMA instead
arch/arm/dts/qcom-ipq4019-u-boot.dtsi | 104 ++
1 file changed, 104 insertions(+)
create mode 100644 arch/arm/dts/qcom-ipq4019-u-boot.dtsi
diff --git a/arch/arm/dts/qcom-ipq4019-u-boot.dtsi
b/arch/arm/dts/qcom-ipq4019-u-boot.dtsi
new file mode 100644
index 00..079f41
--- /dev/null
+++ b/arch/arm/dts/qcom-ipq4019-u-boot.dtsi
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/ {
+ soc {
+ switch: switch@c00 {
+ compatible = "qcom,ipq4019-ess";
+ reg = <0xc00 0x8>, <0x98000 0x800>, <0xc08
0x8000>;
+ reg-names = "base", "psgmii_phy", "edma";
+ resets = < ESS_PSGMII_ARES>, < ESS_RESET>;
+ reset-names = "psgmii", "ess";
+ clocks = < GCC_ESS_CLK>;
+ clock-names = "ess";
+ mdio = <>;
+ interrupts = ,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ swport1: port@1 { /* MAC1 */
+ reg = <1>;
+ label = "lan1";
+ phy-handle = <>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+
+ swport2: port@2 { /* MAC2 */
+ reg = <2>;
+ label = "lan2";
+ phy-handle = <>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+
+ swport3: port@3 { /* MAC3 */
+ reg = <3>;
+ label = "lan3";
+ phy-handle = <>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+
+ swport4: port@4 { /* MAC4 */
+ reg = <4>;
+ label = "lan4";
+ phy-handle = <>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+
+ swport5: port@5 { /* MAC5 */
+ reg = <5>;
+ label = "wan";
+ phy-handle = <>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+ };
+ };
+ };
+};
+
+ {
+ psgmiiphy: psgmii-phy@5 {
+ reg = <5>;
+ };
+};
--
2.45.1
[PATCH v3 2/5] dt-bindings: clock: qcom: ipq4019: drop downstream file
IPQ4019 clock dt-bindings are available in Linux upstream, and we can just use those instead of carrying a downstream file that matches the upstream one anyway. Signed-off-by: Robert Marko Reviewed-by: Sumit Garg --- Changes in v2: * Drop the downstream dt-bindings header as it matches the upstream Linux one include/dt-bindings/clock/qcom,gcc-ipq4019.h | 169 --- 1 file changed, 169 deletions(-) delete mode 100644 include/dt-bindings/clock/qcom,gcc-ipq4019.h diff --git a/include/dt-bindings/clock/qcom,gcc-ipq4019.h b/include/dt-bindings/clock/qcom,gcc-ipq4019.h deleted file mode 100644 index 7e8a7be6dc..00 --- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h +++ /dev/null @@ -1,169 +0,0 @@ -/* Copyright (c) 2015 The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ -#ifndef __QCOM_CLK_IPQ4019_H__ -#define __QCOM_CLK_IPQ4019_H__ - -#define GCC_DUMMY_CLK 0 -#define AUDIO_CLK_SRC 1 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC2 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC3 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC4 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC5 -#define BLSP1_UART1_APPS_CLK_SRC 6 -#define BLSP1_UART2_APPS_CLK_SRC 7 -#define GCC_USB3_MOCK_UTMI_CLK_SRC 8 -#define GCC_APPS_CLK_SRC 9 -#define GCC_APPS_AHB_CLK_SRC 10 -#define GP1_CLK_SRC11 -#define GP2_CLK_SRC12 -#define GP3_CLK_SRC13 -#define SDCC1_APPS_CLK_SRC 14 -#define FEPHY_125M_DLY_CLK_SRC 15 -#define WCSS2G_CLK_SRC 16 -#define WCSS5G_CLK_SRC 17 -#define GCC_APSS_AHB_CLK 18 -#define GCC_AUDIO_AHB_CLK 19 -#define GCC_AUDIO_PWM_CLK 20 -#define GCC_BLSP1_AHB_CLK 21 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK22 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK23 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK24 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK25 -#define GCC_BLSP1_UART1_APPS_CLK 26 -#define GCC_BLSP1_UART2_APPS_CLK 27 -#define GCC_DCD_XO_CLK 28 -#define GCC_GP1_CLK29 -#define GCC_GP2_CLK30 -#define GCC_GP3_CLK31 -#define GCC_BOOT_ROM_AHB_CLK 32 -#define GCC_CRYPTO_AHB_CLK 33 -#define GCC_CRYPTO_AXI_CLK 34 -#define GCC_CRYPTO_CLK 35 -#define GCC_ESS_CLK36 -#define GCC_IMEM_AXI_CLK 37 -#define GCC_IMEM_CFG_AHB_CLK 38 -#define GCC_PCIE_AHB_CLK 39 -#define GCC_PCIE_AXI_M_CLK 40 -#define GCC_PCIE_AXI_S_CLK 41 -#define GCC_PCNOC_AHB_CLK 42 -#define GCC_PRNG_AHB_CLK 43 -#define GCC_QPIC_AHB_CLK 44 -#define GCC_QPIC_CLK 45 -#define GCC_SDCC1_AHB_CLK 46 -#define GCC_SDCC1_APPS_CLK 47 -#define GCC_SNOC_PCNOC_AHB_CLK 48 -#define GCC_SYS_NOC_125M_CLK 49 -#define GCC_SYS_NOC_AXI_CLK50 -#define GCC_TCSR_AHB_CLK 51 -#define GCC_TLMM_AHB_CLK 52 -#define GCC_USB2_MASTER_CLK53 -#define GCC_USB2_SLEEP_CLK 54 -#define GCC_USB2_MOCK_UTMI_CLK 55 -#define GCC_USB3_MASTER_CLK56 -#define GCC_USB3
[PATCH v3 1/5] clock: qcom: ipq4019: add ESS clock
ESS clock is the Ethernet Subsystem clock, so lets add it as its already configured by SBL1. Signed-off-by: Robert Marko Reviewed-by: Caleb Connolly --- drivers/clk/qcom/clock-ipq4019.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c index 72f235eab2..09be203d4b 100644 --- a/drivers/clk/qcom/clock-ipq4019.c +++ b/drivers/clk/qcom/clock-ipq4019.c @@ -44,6 +44,9 @@ static int ipq4019_clk_enable(struct clk *clk) case GCC_USB2_MOCK_UTMI_CLK: /* These clocks is already initialized by SBL1 */ return 0; + case GCC_ESS_CLK: + /* This clock is already initialized by SBL1 */ + return 0; default: return -EINVAL; } -- 2.45.1
[PATCH] clock: qcom: ipq4019: add I2C clocks
I2C clocks are not initialized by the SBL, so lets add support for clocks
required by both of the QUP I2C controllers.
BLSP1 AHB clock is already initialized by SBL, but QUP I2C driver is
requesting it so we have to add it to the enable list.
Based off QCS404 clock driver.
Signed-off-by: Robert Marko
---
drivers/clk/qcom/clock-ipq4019.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c
index fca7626ada..73dbd25811 100644
--- a/drivers/clk/qcom/clock-ipq4019.c
+++ b/drivers/clk/qcom/clock-ipq4019.c
@@ -16,6 +16,12 @@
#include "clock-qcom.h"
+/* I2C controller clock control registerss */
+#define BLSP1_QUP1_I2C_APPS_CBCR (0x2008)
+#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x200C)
+#define BLSP1_QUP2_I2C_APPS_CBCR (0x3010)
+#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x3000)
+
static ulong ipq4019_clk_set_rate(struct clk *clk, ulong rate)
{
switch (clk->id) {
@@ -29,7 +35,22 @@ static ulong ipq4019_clk_set_rate(struct clk *clk, ulong
rate)
static int ipq4019_clk_enable(struct clk *clk)
{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
switch (clk->id) {
+ case GCC_BLSP1_AHB_CLK:
+ /* This clock is already initialized by SBL1 */
+ return 0;
+ case GCC_BLSP1_QUP1_I2C_APPS_CLK:
+ clk_enable_cbc(priv->base + BLSP1_QUP1_I2C_APPS_CBCR);
+ clk_rcg_set_rate(priv->base, BLSP1_QUP1_I2C_APPS_CMD_RCGR, 0,
+CFG_CLK_SRC_CXO);
+ return 0;
+ case GCC_BLSP1_QUP2_I2C_APPS_CLK:
+ clk_enable_cbc(priv->base + BLSP1_QUP2_I2C_APPS_CBCR);
+ clk_rcg_set_rate(priv->base, BLSP1_QUP2_I2C_APPS_CMD_RCGR, 0,
+CFG_CLK_SRC_CXO);
+ return 0;
case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/
/* This clock is already initialized by SBL1 */
return 0;
--
2.45.1
[PATCH v2 4/5] net: add Qualcomm ESS EDMA adapter
This adds the driver for the ESS EDMA ethernet adapter
found inside of Qualcomm IPQ40xx SoC series.
This driver also integrates the built in modified QCA8337N
switch support as they are tightly integrated.
Co-Developed-by: Gabor Juhos
Signed-off-by: Gabor Juhos
Signed-off-by: Robert Marko
---
Changes in v2:
* Adapt to the Linux pending DT node instead
* Check if port node is enabled
drivers/net/Kconfig |8 +
drivers/net/Makefile |1 +
drivers/net/essedma.c | 1185 +
drivers/net/essedma.h | 198 +++
4 files changed, 1392 insertions(+)
create mode 100644 drivers/net/essedma.c
create mode 100644 drivers/net/essedma.h
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index b2d7b49976..9b7626e1c5 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -307,6 +307,14 @@ config EEPRO100
This driver supports Intel(R) PRO/100 82557/82559/82559ER fast
ethernet family of adapters.
+config ESSEDMA
+ bool "Qualcomm ESS Edma support"
+ depends on DM_ETH && ARCH_IPQ40XX
+ select PHYLIB
+ help
+ This driver supports ethernet DMA adapter found in
+ Qualcomm IPQ40xx series SoC-s.
+
config ETH_SANDBOX
depends on SANDBOX
default y
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index dc3404519d..8533793de5 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_DWC_ETH_QOS_STM32) += dwc_eth_qos_stm32.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
+obj-$(CONFIG_ESSEDMA) += essedma.o
obj-$(CONFIG_ETHOC) += ethoc.o
obj-$(CONFIG_ETH_DESIGNWARE) += designware.o
obj-$(CONFIG_ETH_DESIGNWARE_MESON8B) += dwmac_meson8b.o
diff --git a/drivers/net/essedma.c b/drivers/net/essedma.c
new file mode 100644
index 00..1be125bafd
--- /dev/null
+++ b/drivers/net/essedma.c
@@ -0,0 +1,1185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Sartura Ltd.
+ *
+ * Author: Robert Marko
+ *
+ * Copyright (c) 2021 Toco Technologies FZE
+ * Copyright (c) 2021 Gabor Juhos
+ *
+ * Qualcomm ESS EDMA ethernet driver
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "essedma.h"
+
+#define EDMA_MAX_PKT_SIZE (PKTSIZE_ALIGN + PKTALIGN)
+
+#define EDMA_RXQ_ID0
+#define EDMA_TXQ_ID0
+
+/* descriptor ring */
+struct edma_ring {
+ u16 count; /* number of descriptors in the ring */
+ void *hw_desc; /* descriptor ring virtual address */
+ unsigned int hw_size; /* hw descriptor ring length in bytes */
+ dma_addr_t dma; /* descriptor ring physical address */
+ u16 head; /* next Tx descriptor to fill */
+ u16 tail; /* next Tx descriptor to clean */
+};
+
+struct ess_switch {
+ phys_addr_t base;
+ struct phy_device *phydev[ESS_PORTS_NUM];
+ u32 phy_mask;
+ ofnode ports_node;
+ phy_interface_t port_wrapper_mode;
+ int num_phy;
+};
+
+struct essedma_priv {
+ phys_addr_t base;
+ struct clk ess_clk;
+ struct reset_ctl ess_rst;
+ struct udevice *mdio_dev;
+ struct ess_switch esw;
+ phys_addr_t psgmii_base;
+ struct edma_ring tpd_ring;
+ struct edma_ring rfd_ring;
+};
+
+static void esw_port_loopback_set(struct ess_switch *esw, int port,
+ bool enable)
+{
+ u32 t;
+
+ t = readl(esw->base + ESS_PORT_LOOKUP_CTRL(port));
+ if (enable)
+ t |= ESS_PORT_LOOP_BACK_EN;
+ else
+ t &= ~ESS_PORT_LOOP_BACK_EN;
+ writel(t, esw->base + ESS_PORT_LOOKUP_CTRL(port));
+}
+
+static void esw_port_loopback_set_all(struct ess_switch *esw, bool enable)
+{
+ int i;
+
+ for (i = 1; i < ESS_PORTS_NUM; i++)
+ esw_port_loopback_set(esw, i, enable);
+}
+
+static void ess_reset(struct udevice *dev)
+{
+ struct essedma_priv *priv = dev_get_priv(dev);
+
+ reset_assert(>ess_rst);
+ mdelay(10);
+
+ reset_deassert(>ess_rst);
+ mdelay(10);
+}
+
+void qca8075_ess_reset(struct udevice *dev)
+{
+ struct essedma_priv *priv = dev_get_priv(dev);
+ struct phy_device *psgmii_phy;
+ int i, val;
+
+ /* Find the PSGMII PHY */
+ psgmii_phy = priv->esw.phydev[priv->esw.num_phy - 1];
+
+ /* Fix phy psgmii RX 20bit */
+ phy_write(psgmii_phy, MDIO_DEVAD_NONE, MII_BMCR, 0x005b);
+
+ /* Reset phy psgmii */
+ phy_write(psgmii_phy, MDIO_DEVAD_NONE, MII_BMCR, 0x001b);
+
+ /* Release reset phy psgmii */
+ phy_write(psgmii_phy, MDIO_DEVAD_NONE, MII_BMCR, 0x005b);
+ for (i = 0; i < 100; i++) {
+ val = phy_read_mmd(psgmii_phy, MDIO_MMD_PMAPMD, 0x28);
+ if (val & 0x1)
+ brea
[PATCH v2 5/5] arm: dts: add IPQ4019 ESS EDMA U-Boot additions
IPQ4019 ESS EDMA support is not yet in upstream Linux, so for now lets use
the latest pending Linux DTS node for wired networking.
Signed-off-by: Robert Marko
---
Chanes in v2:
* Use the latest pending Linux DT node for EDMA instead
arch/arm/dts/qcom-ipq4019-u-boot.dtsi | 104 ++
1 file changed, 104 insertions(+)
create mode 100644 arch/arm/dts/qcom-ipq4019-u-boot.dtsi
diff --git a/arch/arm/dts/qcom-ipq4019-u-boot.dtsi
b/arch/arm/dts/qcom-ipq4019-u-boot.dtsi
new file mode 100644
index 00..079f41
--- /dev/null
+++ b/arch/arm/dts/qcom-ipq4019-u-boot.dtsi
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/ {
+ soc {
+ switch: switch@c00 {
+ compatible = "qcom,ipq4019-ess";
+ reg = <0xc00 0x8>, <0x98000 0x800>, <0xc08
0x8000>;
+ reg-names = "base", "psgmii_phy", "edma";
+ resets = < ESS_PSGMII_ARES>, < ESS_RESET>;
+ reset-names = "psgmii", "ess";
+ clocks = < GCC_ESS_CLK>;
+ clock-names = "ess";
+ mdio = <>;
+ interrupts = ,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ swport1: port@1 { /* MAC1 */
+ reg = <1>;
+ label = "lan1";
+ phy-handle = <>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+
+ swport2: port@2 { /* MAC2 */
+ reg = <2>;
+ label = "lan2";
+ phy-handle = <>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+
+ swport3: port@3 { /* MAC3 */
+ reg = <3>;
+ label = "lan3";
+ phy-handle = <>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+
+ swport4: port@4 { /* MAC4 */
+ reg = <4>;
+ label = "lan4";
+ phy-handle = <>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+
+ swport5: port@5 { /* MAC5 */
+ reg = <5>;
+ label = "wan";
+ phy-handle = <>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+ };
+ };
+ };
+};
+
+ {
+ psgmiiphy: psgmii-phy@5 {
+ reg = <5>;
+ };
+};
--
2.45.1
[PATCH v2 2/5] dt-bindings: clock: qcom: ipq4019: drop downstream file
IPQ4019 clock dt-bindings are available in Linux upstream, and we can just use those instead of carrying a downstream file that matches the upstream one anyway. Signed-off-by: Robert Marko --- Changes in v2: * Drop the downstream dt-bindings header as it matches the upstream Linux one include/dt-bindings/clock/qcom,gcc-ipq4019.h | 169 --- 1 file changed, 169 deletions(-) delete mode 100644 include/dt-bindings/clock/qcom,gcc-ipq4019.h diff --git a/include/dt-bindings/clock/qcom,gcc-ipq4019.h b/include/dt-bindings/clock/qcom,gcc-ipq4019.h deleted file mode 100644 index 7e8a7be6dc..00 --- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h +++ /dev/null @@ -1,169 +0,0 @@ -/* Copyright (c) 2015 The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ -#ifndef __QCOM_CLK_IPQ4019_H__ -#define __QCOM_CLK_IPQ4019_H__ - -#define GCC_DUMMY_CLK 0 -#define AUDIO_CLK_SRC 1 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC2 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC3 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC4 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC5 -#define BLSP1_UART1_APPS_CLK_SRC 6 -#define BLSP1_UART2_APPS_CLK_SRC 7 -#define GCC_USB3_MOCK_UTMI_CLK_SRC 8 -#define GCC_APPS_CLK_SRC 9 -#define GCC_APPS_AHB_CLK_SRC 10 -#define GP1_CLK_SRC11 -#define GP2_CLK_SRC12 -#define GP3_CLK_SRC13 -#define SDCC1_APPS_CLK_SRC 14 -#define FEPHY_125M_DLY_CLK_SRC 15 -#define WCSS2G_CLK_SRC 16 -#define WCSS5G_CLK_SRC 17 -#define GCC_APSS_AHB_CLK 18 -#define GCC_AUDIO_AHB_CLK 19 -#define GCC_AUDIO_PWM_CLK 20 -#define GCC_BLSP1_AHB_CLK 21 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK22 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK23 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK24 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK25 -#define GCC_BLSP1_UART1_APPS_CLK 26 -#define GCC_BLSP1_UART2_APPS_CLK 27 -#define GCC_DCD_XO_CLK 28 -#define GCC_GP1_CLK29 -#define GCC_GP2_CLK30 -#define GCC_GP3_CLK31 -#define GCC_BOOT_ROM_AHB_CLK 32 -#define GCC_CRYPTO_AHB_CLK 33 -#define GCC_CRYPTO_AXI_CLK 34 -#define GCC_CRYPTO_CLK 35 -#define GCC_ESS_CLK36 -#define GCC_IMEM_AXI_CLK 37 -#define GCC_IMEM_CFG_AHB_CLK 38 -#define GCC_PCIE_AHB_CLK 39 -#define GCC_PCIE_AXI_M_CLK 40 -#define GCC_PCIE_AXI_S_CLK 41 -#define GCC_PCNOC_AHB_CLK 42 -#define GCC_PRNG_AHB_CLK 43 -#define GCC_QPIC_AHB_CLK 44 -#define GCC_QPIC_CLK 45 -#define GCC_SDCC1_AHB_CLK 46 -#define GCC_SDCC1_APPS_CLK 47 -#define GCC_SNOC_PCNOC_AHB_CLK 48 -#define GCC_SYS_NOC_125M_CLK 49 -#define GCC_SYS_NOC_AXI_CLK50 -#define GCC_TCSR_AHB_CLK 51 -#define GCC_TLMM_AHB_CLK 52 -#define GCC_USB2_MASTER_CLK53 -#define GCC_USB2_SLEEP_CLK 54 -#define GCC_USB2_MOCK_UTMI_CLK 55 -#define GCC_USB3_MASTER_CLK56 -#define GCC_USB3
[PATCH v2 3/5] clock: qcom: ipq4019: add missing networking resets
IPQ4019 has more networking related resets that will be required for future
wired networking support, so lets add them.
This syncs the driver with Linux.
Signed-off-by: Robert Marko
Reviewed-by: Caleb Connolly
---
drivers/clk/qcom/clock-ipq4019.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c
index e416c9cdb0..2773bbc2d4 100644
--- a/drivers/clk/qcom/clock-ipq4019.c
+++ b/drivers/clk/qcom/clock-ipq4019.c
@@ -205,6 +205,12 @@ static const struct qcom_reset_map gcc_ipq4019_resets[] = {
[GCC_TCSR_BCR] = {0x22000, 0},
[GCC_MPM_BCR] = {0x24000, 0},
[GCC_SPDM_BCR] = {0x25000, 0},
+ [ESS_MAC1_ARES] = {0x1200C, 0},
+ [ESS_MAC2_ARES] = {0x1200C, 1},
+ [ESS_MAC3_ARES] = {0x1200C, 2},
+ [ESS_MAC4_ARES] = {0x1200C, 3},
+ [ESS_MAC5_ARES] = {0x1200C, 4},
+ [ESS_PSGMII_ARES] = {0x1200C, 5},
};
static struct msm_clk_data ipq4019_clk_data = {
--
2.45.1
[PATCH v2 1/5] clock: qcom: ipq4019: add ESS clock
ESS clock is the Ethernet Subsystem clock, so lets add it as its already configured by SBL1. Signed-off-by: Robert Marko Reviewed-by: Caleb Connolly --- drivers/clk/qcom/clock-ipq4019.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c index 0492e536e7..e416c9cdb0 100644 --- a/drivers/clk/qcom/clock-ipq4019.c +++ b/drivers/clk/qcom/clock-ipq4019.c @@ -125,6 +125,9 @@ static int ipq4019_clk_enable(struct clk *clk) case GCC_USB2_MOCK_UTMI_CLK: /* These clocks is already initialized by SBL1 */ return 0; + case GCC_ESS_CLK: + /* This clock is already initialized by SBL1 */ + return 0; default: return -EINVAL; } -- 2.45.1
Re: [PATCH 5/5] arm: dts: add IPQ4019 ESS EDMA U-Boot additions
On Wed, May 22, 2024 at 6:21 PM Caleb Connolly
wrote:
>
> Hi Robert,
>
> Thanks for the patches.
>
> On 22/05/2024 12:13, Robert Marko wrote:
> > IPQ4019 ESS EDMA support is not yet in upstream Linux, and even when
> > eventually it is merged the node will not be compatible with U-Boot driver
> > as the Linux driver properly models the internal switch.
>
> Is this going to cause dtc compile errors when the node eventually does
> land upstream and gets pulled into U-Boot?
Yes, most likely the nodes will conflict.
>
> How hard would it be to adjust the U-Boot driver to work with the
> upstream bindings?
I can probably make it work with the current latest pending Linux node plus some
minor U-Boot additions, I don't think the node will change much (If at
all) in newer Linux
patch series for the IPQESS driver.
Regards,
Robert
>
> Kind regards,
> >
> > So, lets add the U-Boot additions DTSI for ESS EDMA for now.
> >
> > Signed-off-by: Robert Marko
> > ---
> > arch/arm/dts/qcom-ipq4019-u-boot.dtsi | 27 +++
> > 1 file changed, 27 insertions(+)
> > create mode 100644 arch/arm/dts/qcom-ipq4019-u-boot.dtsi
> >
> > diff --git a/arch/arm/dts/qcom-ipq4019-u-boot.dtsi
> > b/arch/arm/dts/qcom-ipq4019-u-boot.dtsi
> > new file mode 100644
> > index 00..f70ef5c9a5
> > --- /dev/null
> > +++ b/arch/arm/dts/qcom-ipq4019-u-boot.dtsi
> > @@ -0,0 +1,27 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> > +/ {
> > + soc {
> > + edma: edma@c08 {
> > + compatible = "qcom,ess-edma";
> > + reg = <0xc08 0x8000>, <0x98000 0x800>, <0xc00
> > 0x8>;
> > + reg-names = "edma", "psgmii_phy", "switch";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + resets = < ESS_PSGMII_ARES>, < ESS_RESET>;
> > + reset-names = "psgmii", "ess";
> > + clocks = < GCC_ESS_CLK>;
> > + clock-names = "ess";
> > + status = "disabled";
> > +
> > + switch_ports: switch-ports {
> > + phy-mode = "psgmii";
> > + };
> > + };
> > + };
> > +};
> > +
> > + {
> > + psgmiiphy: psgmii-phy@5 {
> > + reg = <5>;
> > + };
> > +};
>
> --
> // Caleb (they/them)
--
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
1 Zagreb, Croatia
Email: robert.ma...@sartura.hr
Web: www.sartura.hr
Re: [PATCH 2/5] dt-bindings: clock: qcom: ipq4019: add missing networking resets
On Wed, May 22, 2024 at 6:22 PM Caleb Connolly wrote: > > Hi Robert, > > On 22/05/2024 12:13, Robert Marko wrote: > > Add bindings for the missing networking resets found in IPQ4019 GCC. > > This syncs the bindigs with Linux. > > These bindings are already synced from Linux in dts/upstream/include/... > > You should be able to just delete this vendored file instead. Thanks for the tip, indeed it can just be removed. Regards, Robert > > Kind regards, > > > > Signed-off-by: Robert Marko > > --- > > include/dt-bindings/clock/qcom,gcc-ipq4019.h | 6 ++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/include/dt-bindings/clock/qcom,gcc-ipq4019.h > > b/include/dt-bindings/clock/qcom,gcc-ipq4019.h > > index 7e8a7be6dc..fa05878575 100644 > > --- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h > > +++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h > > @@ -165,5 +165,11 @@ > > #define GCC_QDSS_BCR69 > > #define GCC_MPM_BCR 70 > > #define GCC_SPDM_BCR71 > > +#define ESS_MAC1_ARES72 > > +#define ESS_MAC2_ARES73 > > +#define ESS_MAC3_ARES74 > > +#define ESS_MAC4_ARES75 > > +#define ESS_MAC5_ARES 76 > > +#define ESS_PSGMII_ARES 77 > > > > #endif > > -- > // Caleb (they/them) -- Robert Marko Staff Embedded Linux Engineer Sartura Ltd. Lendavska ulica 16a 1 Zagreb, Croatia Email: robert.ma...@sartura.hr Web: www.sartura.hr
[PATCH 5/5] arm: dts: add IPQ4019 ESS EDMA U-Boot additions
IPQ4019 ESS EDMA support is not yet in upstream Linux, and even when
eventually it is merged the node will not be compatible with U-Boot driver
as the Linux driver properly models the internal switch.
So, lets add the U-Boot additions DTSI for ESS EDMA for now.
Signed-off-by: Robert Marko
---
arch/arm/dts/qcom-ipq4019-u-boot.dtsi | 27 +++
1 file changed, 27 insertions(+)
create mode 100644 arch/arm/dts/qcom-ipq4019-u-boot.dtsi
diff --git a/arch/arm/dts/qcom-ipq4019-u-boot.dtsi
b/arch/arm/dts/qcom-ipq4019-u-boot.dtsi
new file mode 100644
index 00..f70ef5c9a5
--- /dev/null
+++ b/arch/arm/dts/qcom-ipq4019-u-boot.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/ {
+ soc {
+ edma: edma@c08 {
+ compatible = "qcom,ess-edma";
+ reg = <0xc08 0x8000>, <0x98000 0x800>, <0xc00
0x8>;
+ reg-names = "edma", "psgmii_phy", "switch";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ resets = < ESS_PSGMII_ARES>, < ESS_RESET>;
+ reset-names = "psgmii", "ess";
+ clocks = < GCC_ESS_CLK>;
+ clock-names = "ess";
+ status = "disabled";
+
+ switch_ports: switch-ports {
+ phy-mode = "psgmii";
+ };
+ };
+ };
+};
+
+ {
+ psgmiiphy: psgmii-phy@5 {
+ reg = <5>;
+ };
+};
--
2.45.1
[PATCH 4/5] net: add Qualcomm ESS EDMA adapter
This adds the driver for the ESS EDMA ethernet adapter
found inside of Qualcomm IPQ40xx SoC series.
This driver also integrates the built in modified QCA8337N
switch support as they are tightly integrated.
Co-Developed-by: Gabor Juhos
Signed-off-by: Gabor Juhos
Signed-off-by: Robert Marko
---
drivers/net/Kconfig |8 +
drivers/net/Makefile |1 +
drivers/net/essedma.c | 1183 +
drivers/net/essedma.h | 198 +++
4 files changed, 1390 insertions(+)
create mode 100644 drivers/net/essedma.c
create mode 100644 drivers/net/essedma.h
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index b2d7b49976..9b7626e1c5 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -307,6 +307,14 @@ config EEPRO100
This driver supports Intel(R) PRO/100 82557/82559/82559ER fast
ethernet family of adapters.
+config ESSEDMA
+ bool "Qualcomm ESS Edma support"
+ depends on DM_ETH && ARCH_IPQ40XX
+ select PHYLIB
+ help
+ This driver supports ethernet DMA adapter found in
+ Qualcomm IPQ40xx series SoC-s.
+
config ETH_SANDBOX
depends on SANDBOX
default y
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index dc3404519d..8533793de5 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_DWC_ETH_QOS_STM32) += dwc_eth_qos_stm32.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
+obj-$(CONFIG_ESSEDMA) += essedma.o
obj-$(CONFIG_ETHOC) += ethoc.o
obj-$(CONFIG_ETH_DESIGNWARE) += designware.o
obj-$(CONFIG_ETH_DESIGNWARE_MESON8B) += dwmac_meson8b.o
diff --git a/drivers/net/essedma.c b/drivers/net/essedma.c
new file mode 100644
index 00..5dea2419e8
--- /dev/null
+++ b/drivers/net/essedma.c
@@ -0,0 +1,1183 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Sartura Ltd.
+ *
+ * Author: Robert Marko
+ *
+ * Copyright (c) 2021 Toco Technologies FZE
+ * Copyright (c) 2021 Gabor Juhos
+ *
+ * Qualcomm ESS EDMA ethernet driver
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "essedma.h"
+
+#define EDMA_MAX_PKT_SIZE (PKTSIZE_ALIGN + PKTALIGN)
+
+#define EDMA_RXQ_ID0
+#define EDMA_TXQ_ID0
+
+/* descriptor ring */
+struct edma_ring {
+ u16 count; /* number of descriptors in the ring */
+ void *hw_desc; /* descriptor ring virtual address */
+ unsigned int hw_size; /* hw descriptor ring length in bytes */
+ dma_addr_t dma; /* descriptor ring physical address */
+ u16 head; /* next Tx descriptor to fill */
+ u16 tail; /* next Tx descriptor to clean */
+};
+
+struct ess_switch {
+ phys_addr_t base;
+ struct phy_device *phydev[ESS_PORTS_NUM];
+ u32 phy_mask;
+ ofnode ports_node;
+ phy_interface_t port_wrapper_mode;
+ int num_phy;
+};
+
+struct essedma_priv {
+ phys_addr_t base;
+ struct clk ess_clk;
+ struct reset_ctl ess_rst;
+ struct udevice *mdio_dev;
+ struct ess_switch esw;
+ phys_addr_t psgmii_base;
+ struct edma_ring tpd_ring;
+ struct edma_ring rfd_ring;
+};
+
+static void esw_port_loopback_set(struct ess_switch *esw, int port,
+ bool enable)
+{
+ u32 t;
+
+ t = readl(esw->base + ESS_PORT_LOOKUP_CTRL(port));
+ if (enable)
+ t |= ESS_PORT_LOOP_BACK_EN;
+ else
+ t &= ~ESS_PORT_LOOP_BACK_EN;
+ writel(t, esw->base + ESS_PORT_LOOKUP_CTRL(port));
+}
+
+static void esw_port_loopback_set_all(struct ess_switch *esw, bool enable)
+{
+ int i;
+
+ for (i = 1; i < ESS_PORTS_NUM; i++)
+ esw_port_loopback_set(esw, i, enable);
+}
+
+static void ess_reset(struct udevice *dev)
+{
+ struct essedma_priv *priv = dev_get_priv(dev);
+
+ reset_assert(>ess_rst);
+ mdelay(10);
+
+ reset_deassert(>ess_rst);
+ mdelay(10);
+}
+
+void qca8075_ess_reset(struct udevice *dev)
+{
+ struct essedma_priv *priv = dev_get_priv(dev);
+ struct phy_device *psgmii_phy;
+ int i, val;
+
+ /* Find the PSGMII PHY */
+ psgmii_phy = priv->esw.phydev[priv->esw.num_phy - 1];
+
+ /* Fix phy psgmii RX 20bit */
+ phy_write(psgmii_phy, MDIO_DEVAD_NONE, MII_BMCR, 0x005b);
+
+ /* Reset phy psgmii */
+ phy_write(psgmii_phy, MDIO_DEVAD_NONE, MII_BMCR, 0x001b);
+
+ /* Release reset phy psgmii */
+ phy_write(psgmii_phy, MDIO_DEVAD_NONE, MII_BMCR, 0x005b);
+ for (i = 0; i < 100; i++) {
+ val = phy_read_mmd(psgmii_phy, MDIO_MMD_PMAPMD, 0x28);
+ if (val & 0x1)
+ break;
+ mdelay(1);
+ }
+ if (i >= 100)
+ printf("QCA807x PSGMII PLL_V
[PATCH 3/5] clock: qcom: ipq4019: add missing networking resets
IPQ4019 has more networking related resets that will be required for future
wired networking support, so lets add them.
This syncs the driver with Linux.
Signed-off-by: Robert Marko
---
drivers/clk/qcom/clock-ipq4019.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c
index e416c9cdb0..2773bbc2d4 100644
--- a/drivers/clk/qcom/clock-ipq4019.c
+++ b/drivers/clk/qcom/clock-ipq4019.c
@@ -205,6 +205,12 @@ static const struct qcom_reset_map gcc_ipq4019_resets[] = {
[GCC_TCSR_BCR] = {0x22000, 0},
[GCC_MPM_BCR] = {0x24000, 0},
[GCC_SPDM_BCR] = {0x25000, 0},
+ [ESS_MAC1_ARES] = {0x1200C, 0},
+ [ESS_MAC2_ARES] = {0x1200C, 1},
+ [ESS_MAC3_ARES] = {0x1200C, 2},
+ [ESS_MAC4_ARES] = {0x1200C, 3},
+ [ESS_MAC5_ARES] = {0x1200C, 4},
+ [ESS_PSGMII_ARES] = {0x1200C, 5},
};
static struct msm_clk_data ipq4019_clk_data = {
--
2.45.1
[PATCH 2/5] dt-bindings: clock: qcom: ipq4019: add missing networking resets
Add bindings for the missing networking resets found in IPQ4019 GCC. This syncs the bindigs with Linux. Signed-off-by: Robert Marko --- include/dt-bindings/clock/qcom,gcc-ipq4019.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq4019.h b/include/dt-bindings/clock/qcom,gcc-ipq4019.h index 7e8a7be6dc..fa05878575 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h @@ -165,5 +165,11 @@ #define GCC_QDSS_BCR 69 #define GCC_MPM_BCR70 #define GCC_SPDM_BCR 71 +#define ESS_MAC1_ARES 72 +#define ESS_MAC2_ARES 73 +#define ESS_MAC3_ARES 74 +#define ESS_MAC4_ARES 75 +#define ESS_MAC5_ARES 76 +#define ESS_PSGMII_ARES77 #endif -- 2.45.1
[PATCH 1/5] clock: qcom: ipq4019: add ESS clock
ESS clock is the Ethernet Subsystem clock, so lets add it as its already configured by SBL1. Signed-off-by: Robert Marko --- drivers/clk/qcom/clock-ipq4019.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c index 0492e536e7..e416c9cdb0 100644 --- a/drivers/clk/qcom/clock-ipq4019.c +++ b/drivers/clk/qcom/clock-ipq4019.c @@ -125,6 +125,9 @@ static int ipq4019_clk_enable(struct clk *clk) case GCC_USB2_MOCK_UTMI_CLK: /* These clocks is already initialized by SBL1 */ return 0; + case GCC_ESS_CLK: + /* This clock is already initialized by SBL1 */ + return 0; default: return -EINVAL; } -- 2.45.1
[PATCH 2/2] net: phy: add Qualcomm QCA807x driver
This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s. They are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s. They feature 2 SerDes, one for PSGMII or QSGMII connection with MAC, while second one is SGMII for connection to MAC or fiber. Both models have a combo port that supports 1000BASE-X and 100BASE-FX fiber (Currently not supported in U-Boot) Each PHY inside of QCA807x series has 2 digitally controlled output only pins that natively drive LED-s. These PHY-s are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x boards. Signed-off-by: Robert Marko --- drivers/net/phy/Kconfig | 6 ++ drivers/net/phy/Makefile | 1 + drivers/net/phy/qca807x.c | 211 ++ 3 files changed, 218 insertions(+) create mode 100644 drivers/net/phy/qca807x.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 3d96938eab..cc79043b97 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -243,6 +243,12 @@ config PHY_NXP_TJA11XX help Currently supports the NXP TJA1100 and TJA1101 PHY. +config PHY_QCA807X + bool "Qualcomm QCA807x PHYs support" + help + Currently supports the Qualcomm QCA8072, QCA8075 and the PSGMII + control PHY. + config PHY_REALTEK bool "Realtek Ethernet PHYs support" diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 2487f366e1..b2d31fe4f2 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_PHY_MOTORCOMM) += motorcomm.o obj-$(CONFIG_PHY_NATSEMI) += natsemi.o obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o +obj-$(CONFIG_PHY_QCA807X) += qca807x.o obj-$(CONFIG_PHY_REALTEK) += realtek.o obj-$(CONFIG_PHY_SMSC) += smsc.o obj-$(CONFIG_PHY_TERANETICS) += teranetics.o diff --git a/drivers/net/phy/qca807x.c b/drivers/net/phy/qca807x.c new file mode 100644 index 00..a851ff34a0 --- /dev/null +++ b/drivers/net/phy/qca807x.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 Sartura Ltd. + * + * Author: Robert Marko + * + * Qualcomm QCA8072 and QCA8075 PHY driver + */ + +#include +#include +#include +#include + +#define PHY_ID_QCA8072 0x004dd0b2 +#define PHY_ID_QCA8075 0x004dd0b1 +#define PHY_ID_QCA807X_PSGMII 0x06820805 +#define PHY_ID_QCA807X_MASKGENMASK(31, 0) + +#define QCA807X_CHIP_CONFIGURATION 0x1f +#define QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH0x801a +#define QCA807X_CONTROL_DAC_MASK GENMASK(2, 0) +/* List of tweaks enabled by this bit: + * - With both FULL amplitude and FULL bias current: bias current + * is set to half. + * - With only DSP amplitude: bias current is set to half and + * is set to 1/4 with cable < 10m. + * - With DSP bias current (included both DSP amplitude and + * DSP bias current): bias current is half the detected current + * with cable < 10m. + */ +#define QCA807X_CONTROL_DAC_BIAS_CURRENT_TWEAK BIT(2) +#define QCA807X_CONTROL_DAC_DSP_BIAS_CURRENT BIT(1) +#define QCA807X_CONTROL_DAC_DSP_AMPLITUDE BIT(0) + +#define QCA807X_MMD7_LED_100N_10x8074 +#define QCA807X_MMD7_LED_100N_20x8075 +#define QCA807X_MMD7_LED_1000N_1 0x8076 +#define QCA807X_MMD7_LED_1000N_2 0x8077 +#define QCA807X_LED_TXACT_BLK_EN_2 BIT(10) +#define QCA807X_LED_RXACT_BLK_EN_2 BIT(9) +#define QCA807X_LED_GT_ON_EN_2 BIT(6) +#define QCA807X_LED_HT_ON_EN_2 BIT(5) +#define QCA807X_LED_BT_ON_EN_2 BIT(4) + +/* PSGMII PHY specific */ +#define PSGMII_QSGMII_DRIVE_CONTROL_1 0xb +#define PSGMII_QSGMII_TX_DRIVER_MASK GENMASK(7, 4) +#define PQSGMII_TX_DRIVER_140MV0x0 +#define PQSGMII_TX_DRIVER_160MV0x1 +#define PQSGMII_TX_DRIVER_180MV0x2 +#define PQSGMII_TX_DRIVER_200MV0x3 +#define PQSGMII_TX_DRIVER_220MV0x4 +#define PQSGMII_TX_DRIVER_240MV0x5 +#define PQSGMII_TX_DRIVER_260MV0x6 +#define PQSGMII_TX_DRIVER_280MV0x7 +#define PQSGMII_TX_DRIVER_300MV0x8 +#define PQSGMII_TX_DRIVER_320MV0x9 +#define PQSGMII_TX_DRIVER_400MV0xa +#define PQSGMII_TX_DRIVER_500MV0xb +#define PQSGMII_TX_DRIVER_600MV0xc +#define PSGMII_MODE_CTRL 0x6d +#define PSGMII_MODE_CTRL_AZ_WORKAROUND_MASKGENMASK(3, 0) +#define PSGMII_MMD3_SERDES_CONTROL 0x805a + +static
[PATCH 1/2] net: phy: add PSGMII (Penta SGMII) mode
The PSGMII interface is similar to QSGMII. The main difference
is that the PSGMII interface combines five SGMII lines into a
single link while in QSGMII only four lines are combined.
Similarly to the QSGMII, this interface mode might also needs
special handling within the MAC driver.
It is commonly used by Qualcomm with their QCA807x PHY series and
modern WiSoC-s.
Add definitions for the PHY layer to allow to express this type
of connection between the MAC and PHY.
This is basically a direct port from Linux which already supports this
mode.
Signed-off-by: Robert Marko
---
include/phy_interface.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/phy_interface.h b/include/phy_interface.h
index 31be3228c7..04826bc65d 100644
--- a/include/phy_interface.h
+++ b/include/phy_interface.h
@@ -31,6 +31,7 @@ typedef enum {
PHY_INTERFACE_MODE_XGMII,
PHY_INTERFACE_MODE_XLGMII,
PHY_INTERFACE_MODE_MOCA,
+ PHY_INTERFACE_MODE_PSGMII,
PHY_INTERFACE_MODE_QSGMII,
PHY_INTERFACE_MODE_TRGMII,
PHY_INTERFACE_MODE_100BASEX,
@@ -79,6 +80,7 @@ static const char * const phy_interface_strings[] = {
[PHY_INTERFACE_MODE_XGMII] = "xgmii",
[PHY_INTERFACE_MODE_XLGMII] = "xlgmii",
[PHY_INTERFACE_MODE_MOCA] = "moca",
+ [PHY_INTERFACE_MODE_PSGMII] = "psgmii",
[PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
[PHY_INTERFACE_MODE_TRGMII] = "trgmii",
[PHY_INTERFACE_MODE_1000BASEX] = "1000base-x",
--
2.45.1
[PATCH v2 3/3] arm: dts: drop downstream IPQ4019 DTSI
We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so
lets drop our downstream DTSI.
Signed-off-by: Robert Marko
Acked-by: Caleb Connolly
---
arch/arm/dts/qcom-ipq4019.dtsi | 202 -
1 file changed, 202 deletions(-)
delete mode 100644 arch/arm/dts/qcom-ipq4019.dtsi
diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi
deleted file mode 100644
index f9489e42ea..00
--- a/arch/arm/dts/qcom-ipq4019.dtsi
+++ /dev/null
@@ -1,202 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2019 Sartura Ltd.
- *
- * Author: Robert Marko
- */
-
- /dts-v1/;
-
-#include "skeleton.dtsi"
-#include
-#include
-#include
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- model = "Qualcomm Technologies, Inc. IPQ4019";
- compatible = "qcom,ipq4019";
-
- aliases {
- serial0 = _uart1;
- spi0 = _spi1;
- };
-
- reserved-memory {
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- ranges;
-
- smem_mem: smem_region: smem@87e0 {
- reg = <0x87e0 0x08>;
- no-map;
- };
-
- tz@87e8 {
- reg = <0x87e8 0x18>;
- no-map;
- };
- };
-
- smem {
- compatible = "qcom,smem";
- memory-region = <_mem>;
- };
-
- soc: soc {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- compatible = "simple-bus";
-
- gcc: clock-controller@180 {
- compatible = "qcom,gcc-ipq4019";
- reg = <0x180 0x6>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- bootph-all;
- };
-
- rng: rng@22000 {
- compatible = "qcom,prng";
- reg = <0x22000 0x140>;
- clocks = < GCC_PRNG_AHB_CLK>;
- status = "disabled";
- };
-
- soc_gpios: pinctrl@100 {
- compatible = "qcom,ipq4019-pinctrl";
- reg = <0x100 0x30>;
- gpio-controller;
- gpio-count = <100>;
- gpio-bank-name="soc";
- #gpio-cells = <2>;
- bootph-all;
- };
-
- blsp1_uart1: serial@78af000 {
- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- reg = <0x78af000 0x200>;
- clock = < GCC_BLSP1_UART1_APPS_CLK>;
- bit-rate = <0xFF>;
- status = "disabled";
- bootph-all;
- };
-
- blsp1_spi1: spi@78b5000 {
- compatible = "qcom,spi-qup-v2.2.1";
- reg = <0x78b5000 0x600>;
- clocks = < GCC_BLSP1_QUP1_SPI_APPS_CLK>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- bootph-all;
- };
-
- mdio: mdio@9 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "qcom,ipq4019-mdio";
- reg = <0x9 0x64>;
- status = "disabled";
-
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- ethphy1: ethernet-phy@1 {
- reg = <1>;
- };
-
- ethphy2: ethernet-phy@2 {
- reg = <2>;
- };
-
- ethphy3: ethernet-phy@3 {
- reg = <3>;
- };
-
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
- };
-
- usb3_ss_phy: ssphy@9a000 {
- compatible = "qcom,usb-ss-ipq4019-phy";
- #phy-cells = <0>;
- reg = <0x9a000 0x800>;
- reg-names = "phy_base";
- resets = < USB3_UNIPHY_PH
[PATCH v2 1/3] mach-ipq40xx: add CPU specific code
Provide basic DRAM info population from DT, cache setting and the
board_init stub.
Signed-off-by: Robert Marko
Acked-by: Caleb Connolly
---
Changes in v2:
* Drop
arch/arm/mach-ipq40xx/Makefile | 7 ++
arch/arm/mach-ipq40xx/cpu.c| 43 ++
2 files changed, 50 insertions(+)
create mode 100644 arch/arm/mach-ipq40xx/Makefile
create mode 100644 arch/arm/mach-ipq40xx/cpu.c
diff --git a/arch/arm/mach-ipq40xx/Makefile b/arch/arm/mach-ipq40xx/Makefile
new file mode 100644
index 00..d611de9933
--- /dev/null
+++ b/arch/arm/mach-ipq40xx/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024 Sartura Ltd.
+#
+# Author: Robert Marko
+
+obj-y += cpu.o
diff --git a/arch/arm/mach-ipq40xx/cpu.c b/arch/arm/mach-ipq40xx/cpu.c
new file mode 100644
index 00..92c34d6111
--- /dev/null
+++ b/arch/arm/mach-ipq40xx/cpu.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * CPU code for Qualcomm IPQ40xx SoC
+ *
+ * Copyright (c) 2024 Sartura Ltd.
+ *
+ * Author: Robert Marko
+ */
+
+#include
+#include
+
+int dram_init(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+ return fdtdec_setup_mem_size_base();
+}
+
+/*
+ * Enable/Disable D-cache.
+ * I-cache is already enabled in start.S
+ */
+void enable_caches(void)
+{
+ dcache_enable();
+}
+
+void disable_caches(void)
+{
+ dcache_disable();
+}
+
+/*
+ * In case boards need specific init code, they can override this stub.
+ */
+int __weak board_init(void)
+{
+ return 0;
+}
--
2.45.0
[PATCH v2 2/3] mach-ipq40xx: use OF_UPSTREAM
Now that drivers are compatible enough with the upstream DTS, there is no reason to not use the upstream DTS, so imply OF_UPSTREAM by default. Signed-off-by: Robert Marko Acked-by: Caleb Connolly --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 39ad03acd2..914a7552b4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -769,6 +769,7 @@ config ARCH_IPQ40XX select CLK_QCOM_IPQ4019 select PINCTRL_QCOM_IPQ4019 imply CMD_DM + imply OF_UPSTREAM config ARCH_KEYSTONE bool "TI Keystone" -- 2.45.0
[PATCH v3] sysreset: add Qualcomm PSHOLD reset driver
Number of Qualcomm ARMv7 SoC-s did not use PSCI but rather used PSHOLD
(Qualcomm Power Supply Hold Reset) bit to trigger reset or poweroff.
Qualcomm IPQ40XX is one of them, so provide a simple sysreset driver based
on the upstream Linux one, it is DT compatible as well.
Signed-off-by: Robert Marko
Reviewed-by: Caleb Connolly
---
Changes in v3:
* Drop
Changes in v2:
* Use QCOM instead of MSM naming
drivers/sysreset/Kconfig| 6 +++
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_qcom-pshold.c | 55 +
3 files changed, 62 insertions(+)
create mode 100644 drivers/sysreset/sysreset_qcom-pshold.c
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index b64bfadb20..121194e441 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -240,6 +240,12 @@ config SYSRESET_RAA215300
help
Add support for the system reboot via the Renesas RAA215300 PMIC.
+config SYSRESET_QCOM_PSHOLD
+ bool "Support sysreset for Qualcomm SoCs via PSHOLD"
+ depends on ARCH_IPQ40XX
+ help
+ Add support for the system reboot on Qualcomm SoCs via PSHOLD.
+
endif
endmenu
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index d59299aa31..a6a0584585 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -29,4 +29,5 @@ obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_AT91) += sysreset_at91.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
obj-$(CONFIG_SYSRESET_RAA215300) += sysreset_raa215300.o
+obj-$(CONFIG_SYSRESET_QCOM_PSHOLD) += sysreset_qcom-pshold.o
obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
diff --git a/drivers/sysreset/sysreset_qcom-pshold.c
b/drivers/sysreset/sysreset_qcom-pshold.c
new file mode 100644
index 00..4529047853
--- /dev/null
+++ b/drivers/sysreset/sysreset_qcom-pshold.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm PSHOLD reset driver
+ *
+ * Copyright (c) 2024 Sartura Ltd.
+ *
+ * Author: Robert Marko
+ * Based on the Linux msm-poweroff driver.
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+struct qcom_pshold_priv {
+ phys_addr_t base;
+};
+
+static int qcom_pshold_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct qcom_pshold_priv *priv = dev_get_priv(dev);
+
+ writel(0, priv->base);
+ mdelay(1);
+
+ return 0;
+}
+
+static struct sysreset_ops qcom_pshold_ops = {
+ .request = qcom_pshold_request,
+};
+
+static int qcom_pshold_probe(struct udevice *dev)
+{
+ struct qcom_pshold_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr(dev);
+ return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
+}
+
+static const struct udevice_id qcom_pshold_ids[] = {
+ { .compatible = "qcom,pshold", },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(qcom_pshold) = {
+ .name = "qcom_pshold",
+ .id = UCLASS_SYSRESET,
+ .of_match = qcom_pshold_ids,
+ .probe = qcom_pshold_probe,
+ .priv_auto = sizeof(struct qcom_pshold_priv),
+ .ops= _pshold_ops,
+};
--
2.45.0
[RFC PATCH 5/5] sysreset: call .on_reset for UCLASS_SPI_FLASH before reset request
Call .on_reset method for UCLASS_SPI_FLASH devices before requesting reset. This fixes the issue with 4-byte adressing mode being left enabled on board reset. That is an issue on Qualcomm IPQ4019 boards since the CPU expects flash to be in 3-byte adressing mode and will just hang otherwise. Note that this does not fix a case where you remove the power while U-Boot is still running and in that case it will still be stuck in 4-byte mode. Signed-off-by: Robert Marko --- drivers/sysreset/sysreset-uclass.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/sysreset/sysreset-uclass.c b/drivers/sysreset/sysreset-uclass.c index 6151b5fe03..8321cc4230 100644 --- a/drivers/sysreset/sysreset-uclass.c +++ b/drivers/sysreset/sysreset-uclass.c @@ -30,6 +30,13 @@ int sysreset_request(struct udevice *dev, enum sysreset_t type) if (!ops->request) return -ENOSYS; + /* +* Call the .on_reset op for SPI flash devices. +* This is required for most devices in order to exit the +* 4-byte adressing mode. +*/ + uclass_id_on_reset(UCLASS_SPI_FLASH); + return ops->request(dev, type); } -- 2.45.0
[RFC PATCH 4/5] mtd: spi: sf: implement .on_reset method
Implement .on_reset method for SPI flash, by extending the remove method
to exit 4-byte adressing mode in case it was entered before.
This fixes the issue with 4-byte adressing mode being left enabled on
board reset.
That is an issue on Qualcomm IPQ4019 boards since the CPU expects flash
to be in 3-byte adressing mode and will just hang otherwise.
Note that this does not fix a case where you remove the power while U-Boot
is still running and in that case it will still be stuck in 4-byte mode.
Signed-off-by: Robert Marko
---
drivers/mtd/spi/sf_probe.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index de6516f106..31dae17ba0 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -225,6 +225,15 @@ static int spi_flash_std_remove(struct udevice *dev)
struct spi_flash *flash = dev_get_uclass_priv(dev);
int ret;
+ if (flash->addr_width == 4 &&
+ !(flash->info->flags & SPI_NOR_OCTAL_DTR_READ) &&
+ (JEDEC_MFR(flash->info) != SNOR_MFR_SPANSION) &&
+ !(flash->flags & SNOR_F_4B_OPCODES)) {
+ ret = spi_nor_set_4byte(flash, flash->info, 0);
+ if (ret)
+ return ret;
+ }
+
if (CONFIG_IS_ENABLED(SPI_DIRMAP)) {
spi_mem_dirmap_destroy(flash->dirmap.wdesc);
spi_mem_dirmap_destroy(flash->dirmap.rdesc);
@@ -258,6 +267,7 @@ U_BOOT_DRIVER(jedec_spi_nor) = {
.of_match = spi_flash_std_ids,
.probe = spi_flash_std_probe,
.remove = spi_flash_std_remove,
+ .on_reset = spi_flash_std_remove,
.priv_auto = sizeof(struct spi_nor),
.ops= _flash_std_ops,
.flags = DM_FLAG_OS_PREPARE,
--
2.45.0
[RFC PATCH 3/5] mtd: spi-nor: rename and export 4-byte adressing mode function
Currently 4-byte adressing mode function is not exported, but since we plan
to use it outside of the SPI NOR core we need to export it.
While we are here, rename it to align the naming with the rest of exported
functions.
Signed-off-by: Robert Marko
---
drivers/mtd/spi/spi-nor-core.c | 7 +++
include/linux/mtd/spi-nor.h| 10 ++
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 8882b045ce..8a64ee40c3 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -682,8 +682,7 @@ static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
#endif /* !CONFIG_SPI_FLASH_BAR */
/* Enable/disable 4-byte addressing mode. */
-static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
-int enable)
+int spi_nor_set_4byte(struct spi_nor *nor, const struct flash_info *info, int
enable)
{
int status;
bool need_wren = false;
@@ -3481,7 +3480,7 @@ static int s25_s28_post_bfpt_fixup(struct spi_nor *nor,
*/
if (params->size > SZ_128M) {
if (bfpt->dwords[BFPT_DWORD(16)] & BFPT_DWORD16_EX4B_PWRCYC) {
- ret = set_4byte(nor, nor->info, 1);
+ ret = spi_nor_set_4byte(nor, nor->info, 1);
if (ret)
return ret;
}
@@ -3915,7 +3914,7 @@ static int spi_nor_init(struct spi_nor *nor)
*/
if (nor->flags & SNOR_F_BROKEN_RESET)
debug("enabling reset hack; may not recover from
unexpected reboots\n");
- set_4byte(nor, nor->info, 1);
+ spi_nor_set_4byte(nor, nor->info, 1);
}
return 0;
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 80e56cf308..94c0e5e98f 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -646,6 +646,16 @@ static inline int spi_nor_remove(struct spi_nor *nor)
* Return: 0 for success, -errno for failure.
*/
int spi_nor_remove(struct spi_nor *nor);
+
+/**
+ * spi_nor_set_4byte() - perform cleanup before booting to the next stage
+ * @nor: the spi_nor structure
+ * @flash_info:the flash_info structure
+ * @enable:enable or disable 4byte mode
+ *
+ * Return: 0 for success, -errno for failure.
+ */
+int spi_nor_set_4byte(struct spi_nor *nor, const struct flash_info *info, int
enable);
#endif
#endif
--
2.45.0
[RFC PATCH 1/5] dm: core: add on_reset method
Currently, we dont have a specific method that is intented to be called
right before calling board reset.
Intention for this method is to be able to exit 4-byte adressing mode on
SPI-NOR devices before reset.
Signed-off-by: Robert Marko
---
include/dm/device.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dm/device.h b/include/dm/device.h
index add67f9ec0..19713d958c 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -344,6 +344,7 @@ struct udevice_id {
* @probe: Called to probe a device, i.e. activate it
* @remove: Called to remove a device, i.e. de-activate it
* @unbind: Called to unbind a device from its driver
+ * @on_reset: Called befora calling board reset
* @of_to_plat: Called before probe to decode device tree data
* @child_post_bind: Called after a new child has been bound
* @child_pre_probe: Called before a child device is probed. The device has
@@ -379,6 +380,7 @@ struct driver {
int (*probe)(struct udevice *dev);
int (*remove)(struct udevice *dev);
int (*unbind)(struct udevice *dev);
+ int (*on_reset)(struct udevice *dev);
int (*of_to_plat)(struct udevice *dev);
int (*child_post_bind)(struct udevice *dev);
int (*child_pre_probe)(struct udevice *dev);
--
2.45.0
[RFC PATCH 2/5] dm: core: introduce uclass_id_on_reset()
Implement a helper to call .on_reset method for every device in a
certain uclass.
Intention is to use this helper for UCLASS_SPI_FLASH before board
reset to exit 4-byte adressing mode.
Signed-off-by: Robert Marko
---
drivers/core/uclass.c | 13 +
include/dm/uclass.h | 8
2 files changed, 21 insertions(+)
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index e46d5717aa..bed5553d5e 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -831,6 +831,19 @@ int uclass_id_count(enum uclass_id id)
return count;
}
+int uclass_id_on_reset(enum uclass_id id)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+
+ uclass_id_foreach_dev(id, dev, uc) {
+ if (dev->driver->on_reset)
+ return dev->driver->on_reset(dev);
+ }
+
+ return 0;
+}
+
UCLASS_DRIVER(nop) = {
.id = UCLASS_NOP,
.name = "nop",
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index 456eef7f2f..57eb1b144f 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -454,6 +454,14 @@ int uclass_probe_all(enum uclass_id id);
*/
int uclass_id_count(enum uclass_id id);
+/**
+ * uclass_id_on_reset() - call on_reset for devices of a given uclass ID
+ *
+ * @id: uclass ID to look up
+ * Return: 0 if OK, other -ve on error
+ */
+int uclass_id_on_reset(enum uclass_id id);
+
/**
* uclass_id_foreach_dev() - iterate through devices of a given uclass ID
*
--
2.45.0
[RFC PATCH 0/5] Implement exiting 4-byte adressing mode before reset
This fixes the issue with 4-byte adressing mode being left enabled on board reset. That is an issue on Qualcomm IPQ4019 boards since the CPU expects flash to be in 3-byte adressing mode and will just hang otherwise. Note that this does not fix a case where you remove the power while U-Boot is still running and in that case it will still be stuck in 4-byte mode. Robert Marko (5): dm: core: add on_reset method dm: core: introduce uclass_id_on_reset() mtd: spi-nor: rename and export 4-byte adressing mode function mtd: spi: sf: implement .on_reset method sysreset: call .on_reset for UCLASS_SPI_FLASH before reset request drivers/core/uclass.c | 13 + drivers/mtd/spi/sf_probe.c | 10 ++ drivers/mtd/spi/spi-nor-core.c | 7 +++ drivers/sysreset/sysreset-uclass.c | 7 +++ include/dm/device.h| 2 ++ include/dm/uclass.h| 8 include/linux/mtd/spi-nor.h| 10 ++ 7 files changed, 53 insertions(+), 4 deletions(-) -- 2.45.0
Re: [PATCH 0/2] qcom: ehci: enable core + iface clocks
On Thu, May 2, 2024 at 3:41 PM Caleb Connolly wrote: > > Hi Sam, > > On 02/05/2024 15:16, Sam Day wrote: > > These clocks are mandatory, as can be seen in msm_hsusb driver in the > > Linux kernel. > > > > The appropriate HS_USB AHB/SYSTEM clocks were added to gcc_apq8016. > > > > Technically there's other adjacent SoC families that can use the > > msm_hsusb driver with different clocks, but only msm8916/apq8016 are > > currently making use of it so I think this change shouldn't break > > anything elsewhere. > > Thanks for the patches. I have a feeling this might break IPQ4019, you > might need to stub the clks there (cc Robert). Hi, IPQ4019 does not use ehci-msm, but rather DWC3 so it should be fine. Regards, Robert > > Seems like the To: and Cc: addresses aren't all quite right still. > > > > Signed-off-by: Sam Day > > --- > > Sam Day (2): > >clk/qcom: apq8016: add support for USB_HS clocks > >ehci: msm: bring up iface + core clocks > > > > drivers/clk/qcom/clock-apq8016.c | 31 +++ > > drivers/usb/host/ehci-msm.c | 37 > > +++-- > > 2 files changed, 66 insertions(+), 2 deletions(-) > > --- > > base-commit: ff0de1f0557ed7d2dab47ba976a37347a1fdc432 > > change-id: 20240502-msm8916-hs-usb-clocks-34bc22b03f3d > > > > Best regards, > > -- > // Caleb (they/them) -- Robert Marko Staff Embedded Linux Engineer Sartura Ltd. Lendavska ulica 16a 1 Zagreb, Croatia Email: robert.ma...@sartura.hr Web: www.sartura.hr
[PATCH 2/2] mtd: spi-nor-core: add 4-byte OPCODE support for Winbond W25Q256JV
Winbond W25Q256FV and W25Q256JV share the same JEDEC ID, but only
W25Q256JV fully supports 4-byte OPCODE-s.
In order to differentiate between them we can use the SFDP header version
and apply a fixup post BFPT.
Based on upstream Linux commit ("mtd: spi-nor: winbond: Fix 4-byte opcode
support for w25q256").
Signed-off-by: Robert Marko
---
drivers/mtd/spi/spi-nor-core.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 7615ba602f..8882b045ce 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3816,6 +3816,32 @@ static struct spi_nor_fixups macronix_octal_fixups = {
};
#endif /* CONFIG_SPI_FLASH_MACRONIX */
+#if CONFIG_IS_ENABLED(SPI_FLASH_WINBOND)
+static int w25q256_post_bfpt_fixup(struct spi_nor *nor,
+ const struct sfdp_parameter_header *header,
+ const struct sfdp_bfpt *bfpt,
+ struct spi_nor_flash_parameter *params)
+{
+ /*
+* W25Q256JV supports 4B opcodes but W25Q256FV does not.
+* Unfortunately, Winbond has re-used the same JEDEC ID for both
+* variants which prevents us from defining a new entry in the parts
+* table.
+* To differentiate between W25Q256JV and W25Q256FV check SFDP header
+* version: only JV has JESD216A compliant structure (version 5).
+*/
+ if(header->major == SFDP_JESD216_MAJOR &&
+ header->minor == SFDP_JESD216A_MINOR)
+ nor->flags |= SNOR_F_4B_OPCODES;
+
+ return 0;
+}
+
+static struct spi_nor_fixups w25q256_fixups = {
+ .post_bfpt = w25q256_post_bfpt_fixup,
+};
+#endif /* CONFIG_SPI_FLASH_WINBOND */
+
/** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
* @nor: pointer to a 'struct spi_nor'
*
@@ -4004,6 +4030,11 @@ void spi_nor_set_fixups(struct spi_nor *nor)
#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
nor->fixups = _octal_fixups;
#endif /* SPI_FLASH_MACRONIX */
+
+#if CONFIG_IS_ENABLED(SPI_FLASH_WINBOND)
+ if (!strcmp(nor->info->name, "w25q256"))
+ nor->fixups = _fixups;
+#endif /* SPI_FLASH_WINBOND */
}
int spi_nor_scan(struct spi_nor *nor)
--
2.44.0
[PATCH 1/2] mtd: spi-nor-core: allow overriding 4-byte OPCODE support
Currently, the only way to indicate 4-byte OPCODE support is by setting
the SPI_NOR_4B_OPCODES feature flag for each JEDEC ID in spi_nor_ids[].
However, its becoming increasingly common practice for vendors to reuse
the same JEDEC ID for new revisions of current parts.
For example Winbond W25Q256FV does not fully support 4-byte OPCODE-s while
newer W25Q256JV revision does fully support them but they share the same
JEDEC ID thus currently its not possible to advertise support for 4-byte
OPCODE-s on W25Q256JV.
Luckily for us, there usually is a way to differentiate between parts with
the same JEDEC ID by differences in SFDP tables, so in order to be able to
apply a fixup after they are parsed lets add a feature flag that we can
override.
Signed-off-by: Robert Marko
---
drivers/mtd/spi/spi-nor-core.c | 6 --
include/linux/mtd/spi-nor.h| 1 +
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index f86003ca8c..7615ba602f 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3879,7 +3879,7 @@ static int spi_nor_init(struct spi_nor *nor)
if (nor->addr_width == 4 &&
!(nor->info->flags & SPI_NOR_OCTAL_DTR_READ) &&
(JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
- !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
+ !(nor->flags & SNOR_F_4B_OPCODES)) {
/*
* If the RESET# pin isn't hooked up properly, or the system
* otherwise doesn't perform a reset command in the boot
@@ -4118,6 +4118,8 @@ int spi_nor_scan(struct spi_nor *nor)
nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
if (info->flags & USE_CLSR)
nor->flags |= SNOR_F_USE_CLSR;
+ if (info->flags & SPI_NOR_4B_OPCODES)
+ nor->flags |= SNOR_F_4B_OPCODES;
if (info->flags & SPI_NOR_NO_ERASE)
mtd->flags |= MTD_NO_ERASE;
@@ -4156,7 +4158,7 @@ int spi_nor_scan(struct spi_nor *nor)
/* enable 4-byte addressing if the device exceeds 16MiB */
nor->addr_width = 4;
if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
- info->flags & SPI_NOR_4B_OPCODES)
+ nor->flags & SNOR_F_4B_OPCODES)
spi_nor_set_4byte_opcodes(nor, info);
#else
/* Configure the BAR - discover bank cmds and read current bank */
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index d1dbf3eadb..80e56cf308 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -294,6 +294,7 @@ enum spi_nor_option_flags {
SNOR_F_BROKEN_RESET = BIT(6),
SNOR_F_SOFT_RESET = BIT(7),
SNOR_F_IO_MODE_EN_VOLATILE = BIT(8),
+ SNOR_F_4B_OPCODES = BIT(9),
};
struct spi_nor;
--
2.44.0
[PATCH v2] sysreset: add Qualcomm PSHOLD reset driver
Number of Qualcomm ARMv7 SoC-s did not use PSCI but rather used PSHOLD
(Qualcomm Power Supply Hold Reset) bit to trigger reset or poweroff.
Qualcomm IPQ40XX is one of them, so provide a simple sysreset driver based
on the upstream Linux one, it is DT compatible as well.
Signed-off-by: Robert Marko
Reviewed-by: Caleb Connolly
---
Changes in v2:
* Use QCOM instead of MSM naming
drivers/sysreset/Kconfig| 6 +++
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_qcom-pshold.c | 56 +
3 files changed, 63 insertions(+)
create mode 100644 drivers/sysreset/sysreset_qcom-pshold.c
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 49c0787b26..920dceb70b 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -235,6 +235,12 @@ config SYSRESET_RAA215300
help
Add support for the system reboot via the Renesas RAA215300 PMIC.
+config SYSRESET_QCOM_PSHOLD
+ bool "Support sysreset for Qualcomm SoCs via PSHOLD"
+ depends on ARCH_IPQ40XX
+ help
+ Add support for the system reboot on Qualcomm SoCs via PSHOLD.
+
endif
endmenu
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index e0e732205d..f0620c391e 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -28,4 +28,5 @@ obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_AT91) += sysreset_at91.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
obj-$(CONFIG_SYSRESET_RAA215300) += sysreset_raa215300.o
+obj-$(CONFIG_SYSRESET_QCOM_PSHOLD) += sysreset_qcom-pshold.o
obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
diff --git a/drivers/sysreset/sysreset_qcom-pshold.c
b/drivers/sysreset/sysreset_qcom-pshold.c
new file mode 100644
index 00..25231cf5e2
--- /dev/null
+++ b/drivers/sysreset/sysreset_qcom-pshold.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm PSHOLD reset driver
+ *
+ * Copyright (c) 2024 Sartura Ltd.
+ *
+ * Author: Robert Marko
+ * Based on the Linux msm-poweroff driver.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct qcom_pshold_priv {
+ phys_addr_t base;
+};
+
+static int qcom_pshold_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct qcom_pshold_priv *priv = dev_get_priv(dev);
+
+ writel(0, priv->base);
+ mdelay(1);
+
+ return 0;
+}
+
+static struct sysreset_ops qcom_pshold_ops = {
+ .request = qcom_pshold_request,
+};
+
+static int qcom_pshold_probe(struct udevice *dev)
+{
+ struct qcom_pshold_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr(dev);
+ return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
+}
+
+static const struct udevice_id qcom_pshold_ids[] = {
+ { .compatible = "qcom,pshold", },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(qcom_pshold) = {
+ .name = "qcom_pshold",
+ .id = UCLASS_SYSRESET,
+ .of_match = qcom_pshold_ids,
+ .probe = qcom_pshold_probe,
+ .priv_auto = sizeof(struct qcom_pshold_priv),
+ .ops= _pshold_ops,
+};
--
2.44.0
[PATCH 3/3] arm: dts: drop downstream IPQ4019 DTSI
We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so
lets drop our downstream DTSI.
Signed-off-by: Robert Marko
---
arch/arm/dts/qcom-ipq4019.dtsi | 202 -
1 file changed, 202 deletions(-)
delete mode 100644 arch/arm/dts/qcom-ipq4019.dtsi
diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi
deleted file mode 100644
index f9489e42ea..00
--- a/arch/arm/dts/qcom-ipq4019.dtsi
+++ /dev/null
@@ -1,202 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2019 Sartura Ltd.
- *
- * Author: Robert Marko
- */
-
- /dts-v1/;
-
-#include "skeleton.dtsi"
-#include
-#include
-#include
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- model = "Qualcomm Technologies, Inc. IPQ4019";
- compatible = "qcom,ipq4019";
-
- aliases {
- serial0 = _uart1;
- spi0 = _spi1;
- };
-
- reserved-memory {
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- ranges;
-
- smem_mem: smem_region: smem@87e0 {
- reg = <0x87e0 0x08>;
- no-map;
- };
-
- tz@87e8 {
- reg = <0x87e8 0x18>;
- no-map;
- };
- };
-
- smem {
- compatible = "qcom,smem";
- memory-region = <_mem>;
- };
-
- soc: soc {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- compatible = "simple-bus";
-
- gcc: clock-controller@180 {
- compatible = "qcom,gcc-ipq4019";
- reg = <0x180 0x6>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- bootph-all;
- };
-
- rng: rng@22000 {
- compatible = "qcom,prng";
- reg = <0x22000 0x140>;
- clocks = < GCC_PRNG_AHB_CLK>;
- status = "disabled";
- };
-
- soc_gpios: pinctrl@100 {
- compatible = "qcom,ipq4019-pinctrl";
- reg = <0x100 0x30>;
- gpio-controller;
- gpio-count = <100>;
- gpio-bank-name="soc";
- #gpio-cells = <2>;
- bootph-all;
- };
-
- blsp1_uart1: serial@78af000 {
- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- reg = <0x78af000 0x200>;
- clock = < GCC_BLSP1_UART1_APPS_CLK>;
- bit-rate = <0xFF>;
- status = "disabled";
- bootph-all;
- };
-
- blsp1_spi1: spi@78b5000 {
- compatible = "qcom,spi-qup-v2.2.1";
- reg = <0x78b5000 0x600>;
- clocks = < GCC_BLSP1_QUP1_SPI_APPS_CLK>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- bootph-all;
- };
-
- mdio: mdio@9 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "qcom,ipq4019-mdio";
- reg = <0x9 0x64>;
- status = "disabled";
-
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- ethphy1: ethernet-phy@1 {
- reg = <1>;
- };
-
- ethphy2: ethernet-phy@2 {
- reg = <2>;
- };
-
- ethphy3: ethernet-phy@3 {
- reg = <3>;
- };
-
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
- };
-
- usb3_ss_phy: ssphy@9a000 {
- compatible = "qcom,usb-ss-ipq4019-phy";
- #phy-cells = <0>;
- reg = <0x9a000 0x800>;
- reg-names = "phy_base";
- resets = < USB3_UNIPHY_PHY_ARES>;
-
[PATCH 2/3] mach-ipq40xx: use OF_UPSTREAM
Now that drivers are compatible enough with the upstream DTS, there is no reason to not use the upstream DTS, so imply OF_UPSTREAM by default. Signed-off-by: Robert Marko --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 93e12d8d53..5c2769b59d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -768,6 +768,7 @@ config ARCH_IPQ40XX select CLK_QCOM_IPQ4019 select PINCTRL_QCOM_IPQ4019 imply CMD_DM + imply OF_UPSTREAM config ARCH_KEYSTONE bool "TI Keystone" -- 2.44.0
[PATCH 1/3] mach-ipq40xx: add CPU specific code
Provide basic DRAM info population from DT, cache setting and the
board_init stub.
Signed-off-by: Robert Marko
---
arch/arm/mach-ipq40xx/Makefile | 7 ++
arch/arm/mach-ipq40xx/cpu.c| 44 ++
2 files changed, 51 insertions(+)
create mode 100644 arch/arm/mach-ipq40xx/Makefile
create mode 100644 arch/arm/mach-ipq40xx/cpu.c
diff --git a/arch/arm/mach-ipq40xx/Makefile b/arch/arm/mach-ipq40xx/Makefile
new file mode 100644
index 00..d611de9933
--- /dev/null
+++ b/arch/arm/mach-ipq40xx/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024 Sartura Ltd.
+#
+# Author: Robert Marko
+
+obj-y += cpu.o
diff --git a/arch/arm/mach-ipq40xx/cpu.c b/arch/arm/mach-ipq40xx/cpu.c
new file mode 100644
index 00..0446627a8f
--- /dev/null
+++ b/arch/arm/mach-ipq40xx/cpu.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * CPU code for Qualcomm IPQ40xx SoC
+ *
+ * Copyright (c) 2024 Sartura Ltd.
+ *
+ * Author: Robert Marko
+ */
+
+#include
+#include
+#include
+
+int dram_init(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+ return fdtdec_setup_mem_size_base();
+}
+
+/*
+ * Enable/Disable D-cache.
+ * I-cache is already enabled in start.S
+ */
+void enable_caches(void)
+{
+ dcache_enable();
+}
+
+void disable_caches(void)
+{
+ dcache_disable();
+}
+
+/*
+ * In case boards need specific init code, they can override this stub.
+ */
+int __weak board_init(void)
+{
+ return 0;
+}
--
2.44.0
[PATCH 4/4] MAINTAINERS: IPQ40XX: add pinctrl driver
Pinctrl drivers were moved to a dedicated directory but the entry was never updated, so add the pinctrl-ipq4019 driver entry. Signed-off-by: Robert Marko --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 207c8b763f..382376b8e3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -343,6 +343,7 @@ F: drivers/phy/phy-qcom-ipq4019-usb.c F: drivers/spi/spi-qup.c F: drivers/net/mdio-ipq4019.c F: drivers/rng/msm_rng.c +F: drivers/pinctrl/qcom/pinctrl-ipq4019.c ARM LAYERSCAPE SFP M: Sean Anderson -- 2.44.0
[PATCH 3/4] MAINTAINERS: IPQ40XX: add clock-ipq4019 instead of reset driver
The reset handling was added to the clock drivers but the entry was never updated, so add the clock-ipq4019 driver instead. Signed-off-by: Robert Marko --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index fdce7c8334..207c8b763f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -338,7 +338,7 @@ M: Luka Perkov S: Maintained F: arch/arm/mach-ipq40xx/ F: include/dt-bindings/clock/qcom,gcc-ipq4019.h -F: drivers/reset/reset-ipq4019.c +F: drivers/clk/qcom/clock-ipq4019.c F: drivers/phy/phy-qcom-ipq4019-usb.c F: drivers/spi/spi-qup.c F: drivers/net/mdio-ipq4019.c -- 2.44.0
[PATCH 2/4] MAINTAINERS: IPQ40XX: update GCC dt-bindings
The separate clock and reset dt-bindings for IPQ40XX were merged into one recently, but the entry was not updated so do it now. Signed-off-by: Robert Marko --- MAINTAINERS | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8691500d28..fdce7c8334 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -337,8 +337,7 @@ M: Robert Marko M: Luka Perkov S: Maintained F: arch/arm/mach-ipq40xx/ -F: include/dt-bindings/clock/qcom,ipq4019-gcc.h -F: include/dt-bindings/reset/qcom,ipq4019-reset.h +F: include/dt-bindings/clock/qcom,gcc-ipq4019.h F: drivers/reset/reset-ipq4019.c F: drivers/phy/phy-qcom-ipq4019-usb.c F: drivers/spi/spi-qup.c -- 2.44.0
[PATCH 1/4] MAINTAINERS: IPQ40XX: remove Luka Kovacic as maintainer
Luka Kovacic is no longer at Sartura, so remove him as one of IPQ40xx maintainers. Signed-off-by: Robert Marko --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index d0a4a28b40..8691500d28 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -334,7 +334,6 @@ F: drivers/spi/gxp_spi.c ARM IPQ40XX M: Robert Marko -M: Luka Kovacic M: Luka Perkov S: Maintained F: arch/arm/mach-ipq40xx/ -- 2.44.0
[PATCH] sysreset: add Qualcomm PSHOLD reset driver
Number of Qualcomm ARMv7 SoC-s did not use PSCI but rather used PSHOLD
(Qualcomm Power Supply Hold Reset) bit to trigger reset or poweroff.
Qualcomm IPQ40XX is one of them, so provide a simple sysreset driver based
on the upstream Linux one, it is DT compatible as well.
Signed-off-by: Robert Marko
---
drivers/sysreset/Kconfig | 6 +++
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_msm-pshold.c | 56 ++
3 files changed, 63 insertions(+)
create mode 100644 drivers/sysreset/sysreset_msm-pshold.c
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 49c0787b26..30ff9e576d 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -235,6 +235,12 @@ config SYSRESET_RAA215300
help
Add support for the system reboot via the Renesas RAA215300 PMIC.
+config SYSRESET_MSM_PSHOLD
+ bool "Support sysreset for Qualcomm SoCs via PSHOLD"
+ depends on ARCH_IPQ40XX
+ help
+ Add support for the system reboot on Qualcomm SoCs via PSHOLD.
+
endif
endmenu
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index e0e732205d..da61dca8e2 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -28,4 +28,5 @@ obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_AT91) += sysreset_at91.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
obj-$(CONFIG_SYSRESET_RAA215300) += sysreset_raa215300.o
+obj-$(CONFIG_SYSRESET_MSM_PSHOLD) += sysreset_msm-pshold.o
obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
diff --git a/drivers/sysreset/sysreset_msm-pshold.c
b/drivers/sysreset/sysreset_msm-pshold.c
new file mode 100644
index 00..d25a412954
--- /dev/null
+++ b/drivers/sysreset/sysreset_msm-pshold.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm PSHOLD reset driver
+ *
+ * Copyright (c) 2024 Sartura Ltd.
+ *
+ * Author: Robert Marko
+ * Based on the Linux msm-poweroff driver.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct msm_pshold_priv {
+ phys_addr_t base;
+};
+
+static int msm_pshold_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct msm_pshold_priv *priv = dev_get_priv(dev);
+
+ writel(0, priv->base);
+ mdelay(1);
+
+ return 0;
+}
+
+static struct sysreset_ops msm_pshold_ops = {
+ .request = msm_pshold_request,
+};
+
+static int msm_pshold_probe(struct udevice *dev)
+{
+ struct msm_pshold_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr(dev);
+ return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
+}
+
+static const struct udevice_id msm_pshold_ids[] = {
+ { .compatible = "qcom,pshold", },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(msm_pshold) = {
+ .name = "msm_pshold",
+ .id = UCLASS_SYSRESET,
+ .of_match = msm_pshold_ids,
+ .probe = msm_pshold_probe,
+ .priv_auto = sizeof(struct msm_pshold_priv),
+ .ops= _pshold_ops,
+};
--
2.44.0
[PATCH] .gitignore: add LTO generated file
Currently, keep-syms-lto.c is being generated if LTO is enabled but unlike keep-syms-lto.o it is not being ignored, so lets add keep-syms-lto.* to .gitignore. Signed-off-by: Robert Marko --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index be137040a2..324078769b 100644 --- a/.gitignore +++ b/.gitignore @@ -67,6 +67,7 @@ fit-dtb.blob* /Test* /capsule.*.efi-capsule /capsule*.map +/keep-syms-lto.* # # Generated include files -- 2.44.0
[PATCH v2 5/5] pinctrl: qcom: ipq4019: support all pin functions
Currently, IPQ4019 pinctrl driver supports only a very limited number of
pin functions and is not fully DT compatible with Linux pinctrl nodes.
IPQ40xx SoC-s sometimes use different pin function numbers for the same
function depending on the pin number, so for example I2C0 on GPIO58 uses
function number 3 while on GPIO59 it uses function number 2.
So, in order to make the driver compatible with upstream DTS to avoid the
need to patch the pinctrl nodes in U-Boot and support all of the missing
pin functions lets rework the driver based on upstream Linux IPQ4019
pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses
different function numbers pased on the exact pin number.
Signed-off-by: Robert Marko
---
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 306 +++--
1 file changed, 293 insertions(+), 13 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index 48644a51ae..26ab487857 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -14,19 +14,291 @@
#define MAX_PIN_NAME_LEN 32
static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+enum ipq4019_functions {
+ qca_mux_gpio,
+ qca_mux_aud_pin,
+ qca_mux_audio_pwm,
+ qca_mux_blsp_i2c0,
+ qca_mux_blsp_i2c1,
+ qca_mux_blsp_spi0,
+ qca_mux_blsp_spi1,
+ qca_mux_blsp_uart0,
+ qca_mux_blsp_uart1,
+ qca_mux_chip_rst,
+ qca_mux_i2s_rx,
+ qca_mux_i2s_spdif_in,
+ qca_mux_i2s_spdif_out,
+ qca_mux_i2s_td,
+ qca_mux_i2s_tx,
+ qca_mux_jtag,
+ qca_mux_led0,
+ qca_mux_led1,
+ qca_mux_led2,
+ qca_mux_led3,
+ qca_mux_led4,
+ qca_mux_led5,
+ qca_mux_led6,
+ qca_mux_led7,
+ qca_mux_led8,
+ qca_mux_led9,
+ qca_mux_led10,
+ qca_mux_led11,
+ qca_mux_mdc,
+ qca_mux_mdio,
+ qca_mux_pcie,
+ qca_mux_pmu,
+ qca_mux_prng_rosc,
+ qca_mux_qpic,
+ qca_mux_rgmii,
+ qca_mux_rmii,
+ qca_mux_sdio,
+ qca_mux_smart0,
+ qca_mux_smart1,
+ qca_mux_smart2,
+ qca_mux_smart3,
+ qca_mux_tm,
+ qca_mux_wifi0,
+ qca_mux_wifi1,
+ qca_mux_NA,
+};
+
+#define QCA_PIN_FUNCTION(fname)\
+ [qca_mux_##fname] = {#fname, qca_mux_##fname}
+
static const struct pinctrl_function msm_pinctrl_functions[] = {
- {"gpio", 0},
- {"blsp_uart0_0", 1}, /* Only for GPIO:16,17 */
- {"blsp_uart0_1", 2}, /* Only for GPIO:60,61 */
- {"blsp_uart1", 1},
- {"blsp_spi0_0", 1}, /* Only for GPIO:12,13,14,15 */
- {"blsp_spi0_1", 2}, /* Only for GPIO:54,55,56,57 */
- {"blsp_spi1", 2},
- {"mdio_0", 1}, /* Only for GPIO6 */
- {"mdio_1", 2}, /* Only for GPIO53 */
- {"mdc_0", 1}, /* Only for GPIO7 */
- {"mdc_1", 2}, /* Only for GPIO52 */
+ QCA_PIN_FUNCTION(aud_pin),
+ QCA_PIN_FUNCTION(audio_pwm),
+ QCA_PIN_FUNCTION(blsp_i2c0),
+ QCA_PIN_FUNCTION(blsp_i2c1),
+ QCA_PIN_FUNCTION(blsp_spi0),
+ QCA_PIN_FUNCTION(blsp_spi1),
+ QCA_PIN_FUNCTION(blsp_uart0),
+ QCA_PIN_FUNCTION(blsp_uart1),
+ QCA_PIN_FUNCTION(chip_rst),
+ QCA_PIN_FUNCTION(gpio),
+ QCA_PIN_FUNCTION(i2s_rx),
+ QCA_PIN_FUNCTION(i2s_spdif_in),
+ QCA_PIN_FUNCTION(i2s_spdif_out),
+ QCA_PIN_FUNCTION(i2s_td),
+ QCA_PIN_FUNCTION(i2s_tx),
+ QCA_PIN_FUNCTION(jtag),
+ QCA_PIN_FUNCTION(led0),
+ QCA_PIN_FUNCTION(led1),
+ QCA_PIN_FUNCTION(led2),
+ QCA_PIN_FUNCTION(led3),
+ QCA_PIN_FUNCTION(led4),
+ QCA_PIN_FUNCTION(led5),
+ QCA_PIN_FUNCTION(led6),
+ QCA_PIN_FUNCTION(led7),
+ QCA_PIN_FUNCTION(led8),
+ QCA_PIN_FUNCTION(led9),
+ QCA_PIN_FUNCTION(led10),
+ QCA_PIN_FUNCTION(led11),
+ QCA_PIN_FUNCTION(mdc),
+ QCA_PIN_FUNCTION(mdio),
+ QCA_PIN_FUNCTION(pcie),
+ QCA_PIN_FUNCTION(pmu),
+ QCA_PIN_FUNCTION(prng_rosc),
+ QCA_PIN_FUNCTION(qpic),
+ QCA_PIN_FUNCTION(rgmii),
+ QCA_PIN_FUNCTION(rmii),
+ QCA_PIN_FUNCTION(sdio),
+ QCA_PIN_FUNCTION(smart0),
+ QCA_PIN_FUNCTION(smart1),
+ QCA_PIN_FUNCTION(smart2),
+ QCA_PIN_FUNCTION(smart3),
+ QCA_PIN_FUNCTION(tm),
+ QCA_PIN_FUNCTION(wifi0),
+ QCA_PIN_FUNCTION(wifi1),
};
+
+typedef unsigned int msm_pin_function[15];
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13,
f14) \
+ [id] = {qca_mux_gpio, /* gpio mode */ \
+ qca_mux_##f1, \
+ qca_mux_##f2, \
+ qca_mux_##f3, \
+ qca_mux_
[PATCH v2 4/5] pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC
If compiled with logging and debug UART support, the following is printed:
serial_msm serial@78af000: pinctrl_select_state_full:
uclass_get_device_by_phandle_id: err=-19
This is due to the fact that IPQ4019 pinctrl driver is not available prior
to relocation and thus MSM serial will fail probing as pinctrl provider is
not available.
So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this.
Signed-off-by: Robert Marko
---
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index 4fcc4b1810..48644a51ae 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -68,4 +68,5 @@ U_BOOT_DRIVER(pinctrl_ipq4019) = {
.of_match = msm_pinctrl_ids,
.ops= _pinctrl_ops,
.bind = msm_pinctrl_bind,
+ .flags = DM_FLAG_PRE_RELOC,
};
--
2.44.0
[PATCH v2 3/5] pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS
We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so
as a preparation update pinctrl driver to look for the upstream pin format.
Signed-off-by: Robert Marko
Reviewed-by: Caleb Connolly
---
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index 4479230313..4fcc4b1810 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -36,7 +36,7 @@ static const char *ipq4019_get_function_name(struct udevice
*dev,
static const char *ipq4019_get_pin_name(struct udevice *dev,
unsigned int selector)
{
- snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
return pin_name;
}
--
2.44.0
[PATCH v2 2/5] mach-ipq40xx: import GPIO header from mach-snapgradon
Pinctrl driver was refactored and moved, but the required header that
it depends on was not included.
Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx")
Signed-off-by: Robert Marko
---
arch/arm/mach-ipq40xx/include/mach/gpio.h | 37 +++
1 file changed, 31 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-ipq40xx/include/mach/gpio.h
b/arch/arm/mach-ipq40xx/include/mach/gpio.h
index a45747c0fe..53c6ae0649 100644
--- a/arch/arm/mach-ipq40xx/include/mach/gpio.h
+++ b/arch/arm/mach-ipq40xx/include/mach/gpio.h
@@ -1,10 +1,35 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Empty gpio.h
+ * Qualcomm common pin control data.
*
- * This file must stay as arch/arm/include/asm/gpio.h requires it.
- *
- * Copyright (c) 2019 Sartura Ltd.
- *
- * Author: Robert Marko
+ * Copyright (C) 2023 Linaro Ltd.
*/
+#ifndef _QCOM_GPIO_H_
+#define _QCOM_GPIO_H_
+
+#include
+#include
+
+struct msm_pin_data {
+ int pin_count;
+ const unsigned int *pin_offsets;
+ /* Index of first special pin, these are ignored for now */
+ unsigned int special_pins_start;
+};
+
+static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int
selector)
+{
+ u32 out = (selector * 0x1000);
+
+ if (offs)
+ return out + offs[selector];
+
+ return out;
+}
+
+static inline bool qcom_is_special_pin(const struct msm_pin_data *pindata,
unsigned int pin)
+{
+ return pindata->special_pins_start && pin >=
pindata->special_pins_start;
+}
+
+#endif /* _QCOM_GPIO_H_ */
--
2.44.0
[PATCH v2 1/5] pinctrl: qcom: allow selecting with ARCH_IPQ40XX
IPQ4019 pinctrl driver was moved to the dedicated Qualcomm pinctrl
directory, but the KConfig depends on ARCH_SNAPDRAGON only and thus
PINCTRL_QCOM_IPQ4019 cannot be selected when ARCH_IPQ40XX is used.
Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx")
Signed-off-by: Robert Marko
Reviewed-by: Caleb Connolly
---
drivers/pinctrl/qcom/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 2fe6398147..bd2019c866 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -1,4 +1,4 @@
-if ARCH_SNAPDRAGON
+if ARCH_SNAPDRAGON || ARCH_IPQ40XX
config PINCTRL_QCOM
depends on PINCTRL_GENERIC
--
2.44.0
Re: [PATCH 2/3] mach-ipq40xx: import GPIO header from mach-snapgradon
On Thu, Apr 18, 2024 at 1:02 PM Caleb Connolly
wrote:
>
> Hi Robert,
>
> On 18/04/2024 10:14, Robert Marko wrote:
> > Pinctrl driver was refactored and moved, but the required header that
> > it depends on was not included.
>
> Thanks for these patches!
>
> I'm a bit worried about duplicating this header file, we could probably
> move it to the main include directory instead?
Hi Caleb,
That works for me as its a straight copy from mach-snapdragon.
>
> Alternatively, do you think it would be sensible to combine
> mach-snapdragon with mach-ipq40xx ?
>
> I received some patches a while ago from some Qualcomm engineers trying
> to introduce support for newer IPQ SoCs, where they also seem to want to
> build U-Boot as 32-bit (something I guess ipq40xx may also do?).
If it's possible, I would prefer to keep mach-ipq40xx separate and
probably convert it
to mach-ipq later since I would also love to see some newer SoC-s as well.
While Snapdragon and IPQ40xx are similar currently they will diverge for sure.
I dont understand why Qualcomm still insists on building the stock
U-Boot in ARMv7 32-bit
compatibility mode for all of the Cortex-A53 based IPQ807x/60xx/50xx and so on.
Regards,
Robert
>
> I'm easy either way, just want to get a better understanding of this.
>
> Kind regards,
> >
> > Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx")
> > Signed-off-by: Robert Marko
> > ---
> > arch/arm/mach-ipq40xx/include/mach/gpio.h | 37 +++
> > 1 file changed, 31 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm/mach-ipq40xx/include/mach/gpio.h
> > b/arch/arm/mach-ipq40xx/include/mach/gpio.h
> > index a45747c0fe..53c6ae0649 100644
> > --- a/arch/arm/mach-ipq40xx/include/mach/gpio.h
> > +++ b/arch/arm/mach-ipq40xx/include/mach/gpio.h
> > @@ -1,10 +1,35 @@
> > /* SPDX-License-Identifier: GPL-2.0+ */
> > /*
> > - * Empty gpio.h
> > + * Qualcomm common pin control data.
> > *
> > - * This file must stay as arch/arm/include/asm/gpio.h requires it.
> > - *
> > - * Copyright (c) 2019 Sartura Ltd.
> > - *
> > - * Author: Robert Marko
> > + * Copyright (C) 2023 Linaro Ltd.
> > */
> > +#ifndef _QCOM_GPIO_H_
> > +#define _QCOM_GPIO_H_
> > +
> > +#include
> > +#include
> > +
> > +struct msm_pin_data {
> > + int pin_count;
> > + const unsigned int *pin_offsets;
> > + /* Index of first special pin, these are ignored for now */
> > + unsigned int special_pins_start;
> > +};
> > +
> > +static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int
> > selector)
> > +{
> > + u32 out = (selector * 0x1000);
> > +
> > + if (offs)
> > + return out + offs[selector];
> > +
> > + return out;
> > +}
> > +
> > +static inline bool qcom_is_special_pin(const struct msm_pin_data *pindata,
> > unsigned int pin)
> > +{
> > + return pindata->special_pins_start && pin >=
> > pindata->special_pins_start;
> > +}
> > +
> > +#endif /* _QCOM_GPIO_H_ */
>
> --
> // Caleb (they/them)
--
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
1 Zagreb, Croatia
Email: robert.ma...@sartura.hr
Web: www.sartura.hr
[PATCH] arm: mach-ipq40xx: dont select SMEM by default
IPQ40xx SoC-s dont have proper SMEM support like more modern Qualcomm SoC-s so there is no point in selecting the required drivers. Signed-off-by: Robert Marko --- arch/arm/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 23ee25269a..922c28cca9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -762,10 +762,8 @@ config ARCH_IPQ40XX select DM_SERIAL select DM_RESET select GPIO_EXTRA_HEADER - select MSM_SMEM select PINCTRL select CLK - select SMEM select OF_CONTROL select CLK_QCOM_IPQ4019 select PINCTRL_QCOM_IPQ4019 -- 2.44.0
[PATCH 3/3] pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS
We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so
as a preparation update pinctrl driver to look for the upstream pin format.
Signed-off-by: Robert Marko
---
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index 4479230313..4fcc4b1810 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -36,7 +36,7 @@ static const char *ipq4019_get_function_name(struct udevice
*dev,
static const char *ipq4019_get_pin_name(struct udevice *dev,
unsigned int selector)
{
- snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
return pin_name;
}
--
2.44.0
[PATCH 2/3] mach-ipq40xx: import GPIO header from mach-snapgradon
Pinctrl driver was refactored and moved, but the required header that
it depends on was not included.
Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx")
Signed-off-by: Robert Marko
---
arch/arm/mach-ipq40xx/include/mach/gpio.h | 37 +++
1 file changed, 31 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-ipq40xx/include/mach/gpio.h
b/arch/arm/mach-ipq40xx/include/mach/gpio.h
index a45747c0fe..53c6ae0649 100644
--- a/arch/arm/mach-ipq40xx/include/mach/gpio.h
+++ b/arch/arm/mach-ipq40xx/include/mach/gpio.h
@@ -1,10 +1,35 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Empty gpio.h
+ * Qualcomm common pin control data.
*
- * This file must stay as arch/arm/include/asm/gpio.h requires it.
- *
- * Copyright (c) 2019 Sartura Ltd.
- *
- * Author: Robert Marko
+ * Copyright (C) 2023 Linaro Ltd.
*/
+#ifndef _QCOM_GPIO_H_
+#define _QCOM_GPIO_H_
+
+#include
+#include
+
+struct msm_pin_data {
+ int pin_count;
+ const unsigned int *pin_offsets;
+ /* Index of first special pin, these are ignored for now */
+ unsigned int special_pins_start;
+};
+
+static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int
selector)
+{
+ u32 out = (selector * 0x1000);
+
+ if (offs)
+ return out + offs[selector];
+
+ return out;
+}
+
+static inline bool qcom_is_special_pin(const struct msm_pin_data *pindata,
unsigned int pin)
+{
+ return pindata->special_pins_start && pin >=
pindata->special_pins_start;
+}
+
+#endif /* _QCOM_GPIO_H_ */
--
2.44.0
[PATCH 1/3] pinctrl: qcom: allow selecting with ARCH_IPQ40XX
IPQ4019 pinctrl driver was moved to the dedicated Qualcomm pinctrl
directory, but the KConfig depends on ARCH_SNAPDRAGON only and thus
PINCTRL_QCOM_IPQ4019 cannot be selected when ARCH_IPQ40XX is used.
Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx")
Signed-off-by: Robert Marko
---
drivers/pinctrl/qcom/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 2fe6398147..bd2019c866 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -1,4 +1,4 @@
-if ARCH_SNAPDRAGON
+if ARCH_SNAPDRAGON || ARCH_IPQ40XX
config PINCTRL_QCOM
depends on PINCTRL_GENERIC
--
2.44.0
Re: [PATCH 1/3] serial: allow selecting MSM debug UART with ARCH_IPQ40XX
On Mon, Apr 15, 2024 at 1:21 PM Caleb Connolly wrote: > > Hi Robert, > > Happy to see someone working on those IPQ platforms. If it makes sense > to then I'd be happy to adopt them under ARCH_SNAPDRAGON at some point? > I'm not hugely familiar with the usecase here (but eager to learn more!). Well, IPQ40xx is quite a popular WiSoC family and its cheap but the stock bootloader limits any kind of custom use case, so here we are. Regards, Robert > > On 15/04/2024 11:49, Robert Marko wrote: > > Currently, DEBUG_UART_MSM depends on ARCH_SNAPDRAGON only, but IPQ40XX > > devices also use the same UART HW so they can also use the debug UART. > > > > So, allow selecting DEBUG_UART_MSM when using ARCH_IPQ40XX as well. > > > > Signed-off-by: Robert Marko > > Reviewed-by: Caleb Connolly > > --- > > drivers/serial/Kconfig | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig > > index 8b19e2684e..1fe4607598 100644 > > --- a/drivers/serial/Kconfig > > +++ b/drivers/serial/Kconfig > > @@ -321,7 +321,7 @@ config DEBUG_UART_S5P > > > > config DEBUG_UART_MSM > > bool "Qualcomm QUP UART debug" > > - depends on ARCH_SNAPDRAGON > > + depends on ARCH_SNAPDRAGON || ARCH_IPQ40XX > > help > > Select this to enable a debug UART using the serial_msm driver. You > > will need to provide parameters to make this work. The driver will > > -- > // Caleb (they/them) -- Robert Marko Staff Embedded Linux Engineer Sartura Ltd. Lendavska ulica 16a 1 Zagreb, Croatia Email: robert.ma...@sartura.hr Web: www.sartura.hr
Re: [PATCH 3/3] serial: msm: calculate bit clock divider
On Mon, Apr 15, 2024 at 4:18 PM Caleb Connolly
wrote:
>
>
>
> On 15/04/2024 14:05, Robert Marko wrote:
> > On Mon, Apr 15, 2024 at 2:44 PM Caleb Connolly
> > wrote:
> >>
> >> The driver currently requires the bit clock divider be hardcoded in
> >> devicetree (or use the hardcoded default from apq8016).
> >>
> >> The bit clock divider is used to derive the baud rate from the core
> >> clock:
> >>
> >> baudrate = clk_rate / csr_div
> >>
> >> clk_rate is the actual programmed core clock rate which is returned by
> >> clk_set_rate(), and this UART driver only supports a baudrate of 115200.
> >> We can therefore determine the appropriate value for UARTDM_CSR by
> >> iterating over the possible values and finding the one where the
> >> equation above holds true for a baudrate of 115200.
> >>
> >> Implement this logic and drop the non-standard DT bindings for this
> >> driver.
> >>
> >> Tested on dragonboard410c.
> >>
> >> Signed-off-by: Caleb Connolly
> >
> > Works on Alfa AP120C (IPQ4018) with full DM UART, but debug UART
> > prints junk since .clk_rate = 7372800 is not correct for IPQ40xx.
> > I would suggest using .clk_rate = CONFIG_VAL(DEBUG_UART_CLOCK) instead
> > to populate the value per board, this also avoids per ARCH ifdefs.
>
> Ok awesome, thanks for trying this out. I'll send a v2 with your suggestion.
>
> Can I add your Tested-by?
Sure,
Tested-by: Robert Marko
Regards,
Robert
> >
> > Regards,
> > Robert
> >> ---
> >> Cc: Robert Marko
> >> ---
> >> doc/device-tree-bindings/serial/msm-serial.txt | 10 ---
> >> drivers/serial/serial_msm.c| 87
> >> +-
> >> 2 files changed, 70 insertions(+), 27 deletions(-)
> >>
> >> diff --git a/doc/device-tree-bindings/serial/msm-serial.txt
> >> b/doc/device-tree-bindings/serial/msm-serial.txt
> >> deleted file mode 100644
> >> index dca995798a90..
> >> --- a/doc/device-tree-bindings/serial/msm-serial.txt
> >> +++ /dev/null
> >> @@ -1,10 +0,0 @@
> >> -Qualcomm UART (Data Mover mode)
> >> -
> >> -Required properties:
> >> -- compatible: must be "qcom,msm-uartdm-v1.4"
> >> -- reg: start address and size of the registers
> >> -- clock: interface clock (must accept baudrate as a frequency)
> >> -
> >> -Optional properties:
> >> -- bit-rate: Data Mover bit rate register value
> >> - (If not defined then 0xCC is used as default)
> >> diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
> >> index 8044d38518db..e461929b4338 100644
> >> --- a/drivers/serial/serial_msm.c
> >> +++ b/drivers/serial/serial_msm.c
> >> @@ -31,8 +31,18 @@
> >> #define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing
> >> buffer */
> >> #define UARTDM_RXFS_BUF_MASK0x7
> >> #define UARTDM_MR1 0x00
> >> #define UARTDM_MR2 0x04
> >> +/*
> >> + * This is documented on page 1817 of the apq8016e technical reference
> >> manual.
> >> + * section 6.2.5.3.26
> >> + *
> >> + * The upper nybble contains the bit clock divider for the RX pin, the
> >> lower
> >> + * nybble defines the TX pin. In almost all cases these should be the
> >> same value.
> >> + *
> >> + * The baud rate is the core clock frequency divided by the fixed divider
> >> value
> >> + * programmed into this register (defined in calc_csr_bitrate()).
> >> + */
> >> #define UARTDM_CSR 0xA0
> >>
> >> #define UARTDM_SR0xA4 /* Status register */
> >> #define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */
> >> @@ -52,9 +62,8 @@
> >>
> >> #define UARTDM_TF 0x100 /* UART Transmit FIFO register */
> >> #define UARTDM_RF 0x140 /* UART Receive FIFO register */
> >>
> >> -#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
> >> #define MSM_BOOT_UART_DM_8_N_1_MODE 0x34
> >> #define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10
> >> #define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20
> >>
> >> @@ -63,9 +72,9 @@ DECLARE_GLOBAL_DATA_PTR;
> >> struct msm_serial_data {
> >> phys_addr_t base;
> >> unsigned chars_cn
Re: [PATCH 3/3] serial: msm: calculate bit clock divider
On Mon, Apr 15, 2024 at 2:44 PM Caleb Connolly
wrote:
>
> The driver currently requires the bit clock divider be hardcoded in
> devicetree (or use the hardcoded default from apq8016).
>
> The bit clock divider is used to derive the baud rate from the core
> clock:
>
> baudrate = clk_rate / csr_div
>
> clk_rate is the actual programmed core clock rate which is returned by
> clk_set_rate(), and this UART driver only supports a baudrate of 115200.
> We can therefore determine the appropriate value for UARTDM_CSR by
> iterating over the possible values and finding the one where the
> equation above holds true for a baudrate of 115200.
>
> Implement this logic and drop the non-standard DT bindings for this
> driver.
>
> Tested on dragonboard410c.
>
> Signed-off-by: Caleb Connolly
Works on Alfa AP120C (IPQ4018) with full DM UART, but debug UART
prints junk since .clk_rate = 7372800 is not correct for IPQ40xx.
I would suggest using .clk_rate = CONFIG_VAL(DEBUG_UART_CLOCK) instead
to populate the value per board, this also avoids per ARCH ifdefs.
Regards,
Robert
> ---
> Cc: Robert Marko
> ---
> doc/device-tree-bindings/serial/msm-serial.txt | 10 ---
> drivers/serial/serial_msm.c| 87
> +-
> 2 files changed, 70 insertions(+), 27 deletions(-)
>
> diff --git a/doc/device-tree-bindings/serial/msm-serial.txt
> b/doc/device-tree-bindings/serial/msm-serial.txt
> deleted file mode 100644
> index dca995798a90..
> --- a/doc/device-tree-bindings/serial/msm-serial.txt
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -Qualcomm UART (Data Mover mode)
> -
> -Required properties:
> -- compatible: must be "qcom,msm-uartdm-v1.4"
> -- reg: start address and size of the registers
> -- clock: interface clock (must accept baudrate as a frequency)
> -
> -Optional properties:
> -- bit-rate: Data Mover bit rate register value
> - (If not defined then 0xCC is used as default)
> diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
> index 8044d38518db..e461929b4338 100644
> --- a/drivers/serial/serial_msm.c
> +++ b/drivers/serial/serial_msm.c
> @@ -31,8 +31,18 @@
> #define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing
> buffer */
> #define UARTDM_RXFS_BUF_MASK0x7
> #define UARTDM_MR1 0x00
> #define UARTDM_MR2 0x04
> +/*
> + * This is documented on page 1817 of the apq8016e technical reference
> manual.
> + * section 6.2.5.3.26
> + *
> + * The upper nybble contains the bit clock divider for the RX pin, the lower
> + * nybble defines the TX pin. In almost all cases these should be the same
> value.
> + *
> + * The baud rate is the core clock frequency divided by the fixed divider
> value
> + * programmed into this register (defined in calc_csr_bitrate()).
> + */
> #define UARTDM_CSR 0xA0
>
> #define UARTDM_SR0xA4 /* Status register */
> #define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */
> @@ -52,9 +62,8 @@
>
> #define UARTDM_TF 0x100 /* UART Transmit FIFO register */
> #define UARTDM_RF 0x140 /* UART Receive FIFO register */
>
> -#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
> #define MSM_BOOT_UART_DM_8_N_1_MODE 0x34
> #define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10
> #define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20
>
> @@ -63,9 +72,9 @@ DECLARE_GLOBAL_DATA_PTR;
> struct msm_serial_data {
> phys_addr_t base;
> unsigned chars_cnt; /* number of buffered chars */
> uint32_t chars_buf; /* buffered chars */
> - uint32_t clk_bit_rate; /* data mover mode bit rate register value */
> + uint32_t clk_rate; /* core clock rate */
> };
>
> static int msm_serial_fetch(struct udevice *dev)
> {
> @@ -155,34 +164,63 @@ static const struct dm_serial_ops msm_serial_ops = {
> .pending = msm_serial_pending,
> .getc = msm_serial_getc,
> };
>
> -static int msm_uart_clk_init(struct udevice *dev)
> +static long msm_uart_clk_init(struct udevice *dev)
> {
> - uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
> - "clock-frequency", 115200);
> + struct msm_serial_data *priv = dev_get_priv(dev);
> struct clk clk;
> int ret;
> + long rate;
>
> ret = clk_get_by_name(dev, "core", );
> if (ret < 0) {
> pr_warn("%s: Failed to get clock: %d\n", __func__, ret);
> - return ret;
> + return 0;
> }
>
> -
[PATCH v2] usb: dwc3-generic: fix support without DM_REGULATOR
Recent addition of vbus-supply support has broke platform which dont use
controllable regulators for USB.
Issue is that even withou DM_REGULATOR being enabled regulator related
functions will still build as there is a stub in regulator.h but they will
simply return -ENOSYS which will then make dwc3_generic_host_probe()
return the same error thus breaking probe.
So, check whether return code is -ENOSYS before erroring out.
Fixes: de451d5d5b6f ("usb: dwc3-generic: support external vbus regulator")
Signed-off-by: Robert Marko
---
Changes in v2:
* Drop #ifdefs and check for -ENOSYS that regulator stub returns
drivers/usb/dwc3/dwc3-generic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 7a00529a2a..df0b0b8c02 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -248,7 +248,7 @@ static int dwc3_generic_host_probe(struct udevice *dev)
/* Only returns an error if regulator is valid and failed to enable due
to a driver issue */
rc = regulator_set_enable_if_allowed(priv->vbus_supply, true);
- if (rc)
+ if (rc && rc != -ENOSYS)
return rc;
hccr = (struct xhci_hccr *)priv->gen_priv.base;
--
2.44.0
Re: [PATCH 3/3] serial: msm_serial: set .clk_bit_rate in debug UART
On Mon, Apr 15, 2024 at 1:46 PM Caleb Connolly
wrote:
>
>
>
> On 15/04/2024 11:49, Robert Marko wrote:
> > Currently, .clk_bit_rate is not being set in init_serial_data for debug
> > UART, but its then used uart_dm_init() and this breaks debug UART on
> > IPQ40xx.
> >
> > So, lets populate .clk_bit_rate for debug UART as well.
> > IPQ40xx requires special value of 0xff, so set it if ARCH_IPQ40XX is
> > selected, otherwise default to the same value that regular DM UART
> > will use.
>
> Ah, I have a patch lying around to configure this automatically, but
> didn't get around to sending it. Could you give it a test on your IPQ
> board if I send it your way?
Sure, that would be great.
Regards,
Robert
>
> Kind regards,
> >
> > Signed-off-by: Robert Marko
> > ---
> > drivers/serial/serial_msm.c | 5 +
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
> > index 8044d38518..80069f5cfb 100644
> > --- a/drivers/serial/serial_msm.c
> > +++ b/drivers/serial/serial_msm.c
> > @@ -242,6 +242,11 @@ U_BOOT_DRIVER(serial_msm) = {
> >
> > static struct msm_serial_data init_serial_data = {
> > .base = CONFIG_VAL(DEBUG_UART_BASE),
> > +#ifdef CONFIG_ARCH_IPQ40XX
> > + .clk_bit_rate = 0xff,
> > +#else
> > + .clk_bit_rate = UART_DM_CLK_RX_TX_BIT_RATE,
> > +#endif
> > };
> >
> > #include
>
> --
> // Caleb (they/them)
--
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
1 Zagreb, Croatia
Email: robert.ma...@sartura.hr
Web: www.sartura.hr
Re: [PATCH] usb: dwc3-generic: fix support without DM_REGULATOR
On Mon, Apr 15, 2024 at 12:57 PM Caleb Connolly
wrote:
>
>
>
> On 15/04/2024 11:53, Robert Marko wrote:
> > Recent addition of vbus-supply support has broke platform which dont use
> > controllable regulators for USB.
> >
> > Issue is that even withou DM_REGULATOR being enabled regulator related
> > functions will still build as there is a stub in regulator.h but they will
> > simply return -ENOSYS which will then make dwc3_generic_host_probe()
> > return the same error thus breaking probe.
>
> Rather than stubbing out the code, could you check for -ENOSYS and
> ignore the error in that case? I believe there's only one place where
> this matters (marked below).
Sure, that was my first approach but it did not seem right to me.
But if its OK with you, I can do that.
Regards,
Robert
> >
> > Fixes: de451d5d5b6f ("usb: dwc3-generic: support external vbus regulator")
> > Signed-off-by: Robert Marko
> > ---
> > drivers/usb/dwc3/dwc3-generic.c | 8
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/usb/dwc3/dwc3-generic.c
> > b/drivers/usb/dwc3/dwc3-generic.c
> > index 7a00529a2a..784d3ec2ed 100644
> > --- a/drivers/usb/dwc3/dwc3-generic.c
> > +++ b/drivers/usb/dwc3/dwc3-generic.c
> > @@ -242,6 +242,7 @@ static int dwc3_generic_host_probe(struct udevice *dev)
> > if (rc)
> > return rc;
> >
> > +#if CONFIG_IS_ENABLED(DM_REGULATOR)
> > rc = device_get_supply_regulator(dev, "vbus-supply",
> > >vbus_supply);
> > if (rc)
> > debug("%s: No vbus regulator found: %d\n", dev->name, rc);
> > @@ -250,14 +251,17 @@ static int dwc3_generic_host_probe(struct udevice
> > *dev)
> > rc = regulator_set_enable_if_allowed(priv->vbus_supply, true);
> > if (rc)
> > return rc;
>
> Here, if (rc && rc != -ENOSYS)
> or even if (CONFIG_IS_ENABLED(DM_REGULATOR) && rc) to be verbose (maybe
> not the preferred style though).
>
> All the other regulator_* calls either ignore the result or only print a
> debug message.
> > +#endif
> >
> > hccr = (struct xhci_hccr *)priv->gen_priv.base;
> > hcor = (struct xhci_hcor *)(priv->gen_priv.base +
> > HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
> >
> > rc = xhci_register(dev, hccr, hcor);
> > +#if CONFIG_IS_ENABLED(DM_REGULATOR)
> > if (rc)
> > regulator_set_enable_if_allowed(priv->vbus_supply, false);
> > +#endif
> >
> > return rc;
> > }
> > @@ -265,14 +269,18 @@ static int dwc3_generic_host_probe(struct udevice
> > *dev)
> > static int dwc3_generic_host_remove(struct udevice *dev)
> > {
> > struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
> > +#if CONFIG_IS_ENABLED(DM_REGULATOR)
> > int rc;
> > +#endif
> >
> > /* This function always returns 0 */
> > xhci_deregister(dev);
> >
> > +#if CONFIG_IS_ENABLED(DM_REGULATOR)
> > rc = regulator_set_enable_if_allowed(priv->vbus_supply, false);
> > if (rc)
> > debug("%s: Failed to disable vbus regulator: %d\n",
> > dev->name, rc);
> > +#endif
> >
> > return dwc3_generic_remove(dev, >gen_priv);
> > }
>
> --
> // Caleb (they/them)
--
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
1 Zagreb, Croatia
Email: robert.ma...@sartura.hr
Web: www.sartura.hr
[PATCH] usb: dwc3-generic: fix support without DM_REGULATOR
Recent addition of vbus-supply support has broke platform which dont use
controllable regulators for USB.
Issue is that even withou DM_REGULATOR being enabled regulator related
functions will still build as there is a stub in regulator.h but they will
simply return -ENOSYS which will then make dwc3_generic_host_probe()
return the same error thus breaking probe.
Fixes: de451d5d5b6f ("usb: dwc3-generic: support external vbus regulator")
Signed-off-by: Robert Marko
---
drivers/usb/dwc3/dwc3-generic.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 7a00529a2a..784d3ec2ed 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -242,6 +242,7 @@ static int dwc3_generic_host_probe(struct udevice *dev)
if (rc)
return rc;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
rc = device_get_supply_regulator(dev, "vbus-supply",
>vbus_supply);
if (rc)
debug("%s: No vbus regulator found: %d\n", dev->name, rc);
@@ -250,14 +251,17 @@ static int dwc3_generic_host_probe(struct udevice *dev)
rc = regulator_set_enable_if_allowed(priv->vbus_supply, true);
if (rc)
return rc;
+#endif
hccr = (struct xhci_hccr *)priv->gen_priv.base;
hcor = (struct xhci_hcor *)(priv->gen_priv.base +
HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
rc = xhci_register(dev, hccr, hcor);
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (rc)
regulator_set_enable_if_allowed(priv->vbus_supply, false);
+#endif
return rc;
}
@@ -265,14 +269,18 @@ static int dwc3_generic_host_probe(struct udevice *dev)
static int dwc3_generic_host_remove(struct udevice *dev)
{
struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
int rc;
+#endif
/* This function always returns 0 */
xhci_deregister(dev);
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
rc = regulator_set_enable_if_allowed(priv->vbus_supply, false);
if (rc)
debug("%s: Failed to disable vbus regulator: %d\n", dev->name,
rc);
+#endif
return dwc3_generic_remove(dev, >gen_priv);
}
--
2.44.0
[PATCH 3/3] serial: msm_serial: set .clk_bit_rate in debug UART
Currently, .clk_bit_rate is not being set in init_serial_data for debug
UART, but its then used uart_dm_init() and this breaks debug UART on
IPQ40xx.
So, lets populate .clk_bit_rate for debug UART as well.
IPQ40xx requires special value of 0xff, so set it if ARCH_IPQ40XX is
selected, otherwise default to the same value that regular DM UART
will use.
Signed-off-by: Robert Marko
---
drivers/serial/serial_msm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index 8044d38518..80069f5cfb 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -242,6 +242,11 @@ U_BOOT_DRIVER(serial_msm) = {
static struct msm_serial_data init_serial_data = {
.base = CONFIG_VAL(DEBUG_UART_BASE),
+#ifdef CONFIG_ARCH_IPQ40XX
+ .clk_bit_rate = 0xff,
+#else
+ .clk_bit_rate = UART_DM_CLK_RX_TX_BIT_RATE,
+#endif
};
#include
--
2.44.0
[PATCH 2/3] serial: msm_serial: remove .clk_rate from debug UART
MSM serial in DEBUG UART mode is trying to set .clk_rate, but the
msm_serial_data structure does not have such property at all, so lets
remove it as otherwise it will fail compiling.
Fixes: 90023bdfe979 ("serial: msm: add debug UART")
Signed-off-by: Robert Marko
---
drivers/serial/serial_msm.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index ac4280c6c4..8044d38518 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -242,7 +242,6 @@ U_BOOT_DRIVER(serial_msm) = {
static struct msm_serial_data init_serial_data = {
.base = CONFIG_VAL(DEBUG_UART_BASE),
- .clk_rate = 7372800,
};
#include
--
2.44.0
[PATCH 1/3] serial: allow selecting MSM debug UART with ARCH_IPQ40XX
Currently, DEBUG_UART_MSM depends on ARCH_SNAPDRAGON only, but IPQ40XX devices also use the same UART HW so they can also use the debug UART. So, allow selecting DEBUG_UART_MSM when using ARCH_IPQ40XX as well. Signed-off-by: Robert Marko --- drivers/serial/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 8b19e2684e..1fe4607598 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -321,7 +321,7 @@ config DEBUG_UART_S5P config DEBUG_UART_MSM bool "Qualcomm QUP UART debug" - depends on ARCH_SNAPDRAGON + depends on ARCH_SNAPDRAGON || ARCH_IPQ40XX help Select this to enable a debug UART using the serial_msm driver. You will need to provide parameters to make this work. The driver will -- 2.44.0
Re: [PATCH 1/4] board: beagle: beagleplay: Enable 32k crystal
On Mon, Feb 12, 2024 at 9:53 AM Nishanth Menon wrote: > > Enable the external 32k crystal similar to that found on other > production AM62X board. The trim settings for the crystal is board > dependent, so the sequences tend to be board specific. Since this is > a configuration that needs to be done prior to DM managing the system > and all other muxes get set, do the same from R5 context. > > Signed-off-by: Nishanth Menon Tested-by: Robert Nelson Yay, WiFi (wl18xx) now works on the BeaglePay with these 4 patches on top of v2024.01-rc1 debian@BeaglePlay-57:~$ dmesg | grep wl [1.892839] wlan_en: supplied by vdd_3v3 [8.437425] systemd[1]: Expecting device sys-subsystem-net-devices-wlan0.device - /sys/subsystem/net/devices/wlan0... [ 13.241739] wlcore: wl18xx HW: 183x or 180x, PG 2.2 (ROM 0x11) [ 13.246116] wlcore: WARNING Detected unconfigured mac address in nvs, derive from fuse instead. [ 13.246155] wlcore: WARNING This default nvs file can be removed from the file system [ 13.253088] wlcore: loaded [ 13.788451] wlcore: using inverted interrupt logic: 2 [ 13.842464] wlcore: PHY firmware version: Rev 8.2.0.0.243 [ 13.938371] wlcore: firmware booted (Rev 8.9.0.0.83) Regards, -- Robert Nelson https://rcn-ee.com/
Re: [PATCH v3 1/3] arm: mvebu: Espressobin: move FDT fixup into a separate function
On Tue, Jan 9, 2024 at 4:34 PM Stefan Roese wrote:
>
> Hi Robert,
>
> On 1/9/24 14:16, Robert Marko wrote:
> > On Wed, Nov 29, 2023 at 11:11 AM Robert Marko
> > wrote:
> >>
> >> Currently, Esspresobin FDT is being fixed up directly in ft_board_setup()
> >> which makes it hard to add support for any other board to be fixed up.
> >>
> >> So, lets just move the FDT fixup code to a separate function and call it
> >> if compatible matches, there should be no functional change.
> >>
> >> Signed-off-by: Robert Marko
> >> Reviewed-by: Stefan Roese
> >
> >
> > Hi Stefan,
> > Since 2024.01 was released, can this series be pulled in now?
>
> It's on my list. I actually already started with some CI build tests.
> Hope to get this done by end of this week, before I leave for a
> short vacation.
Sounds good.
Regards,
Robert
>
> Thanks,
> Stefan
>
> > Regards,
> > Robert
> >
> >>
> >> ---
> >> board/Marvell/mvebu_armada-37xx/board.c | 14 +-
> >> 1 file changed, 9 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/board/Marvell/mvebu_armada-37xx/board.c
> >> b/board/Marvell/mvebu_armada-37xx/board.c
> >> index 04124d8014..1471caa9a6 100644
> >> --- a/board/Marvell/mvebu_armada-37xx/board.c
> >> +++ b/board/Marvell/mvebu_armada-37xx/board.c
> >> @@ -363,18 +363,14 @@ EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT,
> >> last_stage_init);
> >> #endif
> >>
> >> #ifdef CONFIG_OF_BOARD_SETUP
> >> -int ft_board_setup(void *blob, struct bd_info *bd)
> >> +static int espressobin_fdt_setup(void *blob)
> >> {
> >> -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
> >> int ret;
> >> int spi_off;
> >> int parts_off;
> >> int part_off;
> >>
> >> /* Fill SPI MTD partitions for Linux kernel on Espressobin */
> >> - if (!of_machine_is_compatible("globalscale,espressobin"))
> >> - return 0;
> >> -
> >> spi_off = fdt_node_offset_by_compatible(blob, -1,
> >> "jedec,spi-nor");
> >> if (spi_off < 0)
> >> return 0;
> >> @@ -459,6 +455,14 @@ int ft_board_setup(void *blob, struct bd_info *bd)
> >> return 0;
> >> }
> >>
> >> + return 0;
> >> +}
> >> +
> >> +int ft_board_setup(void *blob, struct bd_info *bd)
> >> +{
> >> +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
> >> + if (of_machine_is_compatible("globalscale,espressobin"))
> >> + return espressobin_fdt_setup(blob);
> >> #endif
> >> return 0;
> >> }
> >> --
> >> 2.43.0
> >>
> >
> >
>
> Viele Grüße,
> Stefan Roese
>
> --
> DENX Software Engineering GmbH, Managing Director: Erika Unter
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
--
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
1 Zagreb, Croatia
Email: robert.ma...@sartura.hr
Web: www.sartura.hr
Re: [PATCH v3 1/3] arm: mvebu: Espressobin: move FDT fixup into a separate function
On Wed, Nov 29, 2023 at 11:11 AM Robert Marko wrote:
>
> Currently, Esspresobin FDT is being fixed up directly in ft_board_setup()
> which makes it hard to add support for any other board to be fixed up.
>
> So, lets just move the FDT fixup code to a separate function and call it
> if compatible matches, there should be no functional change.
>
> Signed-off-by: Robert Marko
> Reviewed-by: Stefan Roese
Hi Stefan,
Since 2024.01 was released, can this series be pulled in now?
Regards,
Robert
>
> ---
> board/Marvell/mvebu_armada-37xx/board.c | 14 +-
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/board/Marvell/mvebu_armada-37xx/board.c
> b/board/Marvell/mvebu_armada-37xx/board.c
> index 04124d8014..1471caa9a6 100644
> --- a/board/Marvell/mvebu_armada-37xx/board.c
> +++ b/board/Marvell/mvebu_armada-37xx/board.c
> @@ -363,18 +363,14 @@ EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
> #endif
>
> #ifdef CONFIG_OF_BOARD_SETUP
> -int ft_board_setup(void *blob, struct bd_info *bd)
> +static int espressobin_fdt_setup(void *blob)
> {
> -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
> int ret;
> int spi_off;
> int parts_off;
> int part_off;
>
> /* Fill SPI MTD partitions for Linux kernel on Espressobin */
> - if (!of_machine_is_compatible("globalscale,espressobin"))
> - return 0;
> -
> spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
> if (spi_off < 0)
> return 0;
> @@ -459,6 +455,14 @@ int ft_board_setup(void *blob, struct bd_info *bd)
> return 0;
> }
>
> + return 0;
> +}
> +
> +int ft_board_setup(void *blob, struct bd_info *bd)
> +{
> +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
> + if (of_machine_is_compatible("globalscale,espressobin"))
> + return espressobin_fdt_setup(blob);
> #endif
> return 0;
> }
> --
> 2.43.0
>
--
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
1 Zagreb, Croatia
Email: robert.ma...@sartura.hr
Web: www.sartura.hr
[PATCH v3 3/3] arm: mvebu: eDPU: support new board revision
There is a new eDPU revision that uses Marvell 88E6361 switch onboard.
We can rely on detecting the switch to enable and fixup the Linux DTS
so a single DTS can be used.
There is currently no support for the 88E6361 switch and thus no working
networking in U-Boot, so we disable both ports.
Signed-off-by: Robert Marko
Reviewed-by: Stefan Roese
---
Changes in v3:
* Add check for DM_MDIO
arch/arm/dts/armada-3720-eDPU-u-boot.dtsi | 13 ++-
arch/arm/dts/armada-3720-eDPU.dts | 47
board/Marvell/mvebu_armada-37xx/board.c | 128 ++
configs/eDPU_defconfig| 1 +
4 files changed, 184 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi
b/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi
index cb02b70e54..c3d450dd83 100644
--- a/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi
+++ b/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi
@@ -32,14 +32,17 @@
bootph-all;
};
- {
- /* G.hn does not work without additional configuration */
- status = "disabled";
-};
-
{
fixed-link {
speed = <1000>;
full-duplex;
};
};
+
+/*
+ * eDPU v2 has a MV88E6361 switch on the MDIO bus and U-boot is used
+ * to patch the Linux DTS if its found so enable MDIO by default.
+ */
+ {
+ status = "okay";
+};
diff --git a/arch/arm/dts/armada-3720-eDPU.dts
b/arch/arm/dts/armada-3720-eDPU.dts
index 57fc698e55..d6d37a1f6f 100644
--- a/arch/arm/dts/armada-3720-eDPU.dts
+++ b/arch/arm/dts/armada-3720-eDPU.dts
@@ -12,3 +12,50 @@
{
phy-mode = "2500base-x";
};
+
+/*
+ * External MV88E6361 switch is only available on v2 of the board.
+ * U-Boot will enable the MDIO bus and switch nodes.
+ */
+ {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+
+ /* Actual device is MV88E6361 */
+ switch: switch@0 {
+ compatible = "marvell,mv88e6190";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "cpu";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ ethernet = <>;
+ };
+
+ port@9 {
+ reg = <9>;
+ label = "downlink";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ };
+
+ port@a {
+ reg = <10>;
+ label = "uplink";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ sfp = <_eth1>;
+ };
+ };
+ };
+};
diff --git a/board/Marvell/mvebu_armada-37xx/board.c
b/board/Marvell/mvebu_armada-37xx/board.c
index f532486b70..1685b12b84 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -50,6 +51,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* Single-chip mode */
/* Switch Port Registers */
#define MVEBU_SW_LINK_CTRL_REG (1)
+#define MVEBU_SW_PORT_SWITCH_ID(3)
#define MVEBU_SW_PORT_CTRL_REG (4)
#define MVEBU_SW_PORT_BASE_VLAN(6)
@@ -57,6 +59,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define MVEBU_G2_SMI_PHY_CMD_REG (24)
#define MVEBU_G2_SMI_PHY_DATA_REG (25)
+#define SWITCH_88E6361_PRODUCT_NUMBER 0x2610
+
/*
* Memory Controller Registers
*
@@ -73,6 +77,30 @@ DECLARE_GLOBAL_DATA_PTR;
#define A3700_MC_CTRL2_SDRAM_TYPE_DDR3 2
#define A3700_MC_CTRL2_SDRAM_TYPE_DDR4 3
+static bool is_edpu_plus(void)
+{
+ struct udevice *bus;
+ ofnode node;
+ int val;
+
+ if (!CONFIG_IS_ENABLED(DM_MDIO))
+ return false;
+
+ node = ofnode_by_compatible(ofnode_null(), "marvell,orion-mdio");
+ if (!ofnode_valid(node) ||
+ uclass_get_device_by_ofnode(UCLASS_MDIO, node, ) ||
+ device_probe(bus)) {
+ printf("Cannot find MDIO bus\n");
+ return -ENODEV;
+ }
+
+ val = dm_mdio_read(bus, 0x0, MDIO_DEVAD_NONE, MVEBU_SW_PORT_SWITCH_ID);
+ if (val == SWITCH_88E6361_PRODUCT_NUMBER)
+
[PATCH v3 2/3] arm: mvebu: Espressobin: move network setup into a separate function
Currently, Esspresobin switch is being setup directly in last_stage_init()
which makes it hard to add support for any other board to be setup.
So, lets just move the switch setup code to a separate function and call it
if compatible matches, there should be no functional change.
Signed-off-by: Robert Marko
Reviewed-by: Stefan Roese
---
Changes in v2:
* Rebase on top of current master and resolve conflicts
board/Marvell/mvebu_armada-37xx/board.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/board/Marvell/mvebu_armada-37xx/board.c
b/board/Marvell/mvebu_armada-37xx/board.c
index 1471caa9a6..f532486b70 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -301,14 +301,12 @@ static int mii_multi_chip_mode_write(struct udevice *bus,
int dev_smi_addr,
return 0;
}
-/* Bring-up board-specific network stuff */
-static int last_stage_init(void)
+static int espressobin_last_stage_init(void)
{
struct udevice *bus;
ofnode node;
- if (!CONFIG_IS_ENABLED(DM_MDIO) ||
- !of_machine_is_compatible("globalscale,espressobin"))
+ if (!CONFIG_IS_ENABLED(DM_MDIO))
return 0;
node = ofnode_by_compatible(ofnode_null(), "marvell,orion-mdio");
@@ -358,8 +356,17 @@ static int last_stage_init(void)
return 0;
}
-EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
+/* Bring-up board-specific network stuff */
+static int last_stage_init(void)
+{
+
+ if (of_machine_is_compatible("globalscale,espressobin"))
+ return espressobin_last_stage_init();
+
+ return 0;
+}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
#endif
#ifdef CONFIG_OF_BOARD_SETUP
--
2.43.0
[PATCH v3 1/3] arm: mvebu: Espressobin: move FDT fixup into a separate function
Currently, Esspresobin FDT is being fixed up directly in ft_board_setup()
which makes it hard to add support for any other board to be fixed up.
So, lets just move the FDT fixup code to a separate function and call it
if compatible matches, there should be no functional change.
Signed-off-by: Robert Marko
Reviewed-by: Stefan Roese
---
board/Marvell/mvebu_armada-37xx/board.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/board/Marvell/mvebu_armada-37xx/board.c
b/board/Marvell/mvebu_armada-37xx/board.c
index 04124d8014..1471caa9a6 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -363,18 +363,14 @@ EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
#endif
#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, struct bd_info *bd)
+static int espressobin_fdt_setup(void *blob)
{
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
int ret;
int spi_off;
int parts_off;
int part_off;
/* Fill SPI MTD partitions for Linux kernel on Espressobin */
- if (!of_machine_is_compatible("globalscale,espressobin"))
- return 0;
-
spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
if (spi_off < 0)
return 0;
@@ -459,6 +455,14 @@ int ft_board_setup(void *blob, struct bd_info *bd)
return 0;
}
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+ if (of_machine_is_compatible("globalscale,espressobin"))
+ return espressobin_fdt_setup(blob);
#endif
return 0;
}
--
2.43.0
Re: [PATCH v2 1/3] arm: mvebu: Espressobin: move FDT fixup into a separate function
On Tue, Nov 28, 2023 at 4:49 PM Stefan Roese wrote:
>
> Hi Robert,
>
> On 11/28/23 16:44, Stefan Roese wrote:
> > Hi Robert,
> >
> > On 11/28/23 11:19, Robert Marko wrote:
> >> On Fri, Oct 20, 2023 at 12:21 PM Robert Marko
> >> wrote:
> >>>
> >>> Currently, Esspresobin FDT is being fixed up directly in
> >>> ft_board_setup()
> >>> which makes it hard to add support for any other board to be fixed up.
> >>>
> >>> So, lets just move the FDT fixup code to a separate function and call it
> >>> if compatible matches, there should be no functional change.
> >>>
> >>> Signed-off-by: Robert Marko
> >>> Reviewed-by: Stefan Roese
> >>
> >> Hi Stefan,
> >>
> >> Is there anything I can do to get this series merged?
> >
> > I just looked at it (again). My recollection was that something was
> > missing here - so I was waiting for a new version. Does not seem to
> > be the case though. So I guess I forgot to pull it (sorry for that)
> > and now with rc3 out it seems a bit too late in the release cycle.
> > I hope you don't mind that it's postponed to the next merge window.
>
> Seems my memory is not that bad after all. A world CI build fails with
> these 3 commits. Could you please have a look?
>
> Completed: 84 total built, 84 newly), duration 1:01:11, rate 0.02
> + ret=100
> + [[ 100 -ne 0 ]]
> + tools/buildman/buildman -o /tmp -seP am33xx at91_kirkwood mvebu omap
> -x siemens
> Summary of current source for 84 boards (2 threads, 1 job per thread)
> aarch64: w+ x240 turris_mox mvebu_ac5_rd eDPU
> mvebu_espressobin-88f3720 uDPU clearfog_gt_8k mvebu_db_armada8k
> mvebu_mcbin-88f8040 mvebu_puzzle-m801-88f8040 mvebu_crb_cn9130
> mvebu_db_cn9130 + mvebu_db-88f3720
> arm: w+ am335x_shc am335x_shc_ict am335x_shc_netboot
> am335x_shc_sdboot brsmarc1 cm_t43 chiliboard am335x_igep003x am335x_sl50
> am43xx_evm_qspiboot am43xx_hs_evm_qspi controlcenterdc db-88f6720
> db-88f6820-gp igep00x0 sniper omap3_beagle omap4_panda omap4_sdp4430
> +aarch64-linux-ld.bfd: board/Marvell/mvebu_armada-37xx/board.o: in
> function `is_edpu_plus':
> +board/Marvell/mvebu_armada-37xx/board.c:94:(.text.last_stage_init+0xb4):
> undefined reference to `dm_mdio_read'
> +make[1]: *** [Makefile:1765: u-boot] Error 139
> +make[1]: *** Deleting file 'u-boot'
> +make: *** [Makefile:177: sub-make] Error 2
Ok, seems like CI doesn't have DM MDIO enabled.
Will fixup today.
I am fine with pulling the fixed patchset after the stable release.
Regards,
Robert
>
>
> Thanks,
> Stefan
>
>
> > Thanks,
> > Stefan
> >
> >> Regards,
> >> Robert
> >>
> >>> ---
> >>> board/Marvell/mvebu_armada-37xx/board.c | 14 +-
> >>> 1 file changed, 9 insertions(+), 5 deletions(-)
> >>>
> >>> diff --git a/board/Marvell/mvebu_armada-37xx/board.c
> >>> b/board/Marvell/mvebu_armada-37xx/board.c
> >>> index 04124d8014..1471caa9a6 100644
> >>> --- a/board/Marvell/mvebu_armada-37xx/board.c
> >>> +++ b/board/Marvell/mvebu_armada-37xx/board.c
> >>> @@ -363,18 +363,14 @@ EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT,
> >>> last_stage_init);
> >>> #endif
> >>>
> >>> #ifdef CONFIG_OF_BOARD_SETUP
> >>> -int ft_board_setup(void *blob, struct bd_info *bd)
> >>> +static int espressobin_fdt_setup(void *blob)
> >>> {
> >>> -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
> >>> int ret;
> >>> int spi_off;
> >>> int parts_off;
> >>> int part_off;
> >>>
> >>> /* Fill SPI MTD partitions for Linux kernel on Espressobin */
> >>> - if (!of_machine_is_compatible("globalscale,espressobin"))
> >>> - return 0;
> >>> -
> >>> spi_off = fdt_node_offset_by_compatible(blob, -1,
> >>> "jedec,spi-nor");
> >>> if (spi_off < 0)
> >>> return 0;
> >>> @@ -459,6 +455,14 @@ int ft_board_setup(void *blob, struct bd_info *bd)
> >>> return 0;
> >>> }
> >>>
> >>> + return 0;
> >>> +}
> >>> +
> >>> +int ft_board_setup(void *blob, struct bd_info *bd)
> >>> +{
> >>> +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
> >>> + if (of_machine_is_compatible("globalscale,espressobin"))
> >>> + return espressobin_fdt_setup(blob);
> >>> #endif
> >>> return 0;
> >>> }
> >>> --
> >>> 2.41.0
> >>>
> >>
> >>
> >
> > Viele Grüße,
> > Stefan Roese
> >
>
> Viele Grüße,
> Stefan Roese
>
> --
> DENX Software Engineering GmbH, Managing Director: Erika Unter
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
--
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
1 Zagreb, Croatia
Email: robert.ma...@sartura.hr
Web: www.sartura.hr
Re: [PATCH v2 1/3] arm: mvebu: Espressobin: move FDT fixup into a separate function
On Fri, Oct 20, 2023 at 12:21 PM Robert Marko wrote:
>
> Currently, Esspresobin FDT is being fixed up directly in ft_board_setup()
> which makes it hard to add support for any other board to be fixed up.
>
> So, lets just move the FDT fixup code to a separate function and call it
> if compatible matches, there should be no functional change.
>
> Signed-off-by: Robert Marko
> Reviewed-by: Stefan Roese
Hi Stefan,
Is there anything I can do to get this series merged?
Regards,
Robert
> ---
> board/Marvell/mvebu_armada-37xx/board.c | 14 +-
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/board/Marvell/mvebu_armada-37xx/board.c
> b/board/Marvell/mvebu_armada-37xx/board.c
> index 04124d8014..1471caa9a6 100644
> --- a/board/Marvell/mvebu_armada-37xx/board.c
> +++ b/board/Marvell/mvebu_armada-37xx/board.c
> @@ -363,18 +363,14 @@ EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
> #endif
>
> #ifdef CONFIG_OF_BOARD_SETUP
> -int ft_board_setup(void *blob, struct bd_info *bd)
> +static int espressobin_fdt_setup(void *blob)
> {
> -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
> int ret;
> int spi_off;
> int parts_off;
> int part_off;
>
> /* Fill SPI MTD partitions for Linux kernel on Espressobin */
> - if (!of_machine_is_compatible("globalscale,espressobin"))
> - return 0;
> -
> spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
> if (spi_off < 0)
> return 0;
> @@ -459,6 +455,14 @@ int ft_board_setup(void *blob, struct bd_info *bd)
> return 0;
> }
>
> + return 0;
> +}
> +
> +int ft_board_setup(void *blob, struct bd_info *bd)
> +{
> +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
> + if (of_machine_is_compatible("globalscale,espressobin"))
> + return espressobin_fdt_setup(blob);
> #endif
> return 0;
> }
> --
> 2.41.0
>
--
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
1 Zagreb, Croatia
Email: robert.ma...@sartura.hr
Web: www.sartura.hr
[PATCH] arm: vexpress64: juno: Allow boot from VirtIO
From: Robert Catherall The AEM and Juno FVPs (Fixed Virtual Platforms) support a VirtIO disc interface. Adding VIRTIO to the list of boot devices allows these FastModel platforms to boot from 'disc' in the same way the hardware counterpart can boot from SATA or USB. This is a NOP if CONFIG_CMD_VIRTIO is not enabled, so no impact on Juno hardware (which is built with vexpress_aemv8a_juno_defconfig) Signed-off-by: Robert Catherall --- include/configs/vexpress_aemv8.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 24d8ca0866..8020689e39 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -187,6 +187,7 @@ func(USB, usb, 0) \ func(SATA, sata, 0) \ func(SATA, sata, 1) \ + FUNC_VIRTIO(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na)\ func(AFS, afs, na) -- 2.17.1
Re: [PATCH] arm: afs: Set the filesize env. var. on load
On 23/11/2023 17:15, robert.cather...@foss.arm.com wrote: From: Robert Catherall The `afs load` command copies data to RAM. Set the filesize environment variable to record how much data was 'loaded' Signed-off-by: Robert Catherall Apologies for the duplicate patch; I had issues with getting mail server set up correctly. Please disregard this copy and refer instead to the earlier message with the slightly different subject [PATCH 1/1] arm: afs: Set the filesize env. var. on load (the actual code is identical) Kind regards Robert
[PATCH] arm: afs: Set the filesize env. var. on load
From: Robert Catherall
The `afs load` command copies data to RAM. Set the filesize
environment variable to record how much data was 'loaded'
Signed-off-by: Robert Catherall
---
cmd/armflash.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/cmd/armflash.c b/cmd/armflash.c
index d1466f73aa..fdaea5ad81 100644
--- a/cmd/armflash.c
+++ b/cmd/armflash.c
@@ -180,6 +180,7 @@ static int load_image(const char * const name, const ulong
address)
{
struct afs_image *afi = NULL;
int i;
+ loff_t len_read = 0;
parse_flash();
for (i = 0; i < num_afs_images; i++) {
@@ -197,6 +198,7 @@ static int load_image(const char * const name, const ulong
address)
for (i = 0; i < afi->region_count; i++) {
ulong from, to;
+ u32 size;
from = afi->flash_mem_start + afi->regions[i].offset;
if (address) {
@@ -208,14 +210,20 @@ static int load_image(const char * const name, const
ulong address)
return CMD_RET_FAILURE;
}
- memcpy((void *)to, (void *)from, afi->regions[i].size);
+ size = afi->regions[i].size;
+ memcpy((void *)to, (void *)from, size);
printf("loaded region %d from %08lX to %08lX, %08X bytes\n",
i,
from,
to,
- afi->regions[i].size);
+ size);
+
+ len_read += size;
}
+
+ env_set_hex("filesize", len_read);
+
return CMD_RET_SUCCESS;
}
--
2.17.1
[PATCH 1/1] arm: afs: Set the filesize env. var. on load
The `afs load` command copies data to RAM. Set the filesize
environment variable to record how much data was 'loaded'
Signed-off-by: Robert Catherall
---
cmd/armflash.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/cmd/armflash.c b/cmd/armflash.c
index d1466f73aa..fdaea5ad81 100644
--- a/cmd/armflash.c
+++ b/cmd/armflash.c
@@ -180,6 +180,7 @@ static int load_image(const char * const name, const ulong
address)
{
struct afs_image *afi = NULL;
int i;
+ loff_t len_read = 0;
parse_flash();
for (i = 0; i < num_afs_images; i++) {
@@ -197,6 +198,7 @@ static int load_image(const char * const name, const ulong
address)
for (i = 0; i < afi->region_count; i++) {
ulong from, to;
+ u32 size;
from = afi->flash_mem_start + afi->regions[i].offset;
if (address) {
@@ -208,14 +210,20 @@ static int load_image(const char * const name, const
ulong address)
return CMD_RET_FAILURE;
}
- memcpy((void *)to, (void *)from, afi->regions[i].size);
+ size = afi->regions[i].size;
+ memcpy((void *)to, (void *)from, size);
printf("loaded region %d from %08lX to %08lX, %08X bytes\n",
i,
from,
to,
- afi->regions[i].size);
+ size);
+
+ len_read += size;
}
+
+ env_set_hex("filesize", len_read);
+
return CMD_RET_SUCCESS;
}
--
2.17.1
Re: [PATCH 2/3] arm: mvebu: Espressobin: move network setup into a separate function
On Fri, Oct 20, 2023 at 8:46 AM Stefan Roese wrote:
>
> Hi Robert,
>
> On 9/18/23 08:47, Stefan Roese wrote:
> > On 9/14/23 12:16, Robert Marko wrote:
> >> Currently, Esspresobin switch is being setup directly in
> >> last_stage_init()
> >> which makes it hard to add support for any other board to be setup.
> >>
> >> So, lets just move the switch setup code to a separate function and
> >> call it
> >> if compatible matches, there should be no functional change.
> >>
> >> Signed-off-by: Robert Marko
> >
> > Reviewed-by: Stefan Roese
>
> This patch and the next one do not apply on latest master. Could you
> please re-spin the patch series?
Done.
Regards,
Robert
>
> Thanks,
> Stefan
>
> > Thanks,
> > Stefan
> >
> >> ---
> >> board/Marvell/mvebu_armada-37xx/board.c | 16 +++-
> >> 1 file changed, 11 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/board/Marvell/mvebu_armada-37xx/board.c
> >> b/board/Marvell/mvebu_armada-37xx/board.c
> >> index da325e8c75..6527155c6e 100644
> >> --- a/board/Marvell/mvebu_armada-37xx/board.c
> >> +++ b/board/Marvell/mvebu_armada-37xx/board.c
> >> @@ -300,15 +300,11 @@ static int mii_multi_chip_mode_write(struct
> >> udevice *bus, int dev_smi_addr,
> >> return 0;
> >> }
> >> -/* Bring-up board-specific network stuff */
> >> -int last_stage_init(void)
> >> +static int espressobin_last_stage_init(void)
> >> {
> >> struct udevice *bus;
> >> ofnode node;
> >> -if (!of_machine_is_compatible("globalscale,espressobin"))
> >> -return 0;
> >> -
> >> node = ofnode_by_compatible(ofnode_null(), "marvell,orion-mdio");
> >> if (!ofnode_valid(node) ||
> >> uclass_get_device_by_ofnode(UCLASS_MDIO, node, ) ||
> >> @@ -356,6 +352,16 @@ int last_stage_init(void)
> >> return 0;
> >> }
> >> +
> >> +/* Bring-up board-specific network stuff */
> >> +int last_stage_init(void)
> >> +{
> >> +
> >> +if (of_machine_is_compatible("globalscale,espressobin"))
> >> +return espressobin_last_stage_init();
> >> +
> >> +return 0;
> >> +}
> >> #endif
> >> #ifdef CONFIG_OF_BOARD_SETUP
> >
> > Viele Grüße,
> > Stefan Roese
> >
>
> Viele Grüße,
> Stefan Roese
>
> --
> DENX Software Engineering GmbH, Managing Director: Erika Unter
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
--
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
1 Zagreb, Croatia
Email: robert.ma...@sartura.hr
Web: www.sartura.hr
[PATCH v2 3/3] arm: mvebu: eDPU: support new board revision
There is a new eDPU revision that uses Marvell 88E6361 switch onboard.
We can rely on detecting the switch to enable and fixup the Linux DTS
so a single DTS can be used.
There is currently no support for the 88E6361 switch and thus no working
networking in U-Boot, so we disable both ports.
Signed-off-by: Robert Marko
Reviewed-by: Stefan Roese
---
arch/arm/dts/armada-3720-eDPU-u-boot.dtsi | 13 ++-
arch/arm/dts/armada-3720-eDPU.dts | 47
board/Marvell/mvebu_armada-37xx/board.c | 125 ++
configs/eDPU_defconfig| 1 +
4 files changed, 181 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi
b/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi
index cb02b70e54..c3d450dd83 100644
--- a/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi
+++ b/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi
@@ -32,14 +32,17 @@
bootph-all;
};
- {
- /* G.hn does not work without additional configuration */
- status = "disabled";
-};
-
{
fixed-link {
speed = <1000>;
full-duplex;
};
};
+
+/*
+ * eDPU v2 has a MV88E6361 switch on the MDIO bus and U-boot is used
+ * to patch the Linux DTS if its found so enable MDIO by default.
+ */
+ {
+ status = "okay";
+};
diff --git a/arch/arm/dts/armada-3720-eDPU.dts
b/arch/arm/dts/armada-3720-eDPU.dts
index 57fc698e55..d6d37a1f6f 100644
--- a/arch/arm/dts/armada-3720-eDPU.dts
+++ b/arch/arm/dts/armada-3720-eDPU.dts
@@ -12,3 +12,50 @@
{
phy-mode = "2500base-x";
};
+
+/*
+ * External MV88E6361 switch is only available on v2 of the board.
+ * U-Boot will enable the MDIO bus and switch nodes.
+ */
+ {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+
+ /* Actual device is MV88E6361 */
+ switch: switch@0 {
+ compatible = "marvell,mv88e6190";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "cpu";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ ethernet = <>;
+ };
+
+ port@9 {
+ reg = <9>;
+ label = "downlink";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ };
+
+ port@a {
+ reg = <10>;
+ label = "uplink";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ sfp = <_eth1>;
+ };
+ };
+ };
+};
diff --git a/board/Marvell/mvebu_armada-37xx/board.c
b/board/Marvell/mvebu_armada-37xx/board.c
index f532486b70..aeddff7468 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -50,6 +51,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* Single-chip mode */
/* Switch Port Registers */
#define MVEBU_SW_LINK_CTRL_REG (1)
+#define MVEBU_SW_PORT_SWITCH_ID(3)
#define MVEBU_SW_PORT_CTRL_REG (4)
#define MVEBU_SW_PORT_BASE_VLAN(6)
@@ -57,6 +59,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define MVEBU_G2_SMI_PHY_CMD_REG (24)
#define MVEBU_G2_SMI_PHY_DATA_REG (25)
+#define SWITCH_88E6361_PRODUCT_NUMBER 0x2610
+
/*
* Memory Controller Registers
*
@@ -73,6 +77,27 @@ DECLARE_GLOBAL_DATA_PTR;
#define A3700_MC_CTRL2_SDRAM_TYPE_DDR3 2
#define A3700_MC_CTRL2_SDRAM_TYPE_DDR4 3
+static bool is_edpu_plus(void)
+{
+ struct udevice *bus;
+ ofnode node;
+ int val;
+
+ node = ofnode_by_compatible(ofnode_null(), "marvell,orion-mdio");
+ if (!ofnode_valid(node) ||
+ uclass_get_device_by_ofnode(UCLASS_MDIO, node, ) ||
+ device_probe(bus)) {
+ printf("Cannot find MDIO bus\n");
+ return -ENODEV;
+ }
+
+ val = dm_mdio_read(bus, 0x0, MDIO_DEVAD_NONE, MVEBU_SW_PORT_SWITCH_ID);
+ if (val == SWITCH_88E6361_PRODUCT_NUMBER)
+ return true;
+ else
+ return false;
+}
+
int board_early_init_f(void)
{
return 0;
@@ -357,6
[PATCH v2 2/3] arm: mvebu: Espressobin: move network setup into a separate function
Currently, Esspresobin switch is being setup directly in last_stage_init()
which makes it hard to add support for any other board to be setup.
So, lets just move the switch setup code to a separate function and call it
if compatible matches, there should be no functional change.
Signed-off-by: Robert Marko
Reviewed-by: Stefan Roese
---
Changes in v2:
* Rebase on top of current master and resolve conflicts
board/Marvell/mvebu_armada-37xx/board.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/board/Marvell/mvebu_armada-37xx/board.c
b/board/Marvell/mvebu_armada-37xx/board.c
index 1471caa9a6..f532486b70 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -301,14 +301,12 @@ static int mii_multi_chip_mode_write(struct udevice *bus,
int dev_smi_addr,
return 0;
}
-/* Bring-up board-specific network stuff */
-static int last_stage_init(void)
+static int espressobin_last_stage_init(void)
{
struct udevice *bus;
ofnode node;
- if (!CONFIG_IS_ENABLED(DM_MDIO) ||
- !of_machine_is_compatible("globalscale,espressobin"))
+ if (!CONFIG_IS_ENABLED(DM_MDIO))
return 0;
node = ofnode_by_compatible(ofnode_null(), "marvell,orion-mdio");
@@ -358,8 +356,17 @@ static int last_stage_init(void)
return 0;
}
-EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
+/* Bring-up board-specific network stuff */
+static int last_stage_init(void)
+{
+
+ if (of_machine_is_compatible("globalscale,espressobin"))
+ return espressobin_last_stage_init();
+
+ return 0;
+}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
#endif
#ifdef CONFIG_OF_BOARD_SETUP
--
2.41.0
[PATCH v2 1/3] arm: mvebu: Espressobin: move FDT fixup into a separate function
Currently, Esspresobin FDT is being fixed up directly in ft_board_setup()
which makes it hard to add support for any other board to be fixed up.
So, lets just move the FDT fixup code to a separate function and call it
if compatible matches, there should be no functional change.
Signed-off-by: Robert Marko
Reviewed-by: Stefan Roese
---
board/Marvell/mvebu_armada-37xx/board.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/board/Marvell/mvebu_armada-37xx/board.c
b/board/Marvell/mvebu_armada-37xx/board.c
index 04124d8014..1471caa9a6 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -363,18 +363,14 @@ EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
#endif
#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, struct bd_info *bd)
+static int espressobin_fdt_setup(void *blob)
{
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
int ret;
int spi_off;
int parts_off;
int part_off;
/* Fill SPI MTD partitions for Linux kernel on Espressobin */
- if (!of_machine_is_compatible("globalscale,espressobin"))
- return 0;
-
spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
if (spi_off < 0)
return 0;
@@ -459,6 +455,14 @@ int ft_board_setup(void *blob, struct bd_info *bd)
return 0;
}
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+ if (of_machine_is_compatible("globalscale,espressobin"))
+ return espressobin_fdt_setup(blob);
#endif
return 0;
}
--
2.41.0
Re: [PATCH] kbuild: use which $(DTC) as a dependency
On 17. 10. 2023. 12:44, Richard Marko wrote: If we try to build using external dtc using make DTC=dtc we get a confusing error like make[2]: *** No rule to make target 'arch/x86/dts/bayleybay.dtb', needed by 'dtbs'. Stop. Workaround is to use make DTC=$( which dtc ) Can you please use command -v dtc instead as which is not part of POSIX? Regards, Robert which gives make a full path, so the dependency is satisfied. This was introduced by commit d50af66 kbuild: add dtc as dependency on .dtb files and we extend it so it calls which automatically (similar to scripts/dtc-version.sh) Signed-off-by: Richard Marko --- scripts/Makefile.lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 8dc6ec82cd..04fc9b0752 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -351,7 +351,7 @@ endif dtsi_include_list_deps = $(addprefix $(obj)/,$(subst $(quote),,$(dtsi_include_list))) -$(obj)/%.dtb: $(src)/%.dts $(DTC) $(dtsi_include_list_deps) FORCE +$(obj)/%.dtb: $(src)/%.dts $(shell which $(DTC)) $(dtsi_include_list_deps) FORCE $(call if_changed_dep,dtc) pre-tmp = $(subst $(comma),_,$(dot-target).pre.tmp)
[PATCH 3/3] arm: mvebu: eDPU: support new board revision
There is a new eDPU revision that uses Marvell 88E6361 switch onboard.
We can rely on detecting the switch to enable and fixup the Linux DTS
so a single DTS can be used.
There is currently no support for the 88E6361 switch and thus no working
networking in U-Boot, so we disable both ports.
Signed-off-by: Robert Marko
---
arch/arm/dts/armada-3720-eDPU-u-boot.dtsi | 13 ++-
arch/arm/dts/armada-3720-eDPU.dts | 47
board/Marvell/mvebu_armada-37xx/board.c | 125 ++
configs/eDPU_defconfig| 2 +
4 files changed, 182 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi
b/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi
index cb02b70e54..c3d450dd83 100644
--- a/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi
+++ b/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi
@@ -32,14 +32,17 @@
bootph-all;
};
- {
- /* G.hn does not work without additional configuration */
- status = "disabled";
-};
-
{
fixed-link {
speed = <1000>;
full-duplex;
};
};
+
+/*
+ * eDPU v2 has a MV88E6361 switch on the MDIO bus and U-boot is used
+ * to patch the Linux DTS if its found so enable MDIO by default.
+ */
+ {
+ status = "okay";
+};
diff --git a/arch/arm/dts/armada-3720-eDPU.dts
b/arch/arm/dts/armada-3720-eDPU.dts
index 57fc698e55..d6d37a1f6f 100644
--- a/arch/arm/dts/armada-3720-eDPU.dts
+++ b/arch/arm/dts/armada-3720-eDPU.dts
@@ -12,3 +12,50 @@
{
phy-mode = "2500base-x";
};
+
+/*
+ * External MV88E6361 switch is only available on v2 of the board.
+ * U-Boot will enable the MDIO bus and switch nodes.
+ */
+ {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+
+ /* Actual device is MV88E6361 */
+ switch: switch@0 {
+ compatible = "marvell,mv88e6190";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "cpu";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ ethernet = <>;
+ };
+
+ port@9 {
+ reg = <9>;
+ label = "downlink";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ };
+
+ port@a {
+ reg = <10>;
+ label = "uplink";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ sfp = <_eth1>;
+ };
+ };
+ };
+};
diff --git a/board/Marvell/mvebu_armada-37xx/board.c
b/board/Marvell/mvebu_armada-37xx/board.c
index 6527155c6e..6d633e94f3 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -49,6 +50,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* Single-chip mode */
/* Switch Port Registers */
#define MVEBU_SW_LINK_CTRL_REG (1)
+#define MVEBU_SW_PORT_SWITCH_ID(3)
#define MVEBU_SW_PORT_CTRL_REG (4)
#define MVEBU_SW_PORT_BASE_VLAN(6)
@@ -56,6 +58,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define MVEBU_G2_SMI_PHY_CMD_REG (24)
#define MVEBU_G2_SMI_PHY_DATA_REG (25)
+#define SWITCH_88E6361_PRODUCT_NUMBER 0x2610
+
/*
* Memory Controller Registers
*
@@ -72,6 +76,27 @@ DECLARE_GLOBAL_DATA_PTR;
#define A3700_MC_CTRL2_SDRAM_TYPE_DDR3 2
#define A3700_MC_CTRL2_SDRAM_TYPE_DDR4 3
+static bool is_edpu_plus(void)
+{
+ struct udevice *bus;
+ ofnode node;
+ int val;
+
+ node = ofnode_by_compatible(ofnode_null(), "marvell,orion-mdio");
+ if (!ofnode_valid(node) ||
+ uclass_get_device_by_ofnode(UCLASS_MDIO, node, ) ||
+ device_probe(bus)) {
+ printf("Cannot find MDIO bus\n");
+ return -ENODEV;
+ }
+
+ val = dm_mdio_read(bus, 0x0, MDIO_DEVAD_NONE, MVEBU_SW_PORT_SWITCH_ID);
+ if (val == SWITCH_88E6361_PRODUCT_NUMBER)
+ return true;
+ else
+ return false;
+}
+
int board_early_init_f(void)
{
return 0;
@@ -353,6 +378,41 @@
[PATCH 2/3] arm: mvebu: Espressobin: move network setup into a separate function
Currently, Esspresobin switch is being setup directly in last_stage_init()
which makes it hard to add support for any other board to be setup.
So, lets just move the switch setup code to a separate function and call it
if compatible matches, there should be no functional change.
Signed-off-by: Robert Marko
---
board/Marvell/mvebu_armada-37xx/board.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/board/Marvell/mvebu_armada-37xx/board.c
b/board/Marvell/mvebu_armada-37xx/board.c
index da325e8c75..6527155c6e 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -300,15 +300,11 @@ static int mii_multi_chip_mode_write(struct udevice *bus,
int dev_smi_addr,
return 0;
}
-/* Bring-up board-specific network stuff */
-int last_stage_init(void)
+static int espressobin_last_stage_init(void)
{
struct udevice *bus;
ofnode node;
- if (!of_machine_is_compatible("globalscale,espressobin"))
- return 0;
-
node = ofnode_by_compatible(ofnode_null(), "marvell,orion-mdio");
if (!ofnode_valid(node) ||
uclass_get_device_by_ofnode(UCLASS_MDIO, node, ) ||
@@ -356,6 +352,16 @@ int last_stage_init(void)
return 0;
}
+
+/* Bring-up board-specific network stuff */
+int last_stage_init(void)
+{
+
+ if (of_machine_is_compatible("globalscale,espressobin"))
+ return espressobin_last_stage_init();
+
+ return 0;
+}
#endif
#ifdef CONFIG_OF_BOARD_SETUP
--
2.41.0
[PATCH 1/3] arm: mvebu: Espressobin: move FDT fixup into a separate function
Currently, Esspresobin FDT is being fixed up directly in ft_board_setup()
which makes it hard to add support for any other board to be fixed up.
So, lets just move the FDT fixup code to a separate function and call it
if compatible matches, there should be no functional change.
Signed-off-by: Robert Marko
---
board/Marvell/mvebu_armada-37xx/board.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/board/Marvell/mvebu_armada-37xx/board.c
b/board/Marvell/mvebu_armada-37xx/board.c
index 3ab6e8873d..da325e8c75 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -359,18 +359,14 @@ int last_stage_init(void)
#endif
#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, struct bd_info *bd)
+static int espressobin_fdt_setup(void *blob)
{
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
int ret;
int spi_off;
int parts_off;
int part_off;
/* Fill SPI MTD partitions for Linux kernel on Espressobin */
- if (!of_machine_is_compatible("globalscale,espressobin"))
- return 0;
-
spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
if (spi_off < 0)
return 0;
@@ -455,6 +451,14 @@ int ft_board_setup(void *blob, struct bd_info *bd)
return 0;
}
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+ if (of_machine_is_compatible("globalscale,espressobin"))
+ return espressobin_fdt_setup(blob);
#endif
return 0;
}
--
2.41.0
Re: [PATCH] ARM: dts: am335x-pocketbeagle: choose tick-timer
On Wed, Aug 30, 2023 at 10:26 AM Trevor Woerner wrote:
>
> Commit 4b2be78ab66c ("time: Fix get_ticks being non-monotonic")
> requires '/chosen/tick-timer' in device-tree. Otherwise we get:
>
> U-Boot 2023.07.02 (Jul 11 2023 - 15:20:44 +)
>
> CPU : AM335X-GP rev 2.1
> Model: TI AM335x PocketBeagle
> DRAM: 512 MiB
> Core: 154 devices, 16 uclasses, devicetree: separate
> Could not initialize timer (err -19)
>
> resetting ...
>
> Suggested-by: Pierre Lebleu
> Signed-off-by: Trevor Woerner
Tested-by: Robert Nelson
> ---
> arch/arm/dts/am335x-pocketbeagle.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/dts/am335x-pocketbeagle.dts
> b/arch/arm/dts/am335x-pocketbeagle.dts
> index b379e3a5570d..02e3aac56064 100644
> --- a/arch/arm/dts/am335x-pocketbeagle.dts
> +++ b/arch/arm/dts/am335x-pocketbeagle.dts
> @@ -15,6 +15,7 @@
>
> chosen {
> stdout-path =
> + tick-timer =
> };
>
> leds {
> --
> 2.41.0.327.gaa9166bcc0ba
Thanks for posting this Trevor, I'm also running with this change..
Regards,
--
Robert Nelson
https://rcn-ee.com/
Re: [PATCH V4 8/8] doc: board: ti: Add BeaglePlay documentation
> > Just https://etcher.balena.io/ and flash an SD card with the official > > image here: https://www.beagleboard.org/distros/beagleplay-debian-11-flasher > > > > https://files.beagle.cc/file/beagleboard-public-2021/images/am625x-emmc-flasher-debian-11.6-xfce-arm64-2023-02-04-10gb.img.xz > > OK I tried that on an SD card, but it is still bricked. > Hi Simon, I've found the bootrom can be a little too quick and you'll get stuck on a failed eMMC bootloader. I find it best, with power applied, if you hold both the USR and RESET buttons down, then lift off the RESET button.. This will ensure the bootrom/sysboot will actually load the microSD's version of u-boot. If it's still failing, please grab this newer small August release: That's posted here: https://forum.beagleboard.org/t/arm64-debian-11-x-bullseye-monthly-snapshots-2023-08-05/32318 (updated monthly) Specifically this flasher file: https://rcn-ee.com/rootfs/release/2023-08-05/bullseye-minimal-arm64/beagleplay-emmc-flasher-debian-11.7-minimal-arm64-2023-08-05-4gb.img.xz Use Balena Etcher to write it directly to a microSD. Insert microSD in Apply Power (leds should turn on, if not hit the PWR button to wake up the TPS...) Next, hold both USR and RESET buttons Now, Lift off only the RESET button When even more leds turn on, lift up on the USR button. At this point the serial should be loading/booting linux, and then running the eMMC flasher in single user mode. Within 5 minutes or so, it should shutdown with a new image in the eMMC.. Regards, -- Robert Nelson https://rcn-ee.com/
[PATCH 2/2] net: mv88e6xxx: add Clause 45 support
Marvell LinkStreet switches support Clause 45 MDIO on the internal bus.
C45 read or writes require the register address to be written first to
the SMI PHY Data register, and then a special C45 Write Address Register
OP is used on the SMI PHY Register before making a C45 Read Data Register
OP and being able to actually read the register.
Signed-off-by: Robert Marko
---
drivers/net/mv88e6xxx.c | 69 +++--
1 file changed, 67 insertions(+), 2 deletions(-)
diff --git a/drivers/net/mv88e6xxx.c b/drivers/net/mv88e6xxx.c
index deb72772d19..b9ee093c3af 100644
--- a/drivers/net/mv88e6xxx.c
+++ b/drivers/net/mv88e6xxx.c
@@ -114,6 +114,9 @@
#define SMI_CMD_OP_MASKGENMASK(11, 10)
#define SMI_CMD_CLAUSE_22_OP_WRITE 0x1
#define SMI_CMD_CLAUSE_22_OP_READ 0x2
+#define SMI_CMD_CLAUSE_45_OP_WRITE_ADDR0x0
+#define SMI_CMD_CLAUSE_45_OP_WRITE 0x1
+#define SMI_CMD_CLAUSE_45_OP_READ 0x3
#define SMI_CMD_ADDR_MASK GENMASK(9, 5)
#define SMI_CMD_REG_MASK GENMASK(4, 0)
@@ -125,6 +128,18 @@
(SMI_BUSY | SMI_CMD_CLAUSE_22 | FIELD_PREP(SMI_CMD_OP_MASK,
SMI_CMD_CLAUSE_22_OP_WRITE)) | \
(FIELD_PREP(SMI_CMD_ADDR_MASK, addr)) | \
(FIELD_PREP(SMI_CMD_REG_MASK, reg))
+#define SMI_CMD_SET_C45_ADDR(phyad, devad) \
+ (SMI_BUSY | FIELD_PREP(SMI_CMD_OP_MASK,
SMI_CMD_CLAUSE_45_OP_WRITE_ADDR)) | \
+ (FIELD_PREP(SMI_CMD_ADDR_MASK, phyad)) | \
+ (FIELD_PREP(SMI_CMD_REG_MASK, devad))
+#define SMI_CMD_READ_C45(phyad, devad) \
+ (SMI_BUSY | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_45_OP_READ)) | \
+ (FIELD_PREP(SMI_CMD_ADDR_MASK, phyad)) | \
+ (FIELD_PREP(SMI_CMD_REG_MASK, devad))
+#define SMI_CMD_WRITE_C45(phyad, devad) \
+ (SMI_BUSY | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_45_OP_WRITE)) | \
+ (FIELD_PREP(SMI_CMD_ADDR_MASK, phyad)) | \
+ (FIELD_PREP(SMI_CMD_REG_MASK, devad))
/* ID register values for different switch models */
#define PORT_SWITCH_ID_60200x0200
@@ -273,12 +288,37 @@ static int mv88e6xxx_phy_wait(struct udevice *dev)
static int mv88e6xxx_phy_read_indirect(struct udevice *dev, int phyad, int
devad, int reg)
{
struct mv88e6xxx_priv *priv = dev_get_priv(dev);
+ u16 smi_cmd;
int res;
+ if (devad >= 0) {
+ /*
+* For C45 we need to write the register address into the
+* PHY Data register first and then call the Write Address
+* Register OP in the PHY command register.
+*/
+ res = mv88e6xxx_reg_write(dev, priv->global2,
+ GLOBAL2_REG_PHY_DATA,
+ reg);
+
+ res = mv88e6xxx_reg_write(dev, priv->global2,
+ GLOBAL2_REG_PHY_CMD,
+ SMI_CMD_SET_C45_ADDR(phyad, devad));
+
+ /* Wait for busy bit to clear */
+ res = mv88e6xxx_phy_wait(dev);
+ if (res < 0)
+ return res;
+
+ /* Set the actual C45 or C22 OP-s */
+ smi_cmd = SMI_CMD_READ_C45(phyad, devad);
+ } else
+ smi_cmd = SMI_CMD_READ(phyad, reg);
+
/* Issue command to read */
res = mv88e6xxx_reg_write(dev, priv->global2,
GLOBAL2_REG_PHY_CMD,
- SMI_CMD_READ(phyad, reg));
+ smi_cmd);
/* Wait for data to be read */
res = mv88e6xxx_phy_wait(dev);
@@ -294,8 +334,33 @@ static int mv88e6xxx_phy_write_indirect(struct udevice
*dev, int phyad,
int devad, int reg, u16 data)
{
struct mv88e6xxx_priv *priv = dev_get_priv(dev);
+ u16 smi_cmd;
int res;
+ if (devad >= 0) {
+ /*
+* For C45 we need to write the register address into the
+* PHY Data register first and then call the Write Address
+* Register OP in the PHY command register.
+*/
+ res = mv88e6xxx_reg_write(dev, priv->global2,
+ GLOBAL2_REG_PHY_DATA,
+ reg);
+
+ res = mv88e6xxx_reg_write(dev, priv->global2,
+ GLOBAL2_REG_PHY_CMD,
+ SMI_CMD_SET_C45_ADDR(phyad, devad));
+
+ /* Wait for busy bit to clear */
+ res = mv88e6xxx_phy_wait(dev);
+ if (res < 0)
+ return res;
+
+ /* Set the actual C45 or C22 OP-s */
+ smi_cmd = SMI_CMD_WRITE_C45(phyad, devad);
+ } else
+ smi_cmd = SMI_CMD_WRITE(phyad, reg);
+
/* Set the d
[PATCH 1/2] net: mv88e6xxx: use generic bitfield macros for MDIO
Driver is currently defining the mask and bit shifting itself, there is no need for that as U-Boot has generic bitfield macros that help us achieve the same result but in a cleaner way. Signed-off-by: Robert Marko --- drivers/net/mv88e6xxx.c | 25 + 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/net/mv88e6xxx.c b/drivers/net/mv88e6xxx.c index 64e860e324d..deb72772d19 100644 --- a/drivers/net/mv88e6xxx.c +++ b/drivers/net/mv88e6xxx.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -110,20 +111,20 @@ */ #define SMI_BUSY BIT(15) #define SMI_CMD_CLAUSE_22 BIT(12) -#define SMI_CMD_CLAUSE_22_OP_READ (2 << 10) -#define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10) -#define SMI_CMD_ADDR_SHIFT 5 -#define SMI_CMD_ADDR_MASK 0x1f -#define SMI_CMD_REG_SHIFT 0 -#define SMI_CMD_REG_MASK 0x1f +#define SMI_CMD_OP_MASKGENMASK(11, 10) +#define SMI_CMD_CLAUSE_22_OP_WRITE 0x1 +#define SMI_CMD_CLAUSE_22_OP_READ 0x2 + +#define SMI_CMD_ADDR_MASK GENMASK(9, 5) +#define SMI_CMD_REG_MASK GENMASK(4, 0) #define SMI_CMD_READ(addr, reg) \ - (SMI_BUSY | SMI_CMD_CLAUSE_22 | SMI_CMD_CLAUSE_22_OP_READ) | \ - (((addr) & SMI_CMD_ADDR_MASK) << SMI_CMD_ADDR_SHIFT) | \ - (((reg) & SMI_CMD_REG_MASK) << SMI_CMD_REG_SHIFT) + (SMI_BUSY | SMI_CMD_CLAUSE_22 | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_22_OP_READ)) | \ + (FIELD_PREP(SMI_CMD_ADDR_MASK, addr)) | \ + (FIELD_PREP(SMI_CMD_REG_MASK, reg)) #define SMI_CMD_WRITE(addr, reg) \ - (SMI_BUSY | SMI_CMD_CLAUSE_22 | SMI_CMD_CLAUSE_22_OP_WRITE) | \ - (((addr) & SMI_CMD_ADDR_MASK) << SMI_CMD_ADDR_SHIFT) | \ - (((reg) & SMI_CMD_REG_MASK) << SMI_CMD_REG_SHIFT) + (SMI_BUSY | SMI_CMD_CLAUSE_22 | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_22_OP_WRITE)) | \ + (FIELD_PREP(SMI_CMD_ADDR_MASK, addr)) | \ + (FIELD_PREP(SMI_CMD_REG_MASK, reg)) /* ID register values for different switch models */ #define PORT_SWITCH_ID_60200x0200 -- 2.41.0
AW: getting u-boot to work on raspi 3b (32bit)
Hi Simon,
meanwhile I've tried booting from an FIT image. I.e. I wrote an ist file and
baked an itb for booting.
However, that gave me errors along the lines of "Wrong image format for bootm
command".
So I kept trying to boot the thing using the old fashioned way.
After some trial and error (recompiling the kernel with identical setting and
hooking up a monitor) u-boot handed control over to the kernel and I was indeed
greeted by 4 raspberries.
Unfortunately it got stuck after that, not leaving any (error) messages.
I next tried to boot from a pre-built raspbian kernel which I knew should work.
It gave identical results.
For fun, I also tried to boot from the console, entering the commands manually.
Then it complained about wrong magic bytes or some such (also for the Raspbian
kernel). Why this, all of a sudden?
I'm running out of ideas of might go wrong here.
Am I missing something completely here?
Have a nice weekend
Robert
PS: The problems with the serial port outputting garbage when scanning USB and
starting the kernel still persist. I guess this doesn't work as intended?
PPS: A ready to go distribution probably isn't going to help much as, figuring
out how to setup the boot process with u-boot from scratch is the whole point
of the project. Later on we want to repeat the process on some old, exotic
embedded system which is already known to be quite quirky. (Of course, it has
dropped out of support a long time ago...)
-Ursprüngliche Nachricht-
Von: Simon Glass
Gesendet: Dienstag, 25. Juli 2023 23:29
An: Robert Wenisch
Cc: u-boot@lists.denx.de
Betreff: Re: getting u-boot to work on raspi 3b (32bit)
Hi Robert,
On Tue, 25 Jul 2023 at 09:42, Robert Wenisch wrote:
>
> Hello,
>
> in order to study the boot process of embedded ARM systems, I decided to
> start with something well documented: booting as raspi 3b using u-boot.
> I downloaded kernel sources and u-boot sources. I built the kernel
> with
>
> CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm make bcmrpi_defconfig
> CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm make -j6 zImage dtbs
> modules cp arch/arm/boot/zImage /path/to/sdcard-boot-partition cp
> arch/arm/boot/dts/bcm2710-rpi-3-b.dtb /path/to/sdcard-boot-partition
> CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm INSTALL_MOD_PATH make
> modules_install
>
> Further I compiled and setup u-boot:
>
> CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm make rpi_3_32b_defconfig
> CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm make -j6
>
> cp u-boot.bin /path/to/ sdcard-boot-partition
>
> I then went on to edit the config.txt:
>
> kernel=u-boot-bin
> enable_uart=1
> arm_64bit=0
> device_tree=bcm2710-rpi-3-b.dtb
>
> and boot.txt goes
>
> fatload mmc 0:1 ${fdt_addr_r} bcm2710-rpi-3-b.dtb fatload mmc 0:1
> $kernel_addr_r} zImage setenv bootargs console=ttyS0,115200
> root=/dev/mmcblk0p2 rootfstype=ext4 rootwait rw earlyprintk bootz
> ${kernel_addr_r} - {fdt_addr_r}
>
> I produced an image of boot.txt
>
> mkimage -A arm -O linux -T script -d boot.txt boot.scr
>
> Frustratingly, it didn't go as smoothly as expected.
You should really be using FIT [1] for this, rather than legacy images.
>
> With these setting I got up to state "Starting Kernel ..." over the serial
> port, then it freezes (or at least doesn't log anything on the tty).
> I can't post the whole log as I only have it on my dev-machine.
You could try things like earlycon to get some console output.
> However some interesting bits for now:
> I'm booting on u-boot 2023-07-0967-g94e7cb181a
> 1 - Pretty much at the beginning it says "Loading Environment from FAT... ***
> warning - bad CRC, using default environment"
> I suppose this only means we're not providing a .env file?
Yes
>
> 2 - Upon "Scanning bus usb@7e98 for devices... it's logging a lot of
> garbage (as in misinterpreted character codes), what might be going on there?
No...some sort of clock problem?
>
> 3 - A bit further down it states "Found U-Boot script /boot.scr"
> [...]
> "## Executing script at 0240"
> As this changes when I edit around the boot.txt and mkimage, I infer u-boot
> is indeed loading my boot instructions not just some default values.
OK
>
> Then follow some info on kernel image flatted device tree blob and their
> respective memory addresses.
> It the tries to load the kernel to little apparent success :/
>
> This procedure is what I gathered from a plethora of tutorial and howtos.
> Most of these are quite old, have there been breaking changes in u-boot's
> development in the meanwhile?
> For example some sources state the kernel is launched via booti
> ${kernel_addr_r} - {fdt_addr_r}, however the booti command seem to be absent
> in my u-boot version.
getting u-boot to work on raspi 3b (32bit)
Hello,
in order to study the boot process of embedded ARM systems, I decided to start
with something well documented: booting as raspi 3b using u-boot.
I downloaded kernel sources and u-boot sources. I built the kernel with
CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm make bcmrpi_defconfig
CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm make -j6 zImage dtbs modules
cp arch/arm/boot/zImage /path/to/sdcard-boot-partition
cp arch/arm/boot/dts/bcm2710-rpi-3-b.dtb /path/to/sdcard-boot-partition
CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm INSTALL_MOD_PATH make
modules_install
Further I compiled and setup u-boot:
CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm make rpi_3_32b_defconfig
CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm make -j6
cp u-boot.bin /path/to/ sdcard-boot-partition
I then went on to edit the config.txt:
kernel=u-boot-bin
enable_uart=1
arm_64bit=0
device_tree=bcm2710-rpi-3-b.dtb
and boot.txt goes
fatload mmc 0:1 ${fdt_addr_r} bcm2710-rpi-3-b.dtb
fatload mmc 0:1 $kernel_addr_r} zImage
setenv bootargs console=ttyS0,115200 root=/dev/mmcblk0p2 rootfstype=ext4
rootwait rw earlyprintk
bootz ${kernel_addr_r} - {fdt_addr_r}
I produced an image of boot.txt
mkimage -A arm -O linux -T script -d boot.txt boot.scr
Frustratingly, it didn't go as smoothly as expected.
With these setting I got up to state "Starting Kernel ..." over the serial
port, then it freezes (or at least doesn't log anything on the tty).
I can't post the whole log as I only have it on my dev-machine.
However some interesting bits for now:
I'm booting on u-boot 2023-07-0967-g94e7cb181a
1 - Pretty much at the beginning it says "Loading Environment from FAT... ***
warning - bad CRC, using default environment"
I suppose this only means we're not providing a .env file?
2 - Upon "Scanning bus usb@7e98 for devices... it's logging a lot of
garbage (as in misinterpreted character codes), what might be going on there?
3 - A bit further down it states "Found U-Boot script /boot.scr"
[...]
"## Executing script at 0240"
As this changes when I edit around the boot.txt and mkimage, I infer u-boot is
indeed loading my boot instructions not just some default values.
Then follow some info on kernel image flatted device tree blob and their
respective memory addresses.
It the tries to load the kernel to little apparent success :/
This procedure is what I gathered from a plethora of tutorial and howtos. Most
of these are quite old, have there been breaking changes in u-boot's
development in the meanwhile?
For example some sources state the kernel is launched via booti
${kernel_addr_r} - {fdt_addr_r}, however the booti command seem to be absent in
my u-boot version.
Is there anything else I#m doing wrong?
I'll be grateful for any hints at this point...
Cheers Robert
Re-writing SMC91111 Ethernet driver
Hi, The SMC9 Ethernet driver was removed in commit ecf1d2741d95f5f84e31dc1d0bef149d8ff1f0a3 because it had not been converted to DM_ETH. I would be interested in doing the conversion and re-instating the driver to support Arm FastModel virtual prototypes (and Juno r0 hardware while I'm at it). I had a couple of questions 1. Is there any advantage or preference for starting with the previous code or am I free to start from another point? My inclination was to copy'n'paste something like the SMC91x driver in order to get the outline, CONFIG_OF and DM_ETH framework correct and then fill out the actual moving parts with code from the previous implementation (or the Linux kernel if that has been updated more recently). 2. Can I ignore all the original CONFIG_ options and just write a driver that supports one fixed combination of those options and is only intended to work in the vexpress64 config? Based on the commit above it was only still in use on two armltd platforms: integrator (splendidly obsolete) and vexpress64 (which covers my two cases). I don't want to unnecessarily disadvantage another platform that could otherwise benefit from re-enabling the device again, but equally it would be nice to avoid the various macros for different types of access especially if I can't test them, and they are unlikely to ever be used. Many thanks Robert
Re: [PATCH] arm64: a37xx: pinctrl: probe after binding
On Mon, Feb 13, 2023 at 12:36 AM Simon Glass wrote:
>
> Hi,
>
> On Thu, 19 Jan 2023 at 00:00, Stefan Roese wrote:
> >
> > On 1/17/23 15:08, Robert Marko wrote:
> > > Currently, pinctrl drivers are getting probed during post-bind, however
> > > that is being reverted, and on A37XX pinctrl driver is the one that
> > > registers the GPIO driver during the probe.
> > >
> > > So, if the pinctrl driver doesn't get probed GPIO-s won't get registered
> > > and thus they cannot be used.
> > >
> > > This is a problem on the Methode eDPU as it just uses SB pins as GPIO-s
> > > and without them being registered networking won't work as it only has
> > > one SFP slot and the TX disable GPIO is on the SB controller.
> > >
> > > So, lets just add a flag only to A37XX driver to probe after binding
> > > in order for the GPIO driver to always get registered.
> > >
> > > Signed-off-by: Robert Marko
> >
> > Reviewed--by: Stefan Roese
> >
> > Thanks,
> > Stefan
> >
> > > ---
> > > drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 14 ++
> > > 1 file changed, 14 insertions(+)
> > >
> > > diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> > > b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> > > index 25fbe39abd1..1be6252227d 100644
> > > --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> > > +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> > > @@ -745,6 +745,19 @@ static int armada_37xx_pinctrl_probe(struct udevice
> > > *dev)
> > > return 0;
> > > }
> > >
> > > +static int armada_37xx_pinctrl_bind(struct udevice *dev)
> > > +{
> > > + /*
> > > + * Make sure that the pinctrl driver gets probed after binding
> > > + * as on A37XX the pinctrl driver is the one that is also
> > > + * registering the GPIO one during probe, so if its not probed
> > > + * GPIO-s are not registered as well.
> > > + */
> > > + dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > static const struct udevice_id armada_37xx_pinctrl_of_match[] = {
> > > {
> > > .compatible = "marvell,armada3710-sb-pinctrl",
> > > @@ -762,6 +775,7 @@ U_BOOT_DRIVER(armada_37xx_pinctrl) = {
> > > .id = UCLASS_PINCTRL,
> > > .of_match = of_match_ptr(armada_37xx_pinctrl_of_match),
> > > .probe = armada_37xx_pinctrl_probe,
> > > + .bind = armada_37xx_pinctrl_bind,
> > > .priv_auto = sizeof(struct armada_37xx_pinctrl),
> > > .ops = _37xx_pinctrl_ops,
> > > };
> >
>
> This is OK if you really want to do this. Is it not possible to do the
> bind of the GPIO devices in the pinctrl bind() handler, as is done by
> other SoCs? Why do we need to probe the pinctrl driver first?
Because on A37xx the pinctrl driver needs to be probed before the GPIO
one can be probed as GPIO driver is using internal data that is filled in
by the pinctrl driver.
Regards,
Robert
>
> Reviewed-by: Simon Glass
--
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
1 Zagreb, Croatia
Email: robert.ma...@sartura.hr
Web: www.sartura.hr
[PATCH] arm64: a37xx: pinctrl: probe after binding
Currently, pinctrl drivers are getting probed during post-bind, however
that is being reverted, and on A37XX pinctrl driver is the one that
registers the GPIO driver during the probe.
So, if the pinctrl driver doesn't get probed GPIO-s won't get registered
and thus they cannot be used.
This is a problem on the Methode eDPU as it just uses SB pins as GPIO-s
and without them being registered networking won't work as it only has
one SFP slot and the TX disable GPIO is on the SB controller.
So, lets just add a flag only to A37XX driver to probe after binding
in order for the GPIO driver to always get registered.
Signed-off-by: Robert Marko
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 25fbe39abd1..1be6252227d 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -745,6 +745,19 @@ static int armada_37xx_pinctrl_probe(struct udevice *dev)
return 0;
}
+static int armada_37xx_pinctrl_bind(struct udevice *dev)
+{
+ /*
+* Make sure that the pinctrl driver gets probed after binding
+* as on A37XX the pinctrl driver is the one that is also
+* registering the GPIO one during probe, so if its not probed
+* GPIO-s are not registered as well.
+*/
+ dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
+ return 0;
+}
+
static const struct udevice_id armada_37xx_pinctrl_of_match[] = {
{
.compatible = "marvell,armada3710-sb-pinctrl",
@@ -762,6 +775,7 @@ U_BOOT_DRIVER(armada_37xx_pinctrl) = {
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(armada_37xx_pinctrl_of_match),
.probe = armada_37xx_pinctrl_probe,
+ .bind = armada_37xx_pinctrl_bind,
.priv_auto = sizeof(struct armada_37xx_pinctrl),
.ops = _37xx_pinctrl_ops,
};
--
2.39.0
Re: [PATCH] dm: pinctrl: Revert "pinctrl: probe pinctrl drivers during post-bind"
On Fri, Jan 13, 2023 at 12:43 AM Simon Glass wrote: > > Hi, > > On Tue, 3 Jan 2023 at 10:05, Simon Glass wrote: > > > > Hi Robert, > > > > On Fri, 30 Dec 2022 at 13:26, Robert Marko wrote: > > > > > > > > > > > > On Fri, Dec 30, 2022 at 8:02 PM Simon Glass wrote: > > >> > > >> Hi Pali, > > >> > > >> On Fri, 30 Dec 2022 at 12:02, Pali Rohár wrote: > > >> > > > >> > On Friday 30 December 2022 11:47:29 Simon Glass wrote: > > >> > > Hi Pali, > > >> > > > > >> > > On Fri, 30 Dec 2022 at 10:13, Pali Rohár wrote: > > >> > > > > > >> > > > On Friday 30 December 2022 10:00:11 Simon Glass wrote: > > >> > > > > Hi Pali, > > >> > > > > > > >> > > > > On Fri, 30 Dec 2022 at 09:53, Pali Rohár wrote: > > >> > > > > > > > >> > > > > > On Friday 30 December 2022 09:30:27 Simon Glass wrote: > > >> > > > > > > Hi Pali, > > >> > > > > > > > > >> > > > > > > On Wed, 21 Dec 2022 at 17:02, Pali Rohár > > >> > > > > > > wrote: > > >> > > > > > > > > > >> > > > > > > > On Wednesday 21 December 2022 07:27:39 Simon Glass wrote: > > >> > > > > > > > > This breaks chromebook_coral and it is also not how > > >> > > > > > > > > things should work. If > > >> > > > > > > > > a board needs to bind GPIOs as part of a pinctrl driver > > >> > > > > > > > > this can be done > > >> > > > > > > > > during the bind step, if needed. > > >> > > > > > > > > > > >> > > > > > > > > We cannot probe pinctrl devices when binding as a rule, > > >> > > > > > > > > since it cannot be > > >> > > > > > > > > supported on some platforms. > > >> > > > > > > > > > > >> > > > > > > > > The bind and probe steps are separate in U-Boot and they > > >> > > > > > > > > should remain > > >> > > > > > > > > separate. > > >> > > > > > > > > > > >> > > > > > > > > This reverts commit > > >> > > > > > > > > f9ec791b5e24378b71590877499f8683d5f54dac. > > >> > > > > > > > > > >> > > > > > > > Unfortunately reverting this patch would break other > > >> > > > > > > > devices, mostly > > >> > > > > > > > A3720 based where pinctrl driver acts also as gpio driver. > > >> > > > > > > > Because no > > >> > > > > > > > other caller then register gpio driver and so other > > >> > > > > > > > drivers which parses > > >> > > > > > > > gpios from DT (which belongs to that gpio driver) will > > >> > > > > > > > fail during > > >> > > > > > > > probe. > > >> > > > > > > > > >> > > > > > > That is something to be sorted out for that platform. You > > >> > > > > > > can bind > > >> > > > > > > GPIO devices in the pinctrl driver's bind() method as other > > >> > > > > > > SoCs do. > > >> > > > > > > Even better, the device tree typically has that info in it, > > >> > > > > > > i.e. GPIO > > >> > > > > > > subnodes within the pinctrl node. > > >> > > > > > > > > >> > > > > > > Probing pinctrl in a bind function is unfortunately just > > >> > > > > > > wrong. It > > >> > > > > > > will cause all sorts of problems, and perhaps already has. > > >> > > > > > > > >> > > > > > Ok, so it means that > > >> > > > > > drivers/pinctrl/mvebu/pinctrl-armada-37xx.c needs > > >> > > > > >
Re: [PATCH] dm: pinctrl: Revert "pinctrl: probe pinctrl drivers during post-bind"
On Fri, Dec 30, 2022 at 8:02 PM Simon Glass wrote:
> Hi Pali,
>
> On Fri, 30 Dec 2022 at 12:02, Pali Rohár wrote:
> >
> > On Friday 30 December 2022 11:47:29 Simon Glass wrote:
> > > Hi Pali,
> > >
> > > On Fri, 30 Dec 2022 at 10:13, Pali Rohár wrote:
> > > >
> > > > On Friday 30 December 2022 10:00:11 Simon Glass wrote:
> > > > > Hi Pali,
> > > > >
> > > > > On Fri, 30 Dec 2022 at 09:53, Pali Rohár wrote:
> > > > > >
> > > > > > On Friday 30 December 2022 09:30:27 Simon Glass wrote:
> > > > > > > Hi Pali,
> > > > > > >
> > > > > > > On Wed, 21 Dec 2022 at 17:02, Pali Rohár
> wrote:
> > > > > > > >
> > > > > > > > On Wednesday 21 December 2022 07:27:39 Simon Glass wrote:
> > > > > > > > > This breaks chromebook_coral and it is also not how things
> should work. If
> > > > > > > > > a board needs to bind GPIOs as part of a pinctrl driver
> this can be done
> > > > > > > > > during the bind step, if needed.
> > > > > > > > >
> > > > > > > > > We cannot probe pinctrl devices when binding as a rule,
> since it cannot be
> > > > > > > > > supported on some platforms.
> > > > > > > > >
> > > > > > > > > The bind and probe steps are separate in U-Boot and they
> should remain
> > > > > > > > > separate.
> > > > > > > > >
> > > > > > > > > This reverts commit
> f9ec791b5e24378b71590877499f8683d5f54dac.
> > > > > > > >
> > > > > > > > Unfortunately reverting this patch would break other
> devices, mostly
> > > > > > > > A3720 based where pinctrl driver acts also as gpio driver.
> Because no
> > > > > > > > other caller then register gpio driver and so other drivers
> which parses
> > > > > > > > gpios from DT (which belongs to that gpio driver) will fail
> during
> > > > > > > > probe.
> > > > > > >
> > > > > > > That is something to be sorted out for that platform. You can
> bind
> > > > > > > GPIO devices in the pinctrl driver's bind() method as other
> SoCs do.
> > > > > > > Even better, the device tree typically has that info in it,
> i.e. GPIO
> > > > > > > subnodes within the pinctrl node.
> > > > > > >
> > > > > > > Probing pinctrl in a bind function is unfortunately just
> wrong. It
> > > > > > > will cause all sorts of problems, and perhaps already has.
> > > > > >
> > > > > > Ok, so it means that drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> needs
> > > > > > to be refactored and fixed to handle these restrictions.
> > > > >
> > > > > It is not a restriction. It is simply that binding and probing are
> > > > > different things and we should not tie them together. It will just
> > > > > become a nightmare for board bringup and other drivers.
> > > > >
> > > > > >
> > > > > > > > Also I think that pinctrl command would not work in this
> case if pinctrl
> > > > > > > > would not be probed.
> > > > > > >
> > > > > > > Devices are probed before use, including by commands.
> > > > > > >
> > > > > > > This is quite important to fix before the release.
> > > > > >
> > > > > > Unfortunately in this time I do not have any a3720 board for
> testing.
> > > > > > Robert was able to easily trigger this issue and also introduced
> that
> > > > > > commit f9ec791b5e24 ("pinctrl: probe pinctrl drivers during
> post-bind").
> > > > > >
> > > > > > So may I ask Robert to look at it? In past days I looked at
> powerpc
> > > > > > release issues and I do not have time for other things.
> > > > >
> > > > > That driver has a few FIXMEs in it and could use a look anyway. I
> see
> > > > > that the gpio controller is a subnode of pinctrl anyway. Adding a
> > > > > compatible string for it would fix the problem just like that, and
>
Re: [RFC PATCH] board: ti: common: board_detect: Fix EEPROM read quirk for 2-byte
> >>> Tested on J721E, J7200, DRA7xx, AM64x > >> > >> I'll try to test this on the AM335x boards I have as soon as possible. > > > > I wonder if we should re-factor this code a bit and not have a single > > ti_i2c_eeprom_get but instead build for whichever sets of quirks a given > > family of boards has with their EEPROMs. I really worry that we're going > > to find that this change here breaks yet another different EEPROM than > > before. > > > > Yes that does make sense... considering a new behavior of EEPROM keeps > showing up. I will try refactoring the logic that way. Due to part shorages, sadly the BeagleBone AI64 (J721E) has both 1byte and 2byte eeproms in user hands today.. While I think most other previous designs have stuck with one type of eeprom throughout their production life. So just one big outlier that I personally know of.. Regards, -- Robert Nelson https://rcn-ee.com/
