[U-Boot] [U-Boot, V5, PATCH 3/3] ag7xxx: add initial support for s17
From: Rosy Song
S17 ethernet support is for QCA8337N, which used on
AP152 (QCA9563) board. It is a 7 ports GbE switch.
Signed-off-by: Rosy Song
Changes for v2-v3:
- add more commit message for s17
Changes for v4-v5:
- coding style cleanup
---
drivers/net/ag7xxx.c | 139 ++-
1 file changed, 123 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ag7xxx.c b/drivers/net/ag7xxx.c
index 403eb64895..7f1dee4b3e 100644
--- a/drivers/net/ag7xxx.c
+++ b/drivers/net/ag7xxx.c
@@ -3,6 +3,7 @@
* Atheros AR71xx / AR9xxx GMAC driver
*
* Copyright (C) 2016 Marek Vasut
+ * Copyright (C) 2019 Rosy Song
*/
#include
@@ -23,7 +24,8 @@ DECLARE_GLOBAL_DATA_PTR;
enum ag7xxx_model {
AG7XXX_MODEL_AG933X,
AG7XXX_MODEL_AG934X,
- AG7XXX_MODEL_AG953X
+ AG7XXX_MODEL_AG953X,
+ AG7XXX_MODEL_AG956X
};
/* MAC Configuration 1 */
@@ -219,6 +221,7 @@ static int ag7xxx_switch_reg_read(struct mii_dev *bus, int
reg, u32 *val)
u32 reg_addr;
u32 phy_temp;
u32 reg_temp;
+ u32 reg_temp_w = (reg & 0xfffc) >> 1;
u16 rv = 0;
int ret;
@@ -226,18 +229,25 @@ static int ag7xxx_switch_reg_read(struct mii_dev *bus,
int reg, u32 *val)
priv->model == AG7XXX_MODEL_AG953X) {
phy_addr = 0x1f;
reg_addr = 0x10;
- } else if (priv->model == AG7XXX_MODEL_AG934X) {
+ } else if (priv->model == AG7XXX_MODEL_AG934X ||
+ priv->model == AG7XXX_MODEL_AG956X) {
phy_addr = 0x18;
reg_addr = 0x00;
} else
return -EINVAL;
- ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
+ if (priv->model == AG7XXX_MODEL_AG956X)
+ ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) &
0x1ff);
+ else
+ ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
if (ret)
return ret;
phy_temp = ((reg >> 6) & 0x7) | 0x10;
- reg_temp = (reg >> 1) & 0x1e;
+ if (priv->model == AG7XXX_MODEL_AG956X)
+ reg_temp = reg_temp_w & 0x1f;
+ else
+ reg_temp = (reg >> 1) & 0x1e;
*val = 0;
ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, );
@@ -245,7 +255,13 @@ static int ag7xxx_switch_reg_read(struct mii_dev *bus, int
reg, u32 *val)
return ret;
*val |= rv;
- ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, );
+ if (priv->model == AG7XXX_MODEL_AG956X) {
+ phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
+ reg_temp = (reg_temp_w + 1) & 0x1f;
+ ret = ag7xxx_switch_read(bus, phy_temp, reg_temp, );
+ } else {
+ ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, );
+ }
if (ret < 0)
return ret;
*val |= (rv << 16);
@@ -260,24 +276,34 @@ static int ag7xxx_switch_reg_write(struct mii_dev *bus,
int reg, u32 val)
u32 reg_addr;
u32 phy_temp;
u32 reg_temp;
+ u32 reg_temp_w = (reg & 0xfffc) >> 1;
int ret;
if (priv->model == AG7XXX_MODEL_AG933X ||
priv->model == AG7XXX_MODEL_AG953X) {
phy_addr = 0x1f;
reg_addr = 0x10;
- } else if (priv->model == AG7XXX_MODEL_AG934X) {
+ } else if (priv->model == AG7XXX_MODEL_AG934X ||
+ priv->model == AG7XXX_MODEL_AG956X) {
phy_addr = 0x18;
reg_addr = 0x00;
} else
return -EINVAL;
- ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
+ if (priv->model == AG7XXX_MODEL_AG956X)
+ ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) &
0x1ff);
+ else
+ ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
if (ret)
return ret;
- phy_temp = ((reg >> 6) & 0x7) | 0x10;
- reg_temp = (reg >> 1) & 0x1e;
+ if (priv->model == AG7XXX_MODEL_AG956X) {
+ reg_temp = (reg_temp_w + 1) & 0x1f;
+ phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
+ } else {
+ phy_temp = ((reg >> 6) & 0x7) | 0x10;
+ reg_temp = (reg >> 1) & 0x1e;
+ }
/*
* The switch on AR933x has some special register behavior, which
@@ -296,10 +322,18 @@ static int ag7xxx_switch_reg_write(struct mii_dev *bus,
int reg, u32 val)
if (ret < 0)
return ret;
} else {
- ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >>
16);
+ if (priv->model == AG7XXX_MODEL_AG956X)
+ ret = ag7xxx_switch_write(bus, phy_temp, reg_temp, val
>> 16);
+ else
+ ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1,
val >> 16);
if (ret <
[U-Boot] [U-Boot, V5, PATCH 2/3] mips: add initial support for qca956x referenced board
From: Rosy Song
QCA9563 is CPU used on AP152 board :
Clock speed : 750 MHz ,
Arch : Mips 74Kc,
Eth : SGMII interface,
MIMO config : 3 * 3 450M,
2 * USB 2.0,
Signed-off-by: Rosy Song
Changes for v2:
- coding style cleanup
- remove ununsed flash chip in defconfig
- enable automatic icache / dcache size in defconfig
Changes for v3:
- add detailed information for qca956x in commit message
Changes for v4:
- remove pre-configured network settings in ap152.h
Changes for v5:
- coding style cleanup
---
arch/mips/dts/Makefile| 1 +
arch/mips/dts/ap152.dts | 48 ++
arch/mips/dts/qca956x.dtsi| 87
arch/mips/mach-ath79/Kconfig | 14 +
arch/mips/mach-ath79/Makefile | 1 +
.../mach-ath79/include/mach/ar71xx_regs.h | 73 +++
arch/mips/mach-ath79/include/mach/ath79.h | 3 +
arch/mips/mach-ath79/qca956x/Makefile | 5 +
arch/mips/mach-ath79/qca956x/clk.c| 419 ++
arch/mips/mach-ath79/qca956x/cpu.c| 9 +
arch/mips/mach-ath79/qca956x/ddr.c| 308 +
.../mips/mach-ath79/qca956x/qca956x-ddr-tap.S | 193
arch/mips/mach-ath79/reset.c | 271 +++
board/qca/ap152/Kconfig | 15 +
board/qca/ap152/MAINTAINERS | 6 +
board/qca/ap152/Makefile | 3 +
board/qca/ap152/ap152.c | 81
configs/ap152_defconfig | 49 ++
include/configs/ap152.h | 50 +++
19 files changed, 1636 insertions(+)
create mode 100644 arch/mips/dts/ap152.dts
create mode 100644 arch/mips/dts/qca956x.dtsi
create mode 100644 arch/mips/mach-ath79/qca956x/Makefile
create mode 100644 arch/mips/mach-ath79/qca956x/clk.c
create mode 100644 arch/mips/mach-ath79/qca956x/cpu.c
create mode 100644 arch/mips/mach-ath79/qca956x/ddr.c
create mode 100644 arch/mips/mach-ath79/qca956x/qca956x-ddr-tap.S
create mode 100644 board/qca/ap152/Kconfig
create mode 100644 board/qca/ap152/MAINTAINERS
create mode 100644 board/qca/ap152/Makefile
create mode 100644 board/qca/ap152/ap152.c
create mode 100644 configs/ap152_defconfig
create mode 100644 include/configs/ap152.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index b94b582837..621c35f0ef 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -2,6 +2,7 @@
dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
+dtb-$(CONFIG_TARGET_AP152) += ap152.dtb
dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
diff --git a/arch/mips/dts/ap152.dts b/arch/mips/dts/ap152.dts
new file mode 100644
index 00..1722290c73
--- /dev/null
+++ b/arch/mips/dts/ap152.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Rosy Song
+ */
+
+/dts-v1/;
+#include "qca956x.dtsi"
+
+/ {
+ model = "AP152 Reference Board";
+ compatible = "qca,ap152", "qca,qca956x";
+
+ aliases {
+ spi0 =
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+ {
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+ {
+ clock-frequency = <2500>;
+};
+
+ {
+ clock-frequency = <2500>;
+ status = "okay";
+};
+
+ {
+ spi-max-frequency = <2500>;
+ status = "okay";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ memory-map = <0x9f00 0x0100>;
+ spi-max-frequency = <2500>;
+ reg = <0>;
+ };
+};
diff --git a/arch/mips/dts/qca956x.dtsi b/arch/mips/dts/qca956x.dtsi
new file mode 100644
index 00..6cb360b3f8
--- /dev/null
+++ b/arch/mips/dts/qca956x.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Rosy Song
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "qca,qca956x";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "mips,mips74Kc";
+ reg = <0>;
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ xtal: xtal {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-output-names = "xtal";
+ };
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ ranges;
+
+ #address-cells = <1>;
+
[U-Boot] [U-Boot, V5, PATCH 1/3] mips: fix erros on registers macros of pll-ddr-config1-nfrac for QCA956X
From: Rosy Song See details in chapter 8.6.2 and 8.6.4 (page 140-141) of qca9563 datasheet, NFRAC[17:0] So the mask of [17:5] is 0x1fff not 0x3fff. Signed-off-by: Rosy Song Changes for v2-v3: - add more information for this commit Changes for v4-v5: - coding style cleanup --- arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h index 5d371bb582..3506ed1da4 100644 --- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -528,7 +528,7 @@ #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 -#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff #define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 #define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff @@ -540,7 +540,7 @@ #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 -#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff #define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 #define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [U-Boot, V4, PATCH 1/1] mips: add initial support for qca956x referenced board
From: Rosy Song
QCA9563 is CPU used on AP152 board :
Clock speed : 750 MHz ,
Arch : Mips 74Kc,
Eth : SGMII interface,
MIMO config : 3 * 3 450M,
2 * USB 2.0,
Signed-off-by: Rosy Song
Changes for v2:
- coding Style cleanup
- remove ununsed flash chip in defconfig
- enable automatic icache / dcache size in defconfig
Changes for v3:
- add detailed information for qca956x in commit message
Changes for v4:
- remove pre-configured network settings in ap152.h
---
arch/mips/dts/Makefile| 1 +
arch/mips/dts/ap152.dts | 48 ++
arch/mips/dts/qca956x.dtsi| 87
arch/mips/mach-ath79/Kconfig | 14 +
arch/mips/mach-ath79/Makefile | 1 +
.../mach-ath79/include/mach/ar71xx_regs.h | 73 +++
arch/mips/mach-ath79/include/mach/ath79.h | 3 +
arch/mips/mach-ath79/qca956x/Makefile | 5 +
arch/mips/mach-ath79/qca956x/clk.c| 419 ++
arch/mips/mach-ath79/qca956x/cpu.c| 9 +
arch/mips/mach-ath79/qca956x/ddr.c| 308 +
.../mips/mach-ath79/qca956x/qca956x-ddr-tap.S | 193
arch/mips/mach-ath79/reset.c | 271 +++
board/qca/ap152/Kconfig | 15 +
board/qca/ap152/MAINTAINERS | 6 +
board/qca/ap152/Makefile | 3 +
board/qca/ap152/ap152.c | 81
configs/ap152_defconfig | 49 ++
include/configs/ap152.h | 50 +++
19 files changed, 1636 insertions(+)
create mode 100644 arch/mips/dts/ap152.dts
create mode 100644 arch/mips/dts/qca956x.dtsi
create mode 100644 arch/mips/mach-ath79/qca956x/Makefile
create mode 100644 arch/mips/mach-ath79/qca956x/clk.c
create mode 100644 arch/mips/mach-ath79/qca956x/cpu.c
create mode 100644 arch/mips/mach-ath79/qca956x/ddr.c
create mode 100644 arch/mips/mach-ath79/qca956x/qca956x-ddr-tap.S
create mode 100644 board/qca/ap152/Kconfig
create mode 100644 board/qca/ap152/MAINTAINERS
create mode 100644 board/qca/ap152/Makefile
create mode 100644 board/qca/ap152/ap152.c
create mode 100644 configs/ap152_defconfig
create mode 100644 include/configs/ap152.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index b94b582837..621c35f0ef 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -2,6 +2,7 @@
dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
+dtb-$(CONFIG_TARGET_AP152) += ap152.dtb
dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
diff --git a/arch/mips/dts/ap152.dts b/arch/mips/dts/ap152.dts
new file mode 100644
index 00..1722290c73
--- /dev/null
+++ b/arch/mips/dts/ap152.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Rosy Song
+ */
+
+/dts-v1/;
+#include "qca956x.dtsi"
+
+/ {
+ model = "AP152 Reference Board";
+ compatible = "qca,ap152", "qca,qca956x";
+
+ aliases {
+ spi0 =
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+ {
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+ {
+ clock-frequency = <2500>;
+};
+
+ {
+ clock-frequency = <2500>;
+ status = "okay";
+};
+
+ {
+ spi-max-frequency = <2500>;
+ status = "okay";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ memory-map = <0x9f00 0x0100>;
+ spi-max-frequency = <2500>;
+ reg = <0>;
+ };
+};
diff --git a/arch/mips/dts/qca956x.dtsi b/arch/mips/dts/qca956x.dtsi
new file mode 100644
index 00..6cb360b3f8
--- /dev/null
+++ b/arch/mips/dts/qca956x.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Rosy Song
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "qca,qca956x";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "mips,mips74Kc";
+ reg = <0>;
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ xtal: xtal {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-output-names = "xtal";
+ };
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ ranges;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+
[U-Boot] [U-Boot, V3, PATCH 3/3] mips: fix erros on registers macros of pll-ddr-config1-nfrac for QCA956X
From: Rosy Song See details in chapter 8.6.2 and 8.6.4 (page 140-141) of qca9563 datasheet, NFRAC[17:0] So the mask of [17:5] is 0x1fff not 0x3fff. Signed-off-by: Rosy Song Changes for v2-v3: - add more information for this commit --- arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h index 7cd16b8d81..5888f6eb28 100644 --- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -554,7 +554,7 @@ #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 -#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff #define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 #define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff @@ -566,7 +566,7 @@ #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 -#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff #define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 #define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [U-Boot, V3, PATCH 2/3] mips: add initial support for qca956x referenced board
From: Rosy Song
QCA9563 is CPU used on AP152 board :
Clock speed : 750 MHz ,
Arch : Mips 74Kc,
Eth : SGMII interface,
MIMO config : 3 * 3 450M,
2 * USB 2.0,
Signed-off-by: Rosy Song
Changes for v2:
- coding Style cleanup
- remove ununsed flash chip in defconfig
- enable automatic icache / dcache size in defconfig
Changes for v3:
- add detailed information for qca956x in commit message
---
arch/mips/dts/Makefile| 1 +
arch/mips/dts/ap152.dts | 48 ++
arch/mips/dts/qca956x.dtsi| 87
arch/mips/mach-ath79/Kconfig | 14 +
arch/mips/mach-ath79/Makefile | 1 +
.../mach-ath79/include/mach/ar71xx_regs.h | 73 +++
arch/mips/mach-ath79/include/mach/ath79.h | 3 +
arch/mips/mach-ath79/qca956x/Makefile | 5 +
arch/mips/mach-ath79/qca956x/clk.c| 419 ++
arch/mips/mach-ath79/qca956x/cpu.c| 9 +
arch/mips/mach-ath79/qca956x/ddr.c| 308 +
.../mips/mach-ath79/qca956x/qca956x-ddr-tap.S | 193
arch/mips/mach-ath79/reset.c | 271 +++
board/qca/ap152/Kconfig | 15 +
board/qca/ap152/MAINTAINERS | 6 +
board/qca/ap152/Makefile | 3 +
board/qca/ap152/ap152.c | 81
configs/ap152_defconfig | 49 ++
include/configs/ap152.h | 54 +++
19 files changed, 1640 insertions(+)
create mode 100644 arch/mips/dts/ap152.dts
create mode 100644 arch/mips/dts/qca956x.dtsi
create mode 100644 arch/mips/mach-ath79/qca956x/Makefile
create mode 100644 arch/mips/mach-ath79/qca956x/clk.c
create mode 100644 arch/mips/mach-ath79/qca956x/cpu.c
create mode 100644 arch/mips/mach-ath79/qca956x/ddr.c
create mode 100644 arch/mips/mach-ath79/qca956x/qca956x-ddr-tap.S
create mode 100644 board/qca/ap152/Kconfig
create mode 100644 board/qca/ap152/MAINTAINERS
create mode 100644 board/qca/ap152/Makefile
create mode 100644 board/qca/ap152/ap152.c
create mode 100644 configs/ap152_defconfig
create mode 100644 include/configs/ap152.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index b94b582837..621c35f0ef 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -2,6 +2,7 @@
dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
+dtb-$(CONFIG_TARGET_AP152) += ap152.dtb
dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
diff --git a/arch/mips/dts/ap152.dts b/arch/mips/dts/ap152.dts
new file mode 100644
index 00..1722290c73
--- /dev/null
+++ b/arch/mips/dts/ap152.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Rosy Song
+ */
+
+/dts-v1/;
+#include "qca956x.dtsi"
+
+/ {
+ model = "AP152 Reference Board";
+ compatible = "qca,ap152", "qca,qca956x";
+
+ aliases {
+ spi0 =
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+ {
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+ {
+ clock-frequency = <2500>;
+};
+
+ {
+ clock-frequency = <2500>;
+ status = "okay";
+};
+
+ {
+ spi-max-frequency = <2500>;
+ status = "okay";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ memory-map = <0x9f00 0x0100>;
+ spi-max-frequency = <2500>;
+ reg = <0>;
+ };
+};
diff --git a/arch/mips/dts/qca956x.dtsi b/arch/mips/dts/qca956x.dtsi
new file mode 100644
index 00..6cb360b3f8
--- /dev/null
+++ b/arch/mips/dts/qca956x.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Rosy Song
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "qca,qca956x";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "mips,mips74Kc";
+ reg = <0>;
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ xtal: xtal {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-output-names = "xtal";
+ };
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ ranges;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ apb {
+ compatible = "simple-bus";
+
[U-Boot] [U-Boot, V3, PATCH 1/3] ag7xxx: add initial support for s17
From: Rosy Song
S17 ethernet support is for QCA8337N, which used on
AP152 (QCA9563) board. It is a 7 ports GbE switch.
Signed-off-by: Rosy Song
Changes for v2-v3:
- add more commit message for s17
---
drivers/net/ag7xxx.c | 140 ++-
1 file changed, 124 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ag7xxx.c b/drivers/net/ag7xxx.c
index 403eb64895..b3b53205fa 100644
--- a/drivers/net/ag7xxx.c
+++ b/drivers/net/ag7xxx.c
@@ -3,6 +3,7 @@
* Atheros AR71xx / AR9xxx GMAC driver
*
* Copyright (C) 2016 Marek Vasut
+ * Copyright (C) 2019 Rosy Song
*/
#include
@@ -23,7 +24,8 @@ DECLARE_GLOBAL_DATA_PTR;
enum ag7xxx_model {
AG7XXX_MODEL_AG933X,
AG7XXX_MODEL_AG934X,
- AG7XXX_MODEL_AG953X
+ AG7XXX_MODEL_AG953X,
+ AG7XXX_MODEL_AG956X
};
/* MAC Configuration 1 */
@@ -219,6 +221,7 @@ static int ag7xxx_switch_reg_read(struct mii_dev *bus, int
reg, u32 *val)
u32 reg_addr;
u32 phy_temp;
u32 reg_temp;
+ u32 reg_temp_w = (reg & 0xfffc) >> 1;
u16 rv = 0;
int ret;
@@ -226,18 +229,25 @@ static int ag7xxx_switch_reg_read(struct mii_dev *bus,
int reg, u32 *val)
priv->model == AG7XXX_MODEL_AG953X) {
phy_addr = 0x1f;
reg_addr = 0x10;
- } else if (priv->model == AG7XXX_MODEL_AG934X) {
+ } else if (priv->model == AG7XXX_MODEL_AG934X ||
+ priv->model == AG7XXX_MODEL_AG956X) {
phy_addr = 0x18;
reg_addr = 0x00;
} else
return -EINVAL;
- ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
+ if (priv->model == AG7XXX_MODEL_AG956X) {
+ ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) &
0x1ff);
+ } else
+ ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
if (ret)
return ret;
phy_temp = ((reg >> 6) & 0x7) | 0x10;
- reg_temp = (reg >> 1) & 0x1e;
+ if (priv->model == AG7XXX_MODEL_AG956X)
+ reg_temp = reg_temp_w & 0x1f;
+ else
+ reg_temp = (reg >> 1) & 0x1e;
*val = 0;
ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, );
@@ -245,7 +255,13 @@ static int ag7xxx_switch_reg_read(struct mii_dev *bus, int
reg, u32 *val)
return ret;
*val |= rv;
- ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, );
+ if (priv->model == AG7XXX_MODEL_AG956X) {
+ phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
+ reg_temp = (reg_temp_w + 1) & 0x1f;
+ ret = ag7xxx_switch_read(bus, phy_temp, reg_temp, );
+ } else {
+ ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, );
+ }
if (ret < 0)
return ret;
*val |= (rv << 16);
@@ -260,24 +276,35 @@ static int ag7xxx_switch_reg_write(struct mii_dev *bus,
int reg, u32 val)
u32 reg_addr;
u32 phy_temp;
u32 reg_temp;
+ u32 reg_temp_w = (reg & 0xfffc) >> 1;
int ret;
if (priv->model == AG7XXX_MODEL_AG933X ||
priv->model == AG7XXX_MODEL_AG953X) {
phy_addr = 0x1f;
reg_addr = 0x10;
- } else if (priv->model == AG7XXX_MODEL_AG934X) {
+ } else if (priv->model == AG7XXX_MODEL_AG934X ||
+ priv->model == AG7XXX_MODEL_AG956X) {
phy_addr = 0x18;
reg_addr = 0x00;
} else
return -EINVAL;
- ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
+ if (priv->model == AG7XXX_MODEL_AG956X)
+ ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) &
0x1ff);
+ else
+ ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
if (ret)
return ret;
- phy_temp = ((reg >> 6) & 0x7) | 0x10;
- reg_temp = (reg >> 1) & 0x1e;
+
+ if (priv->model == AG7XXX_MODEL_AG956X) {
+ reg_temp = (reg_temp_w + 1) & 0x1f;
+ phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
+ } else {
+ phy_temp = ((reg >> 6) & 0x7) | 0x10;
+ reg_temp = (reg >> 1) & 0x1e;
+ }
/*
* The switch on AR933x has some special register behavior, which
@@ -296,10 +323,18 @@ static int ag7xxx_switch_reg_write(struct mii_dev *bus,
int reg, u32 val)
if (ret < 0)
return ret;
} else {
- ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >>
16);
+ if (priv->model == AG7XXX_MODEL_AG956X) {
+ ret = ag7xxx_switch_write(bus, phy_temp, reg_temp, val
>> 16);
+ } else
+ ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1,
val >> 16);
if (ret < 0)
return
[U-Boot] [PATCH 1/3] ag7xxx: add initial support for s17
From: Rosy Song
S17 ethernet support is for QCA8337N, which used on
AP152 (QCA9563) board. It is a 7 ports GbE switch.
Signed-off-by: Rosy Song
Changes for v2-v3:
- add more commit message for s17
---
drivers/net/ag7xxx.c | 140 ++-
1 file changed, 124 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ag7xxx.c b/drivers/net/ag7xxx.c
index 403eb64895..b3b53205fa 100644
--- a/drivers/net/ag7xxx.c
+++ b/drivers/net/ag7xxx.c
@@ -3,6 +3,7 @@
* Atheros AR71xx / AR9xxx GMAC driver
*
* Copyright (C) 2016 Marek Vasut
+ * Copyright (C) 2019 Rosy Song
*/
#include
@@ -23,7 +24,8 @@ DECLARE_GLOBAL_DATA_PTR;
enum ag7xxx_model {
AG7XXX_MODEL_AG933X,
AG7XXX_MODEL_AG934X,
- AG7XXX_MODEL_AG953X
+ AG7XXX_MODEL_AG953X,
+ AG7XXX_MODEL_AG956X
};
/* MAC Configuration 1 */
@@ -219,6 +221,7 @@ static int ag7xxx_switch_reg_read(struct mii_dev *bus, int
reg, u32 *val)
u32 reg_addr;
u32 phy_temp;
u32 reg_temp;
+ u32 reg_temp_w = (reg & 0xfffc) >> 1;
u16 rv = 0;
int ret;
@@ -226,18 +229,25 @@ static int ag7xxx_switch_reg_read(struct mii_dev *bus,
int reg, u32 *val)
priv->model == AG7XXX_MODEL_AG953X) {
phy_addr = 0x1f;
reg_addr = 0x10;
- } else if (priv->model == AG7XXX_MODEL_AG934X) {
+ } else if (priv->model == AG7XXX_MODEL_AG934X ||
+ priv->model == AG7XXX_MODEL_AG956X) {
phy_addr = 0x18;
reg_addr = 0x00;
} else
return -EINVAL;
- ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
+ if (priv->model == AG7XXX_MODEL_AG956X) {
+ ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) &
0x1ff);
+ } else
+ ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
if (ret)
return ret;
phy_temp = ((reg >> 6) & 0x7) | 0x10;
- reg_temp = (reg >> 1) & 0x1e;
+ if (priv->model == AG7XXX_MODEL_AG956X)
+ reg_temp = reg_temp_w & 0x1f;
+ else
+ reg_temp = (reg >> 1) & 0x1e;
*val = 0;
ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, );
@@ -245,7 +255,13 @@ static int ag7xxx_switch_reg_read(struct mii_dev *bus, int
reg, u32 *val)
return ret;
*val |= rv;
- ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, );
+ if (priv->model == AG7XXX_MODEL_AG956X) {
+ phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
+ reg_temp = (reg_temp_w + 1) & 0x1f;
+ ret = ag7xxx_switch_read(bus, phy_temp, reg_temp, );
+ } else {
+ ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, );
+ }
if (ret < 0)
return ret;
*val |= (rv << 16);
@@ -260,24 +276,35 @@ static int ag7xxx_switch_reg_write(struct mii_dev *bus,
int reg, u32 val)
u32 reg_addr;
u32 phy_temp;
u32 reg_temp;
+ u32 reg_temp_w = (reg & 0xfffc) >> 1;
int ret;
if (priv->model == AG7XXX_MODEL_AG933X ||
priv->model == AG7XXX_MODEL_AG953X) {
phy_addr = 0x1f;
reg_addr = 0x10;
- } else if (priv->model == AG7XXX_MODEL_AG934X) {
+ } else if (priv->model == AG7XXX_MODEL_AG934X ||
+ priv->model == AG7XXX_MODEL_AG956X) {
phy_addr = 0x18;
reg_addr = 0x00;
} else
return -EINVAL;
- ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
+ if (priv->model == AG7XXX_MODEL_AG956X)
+ ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) &
0x1ff);
+ else
+ ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
if (ret)
return ret;
- phy_temp = ((reg >> 6) & 0x7) | 0x10;
- reg_temp = (reg >> 1) & 0x1e;
+
+ if (priv->model == AG7XXX_MODEL_AG956X) {
+ reg_temp = (reg_temp_w + 1) & 0x1f;
+ phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
+ } else {
+ phy_temp = ((reg >> 6) & 0x7) | 0x10;
+ reg_temp = (reg >> 1) & 0x1e;
+ }
/*
* The switch on AR933x has some special register behavior, which
@@ -296,10 +323,18 @@ static int ag7xxx_switch_reg_write(struct mii_dev *bus,
int reg, u32 val)
if (ret < 0)
return ret;
} else {
- ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >>
16);
+ if (priv->model == AG7XXX_MODEL_AG956X) {
+ ret = ag7xxx_switch_write(bus, phy_temp, reg_temp, val
>> 16);
+ } else
+ ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1,
val >> 16);
if (ret < 0)
return
[U-Boot] [U-Boot, V2, PATCH 3/3] mips: fix erros on registers macros of pll-ddr-config1-nfrac for QCA956X
From: Rosy Song See details in chapter 8.6.2 and 8.6.4 (page 140-141) of qca9563 datasheet, NFRAC[17:0] So the mask of [17:5] is 0x1fff not 0x3fff. Signed-off-by: Rosy Song --- arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h index 7cd16b8d81..5888f6eb28 100644 --- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -554,7 +554,7 @@ #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 -#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff #define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 #define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff @@ -566,7 +566,7 @@ #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 -#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff #define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 #define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [U-Boot, V2, PATCH 2/3] mips: add initial support for qca956x referenced board
From: Rosy Song
Signed-off-by: Rosy Song
---
arch/mips/dts/Makefile| 1 +
arch/mips/dts/ap152.dts | 48 ++
arch/mips/dts/qca956x.dtsi| 87
arch/mips/mach-ath79/Kconfig | 14 +
arch/mips/mach-ath79/Makefile | 1 +
.../mach-ath79/include/mach/ar71xx_regs.h | 73 +++
arch/mips/mach-ath79/include/mach/ath79.h | 3 +
arch/mips/mach-ath79/qca956x/Makefile | 5 +
arch/mips/mach-ath79/qca956x/clk.c| 419 ++
arch/mips/mach-ath79/qca956x/cpu.c| 9 +
arch/mips/mach-ath79/qca956x/ddr.c| 308 +
.../mips/mach-ath79/qca956x/qca956x-ddr-tap.S | 193
arch/mips/mach-ath79/reset.c | 271 +++
board/qca/ap152/Kconfig | 15 +
board/qca/ap152/MAINTAINERS | 6 +
board/qca/ap152/Makefile | 3 +
board/qca/ap152/ap152.c | 81
configs/ap152_defconfig | 49 ++
include/configs/ap152.h | 54 +++
19 files changed, 1640 insertions(+)
create mode 100644 arch/mips/dts/ap152.dts
create mode 100644 arch/mips/dts/qca956x.dtsi
create mode 100644 arch/mips/mach-ath79/qca956x/Makefile
create mode 100644 arch/mips/mach-ath79/qca956x/clk.c
create mode 100644 arch/mips/mach-ath79/qca956x/cpu.c
create mode 100644 arch/mips/mach-ath79/qca956x/ddr.c
create mode 100644 arch/mips/mach-ath79/qca956x/qca956x-ddr-tap.S
create mode 100644 board/qca/ap152/Kconfig
create mode 100644 board/qca/ap152/MAINTAINERS
create mode 100644 board/qca/ap152/Makefile
create mode 100644 board/qca/ap152/ap152.c
create mode 100644 configs/ap152_defconfig
create mode 100644 include/configs/ap152.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index b94b582837..621c35f0ef 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -2,6 +2,7 @@
dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
+dtb-$(CONFIG_TARGET_AP152) += ap152.dtb
dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
diff --git a/arch/mips/dts/ap152.dts b/arch/mips/dts/ap152.dts
new file mode 100644
index 00..1722290c73
--- /dev/null
+++ b/arch/mips/dts/ap152.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Rosy Song
+ */
+
+/dts-v1/;
+#include "qca956x.dtsi"
+
+/ {
+ model = "AP152 Reference Board";
+ compatible = "qca,ap152", "qca,qca956x";
+
+ aliases {
+ spi0 =
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+ {
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+ {
+ clock-frequency = <2500>;
+};
+
+ {
+ clock-frequency = <2500>;
+ status = "okay";
+};
+
+ {
+ spi-max-frequency = <2500>;
+ status = "okay";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ memory-map = <0x9f00 0x0100>;
+ spi-max-frequency = <2500>;
+ reg = <0>;
+ };
+};
diff --git a/arch/mips/dts/qca956x.dtsi b/arch/mips/dts/qca956x.dtsi
new file mode 100644
index 00..6cb360b3f8
--- /dev/null
+++ b/arch/mips/dts/qca956x.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Rosy Song
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "qca,qca956x";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "mips,mips74Kc";
+ reg = <0>;
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ xtal: xtal {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-output-names = "xtal";
+ };
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ ranges;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ apb {
+ compatible = "simple-bus";
+ ranges;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart@1802 {
+ compatible = "ns16550";
+ reg = <0x1802 0x20>;
+ reg-shift = <2>;
+
+ status = "disabled";
+
[U-Boot] [U-Boot, V2, PATCH 1/3] ag7xxx: add initial support for s17
From: Rosy Song
Signed-off-by: Rosy Song
---
drivers/net/ag7xxx.c | 140 ++-
1 file changed, 124 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ag7xxx.c b/drivers/net/ag7xxx.c
index 403eb64895..b3b53205fa 100644
--- a/drivers/net/ag7xxx.c
+++ b/drivers/net/ag7xxx.c
@@ -3,6 +3,7 @@
* Atheros AR71xx / AR9xxx GMAC driver
*
* Copyright (C) 2016 Marek Vasut
+ * Copyright (C) 2019 Rosy Song
*/
#include
@@ -23,7 +24,8 @@ DECLARE_GLOBAL_DATA_PTR;
enum ag7xxx_model {
AG7XXX_MODEL_AG933X,
AG7XXX_MODEL_AG934X,
- AG7XXX_MODEL_AG953X
+ AG7XXX_MODEL_AG953X,
+ AG7XXX_MODEL_AG956X
};
/* MAC Configuration 1 */
@@ -219,6 +221,7 @@ static int ag7xxx_switch_reg_read(struct mii_dev *bus, int
reg, u32 *val)
u32 reg_addr;
u32 phy_temp;
u32 reg_temp;
+ u32 reg_temp_w = (reg & 0xfffc) >> 1;
u16 rv = 0;
int ret;
@@ -226,18 +229,25 @@ static int ag7xxx_switch_reg_read(struct mii_dev *bus,
int reg, u32 *val)
priv->model == AG7XXX_MODEL_AG953X) {
phy_addr = 0x1f;
reg_addr = 0x10;
- } else if (priv->model == AG7XXX_MODEL_AG934X) {
+ } else if (priv->model == AG7XXX_MODEL_AG934X ||
+ priv->model == AG7XXX_MODEL_AG956X) {
phy_addr = 0x18;
reg_addr = 0x00;
} else
return -EINVAL;
- ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
+ if (priv->model == AG7XXX_MODEL_AG956X) {
+ ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) &
0x1ff);
+ } else
+ ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
if (ret)
return ret;
phy_temp = ((reg >> 6) & 0x7) | 0x10;
- reg_temp = (reg >> 1) & 0x1e;
+ if (priv->model == AG7XXX_MODEL_AG956X)
+ reg_temp = reg_temp_w & 0x1f;
+ else
+ reg_temp = (reg >> 1) & 0x1e;
*val = 0;
ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, );
@@ -245,7 +255,13 @@ static int ag7xxx_switch_reg_read(struct mii_dev *bus, int
reg, u32 *val)
return ret;
*val |= rv;
- ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, );
+ if (priv->model == AG7XXX_MODEL_AG956X) {
+ phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
+ reg_temp = (reg_temp_w + 1) & 0x1f;
+ ret = ag7xxx_switch_read(bus, phy_temp, reg_temp, );
+ } else {
+ ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, );
+ }
if (ret < 0)
return ret;
*val |= (rv << 16);
@@ -260,24 +276,35 @@ static int ag7xxx_switch_reg_write(struct mii_dev *bus,
int reg, u32 val)
u32 reg_addr;
u32 phy_temp;
u32 reg_temp;
+ u32 reg_temp_w = (reg & 0xfffc) >> 1;
int ret;
if (priv->model == AG7XXX_MODEL_AG933X ||
priv->model == AG7XXX_MODEL_AG953X) {
phy_addr = 0x1f;
reg_addr = 0x10;
- } else if (priv->model == AG7XXX_MODEL_AG934X) {
+ } else if (priv->model == AG7XXX_MODEL_AG934X ||
+ priv->model == AG7XXX_MODEL_AG956X) {
phy_addr = 0x18;
reg_addr = 0x00;
} else
return -EINVAL;
- ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
+ if (priv->model == AG7XXX_MODEL_AG956X)
+ ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) &
0x1ff);
+ else
+ ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
if (ret)
return ret;
- phy_temp = ((reg >> 6) & 0x7) | 0x10;
- reg_temp = (reg >> 1) & 0x1e;
+
+ if (priv->model == AG7XXX_MODEL_AG956X) {
+ reg_temp = (reg_temp_w + 1) & 0x1f;
+ phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
+ } else {
+ phy_temp = ((reg >> 6) & 0x7) | 0x10;
+ reg_temp = (reg >> 1) & 0x1e;
+ }
/*
* The switch on AR933x has some special register behavior, which
@@ -296,10 +323,18 @@ static int ag7xxx_switch_reg_write(struct mii_dev *bus,
int reg, u32 val)
if (ret < 0)
return ret;
} else {
- ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >>
16);
+ if (priv->model == AG7XXX_MODEL_AG956X) {
+ ret = ag7xxx_switch_write(bus, phy_temp, reg_temp, val
>> 16);
+ } else
+ ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1,
val >> 16);
if (ret < 0)
return ret;
+ if (priv->model == AG7XXX_MODEL_AG956X) {
+ phy_temp = ((reg_temp_w >> 5) & 0x7) | 0x10;
+
[U-Boot] None
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