[U-Boot] [PATCH] [resend] net: fman: fix 2.5G SGMII settings

[shh.xie]

From: Shaohui Xie 

The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in
set_if_mode(), and the serdes PCS configuration are wrong, this patch uses
the correct settings took from Linux.

Signed-off-by: Shaohui Xie 
---
not sure what was wrong, the patch did not show in patchwork, so resend it.
Sorry for the bothering.

 drivers/net/fm/eth.c   | 32 ++--
 drivers/net/fm/memac.c |  1 +
 include/fsl_memac.h|  1 +
 3 files changed, 24 insertions(+), 10 deletions(-)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index eb8e936..543aaa8 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -45,9 +45,11 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
 
 qsgmii_loop:
/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
-   value = PHY_SGMII_IF_MODE_SGMII;
-   if (!sgmii_2500)
-   value |= PHY_SGMII_IF_MODE_AN;
+   value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
+   if (sgmii_2500)
+   value = PHY_SGMII_CR_PHY_RESET |
+   PHY_SGMII_IF_SPEED_GIGABIT |
+   PHY_SGMII_IF_MODE_SGMII;
 
memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x14, value);
 
@@ -55,15 +57,24 @@ qsgmii_loop:
value = PHY_SGMII_DEV_ABILITY_SGMII;
memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x4, value);
 
-   /* Adjust link timer for SGMII  -
-   1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
-   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x13, 0x3);
-   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x12, 0xd40);
+   if (sgmii_2500) {
+   /* Adjust link timer for 2.5G SGMII,
+* 1.6 ms in units of 3.2 ns:
+* 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
+*/
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
+   } else {
+   /* Adjust link timer for SGMII,
+* 1.6 ms in units of 8 ns:
+* 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
+*/
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x13, 0x3);
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x12, 0xd40);
+   }
 
/* Restart AN */
-   value = PHY_SGMII_CR_DEF_VAL;
-   if (!sgmii_2500)
-   value |= PHY_SGMII_CR_RESET_AN;
+   value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
memac_mdio_write(, i, MDIO_DEVAD_NONE, 0, value);
 
if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
@@ -391,6 +402,7 @@ static int fm_eth_startup(struct fm_eth *fm_eth)
 
/* For some reason we need to set SPEED_100 */
if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
+(fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
 (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
  mac->set_if_mode)
mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index 81a64bf..1b5779c 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -90,6 +90,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac,
if_mode |= (IF_MODE_GMII | IF_MODE_RM);
break;
case PHY_INTERFACE_MODE_SGMII:
+   case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_QSGMII:
if_mode &= ~IF_MODE_MASK;
if_mode |= (IF_MODE_GMII);
diff --git a/include/fsl_memac.h b/include/fsl_memac.h
index bed2a40..431c2a0 100644
--- a/include/fsl_memac.h
+++ b/include/fsl_memac.h
@@ -226,6 +226,7 @@ struct memac {
 #define PHY_SGMII_CR_PHY_RESET  0x8000
 #define PHY_SGMII_CR_RESET_AN   0x0200
 #define PHY_SGMII_CR_DEF_VAL0x1140
+#define PHY_SGMII_IF_SPEED_GIGABIT  0x0008
 #define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
 #define PHY_SGMII_IF_MODE_AN0x0002
 #define PHY_SGMII_IF_MODE_SGMII 0x0001
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] net: fman: fix 2.5G SGMII settings

[shh.xie]

From: Shaohui Xie 

The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in
set_if_mode(), and the serdes PCS configuration are wrong, this patch uses
the correct settings took from Linux.

Signed-off-by: Shaohui Xie 
---
 drivers/net/fm/eth.c   | 32 ++--
 drivers/net/fm/memac.c |  1 +
 include/fsl_memac.h|  1 +
 3 files changed, 24 insertions(+), 10 deletions(-)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index eb8e936..543aaa8 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -45,9 +45,11 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
 
 qsgmii_loop:
/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
-   value = PHY_SGMII_IF_MODE_SGMII;
-   if (!sgmii_2500)
-   value |= PHY_SGMII_IF_MODE_AN;
+   value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
+   if (sgmii_2500)
+   value = PHY_SGMII_CR_PHY_RESET |
+   PHY_SGMII_IF_SPEED_GIGABIT |
+   PHY_SGMII_IF_MODE_SGMII;
 
memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x14, value);
 
@@ -55,15 +57,24 @@ qsgmii_loop:
value = PHY_SGMII_DEV_ABILITY_SGMII;
memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x4, value);
 
-   /* Adjust link timer for SGMII  -
-   1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
-   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x13, 0x3);
-   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x12, 0xd40);
+   if (sgmii_2500) {
+   /* Adjust link timer for 2.5G SGMII,
+* 1.6 ms in units of 3.2 ns:
+* 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
+*/
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
+   } else {
+   /* Adjust link timer for SGMII,
+* 1.6 ms in units of 8 ns:
+* 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
+*/
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x13, 0x3);
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x12, 0xd40);
+   }
 
/* Restart AN */
-   value = PHY_SGMII_CR_DEF_VAL;
-   if (!sgmii_2500)
-   value |= PHY_SGMII_CR_RESET_AN;
+   value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
memac_mdio_write(, i, MDIO_DEVAD_NONE, 0, value);
 
if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
@@ -391,6 +402,7 @@ static int fm_eth_startup(struct fm_eth *fm_eth)
 
/* For some reason we need to set SPEED_100 */
if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
+(fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
 (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
  mac->set_if_mode)
mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index 81a64bf..1b5779c 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -90,6 +90,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac,
if_mode |= (IF_MODE_GMII | IF_MODE_RM);
break;
case PHY_INTERFACE_MODE_SGMII:
+   case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_QSGMII:
if_mode &= ~IF_MODE_MASK;
if_mode |= (IF_MODE_GMII);
diff --git a/include/fsl_memac.h b/include/fsl_memac.h
index bed2a40..431c2a0 100644
--- a/include/fsl_memac.h
+++ b/include/fsl_memac.h
@@ -226,6 +226,7 @@ struct memac {
 #define PHY_SGMII_CR_PHY_RESET  0x8000
 #define PHY_SGMII_CR_RESET_AN   0x0200
 #define PHY_SGMII_CR_DEF_VAL0x1140
+#define PHY_SGMII_IF_SPEED_GIGABIT  0x0008
 #define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
 #define PHY_SGMII_IF_MODE_AN0x0002
 #define PHY_SGMII_IF_MODE_SGMII 0x0001
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/2][v2] armv8: ls1046aqds: add lpuart support

[shh.xie]

From: Shaohui Xie 

LPUART0 is used by default, and it's using platform clock.

Signed-off-by: Shaohui Xie 
---
changes in v2:
1. dropped CONFIG_LPUART_CLK.
2. uses CONFIG_SYS_FSL_DDR4 in defconfig.

 arch/arm/dts/Makefile   |  1 +
 arch/arm/dts/fsl-ls1046a-qds-lpuart.dts | 16 ++
 arch/arm/dts/fsl-ls1046a-qds.dtsi   |  4 +++
 arch/arm/dts/fsl-ls1046a.dtsi   | 54 +
 board/freescale/ls1046aqds/ls1046aqds.c | 18 +++
 configs/ls1046aqds_lpuart_defconfig | 30 ++
 include/configs/ls1046aqds.h|  8 +
 7 files changed, 131 insertions(+)
 create mode 100644 arch/arm/dts/fsl-ls1046a-qds-lpuart.dts
 create mode 100644 configs/ls1046aqds_lpuart_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8dbaea0..afc68e1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -148,6 +148,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
fsl-ls1046a-qds-duart.dtb \
+   fsl-ls1046a-qds-lpuart.dtb \
fsl-ls1046a-rdb.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
diff --git a/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts 
b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts
new file mode 100644
index 000..21243d0
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright (C) 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1046a-qds.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi 
b/arch/arm/dts/fsl-ls1046a-qds.dtsi
index c512293..a49ca08 100644
--- a/arch/arm/dts/fsl-ls1046a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi
@@ -75,3 +75,7 @@
  {
status = "okay";
 };
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 87dd997..359a9d1 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -151,6 +151,60 @@
clocks = < 4 0>;
};
 
+   lpuart0: serial@295 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x295 0x0 0x1000>;
+   interrupts = <0 48 0x4>;
+   clocks = < 4 0>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart1: serial@296 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x296 0x0 0x1000>;
+   interrupts = <0 49 0x4>;
+   clocks = < 4 1>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart2: serial@297 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x297 0x0 0x1000>;
+   interrupts = <0 50 0x4>;
+   clocks = < 4 1>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart3: serial@298 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x298 0x0 0x1000>;
+   interrupts = <0 51 0x4>;
+   clocks = < 4 1>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart4: serial@299 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x299 0x0 0x1000>;
+   interrupts = <0 52 0x4>;
+   clocks = < 4 1>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart5: serial@29a {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x29a 0x0 0x1000>;
+   interrupts = <0 53 0x4>;
+   clocks = < 4 1>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
qspi: quadspi@155 {
compatible = "fsl,vf610-qspi";
#address-cells = <1>;
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c 
b/board/freescale/ls1046aqds/ls1046aqds.c
index 8c18538..552365b 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -120,6 +120,13 @@ unsigned long get_board_ddr_clk(void)
return ;
 }
 
+#ifdef CONFIG_LPUART
+u32 get_lpuart_clk(void)
+{
+   return gd->bus_clk;
+}
+#endif
+
 

[U-Boot] [PATCH 1/2][v2] lpuart: add a get_lpuart_clk function

[shh.xie]

From: Shaohui Xie 

It's not always true that LPUART clock is CONFIG_SYS_CLK_FREQ, this
patch provides a weak function get_lpuart_clk, so that the clock can be
ovreride on a specific board which uses different clock for LPUART.

Signed-off-by: Shaohui Xie 
---
changes in v2:
none.

 drivers/serial/serial_lpuart.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 042e9a2..beb4243 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -170,9 +170,14 @@ static int lpuart_serial_probe(struct udevice *dev)
 }
 #else
 
+u32 __weak get_lpuart_clk(void)
+{
+   return CONFIG_SYS_CLK_FREQ;
+}
+
 static void _lpuart32_serial_setbrg(struct lpuart_fsl *base, int baudrate)
 {
-   u32 clk = CONFIG_SYS_CLK_FREQ;
+   u32 clk = get_lpuart_clk();
u32 sbr;
 
sbr = (clk / (16 * baudrate));
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8: ls2080aqds: fix SGMII repeater settings

[shh.xie]

From: Shaohui Xie 

The current value to check whether the PHY was configured has dependency
on MC, it expects MC to start PCS AN, this is not true during boot up,
so it should be changed to remove the dependency.

The PHY's register space should be restore to default after accessing
extended space.

Signed-off-by: Shaohui Xie 
---
 board/freescale/ls2080aqds/eth.c | 13 -
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index 95ff68b..cf6791e 100644
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -144,8 +144,10 @@ static void sgmii_configure_repeater(int serdes_port)
 
mdelay(10);
 
-   if ((value & 0xfff) == 0x40f) {
+   if ((value & 0xfff) == 0x401) {
printf("DPMAC %d:PHY is . Configured\n", dpmac_id);
+   miiphy_write(dev[mii_bus], riser_phy_addr[dpmac],
+0x1f, 0);
continue;
}
 
@@ -181,28 +183,29 @@ static void sgmii_configure_repeater(int serdes_port)
if (ret > 0)
goto error;
 
-   mdelay(1);
+   mdelay(100);
ret = miiphy_read(dev[mii_bus],
  riser_phy_addr[dpmac],
  0x11, );
if (ret > 0)
goto error;
-   mdelay(10);
 
-   if ((value & 0xfff) == 0x40f) {
+   if ((value & 0xfff) == 0x401) {
printf("DPMAC %d :PHY is configured ",
   dpmac_id);
printf("after setting repeater 0x%x\n",
   value);
i = 5;
j = 5;
-   } else
+   } else {
printf("DPMAC %d :PHY is failed to ",
   dpmac_id);
printf("configure the repeater 0x%x\n",
   value);
}
+   }
}
+   miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, 0);
}
 error:
if (ret)
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/2] armv8: ls1046aqds: add lpuart support

[shh.xie]

From: Shaohui Xie 

LPUART0 is used by default, and it's using platform clock, if a different
clock is preferred, user can define CONFIG_LPUART_CLK.

Signed-off-by: Shaohui Xie 
---
 arch/arm/dts/Makefile   |  1 +
 arch/arm/dts/fsl-ls1046a-qds-lpuart.dts | 16 ++
 arch/arm/dts/fsl-ls1046a-qds.dtsi   |  4 +++
 arch/arm/dts/fsl-ls1046a.dtsi   | 54 +
 board/freescale/ls1046aqds/ls1046aqds.c | 21 +
 configs/ls1046aqds_lpuart_defconfig | 29 ++
 include/configs/ls1046aqds.h|  8 +
 7 files changed, 133 insertions(+)
 create mode 100644 arch/arm/dts/fsl-ls1046a-qds-lpuart.dts
 create mode 100644 configs/ls1046aqds_lpuart_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 715e9bd..4a7d53b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -144,6 +144,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
fsl-ls1046a-qds-duart.dtb \
+   fsl-ls1046a-qds-lpuart.dtb \
fsl-ls1046a-rdb.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
diff --git a/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts 
b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts
new file mode 100644
index 000..21243d0
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright (C) 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1046a-qds.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi 
b/arch/arm/dts/fsl-ls1046a-qds.dtsi
index c512293..a49ca08 100644
--- a/arch/arm/dts/fsl-ls1046a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi
@@ -75,3 +75,7 @@
  {
status = "okay";
 };
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 87dd997..359a9d1 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -151,6 +151,60 @@
clocks = < 4 0>;
};
 
+   lpuart0: serial@295 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x295 0x0 0x1000>;
+   interrupts = <0 48 0x4>;
+   clocks = < 4 0>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart1: serial@296 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x296 0x0 0x1000>;
+   interrupts = <0 49 0x4>;
+   clocks = < 4 1>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart2: serial@297 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x297 0x0 0x1000>;
+   interrupts = <0 50 0x4>;
+   clocks = < 4 1>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart3: serial@298 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x298 0x0 0x1000>;
+   interrupts = <0 51 0x4>;
+   clocks = < 4 1>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart4: serial@299 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x299 0x0 0x1000>;
+   interrupts = <0 52 0x4>;
+   clocks = < 4 1>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart5: serial@29a {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x29a 0x0 0x1000>;
+   interrupts = <0 53 0x4>;
+   clocks = < 4 1>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
qspi: quadspi@155 {
compatible = "fsl,vf610-qspi";
#address-cells = <1>;
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c 
b/board/freescale/ls1046aqds/ls1046aqds.c
index 8c18538..96d929d 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -120,6 +120,16 @@ unsigned long get_board_ddr_clk(void)
return ;
 }
 
+#ifdef CONFIG_LPUART
+u32 get_lpuart_clk(void)
+{
+#ifdef CONFIG_LPUART_CLK
+   return 

[U-Boot] [PATCH 1/2] lpuart: add a get_lpuart_clk function

[shh.xie]

From: Shaohui Xie 

It's not always true that LPUART clock is CONFIG_SYS_CLK_FREQ, this
patch provides a weak function get_lpuart_clk, so that the clock can be
ovreride on a specific board which uses different clock for LPUART.

Signed-off-by: Shaohui Xie 
---
 drivers/serial/serial_lpuart.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 042e9a2..beb4243 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -170,9 +170,14 @@ static int lpuart_serial_probe(struct udevice *dev)
 }
 #else
 
+u32 __weak get_lpuart_clk(void)
+{
+   return CONFIG_SYS_CLK_FREQ;
+}
+
 static void _lpuart32_serial_setbrg(struct lpuart_fsl *base, int baudrate)
 {
-   u32 clk = CONFIG_SYS_CLK_FREQ;
+   u32 clk = get_lpuart_clk();
u32 sbr;
 
sbr = (clk / (16 * baudrate));
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8: ls1043aqds: fix usb PWRFAULT setting

[shh.xie]

From: Shaohui Xie 

SCFG_USBPWRFAULT_DEDICATED instead of SCFG_USBPWRFAULT_SHARED should be
used for USB 3 & 2.

Signed-off-by: Shaohui Xie 
---
 board/freescale/ls1043aqds/ls1043aqds.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c 
b/board/freescale/ls1043aqds/ls1043aqds.c
index ca393e8..7e47ef0 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -238,8 +238,8 @@ int board_early_init_f(void)
out_be32(>rcwpmuxcr0, 0x);
out_be32(>usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
usb_pwrfault =
-   (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB3_SHIFT) |
-   (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB2_SHIFT) |
+   (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
+   (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
out_be32(>usbpwrfault_selcr, usb_pwrfault);
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8: ls1043ardb: invert irq pin polarity for AQR105 PHY

[shh.xie]

From: Shaohui Xie 

To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity by
setting relative bit in SCFG_INTPCR register, because AQR105 interrupt
is low active but GIC accepts high active.

Signed-off-by: Shaohui Xie 
---
 board/freescale/ls1043ardb/ls1043ardb.c | 4 
 include/configs/ls1043ardb.h| 1 +
 2 files changed, 5 insertions(+)

diff --git a/board/freescale/ls1043ardb/ls1043ardb.c 
b/board/freescale/ls1043ardb/ls1043ardb.c
index ec5fdbf..9e9f24d 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -84,6 +84,8 @@ int board_early_init_f(void)
 int board_init(void)
 {
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+   struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
 
/*
 * Set CCI-400 control override register to enable barrier
@@ -106,6 +108,8 @@ int board_init(void)
 #ifdef CONFIG_U_QE
u_qe_init();
 #endif
+   /* invert AQR105 IRQ pins polarity */
+   out_be32(>intpcr, AQR105_IRQ_MASK);
 
return 0;
 }
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index bc40b06..bfc1a5c 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -254,6 +254,7 @@
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
 #define CONFIG_PHY_AQUANTIA
+#define AQR105_IRQ_MASK0x4000
 
 #define RGMII_PHY1_ADDR0x1
 #define RGMII_PHY2_ADDR0x2
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8: ls1043aqds: make sure fixed-link property is big endian

[shh.xie]

From: Shaohui Xie 

When setting fixed-link property to DTS, the values should be converted
with using cpu_to_fdt32 so that to have correct value on little endian
Soc.

Signed-off-by: Shaohui Xie 
---
 board/freescale/ls1043aqds/eth.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c
index 67b4afe..bf26376 100644
--- a/board/freescale/ls1043aqds/eth.c
+++ b/board/freescale/ls1043aqds/eth.c
@@ -176,9 +176,9 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, 
phys_addr_t addr,
} else if (fm_info_get_enet_if(port) ==
   PHY_INTERFACE_MODE_SGMII_2500) {
/* 2.5G SGMII interface */
-   f_link.phy_id = port;
-   f_link.duplex = 1;
-   f_link.link_speed = 1000;
+   f_link.phy_id = cpu_to_fdt32(port);
+   f_link.duplex = cpu_to_fdt32(1);
+   f_link.link_speed = cpu_to_fdt32(1000);
f_link.pause = 0;
f_link.asym_pause = 0;
/* no PHY for 2.5G SGMII */
@@ -241,9 +241,9 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, 
phys_addr_t addr,
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
   port == FM1_10GEC1) {
/* XFI interface */
-   f_link.phy_id = port;
-   f_link.duplex = 1;
-   f_link.link_speed = 1;
+   f_link.phy_id = cpu_to_fdt32(port);
+   f_link.duplex = cpu_to_fdt32(1);
+   f_link.link_speed = cpu_to_fdt32(1);
f_link.pause = 0;
f_link.asym_pause = 0;
/* no PHY for XFI */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH][v2] armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY

[shh.xie]

From: Shaohui Xie 

To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low
active but GIC accepts high active.

Signed-off-by: Shaohui Xie 
---
changes in v2:
1. move Interrupt register offset define to immap_lsch3.h.

 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 
 board/freescale/ls2080ardb/ls2080ardb.c| 4 
 include/configs/ls2080ardb.h   | 1 +
 3 files changed, 9 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index cd96604..f182dea 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -94,6 +94,10 @@
 #define DCFG_DCSR_BASE 0X70010ULL
 #define DCFG_DCSR_PORCR1   0x000
 
+/* Interrupt Sampling Control */
+#define ISC_BASE   0x01F7
+#define IRQCR_OFFSET   0x14
+
 /* Supplemental Configuration */
 #define SCFG_BASE  0x01fc
 #define SCFG_USB3PRM1CR0x000
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c 
b/board/freescale/ls2080ardb/ls2080ardb.c
index 2ae9d6c..da227a7 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -149,6 +149,7 @@ int board_init(void)
 {
char *env_hwconfig;
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+   u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
u32 val;
 
init_final_memctl_regs();
@@ -170,6 +171,9 @@ int board_init(void)
 
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 
+   /* invert AQR405 IRQ pins polarity */
+   out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
+
return 0;
 }
 
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 65d4f64..0d60420 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -336,6 +336,7 @@ unsigned long get_board_sys_clk(void);
 #define AQ_PHY_ADDR2   0x01
 #define AQ_PHY_ADDR3   0x02
 #define AQ_PHY_ADDR4   0x03
+#define AQR405_IRQ_MASK0x36
 
 #define CONFIG_MII
 #define CONFIG_ETHPRIME"DPNI1"
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/2][v2] net: phy: introduce a quirk PHY_FLAG_BROKEN_RESET

[shh.xie]

From: Shaohui Xie 

Current driver always performs a phy soft reset when connecting the phy
device, but soft reset is not always supported by a phy device, so
introduce a quirk PHY_FLAG_BROKEN_RESET to let such a phy device to skip
soft reset. This commit uses 'flags' of phy device structure to store the
quirk.

Signed-off-by: Shaohui Xie 
---
changes in v2:
1. use PHY_FLAG_BROKEN_RESET instead of PHY_BROKEN_RESET
2. use '&' to check the phydev->flags instead of '=='

 drivers/net/phy/phy.c | 3 +++
 include/phy.h | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 9bf231c..9126d5d 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -741,6 +741,9 @@ int phy_reset(struct phy_device *phydev)
int timeout = 500;
int devad = MDIO_DEVAD_NONE;
 
+   if (phydev->flags & PHY_FLAG_BROKEN_RESET)
+   return 0;
+
 #ifdef CONFIG_PHYLIB_10G
/* If it's 10G, we need to issue reset through one of the MMDs */
if (is_10g_interface(phydev->interface)) {
diff --git a/include/phy.h b/include/phy.h
index e030c9f..09bbe48 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -17,6 +17,8 @@
 
 #define PHY_MAX_ADDR 32
 
+#define PHY_FLAG_BROKEN_RESET  (1 << 0) /* soft reset not supported */
+
 #define PHY_DEFAULT_FEATURES   (SUPPORTED_Autoneg | \
 SUPPORTED_TP | \
 SUPPORTED_MII)
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/2][v2] net: phy: implements probe for Cortina phy

[shh.xie]

From: Shaohui Xie 

Cortina phy cannot support soft reset, this commit implements probe
for Cortina PHY to tell phylib to skip phy soft reset by setting
PHY_FLAG_BROKEN_RESET in flags.

Signed-off-by: Shaohui Xie 
Acked-by: Joe Hershberger 
---
changes in v2:
1. use PHY_FLAG_BROKEN_RESET instead of PHY_BROKEN_RESET

 drivers/net/phy/cortina.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
index 3a2b3bb..ba1157f 100644
--- a/drivers/net/phy/cortina.c
+++ b/drivers/net/phy/cortina.c
@@ -256,6 +256,12 @@ int cs4340_config(struct phy_device *phydev)
return 0;
 }
 
+int cs4340_probe(struct phy_device *phydev)
+{
+   phydev->flags = PHY_FLAG_BROKEN_RESET;
+   return 0;
+}
+
 int cs4340_startup(struct phy_device *phydev)
 {
phydev->link = 1;
@@ -275,6 +281,7 @@ struct phy_driver cs4340_driver = {
 MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
 MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
.config = _config,
+   .probe  = _probe,
.startup = _startup,
.shutdown = _shutdown,
 };
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY

[shh.xie]

From: Shaohui Xie 

To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low active
but GIC accepts high active.

Signed-off-by: Shaohui Xie 
---
 board/freescale/ls2080ardb/ls2080ardb.c | 4 
 include/configs/ls2080a_common.h| 4 
 include/configs/ls2080ardb.h| 1 +
 3 files changed, 9 insertions(+)

diff --git a/board/freescale/ls2080ardb/ls2080ardb.c 
b/board/freescale/ls2080ardb/ls2080ardb.c
index 2ae9d6c..da227a7 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -149,6 +149,7 @@ int board_init(void)
 {
char *env_hwconfig;
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+   u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
u32 val;
 
init_final_memctl_regs();
@@ -170,6 +171,9 @@ int board_init(void)
 
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 
+   /* invert AQR405 IRQ pins polarity */
+   out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
+
return 0;
 }
 
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 2e1fe7a..1740dd6 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -38,6 +38,10 @@
 #define CONFIG_SYS_TEXT_BASE   0x3010
 #endif
 
+/* Interrupt Sampling Control */
+#define ISC_BASE   0x01F7
+#define IRQCR_OFFSET   0x14
+
 #ifdef CONFIG_EMU
 #define CONFIG_SYS_NO_FLASH
 #endif
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 65d4f64..0d60420 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -336,6 +336,7 @@ unsigned long get_board_sys_clk(void);
 #define AQ_PHY_ADDR2   0x01
 #define AQ_PHY_ADDR3   0x02
 #define AQ_PHY_ADDR4   0x03
+#define AQR405_IRQ_MASK0x36
 
 #define CONFIG_MII
 #define CONFIG_ETHPRIME"DPNI1"
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/2] net: phy: introduce a quirk PHY_BROKEN_RESET

[shh.xie]

From: Shaohui Xie 

Current driver always performs a phy soft reset when connecting the phy
device, but soft reset is not always supported by a phy device, so
introduce a quirk PHY_BROKEN_RESET to let such a phy device to skip soft
reset. This commit uses 'flags' of phy device structure to store the
quirk.

Signed-off-by: Shaohui Xie 
---
 drivers/net/phy/phy.c | 3 +++
 include/phy.h | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 51b5746..2a36ae7 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -707,6 +707,9 @@ int phy_reset(struct phy_device *phydev)
int timeout = 500;
int devad = MDIO_DEVAD_NONE;
 
+   if (phydev->flags == PHY_BROKEN_RESET)
+   return 0;
+
 #ifdef CONFIG_PHYLIB_10G
/* If it's 10G, we need to issue reset through one of the MMDs */
if (is_10g_interface(phydev->interface)) {
diff --git a/include/phy.h b/include/phy.h
index 66cf61b..5f604a1 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -16,6 +16,7 @@
 #include 
 
 #define PHY_MAX_ADDR 32
+#define PHY_BROKEN_RESET   (1 << 0) /* soft reset not supported */
 
 #define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
 SUPPORTED_10baseT_Full | \
-- 
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[U-Boot] [PATCH 2/2] net: phy: implements probe for Cortina phy

[shh.xie]

From: Shaohui Xie 

Cortine phy cannot support soft reset, this commit implements probe
for Cortina PHY to tell phylib to skip phy soft reset by setting
PHY_BROKEN_RESET in flags.

Signed-off-by: Shaohui Xie 
---
 drivers/net/phy/cortina.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
index 3a2b3bb..2d04f62 100644
--- a/drivers/net/phy/cortina.c
+++ b/drivers/net/phy/cortina.c
@@ -256,6 +256,12 @@ int cs4340_config(struct phy_device *phydev)
return 0;
 }
 
+int cs4340_probe(struct phy_device *phydev)
+{
+   phydev->flags = PHY_BROKEN_RESET;
+   return 0;
+}
+
 int cs4340_startup(struct phy_device *phydev)
 {
phydev->link = 1;
@@ -275,6 +281,7 @@ struct phy_driver cs4340_driver = {
 MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
 MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
.config = _config,
+   .probe  = _probe,
.startup = _startup,
.shutdown = _shutdown,
 };
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8/ls1043aqds: Add support for >2GB memory

[shh.xie]

From: Shaohui Xie 

This patch also exposes the complete DDR region(s) to Linux.

Signed-off-by: Shaohui Xie 
---
 board/freescale/ls1043aqds/ddr.c| 19 ---
 board/freescale/ls1043aqds/ls1043aqds.c | 10 ++
 include/configs/ls1043aqds.h|  2 +-
 3 files changed, 27 insertions(+), 4 deletions(-)

diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c
index 42d9068..3d3c533 100644
--- a/board/freescale/ls1043aqds/ddr.c
+++ b/board/freescale/ls1043aqds/ddr.c
@@ -132,9 +132,22 @@ void dram_init_banksize(void)
 * The address needs to add the offset of its bank.
 */
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-   gd->bd->bi_dram[0].size = gd->ram_size;
+   if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
+   gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
+   gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+   gd->bd->bi_dram[1].size = gd->ram_size -
+ CONFIG_SYS_DDR_BLOCK1_SIZE;
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-   gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
-   gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+   gd->secure_ram = gd->bd->bi_dram[1].start +
+gd->secure_ram -
+CONFIG_SYS_DDR_BLOCK1_SIZE;
+   gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 #endif
+   } else {
+   gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+   gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
+   gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+   }
 }
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c 
b/board/freescale/ls1043aqds/ls1043aqds.c
index d6696ca..576fa46 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -303,6 +303,16 @@ int board_init(void)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
+   u64 base[CONFIG_NR_DRAM_BANKS];
+   u64 size[CONFIG_NR_DRAM_BANKS];
+
+   /* fixup DT for the two DDR banks */
+   base[0] = gd->bd->bi_dram[0].start;
+   size[0] = gd->bd->bi_dram[0].size;
+   base[1] = gd->bd->bi_dram[1].start;
+   size[1] = gd->bd->bi_dram[1].size;
+
+   fdt_fixup_memory_banks(blob, base, size, 2);
ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 398f1c3..02247b3 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -33,7 +33,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
 /* Physical Memory Map */
 #define CONFIG_CHIP_SELECTS_PER_CTRL   4
-#define CONFIG_NR_DRAM_BANKS   1
+#define CONFIG_NR_DRAM_BANKS   2
 
 #define CONFIG_DDR_SPD
 #define SPD_EEPROM_ADDRESS 0x51
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH][v2] armv8: fsl-layerscape: fixes lsch2 serdes registers define

[shh.xie]

From: Shaohui Xie 

Fixes lsch2 SerDes registers define according to LS1043A RM Rev D.

Signed-off-by: Shaohui Xie 
---
changes in v2:
1. fixes indent.

 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  | 67 +++---
 1 file changed, 47 insertions(+), 20 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 83caa91..b794982 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -450,7 +450,8 @@ struct ccsr_serdes {
u32 res_0c; /* 0x00c */
u32 pllcr3;
u32 pllcr4;
-   u8  res_18[0x20-0x18];
+   u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */
+   u8  res_1c[0x20-0x1c];
} bank[2];
u8  res_40[0x90-0x40];
u32 srdstcalcr; /* 0x90 TX Calibration Control */
@@ -458,25 +459,25 @@ struct ccsr_serdes {
u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
u8  res_a4[0xb0-0xa4];
u32 srdsgr0;/* 0xb0 General Register 0 */
-   u8  res_b4[0xe0-0xb4];
-   u32 srdspccr0;  /* 0xe0 Protocol Converter Config 0 */
-   u32 srdspccr1;  /* 0xe4 Protocol Converter Config 1 */
-   u32 srdspccr2;  /* 0xe8 Protocol Converter Config 2 */
-   u32 srdspccr3;  /* 0xec Protocol Converter Config 3 */
-   u32 srdspccr4;  /* 0xf0 Protocol Converter Config 4 */
-   u8  res_f4[0x100-0xf4];
+   u8  res_b4[0x100-0xb4];
struct {
-   u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
+   u32 lnpssr0;/* 0x100, 0x120, 0x140, 0x160 */
u8  res_104[0x120-0x104];
-   } srdslnpssr[4];
-   u8  res_180[0x300-0x180];
-   u32 srdspexeqcr;
-   u32 srdspexeqpcr[11];
-   u8  res_330[0x400-0x330];
-   u32 srdspexapcr;
-   u8  res_404[0x440-0x404];
-   u32 srdspexbpcr;
-   u8  res_444[0x800-0x444];
+   } lnpssr[4];/* Lane A, B, C, D */
+   u8  res_180[0x200-0x180];
+   u32 srdspccr0;  /* 0x200 Protocol Configuration 0 */
+   u32 srdspccr1;  /* 0x204 Protocol Configuration 1 */
+   u32 srdspccr2;  /* 0x208 Protocol Configuration 2 */
+   u32 srdspccr3;  /* 0x20c Protocol Configuration 3 */
+   u32 srdspccr4;  /* 0x210 Protocol Configuration 4 */
+   u32 srdspccr5;  /* 0x214 Protocol Configuration 5 */
+   u32 srdspccr6;  /* 0x218 Protocol Configuration 6 */
+   u32 srdspccr7;  /* 0x21c Protocol Configuration 7 */
+   u32 srdspccr8;  /* 0x220 Protocol Configuration 8 */
+   u32 srdspccr9;  /* 0x224 Protocol Configuration 9 */
+   u32 srdspccra;  /* 0x228 Protocol Configuration A */
+   u32 srdspccrb;  /* 0x22c Protocol Configuration B */
+   u8  res_230[0x800-0x230];
struct {
u32 gcr0;   /* 0x800 General Control Register 0 */
u32 gcr1;   /* 0x804 General Control Register 1 */
@@ -489,8 +490,34 @@ struct ccsr_serdes {
u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
u8  res_824[0x83c-0x824];
u32 tcsr3;
-   } lane[4];  /* Lane A, B, C, D, E, F, G, H */
-   u8  res_a00[0x1000-0xa00];  /* from 0xa00 to 0xfff */
+   } lane[4];  /* Lane A, B, C, D */
+   u8  res_900[0x1000-0x900];  /* from 0x900 to 0xfff */
+   struct {
+   u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */
+   u8  res_1004[0x1040-0x1004];
+   } pcie[3];
+   u8  res_10c0[0x1800-0x10c0];
+   struct {
+   u8  res_1800[0x1804-0x1800];
+   u32 srdssgmiicr1;   /* 0x1804 SGMII Protocol Control 1 */
+   u8  res_1808[0x180c-0x1808];
+   u32 srdssgmiicr3;   /* 0x180c SGMII Protocol Control 3 */
+   } sgmii[4]; /* Lane A, B, C, D */
+   u8  res_1840[0x1880-0x1840];
+   struct {
+   u8  res_1880[0x1884-0x1880];
+   u32 srdsqsgmiicr1;  /* 0x1884 QSGMII Protocol Control 1 */
+   u8  res_1888[0x188c-0x1888];
+   u32 srdsqsgmiicr3;  /* 0x188c QSGMII Protocol Control 3 */
+   } qsgmii[2];/* Lane A, B */
+   u8  res_18a0[0x1980-0x18a0];
+   struct {
+   u8  res_1980[0x1984-0x1980];
+   u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */
+   u8  res_1988[0x198c-0x1988];
+   u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */
+   } xfi[2];   /* Lane A, B */
+   u8  res_19a0[0x2000-0x19a0];  

[U-Boot] [PATCH] armv8: fsl-layerscape: fixes lsch2 serdes registers define

[shh.xie]

From: Shaohui Xie 

Fixes lsch2 SerDes registers define according to LS1043A RM Rev D.

Signed-off-by: Shaohui Xie 
---
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  | 67 +++---
 1 file changed, 47 insertions(+), 20 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 83caa91..57cbef6 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -450,7 +450,8 @@ struct ccsr_serdes {
u32 res_0c; /* 0x00c */
u32 pllcr3;
u32 pllcr4;
-   u8  res_18[0x20-0x18];
+   u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */
+   u8  res_1c[0x20-0x1c];
} bank[2];
u8  res_40[0x90-0x40];
u32 srdstcalcr; /* 0x90 TX Calibration Control */
@@ -458,25 +459,25 @@ struct ccsr_serdes {
u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
u8  res_a4[0xb0-0xa4];
u32 srdsgr0;/* 0xb0 General Register 0 */
-   u8  res_b4[0xe0-0xb4];
-   u32 srdspccr0;  /* 0xe0 Protocol Converter Config 0 */
-   u32 srdspccr1;  /* 0xe4 Protocol Converter Config 1 */
-   u32 srdspccr2;  /* 0xe8 Protocol Converter Config 2 */
-   u32 srdspccr3;  /* 0xec Protocol Converter Config 3 */
-   u32 srdspccr4;  /* 0xf0 Protocol Converter Config 4 */
-   u8  res_f4[0x100-0xf4];
+   u8  res_b4[0x100-0xb4];
struct {
-   u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
+   u32 lnpssr0;/* 0x100, 0x120, 0x140, 0x160 */
u8  res_104[0x120-0x104];
-   } srdslnpssr[4];
-   u8  res_180[0x300-0x180];
-   u32 srdspexeqcr;
-   u32 srdspexeqpcr[11];
-   u8  res_330[0x400-0x330];
-   u32 srdspexapcr;
-   u8  res_404[0x440-0x404];
-   u32 srdspexbpcr;
-   u8  res_444[0x800-0x444];
+   } lnpssr[4];/* Lane A, B, C, D */
+   u8  res_180[0x200-0x180];
+   u32 srdspccr0;  /* 0x200 Protocol Configuration 0 */
+   u32 srdspccr1;  /* 0x204 Protocol Configuration 1 */
+   u32 srdspccr2;  /* 0x208 Protocol Configuration 2 */
+   u32 srdspccr3;  /* 0x20c Protocol Configuration 3 */
+   u32 srdspccr4;  /* 0x210 Protocol Configuration 4 */
+   u32 srdspccr5;  /* 0x214 Protocol Configuration 5 */
+   u32 srdspccr6;  /* 0x218 Protocol Configuration 6 */
+   u32 srdspccr7;  /* 0x21c Protocol Configuration 7 */
+   u32 srdspccr8;  /* 0x220 Protocol Configuration 8 */
+   u32 srdspccr9;  /* 0x224 Protocol Configuration 9 */
+   u32 srdspccra;  /* 0x228 Protocol Configuration A */
+   u32 srdspccrb;  /* 0x22c Protocol Configuration B */
+   u8  res_230[0x800-0x230];
struct {
u32 gcr0;   /* 0x800 General Control Register 0 */
u32 gcr1;   /* 0x804 General Control Register 1 */
@@ -489,8 +490,34 @@ struct ccsr_serdes {
u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
u8  res_824[0x83c-0x824];
u32 tcsr3;
-   } lane[4];  /* Lane A, B, C, D, E, F, G, H */
-   u8  res_a00[0x1000-0xa00];  /* from 0xa00 to 0xfff */
+   } lane[4];  /* Lane A, B, C, D */
+   u8  res_900[0x1000-0x900];  /* from 0x900 to 0xfff */
+   struct {
+   u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */
+   u8  res_1004[0x1040-0x1004];
+   } pcie[3];
+   u8  res_10c0[0x1800-0x10c0];
+   struct {
+   u8  res_1800[0x1804-0x1800];
+   u32 srdssgmiicr1;   /* 0x1804 SGMII Protocol Control 1 */
+   u8  res_1808[0x180c-0x1808];
+   u32 srdssgmiicr3;   /* 0x180c SGMII Protocol Control 3 */
+   } sgmii[4]; /* Lane A, B, C, D */
+   u8  res_1840[0x1880-0x1840];
+   struct {
+   u8  res_1880[0x1884-0x1880];
+   u32 srdsqsgmiicr1;  /* 0x1884 QSGMII Protocol Control 1 */
+   u8  res_1888[0x188c-0x1888];
+   u32 srdsqsgmiicr3;  /* 0x188c QSGMII Protocol Control 3 */
+   } qsgmii[2];/* Lane A, B */
+   u8  res_18a0[0x1980-0x18a0];
+   struct {
+   u8  res_1980[0x1984-0x1980];
+   u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */
+   u8  res_1988[0x198c-0x1988];
+   u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */
+   } xfi[2];   /* Lane A, B */
+   u8  res_19a0[0x2000-0x19a0];/* from 0x19a0 to 0x1fff */
 };
 
 #define 

[U-Boot] [PATCH] net: fm: disables unused FM1-DTSEC1 MAC node in DTS

[shh.xie]

From: Shaohui Xie 

We don't disable unused FM1-DTSEC1 MAC node in FMAN v2 since its used
for MDIO, in FMAN v3, MDIO uses dedicated controller, so we can disable
the unused FM1-DTSEC1 MAC node to avoid it's being probed in kernel.

Signed-off-by: Shaohui Xie 
---
 drivers/net/fm/init.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 3a1de59..7e312f1 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -242,8 +242,10 @@ int ft_fixup_port(void *blob, struct fm_eth_info *info, 
char *prop)
int off;
uint32_t ph;
phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset;
+#ifndef CONFIG_SYS_FMAN_V3
u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS +
CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET;
+#endif
 
off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
if (off == -FDT_ERR_NOTFOUND)
@@ -295,8 +297,10 @@ int ft_fixup_port(void *blob, struct fm_eth_info *info, 
char *prop)
/* board code might have caused offset to change */
off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
 
+#ifndef CONFIG_SYS_FMAN_V3
/* Don't disable FM1-DTSEC1 MAC as its used for MDIO */
if (paddr != dtsec1_addr)
+#endif
fdt_status_disabled(blob, off); /* disable the MAC node */
 
/* disable the fsl,dpa-ethernet node that points to the MAC */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] net: phy: added aquantia PHY AQR405 support

[shh.xie]

From: Shaohui Xie 

The phy can share driver with other aquantia PHYs, so we only added PHY
ID.

Signed-off-by: Shaohui Xie 
---
 drivers/net/phy/aquantia.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index ef4da4e..f90c2ae 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -146,11 +146,26 @@ struct phy_driver aqr105_driver = {
.startup = _startup,
.shutdown = _shutdown,
 };
+
+struct phy_driver aqr405_driver = {
+   .name = "Aquantia AQR405",
+   .uid = 0x3a1b4b2,
+   .mask = 0xfff0,
+   .features = PHY_10G_FEATURES,
+   .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
+MDIO_MMD_PHYXS | MDIO_MMD_AN |
+MDIO_MMD_VEND1),
+   .config = _config,
+   .startup = _startup,
+   .shutdown = _shutdown,
+};
+
 int phy_aquantia_init(void)
 {
phy_register(_driver);
phy_register(_driver);
phy_register(_driver);
+   phy_register(_driver);
 
return 0;
 }
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8: fsl-layerscape: added XFI protocol support for fsl_lsch3

[shh.xie]

From: Shaohui Xie 

This needed to init dpmac.

Signed-off-by: Shaohui Xie 
---
 arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index 2ab8da6..67c3a45 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -120,6 +120,10 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, 
u32 sd_prctl_shift,
   lane_prtcl <= SGMII16)
wriop_init_dpmac(sd, lane + 1,
 (int)lane_prtcl);
+if (lane_prtcl >= XFI1 &&
+lane_prtcl <= XFI8)
+   wriop_init_dpmac(sd, lane + 1,
+(int)lane_prtcl);
break;
}
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] freescale: fman: make sure phy-handle property is big endian

[shh.xie]

From: Shaohui Xie 

When creating phy-handle property, an unsigned int value is created by
fdt_create_phandle, and memcpy is used to get the value, since DTS is
big endian, the value cannot be used directly on little endian SoCs,
it should be converted by cpu_to_fdt32.

Signed-off-by: Shaohui Xie 
---
 board/freescale/common/fman.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c
index 26cf517..b5025ab 100644
--- a/board/freescale/common/fman.c
+++ b/board/freescale/common/fman.c
@@ -52,6 +52,8 @@ int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t 
addr,
if (!ph)
return -FDT_ERR_BADPHANDLE;
 
+   ph = cpu_to_fdt32(ph);
+
offset = fdt_node_offset_by_compat_reg(fdt, compat, addr);
if (offset < 0)
return offset;
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8: ls2085ardb: enable CONFIG_PHY_AQUANTIA

[shh.xie]

From: Shaohui Xie 

To support on board Aquantia's PHY AQR405.

Signed-off-by: Shaohui Xie 
---
 include/configs/ls2085ardb.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index c1c1572..ec9297d 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -335,6 +335,7 @@ unsigned long get_board_sys_clk(void);
 /* MAC/PHY configuration */
 #ifdef CONFIG_FSL_MC_ENET
 #define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_AQUANTIA
 #define CONFIG_PHY_CORTINA
 #define CONFIG_PHYLIB
 #defineCONFIG_SYS_CORTINA_FW_IN_NOR
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] Powerpc: eSDHC: expand a fix to T4160

[shh.xie]

From: Shaohui Xie 

commit b8e5b07225 "Powerpc: eSDHC: Fix mmc read write err in uboot of
T4240QDS board", T4160 also needs this fix.

Signed-off-by: Shaohui Xie 
---
 drivers/mmc/fsl_esdhc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 0b37002..73730b3 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -106,7 +106,8 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct 
mmc_data *data)
xfertyp |= XFERTYP_RSPTYP_48;
 
 #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
-   defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A)
+   defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A) || \
+   defined(CONFIG_PPC_T4160)
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] powerpc/t4240qds: add support of reading Core voltage

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

A U-boot CMD vdd_read is implemented to read Core voltage.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/t4qds/t4240qds.c | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index 4f2cccd..56273e4 100644
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -887,8 +887,38 @@ static int do_vdd_adjust(cmd_tbl_t *cmdtp,
return 0;
 }
 
+static int do_vdd_read(cmd_tbl_t *cmdtp,
+  int flag, int argc,
+  char * const argv[])
+{
+   int vdd, ret;
+
+   if (argc  1)
+   return CMD_RET_USAGE;
+
+   ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR);
+   if (ret) {
+   printf(VID: I2c failed to switch channel\n);
+   return 0;
+   }
+
+   vdd = read_voltage();
+   if (vdd  0)
+   printf(VID: Could not read voltage\n);
+   else
+   printf(VID: Core voltage is at %d mV\n, vdd);
+
+   return 0;
+}
+
 U_BOOT_CMD(
vdd_override, 2, 0, do_vdd_adjust,
Override VDD,
- override with the voltage specified in mV, eg. 1050
 );
+
+U_BOOT_CMD(
+   vdd_read, 1, 0, do_vdd_read,
+   read VDD,
+- Read the voltage specified in mV
+)
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH][v2] powerpc/t4: update serdes table

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

Serdes Lanes availability on T4160 and T4080 are same, which serdes 2  3
support 8 Lanes, but serdes 1  4 support only 4 Lanes E/F/G/H, Lanes
A/B/C/D are not available, updated the serdes table accordingly with
some minor fix.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes in v2:
rephrase commit message.

 arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 103 +++-
 1 file changed, 48 insertions(+), 55 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c 
b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index 74c4c81..7b43b28 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -214,8 +214,8 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
{5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
-   {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
-   {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
+   {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+   {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
@@ -266,37 +266,30 @@ static const struct serdes_config serdes4_cfg_tbl[] = {
 #elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
 static const struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
-   {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
-   XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+   {1, {NONE, NONE, NONE, NONE,
XAUI_FM1_MAC10, XAUI_FM1_MAC10,
XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
-   {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
-   HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+   {2, {NONE, NONE, NONE, NONE,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
-   {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
-   HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+   {4, {NONE, NONE, NONE, NONE,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
-   {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
-   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   {27, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-   {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
-   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   {28, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-   {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
-   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   {35, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-   {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
-   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   {36, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-   {37, {NONE, NONE, QSGMII_FM1_B, NONE,
+   {37, {NONE, NONE, NONE, NONE,
NONE, NONE, QSGMII_FM1_A, NONE} },
-   {38, {NONE, NONE, QSGMII_FM1_B, NONE,
+   {38, {NONE, NONE, NONE, NONE,
NONE, NONE, QSGMII_FM1_A, NONE} },
{}
 };
@@ -363,45 +356,45 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{37, {NONE, NONE, QSGMII_FM2_B, NONE,
-   NONE, QSGMII_FM1_A, NONE, NONE} },
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{38, {NONE, NONE, QSGMII_FM2_B, NONE,
-   NONE, QSGMII_FM1_A, NONE, NONE} },
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-   NONE, QSGMII_FM1_A, NONE, NONE} },
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-   NONE, QSGMII_FM1_A, NONE, NONE} },
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-   NONE, QSGMII_FM1_A, NONE, NONE} },
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-   NONE, QSGMII_FM1_A, NONE, NONE} },
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{47, 

[U-Boot] [PATCH] powerpc/t4240: update serdes table

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

T4160 and T4080 support same serdes options, which serdes 2  3 support 8
Lanes, same as T4240, but serdes 1  4 support only 4 Lanes, Lanes A, B,
C, D are not available, updated the serdes table accordingly with
some minor fix.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 103 +++-
 1 file changed, 48 insertions(+), 55 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c 
b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index 74c4c81..d07f801 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -214,8 +214,8 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
{5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
-   {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
-   {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
+   {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+   {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
@@ -266,37 +266,30 @@ static const struct serdes_config serdes4_cfg_tbl[] = {
 #elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
 static const struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
-   {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
-   XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+   {1, {NONE, NONE, NONE, NONE,
XAUI_FM1_MAC10, XAUI_FM1_MAC10,
XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
-   {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
-   HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+   {2, {NONE, NONE, NONE, NONE,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
-   {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
-   HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+   {4, {NONE, NONE, NONE, NONE,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
-   {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
-   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   {27, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-   {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
-   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   {28, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-   {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
-   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   {35, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-   {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
-   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   {36, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-   {37, {NONE, NONE, QSGMII_FM1_B, NONE,
+   {37, {NONE, NONE, NONE, NONE,
NONE, NONE, QSGMII_FM1_A, NONE} },
-   {38, {NONE, NONE, QSGMII_FM1_B, NONE,
+   {38, {NONE, NONE, NONE, NONE,
NONE, NONE, QSGMII_FM1_A, NONE} },
{}
 };
@@ -363,45 +356,45 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{37, {NONE, NONE, QSGMII_FM2_B, NONE,
-   NONE, QSGMII_FM1_A, NONE, NONE} },
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{38, {NONE, NONE, QSGMII_FM2_B, NONE,
-   NONE, QSGMII_FM1_A, NONE, NONE} },
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-   NONE, QSGMII_FM1_A, NONE, NONE} },
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-   NONE, QSGMII_FM1_A, NONE, NONE} },
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-   NONE, QSGMII_FM1_A, NONE, NONE} },
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-   NONE, QSGMII_FM1_A, NONE, NONE} },
+   NONE, NONE, QSGMII_FM2_A, NONE} },
{47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,

[U-Boot] [PATCH] powerpc/t4rdb: fix cpld reset altbank

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

cpld reset altbank should always reset to bank4 no matter what current
bank is.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/t4rdb/cpld.c | 8 +---
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c
index d5f3812..d563d0d 100644
--- a/board/freescale/t4rdb/cpld.c
+++ b/board/freescale/t4rdb/cpld.c
@@ -47,14 +47,8 @@ void cpld_set_altbank(void)
 
switch (curbank) {
case CPLD_SELECT_BANK0:
-   altbank = CPLD_SELECT_BANK4;
-   CPLD_WRITE(vbank, altbank);
-   override = CPLD_READ(software_on);
-   CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);
-   CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET);
-   break;
case CPLD_SELECT_BANK4:
-   altbank = CPLD_SELECT_BANK0;
+   altbank = CPLD_SELECT_BANK4;
CPLD_WRITE(vbank, altbank);
override = CPLD_READ(software_on);
CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] t4240qds: apply some updates

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

1. board/freescale/t4qds/t4_rcw.cfg
1.8GHz support is requested as default frequency, so update the rcw.

2. remove un-used configs
configs/T4160QDS_SPIFLASH_defconfig
configs/T4240QDS_SPIFLASH_defconfig
SPI boot is not available on T4QDS, so the configs should be removed.

3. board/freescale/t4qds/MAINTAINERS
Updated MAINTAINERS accordingly.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/t4qds/MAINTAINERS   | 4 +---
 board/freescale/t4qds/t4_rcw.cfg| 2 +-
 configs/T4160QDS_SPIFLASH_defconfig | 4 
 configs/T4240QDS_SPIFLASH_defconfig | 4 
 4 files changed, 2 insertions(+), 12 deletions(-)
 delete mode 100644 configs/T4160QDS_SPIFLASH_defconfig
 delete mode 100644 configs/T4240QDS_SPIFLASH_defconfig

diff --git a/board/freescale/t4qds/MAINTAINERS 
b/board/freescale/t4qds/MAINTAINERS
index f88ee7d..57635ab 100644
--- a/board/freescale/t4qds/MAINTAINERS
+++ b/board/freescale/t4qds/MAINTAINERS
@@ -1,16 +1,14 @@
 T4QDS BOARD
-#M:-
+M: Shaohui Xie shaohui@freescale.com
 S: Maintained
 F: board/freescale/t4qds/
 F: include/configs/T4240QDS.h
 F: configs/T4160QDS_defconfig
 F: configs/T4160QDS_NAND_defconfig
 F: configs/T4160QDS_SDCARD_defconfig
-F: configs/T4160QDS_SPIFLASH_defconfig
 F: configs/T4240QDS_defconfig
 F: configs/T4240QDS_NAND_defconfig
 F: configs/T4240QDS_SDCARD_defconfig
-F: configs/T4240QDS_SPIFLASH_defconfig
 F: configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
 
 T4160QDS_SECURE_BOOT BOARD
diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg
index 6f09a7b..267494c 100644
--- a/board/freescale/t4qds/t4_rcw.cfg
+++ b/board/freescale/t4qds/t4_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 010e0100
 #serdes protocol  1_27_5_11
-16070019 18101916  
+1607001b 18101b16  
 04362858 30548c00 ec02 f500
  eeee  000307fc
    0028
diff --git a/configs/T4160QDS_SPIFLASH_defconfig 
b/configs/T4160QDS_SPIFLASH_defconfig
deleted file mode 100644
index 6146b00..000
--- a/configs/T4160QDS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS=PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF4
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240QDS=y
diff --git a/configs/T4240QDS_SPIFLASH_defconfig 
b/configs/T4240QDS_SPIFLASH_defconfig
deleted file mode 100644
index 14dc48a..000
--- a/configs/T4240QDS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS=PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF4
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240QDS=y
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] ahci: fix compile warning under 64 bit mode

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

When compiling under 64 bit mode, there are warnings as below:

In file included from drivers/block/ahci.c:16:0:
drivers/block/ahci.c: In function 'ahci_reset':
./arch/arm/include/asm/io.h:72:28: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
 #define __arch_getl(a)   (*(volatile unsigned int *)(a))
^
./arch/arm/include/asm/io.h:151:31: note: in expansion of macro
'__arch_getl'
 #define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
   ^
drivers/block/ahci.c:144:12: note: in expansion of macro 'readl'
  u32 tmp = readl(host_ctl_reg); /* global controller reset */
^
./arch/arm/include/asm/io.h:77:29: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
 #define __arch_putl(v,a)  (*(volatile unsigned int *)(a) = (v))
 ^
./arch/arm/include/asm/io.h:146:48: note: in expansion of macro
'__arch_putl'
 #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v;
})
^
drivers/block/ahci.c:28:37: note: in expansion of macro 'writel'
 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
 ^
drivers/block/ahci.c:147:3: note: in expansion of macro
'writel_with_flush'
   writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
   ^
./arch/arm/include/asm/io.h:72:28: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
 #define __arch_getl(a)   (*(volatile unsigned int *)(a))
^
./arch/arm/include/asm/io.h:151:31: note: in expansion of macro
'__arch_getl'
 #define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
   ^
drivers/block/ahci.c:28:50: note: in expansion of macro 'readl'
 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
  ^
drivers/block/ahci.c:147:3: note: in expansion of macro
'writel_with_flush'
   writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
   ^
./arch/arm/include/asm/io.h:72:28: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
 #define __arch_getl(a)   (*(volatile unsigned int *)(a))
^
./arch/arm/include/asm/io.h:151:31: note: in expansion of macro
'__arch_getl'
 #define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
   ^
drivers/block/ahci.c:155:9: note: in expansion of macro 'readl'
   tmp = readl(host_ctl_reg);
 ^
drivers/block/ahci.c: In function 'ahci_host_init':
drivers/block/ahci.c:174:22: warning: cast to pointer from integer of
different size [-Wint-to-pointer-cast]
  volatile u8 *mmio = (volatile u8 *)probe_ent-mmio_base;
  ^
drivers/block/ahci.c:218:49: warning: cast from pointer to integer of
different size [-Wpointer-to-int-cast]
   probe_ent-port[i].port_mmio = ahci_port_base((u32) mmio, i);
 ^
drivers/block/ahci.c:219:15: warning: cast to pointer from integer of
different size [-Wint-to-pointer-cast]
   port_mmio = (u8 *) probe_ent-port[i].port_mmio;
   ^
drivers/block/ahci.c: In function 'ahci_print_info':
drivers/block/ahci.c:332:22: warning: cast to pointer from integer of
different size [-Wint-to-pointer-cast]
  volatile u8 *mmio = (volatile u8 *)probe_ent-mmio_base;
  ^
In file included from ./arch/arm/include/asm/byteorder.h:29:0,
 from include/compiler.h:125,
 from include/image.h:19,
 from include/common.h:82,
 from drivers/block/ahci.c:10:
drivers/block/ahci.c: In function 'ahci_fill_sg':
drivers/block/ahci.c:464:19: warning: cast from pointer to integer of
different size [-Wpointer-to-int-cast]
   cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
   ^
include/linux/byteorder/little_endian.h:34:51: note: in definition of
macro '__cpu_to_le32'
 #define __cpu_to_le32(x) ((__force __le32)(__u32)(x))
   ^
drivers/block/ahci.c:464:7: note: in expansion of macro 'cpu_to_le32'
   cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
   ^
drivers/block/ahci.c: In function 'ahci_port_start':
drivers/block/ahci.c:520:27: warning: cast to pointer from integer of
different size [-Wint-to-pointer-cast]
  volatile u8 *port_mmio = (volatile u8 *)pp-port_mmio;
   ^
drivers/block/ahci.c:532:8: warning: cast from pointer to integer of
different size [-Wpointer-to-int-cast]
  mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
^
drivers/block/ahci.c:540:9: warning: cast to pointer from integer of
different size [-Wint-to-pointer-cast]
  memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
 ^
drivers/block/ahci.c:547:50: warning: cast to pointer from integer of

[U-Boot] [PATCH] phylib: add support for aquantia PHYs

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

This patch supports AQ1202, AQ2104, AQR105 PHY.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 drivers/net/phy/Makefile   |   1 +
 drivers/net/phy/aquantia.c | 156 +
 drivers/net/phy/phy.c  |   3 +
 include/phy.h  |   1 +
 4 files changed, 161 insertions(+)
 create mode 100644 drivers/net/phy/aquantia.c

diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 9556536..87d5c9c 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_MV88E6352_SWITCH) += mv88e6352.o
 
 obj-$(CONFIG_PHYLIB) += phy.o
 obj-$(CONFIG_PHYLIB_10G) += generic_10g.o
+obj-$(CONFIG_PHY_AQUANTIA) += aquantia.o
 obj-$(CONFIG_PHY_ATHEROS) += atheros.o
 obj-$(CONFIG_PHY_BROADCOM) += broadcom.o
 obj-$(CONFIG_PHY_DAVICOM) += davicom.o
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
new file mode 100644
index 000..ef4da4e
--- /dev/null
+++ b/drivers/net/phy/aquantia.c
@@ -0,0 +1,156 @@
+/*
+ * Aquantia PHY drivers
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+#include config.h
+#include common.h
+#include phy.h
+
+#ifndef CONFIG_PHYLIB_10G
+#error The Aquantia PHY needs 10G support
+#endif
+
+#define AQUNTIA_10G_CTL0x20
+#define AQUNTIA_VENDOR_P1  0xc400
+
+#define AQUNTIA_SPEED_LSB_MASK 0x2000
+#define AQUNTIA_SPEED_MSB_MASK 0x40
+
+int aquantia_config(struct phy_device *phydev)
+{
+   u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
+
+   if (phydev-interface == PHY_INTERFACE_MODE_SGMII) {
+   /* 1000BASE-T mode */
+   phydev-advertising = SUPPORTED_1000baseT_Full;
+   phydev-supported = phydev-advertising;
+
+   val = (val  ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK;
+   phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
+   } else if (phydev-interface == PHY_INTERFACE_MODE_XGMII) {
+   /* 10GBASE-T mode */
+   phydev-advertising = SUPPORTED_1baseT_Full;
+   phydev-supported = phydev-advertising;
+
+   if (!(val  AQUNTIA_SPEED_LSB_MASK) ||
+   !(val  AQUNTIA_SPEED_MSB_MASK))
+   phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
+ AQUNTIA_SPEED_LSB_MASK |
+ AQUNTIA_SPEED_MSB_MASK);
+   } else if (phydev-interface == PHY_INTERFACE_MODE_SGMII_2500) {
+   /* 2.5GBASE-T mode */
+   phydev-advertising = SUPPORTED_1000baseT_Full;
+   phydev-supported = phydev-advertising;
+
+   phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1);
+   phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);
+   } else if (phydev-interface == PHY_INTERFACE_MODE_MII) {
+   /* 100BASE-TX mode */
+   phydev-advertising = SUPPORTED_100baseT_Full;
+   phydev-supported = phydev-advertising;
+
+   val = (val  ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
+   phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
+   }
+   return 0;
+}
+
+int aquantia_startup(struct phy_device *phydev)
+{
+   u32 reg, speed;
+   int i = 0;
+
+   phydev-duplex = DUPLEX_FULL;
+
+   /* if the AN is still in progress, wait till timeout. */
+   phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
+   reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
+   if (!(reg  MDIO_AN_STAT1_COMPLETE)) {
+   printf(%s Waiting for PHY auto negotiation to complete,
+  phydev-dev-name);
+   do {
+   udelay(1000);
+   reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
+   if ((i++ % 500) == 0)
+   printf(.);
+   } while (!(reg  MDIO_AN_STAT1_COMPLETE) 
+i  (4 * PHY_ANEG_TIMEOUT));
+
+   if (i  PHY_ANEG_TIMEOUT)
+   printf( TIMEOUT !\n);
+   }
+
+   /* Read twice because link state is latched and a
+* read moves the current state into the register */
+   phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
+   reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
+   if (reg  0 || !(reg  MDIO_STAT1_LSTATUS))
+   phydev-link = 0;
+   else
+   phydev-link = 1;
+
+   speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
+   if (speed  AQUNTIA_SPEED_MSB_MASK) {
+   if (speed  AQUNTIA_SPEED_LSB_MASK)
+   phydev-speed = SPEED_1;
+   else
+   phydev-speed = SPEED_1000;
+   } else {
+   if (speed  AQUNTIA_SPEED_LSB_MASK)
+   phydev-speed = SPEED_100;
+   else
+   phydev-speed = SPEED_10;
+ 

[U-Boot] [PATCH] powerpc/p2041rdb: enable generic board configs

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

Add following configs in header file:
CONFIG_SYS_GENERIC_BOARD
CONFIG_DISPLAY_BOARDINFO

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 include/configs/P2041RDB.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 16f7525..ef06227 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -13,6 +13,8 @@
 
 #define CONFIG_P2041RDB
 #define CONFIG_PHYS_64BIT
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_PPC_P2041
 
 #ifdef CONFIG_RAMBOOT_PBL
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] powerpc/hydra: fix judging condition of RGMII selection

[shh.xie]

From: Minghuan Lian minghuan.l...@freescale.com

BRDCFG1_EMI1_SEL_MASK has been changed to 0x78, which contains
selection bits and connected status bit. So the Corresponding mux
value of RGMII is changed to BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN.

Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/corenet_ds/eth_hydra.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/board/freescale/corenet_ds/eth_hydra.c 
b/board/freescale/corenet_ds/eth_hydra.c
index 35825c4..9d8ca9e 100644
--- a/board/freescale/corenet_ds/eth_hydra.c
+++ b/board/freescale/corenet_ds/eth_hydra.c
@@ -250,11 +250,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, 
phys_addr_t addr,
return;
}
 
-   if (mux == BRDCFG1_EMI1_SEL_RGMII) {
+   if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) {
/* RGMII */
/* The RGMII PHY is identified by the MAC connected to it */
sprintf(phy, phy_rgmii_%u, port == FM1_DTSEC4 ? 0 : 1);
fdt_set_phy_handle(fdt, compat, addr, phy);
+   return;
}
 
/* If it's not RGMII or XGMII, it must be SGMII */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/5] powerpc/b4860qds: add xfi support

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

We need following changes to make xfi work on B4:
1. set cross-point switch VSC3308 to use sfp config when running xfi;
2. add 10G interface check for xfi;
3. set phy address for xfi so the 10G ports can be registered by mdio;

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/b4860qds/b4860qds.c | 40 +++--
 board/freescale/b4860qds/eth_b4860qds.c |  6 +
 drivers/net/fm/b4860.c  |  4 +++-
 3 files changed, 42 insertions(+), 8 deletions(-)

diff --git a/board/freescale/b4860qds/b4860qds.c 
b/board/freescale/b4860qds/b4860qds.c
index c819368..6a7e426 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -490,6 +490,9 @@ int configure_vsc3316_3308(void)
return -1;
}
 
+   num_vsc08_con = NUM_CON_VSC3308;
+   /* Configure VSC3308 crossbar switch */
+   ret = select_i2c_ch_pca(I2C_CH_VSC3308);
switch (serdes2_prtcl) {
 #ifdef CONFIG_PPC_B4420
case 0x9d:
@@ -497,18 +500,11 @@ int configure_vsc3316_3308(void)
case 0x9E:
case 0x9A:
case 0x98:
-   case 0xb1:
-   case 0xb2:
case 0x48:
case 0x49:
case 0x4E:
-   case 0x8C:
-   case 0x8D:
case 0x79:
case 0x7A:
-   num_vsc08_con = NUM_CON_VSC3308;
-   /* Configure VSC3308 crossbar switch */
-   ret = select_i2c_ch_pca(I2C_CH_VSC3308);
if (!ret) {
ret = vsc3308_config(VSC3308_TX_ADDRESS,
vsc08_tx_amc, num_vsc08_con);
@@ -522,6 +518,36 @@ int configure_vsc3316_3308(void)
return ret;
}
break;
+   case 0x80:
+   case 0x81:
+   case 0x82:
+   case 0x83:
+   case 0x84:
+   case 0x85:
+   case 0x86:
+   case 0x87:
+   case 0x88:
+   case 0x89:
+   case 0x8a:
+   case 0x8b:
+   case 0x8c:
+   case 0x8d:
+   case 0x8e:
+   case 0xb1:
+   case 0xb2:
+   if (!ret) {
+   ret = vsc3308_config(VSC3308_TX_ADDRESS,
+   vsc08_tx_sfp, num_vsc08_con);
+   if (ret)
+   return ret;
+   ret = vsc3308_config(VSC3308_RX_ADDRESS,
+   vsc08_rx_sfp, num_vsc08_con);
+   if (ret)
+   return ret;
+   } else {
+   return ret;
+   }
+   break;
default:
printf(WARNING:VSC crossbars programming not supported for: %x
 SerDes2 Protocol.\n, serdes2_prtcl);
diff --git a/board/freescale/b4860qds/eth_b4860qds.c 
b/board/freescale/b4860qds/eth_b4860qds.c
index 2726cd2..aa48b5e 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -268,6 +268,12 @@ int board_eth_init(bd_t *bis)
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
+   /*
+* XFI does not need a PHY to work, but to make U-boot
+* happy, assign a fake PHY address for a XFI port.
+*/
+   fm_info_set_phy_address(FM1_10GEC1, 0);
+   fm_info_set_phy_address(FM1_10GEC2, 1);
break;
case 0x98:
/* XAUI in Slot1 and Slot2 */
diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c
index 373cc4f..71285a8 100644
--- a/drivers/net/fm/b4860.c
+++ b/drivers/net/fm/b4860.c
@@ -52,7 +52,9 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
/*B4860 has two 10Gig Mac*/
if ((port == FM1_10GEC1 || port == FM1_10GEC2)  
((is_serdes_configured(XAUI_FM1_MAC9))  ||
-   (is_serdes_configured(XAUI_FM1_MAC10
+(is_serdes_configured(XAUI_FM1_MAC10)) ||
+(is_serdes_configured(XFI_FM1_MAC9))   ||
+(is_serdes_configured(XFI_FM1_MAC10
return PHY_INTERFACE_MODE_XGMII;
 
/* Fix me need to handle RGMII here first */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 4/5] powerpc/b4860qds: add workaround for XFI

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

XFI does not work stable on current board, it's due to heat sink issue,
to make it work stable the board needs additional heat sink, enable two
XFI lanes only. Right now we do not have such an erratum for the issue,
so use a define CONFIG_SYS_FSL_B4860QDS_XFI_ERR to identify it.
The workaround will only be used in XFI protocols and only if the
hwconfig indicates that XFI is prefered.

A new VSC3308 config function is used instead of re-use the original
function, to avoid making the function complex and ugly.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c |   3 +
 board/freescale/b4860qds/b4860qds.c   |  13 
 board/freescale/common/vsc3316_3308.c | 108 ++
 board/freescale/common/vsc3316_3308.h |   4 ++
 include/configs/B4860QDS.h|   2 +
 5 files changed, 130 insertions(+)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c 
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 3a04a89..6de867f 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -308,6 +308,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_A005434
puts(Work-around for Erratum A-005434 enabled\n);
 #endif
+#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR)  defined(CONFIG_B4860QDS)
+   puts(Work-around for Erratum XFI on B4860QDS enabled\n);
+#endif
 
return 0;
 }
diff --git a/board/freescale/b4860qds/b4860qds.c 
b/board/freescale/b4860qds/b4860qds.c
index 86c7c66..1006d2e 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -548,6 +548,18 @@ int configure_vsc3316_3308(void)
 
if (hwconfig_subarg_cmp_f(fsl_b4860_serdes2,
  sfp_amc, sfp, buf)) {
+#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
+   /* change default VSC3308 for XFI erratum */
+   ret = vsc3308_config_adjust(VSC3308_TX_ADDRESS,
+   vsc08_tx_sfp, num_vsc08_con);
+   if (ret)
+   return ret;
+
+   ret = vsc3308_config_adjust(VSC3308_RX_ADDRESS,
+   vsc08_rx_sfp, num_vsc08_con);
+   if (ret)
+   return ret;
+#else
ret = vsc3308_config(VSC3308_TX_ADDRESS,
vsc08_tx_sfp, num_vsc08_con);
if (ret)
@@ -557,6 +569,7 @@ int configure_vsc3316_3308(void)
vsc08_rx_sfp, num_vsc08_con);
if (ret)
return ret;
+#endif
} else {
ret = vsc3308_config(VSC3308_TX_ADDRESS,
vsc08_tx_amc, num_vsc08_con);
diff --git a/board/freescale/common/vsc3316_3308.c 
b/board/freescale/common/vsc3316_3308.c
index 97a25e8..dd9c37e 100644
--- a/board/freescale/common/vsc3316_3308.c
+++ b/board/freescale/common/vsc3316_3308.c
@@ -13,7 +13,12 @@
 #define INPUT_STATE_REG0x13
 #define GLOBAL_INPUT_ISE1  0x51
 #define GLOBAL_INPUT_ISE2  0x52
+#define GLOBAL_INPUT_GAIN  0x53
 #define GLOBAL_INPUT_LOS   0x55
+#define GLOBAL_OUTPUT_PE1  0x56
+#define GLOBAL_OUTPUT_PE2  0x57
+#define GLOBAL_OUTPUT_LEVEL0x58
+#define GLOBAL_OUTPUT_TERMINATION  0x5A
 #define GLOBAL_CORE_CNTRL  0x5D
 #define OUTPUT_MODE_PAGE   0x23
 #define CORE_CONTROL_PAGE  0x25
@@ -92,6 +97,109 @@ int vsc3316_config(unsigned int vsc_addr, int8_t 
con_arr[][2],
return 0;
 }
 
+#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
+int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2],
+   unsigned int num_con)
+{
+   unsigned int i;
+   u8 rev_id = 0;
+   int ret;
+
+   debug(VSC:Initializing VSC3308 at I2C address 0x%x for Tx\n,
+ vsc_addr);
+
+   ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, rev_id, 1);
+   if (ret  0) {
+   printf(VSC:0x%x could not read REV_ID from device.\n,
+  vsc_addr);
+   return ret;
+   }
+
+   if (rev_id != 0xab) {
+   printf(VSC: device at address 0x%x is not VSC3316/3308.\n,
+  vsc_addr);
+   return -ENODEV;
+   }
+
+   ret = vsc_if_enable(vsc_addr);
+   if (ret) {
+   printf(VSC:0x%x could not configured for 2-wire I/F.\n,
+  vsc_addr);
+   return ret;
+   }
+
+   /* config connections - page 

[U-Boot] [PATCH 5/5] B4860QDS: Enable enet port as per fsl_b4860_serdes2 string in hwconfig

[shh.xie]

From: Suresh Gupta suresh.gu...@freescale.com

In B4860QDS board SerDes2 lanes EFGH either go to SFP or AMC riser card
slot2 so either DTSEC3/DTSEC4 or TGEC1/TGEC2 should be accessible. This
Patch enables DTSEC3/DTSEC4 or TGEC1/TGEC2 on bases of user specified
string fsl_b4860_serdes2:sfp_amc=amc or fsl_b4860_serdes2:sfp_amc=sfp
respectively in hwconfig.

Signed-off-by: Suresh Gupta suresh.gu...@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/b4860qds/eth_b4860qds.c | 19 ++
 drivers/net/fm/b4860.c  | 64 +++--
 2 files changed, 81 insertions(+), 2 deletions(-)

diff --git a/board/freescale/b4860qds/eth_b4860qds.c 
b/board/freescale/b4860qds/eth_b4860qds.c
index 595bb4c..501d4b3 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -407,6 +407,25 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, 
phys_addr_t addr,
fdt_setprop(fdt, offset, fixed-link, f_link,
sizeof(f_link));
break;
+   case 0x98: /* XAUI interface */
+   sprintf(alias, phy_xaui_slot1);
+   fdt_status_okay_by_alias(fdt, alias);
+
+   sprintf(alias, phy_xaui_slot2);
+   fdt_status_okay_by_alias(fdt, alias);
+   break;
+   case 0x9e: /* XAUI interface */
+   case 0x9a:
+   case 0x93:
+   case 0x91:
+   sprintf(alias, phy_xaui_slot1);
+   fdt_status_okay_by_alias(fdt, alias);
+   break;
+   case 0x97: /* XAUI interface */
+   case 0xc3:
+   sprintf(alias, phy_xaui_slot2);
+   fdt_status_okay_by_alias(fdt, alias);
+   break;
default:
break;
}
diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c
index 71285a8..eb058c9 100644
--- a/drivers/net/fm/b4860.c
+++ b/drivers/net/fm/b4860.c
@@ -10,6 +10,7 @@
 #include asm/io.h
 #include asm/immap_85xx.h
 #include asm/fsl_serdes.h
+#include hwconfig.h
 
 u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
@@ -46,17 +47,76 @@ void fman_enable_port(enum fm_port port)
 
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
+#if defined(CONFIG_B4860QDS)
+   u32 serdes2_prtcl;
+   char buffer[HWCONFIG_BUFFER_SIZE];
+   char *buf = NULL;
+   ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
 
/*B4860 has two 10Gig Mac*/
if ((port == FM1_10GEC1 || port == FM1_10GEC2)  
((is_serdes_configured(XAUI_FM1_MAC9))  ||
-(is_serdes_configured(XAUI_FM1_MAC10)) ||
+#if !defined(CONFIG_B4860QDS)
 (is_serdes_configured(XFI_FM1_MAC9))   ||
-(is_serdes_configured(XFI_FM1_MAC10
+(is_serdes_configured(XFI_FM1_MAC10))  ||
+#endif
+(is_serdes_configured(XAUI_FM1_MAC10))
+))
return PHY_INTERFACE_MODE_XGMII;
 
+#if defined(CONFIG_B4860QDS)
+   serdes2_prtcl = in_be32(gur-rcwsr[4]) 
+   FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+
+   if (serdes2_prtcl) {
+   serdes2_prtcl = FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+   switch (serdes2_prtcl) {
+   case 0x80:
+   case 0x81:
+   case 0x82:
+   case 0x83:
+   case 0x84:
+   case 0x85:
+   case 0x86:
+   case 0x87:
+   case 0x88:
+   case 0x89:
+   case 0x8a:
+   case 0x8b:
+   case 0x8c:
+   case 0x8d:
+   case 0x8e:
+   case 0xb1:
+   case 0xb2:
+   /*
+* Extract hwconfig from environment since environment
+* is not setup yet
+*/
+   getenv_f(hwconfig, buffer, sizeof(buffer));
+   buf = buffer;
+
+   /* check if XFI interface enable in hwconfig for 10g */
+   if (hwconfig_subarg_cmp_f(fsl_b4860_serdes2,
+ sfp_amc, sfp, buf)) {
+   if ((port == FM1_10GEC1 ||
+port == FM1_10GEC2) 
+   ((is_serdes_configured(XFI_FM1_MAC9)) ||
+   (is_serdes_configured(XFI_FM1_MAC10
+   return PHY_INTERFACE_MODE_XGMII;
+   else if ((port == FM1_DTSEC1) ||
+   

[U-Boot] [PATCH 3/5] B4860QDS: Enable SFP or AMC on basis of hwconfig string

[shh.xie]

From: Suresh Gupta suresh.gu...@freescale.com

SerDes2 lanes EFGH either go to SFP or AMC riser card slot2.
By default AMC will be configured even if no hwconfig is specified.

To enable XFI via SFP use the below hwconfig:
fsl_b4860_serdes2:sfp_amc=sfp

Signed-off-by: Suresh Gupta suresh.gu...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@ffeescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/b4860qds/b4860qds.c | 41 +
 1 file changed, 33 insertions(+), 8 deletions(-)

diff --git a/board/freescale/b4860qds/b4860qds.c 
b/board/freescale/b4860qds/b4860qds.c
index 6a7e426..86c7c66 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -19,6 +19,7 @@
 #include asm/fsl_portals.h
 #include asm/fsl_liodn.h
 #include fm_eth.h
+#include hwconfig.h
 
 #include ../common/qixis.h
 #include ../common/vsc3316_3308.h
@@ -333,6 +334,8 @@ int configure_vsc3316_3308(void)
unsigned int num_vsc16_con, num_vsc08_con;
u32 serdes1_prtcl, serdes2_prtcl;
int ret;
+   char buffer[HWCONFIG_BUFFER_SIZE];
+   char *buf = NULL;
 
serdes1_prtcl = in_be32(gur-rcwsr[4]) 
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
@@ -536,14 +539,36 @@ int configure_vsc3316_3308(void)
case 0xb1:
case 0xb2:
if (!ret) {
-   ret = vsc3308_config(VSC3308_TX_ADDRESS,
-   vsc08_tx_sfp, num_vsc08_con);
-   if (ret)
-   return ret;
-   ret = vsc3308_config(VSC3308_RX_ADDRESS,
-   vsc08_rx_sfp, num_vsc08_con);
-   if (ret)
-   return ret;
+   /*
+* Extract hwconfig from environment since environment
+* is not setup properly yet
+*/
+   getenv_f(hwconfig, buffer, sizeof(buffer));
+   buf = buffer;
+
+   if (hwconfig_subarg_cmp_f(fsl_b4860_serdes2,
+ sfp_amc, sfp, buf)) {
+   ret = vsc3308_config(VSC3308_TX_ADDRESS,
+   vsc08_tx_sfp, num_vsc08_con);
+   if (ret)
+   return ret;
+
+   ret = vsc3308_config(VSC3308_RX_ADDRESS,
+   vsc08_rx_sfp, num_vsc08_con);
+   if (ret)
+   return ret;
+   } else {
+   ret = vsc3308_config(VSC3308_TX_ADDRESS,
+   vsc08_tx_amc, num_vsc08_con);
+   if (ret)
+   return ret;
+
+   ret = vsc3308_config(VSC3308_RX_ADDRESS,
+   vsc08_rx_amc, num_vsc08_con);
+   if (ret)
+   return ret;
+   }
+
} else {
return ret;
}
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/5] powerpc/b4860qds: dtb fixup for xfi

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

Since xfi has no phy, we delete the property phy-handle and use
a fixed-link property for a xfi port.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/b4860qds/eth_b4860qds.c | 38 +
 1 file changed, 38 insertions(+)

diff --git a/board/freescale/b4860qds/eth_b4860qds.c 
b/board/freescale/b4860qds/eth_b4860qds.c
index aa48b5e..595bb4c 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -365,6 +365,11 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, 
phys_addr_t addr,
 {
int phy;
char alias[32];
+   struct fixed_link f_link;
+   ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+   u32 prtcl2 = in_be32(gur-rcwsr[4])  FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+
+   prtcl2 = FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
phy = fm_info_get_phy_address(port);
@@ -372,6 +377,39 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, 
phys_addr_t addr,
sprintf(alias, phy_sgmii_%x, phy);
fdt_set_phy_handle(fdt, compat, addr, alias);
fdt_status_okay_by_alias(fdt, alias);
+   } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
+   /* check if it's XFI interface for 10g */
+   switch (prtcl2) {
+   case 0x80:
+   case 0x81:
+   case 0x82:
+   case 0x83:
+   case 0x84:
+   case 0x85:
+   case 0x86:
+   case 0x87:
+   case 0x88:
+   case 0x89:
+   case 0x8a:
+   case 0x8b:
+   case 0x8c:
+   case 0x8d:
+   case 0x8e:
+   case 0xb1:
+   case 0xb2:
+   f_link.phy_id = port;
+   f_link.duplex = 1;
+   f_link.link_speed = 1;
+   f_link.pause = 0;
+   f_link.asym_pause = 0;
+
+   fdt_delprop(fdt, offset, phy-handle);
+   fdt_setprop(fdt, offset, fixed-link, f_link,
+   sizeof(f_link));
+   break;
+   default:
+   break;
+   }
}
 }
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] powerpc/P5040DS: enable SATA support

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

The define CONFIG_FSL_SATA_V2 is missing, so SATA is not available
in U-boot.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 include/configs/P5040DS.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h
index 371485f..e4a031a 100644
--- a/include/configs/P5040DS.h
+++ b/include/configs/P5040DS.h
@@ -17,6 +17,7 @@
 #define CONFIG_MMC
 #define CONFIG_NAND_FSL_ELBC
 #define CONFIG_PCIE3
+#define CONFIG_FSL_SATA_V2
 #define CONFIG_SYS_FSL_RAID_ENGINE
 
 #define CONFIG_ICS307_REFCLK_HZ2500  /* ICS307 ref clk 
freq */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/2][v2] powerpc/t2080qds: fix for 1000BASE-KX

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

1000BASE-KX(1G-KX) uses SGMII protocol but the serdes lane runs in 1G-KX
mode. By default, the lane runs in SGMII mode, when a MAC uses a lane
in 1G-KX mode, corresponding bit in PCCR1 for the lane needs to be set,
and needs to fixup dtb accordingly for kernel to do proper initialization.

Hwconfig fsl_1gkx is used to indicate a MAC runs in 1G-KX mode, FM1 MAC
1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
MAC runs in 1G-KX mode, set its' corresponding env in fsl_1gkx,
'fm1_1g1' stands for FM1-MAC1, 'fm1_1g2' stands for FM1-MAC2, etc.

If all MAC 1/2/5/6/9/10 run in 1G-KX mode, the hwconfig should has below
setting:

fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes for V2:
- add 1G-KX description in t208xqds README.
- refined commit message.
 board/freescale/t208xqds/README | 12 +
 board/freescale/t208xqds/eth_t208xqds.c | 86 +
 2 files changed, 98 insertions(+)

diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README
index e3eb5ba..83060c1 100755
--- a/board/freescale/t208xqds/README
+++ b/board/freescale/t208xqds/README
@@ -104,6 +104,18 @@ XFI:
  set fsl_10gkr_copper:fm1_10g1,fm1_10g2 in hwconfig, then first two
  XFI ports will use copper cable, the other two XFI ports will use fiber
  cable.
+1000BASE-KX(1G-KX):
+ - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
+ runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
+ in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration
+ Register 1 (PCCR1), and U-boot fixup the dtb for kernel to do proper
+ initialization.
+ Hwconfig fsl_1gkx is used to indicate a lane runs in 1G-KX mode, MAC
+ 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
+ MAC to use 1G-KX mode, set its' corresponding env in fsl_1gkx, 'fm1_1g1'
+ stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc.
+ For ex. set fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10 in
+ hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode.
 
 System Memory map
 
diff --git a/board/freescale/t208xqds/eth_t208xqds.c 
b/board/freescale/t208xqds/eth_t208xqds.c
index 8675dbb..b3a4317 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -47,6 +47,15 @@
 #define EMI2   8
 #endif
 
+#define PCCR1_SGMIIA_KX_MASK   0x8000
+#define PCCR1_SGMIIB_KX_MASK   0x4000
+#define PCCR1_SGMIIC_KX_MASK   0x2000
+#define PCCR1_SGMIID_KX_MASK   0x1000
+#define PCCR1_SGMIIE_KX_MASK   0x0800
+#define PCCR1_SGMIIF_KX_MASK   0x0400
+#define PCCR1_SGMIIG_KX_MASK   0x0200
+#define PCCR1_SGMIIH_KX_MASK   0x0100
+
 static int mdio_mux[NUM_FM_PORTS];
 
 static const char * const mdio_names[] = {
@@ -195,6 +204,10 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, 
phys_addr_t addr,
int off;
 
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+   serdes_corenet_t *srds_regs =
+   (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+   u32 srds1_pccr1 = in_be32(srds_regs-srdspccr1);
+
u32 srds_s1 = in_be32(gur-rcwsr[4]) 
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 
@@ -205,9 +218,54 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, 
phys_addr_t addr,
switch (port) {
 #if defined(CONFIG_T2080QDS)
case FM1_DTSEC1:
+   if (hwconfig_sub(fsl_1gkx, fm1_1g1)) {
+   media_type = 1;
+   fdt_set_phy_handle(fdt, compat, addr,
+  phy_1gkx1);
+   fdt_status_okay_by_alias(fdt, 1gkx_pcs_mdio1);
+   sprintf(buf, %s%s%s, buf, lane-c,,
+   (char *)lane_mode[0]);
+   out_be32(srds_regs-srdspccr1, srds1_pccr1 |
+PCCR1_SGMIIH_KX_MASK);
+   break;
+   }
case FM1_DTSEC2:
+   if (hwconfig_sub(fsl_1gkx, fm1_1g2)) {
+   media_type = 1;
+   fdt_set_phy_handle(fdt, compat, addr,
+  phy_1gkx2);
+   fdt_status_okay_by_alias(fdt, 1gkx_pcs_mdio2);
+   sprintf(buf, %s%s%s, buf, lane-d,,
+   (char *)lane_mode[0]);
+   out_be32(srds_regs-srdspccr1, srds1_pccr1 |
+PCCR1_SGMIIG_KX_MASK);
+   break;
+   }
case 

[U-Boot] [PATCH][v2] powerpc/T4240QDS/eth: some fix for XFI

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

XFI is supported on T4QDS-XFI board, which removed slot3, and four LANEs
of serdes2 are routed to a SFP+ cages, which to house fiber cable or
direct attach cable(copper), the copper cable is used to emulate the
10GBASE-KR scenario.

So, for XFI usage, there are two scenarios, one will use fiber cable,
another will use copper cable. For fiber cable, there is NO PHY, while
for copper cable, we need to use internal PHY which exist in Serdes to
do auto-negotiation and link training, which implemented in kernel.
We use hwconfig to define cable type for XFI, and fixup dtb based on the
cable type.

For copper cable, set below env in hwconfig:

fsl_10gkr_copper:10g_mac_name

the 10g_mac_name can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2. The
four 10g_mac_names do not have to be coexist in hwconfig. For XFI ports,
if a given 10G port will use the copper cable for 10GBASE-KR, set the
10g_mac_name of the port in hwconfig, otherwise, fiber cable will be
assumed to be used for the port.

For ex. if four XFI ports will both use copper cable, the hwconfig
should contain:

fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2

For fiber cable:

1. give PHY address to a XFI port, otherwise, the XFI ports will not be
available in U-boot, there is no PHY physically for XFI when using fiber
cable, this is just to make U-boot happy and we can use the XFI ports
in U-boot.
2. fixup dtb to use fixed-link in case of fiber cable which has no PHY.
Kernel requests that a MAC must have a PHY or fixed-link.

When using XFI protocol, the MAC 9/10 on FM1 should init as 10G interface.

Change serdes 2 protocol 56 to 55 which has same feature as 56 since 56
is not valid any longer.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes for V2:
added XFI information in README.t4240qds

 board/freescale/t4qds/eth.c | 136 ++--
 doc/README.t4240qds |  19 +++
 drivers/net/fm/t4240.c  |   5 ++
 3 files changed, 142 insertions(+), 18 deletions(-)

diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index 6210e46..9b416b1 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -23,6 +23,7 @@
 #include phy.h
 #include asm/fsl_dtsec.h
 #include asm/fsl_serdes.h
+#include hwconfig.h
 #include ../common/qixis.h
 #include ../common/fman.h
 
@@ -173,6 +174,10 @@ void board_ft_fman_fixup_port(void *blob, char * prop, 
phys_addr_t pa,
enum fm_port port, int offset)
 {
int interface = fm_info_get_enet_if(port);
+   ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+   u32 prtcl2 = in_be32(gur-rcwsr[4])  FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+
+   prtcl2 = FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 
if (interface == PHY_INTERFACE_MODE_SGMII ||
interface == PHY_INTERFACE_MODE_QSGMII) {
@@ -262,6 +267,76 @@ void board_ft_fman_fixup_port(void *blob, char * prop, 
phys_addr_t pa,
default:
break;
}
+   } else if (interface == PHY_INTERFACE_MODE_XGMII 
+ ((prtcl2 == 55) || (prtcl2 == 57))) {
+   /*
+* if the 10G is XFI, check hwconfig to see what is the
+* media type, there are two types, fiber or copper,
+* fix the dtb accordingly.
+*/
+   int media_type = 0;
+   struct fixed_link f_link;
+   char lane_mode[20] = {10GBASE-KR};
+   char buf[32] = serdes-2,;
+   int off;
+
+   switch (port) {
+   case FM1_10GEC1:
+   if (hwconfig_sub(fsl_10gkr_copper, fm1_10g1)) {
+   media_type = 1;
+   fdt_set_phy_handle(blob, prop, pa,
+  phy_xfi1);
+   sprintf(buf, %s%s%s, buf, lane-a,,
+   (char *)lane_mode);
+   }
+   break;
+   case FM1_10GEC2:
+   if (hwconfig_sub(fsl_10gkr_copper, fm1_10g2)) {
+   media_type = 1;
+   fdt_set_phy_handle(blob, prop, pa,
+  phy_xfi2);
+   sprintf(buf, %s%s%s, buf, lane-b,,
+   (char *)lane_mode);
+   }
+   break;
+   case FM2_10GEC1:
+   if (hwconfig_sub(fsl_10gkr_copper, fm2_10g1)) {
+   media_type = 1;
+   fdt_set_phy_handle(blob, prop, pa,
+  phy_xfi3);
+   sprintf(buf, %s%s%s, buf, lane-d,,
+   (char *)lane_mode);
+

[U-Boot] [PATCH] Fman/mEMAC: mEMAC fix for 10G MAC and PHY

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

1. use Payload length check disable when enable MAC;
2. add XGMII support for setting MAC interface mode;
3. only enable auto negotiation for Non-XGMII mode;
4. return 0x if clause 22 is used to read 10G phy_id;

Signed-off-by: Shaohui Xie shaohui@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
 arch/powerpc/include/asm/fsl_memac.h |  1 +
 drivers/net/fm/memac.c   | 12 +---
 drivers/net/fm/memac_phy.c   |  2 ++
 3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/include/asm/fsl_memac.h 
b/arch/powerpc/include/asm/fsl_memac.h
index 4640e33..f84c1a9 100644
--- a/arch/powerpc/include/asm/fsl_memac.h
+++ b/arch/powerpc/include/asm/fsl_memac.h
@@ -159,6 +159,7 @@ struct memac {
 #define MEMAC_CMD_CFG_RX_EN0x0002 /* MAC Rx path enable */
 #define MEMAC_CMD_CFG_TX_EN0x0001 /* MAC Tx path enable */
 #define MEMAC_CMD_CFG_RXTX_EN  (MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN)
+#define MEMAC_CMD_CFG_NO_LEN_CHK 0x2 /* Payload length check disable */
 
 /* HASHTABLE_CTRL - Hashtable control register */
 #define HASHTABLE_CTRL_MCAST_EN0x0200 /* enable mulitcast Rx hash 
*/
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index 592a67f..ceed261 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -38,7 +38,8 @@ static void memac_enable_mac(struct fsl_enet_mac *mac)
 {
struct memac *regs = mac-base;
 
-   setbits_be32(regs-command_config, MEMAC_CMD_CFG_RXTX_EN);
+   setbits_be32(regs-command_config,
+MEMAC_CMD_CFG_RXTX_EN | MEMAC_CMD_CFG_NO_LEN_CHK);
 }
 
 static void memac_disable_mac(struct fsl_enet_mac *mac)
@@ -94,11 +95,16 @@ static void memac_set_interface_mode(struct fsl_enet_mac 
*mac,
if_mode = ~IF_MODE_MASK;
if_mode |= (IF_MODE_GMII);
break;
+   case PHY_INTERFACE_MODE_XGMII:
+   if_mode = ~IF_MODE_MASK;
+   if_mode |= IF_MODE_XGMII;
+   break;
default:
break;
}
-   /* Enable automatic speed selection */
-   if_mode |= IF_MODE_EN_AUTO;
+   /* Enable automatic speed selection for Non-XGMII */
+   if (type != PHY_INTERFACE_MODE_XGMII)
+   if_mode |= IF_MODE_EN_AUTO;
 
if (type == PHY_INTERFACE_MODE_RGMII) {
if_mode = ~IF_MODE_EN_AUTO;
diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
index de9c0e9..3fa91b3 100644
--- a/drivers/net/fm/memac_phy.c
+++ b/drivers/net/fm/memac_phy.c
@@ -71,6 +71,8 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int 
dev_addr,
u32 c45 = 1;
 
if (dev_addr == MDIO_DEVAD_NONE) {
+   if (!strcmp(bus-name, DEFAULT_FM_TGEC_MDIO_NAME))
+   return 0x;
c45 = 0; /* clause 22 */
dev_addr = regnum  0x1f;
clrbits_be32(regs-mdio_stat, MDIO_STAT_ENC);
-- 
1.8.0

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[U-Boot] [PATCH] driver/net/fm/memac_phy: set NEG bit for external MDIOs

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

NEG bit default is '1' for external MDIOs as per FMAN-v3 RM, but on some
platforms, e.g. T2080QDS, this bit is '0', which leads to MDIO failure
on XAUI PHY, so set this bit definitely to align with the RM.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 arch/powerpc/include/asm/fsl_memac.h | 1 +
 drivers/net/fm/memac_phy.c   | 5 -
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/include/asm/fsl_memac.h 
b/arch/powerpc/include/asm/fsl_memac.h
index 4640e33..190643e 100644
--- a/arch/powerpc/include/asm/fsl_memac.h
+++ b/arch/powerpc/include/asm/fsl_memac.h
@@ -243,6 +243,7 @@ struct memac_mdio_controller {
 #define MDIO_STAT_PRE  (1  5)
 #define MDIO_STAT_ENC  (1  6)
 #define MDIO_STAT_HOLD_15_CLK  (7  2)
+#define MDIO_STAT_NEG  (1  23)
 
 #define MDIO_CTL_DEV_ADDR(x)   (x  0x1f)
 #define MDIO_CTL_PORT_ADDR(x)  ((x  0x1f)  5)
diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
index de9c0e9..f5b20d5 100644
--- a/drivers/net/fm/memac_phy.c
+++ b/drivers/net/fm/memac_phy.c
@@ -137,9 +137,12 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info 
*info)
 * is zero, so MDIO clock is disabled.
 * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
 * be properly initialized.
+* NEG bit default should be '1' as per FMAN-v3 RM, but on platform
+* like T2080QDS, this bit default is '0', which leads to MDIO failure
+* on XAUI PHY, so set this bit definitely.
 */
setbits_be32(((struct memac_mdio_controller *)info-regs)-mdio_stat,
-MDIO_STAT_CLKDIV(258));
+MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
 
return mdio_register(bus);
 }
-- 
1.8.0

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[U-Boot] [PATCH] powerpc/T4240QDS/eth: some fix for XFI

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

XFI is supported on T4QDS-XFI board, which removed slot3, and four LANEs
of serdes2 are routed to a SFP+ cages, which to house fiber cable or
direct attach cable(copper), the copper cable is used to emulate the
10GBASE-KR scenario.

So, for XFI usage, there are two scenarios, one will use fiber cable,
another will use copper cable. For fiber cable, there is NO PHY, while
for copper cable, we need to use internal PHY which exist in Serdes to
do auto-negotiation and link training, which implemented in kernel.
We use hwconfig to define cable type for XFI, and fixup dtb based on the
cable type.

For copper cable, set below env in hwconfig:

fsl_10gkr_copper:10g_mac_name

the 10g_mac_name can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2. The
four 10g_mac_names do not have to be coexist in hwconfig. For XFI ports,
if a given 10G port will use the copper cable for 10GBASE-KR, set the
10g_mac_name of the port in hwconfig, otherwise, fiber cable will be
assumed to be used for the port.

For ex. if four XFI ports will both use copper cable, the hwconfig
should contain:

fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2

For fiber cable:

1. give PHY address to a XFI port, otherwise, the XFI ports will not be
available in U-boot, there is no PHY physically for XFI when using fiber
cable, this is just to make U-boot happy and we can use the XFI ports
in U-boot.
2. fixup dtb to use fixed-link in case of fiber cable which has no PHY.
Kernel requests that a MAC must have a PHY or fixed-link.

When using XFI protocol, the MAC 9/10 on FM1 should init as 10G interface.

Change serdes 2 protocol 56 to 55 which has same feature as 56 since 56
is not valid any longer.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
based on 'next' of git://git.denx.de/u-boot-mpc85xx.git.

 board/freescale/t4qds/eth.c | 136 ++--
 drivers/net/fm/t4240.c  |   5 ++
 2 files changed, 123 insertions(+), 18 deletions(-)

diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index 6210e46..9b416b1 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -23,6 +23,7 @@
 #include phy.h
 #include asm/fsl_dtsec.h
 #include asm/fsl_serdes.h
+#include hwconfig.h
 #include ../common/qixis.h
 #include ../common/fman.h
 
@@ -173,6 +174,10 @@ void board_ft_fman_fixup_port(void *blob, char * prop, 
phys_addr_t pa,
enum fm_port port, int offset)
 {
int interface = fm_info_get_enet_if(port);
+   ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+   u32 prtcl2 = in_be32(gur-rcwsr[4])  FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+
+   prtcl2 = FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 
if (interface == PHY_INTERFACE_MODE_SGMII ||
interface == PHY_INTERFACE_MODE_QSGMII) {
@@ -262,6 +267,76 @@ void board_ft_fman_fixup_port(void *blob, char * prop, 
phys_addr_t pa,
default:
break;
}
+   } else if (interface == PHY_INTERFACE_MODE_XGMII 
+ ((prtcl2 == 55) || (prtcl2 == 57))) {
+   /*
+* if the 10G is XFI, check hwconfig to see what is the
+* media type, there are two types, fiber or copper,
+* fix the dtb accordingly.
+*/
+   int media_type = 0;
+   struct fixed_link f_link;
+   char lane_mode[20] = {10GBASE-KR};
+   char buf[32] = serdes-2,;
+   int off;
+
+   switch (port) {
+   case FM1_10GEC1:
+   if (hwconfig_sub(fsl_10gkr_copper, fm1_10g1)) {
+   media_type = 1;
+   fdt_set_phy_handle(blob, prop, pa,
+  phy_xfi1);
+   sprintf(buf, %s%s%s, buf, lane-a,,
+   (char *)lane_mode);
+   }
+   break;
+   case FM1_10GEC2:
+   if (hwconfig_sub(fsl_10gkr_copper, fm1_10g2)) {
+   media_type = 1;
+   fdt_set_phy_handle(blob, prop, pa,
+  phy_xfi2);
+   sprintf(buf, %s%s%s, buf, lane-b,,
+   (char *)lane_mode);
+   }
+   break;
+   case FM2_10GEC1:
+   if (hwconfig_sub(fsl_10gkr_copper, fm2_10g1)) {
+   media_type = 1;
+   fdt_set_phy_handle(blob, prop, pa,
+  phy_xfi3);
+   sprintf(buf, %s%s%s, buf, lane-d,,
+   (char *)lane_mode);
+   }
+   break;
+  

[U-Boot] [PATCH] powerpc/T4240QDS/eth: fix for XFI

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

XFI is supported on T4QDS-XFI board, which removed slot3, and four LANEs
of serdes2 are routed to a SFP+ cages, which to house fiber cable or
direct attach cable(copper), the copper cable is used to emulate the
10GBASE-KR scenario.

So, for XFI usage, there are two scenarios, one will use fiber cable,
another will use copper cable. For fiber cable, there is NO PHY, while
for copper cable, we need to use internal PHY which exist in Serdes to
do auto-negotiation and link training, which implemented in kernel.
We use hwconfig to define cable type for XFI, and fixup dtb based on the
cable type.

For copper cable, set below env in hwconfig:

fsl_10gkr_copper:10g_mac_name

the 10g_mac_name can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2. The
four 10g_mac_names do not have to be coexist in hwconfig. For XFI ports,
if a given 10G port will use the copper cable for 10GBASE-KR, set the
10g_mac_name of the port in hwconfig, otherwise, fiber cable will be
assumed to be used for the port.

For ex. if four XFI ports will both use copper cable, the hwconfig
should contain:

fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2

For fiber cable:

1. give PHY address to a XFI port, otherwise, the XFI ports will not be
available in U-boot, there is no PHY physically for XFI when using fiber
cable, this is just to make U-boot happy and we can use the XFI ports
in U-boot.
2. fixup dtb to use fixed-link in case of fiber cable which has no PHY.
Kernel requests that a MAC must have a PHY or fixed-link.

Signed-off-by: Shaohui Xie shaohui@freescale.com
Change-Id: I36cb9602de7be00753d5e2985f9e9f204ff51fb7
Reviewed-on: http://git.am.freescale.net:8181/7361
Tested-by: Review Code-CDREVIEW cdrev...@freescale.com
Reviewed-by: Yusong Sun york...@freescale.com
---
based on git://git.denx.de/u-boot-mpc85xx.git

 board/freescale/t4qds/eth.c | 126 +++-
 drivers/net/fm/t4240.c  |   5 ++
 2 files changed, 118 insertions(+), 13 deletions(-)

diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index 6210e46..e8923c2 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -23,6 +23,7 @@
 #include phy.h
 #include asm/fsl_dtsec.h
 #include asm/fsl_serdes.h
+#include hwconfig.h
 #include ../common/qixis.h
 #include ../common/fman.h
 
@@ -173,6 +174,10 @@ void board_ft_fman_fixup_port(void *blob, char * prop, 
phys_addr_t pa,
enum fm_port port, int offset)
 {
int interface = fm_info_get_enet_if(port);
+   ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+   u32 prtcl2 = in_be32(gur-rcwsr[4])  FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+
+   prtcl2 = FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 
if (interface == PHY_INTERFACE_MODE_SGMII ||
interface == PHY_INTERFACE_MODE_QSGMII) {
@@ -262,6 +267,76 @@ void board_ft_fman_fixup_port(void *blob, char * prop, 
phys_addr_t pa,
default:
break;
}
+   } else if (interface == PHY_INTERFACE_MODE_XGMII 
+ ((prtcl2 == 56) || (prtcl2 == 57))) {
+   /*
+* if the 10G is XFI, check hwconfig to see what is the
+* media type, there are two types, fiber or copper,
+* fix the dtb accordingly.
+*/
+   int media_type = 0;
+   struct fixed_link f_link;
+   char lane_mode[20] = {10GBASE-KR};
+   char buf[32] = serdes-2,;
+   int off;
+
+   switch (port) {
+   case FM1_10GEC1:
+   if (hwconfig_sub(fsl_10gkr_copper, fm1_10g1)) {
+   media_type = 1;
+   fdt_set_phy_handle(blob, prop, pa,
+  phy_xfi1);
+   sprintf(buf, %s%s%s, buf, lane-a,,
+   (char *)lane_mode);
+   }
+   break;
+   case FM1_10GEC2:
+   if (hwconfig_sub(fsl_10gkr_copper, fm1_10g2)) {
+   media_type = 1;
+   fdt_set_phy_handle(blob, prop, pa,
+  phy_xfi2);
+   sprintf(buf, %s%s%s, buf, lane-b,,
+   (char *)lane_mode);
+   }
+   break;
+   case FM2_10GEC1:
+   if (hwconfig_sub(fsl_10gkr_copper, fm2_10g1)) {
+   media_type = 1;
+   fdt_set_phy_handle(blob, prop, pa,
+  phy_xfi3);
+   sprintf(buf, %s%s%s, buf, lane-d,,
+   (char *)lane_mode);
+   

[U-Boot] [PATCH 1/2] powerpc/t2080qds: fixup dtb for 10g-kr

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

XFI ports on t2080qds can work with fiber cable and direct attach
cable(copper). We use hwconfig to define cable type for XFI, and fixup
dtb based on the cable type.

For copper cable, set below env in hwconfig:

fsl_10gkr_copper:10g_mac_name

the 10g_mac_name can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4.
fm1_10g1 stands for FM1-MAC9, fm1_10g2 stands for FM1-MAC10, fm1_10g3
stands for FM1-MAC1, fm1_10g4 stands for FM1-MAC2. The four
10g_mac_names do not have to be coexist in hwconfig. For XFI ports, if
a given 10G port will use the copper cable for 10GBASE-KR, set the
10g_mac_name of the port in hwconfig, otherwise, fiber cable will be
assumed to be used for the port.

For ex. if four XFI ports will both use copper cable, the hwconfig
should contain:

fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/t208xqds/eth_t208xqds.c | 86 +
 1 file changed, 77 insertions(+), 9 deletions(-)

diff --git a/board/freescale/t208xqds/eth_t208xqds.c 
b/board/freescale/t208xqds/eth_t208xqds.c
index 5879198..8675dbb 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -23,6 +23,7 @@
 #include phy.h
 #include asm/fsl_dtsec.h
 #include asm/fsl_serdes.h
+#include hwconfig.h
 #include ../common/qixis.h
 #include ../common/fman.h
 #include t208xqds_qixis.h
@@ -187,7 +188,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, 
phys_addr_t addr,
 {
int phy;
char alias[20];
+   char lane_mode[2][20] = {1000BASE-KX, 10GBASE-KR};
+   char buf[32] = serdes-1,;
struct fixed_link f_link;
+   int media_type = 0;
+   int off;
+
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1 = in_be32(gur-rcwsr[4]) 
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
@@ -265,15 +271,77 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, 
phys_addr_t addr,
case 0x6c:
case 0x6d:
case 0x71:
-   f_link.phy_id = port;
-   f_link.duplex = 1;
-   f_link.link_speed = 1;
-   f_link.pause = 0;
-   f_link.asym_pause = 0;
-   /* no PHY for XFI */
-   fdt_delprop(fdt, offset, phy-handle);
-   fdt_setprop(fdt, offset, fixed-link, f_link,
-   sizeof(f_link));
+   /*
+   * if the 10G is XFI, check hwconfig to see what is the
+   * media type, there are two types, fiber or copper,
+   * fix the dtb accordingly.
+   */
+   switch (port) {
+   case FM1_10GEC1:
+   if (hwconfig_sub(fsl_10gkr_copper, fm1_10g1)) {
+   /* it's MAC9 */
+   media_type = 1;
+   fdt_set_phy_handle(fdt, compat, addr,
+   phy_xfi9);
+   fdt_status_okay_by_alias(fdt, xfi_pcs_mdio9);
+   sprintf(buf, %s%s%s, buf, lane-a,,
+   (char *)lane_mode[1]);
+   }
+   break;
+   case FM1_10GEC2:
+   if (hwconfig_sub(fsl_10gkr_copper, fm1_10g2)) {
+   /* it's MAC10 */
+   media_type = 1;
+   fdt_set_phy_handle(fdt, compat, addr,
+   phy_xfi10);
+   fdt_status_okay_by_alias(fdt, xfi_pcs_mdio10);
+   sprintf(buf, %s%s%s, buf, lane-b,,
+   (char *)lane_mode[1]);
+   }
+   break;
+   case FM1_10GEC3:
+   if (hwconfig_sub(fsl_10gkr_copper, fm1_10g3)) {
+   /* it's MAC1 */
+   media_type = 1;
+   fdt_set_phy_handle(fdt, compat, addr,
+   phy_xfi1);
+   fdt_status_okay_by_alias(fdt, xfi_pcs_mdio1);
+   sprintf(buf, %s%s%s, buf, lane-c,,
+   (char *)lane_mode[1]);
+   }
+   break;
+   case FM1_10GEC4:
+   if (hwconfig_sub(fsl_10gkr_copper, fm1_10g4)) {
+   /* it's MAC2 */
+   media_type = 1;
+   

[U-Boot] [PATCH 2/2] powerpc/t2080qds: fix dtb when runnig 1000BASE-KX protocol

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

1000BASE-KX(1GKX) uses same SGMII interface but the serdes lane run in
1GKX mode. By default, the lane runs in SGMII mode, when a MAC runs in
1GKX mode, the corresponding lane mode needs to be set accordingly.
DTB needs the fixup for kernel to do proper initialization.

hwconfig fsl_1gkx is used to indicate a MAC runs in 1GKX mode, MAC
1/2/5/6/9/10 are available for 1GKX, MAC 3/4 run in RGMII mode. To set a
MAC runs in 1GKX mode, set its' corresponding env in fsl_1gkx,
'fm1_1g1' stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc.

If all MAC 1/2/5/6/9/10 run in 1GKX mode, the hwconfig should has below
setting:

fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/t208xqds/eth_t208xqds.c | 86 +
 1 file changed, 86 insertions(+)

diff --git a/board/freescale/t208xqds/eth_t208xqds.c 
b/board/freescale/t208xqds/eth_t208xqds.c
index 8675dbb..b3a4317 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -47,6 +47,15 @@
 #define EMI2   8
 #endif
 
+#define PCCR1_SGMIIA_KX_MASK   0x8000
+#define PCCR1_SGMIIB_KX_MASK   0x4000
+#define PCCR1_SGMIIC_KX_MASK   0x2000
+#define PCCR1_SGMIID_KX_MASK   0x1000
+#define PCCR1_SGMIIE_KX_MASK   0x0800
+#define PCCR1_SGMIIF_KX_MASK   0x0400
+#define PCCR1_SGMIIG_KX_MASK   0x0200
+#define PCCR1_SGMIIH_KX_MASK   0x0100
+
 static int mdio_mux[NUM_FM_PORTS];
 
 static const char * const mdio_names[] = {
@@ -195,6 +204,10 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, 
phys_addr_t addr,
int off;
 
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+   serdes_corenet_t *srds_regs =
+   (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+   u32 srds1_pccr1 = in_be32(srds_regs-srdspccr1);
+
u32 srds_s1 = in_be32(gur-rcwsr[4]) 
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 
@@ -205,9 +218,54 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, 
phys_addr_t addr,
switch (port) {
 #if defined(CONFIG_T2080QDS)
case FM1_DTSEC1:
+   if (hwconfig_sub(fsl_1gkx, fm1_1g1)) {
+   media_type = 1;
+   fdt_set_phy_handle(fdt, compat, addr,
+  phy_1gkx1);
+   fdt_status_okay_by_alias(fdt, 1gkx_pcs_mdio1);
+   sprintf(buf, %s%s%s, buf, lane-c,,
+   (char *)lane_mode[0]);
+   out_be32(srds_regs-srdspccr1, srds1_pccr1 |
+PCCR1_SGMIIH_KX_MASK);
+   break;
+   }
case FM1_DTSEC2:
+   if (hwconfig_sub(fsl_1gkx, fm1_1g2)) {
+   media_type = 1;
+   fdt_set_phy_handle(fdt, compat, addr,
+  phy_1gkx2);
+   fdt_status_okay_by_alias(fdt, 1gkx_pcs_mdio2);
+   sprintf(buf, %s%s%s, buf, lane-d,,
+   (char *)lane_mode[0]);
+   out_be32(srds_regs-srdspccr1, srds1_pccr1 |
+PCCR1_SGMIIG_KX_MASK);
+   break;
+   }
case FM1_DTSEC9:
+   if (hwconfig_sub(fsl_1gkx, fm1_1g9)) {
+   media_type = 1;
+   fdt_set_phy_handle(fdt, compat, addr,
+  phy_1gkx9);
+   fdt_status_okay_by_alias(fdt, 1gkx_pcs_mdio9);
+   sprintf(buf, %s%s%s, buf, lane-a,,
+   (char *)lane_mode[0]);
+   out_be32(srds_regs-srdspccr1, srds1_pccr1 |
+PCCR1_SGMIIE_KX_MASK);
+   break;
+   }
case FM1_DTSEC10:
+   if (hwconfig_sub(fsl_1gkx, fm1_1g10)) {
+   media_type = 1;
+   fdt_set_phy_handle(fdt, compat, addr,
+  phy_1gkx10);
+   fdt_status_okay_by_alias(fdt,
+1gkx_pcs_mdio10);
+   sprintf(buf, %s%s%s, buf, lane-b,,
+   (char *)lane_mode[0]);
+   out_be32(srds_regs-srdspccr1, srds1_pccr1 |
+  

[U-Boot] [PATCH] powerpc/t4240qds: fix offset of serdes when checking its' reference clock

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

T4240 has 4 serdes, each serdes has 4k memory space, two PLLs.
We use PLL1CR0 to check the serdes reference clock.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 arch/powerpc/include/asm/immap_85xx.h |  6 ++
 board/freescale/t4qds/t4240qds.c  | 10 ++
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/include/asm/immap_85xx.h 
b/arch/powerpc/include/asm/immap_85xx.h
index 8258ab3..dfb370e 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2905,6 +2905,8 @@ struct ccsr_sfp_regs {
 #endif
 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET   0xEA000
 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET  0xEB000
+#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET  0xEC000
+#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET  0xED000
 #define CONFIG_SYS_FSL_CPC_OFFSET  0x1
 #define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x10
@@ -3090,6 +3092,10 @@ struct ccsr_sfp_regs {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
+   (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
+   (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB2_ADDR \
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index fe1bc7f..cbe62c1 100644
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -638,9 +638,10 @@ unsigned long get_board_ddr_clk(void)
 int misc_init_r(void)
 {
u8 sw;
-   serdes_corenet_t *srds_regs =
-   (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+   void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+   serdes_corenet_t *srds_regs;
u32 actual[MAX_SERDES];
+   u32 pllcr0, expected;
unsigned int i;
 
sw = QIXIS_READ(brdcfg[2]);
@@ -663,8 +664,9 @@ int misc_init_r(void)
}
 
for (i = 0; i  MAX_SERDES; i++) {
-   u32 pllcr0 = srds_regs-bank[i].pllcr0;
-   u32 expected = pllcr0  SRDS_PLLCR0_RFCK_SEL_MASK;
+   srds_regs = srds_base + i * 0x1000;
+   pllcr0 = srds_regs-bank[0].pllcr0;
+   expected = pllcr0  SRDS_PLLCR0_RFCK_SEL_MASK;
if (expected != actual[i]) {
printf(Warning: SERDES%u expects reference clock 
%sMHz, but actual is %sMHz\n,
   i + 1, serdes_clock_to_string(expected),
-- 
1.8.0

___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] powerpc/ifc: fix invalid CSn FTIM2.TCH setting

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

On some platforms, CSn FTIM2.TCH is set to zero which is invalid,
an invalid hold time makes DUT timing variances, whether it works
or not on luck.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
based on 'next' of git://git.denx.de/u-boot-mpc85xx.git.

 include/configs/B4860QDS.h   | 2 +-
 include/configs/BSC9132QDS.h | 2 +-
 include/configs/C29XPCIE.h   | 2 +-
 include/configs/P1010RDB.h   | 2 +-
 include/configs/T104xRDB.h   | 2 +-
 include/configs/T208xRDB.h   | 2 +-
 include/configs/T4240QDS.h   | 2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 1af9ba6..43c9df0 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -340,7 +340,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS3_FTIM1   (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS3_FTIM2   (FTIM2_GPCM_TCS(0x0e) | \
-   FTIM2_GPCM_TCH(0x0) | \
+   FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3   0x0
 
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 7bb5d33..49c16af 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -354,7 +354,7 @@ combinations. this should be removed later
 #define CONFIG_SYS_CS2_FTIM1   (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS2_FTIM2   (FTIM2_GPCM_TCS(0x0e) | \
-   FTIM2_GPCM_TCH(0x0) | \
+   FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS2_FTIM3   0x0
 #endif
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 9e12fac..0dd1560 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -319,7 +319,7 @@
 #define CONFIG_SYS_CS2_FTIM1   (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS2_FTIM2   (FTIM2_GPCM_TCS(0x0e) | \
-   FTIM2_GPCM_TCH(0x0) | \
+   FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS2_FTIM3   0x0
 
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index d612a8b..50529bf 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -537,7 +537,7 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_CS3_FTIM1   (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS3_FTIM2   (FTIM2_GPCM_TCS(0x0e) | \
-   FTIM2_GPCM_TCH(0x0) | \
+   FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3   0x0
 
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 8d6c51b..40bfc60 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -286,7 +286,7 @@
 #define CONFIG_SYS_CS2_FTIM1   (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS2_FTIM2   (FTIM2_GPCM_TCS(0x0e) | \
-   FTIM2_GPCM_TCH(0x0) | \
+   FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS2_FTIM3   0x0
 
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 3a1c49c..5d10ad2 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -283,7 +283,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS2_FTIM1   (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS2_FTIM2   (FTIM2_GPCM_TCS(0x0e) | \
-   FTIM2_GPCM_TCH(0x0) | \
+   FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS2_FTIM3   0x0
 
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index a770dd0..efdb68b 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -237,7 +237,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS3_FTIM1   (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
 #define CONFIG_SYS_CS3_FTIM2   (FTIM2_GPCM_TCS(0x0e) | \
-   FTIM2_GPCM_TCH(0x0) | \
+   FTIM2_GPCM_TCH(0x8) | \

[U-Boot] [PATCH][v2] powerpc/t4qds: Add alternate serdes protocols to align with A-007186

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to
increase and cause the PLL to unlock when the temperature delta from the
time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V
or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC VCO.
Only the protocols using Ring VCOs are impacted.

Workaround:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need
to use alternate serdes protocols. The alternate option has the same
functionality as the original option; the only difference being LC VCO
rather than Ring VCO.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes for V2:
refine the commit message.

 arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 172 
 board/freescale/t4qds/eth.c |  20 
 board/freescale/t4qds/t4240qds.c|  27 +
 3 files changed, 219 insertions(+)

diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c 
b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index 1f99a0a..74c4c81 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -30,22 +30,41 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+   {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+   SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+   {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+   SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+   {37, {NONE, NONE, QSGMII_FM1_B, NONE,
+   NONE, NONE, QSGMII_FM1_A, NONE} },
{38, {NONE, NONE, QSGMII_FM1_B, NONE,
NONE, NONE, QSGMII_FM1_A, NONE}},
+   {39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   NONE, NONE, QSGMII_FM1_A, NONE} },
{40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
+   {45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   NONE, NONE, QSGMII_FM1_A, NONE} },
{46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
+   {47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   NONE, NONE, QSGMII_FM1_A, NONE} },
{48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
@@ -65,10 +84,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+   {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+   XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+   SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+   SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+   {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+   XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+   SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+   SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -77,10 +104,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+   {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+   HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+   SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+   SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+   {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ 

[U-Boot] [PATCH][v3] powerpc/t4qds: Add alternate serdes protocols to align with A-007186

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to
increase and cause the PLL to unlock when the temperature delta from the
time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V
(or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC
VCO. Only the protocols using Ring VCOs are impacted.

Workaround:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need
to use alternate serdes protocols. The alternate option has the same
functionality as the original option; the only difference being LC VCO
rather than Ring VCO.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes for V3:
update t4_rcw.cfg.

changes for V2:
refined commit message.

 arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 172 
 board/freescale/t4qds/eth.c |  20 
 board/freescale/t4qds/t4240qds.c|  27 +
 board/freescale/t4qds/t4_rcw.cfg|   4 +-
 4 files changed, 221 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c 
b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index 1f99a0a..74c4c81 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -30,22 +30,41 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+   {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+   SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+   {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+   SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+   {37, {NONE, NONE, QSGMII_FM1_B, NONE,
+   NONE, NONE, QSGMII_FM1_A, NONE} },
{38, {NONE, NONE, QSGMII_FM1_B, NONE,
NONE, NONE, QSGMII_FM1_A, NONE}},
+   {39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   NONE, NONE, QSGMII_FM1_A, NONE} },
{40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
+   {45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   NONE, NONE, QSGMII_FM1_A, NONE} },
{46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
+   {47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   NONE, NONE, QSGMII_FM1_A, NONE} },
{48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
@@ -65,10 +84,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+   {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+   XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+   SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+   SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+   {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+   XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+   SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+   SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -77,10 +104,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+   {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+   HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+   SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+   SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  

[U-Boot] [PATCH] powerpc/t4qds: Add alternate serdes protocols to align with A-007186

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

A-007186: SerDes Ring VCO does not maintain lock throughout specified
temperature range.

Option 1 of the workaround states:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need
to use alternate serdes protocols. The alternate option has the same
functionality as the original option; the only difference being LC VCO
rather than Ring VCO.

So add the alternate serdes protocols by duplicating setting of the
originals.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 172 
 board/freescale/t4qds/eth.c |  20 
 board/freescale/t4qds/t4240qds.c|  27 +
 3 files changed, 219 insertions(+)

diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c 
b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index 1f99a0a..74c4c81 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -30,22 +30,41 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+   {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+   SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+   {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+   SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+   {37, {NONE, NONE, QSGMII_FM1_B, NONE,
+   NONE, NONE, QSGMII_FM1_A, NONE} },
{38, {NONE, NONE, QSGMII_FM1_B, NONE,
NONE, NONE, QSGMII_FM1_A, NONE}},
+   {39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   NONE, NONE, QSGMII_FM1_A, NONE} },
{40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
+   {45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   NONE, NONE, QSGMII_FM1_A, NONE} },
{46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
+   {47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+   SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+   NONE, NONE, QSGMII_FM1_A, NONE} },
{48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
@@ -65,10 +84,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+   {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+   XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+   SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+   SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+   {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+   XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+   SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+   SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -77,10 +104,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+   {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+   HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+   SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+   SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+   {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+   HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+   SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+   SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  

[U-Boot] [PATCH][v2] powerpc/T4QDS: add two stage boot of nand/sd

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

Add support of 2 stage NAND/SD boot loader using SPL framework.
PBL initialise the internal SRAM and copy SPL, this further
initialise DDR using SPD and environment and copy u-boot from
NAND/SD to DDR, finally SPL transfer control to u-boot.
NOR uses CS1 instead of CS2 when NAND boot, fix it.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes for v2:
added Secure Boot header(32KB), adjust settings accordingly.

 board/freescale/t4qds/Makefile |   6 +-
 board/freescale/t4qds/ddr.c|   6 +-
 board/freescale/t4qds/spl.c| 145 +
 board/freescale/t4qds/tlb.c|   8 ++-
 boards.cfg |   7 +-
 doc/README.t4240qds|  53 +++
 include/configs/T4240QDS.h |  99 ++--
 include/configs/t4qds.h|  17 -
 8 files changed, 314 insertions(+), 27 deletions(-)
 create mode 100644 board/freescale/t4qds/spl.c

diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile
index 2b1f7aa..4e8e5cb 100644
--- a/board/freescale/t4qds/Makefile
+++ b/board/freescale/t4qds/Makefile
@@ -4,10 +4,14 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
 obj-$(CONFIG_T4240QDS) += t4240qds.o
 obj-$(CONFIG_T4240EMU) += t4240emu.o
-obj-y  += ddr.o
 obj-$(CONFIG_T4240QDS)+= eth.o
 obj-$(CONFIG_PCI)  += pci.o
+endif
+obj-y  += ddr.o
 obj-y  += law.o
 obj-y  += tlb.o
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index 7586cc3..7abd38d 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -117,11 +117,15 @@ phys_size_t initdram(int board_type)
 
puts(Initializingusing SPD\n);
 
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
dram_size = fsl_ddr_sdram();
 
dram_size = setup_ddr_tlbs(dram_size / 0x10);
dram_size *= 0x10;
 
-   puts(DDR: );
+#else
+   /* DDR has been initialised by first stage boot loader */
+   dram_size = fsl_ddr_sdram_size();
+#endif
return dram_size;
 }
diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c
new file mode 100644
index 000..21463fb
--- /dev/null
+++ b/board/freescale/t4qds/spl.c
@@ -0,0 +1,145 @@
+/* Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/spl.h
+#include malloc.h
+#include ns16550.h
+#include nand.h
+#include mmc.h
+#include fsl_esdhc.h
+#include i2c.h
+#include ../common/qixis.h
+#include t4240qds_qixis.h
+
+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK   0xFF80
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+   return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+   u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+   switch (sysclk_conf  0x0F) {
+   case QIXIS_SYSCLK_83:
+   return 8333;
+   case QIXIS_SYSCLK_100:
+   return 1;
+   case QIXIS_SYSCLK_125:
+   return 12500;
+   case QIXIS_SYSCLK_133:
+   return 1;
+   case QIXIS_SYSCLK_150:
+   return 15000;
+   case QIXIS_SYSCLK_160:
+   return 16000;
+   case QIXIS_SYSCLK_166:
+   return 1;
+   }
+   return ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+   u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+   switch ((ddrclk_conf  0x30)  4) {
+   case QIXIS_DDRCLK_100:
+   return 1;
+   case QIXIS_DDRCLK_125:
+   return 12500;
+   case QIXIS_DDRCLK_133:
+   return 1;
+   }
+   return ;
+}
+
+void board_init_f(ulong bootflag)
+{
+   u32 plat_ratio, sys_clk, ccb_clk;
+   ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#ifdef CONFIG_SPL_NAND_BOOT
+   u32 porsr1, pinctl;
+#endif
+
+#ifdef CONFIG_SPL_NAND_BOOT
+   porsr1 = in_be32(gur-porsr1);
+   pinctl = ((porsr1  ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x2480);
+   out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x2), pinctl);
+#endif
+   /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+   memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+   /* Update GD pointer */
+   gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+   __asm__ __volatile__( : : : memory);
+
+   console_init_f();
+
+   /* initialize selected port with appropriate baud rate */
+   sys_clk = get_board_sys_clk();
+   plat_ratio = (in_be32(gur-rcwsr[0])  25)  0x1f;
+   ccb_clk = sys_clk * plat_ratio / 2;
+
+   NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+   puts(\nSD boot...\n);
+#elif defined(CONFIG_SPL_NAND_BOOT)
+   puts(\nNAND boot...\n);
+#endif
+   

[U-Boot] [PATCH ][v3] powerpc/T4QDS: add two stage boot of nand/sd

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

Add support of 2 stage NAND/SD boot loader using SPL framework.
PBL initialise the internal SRAM and copy SPL, this further
initialise DDR using SPD and environment and copy u-boot from
NAND/SD to DDR, finally SPL transfer control to u-boot.
NOR uses CS1 instead of CS2 when NAND boot, fix it.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes for v3:
updated env to adapt to new spl.

changes for v2:
added Secure Boot header(32KB), adjust settings accordingly.

 board/freescale/t4qds/Makefile |   6 +-
 board/freescale/t4qds/ddr.c|   6 +-
 board/freescale/t4qds/spl.c| 141 +
 board/freescale/t4qds/tlb.c|   8 ++-
 boards.cfg |   7 +-
 doc/README.t4240qds|  53 
 include/configs/T4240QDS.h |  99 +++--
 include/configs/t4qds.h|  17 -
 8 files changed, 310 insertions(+), 27 deletions(-)
 create mode 100644 board/freescale/t4qds/spl.c

diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile
index 2b1f7aa..4e8e5cb 100644
--- a/board/freescale/t4qds/Makefile
+++ b/board/freescale/t4qds/Makefile
@@ -4,10 +4,14 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
 obj-$(CONFIG_T4240QDS) += t4240qds.o
 obj-$(CONFIG_T4240EMU) += t4240emu.o
-obj-y  += ddr.o
 obj-$(CONFIG_T4240QDS)+= eth.o
 obj-$(CONFIG_PCI)  += pci.o
+endif
+obj-y  += ddr.o
 obj-y  += law.o
 obj-y  += tlb.o
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index 7586cc3..7abd38d 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -117,11 +117,15 @@ phys_size_t initdram(int board_type)
 
puts(Initializingusing SPD\n);
 
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
dram_size = fsl_ddr_sdram();
 
dram_size = setup_ddr_tlbs(dram_size / 0x10);
dram_size *= 0x10;
 
-   puts(DDR: );
+#else
+   /* DDR has been initialised by first stage boot loader */
+   dram_size = fsl_ddr_sdram_size();
+#endif
return dram_size;
 }
diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c
new file mode 100644
index 000..0c6156e
--- /dev/null
+++ b/board/freescale/t4qds/spl.c
@@ -0,0 +1,141 @@
+/* Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/spl.h
+#include malloc.h
+#include ns16550.h
+#include nand.h
+#include mmc.h
+#include fsl_esdhc.h
+#include i2c.h
+#include ../common/qixis.h
+#include t4240qds_qixis.h
+
+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK   0xFF80
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+   return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+   u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+   switch (sysclk_conf  0x0F) {
+   case QIXIS_SYSCLK_83:
+   return 8333;
+   case QIXIS_SYSCLK_100:
+   return 1;
+   case QIXIS_SYSCLK_125:
+   return 12500;
+   case QIXIS_SYSCLK_133:
+   return 1;
+   case QIXIS_SYSCLK_150:
+   return 15000;
+   case QIXIS_SYSCLK_160:
+   return 16000;
+   case QIXIS_SYSCLK_166:
+   return 1;
+   }
+   return ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+   u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+   switch ((ddrclk_conf  0x30)  4) {
+   case QIXIS_DDRCLK_100:
+   return 1;
+   case QIXIS_DDRCLK_125:
+   return 12500;
+   case QIXIS_DDRCLK_133:
+   return 1;
+   }
+   return ;
+}
+
+void board_init_f(ulong bootflag)
+{
+   u32 plat_ratio, sys_clk, ccb_clk;
+   ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#ifdef CONFIG_SPL_NAND_BOOT
+   u32 porsr1, pinctl;
+#endif
+
+#ifdef CONFIG_SPL_NAND_BOOT
+   porsr1 = in_be32(gur-porsr1);
+   pinctl = ((porsr1  ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x2480);
+   out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x2), pinctl);
+#endif
+   /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+   memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+   /* Update GD pointer */
+   gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+   /* compiler optimization barrier needed for GCC = 3.4 */
+   __asm__ __volatile__( : : : memory);
+
+   console_init_f();
+
+   /* initialize selected port with appropriate baud rate */
+   sys_clk = get_board_sys_clk();
+   plat_ratio = (in_be32(gur-rcwsr[0])  25)  0x1f;
+   ccb_clk = sys_clk * plat_ratio / 2;
+
+   NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+   puts(\nSD 

[U-Boot] [PATCH] powerpc/fman/memac: use default MDIO_HOLD value

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

Current driver uses a Maximum value for MDIO_HOLD when doing 10G MDIO
access, this is due to an errata A-006260 on T4 rev1.0 which is fixed
on rev2.0, so remove the maximum value to use the default value for rev2.0.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 drivers/net/fm/memac_phy.c | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
index 2f4bc11..de9c0e9 100644
--- a/drivers/net/fm/memac_phy.c
+++ b/drivers/net/fm/memac_phy.c
@@ -29,10 +29,8 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int 
dev_addr,
c45 = 0; /* clause 22 */
dev_addr = regnum  0x1f;
clrbits_be32(regs-mdio_stat, MDIO_STAT_ENC);
-   } else {
+   } else
setbits_be32(regs-mdio_stat, MDIO_STAT_ENC);
-   setbits_be32(regs-mdio_stat, MDIO_STAT_HOLD_15_CLK);
-   }
 
/* Wait till the bus is free */
while ((in_be32(regs-mdio_stat))  MDIO_STAT_BSY)
@@ -76,10 +74,8 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int 
dev_addr,
c45 = 0; /* clause 22 */
dev_addr = regnum  0x1f;
clrbits_be32(regs-mdio_stat, MDIO_STAT_ENC);
-   } else {
+   } else
setbits_be32(regs-mdio_stat, MDIO_STAT_ENC);
-   setbits_be32(regs-mdio_stat, MDIO_STAT_HOLD_15_CLK);
-   }
 
/* Wait till the bus is free */
while ((in_be32(regs-mdio_stat))  MDIO_STAT_BSY)
-- 
1.8.0

___
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[U-Boot] [PATCH 2/2] powerpc/T4QDS: add two stage boot of nand/sd

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

Add support of 2 stage NAND/SD boot loader using SPL framework.
PBL initialise the internal SRAM and copy SPL, this further
initialise DDR using SPD and environment and copy u-boot from
NAND/SD to DDR, finally SPL transfer control to u-boot.
NOR uses CS1 instead of CS2 when NAND boot, fix it.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/t4qds/Makefile |   6 +-
 board/freescale/t4qds/ddr.c|   6 +-
 board/freescale/t4qds/spl.c| 145 +
 board/freescale/t4qds/tlb.c|   8 ++-
 boards.cfg |   7 +-
 doc/README.t4240qds|  51 +++
 include/configs/T4240QDS.h | 100 ++--
 include/configs/t4qds.h|  17 -
 8 files changed, 313 insertions(+), 27 deletions(-)
 create mode 100644 board/freescale/t4qds/spl.c

diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile
index 2b1f7aa..4e8e5cb 100644
--- a/board/freescale/t4qds/Makefile
+++ b/board/freescale/t4qds/Makefile
@@ -4,10 +4,14 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
 obj-$(CONFIG_T4240QDS) += t4240qds.o
 obj-$(CONFIG_T4240EMU) += t4240emu.o
-obj-y  += ddr.o
 obj-$(CONFIG_T4240QDS)+= eth.o
 obj-$(CONFIG_PCI)  += pci.o
+endif
+obj-y  += ddr.o
 obj-y  += law.o
 obj-y  += tlb.o
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index 7586cc3..7abd38d 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -117,11 +117,15 @@ phys_size_t initdram(int board_type)
 
puts(Initializingusing SPD\n);
 
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
dram_size = fsl_ddr_sdram();
 
dram_size = setup_ddr_tlbs(dram_size / 0x10);
dram_size *= 0x10;
 
-   puts(DDR: );
+#else
+   /* DDR has been initialised by first stage boot loader */
+   dram_size = fsl_ddr_sdram_size();
+#endif
return dram_size;
 }
diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c
new file mode 100644
index 000..21463fb
--- /dev/null
+++ b/board/freescale/t4qds/spl.c
@@ -0,0 +1,145 @@
+/* Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/spl.h
+#include malloc.h
+#include ns16550.h
+#include nand.h
+#include mmc.h
+#include fsl_esdhc.h
+#include i2c.h
+#include ../common/qixis.h
+#include t4240qds_qixis.h
+
+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK   0xFF80
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+   return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+   u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+   switch (sysclk_conf  0x0F) {
+   case QIXIS_SYSCLK_83:
+   return 8333;
+   case QIXIS_SYSCLK_100:
+   return 1;
+   case QIXIS_SYSCLK_125:
+   return 12500;
+   case QIXIS_SYSCLK_133:
+   return 1;
+   case QIXIS_SYSCLK_150:
+   return 15000;
+   case QIXIS_SYSCLK_160:
+   return 16000;
+   case QIXIS_SYSCLK_166:
+   return 1;
+   }
+   return ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+   u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+   switch ((ddrclk_conf  0x30)  4) {
+   case QIXIS_DDRCLK_100:
+   return 1;
+   case QIXIS_DDRCLK_125:
+   return 12500;
+   case QIXIS_DDRCLK_133:
+   return 1;
+   }
+   return ;
+}
+
+void board_init_f(ulong bootflag)
+{
+   u32 plat_ratio, sys_clk, ccb_clk;
+   ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#ifdef CONFIG_SPL_NAND_BOOT
+   u32 porsr1, pinctl;
+#endif
+
+#ifdef CONFIG_SPL_NAND_BOOT
+   porsr1 = in_be32(gur-porsr1);
+   pinctl = ((porsr1  ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x2480);
+   out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x2), pinctl);
+#endif
+   /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+   memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+   /* Update GD pointer */
+   gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+   __asm__ __volatile__( : : : memory);
+
+   console_init_f();
+
+   /* initialize selected port with appropriate baud rate */
+   sys_clk = get_board_sys_clk();
+   plat_ratio = (in_be32(gur-rcwsr[0])  25)  0x1f;
+   ccb_clk = sys_clk * plat_ratio / 2;
+
+   NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+   puts(\nSD boot...\n);
+#elif defined(CONFIG_SPL_NAND_BOOT)
+   puts(\nNAND boot...\n);
+#endif
+   relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, 

[U-Boot] [PATCH 1/2] powerpc/t4240: updated RCW and PBI for rev2.0

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

Updated the RCW for rev2.0 which uses new frequency settings as below:

Clock Configuration:
CPU0:1666.667 MHz, CPU1:1666.667 MHz, CPU2:1666.667 MHz, CPU3:1666.667 MHz,
CPU4:1666.667 MHz, CPU5:1666.667 MHz, CPU6:1666.667 MHz, CPU7:1666.667 MHz,
CPU8:1666.667 MHz, CPU9:1666.667 MHz, CPU10:1666.667 MHz, CPU11:1666.667MHz,
CCB:733.333 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:183.333 MHz
FMAN1: 733.333 MHz
FMAN2: 733.333 MHz
QMAN:  366.667 MHz
PME:   533.333 MHz

Remove workaround of IFC bus speed and SERDES A-006031 of rev1.0.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/t4qds/t4_pbi.cfg | 14 --
 board/freescale/t4qds/t4_rcw.cfg |  6 +++---
 2 files changed, 3 insertions(+), 17 deletions(-)

diff --git a/board/freescale/t4qds/t4_pbi.cfg b/board/freescale/t4qds/t4_pbi.cfg
index c598fb5..6126266 100644
--- a/board/freescale/t4qds/t4_pbi.cfg
+++ b/board/freescale/t4qds/t4_pbi.cfg
@@ -13,20 +13,6 @@
 09000d00 
 09000d04 fff8
 09000d08 8112
-#workaround for IFC bus speed
-091241c0 f03f3f3f
-091241c4 ff003f3f
-09124010 0101
-09124130 000c
-#workaround for SERDES A-006031
-090ea000 064740e6
-090ea020 064740e6
-090eb000 064740e6
-090eb020 064740e6
-090ec000 064740e6
-090ec020 064740e6
-090ed000 064740e6
-090ed020 064740e6
 #Configure alternate space
 0910 
 0914 ff00
diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg
index 74df01a..3e56817 100644
--- a/board/freescale/t4qds/t4_rcw.cfg
+++ b/board/freescale/t4qds/t4_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 010e0100
 #serdes protocol  1_28_6_12
-120c0019 0c101915  
-04383063 30548c00 6c02 1d00
+16070019 18101916  
+04383060 30548c00 ec02 f500
  eeee  000307fc
-   0020
+   0028
-- 
1.8.0

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[U-Boot] [PATCH] powerpc/t4240: updated RCW and PBI for rev2.0

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

Also, remove workaround of rev1.0.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/t4qds/t4_pbi.cfg | 14 --
 board/freescale/t4qds/t4_rcw.cfg |  6 +++---
 2 files changed, 3 insertions(+), 17 deletions(-)

diff --git a/board/freescale/t4qds/t4_pbi.cfg b/board/freescale/t4qds/t4_pbi.cfg
index c598fb5..6126266 100644
--- a/board/freescale/t4qds/t4_pbi.cfg
+++ b/board/freescale/t4qds/t4_pbi.cfg
@@ -13,20 +13,6 @@
 09000d00 
 09000d04 fff8
 09000d08 8112
-#workaround for IFC bus speed
-091241c0 f03f3f3f
-091241c4 ff003f3f
-09124010 0101
-09124130 000c
-#workaround for SERDES A-006031
-090ea000 064740e6
-090ea020 064740e6
-090eb000 064740e6
-090eb020 064740e6
-090ec000 064740e6
-090ec020 064740e6
-090ed000 064740e6
-090ed020 064740e6
 #Configure alternate space
 0910 
 0914 ff00
diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg
index 74df01a..076fbc9 100644
--- a/board/freescale/t4qds/t4_rcw.cfg
+++ b/board/freescale/t4qds/t4_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 010e0100
 #serdes protocol  1_28_6_12
-120c0019 0c101915  
-04383063 30548c00 6c02 1d00
+16070019 18101916  
+04383060 30548c00 6c02 f500
  eeee  000307fc
-   0020
+   0028
-- 
1.8.0


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[U-Boot] [PATCH] powerpc/t4240: updated RCW and PBI for rev2.0

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

Also, remove workaround of rev1.0.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/t4qds/t4_pbi.cfg | 14 --
 board/freescale/t4qds/t4_rcw.cfg |  4 ++--
 2 files changed, 2 insertions(+), 16 deletions(-)

diff --git a/board/freescale/t4qds/t4_pbi.cfg b/board/freescale/t4qds/t4_pbi.cfg
index c598fb5..6126266 100644
--- a/board/freescale/t4qds/t4_pbi.cfg
+++ b/board/freescale/t4qds/t4_pbi.cfg
@@ -13,20 +13,6 @@
 09000d00 
 09000d04 fff8
 09000d08 8112
-#workaround for IFC bus speed
-091241c0 f03f3f3f
-091241c4 ff003f3f
-09124010 0101
-09124130 000c
-#workaround for SERDES A-006031
-090ea000 064740e6
-090ea020 064740e6
-090eb000 064740e6
-090eb020 064740e6
-090ec000 064740e6
-090ec020 064740e6
-090ed000 064740e6
-090ed020 064740e6
 #Configure alternate space
 0910 
 0914 ff00
diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg
index 74df01a..7334ca6 100644
--- a/board/freescale/t4qds/t4_rcw.cfg
+++ b/board/freescale/t4qds/t4_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 010e0100
 #serdes protocol  1_28_6_12
-120c0019 0c101915  
+16070019 18101916  
 04383063 30548c00 6c02 1d00
  eeee  000307fc
-   0020
+   0028
-- 
1.8.0


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[U-Boot] [PATCH] powerpc/t4240: updated RCW and PBI for rev2.0

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

Also, remove workaround of rev1.0.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/t4qds/t4_pbi.cfg | 17 +++--
 board/freescale/t4qds/t4_rcw.cfg |  6 +++---
 2 files changed, 6 insertions(+), 17 deletions(-)

diff --git a/board/freescale/t4qds/t4_pbi.cfg b/board/freescale/t4qds/t4_pbi.cfg
index c598fb5..e592c45 100644
--- a/board/freescale/t4qds/t4_pbi.cfg
+++ b/board/freescale/t4qds/t4_pbi.cfg
@@ -13,20 +13,9 @@
 09000d00 
 09000d04 fff8
 09000d08 8112
-#workaround for IFC bus speed
-091241c0 f03f3f3f
-091241c4 ff003f3f
-09124010 0101
-09124130 000c
-#workaround for SERDES A-006031
-090ea000 064740e6
-090ea020 064740e6
-090eb000 064740e6
-090eb020 064740e6
-090ec000 064740e6
-090ec020 064740e6
-090ed000 064740e6
-090ed020 064740e6
+#MDIO workaround for rev2.0
+095fc030 8148
+095fd030 00808148
 #Configure alternate space
 0910 
 0914 ff00
diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg
index 74df01a..0732b9a 100644
--- a/board/freescale/t4qds/t4_rcw.cfg
+++ b/board/freescale/t4qds/t4_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 010e0100
 #serdes protocol  1_28_6_12
-120c0019 0c101915  
-04383063 30548c00 6c02 1d00
+16070019 18101916  
+04383063 30548c00 ec108000 1d00
  eeee  000307fc
-   0020
+   0028
-- 
1.8.0


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[U-Boot] [PATCH] powerpc/t4240: enable NAND boot support

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 boards.cfg | 1 +
 1 file changed, 1 insertion(+)

diff --git a/boards.cfg b/boards.cfg
index 2128996..302ac56 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -966,6 +966,7 @@ Active  powerpc mpc85xx-   freescale
   t4qds
 Active  powerpc mpc85xx-   freescale   t4qds   
T4160QDS_SPIFLASH
T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
  -
 Active  powerpc mpc85xx-   freescale   t4qds   
T4240EMU T4240EMU:PPC_T4240 

   York Sun york...@freescale.com
 Active  powerpc mpc85xx-   freescale   t4qds   
T4240QDS T4240QDS:PPC_T4240 

   -
+Active  powerpc mpc85xx-   freescale   t4qds   
T4240QDS_NAND   
T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8
  -
 Active  powerpc mpc85xx-   freescale   t4qds   
T4240QDS_SDCARD  
T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8  
  -
 Active  powerpc mpc85xx-   freescale   t4qds   
T4240QDS_SPIFLASH
T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8
  -
 Active  powerpc mpc85xx-   freescale   t4qds   
T4240QDS_SRIO_PCIE_BOOT  
T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF8
  -
-- 
1.8.0


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[U-Boot] [PATCH] powerpc/b4860/pbl: fix rcw cfg

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

The BOOT_LOC setting in rcw cfg is wrong, set it to Memory complex 1.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/b4860qds/b4_rcw.cfg | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/freescale/b4860qds/b4_rcw.cfg 
b/board/freescale/b4860qds/b4_rcw.cfg
index 577dabf..597d391 100644
--- a/board/freescale/b4860qds/b4_rcw.cfg
+++ b/board/freescale/b4860qds/b4_rcw.cfg
@@ -2,6 +2,6 @@
 aa55aa55 010e0100
 # serdes protocol 0x2A_0x98
 140e0018 0f001218  
-5498 9000a000 f8025000 a900
+5498 9000a000 e8104000 a900
 0100   0001b1f8
  1420  0011
-- 
1.8.0


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[U-Boot] [PATCH] powerpc/corenet: CPC1 speculation disable

[shh.xie]

From: Dave Liu dave...@freescale.com

In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable
CPC1 speculation and keep it till relocation. Otherwise, speculation
transactions will go to DDR controller, it will cause problem.

Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 arch/powerpc/cpu/mpc85xx/start.S | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 6a81fa7..db84d10 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -886,7 +886,11 @@ delete_ccsr_l2_tlb:
erratum_set_dcsr 0xb0008 0x0090
erratum_set_dcsr 0xb0e40 0xe00a
erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+#ifdef  CONFIG_RAMBOOT_PBL
+   erratum_set_ccsr 0x10f00 0x495e5000
+#else
erratum_set_ccsr 0x10f00 0x415e5000
+#endif
erratum_set_ccsr 0x11f00 0x415e5000
 
/* Make temp mapping uncacheable again, if it was initially */
-- 
1.8.0


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[U-Boot] [PATCH] powerpc/t4240: Add a frequency setting case for fman1

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

A new valid setting case added for fman1, it uses platform frequency.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
based on patch: http://patchwork.ozlabs.org/patch/294663/

 arch/powerpc/cpu/mpc85xx/speed.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 6c862d8..0973261 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -229,6 +229,9 @@ void get_sys_info(sys_info_t *sys_info)
case 4:
sys_info-freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
break;
+   case 5:
+   sys_info-freq_fman[1] = sys_info-freq_systembus;
+   break;
case 6:
sys_info-freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
break;
-- 
1.8.0


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[U-Boot] [PATCH] net/phy: Add Vitesse VSC8514 PHY support

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

The VSC8514 works in QSGMII interface. Its register set and features
are similar to VSC8574 which in QSGMII mode.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 drivers/net/phy/vitesse.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index 61f863e..9af4efe 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -241,6 +241,16 @@ static struct phy_driver VSC8234_driver = {
.shutdown = genphy_shutdown,
 };
 
+static struct phy_driver VSC8514_driver = {
+   .name = Vitesse VSC8514,
+   .uid = 0x70670,
+   .mask = 0x0,
+   .features = PHY_GBIT_FEATURES,
+   .config = vsc8574_config,
+   .startup = vitesse_startup,
+   .shutdown = genphy_shutdown,
+};
+
 static struct phy_driver VSC8574_driver = {
.name = Vitesse VSC8574,
.uid = 0x704a0,
@@ -310,6 +320,7 @@ int phy_vitesse_init(void)
phy_register(VSC8244_driver);
phy_register(VSC8211_driver);
phy_register(VSC8221_driver);
+   phy_register(VSC8514_driver);
phy_register(VSC8574_driver);
phy_register(VSC8662_driver);
phy_register(cis8201_driver);
-- 
1.8.0


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[U-Boot] [PATCH] phy: introduce structure fixed-link

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

fixed-link is used in kernel for PHY-less MAC, so introduce this
structure that U-boot can use it to fixup dtb dynamically.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 include/phy.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/include/phy.h b/include/phy.h
index f0f522a..f86ffb9 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -160,6 +160,14 @@ struct phy_device {
u32 flags;
 };
 
+struct fixed_link {
+   int phy_id;
+   int duplex;
+   int link_speed;
+   int pause;
+   int asym_pause;
+};
+
 static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
 {
struct mii_dev *bus = phydev-bus;
-- 
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[U-Boot] [PATCH] powerpc/p4080: enable support for PCIe SATA

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 include/configs/P4080DS.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index b0cd7d5..2f89008 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -17,6 +17,12 @@
 #define CONFIG_MMC
 #define CONFIG_PCIE3
 
+#define CONFIG_CMD_SATA
+#define CONFIG_SATA_SIL
+#define CONFIG_SYS_SATA_MAX_DEVICE  2
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1   /* SRIO port 1 */
 #define CONFIG_SRIO2   /* SRIO port 2 */
-- 
1.8.0


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[U-Boot] [PATCH] powerpc/B4860: enable PBL tool for B4860

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which
uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a
pbl boot image.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/b4860qds/b4_pbi.cfg |   27 +++
 board/freescale/b4860qds/b4_rcw.cfg |7 +++
 include/configs/B4860QDS.h  |2 ++
 3 files changed, 36 insertions(+), 0 deletions(-)
 create mode 100644 board/freescale/b4860qds/b4_pbi.cfg
 create mode 100644 board/freescale/b4860qds/b4_rcw.cfg

diff --git a/board/freescale/b4860qds/b4_pbi.cfg 
b/board/freescale/b4860qds/b4_pbi.cfg
new file mode 100644
index 000..57b726e
--- /dev/null
+++ b/board/freescale/b4860qds/b4_pbi.cfg
@@ -0,0 +1,27 @@
+#PBI commands
+#Initialize CPC1
+0901 00200400
+09138000 
+091380c0 0100
+#Configure CPC1 as 512KB SRAM
+09010100 
+09010104 fff80009
+09010f00 0800
+0901 8000
+#Configure LAW for CPC1
+09000d00 
+09000d04 fff8
+09000d08 8112
+#Configure alternate space
+0910 
+0914 ff00
+0918 8100
+#Configure SPI controller
+0911 8403
+09110020 2d170008
+09110024 0018
+09110028 0018
+0911002c 0018
+#Flush PBL data
+09138000 
+091380c0 
diff --git a/board/freescale/b4860qds/b4_rcw.cfg 
b/board/freescale/b4860qds/b4_rcw.cfg
new file mode 100644
index 000..7bf0066
--- /dev/null
+++ b/board/freescale/b4860qds/b4_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x2A_0x98
+140e0018 0f001218  
+5498 9000a000 f8025000 a900
+0100   0001b1f8
+ 1420  0011
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 3082d00..05c1632 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -32,6 +32,8 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE   CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS0xfffc
+#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
 #endif
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-- 
1.7.0.4


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[U-Boot] [PATCH] powerpc/t4240: updated rcw_cfg to align with default hardware configuration

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

Default configuration has been changed, the most important one is DDR
ref_clock which is changed from 66.67MHz to 133.33MHz. so the ratio need to
change from 24x to 12x to keep the DDR frequency. There are also some
other optimise to align with default configuration.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 board/freescale/t4qds/t4_rcw.cfg |8 
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg
index 6ac95ff..74df01a 100644
--- a/board/freescale/t4qds/t4_rcw.cfg
+++ b/board/freescale/t4qds/t4_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 010e0100
 #serdes protocol  1_28_6_12
-14180019 0c101916  
-04383060 30548c00 6c02 1900
- eeee  000187fc
-   0018
+120c0019 0c101915  
+04383063 30548c00 6c02 1d00
+ eeee  000307fc
+   0020
-- 
1.7.0.4


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[U-Boot] [PATCH] powerpc/tool/pbl: fix pbl image compiling process

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

Previous process of compiling a PBL boot image is:
1: make board_name_config
2: make u-boot.pbl

for example:
make T4240QDS_SDCARD_config
make u-boot.pbl

Now the process is:
1: make board_name

for example:
make T4240QDS_SDCARD

Also, updated README.pblimage.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 Makefile|1 +
 doc/README.pblimage |   15 ++-
 2 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/Makefile b/Makefile
index 8aa8039..9ae1719 100644
--- a/Makefile
+++ b/Makefile
@@ -397,6 +397,7 @@ ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
 
 ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
 ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
+ALL-$(CONFIG_RAMBOOT_PBL) += $(obj)u-boot.pbl
 ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
 ALL-$(CONFIG_SPL_FRAMEWORK) += $(obj)u-boot.img
 ALL-$(CONFIG_TPL) += $(obj)tpl/u-boot-tpl.bin
diff --git a/doc/README.pblimage b/doc/README.pblimage
index 2b9bb5c..7fdd26b 100644
--- a/doc/README.pblimage
+++ b/doc/README.pblimage
@@ -14,20 +14,17 @@ Building PBL Boot Image and boot steps
 1. Building PBL Boot Image.
The default Image is u-boot.pbl.
 
-   For eSPI boot(available on P3041/P4080/P5020):
+   For eSPI boot(available on P2041/P3041/P4080/P5020/P5040/T4240):
To build the eSPI boot image:
-   make board_name_SPIFLASH_config
-   make u-boot.pbl
+   make board_name_SPIFLASH
 
-   For SD boot(available on P3041/P4080/P5020):
+   For SD boot(available on P2041/P3041/P4080/P5020/P5040/T4240):
To build the SD boot image:
-   make board_name_SDCARD_config
-   make u-boot.pbl
+   make board_name_SDCARD
 
-   For Nand boot(available on P3041/P5020):
+   For Nand boot(available on P2041/P3041/P5020/P5040):
To build the NAND boot image:
-   make board_name_NAND_config
-   make u-boot.pbl
+   make board_name_NAND
 
 
 2. pblimage support available with mkimage utility will generate Freescale PBL
-- 
1.7.0.4


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