[U-Boot] [PATCH v2] armv8/ls1088a: configure PMU's PCTBENR to enable WDT

2018-01-09 Thread ying.zhang22455 
From: Zhang Ying-22455 

The SP805-WDT module on LS1088A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.

Signed-off-by: Zhang Ying-22455 
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d082629..05c0137 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -574,7 +574,7 @@ int timer_init(void)
 #ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 #endif
-#ifdef CONFIG_ARCH_LS2080A
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
u32 svr_dev_id;
 #endif
@@ -593,7 +593,7 @@ int timer_init(void)
out_le32(cltbenr, 0xf);
 #endif
 
-#ifdef CONFIG_ARCH_LS2080A
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
/*
 * In certain Layerscape SoCs, the clock for each core's
 * has an enable bit in the PMU Physical Core Time Base Enable
-- 
1.7.1

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[U-Boot] [PATCH] freescale: vid: add support LTC3882 and rework of the VID support

2017-12-20 Thread ying.zhang22455 
From: Zhang Ying-22455 

Add support new regular chip: LTC3882.

The origianl VID code didn't properly read the FUSESR on all chips
and set the voltages on all chips. It didn't properly support the
voltage regulators in use by NXP and report voltage changes.

Signed-off-by: Zhang Ying-22455 
---
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |9 +-
 board/freescale/common/vid.c   |  465 +++-
 board/freescale/common/vid.h   |   19 +
 3 files changed, 291 insertions(+), 202 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 957e23b..0ee7a3f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -201,10 +201,15 @@ struct ccsr_gur {
u32 gpporcr3;
u32 gpporcr4;
u8  res_030[0x60-0x30];
-#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
 #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK  0x1F
-#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT  7
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT  20
 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK   0x1F
+#define FSL_CHASSIS3_DCFG_FUSESR_LOW_VID_SHIFT 2
+#define FSL_CHASSIS3_DCFG_FUSESR_LOW_VID_MASK  0x1F
+#define FSL_CHASSIS3_DCFG_FUSESR_LOW_ALTVID_SHIFT  7
+#define FSL_CHASSIS3_DCFG_FUSESR_LOW_ALTVID_MASK   0x1F
+   u8  res_030[0x60-0x30];
u32 dcfg_fusesr;/* Fuse status register */
u8  res_064[0x70-0x64];
u32 devdisr;/* Device disable control 1 */
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index d6d1bfc..1e2ddb0 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -11,6 +11,7 @@
 #ifdef CONFIG_FSL_LSCH2
 #include 
 #elif defined(CONFIG_FSL_LSCH3)
+#include 
 #include 
 #else
 #include 
@@ -33,8 +34,42 @@ int __weak board_vdd_drop_compensation(void)
return 0;
 }
 
+#if defined(CONFIG_VOL_MONITOR_LTC3882)
+/* Helper function to write a mV value as LTC L16 into the chip,
+ * returning a boolean for success */
+static int write_l16_mV_LTC3882(int i2caddress, int cmd, int mv)
+{
+   int wait, vdd_last, l16;
+   int ret;
+   u8 buf[2];
+
+   /* Scale mV to L16 */
+   l16 = mv;
+   l16 <<= 12;
+   l16 /= 1000;
+   debug("VID: cmd 0x%02x voltage write 0x%04x\n", cmd, l16);
+   buf[0] = (l16 & 0xff);
+   buf[1] = (l16 >> 8);
+
+   /* This code assumes that both channels run the very
+* SAME voltage. This is likely true for LS2 style
+* devices. For any other configuration, all hell will
+* break loose!
+*/
+   ret = i2c_write(i2caddress, LTC3882_PAGE, 1,
+  (void *)"\377", 1);
+   if (!ret)
+   ret = i2c_write(i2caddress, cmd, 1,
+  (void *)[0], 2);
+   if (!ret)
+   ret = i2c_write(i2caddress, LTC3882_PAGE, 1,
+  (void *)"\0", 1);
+   return ret;
+}
+#endif
+
 /*
- * Get the i2c address configuration for the IR regulator chip
+ * Get the i2c address configuration for the regulator chip
  *
  * There are some variance in the RDB HW regarding the I2C address 
configuration
  * for the IR regulator chip, which is likely a problem of external resistor
@@ -45,9 +80,13 @@ int __weak board_vdd_drop_compensation(void)
  * 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA)
  * 0x09 (Verified on T1040RDB-PA)
  * 0x38 (Verified on T2080QDS, T2081QDS, T4240RDB)
+ *
+ * For other types of regulator chips, we check the IDs before we
+ * return the address to avoid making damaging mistakes
  */
-static int find_ir_chip_on_i2c(void)
+static int find_vid_chip_on_i2c(void)
 {
+#if defined(CONFIG_VOL_MONITOR_IR36021_READ) || 
defined(CONFIG_VOL_MONITOR_IR36021_SET)
int i2caddress;
int ret;
u8 byte;
@@ -63,6 +102,23 @@ static int find_ir_chip_on_i2c(void)
if ((ret >= 0) && (byte == IR36021_MFR_ID))
return i2caddress;
}
+#endif
+#if defined(CONFIG_VOL_MONITOR_LTC3882)
+   int i2caddress = I2C_VOL_MONITOR_ADDR;
+   int ret;
+   u8 buf[8];
+
+   ret = i2c_read(i2caddress,
+  LTC3882_MFR_ID, 1, (void *)[0],
+  4);
+   if (!ret && memcmp(buf, "\3LTC", 4) == 0) {
+   ret = i2c_read(i2caddress,
+  LTC3882_MFR_MODEL, 1, (void *)[0],
+  8);
+   if (!ret && memcmp(buf, "\7LTC3882", 8) == 0)
+   return i2caddress;
+   }
+#endif
return -1;
 }
 
@@ -83,10 +139,15 @@ static int find_ir_chip_on_i2c(void)
 #ifdef CONFIG_VOL_MONITOR_INA220
 #define WAIT_FOR_ADC   532 /*

[U-Boot] [PATCH] freescale: vid: add support LTC3882 and rework of the VID support

2017-12-20 Thread ying.zhang22455 
From: Zhang Ying-22455 

Add support new regular chip: LTC3882.

The origianl VID code didn't properly read the FUSESR on all chips
and set the voltages on all chips. It didn't properly support the
voltage regulators in use by NXP and report voltage changes.

Signed-off-by: Zhang Ying-22455 
---
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |9 +-
 board/freescale/common/vid.c   |  465 +++-
 board/freescale/common/vid.h   |   19 +
 3 files changed, 291 insertions(+), 202 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 957e23b..0ee7a3f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -201,10 +201,15 @@ struct ccsr_gur {
u32 gpporcr3;
u32 gpporcr4;
u8  res_030[0x60-0x30];
-#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
 #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK  0x1F
-#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT  7
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT  20
 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK   0x1F
+#define FSL_CHASSIS3_DCFG_FUSESR_LOW_VID_SHIFT 2
+#define FSL_CHASSIS3_DCFG_FUSESR_LOW_VID_MASK  0x1F
+#define FSL_CHASSIS3_DCFG_FUSESR_LOW_ALTVID_SHIFT  7
+#define FSL_CHASSIS3_DCFG_FUSESR_LOW_ALTVID_MASK   0x1F
+   u8  res_030[0x60-0x30];
u32 dcfg_fusesr;/* Fuse status register */
u8  res_064[0x70-0x64];
u32 devdisr;/* Device disable control 1 */
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index d6d1bfc..1e2ddb0 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -11,6 +11,7 @@
 #ifdef CONFIG_FSL_LSCH2
 #include 
 #elif defined(CONFIG_FSL_LSCH3)
+#include 
 #include 
 #else
 #include 
@@ -33,8 +34,42 @@ int __weak board_vdd_drop_compensation(void)
return 0;
 }
 
+#if defined(CONFIG_VOL_MONITOR_LTC3882)
+/* Helper function to write a mV value as LTC L16 into the chip,
+ * returning a boolean for success */
+static int write_l16_mV_LTC3882(int i2caddress, int cmd, int mv)
+{
+   int wait, vdd_last, l16;
+   int ret;
+   u8 buf[2];
+
+   /* Scale mV to L16 */
+   l16 = mv;
+   l16 <<= 12;
+   l16 /= 1000;
+   debug("VID: cmd 0x%02x voltage write 0x%04x\n", cmd, l16);
+   buf[0] = (l16 & 0xff);
+   buf[1] = (l16 >> 8);
+
+   /* This code assumes that both channels run the very
+* SAME voltage. This is likely true for LS2 style
+* devices. For any other configuration, all hell will
+* break loose!
+*/
+   ret = i2c_write(i2caddress, LTC3882_PAGE, 1,
+  (void *)"\377", 1);
+   if (!ret)
+   ret = i2c_write(i2caddress, cmd, 1,
+  (void *)[0], 2);
+   if (!ret)
+   ret = i2c_write(i2caddress, LTC3882_PAGE, 1,
+  (void *)"\0", 1);
+   return ret;
+}
+#endif
+
 /*
- * Get the i2c address configuration for the IR regulator chip
+ * Get the i2c address configuration for the regulator chip
  *
  * There are some variance in the RDB HW regarding the I2C address 
configuration
  * for the IR regulator chip, which is likely a problem of external resistor
@@ -45,9 +80,13 @@ int __weak board_vdd_drop_compensation(void)
  * 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA)
  * 0x09 (Verified on T1040RDB-PA)
  * 0x38 (Verified on T2080QDS, T2081QDS, T4240RDB)
+ *
+ * For other types of regulator chips, we check the IDs before we
+ * return the address to avoid making damaging mistakes
  */
-static int find_ir_chip_on_i2c(void)
+static int find_vid_chip_on_i2c(void)
 {
+#if defined(CONFIG_VOL_MONITOR_IR36021_READ) || 
defined(CONFIG_VOL_MONITOR_IR36021_SET)
int i2caddress;
int ret;
u8 byte;
@@ -63,6 +102,23 @@ static int find_ir_chip_on_i2c(void)
if ((ret >= 0) && (byte == IR36021_MFR_ID))
return i2caddress;
}
+#endif
+#if defined(CONFIG_VOL_MONITOR_LTC3882)
+   int i2caddress = I2C_VOL_MONITOR_ADDR;
+   int ret;
+   u8 buf[8];
+
+   ret = i2c_read(i2caddress,
+  LTC3882_MFR_ID, 1, (void *)[0],
+  4);
+   if (!ret && memcmp(buf, "\3LTC", 4) == 0) {
+   ret = i2c_read(i2caddress,
+  LTC3882_MFR_MODEL, 1, (void *)[0],
+  8);
+   if (!ret && memcmp(buf, "\7LTC3882", 8) == 0)
+   return i2caddress;
+   }
+#endif
return -1;
 }
 
@@ -83,10 +139,15 @@ static int find_ir_chip_on_i2c(void)
 #ifdef CONFIG_VOL_MONITOR_INA220
 #define WAIT_FOR_ADC   532 /*

[U-Boot] [PATCH] armv8/ls1088a: configure PMU's PCTBENR to enable WDT

2017-08-22 Thread ying.zhang22455 
From: Zhang Ying-22455 

The SP805-WDT module on LS1088A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.

Signed-off-by: Zhang Ying-22455 
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index c6fede3..ea983e4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -531,7 +531,7 @@ int timer_init(void)
 #ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 #endif
-#ifdef CONFIG_ARCH_LS2080A
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS1088A)
u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
u32 svr_dev_id;
 #endif
@@ -550,7 +550,7 @@ int timer_init(void)
out_le32(cltbenr, 0xf);
 #endif
 
-#ifdef CONFIG_ARCH_LS2080A
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS1088A)
/*
 * In certain Layerscape SoCs, the clock for each core's
 * has an enable bit in the PMU Physical Core Time Base Enable
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] arm64: ls2088ardb: Add distro boot support

2017-06-05 Thread ying.zhang22455 
From: Zhang Ying-22455 

Include common config_distro_defaults.h and config_distro_bootcmd.h
for u-boot enviroments to support automatical distro boot which
scan boot.scr from external storage devices(e.g. SD/USB/SATA/SCSI disk)
and execute autoboot script. Tested on ls2088ardb with automatically
boot Ubuntu from SD card or USB disk, if it fails to detect external
storage disk, fall back to nor/qspi boot.

Signed-off-by: Zhang Ying-22455 
---
 configs/ls2080ardb_defconfig  |  1 +
 configs/ls2088ardb_qspi_defconfig |  1 +
 include/configs/ls2080ardb.h  | 93 +++
 3 files changed, 47 insertions(+), 48 deletions(-)

diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index ed79c97..26aca0d 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -38,3 +38,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls2088ardb_qspi_defconfig 
b/configs/ls2088ardb_qspi_defconfig
index 139ff08..37f92a4 100644
--- a/configs/ls2088ardb_qspi_defconfig
+++ b/configs/ls2088ardb_qspi_defconfig
@@ -44,3 +44,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DISTRO_DEFAULTS=y
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 2dab065..1b4c4b5 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -388,70 +388,67 @@ unsigned long get_board_sys_clk(void);
" 0x580e0 \0"   \
BOOTENV
 #else
-#ifdef CONFIG_QSPI_BOOT
-#define CONFIG_EXTRA_ENV_SETTINGS  \
-   "hwconfig=fsl_ddr:bank_intlv=auto\0"\
-   "scriptaddr=0x8080\0"   \
-   "kernel_addr_r=0x8100\0"\
-   "pxefile_addr_r=0x8100\0"   \
-   "fdt_addr_r=0x8800\0"   \
-   "ramdisk_addr_r=0x8900\0"   \
-   "loadaddr=0x8010\0" \
-   "kernel_addr=0x10\0"\
-   "ramdisk_size=0x200\0"  \
-   "fdt_high=0xa000\0" \
-   "initrd_high=0x\0"  \
-   "kernel_start=0x2100\0" \
-   "mcmemsize=0x4000\0"\
-   "mcinitcmd=fsl_mc start mc 0x20a0" \
-   " 0x20e0 \0"   \
-   BOOTENV
-#else
 #define CONFIG_EXTRA_ENV_SETTINGS  \
"hwconfig=fsl_ddr:bank_intlv=auto\0"\
-   "scriptaddr=0x8080\0"   \
-   "kernel_addr_r=0x8100\0"\
-   "pxefile_addr_r=0x8100\0"   \
-   "fdt_addr_r=0x8800\0"   \
-   "ramdisk_addr_r=0x8900\0"   \
-   "loadaddr=0x8010\0" \
-   "kernel_addr=0x10\0"\
"ramdisk_addr=0x80\0"   \
"ramdisk_size=0x200\0"  \
"fdt_high=0xa000\0" \
"initrd_high=0x\0"  \
-   "kernel_start=0x58100\0"\
-   "kernel_load=0xa000\0"  \
+   "fdt_addr=0x64f0\0" \
+   "kernel_addr=0x6500\0"  \
+   "scriptaddr=0x8000\0"   \
+   "fdtheader_addr_r=0x8010\0" \
+   "kernelheader_addr_r=0x8020\0"  \
+   "kernel_addr_r=0x8100\0"\
+   "fdt_addr_r=0x9000\0"   \
+   "load_addr=0xa000\0"\
"kernel_size=0x280\0"   \
-   "mcmemsize=0x4000\0"\
-   "fdtfile=fsl-ls2080a-rdb.dtb\0" \
-   "mcinitcmd=fsl_mc start mc 0x580a0" \
-   " 0x580e0 \0"   \
-   BOOTENV
-#endif
+   "console=ttyAMA0,38400n8\0" \
+   BOOTENV \
+   "boot_scripts=ls2088ardb_boot.scr\0"\
+   "scan_dev_for_boot_part="   \
+   "part list ${devtype} ${devnum} devplist; " \
+   "env exists devplist || setenv devplist 1; "\
+   "for distro_bootpart in ${devplist}; do "   \
+   "if fstype ${devtype} " \
+   "${devnum}:${distro_bootpart} " \
+   "bootfstype; then " \
+   "run scan_dev_for_boot; "   \
+   "fi; "  \
+   "done\0"\
+   "installer=load mmc 0:2 $load_addr "\
+   "/flex_installer_arm64.itb; "   \
+   "bootm $load_addr#ls2088ardb\0" \
+   "qspi_bootcmd=echo Trying load from qspi..;"

[U-Boot] [PATCH v2] board/ls2088ardb: set rear fan speed to reduce noise

2016-11-21 Thread ying.zhang22455 
From: Ying Zhang 

Fan settings(PWM signal set to ~50% duty cycle for all three rear)
fans provide good thermal air flow with considerable reduction of
fan noise.

Signed-off-by: Ying Zhang 
---
[changed from v1]: make the function static.

 board/freescale/ls2080ardb/ls2080ardb.c | 31 +++
 include/configs/ls2080ardb.h|  6 ++
 2 files changed, 37 insertions(+)

diff --git a/board/freescale/ls2080ardb/ls2080ardb.c 
b/board/freescale/ls2080ardb/ls2080ardb.c
index 83d9e7e..bc5dd53 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -151,6 +151,36 @@ int config_board_mux(int ctrl_type)
return 0;
 }
 
+static void set_fan_speed(void)
+{
+   int ret, i;
+   u8 value;
+
+   select_i2c_ch_pca9547(I2C_MUX_CH_FAN);
+   value = 0x80;
+   ret = i2c_write(I2C_FAN_CONTROLLER_ADDR, 0x0, 1, , 1);
+   if (ret) {
+   printf("Fan: Failed to set fan speed\n");
+   return;
+   }
+   value = 1;
+   ret = i2c_write(I2C_FAN_CONTROLLER_ADDR, 0x58, 1, , 1);
+   if (ret) {
+   printf("Fan: Failed to set fan speed\n");
+   return;
+   }
+
+   /* set PWM = ~50% DCyc for all rear PWM fans */
+   value = 0x20;
+   for (i = 0xb4; i < 0xb9; i++) {
+   ret = i2c_write(I2C_FAN_CONTROLLER_ADDR, i, 1, , 1);
+   if (ret) {
+   printf("Fan: Failed to set fan speed\n");
+   return;
+   }
+   }
+}
+
 int board_init(void)
 {
char *env_hwconfig;
@@ -175,6 +205,7 @@ int board_init(void)
 #ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)_environment[0];
 #endif
+   set_fan_speed();
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index b9cb6d3..05f98c0 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -264,6 +264,7 @@ unsigned long get_board_sys_clk(void);
 
 /* I2C bus multiplexer */
 #define I2C_MUX_CH_DEFAULT  0x8
+#defineI2C_MUX_CH_FAN  0xd
 
 /* SPI */
 #ifdef CONFIG_FSL_DSPI
@@ -279,6 +280,11 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 #define CONFIG_CMD_DATE
 
+/*
+ * Winbond fan controller
+ */
+#define I2C_FAN_CONTROLLER_ADDR0x2c
+
 /* EEPROM */
 #define CONFIG_ID_EEPROM
 #define CONFIG_CMD_EEPROM
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] board/ls2088ardb: set rear fan speed to reduce noise

2016-11-17 Thread ying.zhang22455 
From: Ying Zhang 

Fan settings(PWM signal set to ~50% duty cycle for all three rear)
fans provide good thermal air flow with considerable reduction of
fan noise.

Signed-off-by: Ying Zhang 
---
 board/freescale/ls2080ardb/ls2080ardb.c | 31 +++
 include/configs/ls2080ardb.h|  6 ++
 2 files changed, 37 insertions(+)

diff --git a/board/freescale/ls2080ardb/ls2080ardb.c 
b/board/freescale/ls2080ardb/ls2080ardb.c
index 83d9e7e..1703b96 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -151,6 +151,36 @@ int config_board_mux(int ctrl_type)
return 0;
 }
 
+void set_fan_speed(void)
+{
+   int ret, i;
+   u8 value;
+
+   select_i2c_ch_pca9547(I2C_MUX_CH_FAN);
+   value = 0x80;
+   ret = i2c_write(I2C_FAN_CONTROLLER_ADDR, 0x0, 1, , 1);
+   if (ret) {
+   printf("Fan: Failed to set fan speed\n");
+   return;
+   }
+   value = 1;
+   ret = i2c_write(I2C_FAN_CONTROLLER_ADDR, 0x58, 1, , 1);
+   if (ret) {
+   printf("Fan: Failed to set fan speed\n");
+   return;
+   }
+
+   /* set PWM = ~50% DCyc for all rear PWM fans */
+   value = 0x20;
+   for (i = 0xb4; i < 0xb9; i++) {
+   ret = i2c_write(I2C_FAN_CONTROLLER_ADDR, i, 1, , 1);
+   if (ret) {
+   printf("Fan: Failed to set fan speed\n");
+   return;
+   }
+   }
+}
+
 int board_init(void)
 {
char *env_hwconfig;
@@ -175,6 +205,7 @@ int board_init(void)
 #ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)_environment[0];
 #endif
+   set_fan_speed();
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index b9cb6d3..05f98c0 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -264,6 +264,7 @@ unsigned long get_board_sys_clk(void);
 
 /* I2C bus multiplexer */
 #define I2C_MUX_CH_DEFAULT  0x8
+#defineI2C_MUX_CH_FAN  0xd
 
 /* SPI */
 #ifdef CONFIG_FSL_DSPI
@@ -279,6 +280,11 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 #define CONFIG_CMD_DATE
 
+/*
+ * Winbond fan controller
+ */
+#define I2C_FAN_CONTROLLER_ADDR0x2c
+
 /* EEPROM */
 #define CONFIG_ID_EEPROM
 #define CONFIG_CMD_EEPROM
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/2 v3] powerpc:t4240rdb: Disable the non-existent ethernet ports on T4240RDB

2016-04-21 Thread ying.zhang22455 
From: Ying Zhang 

Disable the non-existent ethernet ports on T4240RDB:FM1_DTSEC5,
FM1_DTSEC6, FM2_DTSEC5 and FM2_DTSEC6.

Signed-off-by: Ying Zhang 
---
[changed from v1]:
--- update the title.
[changed from v2]:
--- update the commit message.

 board/freescale/t4rdb/eth.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index e563a61..ae2451e 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -77,6 +77,9 @@ int board_eth_init(bd_t *bis)
puts("Invalid SerDes1 protocol for T4240RDB\n");
}
 
+   fm_disable_port(FM1_DTSEC5);
+   fm_disable_port(FM1_DTSEC6);
+
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
interface = fm_info_get_enet_if(i);
switch (interface) {
@@ -115,6 +118,8 @@ int board_eth_init(bd_t *bis)
puts("Invalid SerDes2 protocol for T4240RDB\n");
}
 
+   fm_disable_port(FM2_DTSEC5);
+   fm_disable_port(FM2_DTSEC6);
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
interface = fm_info_get_enet_if(i);
switch (interface) {
-- 
2.1.0.27.g96db324

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